text stringlengths 59 71.4k |
|---|
/* This file is part of JT12.
JT12 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 14-2-2017
*/
module jt12_div(
input rst,
input clk,
input cen /* synthesis direct_enable */,
input [1:0] div_setting,
output reg clk_en, // after prescaler
output reg clk_en_2, // cen divided by 2
output reg clk_en_ssg,
output reg clk_en_666, // 666 kHz
output reg clk_en_111, // 111 kHz
output reg clk_en_55 // 55 kHz
);
parameter use_ssg=0;
reg [3:0] opn_pres, opn_cnt=4'd0;
reg [2:0] ssg_pres, ssg_cnt=3'd0;
reg [4:0] adpcm_cnt666 = 5'd0;
reg [2:0] adpcm_cnt111 = 3'd0, adpcm_cnt55=3'd0;
reg cen_int, cen_ssg_int, cen_adpcm_int, cen_adpcm3_int;
// prescaler values for FM
// reset: 1/3
// sel1/sel2
// 0 0 1/3
// 0 1 1/2
// 1 0 1/6
// 1 1 1/2
//
// According to YM2608 document
// FM SSG div[1:0]
// reset value 1/6 1/4 10
// 2D 1/6 1/4 10 | 10
// 2D,2E 1/3 1/2 11 | 01
// 2F 1/2 1/1 00 & 00
//
always @(*) begin
casez( div_setting )
2'b0?: begin // FM 1/2 - SSG 1/1
opn_pres = 4'd2-4'd1;
ssg_pres = 3'd0;
end
2'b10: begin // FM 1/6 - SSG 1/4 (reset value. Fixed for YM2610)
opn_pres = 4'd6-4'd1;
ssg_pres = 3'd3;
end
2'b11: begin // FM 1/3 - SSG 1/2
opn_pres = 4'd3-4'd1;
ssg_pres = 3'd1;
end
endcase // div_setting
end
`ifdef SIMULATION
initial clk_en_666 = 1'b0;
`endif
reg cen_55_int;
reg [1:0] div2=2'b0;
reg pre_clk_en, pre_clk_en_2, pre_clk_en_ssg, pre_clk_en_666, pre_clk_en_111, pre_clk_en_55;
always @(negedge clk) begin // It's important to leave the negedge to use the physical clock enable input
clk_en <= pre_clk_en;
clk_en_2 <= pre_clk_en_2;
clk_en_ssg <= pre_clk_en_ssg;
clk_en_666 <= pre_clk_en_666;
clk_en_111 <= pre_clk_en_111;
clk_en_55 <= pre_clk_en_55;
end
always @(posedge clk) begin
cen_int <= opn_cnt == 4'd0;
cen_ssg_int <= ssg_cnt == 3'd0;
cen_adpcm_int <= adpcm_cnt666 == 5'd0;
cen_adpcm3_int <= adpcm_cnt111 == 3'd0;
cen_55_int <= adpcm_cnt55 == 3'd0;
`ifdef FASTDIV
// always enabled for fast sims (use with GYM output, the timers will not work well)
clk_en <= 1'b1;
clk_en_ssg <= 1'b1;
clk_en_666 <= 1'b1;
clk_en_55 <= 1'b1;
`else
pre_clk_en <= cen & cen_int;
pre_clk_en_2 <= cen && (div2==2'b00);
pre_clk_en_ssg <= use_ssg ? (cen & cen_ssg_int) : 1'b0;
pre_clk_en_666 <= cen & cen_adpcm_int;
pre_clk_en_111 <= cen & cen_adpcm_int & cen_adpcm3_int;
pre_clk_en_55 <= cen & cen_adpcm_int & cen_adpcm3_int & cen_55_int;
`endif
end
// Div/2
always @(posedge clk)
if( cen ) begin
div2 <= div2==2'b10 ? 2'b00 : (div2+2'b01);
end
// OPN
always @(posedge clk)
if( cen ) begin
if( opn_cnt == opn_pres ) begin
opn_cnt <= 4'd0;
end
else opn_cnt <= opn_cnt + 4'd1;
end
// SSG
always @(posedge clk)
if( cen ) begin
if( ssg_cnt == ssg_pres ) begin
ssg_cnt <= 3'd0;
end
else ssg_cnt <= ssg_cnt + 3'd1;
end
// ADPCM-A
always @(posedge clk)
if( cen ) begin
adpcm_cnt666 <= adpcm_cnt666==5'd11 ? 5'd0 : adpcm_cnt666 + 5'd1;
if( adpcm_cnt666==5'd0 ) begin
adpcm_cnt111 <= adpcm_cnt111==3'd5 ? 3'd0 : adpcm_cnt111+3'd1;
if( adpcm_cnt111==3'd0)
adpcm_cnt55 <= adpcm_cnt55==3'd1 ? 3'd0: adpcm_cnt55+3'd1;
end
end
endmodule // jt12_div
|
`include "../../sources_1/new/defines.v"
//////////////////////////////////////////////////////////////////////////////////
// Company: WSIZ Copernicus
// Engineer: Rafa³ B., Szymon S., Darek B.
//
// Create Date: 26.04.2017 18:27:52
// Design Name:
// Module Name: test_bench
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module test_bench();
reg clk;
reg [2:0]panel_przyciskow;
parameter CENA_OP1 = `m300; // cena opcji 1 (3.00z³ - expresso )
parameter CENA_OP2 = `m500; // cena opcji 2 (5.00z³ - expresso grande :P )
parameter CENA_OP3 = `m750; // cena opcji 3 (7.50z³ - cappuccino :P )
parameter tick_every = 20; // w³aciwie nie nale¿y zmieniaæ - regulacja czêstotliwoci maszyny
// aktualnie: (1 000 000 us / 20 us) cykli/s = 50 000 Hz = 50 kHz
parameter speed_up = 50000; // zwiêkszenie spowoduje przyspieszenie licznika (tylko licznika)
// ustawienie na 50 000 spowoduje przyspieszenia licznika do wartoci:
// 1 cykl = 1 sek (pomocne w symulacji)
// pod³¹czamy modu³ g³ówny
reg [2:0]monety_in;
wire [2:0]monety_out;
reg kubki, kawa, woda, mleko, bilon;
top #(.CENA_OP1(CENA_OP1), .CENA_OP2(CENA_OP2), .CENA_OP3(CENA_OP3), .tick_every(tick_every*speed_up))
uut(.clk(clk), .mon_in(monety_in), .panel_przyciskow_in(panel_przyciskow), .mon_out(monety_out),
.c_k(kubki), .i_k(kawa), .p_w(woda), .i_m(mleko), .p_b(bilon));
// podgl¹d zegara dzielnika oraz stanu modu³u g³ównego
wire clk_div;
wire [3:0]stan_top;
assign clk_div = top.clk_div;
assign stan_top = top.old_top.stan_top;
// sterowanie i podgl¹d modu³u monet
wire [1:0]cmd_out_mm;
wire [4:0]stan_mm;
assign stan_mm = top.wrzut_zwrot.stan;
assign cmd_out_mm = top.cmd_out;
// sterowanie i podgl¹d modu³u sprawnoci
wire sprawnosc;
assign sprawnosc = top.sprawnosc_out;
// podgl¹d wywietlacza
wire [3:0]seg_out;
wire seg_dl, seg_dm, seg_dot, seg_dr, seg_mm, seg_ul, seg_um, seg_ur;
assign seg_um = top.seg_um;
assign seg_ul = top.seg_ul;
assign seg_ur = top.seg_ur;
assign seg_mm = top.seg_mm;
assign seg_dl = top.seg_dl;
assign seg_dr = top.seg_dr;
assign seg_dm = top.seg_dm;
assign seg_dot = top.seg_dot;
assign seg_out = top.segment_out;
// podgl¹d licznika
wire [6:0] count_secs;
wire count_out;
assign count_secs = top.count_secs;
assign count_out = top.licz_in;
initial
begin
clk = 1'b0;
panel_przyciskow = `CMD_RESET; // resetujemy autoamt
// modu³ sprawnoci - emulacja czujnikow
kubki <= 1'b0;
kawa <= 1'b0;
woda <= 1'b0;
mleko <= 1'b0;
bilon <= 1'b0;
monety_in = `z0g00;
// zaczynamy
#(tick_every*10) monety_in <= `z0g50; // wrzucamy 50 groszy
#(tick_every*10) monety_in <= `z1g00; // wrzucamy 1 z³
#(tick_every*10) monety_in <= `z2g00; // wrzucamy 2 z³
#(tick_every*10) monety_in <= `z5g00; // wrzucamy 5 z³
#(tick_every*10) panel_przyciskow <= `CMD_OP1; // wybieramy opcjê nr 1
#(tick_every*10) panel_przyciskow <= `CMD_OP2; // wybieramy opcjê nr 2 (bez resetu)
#(tick_every*10) monety_in <= `z2g00; // wrzucamy 2 z³
#(tick_every*10) monety_in <= `z0g50; // wrzucamy 50 gr
#(tick_every*10) panel_przyciskow = `CMD_RESET; // reset
#(tick_every*2) monety_in <= `z5g00; // wrzucamy 5 z³
// ok, teraz zrtobimy kawkê
#(tick_every*30) panel_przyciskow <= `CMD_OP3; // wybieramy opcjê nr 3
#(tick_every*10) monety_in <= `z2g00; // wrzucamy 2 z³
#(tick_every*10) monety_in <= `z0g50; // wrzucamy 50 gr
#(tick_every*10) monety_in <= `z2g00; // wrzucamy 2 z³
#(tick_every*10) monety_in <= `z5g00; // wrzucamy 5 z³
end
always
begin
#(tick_every/2)
begin
clk <= ~clk; // zegar - tick
end
end
always @(clk)
begin
if (monety_in != `z0g00)
#(tick_every*4) monety_in <= `z0g00; // moneta wpad³a wiêc zerujemy sygna³
if (panel_przyciskow != 1'b0)
#(tick_every*4) panel_przyciskow <= `CMD_NIC; // wciniêto przycisk wiêc zerujemy
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLXTN_2_V
`define SKY130_FD_SC_LS__DLXTN_2_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog wrapper for dlxtn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dlxtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlxtn_2 (
Q ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlxtn_2 (
Q ,
D ,
GATE_N
);
output Q ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLXTN_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND4BB_TB_V
`define SKY130_FD_SC_HDLL__AND4BB_TB_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__and4bb.v"
module top();
// Inputs are registered
reg A_N;
reg B_N;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B_N = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B_N = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A_N = 1'b1;
#200 B_N = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A_N = 1'b0;
#360 B_N = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B_N = 1'b1;
#640 A_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B_N = 1'bx;
#800 A_N = 1'bx;
end
sky130_fd_sc_hdll__and4bb dut (.A_N(A_N), .B_N(B_N), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND4BB_TB_V
|
#include<bits/stdc++.h> #include<unordered_map> using namespace std; typedef long long ll; typedef vector<ll> vll; const ll M = 1000000007; bool compare(vll x, vll y) { if (x[0] < y[0]) { return true; } return false; } void solve() { vector<vll> v(3); ll n1, n2, n3; cin >> n1 >> n2 >> n3; vll v1(n1), v2(n2), v3(n3); ll f1 = 0, f2 = 0; ll tsum = 0; for (ll i = 0; i < n1; i++) { cin >> v1[i]; tsum += v1[i]; } for (ll i = 0; i < n2; i++) { cin >> v2[i]; tsum += v2[i]; } for (ll i = 0; i < n3; i++) { cin >> v3[i]; tsum += v3[i]; } sort(v1.begin(), v1.end()); sort(v2.begin(), v2.end()); sort(v3.begin(), v3.end()); v[0] = v1; v[1] = v2; v[2] = v3; sort(v.begin(), v.end(), compare); // for (int i = 0; i < 3; i++) { for (int j = 1; j < v[0].size(); j++) { f1 += v[0][j]; } for (int j = 1; j < v[1].size(); j++) { f2 += v[1][j]; } // } ll sub = 0; if (f1 == 0) { sub = 2 * v[0][0]; } else if (f1 > 0 && f2 == 0) { if (v[1][0] > f1) { sub = 2 * v[0][0] + 2 * f1; } else { sub = 2 * v[1][0]; } } else { sub = 2 * min(f2, v[0][0]) + 2 * min(f1, v[1][0]); } if (v[2].size() == 1) { sub = min(sub , 2 * v[2][0]); } cout << tsum - sub << endl; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); // This macro supported by cc, cf, cses #ifndef ONLINE_JUDGE freopen( in.txt , r , stdin); freopen( out.txt , w , stdout); #endif // int tt; // cin >> tt; // for(int i = 1; i <= tt; i++) { solve(); // } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_BEHAVIORAL_PP_V
/**
* lpflow_isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_l_pp_pg_s/sky130_fd_sc_hd__udp_pwrgood_l_pp_pg_s.v"
`celldefine
module sky130_fd_sc_hd__lpflow_isobufsrc (
X ,
SLEEP,
A ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input SLEEP;
input A ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire pwrgood0_out_X;
// Name Output Other arguments
not not0 (not0_out , SLEEP );
and and0 (and0_out_X , not0_out, A );
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG$S pwrgood0 (pwrgood0_out_X, and0_out_X, VPWR, VGND, SLEEP);
buf buf0 (X , pwrgood0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; int q[111], qr[111], s[111]; int d[222][111]; int dp[111][222]; bool ss[222]; int n, k; bool rec(int kk, int i) { if (dp[kk][k + i] != -1) return dp[kk][k + i]; if (kk == 0) return ss[k + i]; bool r; if (ss[k + i]) r = false; else { r = rec(kk - 1, i - 1) || rec(kk - 1, i + 1); } return dp[kk][k + i] = r; } int main() { cin >> n >> k; for (int(i) = 0; (i) < (int)(n); ++(i)) cin >> q[i], q[i]--; for (int(i) = 0; (i) < (int)(n); ++(i)) cin >> s[i], s[i]--; for (int(i) = 0; (i) < (int)(n); ++(i)) qr[q[i]] = i; for (int(i) = 0; (i) < (int)(n); ++(i)) d[k + 0][i] = i; for (int(i) = (int)(1); (i) <= (int)(k); ++(i)) for (int(j) = 0; (j) < (int)(n); ++(j)) d[k + i][j] = d[k + i - 1][q[j]]; for (int(i) = (int)(1); (i) <= (int)(k); ++(i)) for (int(j) = 0; (j) < (int)(n); ++(j)) d[k - i][j] = d[k + -i + 1][qr[j]]; for (int(i) = (int)(-k); (i) <= (int)(k); ++(i)) { ss[k + i] = vector<int>(d[k + i], d[k + i] + n) == vector<int>(s, s + n); } memset(dp, -1, sizeof(dp)); bool r = rec(k, 0); cout << (r ? YES : NO ) << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, neg = 0; char s[1009]; int main() { vector<int> ans; scanf( %[^=]=%d , s, &n); ans.push_back(n); for (int i = 1; s[i]; i++) { if (s[i] == ) continue; if (s[i] == - ) neg = 1; else if (s[i] == + ) neg = 0; else if (s[i] == ? && !neg) { ans[0] -= 1; ans.push_back(1); } else if (s[i] == ? ) { int c = 0; ans[0] += 1; ans.push_back(-1); } } int c = 1; while (ans[0] > n && c < ans.size()) { if (ans[c] > 0 && ans[c] < n) { ans[0]--; ans[c]++; } else c++; } c = 1; while (ans[0] <= 0 && c < ans.size()) { if (ans[c] < 0 && abs(ans[c]) < n) { ans[0]++; ans[c]--; } else c++; } if (ans[0] <= 0 || ans[0] > n) { printf( Impossible n ); return 0; } printf( Possible n ); printf( %d , ans[0]); for (int i = 1; i < ans.size(); i++) { if (ans[i] > 0) printf( + %d , ans[i]); else printf( - %d , abs(ans[i])); } printf( = %d n , n); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); double l, p, q; cin >> l >> p >> q; cout << setprecision(9) << (p * l) / (p + q); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__TAP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__TAP_BEHAVIORAL_PP_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__tap (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__TAP_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; int n, m, k; vector<int> v[1000010]; vector<int> vv; bool visit[1000010] = {0}; int t, tt; int res = 0; void dfs(int x) { visit[x] = 1; t++; for (int i = 0; i < v[x].size(); i++) { int xi = v[x][i]; if (!visit[xi]) dfs(xi); } } int main() { scanf( %d%d%d , &n, &m, &k); for (int i = 0; i < m; i++) { int x, y; scanf( %d%d , &x, &y); x--, y--; v[x].push_back(y); v[y].push_back(x); } for (int i = 0; i < n; i++) { if (!visit[i]) { t = 0; dfs(i); vv.push_back(min(t, k)); } } if (k == 1) { cout << max(0, (int)(vv.size() - 2)); return 0; } sort(vv.begin(), vv.end()); reverse(vv.begin(), vv.end()); tt = vv[0]; for (int i = 1; i < vv.size(); i++) { if (tt) tt += vv[i] - 2; else { tt++; res++; } } cout << res; return 0; } |
// Three basic tests in here:
// 1. byte must be initialised before any initial or always block
// 2. assignments to (unsigned) bytes with random numbers
// 3. assignments to (unsigned) bytes with random values including X and Z
module ibyte_test;
parameter TRIALS = 100;
parameter MAX = 'h7fffffff;
reg [31:0] ar; // should it be "reg unsigned [7:0] aw"?
reg [31:0] ar_xz; // same as above here?
reg [31:0] ar_expected; // and here
int unsigned bu;
int unsigned bu_xz;
integer i;
assign bu = ar;
assign bu_xz = ar_xz;
// all test
initial begin
// time 0 checkings (Section 6.4 of IEEE 1850 LRM)
if (bu !== 32'b0 | bu_xz != 32'b0)
begin
$display ("FAILED - time zero initialisation incorrect: %b %b", bu, bu_xz);
$finish;
end
// random numbers
for (i = 0; i< TRIALS; i = i+1)
begin
#1;
ar = {$random} % MAX;
#1;
if (bu !== ar)
begin
$display ("FAILED - incorrect assigment to byte: %b", bu);
$finish;
end
end
# 1;
// with 'x injections (Section 4.3.2 of IEEE 1850 LRM)
for (i = 0; i< TRIALS; i = i+1)
begin
#1;
ar = {$random} % MAX;
ar_xz = xz_inject (ar);
ar_expected = xz_expected (ar_xz);
#1;
if (bu_xz !== ar_expected) // 'x -> '0, 'z -> '0
begin
$display ("FAILED - incorrect assigment to byte (when 'x): %b", bu);
$finish;
end
end
# 1;
$display("PASSED");
end
// this returns X and Z states into bit random positions for a value
function [31:0] xz_inject (input [31:0] value); // should it be "input unsigned [7:0]" instead?
integer i, temp;
begin
temp = {$random} % MAX;
for (i=0; i<32; i=i+1)
begin
if (temp[i] == 1'b1)
begin
temp = $random % MAX;
if (temp <= 0)
value[i] = 1'bx; // 'x noise
else
value[i] = 1'bz; // 'z noise
end
end
xz_inject = value;
end
endfunction
// this function returns bit positions with either X or Z to 0 for an input value
function [31:0] xz_expected (input [31:0] value_xz); // should it be "input unsigned [7:0] instead?
integer i;
begin
for (i=0; i<32; i=i+1)
begin
if (value_xz[i] === 1'bx || value_xz[i] === 1'bz )
value_xz[i] = 1'b0; // forced to zero
end
xz_expected = value_xz;
end
endfunction
endmodule
|
// ====================================================================
// Radio-86RK FPGA REPLICA
//
// Copyright (C) 2011 Dmitry Tselikov
//
// This core is distributed under modified BSD license.
// For complete licensing information see LICENSE.TXT.
// --------------------------------------------------------------------
//
// An open implementation of Radio-86RK keyboard
//
// Author: Dmitry Tselikov http://bashkiria-2m.narod.ru/
//
// Design File: rk_kbd.v
//
module rk_kbd(
input clk,
input reset,
input ps2_clk,
input ps2_dat,
input[7:0] addr,
output reg[7:0] odata,
output reg cpurst,
output reg videomode,
output[2:0] shift);
reg[7:0] keystate[10:0];
assign shift = keystate[8][2:0];
always @(addr,keystate) begin
odata =
(keystate[0] & {8{addr[0]}})|
(keystate[1] & {8{addr[1]}})|
(keystate[2] & {8{addr[2]}})|
(keystate[3] & {8{addr[3]}})|
(keystate[4] & {8{addr[4]}})|
(keystate[5] & {8{addr[5]}})|
(keystate[6] & {8{addr[6]}})|
(keystate[7] & {8{addr[7]}});
end
reg[2:0] c;
reg[3:0] r;
reg extkey;
reg unpress;
reg[3:0] prev_clk;
reg[11:0] shift_reg;
wire[11:0] kdata = {ps2_dat,shift_reg[11:1]};
wire[7:0] kcode = kdata[9:2];
always @(*) begin
case (kcode)
8'h6C: {c,r} = 7'h00; // 7 home
8'h7D: {c,r} = 7'h10; // 9 pgup
8'h76: {c,r} = 7'h20; // esc
8'h05: {c,r} = 7'h30; // F1
8'h06: {c,r} = 7'h40; // F2
8'h04: {c,r} = 7'h50; // F3
8'h0C: {c,r} = 7'h60; // F4
8'h03: {c,r} = 7'h70; // F5
8'h0D: {c,r} = 7'h01; // tab
8'h71: {c,r} = 7'h11; // . del
8'h5A: {c,r} = 7'h21; // enter
8'h66: {c,r} = 7'h31; // bksp
8'h6B: {c,r} = 7'h41; // 4 left
8'h75: {c,r} = 7'h51; // 8 up
8'h74: {c,r} = 7'h61; // 6 right
8'h72: {c,r} = 7'h71; // 2 down
8'h45: {c,r} = 7'h02; // 0
8'h16: {c,r} = 7'h12; // 1
8'h1E: {c,r} = 7'h22; // 2
8'h26: {c,r} = 7'h32; // 3
8'h25: {c,r} = 7'h42; // 4
8'h2E: {c,r} = 7'h52; // 5
8'h36: {c,r} = 7'h62; // 6
8'h3D: {c,r} = 7'h72; // 7
8'h3E: {c,r} = 7'h03; // 8
8'h46: {c,r} = 7'h13; // 9
8'h55: {c,r} = 7'h23; // =
8'h0E: {c,r} = 7'h33; // `
8'h41: {c,r} = 7'h43; // ,
8'h4E: {c,r} = 7'h53; // -
8'h49: {c,r} = 7'h63; // .
8'h4A: {c,r} = extkey ? 7'h73 : 7'h73; // gray/ + /
8'h4C: {c,r} = 7'h04; // ;
8'h1C: {c,r} = 7'h14; // A
8'h32: {c,r} = 7'h24; // B
8'h21: {c,r} = 7'h34; // C
8'h23: {c,r} = 7'h44; // D
8'h24: {c,r} = 7'h54; // E
8'h2B: {c,r} = 7'h64; // F
8'h34: {c,r} = 7'h74; // G
8'h33: {c,r} = 7'h05; // H
8'h43: {c,r} = 7'h15; // I
8'h3B: {c,r} = 7'h25; // J
8'h42: {c,r} = 7'h35; // K
8'h4B: {c,r} = 7'h45; // L
8'h3A: {c,r} = 7'h55; // M
8'h31: {c,r} = 7'h65; // N
8'h44: {c,r} = 7'h75; // O
8'h4D: {c,r} = 7'h06; // P
8'h15: {c,r} = 7'h16; // Q
8'h2D: {c,r} = 7'h26; // R
8'h1B: {c,r} = 7'h36; // S
8'h2C: {c,r} = 7'h46; // T
8'h3C: {c,r} = 7'h56; // U
8'h2A: {c,r} = 7'h66; // V
8'h1D: {c,r} = 7'h76; // W
8'h22: {c,r} = 7'h07; // X
8'h35: {c,r} = 7'h17; // Y
8'h1A: {c,r} = 7'h27; // Z
8'h54: {c,r} = 7'h37; // [
8'h52: {c,r} = 7'h47; // '
8'h5B: {c,r} = 7'h57; // ]
8'h5D: {c,r} = 7'h67; // \!
8'h29: {c,r} = 7'h77; // space
8'h12: {c,r} = 7'h08; // lshift
8'h59: {c,r} = 7'h08; // rshift
8'h14: {c,r} = extkey ? 7'h18 : 7'h18; // rctrl + lctrl
8'h11: {c,r} = 7'h28; // lalt
/* 8'h0B: {c,r} = 7'h50; // F6
8'h83: {c,r} = 7'h70; // F7
8'h0A: {c,r} = 7'h12; // F8
8'h01: {c,r} = 7'h33; // F9
8'h07: {c,r} = 7'h56; // F12 - stop
8'h7C: {c,r} = 7'h46; // gray*
8'h7B: {c,r} = 7'h66; // gray-
8'h78: {c,r} = 7'h67; // F11 - rus
8'h73: {c,r} = 7'h28; // 5 center
8'h7A: {c,r} = 7'h48; // 3 pgdn
8'h69: {c,r} = 7'h68; // 1 end
8'h70: {c,r} = 7'h78; // 0 ins
*/ default: {c,r} = 7'h7F;
endcase
end
always @(posedge clk or posedge reset) begin
if (reset) begin
prev_clk <= 0;
shift_reg <= 12'hFFF;
extkey <= 0;
unpress <= 0;
keystate[0] <= 0;
keystate[1] <= 0;
keystate[2] <= 0;
keystate[3] <= 0;
keystate[4] <= 0;
keystate[5] <= 0;
keystate[6] <= 0;
keystate[7] <= 0;
keystate[8] <= 0;
keystate[9] <= 0;
keystate[10] <= 0;
cpurst <= 0;
end else begin
prev_clk <= {ps2_clk,prev_clk[3:1]};
if (prev_clk==4'b1) begin
if (kdata[11]==1'b1 && ^kdata[10:2]==1'b1 && kdata[1:0]==2'b1) begin
shift_reg <= 12'hFFF;
if (kcode==8'hE0) extkey <= 1'b1; else
if (kcode==8'hF0) unpress <= 1'b1; else
begin
extkey <= 0;
unpress <= 0;
if(r!=4'hF) keystate[r][c] <= ~unpress;
if(kcode == 8'h07 && unpress == 1'b0) cpurst <= 1'b1; else cpurst <= 1'b0;
if(kcode == 8'h78 && unpress == 1'b0) videomode <= !videomode;
end
end else
shift_reg <= kdata;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> inline void chkmax(T &a, T b) { if (a < b) a = b; } template <class T> inline void chkmin(T &a, T b) { if (a > b) a = b; } inline int read() { int sum = 0, p = 1; char ch = getchar(); while (!(( 0 <= ch && ch <= 9 ) || ch == - )) ch = getchar(); if (ch == - ) p = -1, ch = getchar(); while ( 0 <= ch && ch <= 9 ) sum = sum * 10 + ch - 48, ch = getchar(); return sum * p; } const int maxn = 5e5 + 20; struct node { int v, next; }; node e[maxn << 1]; int cnt, start[maxn]; inline void addedge(int u, int v) { e[++cnt] = (node){v, start[u]}; start[u] = cnt; } int n; inline void init() { n = read(); for (int i = (1), _end_ = (n - 1); i <= _end_; i++) { int u = read(), v = read(); addedge(u, v); addedge(v, u); } } int sz[maxn]; void get_sz(int u, int fa) { sz[u] = 1; for (int i = start[(u)]; i; i = e[i].next) if (e[i].v != fa) get_sz(e[i].v, u), sz[u] += sz[e[i].v]; } long long ans[maxn]; void dfs(int u, int fa) { for (int i = start[(u)]; i; i = e[i].next) { int v = e[i].v; if (v == fa) continue; ans[v] = ans[u] + (long long)(sz[u] - sz[v]) * sz[v]; dfs(v, u); } } inline void doing() { get_sz(1, 0); ans[1] = (long long)n * (n - 1) >> 1; dfs(1, 0); int u = 2; for (int i = (3), _end_ = (n); i <= _end_; i++) if (ans[u] < ans[i]) { u = i; } get_sz(u, 0); ans[u] = (long long)n * (n - 1) >> 1; dfs(u, 0); long long t = 0; for (int i = (1), _end_ = (n); i <= _end_; i++) chkmax(t, ans[i]); printf( %lld n , t); } int main() { init(); doing(); return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; template <typename T> void uin(T &a, T b) { if (b < a) a = b; } template <typename T> void uax(T &a, T b) { if (b > a) a = b; } const long long maxn = 1000 * 1000 + 228; long long n, k; long long dp[maxn], p[maxn]; long long dpret[maxn], hret[maxn]; vector<long long> g[maxn]; void dfs(long long v, long long deep = 0) { hret[v] = deep; if ((long long)g[v].size() == 1 && v != 1) { dp[v] = 1; dpret[v] = 1; hret[v] = max(0LL, deep - k); } else { for (long long to : g[v]) { if (to != p[v]) { dfs(to, deep + 1); if (hret[to] <= deep) { dpret[v] += dpret[to]; uin(hret[v], hret[to]); } } } dp[v] = dpret[v]; for (long long to : g[v]) { if (to != p[v]) { if (hret[to] <= deep) { uax(dp[v], dp[to] + dpret[v] - dpret[to]); } else { uax(dp[v], dp[to] + dpret[v]); } } } } } void solve() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n >> k; for (long long i = 2; i <= n; ++i) { cin >> p[i]; g[i].push_back(p[i]); g[p[i]].push_back(i); } dfs(1); cout << dp[1] << n ; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int i, j; int k, n, s, p; cin >> k >> n >> s >> p; cout << int(ceil((ceil(n / (s * 1.0)) * k) / (p * 1.0))); return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = int64_t; using vll = vector<ll>; using vvll = vector<vll>; using pll = pair<ll, ll>; using vpll = vector<pll>; using vvpll = vector<vpll>; bool sorted(int arr[], int n) { bool f1 = 1, f2 = 1; for (int i = 0; i < n - 1; i++) { if (arr[i + 1] >= arr[i]) { f1 = 0; break; } } for (int i = 0; i < n - 1; i++) { if (arr[i + 1] <= arr[i]) { f2 = 0; break; } } return f1 || f2; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); ; cout.setf(ios::fixed); cout.precision(32); ; int q; cin >> q; while (q--) { int n; cin >> n; int arr[n]; for (int i = 0; i < n; i++) cin >> arr[i]; int index = -1; for (int i = 0; i < n - 1; i++) { if (abs(arr[i] - arr[i + 1]) != 1) { index = i; break; } } if (index != -1) { reverse(arr, arr + index + 1); reverse(arr + index + 1, arr + n); } if (sorted(arr, n)) cout << YES << endl; else cout << NO << endl; } return 0; } |
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module pfpu_faddsub(
input sys_clk,
input alu_rst,
input [31:0] a,
input [31:0] b,
input sub,
input valid_i,
output [31:0] r,
output reg valid_o
);
wire a_sign = a[31];
wire [7:0] a_expn = a[30:23];
wire [22:0] a_mant = a[22:0];
wire b_sign = b[31] ^ sub;
wire [7:0] b_expn = b[30:23];
wire [22:0] b_mant = b[22:0];
/* Stage 1 */
reg s1_iszero; /* one or both of the operands is zero */
reg s1_sign; /* sign of the result */
reg s1_issub; /* shall we do a subtraction or an addition */
reg [7:0] s1_expn_max; /* exponent of the bigger number (abs value) */
reg [7:0] s1_expn_diff; /* difference with the exponent of the smaller number (abs value) */
reg [22:0] s1_mant_max; /* mantissa of the bigger number (abs value) */
reg [22:0] s1_mant_min; /* mantissa of the smaller number (abs value) */
reg s1_valid;
/* local signals ; explicitly share the comparators */
wire expn_compare = a_expn > b_expn;
wire expn_equal = a_expn == b_expn;
wire mant_compare = a_mant > b_mant;
always @(posedge sys_clk) begin
if(alu_rst)
s1_valid <= 1'b0;
else
s1_valid <= valid_i;
s1_issub <= a_sign ^ b_sign;
if(expn_compare)
/* |b| <= |a| */
s1_sign <= a_sign;
else begin
if(expn_equal) begin
if(mant_compare)
/* |b| <= |a| */
s1_sign <= a_sign;
else
/* |b| > |a| */
s1_sign <= b_sign;
end else
/* |b| > |a| */
s1_sign <= b_sign;
end
if(expn_compare) begin
s1_expn_max <= a_expn;
s1_expn_diff <= a_expn - b_expn;
end else begin
s1_expn_max <= b_expn;
s1_expn_diff <= b_expn - a_expn;
end
if(expn_equal) begin
if(mant_compare) begin
s1_mant_max <= a_mant;
s1_mant_min <= b_mant;
end else begin
s1_mant_max <= b_mant;
s1_mant_min <= a_mant;
end
end else begin
if(expn_compare) begin
s1_mant_max <= a_mant;
s1_mant_min <= b_mant;
end else begin
s1_mant_max <= b_mant;
s1_mant_min <= a_mant;
end
end
s1_iszero <= (a_expn == 8'd0)|(b_expn == 8'd0);
end
/* Stage 2 */
reg s2_sign;
reg [7:0] s2_expn;
reg [25:0] s2_mant;
reg s2_valid;
/* local signals */
wire [24:0] max_expanded = {1'b1, s1_mant_max, 1'b0}; /* 1 guard digit */
wire [24:0] min_expanded = {1'b1, s1_mant_min, 1'b0} >> s1_expn_diff;
always @(posedge sys_clk) begin
if(alu_rst)
s2_valid <= 1'b0;
else
s2_valid <= s1_valid;
s2_sign <= s1_sign;
s2_expn <= s1_expn_max;
if(s1_iszero)
s2_mant <= {2'b01, s1_mant_max, 1'b0};
else begin
if(s1_issub)
s2_mant <= max_expanded - min_expanded;
else
s2_mant <= max_expanded + min_expanded;
end
end
/* Stage 3 */
reg s3_sign;
reg [7:0] s3_expn;
reg [25:0] s3_mant;
wire [4:0] clz;
pfpu_clz32 clz32(
.d({s2_mant, 6'bx}),
.clz(clz)
);
always @(posedge sys_clk) begin
if(alu_rst)
valid_o <= 1'b0;
else
valid_o <= s2_valid;
s3_sign <= s2_sign;
s3_mant <= s2_mant << clz;
s3_expn <= s2_expn - clz + 8'd1;
end
assign r = {s3_sign, s3_expn, s3_mant[24:2]};
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int b, l, d; cin >> b >> l >> d; long long int m = b; if (l > m) { m = l; } if (d > m) { m = d; } long long int miss = 0; if (m - 1 - b > 0) { miss += m - 1 - b; } if (m - 1 - l > 0) { miss += m - 1 - l; } if (m - 1 - d > 0) { miss += m - 1 - d; } cout << miss; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A221O_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__A221O_PP_BLACKBOX_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a221o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A221O_PP_BLACKBOX_V
|
// Test implicit casts during procedural blocking assignments.
module implicit_cast();
real src_r;
bit unsigned [7:0] src_u2;
bit signed [7:0] src_s2;
logic unsigned [7:0] src_u4;
logic signed [7:0] src_s4;
logic unsigned [7:0] src_ux;
logic signed [7:0] src_sx;
real dst_r;
bit unsigned [3:0] dst_u2s;
bit signed [3:0] dst_s2s;
bit unsigned [11:0] dst_u2l;
bit signed [11:0] dst_s2l;
logic unsigned [3:0] dst_u4s;
logic signed [3:0] dst_s4s;
logic unsigned [11:0] dst_u4l;
logic signed [11:0] dst_s4l;
bit failed;
initial begin
failed = 0;
src_r = -7;
src_u2 = 7;
src_s2 = -7;
src_u4 = 7;
src_s4 = -7;
src_ux = 8'bx0z00111;
src_sx = 8'bx0z00111;
$display("cast to real");
dst_r = src_r; $display("%g", dst_r); if (dst_r != -7.0) failed = 1;
dst_r = src_u2; $display("%g", dst_r); if (dst_r != 7.0) failed = 1;
dst_r = src_s2; $display("%g", dst_r); if (dst_r != -7.0) failed = 1;
dst_r = src_u4; $display("%g", dst_r); if (dst_r != 7.0) failed = 1;
dst_r = src_s4; $display("%g", dst_r); if (dst_r != -7.0) failed = 1;
dst_r = src_ux; $display("%g", dst_r); if (dst_r != 7.0) failed = 1;
dst_r = src_sx; $display("%g", dst_r); if (dst_r != 7.0) failed = 1;
$display("cast to small unsigned bit");
dst_u2s = src_r; $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1;
dst_u2s = src_u2; $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1;
dst_u2s = src_s2; $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1;
dst_u2s = src_u4; $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1;
dst_u2s = src_s4; $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1;
dst_u2s = src_ux; $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1;
dst_u2s = src_sx; $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1;
$display("cast to small signed bit");
dst_s2s = src_r; $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1;
dst_s2s = src_u2; $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1;
dst_s2s = src_s2; $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1;
dst_s2s = src_u4; $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1;
dst_s2s = src_s4; $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1;
dst_s2s = src_ux; $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1;
dst_s2s = src_sx; $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1;
$display("cast to large unsigned bit");
dst_u2l = src_r; $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1;
dst_u2l = src_u2; $display("%d", dst_u2l); if (dst_u2l !== 12'd7) failed = 1;
dst_u2l = src_s2; $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1;
dst_u2l = src_u4; $display("%d", dst_u2l); if (dst_u2l !== 12'd7) failed = 1;
dst_u2l = src_s4; $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1;
dst_u2l = src_ux; $display("%b", dst_u2l); if (dst_u2l !== 12'b000000000111) failed = 1;
dst_u2l = src_sx; $display("%b", dst_u2l); if (dst_u2l !== 12'b000000000111) failed = 1;
$display("cast to large signed bit");
dst_s2l = src_r; $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1;
dst_s2l = src_u2; $display("%d", dst_s2l); if (dst_s2l !== 12'sd7) failed = 1;
dst_s2l = src_s2; $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1;
dst_s2l = src_u4; $display("%d", dst_s2l); if (dst_s2l !== 12'sd7) failed = 1;
dst_s2l = src_s4; $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1;
dst_s2l = src_ux; $display("%b", dst_s2l); if (dst_s2l !== 12'b000000000111) failed = 1;
dst_s2l = src_sx; $display("%b", dst_s2l); if (dst_s2l !== 12'b000000000111) failed = 1;
$display("cast to small unsigned logic");
dst_u4s = src_r; $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1;
dst_u4s = src_u2; $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1;
dst_u4s = src_s2; $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1;
dst_u4s = src_u4; $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1;
dst_u4s = src_s4; $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1;
dst_u4s = src_ux; $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1;
dst_u4s = src_sx; $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1;
$display("cast to small signed logic");
dst_s4s = src_r; $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1;
dst_s4s = src_u2; $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1;
dst_s4s = src_s2; $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1;
dst_s4s = src_u4; $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1;
dst_s4s = src_s4; $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1;
dst_s4s = src_ux; $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1;
dst_s4s = src_sx; $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1;
$display("cast to large unsigned logic");
dst_u4l = src_r; $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1;
dst_u4l = src_u2; $display("%d", dst_u4l); if (dst_u4l !== 12'd7) failed = 1;
dst_u4l = src_s2; $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1;
dst_u4l = src_u4; $display("%d", dst_u4l); if (dst_u4l !== 12'd7) failed = 1;
dst_u4l = src_s4; $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1;
dst_u4l = src_ux; $display("%b", dst_u4l); if (dst_u4l !== 12'b0000x0z00111) failed = 1;
dst_u4l = src_sx; $display("%b", dst_u4l); if (dst_u4l !== 12'bxxxxx0z00111) failed = 1;
$display("cast to large signed logic");
dst_s4l = src_r; $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1;
dst_s4l = src_u2; $display("%d", dst_s4l); if (dst_s4l !== 12'sd7) failed = 1;
dst_s4l = src_s2; $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1;
dst_s4l = src_u4; $display("%d", dst_s4l); if (dst_s4l !== 12'sd7) failed = 1;
dst_s4l = src_s4; $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1;
dst_s4l = src_ux; $display("%b", dst_s4l); if (dst_s4l !== 12'b0000x0z00111) failed = 1;
dst_s4l = src_sx; $display("%b", dst_s4l); if (dst_s4l !== 12'bxxxxx0z00111) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_DFF_PR_SYMBOL_V
`define SKY130_FD_SC_MS__UDP_DFF_PR_SYMBOL_V
/**
* udp_dff$PR: Positive edge triggered D flip-flop with active high
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__udp_dff$PR (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET,
//# {{clocks|Clocking}}
input CLK
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_DFF_PR_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int M = 1e5 + 5; vector<pair<long long, long long>> v; int main() { ios_base::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); long long x, y, bx, by, xs, ys, t, temp1, temp2, temp; long long ax, ay; int ans = 0; cin >> x >> y >> ax >> ay >> bx >> by >> xs >> ys >> t; while (x <= 5e16 && y <= 5e16) { v.push_back({x, y}); x = ax * x + bx; y = ay * y + by; } for (int i = 0; i < v.size(); i++) { for (int j = i; j < v.size(); j++) { temp = abs(v[i].first - v[j].first) + abs(v[i].second - v[j].second); temp1 = abs(v[i].first - xs) + abs(v[i].second - ys); temp2 = abs(xs - v[j].first) + abs(ys - v[j].second); if (temp + temp1 <= t) { ans = max(ans, j - i + 1); } if (temp + temp2 <= t) { ans = max(ans, j - i + 1); } } } cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int Max = 1e6 + 100; int pa[Max << 1], son[Max << 1][27]; int deep[Max << 1], sum[Max << 1], tp[Max << 1], S[Max << 1], cnt, root, last; char str[Max << 1]; inline int Newnode(int _deep) { deep[++cnt] = _deep; return cnt; } inline void SAM(int alp) { int np = Newnode(deep[last] + 1); int u = last; S[np] = 1; memset(son[np], 0, sizeof(son[np])); while (u && !son[u][alp]) son[u][alp] = np, u = pa[u]; if (!u) pa[np] = root; else { int v = son[u][alp]; if (deep[v] == deep[u] + 1) pa[np] = v; else { int nv = Newnode(deep[u] + 1); memcpy(son[nv], son[v], sizeof(son[v])); pa[nv] = pa[v], pa[v] = pa[np] = nv; while (u && son[u][alp] == v) son[u][alp] = nv, u = pa[u]; } } last = np; } inline void toposort() { for (int i = 1; i <= deep[last]; i++) sum[i] = 0; for (int i = 1; i <= cnt; i++) sum[deep[i]]++; for (int i = 1; i <= deep[last]; i++) sum[i] += sum[i - 1]; for (int i = 1; i <= cnt; i++) tp[sum[deep[i]]--] = i; for (int i = cnt; i >= 1; i--) S[pa[tp[i]]] += S[tp[i]]; } inline void pre() { root = last = Newnode(0); } int vis[Max], Q; void solve(char *pat, int x) { int len = strlen(pat); int ans = 0, l = 0, now = root; for (int a = 0; a < len; a++) { int c = pat[a] - a ; if (son[now][c]) { now = son[now][c]; l++; } else { while (now && !son[now][c]) now = pa[now]; if (!now) now = root, l = 0; else l = deep[now] + 1, now = son[now][c]; } if (a >= x && l >= x) { int tmp = now; while (!(deep[pa[tmp]] + 1 <= x && deep[tmp] >= x)) tmp = pa[tmp]; if (vis[tmp] != Q + 1) ans += S[tmp], vis[tmp] = Q + 1; } } printf( %d n , ans); } int main() { scanf( %s , str); pre(); int len = strlen(str); for (int a = 0; a < len; a++) SAM(str[a] - a ); toposort(); scanf( %d , &Q); while (Q--) { scanf( %s , str); len = strlen(str); for (int b = 0; b < len; b++) str[b + len] = str[b]; str[len + len] = 0; solve(str, len); } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYMETAL6S2S_BEHAVIORAL_V
`define SKY130_FD_SC_HS__DLYMETAL6S2S_BEHAVIORAL_V
/**
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__dlymetal6s2s (
X ,
A ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
// Local signals
wire buf0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYMETAL6S2S_BEHAVIORAL_V |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Tue Apr 18 23:18:54 2017
// Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ bram_1024_2_stub.v
// Design : bram_1024_2
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clka, ena, wea, addra, dina, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[9:0],dina[19:0],douta[19:0]" */;
input clka;
input ena;
input [0:0]wea;
input [9:0]addra;
input [19:0]dina;
output [19:0]douta;
endmodule
|
`timescale 1ns / 1ps
//Source: http://www.bigmessowires.com/2009/06/21/fpga-pong/
//
// -----------------------------------------------
// updates the ball and paddle positions, and
// determines the output video image
// -----------------------------------------------
module game_module2015(input clk25, input Reset,
input [9:0] xpos,
input [9:0] ypos,
input rota,
input rotb,
output [2:0] red,
output [2:0] green,
output [1:0] blue);
// paddle movement
reg [8:0] paddlePosition;
reg [2:0] quadAr, quadBr;
always @(posedge clk25) quadAr <= {quadAr[1:0], rota};
always @(posedge clk25) quadBr <= {quadBr[1:0], rotb};
always @(posedge clk25)
if(quadAr[2] ^ quadAr[1] ^ quadBr[2] ^ quadBr[1])
begin
if(quadAr[2] ^ quadBr[1]) begin
if(paddlePosition < 508) // make sure the value doesn't overflow
paddlePosition <= paddlePosition + 3'd4;
end
else begin
if(paddlePosition > 2'd3) // make sure the value doesn't underflow
paddlePosition <= paddlePosition - 3'd4;
end
end
// ball movement
reg [9:0] ballX;
reg [8:0] ballY;
reg ballXdir, ballYdir;
reg bounceX, bounceY;
wire endOfFrame = (xpos == 0 && ypos == 480);
always @(posedge clk25) begin
if (endOfFrame) begin // update ball position at end of each frame
if (ballX == 0 && ballY == 0) begin // cheesy reset handling, assumes initial value of 0
ballX <= 480;
ballY <= 300;
end
else begin
if (ballXdir ^ bounceX)
ballX <= ballX + 2'd2;
else
ballX <= ballX - 2'd2;
if (ballYdir ^ bounceY)
ballY <= ballY + 2'd2;
else
ballY <= ballY - 2'd2;
end
end
end
// pixel color
reg [5:0] missTimer;
wire visible = (xpos < 640 && ypos < 480);
wire top = (visible && ypos <= 3);
wire bottom = (visible && ypos >= 476);
wire left = (visible && xpos <= 3);
wire right = (visible && xpos >= 636);
wire border = (visible && (left || right || top));
wire paddle = (xpos >= paddlePosition+4 && xpos <= paddlePosition+124 && ypos >= 440 && ypos <= 447);
wire ball = (xpos >= ballX && xpos <= ballX+7 && ypos >= ballY && ypos <= ballY+7);
wire background = (visible && !(border || paddle || ball));
wire checkerboard = (xpos[5] ^ ypos[5]);
wire missed = visible && missTimer != 0;
assign red = { missed || border || paddle, 2'b00 };
assign green = { !missed && (border || paddle || ball), 2'b00 };
assign blue = { !missed && (border || ball), background && checkerboard};
// ball collision
always @(posedge clk25) begin
if (!endOfFrame) begin
if (ball && (left || right))
bounceX <= 1;
if (ball && (top || bottom || (paddle && ballYdir)))
bounceY <= 1;
if (ball && bottom)
missTimer <= 63;
end
else begin
if (ballX == 0 && ballY == 0) begin // cheesy reset handling, assumes initial value of 0
ballXdir <= 1;
ballYdir <= 1;
bounceX <= 0;
bounceY <= 0;
end
else begin
if (bounceX)
ballXdir <= ~ballXdir;
if (bounceY)
ballYdir <= ~ballYdir;
bounceX <= 0;
bounceY <= 0;
if (missTimer != 0)
missTimer <= missTimer - 1'b1;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int q, n; bool ok(long long edg) { long long b = (edg + 1) >> 1, o = (n - b) * (n - b - 1) >> 1; return (b + min(edg >> 1, o)) == edg && b < n; } long long bs() { long long beg = 0, end = 2LL * n, mid; while (beg < end) { mid = (beg + end + 1) >> 1; if (ok(mid)) beg = mid; else end = mid - 1; } return beg; } int main() { for (scanf( %d , &q); q--;) { scanf( %d , &n); long long ans = bs(); printf( %lld n , ans); } } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:10:19 04/20/2015
// Design Name:
// Module Name: seven_seg_wrapper
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module seven_seg_wrapper(
output [6:0] segdisplay,
output [3:0] segselect,
input [15:0] pcval,
input clock,
input enable
);
reg[3:0] segsel = 4'b1110;
reg[3:0] pcpart = 4'b0000;
bin_to_seven_seg seg_1(.S(segdisplay), .D(pcpart));
always @(*)
begin
pcpart <= 4'b0000;
case(segsel)
4'b1110: pcpart <= pcval[3:0];
4'b1101: pcpart <= pcval[7:4];
4'b1011: pcpart <= pcval[11:8];
4'b0111: pcpart <= pcval[15:12];
default: pcpart <= 4'b0000;
endcase
end
always @(posedge clock)
begin
if (enable) begin
segsel <= {segsel[0],segsel[3:1]};
end
end
assign segselect = segsel;
endmodule
|
module fifo # (parameter abits = 7, dbits = 1)(
input reset, clock,
input rd, wr,
input [dbits-1:0] din,
output [dbits-1:0] dout,
output empty,
output full,
output reg ledres
);
wire db_wr, db_rd;
reg dffw1, dffw2, dffr1, dffr2;
reg [dbits-1:0] out;
//initial ledres = 0;
always @ (posedge clock) dffw1 <= wr;
always @ (posedge clock) dffw2 <= dffw1;
assign db_wr = ~dffw1 & dffw2; //monostable multivibrator to detect only one pulse of the button
always @ (posedge clock) dffr1 <= rd;
always @ (posedge clock) dffr2 <= dffr1;
assign db_rd = ~dffr1 & dffr2; //monostable multivibrator to detect only one pulse of the button
reg [dbits-1:0] regarray[2**abits-1:0]; //number of words in fifo = 2^(number of address bits)
reg [abits-1:0] wr_reg, wr_next, wr_succ; //points to the register that needs to be written to
reg [abits-1:0] rd_reg, rd_next, rd_succ; //points to the register that needs to be read from
reg full_reg, empty_reg, full_next, empty_next;
assign wr_en = db_wr & ~full; //only write if write signal is high and fifo is not full
//always block for write operation
always @ (posedge clock)
begin
if(wr_en)
regarray[wr_reg] <= din; //at wr_reg location of regarray store what is given at din
end
//always block for read operation
always @ (posedge clock)
begin
if(db_rd)
out <= regarray[rd_reg];
end
always @ (posedge clock or posedge reset)
begin
if (reset)
begin
wr_reg <= 0;
rd_reg <= 0;
full_reg <= 1'b0;
empty_reg <= 1'b1;
ledres=0;
end
else
begin
wr_reg <= wr_next; //created the next registers to avoid the error of mixing blocking and non blocking assignment to the same signal
rd_reg <= rd_next;
full_reg <= full_next;
empty_reg <= empty_next;
ledres=1;
end
end
always @(*)
begin
wr_succ = wr_reg + 1; //assigned to new value as wr_next cannot be tested for in same always block
rd_succ = rd_reg + 1; //assigned to new value as rd_next cannot be tested for in same always block
wr_next = wr_reg; //defaults state stays the same
rd_next = rd_reg; //defaults state stays the same
full_next = full_reg; //defaults state stays the same
empty_next = empty_reg; //defaults state stays the same
case({db_wr,db_rd})
//2'b00: do nothing LOL..
2'b01: //read
begin
if(~empty) //if fifo is not empty continue
begin
rd_next = rd_succ;
full_next = 1'b0;
if(rd_succ == wr_reg) //all data has been read
empty_next = 1'b1; //its empty again
end
end
2'b10: //write
begin
if(~full) //if fifo is not full continue
begin
wr_next = wr_succ;
empty_next = 1'b0;
if(wr_succ == (2**abits-1)) //all registers have been written to
full_next = 1'b1; //its full now
end
end
2'b11: //read and write
begin
wr_next = wr_succ;
rd_next = rd_succ;
end
//no empty or full flag will be checked for or asserted in this state since data is being written to and read from together it can not get full in this state.
endcase
end
assign full = full_reg;
assign empty = empty_reg;
assign dout = out;
endmodule
|
/*
Copyright 2015, Google Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module ftl_free_fifo (
input wire clk_50,
input wire reset_n,
input wire [9:0] fifo_data_in,
input wire fifo_data_wr,
output wire [9:0] fifo_data_out,
output reg fifo_data_valid,
input wire fifo_data_rd,
output wire fifo_empty
);
`include "ftl_const.vh"
reg fifo_data_wr_1;
reg fifo_data_rd_1;
//
// storage for the free block fifo
//
reg [9:0] bram_fifo_wraddr;
reg [9:0] bram_fifo_rdaddr;
reg [9:0] bram_fifo_data;
reg bram_fifo_wren;
wire [9:0] bram_fifo_q;
reg [3:0] state;
parameter [3:0] ST_RESET = 'd0,
ST_IDLE = 'd1,
ST_UNK = 'd2;
assign fifo_data_out = bram_fifo_q;
assign fifo_empty = (bram_fifo_rdaddr == bram_fifo_wraddr);
always @(posedge clk_50) begin
bram_fifo_wren <= 0;
fifo_data_wr_1 <= fifo_data_wr;
fifo_data_rd_1 <= fifo_data_rd;
case(state)
ST_RESET: begin
bram_fifo_rdaddr <= 0; // 1020? why
bram_fifo_wraddr <= 0;
fifo_data_valid <= 0;
state <= ST_IDLE;
end
ST_IDLE: begin
if(fifo_data_wr & ~fifo_data_wr_1) begin
// new write
bram_fifo_data <= fifo_data_in;
bram_fifo_wren <= 1'b1;
end else if(fifo_data_rd & ~fifo_data_rd_1) begin
// new read
if(!fifo_empty) begin
fifo_data_valid <= 1;
end
end
if(~fifo_data_wr & fifo_data_wr_1) begin
bram_fifo_wraddr <= bram_fifo_wraddr + 1'b1;
end
if(~fifo_data_rd & fifo_data_rd_1) begin
fifo_data_valid <= 0;
if(fifo_data_valid) begin
bram_fifo_rdaddr <= bram_fifo_rdaddr + 1'b1;
end
end
end
endcase
if(~reset_n) begin
state <= ST_RESET;
end
end
ftl_bram_block_dp #(10, 10) iffbram (
.a_clk ( clk_50 ),
.a_wr ( bram_fifo_wren ),
.a_addr ( bram_fifo_wraddr ),
.a_din ( bram_fifo_data ),
.a_dout ( ),
.b_clk ( clk_50 ),
.b_wr ( 1'b0 ),
.b_addr ( bram_fifo_rdaddr ),
.b_din ( 'h0 ),
.b_dout ( bram_fifo_q )
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Jonathan Whitaker
//
// Create Date: 17:51:49 04/07/2014
// Module Name: fourbit_cpu
// Description: This verilog module implements a 4-bit cpu with manual instruction
// entry or ROM instruction entry.
//////////////////////////////////////////////////////////////////////////////////
module fourbit_cpu(clk, clr, sw, btn, led, decimal, enable, segs);
// Inputs.
input clk, clr;
input [7:0] sw;
input [1:0] btn;
// Outputs.
output [3:0] led, enable;
output [6:0] segs;
output decimal;
// Internal wires.
wire [3:0] Rin, Rout, usr_Data, run_Data, BUS, G, Aoper, ALUout;
wire LEDRegEn, Ain, Gin, Gout, usr_load, run_load, inst_done, rom_done;
wire [1:0] ALUOp, bin;
wire [3:0] Q[3:0];
wire [7:0] rom_inst;
// Debounce the push button inputs.
DeBouncer btn0(clk, clr, btn[0], bin[0]);
DeBouncer btn1(clk, clr, btn[1], bin[1]);
// 7-segment display.
LED_7SEG seg(clk, clr, Q[0], Q[1], Q[2], Q[3], decimal, enable, segs);
// Internal rom module.
internal_rom rom(clk, clr, inst_done, rom_inst, rom_done);
// CPU controller.
cpu_controller ctrl(clk, clr, bin, sw, rom_inst, 1'b1, rom_done, LEDRegEn, Rin, Rout, Ain, Gin, Gout, usr_load, run_load, usr_Data, run_Data, ALUOp, inst_done);
// General registers.
regn R0(BUS, Rin[0], clk, clr, Q[0]);
regn R1(BUS, Rin[1], clk, clr, Q[1]);
regn R2(BUS, Rin[2], clk, clr, Q[2]);
regn R3(BUS, Rin[3], clk, clr, Q[3]);
// Tri-state buffers.
trin T0(Q[0], Rout[0], BUS);
trin T1(Q[1], Rout[1], BUS);
trin T2(Q[2], Rout[2], BUS);
trin T3(Q[3], Rout[3], BUS);
trin TG(G, Gout, BUS);
trin TUL(usr_Data, usr_load, BUS);
trin TRL(run_Data, run_load, BUS);
// LED register.
regn LEDReg(BUS, LEDRegEn, clk, clr, led);
// ALU registers.
regn regA(BUS, Ain, clk, clr, Aoper); // Aoper = Operand(A)
regn regG(ALUout, Gin, clk, clr, G);
// ALU
ALU alu(Aoper, BUS, ALUOp, ALUout);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 200000 + 10; const long long INF = 0x3f3f3f3f3f3f3f3fLL; long long dp[105][105][105]; long long c[105], val[105][105], ans = INF; int main() { int i, j, K, n, m, k; cin >> n >> m >> K; for (i = 1; i <= n; i++) cin >> c[i]; for (i = 1; i <= n; i++) { for (j = 1; j <= m; j++) { cin >> val[i][j]; } } memset(dp, 0x3f, sizeof(dp)); dp[0][0][0] = 0; for (i = 0; i < n; i++) { for (j = 0; j <= m; j++) { for (k = 0; k <= i; k++) { if (dp[i][j][k] != INF) { if (c[i + 1]) { dp[i + 1][c[i + 1]][k + (c[i + 1] != j)] = min(dp[i + 1][c[i + 1]][k + (c[i + 1] != j)], dp[i][j][k]); } else { for (int p = 1; p <= m; p++) { dp[i + 1][p][k + (p != j)] = min(dp[i][j][k] + val[i + 1][p], dp[i + 1][p][k + (p != j)]); } } } } } } for (i = 1; i <= m; i++) { ans = min(dp[n][i][K], ans); } if (ans == INF) cout << -1 << endl; else cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int t[123]; int main() { ios::sync_with_stdio(0); cin.tie(0); int a, n; cin >> n >> a; --a; for (int i = 0; i < n; ++i) cin >> t[i]; int l, r; l = r = a; int res = 0; while (l >= 0 || r < n) { if (l >= 0 && r < n) { if (t[l] > 0 && t[r] > 0) res += t[l] + t[r]; } else if (l >= 0) res += t[l]; else res += t[r]; --l, ++r; } if (t[a] > 0) res--; cout << res << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; const long long inf = 1e9; const long long ninf = LLONG_MIN; const double eps = 1e-12; const long long N = 1000005; const long long LOGN = 19; const double PI = 3.14159265358979323846; long long n, m; long long d[505][505], is[505][505], ini[505][505], last[505][505]; int main() { ios_base::sync_with_stdio(0); cin >> n >> m; for (int i = 0; i < 505; i++) for (int j = 0; j < 505; j++) d[i][j] = inf, ini[i][j] = inf; for (int i = 0; i < m; i++) { long long x, y, l; cin >> x >> y >> l; d[x][y] = l; d[y][x] = l; ini[x][y] = l; ini[y][x] = l; is[x][y] = 1; is[y][x] = 1; } for (int i = 1; i <= n; i++) d[i][i] = 0; for (int k = 1; k <= n; k++) { for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { d[i][j] = min(d[i][j], d[i][k] + d[k][j]); } } } for (int i = 1; i <= n; i++) { for (int k = 1; k <= n; k++) { for (int j = 1; j <= n; j++) { if (d[i][j] == inf) continue; if (d[i][k] + ini[k][j] == d[i][j]) { last[i][j]++; } } } } for (int i = 1; i <= n; i++) { for (int j = i + 1; j <= n; j++) { long long ans = 0; for (int k = 1; k <= n; k++) { if (d[i][k] + d[k][j] == d[i][j]) { ans += last[i][k]; } } cout << ans << ; } } cout << n ; return 0; } |
//-----------------------------------------------------------------------------------------
//-- txstr: Uart_tx example 2
//-- Transmission of string
//-- The reset signal is connected to the dtr signal (in file txstr.pcf)
//-- Fot this example to work is necessary to open a serial terminal
//-- (gtkterm for example)
//-- and deactivate DTR. Every time a reset is done, a string appears
//-- on the terminal
//-- Fixed BAUDRATE: 115200
//-----------------------------------------------------------------------------
`default_nettype none
`include "baudgen.vh"
//-- Top entity
module txstr #(
parameter BAUDRATE = `B115200
)(
input wire clk, //-- System clock
input wire go, //-- When to transmit the string (pulse)
output wire tx //-- Serial data output
);
//-- Serial Unit instantation
uart_tx #(
.BAUDRATE(BAUDRATE) //-- Set the baudrate
) TX0 (
.clk(clk),
.data(data),
.start(start),
.tx(tx),
.ready(ready)
);
//-- Connecting wires
wire ready;
reg start = 0;
reg [7:0] data = 0;
//-- Multiplexer with the 8-character string to transmit
//-- As it is a long string, it would be a better solution to
//-- store it into a rom memory (it is easier to change the text)
always @*
case (char_count)
8'd0: data <= "H";
8'd1: data <= "o";
8'd2: data <= "l";
8'd3: data <= "a";
8'd4: data <= "!";
8'd5: data <= " ";
8'd6: data <= "S";
8'd7: data <= "o";
8'd8: data <= "y";
8'd9: data <= " ";
8'd10: data <= "t";
8'd11: data <= "u";
8'd12: data <= " ";
8'd13: data <= "I";
8'd14: data <= "c";
8'd15: data <= "e";
8'd16: data <= "z";
8'd17: data <= "u";
8'd18: data <= "m";
8'd19: data <= " ";
8'd20: data <= "A";
8'd21: data <= "l";
8'd22: data <= "h";
8'd23: data <= "a";
8'd24: data <= "m";
8'd25: data <= "b";
8'd26: data <= "r";
8'd27: data <= "a";
8'd28: data <= " ";
8'd29: data <= ":";
8'd30: data <= "-";
8'd31: data <= ")";
default: data <= ".";
endcase
//-- Characters counter
//-- It only counts when the cena control signal is enabled
reg [4:0] char_count = 0;
reg cena = 0; //-- Counter enable
always @(posedge clk)
if (cena)
char_count = char_count + 1;
//--------------------- CONTROLLER
localparam INI = 0;
localparam TXCAR = 1;
localparam NEXTCAR = 2;
localparam WAIT = 3;
//-- fsm state
reg [1:0] state = INI;
reg [1:0] next_state;
//-- Transition between states
always @(posedge clk) begin
state <= next_state;
end
//-- Control signal generation and next states
always @(*) begin
next_state = state;
start = 0;
cena = 0;
case (state)
//-- Initial state. Start the trasmission
INI: begin
start = 1;
next_state = TXCAR;
end
//-- Wait until one car is transmitted
TXCAR: begin
if (ready)
next_state = NEXTCAR;
end
//-- Increment the character counter
//-- Finish when it is the last character
NEXTCAR: begin
cena = 1;
if (char_count == 31)
next_state = WAIT;
else
next_state = INI;
end
WAIT: begin
if (go)
next_state = INI;
end
default: begin
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND4_TB_V
`define SKY130_FD_SC_HDLL__NAND4_TB_V
/**
* nand4: 4-input NAND.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nand4.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_hdll__nand4 dut (.A(A), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND4_TB_V
|
/*
* Wishbone Compatible BIOS ROM core using megafunction ROM
* Copyright (C) 2010 Donna Polehn <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
// The following is to get rid of the warning about not initializing the ROM
// altera message_off 10030
module bootrom (
input clk,
input rst,
// Wishbone slave interface
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [19:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input wb_stb_i,
input wb_cyc_i,
input [ 1:0] wb_sel_i,
output wb_ack_o
);
// Net declarations
reg [15:0] rom[0:127]; // Instantiate the ROM
wire [ 6:0] rom_addr;
wire stb;
// Combinatorial logic
assign rom_addr = wb_adr_i[7:1];
assign stb = wb_stb_i & wb_cyc_i;
assign wb_ack_o = stb;
assign wb_dat_o = rom[rom_addr];
initial $readmemh("bootrom.dat", rom);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MM = 120000; vector<int> G[MM], T[MM]; int P[MM], L[MM]; void dfs(int u, int par) { P[u] = par; if (par != -1) L[u] = L[par] + 1; for (auto v : G[u]) { if (v != par) { dfs(v, u); } } } int N, K; bool rip = 0; void dfs2(int u, int par, int lev) { int kek = 0; for (auto v : G[u]) { if (v != par) { kek++; dfs2(v, u, lev + 1); } } if (kek < 3 && kek != 0) { rip = 1; } if (kek == 0 && lev != K) { rip = 1; } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> N >> K; for (int i = 0; i < N - 1; i++) { int u, v; cin >> u >> v; G[u - 1].push_back(v - 1); G[v - 1].push_back(u - 1); } dfs(0, -1); int mx = 0; int el = -1; for (int i = 0; i < N; i++) { mx = max(mx, L[i]); if (mx == L[i]) { el = i; } } if (mx >= K) { mx = K; while (mx--) el = P[el]; int rt = el; dfs2(rt, -1, 0); if (rip) { cout << No ; } else { cout << Yes ; } } else { cout << No ; return 0; } return 0; } |
`timescale 1 ps / 1 ps
module Sobel_cache (
input clk,
input rst,
input start,
input [ADD_WIDTH-1:0] base_add,
input [13:0] rdaddress,
output wire [12:0] valid_lines,
input free_line,
output wire [ 7:0] q,
output wire [ADD_WIDTH-1:0] ram_r_address,
input ram_r_waitrequest,
input ram_r_readdatavalid,
output wire [BYTE_ENABLE_WIDTH-1:0] ram_r_byteenable,
output wire ram_r_read,
input [DATA_WIDTH-1:0] ram_r_readdata,
output wire [BURST_WIDTH_R-1:0] ram_r_burstcount
);
parameter DATA_WIDTH=32;
parameter ADD_WIDTH = 32;
parameter BYTE_ENABLE_WIDTH = 4;
parameter BURST_WIDTH_R = 6;
parameter MAX_BURST_COUNT_R = 32;
reg [ADD_WIDTH-1:0] read_address;
reg [ADD_WIDTH-1:0] write_address;
reg [12:0] used_cache_pixels;
reg [31:0] in_n;
always @(posedge clk or posedge rst) begin
if (rst == 1) begin
in_n <= 0;
end else begin
if (start == 1) begin
in_n <= 384000;
end else begin
if (read_burst_end == 1) begin
in_n <= in_n - MAX_BURST_COUNT_R;
end
end
end
end
always @(posedge clk) begin
if (start == 1) begin
read_address <= base_add;
end else begin
if (read_burst_end == 1) begin
read_address <= read_address + MAX_BURST_COUNT_R * BYTE_ENABLE_WIDTH;
end
end
end
// reg [ 3:0] valid;
always @(posedge clk) begin
if (start == 1) begin
used_cache_pixels <= 0;
end else begin
if (read_complete == 1) begin
if (free_line == 0) begin
used_cache_pixels <= used_cache_pixels + 1;
end else begin
used_cache_pixels <= used_cache_pixels - 799;
end
end else begin
if (free_line == 1) begin
used_cache_pixels <= used_cache_pixels - 800;
end
end
end
end
assign valid_lines = used_cache_pixels;
reg [31:0] reads_pending;
always @ (posedge clk) begin
if (start == 1) begin
reads_pending <= 0;
end else begin
if(read_burst_end == 1) begin
if(read_complete == 0) begin
reads_pending <= reads_pending + MAX_BURST_COUNT_R;
end else begin
reads_pending <= reads_pending + MAX_BURST_COUNT_R - 1;
end
end else begin
if(read_complete == 0) begin
reads_pending <= reads_pending;
end else begin
reads_pending <= reads_pending - 1;
end
end
end
end
reg [31:0] next_r;
always @ (posedge clk) begin
if (start == 1) begin
next_r <= 0;
end else begin
if(read_burst_end == 1) begin
next_r <= 0;
end else begin
if (ram_r_read == 1) begin
next_r <= 1;
end
end
end
end
always @(posedge clk) begin
if (start == 1) begin
write_address <= 0;
end else begin
if (read_complete == 1) begin
if (write_address == 7999) begin
write_address <= 0;
end else begin
write_address <= write_address + 1;
end
end
end
end
altsyncram altsyncram_component (
.clock0 (clk),
.data_a (ram_r_readdata[7:0]),
.address_a (write_address),
.wren_a (read_complete),
.address_b (rdaddress),
.q_b (q),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({8{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 8192,
altsyncram_component.numwords_b = 8192,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 13,
altsyncram_component.widthad_b = 13,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1;
assign read_complete = (ram_r_readdatavalid == 1);
assign read_burst_end = (ram_r_waitrequest == 0) & (next_r == 1);
assign too_many_reads_pending = (reads_pending + used_cache_pixels) > (8000 - MAX_BURST_COUNT_R);
assign ram_r_address = read_address;
assign ram_r_read = (too_many_reads_pending == 0) & (in_n != 0);
assign ram_r_byteenable = {BYTE_ENABLE_WIDTH{1'b1}};
assign ram_r_burstcount = MAX_BURST_COUNT_R;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKBUF_FUNCTIONAL_V
`define SKY130_FD_SC_LS__CLKBUF_FUNCTIONAL_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__clkbuf (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKBUF_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; namespace thecold { inline int read() { int res = 0; bool flag = false; char c = getchar(); while (!isdigit(c)) flag = (c == - ), c = getchar(); while (isdigit(c)) res = res * 10 + (c ^ 48), c = getchar(); return !flag ? res : -res; } const int Max_n = 1e5 + 5; int bak[Max_n], n, m, q; struct node { int l, r, tagl, tagv, mx, mmx; node(int a, int b) { l = a, r = b, tagv = tagl = mx = mmx = 0; } node() {} } tree[Max_n << 3]; inline void push_up(const int tr) { int ls = tr << 1, rs = tr << 1 | 1; if (tree[tr].l == tree[tr].r) return; if (tree[ls].mx > tree[rs].mx) tree[tr].mx = tree[ls].mx, tree[tr].mmx = max(tree[ls].mmx, tree[rs].mx); else if (tree[ls].mx < tree[rs].mx) tree[tr].mx = tree[rs].mx, tree[tr].mmx = max(tree[ls].mx, tree[rs].mmx); else tree[tr].mx = tree[ls].mx, tree[tr].mmx = max(tree[ls].mmx, tree[rs].mmx); } inline void build(const int l, const int r, const int tr) { tree[tr] = node(l, r); if (l == r) return tree[tr].mx = l, tree[tr].mmx = -Max_n, void(); int mid = (l + r) >> 1; build(l, mid, tr << 1), build(mid + 1, r, tr << 1 | 1); push_up(tr); } inline void cop(node &a, node b, const int tr) { a.mx = a.tagv = b.tagv, !a.tagl && (a.tagl = b.tagl); } inline void push_down(const int tr) { if (!tree[tr].tagl) return; int ls = tr << 1, rs = tr << 1 | 1; if (tree[ls].mx == tree[tr].tagl) cop(tree[ls], tree[tr], tr); if (tree[rs].mx == tree[tr].tagl) cop(tree[rs], tree[tr], tr); tree[tr].tagl = tree[tr].tagv = 0; } inline void change(const int l, const int r, const int va, const int lim, const int tr) { int ll = tree[tr].l, rr = tree[tr].r; if (ll > r || rr < l) return; if (tree[tr].mx < lim) return; push_down(tr); if (l <= ll && rr <= r) { if (tree[tr].mmx < lim) return tree[tr].tagl = tree[tr].mx, tree[tr].tagv = tree[tr].mx = va, void(); } change(l, r, va, lim, tr << 1), change(l, r, va, lim, tr << 1 | 1); push_up(tr); } int ans[Max_n]; struct Node { int l, bel; Node(int a, int b) { l = a, bel = b; } Node() {} }; vector<Node> v[Max_n]; inline int query(const int pos, const int tr) { int ll = tree[tr].l, rr = tree[tr].r; if (ll == rr) return tree[tr].mx; push_down(tr); int mid = (ll + rr) >> 1; if (mid >= pos) return query(pos, tr << 1); return query(pos, tr << 1 | 1); } inline void main() { n = read(), m = read(); build(1, n, 1); for (int i = 1; i <= m; ++i) { int ui = read(), vi = read(); bak[vi] = ui; } q = read(); for (int i = 1; i <= q; ++i) { int li = read(), ri = read(); v[ri].push_back(Node(li, i)); } for (int now = 1; now <= n; ++now) { if (bak[now]) change(1, bak[now], now, bak[now], 1); int sz = v[now].size(); for (int i = 0; i < sz; ++i) ans[v[now][i].bel] = query(v[now][i].l, 1); } for (int i = 1; i <= q; ++i) printf( %d n , ans[i]); } } // namespace thecold int main() { thecold::main(); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, k, trap[510]; int e[510][510]; long double t[510][510]; const long double EPS = 1e-9; void mult(long double a[110][110], long double b[110][110], long double c[110][110]) { long double r[110][110] = {}; for (int i = 0; i < (int)(110); i++) for (int j = 0; j < (int)(110); j++) for (int k = 0; k < (int)(110); k++) r[i][k] += a[i][j] * b[j][k]; for (int i = 0; i < (int)(110); i++) for (int j = 0; j < (int)(110); j++) c[i][j] = r[i][j]; } int main() { scanf( %d %d %d , &n, &m, &k); for (int i = 0; i < n; i++) scanf( %d , &trap[i]); while (m--) { int x, y; scanf( %d %d , &x, &y); --x; --y; ++e[x][y]; ++e[y][x]; } for (int i = 0; i < n; i++) if (!trap[i]) { int deg = 0; for (int j = 0; j < n; j++) deg += e[i][j]; for (int j = 0; j < n; j++) t[i][j] -= (long double)e[i][j] / deg; t[i][i] += 1.0; } else { t[i][i] = 1.0; } for (int i = 0; i < n; i++) if (!trap[i]) { int j = i; for (int k = i; k < n; k++) if (abs(t[k][i]) > abs(t[j][i])) j = k; for (int k = 0; k < n; k++) swap(t[i][k], t[j][k]); double scale = t[i][i]; for (int k = 0; k < n; k++) t[i][k] /= scale; for (int j = 0; j < n; j++) if (j != i) { scale = t[j][i]; for (int k = 0; k < n; k++) t[j][k] -= t[i][k] * scale; } } for (int i = 0; i < n; i++) if (trap[i]) t[i][i] = -1.0; long double m[110][110] = {}, v[510][510] = {}, r[110][110] = {}; int nr[510], next = 0; for (int i = 0; i < n; i++) if (trap[i]) nr[i] = next++; for (int i = 0; i < n; i++) if (trap[i]) { int deg = 0; for (int j = 0; j < n; j++) deg += e[i][j]; for (int j = 0; j < n; j++) for (int k = 0; k < n; k++) v[i][k] -= t[j][k] / deg * e[i][j]; for (int j = 0; j < n; j++) if (trap[j]) m[nr[i]][nr[j]] = v[i][j]; } for (int i = 0; i < next; i++) r[i][i] = 1.0; k -= 2; while (k) { if (k & 1) mult(m, r, r); mult(m, m, m); k /= 2; } long double ans = 0.0; for (int i = 0; i < n; i++) if (trap[i]) { ans += -t[0][i] * r[nr[i]][next - 1]; } printf( %.9lf n , (double)ans); return 0; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_tagctlrep.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module sctag_tagctlrep(/*AUTOARG*/
// Outputs
sctag_scdata_set_c2, sctag_scdata_way_sel_c2,
sctag_scdata_col_offset_c2, sctag_scdata_rd_wr_c2,
sctag_scdata_word_en_c2, sctag_scdata_fbrd_c3,
sctag_scdata_fb_hit_c3,
// Inputs
scdata_set_c2, scdata_way_sel_c2, scdata_col_offset_c2,
scdata_rd_wr_c2, scdata_word_en_c2, scdata_fbrd_c3,
scdata_fb_hit_c3
);
input [9:0] scdata_set_c2; // Left
input [11:0] scdata_way_sel_c2;
input [3:0] scdata_col_offset_c2;
input scdata_rd_wr_c2;
input [15:0] scdata_word_en_c2;
input scdata_fbrd_c3;
input scdata_fb_hit_c3;
output [9:0] sctag_scdata_set_c2; // Right
output [11:0] sctag_scdata_way_sel_c2; // Right
output [3:0] sctag_scdata_col_offset_c2; // Right
output sctag_scdata_rd_wr_c2; // Right
output [15:0] sctag_scdata_word_en_c2; // Right
output sctag_scdata_fbrd_c3; // Right
output sctag_scdata_fb_hit_c3; // Right
// 46 control bits.
assign sctag_scdata_fb_hit_c3 = scdata_fb_hit_c3;
assign sctag_scdata_fbrd_c3 = scdata_fbrd_c3 ;
assign sctag_scdata_word_en_c2 = scdata_word_en_c2;
assign sctag_scdata_rd_wr_c2 = scdata_rd_wr_c2 ;
assign sctag_scdata_col_offset_c2 = scdata_col_offset_c2 ;
assign sctag_scdata_way_sel_c2 = scdata_way_sel_c2;
assign sctag_scdata_set_c2 = scdata_set_c2 ;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); string s; cin >> s; long long a = -1, b = -1; int flag = 0; for (int i = 0; i < s.length(); i++) { if (s[i] == [ ) { a = i; flag = 1; break; } } if (flag == 0) { cout << -1 ; return 0; } flag = 0; for (int i = a; i < s.length(); i++) { if (s[i] == : ) { a = i; flag = 1; break; } } if (flag == 0) { cout << -1 ; return 0; } flag = 0; for (int i = s.length() - 1; i >= 0; i--) { if (s[i] == ] ) { b = i; flag = 1; break; } } if (flag == 0) { cout << -1 ; return 0; } flag = 0; for (int i = b; i >= 0; i--) { if (s[i] == : ) { b = i; flag = 1; break; } } if (flag == 0) { cout << -1 ; return 0; } if (a >= b) { cout << -1 ; return 0; } long long ans = 4; for (int i = a + 1; i <= b - 1; i++) { if (s[i] == | ) ans++; } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; int dx8[] = {1, 1, 0, -1, -1, -1, 0, 1}; int dy8[] = {0, 1, 1, 1, 0, -1, -1, -1}; int dx4[] = {1, 0, -1, 0}; int dy4[] = {0, 1, 0, -1}; template <typename Arg1> void __f(const char *name, Arg1 &&arg1) { cerr << name << : << arg1 << n ; ; } template <typename Arg1, typename... Args> void __f(const char *names, Arg1 &&arg1, Args &&...args) { const char *comma = strchr(names + 1, , ); cerr.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } template <class A, class B> ostream &operator<<(ostream &out, const pair<A, B> &a) { return out << ( << a.first << , << a.second << ) ; } template <class A> ostream &operator<<(ostream &out, const vector<A> &a) { for (const A &it : a) out << it << ; return out; } template <class A, class B> istream &operator>>(istream &in, pair<A, B> &a) { return in >> a.first >> a.second; } template <class A> istream &operator>>(istream &in, vector<A> &a) { for (A &i : a) in >> i; return in; } template <typename T, typename T1> T amax(T &a, T1 b) { if (b > a) a = b; return a; } template <typename T, typename T1> T amin(T &a, T1 b) { if (b < a) a = b; return a; } void solve() { long long n, m, k; cin >> n >> m >> k; multiset<long long> mp; vector<long long> v(n); cin >> v; vector<long long> t = v; sort((t).begin(), (t).end(), greater<long long>()); long long sum = 0; for (long long i = 0; i < m * k; i++) { mp.insert(t[i]); sum += t[i]; } int i = 0; vector<long long> res; while (i < n) { int j = i; int cnt = 0; while (j < n && cnt < m) { if (mp.find(v[j]) != mp.end()) { mp.erase(mp.find(v[j])); cnt++; } j++; } res.push_back(j); if ((int)((mp).size()) == m) { break; } i = j; } cout << sum << n ; ; cout << res << n ; ; } int main() { ios_base::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); int t = 1; while (t--) { solve(); } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:58:11 07/01/2012
// Design Name:
// Module Name: GPIO
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module GPIO(input clk,
input rst,
input Start,
input EN,
input [31:0] P_Data,
output reg[1:0] counter_set,
output [15:0] LED_out,
output wire ledclk,
output wire ledsout,
output wire ledclrn,
output wire LEDEN,
output reg[13:0] GPIOf0
);
reg [15:0]LED;
// GPIO out use on LEDs & Counter-Controler read and write
assign LED_out = LED;
always @(negedge clk or posedge rst) begin
if(rst)begin LED <= 8'h2A; counter_set<=2'b00; end
else if(EN) {GPIOf0[13:0],LED,counter_set} <= P_Data; //Counter ch1 ch0
else begin LED <= LED; counter_set<=counter_set; end
end
LEDP2S #(.DATA_BITS(16),.DATA_COUNT_BITS(4),.DIR(0))
LEDP2S(.clk(clk),
.rst(rst),
.Start(Start),
// .PData(~LED),
.PData(LED),
.sclk(ledclk),
.sclrn(ledclrn),
.sout(ledsout),
.EN(LEDEN)
);
/* LED_P2S #(.DATA_BITS(16),.DATA_COUNT_BITS(4))
LED_P2S(clk, rst, Start,
{~{LED[0],LED[1],LED[2],LED[3],LED[4],LED[5],LED[6],LED[7],
LED[8],LED[9],LED[10],LED[11],LED[12],LED[13],LED[14],LED[15]}},
led_clk,
led_clrn,
led_sout,
LED_PEN
);
*/
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long k, n, s, p; cin >> k >> n >> s >> p; long long w = n / s; if (n % s != 0) w++; w *= k; long long ans = w / p; if (w % p != 0) ans++; cout << ans << endl; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DIODE_SYMBOL_V
`define SKY130_FD_SC_HD__DIODE_SYMBOL_V
/**
* diode: Antenna tie-down diode.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__diode (
//# {{power|Power}}
input DIODE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DIODE_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main(void) { string s, t; cin >> s >> t; int ind = -1; for (int i = 0; i < s.length(); i++) { if (s[i] != 0 ) break; else ind = i; } s = s.substr(ind + 1); ind = -1; for (int i = 0; i < t.length(); i++) { if (t[i] != 0 ) break; else ind = i; } t = t.substr(ind + 1); if (s.length() != t.length()) { if (s.length() > t.length()) cout << > n ; else cout << < n ; return 0; } for (int i = 0; i < s.length(); i++) { if (s[i] != t[i]) { if (s[i] > t[i]) cout << > n ; else cout << < n ; return 0; } } cout << = n ; return 0; } |
#include <bits/stdc++.h> using namespace std; char str[100010]; int main() { int ans[] = {4, 0, 0, 0}; while (~scanf( %s , str)) { int tmp = 0; int len = strlen(str); for (int i = 0; i < len; ++i) { tmp = tmp * 10 + str[i] - 0 ; tmp %= 4; } printf( %d n , ans[tmp]); } return 0; } |
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 00:29:41 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_rst_ps7_0_100M_1/zynq_design_1_rst_ps7_0_100M_1_stub.v
// Design : zynq_design_1_rst_ps7_0_100M_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "proc_sys_reset,Vivado 2017.2" *)
module zynq_design_1_rst_ps7_0_100M_1(slowest_sync_clk, ext_reset_in, aux_reset_in,
mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset,
interconnect_aresetn, peripheral_aresetn)
/* synthesis syn_black_box black_box_pad_pin="slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */;
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
output [0:0]bus_struct_reset;
output [0:0]peripheral_reset;
output [0:0]interconnect_aresetn;
output [0:0]peripheral_aresetn;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int i, j, ans = 1, val[256], v; string s, p; cin >> s; char a; for (a = 0 ; a <= 9 ; a++) { p.push_back(a); } for (a = A ; a <= Z ; a++) { p.push_back(a); } for (a = a ; a <= z ; a++) { p.push_back(a); } p.push_back( - ); p.push_back( _ ); for (i = 0; i <= 63; ++i) { val[p[i]] = i; } for (i = 0; i < s.length(); ++i) { v = val[s[i]]; for (j = 0; j < 6; ++j) { if ((v & (1 << j)) == 0) { ans = (ans * 3) % 1000000007; } } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, k, l, r, sall, sk; cin >> n >> k >> l >> r >> sall >> sk; int el[n]; int div, mod, m, sm; m = n - k; sm = sall - sk; if (k > 0) { div = sk / k; mod = sk % k; for (int i = 0; i < k; i++) { el[i] = div; if (i < mod) { el[i] += 1; } } } if (m > 0) { div = sm / m; mod = sm % m; for (int i = 0; i < m; i++) { el[i + k] = div; if (i < mod) { el[i + k] += 1; } } } for (int i = 0; i < n; i++) { cout << el[i] << ; } } |
#include <bits/stdc++.h> using namespace std; struct P { double x, y; } a[259]; long long f[259][259]; int n; int read() { long long x = 0, f = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) f = -1; ch = getchar(); } while (isdigit(ch)) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } double cross(P a, P b, P c) { P x = (P){b.x - a.x, b.y - a.y}; P y = (P){c.x - a.x, c.y - a.y}; return x.x * y.y - x.y * y.x; } bool jud() { double ans = 0; for (int i = 2; i <= n; i++) ans += cross(a[1], a[i - 1], a[i]); if (ans > 0) return 1; return 0; } void rever() { for (int i = 1; i <= n / 2; i++) swap(a[i], a[n - i + 1]); } int main() { n = read(); for (int i = 1; i <= n; i++) scanf( %lf%lf , &a[i].x, &a[i].y); if (jud()) rever(); for (int i = 1; i <= n; i++) f[i][i + 1] = 1; for (int l = 1; l <= n - 1; l++) for (int i = 1; i + l <= n; i++) for (int j = i + 1; j < i + l; j++) f[i][i + l] = (f[i][i + l] + f[i][j] % 1000000007 * f[j][i + l] % 1000000007 * (cross(a[i], a[j], a[i + l]) < 0 ? 1 : 0)) % 1000000007; printf( %lld n , f[1][n] % 1000000007); return 0; } |
/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* Generic source synchronous DDR input
*/
module ssio_ddr_in #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// IODDR style ("IODDR", "IODDR2")
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
// Use IODDR2 for Spartan-6
parameter IODDR_STYLE = "IODDR2",
// Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2")
// Use BUFR for Virtex-6, 7-series
// Use BUFG for Virtex-5, Spartan-6, Ultrascale
parameter CLOCK_INPUT_STYLE = "BUFG",
// Width of register in bits
parameter WIDTH = 1
)
(
input wire input_clk,
input wire [WIDTH-1:0] input_d,
output wire output_clk,
output wire [WIDTH-1:0] output_q1,
output wire [WIDTH-1:0] output_q2
);
wire clk_int;
wire clk_io;
generate
if (TARGET == "XILINX") begin
// use Xilinx clocking primitives
if (CLOCK_INPUT_STYLE == "BUFG") begin
// buffer RX clock
BUFG
clk_bufg (
.I(input_clk),
.O(clk_int)
);
// pass through RX clock to logic and input buffers
assign clk_io = clk_int;
assign output_clk = clk_int;
end else if (CLOCK_INPUT_STYLE == "BUFR") begin
assign clk_int = input_clk;
// pass through RX clock to input buffers
BUFIO
clk_bufio (
.I(clk_int),
.O(clk_io)
);
// pass through RX clock to logic
BUFR #(
.BUFR_DIVIDE("BYPASS")
)
clk_bufr (
.I(clk_int),
.O(output_clk),
.CE(1'b1),
.CLR(1'b0)
);
end else if (CLOCK_INPUT_STYLE == "BUFIO") begin
assign clk_int = input_clk;
// pass through RX clock to input buffers
BUFIO
clk_bufio (
.I(clk_int),
.O(clk_io)
);
// pass through RX clock to MAC
BUFG
clk_bufg (
.I(clk_int),
.O(output_clk)
);
end
end else begin
// pass through RX clock to input buffers
assign clk_io = input_clk;
// pass through RX clock to logic
assign clk_int = input_clk;
assign output_clk = clk_int;
end
endgenerate
iddr #(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.WIDTH(WIDTH)
)
data_iddr_inst (
.clk(clk_io),
.d(input_d),
.q1(output_q1),
.q2(output_q2)
);
endmodule
`resetall
|
#include <bits/stdc++.h> using namespace std; int dx[] = {0, 0, 1, -1, 1, -1, 1, -1}; int dy[] = {1, -1, 0, 0, -1, 1, 1, -1}; long long gcd(long long a, long long b) { return !b ? a : gcd(b, a % b); } long long lcm(long long a, long long b) { return (a / gcd(a, b)) * b; } long long power(long long a, long long b, long long ret = 1LL) { while (b--) ret = (ret * a); return ret; } char a[105]; int main() { long long n, k; cin >> n >> k; int ans = 0; for (int i = 1; i <= n; i++) { int cnt = 0; long long x; cin >> x; while (x > 0) { if (x % 10 == 7 || x % 10 == 4) { cnt++; } x /= 10; } if (cnt <= k) ans++; } cout << ans; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013, David M. Lloyd
//
// This file is part of the PBIBox suite.
//
// PBIBox is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// PBIBox is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with PBIBox. If not, see <http://www.gnu.org/licenses/>.
//
//////////////////////////////////////////////////////////////////////////////////
module PBIBox(
input [15:0] Addr,
input DMA_in,
output DMA_out,
input EXTSEL_in,
output EXTSEL_out,
input EXTCPU,
input EXTMEM,
output D1FF,
output D1XX,
output D6XX,
output D8XX
);
assign D1FF = (Addr == 'hD1FF) ? 'b0 : 'bz;
assign D1XX = (Addr[15:8] == 'hD1) && (Addr[7:0] != 'hFF) ? 'b0 : 'bz;
assign D6XX = (Addr[15:9] == ('hD6 >> 1)) ? 'b0 : 'bz;
assign D8XX = (Addr[15:11] == ('hD8 >> 3)) ? 'b0 : 'bz;
assign DMA_out = (!DMA_in || !EXTCPU) ? 'b0 : 'bz;
assign EXTSEL_out = (!EXTSEL_in || !EXTMEM) ? 'b0 : 'bz;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFXTP_BLACKBOX_V
`define SKY130_FD_SC_MS__SDFXTP_BLACKBOX_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sdfxtp (
Q ,
CLK,
D ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFXTP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n, m, b, mod; int a[505]; int dp[505][505]; int main() { scanf( %d%d%d%d , &n, &m, &b, &mod); for (int i = 1; i <= n; ++i) scanf( %d , a + i); dp[0][0] = 1; for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { for (int k = a[i]; k <= b; ++k) { dp[j][k] += dp[j - 1][k - a[i]]; if (dp[j][k] >= mod) dp[j][k] -= mod; } } } int ans = 0; for (int i = 0; i <= b; ++i) { ans += dp[m][i]; if (ans >= mod) ans -= mod; } printf( %d n , ans); } |
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 24080 $
// $Date: 2011-05-18 15:32:52 -0400 (Wed, 18 May 2011) $
`ifdef BSV_WARN_REGFILE_ADDR_RANGE
`else
`define BSV_WARN_REGFILE_ADDR_RANGE 0
`endif
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// Multi-ported Register File
module RegFile(CLK,
ADDR_IN, D_IN, WE,
ADDR_1, D_OUT_1,
ADDR_2, D_OUT_2,
ADDR_3, D_OUT_3,
ADDR_4, D_OUT_4,
ADDR_5, D_OUT_5
);
parameter addr_width = 1;
parameter data_width = 1;
parameter lo = 0;
parameter hi = 1;
input CLK;
input [addr_width - 1 : 0] ADDR_IN;
input [data_width - 1 : 0] D_IN;
input WE;
input [addr_width - 1 : 0] ADDR_1;
output [data_width - 1 : 0] D_OUT_1;
input [addr_width - 1 : 0] ADDR_2;
output [data_width - 1 : 0] D_OUT_2;
input [addr_width - 1 : 0] ADDR_3;
output [data_width - 1 : 0] D_OUT_3;
input [addr_width - 1 : 0] ADDR_4;
output [data_width - 1 : 0] D_OUT_4;
input [addr_width - 1 : 0] ADDR_5;
output [data_width - 1 : 0] D_OUT_5;
(* RAM_STYLE = "DISTRIBUTED" *)
reg [data_width - 1 : 0] arr[lo:hi];
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin : init_block
integer i; // temporary for generate reset value
for (i = lo; i <= hi; i = i + 1) begin
arr[i] = {((data_width + 1)/2){2'b10}} ;
end
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
always@(posedge CLK)
begin
if (WE)
arr[ADDR_IN] <= `BSV_ASSIGNMENT_DELAY D_IN;
end // always@ (posedge CLK)
assign D_OUT_1 = arr[ADDR_1];
assign D_OUT_2 = arr[ADDR_2];
assign D_OUT_3 = arr[ADDR_3];
assign D_OUT_4 = arr[ADDR_4];
assign D_OUT_5 = arr[ADDR_5];
// synopsys translate_off
always@(posedge CLK)
begin : runtime_check
reg enable_check;
enable_check = `BSV_WARN_REGFILE_ADDR_RANGE ;
if ( enable_check )
begin
if (( ADDR_1 < lo ) || (ADDR_1 > hi) )
$display( "Warning: RegFile: %m -- Address port 1 is out of bounds: %h", ADDR_1 ) ;
if (( ADDR_2 < lo ) || (ADDR_2 > hi) )
$display( "Warning: RegFile: %m -- Address port 2 is out of bounds: %h", ADDR_2 ) ;
if (( ADDR_3 < lo ) || (ADDR_3 > hi) )
$display( "Warning: RegFile: %m -- Address port 3 is out of bounds: %h", ADDR_3 ) ;
if (( ADDR_4 < lo ) || (ADDR_4 > hi) )
$display( "Warning: RegFile: %m -- Address port 4 is out of bounds: %h", ADDR_4 ) ;
if (( ADDR_5 < lo ) || (ADDR_5 > hi) )
$display( "Warning: RegFile: %m -- Address port 5 is out of bounds: %h", ADDR_5 ) ;
if ( WE && ( ADDR_IN < lo ) || (ADDR_IN > hi) )
$display( "Warning: RegFile: %m -- Write Address port is out of bounds: %h", ADDR_IN ) ;
end
end
// synopsys translate_on
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module axi_interfaces_AXILiteS_s_axi
#(parameter
C_S_AXI_ADDR_WIDTH = 4,
C_S_AXI_DATA_WIDTH = 32
)(
// axi4 lite slave signals
input wire ACLK,
input wire ARESET,
input wire ACLK_EN,
input wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR,
input wire AWVALID,
output wire AWREADY,
input wire [C_S_AXI_DATA_WIDTH-1:0] WDATA,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB,
input wire WVALID,
output wire WREADY,
output wire [1:0] BRESP,
output wire BVALID,
input wire BREADY,
input wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR,
input wire ARVALID,
output wire ARREADY,
output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA,
output wire [1:0] RRESP,
output wire RVALID,
input wire RREADY,
output wire interrupt,
// user signals
output wire ap_start,
input wire ap_done,
input wire ap_ready,
input wire ap_idle
);
//------------------------Address Info-------------------
// 0x0 : Control signals
// bit 0 - ap_start (Read/Write/COH)
// bit 1 - ap_done (Read/COR)
// bit 2 - ap_idle (Read)
// bit 3 - ap_ready (Read)
// bit 7 - auto_restart (Read/Write)
// others - reserved
// 0x4 : Global Interrupt Enable Register
// bit 0 - Global Interrupt Enable (Read/Write)
// others - reserved
// 0x8 : IP Interrupt Enable Register (Read/Write)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0xc : IP Interrupt Status Register (Read/TOW)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
//------------------------Parameter----------------------
localparam
ADDR_AP_CTRL = 4'h0,
ADDR_GIE = 4'h4,
ADDR_IER = 4'h8,
ADDR_ISR = 4'hc,
WRIDLE = 2'd0,
WRDATA = 2'd1,
WRRESP = 2'd2,
WRRESET = 2'd3,
RDIDLE = 2'd0,
RDDATA = 2'd1,
RDRESET = 2'd2,
ADDR_BITS = 4;
//------------------------Local signal-------------------
reg [1:0] wstate = WRRESET;
reg [1:0] wnext;
reg [ADDR_BITS-1:0] waddr;
wire [31:0] wmask;
wire aw_hs;
wire w_hs;
reg [1:0] rstate = RDRESET;
reg [1:0] rnext;
reg [31:0] rdata;
wire ar_hs;
wire [ADDR_BITS-1:0] raddr;
// internal registers
wire int_ap_idle;
wire int_ap_ready;
reg int_ap_done = 1'b0;
reg int_ap_start = 1'b0;
reg int_auto_restart = 1'b0;
reg int_gie = 1'b0;
reg [1:0] int_ier = 2'b0;
reg [1:0] int_isr = 2'b0;
//------------------------Instantiation------------------
//------------------------AXI write fsm------------------
assign AWREADY = (wstate == WRIDLE);
assign WREADY = (wstate == WRDATA);
assign BRESP = 2'b00; // OKAY
assign BVALID = (wstate == WRRESP);
assign wmask = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} };
assign aw_hs = AWVALID & AWREADY;
assign w_hs = WVALID & WREADY;
// wstate
always @(posedge ACLK) begin
if (ARESET)
wstate <= WRRESET;
else if (ACLK_EN)
wstate <= wnext;
end
// wnext
always @(*) begin
case (wstate)
WRIDLE:
if (AWVALID)
wnext = WRDATA;
else
wnext = WRIDLE;
WRDATA:
if (WVALID)
wnext = WRRESP;
else
wnext = WRDATA;
WRRESP:
if (BREADY)
wnext = WRIDLE;
else
wnext = WRRESP;
default:
wnext = WRIDLE;
endcase
end
// waddr
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (aw_hs)
waddr <= AWADDR[ADDR_BITS-1:0];
end
end
//------------------------AXI read fsm-------------------
assign ARREADY = (rstate == RDIDLE);
assign RDATA = rdata;
assign RRESP = 2'b00; // OKAY
assign RVALID = (rstate == RDDATA);
assign ar_hs = ARVALID & ARREADY;
assign raddr = ARADDR[ADDR_BITS-1:0];
// rstate
always @(posedge ACLK) begin
if (ARESET)
rstate <= RDRESET;
else if (ACLK_EN)
rstate <= rnext;
end
// rnext
always @(*) begin
case (rstate)
RDIDLE:
if (ARVALID)
rnext = RDDATA;
else
rnext = RDIDLE;
RDDATA:
if (RREADY & RVALID)
rnext = RDIDLE;
else
rnext = RDDATA;
default:
rnext = RDIDLE;
endcase
end
// rdata
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (ar_hs) begin
rdata <= 1'b0;
case (raddr)
ADDR_AP_CTRL: begin
rdata[0] <= int_ap_start;
rdata[1] <= int_ap_done;
rdata[2] <= int_ap_idle;
rdata[3] <= int_ap_ready;
rdata[7] <= int_auto_restart;
end
ADDR_GIE: begin
rdata <= int_gie;
end
ADDR_IER: begin
rdata <= int_ier;
end
ADDR_ISR: begin
rdata <= int_isr;
end
endcase
end
end
end
//------------------------Register logic-----------------
assign interrupt = int_gie & (|int_isr);
assign ap_start = int_ap_start;
assign int_ap_idle = ap_idle;
assign int_ap_ready = ap_ready;
// int_ap_start
always @(posedge ACLK) begin
if (ARESET)
int_ap_start <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0] && WDATA[0])
int_ap_start <= 1'b1;
else if (int_ap_ready)
int_ap_start <= int_auto_restart; // clear on handshake/auto restart
end
end
// int_ap_done
always @(posedge ACLK) begin
if (ARESET)
int_ap_done <= 1'b0;
else if (ACLK_EN) begin
if (ap_done)
int_ap_done <= 1'b1;
else if (ar_hs && raddr == ADDR_AP_CTRL)
int_ap_done <= 1'b0; // clear on read
end
end
// int_auto_restart
always @(posedge ACLK) begin
if (ARESET)
int_auto_restart <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0])
int_auto_restart <= WDATA[7];
end
end
// int_gie
always @(posedge ACLK) begin
if (ARESET)
int_gie <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_GIE && WSTRB[0])
int_gie <= WDATA[0];
end
end
// int_ier
always @(posedge ACLK) begin
if (ARESET)
int_ier <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_IER && WSTRB[0])
int_ier <= WDATA[1:0];
end
end
// int_isr[0]
always @(posedge ACLK) begin
if (ARESET)
int_isr[0] <= 1'b0;
else if (ACLK_EN) begin
if (int_ier[0] & ap_done)
int_isr[0] <= 1'b1;
else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
int_isr[0] <= int_isr[0] ^ WDATA[0]; // toggle on write
end
end
// int_isr[1]
always @(posedge ACLK) begin
if (ARESET)
int_isr[1] <= 1'b0;
else if (ACLK_EN) begin
if (int_ier[1] & ap_ready)
int_isr[1] <= 1'b1;
else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
int_isr[1] <= int_isr[1] ^ WDATA[1]; // toggle on write
end
end
//------------------------Memory logic-------------------
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 5000 + 10; int n, a[N], dp[N][N][2]; int calc(int i, int rem, bool isLess) { if (rem == 0) return 0; if (i >= n) return 2e9; int &ret = dp[i][rem][isLess]; if (ret != -1) return ret; ret = 2e9; if (isLess) { if (i != n - 1) { int h = a[i + 1]; int extra = max(h - a[i] + 1, 0); h -= extra; ret = min(ret, extra + calc(i + 2, rem - 1, h < a[i + 2])); if (i != n - 2) { int h = a[i + 1]; int extra = max(h - a[i + 2] + 1, 0); h -= extra; ret = min(ret, extra + calc(i + 2, rem - (h < a[i]), h < a[i + 2])); } ret = min(ret, calc(i + 1, rem, a[i] < a[i + 1])); if (a[i] >= a[i + 1]) ret = min(ret, (a[i] - a[i + 1] + 1) + calc(i + 1, rem, true)); } else ret = min(ret, calc(i + 1, rem - 1, false)); } else { if (i != n - 1) { ret = min(ret, calc(i + 1, rem, a[i] < a[i + 1])); if (a[i] >= a[i + 1]) ret = min(ret, (a[i] - a[i + 1] + 1) + calc(i + 1, rem, true)); } } return ret; } int main() { scanf( %d , &n); for (int i = 0; i < n; ++i) scanf( %d , a + i); memset(dp, -1, sizeof dp); int k = (n + 1) / 2; for (int i = 1; i <= k; ++i) printf( %d , calc(0, i, true)); puts( ); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFXTP_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__SDFXTP_FUNCTIONAL_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_p/sky130_fd_sc_hdll__udp_dff_p.v"
`celldefine
module sky130_fd_sc_hdll__sdfxtp (
Q ,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hdll__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFXTP_FUNCTIONAL_V |
#include <bits/stdc++.h> int main() { int x, y, z, i, j, k, a, b, c, n, m, t, mat[210210]; scanf( %d , &t); long long w, sum; while (t--) { scanf( %d %lld , &n, &w); j = -1; sum = 0; c = 0; for (x = 0; x < n; x++) { scanf( %d , &mat[x]); if (mat[x] >= (w + 1) / 2 && mat[x] <= w) j = x; if (mat[x] <= w) sum += mat[x]; } if (j != -1) printf( 1 n%d n , j + 1); else if (sum < (w + 1) / 2) puts( -1 ); else { x = -1; if (sum > w) { for (x = 0; x < n; x++) { if (mat[x] > w) continue; sum -= mat[x]; if (sum >= (w + 1) / 2 && sum <= w) break; } } for (y = x + 1; y < n; y++) if (mat[y] <= w) c++; printf( %d n , c); for (y = x + 1; y < n; y++) if (mat[y] <= w) printf( %d , y + 1); puts( ); } } return 0; } |
//`define HIGH_BIOS 13'h0000
`define HIGH_BIOS 13'h00FF
module flash_dump (
input sys_clk_in,
output trx,
output [20:0] flash_addr,
input [15:0] flash_data,
output flash_we_n,
output flash_oe_n,
output flash_ce2
);
reg clk_9600;
reg [11:0] count_uart;
reg [ 6:0] dada_wr;
reg [ 7:0] estat;
reg [ 7:0] addr;
reg [ 2:0] espacios;
reg [ 6:0] char;
reg [ 3:0] nibble;
reg [ 7:0] col;
reg trx_req;
reg [ 7:0] adr0;
wire clk_60M;
wire rst, lock;
wire trx_ack;
wire [15:0] rd_data;
reg [15:0] ram[0:255];
reg [15:0] dades;
reg [ 3:0] count;
// Instanciacions de mòduls
clocks c0 (
.CLKIN_IN (sys_clk_in),
.CLKFX_OUT (clk_60M),
.LOCKED_OUT (lock)
);
uart_ctrl u0 (dada_wr, trx_req, trx_ack, trx,
rst, clk_9600);
// Assignacions contínues
assign rst = ~lock;
assign flash_addr = { `HIGH_BIOS, adr0 };
assign rd_data = flash_data;
assign flash_we_n = 1'b1;
assign flash_oe_n = 1'b0;
assign flash_ce2 = 1'b1;
// Descripció del comportament
// count_uart
always @(posedge clk_60M)
if (rst) count_uart <= 12'h0;
else count_uart <= (count_uart==12'd3124) ?
12'd0 : count_uart + 12'd1;
// clk_9600
always @(posedge clk_60M)
if (rst) clk_9600 <= 1'b0;
else clk_9600 <= (count_uart==12'd0) ?
!clk_9600 : clk_9600;
// adr0
always @(posedge clk_60M)
if (rst) adr0 <= 8'h00;
else adr0 <= (adr0==8'hff || count!=4'hf) ? adr0
: (adr0 + 8'h01);
// count
always @(posedge clk_60M)
if (rst) count <= 4'h0;
else count <= count + 4'h1;
// ram
always @(posedge clk_60M) ram[adr0] <= rd_data;
// dades
always @(posedge clk_60M)
if (rst) dades <= 16'h0;
else dades <= ram[addr];
always @(posedge clk_60M)
if (adr0!=8'hff)
begin
dada_wr <= 7'h30;
trx_req <= 0;
estat <= 8'd0;
addr <= 8'h00;
espacios <= 3'd2;
char <= 7'd00;
nibble <= 4'd0;
col <= 8'd79;
end
else
case (estat)
8'd00: if (~trx_ack)
begin estat <= 8'd01;
if (espacios > 3'd0)
begin char <= 7'h20; espacios <= espacios - 3'd1; end
else
begin
char <= ascii(nibble); espacios <= 3'd4;
nibble <= nibble + 4'd1;
end
end
8'd01: begin dada_wr <= char; trx_req <= 1; estat <= 8'd2; end
8'd02: if (trx_ack) begin trx_req <= 0; estat <= 8'd3; end
8'd03: if (col > 8'd0) begin col <= col - 8'd1; estat <= 8'd0; end
else estat <= 8'd04;
8'd04: if (~trx_ack) estat <= 8'd05;
8'd05: begin dada_wr <= ascii(addr[7:4]); trx_req <= 1; estat <= 8'd10; end
8'd10: if (trx_ack) begin trx_req <= 0; estat <= 8'd15; end
8'd15: if (~trx_ack) estat <= 8'd20;
8'd20: begin dada_wr <= ascii(dades[15:12]); trx_req <= 1; estat <= 8'd25; end
8'd25: if (trx_ack) begin trx_req <= 0; estat <= 8'd30; end
8'd30: if (~trx_ack) estat <= 8'd35;
8'd35: begin dada_wr <= ascii(dades[11:8]); trx_req <= 1; estat <= 8'd40; end
8'd40: if (trx_ack) begin trx_req <= 0; estat <= 8'd45; end
8'd45: if (~trx_ack) estat <= 8'd50;
8'd50: begin dada_wr <= ascii(dades[7:4]); trx_req <= 1; estat <= 8'd55; end
8'd55: if (trx_ack) begin trx_req <= 0; estat <= 8'd60; end
8'd60: if (~trx_ack) estat <= 8'd65;
8'd65: begin dada_wr <= ascii(dades[3:0]); trx_req <= 1; estat <= 8'd70; end
8'd70: if (trx_ack) begin trx_req <= 0; estat <= 8'd75; end
8'd75: if (addr[3:0] == 4'hf) estat <= 8'd90;
else if (~trx_ack) estat <= 8'd80;
8'd80: begin dada_wr <= 7'h20; trx_req <= 1; estat <= 8'd85; end
8'd85: if (trx_ack) begin trx_req <= 0; estat <= 8'd90; end
8'd90: if (addr < 9'h0ff) begin addr <= addr + 8'd1; estat <= 8'd91; end
else estat <= 8'd95;
8'd91: estat <= (addr[3:0]==4'h0) ? 8'd4 : 8'd15;
endcase
function [6:0] ascii(input [3:0] num);
if (num <= 4'd9) ascii = 7'h30 + num;
else ascii = 7'd87 + num;
endfunction
endmodule
|
#include <bits/stdc++.h> int main() { int n, m; int a, b; int min1, min2; int s1 = 0, s2 = 0, k1 = 0, k2 = 0; scanf( %d%d , &n, &m); while (n--) { scanf( %d , &a); if (a % 2 == 0) s1++; else s2++; } while (m--) { scanf( %d , &b); if (b % 2 == 0) k1++; else k2++; } if (s1 > k2) min1 = k2; else min1 = s1; if (k1 > s2) min2 = s2; else min2 = k1; printf( %d , min1 + min2); } |
#include <bits/stdc++.h> using namespace std; int main() { int k; int l; cin >> k >> l; int u[k]; int y[l]; for (int i = 0; i < k; i++) { cin >> u[i]; } for (int i = 0; i < l; i++) { cin >> y[i]; } long long int h = 0; long long int v = 0; int f = 0; int g = 0; int p = 0; while (p != k || g != l) { if (v == h && v == 0) { v += y[g]; h += u[p]; g++; p++; } else if (v > h) { h += u[p]; p++; } else if (v < h) { v += y[g]; g++; } else { f++; h = 0; v = 0; } } cout << f + 1; return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:28:30 03/06/2016
// Design Name: summed
// Module Name: C:/XilinxP/Practica1/summed_test.v
// Project Name: Practica1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: summed
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module summed_test;
// Inputs
reg xi;
reg yi;
// Outputs
wire Si;
wire Co;
// Instantiate the Unit Under Test (UUT)
summed uut (
.xi(xi),
.yi(yi),
.Si(Si),
.Co(Co)
);
initial begin
$display("...");
// Initialize Inputs
xi = 0;
yi = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
xi = 0; yi = 0; //00
#50;
$display("xi = %b, yi = %b, Si = %b, Co = %b", xi, yi, Si, Co);
xi = 0; yi = 1; //01
#50;
$display("xi = %b, yi = %b, Si = %b, Co = %b", xi, yi, Si, Co);
xi = 1; yi = 0; //10
#50;
$display("xi = %b, yi = %b, Si = %b, Co = %b", xi, yi, Si, Co);
xi = 1; yi = 1; //11
#50;
$display("xi = %b, yi = %b, Si = %b, Co = %b", xi, yi, Si, Co);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long a[200100]; int main() { long long k, Answer = 0; int n; cin >> n >> k; for (int i = 0; i < n; i++) scanf( %I64d , &a[i]); for (int i = 0; i < n; i++) { Answer += a[i] / k; a[i] = a[i] % k; if (a[i] + a[i + 1] >= k) a[i + 1] += a[i]; else if (a[i] > 0) { a[i + 1] = 0; Answer++; } } cout << Answer; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 2e6 + 500; const long double eps = (1e-12); const int logn = 21; const double Pi = acos(-1.0); const long long pp = 998244353; int lowbit(int x) { return x & (-x); } const long long INF = 1e11 + 7; long long dp[3][205][4]; long long a[MAXN]; long long pre[MAXN]; long long lst[MAXN]; signed main() { long long n; scanf( %lld , &n); for (long long i = 1; i <= n; i++) { scanf( %lld , &a[i]); } dp[0][1][2] = 1; long long now = 0; for (long long i = 1; i <= n; i++) { now ^= 1; for (long long j = 1; j <= 200; j++) { pre[j] = lst[j] = 0; for (long long k = 0; k <= 2; k++) dp[now][j][k] = 0; } for (long long k = 0; k <= 2; k++) pre[1] += dp[now ^ 1][1][k]; for (long long j = 2; j <= 200; j++) { for (long long k = 0; k <= 2; k++) pre[j] += dp[now ^ 1][j][k]; pre[j] %= pp; pre[j] += pre[j - 1]; pre[j] %= pp; } for (long long k = 1; k <= 2; k++) lst[200] += dp[now ^ 1][200][k]; for (long long j = 199; j > 0; j--) { for (long long k = 1; k <= 2; k++) lst[j] += dp[now ^ 1][j][k]; lst[j] %= pp; lst[j] += lst[j + 1]; lst[j] %= pp; } for (long long j = 1; j <= 200; j++) { dp[now][j][0] += pre[j - 1]; dp[now][j][0] %= pp; dp[now][j][1] += dp[now ^ 1][j][0] + dp[now ^ 1][j][1] + dp[now ^ 1][j][2]; dp[now][j][1] %= pp; dp[now][j][2] += lst[j + 1]; dp[now][j][2] %= pp; } if (a[i] != -1) { for (long long j = 1; j <= 200; j++) { if (j == a[i]) continue; for (long long k = 0; k <= 2; k++) { dp[now][j][k] = 0; } } } } long long ans = 0; for (long long j = 1; j <= 200; j++) { for (long long k = 1; k <= 2; k++) { ans += dp[now][j][k]; ans %= pp; } } printf( %lld , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; bool comp(const vector<int> &l, const vector<int> &r) { if (l[0] % 2 && r[0] % 2) { return l[1] < r[1]; } if ((l[0] % 2) && (r[0] % 2 == 0)) return true; if ((l[0] % 2 == 0) && (r[0] % 2)) return false; else return true; } int main() { int tmp, ans, test, c, i, j, n, k, t, odd, ans1 = 0, ans2 = 0; vector<int> ar[102], v; scanf( %d , &test); for (int i = 1; i <= test; i++) { scanf( %d , &n); ar[i].push_back(n); if (n % 2 == 0) { ans = 0; for (k = 1; k <= n / 2; k++) { scanf( %d , &t); ans += t; } ar[i].push_back(ans); ans = 0; for (k = 1; k <= n / 2; k++) { scanf( %d , &t); ans += t; } ar[i].push_back(ans); ar[i].push_back(-1); } else { ans = 0; for (k = 1; k <= n / 2; k++) { scanf( %d , &t); ans += t; } ar[i].push_back(ans); scanf( %d , &odd); ans = 0; for (k = 1; k <= n / 2; k++) { scanf( %d , &t); ans += t; } ar[i].push_back(ans); ar[i].push_back(odd); v.push_back(odd); } } for (i = 1; i <= test; i++) { if (1 || ar[i][0] % 2 == 0) { ans1 += ar[i][1]; ans2 += ar[i][2]; } } sort(v.begin(), v.end()); reverse(v.begin(), v.end()); bool ok = true; for (i = 0; i < v.size(); i++) { if (ok) ans1 += v[i]; else ans2 += v[i]; ok = !ok; } cout << ans1 << << ans2 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long maxn = 1e5 + 5; long long n, a[maxn], dp[maxn][2], f[maxn][2], d[maxn]; long long head[maxn], ecnt; struct edge { long long to, next; } e[maxn << 1]; void adde(long long u, long long v) { e[++ecnt].to = v; e[ecnt].next = head[u]; head[u] = ecnt; } long long read() { long long res = 0, f = 1; char ch; do { ch = getchar(); if (ch == - ) f = -1; } while (!isdigit(ch)); do { res = res * 10 + ch - 0 ; ch = getchar(); } while (isdigit(ch)); return res * f; } void dfs1(long long u, long long fa) { dp[u][0] = dp[u][1] = f[u][0] = d[u] = a[u]; for (long long i = head[u]; i; i = e[i].next) { long long v = e[i].to; if (v == fa) continue; dfs1(v, u); dp[u][0] = max(dp[u][0], dp[v][0]); dp[u][0] = max(dp[u][0], dp[u][1] + dp[v][1]); dp[u][0] = max(dp[u][0], d[u] + f[v][0]); dp[u][0] = max(dp[u][0], d[v] + f[u][0]); dp[u][1] = max(dp[u][1], dp[v][1]); dp[u][1] = max(dp[u][1], d[u] + d[v]); f[u][0] = max(f[u][0], a[u] + f[v][0]); f[u][0] = max(f[u][0], d[u] + dp[v][1]); f[u][0] = max(f[u][0], a[u] + d[v] + f[u][1]); f[u][1] = max(f[u][1], dp[v][1]); d[u] = max(d[u], d[v] + a[u]); } } signed main() { n = read(); for (long long i = (1); i <= (n); ++i) a[i] = read(); for (long long i = (1); i <= (n - 1); ++i) { long long u = read(), v = read(); adde(u, v); adde(v, u); } dfs1(1, 0); printf( %lld n , dp[1][0]); } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; const long long mod = 1e9 + 7; long long qpow(long long a, long long b) { long long res = 1; while (b) { if (b & 1) res = res * a % mod; a = a * a % mod; b >>= 1; } return res; } int n; int vis[N], prime[N], num, mu[N], inv[N]; void makeMobius(int siz) { mu[1] = 1, num = 0; for (int i = 2; i <= siz; i++) { if (!vis[i]) prime[++num] = i, mu[i] = -1; for (int j = 1; j <= num && i * prime[j] <= siz; j++) { vis[i * prime[j]] = 1; if (i % prime[j] == 0) { mu[i * prime[j]] = 0; break; } else mu[i * prime[j]] = mu[i] * mu[prime[j]]; } } inv[1] = 1; for (int i = 2; i <= siz; i++) inv[i] = qpow(i, mod - 2); } long long calc(long long d) { long long y = n / d; return y * inv[n - y] % mod; } int main() { scanf( %d , &n); makeMobius(n); long long ans = 1; for (int d = 2; d <= n; d++) ans = (ans - calc(d) * mu[d] % mod + mod) % mod; printf( %lld n , (ans + mod) % mod); return 0; } |
#include <bits/stdc++.h> using namespace std; long long nt[105]; string s; vector<long long> V; void ts() { nt[0] = 0; nt[1] = 0; for (long long i = 2; i <= 100; i++) { nt[i] = 1; } for (long long i = 2; i <= 100; i++) { if (nt[i] == 1) { for (long long j = i * i; j <= 100; j += i) { nt[j] = 0; } V.push_back(i); } } } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); V.push_back(4); V.push_back(9); V.push_back(25); V.push_back(49); ts(); long long i = 0; long long dem = 0; while (i < 20) { cout << V[i] << endl; cin >> s; if (s == yes ) dem++; if (dem == 2) { cout << composite ; return 0; } i++; } cout << prime ; return 0; } |
// (C) 1992-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_custom_add_wrapper(clock, resetn, dataa, datab, result, valid_in, valid_out, stall_in, stall_out, enable);
input clock, resetn;
input valid_in, stall_in;
output valid_out, stall_out;
input enable;
input [36:0] dataa;
input [36:0] datab;
output [37:0] result;
parameter HIGH_CAPACITY = 0;
parameter FLUSH_DENORMS = 0;
parameter HIGH_LATENCY = 0;
parameter ROUNDING_MODE = 0;
parameter FINITE_MATH_ONLY = 1;
parameter REMOVE_STICKY = 1;
// Total Latency = 12-7.
wire [26:0] input_a_mantissa = dataa[26:0];
wire [26:0] input_b_mantissa = datab[26:0];
wire input_a_sign = dataa[36];
wire input_b_sign = datab[36];
wire [8:0] input_a_exponent = dataa[35:27];
wire [8:0] input_b_exponent = datab[35:27];
wire [26:0] left_mantissa;
wire [26:0] right_mantissa;
wire left_sign, right_sign, align_valid_out;
wire [8:0] align_exponent;
wire stall_align;
wire conversion_valid = valid_in;
wire alignment_stall;
assign stall_out = alignment_stall;
acl_fp_custom_align alignment(
.clock(clock),
.resetn(resetn),
.input_a_mantissa(input_a_mantissa),
.input_a_exponent(input_a_exponent),
.input_a_sign(input_a_sign),
.input_b_mantissa(input_b_mantissa),
.input_b_exponent(input_b_exponent),
.input_b_sign(input_b_sign),
.left_mantissa(left_mantissa),
.left_exponent(align_exponent),
.left_sign(left_sign),
.right_mantissa(right_mantissa),
.right_exponent(),
.right_sign(right_sign),
.valid_in(conversion_valid),
.valid_out(align_valid_out),
.stall_in(stall_align),
.stall_out(alignment_stall),
.enable(enable));
defparam alignment.HIGH_CAPACITY = HIGH_CAPACITY;
defparam alignment.FLUSH_DENORMS = FLUSH_DENORMS;
defparam alignment.HIGH_LATENCY = HIGH_LATENCY;
defparam alignment.ROUNDING_MODE = ROUNDING_MODE;
defparam alignment.FINITE_MATH_ONLY = FINITE_MATH_ONLY;
defparam alignment.REMOVE_STICKY = REMOVE_STICKY;
wire [27:0] resulting_mantissa;
wire [8:0] resulting_exponent;
wire resulting_sign;
wire valid_sum;
acl_fp_custom_add_op op(
.clock(clock),
.resetn(resetn),
.left_mantissa(left_mantissa),
.right_mantissa(right_mantissa),
.left_sign(left_sign),
.right_sign(right_sign),
.common_exponent(align_exponent),
.resulting_mantissa(resulting_mantissa),
.resulting_exponent(resulting_exponent),
.resulting_sign(resulting_sign),
.valid_in(align_valid_out),
.valid_out(valid_out),
.stall_in(stall_in),
.stall_out(stall_align),
.enable(enable));
defparam op.HIGH_CAPACITY = HIGH_CAPACITY;
assign result = {resulting_sign, resulting_exponent, resulting_mantissa};
endmodule
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } template <class T1, class T2> struct cmpf { bool rev; inline bool operator()(const pair<T1, T2>& a, const pair<T1, T2>& b) const { return (a.first < b.first) ^ rev; } cmpf(bool b = false) { rev = b; } }; template <class T1, class T2> struct cmps { bool rev; inline bool operator()(const pair<T1, T2>& a, const pair<T1, T2>& b) const { return (a.second < b.second) ^ rev; } cmps(bool b = false) { rev = b; } }; string to_string(const char& c) { return string(1, c); } string to_string(const string& s) { return + s + ; } string to_string(const char* s) { return to_string((string)s); } string to_string(const bool& b) { return (b ? true : false ); } string to_string(const vector<bool>& v, const string& sep = ) { string s = [ ; for (int i = 0; i < v.size(); i++) { if (i) { s += sep; } s += to_string(v[i]); } return s + ] ; } template <size_t N> string to_string(const bitset<N>& v) { string s = [ ; for (size_t i = 0; i < N; i++) s += v[i] ? 1 : 0 ; return s + ] ; } template <class T1, class T2> string to_string(const pair<T1, T2>& p, const string& sep = , ); template <class T> string to_string(const T& v, const string& sep = ) { bool first = true; string s = { ; for (const auto& x : v) { if (!first) s += sep; else first = false; s += to_string(x); } return s + } ; } template <class T> string to_string(const T& v, const int& sz, const string& sep = ) { string s = [ ; for (int i = 0; i < sz; i++) { if (i) { s += sep; } s += to_string(v[i]); } return s + ] ; } template <class T1, class T2> string to_string(const pair<T1, T2>& p, const string& sep) { return ( + to_string(p.first) + sep + to_string(p.second) + ) ; } long long binpow(const long long& x, const long long& p, const long long& mod) { assert(mod > 0); if (p == 0) return 1; if (p == 1) return x % mod; if (p & 1) return (binpow((x * x) % mod, p / 2, mod) * x) % mod; return binpow((x * x) % mod, p / 2, mod) % mod; } template <class T> void chmn(T& a, const T& b) { if (a > b) a = b; } template <class T> void chmx(T& a, const T& b) { if (a < b) a = b; } void setIO() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); } int chr[8] = {-1, 0, 1, 0, -1, -1, 1, 1}; int chc[8] = {0, 1, 0, -1, -1, 1, -1, 1}; const long long MOD = 1e9 + 7; const int INIT = 1001001001; const int MN = 255; bool mat[MN][MN]; int N, M; inline const bool out(int r, int c) { return r <= 0 || r > N || c <= 0 || c > M; } inline const bool ok(int r, int c, int skip1, int skip2, int n) { if (out(r, c) || !mat[r][c]) return false; for (int i = 0; i < n; i++) { if (i != skip1 && i != skip2) { if (mat[r + chr[i]][c + chc[i]]) return false; } } return true; } bool side_square(int r, int c, int len) { if (!ok(r, c, 1, 2, 4)) return false; if (mat[r - 1][c - 1]) return false; r++; for (int i = 0; i + 2 < len; i++) { if (!ok(r, c, 0, 2, 4)) return false; r++; } if (!ok(r, c, 0, 1, 4)) return false; if (mat[r + 1][c - 1]) return false; c++; for (int i = 0; i + 2 < len; i++) { if (!ok(r, c, 1, 3, 4)) return false; c++; } if (!ok(r, c, 0, 3, 4)) return false; if (mat[r + 1][c + 1]) return false; r--; for (int i = 0; i + 2 < len; i++) { if (!ok(r, c, 0, 2, 4)) return false; r--; } if (!ok(r, c, 2, 3, 4)) return false; if (mat[r - 1][c + 1]) return false; c--; for (int i = 0; i + 2 < len; i++) { if (!ok(r, c, 1, 3, 4)) return false; c--; } return true; } bool diag_square(int r, int c, int len) { if (!ok(r, c, 6, 7, 8)) return false; r++; c--; for (int i = 0; i + 2 < len; i++) { if (!ok(r, c, 5, 6, 8)) return false; r++; c--; } if (!ok(r, c, 5, 7, 8)) return false; r++; c++; for (int i = 0; i + 2 < len; i++) { if (!ok(r, c, 4, 7, 8)) return false; r++; c++; } if (!ok(r, c, 4, 5, 8)) return false; r--; c++; for (int i = 0; i + 2 < len; i++) { if (!ok(r, c, 5, 6, 8)) return false; r--; c++; } if (!ok(r, c, 4, 6, 8)) return false; r--; c--; for (int i = 0; i + 2 < len; i++) { if (!ok(r, c, 4, 7, 8)) return false; r--; c--; } return true; } void solve() { cin >> N >> M; for (int i = 0; i < N + 5; i++) { for (int j = 0; j < M + 5; j++) { mat[i][j] = false; } } char c; for (int i = 1; i <= N; i++) { for (int j = 1; j <= M; j++) { cin >> c; mat[i][j] = c == 1 ; } } long long ans = 0; for (int i = 1; i <= N; i++) { for (int j = 1; j <= M; j++) { if (mat[i][j]) { bool stop = false; for (int len = 2; i + len - 1 <= N && j + len - 1 <= M; len++) { if (side_square(i, j, len)) { ++ans; stop = true; } if (diag_square(i, j, len)) { ++ans; stop = true; } if (stop) break; } } } } cout << ans << n ; } int main() { setIO(); long long T = 1; cin >> T; while (T--) solve(); return 0; } |
//======================================================================
//
// tb_blake2_G.v
// -------------
// Testbench for the Blake2 G function.
//
//
// Author: Joachim Strömbergson
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
//------------------------------------------------------------------
// Simulator directives.
//------------------------------------------------------------------
`timescale 1ns/100ps
module tb_blake2_G();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter DEBUG = 0;
parameter CLK_HALF_PERIOD = 2;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
parameter [63 : 0]
TEST_A_PRIME = 64'hf0c9aa0de38b1b89,
TEST_B_PRIME = 64'hbbdf863401fde49b,
TEST_C_PRIME = 64'he85eb23c42183d3d,
TEST_D_PRIME = 64'h7111fd8b6445099d;
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [63 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg tb_clk;
reg [63 : 0] tb_a;
reg [63 : 0] tb_b;
reg [63 : 0] tb_c;
reg [63 : 0] tb_d;
reg [63 : 0] tb_m0;
reg [63 : 0] tb_m1;
wire [63 : 0] tb_a_prim;
wire [63 : 0] tb_b_prim;
wire [63 : 0] tb_c_prim;
wire [63 : 0] tb_d_prim;
reg display_cycle_ctr;
//----------------------------------------------------------------
// blake2_G device under test.
//----------------------------------------------------------------
blake2_G DUT(
.a(tb_a),
.b(tb_b),
.c(tb_c),
.d(tb_d),
.m0(tb_m0),
.m1(tb_m1),
.a_prim(tb_a_prim),
.b_prim(tb_b_prim),
.c_prim(tb_c_prim),
.d_prim(tb_d_prim)
);
//----------------------------------------------------------------
// clk_gen
//
// Clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD tb_clk = !tb_clk;
end // clk_gen
//--------------------------------------------------------------------
// dut_monitor
//
// Monitor displaying information every cycle.
// Includes the cycle counter.
//--------------------------------------------------------------------
always @ (posedge tb_clk)
begin : dut_monitor
cycle_ctr = cycle_ctr + 1;
if (display_cycle_ctr)
begin
$display("cycle = %016x:", cycle_ctr);
end
end // dut_monitor
//----------------------------------------------------------------
// dump_dut_state
//
// Dump the internal state of the dut to std out.
//----------------------------------------------------------------
task dump_dut_state();
begin
$display("");
$display("DUT internal state");
$display("------------------");
$display("");
end
endtask // dump_dut_state
//----------------------------------------------------------------
// display_test_result()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_result();
begin
if (error_ctr == 0)
begin
$display("*** All %02d test cases completed successfully", tc_ctr);
end
else
begin
$display("*** %02d test cases did not complete successfully.", error_ctr);
end
end
endtask // display_test_result
//----------------------------------------------------------------
// init_dut()
//
// Set the input to the DUT to defined values.
//----------------------------------------------------------------
task init_dut();
begin
cycle_ctr = 0;
error_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_a = 64'h6a09e667f2bdc948;
tb_b = 64'h510e527fade682d1;
tb_c = 64'h6a09e667f3bcc908;
tb_d = 64'h510e527fade68251;
tb_m0 = 64'h0000000000000000;
tb_m1 = 64'h0000000000000000;
end
endtask // init_dut
//----------------------------------------------------------------
// blake2_core
//
// The main test functionality.
//----------------------------------------------------------------
initial
begin : tb_blake2_G_test
$display(" -- Testbench for Blake2 G function test started --");
init_dut();
#(CLK_PERIOD);
if (tb_a_prim == TEST_A_PRIME)
tc_ctr = tc_ctr + 1;
else
error_ctr = error_ctr + 1;
if (tb_b_prim == TEST_B_PRIME)
tc_ctr = tc_ctr + 1;
else
error_ctr = error_ctr + 1;
if (tb_c_prim == TEST_C_PRIME)
tc_ctr = tc_ctr + 1;
else
error_ctr = error_ctr + 1;
if (tb_d_prim == TEST_D_PRIME)
tc_ctr = tc_ctr + 1;
else
error_ctr = error_ctr + 1;
if (error_ctr)
begin
$display("Errors found--dumping state:");
$display("tb_a_prim: %016x", tb_a_prim);
$display("tb_b_prim: %016x", tb_b_prim);
$display("tb_c_prim: %016x", tb_c_prim);
$display("tb_d_prim: %016x", tb_d_prim);
end
display_test_result();
$display("*** Blake2 G functions simulation done.");
$finish_and_return(error_ctr);
end // tb_blake2_G_test
endmodule // tb_blake2_G
//======================================================================
// EOF tb_blake2_G.v
//======================================================================
|
#include <bits/stdc++.h> using namespace std; int n, m, a[5005], b[5005], c[5005], dp[5005][5005][2], size[5005]; vector<int> G[5005]; void DP(int u) { size[u] = 1; dp[u][0][0] = 0; dp[u][1][0] = a[u]; dp[u][1][1] = a[u] - b[u]; for (int i = 0; i < G[u].size(); i++) { int v = G[u][i]; DP(v); for (int j = size[u]; j >= 0; j--) { for (int k = 0; k <= size[v]; k++) { dp[u][j + k][0] = min(dp[u][j + k][0], dp[u][j][0] + dp[v][k][0]); dp[u][j + k][1] = min(dp[u][j + k][1], dp[u][j][1] + dp[v][k][1]); dp[u][j + k][1] = min(dp[u][j + k][1], dp[u][j][1] + dp[v][k][0]); } } size[u] += size[v]; } } int main() { scanf( %d %d , &n, &m); scanf( %d %d , &a[1], &b[1]); for (int i = 2; i <= n; i++) { scanf( %d %d %d , &a[i], &b[i], &c[i]); G[c[i]].push_back(i); } memset(dp, 0x3f3f3f3f, sizeof dp); DP(1); for (int i = n; i >= 1; i--) if (dp[1][i][0] <= m || dp[1][i][1] <= m) { printf( %d , i); return 0; } printf( 0 ); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKINV_SYMBOL_V
`define SKY130_FD_SC_LS__CLKINV_SYMBOL_V
/**
* clkinv: Clock tree inverter.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__clkinv (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKINV_SYMBOL_V
|
/*
* Text mode graphics for VGA
* Copyright (C) 2010 Zeus Gomez Marmolejo <>
*
* VGA FML support
* Copyright (C) 2013 Charley Picker <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
/*
* Pipeline description
* h_count[3:0]
* 000
* 001 col_addr, row_addr
* 010 ver_addr, hor_addr
* 011 csr_adr_o
* 100 csr_adr_i
* 101 sram_addr_
* 110 csr_dat_o
* 111 char_data_out, attr_data_out
* 000 vga_shift
* 001 vga_blue_o <= vga_shift[7]
*/
module vga_text_mode_fml (
input clk,
input rst,
input enable,
// CSR slave interface for reading
output reg [16:1] fml_adr_o,
input [15:0] fml_dat_i,
output fml_stb_o,
input [9:0] h_count,
input [9:0] v_count,
input horiz_sync_i,
input video_on_h_i,
output video_on_h_o,
// CRTC
input [5:0] cur_start,
input [5:0] cur_end,
input [4:0] vcursor,
input [6:0] hcursor,
output reg [3:0] attr,
output horiz_sync_o
);
// Registers and nets
reg [ 6:0] col_addr;
reg [ 4:0] row_addr;
reg [ 6:0] hor_addr;
reg [ 6:0] ver_addr;
wire [10:0] vga_addr;
reg [ 15:0] fml1_dat;
wire [11:0] char_addr;
wire [ 7:0] char_data_out;
reg [ 7:0] attr_data_out;
reg [ 7:0] char_addr_in;
reg [15:0] pipe;
wire load_shift;
reg [7:0] video_on_h;
reg [7:0] horiz_sync;
wire fg_or_bg;
wire brown_bg;
wire brown_fg;
reg [ 7:0] vga_shift;
reg [ 3:0] fg_colour;
reg [ 2:0] bg_colour;
reg [22:0] blink_count;
// Cursor
reg cursor_on_v;
reg cursor_on_h;
reg cursor_on;
wire cursor_on1;
// Module instances
vga_char_rom char_rom (
.clk (clk),
.addr (char_addr),
.q (char_data_out)
);
// Continuous assignments
assign vga_addr = { 4'b0, hor_addr } + { ver_addr, 4'b0 };
assign char_addr = { char_addr_in, v_count[3:0] };
assign load_shift = pipe[7] | pipe[15];
assign video_on_h_o = video_on_h[7];
assign horiz_sync_o = horiz_sync[7];
assign fml_stb_o = pipe[2];
assign fg_or_bg = vga_shift[7] ^ cursor_on;
assign cursor_on1 = cursor_on_h && cursor_on_v;
// Behaviour
// Address generation
always @(posedge clk)
if (rst)
begin
col_addr <= 7'h0;
row_addr <= 5'h0;
ver_addr <= 7'h0;
hor_addr <= 7'h0;
fml_adr_o <= 16'h0;
end
else
if (enable)
begin
// h_count[2:0] == 001
col_addr <= h_count[9:3];
row_addr <= v_count[8:4];
// h_count[2:0] == 010
ver_addr <= { 2'b00, row_addr } + { row_addr, 2'b00 };
// ver_addr = row_addr x 5
hor_addr <= col_addr;
// h_count[2:0] == 011
// vga_addr = row_addr * 80 + hor_addr
fml_adr_o <= { 3'h0, vga_addr, 2'b00 };
end
// cursor
always @(posedge clk)
if (rst)
begin
cursor_on_v <= 1'b0;
cursor_on_h <= 1'b0;
end
else
if (enable)
begin
cursor_on_h <= (h_count[9:3] == hcursor[6:0]);
cursor_on_v <= (v_count[8:4] == vcursor[4:0])
&& ({2'b00, v_count[3:0]} >= cur_start)
&& ({2'b00, v_count[3:0]} <= cur_end);
end
// FML 8x16 pipeline count
always @(posedge clk)
if (rst)
begin
pipe <= 15'b0;
end
else
if (enable)
begin
pipe <= { pipe[14:0], (h_count[3:0]==3'b0) };
end
// Load FML 8x16 burst
always @(posedge clk)
if (enable)
begin
fml1_dat <= pipe[9] ? fml_dat_i[15:0] : fml1_dat;
end
// attr_data_out
always @(posedge clk)
if (enable)
begin
if (pipe[5])
attr_data_out <= fml_dat_i[15:8];
else
if (pipe[13])
attr_data_out <= fml1_dat[15:8];
end
// char_addr_in
always @(posedge clk)
if (enable)
begin
if (pipe[5])
char_addr_in <= fml_dat_i[7:0];
else
if (pipe[13])
char_addr_in <= fml1_dat[7:0];
end
// video_on_h
always @(posedge clk)
if (rst)
begin
video_on_h <= 8'b0;
end
else
if (enable)
begin
video_on_h <= { video_on_h[6:0], video_on_h_i };
end
// horiz_sync
always @(posedge clk)
if (rst)
begin
horiz_sync <= 8'b0;
end
else
if (enable)
begin
horiz_sync <= { horiz_sync[6:0], horiz_sync_i };
end
// blink_count
always @(posedge clk)
if (rst)
begin
blink_count <= 23'h0;
end
else
if (enable)
begin
blink_count <= (blink_count + 23'h1);
end
// Video shift register
always @(posedge clk)
if (rst)
begin
fg_colour <= 4'b0;
bg_colour <= 3'b0;
vga_shift <= 8'h0;
end
else
if (enable)
begin
if (load_shift)
begin
fg_colour <= attr_data_out[3:0];
bg_colour <= attr_data_out[6:4];
cursor_on <= (cursor_on1 | attr_data_out[7]) & blink_count[22];
vga_shift <= char_data_out;
end
else vga_shift <= { vga_shift[6:0], 1'b0 };
end
// pixel attribute
always @(posedge clk)
if (rst)
begin
attr <= 4'h0;
end
else
if (enable)
begin
attr <= fg_or_bg ? fg_colour : { 1'b0, bg_colour };
end
endmodule
|
`include "define.v"
module memory( clk, rst, cs, wen, addr, data_in, fileid, data_out);
parameter ASIZE=16;
parameter DSIZE=16;
parameter STATE=2;//2**STATE >= LATENCY
parameter LATENCY=3;
input clk;
input rst;
input cs;
input wen;
input [ASIZE-1:0] addr; // address input
input [DSIZE-1:0] data_in; // data input
input [3:0] fileid;
output [DSIZE-1:0] data_out; // data output
reg [DSIZE-1:0] memory [0:2**ASIZE-1];
reg [8*`MAX_LINE_LENGTH:0] line; /* Line of text read from file */
integer fin, i, c, r;
reg [ASIZE-1:0] t_addr;
reg [DSIZE-1:0] t_data;
reg [ASIZE-1:0] addr_pipe [0:LATENCY-1];
reg wen_pipe [0:LATENCY-1];
reg [DSIZE-1:0] data_pipe [0:LATENCY-1];
reg [STATE:0] cur_state;
reg [STATE:0] next_state;
assign data_out = (cur_state == 0) ? memory[addr_pipe[LATENCY-1]]: 0;
always @(posedge clk)
begin
if(rst)
begin
case(fileid)
0: fin = $fopen("mem_test0.txt","r");
1: fin = $fopen("mem_test1.txt","r");
2: fin = $fopen("mem_test2.txt","r");
3: fin = $fopen("mem_test3.txt","r");
endcase
$write("Opening Fileid %d\n", fileid);
//First, initialize everything to 0
for (i = 0; i < 2 ** ASIZE; i = i + 1)
begin
memory[i] = 16'h0000;
end
//Now read in the input file
while(!$feof(fin))
begin
c = $fgetc(fin);
// check for comment
if (c == "/" | c == "#" | c == "%")
r = $fgets(line, fin);
else
begin
// Push the character back to the file then read the next time
r = $ungetc(c, fin);
r = $fscanf(fin, "%h %h",t_addr, t_data);
memory[t_addr]=t_data;
$write("%0dns: Write %h to addr %h\n",$time, t_data, t_addr);
end
end
$fclose(fin);
for(i=0; i< LATENCY; i = i+1) begin
addr_pipe[i] <= 0;
wen_pipe[i] <= 1;
data_pipe[i] <= 0;
end
end
else
begin
for(i=LATENCY-1; i > 0; i = i-1) begin
addr_pipe[i] <= addr_pipe[i-1];
wen_pipe[i] <= wen_pipe[i-1];
data_pipe[i] <= data_pipe[i-1];
end
addr_pipe[0] <= addr;
wen_pipe[0] <= wen;
data_pipe[0] <= data_in;
end
end
always@(posedge clk) begin
if(rst)
begin
cur_state <= 0;
end
else
begin
cur_state <= next_state;
if((cur_state == 0) && (wen_pipe[LATENCY-1] == 0)) begin
memory[addr_pipe[LATENCY-1]]=data_pipe[LATENCY-1];
end
end
end
always@(*) begin
if(cur_state == 0) begin
if(cs == 1)
next_state <= LATENCY-1;
else
next_state <= 0;
end
else begin
next_state <= cur_state - 1;
end
end
endmodule |
#include <bits/stdc++.h> using namespace std; inline int read() { int f = 1, x = 0; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) { f = -1; } ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } const int N = 55; struct W { int x, y, tx, ty, id; } up[N], down[N]; bool cmp_down(W a, W b) { return a.tx == b.tx ? a.ty < b.ty : a.tx > b.tx; } bool cmp_up(W a, W b) { return a.x == b.x ? a.y < b.y : a.x < b.x; } vector<pair<int, int> > ans_fr, ans_to; bool has[N][N]; void move_up(int& x, int y) { int dx = x; has[x][y] = 0; has[x - 1][y] = 1; ans_fr.push_back(make_pair(dx, y)); ans_to.push_back(make_pair(dx - 1, y)); --x; } void move_down(int& x, int y) { int dx = x; has[x][y] = 0; has[x + 1][y] = 1; ans_fr.push_back(make_pair(dx, y)); ans_to.push_back(make_pair(dx + 1, y)); ++x; } void move_left(int x, int& y) { int dy = y; has[x][y] = 0; has[x][y - 1] = 1; ans_fr.push_back(make_pair(x, dy)); ans_to.push_back(make_pair(x, dy - 1)); --y; } void move_right(int x, int& y) { int dy = y; has[x][y] = 0; has[x][y + 1] = 1; ans_fr.push_back(make_pair(x, dy)); ans_to.push_back(make_pair(x, dy + 1)); ++y; } void move_row(int& x, int& y, int tx, int ty) { while (y < ty && has[x][y + 1] == 0) { move_right(x, y); } while (y > ty && has[x][y - 1] == 0) { move_left(x, y); } } void move(int& x, int& y, int tx, int ty) { while (x < tx) { move_down(x, y); } while (x > tx) { move_up(x, y); } while (y < ty) { move_right(x, y); } while (y > ty) { move_left(x, y); } } int check(W a) { if (a.x == a.tx) { return a.y == a.ty ? 0 : 1; } else { return a.y == a.ty ? 2 : 3; } } int nx[N], ny[N]; char mp[N][N]; int vis[N]; void write(int n) { for (int i = 1; i <= n; i++) { cout << mp[i] + 1 << endl; } puts( ---------------------- ); } void deal(int n, int m) { if (n == 1) { puts( 0 ); } else { if (m == 1) { move(up[1].x, up[1].y, up[1].tx, up[1].ty); } else { if (cmp_up(up[1], up[2]) == 0) { swap(up[1], up[2]); } if (up[1].x == 2) { move_up(up[1].x, up[1].y); move_up(up[2].x, up[2].y); } else if (up[2].x == 2) { move_up(up[2].x, up[2].y); } switch (check(up[1])) { case 0: break; case 1: move(up[2].x, up[2].y, 2, 1); move_right(up[1].x, up[1].y); break; case 2: move(up[1].x, up[1].y, up[1].tx, up[1].ty); break; case 3: move(up[1].x, up[1].y, up[1].tx, up[1].ty); move_left(up[2].x, up[2].y); break; } move(up[2].x, up[2].y, up[2].tx, up[2].ty); } cout << ans_fr.size() << endl; for (int i = 0; i < ans_fr.size(); i++) { int xx1 = ans_fr[i].first, xx2 = ans_to[i].first; int yy1 = ans_fr[i].second, yy2 = ans_to[i].second; printf( %d %d %d %d n , xx1, yy1, xx2, yy2); } } } int main() { int n = read(), m = read(); for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { mp[i][j] = . ; } } for (int i = 1; i <= m; i++) { up[i].id = i; nx[i] = up[i].x = read(); ny[i] = up[i].y = read(); has[nx[i]][ny[i]] = 1; mp[nx[i]][ny[i]] = i + 0 ; } for (int i = 1; i <= m; i++) { up[i].tx = read(); up[i].ty = read(); } if (n <= 2) { deal(n, m); return 0; } copy(up + 1, up + 1 + m, down + 1); sort(up + 1, up + 1 + m, cmp_up); int cnt = m; while (cnt) { for (int i = 1; i <= m; i++) { if (vis[i] == 0) { int id = up[i].id; move_row(nx[id], ny[id], 1, i); if (ny[id] == i) { vis[i] = 1; cnt--; } } } } for (int i = 1; i <= m; i++) { int id = up[i].id; while (nx[id] > 1) { move_up(nx[id], ny[id]); } } for (int i = 1; i <= m; i++) { move_down(nx[i], ny[i]); move_down(nx[i], ny[i]); } sort(down + 1, down + 1 + m, cmp_down); for (int i = 1; i <= m; i++) { int id = down[i].id; move_up(nx[id], ny[id]); move_row(nx[id], ny[id], 1, i); move_up(nx[id], ny[id]); } for (int i = 1; i <= m; i++) { int id = down[i].id; while (nx[id] < down[i].tx) { move_down(nx[id], ny[id]); } } cnt = m; while (cnt) { for (int i = 1; i <= m; i++) { if (vis[i] == 1) { int id = down[i].id; move_row(nx[id], ny[id], nx[id], down[i].ty); if (ny[id] == down[i].ty) { vis[i] = 2; cnt--; } } } } assert(ans_fr.size() == ans_to.size()); assert(ans_fr.size() <= 10800); cout << ans_fr.size() << endl; for (int i = 0; i < ans_fr.size(); i++) { int xx1 = ans_fr[i].first, xx2 = ans_to[i].first; int yy1 = ans_fr[i].second, yy2 = ans_to[i].second; printf( %d %d %d %d n , xx1, yy1, xx2, yy2); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MxN = (int)15e4 + 9; int n, Q; int parent[MxN + 9]; vector<int> adj[MxN + 9]; int height[MxN + 9]; char label[MxN + 9]; const string YES = Shi ; const string NO = Fou ; int parent2[MxN + 9]; vector<int> adj2[MxN + 9]; array<int, 26> label2[MxN + 9]; array<int, 26> dp[MxN + 9]; int dpSum[MxN + 9]; bool valid[MxN + 9]; void noAll() { for (int i = 0; i < Q; ++i) cout << NO << n ; exit(0); } bool spe(const int u) { return u == 1 || 0 == (adj[u].size() & 1); } inline void update(const int u, const int j) { assert(0 <= j && j < 26); assert(spe(u)); valid[u] = true; if (adj[u].empty()) return; dpSum[u] -= dp[u][j]; dp[u][j] = 0; for (const int v : adj2[u]) { valid[u] &= valid[v]; dp[u][j] = max(dp[u][j], dp[v][j] + label2[v][j]); } dpSum[u] += dp[u][j]; valid[u] &= dpSum[u] <= height[u]; } inline void chainUpdate(int u, const int j) { do { update(u, j); u = parent2[u]; } while (u); } int main() { ios::sync_with_stdio(false); cin.tie(nullptr), cout.tie(nullptr); cin >> n >> Q; for (int i = 2; i <= n; ++i) { cin >> parent[i] >> label[i]; adj[parent[i]].push_back(i); assert(adj[parent[i]].size() <= 2); } for (int i = n; i >= 1; --i) { if (adj[i].empty()) continue; const int u = adj[i][0]; if (adj[i].size() == 2) { const int v = adj[i][1]; if (height[u] != height[v]) noAll(); } height[i] = height[u] + 1; } for (int i = 2; i <= n; ++i) { if (spe(parent[i])) { parent2[i] = parent[i]; } else { parent2[i] = parent2[parent[i]]; label2[i] = label2[parent[i]]; } if (label[i] != ? ) label2[i][label[i] - a ]++; } for (int i = n; i >= 1; --i) { for (int x : adj[i]) { const int y = spe(x) ? x : adj2[x][0]; adj2[i].push_back(y); } } for (int i = n; i >= 1; --i) if (spe(i)) for (int j = 0; j < 26; ++j) update(i, j); for (int rep = 0;; ++rep) { ostream &out = rep == 0 ? cerr : cout; if (!valid[1]) out << NO << n ; else { long long ans = 0; for (int j = 0; j < 26; ++j) ans += (j + 1LL) * (dp[1][j] + (height[1] - dpSum[1])); out << YES << << ans << n ; } if (rep == Q) break; int u; char ch; cin >> u >> ch; const int v = spe(u) ? u : adj2[u][0]; if (label[u] != ? ) { const int j = label[u] - a ; label2[v][j]--; chainUpdate(v, j); } if (ch != ? ) { const int j = ch - a ; label2[v][j]++; chainUpdate(v, j); } label[u] = ch; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_MUX_4TO2_TB_V
`define SKY130_FD_SC_LP__UDP_MUX_4TO2_TB_V
/**
* udp_mux_4to2: Four to one multiplexer with 2 select controls
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__udp_mux_4to2.v"
module top();
// Inputs are registered
reg A0;
reg A1;
reg A2;
reg A3;
reg S0;
reg S1;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
S0 = 1'bX;
S1 = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 A2 = 1'b0;
#80 A3 = 1'b0;
#100 S0 = 1'b0;
#120 S1 = 1'b0;
#140 A0 = 1'b1;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 A3 = 1'b1;
#220 S0 = 1'b1;
#240 S1 = 1'b1;
#260 A0 = 1'b0;
#280 A1 = 1'b0;
#300 A2 = 1'b0;
#320 A3 = 1'b0;
#340 S0 = 1'b0;
#360 S1 = 1'b0;
#380 S1 = 1'b1;
#400 S0 = 1'b1;
#420 A3 = 1'b1;
#440 A2 = 1'b1;
#460 A1 = 1'b1;
#480 A0 = 1'b1;
#500 S1 = 1'bx;
#520 S0 = 1'bx;
#540 A3 = 1'bx;
#560 A2 = 1'bx;
#580 A1 = 1'bx;
#600 A0 = 1'bx;
end
sky130_fd_sc_lp__udp_mux_4to2 dut (.A0(A0), .A1(A1), .A2(A2), .A3(A3), .S0(S0), .S1(S1), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_MUX_4TO2_TB_V
|
#include <bits/stdc++.h> using namespace std; const int apsz = 26; const long long o = 1; const int maxn = 300007; const int ooi = 1e9 + 7; const int up = 62; int n; long long mask[maxn]; long long val[maxn]; inline int hb(long long x) { int k = 0; while ((o << (k + 1)) <= x) k++; return k; } int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n; long long sum = 0; for (int i = (0); i < (n); ++i) cin >> val[i] >> mask[i], sum += val[i]; vector<vector<int> > pos(up); vector<vector<int> > exist(up); for (int i = (0); i < (n); ++i) { pos[hb(mask[i])].push_back(i); for (int j = (0); j < (up); ++j) if ((o << j) & mask[i]) exist[j].push_back(i); } long long ans = 0; for (int i = (0); i < (up); ++i) { if (pos[i].empty()) continue; long long tmp = 0; for (auto x : pos[i]) tmp += val[x]; if (tmp == 0) continue; if (tmp > 0 == sum > 0) { ans |= (o << (long long)i); for (auto x : exist[i]) val[x] = -val[x]; } } cout << ans << endl; return 0; } |
`include "../config.inc"
`include "../video2ram.v"
`include "../edge_detect.v"
`include "../Flag_CrossDomain.v"
`include "../ram2video.v"
module video2ram_tb;
reg clkIn = 0;
reg clkOut = 0;
reg [11:0] counterX;
reg [11:0] counterY;
wire [23:0] wrdata;
wire [23:0] rddata;
wire [14:0] wraddr;
wire wren;
wire wrclock;
wire starttriggerIn;
wire [14:0] rdaddr;
wire starttriggerOut;
wire HSYNC;
wire VSYNC;
wire DE;
wire CLOCK;
wire [23:0] video_out;
video2ram video2ram(
.clock(clkIn),
.R(8'd0),
.G(8'd0),
.B(8'd0),
.counterX(counterX),
.counterY(counterY),
.line_doubler(1'b0),
.wrdata(wrdata),
.wraddr(wraddr),
.wren(wren),
.wrclock(wrclock),
.starttrigger(starttriggerIn)
);
Flag_CrossDomain trigger(
.clkA(clkIn),
.FlagIn_clkA(starttriggerIn),
.clkB(clkOut),
.FlagOut_clkB(starttriggerOut)
);
ram2video ram2video(
.starttrigger(starttriggerOut),
.clock(clkOut),
.reset(1'b1),
.line_doubler(1'b0),
.add_line(1'b0),
.rddata(rddata),
.hsync(HSYNC),
.vsync(VSYNC),
.DrawArea(DE),
.videoClock(CLOCK),
.rdaddr(rdaddr),
.video_out(video_out)
);
`ifdef _1080p_
initial $display("1080p");
always #250 clkIn = ~clkIn;
always #91 clkOut = ~clkOut;
`endif
`ifdef _960p_
initial $display("960p");
always #2000 clkIn = ~clkIn;
always #1001 clkOut = ~clkOut;
`endif
`ifdef _VGA_
initial $display("VGA");
always #400 clkIn = ~clkIn;
always #429 clkOut = ~clkOut;
`endif
always @(posedge clkIn) begin
if (counterX < 858 - 1) begin
counterX <= counterX + 1;
end else begin
counterX <= 0;
if (counterY < 525 - 1) begin
//$display("y:%0d ay:%0d ay2:%0d - %0d %0d", counterY, video2ram.ram_addrY_reg, ram2video.ram_addrY_reg, (video2ram.ram_addrY_reg == ram2video.ram_addrY_reg), rdaddr);
counterY <= counterY + 1;
end else begin
counterY <= 0;
end
end
end
`define __IsVerticalCaptureTime(y) ( \
video2ram.line_doubler \
? (y < 240 || (y > 262 && y < video2ram.V_CAPTURE_END)) \
: (y >= video2ram.V_CAPTURE_START && y < video2ram.V_CAPTURE_END) \
)
`define __IsCaptureTime(x,y) ( \
`__IsVerticalCaptureTime(y) && x >= video2ram.H_CAPTURE_START && x < video2ram.H_CAPTURE_END \
)
initial
begin
counterX <= 0;
counterY <= 0;
$monitor("%0d - %0d: %0dx%0d %0d(%0d) %0dx%0d %0d", $time, starttriggerOut, counterX, counterY, wraddr, wren, ram2video.counterX_reg, ram2video.counterY_reg, rdaddr);
wait (starttriggerOut) begin
$display("TRIGGER");
end
wait ((counterY >= 480 && ram2video.counterY_reg >= `VERTICAL_LINES_VISIBLE - `VERTICAL_OFFSET) || (wren && `IsDrawAreaVGA(ram2video.counterX_reg, ram2video.counterY_reg) && wraddr == rdaddr)) begin
$display("stop: y:%0d ay:%0d ay2:%0d", counterY, wraddr, rdaddr);
$finish;
end
end
endmodule
|
//----------------------------------------------------------------------------
//-- Ejemplo 1 de puerta tri-estado
//-- Conectar y desconectar un biestable a 1 al led, a través de
//-- una puerta tri-estado, con una cadencia de 1 segundo
//----------------------------------------------------------------------------
//-- (C) BQ. November 2015. Written by Juan Gonzalez (Obijuan)
//-- GPL license
//----------------------------------------------------------------------------
`default_nettype none
`include "divider.vh"
module tristate1 (
input wire clk, //-- Entrada de reloj
output wire led0); //-- Led a controlar
//-- Parametro: periodo de parpadeo
parameter DELAY = `T_1s;
//-- Cable con la señal de tiempo
wire clk_delay;
//-- Biestable que está siempre a 1
reg reg1;
always @(posedge clk)
reg1 <= 1'b1;
//-- Conectar el biestable al led a traves de la puerta tri-estado
assign led0 = (clk_delay) ? reg1 : 1'bz;
//-- Divisor para temporizacion
divider #(DELAY)
CH0 (
.clk_in(clk),
.clk_out(clk_delay)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int max_n = 303333, inf = 1000111222; int n, x, y; pair<int, int> a[max_n]; void wa() { printf( No n ); exit(0); } int main() { scanf( %d%d%d , &n, &x, &y); for (int i = 0; i < n; ++i) { scanf( %d , &a[i].first); a[i].second = i + 1; } sort(a, a + n); int last = -1; for (int i = n - 1; i >= 0; --i) { if (1LL * a[i].first * (n - i) >= y) { last = i; break; } } if (last == -1) { wa(); } for (int i = 0; i < n; ++i) { int need = (x + a[i].first - 1) / a[i].first; if (i + need <= last) { printf( Yes n ); printf( %d %d n , need, n - last); for (int j = i; j < i + need; ++j) { printf( %d , a[j].second); } printf( n ); for (int j = last; j < n; ++j) { printf( %d , a[j].second); } printf( n ); return 0; } } swap(x, y); last = -1; for (int i = n - 1; i >= 0; --i) { if (1LL * a[i].first * (n - i) >= y) { last = i; break; } } if (last == -1) { wa(); } for (int i = 0; i < n; ++i) { int need = (x + a[i].first - 1) / a[i].first; if (i + need <= last) { printf( Yes n ); printf( %d %d n , n - last, need); for (int j = last; j < n; ++j) { printf( %d , a[j].second); } printf( n ); for (int j = i; j < i + need; ++j) { printf( %d , a[j].second); } printf( n ); return 0; } } wa(); return 0; } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.1
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module doHistStretch_sitofp_32s_32_6
#(parameter
ID = 3,
NUM_STAGE = 6,
din0_WIDTH = 32,
dout_WIDTH = 32
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [31:0] a_tdata;
wire r_tvalid;
wire [31:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
//------------------------Instantiation------------------
doHistStretch_ap_sitofp_4_no_dsp_32 doHistStretch_ap_sitofp_4_no_dsp_32_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e13, Mo = 998244353; const int N = 1000000; const double eps = 1e-6; namespace slow_IO { long long read() { long long x = 0; int zf = 1; char ch = getchar(); while (ch != - && (ch < 0 || ch > 9 )) ch = getchar(); if (ch == - ) zf = -1, ch = getchar(); while (ch >= 0 && ch <= 9 ) x = x * 10 + ch - 0 , ch = getchar(); return x * zf; } void write(long long y) { if (y < 0) putchar( - ), y = -y; if (y > 9) write(y / 10); putchar(y % 10 + 0 ); } } // namespace slow_IO using namespace slow_IO; vector<int> E1[N + 5], E2[N + 5]; int Flag1[N + 5], Flag2[N + 5]; int Ans[N + 5]; int ans = 0; int main() { int n = read(), m = read(); for (int i = (1); i <= (m); i++) { int x = read(), y = read(); E1[x].push_back(y); E2[y].push_back(x); } for (int i = (1); i <= (n); i++) if (!Flag1[i]) { Flag1[i] = Flag2[i] = 1; for (int j = (0); j < (E1[i].size()); j++) Flag1[E1[i][j]] = 1; } for (int i = (n); i >= (1); i--) if (Flag2[i]) { for (int j = (0); j < (E2[i].size()); j++) if (Flag2[E2[i][j]]) Flag2[i] = 0; } for (int i = (1); i <= (n); i++) if (Flag2[i]) Ans[++ans] = i; printf( %d n , ans); for (int i = (1); i <= (ans); i++) printf( %d%c , Ans[i], i == ans ? n : ); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:18:18 10/17/2016
// Design Name:
// Module Name: num_6
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module num_6(
input [2:0] in_row,
output reg [4:0] out_code
);
parameter [4:0] d_0 = 5'b01110; // XXX
parameter [4:0] d_1 = 5'b00001; // X
parameter [4:0] d_2 = 5'b01111; // XXXX
parameter [4:0] d_3 = 5'b10001; // X X
always @ *
begin
case (in_row)
3'b000:
out_code = d_0;
3'b001:
out_code = d_1;
3'b010:
out_code = d_2;
3'b011:
out_code = d_3;
3'b100:
out_code = d_3;
3'b101:
out_code = d_0;
default:
out_code = 5'b0;
endcase
end
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module softusb_phy(
input usb_clk,
input usb_rst,
output usba_spd,
output usba_oe_n,
input usba_rcv,
inout usba_vp,
inout usba_vm,
output usbb_spd,
output usbb_oe_n,
input usbb_rcv,
inout usbb_vp,
inout usbb_vm,
output usba_discon,
output usbb_discon,
output [1:0] line_state_a,
output [1:0] line_state_b,
input port_sel_rx,
input [1:0] port_sel_tx,
input [7:0] tx_data,
input tx_valid,
output tx_ready, /* data acknowledgment */
output tx_busy, /* busy generating EOP, sending data, etc. */
input [1:0] generate_reset,
output [7:0] rx_data,
output rx_valid,
output rx_active,
input tx_low_speed,
input [1:0] low_speed,
input generate_eop
);
/* RX synchronizer */
wire vp_s_a;
wire vm_s_a;
wire rcv_s_a;
softusb_filter filter_a(
.usb_clk(usb_clk),
.rcv(usba_rcv),
.vp(usba_vp),
.vm(usba_vm),
.rcv_s(rcv_s_a),
.vp_s(vp_s_a),
.vm_s(vm_s_a)
);
assign line_state_a = {vm_s_a, vp_s_a};
wire vp_s_b;
wire vm_s_b;
wire rcv_s_b;
softusb_filter filter_b(
.usb_clk(usb_clk),
.rcv(usbb_rcv),
.vp(usbb_vp),
.vm(usbb_vm),
.rcv_s(rcv_s_b),
.vp_s(vp_s_b),
.vm_s(vm_s_b)
);
assign line_state_b = {vm_s_b, vp_s_b};
/* TX section */
wire txp;
wire txm;
wire txoe;
softusb_tx tx(
.usb_clk(usb_clk),
.usb_rst(usb_rst),
.tx_data(tx_data),
.tx_valid(tx_valid),
.tx_ready(tx_ready),
.txp(txp),
.txm(txm),
.txoe(txoe),
.low_speed(tx_low_speed),
.generate_eop(generate_eop)
);
assign tx_busy = txoe;
/* RX section */
reg txoe0;
reg txoe1;
always @(posedge usb_clk) begin
txoe0 <= txoe;
txoe1 <= txoe0;
end
softusb_rx rx(
.usb_clk(usb_clk),
.rxreset(txoe1),
.rx(port_sel_rx ? rcv_s_b : rcv_s_a),
.rxp(port_sel_rx ? vp_s_b : vp_s_a),
.rxm(port_sel_rx ? vm_s_b : vm_s_a),
.rx_data(rx_data),
.rx_valid(rx_valid),
.rx_active(rx_active),
.low_speed(port_sel_rx ? low_speed[1] : low_speed[0])
);
/* Tri-state enables and drivers */
wire txoe_a = (txoe & port_sel_tx[0])|generate_reset[0];
wire txoe_b = (txoe & port_sel_tx[1])|generate_reset[1];
assign usba_oe_n = ~txoe_a;
assign usba_vp = txoe_a ? (generate_reset[0] ? 1'b0 : txp) : 1'bz;
assign usba_vm = txoe_a ? (generate_reset[0] ? 1'b0 : txm) : 1'bz;
assign usbb_oe_n = ~txoe_b;
assign usbb_vp = txoe_b ? (generate_reset[1] ? 1'b0 : txp) : 1'bz;
assign usbb_vm = txoe_b ? (generate_reset[1] ? 1'b0 : txm) : 1'bz;
/* Assert USB disconnect if we see SE0 for at least 2.5us */
reg [6:0] usba_discon_cnt;
assign usba_discon = (usba_discon_cnt == 7'd127);
always @(posedge usb_clk) begin
if(usb_rst)
usba_discon_cnt <= 7'd0;
else begin
if(line_state_a != 7'd0)
usba_discon_cnt <= 7'd0;
else if(~usba_discon)
usba_discon_cnt <= usba_discon_cnt + 7'd1;
end
end
reg [6:0] usbb_discon_cnt;
assign usbb_discon = (usbb_discon_cnt == 7'd127);
always @(posedge usb_clk) begin
if(usb_rst)
usbb_discon_cnt <= 7'd0;
else begin
if(line_state_b != 2'h0)
usbb_discon_cnt <= 7'd0;
else if(~usbb_discon)
usbb_discon_cnt <= usbb_discon_cnt + 7'd1;
end
end
assign usba_spd = ~low_speed[0];
assign usbb_spd = ~low_speed[1];
endmodule
|
#include <bits/stdc++.h> using namespace std; pair<long long, long long> a[200005]; signed main() { long long n, j; cin >> n >> j; j %= 2 * n; long long x0, y0; cin >> x0 >> y0; for (long long i = 0; i < n; i++) { cin >> a[i].first >> a[i].second; } for (long long i = 1; i <= j; i++) { x0 = 2 * a[(i - 1) % n].first - x0; y0 = 2 * a[(i - 1) % n].second - y0; } cout << x0 << << y0; } |
/*
Anthony De Caria - April 4, 2014
This module creates a Shift Register with a seperate enable signal.
This specific module creates an output that is 16-bits wide.
This module uses asyncronous D Flip Flops.
It also can allow data to be inputed into the flip flops before shifting.
*/
module ShiftRegisterWEnableSixteenAsyncMuxedInput(clk, resetn, enable, select, d, q);
//Define the inputs and outputs
input clk;
input resetn;
input enable;
input select;
input [15:0] d;
output [15:0] q;
wire [15:1]muxOut;
mux2to1_1bit One_mux(.data1x(d[1]), .data0x(q[0]), .sel(select), .result(muxOut[1]) );
mux2to1_1bit Two_mux(.data1x(d[2]), .data0x(q[1]), .sel(select), .result(muxOut[2]) );
mux2to1_1bit Three_mux(.data1x(d[3]), .data0x(q[2]), .sel(select), .result(muxOut[3]) );
mux2to1_1bit Four_mux(.data1x(d[4]), .data0x(q[3]), .sel(select), .result(muxOut[4]) );
mux2to1_1bit Five_mux(.data1x(d[5]), .data0x(q[4]), .sel(select), .result(muxOut[5]) );
mux2to1_1bit Six_mux(.data1x(d[6]), .data0x(q[5]), .sel(select), .result(muxOut[6]) );
mux2to1_1bit Seven_mux(.data1x(d[7]), .data0x(q[6]), .sel(select), .result(muxOut[7]) );
mux2to1_1bit Eight_mux(.data1x(d[8]), .data0x(q[7]), .sel(select), .result(muxOut[8]) );
mux2to1_1bit Nine_mux(.data1x(d[9]), .data0x(q[8]), .sel(select), .result(muxOut[9]) );
mux2to1_1bit Ten_mux(.data1x(d[10]), .data0x(q[9]), .sel(select), .result(muxOut[10]) );
mux2to1_1bit Eleven_mux(.data1x(d[11]), .data0x(q[10]), .sel(select), .result(muxOut[11]) );
mux2to1_1bit Twelve_mux(.data1x(d[12]), .data0x(q[11]), .sel(select), .result(muxOut[12]) );
mux2to1_1bit Thirteen_mux(.data1x(d[13]), .data0x(q[12]), .sel(select), .result(muxOut[13]) );
mux2to1_1bit Fourteen_mux(.data1x(d[14]), .data0x(q[13]), .sel(select), .result(muxOut[14]) );
mux2to1_1bit Fifteen_mux(.data1x(d[15]), .data0x(q[14]), .sel(select), .result(muxOut[15]) );
D_FF_with_Enable Zero(.clk(clk), .resetn(resetn), .enable(enable), .d(d[0]), .q(q[0]) );
D_FF_with_Enable One(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[1]), .q(q[1]) );
D_FF_with_Enable Two(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[2]), .q(q[2]) );
D_FF_with_Enable Three(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[3]), .q(q[3]) );
D_FF_with_Enable Four(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[4]), .q(q[4]) );
D_FF_with_Enable Five(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[5]), .q(q[5]) );
D_FF_with_Enable Six(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[6]), .q(q[6]) );
D_FF_with_Enable Seven(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[7]), .q(q[7]) );
D_FF_with_Enable Eight(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[8]), .q(q[8]) );
D_FF_with_Enable Nine(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[9]), .q(q[9]) );
D_FF_with_Enable Ten(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[10]), .q(q[10]) );
D_FF_with_Enable Eleven(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[11]), .q(q[11]) );
D_FF_with_Enable Twelve(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[12]), .q(q[12]) );
D_FF_with_Enable Thirteen(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[13]), .q(q[13]) );
D_FF_with_Enable Fourteen(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[14]), .q(q[14]) );
D_FF_with_Enable Fifteen(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[15]), .q(q[15]) );
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:user:KeyboardCtrl:1.0
// IP Revision: 2
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module KeyboardCtrl_0 (
key_in,
is_extend,
is_break,
valid,
err,
PS2_DATA,
PS2_CLK,
rst,
clk
);
output wire [7 : 0] key_in;
output wire is_extend;
output wire is_break;
output wire valid;
output wire err;
inout wire PS2_DATA;
inout wire PS2_CLK;
input wire rst;
input wire clk;
KeyboardCtrl #(
.SYSCLK_FREQUENCY_HZ(100000000)
) inst (
.key_in(key_in),
.is_extend(is_extend),
.is_break(is_break),
.valid(valid),
.err(err),
.PS2_DATA(PS2_DATA),
.PS2_CLK(PS2_CLK),
.rst(rst),
.clk(clk)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; char s[200010], t[200010]; string ans; void solve() { int n = strlen(s), x = 0; for (int i = 0; i < n; i++) { if (i) ans += + ; if (i < n - 1 && rand() % 2 == 0) { ans += (s[i]), ans += s[++i]; x += 10 * (s[i - 1] - 0 ) + s[i] - 0 ; } else { ans += (s[i]); x += s[i] - 0 ; } } ans += n ; sprintf(s, %d , x); } int main() { srand(time(0)); scanf( %s%s , s, t); while (1) { strcpy(s, t); ans = ; solve(); solve(); solve(); if (strlen(s) == 1) return cout << ans, 0; } } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_src0_cols_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_src0_cols_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_src0_cols_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_src0_cols_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XOR2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__XOR2_FUNCTIONAL_PP_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__xor2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X , B, A );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XOR2_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int N = 1e6; vector<vector<int>> g(N); bool isDeleted[N]; vector<int> res; void del(int s, int p) { res.push_back(s); isDeleted[s] = true; for (auto I : g[s]) { if (!isDeleted[I] && I != p) { del(I, s); } } } bool dfs(int s, int p) { int siz = g[s].size(); for (auto I : g[s]) { if (I != p) { bool isDeleted = dfs(I, s); if (isDeleted) { --siz; } } } if (siz % 2 == 0) { del(s, p); return true; } else return false; } int main() { int n, x; scanf( %d , &n); for (int i = 0; i < n; ++i) { scanf( %d , &x); if (x) { g[i].push_back(x - 1); g[x - 1].push_back(i); } } bool ans = dfs(0, -1); if (ans) { printf( YES n ); for (auto I : res) { printf( %d n , I + 1); } } else printf( NO n ); return 0; } |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.