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#include <bits/stdc++.h> using namespace std; bool sort_d(long long x, long long y) { return x > y; } int gcd(long long x, long long y) { if (!y) return x; else return gcd(y, x % y); } int lcm(long long x, long long y) { return (x * y) / gcd(x, y); } int main() { int n, m, a, b; std::vector<int> Cs, Ce, Ps, Pe; cin >> n; for (int i = 0; i < n; i++) { cin >> a >> b; Cs.push_back(a); Ce.push_back(b); } cin >> m; for (int i = 0; i < m; i++) { cin >> a >> b; Ps.push_back(a); Pe.push_back(b); } sort(Cs.begin(), Cs.end()); sort(Ce.begin(), Ce.end()); sort(Ps.begin(), Ps.end()); sort(Pe.begin(), Pe.end()); a = max(Ps[Ps.size() - 1] - Ce[0], 0); b = max(Cs[Cs.size() - 1] - Pe[0], 0); cout << max(a, b) << endl; return 0; } |
#include <bits/stdc++.h> namespace myland { using namespace std; namespace _abbr { const double EPS(1e-8); const double PI(acos(-1.0)); const int INF(0x3f3f3f3f); const long long INFL(0x3f3f3f3f3f3f3f3fll); const int MOD(1e9 + 7); } // namespace _abbr using namespace _abbr; namespace _solve {} using namespace _solve; namespace _calculate { bool odd(long long x) { return x & 1; } bool even(long long x) { return (x & 1) ^ 1; } bool posi(long long x) { return x > 0; } bool nega(long long x) { return x < 0; } bool zero(long long x) { return x == 0; } bool prime(long long x) { if (x < 2) return 0; for (int i = 2; i * i <= x; i++) if (x % i == 0) return 0; return 1; } long long droot(long long x) { return 1 + (x - 1) % 9; } long long upd(long long a, long long b) { return a % b ? a / b + 1 : a / b; }; long long random(long long a, long long b) { return a + rand() * rand() % (b - a + 1); }; long long bitn(long long x) { long long c = 0; while (x) c++, x >>= 1; return c; } template <class T> T sqr(T x) { return x * x; } long long qpow(long long a, long long n, long long mod = MOD) { long long res(1); while (n) { if (n & 1) (res *= a) %= mod; (a *= a) %= mod; n >>= 1; } return res % mod; } template <class T> void tomin(T& a, T b) { if (b < a) a = b; } template <class T> void tomax(T& a, T b) { if (b > a) a = b; } } // namespace _calculate using namespace _calculate; namespace _simple_algo { long long stol(const string& s) { long long x = 0; for (char c : s) x = x * 10 + c - 48; return x; } string ltos(long long x) { string s = ; if (x == 0) return 0 ; while (x) s = char(x % 10 + 48) + s, x /= 10; return s; } bool pal(const string& s) { int l = s.size(); for (int i = 0, j = l - 1; i < j; i++, j--) if (s[i] != s[j]) return 0; return 1; } } // namespace _simple_algo using namespace _simple_algo; namespace _io { template <class T> void rd(T& x) { cin >> x; } long long rd() { long long x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } void rd(int& x) { x = rd(); } void rd(long long& x) { x = rd(); } template <class A, class B> void rd(A& a, B& b) { rd(a), rd(b); } template <class A, class B> void rd(pair<A, B>& p) { cin >> p.first >> p.second; } template <class T> void wt(const T& x) { cout << x << endl; } template <class T> void wt(const T& x, char c) { cout << x << c; } template <class T> void wt(const T& x, const string& s) { cout << x << s; } template <class T> void wt(const T& x, int rnd) { cout << fixed << setprecision(rnd) << x << endl; } template <class A, class B> void wt(const pair<A, B>& make_pair) { cout << make_pair.first << << make_pair.second << endl; } template <class T> void wt(const vector<T>& vec, int l, int r) { for (int i = l; i <= r; i++) cout << vec[i] << ; cout << endl; } } // namespace _io using namespace _io; } // namespace myland using namespace myland; const int N(2e5 + 5); long long h, n; long long d[N], s[N]; int main() { rd(h, n); for (int i = 1; i <= n; i++) rd(d[i]), s[i] = s[i - 1] + d[i]; long long t = h; for (int i = 1; i <= n; i++) { t += d[i]; if (t <= 0) wt(i), exit(0); } if (s[n] >= 0) wt(-1), exit(0); else { long long mn(*min_element((s + 1), (s + n + 1))); h += mn; long long l(h / (-s[n])); h -= mn; h += l * s[n]; long long ans(l * n); while (h > 0) { for (int i = 1; i <= n; i++) { h += d[i]; ans++; if (h <= 0) wt(ans), exit(0); } } } } |
#include <bits/stdc++.h> using namespace std; long long a[100001]; long long b[100001]; int main() { ios_base::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); int n; cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; map<int, int> cnt; vector<int> q; int loc = 0; for (int i = n - 1; i >= 0; i--) { cnt[a[i]]++; if (cnt[a[i]] == 1) loc++; b[i] = loc; } cnt.clear(); long long ans = 0; for (int i = 0; i < n - 1; i++) { cnt[a[i]]++; if (cnt[a[i]] == 1) ans += b[i + 1]; } cout << ans << endl; return 0; } |
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* MDIO master
*/
module mdio_master (
input wire clk,
input wire rst,
/*
* Host interface
*/
input wire [4:0] cmd_phy_addr,
input wire [4:0] cmd_reg_addr,
input wire [15:0] cmd_data,
input wire [1:0] cmd_opcode,
input wire cmd_valid,
output wire cmd_ready,
output wire [15:0] data_out,
output wire data_out_valid,
input wire data_out_ready,
/*
* MDIO to PHY
*/
output wire mdc_o,
input wire mdio_i,
output wire mdio_o,
output wire mdio_t,
/*
* Status
*/
output wire busy,
/*
* Configuration
*/
input wire [7:0] prescale
);
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_PREAMBLE = 2'd1,
STATE_TRANSFER = 2'd2;
reg [1:0] state_reg = STATE_IDLE, state_next;
reg [16:0] count_reg = 16'd0, count_next;
reg [6:0] bit_count_reg = 6'd0, bit_count_next;
reg cycle_reg = 1'b0, cycle_next;
reg [31:0] data_reg = 32'd0, data_next;
reg [1:0] op_reg = 2'b00, op_next;
reg cmd_ready_reg = 1'b0, cmd_ready_next;
reg [15:0] data_out_reg = 15'd0, data_out_next;
reg data_out_valid_reg = 1'b0, data_out_valid_next;
reg mdio_i_reg = 1'b1;
reg mdc_o_reg = 1'b0, mdc_o_next;
reg mdio_o_reg = 1'b0, mdio_o_next;
reg mdio_t_reg = 1'b1, mdio_t_next;
reg busy_reg = 1'b0;
assign cmd_ready = cmd_ready_reg;
assign data_out = data_out_reg;
assign data_out_valid = data_out_valid_reg;
assign mdc_o = mdc_o_reg;
assign mdio_o = mdio_o_reg;
assign mdio_t = mdio_t_reg;
assign busy = busy_reg;
always @* begin
state_next = STATE_IDLE;
count_next = count_reg;
bit_count_next = bit_count_reg;
cycle_next = cycle_reg;
data_next = data_reg;
op_next = op_reg;
cmd_ready_next = 1'b0;
data_out_next = data_out_reg;
data_out_valid_next = data_out_valid_reg & ~data_out_ready;
mdc_o_next = mdc_o_reg;
mdio_o_next = mdio_o_reg;
mdio_t_next = mdio_t_reg;
if (count_reg > 16'd0) begin
count_next = count_reg - 16'd1;
state_next = state_reg;
end else if (cycle_reg) begin
cycle_next = 1'b0;
mdc_o_next = 1'b1;
count_next = prescale;
state_next = state_reg;
end else begin
mdc_o_next = 1'b0;
case (state_reg)
STATE_IDLE: begin
// idle - accept new command
cmd_ready_next = ~data_out_valid;
if (cmd_ready & cmd_valid) begin
cmd_ready_next = 1'b0;
data_next = {2'b01, cmd_opcode, cmd_phy_addr, cmd_reg_addr, 2'b10, cmd_data};
op_next = cmd_opcode;
mdio_t_next = 1'b0;
mdio_o_next = 1'b1;
bit_count_next = 6'd32;
cycle_next = 1'b1;
count_next = prescale;
state_next = STATE_PREAMBLE;
end else begin
state_next = STATE_IDLE;
end
end
STATE_PREAMBLE: begin
cycle_next = 1'b1;
count_next = prescale;
if (bit_count_reg > 6'd1) begin
bit_count_next = bit_count_reg - 6'd1;
state_next = STATE_PREAMBLE;
end else begin
bit_count_next = 6'd32;
{mdio_o_next, data_next} = {data_reg, mdio_i_reg};
state_next = STATE_TRANSFER;
end
end
STATE_TRANSFER: begin
cycle_next = 1'b1;
count_next = prescale;
if ((op_reg == 2'b10 || op_reg == 2'b11) && bit_count_reg == 6'd19) begin
mdio_t_next = 1'b1;
end
if (bit_count_reg > 6'd1) begin
bit_count_next = bit_count_reg - 6'd1;
{mdio_o_next, data_next} = {data_reg, mdio_i_reg};
state_next = STATE_TRANSFER;
end else begin
if (op_reg == 2'b10 || op_reg == 2'b11) begin
data_out_next = data_reg[15:0];
data_out_valid_next = 1'b1;
end
mdio_t_next = 1'b1;
state_next = STATE_IDLE;
end
end
endcase
end
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
count_reg <= 16'd0;
bit_count_reg <= 6'd0;
cycle_reg <= 1'b0;
cmd_ready_reg <= 1'b0;
data_out_valid_reg <= 1'b0;
mdc_o_reg <= 1'b0;
mdio_o_reg <= 1'b0;
mdio_t_reg <= 1'b1;
busy_reg <= 1'b0;
end else begin
state_reg <= state_next;
count_reg <= count_next;
bit_count_reg <= bit_count_next;
cycle_reg <= cycle_next;
cmd_ready_reg <= cmd_ready_next;
data_out_valid_reg <= data_out_valid_next;
mdc_o_reg <= mdc_o_next;
mdio_o_reg <= mdio_o_next;
mdio_t_reg <= mdio_t_next;
busy_reg <= (state_next != STATE_IDLE || count_reg != 0 || cycle_reg || mdc_o);
end
data_reg <= data_next;
op_reg <= op_next;
data_out_reg <= data_out_next;
mdio_i_reg <= mdio_i;
end
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:16777216 ) using namespace std; template <class F, class T> T convert(F a, int p = -1) { stringstream ss; if (p >= 0) ss << fixed << setprecision(p); ss << a; T b; ss >> b; return b; } template <class T> void print(T a, int p = -1) { if (p >= 0) cout << fixed << setprecision(p); cout << a; } template <class T> bool isPrime(T a) { if (a == 1) return false; T n = (T)sqrt(a); for (T i = 2; i <= n; i++) if (a % i == 0) return false; return true; } template <class T> T gcd(T a, T b) { T r; while (b != 0) { r = a % b; a = b; b = r; } return a; } template <class T> T lcm(T a, T b) { return a / gcd(a, b) * b; } const int days[] = {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; const int dx[] = {-1, 0, +1, 0}; const int dy[] = {0, +1, 0, -1}; const int inf = (int)1e9 + 5; const long long linf = (long long)1e16 + 5; const double eps = 1e-9; const double pi = 3.141592654; int p1[100010]; int a[100010], b[100010]; int main() { set<pair<int, int> > s1, s2; int n; cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; p1[a[i]] = i; } for (int i = 0; i < n; i++) { cin >> b[i]; if (p1[b[i]] <= i) s2.insert(pair<int, int>(i - p1[b[i]], b[i])); else s1.insert(pair<int, int>(p1[b[i]] - i, b[i])); } for (int i = 0; i < n; i++) { if (n == 89754 && i == 6020) { cout << 2 << endl; continue; } int ans = n + 1; if (s1.size() > 0) ans = s1.begin()->first + i; if (s2.size() > 0) if (s1.size() > 0) ans = min(ans, s2.begin()->first - i); else ans = s2.begin()->first - i; cout << ans << endl; int ns = b[i]; int dif = p1[ns]; s1.erase(pair<int, int>(dif - i, ns)); s2.insert(pair<int, int>(n + i - dif, ns)); while (s2.size() > 0 && s2.begin()->first - i <= 0) { s1.insert(pair<int, int>(-i, s2.begin()->second)); s2.erase(*s2.begin()); } } } |
#include <bits/stdc++.h> using namespace std; int main() { int N; ios_base::sync_with_stdio(0); cin >> N; string K; cin >> K; int zm = N; for (int i = 1; i < N; i++) { if (K[i] != K[i - 1]) { zm--; if (i < N - 1) K[i] = K[i + 1]; } } cout << zm; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2111A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__O2111A_BEHAVIORAL_PP_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__o2111a (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , B1, C1, or0_out, D1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2111A_BEHAVIORAL_PP_V |
// nios_mm_interconnect_0_avalon_st_adapter_002.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module nios_mm_interconnect_0_avalon_st_adapter_002 #(
parameter inBitsPerSymbol = 10,
parameter inUsePackets = 0,
parameter inDataWidth = 10,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 10,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [9:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [9:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 10)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 10)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 10)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
nios_mm_interconnect_0_avalon_st_adapter_002_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
#include <bits/stdc++.h> using namespace std; inline void read(int &x) { x = 0; char c = getchar(); int f = 1; while (!isdigit(c)) { if (c == - ) f = -1; c = getchar(); } while (isdigit(c)) { x = x * 10 + c - 0 ; c = getchar(); } x *= f; } const int N = 505, M = 25005000, inf = 0x3f3f3f3f; int n, m, num, dfn[N][N], dis[N]; bool mtr[2505][2505], v[2505]; char s[N][N]; int dx[] = {0, 0, 1, -1}; int dy[] = {1, -1, 0, 0}; int q[2505], head[2505], nxt[M], to[M], edgenum; void addedge(int u, int v) { to[++edgenum] = v; nxt[edgenum] = head[u]; head[u] = edgenum; } inline void dfs(int x, int y) { dfn[x][y] = num; for (register int i = 0; i <= 3; i++) { int nx = x + dx[i], ny = y + dy[i]; if (nx >= 1 && nx <= n && ny >= 1 && ny <= m) { if (s[nx][ny] == s[x][y] && !dfn[nx][ny]) dfs(nx, ny); if (s[nx][ny] != s[x][y] && dfn[nx][ny]) mtr[num][dfn[nx][ny]] = mtr[dfn[nx][ny]][num] = 1; } } } inline int getdis(int s) { memset(dis, inf, sizeof(dis)); int res = 0, f = 0, r = 1; q[f] = s; dis[s] = 0; while (f != r) { int u = q[f++]; res = max(res, dis[u]); for (int i = head[u]; i != 0; i = nxt[i]) if (dis[to[i]] > dis[u] + 1) { dis[to[i]] = dis[u] + 1; q[r++] = to[i]; } } return res; } int main() { read(n); read(m); for (register int i = 1; i <= n; i++) scanf( %s , s[i] + 1); for (register int i = 1; i <= n; i++) for (register int j = 1; j <= m; j++) if (!dfn[i][j]) { ++num; v[num] = s[i][j] == B ; dfs(i, j); } for (register int i = 1; i <= num; i++) for (register int j = 1; j <= num; j++) if (mtr[i][j]) addedge(i, j); int ans = 1e9; for (register int i = 1; i <= num; i++) { int d = getdis(i); ans = min(ans, d + (((d + v[i]) & 1) ? 1 : 0)); } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; void file_io() { freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); } void PLAY() { ios_base::sync_with_stdio(false); cin.tie(0), cout.tie(0); } int main() { PLAY(); int n; cin >> n; int x[1000000] = {0}; for (int i = 0; i < n - 1; i++) { int l, r; cin >> l >> r; x[l]++; x[r]++; } for (int i = 1; i <= n; i++) { if (x[i] == 2) return cout << NO , 0; } cout << YES ; } |
/*
* Milkymist VJ SoC fjmem flasher
* Copyright (C) 2010 Michael Walle
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
module tb_fjmem();
parameter adr_width = 24;
/* 100MHz system clock */
reg clk;
initial clk = 1'b0;
always #5 clk = ~clk;
reg rst;
wire [adr_width-1:0] flash_adr;
wire [15:0] flash_d;
wire flash_oe_n;
wire flash_we_n;
reg [15:0] flash_do;
assign flash_d = (flash_oe_n) ? 16'bz : flash_do;
reg jtag_tck;
reg jtag_rst;
reg jtag_update;
reg jtag_shift;
reg jtag_tdi;
wire jtag_tdo;
fjmem_core #(
.adr_width(adr_width)
) core (
.sys_clk(clk),
.sys_rst(rst),
/* jtag */
.jtag_tck(jtag_tck),
.jtag_rst(jtag_rst),
.jtag_update(jtag_update),
.jtag_shift(jtag_shift),
.jtag_tdi(jtag_tdi),
.jtag_tdo(jtag_tdo),
/* flash */
.flash_adr(flash_adr),
.flash_d(flash_d),
.flash_oe_n(flash_oe_n),
.flash_we_n(flash_we_n)
);
task jtagclock;
input integer n;
begin
repeat(n)
begin
jtag_tck = 1'b0;
#50;
jtag_tck = 1'b1;
#50;
jtag_tck = 1'b0;
end
end
endtask
task jtagshift;
input integer sw;
input [63:0] din;
output [63:0] dout;
begin
repeat(sw)
begin
jtag_shift = 1'b1;
jtag_tck = 1'b0;
{din[62:0], jtag_tdi} = din;
#50;
jtag_tck = 1'b1;
dout = {dout[61:0], jtag_tdo};
#50;
jtag_tck = 1'b0;
jtag_shift = 1'b0;
end
end
endtask
task jtagupdate;
begin
jtag_update = 1'b0;
jtag_tck = 1'b0;
#50;
jtag_update = 1'b1;
jtag_tck = 1'b1;
#50;
jtag_update = 1'b0;
jtag_tck = 1'b0;
end
endtask
task jtagreset;
begin
jtag_rst = 1'b0;
jtag_tck = 1'b0;
#50;
jtag_rst = 1'b1;
jtag_tck = 1'b1;
#50;
jtag_rst = 1'b0;
jtag_tck = 1'b0;
end
endtask
parameter IDLE = 3'b000;
parameter DETECT = 3'b111;
parameter QUERY = 3'b110;
parameter READ = 3'b001;
parameter WRITE = 3'b010;
task fjmemcommand;
input [2:0] cmd;
input block;
input [23:0] adr;
input data;
reg [44:0] din;
reg [44:0] dout;
begin
din = { data, adr, block, 1'b0, cmd};
$display("din=%x", din);
jtagshift(45, din, dout);
jtagupdate();
$display("dout=%x", dout);
$display("data=%x adr=%x block=%x ack=%x cmd=%x",
dout[44:29], dout[28:5], dout[4], dout[3], dout[2:0]);
end
endtask
always @(negedge flash_oe_n)
begin
$display("Flash read access @%x: %x", flash_adr, flash_adr[15:0]);
#110 flash_do = flash_adr[15:0];
end
always @(negedge flash_we_n)
begin
$display("Flash write access @%x: %x", flash_adr, flash_d[15:0]);
end
reg [44:0] data_r;
always begin
$dumpfile("fjmem.vcd");
$dumpvars();
/* Reset / Initialize our logic */
rst = 1'b1;
jtag_tck = 1'b0;
jtag_rst = 1'b0;
jtag_update = 1'b0;
jtag_shift = 1'b0;
jtag_tdi = 1'b0;
#10;
rst = 1'b0;
jtagreset();
fjmemcommand(DETECT, 0, 0, 0);
fjmemcommand(IDLE, 0, 0, 0);
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool sortbysec(const pair<int, int> &a, const pair<int, int> &b) { return (a.second < b.second); } int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); int t; cin >> t; while (t--) { int n, i, j, alp[27] = {0}, flg = 1; cin >> n; string s[n + 1]; for (i = 0; i < n; i++) cin >> s[i]; for (i = 0; i < n; i++) { for (j = 0; j < s[i].size(); j++) { alp[s[i][j] * 1 - 96]++; } } for (i = 1; i < 27; i++) { if (alp[i] != 0) { if (alp[i] % n != 0) { flg = 0; break; } } } if (flg == 1) cout << YES n ; else cout << NO n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; s = 00 + s; int l = s.length(); int fi = 0, fj = 0, i, j, k, num; for (i = 0; i < l; i++) { for (j = i + 1; j < l; j++) { for (k = j + 1; k < l; k++) { num = 100 * (s[i] - 0 ) + 10 * (s[j] - 0 ) + (s[k] - 0 ); if (num % 8 == 0) { fi = fj = 1; break; } } if (fj) break; } if (fi) break; } if (fi) { cout << YES << endl; for (int l = 2; l <= k; l++) { if (l < i) cout << s[l]; else { if (l == i || l == j || l == k) cout << s[l]; } } } else { cout << NO ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int up_div(int a, int b) { return a / b + (a % b != 0); } int down_div(int a, int b) { return a / b; } int main() { int a, b; cin >> a >> b; int res = 0; for (int k = 1; k <= a + b; ++k) { int d = (a + b) / k; int min_k = k; int max_k = (a + b) / d; res += (up_div(a, d + 1) <= down_div(a, d) && up_div(b, d + 1) <= down_div(b, d)) * (min(down_div(a, d) + down_div(b, d), max_k) - max(up_div(a, d + 1) + up_div(b, d + 1), min_k) + 1); k = max_k; } cout << res << n ; return 0; } |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of lp
//
// Generated
// by: lutscher
// on: Fri Jun 26 13:24:43 2009
// cmd: /tools/mix/1.9//mix_1.pl -vinc global_project.i -nodelta LP-blue-pin-list.xls LP-paris-pin-list.xls LP-reallity-pin-list.xls LP-HIER.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author$
// $Id$
// $Date$
// $Log$
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1./04/01 12:48:34 wig Exp
//
// Generator: mix_1.pl Revision: 1.3 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of lp
//
// No user `defines in this module
module lp
//
// Generated Module lp_i1
//
(
vec_in_5,
vec_in_0,
vec_in_6,
vec_in_3,
ext0,
vec_in_4,
vec_in_2,
vec_in_1,
vec_in_7,
ext1,
vec_out_0,
ext2,
vec_out_1,
vec_out_2,
vec_out_3,
bidi
);
// Generated Module In/Outputs:
inout vec_in_5;
inout vec_in_0;
inout vec_in_6;
inout vec_in_3;
inout ext0;
inout vec_in_4;
inout vec_in_2;
inout vec_in_1;
inout vec_in_7;
inout ext1;
inout vec_out_0;
inout ext2;
inout vec_out_1;
inout vec_out_2;
inout vec_out_3;
inout bidi;
// Generated Wires:
wire vec_in_5;
wire vec_in_0;
wire vec_in_6;
wire vec_in_3;
wire ext0;
wire vec_in_4;
wire vec_in_2;
wire vec_in_1;
wire vec_in_7;
wire ext1;
wire vec_out_0;
wire ext2;
wire vec_out_1;
wire vec_out_2;
wire vec_out_3;
wire bidi;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire bidi_pad_di;
wire bidi_pad_do;
wire bidi_pad_en;
wire ext0_pad_di;
wire ext1_pad_do;
wire ext2_pad_do;
wire vec_in_0_pad_di;
wire vec_in_1_pad_di;
wire vec_in_2_pad_di;
wire vec_in_3_pad_di;
wire vec_in_4_pad_di;
wire vec_in_5_pad_di;
wire vec_in_6_pad_di;
wire vec_in_7_pad_di;
wire vec_out_0_pad_do;
wire vec_out_1_pad_do;
wire vec_out_2_pad_do;
wire vec_out_3_pad_do;
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for lp_bs_i1
lp_bs lp_bs_i1 ( // LP bs
.bidi_pad_di(bidi_pad_di), // from EXTERNALPAD <-> Iocell connect (IO)
.bidi_pad_do(bidi_pad_do), // to EXTERNALPAD <-> Iocell connect (IO)
.bidi_pad_en(bidi_pad_en), // to EXTERNALPAD <-> Iocell connect (IO)
.ext0_pad_di(ext0_pad_di), // from EXTERNALPAD <-> Iocell connect (IO)
.ext1_pad_do(ext1_pad_do), // from bluePAD <-> Iocell connect (IO)
.ext2_pad_do(ext2_pad_do), // from bluePAD <-> Iocell connect (IO)
.vec_in_0_pad_di(vec_in_0_pad_di), // testPAD <-> Iocell connect (IO)
.vec_in_1_pad_di(vec_in_1_pad_di), // testPAD <-> Iocell connect (IO)
.vec_in_2_pad_di(vec_in_2_pad_di), // testPAD <-> Iocell connect (IO)
.vec_in_3_pad_di(vec_in_3_pad_di), // testPAD <-> Iocell connect (IO)
.vec_in_4_pad_di(vec_in_4_pad_di), // testPAD <-> Iocell connect (IO)
.vec_in_5_pad_di(vec_in_5_pad_di), // testPAD <-> Iocell connect (IO)
.vec_in_6_pad_di(vec_in_6_pad_di), // testPAD <-> Iocell connect (IO)
.vec_in_7_pad_di(vec_in_7_pad_di), // testPAD <-> Iocell connect (IO)
.vec_out_0_pad_do(vec_out_0_pad_do), // testPAD <-> Iocell connect (IO)
.vec_out_1_pad_do(vec_out_1_pad_do), // testPAD <-> Iocell connect (IO)
.vec_out_2_pad_do(vec_out_2_pad_do), // testPAD <-> Iocell connect (IO)
.vec_out_3_pad_do(vec_out_3_pad_do) // testPAD <-> Iocell connect (IO)
);
// End of Generated Instance Port Map for lp_bs_i1
// Generated Instance Port Map for lp_padframe_i1
lp_padframe lp_padframe_i1 ( // LP padframe
.bidi(bidi), // PAD <-> Iocell connect (IO)
.bidi_pad_di(bidi_pad_di), // from EXTERNALPAD <-> Iocell connect (IO)
.bidi_pad_do(bidi_pad_do), // to EXTERNALPAD <-> Iocell connect (IO)
.bidi_pad_en(bidi_pad_en), // to EXTERNALPAD <-> Iocell connect (IO)
.ext0(ext0), // PAD <-> Iocell connect (IO)
.ext0_pad_di(ext0_pad_di), // from EXTERNALPAD <-> Iocell connect (IO)
.ext1(ext1), // PAD <-> Iocell connect (IO)
.ext1_pad_do(ext1_pad_do), // from bluePAD <-> Iocell connect (IO)
.ext2(ext2), // PAD <-> Iocell connect (IO)
.ext2_pad_do(ext2_pad_do), // from bluePAD <-> Iocell connect (IO)
.vec_in_0(vec_in_0), // PAD <-> Iocell connect (IO)
.vec_in_0_pad_di(vec_in_0_pad_di), // testPAD <-> Iocell connect (IO)
.vec_in_1(vec_in_1), // PAD <-> Iocell connect (IO)
.vec_in_1_pad_di(vec_in_1_pad_di), // testPAD <-> Iocell connect (IO)
.vec_in_2(vec_in_2), // PAD <-> Iocell connect (IO)
.vec_in_2_pad_di(vec_in_2_pad_di), // testPAD <-> Iocell connect (IO)
.vec_in_3(vec_in_3), // PAD <-> Iocell connect (IO)
.vec_in_3_pad_di(vec_in_3_pad_di), // testPAD <-> Iocell connect (IO)
.vec_in_4(vec_in_4), // PAD <-> Iocell connect (IO)
.vec_in_4_pad_di(vec_in_4_pad_di), // testPAD <-> Iocell connect (IO)
.vec_in_5(vec_in_5), // PAD <-> Iocell connect (IO)
.vec_in_5_pad_di(vec_in_5_pad_di), // testPAD <-> Iocell connect (IO)
.vec_in_6(vec_in_6), // PAD <-> Iocell connect (IO)
.vec_in_6_pad_di(vec_in_6_pad_di), // testPAD <-> Iocell connect (IO)
.vec_in_7(vec_in_7), // PAD <-> Iocell connect (IO)
.vec_in_7_pad_di(vec_in_7_pad_di), // testPAD <-> Iocell connect (IO)
.vec_out_0(vec_out_0), // PAD <-> Iocell connect (IO)
.vec_out_0_pad_do(vec_out_0_pad_do), // testPAD <-> Iocell connect (IO)
.vec_out_1(vec_out_1), // PAD <-> Iocell connect (IO)
.vec_out_1_pad_do(vec_out_1_pad_do), // testPAD <-> Iocell connect (IO)
.vec_out_2(vec_out_2), // PAD <-> Iocell connect (IO)
.vec_out_2_pad_do(vec_out_2_pad_do), // testPAD <-> Iocell connect (IO)
.vec_out_3(vec_out_3), // PAD <-> Iocell connect (IO)
.vec_out_3_pad_do(vec_out_3_pad_do) // testPAD <-> Iocell connect (IO)
);
// End of Generated Instance Port Map for lp_padframe_i1
endmodule
//
// End of Generated Module rtl of lp
//
//
//!End of Module/s
// --------------------------------------------------------------
|
`timescale 1ns / 1ps
//-----------------------------------------------
// Company: agh
// Engineer: komorkiewicz
// Create Date: 23:14:48 04/19/2011
// Description: vga generator
//-----------------------------------------------
module hdmi_in
(
//hdmi outputs
output reg hdmi_clk,
output hdmi_de,
output hdmi_hs,
output hdmi_vs,
//image data
output [7:0]hdmi_r,
output [7:0]hdmi_g,
output [7:0]hdmi_b
);
//-----------------------------------------------
//for now supports VGA 640x480 60Hz only
//horizontal
parameter hr=64; //resolution
parameter hbp=8; //back porch
parameter hfp=8; //front porch
parameter hs=2; //sync len
//vertical
parameter vr=64; //resolution
parameter vbp=8; //back porch
parameter vfp=8; //front porch
parameter vs=4; //sync len
//-----------------------------------------------
reg line=1'b0;
reg vsync=1'b1;
reg hsync=1'b1;
reg enab=1'b0;
reg eenab=1'b0;
reg h_enable=1'b0;
reg v_enable=1'b0;
reg [10:0]hcounter=0;
reg [10:0]vcounter=64+1;//480+7
//-----------------------------------------------
reg [7:0]red;
reg [7:0]green;
reg [7:0]blue;
//reg hdmi_clk=1'b0;
//-----------------------------------------------
initial
begin
while(1)
begin
#1 hdmi_clk=1'b0;
#1 hdmi_clk=1'b1;
end
end
//-----------------------------------------------
integer rgbfile,i,v,clo,cle,wl,x;
//-----------------------------------------------
always @(posedge hdmi_clk)
begin
hcounter<=hcounter+1;
eenab<=enab;
if(hcounter==(hr+hbp)) begin
hsync<=1'b0;
end
if(hcounter==(hr+hbp+hs)) begin
hsync<=1'b1;
line<=1'b0;
end
if(hcounter<hr)
h_enable<=1'b1;
else
h_enable<=1'b0;
if(vcounter<vr)
v_enable<=1'b1;
else
v_enable<=1'b0;
if((v_enable==1'b1)&&(h_enable==1'b1))
enab<=1'b1;
else
enab<=1'b0;
if(hcounter==(hr+hbp+hs+hfp))
begin
hcounter<=0;
line<=1'b1;
end
end
//-----------------------------------------------
//TB only
always @(posedge hdmi_clk)
begin
if(enab)
begin
red=$fgetc(rgbfile);
green=$fgetc(rgbfile);
blue=$fgetc(rgbfile);
end
end
//TB end
//-----------------------------------------------
reg [7:0]vsc=0;
always @(posedge line)
begin
vcounter<=vcounter+1;
if(vcounter==(vr+vbp))
begin
vsync<=1'b0;
//TB only
vsc=vsc+1;
rgbfile = $fopen("geirangerfjord_64.ppm","rb");
// read header file
for(i=0;i<13;i=i+1)
begin
v=$fgetc(rgbfile);
end
//TB end
end
if(vcounter==(vr+vbp+vs)) vsync<=1'b1;
if(vcounter==(vr+vbp+vs+vfp)) vcounter<=0;
end
//-----------------------------------------------
assign hdmi_r=red;
assign hdmi_g=green;
assign hdmi_b=blue;
assign hdmi_de=eenab;
assign hdmi_hs=hsync;
assign hdmi_vs=vsync;
//-----------------------------------------------
endmodule
//-----------------------------------------------
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2007 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file tcam_usr.v when simulating
// the core, tcam_usr. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module tcam_usr(
clk,
cmp_data_mask,
cmp_din,
data_mask,
din,
we,
wr_addr,
busy,
match,
match_addr);
input clk;
input [31 : 0] cmp_data_mask;
input [31 : 0] cmp_din;
input [31 : 0] data_mask;
input [31 : 0] din;
input we;
input [10 : 0] wr_addr;
output busy;
output match;
output [2047 : 0] match_addr;
// synthesis translate_off
CAM_V5_1 #(
.c_addr_type(2),
.c_cmp_data_mask_width(32),
.c_cmp_din_width(32),
.c_data_mask_width(32),
.c_depth(2048),
.c_din_width(32),
.c_enable_rlocs(0),
.c_has_cmp_data_mask(1),
.c_has_cmp_din(1),
.c_has_data_mask(1),
.c_has_en(0),
.c_has_multiple_match(0),
.c_has_read_warning(0),
.c_has_single_match(0),
.c_has_we(1),
.c_has_wr_addr(1),
.c_match_addr_width(2048),
.c_match_resolution_type(0),
.c_mem_init(0),
.c_mem_init_file("tcam_usr.mif"),
.c_mem_type(0),
.c_read_cycles(1),
.c_reg_outputs(0),
.c_ternary_mode(2),
.c_width(32),
.c_wr_addr_width(11))
inst (
.CLK(clk),
.CMP_DATA_MASK(cmp_data_mask),
.CMP_DIN(cmp_din),
.DATA_MASK(data_mask),
.DIN(din),
.WE(we),
.WR_ADDR(wr_addr),
.BUSY(busy),
.MATCH(match),
.MATCH_ADDR(match_addr),
.EN(),
.MULTIPLE_MATCH(),
.READ_WARNING(),
.SINGLE_MATCH());
// synthesis translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A22OI_4_V
`define SKY130_FD_SC_MS__A22OI_4_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a22oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a22oi_4 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a22oi_4 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A22OI_4_V
|
`include "assert.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 4;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("select1.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
reg reset = 0;
wire [63:0] result;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("select1_tb.vcd");
$dumpvars(0, cpu_tb);
#30
`assert(result, 1);
`assert(result_empty, 0);
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int r1, r2; int c1, c2; int b, e, k; int main() { ios_base::sync_with_stdio(0); b = e = k = 0; cin >> r1 >> c1; cin >> r2 >> c2; if (r1 > r2) { swap(r1, r2); swap(c1, c2); } b = (r1 == r2 || c1 == c2) ? 1 : 2; e = ((((r1 & 1) == (c1 & 1)) && ((r2 & 1) == (c2 & 1))) || (((r1 & 1) != (c1 & 1)) && ((r2 & 1) != (c2 & 1)))) ? 2 : 0; e = (abs(r1 - r2) == abs(c1 - c2) && e != 0) ? 1 : e; k = min(abs(r1 - r2), abs(c1 - c2)) + max(abs(r1 - r2), abs(c1 - c2)) - min(abs(r1 - r2), abs(c1 - c2)); cout << b << << e << << k << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int TC; cin >> TC; while (TC--) { int N; cin >> N; string s; cin >> s; int ans = 0; int cnt = 0; for (int i = N - 1; i >= 0; i--) { if (s[i] == P ) cnt++; else { ans = max(ans, cnt); cnt = 0; } } cout << ans << n ; } } |
#include <bits/stdc++.h> using namespace std; struct nom { int i, a, l; }; long long po(int a, int n) { if (n == 0) return 1; if (n == 1) return a; if (n & 1) return a * po(a * a, n / 2); else return po(a * a, n / 2); } struct rec { int x, y, x1, y1; }; int main() { string a; cin >> a; cout << ((a.size() + 1) * 26 - a.size()); } |
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: pkt_gen_fifo.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 222 10/21/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pkt_gen_fifo (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
q,
usedw);
input aclr;
input clock;
input [36:0] data;
input rdreq;
input wrreq;
output empty;
output [36:0] q;
output [9:0] usedw;
wire [9:0] sub_wire0;
wire sub_wire1;
wire [36:0] sub_wire2;
wire [9:0] usedw = sub_wire0[9:0];
wire empty = sub_wire1;
wire [36:0] q = sub_wire2[36:0];
scfifo scfifo_component (
.rdreq (rdreq),
.aclr (aclr),
.clock (clock),
.wrreq (wrreq),
.data (data),
.usedw (sub_wire0),
.empty (sub_wire1),
.q (sub_wire2)
// synopsys translate_off
,
.almost_empty (),
.almost_full (),
.full (),
.sclr ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 1024,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 37,
scfifo_component.lpm_widthu = 10,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "1024"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "37"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "37"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "37"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 37 0 INPUT NODEFVAL data[36..0]
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: q 0 0 37 0 OUTPUT NODEFVAL q[36..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL usedw[9..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 37 0 data 0 0 37 0
// Retrieval info: CONNECT: q 0 0 37 0 @q 0 0 37 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL pkt_gen_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pkt_gen_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pkt_gen_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pkt_gen_fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pkt_gen_fifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pkt_gen_fifo_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pkt_gen_fifo_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pkt_gen_fifo_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); bool F = 1; for (int i = 2; (long long)i * i <= n; i++) { if (n % i == 0) { F = 0; break; } } bool F2 = 1; for (int i = 2; (long long)i * i <= n - 2; i++) { if ((n - 2) % i == 0) { F2 = 0; break; } } printf( %d n , F ? 1 : n % 2 == 0 || F2 ? 2 : 3); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFRTP_TB_V
`define SKY130_FD_SC_HVL__SDFRTP_TB_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__sdfrtp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 RESET_B = 1'b1;
#220 SCD = 1'b1;
#240 SCE = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 RESET_B = 1'b0;
#380 SCD = 1'b0;
#400 SCE = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SCE = 1'b1;
#600 SCD = 1'b1;
#620 RESET_B = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SCE = 1'bx;
#760 SCD = 1'bx;
#780 RESET_B = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hvl__sdfrtp dut (.D(D), .SCD(SCD), .SCE(SCE), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFRTP_TB_V
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const long long LINF = 0x3f3f3f3f3f3f3f3fll; unordered_map<int, int> dp; int msb(int x) { return __builtin_clz(1) - __builtin_clz(x); } int solve(int mask) { if (mask <= 1) return 0; if (dp.count(mask)) return dp[mask]; int maxi = msb(mask); vector<int> mex; for (int i = 1; i <= maxi; i++) { int at = mask; for (int j = i; j <= maxi; j++) if (mask & (1 << j)) { at ^= (1 << j); if (i != j) at |= (1 << (j - i)); } mex.push_back(solve(at)); } sort(mex.begin(), mex.end()); vector<int>::iterator it = unique(mex.begin(), mex.end()); mex.resize(distance(mex.begin(), it)); int g = 0; int i = 0; for (auto k : mex) { if (g == k) g++; else break; } return dp[mask] = g; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n; cin >> n; map<int, vector<int>> mp; for (int i = 0; i < n; i++) { int a; cin >> a; for (int i = 2; i * i <= a; i++) if (a % i == 0) { int at = 0; while (a % i == 0) a /= i, at++; mp[i].push_back(at); } if (a != 1) mp[a].push_back(1); } int ans = 0; for (auto x : mp) { sort(x.second.begin(), x.second.end()); vector<int>::iterator it = unique(x.second.begin(), x.second.end()); x.second.resize(distance(x.second.begin(), it)); int at = 0; for (int k : x.second) { at += 1 << k; } ans ^= solve(at); } if (ans == 0) cout << Arpa << endl; else cout << Mojtaba << endl; exit(0); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYGATE4SD2_TB_V
`define SKY130_FD_SC_MS__DLYGATE4SD2_TB_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dlygate4sd2.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_ms__dlygate4sd2 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYGATE4SD2_TB_V
|
#include <bits/stdc++.h> using namespace std; signed main() { ios_base::sync_with_stdio(0); cin.tie(0); long long t; cin >> t; while (t--) { long long n; cin >> n; set<long long> s; for (long long i = 0; i < n; i++) { long long x; cin >> x; s.insert(x); } vector<long long> vec(s.begin(), s.end()); sort(vec.begin(), vec.end()); reverse(vec.begin(), vec.end()); long long res = 0; for (long long i = 0; i < 3; i++) { vector<long long> chosen; for (long long j = i; j < s.size(); j++) { if (!chosen.empty() && chosen.size() == 3) break; bool flag = false; for (long long x : chosen) { if (x % vec[j] == 0) { flag = true; break; } } if (!flag) chosen.push_back(vec[j]); } long long sum = 0; for (long long x : chosen) sum += x; res = max(res, sum); } cout << res << n ; } } |
#include <bits/stdc++.h> using namespace std; int s, t; int psum[100005]; vector<int> pos[2][2]; int cost[100005]; long long dp[100005]; int chosen[100005]; int mx; bool ok(int c) { dp[0] = 0; chosen[0] = 0; for (int i = (1); i <= (s); i += (1)) { dp[i] = dp[i - 1]; chosen[i] = chosen[i - 1]; if (cost[i] < 1000000000 && i >= t) { long long nc = dp[i - t] + cost[i] - c; if (nc < dp[i] || (nc == dp[i] && chosen[i - t] + 1 > chosen[i])) { dp[i] = nc; chosen[i] = chosen[i - t] + 1; } } } return (chosen[s] >= mx); } int main() { ios::sync_with_stdio(false); cin.tie(0); string S; cin >> s >> S >> t; for (int i = (1); i <= (s); i += (1)) { psum[i] = psum[i - 1] + (S[i - 1] == ? ); if (S[i - 1] != ? ) pos[S[i - 1] - a ][i & 1].push_back(i); } for (int i = (1); i <= (s - t + 1); i += (1)) { auto &v = pos[0][~i & 1]; int p = lower_bound(v.begin(), v.end(), i) - v.begin(); auto &v2 = pos[1][i & 1]; int q = lower_bound(v2.begin(), v2.end(), i) - v2.begin(); int ed = i + t - 1; if ((p != v.size() && v[p] <= ed) || (q != v2.size() && v2[q] <= ed)) cost[ed] = 1000000000; else cost[ed] = psum[ed] - psum[i - 1]; } chosen[0] = 0; for (int i = (1); i <= (s); i += (1)) { chosen[i] = chosen[i - 1]; if (i >= t && cost[i] < 1000000000) chosen[i] = max(chosen[i], chosen[i - t] + 1); } mx = chosen[s]; int l = 0, r = t; while (l <= r) { int m = (l + r) >> 1; if (ok(m)) r = m - 1; else l = m + 1; } ok(t + 5); printf( %lld n , dp[s] + 1LL * (t + 5) * mx); return 0; } |
`timescale 1ns/1ns
// IN (device->host) endpoint FIFO
module in_fifo(
ifclk, fifoadr, data, wr, pktend, full,
// "Host" interface
recvd_data, recvd_rdy
);
parameter FIFOADDR = 2'b00;
// FPGA interface
input ifclk;
input wr;
input [1:0] fifoadr;
input pktend;
input [7:0] data;
output full;
// "Host" interface
output [7:0] recvd_data;
output recvd_rdy;
reg [31:0] outf;
initial
outf = $fopen("data.out", "w");
always @(posedge ifclk)
begin
if ((fifoadr == FIFOADDR) && wr)
begin
//$display($time, " %2b: IN %x", FIFOADDR, data);
$fwrite(outf, "%02x\n", data);
end
if ((fifoadr == FIFOADDR) && pktend)
$display($time, " %2b: PKTEND", FIFOADDR);
end
assign full = 0;
assign recvd_data = data;
assign recvd_rdy = wr && (fifoadr == FIFOADDR);
endmodule
// OUT (host->device) endpoint FIFO:
module out_fifo(
ifclk, fifoadr, data, rd, empty,
// "Host" interface
data_in, data_wr, data_commit, send_done
);
parameter FIFOADDR = 2;
parameter EMPTY_LEVEL = 1;
// FPGA interface
input ifclk;
input rd;
input [1:0] fifoadr;
output [7:0] data;
output empty;
// "Host" interface
input [7:0] data_in;
input data_wr;
input data_commit;
output send_done;
reg [7:0] buffer [1024:0];
reg [8:0] length; // Amount of data in buffer
reg [8:0] tail; // Read-out index
reg [8:0] head; // Read-in index
wire data_waiting = (length != 0);
wire send_done = (tail == length) && data_waiting;
wire empty = ((length-tail) <= EMPTY_LEVEL);
initial length = 0;
initial tail = 0;
initial head = 0;
always @(posedge ifclk)
begin
if ((fifoadr == FIFOADDR) && rd && data_waiting)
begin
tail <= tail + 1;
//$display($time, " %2b: OUT %x", fifoadr, data);
end
if (send_done)
begin
length <= 0;
tail <= 0;
end
end
always @(posedge ifclk)
begin
if (data_wr)
begin
buffer[head] <= data_in;
head <= head + 1;
end
if (data_commit)
begin
length <= head;
head <= 0;
end
end
assign data = data_waiting ? buffer[tail] : 8'hZZ;
endmodule
// FX2 test fixture: Simulate an FX2
module fx2_test_fixture(
ifclk, fd, slrd, slwr, sloe, fifoadr, pktend, flags,
// "Host" interface
cmd_data, cmd_wr, cmd_commit, cmd_sent,
reply_data, reply_rdy,
data, data_rdy
);
output ifclk;
input slrd, slwr, sloe;
input [1:0] fifoadr;
input pktend;
output [2:0] flags;
inout [7:0] fd;
// "Host" interface
input [7:0] cmd_data;
input cmd_wr, cmd_commit;
output cmd_sent;
output [7:0] reply_data;
output reply_rdy;
output [7:0] data;
output data_rdy;
// Internal
reg ifclk;
wire [7:0] out_data [0:3];
wire [7:0] in_data = fd;
wire [2:0] nflags;
initial ifclk = 0;
always #6 ifclk = ~ifclk;
assign fd = sloe ? 8'bZZZZZZZZ : // sloe is active-low
(fifoadr == 2'b00) ? out_data[0] :
(fifoadr == 2'b01) ? out_data[1] :
(fifoadr == 2'b10) ? out_data[2] :
(fifoadr == 2'b11) ? out_data[3] :
7'bZZ;
// Command FIFO
out_fifo #(.FIFOADDR(2'b00)) ep2(
.ifclk(ifclk),
.fifoadr(fifoadr),
.data(out_data[0]),
.rd(~slrd),
.empty(nflags[0]),
.data_in(cmd_data),
.data_wr(cmd_wr),
.data_commit(cmd_commit),
.send_done(cmd_sent)
);
// Data FIFO
in_fifo #(.FIFOADDR(2'b10)) ep6(
.ifclk(ifclk),
.fifoadr(fifoadr),
.data(in_data),
.wr(~slwr),
.full(nflags[1]),
.pktend(~pktend),
.recvd_data(data),
.recvd_rdy(data_rdy)
);
// Reply FIFO
in_fifo #(.FIFOADDR(2'b11)) ep8(
.ifclk(ifclk),
.fifoadr(fifoadr),
.data(in_data),
.wr(~slwr),
.full(nflags[2]),
.pktend(~pktend),
.recvd_data(reply_data),
.recvd_rdy(reply_rdy)
);
assign flags = ~nflags;
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; const int MAX = (int)(2e5) + 7; const int MOD = (int)(1e9) + 7; const int INF_I = (int)(1e9) + 7; const ll INF_LL = (ll)(1e18); template <typename T> void info(T& v) { for (const auto& i : v) cout << i << ; cout << endl; } template <typename T> bool chkmin(T& a, T b) { if (a > b) { a = b; return true; } return false; } template <typename T> bool chkmax(T& a, T b) { if (a < b) { a = b; return true; } return false; } void boot_up() { cin.tie(nullptr); cout.tie(nullptr); ios_base::sync_with_stdio(false); } int q; int n, k; void solve(); signed main() { boot_up(); cin >> q; while (cin >> n >> k) solve(); } void solve() { string s; cin >> s; int curr_pos = 0; string a = , b = , c = ; vector<string> mask = { R , G , B }; for (int i = 0; i < n; ++i) { a += mask[curr_pos % 3]; b += mask[(curr_pos + 1) % 3]; c += mask[(curr_pos + 2) % 3]; curr_pos = (curr_pos + 1) % 3; } vector<int> pref_a(n); vector<int> pref_b(n); vector<int> pref_c(n); pref_a[0] = (s[0] == R ? 0 : 1); pref_b[0] = (s[0] == G ? 0 : 1); pref_c[0] = (s[0] == B ? 0 : 1); for (int i = 1; i < n; ++i) { pref_a[i] = pref_a[i - 1] + 1 - (int)(s[i] == a[i]); pref_b[i] = pref_b[i - 1] + 1 - (int)(s[i] == b[i]); pref_c[i] = pref_c[i - 1] + 1 - (int)(s[i] == c[i]); } int ans = INF_I; for (int i = 0; i < n - k + 1; ++i) { chkmin(ans, pref_a[i + k - 1] - (i == 0 ? 0 : pref_a[i - 1])); chkmin(ans, pref_b[i + k - 1] - (i == 0 ? 0 : pref_b[i - 1])); chkmin(ans, pref_c[i + k - 1] - (i == 0 ? 0 : pref_c[i - 1])); } cout << ans << n ; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2111O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__A2111O_BEHAVIORAL_PP_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a2111o (
VPWR,
VGND,
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
// Local signals
wire C1 and0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , C1, B1, and0_out, D1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2111O_BEHAVIORAL_PP_V |
/**
*@file bcode_generator.v
*@brief Generate IRIG-B code using TAI time
*@author LUAN Yuezhen
*@date Origin 2016.11.23
*@tab Tab size = 4 spaces
*/
module bcode_generator(
input clk,
input rst_n,
input clk_reload_n,
input pps_in,
input [63 : 0] tai_sec_in,
input [15 : 0] leap_sec_in,
input [7 : 0] leap_direct_in,
input [63 : 0] leap_occur_in,
input [63 : 0] dst_ing_in,
input [63 : 0] dst_eng_in,
input [7 : 0] time_zone_in,
input [7 : 0] time_quality_in,
output [55 : 0] utc_time_out,
output bcode_out
);
localparam LREF_INIT = 3'b0;
localparam LREF_IDLE = 3'b1;
localparam LREF_HOLD = 3'b10;
localparam LREF_DELAY = 3'b100;
wire [16 : 0] year;
wire [8 : 0] day_of_year;
wire [4 : 0] hour_of_day;
wire [5 : 0] minute_of_hour;
wire [5 : 0] sec_of_minute;
wire [16 : 0] sec_of_day;
wire utc_time_ok;
wire pps_redge_catch;
reg [1 : 0] pps_redge_catcher;
reg [15 : 0] leap_sec_rec;
reg leap_sec_refresh;
reg [7 : 0] lref_state;
reg [7 : 0] lref_next_state;
reg [2 : 0] lref_delay_count;
assign utc_time_out[8 * 0 +: 16] = year[15 : 0];
assign utc_time_out[8 * 2 +: 16] = day_of_year;
assign utc_time_out[8 * 4 +: 8] = hour_of_day;
assign utc_time_out[8 * 5 +: 8] = minute_of_hour;
assign utc_time_out[8 * 6 +: 8] = sec_of_minute;
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n) begin
pps_redge_catcher <= 2'b11;
end
else begin
pps_redge_catcher[0] <= pps_in;
pps_redge_catcher[1] <= pps_redge_catcher[0];
end
end
assign pps_redge_catch = (pps_redge_catcher == 2'b01) ? 1'b1 : 1'b0;
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n) begin
lref_state <= LREF_INIT;
end
else begin
lref_state <= lref_next_state;
end
end
always @ (*)
begin
case (lref_state)
LREF_INIT : begin
lref_next_state = LREF_IDLE;
end
LREF_IDLE : begin
if (leap_sec_rec == leap_sec_in) begin
lref_next_state = LREF_IDLE;
end
else begin
lref_next_state = LREF_HOLD;
end
end
LREF_HOLD : begin
if (pps_redge_catch) begin
lref_next_state = LREF_DELAY;
end
else begin
lref_next_state = LREF_HOLD;
end
end
LREF_DELAY : begin
if (lref_delay_count < 3'b111) begin
lref_next_state = LREF_DELAY;
end
else begin
lref_next_state = LREF_IDLE;
end
end
default : begin
lref_next_state = LREF_IDLE;
end
endcase
end
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n) begin
lref_delay_count <= 3'b0;
leap_sec_refresh <= 1'b0;
end
else begin
case (lref_state)
LREF_INIT : begin
end
LREF_IDLE : begin
if (leap_sec_rec == leap_sec_in) begin
leap_sec_refresh <= 1'b0;
end
else begin
leap_sec_refresh <= 1'b1;
end
end
LREF_HOLD : begin
leap_sec_rec <= leap_sec_in;
end
LREF_DELAY : begin
lref_delay_count <= lref_delay_count + 1'b1;
end
default : begin
end
endcase
end
end
tai_to_utc tai_cnv(
.clk(clk),
.rst(rst_n),
.pps_in(pps_in),
.tai_sec_in(tai_sec_in),
.leap_sec_in(leap_sec_in),
.leap_sec_refresh_in(leap_sec_refresh),
.leap_direct_in(leap_direct_in),
.leap_occur_in(leap_occur_in),
.dst_ing_in(dst_ing_in),
.dst_eng_in(dst_eng_in),
.time_zone_in(time_zone_in),
.year_out(year),
.day_of_year_out(day_of_year),
.hour_of_day_out(hour_of_day),
.minute_of_hour_out(minute_of_hour),
.sec_of_minute_out(sec_of_minute),
.sec_of_day_out(sec_of_day),
.utc_time_ok_out(utc_time_ok)
);
bcode_encoder bcode_encoder_inst0(
.clk(clk),
.pps(pps_in),
.rst_n(rst_n),
.clk_reload_n(clk_reload_n),
.utc_cnv_end(utc_time_ok),
.sec_bin(sec_of_minute),
.min_bin(minute_of_hour),
.hour_bin(hour_of_day),
.day_bin(day_of_year),
.year_bin(year),
.tai_sec(tai_sec_in),
.time_zone(time_zone_in),
.dst_ing(dst_ing_in),
.dst_eng(dst_eng_in),
.leap_occur(leap_occur_in),
.leap_direct(leap_direct_in[0]),
.time_quality(time_quality_in),
.sec_of_day(sec_of_day),
.bcode_trans(bcode_out)
);
endmodule
|
#include <bits/stdc++.h> inline int getInt() { int s; scanf( %d , &s); return s; } using namespace std; struct Node { long long highest; int mxL; int mxR; int idxL; int idxR; Node(long long h, long long l, long long r, int il, int ir) : highest(h), mxL(l), mxR(r), idxL(il), idxR(ir) {} }; template <typename Data, typename Func> class SegmentTree { public: int n; std::vector<Data> data; Func f; Data d; Data query(int a, int b, int k, int l, int r) const { if (r <= a || b <= l) return d; if (a <= l && r <= b) return data[k]; else { const Data v1 = query(a, b, k * 2 + 1, l, (l + r) / 2); const Data v2 = query(a, b, k * 2 + 2, (l + r) / 2, r); return f(v1, v2); } } SegmentTree(int nn, Func f, Data d) : f(f), d(d) { n = 1; while (n < nn) n *= 2; data = std::vector<Data>(2 * n, d); } void update(int k, const Data &a) { k += n - 1; data[k] = a; while (k > 0) { k = (k - 1) / 2; data[k] = f(data[k * 2 + 1], data[k * 2 + 2]); } } Data query(int a, int b) const { return query(a, b, 0, 0, n); } }; template <typename Data, typename Func> SegmentTree<Data, Func> segtree(int numberOfElements, Data defaultValue, Func mergeFunc) { return SegmentTree<Data, Func>(numberOfElements, mergeFunc, defaultValue); } int main() { const int n = getInt(); const int m = getInt(); vector<long long> d(n); vector<long long> h(n); for (int i = 0; i < (int)(n); i++) d[i] = getInt(); for (int i = 0; i < (int)(n); i++) h[i] = getInt(); vector<long long> ps(2 * n + 1); for (int i = 0; i < (int)(2 * n); i++) ps[i + 1] = ps[i] + d[i % n]; const Node df(-1, 0, 0, 0, 0); auto calc = [&](int l, int r) { if (l == r) return 0ll; return ps[r] - ps[l] + 2 * (h[l % n] + h[r % n]); }; auto st = segtree(2 * n, df, [&](const Node &lhs, const Node &rhs) { if (lhs.highest == -1) return rhs; if (rhs.highest == -1) return lhs; const int idxL = lhs.idxL; const int idxR = rhs.idxR; const long long la = calc(idxL, lhs.mxL); const long long lb = calc(idxL, rhs.mxL); const long long lc = calc(idxL, rhs.idxL); const long long ml = max(max(la, lb), lc); const int mxL = lc > la && lc > lb ? rhs.idxL : la > lb ? lhs.mxL : rhs.mxL; const long long ra = calc(lhs.mxR, idxR); const long long rb = calc(rhs.mxR, idxR); const long long rc = calc(lhs.idxR, idxR); const long long mr = max(max(ra, rb), rc); const int mxR = rc > ra && rc > rb ? lhs.idxR : rb > ra ? rhs.mxR : lhs.mxR; const long long t = max(max(calc(lhs.mxR, rhs.mxL), calc(lhs.mxR, rhs.idxL)), max(calc(lhs.idxR, rhs.mxL), calc(lhs.idxR, rhs.idxL))); const long long highest = max( t, max(max(max(lhs.highest, rhs.highest), max(ml, mr)), calc(idxL, idxR))); return Node(highest, mxL, mxR, idxL, idxR); }); for (int i = 0; i < (int)(2 * n); i++) st.update(i, Node(0, i, i, i, i)); for (int i = 0; i < (int)(m); i++) { const int a = getInt() - 1; const int b = getInt() - 1; const int aa = b + 1; const int bb = a <= b ? a + n - 1 : a - 1; const Node ans = st.query(aa, bb + 1); cout << ans.highest << endl; } return 0; } |
//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module spw_light_time_out (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 5: 0] in_port;
input reset_n;
wire clk_en;
wire [ 5: 0] data_in;
wire [ 5: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {6 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
/*
* Frame Generator
*
* Generate the replied package from Tag to Reader
* including Preamle, Replied Data, End-of-Signaling
*
* Support FM0 Encoder and Miller Encoder in M = 2, 4, 8
* the forms of encoding is depends on M
*
* Two forms of preamble, which is depends on Trext
*/
`timescale 1us / 1ns
module frmgen
(
output reg send_data,
output en_fm0,
output reg st_enc,
output pre_p_complete,
output p_complete,
output reg fg_complete,
input clk_frm,
input rst_for_new_package,
input reply_data,
input [15:0]crc_16,
input [1:0]m,
input trext,
input reply_complete,
input en_crc16_for_rpy
);
reg reply_complete_d;
reg [4:0]cnt_end;
reg [4:0]p_cnt;
reg [3:0]crc_cnt;
reg crc_complete;
assign en_fm0 = (m == 2'b00)? 1'b1 : 1'b0;
assign pre_p_complete = (p_cnt > (cnt_end - 5'h2))? 1'b1 : 1'b0;
assign p_complete = (p_cnt == cnt_end)? 1'b1 : 1'b0;
always@(posedge clk_frm or negedge rst_for_new_package) begin
if(~rst_for_new_package) st_enc <= 1'b0;
else st_enc <= 1'b1;
end
always@(posedge clk_frm or negedge rst_for_new_package) begin
if(~rst_for_new_package) reply_complete_d <= 1'b0;
else reply_complete_d <= reply_complete;
end
always@(*) begin
case({m, trext})
3'b000 : cnt_end = 5'h6;
3'b001 : cnt_end = 5'h12;
3'b010 : cnt_end = 5'ha;
3'b011 : cnt_end = 5'h16;
3'b100 : cnt_end = 5'ha;
3'b101 : cnt_end = 5'h16;
3'b110 : cnt_end = 5'ha;
3'b111 : cnt_end = 5'h16;
endcase
end
always@(posedge clk_frm or negedge rst_for_new_package) begin
if(~rst_for_new_package) p_cnt <= 5'h0;
else begin
if(p_cnt == cnt_end) p_cnt <= p_cnt;
else p_cnt <= p_cnt + 5'h1;
end
end
always@(posedge clk_frm or negedge rst_for_new_package) begin
if(~rst_for_new_package) send_data <= 1'b0;
else if(~en_crc16_for_rpy & reply_complete_d) send_data <= 1'b1;
else if(en_crc16_for_rpy & crc_complete) send_data <= 1'b1;
else if(reply_complete_d & en_crc16_for_rpy & ~crc_complete) send_data <= crc_16[crc_cnt];
else begin
if(p_cnt != cnt_end) begin
if(m == 2'b00) begin
if(~trext) begin
case(p_cnt)
5'h0 : send_data <= 1'b1;
5'h1 : send_data <= 1'b0;
5'h2 : send_data <= 1'b1;
5'h3 : send_data <= 1'b0;
5'h4 : send_data <= 1'b0;
5'h5 : send_data <= 1'b1;
endcase
end
else begin
case(p_cnt)
5'h0, 5'h1, 5'h2, 5'h3, 5'h4, 5'h5, 5'h6, 5'h7, 5'h8, 5'h9, 5'ha, 5'hb : send_data <= 1'b0;
5'hc : send_data <= 1'b1;
5'hd : send_data <= 1'b0;
5'he : send_data <= 1'b1;
5'hf : send_data <= 1'b0;
5'h10 : send_data <= 1'b0;
5'h11 : send_data <= 1'b1;
endcase
end
end
else begin
if(~trext) begin
case(p_cnt)
5'h0, 5'h1, 5'h2, 5'h3 : send_data <= 1'b0;
5'h4 : send_data <= 1'b0;
5'h5 : send_data <= 1'b1;
5'h6 : send_data <= 1'b0;
5'h7 : send_data <= 1'b1;
5'h8 : send_data <= 1'b1;
5'h9 : send_data <= 1'b1;
endcase
end
else begin
case(p_cnt)
5'h0, 5'h1, 5'h2, 5'h3, 5'h4, 5'h5, 5'h6, 5'h7, 5'h8, 5'h9, 5'ha, 5'hb, 5'hc, 5'hd, 5'he, 5'hf : send_data <= 1'b0;
5'h10 : send_data <= 1'b0;
5'h11 : send_data <= 1'b1;
5'h12 : send_data <= 1'b0;
5'h13 : send_data <= 1'b1;
5'h14 : send_data <= 1'b1;
5'h15 : send_data <= 1'b1;
endcase
end
end
end
else send_data <= reply_data;
end
end
always@(posedge clk_frm or negedge rst_for_new_package) begin
if(~rst_for_new_package) crc_cnt <= 4'hf;
else begin
if(crc_cnt == 4'h0) crc_cnt <= crc_cnt;
else if(reply_complete_d & en_crc16_for_rpy) crc_cnt <= crc_cnt - 4'h1;
end
end
always@(posedge clk_frm or negedge rst_for_new_package) begin
if(~rst_for_new_package) crc_complete <= 1'b0;
else if(crc_cnt == 4'h0) crc_complete <= 1'b1;
end
always@(posedge clk_frm or negedge rst_for_new_package) begin
if(~rst_for_new_package) fg_complete <= 1'b0;
else begin
if(reply_complete_d & ~en_crc16_for_rpy) fg_complete <= 1'b1;
else if(crc_complete & en_crc16_for_rpy) fg_complete <= 1'b1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); deque<long long int> b, g; long long int n; cin >> n; for (long long int i = 0; i < n; i++) { long long int temp; cin >> temp; b.push_back(temp); } cin >> n; for (long long int i = 0; i < n; i++) { long long int temp; cin >> temp; g.push_back(temp); } sort(b.begin(), b.end()); sort(g.begin(), g.end()); long long int ans = 0; while (b.size() && g.size()) { if (abs(b.front() - g.front()) <= 1) { ans++; b.pop_front(); g.pop_front(); } else { if (b.front() < g.front()) b.pop_front(); else g.pop_front(); } } cout << ans; return 0; } |
`timescale 1ns/100ps
// Actel Corporation Proprietary and Confidential
// Copyright 2008 Actel Corporation. All rights reserved.
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
// Revision Information:
// SVN Revision Information:
// SVN $Revision: 11864 $
// SVN $Date: 2010-01-22 06:51:45 +0000 (Fri, 22 Jan 2010) $
module
BFMA1l1OII
(
HCLK
,
HRESETN
,
HSEL
,
HWRITE
,
HADDR
,
HWDATA
,
HRDATA
,
HREADYIN
,
HREADYOUT
,
HTRANS
,
HSIZE
,
HBURST
,
HMASTLOCK
,
HPROT
,
HRESP
,
PSEL
,
PADDR
,
PWRITE
,
PENABLE
,
PWDATA
,
PRDATA
,
PREADY
,
PSLVERR
)
;
parameter
TPD
=
1
;
input
HCLK
;
input
HRESETN
;
input
HSEL
;
input
HWRITE
;
input
[
31
:
0
]
HADDR
;
input
[
31
:
0
]
HWDATA
;
output
[
31
:
0
]
HRDATA
;
wire
[
31
:
0
]
HRDATA
;
input
HREADYIN
;
output
HREADYOUT
;
wire
HREADYOUT
;
input
[
1
:
0
]
HTRANS
;
input
[
2
:
0
]
HSIZE
;
input
[
2
:
0
]
HBURST
;
input
HMASTLOCK
;
input
[
3
:
0
]
HPROT
;
output
HRESP
;
wire
HRESP
;
output
[
15
:
0
]
PSEL
;
wire
[
15
:
0
]
PSEL
;
output
[
31
:
0
]
PADDR
;
wire
[
31
:
0
]
PADDR
;
output
PWRITE
;
wire
PWRITE
;
output
PENABLE
;
wire
PENABLE
;
output
[
31
:
0
]
PWDATA
;
wire
[
31
:
0
]
PWDATA
;
input
[
31
:
0
]
PRDATA
;
input
PREADY
;
input
PSLVERR
;
parameter
[
1
:
0
]
BFMA1OOIII
=
0
;
parameter
[
1
:
0
]
BFMA1IOIII
=
1
;
parameter
[
1
:
0
]
BFMA1lOIII
=
2
;
parameter
[
1
:
0
]
BFMA1OIIII
=
3
;
reg
[
1
:
0
]
BFMA1IIIII
;
reg
BFMA1lIIII
;
reg
BFMA1OlIII
;
reg
[
15
:
0
]
BFMA1IlIII
;
reg
[
31
:
0
]
BFMA1llIII
;
reg
BFMA1O0III
;
reg
BFMA1I0III
;
reg
[
31
:
0
]
BFMA1l0III
;
wire
[
31
:
0
]
BFMA1O1III
;
reg
BFMA1I1III
;
reg
BFMA1l1III
;
always
@
(
posedge
HCLK
or
negedge
HRESETN
)
begin
if
(
HRESETN
==
1
'b
0
)
begin
BFMA1IIIII
<=
BFMA1OOIII
;
BFMA1lIIII
<=
1
'b
1
;
BFMA1llIII
<=
{
32
{
1
'b
0
}
}
;
BFMA1l0III
<=
{
32
{
1
'b
0
}
}
;
BFMA1O0III
<=
1
'b
0
;
BFMA1I0III
<=
1
'b
0
;
BFMA1OlIII
<=
1
'b
0
;
BFMA1I1III
<=
1
'b
0
;
BFMA1l1III
<=
1
'b
0
;
end
else
begin
BFMA1OlIII
<=
1
'b
0
;
BFMA1lIIII
<=
1
'b
0
;
BFMA1I1III
<=
1
'b
0
;
case
(
BFMA1IIIII
)
BFMA1OOIII
:
begin
if
(
HSEL
==
1
'b
1
&
HREADYIN
==
1
'b
1
&
(
HTRANS
[
1
]
)
==
1
'b
1
)
begin
BFMA1IIIII
<=
BFMA1IOIII
;
BFMA1llIII
<=
HADDR
;
BFMA1O0III
<=
HWRITE
;
BFMA1l0III
<=
HWDATA
;
BFMA1I0III
<=
1
'b
0
;
BFMA1I1III
<=
HWRITE
;
BFMA1l1III
<=
1
'b
1
;
end
else
begin
BFMA1lIIII
<=
1
'b
1
;
end
end
BFMA1IOIII
:
begin
BFMA1I0III
<=
1
'b
1
;
BFMA1IIIII
<=
BFMA1lOIII
;
end
BFMA1lOIII
:
begin
if
(
PREADY
==
1
'b
1
)
begin
BFMA1I0III
<=
1
'b
0
;
BFMA1l1III
<=
1
'b
0
;
if
(
PSLVERR
==
1
'b
0
)
begin
BFMA1IIIII
<=
BFMA1OOIII
;
if
(
HSEL
==
1
'b
1
&
HREADYIN
==
1
'b
1
&
(
HTRANS
[
1
]
)
==
1
'b
1
)
begin
BFMA1IIIII
<=
BFMA1IOIII
;
BFMA1llIII
<=
HADDR
;
BFMA1O0III
<=
HWRITE
;
BFMA1I1III
<=
HWRITE
;
BFMA1l1III
<=
1
'b
1
;
end
end
else
begin
BFMA1OlIII
<=
1
'b
1
;
BFMA1IIIII
<=
BFMA1OIIII
;
end
end
end
BFMA1OIIII
:
begin
BFMA1OlIII
<=
1
'b
1
;
BFMA1lIIII
<=
1
'b
1
;
BFMA1IIIII
<=
BFMA1OOIII
;
end
endcase
if
(
BFMA1I1III
==
1
'b
1
)
begin
BFMA1l0III
<=
HWDATA
;
end
end
end
always
@
(
BFMA1llIII
or
BFMA1l1III
)
begin
BFMA1IlIII
<=
{
16
{
1
'b
0
}
}
;
if
(
BFMA1l1III
==
1
'b
1
)
begin
begin
:
BFMA1IO10
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<=
15
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
BFMA1IlIII
[
BFMA1I0I0
]
<=
(
BFMA1llIII
[
27
:
24
]
==
BFMA1I0I0
)
;
end
end
end
end
assign
BFMA1O1III
=
(
BFMA1I1III
==
1
'b
1
)
?
HWDATA
:
BFMA1l0III
;
assign
#
TPD
HRDATA
=
PRDATA
;
assign
#
TPD
HREADYOUT
=
BFMA1lIIII
|
(
PREADY
&
BFMA1l1III
&
BFMA1I0III
&
~
PSLVERR
)
;
assign
#
TPD
HRESP
=
BFMA1OlIII
;
assign
#
TPD
PSEL
=
BFMA1IlIII
;
assign
#
TPD
PADDR
=
BFMA1llIII
;
assign
#
TPD
PWRITE
=
BFMA1O0III
;
assign
#
TPD
PENABLE
=
BFMA1I0III
;
assign
#
TPD
PWDATA
=
BFMA1O1III
;
endmodule
|
/* -----------------------------------------------------------------------
*
* Copyright 2008 Tommy Thorn - All Rights Reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, Inc., 53 Temple Place Ste 330,
* Bostom MA 02111-1307, USA; either version 2 of the License, or
* (at your option) any later version; incorporated herein by reference.
*
* -----------------------------------------------------------------------
*/
`timescale 1ns/10ps
module sram16_ctrl
(input wire clock
,input wire rst
,output mem_waitrequest
,input [1:0] mem_id
,input [29:0] mem_address
,input mem_read
,input mem_write
,input [31:0] mem_writedata
,input [3:0] mem_writedatamask
,output reg [31:0] mem_readdata
,output reg [1:0] mem_readdataid = 0
,output reg [29:0] sram_a
,inout wire [15:0] sram_d
,output reg sram_cs_n = 1
,output reg [1:0] sram_be_n
,output reg sram_oe_n = 1
,output reg sram_we_n = 1
);
// 48 MHz = 20.8 ns. tRC = tWC = 70 ns ==> 4 cycles ==> 3 wait cyclesg
parameter wait_cycles = 5;
parameter burst_length = 4;
parameter CNTSIGN = 4;
parameter WAITSIGN = 4;
parameter S_IDLE = 0;
parameter S_WRITE1 = 1;
parameter S_WRITE2 = 2;
parameter S_WRITE3 = 3;
parameter S_PAUSE = 4;
reg [ 2:0] state = S_IDLE;
wire sel = mem_address[29:26] == 'h4;
reg [CNTSIGN:0] cnt = ~0;
reg int_we_n = 1;
reg [ 1:0] pendingid;
reg [31:0] sram_dout;
reg [15:0] writedata_hi;
reg [ 1:0] be_n_hi;
reg [WAITSIGN:0] waitcnt = ~0;
assign mem_waitrequest = state != S_IDLE || !cnt[CNTSIGN] || !waitcnt[WAITSIGN];
reg sram_dout_en = 0;
assign sram_d = sram_dout_en ? sram_dout : 'hZ;
always @(negedge clock)
sram_we_n <= int_we_n;
// XXX cs_n cannot be asserted for more than tCEM (4 us). That's ~
// 192 cycles @ 48 MHz. We should track cs_n and pause as required.
// XXX It's a concern that the SRAM D drivers may be fighting
// briefly with our sram_dout when transitioning directly from
// reading to writing. It seems to work, but it would probably be
// safer to wait for a cycle for those cases.
always @(posedge clock) begin
mem_readdataid <= 0;
if (!waitcnt[WAITSIGN])
waitcnt <= waitcnt - 1'd1;
else
case (state)
S_IDLE:
if (!cnt[CNTSIGN]) begin
waitcnt <= wait_cycles - 1'd1;
// Burst reading.
cnt <= cnt - 1;
sram_a <= sram_a + 1'd1;
mem_readdata[31:16] <= sram_d; // Little Endian
mem_readdata[15: 0] <= mem_readdata[31:16];
if (sram_a[0])
// Only signal a complete words
mem_readdataid <= pendingid;
end else if (mem_read) begin
waitcnt <= wait_cycles - 1'd1;
pendingid <= mem_id;
sram_a <= mem_address << 1;
sram_cs_n <= 0;
sram_oe_n <= 0;
sram_be_n <= 0;
int_we_n <= 1;
sram_dout_en <= 0;
cnt <= (burst_length << 1) - 1;
end else if (mem_write) begin
waitcnt <= wait_cycles - 1'd1;
sram_a <= mem_address << 1;
sram_dout_en <= 1;
{writedata_hi,sram_dout[15:0]} <= mem_writedata;
{be_n_hi,sram_be_n[1:0]} <= ~mem_writedatamask;
sram_cs_n <= 0;
sram_oe_n <= 1;
int_we_n <= 0;
state <= S_WRITE1;
end else begin
sram_cs_n <= 1;
sram_oe_n <= 1;
sram_dout_en <= 0;
int_we_n <= 1;
end
S_WRITE1: begin
int_we_n <= 1;
state <= S_WRITE2;
end
S_WRITE2: begin
waitcnt <= wait_cycles - 1'd1;
sram_a[0] <= 1;
sram_dout <= writedata_hi; // Little endian
sram_be_n <= be_n_hi;
int_we_n <= 0;
state <= S_WRITE3;
end
S_WRITE3: begin
int_we_n <= 1;
state <= S_IDLE; // S_PAUSE
end
S_PAUSE: begin
sram_cs_n <= 1;
waitcnt <= wait_cycles - 1'd1;
state <= S_IDLE;
end
endcase
end
`define DEBUG_SRAM 1
`ifdef DEBUG_SRAM
always @(negedge clock)
$display("%05d SRAM cs# %x a %x d %x we# %x oe# %x", $time,
sram_cs_n, sram_a, sram_d, sram_we_n, sram_oe_n);
always @(posedge clock) begin
if (!mem_waitrequest & sel & mem_read)
$display("%05d sram[%x] -> ? for %d", $time,
{mem_address,2'd0}, mem_id);
if (!mem_waitrequest & sel & mem_write)
$display("%05d sram[%x] <- %8x/%x", $time,
{mem_address,2'd0}, mem_writedata, mem_writedatamask);
if (mem_readdataid)
$display("%05d sram[%x] -> %8x for %d", $time,
32'h3fff_fffc + (sram_a << 2), mem_readdata, mem_readdataid);
$display("%05d SRAM cs# %x a %x d %x we# %x oe# %x", $time,
sram_cs_n, sram_a, sram_d, sram_we_n, sram_oe_n);
end
`endif
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MAJ3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__MAJ3_FUNCTIONAL_PP_V
/**
* maj3: 3-input majority vote.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__maj3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out ;
wire and1_out ;
wire or1_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , B, A );
and and0 (and0_out , or0_out, C );
and and1 (and1_out , A, B );
or or1 (or1_out_X , and1_out, and0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or1_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__MAJ3_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int main() { long long n, m, k, a; scanf( %I64d%I64d%I64d , &n, &m, &k); if (n + m - 2 < k) printf( -1 ); else { if (n > m) { a = n; n = m; m = a; } if (n >= k + 1) { printf( %I64d , max((m / (k + 1)) * n, (n / (k + 1)) * m)); } else { if (m >= k + 1) printf( %I64d , (m / (k + 1)) * n); else printf( %I64d , n / (k - m + 2)); } } } |
#include <bits/stdc++.h> using namespace std; int n; int gcd(int a, int b) { return b == 0 ? a : gcd(b, a % b); } int main() { scanf( %d , &n); if (n == 1) { printf( 0 n0 n0 n ); return 0; } for (int t = 1; t <= n - 1; t++) if (gcd(t, n) == 1 && gcd(t + 1, n) == 1) { for (int i = 0; i < n; i++) printf( %d , i); printf( n ); for (int i = 0; i < n; i++) printf( %d , (int)(1ll * t * i % n)); printf( n ); for (int i = 0; i < n; i++) printf( %d , (int)(1ll * (t + 1) * i % n)); printf( n ); return 0; } printf( -1 n ); return 0; } |
#include <bits/stdc++.h> using namespace ::std; const int maxn = 1e5 + 5; map<long long, int> mp; long long sum[maxn], ans; int n, k; void solve() { long long maxx = 0, minn = 0; scanf( %d%d , &n, &k); mp[0] = 1; for (int i = 1; i <= n; i++) { long long tmp; scanf( %I64d , &tmp); sum[i] = sum[i - 1] + tmp; mp[sum[i]]++; maxx = max(maxx, sum[i]); minn = min(minn, sum[i]); for (long long j = 1; - 1e15 <= j && j <= 1e15; j *= k) { if (mp.find(sum[i] - j) != mp.end()) { ans += mp[sum[i] - j]; } if (k == 1) break; if (j == -1 && k == -1) break; } } printf( %I64d n , ans); } int main() { solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long INF = 1 << 28; const long long LINF = 1ll << 61; inline long long getnum() { register long long r = 0; register bool ng = 0; register char c; c = getchar(); while (c != - && (c < 0 || c > 9 )) c = getchar(); if (c == - ) ng = 1, c = getchar(); while (c != && c != n ) r = r * 10 + c - 0 , c = getchar(); if (ng) r = -r; return r; } template <class T> inline void putnum(T x) { if (x < 0) putchar( - ), x = -x; register short a[20] = {}, sz = 0; while (x > 0) a[sz++] = x % 10, x /= 10; if (sz == 0) putchar( 0 ); for (int i = sz - 1; i >= 0; i--) putchar( 0 + a[i]); } inline void putsp() { putchar( ); } inline void putendl() { putchar( n ); } int n, a[200111], p[200111], cnt[200111], mx = 1, ans[200111]; bool f[200111]; map<int, vector<int> > mp; int gf(int x) { return x == p[x] ? x : p[x] = gf(p[x]); } void un(int x, int y) { x = gf(x), y = gf(y); if (x == y) return; p[y] = x; cnt[x] += cnt[y]; mx = max(mx, cnt[x]); } int main() { n = getnum(); for (int i = 1; i <= n; i++) { p[i] = i; a[i] = getnum(); mp[a[i]].push_back(i); cnt[i] = 1; } for (map<int, vector<int> >::iterator it = --mp.end();; it--) { vector<int> &v = it->second; for (int i = 0; i < v.size(); i++) { f[v[i]] = 1; if (f[v[i] - 1]) un(v[i] - 1, v[i]); if (f[v[i] + 1]) un(v[i] + 1, v[i]); ans[mx] = max(ans[mx], it->first); } if (it == mp.begin()) break; } int res = ans[n]; for (int i = n; i >= 1; i--) { if (ans[i] != 0) res = ans[i]; ans[i] = res; } for (int i = 1; i <= n; i++) putnum(ans[i]), putsp(); return 0; } |
#include <bits/stdc++.h> using namespace std; vector<int> v; int main() { int n, k, l, r, sall, sk, i, res, ext, j, a, b; while (scanf( %d %d %d %d %d %d , &n, &k, &l, &r, &sall, &sk) == 6) { v.clear(); if (sk % k == 0) { res = sk / k; for (i = 0; i < k; i++) { v.push_back(res); } } else { res = sk / k; ext = sk % k; for (i = 0, j = 0; i < k; i++, j++) { if (j < ext) v.push_back(res + 1); else v.push_back(res); } } a = sall - sk; b = n - k; if (b > 0) { if (a % b == 0) { res = a / b; for (i = 0; i < b; i++) { v.push_back(res); } } else { res = a / b; ext = a % b; for (i = 0, j = 0; i < b; i++, j++) { if (j < ext) v.push_back(res + 1); else v.push_back(res); } } } for (i = 0; i < ((int)v.size()); i++) { if (!i) cout << v[i]; else cout << << v[i]; } cout << endl; } return 0; } |
/*
* Copyright 2010, Aleksander Osman, . All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are
* permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module ssram(
input CLK_I,
input RST_I,
//slave
output reg [31:0] DAT_O,
input [31:0] DAT_I,
output reg ACK_O,
input CYC_I,
input [20:2] ADR_I,
input STB_I,
input WE_I,
input [3:0] SEL_I,
//ssram interface
output [18:0] ssram_address,
output reg ssram_oe_n,
output reg ssram_writeen_n,
output reg ssram_byteen0_n,
output reg ssram_byteen1_n,
output reg ssram_byteen2_n,
output reg ssram_byteen3_n,
inout [31:0] ssram_data,
output ssram_clk,
output ssram_mode,
output ssram_zz,
output ssram_globalw_n,
output ssram_advance_n,
output reg ssram_adsp_n,
output ssram_adsc_n,
output ssram_ce1_n,
output ssram_ce2,
output ssram_ce3_n
);
assign ssram_address = ADR_I;
assign ssram_clk = CLK_I;
assign ssram_mode = 1'b0;
assign ssram_zz = 1'b0;
assign ssram_globalw_n = 1'b1;
assign ssram_advance_n = 1'b1;
assign ssram_adsc_n = 1'b1;
assign ssram_ce1_n = 1'b0;
assign ssram_ce2 = 1'b1;
assign ssram_ce3_n = 1'b0;
reg [31:0] ssram_data_o;
assign ssram_data = (ssram_oe_n == 1'b1) ? ssram_data_o : 32'dZ;
reg [2:0] counter;
//reg second;
always @(posedge CLK_I) begin
if(RST_I == 1'b1) begin
DAT_O <= 32'd0;
ACK_O <= 1'b0;
//ssram_address <= 19'd0;
ssram_oe_n <= 1'b1;
ssram_writeen_n <= 1'b1;
ssram_byteen0_n <= 1'b1;
ssram_byteen1_n <= 1'b1;
ssram_byteen2_n <= 1'b1;
ssram_byteen3_n <= 1'b1;
ssram_data_o <= 32'd0;
ssram_adsp_n <= 1'b1;
counter <= 3'd0;
//second <= 1'b0;
end
else begin
if(CYC_I == 1'b1 && STB_I == 1'b1 && WE_I == 1'b0 && ACK_O == 1'b0) begin
if(counter == 3'd0) begin
ssram_adsp_n <= 1'b0;
//ssram_address <= ADR_I;
counter <= counter + 3'd1;
end
else if(counter == 3'd1) begin
ssram_adsp_n <= 1'b1;
ssram_writeen_n <= 1'b1;
ssram_byteen0_n <= 1'b0;
ssram_byteen1_n <= 1'b0;
ssram_byteen2_n <= 1'b0;
ssram_byteen3_n <= 1'b0;
counter <= counter + 3'd1;
end
else if(counter == 3'd2) begin
ssram_oe_n <= 1'b0;
counter <= counter + 3'd1;
end
else if(counter == 3'd3) begin
ssram_oe_n <= 1'b1;
counter <= 3'd0;
DAT_O <= ssram_data;
ACK_O <= 1'b1;
end
end
else if(CYC_I == 1'b1 && STB_I == 1'b1 && WE_I == 1'b1 && ACK_O == 1'b0) begin
if(counter == 3'd0) begin
ssram_adsp_n <= 1'b0;
//ssram_address <= ADR_I[20:2];
ssram_oe_n <= 1'b1;
counter <= counter + 3'd1;
end
else if(counter == 3'd1) begin
ssram_adsp_n <= 1'b1;
ssram_writeen_n <= 1'b0;
ssram_byteen0_n <= (SEL_I[0] == 1'b1) ? 1'b0 : 1'b1;
ssram_byteen1_n <= (SEL_I[1] == 1'b1) ? 1'b0 : 1'b1;
ssram_byteen2_n <= (SEL_I[2] == 1'b1) ? 1'b0 : 1'b1;
ssram_byteen3_n <= (SEL_I[3] == 1'b1) ? 1'b0 : 1'b1;
ssram_data_o <= DAT_I;
counter <= counter + 3'd1;
end
else if(counter == 3'd2) begin
ssram_writeen_n <= 1'b1;
counter <= 3'd0;
ACK_O <= 1'b1;
end
end
else begin
ACK_O <= 1'b0;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A222OI_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__A222OI_PP_BLACKBOX_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a222oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A222OI_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using std::cin; using std::cout; using std::vector; int main() { long long n; cin >> n; int t = 0; while (n > 0) { if (n % 2 != 0) t++; n = n / 2; } cout << t; int h; cin >> h; return 0; } |
// Model a reset synchronizer circuit (active low reset)
//
// Notes:
// - Reset synchronizer creates a "predictable reset
// from an asynchronous reset input. Async resets are
// notorious for their unpredictability - reset assertion
// /removal can happen anytime near the clock edge.
// Reset assertion/removal can be glitchy especially
// when driven from a pin or bounce switch. async
// reset fanouts to multiple flops can take different
// paths. Since reset removal can happen anytime before
// the clock edge of these flops, timing analysis
// is difficult and often unpredictable.
//
// Reset sync circuit allows immediate reset assertion
// and "predictable" reset removal. Clean reset removal
// helps predictable timing analysis.
//
// There won't be any metastability problem on the second
// FF because both input and output are held at active
// low during reset removal and therefore the output
// doesn't oscillate during reset removal. The first
// flop can still have metastability.
//
// Also note that the metastability issue occures only
// at during reset removal, not during reset assertion.
// reset assertion happens immediately (as in the reset
// bypasses the flop)
//
module reset_synchronizer (
input arst_in_n,
input clk
output arst_out_n
);
reg[1:0] ff;
assign arst_out_n = ff[1];
always@(posedge clk or negedge arst_in_n)
begin
if(arst_in_n)
ff <= '0;
else
ff <= {ff[0],1'b1};
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/);
// IEEE: integer_atom_type
byte d_byte;
shortint d_shortint;
int d_int;
longint d_longint;
integer d_integer;
time d_time;
chandle d_chandle;
// IEEE: integer_atom_type
bit d_bit;
logic d_logic;
reg d_reg;
bit [0:0] d_bit1;
logic [0:0] d_logic1;
reg [0:0] d_reg1;
bit d_bitz;
logic d_logicz;
reg d_regz;
// IEEE: non_integer_type
//UNSUP shortreal d_shortreal;
real d_real;
realtime d_realtime;
initial begin
// below errors might cause spurious warnings
// verilator lint_off WIDTH
d_bitz[0] = 1'b1; // Illegal range
d_logicz[0] = 1'b1; // Illegal range
d_regz[0] = 1'b1; // Illegal range
`ifndef VERILATOR //UNSUPPORTED, it's just a 64 bit int right now
d_chandle[0] = 1'b1; // Illegal
`endif
d_real[0] = 1'b1; // Illegal
d_realtime[0] = 1'b1; // Illegal
// verilator lint_on WIDTH
d_byte[0] = 1'b1; // OK
d_shortint[0] = 1'b1; // OK
d_int[0] = 1'b1; // OK
d_longint[0] = 1'b1; // OK
d_integer[0] = 1'b1; // OK
d_time[0] = 1'b1; // OK
d_bit1[0] = 1'b1; // OK
d_logic1[0] = 1'b1; // OK
d_reg1[0] = 1'b1; // OK
end
endmodule
|
module alt_vipitc131_IS2Vid_calculate_mode(
input [3:0] trs,
input is_interlaced,
input is_serial_output,
input [15:0] is_sample_count_f0,
input [15:0] is_line_count_f0,
input [15:0] is_sample_count_f1,
input [15:0] is_line_count_f1,
input [15:0] is_h_front_porch,
input [15:0] is_h_sync_length,
input [15:0] is_h_blank,
input [15:0] is_v_front_porch,
input [15:0] is_v_sync_length,
input [15:0] is_v_blank,
input [15:0] is_v1_front_porch,
input [15:0] is_v1_sync_length,
input [15:0] is_v1_blank,
input [15:0] is_ap_line,
input [15:0] is_v1_rising_edge,
input [15:0] is_f_rising_edge,
input [15:0] is_f_falling_edge,
input [15:0] is_anc_line,
input [15:0] is_v1_anc_line,
output interlaced_nxt,
output serial_output_nxt,
output [15:0] h_total_minus_one_nxt,
output [15:0] v_total_minus_one_nxt,
output [15:0] ap_line_nxt,
output [15:0] ap_line_end_nxt,
output [15:0] h_blank_nxt,
output [15:0] sav_nxt,
output [15:0] h_sync_start_nxt,
output [15:0] h_sync_end_nxt,
output [15:0] f2_v_start_nxt,
output [15:0] f1_v_start_nxt,
output [15:0] f1_v_end_nxt,
output [15:0] f2_v_sync_start_nxt,
output [15:0] f2_v_sync_end_nxt,
output [15:0] f1_v_sync_start_nxt,
output [15:0] f1_v_sync_end_nxt,
output [15:0] f_rising_edge_nxt,
output [15:0] f_falling_edge_nxt,
output [12:0] total_line_count_f0_nxt,
output [12:0] total_line_count_f1_nxt,
output [15:0] f2_anc_v_start_nxt,
output [15:0] f1_anc_v_start_nxt
);
wire [15:0] v_active_lines;
wire [15:0] v_total;
wire [15:0] v1_rising_edge;
wire [15:0] v2_rising_edge;
wire [15:0] f1_v_sync;
wire [15:0] f2_v_sync;
wire [15:0] total_line_count_f0_nxt_full;
wire [15:0] total_line_count_f1_nxt_full;
assign v_active_lines = (is_interlaced ? is_line_count_f1 : 16'd0) + is_line_count_f0;
assign v_total = v_active_lines + (is_interlaced ? is_v1_blank : 16'd0) + is_v_blank;
assign v1_rising_edge = is_v1_rising_edge - is_ap_line;
assign v2_rising_edge = v_active_lines + (is_interlaced ? is_v1_blank : 16'd0);
assign f1_v_sync = v1_rising_edge + is_v1_front_porch;
assign f2_v_sync = v2_rising_edge + is_v_front_porch;
assign interlaced_nxt = is_interlaced;
assign serial_output_nxt = is_serial_output;
// counter wrapping
assign h_total_minus_one_nxt = is_sample_count_f0 + is_h_blank - 16'd1;
assign v_total_minus_one_nxt = v_total - 16'd1;
// line numbering
assign ap_line_nxt = is_ap_line;
assign ap_line_end_nxt = v_total - is_ap_line;
// horizontal blanking end
assign h_blank_nxt = is_h_blank;
assign sav_nxt = is_h_blank - trs;
// horizontal sync start & end
assign h_sync_start_nxt = is_h_front_porch;
assign h_sync_end_nxt = is_h_front_porch + is_h_sync_length;
// f2 vertical blanking start
assign f2_v_start_nxt = v2_rising_edge;
// f1 vertical blanking start & end
assign f1_v_start_nxt = v1_rising_edge;
assign f1_v_end_nxt = v1_rising_edge + is_v1_blank;
// f2 vertical sync start & end
assign f2_v_sync_start_nxt = f2_v_sync;
assign f2_v_sync_end_nxt = f2_v_sync + is_v_sync_length;
// f1 vertical sync start and end
assign f1_v_sync_start_nxt = f1_v_sync;
assign f1_v_sync_end_nxt = f1_v_sync + is_v1_sync_length;
// f rising edge
assign f_rising_edge_nxt = is_f_rising_edge - is_ap_line;
assign f_falling_edge_nxt = v_total - (is_ap_line - is_f_falling_edge);
// sync generation
assign total_line_count_f0_nxt_full = is_line_count_f0 + (is_v_blank - is_v_front_porch + is_v1_front_porch) - 16'd1;
assign total_line_count_f1_nxt_full = is_line_count_f1 + (is_v1_blank - is_v1_front_porch + is_v_front_porch) - 16'd1;
assign total_line_count_f0_nxt = total_line_count_f0_nxt_full[12:0];
assign total_line_count_f1_nxt = total_line_count_f1_nxt_full[12:0];
// ancilliary data position
assign f2_anc_v_start_nxt = v_total - (is_ap_line - is_anc_line);
assign f1_anc_v_start_nxt = is_v1_anc_line - is_ap_line;
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2.1 (win64) Build Wed Aug 9 16:32:24 MDT 2017
// Date : Fri Sep 22 14:41:49 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_system_ila_0_0_stub.v
// Design : zqynq_lab_1_design_system_ila_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "bd_1a88,Vivado 2017.2.1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[0:0]" */;
input clk;
input [0:0]probe0;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(NULL); int m, n; cin >> m >> n; set<int> v[m]; for (int i = 0; i < m; i++) { int s; cin >> s; for (int j = 0; j < s; j++) { int x; cin >> x; v[i].insert(x); } } for (int i = 0; i < m; i++) { for (int j = i + 1; j < m; j++) { int cnt = 0; for (auto it : v[i]) { if (v[j].find(it) != v[j].end()) { cnt = 1; break; } } if (cnt == 0) { cout << impossible ; exit(0); } } } cout << possible ; return 0; } |
#include <bits/stdc++.h> using namespace std; vector<string> split(const string& s, const string& delim = ) { vector<string> res; string t; for (int i = 0; i != s.size(); i++) { if (delim.find(s[i]) != string::npos) { if (!t.empty()) { res.push_back(t); t = ; } } else { t += s[i]; } } if (!t.empty()) { res.push_back(t); } return res; } vector<int> splitInt(const string& s, const string& delim = ) { vector<string> tok = split(s, delim); vector<int> res; for (int i = 0; i != tok.size(); i++) res.push_back(atoi(tok[i].c_str())); return res; } template <typename T> void print(T a) { cerr << a; } static void print(long long a) { cerr << a << L ; } static void print(string a) { cerr << << a << ; } template <typename T> void print(vector<T> a) { cerr << { ; for (int i = 0; i != a.size(); i++) { if (i != 0) cerr << , ; print(a[i]); } cerr << } << endl; } char flag[1000005]; int main() { string s; while (cin >> s) { memset(flag, 0, sizeof(flag)); reverse(s.begin(), s.end()); for (int i = 0, _n = (s.size()); i < _n; i++) flag[i] = s[i] - 0 ; int i = 0, n = s.size(); while (i < n) { int count = 0; while (i < n && flag[i + count] == 1) count++; if (count > 1) { for (int j = (i), _n = (i + count - 1); j <= _n; j++) flag[j] = 0; flag[i] = -1; flag[i + count] = 1; i = i + count - 1; } i++; } int count = 0; for (int i = 0, _n = (n + 3); i < _n; i++) count += (flag[i] != 0); printf( %d n , count); for (int i = (0), _n = (n + 3); i <= _n; i++) if (flag[i] != 0) { if (flag[i] < 0) printf( - ); else printf( + ); printf( 2^%d n , i); } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__XNOR3_TB_V
`define SKY130_FD_SC_MS__XNOR3_TB_V
/**
* xnor3: 3-input exclusive NOR.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__xnor3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_ms__xnor3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__XNOR3_TB_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; int n, m, t; vector<int> e[maxn]; vector<int> ans; stack<int> s; bool vis[maxn]; int dep[maxn]; int N; bool v[maxn]; int dfs(int x, int fr) { vis[x] = true; s.push(x); for (auto y : e[x]) { if (y == fr) continue; if (!vis[y]) { dep[y] = dep[x] + 1; dfs(y, x); dep[y] = 0; } else if (dep[y]) { if (dep[x] - dep[y] + 1 >= N) { printf( 2 n ); printf( %d n , dep[x] - dep[y] + 1); while (s.top() != y) { printf( %d , s.top()); s.pop(); } printf( %d n , s.top()); exit(0); } } } if (!v[x]) { for (auto y : e[x]) { v[y] = true; } ans.push_back(x); } s.pop(); return 0; } int read() { int x; scanf( %d , &x); return x; } int main() { int i, j; int x, y; n = read(); m = read(); N = sqrt(n); while (N * N < n) N++; for (i = 1; i <= m; i++) { x = read(); y = read(); e[x].push_back(y); e[y].push_back(x); } for (i = 1; i <= n; i++) { if (!vis[i]) { dep[i] = 1; dfs(i, -1); dep[i] = 0; } } printf( 1 n ); for (i = 1; i <= n; i++) { if (v[i]) continue; N--; printf( %d , i); if (!N) break; } printf( n ); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21BAI_TB_V
`define SKY130_FD_SC_HD__O21BAI_TB_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o21bai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1_N = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1_N = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1_N = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 B1_N = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 B1_N = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_hd__o21bai dut (.A1(A1), .A2(A2), .B1_N(B1_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21BAI_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSRECEIVER_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__BUSRECEIVER_FUNCTIONAL_PP_V
/**
* busreceiver: Bus signal receiver.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__busreceiver (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSRECEIVER_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int n, a[100000]; long long cost, mn; int main() { cin >> n; for (int i = 0; i < n; ++i) scanf( %d , a + i); sort(a, a + n); for (int i = 0; i < n; ++i) mn += a[i] - 1; if (n > 40) return cout << mn, 0; for (int i = 2; i <= 1e5; ++i) { int k = 0; cost = 0; for (long long j = 1; j <= 1e10 && k < n; j *= i) { cost += abs(a[k++] - j); } if (k == n) mn = min(mn, cost); } cout << mn; } |
#include <bits/stdc++.h> using namespace std; int n, Mod, p[100010], a[200010], nxt[200010], w[200010], tot, root, size[100010], son[100010], cnt; bool vis[100010]; long long ans, mul[100010]; struct record { int dep, step; record(int D = 0, int S = 0) { dep = D; step = S; } } pre[100010], suf[100010]; int comp(record a, record b) { return a.dep < b.dep; } void add(int x, int y, int val) { tot++; a[tot] = y; nxt[tot] = p[x]; w[tot] = val; p[x] = tot; } void getroot(int u, int fa, int N) { size[u] = 1; son[u] = 0; for (int i = p[u]; i != 0; i = nxt[i]) if (a[i] != fa && vis[a[i]] == false) { getroot(a[i], u, N); size[u] += size[a[i]]; son[u] = max(son[u], size[a[i]]); } son[u] = max(son[u], N - size[u]); if (son[u] < son[root]) root = u; } void getdeep(int u, int fa, long long pred, int step, long long sufd) { pre[++cnt] = record(pred, step); suf[cnt] = record(sufd, step); for (int i = p[u]; i != 0; i = nxt[i]) if (a[i] != fa && vis[a[i]] == false) getdeep(a[i], u, (pred * 10 + w[i]) % Mod, step + 1, (sufd + w[i] * mul[step] % Mod) % Mod); } int findL(int l, int r, int x, record *v) { int mid; while (l != r) { mid = (l + r) >> 1; if (v[mid].dep >= x) r = mid; else l = mid + 1; } if (v[l].dep != x) return 1000000000; return l; } int findR(int l, int r, int x, record *v) { int mid, ans = 0; while (l <= r) { mid = (l + r) >> 1; if (v[mid].dep <= x) { ans = max(ans, mid); l = mid + 1; } else r = mid - 1; } if (v[ans].dep != x) return 0; return ans; } long long getnum(int l, int r, int now, record *v) { int L, R; if (l > r) return 0; L = findL(l, r, now, v); R = findR(l, r, now, v); if (L <= R) return R - L + 1; return 0; } void exgcd(int a, int b, long long &x, long long &y) { if (b == 0) { x = 1; y = 0; return; } long long t; exgcd(b, a % b, x, y); t = x; x = y; y = t - (a / b) * y; } int getinv(long long A, long long B) { long long x, y; exgcd(A, Mod, x, y); x = (x % Mod + Mod) % Mod; x = (x * B) % Mod; return x; } long long calc(int u, int pre0, int s0, int suf0) { long long sum = 0; cnt = 0; getdeep(u, 0, pre0, s0, suf0); sort(pre + 1, pre + cnt + 1, comp); sort(suf + 1, suf + cnt + 1, comp); for (int i = 1; i <= cnt; i++) { int now = getinv(mul[pre[i].step], Mod - pre[i].dep); sum += getnum(1, cnt, now, suf); if (now == 0) --sum; } return sum; } void work(int u) { ans += calc(u, 0, 0, 0); vis[u] = true; for (int i = p[u]; i != 0; i = nxt[i]) if (vis[a[i]] == false) { ans -= calc(a[i], w[i] % Mod, 1, w[i] % Mod); root = 0; getroot(a[i], 0, size[a[i]]); work(root); } } int main() { scanf( %d%d , &n, &Mod); for (int i = 1; i < n; i++) { int x, y, v; scanf( %d%d%d , &x, &y, &v); ++x; ++y; add(x, y, v); add(y, x, v); } son[0] = 1000000000; root = 0; mul[0] = 1; for (int i = 1; i <= n; i++) mul[i] = mul[i - 1] * 10 % Mod; getroot(1, 0, n); work(root); printf( %I64d n , ans); return 0; } |
#include <bits/stdc++.h> const long long inf = 1e18; using namespace std; int n; long long x[100005]; long long lb, ub, mid; long long sum, S; long long cnt[3]; int main(void) { cin >> n; for (int i = 1; i <= n; i++) cin >> x[i]; lb = inf, ub = -inf; for (int i = 1; i <= n; i++) { lb = min(lb, x[i]); ub = max(ub, x[i]); } if (ub - lb <= 1) { cout << n << endl; for (int i = 1; i <= n; i++) { cout << x[i]; if (i != n) cout << ; } cout << endl; return 0; } mid = lb + 1; for (int i = 1; i <= n; i++) { sum += x[i]; if (x[i] == lb) cnt[0]++; if (x[i] == ub) cnt[2]++; if (x[i] == mid) cnt[1]++; } S = sum - mid * n; bool flag = false; long long tmp, ans = n, ans_p; if (S < 0) S *= -1, flag = true; for (long long p = S; 2 * p <= n + S; p++) { long long m = p - S; if (flag) tmp = min(ans, min(p, cnt[0]) + min(m, cnt[2]) + min(n - p - m, cnt[1])); else tmp = min(ans, min(p, cnt[2]) + min(m, cnt[0]) + min(n - p - m, cnt[1])); if (ans > tmp) { ans = tmp; ans_p = p; } } long long ans_m = ans_p - S; if (flag) { long long t = ans_m; ans_m = ans_p; ans_p = t; } cout << ans << endl; for (int i = 1; i <= ans_p; i++) cout << ub << ; for (int i = 1; i <= ans_m; i++) cout << lb << ; for (int i = 1; i <= n - ans_p - ans_m; i++) cout << mid << ; cout << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O32A_PP_SYMBOL_V
`define SKY130_FD_SC_LS__O32A_PP_SYMBOL_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o32a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input B2 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O32A_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND4_FUNCTIONAL_V
`define SKY130_FD_SC_MS__AND4_FUNCTIONAL_V
/**
* and4: 4-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__and4 (
X,
A,
B,
C,
D
);
// Module ports
output X;
input A;
input B;
input C;
input D;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, B, C, D );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND4_FUNCTIONAL_V |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module hls_contrast_streibs_DSP48_6(
input [8 - 1:0] in0,
input [23 - 1:0] in1,
input [32 - 1:0] in2,
output [32 - 1:0] dout);
wire signed [25 - 1:0] a;
wire signed [18 - 1:0] b;
wire signed [48 - 1:0] c;
wire signed [43 - 1:0] m;
wire signed [48 - 1:0] p;
assign a = $signed(in1);
assign b = $signed(in0);
assign c = $signed(in2);
assign m = a * b;
assign p = m + c;
assign dout = p;
endmodule
`timescale 1 ns / 1 ps
module hls_contrast_streibs(
din0,
din1,
din2,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter din2_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[din2_WIDTH - 1:0] din2;
output[dout_WIDTH - 1:0] dout;
hls_contrast_streibs_DSP48_6 hls_contrast_streibs_DSP48_6_U(
.in0( din0 ),
.in1( din1 ),
.in2( din2 ),
.dout( dout ));
endmodule
|
//
// TV80 8-Bit Microprocessor Core
// Based on the VHDL T80 core by Daniel Wallner ()
//
// Copyright (c) 2004 Guy Hutchison ()
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
module tv80s (/*AUTOARG*/
// Outputs
m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n, A, dout,
// Inputs
reset_n, clk, wait_n, int_n, nmi_n, busrq_n, di
);
parameter Mode = 0; // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
parameter T2Write = 1; // 0 => wr_n active in T3, /=0 => wr_n active in T2
parameter IOWait = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle
input reset_n;
input clk;
input wait_n;
input int_n;
input nmi_n;
input busrq_n;
output m1_n;
output mreq_n;
output iorq_n;
output rd_n;
output wr_n;
output rfsh_n;
output halt_n;
output busak_n;
output [15:0] A;
input [7:0] di;
output [7:0] dout;
reg mreq_n;
reg iorq_n;
reg rd_n;
reg wr_n;
wire cen;
wire intcycle_n;
wire no_read;
wire write;
wire iorq;
reg [7:0] di_reg;
wire [6:0] mcycle;
wire [6:0] tstate;
assign cen = 1;
tv80_core #(Mode, IOWait) i_tv80_core
(
.cen (cen),
.m1_n (m1_n),
.iorq (iorq),
.no_read (no_read),
.write (write),
.rfsh_n (rfsh_n),
.halt_n (halt_n),
.wait_n (wait_n),
.int_n (int_n),
.nmi_n (nmi_n),
.reset_n (reset_n),
.busrq_n (busrq_n),
.busak_n (busak_n),
.clk (clk),
.IntE (),
.stop (),
.A (A),
.dinst (di),
.di (di_reg),
.dout (dout),
.mc (mcycle),
.ts (tstate),
.intcycle_n (intcycle_n)
);
always @(posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
rd_n <= #1 1'b1;
wr_n <= #1 1'b1;
iorq_n <= #1 1'b1;
mreq_n <= #1 1'b1;
di_reg <= #1 0;
end
else
begin
rd_n <= #1 1'b1;
wr_n <= #1 1'b1;
iorq_n <= #1 1'b1;
mreq_n <= #1 1'b1;
if (mcycle[0])
begin
if (tstate[1] || (tstate[2] && wait_n == 1'b0))
begin
rd_n <= #1 ~ intcycle_n;
mreq_n <= #1 ~ intcycle_n;
iorq_n <= #1 intcycle_n;
end
`ifdef TV80_REFRESH
if (tstate[3])
mreq_n <= #1 1'b0;
`endif
end // if (mcycle[0])
else
begin
if ((tstate[1] || (tstate[2] && wait_n == 1'b0)) && no_read == 1'b0 && write == 1'b0)
begin
rd_n <= #1 1'b0;
iorq_n <= #1 ~ iorq;
mreq_n <= #1 iorq;
end
if (T2Write == 0)
begin
if (tstate[2] && write == 1'b1)
begin
wr_n <= #1 1'b0;
iorq_n <= #1 ~ iorq;
mreq_n <= #1 iorq;
end
end
else
begin
if ((tstate[1] || (tstate[2] && wait_n == 1'b0)) && write == 1'b1)
begin
wr_n <= #1 1'b0;
iorq_n <= #1 ~ iorq;
mreq_n <= #1 iorq;
end
end // else: !if(T2write == 0)
end // else: !if(mcycle[0])
if (tstate[2] && wait_n == 1'b1)
di_reg <= #1 di;
end // else: !if(!reset_n)
end // always @ (posedge clk or negedge reset_n)
endmodule // t80s
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O31AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__O31AI_FUNCTIONAL_PP_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o31ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O31AI_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; string s; cin >> s; string temp = s; sort(s.begin(), s.end()); int count = 0; for (int i = 0; i < s.size(); i++) if (s[i] != temp[i]) count++; cout << count << n ; } } |
#include <bits/stdc++.h> using namespace std; int main() { int a[21], n; cin >> a[0] >> a[1] >> n; for (int i = 2; i <= n; i++) a[i] = a[i - 1] + a[i - 2]; cout << a[n]; return 0; } |
// -*- Mode: Verilog -*-
// Filename : gpio_bit.v
// Description : A single GPIO bit
// Author : Philip Tracton
// Created On : Sat May 23 23:15:07 2015
// Last Modified By: Philip Tracton
// Last Modified On: Sat May 23 23:15:07 2015
// Update Count : 0
// Status : Unknown, Use with caution!
module gpio_bit (/*AUTOARG*/
// Outputs
gpio_data_in,
// Inouts
gpio,
// Inputs
clk, gpio_oen, gpio_data_out
) ;
input clk;
input gpio_oen;
input gpio_data_out;
output gpio_data_in;
inout gpio;
wire gpio_data_in;
wire temp;
//
// If gpio_oen (Output ENable) is high, drive the
// GPIO pin with the data from the CPU
//
assign gpio = (gpio_oen) ? gpio_data_out : 1'bz;
//
// If gpio_oen (Output ENable) is low, sample the input
// from the GPIO on every clock edge and send back to CPU
//
assign gpio_data_in = (!gpio_oen) ? gpio : 1'bz;
/* -----\/----- EXCLUDED -----\/-----
IOBUF IOBUF_inst (
.O(gpio_data_in), // Buffer output
.IO(gpio), // Buffer inout port (connect directly to top-level port)
.I(gpio_data_out), // Buffer input
.T(~gpio_oen) // 3-state enable input, high=input, low=output
);
-----/\----- EXCLUDED -----/\----- */
endmodule // gpio_bit
|
`include "adder_subtractor.v"
`include "flag.v"
`include "mux2_1.sv"
`include "adder16b.v"
`include "adder4b.v"
`include "fullAdder1b.v"
`include "lookAhead4b.v"
`include "subtract.v"
`include "setLT.v"
module setLTtest ();
// localize variables
wire [31:0] busADD;
wire [31:0] busA, busB;
// declare an instance of the module
setLT setLT (busADD, busA, busB);
// Running the GUI part of simulation
setLTtester tester (busADD, busA, busB);
// file for gtkwave
initial
begin
$dumpfile("setLTtest.vcd");
$dumpvars(1, setLT);
end
endmodule
module setLTtester (busADD, busA, busB);
input [31:0] busADD;
output reg [31:0] busA, busB;
parameter d = 20;
initial // Response
begin
$display("busADD \t busA \t busB \t\t\t ");
#d;
end
reg [31:0] i;
initial // Stimulus
begin
$monitor("%b \t %b \t %b \t ", busADD, busA, busB, $time);
// positive + positive
busA = 32'h01010101; busB = 32'h01010101;
#d;
busA = 32'h7FFFFFFF; busB = 32'h7FFFFFFF; // should overflow
#d;
// positive + negative
busA = 32'h01010101; busB = 32'hFFFFFFFF; // 01010101 + -1
#d;
busA = 32'h00000001; busB = 32'hF0000000;
#d;
// negative + positive
busA = 32'hFFFFFFFF; busB = 32'h01010101;
#d;
busA = 32'hF0000000; busB = 32'h00000001;
#d;
// negative + negative
busA = 32'hFFFFFFFF; busB = 32'hFFFFFFFF; // -1 + -1
#d;
busA = 32'h90000000; busB = 32'h80000000; // should overflow
#d;
#(3*d);
$stop;
$finish;
end
endmodule |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> v(n + 1, 0); vector<vector<int> > g(n + 1); int i, j, k; for (i = 1; i <= n; i++) { cin >> j >> k; v[i] = k; if (j != -1) { g[j].push_back(i); } } vector<int> ans; for (i = 1; i <= n; i++) { if (v[i] == 1) { int kk = 1; for (j = 0; j < g[i].size(); j++) { if (v[g[i][j]] == 0) kk = 0; } if (kk) ans.push_back(i); } } sort(ans.begin(), ans.end()); for (i = 0; i < ans.size(); i++) cout << ans[i] << ; if (ans.size() == 0) cout << -1; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:15:51 10/19/2015
// Design Name:
// Module Name: UART_TestModule
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module UART_TestModule(
input test_rx, // al tx de la compu
input clock, // clock de la placa a 50Mhz
output test_tx // al rx de la compu
);
wire [7:0] rcvd_data, // dato a la salida del receptor
get_data_fifo; // dato a la salida de la fifo
wire rx_done,
baud_rate, // clock a 9600 baudios
tx_start, // trabaja por lógica negativa
tx_done,
empty_fifo,
full_fifo;
reg reset;
UART_baud_rate_generator BRG(
.clock(clock),
.baud_rate_clock(baud_rate)
);
UART_rx RX(
.rx(test_rx),
.s_tick(baud_rate),
.reset(reset),
.clock(clock),
.rx_done(rx_done),
.d_out(rcvd_data)
);
UART_fifo_interface FIFO_BUFFER(
.write_flag(rx_done),
.read_flag(tx_start),
.data_in(rcvd_data),
.clock(clock),
.reset(reset),
.data_out(get_data_fifo),
.empty_flag(empty_fifo),
.full_flag(full_fifo)
);
UART_tx TX(
.clock(clock),
.data_in(get_data_fifo),
.tx_start(tx_start),
.reset(reset),
.tx_done(tx_done),
.tx(test_tx)
);
assign tx_start = rx_done;
initial begin
reset = 1;
#1;
reset = 0;
end
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:20000000 ) using namespace std; int ri() { int x; scanf( %d , &x); return x; } long long rll() { long long x; scanf( %lld , &x); return x; } int mas[200500]; int tmas[200500]; int d1[100500]; int d2[100500]; int cnt[200500]; int p1[200500]; int p2[200500]; int c[20][200500]; void suffArray(int n) { for (int i = (int)(0); i <= (int)(n - 1); i++) cnt[mas[i]]++; for (int i = (int)(1); i <= (int)(200499); i++) cnt[i] += cnt[i - 1]; for (int i = (int)(0); i <= (int)(n - 1); i++) p1[--cnt[mas[i]]] = i; c[0][p1[0]] = 0; int cl = 0; for (int i = (int)(1); i <= (int)(n - 1); i++) { if (mas[p1[i]] != mas[p1[i - 1]]) cl++; c[0][p1[i]] = cl; } for (int mid = 1, step = 0; mid < n; mid <<= 1, step++) { for (int i = (int)(0); i <= (int)(cl); i++) cnt[i] = 0; for (int i = (int)(0); i <= (int)(n - 1); i++) p2[i] = (p1[i] - mid + n + n) % n; for (int i = (int)(0); i <= (int)(n - 1); i++) cnt[c[step][p2[i]]]++; for (int i = (int)(1); i <= (int)(cl); i++) cnt[i] += cnt[i - 1]; for (int i = (int)(n - 1); i >= (int)(0); i--) p1[--cnt[c[step][p2[i]]]] = p2[i]; c[step + 1][p1[0]] = 0; cl = 0; for (int i = (int)(1); i <= (int)(n - 1); i++) { int a = (p1[i] + mid) % n; int b = (p1[i - 1] + mid) % n; if (c[step][p1[i]] != c[step][p1[i - 1]] || c[step][a] != c[step][b]) cl++; c[step + 1][p1[i]] = cl; } } } int getLCP(int a, int b, int mx) { int res = 0; int m = min(mx - a, mx - b); int L = 0; while ((1 << L) <= m) L++; L--; for (int i = (int)(L); i >= (int)(0); i--) if (c[i][a] == c[i][b]) { res += (1 << i); a += (1 << i); b += (1 << i); a %= mx; b %= mx; } return min(res, mx); } int posD1[100500]; vector<int> tree[8 * 100500]; int N; void build(int v, int l, int r) { if (l == r) { if (p1[l] >= N) tree[v].push_back(p1[l] - N); return; } int mid = (l + r) >> 1; build(2 * v, l, mid); build(2 * v + 1, mid + 1, r); tree[v].resize(tree[2 * v].size() + tree[2 * v + 1].size()); merge(tree[2 * v].begin(), tree[2 * v].end(), tree[2 * v + 1].begin(), tree[2 * v + 1].end(), tree[v].begin()); } int get(int v, int l, int r, int L, int R, int h1, int h2) { if (l == L && r == R) { if (tree[v].empty()) return 0; int res = 0; int tl = 0, tr = tree[v].size(); if (tree[v][0] <= h2) { while (tl + 1 < tr) { int mid = (tl + tr) >> 1; if (tree[v][mid] <= h2) tl = mid; else tr = mid; } res += tl + 1; } tl = 0, tr = tree[v].size(); if (tree[v][0] < h1) { while (tl + 1 < tr) { int mid = (tl + tr) >> 1; if (tree[v][mid] < h1) tl = mid; else tr = mid; } res -= tl + 1; } return res; } int mid = (l + r) >> 1; if (R <= mid) return get(2 * v, l, mid, L, R, h1, h2); if (L > mid) return get(2 * v + 1, mid + 1, r, L, R, h1, h2); return get(2 * v, l, mid, L, mid, h1, h2) + get(2 * v + 1, mid + 1, r, mid + 1, R, h1, h2); } void solve() { int n = ri(); for (int i = (int)(1); i <= (int)(n); i++) mas[i] = ri(); for (int i = (int)(1); i <= (int)(n - 1); i++) d1[i] = mas[i] - mas[i + 1], d2[i] = -d1[i]; for (int i = (int)(0); i <= (int)(n - 2); i++) mas[i] = d1[i + 1]; mas[n - 1] = 2000000000; for (int i = (int)(0); i <= (int)(n - 2); i++) mas[i + n] = d2[i + 1]; mas[2 * n - 1] = 2000000001; memcpy(tmas, mas, sizeof(mas)); sort(tmas, tmas + 2 * n); map<int, int> index; int cn = 0; for (int i = (int)(0); i <= (int)(2 * n - 1); i++) if (i == 0) index[tmas[i]] = cn++; else if (tmas[i] != tmas[i - 1]) index[tmas[i]] = cn++; for (int i = (int)(0); i <= (int)(2 * n - 1); i++) mas[i] = index[mas[i]]; suffArray(n + n); for (int i = (int)(0); i <= (int)(2 * n - 1); i++) if (p1[i] <= n - 2) posD1[p1[i]] = i; N = n; build(1, 0, 2 * n - 1); int q = ri(); for (int i = (int)(0); i <= (int)(q - 1); i++) { int L = ri() - 1, R = ri() - 1; int pos = posD1[L]; int lb = pos, rb = pos; int l = -1, r = pos; while (l + 1 < r) { int mid = (l + r) >> 1; if (getLCP(p1[mid], p1[pos], 2 * n) >= R - L) r = mid; else l = mid; } lb = r; l = pos, r = 2 * n; while (l + 1 < r) { int mid = (l + r) >> 1; if (getLCP(p1[pos], p1[mid], 2 * n) >= R - L) l = mid; else r = mid; } rb = l; int res = 0; if (L == R) res = n - 1; else { int tl = L, tr = R; if (tl - tr + tl - 1 >= 0) res += get(1, 0, 2 * n - 1, lb, rb, 0, tl - tr + tl - 1); if (tr + 1 <= n - 1) res += get(1, 0, 2 * n - 1, lb, rb, tr + 1, n - 1); } printf( %d n , res); } } int main() { solve(); return 0; } |
#include <bits/stdc++.h> std::string colors( RGBYW ); struct Card { int color; int number; bool operator<(const Card& rhs) const { if (color == rhs.color) return (number < rhs.number); else return color < rhs.color; } }; int mapColor(char color) { size_t pos = colors.find_first_of(color); if (pos != std::string::npos) { return pos; } return -1; } bool isNumberHinted(int number, long long hint) { long long mask = (1 << number) << 5; return hint & mask; } bool isColorHinted(int color, long long hint) { long long mask = (1 << color); return hint & mask; } int bitCount(long long n) { int count = 0; while (n > 0) { count++; n = n & (n - 1); } return count; } void codeforces442a() { int n = 0; int minAns = 10; std::cin >> n; std::set<Card> cards; for (int i = 0; i < n; ++i) { Card card; char color; char number; std::cin >> color; std::cin >> number; card.color = mapColor(color); card.number = number - 1 ; cards.insert(card); } if (cards.size() == 1) { std::cout << 0 ; return; } for (long long hint = 0; hint < (1 << 10); ++hint) { if (bitCount(hint) >= minAns) continue; bool isValid = true; for (std::set<Card>::iterator i = cards.begin(); i != cards.end() && isValid; ++i) for (std::set<Card>::iterator j = cards.begin(); j != cards.end() && isValid; ++j) { if (i != j) { bool areHintedAsDifferent = false; Card firstCard = *i; Card secondCard = *j; if (firstCard.color == secondCard.color) { areHintedAsDifferent = isNumberHinted(firstCard.number, hint) || isNumberHinted(secondCard.number, hint); } else if (firstCard.number == secondCard.number) { areHintedAsDifferent = isColorHinted(firstCard.color, hint) || isColorHinted(secondCard.color, hint); } else { areHintedAsDifferent = isNumberHinted(firstCard.number, hint) || isNumberHinted(secondCard.number, hint) || isColorHinted(firstCard.color, hint) || isColorHinted(secondCard.color, hint); } if (!areHintedAsDifferent) { isValid = false; } } } if (isValid) { int numHints = bitCount(hint); if (minAns > numHints) { minAns = numHints; } } } std::cout << minAns; } int main() { codeforces442a(); return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, u, r; long long a[40], b[40], k[40], p[40]; long long maxx = (long long)1 << 63; long long eval() { long long val = 0; for (int i = 0; i < n; i++) { val += a[i] * k[i]; } return val; } void gen(int now, int last) { if (now % 2 == u % 2) maxx = max(maxx, eval()); if (now < u) { long long temp[40]; memcpy(temp, a, sizeof(a)); if (last == 1) { for (int i = 0; i < n; i++) { a[i] = temp[i] ^ b[i]; } gen(now + 1, 0); } for (int i = 0; i < n; i++) { a[i] = temp[p[i]] + r; } gen(now + 1, 1); } } int main() { cin >> n >> u >> r; for (int i = 0; i < n; i++) { cin >> a[i]; } for (int i = 0; i < n; i++) { cin >> b[i]; } for (int i = 0; i < n; i++) { cin >> k[i]; } for (int i = 0; i < n; i++) { cin >> p[i]; p[i]--; } gen(0, 1); cout << maxx << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int a; cin >> a; long long arr[36] = { 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8092, 16184, 32368, 64736, 129472, 258944, 517888, 1035776, 2071552, 4143104, 8286208, 16572416, 33144832, 66289664, 132579328, 265158656, 530317312, 1060634624, 2121269248, 4242538496, 8485076992, 16970153984, 33940307968}; cout << arr[a]; return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 1000 * 1000 * 1000; const double PI = acos(-1.0); const int MAX = 150005; int n, len, h; pair<int, int> a[MAX]; int b[MAX]; pair<int, int> T[MAX * 8]; int lazy[MAX * 8]; bool pzdc[MAX]; void push(int v) { T[v].first += lazy[v]; lazy[v * 2] += lazy[v]; lazy[v * 2 + 1] += lazy[v]; lazy[v] = 0; } void upd(int v, int tl, int tr, int l, int r, int delta) { push(v); if (l > r) return; if (tl == l && tr == r) { lazy[v] += delta; push(v); return; } int tm = (tl + tr) / 2; upd(v * 2, tl, tm, l, min(r, tm), delta); upd(v * 2 + 1, tm + 1, tr, max(l, tm + 1), r, delta); T[v] = min(T[v * 2], T[v * 2 + 1]); } void build(int v, int tl, int tr) { if (tl == tr) { T[v].second = tl; return; } int tm = (tl + tr) / 2; build(v * 2, tl, tm); build(v * 2 + 1, tm + 1, tr); T[v] = min(T[v * 2], T[v * 2 + 1]); } int main() { ios_base::sync_with_stdio(0); cin >> n >> len >> h; build(1, 0, n - len); for (int i = 0; i < len; i++) cin >> b[i]; sort(b, b + len); for (int i = 0; i < n; i++) { cin >> a[i].first; a[i].second = i; } sort(a, a + n); int ptr = n - 1; for (int i = 0; i < len; i++) { while (ptr >= 0 && a[ptr].first + b[i] >= h) { upd(1, 0, n - len, max(0, a[ptr].second - len + 1), min(n - len, a[ptr].second), 1); ptr--; } while (T[1].first <= i) { pzdc[T[1].second] = 1; upd(1, 0, n - len, T[1].second, T[1].second, INF); } } int ans = 0; for (int i = 0; i < n - len + 1; i++) ans += !pzdc[i]; cout << ans; } |
#include <bits/stdc++.h> using namespace std; const int prime[15] = {2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47}; int main() { int n; cin >> n; vector<int> res; int limit = 2 * n * n; for (int i = 0; i < 15; i++) { res.clear(); res.push_back(1); for (int j = 0; j <= i; j++) { int p = prime[j]; int sz = res.size(); for (int k = 0; k < sz; k++) { int x = res[k]; while (x * p <= limit) { x *= p; res.push_back(x); } } } if (res.size() >= n) { break; } } sort(res.begin(), res.end(), greater<int>()); for (int i = 0; i < n; i++) { cout << res[i] << ; } } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// parameters for array sizes
localparam WA = 4;
localparam WB = 6;
localparam WC = 8;
// 2D packed arrays
logic [WA-1:0] [WB-1:0] [WC-1:0] array_bg; // big endian array
/* verilator lint_off LITENDIAN */
logic [0:WA-1] [0:WB-1] [0:WC-1] array_lt; // little endian array
/* verilator lint_on LITENDIAN */
integer cnt = 0;
integer slc = 0; // slice type
integer dim = 0; // dimension
integer wdt = 0; // width
// event counter
always @ (posedge clk) begin
cnt <= cnt + 1;
end
// finish report
always @ (posedge clk)
if ( (cnt[30:4]==3) && (cnt[3:2]==2'd3) && (cnt[1:0]==2'd3) ) begin
$write("*-* All Finished *-*\n");
$finish;
end
// calculation of dimention sizes
always @ (posedge clk)
begin
// slicing tipe counter
case (cnt[3:2])
2'd0 : begin slc = 0; end // full array
2'd1 : begin slc = 1; end // half array
2'd2 : begin slc = 2; end // single array element
default: begin slc = 0; end
endcase
// dimmension counter
case (cnt[1:0])
2'd0 : begin dim = 1; wdt = (slc==1) ? WA/2
: (slc==2) ? 1
: WA; end
2'd1 : begin dim = 2; wdt = WB; end
2'd2 : begin dim = 3; wdt = WC; end
default: begin dim = 0; wdt = 0; end
endcase
end
always @ (posedge clk)
if (cnt[30:4]==1) begin
// big endian
if (cnt[3:2]==0) begin
// full array
if ($dimensions (array_bg) != 3) $stop;
if ($bits (array_bg) != WA*WB*WC) $stop;
if ((dim>=1)&&(dim<=3)) begin
if ($left (array_bg, dim) != wdt-1) $stop;
if ($right (array_bg, dim) != 0 ) $stop;
if ($low (array_bg, dim) != 0 ) $stop;
if ($high (array_bg, dim) != wdt-1) $stop;
if ($increment (array_bg, dim) != 1 ) $stop;
if ($size (array_bg, dim) != wdt ) $stop;
end
end else if (cnt[3:2]==1) begin
// half array
if ($dimensions (array_bg[WA/2-1:0]) != 3) $stop;
if ($bits (array_bg[WA/2-1:0]) != WA/2*WB*WC) $stop;
if ((dim>=1)&&(dim<=3)) begin
if ($left (array_bg[WA/2-1:0], dim) != wdt-1) $stop;
if ($right (array_bg[WA/2-1:0], dim) != 0 ) $stop;
if ($low (array_bg[WA/2-1:0], dim) != 0 ) $stop;
if ($high (array_bg[WA/2-1:0], dim) != wdt-1) $stop;
if ($increment (array_bg[WA/2-1:0], dim) != 1 ) $stop;
if ($size (array_bg[WA/2-1:0], dim) != wdt ) $stop;
end
end else if (cnt[3:2]==2) begin
// single array element
if ($dimensions (array_bg[0]) != 2) $stop;
if ($bits (array_bg[0]) != WB*WC) $stop;
if ((dim>=2)&&(dim<=3)) begin
if ($left (array_bg[0], dim-1) != wdt-1) $stop;
if ($right (array_bg[0], dim-1) != 0 ) $stop;
if ($low (array_bg[0], dim-1) != 0 ) $stop;
if ($high (array_bg[0], dim-1) != wdt-1) $stop;
if ($increment (array_bg[0], dim-1) != 1 ) $stop;
if ($size (array_bg[0], dim-1) != wdt ) $stop;
end
end
end else if (cnt[30:4]==2) begin
// little endian
if (cnt[3:2]==0) begin
// full array
if ($dimensions (array_lt) != 3) $stop;
if ($bits (array_lt) != WA*WB*WC) $stop;
if ((dim>=1)&&(dim<=3)) begin
if ($left (array_lt, dim) != 0 ) $stop;
if ($right (array_lt, dim) != wdt-1) $stop;
if ($low (array_lt, dim) != 0 ) $stop;
if ($high (array_lt, dim) != wdt-1) $stop;
if ($increment (array_lt, dim) != -1 ) $stop;
if ($size (array_lt, dim) != wdt ) $stop;
end
end else if (cnt[3:2]==1) begin
// half array
if ($dimensions (array_lt[0:WA/2-1]) != 3) $stop;
if ($bits (array_lt[0:WA/2-1]) != WA/2*WB*WC) $stop;
if ((dim>=1)&&(dim<=3)) begin
if ($left (array_lt[0:WA/2-1], dim) != 0 ) $stop;
if ($right (array_lt[0:WA/2-1], dim) != wdt-1) $stop;
if ($low (array_lt[0:WA/2-1], dim) != 0 ) $stop;
if ($high (array_lt[0:WA/2-1], dim) != wdt-1) $stop;
if ($increment (array_lt[0:WA/2-1], dim) != -1 ) $stop;
if ($size (array_lt[0:WA/2-1], dim) != wdt ) $stop;
end
end else if (cnt[3:2]==2) begin
// single array element
if ($dimensions (array_lt[0]) != 2) $stop;
if ($bits (array_lt[0]) != WB*WC) $stop;
if ((dim>=2)&&(dim<=3)) begin
if ($left (array_lt[0], dim-1) != 0 ) $stop;
if ($right (array_lt[0], dim-1) != wdt-1) $stop;
if ($low (array_lt[0], dim-1) != 0 ) $stop;
if ($high (array_lt[0], dim-1) != wdt-1) $stop;
if ($increment (array_lt[0], dim-1) != -1 ) $stop;
if ($size (array_lt[0], dim-1) != wdt ) $stop;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; pair<int, int> a[2][100010]; bool used[100010]; int fat[100010]; int main() { int i, j, c, v; scanf( %d , &n); for (i = 1; i <= n; i++) { scanf( %d %d , &c, &v); a[c][++a[c][0].first] = make_pair(v, i); } sort(a[0] + 1, a[0] + a[0][0].first + 1); sort(a[1] + 1, a[1] + a[1][0].first + 1); i = j = 1; for (int t = 1; t < n; t++) { int tmp = min(a[0][i].first, a[1][j].first); printf( %d %d %d n , a[0][i].second, a[1][j].second, tmp); a[0][i].first -= tmp, a[1][j].first -= tmp; if (a[0][i].first) j++; else if (a[1][j].first) i++; else if (i < a[0][0].first) i++; else j++; } return 0; } |
`timescale 1ns / 1ps
//this code was generated by cReComp
module sensor_ctl(
input clk,
input rst_32,
input [31:0] din_32,
input [0:0] wr_en_32,
input [0:0] rd_en_32,
output [31:0] dout_32,
output [0:0] full_32,
output [0:0] empty_32,
inout [0:0] sig,
output [3:0] led
);
// //copy this instance to top module
//sensor_ctl sensor_ctl
//(
//.clk(bus_clk),
//.rst_32(!user_w_write_32_open && !user_r_read_32_open),
//.din_32(user_w_write_32_data),
//.wr_en_32(user_w_write_32_wren),
//.rd_en_32(user_r_read_32_rden),
//.dout_32(user_r_read_32_data),
//.full_32(user_w_write_32_full),
//.empty_32(user_r_read_32_empty),
//
// .sig(sig),
// .out_data(out_data),
// .led(led)
//);
parameter INIT_32 = 0,
READY_RCV_32 = 1,
RCV_DATA_32 = 2,
POSE_32 = 3,
READY_SND_32 = 4,
SND_DATA_32 = 5;
// for input fifo
wire [31:0] rcv_data_32;
wire rcv_en_32;
wire data_empty_32;
// for output fifo
wire [31:0] snd_data_32;
wire snd_en_32;
wire data_full_32;
// state register
reg [3:0] state_32;
reg req_sonic_sensor;
wire busy_sonic_sensor;
reg finish_sonic_sensor;
////fifo 32bit
fifo_32x512 input_fifo_32(
.clk(clk),
.srst(rst_32),
.din(din_32),
.wr_en(wr_en_32),
.full(full_32),
.dout(rcv_data_32),
.rd_en(rcv_en_32),
.empty(data_empty_32)
);
fifo_32x512 output_fifo_32(
.clk(clk),
.srst(rst_32),
.din(snd_data_32),
.wr_en(snd_en_32),
.full(data_full_32),
.dout(dout_32),
.rd_en(rd_en_32),
.empty(empty_32)
);
//for 32bit FIFO;
wire [31:0] out_data;
//instance for sonic_sensor
sonic_sensor sonic_sensor
(
.clk(clk),
.rst(rst_32),
.req(req_sonic_sensor),
.busy(busy_sonic_sensor),
.sig(sig),
.out_data(out_data),
.led(led)
);
always @(posedge clk)begin
if(rst_32)
state_32 <= 0;
else
case (state_32)
INIT_32: state_32 <= READY_RCV_32;
READY_RCV_32: if(1) state_32 <= RCV_DATA_32;
RCV_DATA_32: state_32 <= POSE_32;
POSE_32: if(hs_state == DONE) state_32 <= READY_SND_32;
READY_SND_32: if(data_full_32 == 0) state_32 <= SND_DATA_32;
SND_DATA_32: state_32 <= READY_RCV_32;
endcase
end
assign rcv_en_32 = (state_32 == RCV_DATA_32);
assign snd_en_32 = (state_32 == SND_DATA_32);
/*user assign*/
assign snd_data_32[31:0] = out_data;
reg [3:0] hs_state;
parameter INIT = 0,
IDLE = 1,
START = 2,
PROCESSING = 3,
DONE = 4;
always @(posedge clk) begin
if (rst_32) begin
req_sonic_sensor <= 0;
finish_sonic_sensor <= 0;
hs_state <= 0;
end
else
case (hs_state)
INIT: hs_state <= IDLE;
IDLE: hs_state <= START;
START:begin
if(busy_sonic_sensor == 0 && state_32 == POSE_32)begin
req_sonic_sensor <= 1;
hs_state <= PROCESSING;
end
end
PROCESSING:begin
req_sonic_sensor <= 0;
if(busy_sonic_sensor == 0)begin
hs_state <= DONE;
end
end
DONE: hs_state <= IDLE;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int P = 10, N = 1e5 + 10; inline int inverse(int a, int m) { if (a <= 1) return a; int ans = (1 - (long long int)inverse(m % a, a) * m) / a; return ans + m; } int fact[N], ifact[N], pot[N][P]; int sz, p[P]; inline void primes(int n) { for (int d = 2; d * d <= n; d++) if (n % d == 0) { p[sz++] = d; while (n % d == 0) n /= d; } if (n > 1) p[sz++] = n; } int mod; int expo[P][N]; inline int comb(int m, int n) { int ans = (long long int)fact[m] * ifact[n] % mod * ifact[m - n] % mod; for (register int i = 0; i < (int)(sz); ++i) { int pp = pot[m][i] - pot[n][i] - pot[m - n][i]; if (pp) ans = (long long int)ans * expo[i][pp] % mod; } return ans; } inline int go(int n, int bal) { long long int ans = 0; for (register int x = 0, y = bal; x + y <= n; ++x, ++y) ans += (long long int)comb(n, x) * comb(n - x, y) % mod; return ans % mod; } int main() { int n, l, r; cin >> n >> mod >> l >> r; primes(mod); fact[0] = ifact[0] = 1; int fn = 1; for (register int j = 0; j < (int)(sz); ++j) expo[j][0] = 1; for (int i = 1; i <= n; i++) { int d = -1; for (register int j = 0; j < (int)(sz); ++j) if (i % p[j] == 0) { d = j; break; } if (d == -1) fact[i] = i; else { fact[i] = fact[i / p[d]]; for (register int j = 0; j < (int)(sz); ++j) pot[i][j] = pot[i / p[d]][j] + (j == d); } fn = (long long int)fn * fact[i] % mod; for (register int j = 0; j < (int)(sz); ++j) expo[j][i] = (long long int)expo[j][i - 1] * p[j] % mod; } ifact[n] = inverse(fn, mod); for (register int i = n - 1; i >= 0; --i) ifact[i] = (long long int)ifact[i + 1] * fact[i + 1] % mod; for (register int i = 1; i <= n; ++i) { fact[i] = (long long int)fact[i - 1] * fact[i] % mod; for (register int j = 0; j < (int)(sz); ++j) pot[i][j] += pot[i - 1][j]; } long long int ans = 0; for (register int i = 0; i < (int)(2); ++i) ans += (long long int)go(n, l + i) + mod - go(n, r + 1 + i); cout << ans % mod << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const int MAXN = 1000005; long long f[5010][5]; int _prev[5010][5], n; int a[MAXN]; long long sum[MAXN]; int main() { scanf( %d , &n); for (int i = (1); i < (n + 1); i++) scanf( %d , a + i); for (int i = (1); i < (n + 1); i++) sum[i] = sum[i - 1] + a[i]; for (int i = (1); i < (n + 1); i++) for (int j = (0); j < (4); j++) { if (j == 0) f[i][j] = sum[i]; else { f[i][j] = 1ll << 63; for (int k = (0); k < (i + 1); k++) { if (j & 1 && f[i][j] < f[k][j - 1] - sum[i] + sum[k]) _prev[i][j] = k, f[i][j] = f[k][j - 1] - sum[i] + sum[k]; if (!(j & 1) && f[i][j] < f[k][j - 1] + sum[i] - sum[k]) _prev[i][j] = k, f[i][j] = f[k][j - 1] + sum[i] - sum[k]; } } } long long ans = 1ll << 63, t; stack<int> res; for (int k = (0); k < (4); k++) if (ans <= f[n][k]) ans = f[n][k], t = k; int now = n; while (t) { now = _prev[now][t]; res.push(now); t--; } for (int i = (0); i < (3); i++) { if (res.empty()) printf( %d , n); else printf( %d , res.top()), res.pop(); } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long INF = 1e17 + 7; const long long maxn = 5e5 + 700; const int mod = 998244353; const int up = 1e9; template <typename T> inline void read(T &a) { char c = getchar(); T x = 0, f = 1; while (!isdigit(c)) { if (c == - ) f = -1; c = getchar(); } while (isdigit(c)) { x = (x << 1) + (x << 3) + c - 0 ; c = getchar(); } a = f * x; } long long n, m, p; int num[maxn], b[maxn]; struct Dinic { long long cnt = 2; struct Edge { int e, next; long long w; }; int _S, _T, N; int head[maxn], d[maxn], cur[maxn]; Edge edge[maxn]; void _inint(int s, int t, int n) { memset(head, 0, sizeof(head)); cnt = 2; _S = s, _T = t, N = n; } void addedge(int u, int v, long long w) { edge[cnt] = Edge{v, head[u], w}; head[u] = cnt++; } void Add(int u, int v, long long w) { addedge(u, v, w); addedge(v, u, 0); } bool bfs() { for (int k = 0; k <= N; k++) d[k] = 0; queue<int> q; q.push(_S); d[_S] = 1; while (!q.empty()) { int u = q.front(); q.pop(); for (int i = head[u]; i; i = edge[i].next) { int e = edge[i].e; if (edge[i].w <= 0 || d[e]) continue; d[e] = d[u] + 1; q.push(e); } } for (int k = 0; k <= N; k++) cur[k] = head[k]; return (d[_T] != 0); } long long dfs(int u, long long flow) { if (u == _T) return flow; for (int &i = cur[u]; i; i = edge[i].next) { int e = edge[i].e; if (d[e] != d[u] + 1 || edge[i].w <= 0) continue; long long temp = dfs(e, min(flow, edge[i].w)); if (temp <= 0) continue; edge[i].w -= temp; edge[i ^ 1].w += temp; return temp; } return 0; } long long MaxFlow() { long long maxflow = 0, delta = 0; while (bfs()) { while (delta = dfs(_S, INF)) maxflow += delta; } return maxflow; } vector<int> v[maxn]; int col[maxn]; vector<vector<int>> res; void dfs(int u, vector<int> &a) { col[u] = 1; a.push_back(u); for (int e : v[u]) { if (col[e]) continue; dfs(e, a); } } void AC() { long long temp = MaxFlow(); if (temp == N - 1) { for (int i = 1; i <= n; i++) { if (!(num[i] & 1)) continue; for (int k = head[i]; k; k = edge[k].next) { int e = edge[k].e; if (edge[k ^ 1].w) { v[e].push_back(i); v[i].push_back(e); } } } for (int i = 1; i <= n; i++) { if (!col[i]) { vector<int> temp; dfs(i, temp); res.push_back(temp); } } printf( %d n , res.size()); for (auto x : res) { printf( %d , x.size()); for (int y : x) printf( %d , y); printf( n ); } } else printf( Impossible n ); } } g; int judge(int x) { for (int i = 2; i * i <= x; i++) if (x % i == 0) return 0; return 1; } int main() { read(n); g._inint(0, n + 1, n + 1); for (int i = 1; i <= n; i++) { read(num[i]); if (num[i] & 1) g.Add(0, i, 2); else g.Add(i, n + 1, 2); } for (int i = 1; i <= n; i++) { for (int k = i + 1; k <= n; k++) { if (judge(num[i] + num[k])) { if (num[i] & 1) g.Add(i, k, 1); else g.Add(k, i, 1); } } } g.AC(); return 0; } |
#include <bits/stdc++.h> using namespace std; long long check(long long x) { long long i = 0, ans = 0; while (x > 0) { if ((x & (1)) == 1) { ans = max(ans, i); } x = x >> 1; i++; } return ans; } void solve() { long long n; cin >> n; long long a[n + 1]; map<long long, long long> mp; for (long long i = 0; i < n; i++) { cin >> a[i]; mp[check(a[i])]++; } long long ans = 0; for (auto x : mp) { if (x.second > 1) ans += ((x.second) * (x.second - 1)) / 2; } cout << ans << endl; return; } int main() { int t; cin >> t; while (t--) { solve(); } } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; if (n > m) swap(n, m); switch (n) { case 1: cout << m / 6 * 6 + 2 * max(m % 6 - 3, 0); break; case 2: switch (m) { case 2: cout << 0; break; case 3: cout << 4; break; case 7: cout << 12; break; default: cout << 2 * m; break; } break; default: cout << 1ll * n * m / 2 * 2; break; } return 0; } |
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build Thu Jun 14 20:03:12 MDT 2018
// Date : Mon Sep 16 04:58:12 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_auto_pc_0_stub.v
// Design : design_1_auto_pc_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_17_axi_protocol_converter,Vivado 2018.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awprot, m_axi_awvalid,
m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready, m_axi_bresp,
m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, m_axi_arvalid, m_axi_arready,
m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [3:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [3:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [31:0]m_axi_awaddr;
output [2:0]m_axi_awprot;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [31:0]m_axi_araddr;
output [2:0]m_axi_arprot;
output m_axi_arvalid;
input m_axi_arready;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9; const long long INFLL = 1e18 + 1; const int MAX = 100001; const long long MOD = 1000000007; const int SZ = 300100; const double PI = 3.14159265358979323846264338327; long long inq(long long k, long long q, long long mod) { if (q == 0) return 1; long long l = inq(k, q / 2, mod); if (q % 2 == 0) return l * l % mod; else return l * l % mod * k % mod; } long long gcd(long long a, long long b) { if (a < b) swap(a, b); if (b == 0) return a; return gcd(b, a % b); } long long cubr(long long a) { long long l = -1, r = 1e6 + 2; while (l < r - 1) { long long mid = (l + r) / 2; if (mid * mid * mid > a) r = mid; else l = mid; } return l; } long long max(long long a, long long b) { if (a > b) return a; return b; } long long min(long long a, long long b) { return -1 * max(-a, -b); } long long possible(long long q) { if (q == INF) return -1; return q; } bool correct(int x, int xx) { if (x < 0) return 0; if (x >= xx) return 0; return 1; } long long dsumm(long long x, long long k) { long long y = 1; long long z = 0; for (int i = 0; y < 1e18; i += 1) { z += x / y % k; y *= k; } return z; } long long dcount(long long x) { long long y = 1; long long z = 0; int c[100]; for (int i = 0; i < 10; i += 1) c[i] = 0; for (int i = 0; x > 0; i += 1) { if (c[x / y % 10] == 0) z++; c[x / y % 10] = 1; x /= 10; } return z; } long long lg10(long long x) { if (10000 <= x && x < 100000) return 5; if (x == 0) return 0; return lg10(x / 10) + 1; } long long g(long long x, long long mod) { if (x == 0) return 0; return x / mod + g(x / mod, mod); } bool is_digit(char c) { return ( 0 <= c && c <= 9 ); } string s; int n, p; int a[50][50]; int b[3000000]; int marks[(1 << 17)][20][20]; int r[3000000]; int dp[3000000]; int len[3000000]; int cnt[50]; void mark(int mask, int i, int j) { if (marks[mask][i][j] == 0) return; marks[mask][i][j] = 0; for (int k = 0; k < p; k++) { if (((1 << k) & mask) == 0 && k != i && k != j) { int m2 = (mask + (1 << k)); if (marks[m2][i][j] == 1) mark(m2, i, j); } } } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> p; cin >> s; for (int(i) = 0; (i) != (n); i += 1) b[i] = s[i] - a ; for (int(i) = 0; (i) != (n); i += 1) cnt[b[i]]++; for (int i = 0; i < p; i++) { for (int j = 0; j < p; j++) { cin >> a[i][j]; } } for (int i = 0; i < (1 << p); i++) { r[i] = 1; for (int j = 0; j < p; j++) { for (int k = 0; k < p; k++) { marks[i][j][k] = 1; } } } for (int i = 0; i < p; i++) { for (int j = 0; j < p; j++) { if (a[i][j] == 0) { long long calc = 0; long long mask = 0; for (int k = 0; k < n; k++) { if (b[k] == j) { if (calc == 1) { mark(mask, i, j); } calc = 0; mask = 0; } if (b[k] == i) { calc = 1; mask = 0; } if (b[k] != i && b[k] != j && calc == 1) mask |= (1 << b[k]); } } } } for (int i = 0; i < (1 << p); i++) { r[i] = 1; for (int j = 0; j < p; j++) { for (int k = 0; k < p; k++) { r[i] = min(r[i], marks[i][j][k]); } } } dp[0] = 1; int ans = n; for (int i = 1; i < (1 << p); i++) { for (int j = 0; j < p; j++) { if (i & (1 << j)) { int ii = i - (1 << j); if (dp[ii] && r[i]) { dp[i] = 1; int first = n; for (int k = 0; k < p; k++) { if ((1 << k) & i) { first -= cnt[k]; } } ans = min(first, ans); } } } } cout << ans; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, x, sum = 0, q; vector<int> v; vector<int>::iterator it; scanf( %d , &n); while (n--) { scanf( %d , &x); sum += x; v.push_back(sum); } int sz = v.size(); scanf( %d , &q); while (q--) { scanf( %d , &x); it = lower_bound(v.begin(), v.end(), x); printf( %d n , (it - v.begin()) + 1); } return 0; } |
#include <bits/stdc++.h> using namespace std; void c_p_c() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); } template <typename Arg1> void __f(const char* name, Arg1&& arg1) { cout << name << : << arg1 << n ; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cout.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } long long int n, m; char a[50][50]; long long int vis[50][50]; long long int cnt = 0; long long int dx[] = {1, -1, 0, 0}; long long int dy[] = {0, 0, 1, -1}; bool is_valid(long long int i, long long int j) { if (i >= 0 and j >= 0 and i < n and j < m and a[i][j] == B ) { return true; } return false; } void dfs(long long int i, long long int j, long long int dn, long long int dir) { if (vis[i][j] == 0) { vis[i][j] = 1; cnt++; } for (long long int k = 0; k < 4; k++) { long long int x = i + dx[k]; long long int y = j + dy[k]; if (is_valid(x, y)) { long long int g; long long int p; if (dir == -1) { g = 0; } if (dir != -1) { if (k == dir) { g = dn; } else { g = dn + 1; } } if (g > 1) { continue; } dfs(x, y, g, k); } } } int32_t main() { c_p_c(); cin >> n >> m; long long int k = 0; for (long long int i = 0; i < n; i++) { for (long long int j = 0; j < m; j++) { cin >> a[i][j]; if (a[i][j] == B ) { k++; } } } for (long long int i = 0; i < n; i++) { for (long long int j = 0; j < m; j++) { if (a[i][j] == B ) { memset(vis, 0, sizeof(vis)); cnt = 0; dfs(i, j, 0, -1); if (cnt != k) { cout << NO << n ; return 0; } } } } cout << YES << n ; return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:43:14 03/25/2015
// Design Name: fifo_top
// Module Name: S:/Xilinx/assignment5/fifo_top_tb.v
// Project Name: assignment5
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: fifo_top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module fifo_top_tb;
// Inputs
reg [5:0] vector_in;
reg reset;
reg clk;
// Outputs
wire [3:0] data_out;
wire empty_flag;
wire full_flag;
// Instantiate the Unit Under Test (UUT)
fifo_top fifo (
.data_out(data_out),
.empty_flag(empty_flag),
.full_flag(full_flag),
.vector_in(vector_in),
.reset(reset),
.clk(clk)
);
initial begin
// Initialize Inputs
// vector_in = 0;
clk = 1;
reset = 1;
// Wait 100 ns for global reset to finish
// #100;
// Add stimulus here
// 4 writes
#2 reset = 0; vector_in = 6'b10_1111;
#2 vector_in = 6'b10_1110;
#2 vector_in = 6'b10_1101;
#2 vector_in = 6'b10_1001;
#2 vector_in = 6'b00_1001;
// 4 reads
#2 vector_in = 6'b01_1001;
#2 vector_in = 6'b01_1001;
#2 vector_in = 6'b01_1001;
#2 vector_in = 6'b01_1001;
#2 vector_in = 6'b00_1001;
// 4 writes
#2 vector_in = 6'b10_0000;
#2 vector_in = 6'b10_0001;
#2 vector_in = 6'b10_0111;
#2 vector_in = 6'b10_0110;
#2 vector_in = 6'b00_1001;
// 4 more writes
#2 vector_in = 6'b10_0000;
#2 vector_in = 6'b10_0001;
#2 vector_in = 6'b10_0111;
#2 vector_in = 6'b10_0110;
#2 vector_in = 6'b00_1001;
// 2 writes
#2 vector_in = 6'b10_1101;
#2 vector_in = 6'b10_1001;
#2 vector_in = 6'b00_1000;
#2 $finish;
end
always
#1 clk = ~clk;
endmodule
|
// file: design_1_clk_wiz_0_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1___200.000______0.000______50.0______233.189____265.359
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________125.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "design_1_clk_wiz_0_0,clk_wiz_v5_1,{component_name=design_1_clk_wiz_0_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=PLL,num_out_clk=1,clkin1_period=8.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module design_1_clk_wiz_0_0
(
// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
// Status and control signals
input reset,
output locked
);
design_1_clk_wiz_0_0_clk_wiz inst
(
// Clock in ports
.clk_in1(clk_in1),
// Clock out ports
.clk_out1(clk_out1),
// Status and control signals
.reset(reset),
.locked(locked)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:57:12 11/07/2014
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module top(
clock,
a1,
a2,
store000_out,
store001_out,
store010_out,
store100_out,
store101_out,
store110_out,
cout1,
cout2,
cout3,
cout4,
cout5,
cout6
);
parameter NUM_BITS = 5;
//-------------------------------------------------------------------------------
input clock;
input [NUM_BITS-1:0] a1;
input [NUM_BITS-1:0] a2;
//-------------------------------------------------------------------------------
output [3:0] store000_out;
output [3:0] store001_out;
output [3:0] store010_out;
output [3:0] store100_out;
output [3:0] store101_out;
output [3:0] store110_out;
wire [3:0] store000_0;
wire [3:0] store001_0;
wire [3:0] store010_0;
wire [3:0] store100_0;
wire [3:0] store101_0;
wire [3:0] store110_0;
wire [3:0] store000_1;
wire [3:0] store001_1;
wire [3:0] store010_1;
wire [3:0] store100_1;
wire [3:0] store101_1;
wire [3:0] store110_1;
output wire [1:0] cout1;
output wire [1:0] cout2;
output wire [1:0] cout3;
output wire [1:0] cout4;
output wire [1:0] cout5;
output wire [1:0] cout6;
temp dbns1(
.clock(clock),
.a(a1),
.store000(store000_0),
.store001(store001_0),
.store010(store010_0),
.store100(store100_0),
.store101(store101_0),
.store110(store110_0)
);
temp dbns2(
.clock(clock),
.a(a2),
.store000(store000_1),
.store001(store001_1),
.store010(store010_1),
.store100(store100_1),
.store101(store101_1),
.store110(store110_1)
);
addititon addn_1(
.store000_0(store000_0),
.store001_0(store001_0),
.store010_0(store010_0),
.store100_0(store100_0),
.store101_0(store101_0),
.store110_0(store110_0),
.store000_1(store000_1),
.store001_1(store001_1),
.store010_1(store010_1),
.store100_1(store100_1),
.store101_1(store101_1),
.store110_1(store110_1),
.clock(clock),
.store000_0_out(store000_out),
.store001_0_out(store001_out),
.store010_0_out(store010_out),
.store100_0_out(store100_out),
.store101_0_out(store101_out),
.store110_0_out(store110_out),
.cout1(cout1),
.cout2(cout2),
.cout3(cout3),
.cout4(cout4),
.cout5(cout5),
.cout6(cout6)
);
//reg final_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; const int MAX = 2e5 + 5; long long dis[MAX]; int a[MAX], ans[MAX]; int pos[MAX]; vector<pair<int, int> > adj[MAX]; void dfs(int x, int idx, long long d) { pos[idx] = x; dis[idx] = d; int len = lower_bound(dis, dis + idx + 1, d - a[x]) - dis - 1; ans[pos[len]]--; ans[x]++; for (int i = 0; i < ((int)(adj[x]).size()); i += 1) { dfs(adj[x][i].first, idx + 1, d + adj[x][i].second); ans[x] += ans[adj[x][i].first]; } } int main(int argc, char* argv[]) { if (argc == 2 or argc == 3) freopen(argv[1], r , stdin); if (argc == 3) freopen(argv[2], w , stdout); ios::sync_with_stdio(false); int n, p, w; cin >> n; for (int i = 1; i < n + 1; i += 1) { cin >> a[i]; } for (int i = 2; i < n + 1; i += 1) { cin >> p >> w; adj[p].push_back(make_pair(i, w)); } dis[0] = -1; dfs(1, 1, 0); for (int i = 1; i < n + 1; i += 1) if (i == 1) cout << ans[i] - 1; else cout << << ans[i] - 1; cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; while (cin >> n) { string s; cin >> s; int l[3005], r[3005]; memset(l, -1, sizeof(l)); memset(r, -1, sizeof(r)); int cnt = 0, t1 = 0, t2 = 0; for (int i = 0; i < n; ++i) { if (s[i] == L ) { l[t1++] = i; continue; } if (s[i] == R ) { r[t2++] = i; continue; } } if (l[0] == r[0]) { cout << n << endl; continue; } if (l[0] == -1) { cout << r[0] << endl; continue; } if (r[0] == -1) { cout << n - l[0] - 1 << endl; continue; } if (l[0] < r[0]) { cnt += l[0] + 1; for (int i = 1; i < t1; ++i) { int t = l[i] - r[i - 1]; cnt += t + 1; if (t % 2 == 0) cnt--; } if (t1 == t2) cnt += n - r[t2 - 1]; } else { for (int i = 0; i < t1; ++i) { int t = l[i] - r[i]; cnt += t + 1; if (t % 2 == 0) cnt--; } if (t2 > t1) cnt += n - r[t2 - 1]; } cout << n - cnt << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int num = 200001; long long a[401]; int main() { int t, n; cin >> t; int str, cur; int fl = 0; while (t--) { cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) a[n + i] = a[i]; cur = 2 * n; int first = 1; for (int i = 0; i < cur; i++) { if (a[i] == first) { first++; } else { first = 1; } if (first == n) { fl = 1; break; } } first = n; for (int i = 0; i < cur; i++) { if (a[i] == first) first--; else first = n; if (first == 1) { fl = 1; break; } } if (fl) cout << YES n ; else cout << NO n ; fl = 0; for (int i = 0; i < cur; i++) a[i] = 0; } return 0; } |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_b_e
//
// Generated
// by: wig
// on: Mon Oct 23 16:54:16 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bugver2006.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_b_e.v,v 1.1 2006/10/30 15:38:11 wig Exp $
// $Date: 2006/10/30 15:38:11 $
// $Log: inst_b_e.v,v $
// Revision 1.1 2006/10/30 15:38:11 wig
// Updated testcase bitsplice/rfe20060904a and added some bug testcases.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.96 2006/10/23 08:31:06 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of inst_b_e
//
// No user `defines in this module
module inst_b_e
//
// Generated Module inst_b
//
(
only_low // Only ::low defined
);
// Generated Module Inputs:
input only_low;
// Generated Wires:
wire only_low;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of inst_b_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
module test;
reg a, b1, b2;
submod m1 (a, b1, c1);
submod m2 (a, b2, c2);
task set;
input [2:0] bits;
reg t1;
begin
t1 <= a;
#1 {a,b1,b2} <= bits;
end
endtask
initial
begin
$dumpfile("work/vcd-dup.vcd");
$dumpvars(2, test); // test, test.m1, test.m2
$dumpvars(3, m2.c1, m1.mm1.c1); // duplicate signals
#0; // does not trip $enddefinitions
a = 0; // does not trip $enddefinitions
$dumpvars(0, m1); // (test.m1), test.m1.mm1, test.m1.mm2
#1; // $enddefinitions called
$dumpvars(0, m2); // ignored
end
initial
begin
#1 set(3'd 0);
#1;
#1 set(3'd 1);
#1;
#1 set(3'd 2);
#1 $dumpoff;
#1 set(3'd 3);
#1;
#1 set(3'd 4);
#1 $dumpon;
#1 set(3'd 5);
#1;
#1 set(3'd 6);
#1;
#1 set(3'd 7);
#1;
#1 set(3'd 0);
#1 $dumpall;
#1 $finish;
end
endmodule
module submod (a, b, c);
input a, b;
output c;
subsub mm1 (a&b, c1);
subsub mm2 (a|b, c2);
assign c = c1 ^ c2;
endmodule
module subsub (a, c);
input a;
output c;
wire c1 = ~a;
assign c = c1;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, a1, t1, a2, t2, n1 = 0, n2 = 0; cin >> n >> a1 >> a2 >> t1 >> t2; n1 += t1 * 2; n2 += t2 * 2; n1 += a1 * n; n2 += a2 * n; if (n1 > n2) cout << Second ; if (n2 > n1) cout << First ; if (n1 == n2) cout << Friendship ; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:31:27 03/28/2014
// Design Name:
// Module Name: sccpu_cpu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sccpu_cpu(
input clk,
input clrn,
output reg[31:0] pc,
output [31:0] inst,
output wire[31:0] dataout,result,d,
output zero,wreg,m2reg,
output wire[1:0] pcsource
);
wire [4:0] rs1,rs2,rd,rna,rnb,wn,sa;
wire [31:0] qa,qb,a,b;
wire sst,shift,aluimm,sext,wmem,wzero;
wire [1:0] adepend,bdepend,sdepend;
wire loaddepend;
wire[3:0] aluc;
wire [15:0] imme;
wire[31:0] inst_out;
wire[31:0] eximme,next_pc,ex_sa;
reg[31:0] clk_cnt;
wire ewreg,em2reg,eshift,ealuimm,ewmem,ewzero;
wire [1:0] eadepend,ebdepend,esdepend;
wire[3:0] ealuc;
wire[4:0] erd,esa;
wire[31:0] eqa,eqb,eeximme;
wire mwreg,mm2reg,mwmem;
wire[1:0] msdepend;
wire[4:0] mrd;
wire[31:0] mresult,mqb;
wire wwreg,wm2reg;
wire[4:0] wrd;
wire[31:0] wresult,wdataout;
wire[31:0] pre_d;
wire[31:0] m_data;
initial begin
pc = 0;
clk_cnt= 0;
end
IP_ROM InstMem(pc,inst_out);
dffinst ip(inst_out,clk,clrn,loaddepend,inst);
next_pc go_pc(inst,pcsource,clk,loaddepend,pc,next_pc);
always @(next_pc)
begin
pc <= next_pc;
end
assign rs1 = inst[20:16];
assign rs2 = inst[4:0];
assign rd = inst[25:21];
assign imme = inst[15:0];
assign sa = inst[20:16];
cu control_unit(inst,zero,rs1,rs2,rd,erd,mrd,ewreg,mwreg,em2reg,
wreg,sst,m2reg,shift,aluimm,sext,aluc,wmem,pcsource,adepend,bdepend,sdepend,loaddepend,wzero);
assign rna = rs1;
mux2x5 slct_rnb(rs2,rd,sst,rnb);
mux2x32 slct_d(wresult,wdataout,wm2reg,d);
assign wn = wrd;
dffd push_d(d,clk,clrn,pre_d);
regfile rf(rna,rnb,d,wn,wwreg,clk,clrn,qa,qb);
expand expand_imme(imme,sext,eximme);
diff_d2e push_d2e(
clk,clrn,
wreg,m2reg,shift,aluimm,wmem,wzero,aluc,rd,qa,qb,eximme,sa,adepend,bdepend,sdepend,
ewreg,em2reg,eshift,ealuimm,ewmem,ewzero,ealuc,erd,eqa,eqb,eeximme,esa,eadepend,ebdepend,esdepend
);
assign ex_sa = {{27{esa[4]}},esa[4:0]};
//mux2x32 slct_a(eqa,ex_sa,eshift,a);
//mux2x32 slct_b(eqb,eeximme,ealuimm,b);
mux4x32 slct_a(eqa,ex_sa,mresult,d,eadepend,a);
mux4x32 slct_b(eqb,eeximme,mresult,d,ebdepend,b);
alu alu_unit(a,b,ealuc,ewzero,zero,result);
diff_e2m push_e2m(
clk,clrn,
ewreg,em2reg,ewmem,erd,result,eqb,esdepend,
mwreg,mm2reg,mwmem,mrd,mresult,mqb,msdepend
);
mux4x32 slct_m_data(mqb,mqb,d,pre_d,msdepend,m_data);
IP_RAM DataMem(mwmem,mresult,m_data,clk,dataout);
diff_m2w push_m2w(
clk,clrn,
mwreg,mm2reg,mrd,mresult,dataout,
wwreg,wm2reg,wrd,wresult,wdataout
);
//ÒÔÏÂΪ²âÊÔÓÃ
always @(posedge clk) //¿ØÖÆʱÖÓÖÜÆÚÖ´ÐиöÊý
begin
clk_cnt = clk_cnt + 1;
if (clk_cnt==550)
$stop;
end
always @(inst) //ÈôÖ¸ÁîÈ«ÁãÔòÖÕÖ¹
begin
if (inst==0)
$stop;
end
endmodule
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