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#include <bits/stdc++.h> using namespace std; int n, k; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> k; if (n < 2 * k + 1) { cout << -1 << endl; return 0; } cout << n * k << endl; for (int i = 0; i < n; i++) for (int j = 1; j <= k; j++) cout << i + 1 << << (i + j) % n + 1 << n ; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 60; int n, l; char s[maxn][maxn], t[maxn]; bool eq(int x, int i, int j) { for (int k = 0; k < l; k++) { if (s[x][i] != t[j]) return false; i = (i + 1) % l; j = (j + 1) % l; } return true; } int dist(int x, int j) { for (int i = 0; i < l; i++) if (eq(x, i, j)) return i; return -1; } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %s , s[i]); l = strlen(s[0]); strcpy(t, s[0]); int ans = 0x3f3f3f3f; for (int j = 0; j < l; j++) { int t = 0; for (int x = 0; x < n; x++) { int d = dist(x, j); if (d == -1) { printf( -1 n ); return 0; } t += d; } if (t < ans) ans = t; } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1000010; bitset<N> b; int p[N]; int cnt[N]; bool was[N]; int main() { int n, k; scanf( %d %d , &n, &k); for (int i = 0; i < n; i++) { scanf( %d , p + i); p[i]--; was[i] = false; } for (int i = 1; i <= n; i++) { cnt[i] = 0; } int c1 = 0, c2 = 0; for (int i = 0; i < n; i++) { if (was[i]) { continue; } int x = i; int len = 0; while (!was[x]) { was[x] = true; x = p[x]; len++; } c1 += len % 2; c2 += len / 2; cnt[len]++; } b.set(0); for (int i = 1; i <= n; i++) { if (cnt[i] == 0) { continue; } int j = 1; while (cnt[i] > 0) { j = min(j, cnt[i]); int u = i * j; b |= (b << u); cnt[i] -= j; j *= 2; } } int ans_min = k; if (!b.test(k)) { ans_min++; } int ans_max = 0; ans_max += 2 * min(k, c2); k -= min(k, c2); ans_max += min(k, c1); printf( %d %d n , ans_min, ans_max); return 0; } |
module memif_d(
input wire clk,
input wire reset,
// Avalon Slave
input wire [1:0] s_address,
input wire s_write,
input wire s_read,
input wire [31:0] s_writedata,
output reg [31:0] s_readdata,
output wire s_waitrequest,
// 64 bit Avalon Master
output wire [31:0] m_address,
output reg m_write,
output reg m_read,
output wire [63:0] m_writedata,
input wire [63:0] m_readdata,
input wire m_waitrequest
);
reg [31:0] addr;
reg [63:0] word;
assign m_address = addr;
assign m_writedata = word;
wire write_edge, read_edge;
edgedet e0(clk, reset, s_write, write_edge);
edgedet e1(clk, reset, s_read, read_edge);
reg waiting;
wire req = (write_edge|read_edge) & s_address == 2'h2;
assign s_waitrequest = req | waiting;
always @(posedge clk or negedge reset) begin
if(~reset) begin
m_write <= 0;
m_read <= 0;
waiting <= 0;
addr <= 0;
word <= 0;
end else begin
if(write_edge) begin
case(s_address)
2'h0: addr <= s_writedata[31:0];
2'h1: word[31:0] <= s_writedata[31:0];
2'h2: word[63:32] <= s_writedata[31:0];
endcase
end
if(req) begin
waiting <= 1;
if(s_write)
m_write <= 1;
else if(s_read)
m_read <= 1;
end
if(m_write & ~m_waitrequest) begin
m_write <= 0;
waiting <= 0;
end
if(m_read & ~m_waitrequest) begin
m_read <= 0;
waiting <= 0;
word <= m_readdata;
end
end
end
always @(*) begin
case(s_address)
2'h1: s_readdata <= word[31:0];
2'h2: s_readdata <= word[63:32];
default: s_readdata <= 32'b0;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, m, q; long long siz[100005]; long long par[100005]; string s; unordered_map<string, long long> idx; vector<pair<long long, long long> > e[100005]; long long ans[100005]; long long dis[100005]; pair<long long, pair<long long, long long> > edges[100005]; long long find_set(long long a) { if (a == par[a]) return a; return par[a] = find_set(par[a]); } void union_set(long long a, long long b) { a = find_set(a); b = find_set(b); if (a != b) { if (siz[a] < siz[b]) swap(a, b); par[b] = a; siz[a] += siz[b]; } } void dfs(long long u, long long len, long long par) { dis[u] = len; for (auto i : e[u]) { if (i.first != par) dfs(i.first, len + i.second, u); } } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> m >> q; for (long long i = 0; i < n; i++) { cin >> s; idx[s] = i; par[i] = i; siz[i] = 1; } for (long long i = 0; i < m; i++) { long long type; string a, b; cin >> type >> a >> b; long long u = idx[a]; long long v = idx[b]; edges[i] = {type, {u, v}}; long long uRep = find_set(u); long long vRep = find_set(v); if (uRep == vRep) continue; union_set(uRep, vRep); if (type == 1) e[u].push_back({v, 0}), e[v].push_back({u, 0}); else e[u].push_back({v, 1}), e[v].push_back({u, 1}); ans[i] = 1; } memset(dis, -1, sizeof(dis)); for (long long i = 0; i < n; i++) { if (dis[i] == -1) { long long iRep = find_set(i); dfs(iRep, 0, -1); } } for (long long i = 0; i < m; i++) { if (ans[i]) cout << YES n ; else { long long u = edges[i].second.first; long long v = edges[i].second.second; long long type = edges[i].first; long long real_type; if (dis[u] % 2 == dis[v] % 2) real_type = 1; else real_type = 2; if (real_type == type) cout << YES n ; else cout << NO n ; } } while (q--) { string a, b; cin >> a >> b; long long u = idx[a]; long long v = idx[b]; long long uRep = find_set(u); long long vRep = find_set(v); if (uRep != vRep) cout << 3 << endl; else { if (dis[u] % 2 == dis[v] % 2) cout << 1 << endl; else cout << 2 << endl; } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MUX2I_SYMBOL_V
`define SKY130_FD_SC_HS__MUX2I_SYMBOL_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__mux2i (
//# {{data|Data Signals}}
input A0,
input A1,
output Y ,
//# {{control|Control Signals}}
input S
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__MUX2I_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; inline long long read(long long num = 0, char c = 0) { while (c > 9 || c < 0 ) c = getchar(); while (c >= 0 && c <= 9 ) num = num * 10 + c - 48, c = getchar(); return num; } struct node { int x, y, val, num; void in() { x = read(), y = read(), val = read(); } } p[500010]; int f[2005], n, m, q, l, r; int find(int x) { return f[x] == x ? x : f[x] = find(f[x]); } bool cmp(node a, node b) { return a.val > b.val; } int work() { for (register int i = 1; i <= m; ++i) { if (p[i].num >= l && p[i].num <= r) { if (find(p[i].x) == find(p[i].y)) { return p[i].val; } else { f[find(p[i].x + n)] = f[find(p[i].y)]; f[find(p[i].y + n)] = f[find(p[i].x)]; } } } return -1; } int main() { n = read(), m = read(), q = read(); for (register int i = 1; i <= m; ++i) p[i].in(), p[i].num = i; sort(p + 1, p + 1 + m, cmp); for (register int i = 1; i <= q; ++i) { l = read(), r = read(); for (register int i = 1; i <= 2 * n; ++i) f[i] = i; printf( %d n , work()); } return 0; } |
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module address_filter
(input clk,
input reset,
input go,
input [7:0] data,
input [47:0] address,
output match,
output done);
reg [2:0] af_state;
always @(posedge clk)
if(reset)
af_state <= 0;
else
if(go)
af_state <= (data == address[47:40]) ? 1 : 7;
else
case(af_state)
1 : af_state <= (data == address[39:32]) ? 2 : 7;
2 : af_state <= (data == address[31:24]) ? 3 : 7;
3 : af_state <= (data == address[23:16]) ? 4 : 7;
4 : af_state <= (data == address[15:8]) ? 5 : 7;
5 : af_state <= (data == address[7:0]) ? 6 : 7;
6, 7 : af_state <= 0;
endcase // case (af_state)
assign match = (af_state==6);
assign done = (af_state==6)|(af_state==7);
endmodule // address_filter
|
#include <bits/stdc++.h> using namespace std; vector<int> edges[500000]; bool vis[500000]; int order[1000000]; int first[500000], second[500000]; int C; void dfs(int i) { vis[i] = 1; first[i] = C; order[C++] = i; for (int j = 0; j < edges[i].size(); j++) if (!vis[edges[i][j]]) dfs(edges[i][j]); second[i] = C; order[C++] = i; } int segFill[2 * (1 << 20)], up[2 * (1 << 20)]; int segEmpty[2 * (1 << 20)]; int l[2 * (1 << 20)], r[2 * (1 << 20)]; void init() { for (int i = (1 << 20); i < 2 * (1 << 20); i++) { segFill[i] = -1; up[i] = 0; segEmpty[i] = 0; l[i] = r[i] = i - (1 << 20); } for (int i = (1 << 20) - 1; i > 0; i--) { segFill[i] = -1; up[i] = 0; segEmpty[i] = 0; l[i] = l[2 * i]; r[i] = r[2 * i + 1]; } } void push(int i) { if (up[i] > 0) { if (i < (1 << 20)) { up[(i << 1)] = up[i]; up[(i << 1) + 1] = up[i]; } segFill[i] = up[i]; up[i] = 0; } } int getFill(int i, int loc) { push(i); if (i >= (1 << 20)) return segFill[i]; else if (r[(i << 1)] >= loc) return getFill((i << 1), loc); else return getFill((i << 1) + 1, loc); } int low, high; void setFill(int i, int v) { push(i); if ((l[i] > high) || (r[i] < low)) return; if ((l[i] >= low) && (r[i] <= high)) { up[i] = v; push(i); return; } setFill((i << 1), v); setFill((i << 1) + 1, v); segFill[i] = max(segFill[(i << 1)], segFill[(i << 1) + 1]); } void setEmpty(int loc, int v) { loc += (1 << 20); segEmpty[loc] = v; for (loc /= 2; loc > 0; loc /= 2) segEmpty[loc] = max(segEmpty[2 * loc], segEmpty[2 * loc + 1]); } int getEmpty(int i) { if ((l[i] > high) || (r[i] < low)) return 0; if ((l[i] >= low) && (r[i] <= high)) return segEmpty[i]; return max(getEmpty((i << 1)), getEmpty((i << 1) + 1)); } int main() { int N, a, b; scanf( %d , &N); for (int i = 1; i < N; i++) { scanf( %d %d , &a, &b); a--, b--; edges[a].push_back(b); edges[b].push_back(a); } C = 0; dfs(0); init(); int Q, tp, v; scanf( %d , &Q); for (int i = 0; i < Q; i++) { scanf( %d %d , &tp, &v); v--; if (tp == 1) { low = first[v]; high = second[v]; setFill(1, i + 1); } if (tp == 2) setEmpty(first[v], i + 1); if (tp == 3) { low = first[v]; high = second[v]; a = getFill(1, first[v]); b = getEmpty(1); printf( %d n , a >= b); } } } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t; cin >> t; while (t--) { int n, m, a, b; cin >> n >> m >> a >> b; int total_ones = n * a; if (total_ones != m * b) { cout << NO << endl; } else { cout << YES << endl; string str = ; for (int i = 0; i < m; i++) { if (i < a) str += 1 ; else str += 0 ; } for (int i = 0; i < n; i++) { cout << str << endl; for (int j = 0; j < a; j++) { char c = str[0]; str = str.substr(1); str = str + c; } } } } } |
//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=25 clk0_duty_cycle=50 clk0_multiply_by=1 clk0_phase_shift="0" compensate_clock="CLK0" device_family="Cyclone IV E" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=dac_pll" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 clk inclk CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
//VERSION_BEGIN 16.0 cbx_altclkbuf 2016:04:27:18:05:34:SJ cbx_altiobuf_bidir 2016:04:27:18:05:34:SJ cbx_altiobuf_in 2016:04:27:18:05:34:SJ cbx_altiobuf_out 2016:04:27:18:05:34:SJ cbx_altpll 2016:04:27:18:05:34:SJ cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_lpm_compare 2016:04:27:18:05:34:SJ cbx_lpm_counter 2016:04:27:18:05:34:SJ cbx_lpm_decode 2016:04:27:18:05:34:SJ cbx_lpm_mux 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ cbx_stratixiii 2016:04:27:18:05:34:SJ cbx_stratixv 2016:04:27:18:05:34:SJ cbx_util_mgl 2016:04:27:18:05:34:SJ VERSION_END
//CBXI_INSTANCE_NAME="DE0_myfirstfpga_dac_pll_inst_altpll_altpll_component"
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = cycloneive_pll 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module dac_pll_altpll
(
clk,
inclk) /* synthesis synthesis_clearbox=1 */;
output [4:0] clk;
input [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] wire_pll1_clk;
wire wire_pll1_fbout;
cycloneive_pll pll1
(
.activeclock(),
.clk(wire_pll1_clk),
.clkbad(),
.fbin(wire_pll1_fbout),
.fbout(wire_pll1_fbout),
.inclk(inclk),
.locked(),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll1.bandwidth_type = "auto",
pll1.clk0_divide_by = 25,
pll1.clk0_duty_cycle = 50,
pll1.clk0_multiply_by = 1,
pll1.clk0_phase_shift = "0",
pll1.compensate_clock = "clk0",
pll1.inclk0_input_frequency = 20000,
pll1.operation_mode = "normal",
pll1.pll_type = "auto",
pll1.lpm_type = "cycloneive_pll";
assign
clk = {wire_pll1_clk[4:0]};
endmodule //dac_pll_altpll
//VALID FILE
|
#include <bits/stdc++.h> using namespace std; int x[55], y[55]; int main(int argc, char** argv) { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &x[i]); for (int i = 1; i <= n; i++) scanf( %d , &y[i]); int sum = 0; for (int i = 1; i <= n; i++) { sum += x[i] - y[i]; } if (sum >= 0) cout << Yes ; else cout << No ; return 0; } |
#include <bits/stdc++.h> using namespace std; float calc(int h, int d, int c, int n) { float a; if (h % n == 0) { a = (h / n) * c; } else a = ((h / n) + 1) * c; return a; } int main() { int p = 0, q = 0; int h, d, c, n, eh; int hh, mm; cin >> hh >> mm; cin >> h >> d >> c >> n; float a = calc(h, d, c, n); if (hh >= 20) { a = a * 0.8; printf( %f , a); return 0; } if (mm != 00) { q = 60 - mm; p = 19 - hh; } else p = 20 - hh; eh = (p * 60 + q) * d; h = h + eh; float b = calc(h, d, c, n); b = b * 0.8; if (b < a) a = b; printf( %f , a); return 0; } |
#include <bits/stdc++.h> using namespace std; bool cmp(int a, int b) { return a > b; } const int maxen = 1e5 + 5, minn = 1e-5; string a[1005]; int main() { int n; cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; int res = 0, mn = 13; for (int i = 0; i < n - 1; i++) { for (int j = i + 1; j < n; j++) { string b = a[i]; string c = a[j]; res = 0; for (int k = 0; k < 6; k++) if (b[k] != c[k]) res++; mn = min(mn, res); } } cout << (mn - 1) / 2 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 1000 * 1000 * 1000 + 47; const long long LINF = (long long)INF * INF; const int MAX = 2e5; const double EPS = 1e-9; const double PI = acos(-1.); int n; int a[10][10]; int dx[8] = {2, 2, 1, -1, -2, -2, -1, 1}; int dy[8] = {1, -1, -2, -2, -1, 1, 2, 2}; pair<int, int> dpT[100][10][10][3][212]; bool ok(int x, int y) { if (min(x, y) < 0) return false; if (max(x, y) >= n) return false; return true; } pair<int, int> dp(int cur, int x, int y, int fig, int steps) { if (steps == 212) { return make_pair(INF, INF); } if (cur == n * n) { return make_pair(0, 0); } if (dpT[cur][x][y][fig][steps] != make_pair(-1, -1)) { return dpT[cur][x][y][fig][steps]; } if (a[x][y] == cur) { return dpT[cur][x][y][fig][steps] = dp(cur + 1, x, y, fig, steps); } pair<int, int> best = make_pair(INF, INF); if (fig != 0) { pair<int, int> a = dp(cur, x, y, 0, steps + 1); best = min(best, make_pair(a.first + 1, a.second + 1)); } if (fig != 1) { pair<int, int> a = dp(cur, x, y, 1, steps + 1); best = min(best, make_pair(a.first + 1, a.second + 1)); } if (fig != 2) { pair<int, int> a = dp(cur, x, y, 2, steps + 1); best = min(best, make_pair(a.first + 1, a.second + 1)); } if (fig == 0) { for (int i = (0); i < (8); ++i) { int nx = x + dx[i]; int ny = y + dy[i]; if (ok(nx, ny)) { pair<int, int> a = dp(cur, nx, ny, fig, steps + 1); best = min(best, make_pair(a.first + 1, a.second)); } } } if (fig == 1) { for (int i = (-n); i < (n + 1); ++i) { if (!i) continue; int nx = x + i; int ny = y; if (ok(nx, ny)) { pair<int, int> a = dp(cur, nx, ny, fig, steps + 1); best = min(best, make_pair(a.first + 1, a.second)); } nx = x; ny = y + i; if (ok(nx, ny)) { pair<int, int> a = dp(cur, nx, ny, fig, steps + 1); best = min(best, make_pair(a.first + 1, a.second)); } } } if (fig == 2) { for (int i = (-n); i < (n + 1); ++i) { if (!i) continue; int nx = x + i; int ny = y + i; if (ok(nx, ny)) { pair<int, int> a = dp(cur, nx, ny, fig, steps + 1); best = min(best, make_pair(a.first + 1, a.second)); } nx = x - i; ny = y + i; if (ok(nx, ny)) { pair<int, int> a = dp(cur, nx, ny, fig, steps + 1); best = min(best, make_pair(a.first + 1, a.second)); } } } return dpT[cur][x][y][fig][steps] = best; } int main() { ios_base::sync_with_stdio(0); memset(dpT, -1, sizeof(dpT)); cin >> n; int x, y; for (int i = (0); i < (n); ++i) { for (int j = (0); j < (n); ++j) { cin >> a[i][j]; a[i][j]--; if (a[i][j] == 0) { x = i; y = j; } } } pair<int, int> best = make_pair(INF, INF); best = min(best, dp(1, x, y, 0, 0)); best = min(best, dp(1, x, y, 1, 0)); best = min(best, dp(1, x, y, 2, 0)); cout << best.first << << best.second << endl; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 7; int vis1[MAXN], vis2[MAXN], dis[MAXN]; int st, ed, n, ans; queue<int> q; vector<int> G[MAXN]; void Bfs1() { for (; !q.empty();) q.pop(); q.push(1); vis1[1] = 1; for (; !q.empty();) { int u = q.front(); q.pop(); for (auto v : G[u]) { if (vis1[v]) continue; q.push(v); vis1[v] = u; } st = u; } } void Bfs2() { for (; !q.empty();) q.pop(); q.push(st); vis2[st] = st; for (; !q.empty();) { int u = q.front(); q.pop(); for (auto v : G[u]) { if (vis2[v]) continue; q.push(v); vis2[v] = u; } ed = u; } } int degree(int x) { return (int)G[x].size(); } bool check(int root) { int Tim = 0; for (int i = 1; i <= n; i++) vis1[i] = dis[i] = 0; for (; !q.empty();) q.pop(); q.push(root); vis1[root] = 1; for (; !q.empty();) { int u = q.front(); q.pop(); for (auto v : G[u]) { if (vis1[v]) continue; if (++Tim == n) { } q.push(v); vis1[v] = vis1[u] + 1; if (!dis[vis1[v]]) dis[vis1[v]] = v; if (degree(v) != degree(dis[vis1[v]])) return false; } } ans = root; return true; } bool checkCenter() { int Tim = 0; int D = 0; for (int u = ed; u != st; u = vis2[u]) D++; if (D & 1) return false; int center = ed; for (int i = 0; i != D / 2; i++, center = vis2[center]) ; if (check(center)) return true; for (int i = 1; i <= n; i++) vis1[i] = dis[i] = 0; for (; !q.empty();) q.pop(); q.push(center); vis1[center] = 1; for (; !q.empty();) { int u = q.front(); q.pop(); for (auto v : G[u]) { if (vis1[v]) continue; if (++Tim == n) { } q.push(v); vis1[v] = vis1[u] + 1; if (!dis[vis1[v]]) dis[vis1[v]] = v; if (degree(v) != degree(dis[vis1[v]])) { for (int x = v, tim = 0;;) { if (++tim == n) break; if (G[x].size() == 1) { if (check(x)) return true; else break; } else x = (vis1[G[x][0]] == 0) ? G[x][0] : G[x][1]; } for (int x = dis[vis1[v]], tim = 0;;) { if (++tim == n) break; if (G[x].size() == 1) { if (check(x)) return true; else break; } else x = (vis1[G[x][0]] == 0) ? G[x][0] : G[x][1]; } return false; } } } ans = center; return true; } int main() { cin >> n; for (int i = 1; i < n; i++) { int u, v; cin >> u >> v; G[u].push_back(v); G[v].push_back(u); } Bfs1(); Bfs2(); if (check(st) || check(ed)) cout << ans; else if (checkCenter()) cout << ans; else cout << -1; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:32:00 07/21/2013
// Design Name: sha256_chunk
// Module Name: C:/Dropbox/xilinx/processor/test/sha_chunk_test.v
// Project Name: processor
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: sha256_chunk
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module sha_chunk_test;
// Inputs
reg [511:0] data;
reg [255:0] V_in;
reg clk = 0;
// Outputs
wire [255:0] hash;
// Instantiate the Unit Under Test (UUT)
sha256_chunk uut (
.clk(clk),
.data(data),
.V_in(V_in),
.hash(hash)
);
parameter P=10;
always #(P/2) clk = ~clk;
initial begin
// Initialize Inputs
data = 0;
data[7:0] = 8'd97;
data[15:8] = 8'd98;
data[23:16] = 8'd99;
data[31:24] = 8'h80;
data[511:504] = 8'd24;
V_in = 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
uut.roundnum = 6'h3e;
#(80*P);
$stop();
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m; char ch[201][201]; int main() { cin >> m >> n; n *= 2; m *= 2; for (int i = 1; i <= n; i += 2) for (int j = 1; j <= m; j += 2) { cin >> ch[i][j]; ch[i + 1][j] = ch[i][j + 1] = ch[i + 1][j + 1] = ch[i][j]; } for (int j = 1; j <= m; j++) { for (int i = 1; i <= n; i++) cout << ch[i][j]; cout << endl; } return 0; } |
module instruction_decoder_testbench();
reg[31:0] instruction_data;
wire[3:0] opcode;
wire input_type_1;
wire[1:0] input_register_selector_1;
wire[7:0] input_immediate_1;
wire input_type_2;
wire[1:0] input_register_selector_2;
wire[7:0] input_immediate_2;
wire[1:0] output_register_selector;
instruction_decoder id(instruction_data, opcode,
input_type_1, input_register_selector_1,
input_immediate_1, input_type_2,
input_register_selector_2, input_immediate_2,
output_register_selector);
initial
begin
#0 assign instruction_data = 'h00000000;
$display("opcode\treg s1\treg s2\treg d\timm 1\timm 2");
$monitor("%b\t%d\t%d\t%d\t%d\t%d",
opcode, input_register_selector_1, input_register_selector_2,
output_register_selector,
input_immediate_1, input_immediate_2);
/* 0 | r0 | i 255 | r0 | 0 */
#1 assign instruction_data = 'b00000010000001111111110000000000;
/* 1 | r3 | i 42 | r0 | 0 */
#2 assign instruction_data = 'b00010110000001001010100100000000;
/* 2 | i 1 | r0 | r0 | 0 */
#3 assign instruction_data = 'b00101000000010000000001000000000;
/* 3 | i 255 | r2 | r0 | 0 */
#4 assign instruction_data = 'b00111111111110100000001100000000;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MN = 100005, inf = 1000000005, mod = 1000000007; const long long INF = 1000000000000000005LL; const long double eps = (long double)1e-10; long long det(pair<int, int> x, pair<int, int> y) { return 1LL * x.first * y.second - 1LL * x.second * y.first; } long long det_pts(pair<int, int> x, pair<int, int> y, pair<int, int> z) { y.first -= x.first; y.second -= x.second; z.first -= x.first; z.second -= x.second; return det(y, z); } long double detf(pair<long double, long double> x, pair<long double, long double> y) { return x.first * y.second - x.second * y.first; } namespace hull { vector<pair<int, int> > half_oto(vector<pair<int, int> >& P) { vector<pair<int, int> > H; for (auto p : P) { while (H.size() > 1 && det_pts(H[H.size() - 2], H.back(), p) >= 0LL) H.pop_back(); H.push_back(p); } return H; } vector<pair<int, int> > oto(vector<pair<int, int> > P) { vector<pair<int, int> > L, U, ret; sort((P).begin(), (P).end()); U = half_oto(P); reverse((P).begin(), (P).end()); L = half_oto(P); int su = U.size(), sl = L.size(); for (int i = 0; i < su; ++i) ret.push_back(U[i]); for (int i = 1; i < sl - 1; ++i) ret.push_back(L[i]); return ret; } }; // namespace hull pair<long double, long double> daj(pair<long double, long double> a, pair<long double, long double> b, long double alfa) { return {a.first * alfa + b.first * (1.0 - alfa), a.second * alfa + b.second * (1.0 - alfa)}; } long double P, Q; long double wyn(pair<long double, long double> p) { if (min(p.first, p.second) < eps) return (long double)INF; return max(P / p.first, Q / p.second); } long double tern(pair<int, int> a, pair<int, int> b) { pair<long double, long double> af = {(long double)a.first, (long double)a.second}; pair<long double, long double> bf = {(long double)b.first, (long double)b.second}; long double zd = 0.0, zg = 1.0; for (int i = 1; i <= 60; ++i) { long double one_th = (zg - zd) / 3.0, a1 = zd + one_th, a2 = zg - one_th; pair<long double, long double> l = daj(af, bf, a1), r = daj(af, bf, a2); if (wyn(l) > wyn(r)) zd = a1; else zg = a2; } long double alfa = (zd + zg) / 2.0; return wyn(daj(af, bf, alfa)); } int main() { int n, p, q; scanf( %d%d%d , &n, &p, &q); P = p, Q = q; vector<pair<int, int> > pts; for (int i = 1; i <= n; ++i) { int a, b; scanf( %d%d , &a, &b); pair<int, int> p = {a, b}; pts.push_back(p); p = {a, 0}; pts.push_back(p); p = {0, b}; pts.push_back(p); } pts = hull::oto(pts); int s = pts.size(); long double ans = (long double)INF; for (int i = 1; i < s; ++i) { auto cur_wyn = tern(pts[i - 1], pts[i]); ans = min(ans, cur_wyn); } printf( %.9Lf , ans); } |
`timescale 1ns/1ps
`define INDEX(x,y) x*y +: y
module tb_register ;
localparam REGISTER_NUM_REGISTERS = 16 ;
localparam REGISTER_NUM_DATA_IN = 2 ;
localparam REGISTER_NUM_DATA_OUT = 4 ;
localparam REGISTER_NUM_SEL_BITS = $clog2(REGISTER_NUM_REGISTERS) ;
localparam REGISTER_WIDTH_DATA = 32 ;
localparam REGISTER_NUM_WRITE_TESTS = 128 ;
reg r_clk ;
reg [REGISTER_NUM_DATA_IN-1:0] r_we ;
reg [REGISTER_NUM_DATA_OUT-1:0] r_re ;
reg [REGISTER_NUM_DATA_IN*REGISTER_NUM_SEL_BITS-1:0] r_data_in_sel ;
reg [REGISTER_NUM_DATA_OUT*REGISTER_NUM_SEL_BITS-1:0] r_data_out_sel ;
reg [REGISTER_NUM_DATA_IN*REGISTER_WIDTH_DATA-1:0] r_data_in ;
wire [REGISTER_NUM_DATA_OUT*REGISTER_WIDTH_DATA-1:0] w_data_out ;
register dut (
.i_clk (r_clk),
.i_we (r_we),
.i_re (r_re),
.i_data_in_sel (r_data_in_sel),
.i_data_out_sel (r_data_out_sel),
.i_data_in (r_data_in),
.o_data_out (w_data_out)
) ;
initial begin
r_clk = 0 ;
r_we = {REGISTER_NUM_DATA_IN{1'b0}} ;
r_re = {REGISTER_NUM_DATA_OUT{1'b0}} ;
r_data_in_sel = {REGISTER_NUM_DATA_IN*REGISTER_NUM_SEL_BITS{1'b0}} ;
r_data_out_sel = {REGISTER_NUM_DATA_OUT*REGISTER_NUM_SEL_BITS{1'b0}} ;
r_data_in = {REGISTER_NUM_DATA_IN*REGISTER_WIDTH_DATA{1'b0}} ;
end
initial begin
$dumpfile ("tb_register.dump") ;
$dumpvars ;
end
initial begin
$display("\t|%10s |%4s |%4s |%13s |%18s |%4s |%14s |%34s |","time","clk","we","data_in_sel","data_in","re",
"data_out_sel","data_out") ;
$monitor("\t|%10t |%4h |%4h |%13h |%18h |%4h |%14h |%34h |",$time,r_clk,r_we,r_data_in_sel,r_data_in,r_re,
r_data_out_sel, w_data_out) ;
end
always begin
#50 r_clk = !r_clk ;
end
initial begin : Test_Cases
integer i ;
for (i=0; i<REGISTER_NUM_WRITE_TESTS; i=i+1) begin : Writing_Test
#20 r_we[$urandom%REGISTER_NUM_DATA_IN] = $random ;
r_data_in_sel[`INDEX($clog2(r_we),REGISTER_NUM_SEL_BITS)] = $random ;
r_data_in[`INDEX($clog2(r_we),REGISTER_WIDTH_DATA)] = $random ;
r_re = 1'b1 ;
r_data_out_sel[`INDEX(0,REGISTER_NUM_SEL_BITS)] = r_data_in_sel[`INDEX($clog2(r_we),
REGISTER_NUM_SEL_BITS)] ;
#150 if ((r_we != {REGISTER_NUM_DATA_IN{1'b0}}) && (w_data_out[`INDEX(0,REGISTER_WIDTH_DATA)] !=
r_data_in[`INDEX($clog2(r_we),REGISTER_WIDTH_DATA)])) begin
$display ("Write error at time %0t",$time) ;
$display ("Expected value: %0h, Actual value: %0h", r_data_in[`INDEX($clog2(r_we),REGISTER_WIDTH_DATA)],
w_data_out[`INDEX(0,REGISTER_WIDTH_DATA)]) ;
$stop ;
end
#30 r_we = {REGISTER_NUM_DATA_IN{1'b0}} ;
r_data_in_sel = {REGISTER_NUM_DATA_IN*REGISTER_NUM_SEL_BITS{1'b0}} ;
r_data_in = {REGISTER_NUM_DATA_IN*REGISTER_WIDTH_DATA{1'b0}} ;
r_re = {REGISTER_NUM_DATA_OUT{1'b0}} ;
r_data_out_sel = {REGISTER_NUM_DATA_OUT*REGISTER_NUM_SEL_BITS{1'b0}} ;
end
$stop ;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = (int)2e9; const double EPS = 1e-6; const double PI = 3.1415926535; const int MOD = 1000003; int last[100000]; int main() { int a, b, m, now, i = 2; cin >> a >> b >> m >> now; last[now] = 1; while (1) { now = (a * now + b) % m; if (last[now]) { cout << i - last[now]; return 0; } else last[now] = i++; } } |
#include <bits/stdc++.h> using namespace std; int main() { long long n, count = 0, ans; cin >> n; string s; cin >> s; long long r = 0, b = 0; for (long long i = 0; i < n; i++) if (s[i] == r ) r++; else if (s[i] == b ) b++; for (long long i = 0; i < n; i++) if (i % 2 == 0 && s[i] != r ) count++; else if (i % 2 == 1 && s[i] != b ) count++; long long rx = n % 2 == 1 ? 1 + (long long)(n / 2) : n / 2; ans = abs(r - rx); count -= ans; ans += (count / 2); count = 0; for (long long i = 0; i < n; i++) if (i % 2 == 1 && s[i] != r ) count++; else if (i % 2 == 0 && s[i] != b ) count++; ans = min(ans, abs(b - rx) + (count - abs(b - rx)) / 2); cout << ans; } |
#include <bits/stdc++.h> using namespace std; const double EPS = 1e-9; const long long MOD = 1000000007; const int inf = 1 << 30; const long long linf = 1LL << 60; const double PI = 3.14159265358979323846; int n, k; char s[100000]; vector<int> v[2]; int main() { scanf( %d%d , &n, &k); for (int i = 0; i < n; i++) scanf( %c , s + i); for (int i = 0; i < n; i++) { if (s[i] == 0 ) v[0].push_back(i); else v[1].push_back(i); } if (v[0].size() == 0 || v[1].size() == 0) { puts( tokitsukaze ); return 0; } if (v[0][v[0].size() - 1] - v[0][0] + 1 <= k || v[1][v[1].size() - 1] - v[1][0] + 1 <= k) { puts( tokitsukaze ); return 0; } for (int i = 0; i < n - k + 1; i++) { for (int j = 0; j < 2; j++) { if (i <= v[j ^ 1][0] && v[j ^ 1][0] < i + k) { int pos = lower_bound(v[j ^ 1].begin(), v[j ^ 1].end(), i + k) - v[j ^ 1].begin(); if (v[j ^ 1][v[j ^ 1].size() - 1] - v[j ^ 1][pos] + 1 > k) { puts( once again ); return 0; } } else if (i <= v[j ^ 1][v[j ^ 1].size() - 1] && v[j ^ 1][v[j ^ 1].size() - 1] < i + k) { int pos = lower_bound(v[j ^ 1].begin(), v[j ^ 1].end(), i) - v[j ^ 1].begin(); pos--; if (v[j ^ 1][pos] - v[j ^ 1][0] + 1 > k) { puts( once again ); return 0; } } else { puts( once again ); return 0; } } } puts( quailty ); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_ISOLATCH_PP_PKG_SN_BLACKBOX_V
`define SKY130_FD_SC_LP__UDP_ISOLATCH_PP_PKG_SN_BLACKBOX_V
/**
* udp_isolatch_pp$PKG$sN: Power isolating latch. Includes VPWR,
* KAPWR, and VGND power pins with notifier
* and active low sleep pin (SLEEP_B).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_isolatch_pp$PKG$sN (
Q ,
D ,
SLEEP_B ,
NOTIFIER,
KAPWR ,
VGND ,
VPWR
);
output Q ;
input D ;
input SLEEP_B ;
input NOTIFIER;
input KAPWR ;
input VGND ;
input VPWR ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_ISOLATCH_PP_PKG_SN_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; namespace whatever { const long long inf = 1000000000000000001ll; template <typename type> type read() { char ch = getchar(); while (!isdigit(ch)) ch = getchar(); type value = ch - 0 ; ch = getchar(); while (isdigit(ch)) { value = value * 10 + ch - 0 ; ch = getchar(); } return value; } int n; string f[201]; char result[202]; int fail[201]; int match(const string &str, int l) { int cnt = 0; int cur = 0; for (char ch : str) { while (cur && ch != result[cur + 1]) cur = fail[cur]; if (ch == result[cur + 1]) ++cur; if (cur == l) { ++cnt; cur = fail[cur]; } } return cnt; } long long count(int l) { static long long cnt[201]; int i; for (i = 0; i <= n && (i < 2 || int(f[i - 2].size()) <= l); ++i) cnt[i] = match(f[i], l); if (i <= n) { long long span_cnt[2]; span_cnt[i % 2] = match( f[i - 2].substr(f[i - 2].size() - l + 1) + f[i - 1].substr(0, l - 1), l); span_cnt[1 - i % 2] = match( f[i - 2].substr(f[i - 2].size() - l + 1) + f[i - 2].substr(0, l - 1), l); do { cnt[i] = cnt[i - 2] + cnt[i - 1] + span_cnt[i % 2]; if (cnt[i] >= inf) return inf; } while (++i <= n); } return cnt[n]; } void insert(int l, char ch) { result[l] = ch; if (l == 1) return; int cur = fail[l - 1]; while (cur && ch != result[cur + 1]) cur = fail[cur]; if (ch == result[cur + 1]) ++cur; fail[l] = cur; } void run() { n = read<int>(); long long k = read<long long>() + 1; int m = read<int>(); f[0] = 0 ; f[1] = 1 ; int last = n; for (int i = 2; i <= n; ++i) if (int(f[i - 2].size()) <= m) f[i] = f[i - 2] + f[i - 1]; else { last = i - 1; break; } cerr << last: << last << endl; fail[1] = 0; for (int i = 1; i <= m; ++i) { if (f[last].substr(f[last].size() - i + 1) == string(result + 1, result + i)) { if (--k == 0) break; } insert(i, 0 ); long long cnt = count(i); if (cnt >= k) putchar( 0 ); else { k -= cnt; insert(i, 1 ); putchar( 1 ); } } putchar( n ); } } // namespace whatever int main() { whatever::run(); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRTN_PP_SYMBOL_V
`define SKY130_FD_SC_LP__SDFRTN_PP_SYMBOL_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfrtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK_N ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRTN_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int T = 1; while (T--) { int n, m; cin >> n >> m; map<int, int> mp; vector<pair<int, int> > pp; for (int i = 0; i < m; i++) { int a, b; cin >> a >> b; pp.push_back({a, b}); if (a != b) { mp[a]++; mp[b]++; } else mp[a]++; } vector<pair<int, int> > maxi; for (auto x : mp) { maxi.push_back({x.second, x.first}); } sort(maxi.rbegin(), maxi.rend()); int mm = min(4, int((maxi).size())); for (int q = 0; q < mm; q++) { vector<int> v(m, 0); int cnt = 0; for (int i = 0; i < m; i++) { if (pp[i].first == maxi[q].second || pp[i].second == maxi[q].second) { v[i] = 1; cnt++; } } cnt = m - cnt; if (cnt == 0) { cout << YES ; exit(0); } mp.clear(); for (int i = 0; i < m; i++) { if (v[i] == 0) { if (pp[i].first != pp[i].second) { mp[pp[i].first]++; mp[pp[i].second]++; } else mp[pp[i].first]++; } } for (auto x : mp) { if (x.second == cnt) { cout << YES ; exit(0); } } } cout << NO ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INV_M_V
`define SKY130_FD_SC_LP__INV_M_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__inv_m (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__inv_m (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__INV_M_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:26:57 02/28/2016
// Design Name: Pc
// Module Name: C:/Users/Ranolazine/Desktop/Lab/lab5/test_Pc.v
// Project Name: lab5
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Pc
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_Pc;
// Inputs
reg clock_in;
reg [31:0] nextPC;
// Outputs
wire [31:0] currPC;
// Instantiate the Unit Under Test (UUT)
Pc uut (
.clock_in(clock_in),
.nextPC(nextPC),
.currPC(currPC)
);
always #10 clock_in = ~clock_in;
initial begin
// Initialize Inputs
clock_in = 0;
nextPC = 0;
// Wait 100 ns for global reset to finish
#105;
// Add stimulus here
nextPC = 32'b00000000000000000000000000001111;
#15;
nextPC = 32'b00000000000000000000000000011011;
#20;
nextPC = 32'b00000000000111111111111100011011;
end
endmodule
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_sysid_qsys (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? : ;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1000000; const int INF = 1000000001; vector<int> G[MAXN + 1]; bool vis[MAXN + 1]; vector<int> CC; int n, m, k; int dfs(int v) { vis[v] = true; int ret = 1; for (__typeof((G[v]).begin()) u = (G[v]).begin(); u != (G[v]).end(); ++u) if (!vis[*u]) ret += dfs(*u); return ret; } int main(int argc, char *argv[]) { scanf( %d %d %d , &n, &m, &k); while (m--) { int a, b; scanf( %d %d , &a, &b); G[a].push_back(b); G[b].push_back(a); } int t = 0; int s = 0; for (int i = 1; i <= n; ++i) if (!vis[i]) CC.push_back(min(k, dfs(i))), t += CC.back() == 1 ? 0 : CC.back(), s += CC.back() != 1; t = t - 2 * s + 2; if (k == 1) printf( %d n , max(0, (int)CC.size() - 2)); else printf( %d n , (max(0, ((int)CC.size() - s) - t + 1)) / 2); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUXB4TO1_4_V
`define SKY130_FD_SC_HDLL__MUXB4TO1_4_V
/**
* muxb4to1: Buffered 4-input multiplexer.
*
* Verilog wrapper for muxb4to1 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__muxb4to1.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__muxb4to1_4 (
Z ,
D ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input [3:0] D ;
input [3:0] S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__muxb4to1 base (
.Z(Z),
.D(D),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__muxb4to1_4 (
Z,
D,
S
);
output Z;
input [3:0] D;
input [3:0] S;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__muxb4to1 base (
.Z(Z),
.D(D),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUXB4TO1_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O32AI_PP_SYMBOL_V
`define SKY130_FD_SC_HD__O32AI_PP_SYMBOL_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o32ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O32AI_PP_SYMBOL_V
|
/*
* Copyright (C) 2017 Harmon Instruments, LLC
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/
*
*/
`timescale 1ns / 1ps
// divide a double precision float by 3e9 0x41E65A0BC0000000
// 63: sign, 62:52 exponent with bias of 1023, 51:0 mantissa
//
module div_3e9
(
input c,
input [62:0] i, // double float without sign bit
input iv,
output reg [62:0] o,
output reg [10:0] oe,
output reg ov = 0);
reg [53:0] sr;
reg [6:0] state = 0;
wire [53:0] sub = sr - 54'h165A0BC0000000;
always @ (posedge c)
begin
if(iv)
oe <= i[62:52] - (1023+31);
else if(state == 64)
oe <= o[62] ? oe : oe-1'b1;
if(iv)
state <= 1'b1;
else if(state == 64)
state <= 1'b0;
else
state <= state + (state != 0);
if(iv)
sr <= {2'b01,i[51:0]};
else
sr <= sub[53] ? {sr[52:0],1'b0} : {sub[52:0],1'b0};
if(state == 64)
o <= o[62] ? o : {o[61:0],1'b0};
else if(state != 0)
o <= {o[61:0], ~sub[53]};
ov <= (state == 64);
end
initial
begin
$dumpfile("dump.vcd");
$dumpvars(0);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 60; long long fib[MAXN]; int main() { int n; long long k; cin >> n >> k; fib[0] = 1; fib[1] = 1; for (int i = 2; i <= n; i++) fib[i] = fib[i - 1] + fib[i - 2]; int i = 0; while (i < n) { if (fib[n - i - 1] < k) { k -= fib[n - i - 1]; cout << i + 2 << << i + 1 << ; i += 2; } else { cout << i + 1 << ; i++; } } cout << endl; } |
#include<bits/stdc++.h> using namespace std; #define int long long int32_t main() { int t; cin >> t; while(t--) { string s; int n; cin >> n; cin >> s; sort(s.begin(),s.end()); cout << s << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long a; int b = 1; bool check(long long x) { if (x < 0) x = -x; while (x) { if (x % 10 == 8) return 1; x /= 10; } return 0; } int main() { scanf( %lld , &a); while (!check(a + b)) ++b; printf( %d , b); } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> a(n); int even = 0, odd = 0; for (int i = 0; i < n; i++) { cin >> a[i]; if (a[i] % 2 == 0) { even++; } else { odd++; } } if (even > odd) { cout << odd << endl; } else { cout << even << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); vector<long> A; long N, L, R, M, T, Sum, Min = 2147483647; cin >> N; A.resize(N); for (long i = 0; i < N; ++i) cin >> A[i]; for (long M = 1; M <= 100; ++M) { Sum = 0; for (long i = 0; i < N; ++i) Sum += min(min(abs(A[i] - M + 1), abs(A[i] - M - 1)), abs(A[i] - M)); if (Sum < Min) { Min = Sum; T = M; } } cout << T << << Min; return 0; } |
#include <bits/stdc++.h> using namespace std; const int NMax = 110000; struct edge { int num; edge *next; } * G[NMax], pool[NMax * 2]; int N, M, K, cant[NMax], L, deg[NMax], cnt[NMax], del[NMax], cur[NMax]; void Build(int x, int y) { edge *p = &pool[L++], *q = &pool[L++]; p->num = y; p->next = G[x]; G[x] = p; q->num = x; q->next = G[y]; G[y] = q; } void DFS(int a, long double k) { for (edge *p = G[a]; p; p = p->next) if (!del[p->num]) cur[p->num]--; for (edge *p = G[a]; p; p = p->next) if (!del[p->num]) { if ((long double)cur[p->num] / (long double)deg[p->num] < k) { del[p->num] = 1; DFS(p->num, k); } } } int main() { scanf( %d%d%d , &N, &M, &K); for (int i = 1; i <= K; i++) { int x; scanf( %d , &x); cant[x] = 1; } for (int i = 1; i <= M; i++) { int x, y; scanf( %d%d , &x, &y); Build(x, y); deg[x]++; deg[y]++; } for (int i = 1; i <= N; i++) if (!cant[i]) for (edge *p = G[i]; p; p = p->next) if (!cant[p->num]) cnt[i]++; long double l = -1e-4f, r = 1.0; while (l + 1e-6f < r) { long double mid = (l + r) / 2; for (int i = 1; i <= N; i++) del[i] = cant[i], cur[i] = cnt[i]; for (int i = 1; i <= N; i++) if (!del[i]) { if ((long double)cur[i] / (long double)deg[i] < mid) { del[i] = 1; DFS(i, mid); } } int flag = 0; for (int i = 1; i <= N; i++) if (!del[i]) flag = 1; if (flag) l = mid; else r = mid; } for (int i = 1; i <= N; i++) del[i] = cant[i], cur[i] = cnt[i]; for (int i = 1; i <= N; i++) if (!del[i]) { if ((long double)cur[i] / (long double)deg[i] < l) { del[i] = 1; DFS(i, l); } } int ans = 0; for (int i = 1; i <= N; i++) if (!del[i]) ans++; printf( %d n , ans); for (int i = 1; i <= N; i++) if (!del[i]) printf( %d , i); puts( ); getchar(); getchar(); return 0; } |
#include <bits/stdc++.h> using namespace std; char a[100100]; int main() { scanf( %s , a); int en; int len = strlen(a); int r = 0, l = 0; int ll, rr; int flag = 0; int last; int cnt = 0; for (int i = 0; a[i] != 0 ; i++) if (a[i] == # ) en = i; for (int i = 0; i < len; i++) { if (a[i] == ( ) l++; else { r++; if (a[i] == # ) cnt++; } if (r > l) { flag = 1; break; } if (i == en) ll = l, rr = r; } last = l - r + 1; rr += last - 1; if (ll < rr) flag = 1; for (int i = en + 1; i < len; i++) { if (a[i] == ( ) ll++; else rr++; if (rr > ll) { flag = 1; break; } } if (rr != ll) flag = 1; if (flag) puts( -1 ); else { for (int i = 0; i < cnt - 1; i++) puts( 1 ); printf( %d n , last); } } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int tc; cin >> tc; while (tc-- > 0) { long long int n; cin >> n; if (n % 2 == 0) { long long int a = 2; long long int b = n / 2; cout << a << << b << n ; } else { cout << 2 << << n - 1 << n ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long N = 1e3 + 5; long long n, m, c, cur, loc; long long a[N]; void work() { long long lim = c / 2 + c % 2; if (cur > lim) { for (long long i = n; i >= 1; i--) { if (cur > a[i] || !a[i]) { loc = i; return; } } loc = 1; return; } else { for (long long i = 1; i <= n; i++) { if (cur < a[i] || !a[i]) { loc = i; return; } } loc = n; return; } } bool check() { for (long long i = 1; i <= n; i++) { if (!a[i]) return 0; } for (long long i = 2; i <= n; i++) { if (a[i] < a[i - 1]) return 0; } return 1; } int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cin >> n >> m >> c; for (long long i = 1; i <= m; i++) { cin >> cur; work(); a[loc] = cur; cout << loc << endl; if (check()) { return 0; } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DFSTP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__DFSTP_BLACKBOX_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__dfstp (
Q ,
CLK ,
D ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DFSTP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; double safe_sqrt(double x) { return sqrt(max((double)0.0, x)); } long long GI(long long& x) { return scanf( %lld , &x); } const long long MOD = 1e9 + 7; const long long MN = 1000111; long long gt[MN]; vector<long long> h[MN]; int main() { ios::sync_with_stdio(0); cin.tie(0); cout << (fixed) << setprecision(9); const long long MOD = 1e9 + 7; gt[0] = 1; for (long long i = (1), _b = (MN - 1); i <= _b; ++i) gt[i] = gt[i - 1] * i % MOD; long long n, m; while (GI(n) == 1 && GI(m) == 1) { for (long long i = (1), _b = (m); i <= _b; ++i) h[i].clear(); for (long long i = (1), _b = (n); i <= _b; ++i) { long long k; GI(k); while (k--) { long long u; GI(u); h[u].push_back(i); } } sort(h + 1, h + m + 1); long long i = 1; long long res = 1; while (i <= m) { long long j = i; while (j < m && h[j + 1] == h[i]) j++; res = res * gt[j - i + 1] % MOD; i = j + 1; } cout << res << endl; } } |
#include <bits/stdc++.h> using namespace std; using INT = long long; const int NN = 202020; int a[NN], b[NN]; map<int, int> mp; int main() { int n, y; cin >> n >> y; for (int i = 1; i <= n; i++) cin >> a[i]; int m, yy; cin >> m >> yy; for (int i = 1; i <= m; i++) cin >> b[i]; int ans = 2; for (int bt = 0; bt < 30; bt++) { int d = (1 << bt); mp.clear(); for (int i = 1; i <= n; i++) { int ha = a[i] % (2 * d); mp[ha]++; ans = max(ans, mp[ha]); } for (int i = 1; i <= m; i++) { int ha = (b[i] + d) % (2 * d); mp[ha]++; ans = max(ans, mp[ha]); } } cout << ans; } |
module top;
reg pass = 1'b1;
parameter parm = 1;
/***********
* Check generate tasks.
***********/
// Only one is created.
generate
if (parm) begin: name_ti
task name_task;
$display("OK in task from scope name_ti");
endtask
end else begin: name_ti
task name_task;
begin
$display("FAILED in task from scope name_ti");
pass = 1'b0;
end
endtask
end
endgenerate
// Again only one is created.
generate
case (parm)
1: begin: name_tc
task name_task;
$display("OK in task from scope name_tc");
endtask
end
default: begin: name_tc
task name_task;
begin
$display("FAILED in task from scope name_tc");
pass = 1'b0;
end
endtask
end
endcase
endgenerate
// Two are created, but they are in a different scope.
genvar lpt;
generate
for (lpt = 0; lpt < 2; lpt = lpt + 1) begin: name_tf
task name_task;
$display("OK in task from scope name_tf[%0d]", lpt);
endtask
end
endgenerate
/***********
* Check functions.
***********/
// Only one is created.
generate
if (parm) begin: name_fi
function name_func;
input in;
name_func = ~in;
endfunction
end else begin: name_fi
function name_func;
input in;
name_func = in;
endfunction
end
endgenerate
// Again only one is created.
generate
case (parm)
1: begin: name_fc
function name_func;
input in;
name_func = ~in;
endfunction
end
default: begin: name_fc
function name_func;
input in;
name_func = in;
endfunction
end
endcase
endgenerate
// Two are created, but they are in a different scope.
genvar lpf;
generate
for (lpf = 0; lpf < 2; lpf = lpf + 1) begin: name_ff
function name_func;
input in;
name_func = (lpf % 2) ? in : ~in ;
endfunction
end
endgenerate
initial begin
name_ti.name_task;
name_tc.name_task;
name_tf[0].name_task;
name_tf[1].name_task;
if (name_fi.name_func(1'b1) !== 1'b0) begin
$display("FAILED in function from scope name_fi");
pass = 1'b0;
end else $display("OK in function from scope name_fi");
if (name_fc.name_func(1'b1) !== 1'b0) begin
$display("FAILED in function from scope name_fc");
pass = 1'b0;
end else $display("OK in function from scope name_fc");
if (name_ff[0].name_func(1'b1) !== 1'b0) begin
$display("FAILED in function from scope name_ff[0]");
pass = 1'b0;
end else $display("OK in function from scope name_ff[0]");
if (name_ff[1].name_func(1'b1) !== 1'b1) begin
$display("FAILED in function from scope name_ff[1]");
pass = 1'b0;
end else $display("OK in function from scope name_ff[1]");
if (pass) $display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct node { int to; int l, r; node() {} node(int to, int l, int r) : to(to), l(l), r(r) {} }; struct node1 { int l, r; node1() {} node1(int l, int r) : l(l), r(r) {} }; vector<node> G[1010]; vector<node1> Q[1010]; int n, m, ans = 0; bool book[1010], came[1010]; void init() { for (int i = 1; i <= n; i++) { G[i].clear(); Q[i].clear(); } } void add(int u, int v, int l, int r) { G[u].push_back(node(v, l, r)); G[v].push_back(node(u, l, r)); } void dfs(int cur, int le, int ri) { if (book[cur]) return; if (cur == n) { ans = max(ans, ri - le + 1); return; } if (ans >= ri - le + 1) return; book[cur] = 1; for (int i = 0; i < G[cur].size(); i++) { node tmp = G[cur][i]; int newl = max(le, G[cur][i].l); int newr = min(ri, G[cur][i].r); if (newl > newr) continue; int flag = 1; for (int j = 0; j < Q[tmp.to].size(); j++) { if (Q[tmp.to][j].l <= newl && Q[tmp.to][j].r >= newr) { flag = 0; break; } } if (flag) { Q[tmp.to].push_back(node1(newl, newr)); dfs(tmp.to, newl, newr); } } book[cur] = 0; } int main() { scanf( %d%d , &n, &m); init(); for (int i = 1; i <= m; i++) { int u, v, l, r; scanf( %d%d%d%d , &u, &v, &l, &r); add(u, v, l, r); } ans = 0; memset(book, 0, sizeof(book)); memset(came, 0, sizeof(came)); dfs(1, 0, 1000000 + 10); if (ans) printf( %d n , ans); else printf( Nice work, Dima! n ); } |
//See README and tcl for more info
`include "defines.v"
module roi(input clk,
input [DIN_N-1:0] din, output [DOUT_N-1:0] dout);
parameter DIN_N = `DIN_N;
parameter DOUT_N = `DOUT_N;
genvar i;
generate
//CLK
(* KEEP, DONT_TOUCH *)
reg clk_reg;
always @(posedge clk) begin
clk_reg <= clk_reg;
end
//DIN
for (i = 0; i < DIN_N; i = i+1) begin:ins
(* KEEP, DONT_TOUCH *)
LUT6 #(
.INIT(64'b01)
) lut (
.I0(din[i]),
.I1(1'b0),
.I2(1'b0),
.I3(1'b0),
.I4(1'b0),
.I5(1'b0),
.O());
end
//DOUT
for (i = 0; i < DOUT_N; i = i+1) begin:outs
(* KEEP, DONT_TOUCH *)
LUT6 #(
.INIT(64'b01)
) lut (
.I0(1'b0),
.I1(1'b0),
.I2(1'b0),
.I3(1'b0),
.I4(1'b0),
.I5(1'b0),
.O(dout[i]));
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; bool prime[101]; void SieveOfEratosthenes(int n) { memset(prime, true, sizeof(prime)); for (int p = 2; p * p <= n; p++) { if (prime[p] == true) { for (int i = p * p; i <= n; i += p) prime[i] = false; } } } int main() { long long n, m; cin >> n; long long c[n + 1]; if (n % 2 != 0) { cout << -1; return 0; } for (long long i = 1; i <= n; i++) { c[i] = i; } for (long long i = 1; i <= n; i += 2) { swap(c[i], c[i + 1]); } for (long long i = 1; i <= n; i++) { cout << c[i] << ; } } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun Apr 09 07:04:52 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_inverter_0_0/system_inverter_0_0_sim_netlist.v
// Design : system_inverter_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_inverter_0_0,inverter,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "inverter,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_inverter_0_0
(x,
x_not);
input x;
output x_not;
wire x;
wire x_not;
LUT1 #(
.INIT(2'h1))
x_not_INST_0
(.I0(x),
.O(x_not));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9; const int N = 100200; struct Node { int to, cost; }; vector<Node> g[N]; int dist[105][N] = {}, arr[N] = {}, n, m, type[N] = {}, k, s, vis[N] = {}; void addedge(int u, int v, int cost) { g[u].push_back((Node){v, cost}); g[v].push_back((Node){u, cost}); } void bfs(int s, int n, int* d) { queue<int> que; memset(vis, 0, sizeof(vis)); int p, to, cost; que.push(s); vis[s] = 1; while (!que.empty()) { p = que.front(); que.pop(); const int sz = g[p].size(); for (int i = 0; i < sz; i++) { to = g[p][i].to; if (to > n - 1 || vis[to]) continue; d[to] = d[p] + 1; que.push(to); vis[to] = 1; } } } int main(void) { std::ios::sync_with_stdio(false); cin >> n >> m >> k >> s; for (int i = 0; i < n; i++) cin >> type[i]; int u, v; for (int i = 0; i < m; i++) { cin >> u >> v; u--; v--; addedge(u, v, 1); } for (int i = 0; i < n; i++) { addedge(n - 1 + type[i], i, 1); } for (int i = 1; i <= k; i++) { bfs(n - 1 + i, n, dist[i]); } for (int i = 0; i < n; i++) { int ans = 0; for (int j = 1; j <= k; j++) arr[j] = dist[j][i] - 1; sort(arr + 1, arr + k + 1); for (int i = 1; i <= s; i++) ans += arr[i]; cout << ans << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> void Read(T &cn) { char c; int sig = 1; while (!isdigit(c = getchar())) if (c == - ) sig = -1; cn = c - 48; while (isdigit(c = getchar())) cn = cn * 10 + c - 48; cn *= sig; } template <typename T> void Write(T cn) { if (cn < 0) { putchar( - ); cn = 0 - cn; } int wei = 0; T cm = 0; int cx = cn % 10; cn /= 10; while (cn) cm = cm * 10 + cn % 10, cn /= 10, wei++; while (wei--) putchar(cm % 10 + 48), cm /= 10; putchar(cx + 48); } int f[500 / 2 + 1][500 + 1][500 + 1]; int n, m, q; int a[500 + 1][500 + 1]; int b[500 + 1][500 + 1]; int jian_c(int cn, int cm, int cx) { if (a[cn - cx + 1][cm - cx + 1] != R || b[cn - cx + 1][cm - cx + 1] != cx) return 0; if (a[cn - cx + 1][cm + 1] != G || b[cn - cx + 1][cm + 1] != cx) return 0; if (a[cn + 1][cm - cx + 1] != Y || b[cn + 1][cm - cx + 1] != cx) return 0; if (a[cn + 1][cm + 1] != B || b[cn + 1][cm + 1] < cx) return 0; return 1; } void jian(int cn, int cm) { int lin = min(min(cn, cm), min(n - cn, m - cm)); for (int i = 1; i <= lin; i++) { if (!jian_c(cn, cm, i)) return; f[i][cn - i + 1][cm - i + 1] = 1; } } void yuchu() { for (int i = 1; i <= n; i++) b[i][m] = 1; for (int i = 1; i <= m; i++) b[n][i] = 1; for (int i = n - 1; i >= 1; i--) for (int j = m - 1; j >= 1; j--) { if (a[i][j] == a[i + 1][j + 1] && a[i][j] == a[i + 1][j] && a[i][j] == a[i][j + 1]) b[i][j] = 1 + min(min(b[i + 1][j], b[i][j + 1]), b[i + 1][j + 1]); else b[i][j] = 1; } } int suan(int cn, int cx1, int cy1, int cx2, int cy2) { return f[cn][cx2][cy2] - f[cn][cx2][cy1] - f[cn][cx1][cy2] + f[cn][cx1][cy1]; } int main() { Read(n); Read(m); Read(q); for (int i = 1; i <= n; i++) { while (!isalpha(a[i][1] = getchar())) ; for (int j = 2; j <= m; j++) a[i][j] = getchar(); } yuchu(); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) jian(i, j); for (int ij = 1; ij <= n / 2; ij++) for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) f[ij][i][j] = f[ij][i - 1][j] + f[ij][i][j - 1] - f[ij][i - 1][j - 1] + f[ij][i][j]; for (int i = 1; i <= q; i++) { int bx1, by1, bx2, by2; Read(bx1); Read(by1); Read(bx2); Read(by2); int ans = 0; int lin = (min(bx2 - bx1, by2 - by1) + 1) / 2; for (int j = lin; j >= 1; j--) if (suan(j, bx1 - 1, by1 - 1, bx2 - j * 2 + 1, by2 - j * 2 + 1)) { ans = 4 * j * j; break; } Write(ans); puts( ); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__TAPVGND_TB_V
`define SKY130_FD_SC_HDLL__TAPVGND_TB_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection
* 1 row down.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__tapvgnd.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_hdll__tapvgnd dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__TAPVGND_TB_V
|
#include <bits/stdc++.h> #pragma warning(disable : 4996) using namespace std; int n, m; struct GUGAN { int s, e; int type; int idx, x; bool operator<(const GUGAN &p) const { return e < p.e; } GUGAN() {} GUGAN(int s, int e, int type, int idx, int x) { this->s = s, this->e = e, this->type = type, this->idx = idx, this->x = x; } }; bool cmp(GUGAN p, GUGAN q) { if (p.s != q.s) return p.s < q.s; return p.type < q.type; } vector<GUGAN> v; multiset<GUGAN> s; int dab[200000]; int main() { int i, j, k; scanf( %d , &n); for (i = 0; i < n; i++) { int x, y; scanf( %d%d , &x, &y); v.push_back(GUGAN(x, y, 2, i, -1)); } scanf( %d , &m); for (i = 0; i < m; i++) { int x, y, z; scanf( %d%d%d , &x, &y, &z); v.push_back(GUGAN(x, y, 1, i, z)); } sort(v.begin(), v.end(), cmp); for (auto e : v) { if (e.type == 1) s.insert(e); else { auto it = s.lower_bound(GUGAN(0, e.e, 0, 0, 0)); if (it == s.end()) return printf( NO ), 0; GUGAN u = *it; s.erase(it); u.x--; dab[e.idx] = u.idx; if (u.x != 0) s.insert(u); } } printf( YES n ); for (i = 0; i < n; i++) printf( %d , dab[i] + 1); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A221O_FUNCTIONAL_V
`define SKY130_FD_SC_HS__A221O_FUNCTIONAL_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a221o (
VPWR,
VGND,
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
// Local signals
wire B2 and0_out ;
wire B2 and1_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X , and1_out, and0_out, C1);
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND );
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A221O_FUNCTIONAL_V |
//#############################################################################
//# Function: Achive high latch #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_lat1 #(parameter DW = 1 //data width
)
( input clk, // clk, latch when clk=1
input [DW-1:0] in, // input data
output [DW-1:0] out // output data (stable/latched when clk=0)
);
localparam ASIC = `CFG_ASIC; // use ASIC lib
generate
if(ASIC)
begin : g0
asic_lat1 i_lat [DW-1:0] (.clk(clk),
.in(in[DW-1:0]),
.out(out[DW-1:0]));
end
else
begin : g0
reg [DW-1:0] out_reg;
always @ (clk or in)
if (clk)
out_reg[DW-1:0] <= in[DW-1:0];
assign out[DW-1:0] = out_reg[DW-1:0];
end
endgenerate
endmodule // oh_lat1
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FAHCIN_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__FAHCIN_PP_BLACKBOX_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__fahcin (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__FAHCIN_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { string a, b; cin >> a >> b; if (a == b) { cout << a; } else { cout << 1; } } |
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; long long dp[57 + 7][57 + 7]; long long mdp[57 + 7][57 + 7]; bool vis[57 + 7][57 + 7]; int n, K; long long ncr[57 + 7][57 + 7]; int L, R; long long func(int l, int r, int i, int j, int k, int m) { long long ret = (ncr[l][i] * ncr[r][j]) % mod; ret = (ret * ncr[L - l + i][k]) % mod; ret = (ret * ncr[R - r + j][m]) % mod; return ret; } void back(int l, int r) { if (vis[l][r]) return; mdp[l][r] = 200000007; dp[l][r] = 0; vis[l][r] = true; if (l == 0 && r == 0) { mdp[l][r] = 0; dp[l][r] = 1; return; } if (l * 50 + r * 100 <= K) { mdp[l][r] = 1; dp[l][r] = 1; return; } for (int i = 0; i <= l && i * 50 <= K; i++) { for (int j = 0; j <= r; j++) { if (i == 0 && j == 0) continue; if (i * 50 + j * 100 > K) break; for (int k = 0; k <= L - l + i; k++) { for (int m = 0; m <= R - r + j; m++) { if (k * 50 + m * 100 == 0) continue; if (k * 50 + m * 100 > K) break; if (l * 50 + r * 100 <= (l - i + k) * 50 + (r - j + m) * 100) continue; back(l - (i - k), r - (j - m)); mdp[l][r] = min(mdp[l][r], mdp[l - i + k][r - j + m] + 2); } } } } for (int i = 0; i <= l && i * 50 <= K; i++) { for (int j = 0; j <= r; j++) { if (i == 0 && j == 0) continue; if (i * 50 + j * 100 > K) break; for (int k = 0; k <= L - l + i; k++) { for (int m = 0; m <= R - r + j; m++) { if (k * 50 + m * 100 == 0) continue; if (k * 50 + m * 100 > K) break; if (l * 50 + r * 100 <= (l - i + k) * 50 + (r - j + m) * 100) continue; if (mdp[l - i + k][r - j + m] + 2 == mdp[l][r]) { dp[l][r] += (func(l, r, i, j, k, m) * dp[l - i + k][r - j + m]) % mod; dp[l][r] %= mod; } } } } } } int main() { ncr[0][0] = 1; for (int i = 1; i <= 57; i++) { ncr[i][0] = 1; ncr[i][i] = 1; ncr[i][1] = i; } for (int i = 2; i <= 57; i++) { for (int j = 2; j < i; j++) { ncr[i][j] = (ncr[i - 1][j - 1] + ncr[i - 1][j]) % mod; } } scanf( %d%d , &n, &K); int l = 0; int r = 0; for (int i = 1; i <= n; i++) { int v; scanf( %d , &v); if (v == 50) l++; else r++; } L = l; R = r; back(l, r); if (mdp[l][r] != 200000007) { printf( %d n , (int)mdp[l][r]); printf( %d n , (int)dp[l][r]); } else { printf( -1 n0 n ); } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:14:32 03/19/2015
// Design Name:
// Module Name: fsm
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module fsm(
input clk,
input rst,
input send,
input [7:0] data,
output txd
);
localparam STATE1 = 2'b00;
localparam STATE2 = 2'b01;
localparam STATE3 = 2'b10;
localparam STATE4 = 2'b11;
reg [1:0] state = STATE1;
reg [7:0] tmp_data;
reg last_send_val = 1'b0;
reg [2:0] current_bit;
reg d = 1'b0;
always @(posedge clk)
begin
if(rst)
begin
d <= 0;
state <= STATE1;
end
case(state)
STATE1:
begin
if(send == 1 & last_send_val == 0)
begin
tmp_data <= data;
current_bit <= 3'b000;
state <= STATE2;
end
end
STATE2:
begin
d <= 1'b1;
state <= STATE3;
end
STATE3:
begin
d <= tmp_data[current_bit];
current_bit <= current_bit + 1;
if(current_bit == 3'b111) state <= STATE4; // wszystkie bity wysano
end
STATE4:
begin
d <= 1'b0;
state <= STATE1;
end
endcase
last_send_val <= send;
end
assign txd = d;
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; using ll = long long; using ld = long double; using pi = pair<int, int>; using pl = pair<ll, ll>; using vi = vector<int>; using vl = vector<ll>; using vpi = vector<pi>; using si = set<int>; using sl = set<ll>; using qi = queue<int>; using ql = queue<ll>; template <class T> bool uin(T& a, T b) { return a > b ? (a = b, true) : false; } template <class T> bool uax(T& a, T b) { return a < b ? (a = b, true) : false; } template <class T> bool uin(T& u, T& v, T a, T b) { return v - u > b - a ? (u = a, v = b, true) : false; } template <class T> bool uax(T& u, T& v, T a, T b) { return v - u < b - a ? (u = a, v = b, true) : false; } namespace input { template <class T> void re(complex<T>& x); template <class T1, class T2> void re(pair<T1, T2>& p); template <class T> void re(vector<T>& a); template <class T, size_t SZ> void re(array<T, SZ>& a); template <class T> void re(T& x) { cin >> x; } void re(double& x) { string t; re(t); x = stod(t); } void re(ld& x) { string t; re(t); x = stold(t); } template <class T, class... Ts> void re(T& t, Ts&... ts) { re(t); re(ts...); } template <class T> void re(complex<T>& x) { T a, b; re(a, b); x = cd(a, b); } template <class T1, class T2> void re(pair<T1, T2>& p) { re(p.f, p.s); } template <class T> void re(vector<T>& a) { for (int i = 0; i < (((int)(a).size())); ++i) re(a[i]); } template <class T, size_t SZ> void re(array<T, SZ>& a) { for (int i = 0; i < (SZ); ++i) re(a[i]); } } // namespace input using namespace input; namespace output { void pr(int x) { cout << x; } void pr(long x) { cout << x; } void pr(ll x) { cout << x; } void pr(unsigned x) { cout << x; } void pr(unsigned long x) { cout << x; } void pr(unsigned long long x) { cout << x; } void pr(float x) { cout << x; } void pr(double x) { cout << x; } void pr(ld x) { cout << x; } void pr(char x) { cout << x; } void pr(const char* x) { cout << x; } void pr(const string& x) { cout << x; } void pr(bool x) { pr(x ? true : false ); } template <class T> void pr(const complex<T>& x) { cout << x; } template <class T1, class T2> void pr(const pair<T1, T2>& x); template <class T> void pr(const T& x); template <class T, class... Ts> void pr(const T& t, const Ts&... ts) { pr(t); pr(ts...); } template <class T1, class T2> void pr(const pair<T1, T2>& x) { pr( { , x.f, , , x.s, } ); } template <class T> void pr(const T& x) { pr( { ); bool fst = 1; for (const auto& a : x) pr(!fst ? , : , a), fst = 0; pr( } ); } void ps() { pr( n ); } template <class T, class... Ts> void ps(const T& t, const Ts&... ts) { pr(t); if (sizeof...(ts)) pr( ); ps(ts...); } void pc() { pr( ] n ); } template <class T, class... Ts> void pc(const T& t, const Ts&... ts) { pr(t); if (sizeof...(ts)) pr( , ); pc(ts...); } } // namespace output using namespace output; inline int bs(bool (*valid)(int), int l, int r, bool order) { l--, r++; if (!order) swap(l, r); while (abs(r - l) > 1) { int mid = (l + r) >> 1; if (valid(mid)) r = mid; else l = mid; } valid(r); return r; } struct dsu { vector<int> p; dsu(int n) { p.resize(n + 1); } inline int get(int x) { return p[x] ? p[x] = get(p[x]) : x; } inline bool mrg(int x, int y) { return get(x) == get(y) ? false : p[get(x)] = get(y); } }; const int M = 1e9 + 7; const ll lnf = 1e18 + 3; const int inf = 1e9 + 3; const int nax = 1e6 + 5; typedef decay<decltype(M)>::type T; struct mi { T val; explicit operator T() const { return val; } mi() { val = 0; } mi(const ll& v) { val = (-M <= v && v <= M) ? v : v % M; if (val < 0) val += M; } friend void pr(const mi& a) { pr(a.val); } friend void re(mi& a) { ll x; re(x); a = mi(x); } friend bool operator==(const mi& a, const mi& b) { return a.val == b.val; } friend bool operator!=(const mi& a, const mi& b) { return !(a == b); } friend bool operator<(const mi& a, const mi& b) { return a.val < b.val; } mi operator-() const { return mi(-val); } mi& operator+=(const mi& m) { if ((val += m.val) >= M) val -= M; return *this; } mi& operator-=(const mi& m) { if ((val -= m.val) < 0) val += M; return *this; } mi& operator*=(const mi& m) { val = (ll)val * m.val % M; return *this; } friend mi pow(mi a, ll p) { mi ans = 1; assert(p >= 0); for (; p; p /= 2, a *= a) if (p & 1) ans *= a; return ans; } friend mi inv(const mi& a) { assert(a != 0); return pow(a, M - 2); } mi& operator/=(const mi& m) { return (*this) *= inv(m); } friend mi operator+(mi a, const mi& b) { return a += b; } friend mi operator-(mi a, const mi& b) { return a -= b; } friend mi operator*(mi a, const mi& b) { return a *= b; } friend mi operator/(mi a, const mi& b) { return a /= b; } }; vi invs, fac, ifac; void genFac(int SZ) { invs.resize(SZ), fac.resize(SZ), ifac.resize(SZ); invs[1] = fac[0] = ifac[0] = 1; for (int i = (2); i <= (SZ - 1); ++i) invs[i] = M - (ll)M / i * invs[M % i] % M; for (int i = (1); i <= (SZ - 1); ++i) { fac[i] = (ll)fac[i - 1] * i % M; ifac[i] = (ll)ifac[i - 1] * invs[i] % M; } } ll comb(int a, int b) { if (a < b || b < 0) return 0; return (ll)fac[a] * ifac[b] % M * ifac[a - b] % M; } ll p[nax], s, c; int t, n, q[nax]; int main() { ios_base::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); re(n); vl a(n); re(a); for (int i = 0; i < (n); ++i) { s = a[i], c = 1; while (t && p[t] * c >= s * q[t]) s += p[t], c += q[t--]; p[++t] = s, q[t] = c; } cout << setprecision(10); for (int i = (1); i <= (t); ++i) for (int j = 0; j < (q[i]); ++j) cout << (double)p[i] / q[i] << n ; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:31:25 05/26/2014
// Design Name:
// Module Name: mccomp
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mccomp (
input wire stp,rst,clk,
input wire [1:0] dptype,
input wire [4:0] regselect,
output wire exec,
output wire [5:0] initype,
output wire [3:0] node,
output wire [7:0] segment
);
wire clock,reset,resetn,mem_clk;
wire [31:0] a,b,alu,adr,tom,fromm,pc,ir,dpdata;
wire [2:0] q;
reg [15:0] digit,count=0;
wire wmem;
pbdebounce p0(clk,stp,clock);
always @(posedge clock) count=count+1;
pbdebounce p1(clk,rst,reset);
assign resetn=~reset;
assign mem_clk=clk;
mccpu mc_cpu (clock,resetn,fromm,pc,ir,a,b,alu,wmem,adr,tom,q,regselect,dpdata);
mcmem memory (adr[7:2],tom,mem_clk,wmem,fromm);
display dp(clk,digit,node,segment);
always @* begin
case (dptype)
2'b00:digit<=dpdata[15:0];
2'b01:digit<=dpdata[31:16];
2'b10:digit<=pc[15:0];
2'b11:digit<=count;
endcase
end
assign exec=clock;
assign initype=ir[31:26];
endmodule |
`include "bsg_mem_2r1w_sync_macros.vh"
module bsg_mem_2r1w_sync #( parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(els_p )
, parameter read_write_same_addr_p = 0
, parameter addr_width_lp = `BSG_SAFE_CLOG2(els_p)
, parameter harden_p = 1
, parameter substitute_2r1w_p = 0
)
( input clk_i
, input reset_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [width_p-1:0] w_data_i
, input r0_v_i
, input [addr_width_lp-1:0] r0_addr_i
, output logic [width_p-1:0] r0_data_o
, input r1_v_i
, input [addr_width_lp-1:0] r1_addr_i
, output logic [width_p-1:0] r1_data_o
);
wire unused = reset_i;
// TODO: Define more hardened macro configs here
`bsg_mem_2r1w_sync_macro(32,64,1) else
//`bsg_mem_2r1w_sync_macro(32,32,2) else
// no hardened version found
begin : z
if (substitute_2r1w_p)
begin: s2r1w
logic [width_p-1:0] r0_data_lo, r1_data_lo;
bsg_mem_2r1w #( .width_p(width_p)
, .els_p(els_p)
, .read_write_same_addr_p(0)
)
mem
(.w_clk_i (clk_i)
,.w_reset_i(reset_i)
,.w_v_i (w_v_i & w_v_i)
,.w_addr_i (w_addr_i)
,.w_data_i (w_data_i)
,.r0_v_i (r0_v_i & ~r0_v_i)
,.r0_addr_i(r0_addr_i)
,.r0_data_o(r0_data_lo)
,.r1_v_i (r1_v_i & ~r1_v_i)
,.r1_addr_i(r1_addr_i)
,.r1_data_o(r1_data_lo)
);
// register output data to convert sync to async
always_ff @(posedge clk_i) begin
r0_data_o <= r0_data_lo;
r1_data_o <= r1_data_lo;
end
end // block: s1r1w
else
begin: notmacro
bsg_mem_2r1w_sync_synth #(.width_p(width_p), .els_p(els_p), .read_write_same_addr_p(read_write_same_addr_p))
synth
(.*);
end // block: notmacro
end // block: z
//synopsys translate_off
always_ff @(posedge clk_i)
if (w_v_i)
begin
assert (w_addr_i < els_p)
else $error("Invalid address %x to %m of size %x\n", w_addr_i, els_p);
assert (~(r0_addr_i == w_addr_i && w_v_i && r0_v_i && !read_write_same_addr_p))
else $error("%m: port 0 Attempt to read and write same address");
assert (~(r1_addr_i == w_addr_i && w_v_i && r1_v_i && !read_write_same_addr_p))
else $error("%m: port 1 Attempt to read and write same address");
end
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d, read_write_same_addr_p=%d, harden_p=%d (%m)",width_p,els_p,read_write_same_addr_p,harden_p);
end
//synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_2r1w_sync)
|
#include <bits/stdc++.h> using namespace std; int main() { long long int x, y, l, r; cin >> x >> y >> l >> r; vector<long long int> vec(0); long long int xa = 1; long long int cap = 0; long long int r1 = r; while (r1 > 0) { r1 /= x; ++cap; } for (long long int i = 0; i < cap; ++i) { long long int ya = 1; long long int diff = r - xa; long long int cap2 = 0; while (diff > 0) { diff /= y; ++cap2; } for (long long int j = 0; j < cap2; ++j) { if (xa + ya >= l && xa + ya <= r) { vec.push_back(xa + ya); } ya *= y; } xa *= x; } if (vec.size() == 0) { cout << r - l + 1; return 0; } sort(vec.begin(), vec.end()); long long int answer = vec[0] - l; for (int i = 1; i < vec.size(); ++i) { if (vec[i] - vec[i - 1] - 1 > answer) answer = vec[i] - vec[i - 1] - 1; } if (r - vec[vec.size() - 1] > answer) answer = r - vec[vec.size() - 1]; cout << answer; } |
#include <bits/stdc++.h> using namespace std; const double eps = 1e-8; const double PI = acos(-1.); const int MXN = 200005; const int MOD = 1000000000; int a[MXN], n, m; long long fib[MXN]; long long prefib[MXN]; struct SEG { int l, r; long long lazy; long long g[2]; SEG() {} SEG(int _l, int _r) { l = _l, r = _r; } } SGT[MXN << 2]; void create(SEG &T, int t) { T.lazy = 0; T.g[0] = T.g[1] = a[t]; } void fresh(SEG &T, SEG &L, SEG &R) { int left = L.r - L.l + 1; T.lazy = 0; if (left == 1) { T.g[0] = (L.g[0] + R.g[1]) % MOD; T.g[1] = (L.g[0] + R.g[0] + R.g[1]) % MOD; return; } T.g[0] = (L.g[0] + fib[left - 2] * R.g[0] % MOD + fib[left - 1] * R.g[1] % MOD) % MOD; T.g[1] = (L.g[1] + fib[left - 1] * R.g[0] % MOD + fib[left] * R.g[1] % MOD) % MOD; } void build(int id, int l, int r) { SGT[id] = SEG(l, r); int mid = (l + r) / 2; if (l != r) { build(id * 2, l, mid); build(id * 2 + 1, mid + 1, r); fresh(SGT[id], SGT[id << 1], SGT[id << 1 | 1]); } else create(SGT[id], l); } void update(int id, int l, int r, long long w) { SEG &T = SGT[id]; int mid = (T.l + T.r) / 2; if (T.l == l && T.r == r) { T.lazy = (T.lazy + w) % MOD; T.g[0] = (T.g[0] + w * prefib[T.r - T.l] % MOD) % MOD; T.g[1] = (T.g[1] + w * (prefib[T.r - T.l + 1] - 1) % MOD) % MOD; return; } if (T.lazy) { update(id << 1, T.l, mid, T.lazy); update(id << 1 | 1, mid + 1, T.r, T.lazy); T.lazy = 0; } if (r <= mid) update(id << 1, l, r, w); else if (l > mid) update(id << 1 | 1, l, r, w); else { update(id << 1, l, mid, w); update(id << 1 | 1, mid + 1, r, w); } fresh(T, SGT[id << 1], SGT[id << 1 | 1]); } long long single(int id, int t) { SEG &T = SGT[id]; int mid = (T.l + T.r) / 2; if (T.l == T.r) return T.g[0]; if (t <= mid) return T.lazy + single(id << 1, t); else return T.lazy + single(id << 1 | 1, t); } void query(int id, SEG &A) { SEG &T = SGT[id]; int mid = (T.l + T.r) / 2; if (A.l == T.l && A.r == T.r) { A = T; return; } if (T.lazy && T.l != T.r) { update(id << 1, T.l, mid, T.lazy); update(id << 1 | 1, mid + 1, T.r, T.lazy); T.lazy = 0; } if (A.r <= mid) query(id << 1, A); else if (A.l > mid) query(id << 1 | 1, A); else { SEG L(A.l, mid), R(mid + 1, A.r); query(id << 1, L); query(id << 1 | 1, R); fresh(A, L, R); } } int main() { int i, j; fib[0] = 1; fib[1] = 1; for (i = 2; i < MXN; i++) fib[i] = (fib[i - 1] + fib[i - 2]) % MOD; prefib[0] = 1; for (i = 1; i < MXN; i++) prefib[i] = (prefib[i - 1] + fib[i]) % MOD; while (~scanf( %d%d , &n, &m)) { for (i = 1; i <= n; i++) scanf( %d , &a[i]); build(1, 1, n); while (m--) { int q; scanf( %d , &q); if (q == 1) { int x, v; scanf( %d%d , &x, &v); long long tp = single(1, x); update(1, x, x, v - tp); } if (q == 2) { int l, r; scanf( %d%d , &l, &r); SEG A(l, r); query(1, A); printf( %I64d n , ((A.g[0] % MOD) + MOD) % MOD); } if (q == 3) { int l, r, d; scanf( %d%d%d , &l, &r, &d); update(1, l, r, d); } } } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRBN_BEHAVIORAL_V
`define SKY130_FD_SC_HS__DLRBN_BEHAVIORAL_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dl_p_r_no_pg/sky130_fd_sc_hs__u_dl_p_r_no_pg.v"
`celldefine
module sky130_fd_sc_hs__dlrbn (
RESET_B,
D ,
GATE_N ,
Q ,
Q_N ,
VPWR ,
VGND
);
// Module ports
input RESET_B;
input D ;
input GATE_N ;
output Q ;
output Q_N ;
input VPWR ;
input VGND ;
// Local signals
wire RESET ;
wire intgate ;
reg notifier ;
wire D_delayed ;
wire GATE_N_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intgate, GATE_N_delayed );
sky130_fd_sc_hs__u_dl_p_r_no_pg u_dl_p_r_no_pg0 (buf_Q , D_delayed, intgate, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRBN_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; map<string, string> mp; int main() { string a, b; int n, m; cin >> n >> m; for (int i = 0; i < n; i++) { cin >> a >> b; mp[b] = a; } for (int i = 0; i < m; i++) { cin >> a >> b; b.pop_back(); cout << a << << b << ; # << mp[b] << endl; } return 0; } |
// niosii_nios2_gen2_0.v
// This file was auto-generated from altera_nios2_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module niosii_nios2_gen2_0 (
input wire clk, // clk.clk
input wire reset_n, // reset.reset_n
input wire reset_req, // .reset_req
output wire [17:0] d_address, // data_master.address
output wire [3:0] d_byteenable, // .byteenable
output wire d_read, // .read
input wire [31:0] d_readdata, // .readdata
input wire d_waitrequest, // .waitrequest
output wire d_write, // .write
output wire [31:0] d_writedata, // .writedata
output wire debug_mem_slave_debugaccess_to_roms, // .debugaccess
output wire [17:0] i_address, // instruction_master.address
output wire i_read, // .read
input wire [31:0] i_readdata, // .readdata
input wire i_waitrequest, // .waitrequest
input wire [31:0] irq, // irq.irq
output wire debug_reset_request, // debug_reset_request.reset
input wire [8:0] debug_mem_slave_address, // debug_mem_slave.address
input wire [3:0] debug_mem_slave_byteenable, // .byteenable
input wire debug_mem_slave_debugaccess, // .debugaccess
input wire debug_mem_slave_read, // .read
output wire [31:0] debug_mem_slave_readdata, // .readdata
output wire debug_mem_slave_waitrequest, // .waitrequest
input wire debug_mem_slave_write, // .write
input wire [31:0] debug_mem_slave_writedata, // .writedata
output wire dummy_ci_port // custom_instruction_master.readra
);
niosii_nios2_gen2_0_cpu cpu (
.clk (clk), // clk.clk
.reset_n (reset_n), // reset.reset_n
.reset_req (reset_req), // .reset_req
.d_address (d_address), // data_master.address
.d_byteenable (d_byteenable), // .byteenable
.d_read (d_read), // .read
.d_readdata (d_readdata), // .readdata
.d_waitrequest (d_waitrequest), // .waitrequest
.d_write (d_write), // .write
.d_writedata (d_writedata), // .writedata
.debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms), // .debugaccess
.i_address (i_address), // instruction_master.address
.i_read (i_read), // .read
.i_readdata (i_readdata), // .readdata
.i_waitrequest (i_waitrequest), // .waitrequest
.irq (irq), // irq.irq
.debug_reset_request (debug_reset_request), // debug_reset_request.reset
.debug_mem_slave_address (debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (debug_mem_slave_read), // .read
.debug_mem_slave_readdata (debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (debug_mem_slave_write), // .write
.debug_mem_slave_writedata (debug_mem_slave_writedata), // .writedata
.dummy_ci_port (dummy_ci_port) // custom_instruction_master.readra
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int length; cin >> length; int query; cin >> query; string result; cin >> result; for (int i = 0; i < query; ++i) { int left; int right; cin >> left >> right; char which; char what; cin >> which >> what; for (int j = left; j <= right; ++j) if (result[j - 1] == which) result[j - 1] = what; } cout << result; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); string s; cin >> s; int n = s.size(); bool dp[n + 1][8]; memset(dp, false, sizeof(dp)); string ans[8]; for (int i = 1; i < n + 1; i++) { string temp_ans[8]; dp[i][(s[i - 1] - 0 ) % 8] = true; temp_ans[(s[i - 1] - 0 ) % 8] = s[i - 1]; for (int j = 0; j < 8; j++) { if (dp[i - 1][j]) { int temp = (10 * j + (s[i - 1] - 0 )) % 8; dp[i][temp] = true; temp_ans[temp] = ans[j] + s[i - 1]; dp[i][j] = true; temp_ans[j] = ans[j]; } } for (int j = 0; j < 8; j++) ans[j] = temp_ans[j]; } if (dp[n][0]) { cout << YES n ; cout << ans[0] << endl; } else cout << NO n ; } |
#include <bits/stdc++.h> using namespace std; const int inf = 2e9 + 10, MAXN = 1e5 + 10; int seg[4][MAXN * 4]; int n, S, l; void update(int ind) { seg[1][ind] = min(seg[1][((ind)*2)], seg[1][(((ind)*2) + 1)]); seg[2][ind] = max(seg[2][((ind)*2)], seg[2][(((ind)*2) + 1)]); seg[3][ind] = min(seg[3][((ind)*2)], seg[3][(((ind)*2) + 1)]); } void add(int s, int e, int ind, int x, int val, int t) { if (s > x or e <= x) return; if (s + 1 == e) { seg[t][ind] = val; return; } int mid = (s + e) / 2; add(s, mid, ((ind)*2), x, val, t); add(mid, e, (((ind)*2) + 1), x, val, t); update(ind); } int fin(int s, int e, int ind, int x, int y, int t) { if (s >= y or e <= x) return (t == 1 or t == 3) ? inf : -inf; if (s >= x and e <= y) return seg[t][ind]; int mid = (s + e) / 2; if (t == 1 or t == 3) return min(fin(s, mid, ((ind)*2), x, y, t), fin(mid, e, (((ind)*2) + 1), x, y, t)); return max(fin(s, mid, ((ind)*2), x, y, t), fin(mid, e, (((ind)*2) + 1), x, y, t)); } void show() { for (int i = 0; i < n; i++) cerr << fin(0, n, 1, i, i + 1, 1) << << fin(0, n, 1, i, i + 1, 2) << endl; } int main() { scanf( %d%d%d , &n, &S, &l); fill(seg[1], seg[1] + MAXN * 4, inf); fill(seg[3], seg[3] + MAXN * 4, inf); for (int i = 0; i < n; i++) { int x; scanf( %d , &x); add(0, n, 1, i, x, 1); add(0, n, 1, i, x, 2); } for (int i = 0; i < n; i++) { int s = -1, e = i; while (e - s > 1) { int mid = (s + e) / 2; if (fin(0, n, 1, mid, i + 1, 2) - fin(0, n, 1, mid, i + 1, 1) <= S) e = mid; else s = mid; } if (e == 0 and i + 1 >= l) { int res = 1; add(0, n, 1, i, res, 3); if (i == n - 1) { printf( 1 n ); return 0; } } else if (i - e + 1 >= l) { int res = fin(0, n, 1, e - 1, i - l + 1, 3); res = min(res + 1, inf); add(0, n, 1, i, res, 3); if (i == n - 1) { if (res == inf) printf( -1 n ); else printf( %d n , res); return 0; } } } printf( -1 n ); return 0; } |
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module sysid (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? : 0;
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using pii = pair<int, int>; const int N = 1e6 + 10; struct UFS { stack<pair<int *, int>> stk; int fa[N], rnk[N]; inline void init(int n) { for (int i = 0; i <= n; ++i) fa[i] = i, rnk[i] = 0; } inline int Find(int x) { while (x ^ fa[x]) x = fa[x]; return x; } inline void Merge(int x, int y) { x = Find(x), y = Find(y); if (x == y) return; if (rnk[x] <= rnk[y]) { stk.push({fa + x, fa[x]}); fa[x] = y; if (rnk[x] == rnk[y]) { stk.push({rnk + y, rnk[y]}); rnk[y]++; } } else { stk.push({fa + y, fa[y]}); fa[y] = x; } } inline void Undo() { *stk.top().first = stk.top().second; stk.pop(); } } ufs; struct Edge { int u, v; }; int main() { int n, m, k; cin >> n >> m >> k; vector<int> c(n + 1); for (int i = 1; i <= n; i++) cin >> c[i]; vector<Edge> same_edges; map<pair<int, int>, vector<Edge>> diff_edges; for (int i = 0; i < m; i++) { int u, v; cin >> u >> v; if (c[u] == c[v]) same_edges.push_back({u, v}); else { if (c[u] > c[v]) swap(u, v); diff_edges[{c[u], c[v]}].push_back({u, v}); } } vector<int> group_flag(k + 1, 1); ufs.init((n + 1) * 2); for (auto &[u, v] : same_edges) { ufs.Merge(u * 2, v * 2 + 1); ufs.Merge(u * 2 + 1, v * 2); if (ufs.Find(u * 2) == ufs.Find(u * 2 + 1)) group_flag[c[u]] = 0; if (ufs.Find(v * 2) == ufs.Find(v * 2 + 1)) group_flag[c[v]] = 0; } ll good_group_cnt = 0; for (int i = 1; i <= k; i++) if (group_flag[i]) good_group_cnt++; ll cnt_fail = 0; for (auto &[key, row] : diff_edges) { if (!group_flag[key.first]) continue; if (!group_flag[key.second]) continue; int mark = (int)ufs.stk.size(); int flag = 1; for (auto &[u, v] : row) { ufs.Merge(u * 2, v * 2 + 1); ufs.Merge(u * 2 + 1, v * 2); if (ufs.Find(u * 2) == ufs.Find(u * 2 + 1)) flag = 0; if (ufs.Find(v * 2) == ufs.Find(v * 2 + 1)) flag = 0; } if (!flag) cnt_fail++; while ((int)ufs.stk.size() > mark) { ufs.Undo(); } } ll ans = good_group_cnt * (good_group_cnt - 1) / 2; ans = ans - cnt_fail; cout << ans; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2007 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
v95 v95 ();
v01nc v01nc ();
v01c v01c ();
v05 v05 ();
s05 s05 ();
s09 s09 ();
s12 s12 ();
s17 s17 ();
a23 a23 ();
initial begin
$finish;
end
endmodule
`begin_keywords "1364-1995"
module v95;
integer signed; initial signed = 1;
endmodule
`end_keywords
`begin_keywords "1364-2001-noconfig"
module v01nc;
localparam g = 0;
integer instance; initial instance = 1;
endmodule
`end_keywords
`begin_keywords "1364-2001"
module v01c;
localparam g = 0;
integer bit; initial bit = 1;
endmodule
`end_keywords
`begin_keywords "1364-2005"
module v05;
uwire w;
integer final; initial final = 1;
endmodule
`end_keywords
`begin_keywords "1800-2005"
module s05;
bit b;
integer global; initial global = 1;
endmodule
`end_keywords
`begin_keywords "1800-2009"
module s09;
bit b;
integer soft; initial soft = 1;
endmodule
`end_keywords
`begin_keywords "1800-2012"
module s12;
final begin
$write("*-* All Finished *-*\n");
end
endmodule
`end_keywords
`begin_keywords "1800-2017"
module s17;
final begin
$write("*-* All Finished *-*\n");
end
endmodule
`end_keywords
`begin_keywords "VAMS-2.3"
module a23;
real foo; initial foo = sqrt(2.0);
endmodule
`end_keywords
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; int ar[n]; int cnt = 0, cnt2 = 0; for (int i = 0; i < n; i++) { cin >> ar[i]; if (ar[i] > 0) cnt += ar[i]; else cnt2 += ar[i]; } cout << cnt - cnt2; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { long long int n, i, j, k, l = 0, s, x, y, z = 0, r = 1000000001, rr = 0; cin >> n >> s >> k; long long int a[k]; for (i = 0; i < k; i++) cin >> a[i]; sort(a, a + k); for (i = 0; i < k; i++) { if (a[i] == s) z = 1; } if (z == 0) cout << 0 << endl; else if (z == 1 && k == 1) cout << 1 << endl; else { if (a[0] != 1) { r = std::min(r, s - (a[0] - 1)); r = std::min(r, s - 1); } if (a[k - 1] != n) { r = std::min(r, (a[k - 1] + 1) - s); r = std::min(r, n - s); } for (i = 0; i < k - 1; i++) { if ((a[i + 1] - a[i]) > 1) { rr = a[i + 1] - 1; if (a[i] >= s) { rr = a[i] + 1; r = std::min(r, (rr - s)); } else if (a[i + 1] <= s) { rr = a[i + 1] - 1; r = std::min(r, (s - rr)); } } } cout << r << endl; } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRSDFRTP_TB_V
`define SKY130_FD_SC_LP__SRSDFRTP_TB_V
/**
* srsdfrtp: Scan flop with sleep mode, inverted reset, non-inverted
* clock, single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__srsdfrtp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg RESET_B;
reg SLEEP_B;
reg KAPWR;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
KAPWR = 1'bX;
RESET_B = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 KAPWR = 1'b0;
#60 RESET_B = 1'b0;
#80 SCD = 1'b0;
#100 SCE = 1'b0;
#120 SLEEP_B = 1'b0;
#140 VGND = 1'b0;
#160 VNB = 1'b0;
#180 VPB = 1'b0;
#200 VPWR = 1'b0;
#220 D = 1'b1;
#240 KAPWR = 1'b1;
#260 RESET_B = 1'b1;
#280 SCD = 1'b1;
#300 SCE = 1'b1;
#320 SLEEP_B = 1'b1;
#340 VGND = 1'b1;
#360 VNB = 1'b1;
#380 VPB = 1'b1;
#400 VPWR = 1'b1;
#420 D = 1'b0;
#440 KAPWR = 1'b0;
#460 RESET_B = 1'b0;
#480 SCD = 1'b0;
#500 SCE = 1'b0;
#520 SLEEP_B = 1'b0;
#540 VGND = 1'b0;
#560 VNB = 1'b0;
#580 VPB = 1'b0;
#600 VPWR = 1'b0;
#620 VPWR = 1'b1;
#640 VPB = 1'b1;
#660 VNB = 1'b1;
#680 VGND = 1'b1;
#700 SLEEP_B = 1'b1;
#720 SCE = 1'b1;
#740 SCD = 1'b1;
#760 RESET_B = 1'b1;
#780 KAPWR = 1'b1;
#800 D = 1'b1;
#820 VPWR = 1'bx;
#840 VPB = 1'bx;
#860 VNB = 1'bx;
#880 VGND = 1'bx;
#900 SLEEP_B = 1'bx;
#920 SCE = 1'bx;
#940 SCD = 1'bx;
#960 RESET_B = 1'bx;
#980 KAPWR = 1'bx;
#1000 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_lp__srsdfrtp dut (.D(D), .SCD(SCD), .SCE(SCE), .RESET_B(RESET_B), .SLEEP_B(SLEEP_B), .KAPWR(KAPWR), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRSDFRTP_TB_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2009 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t;
// Speced ignored: system calls. I think this is nasty, so we error instead.
// Speced Illegal: inout/output/ref not allowed
localparam B1 = f_bad_output(1,2);
function integer f_bad_output(input [31:0] a, output [31:0] o);
f_bad_output = 0;
endfunction
// Speced Illegal: void
// Speced Illegal: dotted
localparam EIGHT = 8;
localparam B2 = f_bad_dotted(2);
function integer f_bad_dotted(input [31:0] a);
f_bad_dotted = t.EIGHT;
endfunction
// Speced Illegal: ref to non-local var
integer modvar;
localparam B3 = f_bad_nonparam(3);
function integer f_bad_nonparam(input [31:0] a);
f_bad_nonparam = modvar;
endfunction
// Speced Illegal: needs constant function itself
// Our own - infinite loop
localparam B4 = f_bad_infinite(3);
function integer f_bad_infinite(input [31:0] a);
while (1) begin
f_bad_infinite = 0;
end
endfunction
// Our own - stop
localparam BSTOP = f_bad_stop(3);
function integer f_bad_stop(input [31:0] a);
$stop;
endfunction
// Verify $fatal works with sformatf as argument
localparam BFATAL = f_bad_fatal(3);
function integer f_bad_fatal(input [31:0] a);
for (integer i=0;i<3;i++) begin
$display("Printing in loop: %s", $sformatf("%d", i));
end
$fatal(2, "%s", $sformatf("Fatal Error"));
endfunction
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_3_gt_rx_valid_filter_7x.v
// Version : 1.3
//-- Description: GTX module for 7-series Integrated PCIe Block
//--
//--
//--
//--------------------------------------------------------------------------------
`timescale 1ns / 1ns
module pcie_7x_v1_3_gt_rx_valid_filter_7x #(
parameter CLK_COR_MIN_LAT = 28,
parameter TCQ = 1
)
(
output [1:0] USER_RXCHARISK,
output [15:0] USER_RXDATA,
output USER_RXVALID,
output USER_RXELECIDLE,
output [ 2:0] USER_RX_STATUS,
output USER_RX_PHY_STATUS,
input [1:0] GT_RXCHARISK,
input [15:0] GT_RXDATA,
input GT_RXVALID,
input GT_RXELECIDLE,
input [ 2:0] GT_RX_STATUS,
input GT_RX_PHY_STATUS,
input PLM_IN_L0,
input PLM_IN_RS,
input USER_CLK,
input RESET
);
localparam EIOS_DET_IDL = 5'b00001;
localparam EIOS_DET_NO_STR0 = 5'b00010;
localparam EIOS_DET_STR0 = 5'b00100;
localparam EIOS_DET_STR1 = 5'b01000;
localparam EIOS_DET_DONE = 5'b10000;
localparam EIOS_COM = 8'hBC;
localparam EIOS_IDL = 8'h7C;
localparam FTSOS_COM = 8'hBC;
localparam FTSOS_FTS = 8'h3C;
reg [4:0] reg_state_eios_det;
wire [4:0] state_eios_det;
reg reg_eios_detected;
wire eios_detected;
reg reg_symbol_after_eios;
wire symbol_after_eios;
localparam USER_RXVLD_IDL = 4'b0001;
localparam USER_RXVLD_EI = 4'b0010;
localparam USER_RXVLD_EI_DB0 = 4'b0100;
localparam USER_RXVLD_EI_DB1 = 4'b1000;
reg [1:0] gt_rxcharisk_q;
reg [15:0] gt_rxdata_q;
reg gt_rxvalid_q;
reg gt_rxelecidle_q;
reg [ 2:0] gt_rx_status_q;
reg gt_rx_phy_status_q;
reg gt_rx_is_skp0_q;
reg gt_rx_is_skp1_q;
// EIOS detector
always @(posedge USER_CLK) begin
if (RESET) begin
reg_eios_detected <= #TCQ 1'b0;
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
reg_symbol_after_eios <= #TCQ 1'b0;
gt_rxcharisk_q <= #TCQ 2'b00;
gt_rxdata_q <= #TCQ 16'h0;
gt_rxvalid_q <= #TCQ 1'b0;
gt_rxelecidle_q <= #TCQ 1'b0;
gt_rx_status_q <= #TCQ 3'b000;
gt_rx_phy_status_q <= #TCQ 1'b0;
gt_rx_is_skp0_q <= #TCQ 1'b0;
gt_rx_is_skp1_q <= #TCQ 1'b0;
end else begin
reg_eios_detected <= #TCQ 1'b0;
reg_symbol_after_eios <= #TCQ 1'b0;
gt_rxcharisk_q <= #TCQ GT_RXCHARISK;
gt_rxelecidle_q <= #TCQ GT_RXELECIDLE;
gt_rxdata_q <= #TCQ GT_RXDATA;
gt_rx_phy_status_q <= #TCQ GT_RX_PHY_STATUS;
//De-assert rx_valid signal when EIOS is detected on RXDATA
if(((reg_state_eios_det == 5'b10000)) && (PLM_IN_L0)
) begin
gt_rxvalid_q <= #TCQ 1'b0;
end
else if (GT_RXELECIDLE && !gt_rxvalid_q) begin
gt_rxvalid_q <= #TCQ 1'b0;
end
else begin
gt_rxvalid_q <= GT_RXVALID;
end
if (gt_rxvalid_q) begin
gt_rx_status_q <= #TCQ GT_RX_STATUS;
end
else if (!gt_rxvalid_q && PLM_IN_L0) begin
gt_rx_status_q <= #TCQ 3'b0;
end
else begin
gt_rx_status_q <= #TCQ GT_RX_STATUS;
end
if (GT_RXCHARISK[0] && GT_RXDATA[7:0] == FTSOS_FTS)
gt_rx_is_skp0_q <= #TCQ 1'b1;
else
gt_rx_is_skp0_q <= #TCQ 1'b0;
if (GT_RXCHARISK[1] && GT_RXDATA[15:8] == FTSOS_FTS)
gt_rx_is_skp1_q <= #TCQ 1'b1;
else
gt_rx_is_skp1_q <= #TCQ 1'b0;
case ( state_eios_det )
EIOS_DET_IDL : begin
if ((gt_rxcharisk_q[0]) && (gt_rxdata_q[7:0] == EIOS_COM) &&
(gt_rxcharisk_q[1]) && (gt_rxdata_q[15:8] == EIOS_IDL)) begin
reg_state_eios_det <= #TCQ EIOS_DET_NO_STR0;
reg_eios_detected <= #TCQ 1'b1;
// gt_rxvalid_q <= #TCQ 1'b0;
end else if ((gt_rxcharisk_q[1]) && (gt_rxdata_q[15:8] == EIOS_COM))
reg_state_eios_det <= #TCQ EIOS_DET_STR0;
else
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
EIOS_DET_NO_STR0 : begin
if ((gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_IDL)) &&
(gt_rxcharisk_q[1] && (gt_rxdata_q[15:8] == EIOS_IDL)))
begin
reg_state_eios_det <= #TCQ EIOS_DET_DONE;
gt_rxvalid_q <= #TCQ 1'b0;
end
else if (gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_IDL)) begin
reg_state_eios_det <= #TCQ EIOS_DET_DONE;
gt_rxvalid_q <= #TCQ 1'b0;
end
else
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
EIOS_DET_STR0 : begin
if ((gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_IDL)) &&
(gt_rxcharisk_q[1] && (gt_rxdata_q[15:8] == EIOS_IDL))) begin
reg_state_eios_det <= #TCQ EIOS_DET_STR1;
reg_eios_detected <= #TCQ 1'b1;
gt_rxvalid_q <= #TCQ 1'b0;
reg_symbol_after_eios <= #TCQ 1'b1;
end else
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
EIOS_DET_STR1 : begin
if ((gt_rxcharisk_q[0]) && (gt_rxdata_q[7:0] == EIOS_IDL))
begin
reg_state_eios_det <= #TCQ EIOS_DET_DONE;
gt_rxvalid_q <= #TCQ 1'b0;
end
else
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
EIOS_DET_DONE : begin
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
endcase
end
end
assign state_eios_det = reg_state_eios_det;
assign eios_detected = reg_eios_detected;
assign symbol_after_eios = reg_symbol_after_eios;
/*SRL16E #(.INIT(0)) rx_elec_idle_delay (.Q(USER_RXELECIDLE),
.D(gt_rxelecidle_q),
.CLK(USER_CLK),
.CE(1'b1), .A3(1'b1),.A2(1'b1),.A1(1'b1),.A0(1'b1));
*/
wire rst_l = ~RESET;
assign USER_RXVALID = gt_rxvalid_q;
assign USER_RXCHARISK[0] = gt_rxvalid_q ? gt_rxcharisk_q[0] : 1'b0;
assign USER_RXCHARISK[1] = (gt_rxvalid_q && !symbol_after_eios) ? gt_rxcharisk_q[1] : 1'b0;
assign USER_RXDATA[7:0] = gt_rxdata_q[7:0];
assign USER_RXDATA[15:8] = gt_rxdata_q[15:8];
assign USER_RX_STATUS = gt_rx_status_q;
assign USER_RX_PHY_STATUS = gt_rx_phy_status_q;
assign USER_RXELECIDLE = gt_rxelecidle_q;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CONB_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__CONB_FUNCTIONAL_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__conb (
HI,
LO
);
// Module ports
output HI;
output LO;
// Name Output
pullup pullup0 (HI );
pulldown pulldown0 (LO );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CONB_FUNCTIONAL_V |
// vga_0.v
// This file was auto-generated as part of a generation operation.
// If you edit it your changes will probably be lost.
`timescale 1 ps / 1 ps
module vga_0 (
input wire iCLK, // clk.clk
output wire [9:0] VGA_R, // avalon_slave_0_export.export
output wire [9:0] VGA_G, // .export
output wire [9:0] VGA_B, // .export
output wire VGA_HS, // .export
output wire VGA_VS, // .export
output wire VGA_SYNC, // .export
output wire VGA_BLANK, // .export
output wire VGA_CLK, // .export
input wire iCLK_25, // .export
output wire [15:0] oDATA, // avalon_slave_0.readdata
input wire [15:0] iDATA, // .writedata
input wire [18:0] iADDR, // .address
input wire iWR, // .write
input wire iRD, // .read
input wire iCS, // .chipselect
input wire iRST_N // reset_n.reset_n
);
VGA_NIOS_CTRL #(
.RAM_SIZE (307200)
) vga_0 (
.iCLK (iCLK), // clk.clk
.VGA_R (VGA_R), // avalon_slave_0_export.export
.VGA_G (VGA_G), // .export
.VGA_B (VGA_B), // .export
.VGA_HS (VGA_HS), // .export
.VGA_VS (VGA_VS), // .export
.VGA_SYNC (VGA_SYNC), // .export
.VGA_BLANK (VGA_BLANK), // .export
.VGA_CLK (VGA_CLK), // .export
.iCLK_25 (iCLK_25), // .export
.oDATA (oDATA), // avalon_slave_0.readdata
.iDATA (iDATA), // .writedata
.iADDR (iADDR), // .address
.iWR (iWR), // .write
.iRD (iRD), // .read
.iCS (iCS), // .chipselect
.iRST_N (iRST_N) // reset_n.reset_n
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1000051; long long n; string c; struct btree { int chnum; int child[2]; int num; int typ; int id; } tre[N]; int dfx[N][2]; int tot = 0; int has[N]; void predfs(int x) { if (tre[x].typ == 0) return; if (tre[x].typ == 1) { predfs(tre[x].child[0]); predfs(tre[x].child[1]); tre[x].num = tre[tre[x].child[0]].num & tre[tre[x].child[1]].num; } if (tre[x].typ == 2) { predfs(tre[x].child[0]); predfs(tre[x].child[1]); tre[x].num = tre[tre[x].child[0]].num | tre[tre[x].child[1]].num; } if (tre[x].typ == 3) { predfs(tre[x].child[0]); predfs(tre[x].child[1]); tre[x].num = tre[tre[x].child[0]].num ^ tre[tre[x].child[1]].num; } if (tre[x].typ == 4) { predfs(tre[x].child[0]); tre[x].num = !tre[tre[x].child[0]].num; } } void dfs(int x) { if (tre[x].typ == 0) has[tre[x].id] = dfx[tot][tre[x].num ^ 1]; if (tre[x].typ == 1) { tot++; dfx[tot][0] = dfx[tot - 1][0 & tre[tre[x].child[1]].num]; dfx[tot][1] = dfx[tot - 1][1 & tre[tre[x].child[1]].num]; dfs(tre[x].child[0]); dfx[tot][0] = dfx[tot - 1][0 & tre[tre[x].child[0]].num]; dfx[tot][1] = dfx[tot - 1][1 & tre[tre[x].child[0]].num]; dfs(tre[x].child[1]); tot--; } if (tre[x].typ == 2) { tot++; dfx[tot][0] = dfx[tot - 1][0 | tre[tre[x].child[1]].num]; dfx[tot][1] = dfx[tot - 1][1 | tre[tre[x].child[1]].num]; dfs(tre[x].child[0]); dfx[tot][0] = dfx[tot - 1][0 | tre[tre[x].child[0]].num]; dfx[tot][1] = dfx[tot - 1][1 | tre[tre[x].child[0]].num]; dfs(tre[x].child[1]); tot--; } if (tre[x].typ == 3) { tot++; dfx[tot][0] = dfx[tot - 1][0 ^ tre[tre[x].child[1]].num]; dfx[tot][1] = dfx[tot - 1][1 ^ tre[tre[x].child[1]].num]; dfs(tre[x].child[0]); dfx[tot][0] = dfx[tot - 1][0 ^ tre[tre[x].child[0]].num]; dfx[tot][1] = dfx[tot - 1][1 ^ tre[tre[x].child[0]].num]; dfs(tre[x].child[1]); tot--; } if (tre[x].typ == 4) { tot++; dfx[tot][0] = dfx[tot - 1][1]; dfx[tot][1] = dfx[tot - 1][0]; dfs(tre[x].child[0]); tot--; } } void init() { cin >> n; for (int i = 1; i <= n; i++) has[i] = -1; for (int i = 1; i <= n; i++) { cin >> c; tre[i].id = i; if (c == IN ) { tre[i].chnum = 0; tre[i].typ = 0; scanf( %d , &tre[i].num); } if (c == AND ) { tre[i].chnum = 2; tre[i].typ = 1; tre[i].num = -1; scanf( %d%d , &tre[i].child[0], &tre[i].child[1]); } if (c == OR ) { tre[i].chnum = 2; tre[i].typ = 2; tre[i].num = -1; scanf( %d%d , &tre[i].child[0], &tre[i].child[1]); } if (c == XOR ) { tre[i].chnum = 2; tre[i].typ = 3; tre[i].num = -1; scanf( %d%d , &tre[i].child[0], &tre[i].child[1]); } if (c == NOT ) { tre[i].chnum = 1; tre[i].typ = 4; tre[i].num = -1; scanf( %d , &tre[i].child[0]); } } dfx[0][0] = 0; dfx[0][1] = 1; predfs(1); dfs(1); for (int i = 1; i <= n; i++) if (has[i] != -1) printf( %d , has[i]); printf( n ); } int main() { int T; T = 1; while (T--) init(); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFRTN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__SDFRTN_BEHAVIORAL_PP_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hdll__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_N_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intclk , CLK_N_delayed );
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hdll__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, intclk, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFRTN_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int mod = (int)1e9 + 7; long long modPow(long long n, long long k) { long long res = 1; for (n %= mod; k; k >>= 1) { if (k & 1) res = res * n % mod; n = n * n % mod; } return res; } long long modInv(const long long x) { return modPow(x, mod - 2); } signed main() { ios::sync_with_stdio(false); cin.tie(nullptr), cout.tie(nullptr); int n; cin >> n; vector<int> l(n + 1, 0), r(n + 1, 0); for (int i = 1; i <= n; ++i) cin >> l[i]; for (int i = 1; i <= n; ++i) cin >> r[i]; const auto sz = [&](const int i) { assert(l[i] <= r[i]); return r[i] - l[i] + 1LL; }; long long ans = 0; vector<long long> dp(n); for (int i = 0; i < n; ++i) { const long long c = max(0, min(r[i], r[i + 1]) - max(l[i], l[i + 1]) + 1); dp[i] = 1 - c * modInv(sz(i)) % mod * modInv(sz(i + 1)) % mod; (ans += dp[i]) %= mod; } for (int i = 0; i + 1 < n; ++i) { const int L = max(l[i], max(l[i + 1], l[i + 2])); const int R = min(r[i], min(r[i + 1], r[i + 2])); const long long c = max(0, R - L + 1); const long long temp = 1 - (1 - dp[i]) - (1 - dp[i + 1]) + c * modInv(sz(i) * sz(i + 1) % mod * sz(i + 2) % mod); (ans += 2 * temp) %= mod; } long long sum = 0; for (int i = 2; i < n; ++i) { (sum += dp[i - 2]) %= mod; (ans += 2 * dp[i] * sum) %= mod; } cout << (ans % mod + mod) % mod; return 0; } |
#include <bits/stdc++.h> using namespace std; int lcs(string X, string Y) { int i, j, m = X.length(), n = Y.length(); int L[m + 1][n + 1]; for (i = 0; i <= m; i++) { for (j = 0; j <= n; j++) { if (i == 0 || j == 0) L[i][j] = 0; else if (X[i - 1] == Y[j - 1]) L[i][j] = L[i - 1][j - 1] + 1; else L[i][j] = max(L[i - 1][j], L[i][j - 1]); } } return L[m][n]; } int main() { long long n; cin >> n; vector<long long> v; string x, y; x = to_string(n); int max = 0; for (long long i = 1; i <= sqrt(n); i++) { v.push_back(i * i); y = to_string(i * i); if (max < lcs(x, y) && (lcs(x, y) == y.length())) { max = lcs(x, y); } } if (max != 0) { cout << x.length() - max; } else { cout << -1 ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYGATE4SD1_TB_V
`define SKY130_FD_SC_MS__DLYGATE4SD1_TB_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dlygate4sd1.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_ms__dlygate4sd1 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYGATE4SD1_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { int t, n; cin >> t; while (t--) { cin >> n; vector<int> numbers(n); vector<int> trayectoria(n + 1); for (int &i : numbers) cin >> i; if (numbers[0] == 1) { cout << n + 1 << ; for (int i = 1; i < n + 1; i++) cout << i << ; cout << n ; } else if (numbers[n - 1] == 0) { for (int i = 1; i < n; i++) cout << i << ; cout << n << << n + 1 << ; cout << n ; } else { bool poss = false; for (int i = 0; i < n; i++) { if (i < n - 1 && numbers[i] < numbers[i + 1]) { for (int j = 0; j < i; j++) cout << j + 1 << ; cout << i + 1 << << n + 1 << ; for (int j = i + 1; j < n; j++) cout << j + 1 << ; cout << endl; poss = true; break; } } if (!poss) cout << -1 n ; } } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXTN_PP_SYMBOL_V
`define SKY130_FD_SC_HD__DLXTN_PP_SYMBOL_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlxtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE_N,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXTN_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; bool compare(string &s1, string &s2) { return s1.size() < s2.size(); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); vector<string> s; string str; int n, i, j, flag = 0; cin >> n; for (i = 0; i < n; i++) { cin >> str; s.push_back(str); } sort(s.begin(), s.end(), compare); for (i = 0; i < n - 1; i++) { j = 0; while (j < s[i + 1].length()) { int l = s[i].length(); flag = 0; if (s[i] == s[i + 1].substr(j, l)) { flag = 1; break; } j++; } if (flag != 1) { cout << NO n ; break; } } if (flag == 1 || n == 1) { cout << YES n ; for (i = 0; i < n; i++) { cout << s[i] << n ; } } } |
#include <bits/stdc++.h> template <typename T> T min(T x, T y) { return x < y ? x : y; } template <typename T> T max(T x, T y) { return x > y ? x : y; } template <typename T> T abs(T x) { return x > 0 ? x : -x; } template <typename T> T gcd(T x, T y) { return x ? gcd(y % x, x) : y; } int main() { int t, d, l, r, p; scanf( %d , &t); while (t--) { scanf( %d %d %d %d , &d, &p, &l, &r); printf( %d n , d / p - r / p + (l - 1) / p); } } |
#include <bits/stdc++.h> using namespace std; long long A[1000000]; long long ncr(int n, int k) { long long ans = 1; k = k > n - k ? n - k : k; int j = 1; for (; j <= k; j++, n--) { if (n % j == 0) { ans *= n / j; } else if (ans % j == 0) { ans = ans / j * n; } else { ans = (ans * n) / j; } } return ans; } int main() { ios::sync_with_stdio(false); long long n, m, t; cin >> n >> m >> t; long long sum = 0; for (long long i = 4; i <= n; i++) for (long long j = 1; j <= m; j++) if (i + j == t) sum += ncr(n, i) * ncr(m, j); cout << sum << endl; return 0; } |
`default_nettype none
`define CLKFREQ 12000000 // frequency of incoming signal 'clk'
`define BAUD 115200
// Simple baud generator for transmitter
// ser_clk pulses at 115200 Hz
module baudgen(
input wire clk,
output wire ser_clk);
localparam lim = (`CLKFREQ / `BAUD) - 1;
localparam w = $clog2(lim);
wire [w-1:0] limit = lim;
reg [w-1:0] counter;
assign ser_clk = (counter == limit);
always @(posedge clk)
counter <= ser_clk ? 0 : (counter + 1);
endmodule
// For receiver, a similar baud generator.
//
// Need to restart the counter when the transmission starts
// Generate 2X the baud rate to allow sampling on bit boundary
// So ser_clk pulses at 2*115200 Hz
module baudgen2(
input wire clk,
input wire restart,
output wire ser_clk);
localparam lim = (`CLKFREQ / (2 * `BAUD)) - 1;
localparam w = $clog2(lim);
wire [w-1:0] limit = lim;
reg [w-1:0] counter;
assign ser_clk = (counter == limit);
always @(posedge clk)
if (restart)
counter <= 0;
else
counter <= ser_clk ? 0 : (counter + 1);
endmodule
/*
-----+ +-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+----
| | | | | | | | | | | |
|start| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |stop1|stop2|
| | | | | | | | | | | ? |
+-----+-----+-----+-----+-----+-----+-----+-----+-----+ +
*/
module uart(
input wire clk,
input wire resetq,
output wire uart_busy, // High means UART is transmitting
output reg uart_tx, // UART transmit wire
input wire uart_wr_i, // Raise to transmit byte
input wire [7:0] uart_dat_i
);
reg [3:0] bitcount; // 0 means idle, so this is a 1-based counter
reg [8:0] shifter;
assign uart_busy = |bitcount;
wire sending = |bitcount;
wire ser_clk;
baudgen _baudgen(
.clk(clk),
.ser_clk(ser_clk));
always @(negedge resetq or posedge clk)
begin
if (!resetq) begin
uart_tx <= 1;
bitcount <= 0;
shifter <= 0;
end else begin
if (uart_wr_i) begin
{ shifter, uart_tx } <= { uart_dat_i[7:0], 1'b0, 1'b1 };
bitcount <= 1 + 8 + 1; // 1 start, 8 data, 1 stop
end else if (ser_clk & sending) begin
{ shifter, uart_tx } <= { 1'b1, shifter };
bitcount <= bitcount - 4'd1;
end
end
end
endmodule
module rxuart(
input wire clk,
input wire resetq,
input wire uart_rx, // UART recv wire
input wire rd, // read strobe
output wire valid, // has data
output wire [7:0] data); // data
reg [4:0] bitcount;
reg [7:0] shifter;
// bitcount == 11111: idle
// 0-17: sampling incoming bits
// 18: character received
// On starting edge, wait 3 half-bits then sample, and sample every 2 bits thereafter
wire idle = &bitcount;
assign valid = (bitcount == 18);
wire sample;
reg [2:0] hh = 3'b111;
wire [2:0] hhN = {hh[1:0], uart_rx};
wire startbit = idle & (hhN[2:1] == 2'b10);
wire [7:0] shifterN = sample ? {hh[1], shifter[7:1]} : shifter;
wire ser_clk;
baudgen2 _baudgen(
.clk(clk),
.restart(startbit),
.ser_clk(ser_clk));
reg [4:0] bitcountN;
always @*
if (startbit)
bitcountN = 0;
else if (!idle & !valid & ser_clk)
bitcountN = bitcount + 5'd1;
else if (valid & rd)
bitcountN = 5'b11111;
else
bitcountN = bitcount;
// 3,5,7,9,11,13,15,17
assign sample = (|bitcount[4:1]) & bitcount[0] & ser_clk;
assign data = shifter;
always @(negedge resetq or posedge clk)
begin
if (!resetq) begin
hh <= 3'b111;
bitcount <= 5'b11111;
shifter <= 0;
end else begin
hh <= hhN;
bitcount <= bitcountN;
shifter <= shifterN;
end
end
endmodule
module buart(
input wire clk,
input wire resetq,
input wire rx, // recv wire
output wire tx, // xmit wire
input wire rd, // read strobe
input wire wr, // write strobe
output wire valid, // has recv data
output wire busy, // is transmitting
input wire [7:0] tx_data,
output wire [7:0] rx_data // data
);
rxuart _rx (
.clk(clk),
.resetq(resetq),
.uart_rx(rx),
.rd(rd),
.valid(valid),
.data(rx_data));
uart _tx (
.clk(clk),
.resetq(resetq),
.uart_busy(busy),
.uart_tx(tx),
.uart_wr_i(wr),
.uart_dat_i(tx_data));
endmodule
|
#include <bits/stdc++.h> const int N = 100001, M = 998244353, mod = 1000000007; const long long MX = INT64_MAX, MN = INT64_MIN, oo = 1e18; using namespace std; vector<string> tokenizer(string str, char ch) { std::istringstream var((str)); vector<string> v; string t; while (getline((var), t, (ch))) { v.emplace_back(t); } return v; } template <typename T1, typename T2> istream& operator>>(istream& in, pair<T1, T2>& a) { in >> a.first >> a.second; return in; } template <typename T1, typename T2> ostream& operator<<(ostream& out, pair<T1, T2> a) { out << a.first << << a.second; return out; } void err(istream_iterator<string> it) {} template <typename T, typename... Args> void err(istream_iterator<string> it, T a, Args... args) { cerr << *it << = << a << n ; err(++it, args...); } template <typename... T> void read(T&... args) { ((cin >> args), ...); } template <typename... T> void put(T&&... args) { ((cout << args << ), ...); } void file_i_o() { freopen( ./tests/test01.txt , r , stdin); freopen( ./tests/output01.txt , w , stdout); } void solve(int T) { int n, m, k; read(n, m, k); vector<vector<int>> grid(n, vector<int>(m)); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) cin >> grid[i][j]; while (k--) { int c; read(c); c--; int r = 0; while (r < n) { if (grid[r][c] == 2) r++; else { int nc = c; if (grid[r][c] == 1) nc++; else nc--; grid[r][c] = 2; c = nc; } } put(c + 1); } } int main(int argc, char const* argv[]) { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t = 1; for (int i = 1; i < t + 1; i++) { solve(t); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long int mod = 1000000007; long long int numOfPoints(long long int &x, long long int &y, long long int &n, long long int t) { long long int region1 = 2 * t * (t + 1) + 1; long long int region2; if (y - t >= 1) region2 = 0; else region2 = abs(y - t - 1) * abs(y - t - 1); long long int region3; if (y + t <= n) region3 = 0; else region3 = abs(n - y - t) * abs(n - y - t); long long int region4; if (x - t >= 1) region4 = 0; else region4 = abs(x - t - 1) * abs(x - t - 1); long long int region5; if (x + t <= n) region5 = 0; else region5 = abs(n - x - t) * abs(n - x - t); long long int region6; if (t >= (n + 1 - y) + (n + 1 - x)) region6 = (t - (n + 1 - y) - (n + 1 - x) + 1) * (t - (n + 1 - y) - (n + 1 - x) + 2) / 2; else region6 = 0; long long int region7; if (t >= (n + 1 - y) + (x - 0)) region7 = (t - (n + 1 - y) - (x - 0) + 1) * (t - (n + 1 - y) - (x - 0) + 2) / 2; else region7 = 0; long long int region8; if (t >= (y - 0) + (n + 1 - x)) region8 = (t - (y - 0) - (n + 1 - x) + 1) * (t - (y - 0) - (n + 1 - x) + 2) / 2; else region8 = 0; long long int region9; if (t >= (y - 0) + (x - 0)) region9 = (t - (y - 0) - (x - 0) + 1) * (t - (y - 0) - (x - 0) + 2) / 2; else region9 = 0; return region1 - region2 - region3 - region4 - region5 + region6 + region7 + region8 + region9; } int main() { long long int i, j, k, l, m, n, p, q, x, y, z, a, b, c, r, fs, ls, md; scanf( %lld , &n); scanf( %lld , &x); scanf( %lld , &y); scanf( %lld , &c); if (c == 1) { printf( 0 n ); return 0; } fs = 0, ls = 2000000007LL; while (fs + 1 < ls) { md = (fs + ls) / 2; if (c <= numOfPoints(x, y, n, md)) ls = md; else fs = md; } printf( %lld n , ls); return 0; } |
/////////////////////////////////////////////////////////////////////////////
//
// Silicon Spectrum Corporation - All Rights Reserved
// Copyright (C) 2005
//
// Title : Clock switch module for non programmable PLLs
// File : clk_switch.v
// Author : Jim MacLeod
// Created : 05-Mar-2013
// RCS File : $Source:$
// Status : $Id:$
//
//
//////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module takes in up to 6 PLL derived clocks plus a master clock (PCI).
// This module allows the glitchless switching amongst the clock frequencies.
// The purpose of this is to allow an FPGA w/o a programmable PLL
// (ex Cyclone2) to provide us with a variety of frequencies for generating
// Pixel clock and CRT clocks.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module clk_gen_ipll
(
input hb_clk,
input hb_resetn,
input refclk,
input [1:0] bpp,
input vga_mode,
input write_param, // input
input [3:0] counter_type, // input [3:0]
input [2:0] counter_param, // input[2:0]
input [8:0] data_in, // input [8:0],
input reconfig, // input.
input pll_areset_in, // input.
output busy, // Input busy.
output pix_clk,
output pix_clk_vga,
output reg crt_clk,
output pix_locked
);
pix_pll_rc_top u_pix_pll_rc_top
(
.hb_clk (hb_clk),
.hb_rstn (hb_resetn),
.ref_clk (refclk),
.reconfig (reconfig),
.write_param (write_param),
.counter_param (counter_param),// Input [2:0]
.counter_type (counter_type), // Input [3:0]
.data_in (data_in), // Input [8:0]
.pll_areset_in (pll_areset_in),
.busy (busy), // output.
.pix_clk (pix_clk), // output.
.pix_locked (pix_locked) // output.
);
reg [2:0] crt_counter;
reg [1:0] crt_divider;
always @*
begin
casex({vga_mode, bpp})
3'b1_xx: crt_divider = 2'b00;
3'b0_01: crt_divider = 2'b10;
3'b0_10: crt_divider = 2'b01;
default: crt_divider = 2'b00;
endcase
end
always @(posedge pix_clk or negedge hb_resetn)
begin
if(!hb_resetn)
begin
crt_clk <= 1'b1;
crt_counter <= 3'b000;
end
else begin
crt_counter <= crt_counter + 3'h1;
case (crt_divider)
0: crt_clk <= 1'b1;
1: crt_clk <= ~crt_counter[0];
2: crt_clk <= ~|crt_counter[1:0];
3: crt_clk <= ~|crt_counter[2:0];
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_PS_PP_SN_BLACKBOX_V
`define SKY130_FD_SC_HS__UDP_DFF_PS_PP_SN_BLACKBOX_V
/**
* udp_dff$PS_pp$sN: Positive edge triggered D flip-flop with active
* high
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$PS_pp$sN (
Q ,
D ,
CLK ,
SET ,
SLEEP_B ,
NOTIFIER
);
output Q ;
input D ;
input CLK ;
input SET ;
input SLEEP_B ;
input NOTIFIER;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_PS_PP_SN_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; inline int read() { char ch = getchar(); int x = 0, f = 1; while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while ( 0 <= ch && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } int fac[2000010], inv[2000010], f[2000010]; inline int Power(int x, int y, int Q) { int ret = 1; while (y) { if (y & 1) ret = 1ll * ret * x % Q; x = (1ll * x * x) % Q; y >>= 1; } return ret; } int main() { int n = read(), m = read(), a = read(), Q = read(); int p = 1; for (int i = a; i != 1; i = (1ll * i * a % Q), p++) ; fac[1] = 1; for (int i = (2); i <= (max(n, m)); i++) fac[i] = 1ll * fac[i - 1] * i % p; inv[0] = inv[1] = 1; for (int i = (2); i <= (max(n, m)); i++) inv[i] = 1ll * (p - p / i) * inv[p % i] % p; for (int i = (2); i <= (max(n, m)); i++) inv[i] = 1ll * inv[i - 1] * inv[i] % p; f[0] = 1; for (int i = (1); i <= (m); i++) { f[i] = (f[i - 1] + (1ll * fac[m] * inv[m - i] % p * inv[i] % p)) % p; } for (int i = (m + 1); i <= (n); i++) f[i] = f[i - 1]; for (int i = n; i >= 1; i--) printf( %d , Power(a, f[i - 1], Q)); return 0; } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module convolve_kernel_fcud
#(parameter
ID = 2,
NUM_STAGE = 5,
din0_WIDTH = 32,
din1_WIDTH = 32,
dout_WIDTH = 32
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [31:0] a_tdata;
wire b_tvalid;
wire [31:0] b_tdata;
wire r_tvalid;
wire [31:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
convolve_kernel_ap_fmul_3_max_dsp_32 convolve_kernel_ap_fmul_3_max_dsp_32_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
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