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#include <bits/stdc++.h> using namespace std; int mpow(int base, int exp); void solve() { long long int n; cin >> n; vector<long long int> v(n); vector<long long int> cnt(2 * n + 1, 0); for (long long int i = 0; i < (n); i++) { cin >> v[i]; cnt[v[i]]++; } vector<long long int> out; for (long long int i = 0; i < (n); i++) { out.push_back(v[i]); bool flag = true; for (long long int j = v[i] + 1; j <= 2 * n; j++) { if (cnt[j] == 0) { out.push_back(j); cnt[j]++; flag = false; break; } } if (flag) { cout << -1 << n ; return; } } for (auto i : out) cout << i << ; cout << n ; ; } int main() { int t; cin >> t; while (t--) solve(); return 0; } int mpow(int base, int exp) { base %= 1000000007; int result = 1; while (exp > 0) { if (exp & 1) result = ((long long int)result * base) % 1000000007; base = ((long long int)base * base) % 1000000007; exp >>= 1; } return result; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 7, n = 7, maxm = 101; int m, cntblk = maxn, f[maxn], deg[maxn]; bool used[maxm]; class ed { public: int target, id; char type; ed(int t, int i, char ty) : target(t), id(i), type(ty){}; }; class ans { public: int id; char type; ans(int i, char ty) : id(i), type(ty){}; }; vector<ed> edge[maxn]; vector<ans> answer; inline int getf(int x) { return f[x] == x ? x : f[x] = getf(f[x]); } void euler(int x, int in_id, char in_type) { for (vector<ed>::iterator vi = edge[x].begin(); vi != edge[x].end(); vi++) { if (used[(*vi).id]) continue; used[(*vi).id] = true; euler((*vi).target, (*vi).id, (*vi).type); } if (in_id >= 0) answer.push_back(ans(in_id, in_type)); } int main() { cin >> m; for (int i = 0; i < n; i++) f[i] = i, deg[i] = 0; for (int i = 1, x, y; i <= m; i++) { cin >> x >> y; deg[x]++; deg[y]++; edge[x].push_back(ed(y, i, + )); edge[y].push_back(ed(x, i, - )); if (getf(x) == getf(y)) continue; f[getf(x)] = getf(y); cntblk--; } int tmp = 0, s = -1; for (int i = 0; i < n; i++) { cntblk -= (deg[i] == 0); tmp += (deg[i] & 1); if (deg[i] > 0 && (s == -1 || deg[i] & 1)) s = i; } if (cntblk != 1 || !(tmp == 0 || tmp == 2)) { puts( No solution ); return 0; } memset(used, false, sizeof(used)); euler(s, -1, + ); for (vector<ans>::reverse_iterator vi = answer.rbegin(); vi < answer.rend(); vi++) { printf( %d %c n , (*vi).id, (*vi).type); } return 0; } |
#include <bits/stdc++.h> using namespace std; struct node { int num; double w; } point[1005]; bool cmp(node a, node b) { if (fabs(a.w - b.w) < 0.0001) return a.num < b.num; return a.w > b.w; } int main() { int i, n, t1, t2, k, a, b; scanf( %d%d%d%d , &n, &t1, &t2, &k); for (i = 1; i <= n; i++) { scanf( %d%d , &a, &b); point[i].num = i; point[i].w = t1 * a * (1 - k * 0.01) + t2 * b; if (t1 * b * (1 - k * 0.01) + t2 * a > point[i].w) point[i].w = t1 * b * (1 - k * 0.01) + t2 * a; } sort(point + 1, point + 1 + n, cmp); for (i = 1; i <= n; i++) printf( %d %.2lf n , point[i].num, point[i].w); return 0; } |
#include <bits/stdc++.h> using namespace std; long long gi() { char cc = getchar(); long long cn = 0, flus = 1; while (cc < 0 || cc > 9 ) { if (cc == - ) flus = -flus; cc = getchar(); } while (cc >= 0 && cc <= 9 ) cn = cn * 10 + cc - 0 , cc = getchar(); return cn * flus; } const long long P = 998244353; long long fpow(long long x, long long k) { long long ans = 1, base = x; while (k) { if (k & 1) ans = 1ll * ans * base % P; base = 1ll * base * base % P, k >>= 1; } return ans; } const long long N = 3e5 + 5; long long m, n, a[N], fac[N], inv[N]; long long C(long long x, long long y) { return fac[x] * inv[y] % P * inv[x - y] % P; } signed main() { m = gi(), n = m * 2; for (register long long i = (1); i <= (n); ++i) a[i] = gi(); sort(a + 1, a + n + 1); fac[0] = inv[0] = 1; for (register long long i = (1); i <= (n); ++i) fac[i] = fac[i - 1] * i % P; for (register long long i = (1); i <= (n); ++i) inv[i] = fpow(fac[i], P - 2); long long ans = 0; for (register long long i = (1); i <= (n); ++i) { long long z = a[i] * C(n - 1, m - 1); if (i <= m) ans = (ans - z + P) % P; else ans = (ans + z + P) % P; } cout << ans * 2 % P << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /STACK:1000000000 ) static char s[1000][1000]; static int dp[2][505][505]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n, m, res = 0, d1, d2; cin >> n >> m; for (int i = 0; i < n; ++i) cin >> s[i]; dp[0][0][n - 1] = 1; for (int d = 0; (n + m - 2 - d) >= d; ++d) { d1 = d & 1; d2 = 1 - d1; memset(dp[d2], 0, sizeof(dp[d2])); for (int x = 0; x <= min(d, n - 1); ++x) for (int x1 = n - 1; x1 >= 0 && (n + m - 2 - d) - x1 < m; --x1) { if (s[x][d - x] != s[x1][(n + m - 2 - d) - x1]) dp[d1][x][x1] = 0; if (d == (n + m - 2 - d) && x == x1) res = (res + dp[d1][x][x1]) % (long long)1000000007; if (d == (n + m - 2 - d) - 1 && abs(x - x1) < 2 && abs((d - x) - (d + 1 - x1)) < 2) res = (res + dp[d1][x][x1]) % (long long)1000000007; if (x1) { dp[d2][x + 1][x1 - 1] = (dp[d2][x + 1][x1 - 1] + dp[d1][x][x1]) % (long long)1000000007; dp[d2][x][x1 - 1] = (dp[d2][x][x1 - 1] + dp[d1][x][x1]) % (long long)1000000007; } dp[d2][x + 1][x1] = (dp[d2][x + 1][x1] + dp[d1][x][x1]) % (long long)1000000007; dp[d2][x][x1] = (dp[d2][x][x1] + dp[d1][x][x1]) % (long long)1000000007; } } cout << res << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxint = -1u >> 1; const double pi = 3.14159265358979323; const double eps = 1e-8; int n, k, a[100100]; set<long long> vis; int main() { scanf( %d%d , &n, &k); for (int i = (0); i < (n); i++) scanf( %d , &a[i]); sort(a, a + n); int ans = 0; for (int i = (0); i < (n); i++) { if (vis.find(a[i]) == vis.end()) { ans++; vis.insert(1LL * a[i] * k); } else continue; } printf( %d n , ans); return 0; } |
/***************************************************************************************************
** fpga_nes/hw/src/cpu/apu/apu_envelope_generator.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* APU length counter; building block used by several other APU components. Provides automatic
* duration control for the NES APU waveform channels. Once loaded with a value, it can optionally
* count down and silence the channel when it reaches zero.
***************************************************************************************************/
module apu_envelope_generator
(
input wire clk_in, // system clock signal
input wire rst_in, // reset signal
input wire eg_pulse_in, // 1 clk pulse for every env gen update
input wire [5:0] env_in, // envelope value (e.g., via $4000)
input wire env_wr_in, // envelope value write
input wire env_restart, // envelope restart
output wire [3:0] env_out // output volume
);
reg [5:0] q_reg;
wire [5:0] d_reg;
reg [3:0] q_cnt, d_cnt;
reg q_start_flag, d_start_flag;
always @(posedge clk_in)
begin
if (rst_in)
begin
q_reg <= 6'h00;
q_cnt <= 4'h0;
q_start_flag <= 1'b0;
end
else
begin
q_reg <= d_reg;
q_cnt <= d_cnt;
q_start_flag <= d_start_flag;
end
end
reg divider_pulse_in;
reg divider_reload;
wire divider_pulse_out;
apu_div #(.PERIOD_BITS(4)) divider(
.clk_in(clk_in),
.rst_in(rst_in),
.pulse_in(divider_pulse_in),
.reload_in(divider_reload),
.period_in(q_reg[3:0]),
.pulse_out(divider_pulse_out)
);
always @*
begin
d_cnt = q_cnt;
d_start_flag = q_start_flag;
divider_pulse_in = 1'b0;
divider_reload = 1'b0;
// When the divider outputs a clock, one of two actions occurs: If the counter is non-zero, it
// is decremented, otherwise if the loop flag is set, the counter is loaded with 15.
if (divider_pulse_out)
begin
divider_reload = 1'b1;
if (q_cnt != 4'h0)
d_cnt = q_cnt - 4'h1;
else if (q_reg[5])
d_cnt = 4'hF;
end
// When clocked by the frame counter, one of two actions occurs: if the start flag is clear,
// the divider is clocked, otherwise the start flag is cleared, the counter is loaded with 15,
// and the divider's period is immediately reloaded.
if (eg_pulse_in)
begin
if (q_start_flag == 1'b0)
begin
divider_pulse_in = 1'b1;
end
else
begin
d_start_flag = 1'b0;
d_cnt = 4'hF;
end
end
if (env_restart)
d_start_flag = 1'b1;
end
assign d_reg = (env_wr_in) ? env_in : q_reg;
// The envelope unit's volume output depends on the constant volume flag: if set, the envelope
// parameter directly sets the volume, otherwise the counter's value is the current volume.
assign env_out = (q_reg[4]) ? q_reg[3:0] : q_cnt;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; const int INF = 1e9 + 7; const int base = 1e9; const int MAX = 1e5; const double EPS = 1e-9; const double PI = acos(-1.); int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, *a, *res, j = 0; cin >> n; a = new int[n]; res = new int[n]; set<int> cnt; for (int i = 0; i < n; i++) { cin >> a[i]; } for (int i = n - 1; i >= 0; i--) { if (!cnt.count(a[i])) { cnt.insert(a[i]); res[j] = a[i]; j++; } } cout << j << endl; for (int i = j - 1; i >= 0; i--) { cout << res[i] << ; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2BB2AI_FUNCTIONAL_V
`define SKY130_FD_SC_MS__O2BB2AI_FUNCTIONAL_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o2bb2ai (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire nand1_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
nand nand1 (nand1_out_Y, nand0_out, or0_out);
buf buf0 (Y , nand1_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2BB2AI_FUNCTIONAL_V |
`include "hrfp_defs.vh"
// This module is not used anymore and may not function
// correctly. This is kept here for historical reasons as I may want
// to refer back to this module when implementing double precision
// HRFP_16 numbers.
module hrfp_normalize
#(parameter PIPELINESTAGES=5)
(input wire clk,
input wire [`MSBBIT:0] result_4,
input wire [30:0] mantissa_4,
input wire [7:0] zeroesmask_4,
output reg [30:0] mantissa_5,
output reg [`MSBBIT:0] result_5);
(* KEEP = "SOFT" *) reg [7:0] zeroes;
(* KEEP = "SOFT" *) reg [2:0] expdiff;
(* KEEP = "SOFT" *) reg [1:0] expdiff_mux0;
(* KEEP = "SOFT" *) reg [1:0] expdiff_mux1;
reg expdiff_carryin;
(* KEEP = "SOFT" *) wire rounding_will_overflow_tmp0 = (mantissa_4[30:25] == 6'b011111);
(* KEEP = "SOFT" *) wire rounding_will_overflow_tmp1 = (mantissa_4[24:19] == 6'b111111);
(* KEEP = "SOFT" *) wire rounding_will_overflow_tmp2 = (mantissa_4[18:13] == 6'b111111);
(* KEEP = "SOFT" *) wire rounding_will_overflow_tmp3 = (mantissa_4[12:7] == 6'b111111);
(* KEEP = "SOFT" *) wire rounding_will_overflow_tmp4 = (mantissa_4[6:1] == 6'b111111);
wire rounding_will_overflow_tmp5 = (mantissa_4[0] == 1'b1);
(* KEEP = "SOFT" *) wire rounding_will_overflow = rounding_will_overflow_tmp0 &&
rounding_will_overflow_tmp1 &&
rounding_will_overflow_tmp2 &&
rounding_will_overflow_tmp3 &&
rounding_will_overflow_tmp4 &&
rounding_will_overflow_tmp5;
wire overflow_bit = mantissa_4[30];
initial begin
$display("ERROR ERROR ERROR: This file is deprecated and only kept for historical reasons.");
$stop;
end
/*
rounding_will_overflow = 0;
if(mantissa_4[30:5] == 26'h1ffffff) begin
rounding_will_overflow = 1;
end
*/
// (* KEEP = "SOFT" *) reg iszero;
(* KEEP = "SOFT" *) wire iszero = (mantissa_4 == 0);
always @* begin
zeroes[0] = ~|mantissa_4[1:0] && zeroesmask_4[0];
zeroes[1] = ~|mantissa_4[5:2] && zeroesmask_4[1];
zeroes[2] = ~|mantissa_4[9:6] && zeroesmask_4[2];
zeroes[3] = ~|mantissa_4[13:10] && zeroesmask_4[3];
zeroes[4] = ~|mantissa_4[17:14] && zeroesmask_4[4];
zeroes[5] = ~|mantissa_4[21:18] && zeroesmask_4[5];
zeroes[6] = ~|mantissa_4[25:22] && zeroesmask_4[6];
zeroes[7] = ~|mantissa_4[29:26] && zeroesmask_4[7]; // 8 LUTs (confirmed!)
// iszero = 0;
expdiff = 0;
// if(zeroes == 8'b11111111) begin
// iszero = 1;
// end
casez(zeroes)
8'b1111111?: expdiff = 3'b111; // No need to check for 8'b11111111 since iszero is one in that case!
8'b1111110?: expdiff = 3'b110;
8'b111110??: expdiff = 3'b101;
8'b11110???: expdiff = 3'b100;
8'b1110????: expdiff = 3'b011;
8'b110?????: expdiff = 3'b010;
8'b10??????: expdiff = 3'b001;
8'b0???????: expdiff = 3'b000;
endcase // casez (zeroes) // 4 LUTs (?)
casez({overflow_bit,zeroes[3:0]})
5'b1????: expdiff_mux1 = 3;
5'b0111?: expdiff_mux1 = 3;
5'b0110?: expdiff_mux1 = 2;
5'b010??: expdiff_mux1 = 1;
5'b00???: expdiff_mux1 = 0;
endcase // casez (zeroes) // 4 LUTs (?)
casez(zeroes[7:4])
4'b111?: expdiff_mux0 = 3;
4'b110?: expdiff_mux0 = 2;
4'b10??: expdiff_mux0 = 1;
4'b0???: expdiff_mux0 = 0;
endcase // casez (zeroes) // 4 LUTs (?)
expdiff_carryin = overflow_bit;
// if(mantissa_4[30] ) begin
// expdiff = 0; // In this case, expdiff will be ignored.
// end
// In the code below, 30:5 is used to check for rounded
// overflow. expdiff_carryin will be of course be set in this
// case as well. (Both because mantissa_4[30] is set
// (c.f. above) and because the following condition is true.
if(mantissa_4[29:5] == 25'h1ffffff) begin
// expdiff = 0; // Expdiff value doesn't matter in this case!
expdiff_carryin = 1;
end
end // always @ *
(* KEEP = "SOFT" *) reg [30:0] mantissa_mux_0,mantissa_mux_1;
wire [30:0] mantissa_shifted;
wire [30:0] overflow_mantissa = {3'b000, mantissa_4[30:5], |mantissa_4[4:0]};
wire [30:0] overflow_or_normal_mantissa = overflow_bit ? overflow_mantissa : {mantissa_4[1:0], 28'b0};
always @* begin
case(expdiff_mux1[1:0])
3: mantissa_mux_1 = overflow_mantissa; // Corresponds to expdiff = 7
2: mantissa_mux_1 = {mantissa_4[5:0], 24'b0}; // Corresponds to expdiff = 6
1: mantissa_mux_1 = {mantissa_4[9:0], 20'b0}; // Corresponds to expdiff = 5
0: mantissa_mux_1 = {mantissa_4[13:0], 16'b0}; // Corresponds to expdiff = 4
endcase // case (expdiff[1:0])
case(expdiff_mux0[1:0])
3: mantissa_mux_0 = {mantissa_4[17:0], 12'b0}; // Corresponds to expdiff = 3
2: mantissa_mux_0 = {mantissa_4[21:0], 8'b0}; // Corresponds to expdiff = 2
1: mantissa_mux_0 = {mantissa_4[25:0], 4'b0}; // Corresponds to expdiff = 1
0: mantissa_mux_0 = {mantissa_4[29:0]}; // Corresponds to expdiff = 0
endcase // casez (expdiff[1:0])
end // always @ *
/*
// FIXME - very wasteful since this mux is only needed in a few
// cases due to the large number of zeroes in the expression above.
generate
genvar i;
for(i=0; i <= 30; i = i + 1) begin : f7mux
MUXF7 f7(.I0(mantissa_mux_0[i]),
.I1(mantissa_mux_1[i]),
.S(expdiff[2]),
.O(mantissa_shifted[i]));
end
endgenerate
*/
assign mantissa_shifted = (expdiff[2] || overflow_bit) ? mantissa_mux_1 : mantissa_mux_0;
wire [`EXPONENTBITS:0] expdiff_tmp = expdiff_carryin ? 8'b11111111 : expdiff;
always @(posedge clk) begin
result_5 <= result_4;
// $display("Zeroes is %x", zeroes);
// Note: the case where zeroes == 8'b11111111 is handled implicitly since
// the mantissa is all zero in this case. (That is, mantissa_5 will be set to 0,
// regardless of the setting of expdiff!)
// casez (expdiff)
// 7: mantissa_5 <= {mantissa_4[1:0], 28'b0};
// 6: mantissa_5 <= {mantissa_4[5:0], 24'b0};
// 5: mantissa_5 <= {mantissa_4[9:0], 20'b0};
// 4: mantissa_5 <= {mantissa_4[13:0], 16'b0};
// 3: mantissa_5 <= {mantissa_4[17:0], 12'b0};
// 2: mantissa_5 <= {mantissa_4[21:0], 8'b0};
// 1: mantissa_5 <= {mantissa_4[25:0], 4'b0};
// 0: mantissa_5 <= {mantissa_4[29:0]};
// endcase // casez (zeroes)
mantissa_5 <= mantissa_shifted;
// 4-1 mux: 1 LUT
// 8-1 mux: 2 LUT
// 31 bit 8-1 mux: 62 LUTs (less due to use of reset input!)
// This is the same as the statement above but tweaked so that we hopefully get only one adder.
result_5`EXPONENT <= result_4`EXPONENT - expdiff_tmp;
// if(iszero) result_5`EXPSPEC <= 0;
// if(overflow_bit) begin
// result_5`EXPONENT <= result_4`EXPONENT + 1; // This might also overflow but is also handled below during overflow check.
// mantissa_5 <= {3'b000, mantissa_4[30:5], |mantissa_4[4:0] }; // Oops, a 9-1 mux!
// end
// Detect if rounding operation will overflow!
// Note: Since this is an odd number there is no need to check/generate sticky bit (e.g. |mantissa_4[4:0]
if(rounding_will_overflow) begin
mantissa_5 <= {4'b0001, 26'h0}; // Reset/Set input could be used for this...
// result_5`EXPONENT <= result_4`EXPONENT + 1; // Might overflow but this is handled below during the overflow check where the INF bit will be set.
end
// OVERFLOW!
if(result_4`EXPONENT == 63+8'b01000000) begin
// A thorough testing is needed to determine if this works correctly or not.
if(mantissa_4[29] && !result_4`SPECIAL) begin
result_5`IS_INF_OR_NAN <= 1;
result_5`HRFP_IS_NAN <= 0;
end
end
end // always @ (posedge clk)
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9 + 10; const long long int LINF = 1LL * INF * INF; const int MAXN = 2e5 + 10; const int MAXM = 5e3 + 10; priority_queue<int> pq; vector<vector<int> > graph; queue<int> que; long long int mygcd(long long int a, long long int b) { return a ? mygcd(b % a, a) : b; } int main() { long long int n, m, k, a, b, x, y, q; int sum = 0; int cnt = 0; int mx = 0; int mn = INF; int cur = 0, idx = -1; int tc; ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n; long long int res = n; for (long long int i = 1; i * i <= n; i++) { if (n % i) continue; a = mygcd(i, n / i); if (a == 1) { res = min(n / i, res); } } cout << n / res << << res << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const long long inf = 1e18; const int maxn = 2e5 + 10; const double eps = 1e-7; const double pi = 3.14159265359; long long n, m, a[maxn], par[maxn]; bool check(int x) { long long now = 0; long long cnt = 0; long long cal = 0; for (int i = 0; i < n; i++) { if (cal >= x) { cal = 0; cnt++; } if (a[i] - cnt > 0) { now += a[i] - cnt; cal++; } } if (now >= m) { return 1; } return 0; } int main() { std::ios::sync_with_stdio(0); ; cin.tie(0); cout.tie(0); cin >> n >> m; for (int i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); reverse(a, a + n); par[0] = a[0]; for (int i = 1; i < n; i++) { par[i] = par[i - 1] + a[i]; } int ans = -1; long long l = 1, r = n + 5, mid; while (l <= r) { mid = (l + r) / 2; if (check(mid)) { ans = mid; r = mid - 1; } else { l = mid + 1; } } cout << ans; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR3_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__OR3_PP_BLACKBOX_V
/**
* or3: 3-input OR.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__or3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR3_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O31AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__O31AI_BEHAVIORAL_PP_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__o31ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O31AI_BEHAVIORAL_PP_V |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (clk);
input clk;
reg [43:0] mi;
reg [5:0] index;
integer indexi;
reg read;
initial begin
// Static
mi = 44'b01010101010101010101010101010101010101010101;
if (mi[0] !== 1'b1) $stop;
if (mi[1 -: 2] !== 2'b01) $stop;
`ifdef VERILATOR
// verilator lint_off SELRANGE
if (mi[-1] !== 1'bx && mi[-1] !== 1'b0) $stop;
if (mi[0 -: 2] !== 2'b1x && 1'b0) $stop;
if (mi[-1 -: 2] !== 2'bxx && 1'b0) $stop;
// verilator lint_on SELRANGE
`else
if (mi[-1] !== 1'bx) $stop;
if (mi[0 -: 2] !== 2'b1x) $stop;
if (mi[-1 -: 2] !== 2'bxx) $stop;
`endif
end
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
mi = 44'h123;
end
if (cyc==2) begin
index = 6'd43;
indexi = 43;
end
if (cyc==3) begin
read = mi[index];
if (read!==1'b0) $stop;
read = mi[indexi];
if (read!==1'b0) $stop;
end
if (cyc==4) begin
index = 6'd44;
indexi = 44;
end
if (cyc==5) begin
read = mi[index];
$display("-Illegal read value: %x", read);
//if (read!==1'b1 && read!==1'bx) $stop;
read = mi[indexi];
$display("-Illegal read value: %x", read);
//if (read!==1'b1 && read!==1'bx) $stop;
end
if (cyc==6) begin
indexi = -1;
end
if (cyc==7) begin
read = mi[indexi];
$display("-Illegal read value: %x", read);
//if (read!==1'b1 && read!==1'bx) $stop;
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1000000007; long long int inverse(long long int i) { if (i == 1) return 1; return (MOD - ((MOD / i) * inverse(MOD % i)) % MOD + MOD) % MOD; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n; cin >> n; string s; cin >> s; long long x = 0, y = 0, ans = 0, len = 0, last; for (int i = 0; i < n; i++) { cin >> s; if (s[i] == U ) y++; else if (s[i] == D ) y--; else if (s[i] == R ) x++; else x--; len++; if (len > (abs(x) + abs(y))) { x = 0; y = 0; len = 0; ans++; i--; last = i; } } if (last != (n - 1)) ans++; cout << ans; } |
module testbench_CLA_Array();
localparam bits = 64;
reg[bits-1:0] a;
reg[bits-1:0] b;
reg cin;
wire[bits-1:0] result;
wire cout;
wire[bits:0] expectOutput;
reg errorFlag = 0;
integer i;
assign expectOutput = a + b + cin;
initial begin
a = 64'h1111111111111111;
b = 64'hffffffffffffffff;
cin = 1;
#10;
if ({cout,result} !== expectOutput) begin
errorFlag = 1;
$display("test fail: expect %x + %x = %x, actual %x", a, b, {cout,result}, expectOutput);
end
a = 64'h0000000000000000;
b = 64'hffffffffffffffff;
cin = 1;
#10;
if ({cout,result} !== expectOutput) begin
errorFlag = 1;
$display("test fail: expect %x + %x = %x, actual %x", a, b, {cout,result}, expectOutput);
end
a = 64'h1111111111111111;
b = 64'heeeeeeeeeeeeeeee;
cin = 1;
#10;
if ({cout,result} !== expectOutput) begin
errorFlag = 1;
$display("test fail: expect %x + %x = %x, actual %x", a, b, {cout,result}, expectOutput);
end
for(i = 0;i < 32'hffff; i = i+1) begin
a = {$random(), $random()};
b = {$random(), $random()};
cin = ($random()&1);
#10;
if ({cout,result} !== expectOutput) begin
errorFlag = 1;
$display("test fail: expect %x + %x = %x, actual %x", a, b, {cout,result}, expectOutput);
end
end
if (errorFlag === 0) begin
$display("Test passed");
end
else begin
$display("Test failed");
end
end
CLA_Array #16 cla(.a(a), .b(b), .cin(cin), .result(result), .cout(cout));
endmodule
|
/*
* Copyright 2017 Google Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`define IVERILOG_SIM
`define TEST_PROG "prog_mul.list"
`include "top.v"
module top_test_mul;
localparam WIDTH = 8;
localparam UART_WIDTH = $clog2(WIDTH);
localparam MUL_WIDTH = WIDTH / 2;
reg clk = 1;
reg uart_clk = 0;
reg receiving = 0;
reg display = 0;
reg [UART_WIDTH-1 : 0] serial_cnt = 0;
reg [WIDTH-1 : 0] serial_data;
wire uart_tx;
reg [WIDTH-1 : 0] in_args = 2;
reg [WIDTH-1 : 0] expected_output = 0;
always #2 clk = !clk;
always #4 uart_clk = !uart_clk;
top t(
.clk(clk),
.uart_tx_line(uart_tx));
always @ (posedge uart_clk) begin
if (receiving) begin
if (serial_cnt == WIDTH - 1) begin
receiving <= 0;
display <= 1;
end
serial_data[serial_cnt] <= uart_tx;
serial_cnt <= serial_cnt + 1;
end else if (display) begin
if (in_args == 0) begin
$display("Multiply4x4 test passed!\n");
$finish;
end
if (serial_data != expected_output) begin
$display("Multiply4x4 test failed!\n");
$display("Serial output:%d doesn't match expected_output:%d\n",
serial_data, expected_output);
$finish;
end
in_args <= in_args + 1;
expected_output <= in_args[WIDTH-1 : MUL_WIDTH] * in_args[MUL_WIDTH-1 : 0];
display <= 0;
end else begin
if (uart_tx == 0) begin
receiving <= 1;
end
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Tue Sep 26 16:58:56 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dbg_ila_stub.v
// Design : dbg_ila
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
probe18, probe19, probe20, probe21, probe22, probe23)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[63:0],probe8[0:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[63:0],probe13[0:0],probe14[0:0],probe15[0:0],probe16[0:0],probe17[0:0],probe18[7:0],probe19[7:0],probe20[0:0],probe21[2:0],probe22[2:0],probe23[0:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [0:0]probe2;
input [0:0]probe3;
input [0:0]probe4;
input [0:0]probe5;
input [0:0]probe6;
input [63:0]probe7;
input [0:0]probe8;
input [0:0]probe9;
input [0:0]probe10;
input [0:0]probe11;
input [63:0]probe12;
input [0:0]probe13;
input [0:0]probe14;
input [0:0]probe15;
input [0:0]probe16;
input [0:0]probe17;
input [7:0]probe18;
input [7:0]probe19;
input [0:0]probe20;
input [2:0]probe21;
input [2:0]probe22;
input [0:0]probe23;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
integer i;
reg [63:0] mem [7:0];
always @ (posedge clk) begin
if (cyc==1) begin
for (i=0; i<8; i=i+1) begin
mem[i] <= 64'h0;
end
end
else begin
mem[0] <= crc;
for (i=1; i<8; i=i+1) begin
mem[i] <= mem[i-1];
end
end
end
wire [63:0] outData = mem[7];
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%b q=%x\n",$time, cyc, crc, outData);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc==90) begin
if (outData != 64'h1265e3bddcd9bc27) $stop;
end
else if (cyc==91) begin
if (outData != 64'h24cbc77bb9b3784e) $stop;
end
else if (cyc==92) begin
end
else if (cyc==93) begin
end
else if (cyc==94) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; double r, L; double b, u, A; double x, y, a; double D[95], B[95]; struct st { double x, y, a; }; st bear[50]; int t; double fun(int i, double l) { x = bear[i].x; y = bear[i].y; t = bear[i].a; a = B[t]; b = (fabs(l - x) / y); A = D[t]; if (x < l) u = ((A + b) / (1 - A * b)) * y - l + x; else { if (a < b) u = x - l - ((b - A) / (1 + b * A)) * y; else u = ((A - b) / (1 + A * b)) * y + x - l; } if (u < 0) return 1e9; return u; } const int N = (1 << 20) + 10; double d[N][22]; int main() { for (int i = 1; i <= 90; i++) { B[i] = i * acosl(-1) / 180; D[i] = tan(B[i]); } double l; int n; cin >> n >> l >> r; L = l; for (int i = 0; i < n; i++) cin >> bear[i].x >> bear[i].y >> bear[i].a; int m = (1 << n) - 1, i, j, k; double ans = -1e9; for (i = 1; i <= m; i++) { for (j = 0; j < n; j++) { if (((1 << j) & i)) { d[i][j] = -1e9; if ((1 << j) == i) { d[i][j] = l + fun(j, l); ans = max(ans, d[i][j]); } else { for (k = 0; k < n; k++) { if (((1 << k) & i) && j != k) { d[i][j] = max(d[i][j], d[i ^ (1 << j)][k] + fun(j, d[i ^ (1 << j)][k])); ans = max(ans, d[i][j]); } } } } } } printf( %.6f , min(ans - L, r - L)); } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun Apr 09 08:27:07 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_vga_split_controller_0_0/system_vga_split_controller_0_0_stub.v
// Design : system_vga_split_controller_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_split_controller,Vivado 2016.4" *)
module system_vga_split_controller_0_0(rgb_0, rgb_1, clock, hsync, rgb)
/* synthesis syn_black_box black_box_pad_pin="rgb_0[15:0],rgb_1[15:0],clock,hsync,rgb[15:0]" */;
input [15:0]rgb_0;
input [15:0]rgb_1;
input clock;
input hsync;
output [15:0]rgb;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND3B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__AND3B_FUNCTIONAL_PP_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__and3b (
VPWR,
VGND,
X ,
A_N ,
B ,
C
);
// Module ports
input VPWR;
input VGND;
output X ;
input A_N ;
input B ;
input C ;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , C, not0_out, B );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND3B_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; template <typename T> void print(const T& t) { cout << t << n ; } template <typename T, typename U, typename... ARGS> void print(const T& t, const U& u, const ARGS&... args) { cout << t << ; print(u, args...); } signed main() { ios_base::sync_with_stdio(false), cin.tie(nullptr); long long tc; cin >> tc; while (tc--) { long long x, y, n; cin >> x >> y >> n; long long z = (n / x) * x; while (z + y > n) { z -= x; } print(z + y); } return 0; } |
module reg_ro_4burst(
input wire clk,
input wire [15:0] bus_ad, // raw mux data
input wire [18:0] my_a,
input wire [2:0] bus_a, // high address bits
input wire adv, // active high, so connect to !EIM_LBA
input wire rw, // low = write, high = read, so connect to EIM_RW
input wire cs, // active high, so connect to !EIM_CS[1]
input wire [63:0] reg_d,
output reg [15:0] rbk_d, // readback tri-state interface
output wire strobe
);
reg [2:0] bcount;
reg activated;
reg [15:0] bus_ad_r;
reg cs_r;
reg [2:0] bus_a_r;
reg rw_r;
reg adv_r;
reg [2:0] activated_d;
always @(posedge clk) begin
activated_d[2:0] <= {activated_d[1:0],activated};
end
// delay a couple cycles to avoid pre-mature changing of read data
assign strobe = activated_d[2] & !activated_d[1]; // pulse on falling edge of activated
////// address decode path
always @(posedge clk) begin
bus_ad_r <= bus_ad;
bus_a_r <= bus_a;
cs_r <= cs;
rw_r <= rw;
adv_r <= adv;
if( cs_r && adv_r && ({bus_a_r, bus_ad_r} == my_a) ) begin
activated <= 1'b1;
bcount <= 3'b0;
end else if( !cs_r ) begin
activated <= 1'b0;
bcount <= 3'b0;
end else begin
activated <= activated;
// chip select is active, and we're beyond the address latch stage
if( bcount <= 3'b111 ) begin
bcount <= bcount + 3'b01;
end else begin
bcount <= bcount;
end
end // else: !if( !cs )
end // always @ (posedge clk)
always @(*) begin
if( activated && rw_r ) begin
case (bcount) // bcount is delayed by one due to adr-to-oe turnaround provision
3'b0001: begin
rbk_d = reg_d[15:0];
end
3'b010: begin
rbk_d = reg_d[31:16];
end
3'b011: begin
rbk_d = reg_d[47:32];
end
3'b100: begin
rbk_d = reg_d[63:48];
end
default: begin
rbk_d = 16'hZZZZ;
end
endcase // case (bcount)
end else begin // if ( activated && rw )
rbk_d = 16'hZZZZ;
end // else: !if( activated && rw )
end
endmodule // reg_wo_4burst
|
#include <bits/stdc++.h> using namespace std; map<int, int> cnt; int n; int m; int dp[500][100005]; vector<int> num; map<int, int> can; int ind = 0; int dpnum[500]; map<int, int> mpind; map<int, int> mpvis; int main() { scanf( %d%d , &n, &m); int x; for (int i = 0; i < n; i++) { scanf( %d , &x); num.push_back(x); if (can[x] == 0) { if (cnt[x] < x) { cnt[x]++; } if (cnt[x] == x) { can[x] = 1; } } } for (int i = 0; i < n; i++) { if (!can[num[i]]) continue; if (mpind[num[i]] != 0) continue; if (mpind[num[i]] == 0) { ind++; mpind[num[i]] = ind; dpnum[ind] = num[i]; } int tind = mpind[num[i]]; for (int j = 0; j < n; j++) { if (j == 0) { if (num[j] == num[i]) dp[tind][j + 1] = 1; else dp[tind][j + 1] = 0; } else { if (num[j] == num[i]) dp[tind][j + 1] = dp[tind][j] + 1; else dp[tind][j + 1] = dp[tind][j]; } } } int l, r; for (int i = 0; i < m; i++) { scanf( %d%d , &l, &r); int ans = 0; for (int i = 1; i <= ind; i++) { if (dp[i][r] - dp[i][l - 1] == dpnum[i]) { ans++; } } printf( %d n , ans); } return 0; } |
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 1
(* X_CORE_INFO = "xlconcat_v2_1_1_xlconcat,Vivado 2017.2" *)
(* CHECK_LICENSE_TYPE = "bd_c3fe_slot_0_b_0,xlconcat_v2_1_1_xlconcat,{}" *)
(* CORE_GENERATION_INFO = "bd_c3fe_slot_0_b_0,xlconcat_v2_1_1_xlconcat,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WI\
DTH=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=2,NUM_PORTS=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module bd_c3fe_slot_0_b_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat_v2_1_1_xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 205; int mat[maxn][maxn], tmp[maxn][maxn]; int r[maxn], c[maxn]; int n, m; void invRow(int row) { for (int j = 1; j <= m; ++j) { tmp[row][j] ^= 1; } } void invCol(int col) { for (int i = 1; i <= n; ++i) { tmp[i][col] ^= 1; } } bool solve(int x, int y) { memset(tmp, 0, sizeof(tmp)); memset(r, 0, sizeof(r)); memset(c, 0, sizeof(c)); for (int i = x; i <= n; ++i) { for (int j = 1; j <= m; ++j) { if (i == x && j < y) tmp[i][j] = 0; else tmp[i][j] = 1; } } for (int i = 1; i <= n; ++i) r[i] = mat[i][1] ^ tmp[i][1] ^ c[1]; for (int j = 1; j <= m; ++j) c[j] = mat[1][j] ^ tmp[1][j] ^ r[1]; for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { if ((r[i] ^ c[j]) != (mat[i][j] ^ tmp[i][j])) return false; } } return true; } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { scanf( %d , &mat[i][j]); } } for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { if (solve(i, j)) { puts( YES ); for (int i = 1; i <= n; ++i) printf( %d , r[i]); putchar( n ); for (int j = 1; j <= m; ++j) printf( %d , c[j]); putchar( n ); return 0; } } } puts( NO ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); vector<long long> X(n + 1), Y(n + 1); for (int i = (1); i <= (n); ++i) scanf( %lld%lld , &X[i], &Y[i]); long long S = 0; for (int k = (1); k <= (n); ++k) { vector<double> V; for (int i = (1); i <= (n); ++i) if (i != k) V.push_back(atan2(Y[i] - Y[k], X[i] - X[k])); sort(V.begin(), V.end()); V.insert(V.end(), V.begin(), V.end()); for (int i = 0, j = 0; i + 1 < n; i++) { while (V[j] + (j >= n - 1 ? 2 * acos(-1) : 0.0) - V[i] < acos(-1)) j++; long long x = j - 1 - i, y = n - 2 - x; S += x * (x - 1) / 2 * y * (y - 1) / 2; } } printf( %lld n , S / 2); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, b; int t[200005], d[200005]; queue<pair<int, pair<int, int> > > Q; long long ans[200005]; int main() { int i, j; scanf( %d , &n); scanf( %d , &b); for (i = 1; i <= n; i++) { scanf( %d , &t[i]); scanf( %d , &d[i]); } memset(ans, -1, sizeof(ans)); long long curr = 0; i = 1; while (1) { if (i <= n && Q.size() == 0) { Q.push({i, {t[i], d[i]}}); i++; } if (Q.size() == 0) break; pair<int, pair<int, int> > now = Q.front(); Q.pop(); curr = max(curr, (long long)now.second.first); long long en = curr + now.second.second; ans[now.first] = en; while (i <= n && Q.size() < b) { Q.push({i, {t[i], d[i]}}); i++; } while (i <= n && t[i] < en) { i++; } curr = en; } for (i = 1; i <= n; i++) printf( %lld , ans[i]); return 0; } |
//-----------------------------------------------------------------------------
//-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
//-- systems, Class III medical devices, nuclear facilities,
//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//Purpose:
// Synchronous, shallow FIFO that uses simple as a DP Memory.
// This requires about 1/2 the resources as a Distributed RAM DPRAM
// implementation.
//
// This FIFO will have the current data on the output when data is contained
// in the FIFO. When the FIFO is empty, the output data is invalid.
//
//Reference:
//Revision History:
//
//-----------------------------------------------
//
// MODULE: axi_mc_simple_fifo
//
// This is the simplest form of inferring the
// simple/SRL(16/32)CE in a Xilinx FPGA.
//
//-----------------------------------------------
`timescale 1ns / 100ps
`default_nettype none
module mig_7series_v4_0_axi_mc_simple_fifo #
(
parameter C_WIDTH = 8,
parameter C_AWIDTH = 4,
parameter C_DEPTH = 16
)
(
input wire clk, // Main System Clock (Sync FIFO)
input wire rst, // FIFO Counter Reset (Clk
input wire wr_en, // FIFO Write Enable (Clk)
input wire rd_en, // FIFO Read Enable (Clk)
input wire [C_WIDTH-1:0] din, // FIFO Data Input (Clk)
output wire [C_WIDTH-1:0] dout, // FIFO Data Output (Clk)
output wire a_full,
output wire full, // FIFO FULL Status (Clk)
output wire a_empty,
output wire empty // FIFO EMPTY Status (Clk)
);
///////////////////////////////////////
// FIFO Local Parameters
///////////////////////////////////////
localparam [C_AWIDTH-1:0] C_EMPTY = ~(0);
localparam [C_AWIDTH-1:0] C_EMPTY_PRE = (0);
localparam [C_AWIDTH-1:0] C_FULL = C_EMPTY-1;
localparam [C_AWIDTH-1:0] C_FULL_PRE = (C_DEPTH < 8) ? C_FULL-1 : C_FULL-(C_DEPTH/8);
///////////////////////////////////////
// FIFO Internal Signals
///////////////////////////////////////
reg [C_WIDTH-1:0] memory [C_DEPTH-1:0];
reg [C_AWIDTH-1:0] cnt_read;
///////////////////////////////////////
// Main simple FIFO Array
///////////////////////////////////////
always @(posedge clk) begin : BLKSRL
integer i;
if (wr_en) begin
for (i = 0; i < C_DEPTH-1; i = i + 1) begin
memory[i+1] <= memory[i];
end
memory[0] <= din;
end
end
///////////////////////////////////////
// Read Index Counter
// Up/Down Counter
// *** Notice that there is no ***
// *** OVERRUN protection. ***
///////////////////////////////////////
always @(posedge clk) begin
if (rst) cnt_read <= C_EMPTY;
else if ( wr_en & !rd_en) cnt_read <= cnt_read + 1'b1;
else if (!wr_en & rd_en) cnt_read <= cnt_read - 1'b1;
end
///////////////////////////////////////
// Status Flags / Outputs
// These could be registered, but would
// increase logic in order to pre-decode
// FULL/EMPTY status.
///////////////////////////////////////
assign full = (cnt_read == C_FULL);
assign empty = (cnt_read == C_EMPTY);
assign a_full = ((cnt_read >= C_FULL_PRE) && (cnt_read != C_EMPTY));
assign a_empty = (cnt_read == C_EMPTY_PRE);
assign dout = (C_DEPTH == 1) ? memory[0] : memory[cnt_read];
endmodule // axi_mc_simple_fifo
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; const int N = 111; int a[N], b[N]; int main() { cin.tie(0)->sync_with_stdio(0); int t; cin >> t; while (t--) { queue<int> que; int n; cin >> n; string S; cin >> S; S = + S; for (int i = 1; i <= n; i++) { if (S[i] == R ) { a[i] = 1; b[i] = 1; que.push(i); } else if (S[i] == B ) { a[i] = 2; b[i] = 2; que.push(i); } else { a[i] = 3; b[i] = 3; } } if (que.empty()) { for (int i = 1; i <= n; i++) { if (i % 2 == 1) cout << R ; else cout << B ; } cout << n ; continue; } while (!que.empty()) { int x = que.front(); que.pop(); int left = x - 1; int right = x + 1; while (b[left] == 3 && left >= 1) { if (b[left + 1] == 1) { b[left] = 2; left--; } else { b[left] = 1; left--; } } while (b[right] == 3 && right <= n) { if (b[right - 1] == 1) { b[right] = 2; right++; } else { b[right] = 1; right++; } } } for (int i = 1; i <= n; i++) { if (b[i] == 1) cout << R ; else cout << B ; } cout << n ; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUXB8TO1_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__MUXB8TO1_BEHAVIORAL_PP_V
/**
* muxb8to1: Buffered 8-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__muxb8to1 (
Z ,
D ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input [7:0] D ;
input [7:0] S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_d0 ;
wire pwrgood_pp1_out_s0 ;
wire pwrgood_pp2_out_d1 ;
wire pwrgood_pp3_out_s1 ;
wire pwrgood_pp4_out_d2 ;
wire pwrgood_pp5_out_s2 ;
wire pwrgood_pp6_out_d3 ;
wire pwrgood_pp7_out_s3 ;
wire pwrgood_pp8_out_d4 ;
wire pwrgood_pp9_out_s4 ;
wire pwrgood_pp10_out_d5;
wire pwrgood_pp11_out_s5;
wire pwrgood_pp12_out_d6;
wire pwrgood_pp13_out_s6;
wire pwrgood_pp14_out_d7;
wire pwrgood_pp15_out_s7;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_d0 , D[0], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_s0 , S[0], VPWR, VGND );
bufif1 bufif10 (Z , !pwrgood_pp0_out_d0, pwrgood_pp1_out_s0 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp2 (pwrgood_pp2_out_d1 , D[1], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp3 (pwrgood_pp3_out_s1 , S[1], VPWR, VGND );
bufif1 bufif11 (Z , !pwrgood_pp2_out_d1, pwrgood_pp3_out_s1 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp4 (pwrgood_pp4_out_d2 , D[2], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp5 (pwrgood_pp5_out_s2 , S[2], VPWR, VGND );
bufif1 bufif12 (Z , !pwrgood_pp4_out_d2, pwrgood_pp5_out_s2 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp6 (pwrgood_pp6_out_d3 , D[3], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp7 (pwrgood_pp7_out_s3 , S[3], VPWR, VGND );
bufif1 bufif13 (Z , !pwrgood_pp6_out_d3, pwrgood_pp7_out_s3 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp8 (pwrgood_pp8_out_d4 , D[4], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp9 (pwrgood_pp9_out_s4 , S[4], VPWR, VGND );
bufif1 bufif14 (Z , !pwrgood_pp8_out_d4, pwrgood_pp9_out_s4 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp10 (pwrgood_pp10_out_d5, D[5], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp11 (pwrgood_pp11_out_s5, S[5], VPWR, VGND );
bufif1 bufif15 (Z , !pwrgood_pp10_out_d5, pwrgood_pp11_out_s5);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp12 (pwrgood_pp12_out_d6, D[6], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp13 (pwrgood_pp13_out_s6, S[6], VPWR, VGND );
bufif1 bufif16 (Z , !pwrgood_pp12_out_d6, pwrgood_pp13_out_s6);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp14 (pwrgood_pp14_out_d7, D[7], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp15 (pwrgood_pp15_out_s7, S[7], VPWR, VGND );
bufif1 bufif17 (Z , !pwrgood_pp14_out_d7, pwrgood_pp15_out_s7);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUXB8TO1_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR2B_1_V
`define SKY130_FD_SC_LS__NOR2B_1_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor2b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nor2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor2b_1 (
Y ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor2b_1 (
Y ,
A ,
B_N
);
output Y ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR2B_1_V
|
#include <bits/stdc++.h> using namespace std; int n, x, y, u, v, to[600005], nxt[600005], p[300005], sz[300005]; void dfs(int x, int lst) { sz[x] = 1; for (int i = p[x]; i != -1; i = nxt[i]) if (to[i] != lst) { dfs(to[i], x); sz[x] += sz[to[i]]; } } int main() { scanf( %d%d%d , &n, &x, &y); memset(p, -1, sizeof p); for (int i = 1; i < n; i++) { scanf( %d%d , &u, &v); to[i * 2 - 1] = v, nxt[i * 2 - 1] = p[u], p[u] = i * 2 - 1; to[i * 2] = u, nxt[i * 2] = p[v], p[v] = i * 2; } dfs(x, -1); long long ans = sz[y]; dfs(y, -1); ans *= sz[x]; cout << 1LL * n * (n - 1) - ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; double res, a, b; int main() { int n, k; cin >> n >> k; vector<double> x(n), y(n); for (int i = 0; i < n; i++) { cin >> x[i] >> y[i]; if (i) { a = x[i] - x[i - 1]; b = y[i] - y[i - 1]; res += sqrt((a * a) + (b * b)); } } res /= 50; cout << setprecision(10) << res * k << endl; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A22O_BEHAVIORAL_V
`define SKY130_FD_SC_HD__A22O_BEHAVIORAL_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a22o (
X ,
A1,
A2,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X, and1_out, and0_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A22O_BEHAVIORAL_V |
//This is a 3-stage integer pipeline.
//It fetches dependencies, executes, and writes back to a register file.
module intpipe(
CLK,
PAUSE,
EMPTY,
OPCODE,
A,
B,
C,
ADAT,
BDAT,
FLGS,
aSel,
bSel,
cSel,
cOut,
cWrite,
flgs
);
input CLK;
input PAUSE;
input EMPTY;
input [3:0] OPCODE;
input [2:0] A;
input [2:0] B;
input [2:0] C;
input [15:0] ADAT;
input [15:0] BDAT;
input [7:0] FLGS;
output [2:0] aSel;
output [2:0] bSel;
output [2:0] cSel;
output [15:0] cOut;
output cWrite;
output [7:0] flgs;
wire [15:0] aPath [1:0];
wire [15:0] bPath [1:0];
wire [15:0] aluOut;
wire [3:0] aluOp;
wire [7:0] flgIn;
wire [7:0] flgOut;
reg [7:0] flgs;
wire writeBack;
reg [3:0] opCodeShifter[1:0];
reg [3:0] writeBackRegShifter[2:0];
//reg [15:0] datShifter[1:0]
reg [15:0] aluOutput;
reg [15:0] aDatShifter[1:0];
reg [15:0] bDatShifter[1:0];
reg write;
assign cWrite=write&&(~PAUSE);
wire aPathSel;
wire bPathSel;
assign flgs=flgOut;
assign FLGS=flgIn;
assign aPathSel=writeBackRegShifter[2]==A;
assign bPathSel=writeBackRegShifter[2]==B;
assign aSel=A;
assign bSel=B;
assign cSel=writeBackRegShifter[2];
assign cOut=aluOutput;
assign aPath[0]=aDatShifter[1];
assign aPath[1]=aluOut;
assign bPath[0]=bDatShifter[1];
assign bPath[1]=aluOut;
assign aluOp=opCodeShifter[1];
wire [15:0] AD1;
assign AD1=aDatShifter[0];
wire [15:0] AD2;
assign AD2=aDatShifter[1];
//Build an ALU:
ALU a(aluOp, flgIn, aPath[aPathSel], bPath[bPathSel], flgOut, aluOut, writeBack);
always@(posedge CLK) begin
if(PAUSE==1) begin
//Do nothing!
//Please note that the write output should be anded with pause.
end
else if(EMPTY==0) begin //Do something!
//Set the next string of ops:
opCodeShifter[0]<=OPCODE;
opCodeShifter[1]<=opCodeShifter[0];
writeBackRegShifter[0]<=C;
writeBackRegShifter[1]<=writeBackRegShifter[0];
writeBackRegShifter[2]<=writeBackRegShifter[1];
aluOutput<=aluOut;
write<=writeBack;
aDatShifter[0]<=ADAT;
bDatShifter[0]<=BDAT;
aDatShifter[1]<=aDatShifter[0];
bDatShifter[1]<=bDatShifter[0];
end
else begin //This means that EMPTY is true.
opCodeShifter[0]<=0;
opCodeShifter[1]<=0;
writeBackRegShifter[0]<=0;
writeBackRegShifter[1]<=0;
writeBackRegShifter[2]<=0;
aluOutput<=0;
write<=0;
aDatShifter[0]<=0;
aDatShifter[1]<=0;
bDatShifter[0]<=0;
bDatShifter[1]<=0;
end
end
//This is actually unnecessary. The register file
//operates off of the same clock source and thus would use that for gating.
//always@(negedge CLK) begin
// if(write==1) begin
// write<=~write; //Ensure that the register file can catch up.
// end
//end
initial begin
opCodeShifter[0]=0;
writeBackRegShifter[0]=0;
writeBackRegShifter[2]=0;
aluOutput=0;
write=0;
aDatShifter[0]=0;
bDatShifter[0]=0;
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : DLP Store.
// File : dlp_store.v
// Author : Frank Bruno
// Created : 30-Dec-2008
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// this module stores the dlp data and outputs the data when needed
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module dlp_store
#(parameter BYTES = 4)
(
input hb_clk, // Host bus clock.
input hb_rstn, // Reset signal for control signals
input dlp_rstn_mc, // Synchronous stopping of DLP
input dlp_wreg_pop, // DLP push signal.
input [(BYTES*8)-1:0] dlp_data, // memory controller data in
input dlf, // format selector for format 4
input text, // text mode selector
input char_select, // character selector
input [3:0] sorg_upper, // Upper 4 bits of sorg
output reg [1:0] list_format, // Display list format
output [1:0] wcount, /* Number of registers to write:
* 00 (default) write 3 words
* 01 one word
* 10 two words
* 11 three words */
output wvs, // Wait for vertical sync */
output [31:0] table_org0, // Origin pointer to text tables
output [31:0] table_org1, // Origin pointer to text tables
output char_count, // number of characters 0=1, 1=2
output [31:0] curr_sorg, // Source origin of current entry
output [3:0] curr_pg_cnt, // Pages of current entry
output [7:0] curr_height, // height of current entry
output [7:0] curr_width, // width of current entry
output [8:2] aad,bad,cad, // Address for data
output [127:0] dl_temp, // Mux'd input to DLP
output [15:0] dest_x, // X destination for text mode
output [15:0] dest_y // Y destiantion for text mode
);
reg [127:0] dl_data_reg; // Store data from MC
reg [127:0] dl_text_reg; // Store data from MC
wire [1:0] dlp_format; /* format of the dlp, consists of
* dlf in the command reg
* reg[25:24]
* 000: 3 register write mode
* 001: dma mode
* 01x: textmode
* 1xx: four register write mode */
wire [31:0] dest0, /* XY destination of glyphs */
dest1; /* XY destination of glyphs */
wire [27:0] sorg0, /* Source origin for glyphs */
sorg1; /* Source origin for glyphs */
wire [3:0] pg_cnt0, /* number of pages of glyph */
pg_cnt1; /* number of pages of glyph */
wire [7:0] height0, /* height of glyph */
height1; /* height of glyph */
wire [7:0] width0, /* width of glyph */
width1; /* width of glyph */
wire [7:0] x_off0, /* X offset into the glyph */
x_off1; /* x offset into the glyph */
wire [7:0] y_off0, /* y offset into the glyph */
y_off1; /* y offset into the glyph */
wire curr_org; /* which half of table entry */
wire [15:0] y_off_n; /* inverted Y offset */
wire [31:0] curr_dest; /* destination of current entry */
wire [7:0] curr_x_off; /* X offset of current entry */
wire [7:0] curr_y_off; /* Y offset of current entry */
localparam
REG3 = 2'b00, // 3 registers programmable
REG4 = 2'b01, // 4 registers fixed
DMA = 2'b10, // AGP DMA mode
TEXT = 2'b11; // Text processing mode
/************************************************************************/
/* Mode selector ********************************************************/
always @*
casex ({dlf, dlp_format}) /* synopsys full_case parallel_case */
3'b1_xx: list_format = REG4;
3'b0_00: list_format = REG3;
3'b0_01: list_format = DMA;
3'b0_1x: list_format = TEXT;
endcase
/* Data Registers *******************************************************/
always @(posedge hb_clk or negedge hb_rstn)
if (!hb_rstn) begin
dl_data_reg[31] <= 1'b0;
dl_data_reg[27:24] <= 4'b0;
end else if (dlp_rstn_mc) begin
dl_data_reg[31] <= 1'b0;
dl_data_reg[27:24] <= 4'b0;
end else if (dlp_wreg_pop) begin
if (~text)
case (BYTES)
4: begin
dl_data_reg[127:96] <= dlp_data;
dl_data_reg[95:64] <= dl_data_reg[127:96];
dl_data_reg[63:32] <= dl_data_reg[95:64];
dl_data_reg[31:0] <= dl_data_reg[63:32];
end
8: begin
dl_data_reg[127:64] <= dlp_data;
dl_data_reg[63:0] <= dl_data_reg[127:64];
end
default:
// BYTES = 16
dl_data_reg <= dlp_data;
endcase // case(BYTES)
else
case (BYTES)
4: begin
dl_text_reg[127:96] <= dlp_data;
dl_text_reg[95:64] <= dl_text_reg[127:96];
dl_text_reg[63:32] <= dl_text_reg[95:64];
dl_text_reg[31:0] <= dl_text_reg[63:32];
end
8: begin
dl_text_reg[127:64] <= dlp_data;
dl_text_reg[63:0] <= dl_text_reg[127:64];
end
default:
// BYTES = 16
dl_text_reg <= dlp_data;
endcase // case(BYTES)
end
/* Address Mux **********************************************************/
assign dl_temp = dl_data_reg;
// Command Data for REG3, REG4, DMA modes
assign aad = {dl_data_reg[28], dl_data_reg[7:2]};
assign bad = {dl_data_reg[29], dl_data_reg[15:10]};
assign cad = {dl_data_reg[30], dl_data_reg[23:18]};
assign dlp_format = dl_data_reg[25:24];
assign wcount = dl_data_reg[27:26];
assign wvs = dl_data_reg[31];
// Data for TEXT mode
// assign table_org0 = {dl_data_reg[95:89], dl_data_reg[24:0]};
assign table_org0 = {7'h0, dl_data_reg[24:0]};
assign char_count = dl_data_reg[27];
assign dest0 = dl_data_reg[63:32];
// assign table_org1 = dl_data_reg[95:64];
assign table_org1 = {7'h0, dl_data_reg[88:64]};
assign dest1 = dl_data_reg[127:96];
// assign sorg0 = dl_text_reg[27:0];
assign sorg0 = {3'b000, dl_text_reg[24:0]};
assign pg_cnt0 = dl_text_reg[31:28];
assign height0 = dl_text_reg[39:32];
assign width0 = dl_text_reg[47:40];
assign y_off0 = dl_text_reg[55:48];
assign x_off0 = dl_text_reg[63:56];
// assign sorg1 = dl_text_reg[91:64];
assign sorg1 = {3'b000, dl_text_reg[88:64]};
assign pg_cnt1 = dl_text_reg[95:92];
assign height1 = dl_text_reg[103:96];
assign width1 = dl_text_reg[111:104];
assign y_off1 = dl_text_reg[119:112];
assign x_off1 = dl_text_reg[127:120];
// Select current character
assign curr_org = (char_select) ? table_org1[3] : table_org0[3];
assign curr_dest = (char_select) ? dest1 : dest0;
// assign curr_sorg = (curr_org) ? {sorg_upper, sorg1} : {sorg_upper, sorg0};
assign curr_sorg = (curr_org) ? {4'h0, sorg1} : {4'h0, sorg0};
assign curr_pg_cnt = (curr_org) ? pg_cnt1 : pg_cnt0;
assign curr_height = (curr_org) ? height1 : height0;
assign curr_width = (curr_org) ? width1 : width0;
assign curr_x_off = (curr_org) ? x_off1 : x_off0;
assign curr_y_off = (curr_org) ? y_off1 : y_off0;
//
// Formerly DLP_ALU
// X offset adder
assign dest_x = curr_dest[31:16] +
{{8{curr_x_off[7]}}, curr_x_off}; // X offset adder
// Y offset subtractor
assign y_off_n = ~{{8{curr_y_off[7]}}, curr_y_off};
assign dest_y = curr_dest[15:0] + y_off_n + 16'h1;
endmodule
|
#include <bits/stdc++.h> using namespace std; int p[400050]; int ran[400050]; int find_set(int a) { return p[a] == a ? a : (p[a] = find_set(p[a])); } int unite(int a, int b) { int x = find_set(a); int y = find_set(b); if (x == y) return -1; if (ran[x] < ran[y]) { p[x] = y; } else { p[y] = x; if (ran[x] == ran[y]) ran[x]++; } return 0; } pair<int, pair<int, int> > ed[400050]; int viz[200050]; int main() { int n, m; int s, t, ds, dt; int di = 0, dii = 0; int tes = 0; scanf( %d %d , &n, &m); for (int i = 0; i < m; i++) { int a, b; scanf( %d %d , &a, &b); ed[i] = make_pair(0, make_pair(a, b)); } scanf( %d %d %d %d , &s, &t, &ds, &dt); for (int i = 0; i < m; i++) { if ((ed[i].second.first == s && ed[i].second.second == t) || (ed[i].second.second == s && ed[i].second.first == t)) { ed[i] = make_pair(2, make_pair(ed[i].second.first, ed[i].second.second)); } else if (ed[i].second.first == s || ed[i].second.second == s) { ed[i] = make_pair(1, make_pair(ed[i].second.first, ed[i].second.second)); viz[ed[i].second.first] |= 1; viz[ed[i].second.second] |= 1; } else if (ed[i].second.first == t || ed[i].second.second == t) { ed[i] = make_pair(1, make_pair(ed[i].second.first, ed[i].second.second)); viz[ed[i].second.first] |= 2; viz[ed[i].second.second] |= 2; } } sort(ed, ed + m); for (int i = 0; i <= n; i++) { p[i] = i; ran[i] = 1; } int i; for (i = 0; i < m; i++) { if (ed[i].first) break; if (find_set(ed[i].second.first) != find_set(ed[i].second.second)) { tes++; unite(ed[i].second.first, ed[i].second.second); ed[i] = make_pair(-1, make_pair(ed[i].second.first, ed[i].second.second)); } } for (int j = i; j < m; j++) { int q = (ed[j].second.first == s || ed[j].second.first == t) ? ed[j].second.second : ed[j].second.first; if (ed[j].first == 2) break; if (viz[q] == 3) continue; if (find_set(ed[j].second.first) != find_set(ed[j].second.second)) { if (ed[j].second.first == s || ed[j].second.second == s) { if (di == ds) continue; di++; } if (ed[j].second.first == t || ed[j].second.second == t) { if (dii == dt) continue; dii++; } tes++; unite(ed[j].second.first, ed[j].second.second); ed[j] = make_pair(-1, make_pair(ed[j].second.first, ed[j].second.second)); } } for (int j = i; j < m; j++) { if (find_set(ed[j].second.first) != find_set(ed[j].second.second)) { if (ed[j].second.first == s || ed[j].second.second == s) { if (di == ds) continue; di++; } if (ed[j].second.first == t || ed[j].second.second == t) { if (dii == dt) continue; dii++; } tes++; unite(ed[j].second.first, ed[j].second.second); ed[j] = make_pair(-1, make_pair(ed[j].second.first, ed[j].second.second)); } } if (tes != n - 1) { printf( No n ); } else { printf( Yes n ); for (int i = 0; i < m; i++) { if (ed[i].first == -1) printf( %d %d n , ed[i].second.first, ed[i].second.second); } } return 0; } |
`include "lo_read.v"
/*
pck0 - input main 24MHz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
lo_is_125khz - input freq selector (1=125kHz, 0=136kHz)
pwr_lo - output to coil drivers (ssp_clk / 8)
adc_clk - output A/D clock signal
ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
ssp_clk - output SSP clock signal 1MHz/1.09MHz (pck0 / 2*(11+lo_is_125khz) )
ck_1356meg - input unused
ck_1356megb - input unused
ssp_dout - input unused
cross_hi - input unused
cross_lo - input unused
pwr_hi - output unused, tied low
pwr_oe1 - output unused, undefined
pwr_oe2 - output unused, undefined
pwr_oe3 - output unused, undefined
pwr_oe4 - output unused, undefined
dbg - output alias for adc_clk
*/
module testbed_lo_read;
reg pck0;
reg [7:0] adc_d;
reg lo_is_125khz;
reg [15:0] divisor;
wire pwr_lo;
wire adc_clk;
wire ck_1356meg;
wire ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
lo_read #(5,10) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.lo_is_125khz(lo_is_125khz),
.divisor(divisor)
);
integer idx, i, adc_val=8;
// main clock
always #5 pck0 = !pck0;
task crank_dut;
begin
@(posedge adc_clk) ;
adc_d = adc_val;
adc_val = (adc_val *2) + 53;
end
endtask
initial begin
// init inputs
pck0 = 0;
adc_d = 0;
ssp_dout = 0;
lo_is_125khz = 1;
divisor = 255; //min 16, 95=125kHz, max 255
// simulate 4 A/D cycles at 125kHz
for (i = 0 ; i < 8 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; int tree[500005 << 2]; struct P { int x, y, z; int id; } p[500005]; bool cmp1(P a, P b) { if (a.x != b.x) return a.x > b.x; else if (a.y != b.y) return a.y > b.y; else return a.z > b.z; } bool cmp2(P a, P b) { return a.y < b.y; } void push_up(int rt) { tree[rt] = max(tree[rt << 1], tree[rt << 1 | 1]); } void update(int pos, int x, int l, int r, int rt) { if (l == r) { tree[rt] = max(tree[rt], x); return; } int m = (l + r) >> 1; if (pos <= m) update(pos, x, l, m, rt << 1); else update(pos, x, m + 1, r, rt << 1 | 1); push_up(rt); } int query(int L, int R, int l, int r, int rt) { if (L <= l && R >= r) return tree[rt]; int m = (l + r) >> 1; int ans = 0; if (L <= m) ans = max(ans, query(L, R, l, m, rt << 1)); if (R > m) ans = max(ans, query(L, R, m + 1, r, rt << 1 | 1)); return ans; } int main() { int i, j, n, ans, cnt, pre; while (~scanf( %d , &n)) { ans = 0; cnt = 1; memset(tree, 0, sizeof(tree)); for (i = 0; i < n; i++) scanf( %d , &p[i].x), p[i].id = i; for (i = 0; i < n; i++) scanf( %d , &p[i].y); for (i = 0; i < n; i++) scanf( %d , &p[i].z); sort(p, p + n, cmp2); pre = p[0].y; p[0].y = 1; for (i = 1; i < n; i++) if (p[i].y == pre) { pre = p[i].y; p[i].y = cnt; } else { pre = p[i].y; p[i].y = ++cnt; } sort(p, p + n, cmp1); for (i = 0; i < n;) { for (j = i; j < n && p[i].x == p[j].x; j++) { if (query(p[j].y + 1, cnt, 1, cnt, 1) > p[j].z) ans++; } for (; i < j; i++) update(p[i].y, p[i].z, 1, cnt, 1); } printf( %d n , ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, d; int main() { cin >> n >> d; int m; cin >> m; for (int i = 1; i <= m; i++) { int x, y; cin >> x >> y; puts((d <= x + y && x + y <= 2 * n - d && -d <= x - y && x - y <= d) ? YES : NO ); } } |
#include <bits/stdc++.h> using namespace std; bool cmp(const pair<int, pair<int, int>> a, const pair<int, pair<int, int>> b) { if (a.first == b.first) { return a.second.first > b.second.first; } else { return a.first < b.first; } } int main() { ios_base::sync_with_stdio(false); int n, k; cin >> n >> k; vector<int> be(n); vector<int> en(n); for (int i = 0; i < n; i++) { cin >> be[i] >> en[i]; } int L = 0; int R = 1e9 + 1e9 + 5; while (R - L > 1) { int mid = L + (R - L) / 2; vector<pair<int, pair<int, int>>> even; for (int i = 0; i < n; i++) { long long nooow = (long long)en[i] - mid + 1; if (be[i] <= nooow) { even.push_back({be[i], {1, 0}}); even.push_back({nooow, {-1, 0}}); } } sort(even.begin(), even.end(), cmp); int bal = 0; bool good = false; for (int i = 0; i < even.size(); i++) { bal += even[i].second.first; if (bal >= k) { good = true; } } if (good) { L = mid; } else { R = mid; } } vector<pair<int, pair<int, int>>> even; for (int i = 0; i < n; i++) { long long nooow = (long long)en[i] - L + 1; if (be[i] <= nooow) { even.push_back({be[i], {1, i}}); even.push_back({nooow, {-1, i}}); } } sort(even.begin(), even.end(), cmp); vector<int> ans; ans.push_back(1); int ind = 0; for (int i = 1; i < even.size(); i++) { if (even[i].second.first == 1) { ans.push_back(ans[i - 1] + 1); } else { ans.push_back(ans[i - 1] - 1); } if (ans[i] == k) { ind = i; break; } } if (L == 0) { cout << 0 << endl; for (int i = 0; i < k; i++) { cout << i + 1 << ; } } else { cout << L << endl; set<int> answer; for (int i = 0; i <= ind; i++) { if (even[i].second.first == 1) { answer.insert(even[i].second.second); } else { answer.erase(even[i].second.second); } } for (set<int>::iterator it = answer.begin(); it != answer.end(); it++) { cout << *it + 1 << ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = 0x20202020; const int mod = 1000000007; inline void read(int &x) { char ch; bool f = 0; int a = 0; while (!((((ch = getchar()) >= 0 ) && (ch <= 9 )) || (ch == - ))) ; if (ch != - ) a *= 10, a += ch - 0 ; else f = 1; while (((ch = getchar()) >= 0 ) && (ch <= 9 )) a *= 10, a += ch - 0 ; if (f) a = -a; x = a; } const int DX[] = {1, 0, -1, 0}, DY[] = {0, 1, 0, -1}; long long powmod(long long a, long long b) { long long res = 1; a %= mod; for (; b; b >>= 1) { if (b & 1) res = res * a % mod; a = a * a % mod; } return res; } long long powmod(long long a, long long b, long long mod) { long long res = 1; a %= mod; for (; b; b >>= 1) { if (b & 1) res = res * a % mod; a = a * a % mod; } return res; } long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } const int N = 111111, M = 111111; int l, m, n, t, tot; struct zcc { int x, v; } a[N]; inline bool cmp(const zcc &a, const zcc &b) { return a.v < b.v; } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; ++i) scanf( %d , &a[i].v), a[i].x = i, tot += a[i].v; sort(a + 1, a + 1 + n, cmp); if (n == 1 && m == tot) { puts( Yes ); for (int i = 1; i <= 2 * a[1].v - 1; ++i) printf( %d , a[1].x); printf( %d n , a[1].x); } else if (n >= 2 && m >= 2 && m <= tot) { puts( Yes ); while (m > 2) { if (a[1].v > 1) a[1].v--, printf( %d %d , a[1].x, a[1].x), m--; else if (a[n].v) a[n].v--, printf( %d %d , a[n].x, a[n].x), m--; else n--; } if (a[2].v) { a[2].v--; a[1].v--; printf( %d , a[1].x); for (int i = 2; i <= n; ++i) for (int j = 1; j <= a[i].v; ++j) printf( %d %d , a[i].x, a[i].x); printf( %d , a[1].x); printf( %d , a[2].x); for (int i = 1; i <= a[1].v; ++i) printf( %d %d , a[1].x, a[1].x); printf( %d n , a[2].x); } else { printf( %d %d n , a[1].x, a[1].x); } } else if (n >= 2 && m == 1 && a[1].v == 1) { puts( Yes ); printf( %d , a[1].x); for (int i = 2; i <= n; ++i) for (int j = 1; j <= a[i].v; ++j) printf( %d %d , a[i].x, a[i].x); printf( %d n , a[1].x); } else puts( No ); return 0; } |
#include <bits/stdc++.h> using namespace std; long long int fact(long long int n) { long long int ans = 1; for (long long int i = 2; i <= n; i++) ans = (ans % 1000000007 * i % 1000000007) % 1000000007; return ans; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int t; cin >> t; while (t--) { long long int n; cin >> n; cout << (n % 1000000007 * fact(2 * n - 1) % 1000000007) % 1000000007 << endl; } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module sky130_fd_io__top_refgen (VINREF, VOUTREF, REFLEAK_BIAS,
VCCD, VCCHIB, VDDA, VDDIO, VDDIO_Q, VSSD, VSSIO, VSSIO_Q,
HLD_H_N, IBUF_SEL, OD_H, VOHREF, VREF_SEL, VREG_EN, VTRIP_SEL);
wire error_vsel;
output VINREF;
output VOUTREF;
inout REFLEAK_BIAS;
inout VCCD;
inout VCCHIB;
inout VDDA;
inout VDDIO;
inout VDDIO_Q;
inout VSSD;
inout VSSIO;
inout VSSIO_Q;
input HLD_H_N;
input IBUF_SEL;
input OD_H;
input VOHREF;
input VREF_SEL;
input VREG_EN;
input VTRIP_SEL;
reg [2:0] dm_final;
reg slow_final, vtrip_sel_final, inp_dis_final, hld_ovr_final;
reg [2:0] dm;
reg slow, inp_dis, hld_ovr;
reg [1:0] vsel;
wire pwr_good_active_mode = (VDDIO_Q===1) && (VDDIO===1) && (VSSD===0) && (VCCD===1);
wire pwr_good_hold_mode = (VDDIO_Q===1) && (VDDIO===1) && (VSSD===0);
always @(*)
begin
if (^OD_H===1'bx || !pwr_good_hold_mode || (OD_H===0 && ^HLD_H_N===1'bx))
begin
dm_final = 3'bxxx;
slow_final = 1'bx;
vtrip_sel_final = 1'bx;
inp_dis_final = 1'bx;
hld_ovr_final = 1'bx;
end
else if (OD_H===1)
begin
dm_final = 3'b000;
slow_final = 1'b0;
vtrip_sel_final = 1'b0;
inp_dis_final = 1'b0;
hld_ovr_final = 1'b0;
end
else if (HLD_H_N===1)
begin
dm_final = (^dm[2:0] === 1'bx || !pwr_good_active_mode) ? 3'bxxx : dm;
slow_final = (^slow === 1'bx || !pwr_good_active_mode) ? 1'bx : slow;
vtrip_sel_final = (^VTRIP_SEL === 1'bx || !pwr_good_active_mode) ? 1'bx : VTRIP_SEL;
inp_dis_final = (^inp_dis === 1'bx || !pwr_good_active_mode) ? 1'bx : inp_dis;
hld_ovr_final = (^hld_ovr === 1'bx || !pwr_good_active_mode) ? 1'bx : hld_ovr;
end
end
reg dis_err_msgs;
initial
begin
dis_err_msgs = 1'b1;
`ifdef SKY130_FD_IO_TOP_REFGEN_DIS_ERR_MSGS
`else
#1;
dis_err_msgs = 1'b0;
`endif
end
assign error_vsel = (vsel[1]===1 && vsel[0]===1);
always @(*)
begin
if (!dis_err_msgs)
begin
if (error_vsel==1) $display(" ===ERROR=== sky130_fd_io__top_refgen : %m : Incorrect inputs on vsel[1:0] = 11",$stime);
end
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// A simple chipscope based monitor
`timescale 1ns/100ps
module axi_fft_mon (
clk,
// adc interface
adc_valid,
adc_data,
adc_last,
adc_ready,
// window interface
win_valid,
win_data,
win_last,
win_ready,
// fft magnitude interface
fft_mag_valid,
fft_mag_data,
fft_mag_last,
// monitor outputs for chipscope
fft_mon_sync,
fft_mon_data);
// parameter to control the memory size
parameter PCORE_FFT_MON_ADDR_WIDTH = 0;
localparam AW = PCORE_FFT_MON_ADDR_WIDTH - 1;
input clk;
// adc interface
input adc_valid;
input [15:0] adc_data;
input adc_last;
input adc_ready;
// window interface
input win_valid;
input [15:0] win_data;
input win_last;
input win_ready;
// fft magnitude interface
input fft_mag_valid;
input [31:0] fft_mag_data;
input fft_mag_last;
// monitor outputs for chipscope
output fft_mon_sync;
output [63:0] fft_mon_data;
// internal registers
reg adc_clrn = 'd0;
reg adc_wr = 'd0;
reg [AW:0] adc_waddr = 'd0;
reg [15:0] adc_wdata = 'd0;
reg win_clrn = 'd0;
reg win_wr = 'd0;
reg [AW:0] win_waddr = 'd0;
reg [15:0] win_wdata = 'd0;
reg fft_mag_clrn = 'd0;
reg fft_mag_wr = 'd0;
reg [AW:0] fft_mag_waddr = 'd0;
reg [31:0] fft_mag_wdata = 'd0;
reg [AW:0] fft_mon_raddr = 'd0;
reg fft_mon_sync = 'd0;
reg [63:0] fft_mon_data = 'd0;
// internal signals
wire [63:0] fft_mon_rdata_s;
// samples
always @(posedge clk) begin
if (adc_last == 1'b1) begin
adc_clrn <= 1'b0;
end else if ((adc_valid == 1'b1) && (adc_ready == 1'b1)) begin
adc_clrn <= 1'b1;
end
adc_wr <= adc_valid & adc_ready;
if (adc_wr == 1'b1) begin
adc_waddr <= adc_waddr + 1'b1;
end else if (adc_clrn == 1'b0) begin
adc_waddr <= 'd0;
end
adc_wdata <= adc_data;
end
// windowing controls. again, clear is used to reset the write address
always @(posedge clk) begin
if (win_last == 1'b1) begin
win_clrn <= 1'b0;
end else if ((win_valid == 1'b1) && (win_ready == 1'b1)) begin
win_clrn <= 1'b1;
end
win_wr <= win_valid & win_ready;
if (win_wr == 1'b1) begin
win_waddr <= win_waddr + 1'b1;
end else if (win_clrn == 1'b0) begin
win_waddr <= 'd0;
end
win_wdata <= win_data;
end
// FFT data. once again, clear is used to reset the write address
always @(posedge clk) begin
if (fft_mag_last == 1'b1) begin
fft_mag_clrn <= 1'b0;
end else if (fft_mag_valid == 1'b1) begin
fft_mag_clrn <= 1'b1;
end
fft_mag_wr <= fft_mag_valid;
if (fft_mag_wr == 1'b1) begin
fft_mag_waddr <= fft_mag_waddr + 1'b1;
end else if (fft_mag_clrn == 1'b0) begin
fft_mag_waddr <= 'd0;
end
fft_mag_wdata <= fft_mag_data;
end
// monitor read interface, the resets of write addresses above guarantees that
// sync is always at address 0 (0x1 here to make it trigger out of reset)
always @(posedge clk) begin
fft_mon_raddr <= fft_mon_raddr + 1'b1;
fft_mon_sync <= (fft_mon_raddr == 'd1) ? 1'b1 : 1'b0;
fft_mon_data <= fft_mon_rdata_s;
end
// samples
mem #(.ADDR_WIDTH(PCORE_FFT_MON_ADDR_WIDTH), .DATA_WIDTH(16)) i_mem_adc (
.clka (clk),
.wea (adc_wr),
.addra (adc_waddr),
.dina (adc_wdata),
.clkb (clk),
.addrb (fft_mon_raddr),
.doutb (fft_mon_rdata_s[15:0]));
// window
mem #(.ADDR_WIDTH(PCORE_FFT_MON_ADDR_WIDTH), .DATA_WIDTH(16)) i_mem_win (
.clka (clk),
.wea (win_wr),
.addra (win_waddr),
.dina (win_wdata),
.clkb (clk),
.addrb (fft_mon_raddr),
.doutb (fft_mon_rdata_s[31:16]));
// fft mag.
mem #(.ADDR_WIDTH(PCORE_FFT_MON_ADDR_WIDTH), .DATA_WIDTH(32)) i_mem_fft_mag (
.clka (clk),
.wea (fft_mag_wr),
.addra (fft_mag_waddr),
.dina (fft_mag_wdata),
.clkb (clk),
.addrb (fft_mon_raddr),
.doutb (fft_mon_rdata_s[63:32]));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2015 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file LUTROM.v when simulating
// the core, LUTROM. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module LUTROM(
clka,
addra,
douta
);
input clka;
input [12 : 0] addra;
output [17 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(13),
.C_ADDRB_WIDTH(13),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("virtex5"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(1),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("LUTROM.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(8192),
.C_READ_DEPTH_B(8192),
.C_READ_WIDTH_A(18),
.C_READ_WIDTH_B(18),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(8192),
.C_WRITE_DEPTH_B(8192),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(18),
.C_WRITE_WIDTH_B(18),
.C_XDEVICEFAMILY("virtex5")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = (int)1e9 + 7; const int N = 100005; const double PI = 4 * atan(1); const double eps = 1e-7; const long long oo = 1e10; const int K = 26; vector<int> sort_cyclic_shifts(string const& s) { int n = s.size(); const int alphabet = 256; vector<int> p(n), c(n), cnt((alphabet > n ? alphabet : n), 0); for (int i = 0; i < n; i++) cnt[s[i]]++; for (int i = 1; i < alphabet; i++) cnt[i] += cnt[i - 1]; for (int i = 0; i < n; i++) p[--cnt[s[i]]] = i; c[p[0]] = 0; int classes = 1; for (int i = 1; i < n; i++) { if (s[p[i]] != s[p[i - 1]]) classes++; c[p[i]] = classes - 1; } vector<int> pn(n), cn(n); for (int h = 0; (1 << h) < n; ++h) { for (int i = 0; i < n; i++) { pn[i] = p[i] - (1 << h); if (pn[i] < 0) pn[i] += n; } fill(cnt.begin(), cnt.begin() + classes, 0); for (int i = 0; i < n; i++) cnt[c[pn[i]]]++; for (int i = 1; i < classes; i++) cnt[i] += cnt[i - 1]; for (int i = n - 1; i >= 0; i--) p[--cnt[c[pn[i]]]] = pn[i]; cn[p[0]] = 0; classes = 1; for (int i = 1; i < n; i++) { pair<int, int> cur = {c[p[i]], c[(p[i] + (1 << h)) % n]}; pair<int, int> prev = {c[p[i - 1]], c[(p[i - 1] + (1 << h)) % n]}; if (cur != prev) ++classes; cn[p[i]] = classes - 1; } c.swap(cn); } return p; } vector<int> suffix_array_construction(string s) { s += $ ; vector<int> sorted_shifts = sort_cyclic_shifts(s); sorted_shifts.erase(sorted_shifts.begin()); return sorted_shifts; } vector<int> lcp_construction(string const& s, vector<int> const& p) { int n = s.size(); vector<int> rank(n, 0); for (int i = 0; i < n; i++) rank[p[i]] = i; int k = 0; vector<int> lcp(n - 1, 0); for (int i = 0; i < n; i++) { if (rank[i] == n - 1) { k = 0; continue; } int j = p[rank[i] + 1]; while (i + k < n && j + k < n && s[i + k] == s[j + k]) k++; lcp[rank[i]] = k; if (k) k--; } return lcp; } string s; long long k; int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> s; long long n = s.size(); cin >> k; if (k > n * (n + 1) / 2) { cout << No such line. ; return 0; } vector<int> p = suffix_array_construction(s); vector<int> lcp = lcp_construction(s, p); int st = 0; for (int i = 0; i < n; i++) { if (i == 0) { st = 0; } else { st = lcp[i - 1]; } while (st < n - p[i] && k) { int j = i; k--; while (j < n - 1 && lcp[j] > st && k) { j++; k--; if (k == 0) break; } if (k == 0) break; st++; } if (k == 0) { for (int o = p[i]; o <= p[i] + st; o++) { cout << s[o]; } return 0; } } return 0; } |
//
// Take a 32 bit number in and distribute it's bits over a 1024 bit output bus
// in some randomish pattern.
//
`include "timescale.vh"
module shuff
(
input wire [62 : 0] x,
output wire [32*16 - 1 : 0] out
);
assign out = {
{!x[00], x[62],!x[02], x[28],!x[09], x[55], x[03],!x[34], x[45], x[37],!x[11], x[07],!x[41],!x[50],!x[52],!x[59],!x[27],!x[40], x[01], x[57], x[17],!x[53],!x[24],!x[22],!x[58], x[25], x[16],!x[29],!x[43], x[32],!x[14], x[30]},
{!x[47], x[49],!x[35],!x[38], x[33],!x[31], x[44], x[13], x[06], x[54],!x[05],!x[10],!x[23],!x[19],!x[51], x[20],!x[39],!x[18],!x[46],!x[42], x[36], x[08], x[04], x[60],!x[48],!x[56],!x[26], x[21],!x[12], x[61],!x[15], x[16]},
{!x[23],!x[21],!x[20],!x[47], x[10], x[48], x[51], x[07],!x[19], x[03],!x[50], x[60],!x[36], x[38],!x[33],!x[06],!x[28], x[27], x[00], x[53], x[24], x[52],!x[14],!x[29],!x[04], x[08], x[42],!x[13],!x[45],!x[56],!x[54], x[61]},
{!x[22], x[15], x[41],!x[05], x[59], x[58],!x[35],!x[26],!x[11],!x[12], x[31],!x[01], x[39],!x[43],!x[62],!x[25],!x[55],!x[32],!x[44],!x[02],!x[46],!x[37], x[09], x[17], x[49],!x[18],!x[34], x[40],!x[57], x[30],!x[56],!x[08]},
{!x[37],!x[42],!x[33], x[35], x[39], x[17],!x[10], x[09], x[23],!x[02],!x[60],!x[36], x[18],!x[00], x[32],!x[21],!x[27], x[34], x[20], x[53], x[48], x[15], x[55],!x[14], x[19],!x[62], x[04],!x[29], x[22],!x[28],!x[06], x[03]},
{!x[45], x[26], x[47],!x[43],!x[50],!x[11], x[57],!x[44], x[31],!x[12],!x[41], x[58],!x[13], x[25], x[07],!x[30], x[05],!x[61],!x[49],!x[59], x[46], x[01], x[52],!x[51],!x[32],!x[16],!x[24],!x[38],!x[54],!x[21], x[37], x[40]},
{ x[44],!x[30], x[52], x[62],!x[58], x[45], x[38],!x[55], x[00],!x[12], x[14], x[47],!x[13], x[39], x[53], x[40],!x[18], x[31],!x[03], x[41],!x[48],!x[27], x[09],!x[07],!x[17],!x[15],!x[56], x[20], x[16], x[51],!x[59],!x[11]},
{ x[04], x[06], x[22], x[26],!x[50], x[29],!x[34], x[19], x[60], x[05],!x[49], x[57],!x[33], x[10],!x[01], x[46], x[24],!x[08], x[25], x[23], x[35],!x[42], x[54], x[43],!x[36],!x[02],!x[31],!x[28], x[13],!x[15],!x[61],!x[53]},
{!x[27], x[44],!x[33], x[52],!x[34], x[29],!x[20],!x[35], x[01], x[11], x[60],!x[14],!x[45], x[10],!x[36], x[22],!x[21],!x[55], x[62],!x[46],!x[16],!x[26],!x[07],!x[30],!x[17], x[51], x[02],!x[48],!x[42], x[43],!x[08], x[19]},
{!x[38], x[49], x[05], x[28],!x[39], x[23],!x[57],!x[25],!x[18],!x[54],!x[61],!x[24],!x[09],!x[03], x[56], x[04], x[41], x[37], x[40],!x[47],!x[00],!x[06],!x[59],!x[50], x[51],!x[26],!x[22], x[32],!x[58], x[27],!x[12], x[48]},
{ x[12],!x[17], x[04],!x[54],!x[18], x[02],!x[35], x[44],!x[40], x[50], x[21], x[37], x[15], x[58],!x[19],!x[42], x[41], x[00],!x[47],!x[56], x[46], x[20], x[34], x[11], x[45], x[32],!x[10],!x[60], x[23],!x[62],!x[61], x[13]},
{ x[03], x[53],!x[08], x[33], x[29],!x[01], x[07],!x[28],!x[31],!x[24],!x[57], x[25], x[43],!x[49], x[55],!x[38],!x[06],!x[09], x[05],!x[59],!x[30], x[39], x[16],!x[52], x[14], x[21],!x[20],!x[36], x[13],!x[04],!x[37],!x[34]},
{!x[14],!x[36],!x[35],!x[05], x[45],!x[06],!x[54],!x[41], x[23],!x[15],!x[26],!x[49],!x[39], x[30], x[29],!x[38], x[22],!x[01], x[55],!x[43],!x[46], x[52],!x[53], x[40],!x[16], x[27],!x[00],!x[57],!x[18], x[62], x[28],!x[58]},
{ x[07], x[10], x[32], x[50], x[03],!x[12], x[59], x[09],!x[19], x[56],!x[44], x[25], x[47],!x[08], x[31],!x[51], x[17], x[42],!x[61],!x[02],!x[33], x[24], x[30], x[04],!x[43], x[48],!x[49],!x[11],!x[22],!x[29],!x[60],!x[38]},
{ x[42], x[37], x[10], x[08], x[61], x[21],!x[00], x[20], x[51], x[57],!x[33],!x[01],!x[03],!x[26],!x[32],!x[05],!x[13], x[19],!x[48],!x[31],!x[02],!x[60],!x[07],!x[36],!x[62], x[27],!x[34],!x[14], x[50],!x[16],!x[17], x[11]},
{!x[56],!x[23],!x[28], x[15], x[45], x[09],!x[24],!x[46],!x[53],!x[25],!x[52],!x[39],!x[40], x[44],!x[55], x[54], x[59],!x[21],!x[06], x[08],!x[18],!x[01],!x[11],!x[61], x[47],!x[41], x[12], x[49],!x[20],!x[29], x[35],!x[58]}
};
endmodule
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module xlnx_glbl
(
GSR,
GTS
);
//--------------------------------------------------------------------------
// Parameters
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// IO declarations
//--------------------------------------------------------------------------
output GSR;
output GTS;
//--------------------------------------------------------------------------
// Local declarations
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Internal declarations
//--------------------------------------------------------------------------
assign GSR = 0;
assign GTS = 0;
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : sys_clk_gen.v
// Version : 1.11
//--
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
module sys_clk_gen (sys_clk);
output sys_clk;
reg sys_clk;
parameter offset = 0;
parameter halfcycle = 500;
initial begin
sys_clk = 0;
#(offset);
forever #(halfcycle) sys_clk = ~sys_clk;
end
endmodule // sys_clk_gen
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); const double EPS = 1e-7; const long long BIG_PRIME7 = 1000000007; const long long BIG_PRIME9 = 1000000009; int gcd(int x, int y) { return y ? gcd(y, x % y) : x; } char ch = a ; int j, n, m, L, i; int N, C; int x, y, z, k; string f, s; int a[101], b[101]; int main() { cin >> x; for (i = 0; i < x; i++) { cin >> k; if (k & 1) z++; } if (!(z & 1)) cout << (x - z); else cout << z; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 505; char g[N][N]; int id[N][N]; int cnt = 1; int dx[] = {0, 0, 1, -1}; int dy[] = {1, -1, 0, 0}; int amt[N * N]; int sz[N * N]; int sum; int n, k; void dfs(int i, int j, int idx) { if (g[i][j] == X or id[i][j]) return; id[i][j] = idx; sz[idx]++; for (int k = 0; k < 4; k++) dfs(i + dx[k], j + dy[k], idx); } void add(int c, int l, int r, bool row, bool in, bool rem = false) { for (int i = l; i <= r; i++) { int idx; if (row) idx = id[c][i]; else idx = id[i][c]; if (idx == 0) { if (in) sum = sum + !rem - rem; } else { amt[idx] = amt[idx] + !rem - rem; if (amt[idx] == 1 and !rem) sum += sz[idx]; if (amt[idx] == 0 and rem) sum -= sz[idx]; } } } void addEnv(int i, int j, bool rem = false) { add(i - 1, j, j + k - 1, true, false, rem); add(i + k, j, j + k - 1, true, false, rem); add(j - 1, i, i + k - 1, false, false, rem); add(j + k, i, i + k - 1, false, false, rem); } int main() { cin >> n >> k; for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) cin >> g[i][j]; for (int i = 0; i <= n + 1; i++) g[i][0] = X , g[i][n + 1] = X , g[0][i] = X , g[n + 1][i] = X ; for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) if (!id[i][j] and g[i][j] != X ) dfs(i, j, cnt++); add(0, 1, k, true, false, false); add(k + 1, 1, k, true, false, false); add(0, 1, k, false, false, false); add(k + 1, 1, k, false, false, false); for (int i = 1; i <= k; i++) add(i, 1, k, true, true, false); int ans = sum; int dir = 1; for (int i = 1; i <= n - k + 1;) { int lim = n - k + 1, bg = 1; int j; if (dir == -1) swap(lim, bg); for (j = bg; j != lim;) { addEnv(i, j, true); if (dir == 1) add(j, i, i + k - 1, false, true, true), add(j + k, i, i + k - 1, false, true, false); else add(j + k - 1, i, i + k - 1, false, true, true), add(j - 1, i, i + k - 1, false, true, false); j += dir; addEnv(i, j, false); ans = max(ans, sum); } if (i == n - k + 1) break; addEnv(i, j, true); add(i, j, j + k - 1, true, true, true), add(i + k, j, j + k - 1, true, true, false); i++; dir = -dir; addEnv(i, j, false); ans = max(ans, sum); } cout << ans << endl; } |
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_axis_srl_register_64;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [63:0] input_axis_tdata = 8'd0;
reg [7:0] input_axis_tkeep = 8'd0;
reg input_axis_tvalid = 1'b0;
reg input_axis_tlast = 1'b0;
reg input_axis_tuser = 1'b0;
reg output_axis_tready = 1'b0;
// Outputs
wire input_axis_tready;
wire [63:0] output_axis_tdata;
wire [7:0] output_axis_tkeep;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
// dump file
$dumpfile("test_axis_srl_register_64.lxt");
$dumpvars(0, test_axis_srl_register_64);
end
axis_srl_register_64 #(
.DATA_WIDTH(64)
)
UUT (
.clk(clk),
.rst(rst),
// axi input
.input_axis_tdata(input_axis_tdata),
.input_axis_tkeep(input_axis_tkeep),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
// axi output
.output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> T gcd(T a, T b) { return b == 0 ? a : gcd(b, a % b); } const int MAXN = 1e5 + 1e4; int n, pos_ = 0; vector<int> g[MAXN]; vector<int> a[MAXN]; vector<int> ans; vector<vector<int>> t(4 * MAXN); vector<int> parent(MAXN), depth(MAXN), heavy(MAXN, -1), pos(MAXN), head(MAXN); int dfs(int v) { int sz = 1; int h_sz = 0; for (int u : g[v]) { if (parent[v] == u) { continue; } parent[u] = v; depth[u] = depth[v] + 1; int cur_sz = dfs(u); sz += cur_sz; if (h_sz < cur_sz) { h_sz = cur_sz; heavy[v] = u; } } return sz; } void hld(int v, int root) { head[v] = root; pos[v] = pos_++; ; if (heavy[v] != -1) { hld(heavy[v], root); } for (int u : g[v]) { if (u == heavy[v] || u == parent[v]) { continue; } hld(u, u); } } void build(int v = 1, int l = 0, int r = n) { if (r - l == 1) { t[v] = a[l]; while (((int32_t)(t[v]).size()) > 10) { t[v].pop_back(); }; return; } int m = (l + r) / 2; build(v * 2, l, m); build(v * 2 + 1, m, r); t[v].resize(20, INT_MAX); merge((t[v * 2]).begin(), (t[v * 2]).end(), (t[v * 2 + 1]).begin(), (t[v * 2 + 1]).end(), t[v].begin()); while (((int32_t)(t[v]).size()) > 10 || t[v][((int32_t)(t[v]).size()) - 1] == INT_MAX) { t[v].pop_back(); } } void get_ans(int ql, int qr, int v = 1, int l = 0, int r = n) { if (ql <= l && r <= qr) { vector<int> ans_new(20, INT_MAX); merge((ans).begin(), (ans).end(), (t[v]).begin(), (t[v]).end(), ans_new.begin()); for (int i = 0; i < 20; i++) { ; } while (((int32_t)(ans_new).size()) > 10 || ans_new[((int32_t)(ans_new).size()) - 1] == INT_MAX) { ans_new.pop_back(); } ans = ans_new; return; } if (qr <= l || r <= ql) { return; } int m = (l + r) / 2; get_ans(ql, qr, v * 2, l, m); get_ans(ql, qr, v * 2 + 1, m, r); } void query(int a, int b) { while (head[a] != head[b]) { if (depth[head[a]] > depth[head[b]]) { swap(a, b); }; get_ans(pos[head[b]], pos[b] + 1); b = parent[head[b]]; } if (depth[a] > depth[b]) { swap(a, b); }; get_ans(pos[a], pos[b] + 1); } int32_t main() { { cin.tie(0); cout.tie(0); ios_base::sync_with_stdio(0); }; int m, q; cin >> n >> m >> q; for (int i = 1; i < n; i++) { int v, u; cin >> v >> u; v--; u--; g[u].push_back(v); g[v].push_back(u); } dfs(0); hld(0, 0); for (int i = 0; i < m; i++) { int tmp; cin >> tmp; ; a[pos[tmp - 1]].push_back(i + 1); } build(); while (q--) { int v, u, a; cin >> v >> u >> a; v--; u--; ans.clear(); query(v, u); ; int k = min(a, ((int32_t)(ans).size())); cout << k; for (int i = 0; i < k; i++) { cout << << ans[i]; } cout << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> inline bool uin(T& a, T b) { return a > b ? (a = b, true) : false; } template <class T> inline bool uax(T& a, T b) { return a < b ? (a = b, true) : false; } int main() { ios::sync_with_stdio(false); cin.tie(0); string s; cin >> s; for (int i = (int)s.length() - 1, cnt = 0; i >= 0; --i) { if (s[i] == 0 ) ++cnt; else if (cnt) --cnt; else s[i] = 0 ; } cout << s << n ; } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:66777216 ) using namespace std; const int N = 1001002; int a, b, c, d, i, j, n, m, k, tot, now, last; int nx[N][26], sib[N], pr[N], fir[N]; int cnt[N], en[N]; char str[502]; int num[2][N]; int dp[2][2002][2002]; vector<int> lev[503]; int dfs(int v, int h = 0) { lev[h].push_back(v); for (int _n((26) - 1), i(0); i <= _n; i++) { if (nx[v][i] != -1) cnt[v] += dfs(nx[v][i], h + 1); } return cnt[v]; } inline int g(int v, int c) { if (c < 0) return -1000000000; if (v == -1 && !c) return 0; if (v == -1) return -1000000000; if (!c) return 0; return dp[last][num[last][v]][c]; } inline int f(int v, int c) { if (c < 0) return -1000000000; if (v == -1 && !c) return 0; if (v == -1) return -1000000000; if (!c) return 0; return dp[now][num[now][v]][c]; } int rec(int v, int c) { if (c < 0) return -1000000000; if (v == -1 && !c) return 0; if (v == -1) return -1000000000; if (!c) return 0; int ans = 0, fr = cnt[v] - en[v]; for (int i = (min(cnt[v], c)), _b = (0); i >= _b; i--) { int lf = c - i; if (lf && sib[v] == -1) break; int v1 = g(fir[v], min(fr, i)); if (v1 < 0) continue; int v2 = f(sib[v], lf); if (v2 < 0) continue; ans = max(ans, i * (i - 1) / 2 + v1 + v2); } return dp[now][num[now][v]][c] = ans; } int main() { memset(nx, -1, sizeof(nx)); pr[0] = -1; k = 1; scanf( %d%d , &n, &tot); for (int _n((n)-1), i(0); i <= _n; i++) { scanf( %s , str); m = (int)strlen(str); a = 0; for (int _n((m)-1), i(0); i <= _n; i++) { if (nx[a][str[i] - a ] == -1) { nx[a][str[i] - a ] = k++; pr[k - 1] = a; } a = nx[a][str[i] - a ]; } ++cnt[a]; ++en[a]; } for (int _n((k)-1), i(0); i <= _n; i++) { fir[i] = -1; for (int j = (25), _b = (0); j >= _b; j--) { if (nx[i][j] == -1) continue; sib[nx[i][j]] = fir[i]; fir[i] = nx[i][j]; } } dfs(0); memset((dp), 0, sizeof(dp)); now = 0, last = 1; for (int h = (500), _b = (1); h >= _b; h--) { if (lev[h].empty()) continue; now ^= 1; last ^= 1; for (int _n(((int)((lev[h]).size())) - 1), i(0); i <= _n; i++) num[now][lev[h][i]] = i; for (int i = ((int)((lev[h]).size()) - 1), _b = (0); i >= _b; i--) { int v = lev[h][i], p = pr[v]; for (int _n((k + 1) - 1), j(0); j <= _n; j++) { if (j > cnt[p]) break; rec(v, j); } } } int ans = dp[now][0][tot]; printf( %d n , ans); } |
#include <bits/stdc++.h> #pragma GCC optimize( O3 , unroll-loops ) #pragma GCC target( avx2 ) using namespace std; const int maxn = 1e6 + 5; int n; bool used[maxn]; vector<int> v[maxn]; vector<int> g[maxn]; int ans[maxn]; int pr[maxn]; int t[4 * maxn]; void init() { used[0] = true; used[1] = true; for (int i = 2; i < maxn; ++i) { if (used[i]) continue; v[i] = {i}; for (int j = 2 * i; j < maxn; j += i) { used[j] = true; v[j].push_back(i); } } } vector<int> slv(vector<pair<int, int> > z) { vector<int> f; for (auto h : z) f.push_back(h.second); pr[0] = 0; for (int i = 0; i < f.size(); ++i) pr[i + 1] = pr[i] + f[i]; stack<pair<int, int> > o; for (int i = 0; i <= f.size(); ++i) ans[i] = 1e9; for (int i = 0; i <= f.size(); ++i) { while (true) { if (o.empty()) { o.push({pr[i], i}); break; } pair<int, int> z = o.top(); if (z.first <= pr[i]) { o.push({pr[i], i}); break; } else { ans[z.second] = i; o.pop(); } } } vector<int> res; for (int i = 0; i < f.size(); ++i) { if (ans[i] == 1e9) res.push_back(n); else res.push_back(z[ans[i] - 1].first); } return res; } void to(int node, int tl, int tr, int l, int r, int val) { if (tl >= l && tr <= r) { t[node] = min(t[node], val); return; } if (tl >= r || tr <= l) { return; } int tm = (tl + tr) / 2; to(2 * node + 1, tl, tm, l, r, val); to(2 * node + 2, tm, tr, l, r, val); } int get(int node, int tl, int tr, int pos) { if (tl > pos || tr <= pos) return 1e9; int ans = t[node]; if ((tr - tl) == 1) return ans; int tm = (tl + tr) / 2; ans = min(ans, get(2 * node + 1, tl, tm, pos)); ans = min(ans, get(2 * node + 2, tm, tr, pos)); return ans; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); for (int i = 0; i < 4 * maxn; ++i) t[i] = 1e9; init(); cin >> n; int a[n]; for (int i = 0; i < n; ++i) cin >> a[i]; string s; cin >> s; for (int i = 0; i < n; ++i) for (auto h : v[a[i]]) g[h].push_back(i); vector<pair<pair<int, int>, int> > o; for (int i = 2; i < maxn; ++i) { if (g[i].empty()) continue; vector<pair<int, int> > z; int o1 = 0; for (auto j : g[i]) { o1 = 0; int x = a[j]; assert(x % i == 0); while (x % i == 0) { ++o1; x /= i; } if (s[j] == * ) z.push_back({j, o1}); else z.push_back({j, -o1}); } vector<int> t = slv(z); for (int i = 0; i < z.size(); ++i) { if (i == 0) o.push_back({{0, z[0].first + 1}, t[i]}); else o.push_back({{z[i - 1].first + 1, z[i].first + 1}, t[i]}); } } to(0, 0, n, 0, n, n); for (auto l : o) to(0, 0, n, l.first.first, l.first.second, l.second); long long res = 0; for (int i = 0; i < n; ++i) { int val = get(0, 0, n, i); res += max(0, val - i); } cout << res << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int m, n; int main() { cin >> n >> m; if (n == 1) { cout << 1; return 0; } if (m <= n - m) { cout << m + 1; return 0; } cout << m - 1; } |
#include <bits/stdc++.h> using namespace std; const int L = 500; const int N = 220000; const int M1 = 1e9 + 7; const int M2 = 1e9 + 9; int chd[N][26], go[N][26]; int len[N], q[N], p[N]; int s[N], dp[N], f[17][N], t[N]; char str[N], _str[N]; int st[N], en[N], wh[N], fr[N], to[N], cur[N], state[N], id[N], ans[N], cnt[N], sum[N], chk[N], a[N], b[N]; int h1[N], h2[N], hh1[N], hh2[N], hs1[N], hs2[N], p1[N], p2[N]; vector<int> adj[N], con[N]; int sn, e[N]; char w[N], ch[N]; void dfs(int u, int p) { s[u] = sn; f[0][u] = p; dp[u] = dp[p] + 1; for (int i = 1; i < 17; i++) f[i][u] = f[i - 1][f[i - 1][u]]; for (int tt : adj[u]) { int v = e[tt] ^ u; if (v == p) continue; ch[v] = w[tt]; a[sn] = u, b[sn] = v; t[sn++] = tt; dfs(v, u); a[sn] = v, b[sn] = u; t[sn++] = tt; } } int T; void dfs(int u) { st[u] = ++T; for (int v : con[u]) { dfs(v); } en[u] = T; } void modify(int x, int y) { cnt[x] += y; sum[x / L] += y; } int query(int l, int r) { int ll = l / L, rr = r / L; int ret = 0; if (ll == rr) { for (int i = l; i <= r; i++) ret += cnt[i]; return ret; } for (int i = l; i < min((ll + 1) * L, r + 1); i++) ret += cnt[i]; for (int i = max(l, rr * L); i <= r; i++) ret += cnt[i]; for (int i = ll + 1; i < rr; i++) ret += sum[i]; return ret; } int lca(int u, int v) { if (dp[u] < dp[v]) swap(u, v); for (int d = dp[u] - dp[v], i = 0; i < 17; i++) if (d >> i & 1) u = f[i][u]; if (u == v) return u; for (int i = 16; i >= 0; i--) { if (f[i][u] == f[i][v]) continue; u = f[i][u], v = f[i][v]; } return f[0][u]; } int n, m, Q; const int B1 = 31; const int B2 = 47; pair<int, int> get(int *h1, int *h2, int l, int s, int e) { return make_pair((h1[e + 1] + 1LL * (M1 - h1[s]) * p1[e - s + 1]) % M1, (h2[e + 1] + 1LL * (M2 - h2[s]) * p2[e - s + 1]) % M2); } int make_path(int u, int v) { int p = lca(u, v); int ret = 0; while (u != p) { _str[ret++] = ch[u]; u = f[0][u]; } int nret = ret; while (v != p) { _str[ret++] = ch[v]; v = f[0][v]; } reverse(_str + nret, _str + ret); for (int i = 0; i < ret; i++) { hh1[i + 1] = (1LL * hh1[i] * B1 + _str[i] - a ) % M1; hh2[i + 1] = (1LL * hh2[i] * B2 + _str[i] - a ) % M2; } return ret; } int dist(int u, int v) { return dp[u] + dp[v] - 2 * dp[lca(u, v)]; } int main() { scanf( %d%d%d , &n, &m, &Q); for (int i = 1; i < n; i++) { int u, v; char c[3]; scanf( %d%d%s , &u, &v, c); e[i] = u ^ v; w[i] = c[0]; adj[u].push_back(i); adj[v].push_back(i); } dfs(1, 0); int nodes = 1; for (int i = 0; i < N; i++) p1[i] = (i == 0 ? 1 : 1LL * p1[i - 1] * B1 % M1), p2[i] = (i == 0 ? 1 : 1LL * p2[i - 1] * B2 % M2); for (int i = 1; i <= m; i++) { scanf( %s , str); int l = strlen(str); for (int k = 0; k < 2; k++) { int u = 1, ret1 = 0, ret2 = 0; for (int j = 0; str[j]; j++) { int c = str[j] - a ; ret1 = (1LL * ret1 * B1 + c) % M1, ret2 = (1LL * ret2 * B2 + c) % M2; int &v = chd[u][c]; if (!v) v = ++nodes; u = v; } hs1[k * m + i] = ret1; hs2[k * m + i] = ret2; state[k * m + i] = u; reverse(str, str + l); } len[i] = len[i + m] = l; } int qn = 0; for (int i = 0, u; i < 26; i++) if (u = chd[1][i]) q[qn++] = u, p[u] = 1; for (int i = 0; i < qn; i++) { int u = q[i]; for (int j = 0, v; j < 26; j++) if (v = chd[u][j]) { int w = p[u]; while (w > 1 && !chd[w][j]) w = p[w]; w = max(1, chd[w][j]); p[v] = w; q[qn++] = v; } } for (int i = 0; i < 26; i++) go[1][i] = max(1, chd[1][i]); for (int i = 0; i < qn; i++) { int u = q[i]; for (int j = 0; j < 26; j++) { if (chd[u][j]) go[u][j] = chd[u][j]; else go[u][j] = go[p[u]][j]; } } for (int i = 2; i <= nodes; i++) con[p[i]].push_back(i); dfs(1); for (int i = 1; i <= Q; i++) { scanf( %d%d%d , &fr[i], &to[i], &wh[i]); if (s[fr[i]] > s[to[i]]) { swap(fr[i], to[i]); wh[i] += m; } fr[i] = s[fr[i]]; to[i] = s[to[i]] - 1; id[i] = i; } sort(id + 1, id + Q + 1, [](int i, int j) { if (fr[i] / L != fr[j] / L) return fr[i] / L < fr[j] / L; return to[i] < to[j]; }); for (int i = 1, j; i <= Q; i = j) { int u = id[i]; int r = fr[u] / L * L - 1; memset(chk, 0, sizeof chk); memset(cnt, 0, sizeof cnt); memset(sum, 0, sizeof sum); int rn = 0; cur[0] = 1; for (j = i; j <= Q && fr[id[i]] / L == fr[id[j]] / L; j++) { int v = id[j]; while (r < to[v]) { ++r; int eid = t[r]; int c = w[eid] - a ; if (chk[eid]) { modify(st[cur[rn]], -1); rn--; } else { cur[rn + 1] = go[cur[rn]][c]; h1[rn + 1] = (1LL * h1[rn] * B1 + c) % M1; h2[rn + 1] = (1LL * h2[rn] * B2 + c) % M2; modify(st[cur[++rn]], 1); } chk[eid] ^= 1; } int who = wh[v]; ans[v] = query(st[state[who]], en[state[who]]); int xx = a[fr[u] / L * L]; int yy = a[fr[v]]; int zz = b[r]; int pxy = lca(xx, yy); int pyz = lca(yy, zz); int pzx = lca(zz, xx); int pp = pxy ^ pyz ^ pzx; int xy = dp[xx] + dp[yy] - 2 * dp[pxy]; int yz = dp[zz] + dp[yy] - 2 * dp[pyz]; int zx = dp[xx] + dp[zz] - 2 * dp[pzx]; int xlen = (xy + zx - yz) / 2; assert(xlen == dist(xx, pp)); assert(rn == zx); int _ans = ans[v]; for (int k = 0; k < xlen; k++) { if (k + len[who] - 1 >= rn) break; auto ret = get(h1, h2, rn, k, k + len[who] - 1); if (ret.first == hs1[who] && ret.second == hs2[who]) ans[v]--; } int __ans = ans[v]; int ylen = make_path(yy, pp); for (int k = 0; k < ylen; k++) { if (k + len[who] - 1 < ylen) { auto ret = get(hh1, hh2, ylen, k, k + len[who] - 1); if (ret.first == hs1[who] && ret.second == hs2[who]) ans[v]++; continue; } if (len[who] - ylen + k > rn - xlen) break; auto first = get(hh1, hh2, ylen, k, ylen - 1); auto second = get(h1, h2, rn, xlen, xlen + len[who] - (ylen - k) - 1); int ret1 = (1LL * first.first * p1[len[who] - (ylen - k)] + second.first) % M1; int ret2 = (1LL * first.second * p2[len[who] - (ylen - k)] + second.second) % M2; if (ret1 == hs1[who] && ret2 == hs2[who]) ans[v]++; } } } for (int i = 1; i <= Q; i++) printf( %d n , ans[i]); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S50_PP_SYMBOL_V
`define SKY130_FD_SC_HD__CLKDLYBUF4S50_PP_SYMBOL_V
/**
* clkdlybuf4s50: Clock Delay Buffer 4-stage 0.59um length inner stage
* gates.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__clkdlybuf4s50 (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S50_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 5; const long long INF = 1e18; const long long LIMIT = 1500000LL * 1500000LL; vector<int> V; int ans[MAXN]; struct node { long long x, y, pos; long long dis() { return x * x + y * y; } }; node p[MAXN]; bool cmp(node A, node B) { return A.dis() > B.dis(); } node operator+(const node &A, const node &B) { node ans = A; ans.x += B.x; ans.y += B.y; return ans; } node operator-(const node &A, const node &B) { node ans = A; ans.x -= B.x; ans.y -= B.y; return ans; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; for (int i = 0; i < n; i++) cin >> p[i].x >> p[i].y, p[i].pos = i; node cur{0, 0, 0}; for (int i = n - 1; i >= 0; i--) { if (cmp(cur - p[i], cur + p[i])) cur = cur + p[i], ans[i] = 1; else cur = cur - p[i], ans[i] = -1; } for (int i = 0; i < n; i++) cout << ans[i] << ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 5; const long long p = 1e9 + 7; int par[MAXN][2], size[MAXN][2], dist[MAXN][2], val[MAXN][2]; int groups, n, k; pair<int, int> find(int e, int x) { if (par[x][e] == x) { return pair<int, int>(x, 0); } pair<int, int> t = find(e, par[x][e]); t.second += dist[x][e]; t.second %= 2; dist[x][e] = t.second; par[x][e] = t.first; return t; } bool assign(int e, int x, int v) { find(e, x); if (val[par[x][e]][e] == -1) { val[par[x][e]][e] = (dist[x][e] + v) % 2; --groups; return true; } if (val[par[x][e]][e] != (dist[x][e] + v) % 2) return false; return true; } bool addedge(int e, int x, int y, int v) { find(e, x); find(e, y); if (par[x][e] == par[y][e]) return ((dist[x][e] + dist[y][e] + v) % 2 == 0); v = (dist[x][e] + dist[y][e] + v) % 2; x = par[x][e]; y = par[y][e]; if (size[x][e] > size[y][e]) swap(x, y); par[x][e] = y; dist[x][e] = v; size[y][e] += size[x][e]; if (val[y][e] != -1 && val[x][e] != -1) { if ((val[x][e] + val[y][e] + v) % 2 != 0) return false; return true; } if (val[x][e] != -1) { val[y][e] = (val[x][e] + v) % 2; --groups; return true; } --groups; return true; } int main() { cin >> n >> k; groups = 2 * n - 1; for (int i = 0; i < MAXN; ++i) { par[i][0] = par[i][1] = i; size[i][0] = size[i][1] = 1; dist[i][0] = dist[i][1] = 0; val[i][0] = val[i][1] = -1; } for (int i = 0; i < k; ++i) { int x, y, v; char j; cin >> x >> y >> j; v = (j == o ); x--; y--; if (abs(x - y) <= 1) { if (!assign((x + y) % 2, min(x, y), v)) { cout << 0 << endl; return 0; } } else { if (x > y) swap(x, y); if (!addedge((x + y) % 2, (y - x - (x + y) % 2) / 2 - 1, (y - x - (x + y) % 2) / 2 + x, v)) { cout << 0 << endl; return 0; } } } for (int i = 0; i < n / 2; ++i) { if (!addedge(0, i, n - 1 - i, 0)) { cout << 0 << endl; return 0; } } for (int i = 0; i < (n - 1) / 2; ++i) { if (!addedge(1, i, n - 2 - i, 0)) { cout << 0 << endl; return 0; } } long long prod = 1; for (int i = 0; i < groups; ++i) { prod *= 2; prod %= p; } cout << prod << endl; } |
#include <bits/stdc++.h> using namespace std; const double eps = 1e-9; const int N = (int)2e6 + 5; int n, q, a[N], l[N], r[N]; int main() { for (scanf( %d , &q); q--;) { scanf( %d , &n); for (int i = 1; i <= n; ++i) scanf( %d , a + i); for (int i = 1; i <= n; ++i) l[i] = n + 1, r[i] = -1; for (int i = 1; i <= n; ++i) l[a[i]] = min(l[a[i]], i), r[a[i]] = max(r[a[i]], i); int mx = 0, now = 0, pos = -1, typ = 0; for (int i = 1; i <= n; ++i) if (r[i] != -1) { ++typ; if (now == 0) { now = 1; pos = r[i]; } else { if (pos < l[i]) { pos = r[i]; ++now; } else pos = r[i], now = 1; } mx = max(mx, now); } printf( %d n , typ - mx); } return 0; } |
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ()
// div_pipelined.v
// Created: 4.3.2012
// Modified: 4.5.2012
//
// Testbench for div_pipelined.v
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module t_div_pipelined();
reg clk, start, reset_n;
reg [7:0] dividend, divisor;
wire data_valid, div_by_zero;
wire [7:0] quotient, quotient_correct;
parameter
BITS = 8;
div_pipelined
#(
.BITS(BITS)
)
div_pipelined
(
.clk(clk),
.reset_n(reset_n),
.dividend(dividend),
.divisor(divisor),
.quotient(quotient),
.div_by_zero(div_by_zero),
// .quotient_correct(quotient_correct),
.start(start),
.data_valid(data_valid)
);
initial begin
#10 reset_n = 0;
#50 reset_n = 1;
#1
clk = 0;
dividend = -1;
divisor = 127;
#1000 $finish;
end
// always
// #20 dividend = dividend + 1;
always begin
#10 divisor = divisor - 1; start = 1;
#10 start = 0;
end
always
#5 clk = ~clk;
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// The IFU to implement entire instruction fetch unit.
//
// ====================================================================
`include "e203_defines.v"
module e203_ifu(
output[`E203_PC_SIZE-1:0] inspect_pc,
output ifu_active,
input itcm_nohold,
input [`E203_PC_SIZE-1:0] pc_rtvec,
`ifdef E203_HAS_ITCM //{
input ifu2itcm_holdup,
//input ifu2itcm_replay,
// The ITCM address region indication signal
input [`E203_ADDR_SIZE-1:0] itcm_region_indic,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// Bus Interface to ITCM, internal protocol called ICB (Internal Chip Bus)
// * Bus cmd channel
output ifu2itcm_icb_cmd_valid, // Handshake valid
input ifu2itcm_icb_cmd_ready, // Handshake ready
// Note: The data on rdata or wdata channel must be naturally
// aligned, this is in line with the AXI definition
output [`E203_ITCM_ADDR_WIDTH-1:0] ifu2itcm_icb_cmd_addr, // Bus transaction start addr
// * Bus RSP channel
input ifu2itcm_icb_rsp_valid, // Response valid
output ifu2itcm_icb_rsp_ready, // Response ready
input ifu2itcm_icb_rsp_err, // Response error
// Note: the RSP rdata is inline with AXI definition
input [`E203_ITCM_DATA_WIDTH-1:0] ifu2itcm_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_MEM_ITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// Bus Interface to System Memory, internal protocol called ICB (Internal Chip Bus)
// * Bus cmd channel
output ifu2biu_icb_cmd_valid, // Handshake valid
input ifu2biu_icb_cmd_ready, // Handshake ready
// Note: The data on rdata or wdata channel must be naturally
// aligned, this is in line with the AXI definition
output [`E203_ADDR_SIZE-1:0] ifu2biu_icb_cmd_addr, // Bus transaction start addr
// * Bus RSP channel
input ifu2biu_icb_rsp_valid, // Response valid
output ifu2biu_icb_rsp_ready, // Response ready
input ifu2biu_icb_rsp_err, // Response error
// Note: the RSP rdata is inline with AXI definition
input [`E203_SYSMEM_DATA_WIDTH-1:0] ifu2biu_icb_rsp_rdata,
//input ifu2biu_replay,
`endif//}
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The IR stage to EXU interface
output [`E203_INSTR_SIZE-1:0] ifu_o_ir,// The instruction register
output [`E203_PC_SIZE-1:0] ifu_o_pc, // The PC register along with
output ifu_o_pc_vld,
output ifu_o_misalgn, // The fetch misalign
output ifu_o_buserr, // The fetch bus error
output [`E203_RFIDX_WIDTH-1:0] ifu_o_rs1idx,
output [`E203_RFIDX_WIDTH-1:0] ifu_o_rs2idx,
output ifu_o_prdt_taken, // The Bxx is predicted as taken
output ifu_o_muldiv_b2b,
output ifu_o_valid, // Handshake signals with EXU stage
input ifu_o_ready,
output pipe_flush_ack,
input pipe_flush_req,
input [`E203_PC_SIZE-1:0] pipe_flush_add_op1,
input [`E203_PC_SIZE-1:0] pipe_flush_add_op2,
`ifdef E203_TIMING_BOOST//}
input [`E203_PC_SIZE-1:0] pipe_flush_pc,
`endif//}
// The halt request come from other commit stage
// If the ifu_halt_req is asserting, then IFU will stop fetching new
// instructions and after the oustanding transactions are completed,
// asserting the ifu_halt_ack as the response.
// The IFU will resume fetching only after the ifu_halt_req is deasserted
input ifu_halt_req,
output ifu_halt_ack,
input oitf_empty,
input [`E203_XLEN-1:0] rf2ifu_x1,
input [`E203_XLEN-1:0] rf2ifu_rs1,
input dec2ifu_rden,
input dec2ifu_rs1en,
input [`E203_RFIDX_WIDTH-1:0] dec2ifu_rdidx,
input dec2ifu_mulhsu,
input dec2ifu_div ,
input dec2ifu_rem ,
input dec2ifu_divu ,
input dec2ifu_remu ,
input clk,
input rst_n
);
wire ifu_req_valid;
wire ifu_req_ready;
wire [`E203_PC_SIZE-1:0] ifu_req_pc;
wire ifu_req_seq;
wire ifu_req_seq_rv32;
wire [`E203_PC_SIZE-1:0] ifu_req_last_pc;
wire ifu_rsp_valid;
wire ifu_rsp_ready;
wire ifu_rsp_err;
//wire ifu_rsp_replay;
wire [`E203_INSTR_SIZE-1:0] ifu_rsp_instr;
e203_ifu_ifetch u_e203_ifu_ifetch(
.inspect_pc (inspect_pc),
.pc_rtvec (pc_rtvec),
.ifu_req_valid (ifu_req_valid),
.ifu_req_ready (ifu_req_ready),
.ifu_req_pc (ifu_req_pc ),
.ifu_req_seq (ifu_req_seq ),
.ifu_req_seq_rv32(ifu_req_seq_rv32),
.ifu_req_last_pc (ifu_req_last_pc ),
.ifu_rsp_valid (ifu_rsp_valid),
.ifu_rsp_ready (ifu_rsp_ready),
.ifu_rsp_err (ifu_rsp_err ),
//.ifu_rsp_replay(ifu_rsp_replay),
.ifu_rsp_instr (ifu_rsp_instr),
.ifu_o_ir (ifu_o_ir ),
.ifu_o_pc (ifu_o_pc ),
.ifu_o_pc_vld (ifu_o_pc_vld ),
.ifu_o_misalgn (ifu_o_misalgn),
.ifu_o_buserr (ifu_o_buserr ),
.ifu_o_rs1idx (ifu_o_rs1idx),
.ifu_o_rs2idx (ifu_o_rs2idx),
.ifu_o_prdt_taken(ifu_o_prdt_taken),
.ifu_o_muldiv_b2b(ifu_o_muldiv_b2b),
.ifu_o_valid (ifu_o_valid ),
.ifu_o_ready (ifu_o_ready ),
.pipe_flush_ack (pipe_flush_ack ),
.pipe_flush_req (pipe_flush_req ),
.pipe_flush_add_op1 (pipe_flush_add_op1),
`ifdef E203_TIMING_BOOST//}
.pipe_flush_pc (pipe_flush_pc),
`endif//}
.pipe_flush_add_op2 (pipe_flush_add_op2),
.ifu_halt_req (ifu_halt_req ),
.ifu_halt_ack (ifu_halt_ack ),
.oitf_empty (oitf_empty ),
.rf2ifu_x1 (rf2ifu_x1 ),
.rf2ifu_rs1 (rf2ifu_rs1 ),
.dec2ifu_rden (dec2ifu_rden ),
.dec2ifu_rs1en (dec2ifu_rs1en),
.dec2ifu_rdidx (dec2ifu_rdidx),
.dec2ifu_mulhsu(dec2ifu_mulhsu),
.dec2ifu_div (dec2ifu_div ),
.dec2ifu_rem (dec2ifu_rem ),
.dec2ifu_divu (dec2ifu_divu ),
.dec2ifu_remu (dec2ifu_remu ),
.clk (clk ),
.rst_n (rst_n )
);
e203_ifu_ift2icb u_e203_ifu_ift2icb (
.ifu_req_valid (ifu_req_valid),
.ifu_req_ready (ifu_req_ready),
.ifu_req_pc (ifu_req_pc ),
.ifu_req_seq (ifu_req_seq ),
.ifu_req_seq_rv32(ifu_req_seq_rv32),
.ifu_req_last_pc (ifu_req_last_pc ),
.ifu_rsp_valid (ifu_rsp_valid),
.ifu_rsp_ready (ifu_rsp_ready),
.ifu_rsp_err (ifu_rsp_err ),
//.ifu_rsp_replay(ifu_rsp_replay),
.ifu_rsp_instr (ifu_rsp_instr),
.itcm_nohold (itcm_nohold),
`ifdef E203_HAS_ITCM //{
.itcm_region_indic (itcm_region_indic),
.ifu2itcm_icb_cmd_valid(ifu2itcm_icb_cmd_valid),
.ifu2itcm_icb_cmd_ready(ifu2itcm_icb_cmd_ready),
.ifu2itcm_icb_cmd_addr (ifu2itcm_icb_cmd_addr ),
.ifu2itcm_icb_rsp_valid(ifu2itcm_icb_rsp_valid),
.ifu2itcm_icb_rsp_ready(ifu2itcm_icb_rsp_ready),
.ifu2itcm_icb_rsp_err (ifu2itcm_icb_rsp_err ),
.ifu2itcm_icb_rsp_rdata(ifu2itcm_icb_rsp_rdata),
`endif//}
`ifdef E203_HAS_MEM_ITF //{
.ifu2biu_icb_cmd_valid(ifu2biu_icb_cmd_valid),
.ifu2biu_icb_cmd_ready(ifu2biu_icb_cmd_ready),
.ifu2biu_icb_cmd_addr (ifu2biu_icb_cmd_addr ),
.ifu2biu_icb_rsp_valid(ifu2biu_icb_rsp_valid),
.ifu2biu_icb_rsp_ready(ifu2biu_icb_rsp_ready),
.ifu2biu_icb_rsp_err (ifu2biu_icb_rsp_err ),
.ifu2biu_icb_rsp_rdata(ifu2biu_icb_rsp_rdata),
//.ifu2biu_replay (ifu2biu_replay),
`endif//}
`ifdef E203_HAS_ITCM //{
.ifu2itcm_holdup (ifu2itcm_holdup),
//.ifu2itcm_replay (ifu2itcm_replay),
`endif//}
.clk (clk ),
.rst_n (rst_n )
);
assign ifu_active = 1'b1;// Seems the IFU never rest at block level
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFXBP_PP_SYMBOL_V
`define SKY130_FD_SC_MS__SDFXBP_PP_SYMBOL_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sdfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFXBP_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 400 + 5; const int INF = 1e9; int R, n, m; pair<int, int> H[N], T[N]; int vis[N][N]; vector<pair<int, int> > adj[N][N]; queue<pair<int, int> > Q; int dis[N][N]; int bfs(int h, int t) { memset(dis, 0x3c, sizeof dis); dis[h][t] = 0; Q.push(make_pair(h, t)); while (Q.size()) { int x = Q.front().first, y = Q.front().second; Q.pop(); if (x + y == 0) return dis[x][y]; for (auto it : adj[x][y]) { if (dis[x][y] + 1 < dis[it.first][it.second]) { dis[it.first][it.second] = dis[x][y] + 1; Q.push(it); } } } return INF; } bool isCycle(int h, int t) { vis[h][t] = 1; for (auto it : adj[h][t]) { int x = it.first, y = it.second; if (vis[x][y] == 1) return 1; if (vis[x][y] == 2) continue; if (isCycle(x, y)) return 1; } vis[h][t] = 2; return 0; } int dp[N][N]; int fun(int x, int y) { int &memo = dp[x][y]; if (memo != -1) return memo; if (x + y > R) return memo = 0; int ans = 0; for (auto it : adj[x][y]) { ans = max(ans, fun(it.first, it.second)); } return memo = ans + 1; } int main() { ios::sync_with_stdio(0); cin.tie(0); int h, t; cin >> h >> t >> R; cin >> n; for (int i = 1; i <= n; i++) { cin >> H[i].first >> H[i].second; } cin >> m; for (int i = 1; i <= m; i++) { cin >> T[i].first >> T[i].second; } for (int i = 0; i < N; i++) { for (int j = 0; j < N; j++) { if (i + j == 0) ; else if (i + j > R) ; else { for (int k = 1; k <= n and k <= i; k++) { adj[i][j].push_back(make_pair(i - k + H[k].first, j + H[k].second)); } for (int k = 1; k <= m and k <= j; k++) { adj[i][j].push_back(make_pair(i + T[k].first, j - k + T[k].second)); } } } } int ans = bfs(h, t); if (ans != INF) { cout << Ivan n ; cout << ans << n ; exit(0); } if (isCycle(h, t)) { cout << Draw n ; exit(0); } memset(dp, -1, sizeof dp); cout << Zmey n ; cout << fun(h, t) << n ; return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:14:30 03/29/2014
// Design Name: regfile
// Module Name: D:/XilinxProject/CPU/regfile_test.v
// Project Name: CPU
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: regfile
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module regfile_test;
// Inputs
reg [4:0] rna;
reg [4:0] rnb;
reg [31:0] d;
reg [4:0] wn;
reg we;
reg clk;
reg clrn;
// Outputs
wire [31:0] qa;
wire [31:0] qb;
// Instantiate the Unit Under Test (UUT)
regfile uut (
.rna(rna),
.rnb(rnb),
.d(d),
.wn(wn),
.we(we),
.clk(clk),
.clrn(clrn),
.qa(qa),
.qb(qb)
);
initial begin
// Initialize Inputs
rna = 1;
rnb = 2;
d = 1;
wn = 1;
we = 1;
clk = 0;
clrn = 1;
// Wait 100 ns for global reset to finish
#100;
rna = 1;
rnb = 2;
d = 1;
wn = 1;
we = 1;
clk = ~clk;
#100;
rna = 1;
rnb = 2;
d = 1;
wn = 1;
we = 1;
clk = ~clk;
#100;
rna = 1;
rnb = 2;
d = 1;
wn = 1;
we = 0;
clk = ~clk;
// Add stimulus here
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DECAP_12_V
`define SKY130_FD_SC_HDLL__DECAP_12_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog wrapper for decap with size of 12 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__decap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__decap_12 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__decap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__decap_12 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__decap base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DECAP_12_V
|
// ********************************************************************/
// Actel Corporation Proprietary and Confidential
// Copyright 2010 Actel Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// Description: CoreAHBLite address decode logic
// for master 0 and master 1
//
// Revision Information:
// Date Description
// ---- -----------------------------------------
// 10Feb10 Production Release Version 3.1
//
// SVN Revision Information:
// SVN $Revision: 17372 $
// SVN $Date: 2012-08-03 09:09:54 -0700 (Fri, 03 Aug 2012) $
//
// Resolved SARs
// SAR Date Who Description
//
// Notes:
// 1. best viewed with tabstops set to "4" (tabs used throughout file)
//
// *********************************************************************/
`timescale 1ns/1ps
module COREAHBLITE_ADDRDEC #(
parameter [2:0]MEMSPACE = 0,
parameter [0:0]HADDR_SHG_CFG = 1,
parameter [15:0]SC = 0,
parameter [16:0]M_AHBSLOTENABLE = (2**17)-1
)
(
input [31:0] ADDR,
input REMAP,
output wire [16:0] ADDRDEC,
output wire [31:0] ABSOLUTEADDR,
output wire RESERVEDDEC
);
localparam MSB_ADDR = (MEMSPACE == 1) ? 31 :
(MEMSPACE == 2) ? 27 :
(MEMSPACE == 3) ? 23 :
(MEMSPACE == 4) ? 19 :
(MEMSPACE == 5) ? 15 :
(MEMSPACE == 6) ? 11 :
31 ;
localparam SLAVE_0 = 16'b0000000000000001;
localparam SLAVE_1 = 16'b0000000000000010;
localparam SLAVE_2 = 16'b0000000000000100;
localparam SLAVE_3 = 16'b0000000000001000;
localparam SLAVE_4 = 16'b0000000000010000;
localparam SLAVE_5 = 16'b0000000000100000;
localparam SLAVE_6 = 16'b0000000001000000;
localparam SLAVE_7 = 16'b0000000010000000;
localparam SLAVE_8 = 16'b0000000100000000;
localparam SLAVE_9 = 16'b0000001000000000;
localparam SLAVE_10 = 16'b0000010000000000;
localparam SLAVE_11 = 16'b0000100000000000;
localparam SLAVE_12 = 16'b0001000000000000;
localparam SLAVE_13 = 16'b0010000000000000;
localparam SLAVE_14 = 16'b0100000000000000;
localparam SLAVE_15 = 16'b1000000000000000;
localparam NONE = 16'b0000000000000000;
reg [15:0] sdec_raw;
reg [15:0] sdec;
reg s16dec;
reg [31:0] absaddr;
wire [16:0] ADDRDEC_pre;
wire [3:0] slotdec;
wire m0_hugeslotdec;
wire m0_otherslotsdec;
generate
begin: g_modes
if (MEMSPACE == 0)
begin: g_mem_0
assign m0_hugeslotdec = (ADDR[31]==1'b1);
assign m0_otherslotsdec = (ADDR[30:20]==11'h000);
assign slotdec = ADDR[19:16];
always @ ( * )
begin
absaddr[31:0] = ADDR[31:0];
sdec_raw[15:0] = NONE;
if (m0_hugeslotdec)
begin
s16dec = 1'b1;
if (HADDR_SHG_CFG == 0)
begin
absaddr[31] = 1'b0;
end
else
begin
absaddr[31] = 1'b1;
end
end
else if (m0_otherslotsdec)
begin
case (slotdec)
4'h0:
begin
if (REMAP==1'b0)
begin
sdec_raw[15:0] = SLAVE_0;
end
else
begin
absaddr[16] = 1'b1;
sdec_raw[15:0] = SLAVE_1;
end
end
4'h1:
begin
if (REMAP==1'b0)
begin
sdec_raw[15:0] = SLAVE_1;
end
else
begin
absaddr[16] = 1'b0;
sdec_raw[15:0] = SLAVE_0;
end
end
4'h2: sdec_raw[15:0] = SLAVE_2;
4'h3: sdec_raw[15:0] = SLAVE_3;
4'h4: sdec_raw[15:0] = SLAVE_4;
4'h5: sdec_raw[15:0] = SLAVE_5;
4'h6: sdec_raw[15:0] = SLAVE_6;
4'h7: sdec_raw[15:0] = SLAVE_7;
4'h8: sdec_raw[15:0] = SLAVE_8;
4'h9: sdec_raw[15:0] = SLAVE_9;
4'hA: sdec_raw[15:0] = SLAVE_10;
4'hB: sdec_raw[15:0] = SLAVE_11;
4'hC: sdec_raw[15:0] = SLAVE_12;
4'hD: sdec_raw[15:0] = SLAVE_13;
4'hE: sdec_raw[15:0] = SLAVE_14;
4'hF: sdec_raw[15:0] = SLAVE_15;
endcase
end
sdec = sdec_raw;
s16dec = m0_hugeslotdec;
end
assign RESERVEDDEC = m0_hugeslotdec==1'b0 & m0_otherslotsdec==1'b0;
end
else
begin: g_mem_1
assign m0_hugeslotdec = 1'b0;
assign m0_otherslotsdec = 1'b0;
assign slotdec = ADDR[MSB_ADDR:MSB_ADDR-3];
always @ ( * )
begin
absaddr[31:0] = ADDR[31:0];
case (slotdec)
4'h0:
begin
if (REMAP == 1'b0)
sdec_raw[15:0] = SLAVE_0;
else
begin
absaddr[MSB_ADDR-3] = 1'b1;
sdec_raw[15:0] = SLAVE_1;
end
end
4'h1:
begin
if (REMAP == 1'b0)
sdec_raw[15:0] = SLAVE_1;
else
begin
absaddr[MSB_ADDR-3] = 1'b0;
sdec_raw[15:0] = SLAVE_0;
end
end
4'h2: sdec_raw[15:0] = SLAVE_2;
4'h3: sdec_raw[15:0] = SLAVE_3;
4'h4: sdec_raw[15:0] = SLAVE_4;
4'h5: sdec_raw[15:0] = SLAVE_5;
4'h6: sdec_raw[15:0] = SLAVE_6;
4'h7: sdec_raw[15:0] = SLAVE_7;
4'h8: sdec_raw[15:0] = SLAVE_8;
4'h9: sdec_raw[15:0] = SLAVE_9;
4'hA: sdec_raw[15:0] = SLAVE_10;
4'hB: sdec_raw[15:0] = SLAVE_11;
4'hC: sdec_raw[15:0] = SLAVE_12;
4'hD: sdec_raw[15:0] = SLAVE_13;
4'hE: sdec_raw[15:0] = SLAVE_14;
4'hF: sdec_raw[15:0] = SLAVE_15;
endcase
sdec = sdec_raw & ~SC;
s16dec = |(sdec_raw & SC);
end
assign RESERVEDDEC = 1'b0;
end
assign ADDRDEC_pre[16:0] = {s16dec,sdec[15:0]};
assign ABSOLUTEADDR[31:0] = absaddr[31:0];
assign ADDRDEC[16:0] = ADDRDEC_pre[16:0];
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; #pragma GCC target( avx2 ) #pragma GCC optimization( unroll-loops ) #pragma GCC optimize( O2 ) constexpr int dx[] = {-1, 0, 1, 0, 1, 1, -1, -1}; constexpr int dy[] = {0, -1, 0, 1, 1, -1, 1, -1}; constexpr long long INF = 1999999999999999997; constexpr int inf = INT_MAX; constexpr int MAXSIZE = int(1e6) + 5; constexpr auto PI = 3.14159265358979323846L; constexpr auto oo = numeric_limits<int>::max() / 2 - 2; constexpr auto eps = 1e-6; constexpr auto mod = 1000000007; constexpr auto MOD = 1000000007; constexpr auto MOD9 = 1000000009; constexpr auto maxn = 100006; void fastio() { ios_base::sync_with_stdio(false); cin.tie(NULL); } int n, m, k; int fre; char a[502][502]; int x = -1, y = -1; bool visited[502][502]; int l; void dfs(int x, int y) { if (l == 0) return; if (x + 1 < n && a[x + 1][y] == . && !visited[x + 1][y] && l > 0) { visited[x + 1][y] = 1; l--; dfs(x + 1, y); } if (l == 0) return; if (y + 1 < m && a[x][y + 1] == . && !visited[x][y + 1] && l > 0) { visited[x][y + 1] = 1; l--; dfs(x, y + 1); } if (l == 0) return; if (x - 1 >= 0 && a[x - 1][y] == . && !visited[x - 1][y] && l > 0) { visited[x - 1][y] = 1; l--; dfs(x - 1, y); } if (l == 0) return; if (y - 1 < n && a[x][y - 1] == . && !visited[x][y - 1] && l > 0) { visited[x][y - 1] = 1; l--; dfs(x, y - 1); } if (l == 0) return; } int main() { fastio(); cin >> n >> m >> k; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> a[i][j]; if (a[i][j] == . ) { fre++; if (x == -1) { x = i, y = j; } } } } l = fre - k; int c = k; dfs(x, y); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (a[i][j] == . && !visited[i][j] && c > 0) { a[i][j] = X ; c--; } cout << a[i][j]; } cout << n ; } } |
`include "core.h"
`default_nettype none
module decode_mmucheck(
input wire iPAGING_ENA,
input wire iKERNEL_ACCESS,
input wire [13:0] iMMU_FLAGS,
output wire [2:0] oIRQ40,
output wire [2:0] oIRQ41,
output wire [2:0] oIRQ42
);
/*************************************************
MMU Flag Check
[0] : IRQ40 Invalid page.(Page fault)
[1] : IRQ41 Privilege error.(Page)
[2] : IRQ42 Invalid instruction.(Page)
*************************************************/
function [2:0] func_mmu_flags_fault_check;
input func_paging;
input func_kernel; //1:kernel mode
input [5:0] func_mmu_flags;
begin
if(func_paging)begin
//Page fault check
if(!func_mmu_flags[0])begin
func_mmu_flags_fault_check = 3'h1;
end
//Invalid instruction check
if(!func_mmu_flags[3])begin
func_mmu_flags_fault_check = 3'h4;
end
//Privilege error check
else begin
//Page check
if(func_kernel)begin //Kernell Mode
func_mmu_flags_fault_check = 3'h0;
end
else begin //User Mode
if(func_mmu_flags[5:4] != 2'h0)begin
func_mmu_flags_fault_check = 3'h0;
end
else begin
func_mmu_flags_fault_check = 3'h2; //Privilege Error
end
end
end
end
else begin
func_mmu_flags_fault_check = 3'h0;
end
end
endfunction
assign {oIRQ42, oIRQ41, oIRQ40} = func_mmu_flags_fault_check(iPAGING_ENA, iKERNEL_ACCESS, iMMU_FLAGS[5:0]);
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; template <class T, class L> bool smax(T& x, L y) { return x < y ? (x = y, 1) : 0; } template <class T, class L> bool smin(T& x, L y) { return x > y ? (x = y, 1) : 0; } const int maxn = 2e5 + 17, mod = 1e9 + 7; struct Seg { int lazy[maxn << 2], s[maxn << 2]; void build(int l = 0, int r = maxn, int id = 1) { s[id] = r - l; if (r - l < 2) return; int mid = l + r >> 1; build(l, mid, id << 1), build(mid, r, id << 1 | 1); } Seg() { fill(lazy, lazy + (maxn << 2), 1), build(); } void shift(int id) { lazy[id << 1] = (long long)lazy[id << 1] * lazy[id] % mod, lazy[id << 1 | 1] = (long long)lazy[id << 1 | 1] * lazy[id] % mod; s[id << 1] = (long long)s[id << 1] * lazy[id] % mod, s[id << 1 | 1] = (long long)s[id << 1 | 1] * lazy[id] % mod; lazy[id] = 1; } void add(int st, int en, int v, int l = 0, int r = maxn, int id = 1) { if (st <= l && r <= en) { s[id] = (long long)s[id] * v % mod, lazy[id] = (long long)lazy[id] * v % mod; return; } if (en <= l || r <= st) return; shift(id); int mid = l + r >> 1; add(st, en, v, l, mid, id << 1), add(st, en, v, mid, r, id << 1 | 1); s[id] = (s[id << 1] + s[id << 1 | 1]) % mod; } int get(int st, int en, int l = 0, int r = maxn, int id = 1) { if (st <= l && r <= en) return s[id]; if (en <= l || r <= st) return 0; shift(id); int mid = l + r >> 1; return (get(st, en, l, mid, id << 1) + get(st, en, mid, r, id << 1 | 1)) % mod; } void add(int l, int v) { add(l, l + 1, v); } int get(int l) { return get(l, l + 1); } } d, po, bad; struct Q { int t, p, v; } q[maxn]; int rev(int a) { int b = mod - 2, ans = 1; for (; b; b >>= 1) { if (b & 1) ans = (long long)ans * a % mod; a = (long long)a * a % mod; } return ans; } int tim, st[maxn], en[maxn], nq, deg[maxn], cnt = 1; vector<int> g[maxn]; void dfs(int v = 0) { st[v] = tim++; for (auto u : g[v]) dfs(u); en[v] = tim; } void DeemoLovesInit() { int tmp; cin >> tmp >> nq; po.add(0, tmp); bad.add(0, 0); fill(deg, deg + maxn, 1); for (int i = 0; i < nq && cin >> q[i].t; i++) if (q[i].t == 1) cin >> q[i].p >> q[i].v, g[--q[i].p].push_back(cnt++); else cin >> q[i].v, q[i].v--; dfs(); cnt = 1; } int main() { DeemoLovesInit(); for (int i = 0, t = q[i].t, v = q[i].v, p = q[i].p; i < nq; i++, t = q[i].t, v = q[i].v, p = q[i].p) if (t == 1) { po.add(st[cnt], (long long)rev(po.get(st[cnt])) * v % mod * d.get(st[p]) % mod); bad.add(st[cnt], 0); deg[p]++; d.add(st[p], en[p], (long long)rev(deg[p] - 1) * deg[p] % mod); po.add(st[p], en[p], (long long)rev(deg[p] - 1) * deg[p] % mod); bad.add(st[p], en[p], (long long)rev(deg[p] - 1) * deg[p] % mod); cnt++; } else { cout << (long long)(po.get(st[v], en[v]) - bad.get(st[v], en[v]) + mod) % mod * rev(d.get(st[v])) % mod * deg[v] % mod << n ; } return 0; } |
`include "senior_defines.vh"
`include "mnemonics.h"
`include "registers.h"
module instruction_decoder
#(parameter spr_adr_w = `SPR_ADR_BUS_WIDTH)
(
input wire clk_i,
input wire reset_i,
input wire [31:0] pm_inst_bus_i,
output wire [`AGU_CTRL_WIDTH-1:0] agu_ctrl_o,
output wire [`ALU_CTRL_WIDTH-1:0] alu_ctrl_o,
output wire [`MAC_CTRL_WIDTH-1:0] mac_ctrl_o,
output wire [`COND_LOGIC_CTRL_WIDTH-1:0] cond_logic_ctrl_p5_o,
output wire [`COND_LOGIC_CTRL_WIDTH-1:0] cond_logic_ctrl_p4_o,
output wire [`LC_CTRL_WIDTH-1:0] loop_counter_ctrl_o,
output wire [`WB_MUX_CTRL_WIDTH-1:0] wb_mux_ctrl_o,
output wire [`PFC_CTRL_WIDTH-1:0] pc_fsm_ctrl_o,
output wire [`RF_CTRL_WIDTH-1:0] rf_ctrl_o,
output wire [`IO_CTRL_WIDTH-1:0] io_ctrl_o,
output wire [`OPSEL_CTRL_WIDTH-1:0] opsel_ctrl_o,
output wire [`SENIOR_NATIVE_WIDTH-1:0] imm_val_p3_o,
output wire [`SENIOR_NATIVE_WIDTH-1:0] imm_val_p4_o,
output wire [`SENIOR_NATIVE_WIDTH-1:0] imm_val_p5_o,
output wire [`SPR_CTRL_WIDTH-1:0] spr_ctrl_o,
output wire [`DM_DATA_SELECT_CTRL_WIDTH-1:0] dm_data_select_ctrl_o,
output wire [`FWD_CTRL_WIDTH-1:0] fwd_ctrl_o);
wire [`AGU_CTRL_WIDTH-1:0] agu_ctrl_decoded;
wire [`ALU_CTRL_WIDTH-1:0] alu_ctrl_decoded;
wire [`MAC_CTRL_WIDTH-1:0] mac_ctrl_decoded;
wire [`COND_LOGIC_CTRL_WIDTH-1:0] cond_logic_ctrl_decoded;
wire [`LC_CTRL_WIDTH-1:0] loop_counter_ctrl_decoded;
wire [`WB_MUX_CTRL_WIDTH-1:0] wb_mux_ctrl_decoded;
wire [`PFC_CTRL_WIDTH-1:0] pc_fsm_ctrl_decoded;
wire [`RF_CTRL_WIDTH-1:0] rf_ctrl_decoded;
wire [`IO_CTRL_WIDTH-1:0] io_ctrl_decoded;
wire [`OPSEL_CTRL_WIDTH-1:0] opsel_ctrl_decoded;
wire [`SPR_CTRL_WIDTH-1:0] spr_ctrl_decoded;
wire [`DM_DATA_SELECT_CTRL_WIDTH-1:0] dm_data_select_ctrl_decoded;
// wire [``FWD_CTRL_WIDTH-1:0] fwd_ctrl_decoded;
wire [`ID_PIPE_TYPE_WIDTH-1:0] pipeline_type;
wire [15:0] imm_val_decoded;
id_decode_logic decode_logic
(
// Outputs
.agu_ctrl_o (agu_ctrl_decoded),
.alu_ctrl_o (alu_ctrl_decoded),
.mac_ctrl_o (mac_ctrl_decoded),
.cond_logic_ctrl_o (cond_logic_ctrl_decoded),
.loop_counter_ctrl_o (loop_counter_ctrl_decoded),
.wb_mux_ctrl_o (wb_mux_ctrl_decoded),
.pc_fsm_ctrl_o (pc_fsm_ctrl_decoded),
.rf_ctrl_o (rf_ctrl_decoded),
.io_ctrl_o (io_ctrl_decoded),
.opsel_ctrl_o (opsel_ctrl_decoded),
.imm_val_o (imm_val_decoded),
.pipeline_type_o (pipeline_type),
.spr_ctrl_o (spr_ctrl_decoded),
.dm_data_select_ctrl_o (dm_data_select_ctrl_decoded),
// Inputs
.pm_inst_bus_i (pm_inst_bus_i));
id_pipeline_logic pipeline_logic
(
// Outputs
.agu_ctrl_o (agu_ctrl_o),
.alu_ctrl_o (alu_ctrl_o),
.mac_ctrl_o (mac_ctrl_o),
.cond_logic_ctrl_p5_o (cond_logic_ctrl_p5_o),
.cond_logic_ctrl_p4_o (cond_logic_ctrl_p4_o),
.loop_counter_ctrl_o (loop_counter_ctrl_o),
.wb_mux_ctrl_o (wb_mux_ctrl_o),
.pc_fsm_ctrl_o (pc_fsm_ctrl_o),
.rf_ctrl_o (rf_ctrl_o),
.io_ctrl_o (io_ctrl_o),
.opsel_ctrl_o (opsel_ctrl_o),
.imm_val_p3_o (imm_val_p3_o),
.imm_val_p4_o (imm_val_p4_o),
.imm_val_p5_o (imm_val_p5_o),
.spr_ctrl_o (spr_ctrl_o),
.dm_data_select_ctrl_o (dm_data_select_ctrl_o),
.fwd_ctrl_o (fwd_ctrl_o),
// Inputs
.clk_i (clk_i),
.reset_i (reset_i),
.agu_ctrl_i (agu_ctrl_decoded),
.alu_ctrl_i (alu_ctrl_decoded),
.mac_ctrl_i (mac_ctrl_decoded),
.cond_logic_ctrl_i (cond_logic_ctrl_decoded),
.loop_counter_ctrl_i (loop_counter_ctrl_decoded),
.wb_mux_ctrl_i (wb_mux_ctrl_decoded),
.pc_fsm_ctrl_i (pc_fsm_ctrl_decoded),
.rf_ctrl_i (rf_ctrl_decoded),
.io_ctrl_i (io_ctrl_decoded),
.opsel_ctrl_i (opsel_ctrl_decoded),
.imm_val_i (imm_val_decoded),
.pipeline_type_i (pipeline_type),
.spr_ctrl_i (spr_ctrl_decoded),
.dm_data_select_ctrl_i (dm_data_select_ctrl_decoded));
endmodule // ID_new
|
// niosii_nios2_gen2_0.v
// This file was auto-generated from altera_nios2_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module niosii_nios2_gen2_0 (
input wire clk, // clk.clk
input wire reset_n, // reset.reset_n
input wire reset_req, // .reset_req
output wire [22:0] d_address, // data_master.address
output wire [3:0] d_byteenable, // .byteenable
output wire d_read, // .read
input wire [31:0] d_readdata, // .readdata
input wire d_waitrequest, // .waitrequest
output wire d_write, // .write
output wire [31:0] d_writedata, // .writedata
output wire debug_mem_slave_debugaccess_to_roms, // .debugaccess
output wire [22:0] i_address, // instruction_master.address
output wire i_read, // .read
input wire [31:0] i_readdata, // .readdata
input wire i_waitrequest, // .waitrequest
input wire [31:0] irq, // irq.irq
output wire debug_reset_request, // debug_reset_request.reset
input wire [8:0] debug_mem_slave_address, // debug_mem_slave.address
input wire [3:0] debug_mem_slave_byteenable, // .byteenable
input wire debug_mem_slave_debugaccess, // .debugaccess
input wire debug_mem_slave_read, // .read
output wire [31:0] debug_mem_slave_readdata, // .readdata
output wire debug_mem_slave_waitrequest, // .waitrequest
input wire debug_mem_slave_write, // .write
input wire [31:0] debug_mem_slave_writedata, // .writedata
output wire dummy_ci_port // custom_instruction_master.readra
);
niosii_nios2_gen2_0_cpu cpu (
.clk (clk), // clk.clk
.reset_n (reset_n), // reset.reset_n
.reset_req (reset_req), // .reset_req
.d_address (d_address), // data_master.address
.d_byteenable (d_byteenable), // .byteenable
.d_read (d_read), // .read
.d_readdata (d_readdata), // .readdata
.d_waitrequest (d_waitrequest), // .waitrequest
.d_write (d_write), // .write
.d_writedata (d_writedata), // .writedata
.debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms), // .debugaccess
.i_address (i_address), // instruction_master.address
.i_read (i_read), // .read
.i_readdata (i_readdata), // .readdata
.i_waitrequest (i_waitrequest), // .waitrequest
.irq (irq), // irq.irq
.debug_reset_request (debug_reset_request), // debug_reset_request.reset
.debug_mem_slave_address (debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (debug_mem_slave_read), // .read
.debug_mem_slave_readdata (debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (debug_mem_slave_write), // .write
.debug_mem_slave_writedata (debug_mem_slave_writedata), // .writedata
.dummy_ci_port (dummy_ci_port) // custom_instruction_master.readra
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string str; cin >> str; int t = 0; while (str[t]) { if (str[t] == . ) { cout << 0; t++; } else if (str[t] == - && str[t + 1] == . ) { cout << 1; t += 2; } else if (str[t] == - && str[t + 1] == - ) { cout << 2; t += 2; } } cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; void __print(int x) { cerr << x; } void __print(long x) { cerr << x; } void __print(long long x) { cerr << x; } void __print(unsigned x) { cerr << x; } void __print(unsigned long x) { cerr << x; } void __print(unsigned long long x) { cerr << x; } void __print(float x) { cerr << x; } void __print(double x) { cerr << x; } void __print(long double x) { cerr << x; } void __print(char x) { cerr << << x << ; } void __print(const char *x) { cerr << << x << ; } void __print(const string &x) { cerr << << x << ; } void __print(bool x) { cerr << (x ? true : false ); } template <typename T, typename V> void __print(const pair<T, V> &x) { cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ; } template <typename T> void __print(const T &x) { int f = 0; cerr << { ; for (auto &i : x) cerr << (f++ ? , : ), __print(i); cerr << } ; } void _print() { cerr << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) cerr << , ; _print(v...); } vector<long long> adj[200005]; void solve() { long long n, m; cin >> n >> m; for (long long i = 0; i < m; i++) { long long u, v; cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); } vector<long long> cnt(n + 1); vector<long long> a(n + 1); queue<long long> q; for (long long i = 1; i < n + 1; i++) { cin >> a[i]; if (!a[i]) q.push(i); } vector<long long> ans; vector<long long> vis(n + 1); while (!q.empty()) { long long p = q.front(); q.pop(); cnt[p]++; ans.push_back(p); for (auto x : adj[p]) { cnt[x]++; if (cnt[x] == a[x]) q.push(x); } } cout << ans.size() << n ; for (auto x : ans) cout << x << ; cout << n ; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t; t = 1; for (long long i = 0; i < t; i++) { solve(); } } |
#include <bits/stdc++.h> using namespace std; const int maxn = 5005; int u[maxn], v[maxn], w[maxn], dp[maxn][maxn], parent[maxn][maxn], x[maxn]; int main() { int n, m, t, pos; cin >> n >> m >> t; for (int i = 0; i < m; i++) { cin >> u[i] >> v[i] >> w[i]; } memset(dp, 0x3f, sizeof(dp)); dp[1][1] = 0; for (int i = 2; i <= n; i++) { for (int j = 0; j < m; j++) { if (dp[i - 1][u[j]] + w[j] < dp[i][v[j]]) { dp[i][v[j]] = dp[i - 1][u[j]] + w[j]; parent[i][v[j]] = u[j]; } } if (dp[i][n] <= t) pos = i; } int id = n; for (int i = pos; i >= 1; i--) { x[i] = id; id = parent[i][id]; } cout << pos << endl; for (int i = 1; i <= pos; i++) cout << x[i] << ; return 0; } |
#include <bits/stdc++.h> using namespace std; static const int maxn = 100012; int K1, K2, K3; int T1, T2, T3; int N; int C[maxn]; void Read() { int i; scanf( %d%d%d , &K1, &K2, &K3); scanf( %d%d%d , &T1, &T2, &T3); scanf( %d , &N); for (i = 0; i < N; ++i) { scanf( %d , &C[i]); } } inline bool Greater(long long x, long long y) { return x > y; } long long Result; long long X[maxn]; long long Y[maxn]; long long Z[maxn]; void Work() { int i; Result = 0; memset(X, 0, sizeof(X)); memset(Y, 0, sizeof(Y)); memset(Z, 0, sizeof(Z)); if (K1 > N) K1 = N; if (K2 > N) K2 = N; if (K3 > N) K3 = N; make_heap(X, X + K1, Greater); make_heap(Y, Y + K2, Greater); make_heap(Z, Z + K3, Greater); for (i = 0; i < N; ++i) { long long t = C[i]; pop_heap(X, X + K1, Greater); if (t < X[K1 - 1]) t = X[K1 - 1]; t += T1; X[K1 - 1] = t; push_heap(X, X + K1, Greater); pop_heap(Y, Y + K2, Greater); if (t < Y[K2 - 1]) t = Y[K2 - 1]; t += T2; Y[K2 - 1] = t; push_heap(Y, Y + K2, Greater); pop_heap(Z, Z + K3, Greater); if (t < Z[K3 - 1]) t = Z[K3 - 1]; t += T3; Z[K3 - 1] = t; push_heap(Z, Z + K3, Greater); if (Result < t - C[i]) Result = t - C[i]; } } void Write() { printf( %I64d n , Result); } int main() { Read(); Work(); Write(); return 0; } |
#include <bits/stdc++.h> long long t, a, b, h, f[110]; using namespace std; long long mi(long long n, long long m) { long long res = 1; for (int i = 1; i <= m; i++) res *= n; return res; } void solve(long long a, long long b) { for (int i = h; i; i--) { long long t = mi(a, i); f[i] = b / t; b %= t; } f[0] = b; } int main() { scanf( %lld%lld%lld , &t, &a, &b); if (a == b && b == t) { if (a == 1) puts( inf ); else puts( 2 ); } else if (a == b) puts( 1 ); else { if (t == 1) { h = log(b) / log(a); for (int i = 1; i <= h; i++) if (mi(a, i) == b) { puts( 1 ); return 0; } } h = log(b) / log(a); solve(a, b); long long sum = 0; for (int i = 0; i <= h; i++) sum += f[i] * mi(t, i); if (sum != a) puts( 0 ); else puts( 1 ); } return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; template <typename T> using min_priority_queue = priority_queue<T, vector<T>, greater<T>>; const ll inf = 1LL << 60; vector<ll> dv; void divisor(ll n) { for (ll i = 1; i * i <= n; i++) { if (n % i == 0) { if (i == n / i) { dv.push_back(i); } else { dv.push_back(i); dv.push_back(n / i); } } } } ll gcd(ll a, ll b) { if (a == 0 || b == 0) return 0; if (a % b == 0) return b; return gcd(b, a % b); } int main() { ll l, r, x, y; cin >> l >> r >> x >> y; if (y % x != 0) cout << 0 << endl; else { ll tmp = y / x; divisor(tmp); ll ans = 0; for (auto &z : dv) { ll a = z; ll b = tmp / z; if (gcd(a, b) == 1) { if (l <= x * a && x * a <= r && l <= x * b && x * b <= r) ans++; } } cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> inline void read(T &x) { x = 0; char c = getchar(); bool flag = false; while (!isdigit(c)) { if (c == - ) flag = true; c = getchar(); } while (isdigit(c)) { x = (x << 1) + (x << 3) + (c ^ 48); c = getchar(); } if (flag) x = -x; } int n, q, root = 1; int a[1000010], mn[4000010], val[4000010], tag[4000010]; void pushup(int cur) { if (mn[(cur << 1)] < mn[(cur << 1 | 1)]) mn[cur] = mn[(cur << 1)], val[cur] = val[(cur << 1)]; else if (mn[(cur << 1)] > mn[(cur << 1 | 1)]) mn[cur] = mn[(cur << 1 | 1)], val[cur] = val[(cur << 1 | 1)]; else mn[cur] = mn[(cur << 1)], val[cur] = val[(cur << 1)] + val[(cur << 1 | 1)]; } void pushtag(int cur, int v) { mn[cur] += v, tag[cur] += v; } void pushdown(int cur) { if (!tag[cur]) return; pushtag((cur << 1), tag[cur]), pushtag((cur << 1 | 1), tag[cur]), tag[cur] = 0; } void update(int l, int r, int pos, int v, int cur) { if (l == r) { val[cur] += v; return; } pushdown(cur); if (pos <= ((l + r) >> 1)) update(l, ((l + r) >> 1), pos, v, (cur << 1)); else update(((l + r) >> 1) + 1, r, pos, v, (cur << 1 | 1)); pushup(cur); } void modify(int L, int R, int l, int r, int v, int cur) { if (L > R) return; if (L <= l && R >= r) { pushtag(cur, v); return; } pushdown(cur); if (L <= ((l + r) >> 1)) modify(L, R, l, ((l + r) >> 1), v, (cur << 1)); if (R > ((l + r) >> 1)) modify(L, R, ((l + r) >> 1) + 1, r, v, (cur << 1 | 1)); pushup(cur); } int query(int L, int R, int l, int r, int cur) { if (L <= l && R >= r) return mn[cur] == 1 ? val[cur] : 0; int v = 0; pushdown(cur); if (L <= ((l + r) >> 1)) v += query(L, R, l, ((l + r) >> 1), (cur << 1)); if (R > ((l + r) >> 1)) v += query(L, R, ((l + r) >> 1) + 1, r, (cur << 1 | 1)); return v; } int main() { read(n), read(q), a[0] = 1000001; for (int i = 1; i <= n; ++i) read(a[i]), update(0, 1000001, a[i], 1, root); for (int i = 0; i <= n; ++i) modify(min(a[i], a[i + 1]), max(a[i], a[i + 1]) - 1, 0, 1000001, 1, root); while (q--) { int x; read(x), update(0, 1000001, a[x], -1, root); modify(min(a[x], a[x + 1]), max(a[x], a[x + 1]) - 1, 0, 1000001, -1, root); modify(min(a[x - 1], a[x]), max(a[x - 1], a[x]) - 1, 0, 1000001, -1, root); read(a[x]), update(0, 1000001, a[x], 1, root); modify(min(a[x], a[x + 1]), max(a[x], a[x + 1]) - 1, 0, 1000001, 1, root); modify(min(a[x - 1], a[x]), max(a[x - 1], a[x]) - 1, 0, 1000001, 1, root); printf( %d n , query(1, 1000001 - 1, 0, 1000001, root)); } return 0; } |
#include <bits/stdc++.h> using namespace std; #pragma warning(disable : 4996) const int N = 2e5 + 5, L = 19; string s; int cl[L][N], sf[L][N], ct[N], pos[N], lcp[N], t[L][N], g[N]; pair<int, int> a[N + N]; int *suf = sf[L - 1]; int que(int l, int r) { int k = g[r - l + 1]; return min(t[k][l], t[k][r - (1 << k) + 1]); } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); for (int i = 2; i < N; i++) g[i] = g[i >> 1] + 1; int n, q; cin >> n >> q >> s; s += # ; n++; for (int i = 0; i < n; i++) { ct[s[i]]++; } for (int i = 0; i < N - 1; i++) { ct[i + 1] += ct[i]; } for (int i = n - 1; i >= 0; i--) { sf[0][--ct[s[i]]] = i; cl[0][i] = s[i]; } for (int i = 1; i < L; i++) { for (int j = 0; j < n; j++) { sf[i - 1][j] = (sf[i - 1][j] - (1 << (i - 1)) % n + n) % n; } fill(ct, ct + N, 0); for (int j = 0; j < n; j++) { ct[cl[i - 1][sf[i - 1][j]]]++; } for (int j = 0; j < N - 1; j++) { ct[j + 1] += ct[j]; } for (int j = n - 1; j >= 0; j--) { sf[i][--ct[cl[i - 1][sf[i - 1][j]]]] = sf[i - 1][j]; } for (int j = 0, k = 0; j < n; j++) { cl[i][sf[i][j]] = k; if (j + 1 < n && (cl[i - 1][sf[i][j]] != cl[i - 1][sf[i][j + 1]] || cl[i - 1][(sf[i][j] + (1 << (i - 1))) % n] != cl[i - 1][(sf[i][j + 1] + (1 << (i - 1))) % n])) { k++; } } } for (int i = 0; i < n; i++) { pos[suf[i]] = i; } for (int i = 0, j = 0; i < n; i++) { int p = pos[i]; if (p == n - 1) { j = 0; continue; } int q = suf[p + 1]; while (i + j < n && q + j < n && s[i + j] == s[q + j]) { j++; } lcp[p] = j; j = max(0, j - 1); } for (int i = 0; i < n; i++) { t[0][i] = lcp[i]; } for (int i = 1; i < L; i++) { for (int j = 0; j + (1 << i) <= n; j++) { t[i][j] = min(t[i - 1][j], t[i - 1][j + (1 << (i - 1))]); } } for (int i = 0; i < q; i++) { int la, lb, ls; cin >> la >> lb; ls = 0; for (int j = 0; j < la; j++) { cin >> a[ls].first; a[ls].first--; a[ls++].second = 1; } for (int j = 0; j < lb; j++) { cin >> a[ls].first; a[ls].first--; a[ls++].second = 0; } sort(a, a + ls, [](pair<int, int> &x, pair<int, int> &y) { if (pos[x.first] == pos[y.first]) return x.second < y.second; return pos[x.first] < pos[y.first]; }); long long ans = 0; for (int j = 0; j < ls - 1; j++) { if (a[j].first == a[j + 1].first) ans += n - 1 - a[j].first; } vector<pair<int, int>> v; v.push_back({-1, 0}); long long sum = 0; for (int j = 1; j < ls; j++) { if (a[j - 1].first != a[j].first) { int h = que(pos[a[j - 1].first], pos[a[j].first] - 1), x = a[j - 1].second; while (v.back().first >= h) { x += v.back().second; sum -= v.back().first * (long long)v.back().second; v.pop_back(); } v.push_back({h, x}); sum += x * (long long)h; } if (!a[j].second) ans += sum; } for (int j = 0; j < ls - 1; j++) { if (a[j].first == a[j + 1].first) swap(a[j], a[j + 1]); } v.clear(); v.push_back({-1, 0}); sum = 0; for (int j = ls - 2; j >= 0; j--) { if (a[j + 1].first != a[j].first) { int h = que(pos[a[j].first], pos[a[j + 1].first] - 1), x = a[j + 1].second; while (v.back().first >= h) { x += v.back().second; sum -= v.back().first * (long long)v.back().second; v.pop_back(); } v.push_back({h, x}); sum += x * (long long)h; } if (!a[j].second) ans += sum; } cout << ans << n ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPVGND_1_V
`define SKY130_FD_SC_MS__TAPVGND_1_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection
* 1 row down.
*
* Verilog wrapper for tapvgnd with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__tapvgnd.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__tapvgnd_1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__tapvgnd base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__tapvgnd_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__tapvgnd base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPVGND_1_V
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#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; int main() { int n; cin >> n; int maxn = 0; int x, y; while (n--) { scanf( %d %d , &x, &y); maxn = max(maxn, x + y); } cout << maxn << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> arr(n); for (int i = 0; i < n; i++) { cin >> arr[i]; } int m; cin >> m; while (m--) { int k, pos; cin >> k >> pos; pos--; vector<vector<int>> ans(k); vector<long long> sums(k); int last = 0; for (int i = 0; i < n; i++) { for (int j = last; j >= 0; j--) { if (j >= k) continue; if (ans[j].size() == 0) { if (j == 0) { ans[j].push_back(arr[i]); sums[j] = arr[i]; } else { ans[j] = ans[j - 1]; ans[j].push_back(arr[i]); sums[j] = sums[j - 1] + arr[i]; } } else { if (j == 0) { if (arr[i] > sums[j]) { ans[j][0] = arr[i]; sums[j] = arr[i]; } } else if (sums[j - 1] + arr[i] > sums[j]) { sums[j] = sums[j - 1] + arr[i]; ans[j] = ans[j - 1]; ans[j].push_back(arr[i]); } else if (sums[j - 1] + arr[i] == sums[j]) { bool change = 0; for (int k = 0; k < ans[j - 1].size(); k++) { if (ans[j - 1][k] < ans[j][k]) { change = 1; break; } else if (ans[j - 1][k] > ans[j][k]) { break; } } if (change) { ans[j] = ans[j - 1]; ans[j].push_back(arr[i]); } } } } last += 1; } cout << ans[k - 1][pos] << n ; } return 0; } |
#include <bits/stdc++.h> #pragma optimize( avx ) #pragma optimize( no-stack-protector ) namespace io { inline char gnc() { return (char)getchar(); } template <typename T> inline void gi(T &dx) { dx = 0; int yc = gnc(); bool nega = false; while (yc < 0 || yc > 9 ) { nega = (yc == - ? true : nega); yc = gnc(); } while (yc >= 0 && yc <= 9 ) { dx = (T)(dx * 10 + yc - 0 ); yc = gnc(); } if (nega) { dx = -dx; } } void gc(char &a) { do a = gnc(); while (!isgraph(a)); } void gss(char *c) { *c = gnc(); while (!isgraph(*c)) *c = gnc(); while (isgraph(*c)) *++c = gnc(); *c = 0; } template <typename t1, typename t2> inline void gi(t1 &a, t2 &b) { gi(a); gi(b); } template <typename t1, typename t2, typename t3> inline void gi(t1 &a, t2 &b, t3 &c) { gi(a); gi(b); gi(c); } template <typename t1, typename t2, typename t3, typename t4> inline void gi(t1 &a, t2 &b, t3 &c, t4 &d) { gi(a); gi(b); gi(c); gi(d); } template <typename t1, typename t2, typename t3, typename t4, typename t5> inline void gi(t1 &a, t2 &b, t3 &c, t4 &d, t5 &e) { gi(a); gi(b); gi(c); gi(d); gi(e); } } // namespace io using namespace io; using namespace std; inline int gcd(int x, int y) { return y > x ? gcd(y, x) : y ? gcd(y, x % y) : x; } inline void exgcd(int a, int b, int &x, int &y) { if (!b) { x = 1; y = 0; return; } exgcd(b, a % b, x, y); int t = x; x = y; y = t - (a / b) * y; } const int INF = 0x3f3f3f3f; const int MOD = 1e9 + 7; const int Rev = (MOD + 1) >> 1; template <typename T> inline void Sol(T &x) { if (x >= MOD) x -= MOD; } template <typename t1, typename t2> inline int inc(t1 x, t2 y) { x += y; if (x >= MOD) x -= MOD; return x; } template <typename t1, typename t2> inline int dec(t1 x, t2 y) { x += MOD - y; if (x >= MOD) x -= MOD; return x; } template <typename t1, typename t2> inline long long mul(t1 x, t2 y) { long long res = (long long)x * y; return res >= MOD ? res % MOD : res; } template <typename t1, typename t2, typename t3> inline long long mul(t1 x, t2 y, t3 z) { return mul(mul(x, y), z); } template <typename t1, typename t2, typename t3, typename t4> inline long long mul(t1 a, t2 b, t3 c, t4 d) { return mul(mul(a, b), mul(c, d)); } inline long long qpow(long long x, int y) { long long res = 1; for (; y; y >>= 1, x = x * x % MOD) if (y & 1) res = res * x % MOD; return res; } inline long long read() { int x = 0, f = 1; char c = getchar(); while (!isdigit(c)) { if (c == - ) f = -1; c = getchar(); } while (isdigit(c)) { x = x * 10 + c - 0 ; c = getchar(); } return x * f; } template <typename T1, typename T2> inline void Getmin(T1 &x, T2 y) { if (x > y) x = y; } template <typename T1, typename T2> inline void Getmax(T1 &x, T2 y) { if (x < y) x = y; } const int MAXN = 52; int n, d[MAXN], f[2][MAXN][MAXN][MAXN][MAXN]; inline long long binom(long long x) { return 1LL * x * (x - 1) / 2ll % MOD; } int main() { n = read(); for (int i = 1; i <= n; i++) d[i] = read(); int np = 0; f[np][d[1] == 2][d[1] == 3][d[2] == 2][d[2] == 3] = 1; for (int i = 3; i <= n; i++) { int p = np, op = d[i] & 1; np ^= 1; memset(f[np], 0, sizeof f[np]); for (int pre1 = 0; pre1 < i; pre1++) for (int pre2 = 0; pre2 < i - pre1; pre2++) { int now1up = i - pre1 - pre2, now2up; for (int now1 = 0; now1 < now1up; now1++) { now2up = now1up - now1; for (int now2 = 0; now2 < now2up; now2++) if (f[p][pre1][pre2][now1][now2]) { if (!(now1 || now2 || pre1 || pre2)) continue; int val = f[p][pre1][pre2][now1][now2]; if (!pre1 && !pre2) { if (now1) f[np][now1 - 1][now2][op ^ 1][op] = inc(f[np][now1 - 1][now2][op ^ 1][op], mul(val, now1)); if (now2) f[np][now1 + 1][now2 - 1][op ^ 1][op] = inc( f[np][now1 + 1][now2 - 1][op ^ 1][op], mul(val, now2)); } else { if (pre1) { int newnow1 = now1 + (op ^ 1), newnow2 = now2 + op; long long v = mul(val, pre1); int newpre1 = pre1 - 1; f[np][newpre1][pre2][newnow1][newnow2] = inc(f[np][newpre1][pre2][newnow1][newnow2], v); if (now1) { f[np][newpre1][pre2][now1 - 1 + op][now2] = inc(f[np][newpre1][pre2][now1 - 1 + op][now2], mul(v, now1)); if (op && now1 > 1) f[np][newpre1][pre2][now1 - 2][now2] = inc(f[np][newpre1][pre2][now1 - 2][now2], mul(v, binom(now1))); } if (now2) { f[np][newpre1][pre2][now1 + op + 1][now2 - 1] = inc(f[np][newpre1][pre2][now1 + op + 1][now2 - 1], mul(v, now2)); if (op && now2 > 1) f[np][newpre1][pre2][now1 + 2][now2 - 2] = inc(f[np][newpre1][pre2][now1 + 2][now2 - 2], mul(v, binom(now2))); } if (now1 && now2 && op) f[np][newpre1][pre2][now1][now2 - 1] = inc(f[np][newpre1][pre2][now1][now2 - 1], mul(mul(v, now1), now2)); } if (pre2) { int newnow1 = now1 + (op ^ 1), newnow2 = now2 + op; long long v = mul(val, pre2); int newpre1 = pre1 + 1, newpre2 = pre2 - 1; f[np][newpre1][newpre2][newnow1][newnow2] = inc(f[np][newpre1][newpre2][newnow1][newnow2], v); if (now1) { f[np][newpre1][newpre2][now1 - 1 + op][now2] = inc(f[np][newpre1][newpre2][now1 - 1 + op][now2], mul(v, now1)); if (op && now1 > 1) f[np][newpre1][newpre2][now1 - 2][now2] = inc(f[np][newpre1][newpre2][now1 - 2][now2], mul(v, binom(now1))); } if (now2) { f[np][newpre1][newpre2][now1 + op + 1][now2 - 1] = inc(f[np][newpre1][newpre2][now1 + op + 1][now2 - 1], mul(v, now2)); if (op && now2 > 1) f[np][newpre1][newpre2][now1 + 2][now2 - 2] = inc(f[np][newpre1][newpre2][now1 + 2][now2 - 2], mul(v, binom(now2))); } if (now1 && now2 && op) f[np][newpre1][newpre2][now1][now2 - 1] = inc(f[np][newpre1][newpre2][now1][now2 - 1], mul(v, now1, now2)); } } } } } } int ans = f[n & 1][0][0][0][0]; printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> const int INF = 2147483647; using namespace std; unsigned char like[7][7]; int fenzu[7]; int n, totjy[3]; int getnum(char l[50]) { switch (l[0]) { case A : return 0; case C : if (l[1] == h ) return 1; else return 2; case T : return 3; case D : return 4; case S : return 5; case H : return 6; } } void init_and_read() { int i; char pa[50], pb[50]; scanf( %d , &n); memset(like, 0, sizeof(like)); for (i = 1; i <= n; i++) { scanf( %s likes %s , &pa, &pb); like[getnum(pa)][getnum(pb)] = 1; } for (i = 0; i < 3; i++) scanf( %d , &totjy[i]); } void Dec_To_Three(int x) { int i = 0; while (i < 7) { fenzu[i] = x % 3; x /= 3; i++; } } int Abs(int x) { return (x > 0) ? x : (-x); } int max(int a, int b, int c) { a = (a > b) ? a : b; return (a > c) ? a : c; } void solve_and_print() { int i, j, k, flag, peplo[3], jingyan[3], minidif = INF, maxlike = -INF; int tmp, totlike; for (i = 0; i <= 2186; i++) { Dec_To_Three(i); peplo[0] = peplo[1] = peplo[2] = 0; for (j = 0; j <= 6; j++) { peplo[fenzu[j]]++; } flag = 0; for (j = 0; j <= 2; j++) { if (!peplo[j]) { flag = 1; break; } jingyan[j] = totjy[j] / peplo[j]; } if (flag) continue; tmp = max(Abs(jingyan[0] - jingyan[1]), Abs(jingyan[0] - jingyan[2]), Abs(jingyan[1] - jingyan[2])); if (tmp < minidif) { minidif = tmp; maxlike = -INF; } if (tmp == minidif) { totlike = 0; for (j = 0; j <= 6; j++) { for (k = 0; k <= 6; k++) { if ((fenzu[j] == fenzu[k]) && (like[j][k])) { totlike++; } } } } if (totlike > maxlike) maxlike = totlike; } printf( %d %d n , minidif, maxlike); } int main() { init_and_read(); solve_and_print(); return 0; } |
#include <bits/stdc++.h> using namespace std; int a[100000], b[100000], c[100000][2]; int n, m; long long k, sum; int main() { cin >> n >> k; sum = 0; for (int i = 0; i < n; i++) { scanf( %d , &a[i]); b[i] = a[i]; long long aa = a[i]; sum += aa; } if (sum <= k) { if (sum < k) { printf( -1 n ); } return 0; } sort(b, b + n); m = 0; c[0][0] = b[0]; c[0][1] = 0; for (int i = 1; i < n; i++) if (b[i] != b[i - 1]) { m++; c[m][0] = b[i]; c[m][1] = i; } int pre = 0; for (int i = 0; i <= m; i++) { long long u, v, duc; v = c[i][0] - pre; u = n - c[i][1]; duc = u * v; if (duc <= k) { k -= duc; } else { int h = -1; for (int j = 0; j < n; j++) if (a[j] >= c[i][0]) { h++; a[h] = a[j]; b[h] = j; } long long s, t; s = k / u; t = k % u; int tt, ss; tt = t; ss = s; for (int j = tt; j <= h; j++) { if (j != tt) { printf( ); } printf( %d , b[j] + 1); } for (int j = 0; j < tt; j++) if ((ss + 1 != v) || (a[j] != c[i][0])) { printf( %d , b[j] + 1); } printf( n ); break; } pre = c[i][0]; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; long long d; cin >> n >> d; vector<long long> v; long long x; for (int i = 0; i < n; i++) { cin >> x; v.push_back(x); } int count = 0; for (int i = 0; i < n; i++) { for (int j = i + 1; j < n; j++) { if (v[i] - v[j] >= 0 && v[i] - v[j] <= d) count++; else if (v[j] - v[i] >= 0 && v[j] - v[i] <= d) count++; } } cout << count * 2 << endl; return 0; } |
#include <bits/stdc++.h> struct f { int pos; int num; } a[108]; int cmp(const void *a, const void *b) { return (*(struct f *)a).num - (*(struct f *)b).num; } int main() { int n, k; while (scanf( %d%d , &n, &k) == 2) { int i; for (i = 0; i < n; i++) { scanf( %d , &a[i].num); a[i].pos = i + 1; } qsort(a, n, sizeof(a[0]), cmp); int sum = 0; int count = 0; for (i = 0; i < n; i++) { if (i == 0 && a[i].num > k) break; sum += a[i].num; if (sum > k) break; count++; } printf( %d n , count); for (i = 0; i < count; i++) { if (i != 0) printf( %d , a[i].pos); else printf( %d , a[i].pos); } if (count) printf( n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long ans, p, s; int N; struct node { int a[2]; node *L, *R; node() { a[0] = a[1] = 0; L = R = NULL; } void add() { if (L == NULL) L = new node(); if (R == NULL) R = new node(); } }; void update(node *no, long long x, int h, int inc) { no->add(); if (h < 0) return; if (!(x & (1LL << h))) no->a[0]++, update(no->L, x, h - 1, inc); else no->a[1]++, update(no->R, x, h - 1, inc); } long long query(node *no, long long x, int h) { if (h < 0) return 0; no->add(); if (!(x & (1LL << h)) && no->a[1]) return (1LL << h) + query(no->R, x, h - 1); if ((x & (1LL << h)) && no->a[0]) return (1LL << h) + query(no->L, x, h - 1); if (no->a[0]) return query(no->L, x, h - 1); if (no->a[1]) return query(no->R, x, h - 1); return 0LL; } int main(int argc, char **argv) { node *no; no = new node(); scanf( %d , &N); vector<long long> a(N); for (auto &x : a) scanf( %I64d , &x); update(no, s, 42, 1); for (int i = (N - 1); i >= (0); i--) { s ^= a[i]; ans = max(ans, s); update(no, s, 42, 1); } for (int i = (0); i < (N); i++) { p ^= a[i]; s ^= a[i]; update(no, s, 42, -1); ans = max(ans, query(no, p, 42)); ans = max(ans, p); } printf( %I64d n , ans); return 0; } |
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA top-level module
*/
module fpga (
/*
* Clock: 125MHz
* Reset: Push button, active low
*/
input wire enet_clk_125m,
input wire c10_resetn,
/*
* GPIO
*/
input wire [3:0] user_pb,
input wire [2:0] user_dip,
output wire [3:0] user_led,
/*
* Ethernet: 1000BASE-T RGMII
*/
input wire enet_rx_clk,
input wire [3:0] enet_rx_d,
input wire enet_rx_dv,
output wire enet_tx_clk,
output wire [3:0] enet_tx_d,
output wire enet_tx_en,
output wire enet_resetn,
input wire enet_int
);
// Clock and reset
// Internal 125 MHz clock
wire clk_int;
wire rst_int;
wire pll_rst = ~c10_resetn;
wire pll_locked;
wire clk90_int;
altpll #(
.bandwidth_type("AUTO"),
.clk0_divide_by(1),
.clk0_duty_cycle(50),
.clk0_multiply_by(1),
.clk0_phase_shift("0"),
.clk1_divide_by(1),
.clk1_duty_cycle(50),
.clk1_multiply_by(1),
.clk1_phase_shift("2000"),
.compensate_clock("CLK0"),
.inclk0_input_frequency(8000),
.intended_device_family("Cyclone 10 LP"),
.operation_mode("NORMAL"),
.pll_type("AUTO"),
.port_activeclock("PORT_UNUSED"),
.port_areset("PORT_USED"),
.port_clkbad0("PORT_UNUSED"),
.port_clkbad1("PORT_UNUSED"),
.port_clkloss("PORT_UNUSED"),
.port_clkswitch("PORT_UNUSED"),
.port_configupdate("PORT_UNUSED"),
.port_fbin("PORT_UNUSED"),
.port_inclk0("PORT_USED"),
.port_inclk1("PORT_UNUSED"),
.port_locked("PORT_USED"),
.port_pfdena("PORT_UNUSED"),
.port_phasecounterselect("PORT_UNUSED"),
.port_phasedone("PORT_UNUSED"),
.port_phasestep("PORT_UNUSED"),
.port_phaseupdown("PORT_UNUSED"),
.port_pllena("PORT_UNUSED"),
.port_scanaclr("PORT_UNUSED"),
.port_scanclk("PORT_UNUSED"),
.port_scanclkena("PORT_UNUSED"),
.port_scandata("PORT_UNUSED"),
.port_scandataout("PORT_UNUSED"),
.port_scandone("PORT_UNUSED"),
.port_scanread("PORT_UNUSED"),
.port_scanwrite("PORT_UNUSED"),
.port_clk0("PORT_USED"),
.port_clk1("PORT_USED"),
.port_clk2("PORT_UNUSED"),
.port_clk3("PORT_UNUSED"),
.port_clk4("PORT_UNUSED"),
.port_clk5("PORT_UNUSED"),
.port_clkena0("PORT_UNUSED"),
.port_clkena1("PORT_UNUSED"),
.port_clkena2("PORT_UNUSED"),
.port_clkena3("PORT_UNUSED"),
.port_clkena4("PORT_UNUSED"),
.port_clkena5("PORT_UNUSED"),
.port_extclk0("PORT_UNUSED"),
.port_extclk1("PORT_UNUSED"),
.port_extclk2("PORT_UNUSED"),
.port_extclk3("PORT_UNUSED"),
.self_reset_on_loss_lock("ON"),
.width_clock(5)
)
altpll_component (
.areset(pll_rst),
.inclk({1'b0, enet_clk_125m}),
.clk({clk90_int, clk_int}),
.locked(pll_locked),
.activeclock(),
.clkbad(),
.clkena({6{1'b1}}),
.clkloss(),
.clkswitch(1'b0),
.configupdate(1'b0),
.enable0(),
.enable1(),
.extclk(),
.extclkena({4{1'b1}}),
.fbin(1'b1),
.fbmimicbidir(),
.fbout(),
.fref(),
.icdrclk(),
.pfdena(1'b1),
.phasecounterselect({4{1'b1}}),
.phasedone(),
.phasestep(1'b1),
.phaseupdown(1'b1),
.pllena(1'b1),
.scanaclr(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0),
.scandataout(),
.scandone(),
.scanread(1'b0),
.scanwrite(1'b0),
.sclkout0(),
.sclkout1(),
.vcooverrange(),
.vcounderrange()
);
sync_reset #(
.N(4)
)
sync_reset_inst (
.clk(clk_int),
.rst(~pll_locked),
.out(rst_int)
);
// GPIO
wire [3:0] btn_int;
wire [2:0] sw_int;
wire [3:0] led_int;
debounce_switch #(
.WIDTH(7),
.N(4),
.RATE(125000)
)
debounce_switch_inst (
.clk(clk_int),
.rst(rst_int),
.in({user_pb,
user_dip}),
.out({btn_int,
sw_int})
);
assign user_led = ~led_int;
fpga_core #(
.TARGET("ALTERA")
)
core_inst (
/*
* Clock: 125MHz
* Synchronous reset
*/
.clk(clk_int),
.clk90(clk90_int),
.rst(rst_int),
/*
* GPIO
*/
.btn(btn_int),
.sw(sw_int),
.led(led_int),
/*
* Ethernet: 1000BASE-T RGMII
*/
.phy_rx_clk(enet_rx_clk),
.phy_rxd(enet_rx_d),
.phy_rx_ctl(enet_rx_dv),
.phy_tx_clk(enet_tx_clk),
.phy_txd(enet_tx_d),
.phy_tx_ctl(enet_tx_en),
.phy_reset_n(enet_resetn),
.phy_int_n(enet_int)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long N = 4e5 + 5; pair<long long, long long> arr[N]; long long l[N]; long long s[N]; long long dp[N]; long long bit[N]; long long n; void update(long long idx, long long val) { while (idx <= n) { bit[idx] = max(bit[idx], val); idx += idx & -idx; } } long long query(long long idx) { long long res = 0; while (idx) { res = max(res, bit[idx]); idx -= idx & -idx; } return res; } int main() { scanf( %lld , &n); for (long long i = 1; i <= n; i++) { long long r, h; scanf( %lld%lld , &r, &h); arr[i] = pair<long long, long long>(r * r * h, -i); } sort(arr + 1, arr + n + 1); for (long long i = 1; i <= n; i++) { dp[i] = max(arr[i].first, query(-arr[i].second) + arr[i].first); update(-arr[i].second, dp[i]); } printf( %.7lf n , 3.14159265358979323846 * query(n)); return 0; } |
//======================================================================
//
// coretest_bp_entropy.v
// ---------------------
// Top level module for the BP FPGA entropy source tester.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014 Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module coretest_bp_entropy(
input wire clk,
input wire reset_n,
// External interface.
input wire rxd,
output wire txd,
output wire [7 : 0] debug
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter UART_ADDR_PREFIX = 8'h00;
parameter ENT_ADDR_PREFIX = 8'h10;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
// Coretest connections.
wire coretest_reset_n;
wire coretest_cs;
wire coretest_we;
wire [15 : 0] coretest_address;
wire [31 : 0] coretest_write_data;
reg [31 : 0] coretest_read_data;
reg coretest_error;
// uart connections
wire uart_rxd_syn;
wire [7 : 0] uart_rxd_data;
wire uart_rxd_ack;
wire uart_txd_syn;
wire [7 : 0] uart_txd_data;
wire uart_txd_ack;
reg uart_cs;
reg uart_we;
reg [7 : 0] uart_address;
reg [31 : 0] uart_write_data;
wire [31 : 0] uart_read_data;
wire uart_error;
wire [7 : 0] uart_debug;
reg ent_cs;
reg ent_we;
reg [7 : 0] ent_address;
reg [31 : 0] ent_write_data;
wire [31 : 0] ent_read_data;
wire [7 : 0] ent_debug;
//----------------------------------------------------------------
// Concurrent assignment.
//----------------------------------------------------------------
assign debug = ent_debug;
//----------------------------------------------------------------
// Core instantiations.
//----------------------------------------------------------------
coretest coretest(
.clk(clk),
.reset_n(reset_n),
.rx_syn(uart_rxd_syn),
.rx_data(uart_rxd_data),
.rx_ack(uart_rxd_ack),
.tx_syn(uart_txd_syn),
.tx_data(uart_txd_data),
.tx_ack(uart_txd_ack),
// Interface to the core being tested.
.core_reset_n(coretest_reset_n),
.core_cs(coretest_cs),
.core_we(coretest_we),
.core_address(coretest_address),
.core_write_data(coretest_write_data),
.core_read_data(coretest_read_data),
.core_error(coretest_error)
);
uart uart(
.clk(clk),
.reset_n(reset_n),
.rxd(rxd),
.txd(txd),
.rxd_syn(uart_rxd_syn),
.rxd_data(uart_rxd_data),
.rxd_ack(uart_rxd_ack),
.txd_syn(uart_txd_syn),
.txd_data(uart_txd_data),
.txd_ack(uart_txd_ack),
.cs(uart_cs),
.we(uart_we),
.address(uart_address),
.write_data(uart_write_data),
.read_data(uart_read_data),
.error(uart_error),
.debug(uart_debug)
);
entropy entropy(.clk(clk),
.nreset(reset_n),
.cs(ent_cs),
.we(ent_we),
.addr(ent_address),
.dwrite(ent_write_data),
.dread(ent_read_data),
.debug(ent_debug)
);
//----------------------------------------------------------------
// address_mux
//
// Combinational data mux that handles addressing between
// cores using the 32-bit memory like interface.
//----------------------------------------------------------------
always @*
begin : address_mux
// Default assignments.
coretest_read_data = 32'h00000000;
coretest_error = 0;
uart_cs = 0;
uart_we = 0;
uart_address = 8'h00;
uart_write_data = 32'h00000000;
ent_cs = 0;
ent_we = 0;
ent_address = 8'h00;
ent_write_data = 32'h00000000;
case (coretest_address[15 : 8])
UART_ADDR_PREFIX:
begin
uart_cs = coretest_cs;
uart_we = coretest_we;
uart_address = coretest_address[7 : 0];
uart_write_data = coretest_write_data;
coretest_read_data = uart_read_data;
coretest_error = uart_error;
end
ENT_ADDR_PREFIX:
begin
ent_cs = coretest_cs;
ent_we = coretest_we;
ent_address = coretest_address[7 : 0];
ent_write_data = coretest_write_data[15 : 0];
coretest_read_data = ent_read_data;
coretest_error = 1'b0;
end
default:
begin
end
endcase // case (coretest_address[15 : 8])
end // address_mux
endmodule // coretest_bp_entropy
//======================================================================
// EOF coretest_bp_entropy.v
//======================================================================
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O22A_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__O22A_BEHAVIORAL_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__o22a (
X ,
A1,
A2,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X, or0_out, or1_out);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O22A_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; bool compare(pair<int, int> a, pair<int, int> b) { return a.first < b.first; } int main() { float r1, r2, c1, c2, d1, d2; cin >> r1 >> r2 >> c1 >> c2 >> d1 >> d2; float a = c1 / 2 + (d1 + r1 - d2 - r2) / 4; float c = c1 / 2 - (d1 + r1 - d2 - r2) / 4; float b = c2 / 2 + (r1 + d2 - r2 - d1) / 4; float d = c2 / 2 - (r1 + d2 - r2 - d1) / 4; if (a > 9 || a < 1) { cout << -1; return 0; } if (b > 9 || b < 1) { cout << -1; return 0; } if (c > 9 || c < 1) { cout << -1; return 0; } if (d > 9 || d < 1) { cout << -1; return 0; } if (a + b != r1) { cout << -1; return 0; } if (d + c != r2) { cout << -1; return 0; } if (a + c != c1) { cout << -1; return 0; } if (d + b != c2) { cout << -1; return 0; } if (a + d != d1) { cout << -1; return 0; } if (c + b != d2) { cout << -1; return 0; } if (a == b || a == c || a == d || b == c || b == d || c == d) { cout << -1; return 0; } cout << (int)a << << (int)b << endl << (int)c << << (int)d; return 0; } |
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