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#include <bits/stdc++.h> using namespace std; int n, ys, ans; int main() { cin >> n; ys = 0; ans = 0; for (int i = n; i > 0; i /= 8) { ys = i % 8; if (ys == 1) ans++; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 500000; const long long minx = -0x5fffffffffffffff; struct nn { long long x, y; nn() { y = minx; } }; int n, u, v; nn num[N]; vector<int> node[N]; long long dfs(int f, int x) { for (int i = 0; i < node[x].size(); i++) { if (node[x][i] == f) continue; long long r = dfs(x, node[x][i]); num[x].y += r; } return num[x].y; } long long dfs1(int f, int x, long long &ans) { long long m1 = minx; long long m2 = minx; for (int i = 0; i < node[x].size(); i++) { if (node[x][i] == f) continue; long long r = dfs1(x, node[x][i], ans); if (m1 < r) { m2 = m1; m1 = r; } else if (m2 < r) { m2 = r; } } if (m2 != minx) { if (ans < m1 + m2) ans = m1 + m2; } return m1 > num[x].y ? m1 : num[x].y; } int main() { long long ans; while (scanf( %d , &n) != EOF) { ans = minx; for (int i = 0; i < N; i++) node[i].clear(); for (int i = 1; i <= n; i++) { scanf( %lld , &num[i].x); num[i].y = num[i].x; } for (int i = 0; i < n - 1; i++) { scanf( %d%d , &u, &v); node[u].push_back(v); node[v].push_back(u); } dfs(0, 1); dfs1(0, 1, ans); if (ans != minx) printf( %lld n , ans); else printf( Impossible n ); } return 0; } |
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_altdqdqs (
core_clock_in,
reset_n_core_clock_in,
fr_clock_in,
hr_clock_in,
write_strobe_clock_in,
write_strobe,
strobe_ena_hr_clock_in,
capture_strobe_tracking,
read_write_data_io,
write_oe_in,
strobe_io,
output_strobe_ena,
strobe_n_io,
oct_ena_in,
read_data_out,
capture_strobe_out,
write_data_in,
extra_write_data_in,
extra_write_data_out,
parallelterminationcontrol_in,
seriesterminationcontrol_in,
config_data_in,
config_update,
config_dqs_ena,
config_io_ena,
config_extra_io_ena,
config_dqs_io_ena,
config_clock_in,
lfifo_rdata_en,
lfifo_rdata_en_full,
lfifo_rd_latency,
lfifo_reset_n,
lfifo_rdata_valid,
vfifo_qvld,
vfifo_inc_wr_ptr,
vfifo_reset_n,
rfifo_reset_n,
dll_delayctrl_in
);
input [7-1:0] dll_delayctrl_in;
input core_clock_in;
input reset_n_core_clock_in;
input fr_clock_in;
input hr_clock_in;
input write_strobe_clock_in;
input [3:0] write_strobe;
input strobe_ena_hr_clock_in;
output capture_strobe_tracking;
inout [8-1:0] read_write_data_io;
input [2*8-1:0] write_oe_in;
inout strobe_io;
input [2-1:0] output_strobe_ena;
inout strobe_n_io;
input [2-1:0] oct_ena_in;
output [2 * 2 * 8-1:0] read_data_out;
output capture_strobe_out;
input [2 * 2 * 8-1:0] write_data_in;
input [2 * 2 * 1-1:0] extra_write_data_in;
output [1-1:0] extra_write_data_out;
input [16-1:0] parallelterminationcontrol_in;
input [16-1:0] seriesterminationcontrol_in;
input config_data_in;
input config_update;
input config_dqs_ena;
input [8-1:0] config_io_ena;
input [1-1:0] config_extra_io_ena;
input config_dqs_io_ena;
input config_clock_in;
input [2-1:0] lfifo_rdata_en;
input [2-1:0] lfifo_rdata_en_full;
input [4:0] lfifo_rd_latency;
input lfifo_reset_n;
output lfifo_rdata_valid;
input [2-1:0] vfifo_qvld;
input [2-1:0] vfifo_inc_wr_ptr;
input vfifo_reset_n;
input rfifo_reset_n;
parameter ALTERA_ALTDQ_DQS2_FAST_SIM_MODEL = "";
altdq_dqs2_acv_connect_to_hard_phy_cyclonev altdq_dqs2_inst (
.core_clock_in( core_clock_in),
.reset_n_core_clock_in (reset_n_core_clock_in),
.fr_clock_in( fr_clock_in),
.hr_clock_in( hr_clock_in),
.write_strobe_clock_in (write_strobe_clock_in),
.write_strobe(write_strobe),
.strobe_ena_hr_clock_in( strobe_ena_hr_clock_in),
.capture_strobe_tracking (capture_strobe_tracking),
.read_write_data_io( read_write_data_io),
.write_oe_in( write_oe_in),
.strobe_io( strobe_io),
.output_strobe_ena( output_strobe_ena),
.strobe_n_io( strobe_n_io),
.oct_ena_in( oct_ena_in),
.read_data_out( read_data_out),
.capture_strobe_out( capture_strobe_out),
.write_data_in( write_data_in),
.extra_write_data_in( extra_write_data_in),
.extra_write_data_out( extra_write_data_out),
.parallelterminationcontrol_in( parallelterminationcontrol_in),
.seriesterminationcontrol_in( seriesterminationcontrol_in),
.config_data_in( config_data_in),
.config_update( config_update),
.config_dqs_ena( config_dqs_ena),
.config_io_ena( config_io_ena),
.config_extra_io_ena( config_extra_io_ena),
.config_dqs_io_ena( config_dqs_io_ena),
.config_clock_in( config_clock_in),
.lfifo_rdata_en(lfifo_rdata_en),
.lfifo_rdata_en_full(lfifo_rdata_en_full),
.lfifo_rd_latency(lfifo_rd_latency),
.lfifo_reset_n(lfifo_reset_n),
.lfifo_rdata_valid(lfifo_rdata_valid),
.vfifo_qvld(vfifo_qvld),
.vfifo_inc_wr_ptr(vfifo_inc_wr_ptr),
.vfifo_reset_n(vfifo_reset_n),
.rfifo_reset_n(rfifo_reset_n),
.dll_delayctrl_in(dll_delayctrl_in)
);
defparam altdq_dqs2_inst.PIN_WIDTH = 8;
defparam altdq_dqs2_inst.PIN_TYPE = "bidir";
defparam altdq_dqs2_inst.USE_INPUT_PHASE_ALIGNMENT = "false";
defparam altdq_dqs2_inst.USE_OUTPUT_PHASE_ALIGNMENT = "false";
defparam altdq_dqs2_inst.USE_LDC_AS_LOW_SKEW_CLOCK = "false";
defparam altdq_dqs2_inst.USE_HALF_RATE_INPUT = "false";
defparam altdq_dqs2_inst.USE_HALF_RATE_OUTPUT = "true";
defparam altdq_dqs2_inst.DIFFERENTIAL_CAPTURE_STROBE = "true";
defparam altdq_dqs2_inst.SEPARATE_CAPTURE_STROBE = "false";
defparam altdq_dqs2_inst.INPUT_FREQ = 400.0;
defparam altdq_dqs2_inst.INPUT_FREQ_PS = "2500 ps";
defparam altdq_dqs2_inst.DELAY_CHAIN_BUFFER_MODE = "high";
defparam altdq_dqs2_inst.DQS_PHASE_SETTING = 0;
defparam altdq_dqs2_inst.DQS_PHASE_SHIFT = 0;
defparam altdq_dqs2_inst.DQS_ENABLE_PHASE_SETTING = 3;
defparam altdq_dqs2_inst.USE_DYNAMIC_CONFIG = "true";
defparam altdq_dqs2_inst.INVERT_CAPTURE_STROBE = "true";
defparam altdq_dqs2_inst.SWAP_CAPTURE_STROBE_POLARITY = "false";
defparam altdq_dqs2_inst.USE_TERMINATION_CONTROL = "true";
defparam altdq_dqs2_inst.USE_DQS_ENABLE = "true";
defparam altdq_dqs2_inst.USE_OUTPUT_STROBE = "true";
defparam altdq_dqs2_inst.USE_OUTPUT_STROBE_RESET = "false";
defparam altdq_dqs2_inst.DIFFERENTIAL_OUTPUT_STROBE = "true";
defparam altdq_dqs2_inst.USE_BIDIR_STROBE = "true";
defparam altdq_dqs2_inst.REVERSE_READ_WORDS = "false";
defparam altdq_dqs2_inst.EXTRA_OUTPUT_WIDTH = 1;
defparam altdq_dqs2_inst.DYNAMIC_MODE = "dynamic";
defparam altdq_dqs2_inst.OCT_SERIES_TERM_CONTROL_WIDTH = 16;
defparam altdq_dqs2_inst.OCT_PARALLEL_TERM_CONTROL_WIDTH = 16;
defparam altdq_dqs2_inst.DLL_WIDTH = 7;
defparam altdq_dqs2_inst.USE_DATA_OE_FOR_OCT = "false";
defparam altdq_dqs2_inst.DQS_ENABLE_WIDTH = 1;
defparam altdq_dqs2_inst.USE_OCT_ENA_IN_FOR_OCT = "true";
defparam altdq_dqs2_inst.PREAMBLE_TYPE = "high";
defparam altdq_dqs2_inst.EMIF_UNALIGNED_PREAMBLE_SUPPORT = "false";
defparam altdq_dqs2_inst.EMIF_BYPASS_OCT_DDIO = "true";
defparam altdq_dqs2_inst.USE_OFFSET_CTRL = "false";
defparam altdq_dqs2_inst.HR_DDIO_OUT_HAS_THREE_REGS = "false";
defparam altdq_dqs2_inst.DQS_ENABLE_PHASECTRL = "true";
defparam altdq_dqs2_inst.USE_2X_FF = "false";
defparam altdq_dqs2_inst.DLL_USE_2X_CLK = "false";
defparam altdq_dqs2_inst.USE_DQS_TRACKING = "true";
defparam altdq_dqs2_inst.USE_HARD_FIFOS = "true";
defparam altdq_dqs2_inst.USE_DQSIN_FOR_VFIFO_READ = "false";
defparam altdq_dqs2_inst.CALIBRATION_SUPPORT = "false";
defparam altdq_dqs2_inst.NATURAL_ALIGNMENT = "true";
defparam altdq_dqs2_inst.SEPERATE_LDC_FOR_WRITE_STROBE = "false";
defparam altdq_dqs2_inst.HHP_HPS = "true";
endmodule
|
/*
* Copyright (C) 2011 Kiel Friedt
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
//authors Kiel Friedt, Kevin McIntosh,Cody DeHaan
module lookahead(c_in, c_out, c, p, g, P, G);
input [3:0] p, g;
input c_in;
output [2:0] c;
output c_out;
output P, G;
assign c[0] = g[0] | (p[0] & c_in);
assign c[1] = g[1] | (g[0] & p[1]) | (p[1] & p[0] & c_in);
assign c[2] = g[2] | (g[1] & p[2]) | (g[0] & p[1] & p[2]) | (p[2] & p[1] & p[0] & c_in);
assign c_out = g[3] | (g[2] & p[3]) | (g[1] & p[2] & p[3]) | (g[0] & p[1] & p[2] & p[3]) | (p[3] & p[2] & p[1] & p[0] & c_in);
assign G = g[3] | (g[2] & p[3]) | (g[1] & p[2] & p[3]) | (p[3] & p[2] & p[1] & g[0]);
assign P = p[3] & p[2] & p[1] & p[0];
endmodule |
#include <bits/stdc++.h> using namespace std; void task(); int main() { srand(time(0)); task(); return 0; } const int INF = 0x3f3f3f3f; const int N = 1e6 + 10; const int M = 1e7 + 100; const int OLOLO = 0xFFFFFFFF; int n, k; long long int cnt[N]; set<int> vals; long long int ans; vector<int> masks; void task() { cin >> n >> k; for (int i = 0; i < n; ++i) { int a; cin >> a; ++cnt[a]; vals.insert(a); } for (int i = 0; i < (1 << 14); ++i) { if (__builtin_popcount(i) == k) { masks.push_back(i); } } for (int val : vals) { for (int mask : masks) { int result = val & (mask ^ OLOLO); result |= (val ^ OLOLO) & mask; if (result < N) { if (val == result) { ans += cnt[val] * (cnt[val] - 1); } else { ans += cnt[val] * cnt[result]; } } } } cout << ans / 2; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; cout << 6 * n * (n - 1) + 1; return 0; } |
#include <bits/stdc++.h> using namespace std; int k, n, maxb, t; int b[100010], flag[100010]; int main() { ios::sync_with_stdio(false); cin >> k >> n >> maxb >> t; t = min(t, min(n, maxb)); for (int ti = 1; ti <= k; ti++) { for (int i = 1; i <= n; i++) cin >> b[i]; for (int i = 0; i <= maxb; i++) flag[i] = 0; for (int i = 1; i <= t; i++) for (int j = 1; j <= n; j++) for (int k = b[j]; k <= maxb && flag[k] == flag[b[j] - 1]; k++) flag[k]++; cout << flag[maxb] << endl; } return 0; } |
/*
* integer3gt - a verilog test for integer greater-than conditional >
*
* Copyright (C) 1999 Stephen G. Tell
* Portions inspired by qmark.v by Steven Wilson ()
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this software; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 59 Temple Place, Suite 330,
* Boston, MA 02111-1307 USA
*/
module integer3gt;
integer a;
integer b;
reg error;
initial begin
error = 0;
a = 1;
if(a > 2) begin
$display("FAILED 1 > 2");
error = 1;
end // if (a < 2)
a = 2;
if(a > 2) begin
$display("FAILED 2 > 2");
error = 1;
end
a = 3;
if(a > 2) begin
b = 1;
end else begin
$display("FAILED 3 > 2");
error = 1;
end
b = 0;
for(a = 10; a > 5; a = a - 1) begin
b = b + a;
end
if(b != 40) begin
$display("FAILED forloop b=%d expected 40", b);
error = 1;
end
if(error == 0)
$display("PASSED");
$finish;
end // initial begin
endmodule
|
#include <bits/stdc++.h> using namespace std; using ull = unsigned long long; using ll = long long; const int mod = 1e9 + 7; const int inf = 2e9 + 5; const int N = 501; int n, m, a[N][N], b[N]; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); cin >> n >> m; int q; cin >> q; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) cin >> a[i][j]; for (int i = 0; i < n; i++) { int cur = 0, best = 0; for (int j = 0; j < m; j++) { if (a[i][j] == 1) cur += 1; else cur = 0; best = max(best, cur); } b[i] = best; } while (q--) { int i, j; cin >> i >> j; --i; --j; a[i][j] = 1 - a[i][j]; int cur = 0, best = 0; for (int k = 0; k < m; k++) { if (a[i][k] == 1) cur += 1; else cur = 0; best = max(best, cur); } b[i] = best; cout << *max_element(b, b + n) << n ; } return 0; } |
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_atomics
(
clock, resetn,
// arbitration port
mem_arb_read,
mem_arb_write,
mem_arb_burstcount,
mem_arb_address,
mem_arb_writedata,
mem_arb_byteenable,
mem_arb_waitrequest,
mem_arb_readdata,
mem_arb_readdatavalid,
mem_arb_writeack,
// Avalon port
mem_avm_read,
mem_avm_write,
mem_avm_burstcount,
mem_avm_address,
mem_avm_writedata,
mem_avm_byteenable,
mem_avm_waitrequest,
mem_avm_readdata,
mem_avm_readdatavalid,
mem_avm_writeack
);
/*************
* Parameters *
*************/
// default parameters if host does not specify them
parameter ADDR_WIDTH=27; // Address width
parameter DATA_WIDTH=256; // Data width
parameter BURST_WIDTH=6;
parameter BYTEEN_WIDTH=32;
parameter OPERATION_WIDTH=32; // atomic operations are ALL 32-bit
parameter ATOMIC_OP_WIDTH=5;
parameter LATENCY=4096; // assuming we get a response back in this many cycles
/******************
* Local Variables *
******************/
localparam BYTE_SELECT_BITS=$clog2(OPERATION_WIDTH);
localparam LATENCY_BITS=$clog2(LATENCY);
localparam DATA_WIDTH_BITS=$clog2(DATA_WIDTH);
// these should match ACLIntrinsics::ID enum in ACLIntrinsics.h
localparam a_ADD=0;
localparam a_SUB=1;
localparam a_XCHG=2;
localparam a_INC=3;
localparam a_DEC=4;
localparam a_CMPXCHG=5;
localparam a_MIN=6;
localparam a_MAX=7;
localparam a_AND=8;
localparam a_OR=9;
localparam a_XOR=10;
// atomic operation states
localparam a_IDLE=0;
localparam a_STARTED=1;
localparam a_READCOMPLETE=2;
localparam a_WRITEBACK=3;
/********
* Ports *
********/
// Standard global signals
input logic clock;
input logic resetn;
// Arbitration port
input logic mem_arb_read;
input logic mem_arb_write;
input logic [BURST_WIDTH-1:0] mem_arb_burstcount;
input logic [ADDR_WIDTH-1:0] mem_arb_address;
input logic [DATA_WIDTH-1:0] mem_arb_writedata;
input logic [BYTEEN_WIDTH-1:0] mem_arb_byteenable;
output logic mem_arb_waitrequest;
output logic [DATA_WIDTH-1:0] mem_arb_readdata;
output logic mem_arb_readdatavalid;
output logic mem_arb_writeack;
// Avalon port
output mem_avm_read;
output mem_avm_write;
output [BURST_WIDTH-1:0] mem_avm_burstcount;
output [ADDR_WIDTH-1:0] mem_avm_address;
output [DATA_WIDTH-1:0] mem_avm_writedata;
output [BYTEEN_WIDTH-1:0] mem_avm_byteenable;
input mem_avm_waitrequest;
input [DATA_WIDTH-1:0] mem_avm_readdata;
input mem_avm_readdatavalid;
input mem_avm_writeack;
/**********
* Signals *
**********/
wire atomic;
reg [OPERATION_WIDTH-1:0] a_operand0;
reg [OPERATION_WIDTH-1:0] a_operand1;
reg [DATA_WIDTH_BITS-1:0] a_segment_address;
reg [ATOMIC_OP_WIDTH-1:0] a_atomic_op;
reg [BURST_WIDTH-1:0] a_burstcount;
reg [7:0] counter;
wire atomic_read_ready; // high when memory is ready to receive to a read request
wire atomic_write_ready; // high when memory is ready to receive to a write request
reg [OPERATION_WIDTH-1:0] a_masked_readdata;
wire [OPERATION_WIDTH-1:0] atomic_add_out;
wire [OPERATION_WIDTH-1:0] atomic_sub_out;
wire [OPERATION_WIDTH-1:0] atomic_xchg_out;
wire [OPERATION_WIDTH-1:0] atomic_inc_out;
wire [OPERATION_WIDTH-1:0] atomic_dec_out;
wire [OPERATION_WIDTH-1:0] atomic_cmpxchg_out;
wire [OPERATION_WIDTH-1:0] atomic_min_out;
wire [OPERATION_WIDTH-1:0] atomic_max_out;
wire [OPERATION_WIDTH-1:0] atomic_and_out;
wire [OPERATION_WIDTH-1:0] atomic_or_out;
wire [OPERATION_WIDTH-1:0] atomic_xor_out;
wire [OPERATION_WIDTH-1:0] atomic_out;
// count responses/requests so we can determine when the atomic load is returned
reg [LATENCY_BITS-1:0] count_requests;
reg [LATENCY_BITS-1:0] count_responses;
reg [LATENCY_BITS-1:0] count_atomic;
wire waiting_atomic_read_response;
wire atomic_read_response;
// keep track of atomic operation state
reg [1:0] atomic_state;
wire atomic_idle;
wire atomic_started;
wire atomic_read_complete;
wire atomic_writeback;
// current atomic operation we are servicing
reg [DATA_WIDTH-1:0] a_writedata;
reg [BYTEEN_WIDTH-1:0] a_byteenable;
reg [ADDR_WIDTH-1:0] a_address;
/************************************
* Read Atomic Inputs, Write Output *
************************************/
always@(posedge clock or negedge resetn)
begin
if ( !resetn ) begin
a_writedata <= {DATA_WIDTH{1'b0}};
a_byteenable <= {BYTEEN_WIDTH{1'b0}};
a_address <= {ADDR_WIDTH{1'b0}};
a_operand0 <= {OPERATION_WIDTH{1'b0}};
a_operand1 <= {OPERATION_WIDTH{1'b0}};
a_segment_address <= {DATA_WIDTH_BITS{1'b0}};
a_atomic_op <= {ATOMIC_OP_WIDTH{1'b0}};
a_burstcount <= {BURST_WIDTH{1'b0}};
end
else if( atomic_read_ready ) begin
a_operand0 <= mem_arb_writedata[32:1];
a_operand1 <= mem_arb_writedata[64:33];
a_atomic_op <= mem_arb_writedata[70:65];
a_segment_address <= ( OPERATION_WIDTH * mem_arb_writedata[75:71]);
a_byteenable <= mem_arb_byteenable;
a_address <= mem_arb_address;
a_burstcount <= mem_arb_burstcount;
end
else if( atomic_read_complete ) begin
a_writedata <= ( atomic_out << a_segment_address );
end
else if( atomic_write_ready ) begin
a_writedata <= {DATA_WIDTH{1'b0}};
end
end
/*******************************
* Extract inputs from writedata *
********************************/
assign atomic = mem_arb_read & mem_arb_writedata[0:0];
/*********************************
* Arbitration/Avalon connections *
*********************************/
// mask the response
assign mem_arb_readdatavalid = mem_avm_readdatavalid;
assign mem_arb_writeack = mem_avm_writeack;
assign mem_arb_readdata = mem_avm_readdata;
// dont send a new read/write if servicing an atomic
assign mem_avm_read = ( mem_arb_read & atomic_idle );
assign mem_avm_write = ( mem_arb_write & atomic_idle ) | atomic_writeback;
assign mem_avm_burstcount = atomic_writeback ? a_burstcount : mem_arb_burstcount;
assign mem_avm_address = atomic_writeback ? a_address : mem_arb_address;
assign mem_avm_writedata = atomic_writeback ? a_writedata : mem_arb_writedata;
assign mem_avm_byteenable = atomic_writeback ? a_byteenable : mem_arb_byteenable;
// stall IC 1. stalled by memory
// 2. when servicing an atomic
assign mem_arb_waitrequest = mem_avm_waitrequest | atomic_started | atomic_read_complete | atomic_writeback;
/****************************************
* Keep track of atomic operation states *
****************************************/
always@(posedge clock or negedge resetn)
begin
if ( !resetn ) begin
atomic_state <= a_IDLE;
end
else begin
if( atomic_idle & atomic_read_ready ) atomic_state <= a_STARTED;
else if( atomic_started & atomic_read_response ) atomic_state <= a_READCOMPLETE;
else if( atomic_read_complete ) atomic_state <= a_WRITEBACK;
else if( atomic_writeback & atomic_write_ready ) atomic_state <= a_IDLE;
end
end
assign atomic_idle = ( atomic_state == a_IDLE );
assign atomic_started = ( atomic_state == a_STARTED );
assign atomic_read_complete = ( atomic_state == a_READCOMPLETE );
assign atomic_writeback = ( atomic_state == a_WRITEBACK );
assign atomic_read_ready = ( atomic & atomic_idle & ~mem_avm_waitrequest );
assign atomic_write_ready = ( atomic_writeback & ~mem_avm_waitrequest );
/****************************
* ALU for atomic operations *
****************************/
// read readdata from memory
always@(posedge clock or negedge resetn)
begin
if ( !resetn ) begin
a_masked_readdata <= {OPERATION_WIDTH{1'bx}};
end
else begin
a_masked_readdata <= mem_avm_readdata[a_segment_address +: OPERATION_WIDTH];
end
end
assign atomic_add_out = a_masked_readdata + a_operand0;
assign atomic_sub_out = a_masked_readdata - a_operand0;
assign atomic_xchg_out = a_operand0;
assign atomic_inc_out = a_masked_readdata + 1;
assign atomic_dec_out = a_masked_readdata - 1;
assign atomic_cmpxchg_out = ( a_masked_readdata == a_operand0 ) ? a_operand1 : a_masked_readdata;
assign atomic_min_out = ( a_masked_readdata < a_operand0 ) ? a_masked_readdata : a_operand0;
assign atomic_max_out = ( a_masked_readdata > a_operand0 ) ? a_masked_readdata : a_operand0;
assign atomic_and_out = ( a_masked_readdata & a_operand0 );
assign atomic_or_out = ( a_masked_readdata | a_operand0 );
assign atomic_xor_out = ( a_masked_readdata ^ a_operand0 );
// select the output based on atomic operation
assign atomic_out =
( a_atomic_op == a_ADD ) ? atomic_add_out :
( a_atomic_op == a_SUB ) ? atomic_sub_out :
( a_atomic_op == a_XCHG ) ? atomic_xchg_out :
( a_atomic_op == a_INC ) ? atomic_inc_out :
( a_atomic_op == a_DEC ) ? atomic_dec_out :
( a_atomic_op == a_CMPXCHG ) ? atomic_cmpxchg_out :
( a_atomic_op == a_MIN ) ? atomic_min_out :
( a_atomic_op == a_MAX ) ? atomic_max_out :
( a_atomic_op == a_AND ) ? atomic_and_out :
( a_atomic_op == a_OR ) ? atomic_or_out :
( a_atomic_op == a_XOR ) ? atomic_xor_out : {OPERATION_WIDTH{1'bx}};
/***********************
* Find atomic response *
***********************/
always@(posedge clock or negedge resetn)
begin
// atomic response, clear counters
if ( !resetn ) begin
count_requests <= { LATENCY_BITS{1'b0} };
count_responses <= { LATENCY_BITS{1'b0} };
count_atomic <= {1'b0};
end
else begin
// new read request
if( mem_avm_read & ~mem_avm_waitrequest ) begin
count_requests <= count_requests + mem_arb_burstcount;
end
// new read response
if( mem_avm_readdatavalid ) begin
count_responses <= count_responses + 1;
end
// new read atomic request
if( atomic_read_ready ) begin
count_atomic <= count_requests;
end
end
end
// we already sent a request for an atomic
// the next response will be for atomic
assign waiting_atomic_read_response = atomic_started & ( count_atomic == count_responses );
assign atomic_read_response = ( waiting_atomic_read_response & mem_avm_readdatavalid );
endmodule
|
// $Id: c_gate_bits.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// generic gate-(op) (i.e., apply binary op to all bits)
//==============================================================================
module c_gate_bits
(select, data_in, data_out);
`include "c_constants.v"
// number of input ports
parameter num_ports = 1;
// width of each port
parameter width = 32;
// operator
parameter op = `BINARY_OP_AND;
// control signal to select active port
input [0:num_ports-1] select;
// vector of inputs
input [0:num_ports*width-1] data_in;
// result
output [0:num_ports*width-1] data_out;
wire [0:num_ports*width-1] data_out;
generate
genvar p;
for(p = 0; p < num_ports; p = p + 1)
begin:ps
c_binary_op
#(.num_ports(2),
.width(width),
.op(op))
bop
(.data_in({{width{select[p]}}, data_in[p*width:(p+1)*width-1]}),
.data_out(data_out[p*width:(p+1)*width-1]));
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; string s; int n; int a[26]; int b[26]; bool flag[26]; bool cmp(int x, int y) { return a[x] < a[y]; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> s >> n; memset(a, 0, sizeof(a)); memset(flag, 1, sizeof(flag)); for (int i = 0; i < s.size(); ++i) { a[s[i] - a ]++; } for (int i = 0; i < 26; ++i) { b[i] = i; } int ans = 26; sort(b, b + 26, cmp); for (int i = 0; i < 26; ++i) { if (a[b[i]] <= n) { flag[b[i]] = 0; n -= a[b[i]]; ans--; } } cout << ans << n ; for (int i = 0; i < s.size(); ++i) { if (flag[s[i] - a ]) cout << s[i]; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A222OI_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__A222OI_PP_BLACKBOX_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a222oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A222OI_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const int MOD = 1e9 + 7; const int maxn = 3e5 + 10; const int maxv = 1e3 + 10; const double eps = 1e-9; std::vector<int> G[maxn]; int ans[maxn]; void inv(int i) { ans[i] ^= 1; } bool bad(int u) { int cnt = 0; for (int i = 0; i < G[u].size(); i++) { cnt += ans[u] == ans[G[u][i]]; } return cnt >= 2; } int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { int u, v; scanf( %d%d , &u, &v); if (u > v) swap(u, v); G[v].push_back(u); G[u].push_back(v); } stack<int> s; for (int i = 1; i <= n; i++) { if (bad(i)) s.push(i); } while (s.size()) { int u = s.top(); s.pop(); if (bad(u)) inv(u); for (int i = 0; i < G[u].size(); i++) { int v = G[u][i]; if (bad(G[u][i])) s.push(v); } } for (int i = 1; i <= n; i++) { printf( %d , ans[i]); } puts( ); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND3_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__AND3_PP_BLACKBOX_V
/**
* and3: 3-input AND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__and3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND3_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n, ans = 1, res = 1, x, mn = 0, mx = 1e9; set<int> S; set<int>::iterator it; char s[10]; int main() { scanf( %d , &n); S.insert(1e9), S.insert(0); for (int i = 1; i <= n; ++i) { scanf( %s%d , s, &x); if (s[1] == D ) S.insert(x), res += (x >= mn && x <= mx) ? 1 : 0; else { if (x < mn || x > mx) ans = 0; if (x != mn && x != mx) ans = 2 * ans % 1000000007; S.erase(x); res = 1; it = S.lower_bound(x); mx = *it; mn = *(--it); } } printf( %d n , 1ll * ans * res % 1000000007); } |
#include <bits/stdc++.h> using namespace std; const int MN = 1e5 + 5; int T, N, arr[MN]; void solve() { scanf( %d , &N); for (int i = 0; i < N; i++) scanf( %d , arr + i); sort(arr, arr + N); printf( %d n , min(min(arr[N - 1], arr[N - 2]) - 1, N - 2)); } int main() { scanf( %d , &T); while (T--) solve(); } |
#include <bits/stdc++.h> int check(int num1, int num2); using namespace std; int main() { int k, l, m, n, d; cin >> k; cin >> l; cin >> m; cin >> n; cin >> d; int total = 0; for (int i = 1; i < d + 1; i++) { if (check(i, k) || check(i, l) || check(i, m) || check(i, n)) { total++; } } cout << total << endl; return 0; } int check(int num1, int num2) { if (num1 % num2 == 0) { return 1; } else { return 0; } } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:41:33 10/30/2014
// Design Name:
// Module Name: UART_loop
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module UART_loop(
input UartRx,
output UartTx,
input clk100,
output [7:0]LED
);
wire [7:0]Rx_D;
reg [7:0]Tx_D;
reg WR = 1'b0;
reg RD = 1'b0;
reg RST = 1'b0;
wire RXNE;
wire TXE;
// Instantiate the module
UART_Rx # (
.CLOCK(100_000_000),
.BAUD_RATE(115200)
)rx_module (
.CLK(clk100),
.D(Rx_D),
.RD(RD),
.RST(RST),
.RX(UartRx),
.RXNE(RXNE)
);
// Instantiate the module
UART_Tx # (
.CLOCK(100_000_000),
.BAUD_RATE(115200)
) tx_module (
.CLK(clk100),
.D(Tx_D),
.WR(WR),
.RST(RST),
.TX(UartTx),
.TXE(TXE)
);
assign LED = Rx_D;
reg tog = 1'b0;
reg prevRXNE = 1'b0;
always @(posedge clk100) begin
if (prevRXNE == 1'b0 && RXNE == 1'b1) begin
RD <= 1'b1;
Tx_D <= Rx_D;
WR <= 1'b1;
tog <= !tog;
end else begin
RD <= 1'b0;
WR <= 1'b0;
end
prevRXNE <= RXNE;
end
endmodule
|
//----------------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact :
//----------------------------------------------------------------------------
// Filename : db_left_ram.v
// Author : chewein
// Created : 2014-04-18
// Description : memory of current lcu left pixels:(16 + 8 + 8 ) * 16 * 8 /2 bits
// Y Cb Cr
//----------------------------------------------------------------------------
module db_left_ram(
clka ,
cena_i ,
rena_i ,
wena_i ,
addra_i ,
dataa_o ,
dataa_i ,
clkb ,
cenb_i ,
renb_i ,
wenb_i ,
addrb_i ,
datab_o ,
datab_i
);
// ********************************************
//
// Parameter DECLARATION
//
// ********************************************
parameter DATA_WIDTH = 128 ;
parameter ADDR_WIDTH = 4 ;
// ********************************************
//
// Input/Output DECLARATION
//
// ********************************************
// A port
input clka ; // clock input
input cena_i ; // chip enable, low active
input rena_i ; // data output enable, low active
input wena_i ; // write enable, low active
input [ADDR_WIDTH-1:0] addra_i; // address input
input [DATA_WIDTH-1:0] dataa_i; // data input
output [DATA_WIDTH-1:0] dataa_o; // data output
// B Port
input clkb ; // clock input
input cenb_i ; // chip enable, low active
input renb_i ; // data output enable, low active
input wenb_i ; // write enable, low active
input [ADDR_WIDTH-1:0] addrb_i; // address input
input [DATA_WIDTH-1:0] datab_i; // data input
output [DATA_WIDTH-1:0] datab_o; // data output
// ********************************************
//
// Register DECLARATION
//
// ********************************************
reg [DATA_WIDTH-1:0] mem_array[(1<<ADDR_WIDTH)-1:0];
// ********************************************
//
// Wire DECLARATION
//
// ********************************************
reg [DATA_WIDTH-1:0] dataa_r;
reg [DATA_WIDTH-1:0] datab_r;
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
// -- A Port --//
always @(posedge clka) begin
if(!cena_i && !wena_i)
mem_array[addra_i] <= dataa_i;
end
always @(posedge clka) begin
if (!cena_i && wena_i)
dataa_r <= mem_array[addra_i];
else
dataa_r <= 'bx;
end
assign dataa_o = rena_i ? 'bz : dataa_r;
// -- B Port --//
always @(posedge clkb) begin
if(!cenb_i && !wenb_i)
mem_array[addrb_i] <= datab_i;
end
always @(posedge clkb) begin
if (!cenb_i && wenb_i)
datab_r <= mem_array[addrb_i];
else
datab_r <= 'bx;
end
assign datab_o = renb_i ? 'bz : datab_r;
endmodule
|
// =============================================================================
// COPYRIGHT NOTICE
// Copyright 2006 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court (other locations)
// Hillsboro, OR 97124 web : http://www.latticesemi.com/
// U.S.A email:
// =============================================================================/
// FILE DETAILS
// Project : LatticeMico32
// File : TYPEA.v
// Description:
// This is one of the two types of cells that are used to create ER1/ER2
// register bits.
// Dependencies : None
// Version : 6.1.17
// The SHIFT_DR_CAPTURE_DR and ENABLE_ER1/2 signals of the
// dedicate logic JTAG_PORT didn't act as what their names implied.
// The SHIFT_DR_CAPTURE_DR actually acts as SHIFT_DR.
// The ENABLE_ER1/2 actually acts as SHIFT_DR_CAPTURE_DR.
// These had caused a lot of headaches for a long time and now they are
// fixed by:
// (1) Use SHIFT_DR_CAPTURE_DR and ENABLE_ER1/2 to create
// CAPTURE_DR for all typeA, typeB bits in the ER1, ER2 registers.
// (2) Use ENABLE_ER1 or the enESR, enCSR, enBAR (these 3 signals
// have the same waveform of ENABLE_ER2) directly to be the CLKEN
// of all typeA, typeB bits in the ER1, ER2 registers.
// (3) Modify typea.vhd to use only UPDATE_DR signal for the clock enable
// of the holding flip-flop.
// These changes caused ispTracy.vhd and cge.dat changes and the new
// CGE.exe version will be 1.3.5.
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// =============================================================================
module TYPEA(
input CLK,
input RESET_N,
input CLKEN,
input TDI,
output TDO,
output reg DATA_OUT,
input DATA_IN,
input CAPTURE_DR,
input UPDATE_DR
);
reg tdoInt;
always @ (negedge CLK or negedge RESET_N)
begin
if (RESET_N == 1'b0)
tdoInt <= 1'b0;
else if (CLK == 1'b0)
if (CLKEN == 1'b1)
if (CAPTURE_DR == 1'b0)
tdoInt <= TDI;
else
tdoInt <= DATA_IN;
end
assign TDO = tdoInt;
always @ (negedge CLK or negedge RESET_N)
begin
if (RESET_N == 1'b0)
DATA_OUT <= 1'b0;
else if (CLK == 1'b0)
if (UPDATE_DR == 1'b1)
DATA_OUT <= tdoInt;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 4002; int n = 0, a; char ch[N]; long long ans = 0, sum[N][N], all; long long d[N * 9]; int val(int ind) { return ch[ind - 1] - 0 ; } int main() { cin >> a; while (cin >> ch[n]) n++; for (int i = 1; i <= n; ++i) { for (int j = i; j <= n; ++j) { sum[i][j] = val(j) + sum[1][j - 1] - sum[1][i - 1]; d[sum[i][j]]++; } } for (int tt = 0; tt <= 4000 * 9; ++tt) all += d[tt]; for (int i = 1; i <= n; ++i) { for (int j = i; j <= n; ++j) { if (sum[i][j] == 0) { if (a == 0) ans += all; continue; } int cur = a / sum[i][j]; if (cur * sum[i][j] == a) { if (cur >= 0 && cur <= 4000 * 9) ans += d[cur]; } } } cout << ans << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2BB2O_TB_V
`define SKY130_FD_SC_LP__A2BB2O_TB_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a2bb2o.v"
module top();
// Inputs are registered
reg A1_N;
reg A2_N;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1_N = 1'bX;
A2_N = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1_N = 1'b0;
#40 A2_N = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1_N = 1'b1;
#200 A2_N = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1_N = 1'b0;
#360 A2_N = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2_N = 1'b1;
#640 A1_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2_N = 1'bx;
#800 A1_N = 1'bx;
end
sky130_fd_sc_lp__a2bb2o dut (.A1_N(A1_N), .A2_N(A2_N), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2BB2O_TB_V
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using pii = pair<int, int>; using pll = pair<ll, ll>; using ld = long double; const int MN = 5e5 + 5, MM = 1e6 + 3; vector<int> bs; struct Lady { int a, b, c; } ladies[MN]; int bit[MN]; int n; void update(int i, int v) { for (i = MN - i; i < MN; i += i & -i) bit[i] = max(bit[i], v); } int query(int i) { int ret = 0; for (i = MN - i; i; i ^= i & -i) ret = max(ret, bit[i]); return ret; } void getb(int &b) { b = lower_bound((bs).begin(), (bs).end(), b) - bs.begin() + 1; } int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &ladies[i].a); for (int i = 1; i <= n; i++) scanf( %d , &ladies[i].b), bs.push_back(ladies[i].b); for (int i = 1; i <= n; i++) scanf( %d , &ladies[i].c); sort((bs).begin(), (bs).end()); for (Lady &l : ladies) getb(l.b); sort(ladies + 1, ladies + 1 + n, [](Lady a, Lady b) { return a.a > b.a; }); vector<Lady> toadd; int ans = 0; for (int i = 1; i <= n; i++) { if (ladies[i].a != ladies[i - 1].a) { for (Lady &l : toadd) update(l.b, l.c); toadd.clear(); } toadd.push_back(ladies[i]); ans += query(ladies[i].b + 1) > ladies[i].c; } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int a[200010], b[200010]; bool used[200010]; int main() { int n, k = 0, i, x; scanf( %d , &n); for (i = 1; i <= n; i++) scanf( %d , &a[i]); for (i = 1; i <= n; i++) scanf( %d , &b[i]); int ans = 1 - accumulate(b + 1, b + n + 1, 0) % 2; for (i = 1; i <= n; i++) if (!used[i]) { used[i] = true; x = a[i]; while (!used[x]) { used[x] = true; x = a[x]; } k++; } if (k > 1) ans += k; printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; inline long long read() { long long x = 0; char ch = getchar(); bool f = 0; for (; !isdigit(ch); ch = getchar()) if (ch == - ) f = 1; for (; isdigit(ch); ch = getchar()) x = x * 10 + ch - 0 ; return f ? -x : x; } void write(long long x) { if (x < 0) putchar( - ), x = -x; if (x >= 10) write(x / 10); putchar(x % 10 + 0 ); } void writeln(long long x) { write(x); puts( ); } void writep(long long x) { write(x); putchar( ); } const int N = 100005; int n, S[N], a[N], top; char s[N]; int main() { scanf( %s , s + 1); n = strlen(s + 1); for (int i = (int)(1); i <= (int)(n); i++) { if (s[i] == + ) a[i] = 1; else a[i] = 0; } for (int i = (int)(1); i <= (int)(n); i++) { S[++top] = a[i]; if (top > 1 && S[top - 1] == a[i]) top -= 2; } if (top) puts( No ); else puts( Yes ); } |
#include <bits/stdc++.h> using namespace std; int pw(int a, int b) { if (b == 0) return 1; if (b == 1) return a; long long rep = pw(a, b / 2), M = 1e9 + 7; if (b % 2 == 0) return (rep * rep) % M; return (((rep * rep) % M) * a) % M; } int main() { int n, k, m; cin >> n >> m >> k; if (k == 1 || k > n) { cout << pw(m, n); return 0; } if (k == n) { cout << pw(m, (n + 1) / 2); return 0; } long long answer = m; if (k % 2 == 1) { answer += m * (m - 1); } cout << answer << endl; } |
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module sirv_pwmgpioport(
input clock,
input reset,
input io_pwm_port_0,
input io_pwm_port_1,
input io_pwm_port_2,
input io_pwm_port_3,
input io_pins_pwm_0_i_ival,
output io_pins_pwm_0_o_oval,
output io_pins_pwm_0_o_oe,
output io_pins_pwm_0_o_ie,
output io_pins_pwm_0_o_pue,
output io_pins_pwm_0_o_ds,
input io_pins_pwm_1_i_ival,
output io_pins_pwm_1_o_oval,
output io_pins_pwm_1_o_oe,
output io_pins_pwm_1_o_ie,
output io_pins_pwm_1_o_pue,
output io_pins_pwm_1_o_ds,
input io_pins_pwm_2_i_ival,
output io_pins_pwm_2_o_oval,
output io_pins_pwm_2_o_oe,
output io_pins_pwm_2_o_ie,
output io_pins_pwm_2_o_pue,
output io_pins_pwm_2_o_ds,
input io_pins_pwm_3_i_ival,
output io_pins_pwm_3_o_oval,
output io_pins_pwm_3_o_oe,
output io_pins_pwm_3_o_ie,
output io_pins_pwm_3_o_pue,
output io_pins_pwm_3_o_ds
);
wire [1:0] T_108;
wire [1:0] T_109;
wire [3:0] T_110;
wire T_114;
wire T_115;
wire T_116;
wire T_117;
assign io_pins_pwm_0_o_oval = T_114;
assign io_pins_pwm_0_o_oe = 1'h1;
assign io_pins_pwm_0_o_ie = 1'h0;
assign io_pins_pwm_0_o_pue = 1'h0;
assign io_pins_pwm_0_o_ds = 1'h0;
assign io_pins_pwm_1_o_oval = T_115;
assign io_pins_pwm_1_o_oe = 1'h1;
assign io_pins_pwm_1_o_ie = 1'h0;
assign io_pins_pwm_1_o_pue = 1'h0;
assign io_pins_pwm_1_o_ds = 1'h0;
assign io_pins_pwm_2_o_oval = T_116;
assign io_pins_pwm_2_o_oe = 1'h1;
assign io_pins_pwm_2_o_ie = 1'h0;
assign io_pins_pwm_2_o_pue = 1'h0;
assign io_pins_pwm_2_o_ds = 1'h0;
assign io_pins_pwm_3_o_oval = T_117;
assign io_pins_pwm_3_o_oe = 1'h1;
assign io_pins_pwm_3_o_ie = 1'h0;
assign io_pins_pwm_3_o_pue = 1'h0;
assign io_pins_pwm_3_o_ds = 1'h0;
assign T_108 = {io_pwm_port_1,io_pwm_port_0};
assign T_109 = {io_pwm_port_3,io_pwm_port_2};
assign T_110 = {T_109,T_108};
assign T_114 = T_110[0];
assign T_115 = T_110[1];
assign T_116 = T_110[2];
assign T_117 = T_110[3];
endmodule
|
#include <bits/stdc++.h> using namespace std; bool vt[202][202]; int cnt, n; int dfs(int x, int y) { int mx1 = 0, mx2 = 0, mx = 0; for (int i = 1; i <= n; i++) if (vt[x][i] && i != y) { mx = max(mx, dfs(i, x)); if (cnt > mx1) mx2 = mx1, mx1 = cnt; else if (cnt > mx2) mx2 = cnt; } mx = max(mx, mx1 + mx2); cnt = mx1 + 1; return mx; } int main() { ios::sync_with_stdio(0); int x, y, m, sm = 0; cin >> n; for (int i = 0; i < n - 1; i++) cin >> x >> y, vt[x][y] = 1, vt[y][x] = 1; int mx = 0; for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) { int l = 0, k = 0; if (vt[i][j]) { l = dfs(i, j); k = dfs(j, i); mx = max(mx, l * k); } } cout << mx; } |
#include <bits/stdc++.h> using namespace std; int main() { int tu[200], a[200]; int f[200]; int n, m, k; int min; int i, j; scanf( %d %d %d , &n, &m, &k); for (i = 0; i < m; i++) { scanf( %d , &f[i]); a[i] = 0; } for (i = 0; i < k; i++) scanf( %d , &tu[i]); for (i = 0; i < m; i++) for (j = 0; j < k; j++) if (tu[j] % f[i] == 0) a[i] += 1; min = 1000; for (i = 0; i < m; i++) { if (min > a[i]) min = a[i]; } j = 0; for (i = 0; i < m; i++) { if (a[i] == min) tu[j++] = i; } for (i = 0; i < j; i++) { for (k = i + 1; k < j; k++) { if (tu[i] > tu[k]) { min = tu[k]; tu[k] = tu[i]; tu[i] = min; } } } printf( %d n , j); for (i = 0; i < j; i++) printf( %d , tu[i] + 1); printf( n ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } int current = 1, maxtotal = 0; for (int i = 0; i < n; i++) { current = 1; for (int j = i; j < n - 1 && a[j] >= a[j + 1]; j++, current++) ; for (int j = i; j > 0 && a[j] >= a[j - 1]; j--, current++) ; if (current > maxtotal) { maxtotal = current; } } cout << maxtotal; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string s, s1; int count1 = 0, count2 = 0; cin >> s >> s1; for (int i = 0; i < s.size(); i++) { if (s[i] != s1[i]) { if (s[i] == 4 ) count1++; else count2++; } } if (count1 <= count2) cout << count2; else cout << count1; cin.get(); return 0; } |
`timescale 1ns / 1ps
module uart_rx(
input CLK,
input RST,
input EN,
input RX,
input ISFULL,
output WRITE,
output [DATAWIDTH - 1 : 0] DATA
);
parameter DATAWIDTH = 8;
parameter IDLE = 4'h0;
parameter START = 4'h1;
parameter BIT_RX = 4'h2;
parameter STOP = 4'h3;
reg write_reg;
reg [DATAWIDTH - 1 : 0] data_reg;
reg [1:0] curr_state;
reg [1:0] next_state;
reg [2:0] bit_cnt;
always @ (posedge CLK) begin
if(RST == 1) begin
curr_state <= IDLE;
next_state <= IDLE;
write_reg <= 1'h0;
data_reg <= 8'h0;
bit_cnt <= 3'h0;
end
else begin
case(curr_state)
IDLE: begin
write_reg <= 1'b0;
bit_cnt <= 3'h0;
if((EN == 1'b1) && (RX == 1'b0) && (ISFULL == 1'b0)) begin
next_state <= BIT_RX;
end
else begin
next_state <= IDLE;
end
end
BIT_RX: begin
data_reg[bit_cnt] <= RX;
write_reg <= 'b0;
if(bit_cnt == 3'h7) begin
bit_cnt <= 8'h0;
next_state <= STOP;
end
else begin
bit_cnt <= bit_cnt + 1'b1;
end
end
STOP: begin
write_reg <= 1'b1;
bit_cnt <= 3'h0;
if(RX <= 1'b1) begin
next_state <= IDLE;
end
else begin
next_state <= BIT_RX;
end
end
default: begin
bit_cnt <= 3'h0;
next_state <= IDLE;
data_reg <= data_reg;
write_reg <= 1'b0;
end
endcase
curr_state <= next_state;
end
end
assign DATA = data_reg;
assign WRITE = write_reg;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n; string s; long long cnt[10]; int main(void) { ios::sync_with_stdio(0); cin.tie(0); cin >> n; cin >> s; for (long long(i) = (0); (i) <= (n - 1); (i)++) cnt[s[i] - 0 ]++; cout << min(n / 11, cnt[8]) << endl; return 0; } |
#include <bits/stdc++.h> int main() { int n; scanf( %d , &n); char arr[n + 1]; scanf( %s , arr); int ans[26]; for (int m = 0; m < 26; m++) ans[m] = 0; for (int j = 0; j < n; j++) { int k = arr[j]; if (k > 64 && k < 91) ans[k - 65] = 1; else ans[k - 97] = 1; } int sum = 0; for (int g = 0; g < 26; g++) sum = sum + ans[g]; if (sum == 26) printf( YES n ); else printf( NO n ); } |
#include <bits/stdc++.h> using namespace std; const long long INF = 1e18; const long long MOD = 1e9 + 7; const long long mod = 998244353; const long long mxN = 1e6; void fileio() {} vector<long long> v[mxN]; vector<long long> vis(mxN); long long nd; void dfs(long long x, long long p) { vis[x] = 1; for (auto i : v[x]) { if (i == p) continue; if (!vis[i]) dfs(i, x); else nd = x; } } void solve() { long long n; cin >> n; vector<long long> a(n); for (long long i = 0; i < n; i++) cin >> a[i]; ; for (long long i = 0; i < n; i++) { v[i + 1].push_back(a[i]); v[a[i]].push_back(i + 1); } vector<long long> v; for (long long i = 1; i < n + 1; i++) { if (vis[i]) continue; nd = i; dfs(i, -1); v.push_back(nd); } long long ans = v.size() - 1; long long root = -1; for (long long i = 0; i < v.size(); i++) { if (a[v[i] - 1] == v[i]) { root = v[i]; break; } } if (root == -1) { ans++; a[v[0] - 1] = v[0]; root = v[0]; } for (long long i = 0; i < v.size(); i++) a[v[i] - 1] = root; cout << ans << n ; for (long long i = 0; i < a.size(); i++) cout << a[i] << ; cout << n ; ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; fileio(); long long tc = 1; while (tc--) solve(); } |
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
// IP Revision: 5
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module ball_pixel (
clka,
wea,
addra,
dina,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [11 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [11 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [11 : 0] douta;
blk_mem_gen_v8_3_5 #(
.C_FAMILY("artix7"),
.C_XDEVICEFAMILY("artix7"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(0),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("ball_pixel.mif"),
.C_INIT_FILE("ball_pixel.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(0),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(12),
.C_READ_WIDTH_A(12),
.C_WRITE_DEPTH_A(3600),
.C_READ_DEPTH_A(3600),
.C_ADDRA_WIDTH(12),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(12),
.C_READ_WIDTH_B(12),
.C_WRITE_DEPTH_B(3600),
.C_READ_DEPTH_B(3600),
.C_ADDRB_WIDTH(12),
.C_HAS_MEM_OUTPUT_REGS_A(1),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_EN_SAFETY_CKT(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("1"),
.C_COUNT_18K_BRAM("1"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 3.822999 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(1'D0),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(12'B0),
.dinb(12'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.rsta_busy(),
.rstb_busy(),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(12'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21O_BEHAVIORAL_V
`define SKY130_FD_SC_HD__A21O_BEHAVIORAL_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a21o (
X ,
A1,
A2,
B1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X, and0_out, B1 );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21O_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; int main(void) { int n, k; cin >> n >> k; int r[257] = {}; for (int i = 0; i < 257; i++) { r[i] = -1; } int p; for (int i = 0; i < n; i++) { cin >> p; if (r[p] == -1) { for (int j = (p - k + 1 >= 0) ? p - k + 1 : 0; j <= p; j++) { if (r[j] == -1) { for (int x = j; x <= p; x++) { if (r[x] != -1) break; r[x] = j; } break; } else if (r[j + 1] == -1 && r[j] + k - 1 >= p) { for (int x = j + 1; x <= p; x++) { r[x] = r[j]; } break; } } } cout << r[p] << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 300020; inline int read() { int s = 0, w = 1; char ch = getchar(); while (ch > 9 || ch < 0 ) { if (ch == - ) w = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) s = s * 10 + ch - 0 , ch = getchar(); return s * w; } int T, n; char x[N]; int main() { T = read(); while (T--) { n = read(); scanf( %s , x); int c1 = 0, c2 = 0, c3 = 0; for (int i = 0; i < n; i++) { if (x[i] == > ) c1++; if (x[i] == < ) c2++; if (x[i] == - || x[(i + 1) % n] == - ) c3++; } if (c1 != 0 && c2 != 0) printf( %d n , c3); else printf( %d n , n); } return 0; } |
/* * Copyright (c) 1999 Daniel Nelsen ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
reg [5:0] a ;
reg error;
// test ?: in continuous assignment with mix of constant
// and non-constant inputs
wire [3:0] val1 = a[4] ? a[3:0] : 4'd0 ;
wire [3:0] val2 = a[4] ? 4'hf : ~a[3:0] ;
initial begin
error = 0;
for (a = 0; a < 32; a=a+1 ) begin
#1 ; // wait for change in a[] to propagate to val
if (( a[4] && (( val1 != a[3:0] ) || ( val2 != 15 ))) ||
( !a[4] && (( val1 != 0 ) || ( val2 != ~a[3:0] ))))
begin
$display( "FAILED a=%b, val1=%b, val2=%b",
a[4:0], val1, val2 );
error = 1;
end
end
if(error == 0)
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1000 * 100 + 3, inf = 1000 * 1000 * 100; int n, m, a[MAXN], b[MAXN], t[MAXN], ans = 0, y, z; int main() { cin >> n >> m >> y >> z; for (int i = 0; i < n; i++) cin >> a[i]; b[0] = -inf; b[m + 1] = inf; for (int i = 1; i <= m; i++) cin >> b[i]; for (int i = 0; i <= m; i++) t[i] = -1; for (int i = 0; i < n; i++) { int ind = lower_bound(b, b + m + 2, a[i]) - b; int nex = b[ind], prev = b[ind - 1]; if (nex - a[i] < a[i] - prev) { if (t[ind] != -1) ans++; t[ind] = nex - a[i]; } else if (nex - a[i] > a[i] - prev) { if (t[ind - 1] != -1 && t[ind - 1] < a[i] - prev) { ans++; } else { if (t[ind - 1] > a[i] - prev) ans++; t[ind - 1] = a[i] - prev; } } else { if (t[ind - 1] == -1 || t[ind - 1] == a[i] - prev) { t[ind - 1] = a[i] - prev; } else { t[ind] = nex - a[i]; } } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; #ifdef LOCAL #define DEBUG(...) debug(#__VA_ARGS__, __VA_ARGS__) #else #define DEBUG(...) 6 #endif template<typename T, typename S> ostream& operator << (ostream &os, const pair<T, S> &p) {return os << ( << p.first << , << p.second << ) ;} template<typename C, typename T = decay<decltype(*begin(declval<C>()))>, typename enable_if<!is_same<C, string>::value>::type* = nullptr> ostream& operator << (ostream &os, const C &c) {bool f = true; os << [ ; for (const auto &x : c) {if (!f) os << , ; f = false; os << x;} return os << ] ;} template<typename T> void debug(string s, T x) {cerr << s << = << x << n ;} template<typename T, typename... Args> void debug(string s, T x, Args... args) {for (int i=0, b=0; i<(int)s.size(); i++) if (s[i] == ( || s[i] == { ) b++; else if (s[i] == ) || s[i] == } ) b--; else if (s[i] == , && b == 0) {cerr << s.substr(0, i) << = << x << | ; debug(s.substr(s.find_first_not_of( , i + 1)), args...); break;}} template<int MOD> struct ModInt { long long v; ModInt(long long _v = 0) {v = (-MOD < _v && _v < MOD) ? _v : _v % MOD; if (v < 0) v += MOD;} ModInt& operator += (const ModInt &other) {v += other.v; if (v >= MOD) v -= MOD; return *this;} ModInt& operator -= (const ModInt &other) {v -= other.v; if (v < 0) v += MOD; return *this;} ModInt& operator *= (const ModInt &other) {v = v * other.v % MOD; return *this;} ModInt& operator /= (const ModInt &other) {return *this *= inverse(other);} bool operator == (const ModInt &other) const {return v == other.v;} bool operator != (const ModInt &other) const {return v != other.v;} friend ModInt operator + (ModInt a, const ModInt &b) {return a += b;} friend ModInt operator - (ModInt a, const ModInt &b) {return a -= b;} friend ModInt operator * (ModInt a, const ModInt &b) {return a *= b;} friend ModInt operator / (ModInt a, const ModInt &b) {return a /= b;} friend ModInt operator - (const ModInt &a) {return 0 - a;} friend ModInt power(ModInt a, long long b) {ModInt ret(1); while (b > 0) {if (b & 1) ret *= a; a *= a; b >>= 1;} return ret;} friend ModInt inverse(ModInt a) {return power(a, MOD - 2);} friend istream& operator >> (istream &is, ModInt &m) {is >> m.v; m.v = (-MOD < m.v && m.v < MOD) ? m.v : m.v % MOD; if (m.v < 0) m.v += MOD; return is;} friend ostream& operator << (ostream &os, const ModInt &m) {return os << m.v;} }; typedef ModInt<998244353> M; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, m; cin >> n >> m; vector<vector<int>> d(n, vector<int>(m)); for (int i=0; i<n; i++) for (int j=0; j<m; j++) cin >> d[i][j]; M fact = 1; for (int i=1; i<=n; i++) fact *= i; M ret = m * fact; for (int j=0; j<m; j++) { vector<int> cnt(n + 1); for (int i=0; i<n; i++) cnt[n - d[i][j] + 1]++; M cur = 1; int tot = 0; for (int i=0; i<n; i++) { tot += cnt[i]; cur *= tot--; } ret -= cur; } cout << ret / fact << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; const ll mod = 1e18 + 7; void solve() { int n, k; cin >> n >> k; string s; cin >> s; for (int i = 0; i < k; i++) { int z = 0, one = 0, j = i + k; for (j; j < n; j += k) { if (s[j] == 1 ) one++; else if (s[j] == 0 ) z++; } if (one > 0 && z > 0) { cout << NO n ; return; } if ((one > 0 && s[i] == 0 ) || (z > 0 && s[i] == 1 )) { cout << NO n ; return; } if (one > 0) { j = i; for (j; j < n; j += k) { s[j] = 1 ; } } else if (z > 0) { j = i; for (j; j < n; j += k) { s[j] = 0 ; } } } int z = 0, one = 0; for (int i = 0; i < k; i++) { if (s[i] == 0 ) z++; else if (s[i] == 1 ) one++; } if (one > k / 2 || z > k / 2) { cout << NO n ; } else cout << YES n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; t = 1; cin >> t; while (t--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long int seg[800005], lazy[800005]; void push(long long int v) { if (lazy[v] == 0) return; seg[2 * v] |= lazy[v]; seg[2 * v + 1] |= lazy[v]; lazy[2 * v] = lazy[v]; lazy[2 * v + 1] = lazy[v]; lazy[v] = 0; return; } void update(long long int v, long long int tl, long long int tr, long long int l, long long int r, long long int val) { if (tl > r || tr < l) return; push(v); if (tl == l && tr == r) { lazy[v] = val; seg[v] = val; return; } else if (tl >= l && tr <= r) { lazy[v] = val; seg[v] |= val; return; } long long int tm = (tl + tr) / 2; update(2 * v, tl, tm, l, r, val); update(2 * v + 1, tm + 1, tr, l, r, val); seg[v] = (seg[2 * v] & seg[2 * v + 1]); return; } long long int query(long long int v, long long int tl, long long int tr, long long int l, long long int r) { if (tl > r || tr < l) return (1LL << 40) - 1; push(v); if (tl >= l && tr <= r) { return seg[v]; } long long int tm = (tl + tr) / 2; return (query(2 * v, tl, tm, l, r) & query(2 * v + 1, tm + 1, tr, l, r)); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int tests = 1; while (tests--) { long long int i, j, n, m; cin >> n >> m; vector<long long int> l(m), r(m), q(m); vector<vector<long long int>> cnt(n + 2, vector<long long int>(31, 0)); for (long long int i = 0; i <= m - 1; i++) { cin >> l[i] >> r[i] >> q[i]; for (long long int j = 0; j <= 30; j++) { if (q[i] & (1 << j)) cnt[l[i]][j]++, cnt[r[i] + 1][j]--; } } for (long long int i = 1; i <= n; i++) { for (long long int j = 0; j <= 30; j++) cnt[i][j] += cnt[i - 1][j]; } for (long long int i = 1; i <= n; i++) { long long int val = 0; for (long long int j = 0; j <= 30; j++) { if (cnt[i][j] > 0) val |= (1 << j); } update(1, 1, n, i, i, val); } bool check = true; for (long long int i = 0; i <= m - 1; i++) { long long int val = query(1, 1, n, l[i], r[i]); if (val != q[i]) { check = false; break; } } if (!check) { cout << NO ; return 0; } cout << YES << n ; for (long long int i = 1; i <= n; i++) { cout << query(1, 1, n, i, i) << ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> v(n); for (int i = 0; i < n; i++) cin >> v[i]; string str; getline(cin, str); bool isok = true; for (int i = 0; i < n; i++) { getline(cin, str); int x = 0; for (int j = 0; j < str.length(); j++) { if (str[j] == a || str[j] == e || str[j] == i || str[j] == o || str[j] == u || str[j] == y ) x++; } if (x != v[i]) { cout << NO << endl; return 0; } } cout << YES << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const double pi = 4 * atan(1); int gcd(int a, int b) { return b == 0 ? a : gcd(b, a % b); } int lcm(int a, int b) { return a / gcd(a, b) * b; } const int LEN = 330; int main() { long long x1, y1, x2, y2; long long n; long long arr[LEN][3]; long long x, y; cin >> x1 >> y1; cin >> x2 >> y2; cin >> n; int ans = 0; for (int i = 0; i < n; i++) cin >> arr[i][0] >> arr[i][1] >> arr[i][2]; for (int i = 0; i < n; i++) { x = arr[i][0] * x1 + arr[i][1] * y1 + arr[i][2]; y = arr[i][0] * x2 + arr[i][1] * y2 + arr[i][2]; if (x > 0 && y < 0 || x < 0 && y > 0) ans++; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2010; char mp[N][N]; int n, m, cnt1, cnt2, in[N][N]; int xx[6] = {0, 0, 1, 0, -1}; int yy[6] = {0, 1, 0, -1, 0}; queue<pair<long long, long long> > q; int main() { int n, m; while (cin >> n >> m) { memset(in, 0, sizeof in); for (int i = 1; i <= n; i++) { scanf( %s , mp[i] + 1); } cnt1 = cnt2 = 0; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) if (mp[i][j] == . ) { cnt1++; for (int k = 1; k <= 4; k++) if (mp[i + xx[k]][j + yy[k]] == . ) in[i][j]++; if (in[i][j] == 1) { q.push(pair<long long, long long>(i, j)); } } } while (!q.empty()) { pair<long long, long long> u = q.front(); q.pop(); int x = u.first, y = u.second, tx, ty, i; for (i = 1; i <= 4; i++) { tx = x + xx[i]; ty = y + yy[i]; if (mp[tx][ty] == . ) { cnt2 += 2; if (i == 1) mp[x][y] = < , mp[tx][ty] = > ; if (i == 2) mp[x][y] = ^ , mp[tx][ty] = v ; if (i == 3) mp[x][y] = > , mp[tx][ty] = < ; if (i == 4) mp[x][y] = v , mp[tx][ty] = ^ ; break; } } if (i == 5) continue; x = tx, y = ty; for (int i = 1; i <= 4; i++) { tx = x + xx[i]; ty = y + yy[i]; if (mp[tx][ty] == . ) { in[tx][ty]--; if (in[tx][ty] == 1) { q.push(pair<long long, long long>(tx, ty)); } } } } if (cnt1 < cnt2) { cout << cnt1 << << cnt2 << endl; for (int i = 1; i <= n; i++) { printf( %s n , mp[i] + 1); } break; } if (cnt1 != cnt2) { printf( Not unique n ); continue; } for (int i = 1; i <= n; i++) { printf( %s n , mp[i] + 1); } } } |
#include <bits/stdc++.h> using namespace std; int main() { float n, k, y, s, per; cin >> n >> k >> y; per = (n * y) / 100; s = per - (int)per; if (s != 0) per = (int)per + 1; if ((per - k) > 0) { cout << per - k; } else { cout << 0 ; } } |
/*****************************************************************************
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2012, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: mig_interface_model
-- File: mig_interface_model.v
-- Author: Fredrik Ringhage - Aeroflex Gaisler AB
--
-- This is a interface model for Xilinx Virtex-7 MIG used on eval board
-- VC707 and KC705.
--
-------------------------------------------------------------------------------
*****************************************************************************/
`timescale 1ps/1ps
module mig_interface_model
(
// user interface signals
input [27:0] app_addr,
input [2:0] app_cmd,
input app_en,
input [511:0] app_wdf_data,
input app_wdf_end,
input [63:0] app_wdf_mask,
input app_wdf_wren,
output wire [511:0] app_rd_data,
output wire app_rd_data_end,
output wire app_rd_data_valid,
output wire app_rdy,
output wire app_wdf_rdy,
output reg ui_clk,
output reg ui_clk_sync_rst,
output reg init_calib_complete,
input sys_rst
);
parameter AddressSize = 28 - 12;
parameter WordSize = 512;
parameter MEM_SIZE = (1<<AddressSize);
reg app_rd_data_end_r;
reg app_rd_data_valid_r;
reg app_rdy_r;
reg app_wdf_rdy_r;
reg app_en_r;
reg app_wdf_wren_r;
reg app_wdf_end_r;
reg [27:0] app_addr_r;
reg [27:0] app_addr_r1;
reg [27:0] app_addr_r2;
reg [511:0] mask;
reg [WordSize-1:0] Mem [0:MEM_SIZE];
integer k;
wire [511:0] app_rd_data_hi_data;
wire [511:0] app_rd_data_hi;
wire [511:0] app_rd_data_lo;
wire test;
assign #100 app_rd_data_end = app_rd_data_end_r;
assign #100 app_rdy = app_rdy_r;
assign #100 app_wdf_rdy = app_wdf_rdy_r;
assign app_rd_data_valid = app_rd_data_valid_r;
// assign app_rd_data_lo = Mem[(app_addr_r >> 4) + 0];
// assign app_rd_data_hi = Mem[(app_addr_r >> 4) + 1];
// assign app_rd_data_hi_data = {app_rd_data_hi[255:0],app_rd_data_lo[511:256]};
// assign test = app_addr_r[3];
// assign #100 app_rd_data = test ? app_rd_data_hi_data : app_rd_data_lo;
assign #100 app_rd_data = Mem[app_addr_r >> 3];
// Clear memory
initial
begin
for (k = 0; k < MEM_SIZE ; k = k + 1)
begin
Mem[k] = 512'd0;
end
end
initial
begin
app_rd_data_valid_r = 1'b0;
app_rd_data_end_r = 1'b0;
app_rdy_r = 1'b1;
app_wdf_rdy_r = 1'b1;
init_calib_complete = 1'b0;
ui_clk_sync_rst = 1'b0;
ui_clk = 1'b0;
end
// Generate clocks
always
begin
forever begin
#5000;
ui_clk = ~ui_clk;
end
end
// Release reset and calibration
initial
begin
#10000;
$display("Reset release of simulation time is %d",$time);
@(posedge ui_clk) ui_clk_sync_rst = 1'b1;
#1000;
$display("Calibration release of simulation time is %d",$time);
@(posedge ui_clk) init_calib_complete = 1'b1;
end
// Write Process
always@(posedge app_wdf_wren)
begin
#100;
for (k = 0; k < 511 ; k = k + 1)
begin
mask[k] = ~ app_wdf_mask[k >> 3];
end
Mem[app_addr >> 3] = (app_wdf_data & mask) | (Mem[app_addr >> 3] & (~ mask) );
#10000;
if (app_wdf_wren) begin
#100;
for (k = 0; k < 512 ; k = k + 1)
begin
mask[k] = ~ app_wdf_mask[k >> 3];
end
Mem[app_addr >> 3] = (app_wdf_data & mask) | (Mem[app_addr >> 3] & (~ mask) );
end
end
// Read Process
always@(posedge app_en)
begin
#100;
if (app_cmd == 3'd1) begin
app_addr_r1 = app_addr;
#10000;
app_addr_r2 = app_addr;
#40000;
app_addr_r = app_addr_r1;
#100;
app_rd_data_valid_r = 1'b1;
#10000;
app_addr_r = app_addr_r2;
#10000;
app_rd_data_valid_r = 1'b0;
#10000;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, k, arr[1005][1005]; void ch_col(int x, int y) { for (int i = 1; i <= n; i++) swap(arr[i][x], arr[i][y]); } void ch_row(int x, int y) { for (int i = 1; i <= m; i++) swap(arr[x][i], arr[y][i]); } int row[1005], col[1005]; int main() { for (int i = 1; i <= 1005; i++) { row[i] = i; col[i] = i; } scanf( %d %d %d , &n, &m, &k); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) scanf( %d , &arr[i][j]); while (k--) { char order; int x, y; scanf( %c %d %d , &order, &x, &y); if (order == g ) printf( %d n , arr[row[x]][col[y]]); if (order == c ) swap(col[x], col[y]); if (order == r ) swap(row[x], row[y]); } return 0; } |
/*mjytxdy!*/ #include <bits/stdc++.h> using namespace std; #define pb push_back #define fi first #define se second #define all(x) x.begin(),x.end() #define SZ(x) ((int)x.size()) #define pii pair<int,int> #define pil pair<int,ll> #define pli pair<ll,int> #define pll pair<ll,ll> #define inl inline #define rep(i,l,r) for(int i=(l);i<=(r);i++) #define per(i,r,l) for(int i=(r);i>=(l);i--) #define trv(i,u) for(int i=head[u];i;i=e[i].next) #define lb(x) ((x)&(-(x))) #define debug(x) cout<<#x : <<x<< n #define myput puts( QaQ ) #define file(x) freopen(#x .in , r ,stdin),freopen(#x .out , w ,stdout); typedef long long ll; template<class T>inl bool ylmin(T &a,T b){return a<b?0:(a=b,1);} template<class T>inl bool ylmax(T &a,T b){return a>b?0:(a=b,1);} template<class T>inl T abs(T x){return x<0?-x:x;} inl char read(){ static const int IO_LEN=1024*1024; static char buf[IO_LEN],*ioh,*iot; if(ioh==iot){ iot=(ioh=buf)+fread(buf,1,IO_LEN,stdin); if(ioh==iot) return -1; } return *ioh++; } template<class T>inl void read(T &x){ static int iosig;static char ioc; for(iosig=0,ioc=read();!isdigit(ioc);ioc=read()) if(ioc== - ) iosig=1; for(x=0;isdigit(ioc);ioc=read())x=(x<<1)+(x<<3)+(ioc^ 0 ); if(iosig) x=-x; } const int MAXN = 1e5 + 10; struct Node{ int x,y; }a[MAXN]; int n,m; vector<int> S,T,Set; map<pii,bool> Map; inl bool cmp(Node a,Node b){ return a.x-a.y>b.x-b.y; } struct Segment{ #define ls rt<<1 #define rs rt<<1|1 pii Min[MAXN<<2]; int tag; inl void pushup(int rt){ Min[rt]=min(Min[ls],Min[rs]); } inl pii query(int rt,int l,int r,int L,int R){ if(L>R) return {2e9,-1}; if(l>=L && r<=R) return Min[rt]; int mid=l+r>>1; if(R<=mid) return query(ls,l,mid,L,R); else if(L>mid) return query(rs,mid+1,r,L,R); else return min(query(ls,l,mid,L,R),query(rs,mid+1,r,L,R)); } inl void update(int rt,int l,int r,int pos) { if(l==r) return Min[rt]={2e9,-1},void(); int mid=l+r>>1; if(pos<=mid) update(ls,l,mid,pos); else update(rs,mid+1,r,pos); pushup(rt); } inl void build(int rt,int l,int r,int opt){ if(l==r) { Min[rt]={opt?a[l].y:a[l].x,l}; return ; } int mid=l+r>>1; build(ls,l,mid,opt),build(rs,mid+1,r,opt); pushup(rt); } #undef ls #undef rs }t[2]; int main(){ //freopen( in.txt , r ,stdin); read(n),read(m); rep(i,1,n) read(a[i].x),read(a[i].y),Map[{a[i].x,a[i].y}]=1; sort(a+1,a+n+1,cmp); per(i,n,1) Set.push_back(a[i].x-a[i].y); t[0].build(1,1,n,0),t[1].build(1,1,n,1); int delta=0;S.push_back(-1),T.push_back(-1); rep(i,1,n) { int pos=n-(lower_bound(all(Set),delta)-Set.begin())+1; pii lans=t[0].query(1,1,n,1,pos-1),rans=t[1].query(1,1,n,pos,n); lans.fi-=t[0].tag,rans.fi-=t[1].tag; pii Min=min(lans,rans); int id=Min.se; if(a[id].x-a[id].y==delta) { if(S.back()!=a[id].x && T.back()!=a[id].y) { t[0].tag++,S.push_back(a[id].x); t[1].tag++,T.push_back(a[id].y); } } else if(a[id].x-a[id].y>delta) { if(S.back()!=a[id].x) delta++,t[0].tag++,S.push_back(a[id].x); } else if(a[id].x-a[id].y<delta) { if(T.back()!=a[id].y) delta--,t[1].tag++,T.push_back(a[id].y); } t[0].update(1,1,n,id);t[1].update(1,1,n,id); } rep(i,1,m) { int x,y; read(x),read(y); if(Map[{x,y}]) {puts( LOSE );continue;} if(binary_search(all(S),x) || binary_search(all(T),y)) {puts( WIN );continue;} x-=lower_bound(all(S),x)-S.begin(); y-=lower_bound(all(T),y)-T.begin(); puts(x==y? LOSE : WIN ); } return 0; } |
#include <bits/stdc++.h> using namespace std; vector<int> a; void SieveOfEratosthenes(int n) { bool prime[n + 1]; memset(prime, true, sizeof(prime)); for (int p = 2; p * p <= n; p++) { if (prime[p] == true) { for (int i = p * p; i <= n; i += p) prime[i] = false; } } for (int p = 2; p <= n; p++) if (prime[p]) a.push_back(p); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; SieveOfEratosthenes(100000); for (int i = 2; i <= n; i++) { for (int j = 0; j < a.size(); j++) { if (i % a[j] == 0) { cout << j + 1 << ; break; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; bool rev[35]; int main() { int n, m; cin >> m >> n; for (int i = 0; i < n; i++) { printf( 1 n ); fflush(stdout); int x; scanf( %d , &x); if (x == 0) return 0; if (x < 0) rev[i] = true; else rev[i] = false; } int l = 1, r = m; for (int i = n; i < 60; i++) { int mid = (l + r) / 2; printf( %d n , mid); fflush(stdout); int x; scanf( %d , &x); if (x == 0) return 0; if (x < 0) { if (rev[i % n]) { l = mid + 1; } else r = mid - 1; } else { if (rev[i % n]) { r = mid - 1; } else l = mid + 1; } } } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:102400000,102400000 ) using namespace std; void makedata() { freopen( input.txt , w , stdout); fclose(stdout); } long long a[250000]; int n, q; template <typename T> class SegmentTree { private: T *data, *lazy; int type; void pushup(int rt) { if (type == 0) data[rt] = data[rt << 1] + data[rt << 1 | 1]; else if (type == 1) data[rt] = max(data[rt << 1], data[rt << 1 | 1]); } void pushdown(int rt, T m) { if (lazy[rt] == 0) return; lazy[rt << 1] += lazy[rt]; lazy[rt << 1 | 1] += lazy[rt]; if (type == 0) { data[rt << 1] += (m - (m >> 1)) * lazy[rt]; data[rt << 1 | 1] += (m >> 1) * lazy[rt]; } else if (type == 1) { data[rt << 1] += lazy[rt]; data[rt << 1 | 1] += lazy[rt]; } lazy[rt] = 0; } public: SegmentTree(int n, int t) : data((T *)malloc((n << 3) * sizeof(T))), lazy((T *)malloc((n << 3) * sizeof(T))), type(t) {} void Build(T *base, int l, int r, int rt) { lazy[rt] = 0; if (l == r) data[rt] = base[l]; else { int mid = (l + r) >> 1; Build(base, l, mid, rt << 1); Build(base, mid + 1, r, rt << 1 | 1); pushup(rt); } } void Modify(int l, int r, int rt, int L, int R, T v) { if (L <= l && R >= r) { lazy[rt] += v; if (type == 0) data[rt] += v * (r - l + 1); else if (type == 1) data[rt] += v; return; } pushdown(rt, r - l + 1); int mid = (l + r) >> 1; if (L <= mid) Modify(l, mid, rt << 1, L, R, v); if (R > mid) Modify(mid + 1, r, rt << 1 | 1, L, R, v); pushup(rt); } T QueryPoint(int l, int r, int rt, int val) { if (l == r) return data[rt]; pushdown(rt, r - l + 1); int mid = (l + r) >> 1; T ret = 0; if (val <= mid) ret = QueryPoint(l, mid, rt << 1, val); else ret = QueryPoint(mid + 1, r, rt << 1 | 1, val); pushup(rt); return ret; } T QuerySegment(int l, int r, int rt, int L, int R) { pushdown(rt, r - l + 1); if (L == l && R == r) return data[rt]; int mid = (l + r) >> 1; if (R <= mid) return QuerySegment(l, mid, rt << 1, L, R); if (mid < L) return QuerySegment(mid + 1, r, rt << 1 | 1, L, R); if (type == 0) return QuerySegment(l, mid, rt << 1, L, mid) + QuerySegment(mid + 1, r, rt << 1 | 1, mid + 1, R); else if (type == 1) return max(QuerySegment(l, mid, rt << 1, L, mid), QuerySegment(mid + 1, r, rt << 1 | 1, mid + 1, R)); } int find(int l, int r, int rt, int p, T x) { if (r <= p) return -1; if (data[rt] < x) return -1; if (l == r) return l; int mid = (l + r) >> 1; if (l > p) { if (data[rt << 1] >= x) return find(l, mid, rt << 1, p, x); else return find(mid + 1, r, rt << 1 | 1, p, x); } int rtn = find(l, mid, rt << 1, p, x); if (rtn != -1) return rtn; return find(mid + 1, r, rt << 1 | 1, p, x); } }; SegmentTree<long long> Tsum(250000, 0), Tmax(250000, 1); int main() { std::ios::sync_with_stdio(0), cin.tie(0); cin >> n >> q; for (int i = 1; i <= n; i++) cin >> a[i]; Tsum.Build(a, 1, n, 1); Tmax.Build(a, 1, n, 1); while (q--) { int p; long long x; cin >> p >> x; Tsum.Modify(1, n, 1, p, p, x - a[p]); Tmax.Modify(1, n, 1, p, p, x - a[p]); a[p] = x; if (a[1] == 0) { cout << 1 << endl; continue; } int m = 1; while (1) { long long sum = Tsum.QuerySegment(1, n, 1, 1, m); int nex = Tmax.find(1, n, 1, m, sum); if (nex == -1) { cout << -1 << endl; break; } if (a[nex] == Tsum.QuerySegment(1, n, 1, 1, nex - 1)) { cout << nex << endl; break; } m = nex; } } return 0; } |
/**
* This is written by Zhiyang Ong
* for EE577b Homework 4, Question 3
*/
// Behavioral model for the SIPO convertor
module SIPO(data_out, out_valid, serial_in, in_valid, reset_b, clk);
// Output signals representing the end of the transaction
// Output of the SIPO convertor
output [7:0] data_out;
/**
* Indicate if the data is valid at data_out
* out_valid = 1 when data is valid; it is ZERO otherwise
*/
output out_valid;
// ===============================================================
// Input signals
// Input data bit coming in to the SIPO convertor
input serial_in;
// Clock signal to facilitate state transitions
input clk;
// Active low reset signal to bring all outputs to ZERO
input reset_b;
/**
* Active high flag to enable data to be loaded at the positive
* edge of the clock
*/
input in_valid;
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg out_valid; // Output signal
reg [7:0] data_out; // Output signal
// Outputs of the D flip-flops in the SIPO converter
reg [7:0] q_dff; // Output of the D flip-flops
// Flag to indicate if the flip-flops have their outputs set
reg flag1; // flag of the 1st D flip-flop
reg flag2; // flag of the 2nd D flip-flop
reg flag3; // flag of the 3rd D flip-flop
reg flag4; // flag of the 4th D flip-flop
reg flag5; // flag of the 5th D flip-flop
reg flag6; // flag of the 6th D flip-flop
reg flag7; // flag of the 7th D flip-flop
reg flag8; // flag of the 8th D flip-flop
// ===============================================================
// Definitions for the states in the SIPO convertor
// parameter PARAM_NAME = VALUE;
// ===============================================================
// Logic for active low reset signal to reset the SIPO convertor
always @(~reset_b)
begin
// When "reset_b" goes low, out_valid=0
out_valid<=1'd0;
// Set the output of the SIPO convertor to ZERO
data_out<=8'd0;
// Set the output of the D flip-flops to ZERO
q_dff<=8'd0;
// Set the flags for the flip-flops to zero
flag1<=1'd1;
flag2<=1'd1;
flag3<=1'd1;
flag4<=1'd1;
flag5<=1'd1;
flag6<=1'd1;
flag7<=1'd1;
flag8<=1'd1;
end
// ===============================================================
// 1st D flip-flop
always @(posedge clk)
begin
// If the load enable flag and reset_b are high,
if(in_valid && reset_b && (~out_valid))
begin
if(flag1==1)
begin
$display($time,"Process input #1",serial_in);
q_dff[0]<=serial_in;
flag1<=1'd0;
end
end
end
// ===============================================================
// 2nd D flip-flop
always @(posedge clk)
begin
// If the load enable flag and reset_b are high,
if(in_valid && reset_b && (~out_valid))
begin
if((flag2==1) && (flag1==0))
begin
$display($time,"Process input #2",serial_in);
q_dff[1]<=serial_in;
flag2<=1'd0;
end
end
end
// ===============================================================
// 3rd D flip-flop
always @(posedge clk)
begin
// If the load enable flag and reset_b are high,
if(in_valid && reset_b && (~out_valid))
begin
if((flag3==1) && (flag2==0))
begin
$display($time,"Process input #3",serial_in);
q_dff[2]<=serial_in;
flag3<=1'd0;
end
end
end
// ===============================================================
// 4th D flip-flop
always @(posedge clk)
begin
// If the load enable flag and reset_b are high,
if(in_valid && reset_b && (~out_valid))
begin
if((flag4==1) && (flag3==0))
begin
$display($time,"Process input #4",serial_in);
q_dff[3]<=serial_in;
flag4<=1'd0;
end
end
end
// ===============================================================
// 5th D flip-flop
always @(posedge clk)
begin
// If the load enable flag and reset_b are high,
if(in_valid && reset_b && (~out_valid))
begin
if((flag5==1) && (flag4==0))
begin
$display($time,"Process input #5",serial_in);
q_dff[4]<=serial_in;
flag5<=1'd0;
end
end
end
// ===============================================================
// 6th D flip-flop
always @(posedge clk)
begin
// If the load enable flag and reset_b are high,
if(in_valid && reset_b && (~out_valid))
begin
if((flag6==1) && (flag5==0))
begin
$display($time,"Process input #6",serial_in);
q_dff[5]<=serial_in;
flag6<=1'd0;
end
end
end
// ===============================================================
// 7th D flip-flop
always @(posedge clk)
begin
// If the load enable flag and reset_b are high,
if(in_valid && reset_b && (~out_valid))
begin
if((flag7==1) && (flag6==0))
begin
$display($time,"Process input #7",serial_in);
q_dff[6]<=serial_in;
flag7<=1'd0;
end
end
end
// ===============================================================
// 8th/Final/Last D flip-flop
always @(posedge clk)
begin
// If the load enable flag and reset_b are high,
if(in_valid && reset_b && (~out_valid))
begin
if((flag8==1) && (flag7==0))
begin
$display($time,"Process input #8",serial_in);
q_dff[7]<=serial_in;
flag8<=1'd0;
out_valid<=1'd1;
end
end
else if(out_valid)
begin
$display($time,"Produce the output and reset data",serial_in);
data_out<=q_dff;
flag1<=1'd1;
flag2<=1'd1;
flag3<=1'd1;
flag4<=1'd1;
flag5<=1'd1;
flag6<=1'd1;
flag7<=1'd1;
flag8<=1'd1;
out_valid<=1'd0;
q_dff<=8'd0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; if ((n - 2) % 3 != 0) cout << 1 << 1 << n - 2; else cout << 1 << 2 << n - 3; } |
#include <bits/stdc++.h> using namespace std; vector<int> Arr; int main() { int N, K; cin >> N >> K; int Num, Acum; int i, j; for (i = 0; i < N; i++) { cin >> Num; Arr.push_back(Num); } sort(Arr.begin(), Arr.end()); j = 0; Acum = 0; for (i = 0; i < K; i++) { if (j >= Arr.size()) { cout << 0 << n ; continue; } Arr[j] -= Acum; cout << Arr[j] << n ; Acum += Arr[j]; Arr[j] = 0; while (Arr[j] <= Acum && j < Arr.size()) j += 1; } } |
#include <bits/stdc++.h> using namespace std; long long N, a[100010], s[100100], cnt[100010]; void update(long long *t, long long pos, long long val) { for (; pos <= N; pos += pos & (-pos)) t[pos] += val; } long long query(long long *t, long long r) { long long res = 0; for (; r > 0; r -= r & (-r)) res += t[r]; return res; } int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> N; int i; long long nr, sum; long double res = 0; for (i = 1; i <= N; i++) { cin >> a[i]; update(cnt, a[i], 1); update(s, a[i], i); } for (i = 1; i <= N; i++) { nr = query(cnt, a[i] - 1); sum = query(s, a[i] - 1); res += nr - (1.0 * i * (nr * (N + 1) - sum)) / (N * (N + 1)); nr = N - i - nr; sum = query(s, N) - sum - i; res += (1.0 * i * (nr * (N + 1) - sum)) / (N * (N + 1)); update(cnt, a[i], -1); update(s, a[i], -i); } cout << fixed << setprecision(15) << res << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; pair<long double, pair<long long, long long> > c[250001]; long double p, q, abcd, ABCD; long long a, b, n, i, x, y; bool comp(pair<long double, pair<long long, long long> > a, pair<long double, pair<long long, long long> > b) { if (a.first < b.first) return 1; if (a.first > b.first) return 0; if (a.second.second < b.second.second) return 1; if (a.second.second == b.second.second && a.second.first < b.second.first) return 1; return 0; } int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> x >> y >> n; abcd = x; ABCD = y; for (i = 1; i <= n; i++) { b = i; a = x * b / y; p = a; q = b; c[i * 2 - 1] = make_pair(abs(abcd / ABCD - p / q), make_pair(a, b)); b = i; a = (x * b + y - 1) / y; p = a; q = b; c[i * 2] = make_pair(abs(abcd / ABCD - p / q), make_pair(a, b)); } sort(c + 1, c + 1 + n * 2, comp); cout << c[1].second.first << / << c[1].second.second << n ; return 0; } |
#include <bits/stdc++.h> #pragma warning(disable : 4996) FILE *in = stdin, *out = stdout; using namespace std; int n, ans[100005], N; int alpha[30]; char a[2005], b[2005], c[2005]; void input() { fscanf(in, %d , &n); fscanf(in, %s , &a[1]); fscanf(in, %s , &b[1]); } int most_fit(int start) { for (int i = (start); i <= (n); i++) if (a[i] == b[start]) return i; return 0; } void method1(int l, int r) { ans[++N] = r; ans[++N] = l; ans[++N] = r; for (int i = (1); i <= (r); i++) c[i] = a[l + i]; int t = l; for (int i = (r + 1); i <= (n); i++) c[i] = a[t--]; for (int i = (1); i <= (n); i++) a[i] = c[i]; } void method2(int A, int B, int C) { ans[++N] = C; ans[++N] = A + B; ans[++N] = C; ans[++N] = A; for (int i = (A + 1); i <= (A + C); i++) c[i] = a[i + B]; int t = A + B; for (int i = (A + C + 1); i <= (n); i++) c[i] = a[t--]; for (int i = (A + 1); i <= (n); i++) a[i] = c[i]; } void pro() { for (int i = (1); i <= (n); i++) alpha[a[i] - a ]++, alpha[b[i] - a ]--; for (int i = (0); i <= (25); i++) if (alpha[i] != 0) { fprintf(out, -1 ); return; } for (int i = (1); i <= (n); i++) { for (int j = (i); j <= (n); j++) { if (a[j] == b[n - i + 1]) { ans[++N] = n; ans[++N] = j - 1; ans[++N] = 1; c[1] = a[j]; for (int k = (2); k <= (j); k++) c[k] = a[k - 1]; int t = n; for (int k = (j + 1); k <= (n); k++) c[k] = a[t--]; for (int k = (1); k <= (n); k++) a[k] = c[k]; break; } } } fprintf(out, %d n , N); for (int i = (1); i <= (N); i++) { fprintf(out, %d , ans[i]); } } int main() { input(); pro(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; const long double PI = 3.141592653589793238462643383279502884197; long long fac[1] = {1}, inv[1] = {1}; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } long long mp(long long a, long long b) { long long ret = 1; while (b) { if (b & 1) ret = ret * a % MOD; a = a * a % MOD; b >>= 1; } return ret; } long long cmb(long long r, long long c) { return (c > r || c < 0) ? 0 : fac[r] * inv[c] % MOD * inv[r - c] % MOD; } pair<int, int> vec[6000]; int cnt[2][2]; int main() { int n; scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d %d , &vec[i].first, &vec[i].second); vec[i].first /= 2; vec[i].second /= 2; vec[i].first %= 2; vec[i].second %= 2; cnt[vec[i].first][vec[i].second]++; } long long ans = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (i == j) continue; int g = 0; if (vec[i].first != vec[j].first) g = 1; if (vec[i].second != vec[j].second) g = 1; for (int q = 0; q < 2; q++) { for (int w = 0; w < 2; w++) { int a = 0, b = 0; if (q != vec[i].first || w != vec[i].second) a = 1; if (q != vec[j].first || w != vec[j].second) b = 1; if ((a ^ b ^ g) == 0) ans += cnt[q][w] - !a - !b; } } } } printf( %lld n , ans / 6); } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
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// contributors may be used to endorse or promote products derived
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// of one or more patent holders. This license does not release you
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// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9434 (
// physical interface
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_or_in_p,
adc_or_in_n,
// delay interface
delay_clk,
// dma interface
adc_clk,
adc_enable,
adc_valid,
adc_data,
adc_dovf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready);
// parameters
localparam SERIES7 = 0;
localparam SERIES6 = 1;
parameter PCORE_ID = 0;
parameter PCORE_DEVTYPE = SERIES7;
parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
// physical interface
input adc_clk_in_p;
input adc_clk_in_n;
input [11:0] adc_data_in_p;
input [11:0] adc_data_in_n;
input adc_or_in_p;
input adc_or_in_n;
// delay interface
input delay_clk;
// dma interface
output adc_clk;
output adc_valid;
output adc_enable;
output [63:0] adc_data;
input adc_dovf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
// internal clocks & resets
wire adc_rst;
wire up_rstn;
wire mmcm_rst;
wire up_clk;
wire adc_clk;
// internal signals
wire up_wreq_s;
wire up_rreq_s;
wire [13:0] up_waddr_s;
wire [13:0] up_raddr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_rdata_s;
wire up_wack_s;
wire up_rack_s;
wire [ 1:0] up_status_pn_err_s;
wire [ 1:0] up_status_pn_oos_s;
wire [ 1:0] up_status_or_s;
wire adc_status_s;
wire [12:0] up_dld_s;
wire [64:0] up_dwdata_s;
wire [64:0] up_drdata_s;
wire delay_clk_s;
wire delay_rst;
wire delay_locked_s;
wire up_drp_sel_s;
wire up_drp_wr_s;
wire [11:0] up_drp_addr_s;
wire [15:0] up_drp_wdata_s;
wire [15:0] up_drp_rdata_s;
wire up_drp_ready_s;
wire up_drp_locked_s;
wire [47:0] adc_data_if_s;
wire adc_or_if_s;
// clock/reset assignments
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// single channel always enable
assign adc_enable = 1'b1;
axi_ad9434_if #(
.PCORE_DEVTYPE(PCORE_DEVTYPE),
.PCORE_IODELAY_GROUP(PCORE_IODELAY_GROUP))
i_if(
.adc_clk_in_p(adc_clk_in_p),
.adc_clk_in_n(adc_clk_in_n),
.adc_data_in_p(adc_data_in_p),
.adc_data_in_n(adc_data_in_n),
.adc_or_in_p(adc_or_in_p),
.adc_or_in_n(adc_or_in_n),
.adc_data(adc_data_if_s),
.adc_or(adc_or_if_s),
.adc_clk(adc_clk),
.adc_rst(adc_rst),
.adc_status(adc_status_s),
.up_clk (up_clk),
.up_adc_dld (up_dld_s),
.up_adc_dwdata (up_dwdata_s),
.up_adc_drdata (up_drdata_s),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s),
.mmcm_rst(mmcm_rst),
.up_rstn(up_rstn),
.up_drp_sel(up_drp_sel_s),
.up_drp_wr(up_drp_wr_s),
.up_drp_addr(up_drp_addr_s),
.up_drp_wdata(up_drp_wdata_s),
.up_drp_rdata(up_drp_rdata_s),
.up_drp_ready(up_drp_ready_s),
.up_drp_locked(up_drp_locked_s));
// common processor control
axi_ad9434_core #(.PCORE_ID(PCORE_ID))
i_core (
.adc_clk(adc_clk),
.adc_data(adc_data_if_s),
.adc_or(adc_or_if_s),
.mmcm_rst (mmcm_rst),
.adc_rst (adc_rst),
.adc_status (adc_status_s),
.dma_dvalid (adc_valid),
.dma_data (adc_data),
.dma_dovf (adc_dovf),
.up_dld (up_dld_s),
.up_dwdata (up_dwdata_s),
.up_drdata (up_drdata_s),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s),
.up_drp_sel (up_drp_sel_s),
.up_drp_wr (up_drp_wr_s),
.up_drp_addr (up_drp_addr_s),
.up_drp_wdata (up_drp_wdata_s),
.up_drp_rdata (up_drp_rdata_s),
.up_drp_ready (up_drp_ready_s),
.up_drp_locked (up_drp_locked_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_rdata_s),
.up_wack (up_wack_s),
.up_raddr (up_raddr_s),
.up_rreq (up_rreq_s),
.up_rack (up_rack_s));
endmodule
|
#include <bits/stdc++.h> using namespace std; using lli = long long int; using pii = pair<int, int>; using vi = vector<int>; using vb = vector<bool>; using vvi = vector<vector<int>>; using vlli = vector<long long int>; using vpii = vector<pair<int, int>>; const int N = 200005; const int blockSize = sqrt(N); lli n, t, l, r, x, idx, L, R, res; vlli a, ans, cnt(1000005); vector<tuple<lli, lli, lli, lli>> q; int get(int idx) { return idx / blockSize; } void add(lli x) { res += x * (2 * (cnt[x]++) + 1); } void del(lli x) { res += x * (-2 * (cnt[x]--) + 1); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> t; a.resize(n); ans.resize(t); for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < t; i++) { cin >> l >> r; l--; r--; q.push_back(make_tuple(get(l), r, l, i)); } sort((q).begin(), (q).end()); L = R = 0; add(a[0]); for (int i = 0; i < t; i++) { tie(ignore, r, l, idx) = q[i]; while (L < l) del(a[L++]); while (L > l) add(a[--L]); while (R < r) add(a[++R]); while (R > r) del(a[R--]); ans[idx] = res; } for (int i = 0; i < t; i++) cout << ans[i] << n ; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 2e6 + 3; long long int x[maxn], y[maxn]; long long int w[maxn]; int ct[maxn]; vector<int> v[maxn]; int ans[maxn]; int done_per[maxn]; int main() { int n, m; cin >> n >> m; for (int i = 0; i < n; ++i) { cin >> w[i]; } memset(ct, 0, sizeof(ct)); for (int i = 0; i < m; ++i) { cin >> x[i] >> y[i]; ct[x[i] - 1]++; ct[y[i] - 1]++; x[i]--; y[i]--; v[x[i]].push_back(i); v[y[i]].push_back(i); } memset(done_per, 0, sizeof(done_per)); vector<int> in; int last = m - 1; for (int i = 0; i < n; i++) { if (ct[i] <= w[i]) { in.push_back(i); } } if (in.size() == 0) { cout << DEAD << n ; exit(0); } while (1) { vector<int> in1; for (int j = 0; j < (int)in.size(); j++) { int t1 = in[j]; for (int i = 0; i < (int)v[t1].size(); i++) { if (!done_per[v[t1][i]]) { ans[last--] = v[t1][i]; done_per[v[t1][i]] = 1; int temp = v[t1][i]; if (x[temp] != t1) { ct[x[temp]]--; if (ct[x[temp]] <= w[x[temp]]) in1.push_back(x[temp]); } else { ct[y[temp]]--; if (ct[y[temp]] <= w[y[temp]]) in1.push_back(y[temp]); } } } } if (last == -1) break; if (in1.size() == 0) { cout << DEAD << n ; exit(0); } in.clear(); for (int t4 : in1) in.push_back(t4); } cout << ALIVE << n ; for (int i = 0; i < m; i++) { cout << ans[i] + 1 << ; } cout << endl; } |
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module conflict_out_fanout (
input wire CLK,
input wire [ 8:0] A,
input wire [ 8:0] B,
output reg [17:0] Z,
output wire [ 8:0] X,
);
wire [17:0] z;
always @(posedge CLK)
Z <= z;
MULT9X9 # (
.REGINPUTA("BYPASS"),
.REGINPUTB("BYPASS"),
.REGOUTPUT("BYPASS")
) mult (
.A (A),
.B (B),
.Z (z)
);
assign X = ~z[8:0];
endmodule
module conflict_out_fanout_to_top (
input wire CLK,
input wire [ 8:0] A,
input wire [ 8:0] B,
output reg [17:0] Z,
output wire [ 8:0] X,
);
wire [17:0] z;
always @(posedge CLK)
Z <= z;
MULT9X9 # (
.REGINPUTA("BYPASS"),
.REGINPUTB("BYPASS"),
.REGOUTPUT("BYPASS")
) mult (
.A (A),
.B (B),
.Z (z)
);
assign X = z[8:0];
endmodule
module conflict_inp_fanout (
input wire CLK,
input wire [ 8:0] A,
input wire [ 8:0] B,
output reg [17:0] Z,
output wire [ 3:0] X,
);
wire [8:0] ra;
always @(posedge CLK)
ra <= A;
MULT9X9 # (
.REGINPUTA("BYPASS"),
.REGINPUTB("BYPASS"),
.REGOUTPUT("BYPASS")
) mult (
.A (ra),
.B (B),
.Z (Z)
);
assign X = ~ra[3:0];
endmodule
module conflict_inp_fanout_to_top (
input wire CLK,
input wire [ 8:0] A,
input wire [ 8:0] B,
output reg [17:0] Z,
output wire [ 3:0] X,
);
wire [8:0] ra;
always @(posedge CLK)
ra <= A;
MULT9X9 # (
.REGINPUTA("BYPASS"),
.REGINPUTB("BYPASS"),
.REGOUTPUT("BYPASS")
) mult (
.A (ra),
.B (B),
.Z (Z)
);
assign X = ra[3:0];
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int t; cin >> t; while (t--) { long long int a, b, n, s; cin >> a >> b >> n >> s; long long int r = s % n; long long int q = s / n; if (q <= a) { if (r <= b) { cout << YES << n ; } else cout << NO << n ; } else if (((q - a) * n + r) <= b) { cout << YES << n ; } else { cout << NO << n ; } } } |
#include <bits/stdc++.h> using namespace std; pair<pair<int, int>, pair<int, int> > a[60000]; int ans[60000], b[60000], n, m, maxx; int main() { cin >> n >> m; for (int i = 1; i <= m; i++) cin >> a[i].first.first >> a[i].first.second >> a[i].second.first >> a[i].second.second; for (int i = 1; i <= n; i++) ans[i] = (int)(1e9); for (int i = m; i >= 1; i--) { if (a[i].first.first == 1) { for (int j = a[i].first.second; j <= a[i].second.first; j++) if (ans[j] < (int)(1e9)) ans[j] -= a[i].second.second; } else { for (int j = a[i].first.second; j <= a[i].second.first; j++) if (ans[j] > a[i].second.second) ans[j] = a[i].second.second; } } for (int i = 1; i <= n; i++) b[i] = ans[i]; for (int i = 1; i <= m; i++) { if (a[i].first.first == 1) { for (int j = a[i].first.second; j <= a[i].second.first; j++) if (ans[j] < (int)(1e9)) ans[j] += a[i].second.second; } else { maxx = -(int)(1e9); for (int j = a[i].first.second; j <= a[i].second.first; j++) if (ans[j] > maxx) maxx = ans[j]; if (maxx != a[i].second.second) { cout << NO n ; return 0; } } } cout << YES n ; for (int i = 1; i <= n; i++) cout << b[i] << ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1000006, B = 1000001969; int n, k, m, L[N], R[N]; char a[N], b[N]; long long a1[N], M[N]; set<int> Set; int actual(int x) { auto it = Set.lower_bound(x); return it == Set.end() ? n + 1 : *it; } void hash_build(char a[], int n, long long H[]) { for (int i = 1; i <= n; i++) H[i] = (H[i - 1] * M[1] + a[i]) % B; } long long hash_range(long long H[], int L, int R) { return (H[R] - H[L - 1] * M[R - L + 1] + 1LL * B * B) % B; } int main() { scanf( %d%d , &n, &k); scanf( %s , b + 1); m = strlen(b + 1); for (int i = 1; i <= k; i++) { scanf( %d , &L[i]); R[i] = L[i] + m - 1; } for (int i = 1; i <= n; i++) { a[i] = ? ; Set.insert(i); } for (int i = 1; i <= k; i++) { for (int j = actual(L[i]); j <= R[i]; j = actual(j + 1)) { a[j] = b[j - L[i] + 1]; Set.erase(j); } } M[0] = 1; M[1] = 2309; for (int i = 2; i < N; i++) M[i] = M[i - 1] * M[1] % B; hash_build(a, n, a1); if (k) { long long H = hash_range(a1, L[1], R[1]); for (int i = 2; i <= k; i++) if (hash_range(a1, L[i], R[i]) != H) { cout << 0 << endl; return 0; } } long long P = 1; for (int i = 1; i <= Set.size(); i++) P = P * 26 % 1000000007; cout << P << endl; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 100010; vector<int> g[maxn]; int src[maxn], dest[maxn]; bool vis[maxn]; int main() { int n, m; int a, b; scanf( %d %d , &n, &m); for (int i = 0; i < m; i++) { scanf( %d %d , &a, &b); a--, b--; g[a].push_back(b); g[b].push_back(a); } queue<int> Q; for (int i = 0; i < n; i++) { scanf( %d , &dest[i]); if (dest[i] == 0) { Q.push(i); } } int ans = 0; while (!Q.empty()) { int i = Q.front(); Q.pop(); if (dest[i] == src[i]) { vis[i] = true; ans++; src[i]++; int len = g[i].size(); for (int j = 0; j < len; j++) { src[g[i][j]]++; if (src[g[i][j]] == dest[g[i][j]]) { Q.push(g[i][j]); } } } } printf( %d n , ans); for (int i = 0; i < n; i++) { if (vis[i]) { ans--; printf( %d%c , i + 1, ans ? : n ); } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 10; const int inf = 1e9; int arr[N], pos[N], rMax[N]; int main() { int n, m; scanf( %d %d , &n, &m); for (int i = 0; i < n; i++) { scanf( %d , arr + i); pos[arr[i]] = i; } fill(rMax, rMax + N, n - 1); while (m--) { int a, b; scanf( %d %d , &a, &b); if (pos[a] < pos[b]) { rMax[a] = min(pos[b] - 1, rMax[a]); } else { rMax[b] = min(pos[a] - 1, rMax[b]); } } long long ans = 1; for (int i = n - 2; i >= 0; i--) { int k = arr[i]; int j = arr[i + 1]; rMax[k] = min(rMax[k], rMax[j]); ans += rMax[k] - i + 1; } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; template <typename T> T sqr(T x) { return x * x; } template <typename T> T abs(T x) { return x < 0 ? -x : x; } template <typename T> T gcd(T a, T b) { return b ? gcd(b, a % b) : a; } const int MAXN = 1e5 + 10; int n; int sum = 0; pair<int, int> a[200000]; int col[MAXN]; int cost[300]; int ans = 2000000007; inline bool cmp(pair<int, int> a, pair<int, int> b) { if (a.first < b.first) return true; if (a.first == b.first) return a.second > b.second; return false; } int main() { ios_base ::sync_with_stdio(false); cin >> n; for (int i = 1; i <= n; i++) cin >> a[i].first, col[a[i].first]++; for (int i = 1; i <= n; i++) cin >> a[i].second, cost[a[i].second]++; sort(a + 1, a + n + 1); if (n == 1) { cout << 0; return 0; } if (n == 2) { if (a[1].first != a[2].first) cout << min(a[1].second, a[2].second); else cout << 0; return 0; } a[0].first = 2000000007; int s = 0; for (int i = n; i; i--) { s += a[i].second; cost[a[i].second]--; if (a[i].first != a[i - 1].first) { int c = 0, del = max(0, i - col[a[i].first]); for (int j = 1; j <= 200; j++) { int r = min(del, cost[j]); c += j * r, del -= r; if (!del) break; } ans = min(ans, sum + c); sum += s, s = 0; } } cout << ans; } |
#include <bits/stdc++.h> using namespace std; const int sz = 4e6 + 50; int n, m; string str; int s[sz], e[sz], four[sz], seven[sz], non_dec[sz], non_inc[sz]; vector<bool> lazy(sz, 0); void calculate(int node) { int lc = node * 2; int rc = lc + 1; int f1 = four[lc], s1 = seven[lc], nd1 = non_dec[lc], ni1 = non_inc[lc]; int f2 = four[rc], s2 = seven[rc], nd2 = non_dec[rc], ni2 = non_inc[rc]; if (lazy[lc]) { swap(f1, s1); swap(nd1, ni1); } if (lazy[rc]) { swap(f2, s2); swap(nd2, ni2); } four[node] = f1 + f2; seven[node] = s1 + s2; non_dec[node] = max(f1 + nd2, nd1 + s2); non_inc[node] = max(s1 + ni2, ni1 + f2); } void modify(int node) { int lc = node * 2; int rc = lc + 1; four[node] = four[lc] + four[rc]; seven[node] = seven[lc] + seven[rc]; non_dec[node] = max(four[lc] + non_dec[rc], non_dec[lc] + seven[rc]); non_inc[node] = max(seven[lc] + non_inc[rc], non_inc[lc] + four[rc]); } void lazyPropagation(int node) { if (lazy[node]) { lazy[2 * node] = !lazy[2 * node]; lazy[2 * node + 1] = !lazy[2 * node + 1]; } lazy[node] = 0; } void build(int node, int l, int r) { s[node] = l; e[node] = r; if (l == r) { if (str[l] == 4 ) { four[node] = 1; seven[node] = 0; non_dec[node] = 1; non_inc[node] = 1; } else { four[node] = 0; seven[node] = 1; non_dec[node] = 1; non_inc[node] = 1; } return; } int mid = (l + r) / 2; build(2 * node, l, mid); build(2 * node + 1, mid + 1, r); modify(node); } void update(int node, int l, int r) { if (s[node] > r || e[node] < l) return; if (l <= s[node] && e[node] <= r) { lazy[node] = !lazy[node]; return; } lazyPropagation(node); update(2 * node, l, r); update(2 * node + 1, l, r); calculate(node); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); string tt; int x, y; cin >> n >> m; cin >> str; str = 0 + str; build(1, 1, n); while (m--) { cin >> tt; if (tt[0] == c ) { if (!lazy[1]) cout << non_dec[1] << n ; else cout << non_inc[1] << n ; } else { cin >> x >> y; update(1, x, y); } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; char a[65]; void pre() { int j = 1; for (j = 1; j <= 10; j++) a[j - 1] = (char)(j - 1 + 48); for (int i = 0; i < 26; i++) a[j++] = (char)(i + 97); for (int i = 0; i < 26; i++) a[j++] = (char)(i + 65); a[10] = Z ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); pre(); int T; cin >> T; while (T--) { vector<int> val(65, 0); int r, c, k; cin >> r >> c >> k; string s[r], ans[r]; int R = 0; for (int i = 0; i < r; i++) { cin >> s[i]; for (int j = 0; j < s[i].size(); j++) { if (s[i][j] == R ) R++; ans[i] += . ; } } int x = R / k; R = R % k; for (int i = 0; i < k; i++) { val[i] = x; if (R) { R--; val[i]++; } } int gg = 0; for (int i = 0; i < r; i++) { if (i % 2 == 0) { for (int j = 0; j < c; j++) { ans[i][j] = a[gg]; if (s[i][j] == R ) { val[gg]--; if (!val[gg]) { gg++; } } if (gg >= k - 1) gg = k - 1; } } else { for (int j = c - 1; j >= 0; j--) { ans[i][j] = a[gg]; if (s[i][j] == R ) { val[gg]--; if (!val[gg]) { gg++; } } if (gg >= k - 1) gg = k - 1; } } } for (int i = 0; i < r; i++) cout << ans[i] << n ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O221AI_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__O221AI_PP_BLACKBOX_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o221ai (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O221AI_PP_BLACKBOX_V
|
/*
Filename : UART.v
Compiler : Quartus II
Description : UART TX Send Data and RX Receive Data
Modules : UART_TX...input clk; //系统时钟
input rst;
input [7:0]DATA; //发送数据
input EN; //使能信号
output reg TX; //发送数据
output reg STATUS; //TX状态，高时空闲
output reg END; //TX发送完毕，有一个高电平脉冲
//发送TX时启动波特率发生器
UART_RX...input clk; //系统时钟
input RX; //接受数据
input rst;
output reg [7:0]DATA; //8位数据存储
output reg STATUS; //RX接受完毕，有一个高电平脉冲
BaudGen... input clk; //系统时钟,27MHz
input start; //开始信号
input rst;
output reg clk_9600;//9600Hz脉冲
Attention : clk should be 27MHz
Author : Yeoman Zhuang
Release : *
*/
module UART_TX(
input clk, rst, EN,
input [7:0]DATA,
output reg TX,STATUS,END
);
wire clk_9600; //发送时钟
BaudGen TXbg(.clk(clk),
.clk_9600(clk_9600),
.start(~STATUS),
.rst(rst));
reg [3:0]TX_num;
reg [7:0]TX_DATA;
initial
begin
TX<=1'b1;
STATUS<=1;
END<=0;
TX_num<=4'h0;
end
always @(posedge clk or posedge rst) begin
if (rst) begin
// reset
STATUS<=1;
TX_DATA<=8'h00;
end else if (EN) begin //检测到EN信号
TX_DATA<=DATA;
STATUS<=0;
end else if (TX_num==4'hA) begin
STATUS<=1;
end
end
always @(posedge clk or posedge rst) begin//发送数据
if (rst) begin
// reset
TX<=1'b1;
TX_num<=0;
END<=1'b0;
end
else if (clk_9600&&(~STATUS)) begin
TX_num<=TX_num+4'h1;
case(TX_num)
4'h0: TX<=1'b0; //起始位
4'h1: TX<=TX_DATA[0];
4'h2: TX<=TX_DATA[1];
4'h3: TX<=TX_DATA[2];
4'h4: TX<=TX_DATA[3];
4'h5: TX<=TX_DATA[4];
4'h6: TX<=TX_DATA[5];
4'h7: TX<=TX_DATA[6];
4'h8: begin
TX<=TX_DATA[7];
END<=1'b1;
end
4'h9: TX<=1'b1;
default: ;
endcase
end
else if (TX_num==4'hA) begin
TX_num<=4'h0;
TX<=1'b1;
end
else END<=0;
end
endmodule
module UART_RX(
input clk, rst, RX,
output reg [7:0]DATA,
output reg STATUS
);
wire clk_9600; //中间采样点
reg start; //接受RX时启动波特率发生器
reg [7:0]temp_DATA;
reg [3:0]RX_num; //接受字节数
BaudGen RXbg(.clk(clk),
.clk_9600(clk_9600),
.start(start),
.rst(rst));
always @(posedge clk or posedge rst) begin
if (rst) begin
// reset
start<=1'b0;
end
else if (~RX) begin
start<=1'b1; //开启波特率发生器//开始接受
end
else if (RX_num==4'hA)begin
start<=1'b0; //关闭波特率发生器
end
end
always @(posedge clk or posedge rst) begin
if (rst) begin
// reset
STATUS<=0;
DATA<=8'h00;
temp_DATA<=8'h00;
RX_num<=4'h0;
end
else if (clk_9600&&start) begin
RX_num<=RX_num+4'h1;
case(RX_num)
4'h1: temp_DATA[0] <= RX;
4'h2: temp_DATA[1] <= RX;
4'h3: temp_DATA[2] <= RX;
4'h4: temp_DATA[3] <= RX;
4'h5: temp_DATA[4] <= RX;
4'h6: temp_DATA[5] <= RX;
4'h7: temp_DATA[6] <= RX;
4'h8: temp_DATA[7] <= RX;
default: ;
endcase
end
else if(RX_num==4'hA)begin
RX_num<=0;
STATUS<=1;
DATA<=temp_DATA;
end
else STATUS<=0;
end
endmodule
module BaudGen(
input clk, start, rst,
output reg clk_9600
);
// clk should be 27MHz
// start, rst, 高电平有效
// 产生9600Hz脉冲
input rst;
input start;
input clk;
output reg clk_9600;
reg [15:0]state;
initial
begin
clk_9600 <= 0;
state <= 0;
end
always@(posedge clk or posedge rst) begin
// Counter, period is 1/9600s
if(rst) begin
state<=0;
end
else if(state==2812 || !start) begin//2812
state<=0;
end
else begin
state<=state+16'd1;
end
end
always @(posedge clk or posedge rst) begin
// generate 50%-duty 9600Hz clock, half the counter
if (rst) begin
clk_9600<=0;
end
else if (state==1406) begin//1406
clk_9600<=1;
end
else begin
clk_9600<=0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { size_t n; string s, t; cin >> n >> s >> t; int base = ( z - a ) + 1; vector<int> l(n + 1), r(n + 1); for (int i = 0; i < int(n); ++i) { l[i + 1] = s[i] - a ; } for (int i = 0; i < int(n); ++i) { r[i + 1] = t[i] - a ; } for (int i = n; i >= 0; --i) { l[i] += r[i]; if (i > 0) { l[i - 1] += l[i] / 26; l[i] %= 26; } } vector<int> res(n + 1); for (int i = 0; i <= n; ++i) { int rem = l[i] % 2; l[i] /= 2; if (i < n) { l[i + 1] += rem * 26; } } for (int i = 1; i <= n; ++i) { cout << char(l[i] + a ); } cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 300 * 1000 + 5, SQ = 373; int a[N]; long long dp[2 * N]; pair<pair<int, int>, int> t[N]; long long finans[N]; int main() { ios ::sync_with_stdio(false); int n; cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; } int q; cin >> q; for (int i = 1; i <= q; i++) { cin >> t[i].first.second >> t[i].first.first; t[i].second = i; } sort(t + 1, t + q + 1); for (int i = 1; i <= q; i++) { int x = t[i].first.first, y = t[i].first.second; if (x < SQ) { if (x != t[i - 1].first.first) { for (int j = n; j > 0; j--) { dp[j] = dp[j + x] + a[j]; } } finans[t[i].second] = dp[y]; } else { long long ans = 0; for (int j = y; j <= n; j += x) { ans += a[j]; } finans[t[i].second] = ans; } } for (int i = 1; i <= q; i++) { cout << finans[i] << n ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2111A_SYMBOL_V
`define SKY130_FD_SC_LS__O2111A_SYMBOL_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o2111a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
input D1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2111A_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XNOR3_4_V
`define SKY130_FD_SC_LS__XNOR3_4_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog wrapper for xnor3 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__xnor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__xnor3_4 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__xnor3_4 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__XNOR3_4_V
|
/***************************************************************************************************
** fpga_nes/hw/src/cpu/apu/apu_div.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* APU divider; building block used by several other APU components. Outputs a pulse every n input
* pulses, where n is the divider's period. It contains a counter which is decremented on the
* arrival of each pulse. When the counter reaches 0, it is reloaded with the period and an output
* pulse is generated. A divider can also be forced to reload its counter immediately, but this
* does not output a pulse. When a divider's period is changed, the current count is not affected.
*
* apu_div_const is a variation on apu_div that has an immutable period.
***************************************************************************************************/
module apu_div
#(
parameter PERIOD_BITS = 16
)
(
input clk_in, // system clock signal
input rst_in, // reset signal
input pulse_in, // input pulse
input reload_in, // reset counter to period_in (no pulse_out generated)
input [PERIOD_BITS-1:0] period_in, // new period value
output pulse_out // divided output pulse
);
reg [PERIOD_BITS-1:0] q_cnt;
wire [PERIOD_BITS-1:0] d_cnt;
always @(posedge clk_in)
begin
if (rst_in)
q_cnt <= 0;
else
q_cnt <= d_cnt;
end
assign d_cnt = (reload_in || (pulse_in && (q_cnt == 0))) ? period_in :
(pulse_in) ? q_cnt - 1'h1 : q_cnt;
assign pulse_out = pulse_in && (q_cnt == 0);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 100000 + 1; int a[N]; int main() { float n, x, y; cin >> x >> y; printf( %.12f , (y * y - x * x) / (2 * x)); } |
//==================================================================================================
// Filename : tb_CORDIC_Arch3.v
// Created On : 2016-10-03 23:39:40
// Last Modified : 2016-10-05 14:22:11
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
//==================================================================================================
// Filename : testbench_CORDICArch2.v
// Created On : 2016-10-03 23:33:09
// Last Modified : 2016-10-03 23:33:09
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
`timescale 1ns/1ps
module testbench_CORDIC_Arch3 (); /* this is automatically generated */
parameter PERIOD = 10;
//ESTAS SON DEFINICIONES QUE SE REALIZAN EN LOS COMANDOS O CONFIGURACIONES
//DEL SIMULADOR O EL SINTETIZADOR
`ifdef SINGLE
parameter W = 32;
parameter EW = 8;
parameter SW = 23;
parameter SWR = 26;
parameter EWR = 5;
`endif
`ifdef DOUBLE
parameter W = 64;
parameter EW = 11;
parameter SW = 52;
parameter SWR = 55;
parameter EWR = 6;
`endif
reg clk; // Reloj del sistema.
reg rst; // Señal de reset del sistema.
reg beg_fsm_cordic; // Señal de inicio de la maquina de estados del módulo CORDIC.
reg ack_cordic; // Señal de acknowledge proveniente de otro módulo que indica que ha recibido el resultado del modulo CORDIC.
reg operation; // Señal que indica si se realiza la operacion seno(1'b1) o coseno(1'b0).
//reg [1:0] r_mode;
reg [W-1:0] data_in; // Dato de entrada, contiene el angulo que se desea calcular en radianes.
reg [1:0] shift_region_flag; // Señal que indica si el ángulo a calcular esta fuera del rango de calculo del algoritmo CORDIC.
//Output Signals
wire ready_cordic; // Señal de salida que indica que se ha completado el calculo del seno/coseno.
wire [W-1:0] data_output; // Bus de datos con el valor final del angulo calculado.
wire overflow_flag; // Bandera de overflow de la operacion.
wire underflow_flag; // Bandera de underflow de la operacion.
wire zero_flag;
wire busy;
CORDIC_Arch3 #(.W(W),.EW(EW),.SW(SW),.SWR(SWR),.EWR(EWR)) inst_CORDIC_Arch3
(
.clk (clk),
.rst (rst),
.beg_fsm_cordic (beg_fsm_cordic),
.ack_cordic (ack_cordic),
.operation (operation),
.data_in (data_in),
.shift_region_flag (shift_region_flag),
.ready_cordic (ready_cordic),
.overflow_flag (overflow_flag),
.underflow_flag (underflow_flag),
.zero_flag (zero_flag),
.busy (busy),
.data_output (data_output)
);
reg [W-1:0] Array_IN [0:((2**PERIOD)-1)];
//reg [W-1:0] Array_IN_2 [0:((2**PERIOD)-1)];
integer contador;
integer FileSaveData;
integer Cont_CLK;
integer Recept;
initial begin
clk = 0;
beg_fsm_cordic = 0;
ack_cordic = 0;
operation = 0;
data_in = 32'h00000000;
shift_region_flag = 2'b00;
rst = 1;
//Depending upong the sumulator, this directive will
//understand that if the macro is defined (e.g. RMODE00)
//then the following code will be added to the compilation
//simulation or sinthesis.
//This is added in order to simulate the accuracy change of the system.
//Abre el archivo testbench
FileSaveData = $fopen("ResultadoXilinxFLM.txt","w");
//Inicializa las variables del testbench
contador = 0;
Cont_CLK = 0;
Recept = 1;
#100 rst = 0;
// #15
// data_in = 32'h3f25514d; //37 grados
// shift_region_flag = 2'b00;
// #5
// beg_fsm_cordic = 1;
// #10
// beg_fsm_cordic = 0;
end
initial begin
`ifdef SINGLE
$readmemh("CORDIC32_input_angles_hex.txt", Array_IN);
`endif
`ifdef DOUBLE
$readmemh("CORDIC64_input_angles_hex.txt", Array_IN);
`endif
end
// clock
initial forever #5 clk = ~clk;
always @(posedge clk) begin
if(rst) begin
contador = 0;
Cont_CLK = 0;
end
else begin
if (contador == (2**PERIOD)) begin
$fclose(FileSaveData);
$finish;
end
else begin
if(Cont_CLK ==1) begin
contador = contador + 1;
beg_fsm_cordic = 0;
data_in = Array_IN[contador];
#40;
Cont_CLK = Cont_CLK + 1;
ack_cordic = 0;
#40;
end
else if(Cont_CLK ==2) begin
ack_cordic = 0;
beg_fsm_cordic = 1;
Cont_CLK = Cont_CLK +1 ;
#40;
end
else begin
ack_cordic = 0;
Cont_CLK = Cont_CLK + 1;
beg_fsm_cordic = 0;
#40;
end
if(ready_cordic==1) begin
ack_cordic = 1;
Cont_CLK = 0;
#15;
end
if(ready_cordic==1 && ack_cordic) begin
Cont_CLK = 0;
#15;
end
end
end
end
// Recepción de datos y almacenamiento en archivo*************
always @(posedge clk) begin
if(ready_cordic) begin
if(Recept == 1) begin
$fwrite(FileSaveData,"%h\n",data_output);
Recept = 0;
end
end
else begin
Recept = 1;
end
end
endmodule
|
(* -*- coding: utf-8 -*- *)
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2018 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(** Standard functions and combinators.
Proofs about them require functional extensionality and can be found
in [Combinators].
Author: Matthieu Sozeau
Institution: LRI, CNRS UMR 8623 - University Paris Sud
*)
(** The polymorphic identity function is defined in [Datatypes]. *)
Arguments id {A} x.
(** Function composition. *)
Definition compose {A B C} (g : B -> C) (f : A -> B) :=
fun x : A => g (f x).
Hint Unfold compose.
Notation " g ∘ f " := (compose g f)
(at level 40, left associativity) : program_scope.
Local Open Scope program_scope.
(** The non-dependent function space between [A] and [B]. *)
Definition arrow (A B : Type) := A -> B.
(** Logical implication. *)
Definition impl (A B : Prop) : Prop := A -> B.
(** The constant function [const a] always returns [a]. *)
Definition const {A B} (a : A) := fun _ : B => a.
(** The [flip] combinator reverses the first two arguments of a function. *)
Definition flip {A B C} (f : A -> B -> C) x y := f y x.
(** Application as a combinator. *)
Definition apply {A B} (f : A -> B) (x : A) := f x.
(** Curryfication of [prod] is defined in [Logic.Datatypes]. *)
Arguments prod_curry {A B C} f p.
Arguments prod_uncurry {A B C} f x y.
|
// Memory-WriteBack Pipeline Register
module wb_pipe_reg
(
input wire clk,
input wire reset,
input wire valid_wb_pipe_reg_i,
input wire reg_wr_wb_pipe_reg_i,
input wire mem_to_reg_wb_pipe_reg_i,
input wire[4:0] rd_wb_pipe_reg_i,
input wire[31:0] res_alu_wb_pipe_reg_i,
input wire[31:0] read_data_wb_pipe_reg_i,
input wire use_link_reg_wb_pipe_reg_i,
input wire[31:0] next_seq_pc_wb_pipe_reg_i,
output wire instr_retired_wb_pipe_reg_o,
output wire reg_wr_wb_pipe_reg_o,
output wire mem_to_reg_wb_pipe_reg_o,
output wire[4:0] rd_wb_pipe_reg_o,
output wire[31:0] res_alu_wb_pipe_reg_o,
output wire[31:0] read_data_wb_pipe_reg_o,
output wire use_link_reg_wb_pipe_reg_o,
output wire[31:0] next_seq_pc_wb_pipe_reg_o
);
reg reg_wr_wb_pipe_reg;
reg mem_to_reg_wb_pipe_reg;
reg instr_retired_wb_pipe_reg;
reg[4:0] rd_wb_pipe_reg;
reg[31:0] res_alu_wb_pipe_reg;
reg[31:0] read_data_wb_pipe_reg;
reg use_link_reg_wb_pipe_reg;
reg[31:0] next_seq_pc_wb_pipe_reg;
assign reg_wr_wb_pipe_reg_o = reg_wr_wb_pipe_reg;
assign mem_to_reg_wb_pipe_reg_o = mem_to_reg_wb_pipe_reg;
assign instr_retired_wb_pipe_reg_o = instr_retired_wb_pipe_reg;
assign rd_wb_pipe_reg_o = rd_wb_pipe_reg;
assign res_alu_wb_pipe_reg_o = res_alu_wb_pipe_reg;
assign read_data_wb_pipe_reg_o = read_data_wb_pipe_reg;
assign next_seq_pc_wb_pipe_reg_o = next_seq_pc_wb_pipe_reg;
assign use_link_reg_wb_pipe_reg_o = use_link_reg_wb_pipe_reg;
always @(posedge clk or posedge reset)
if (reset)
begin
reg_wr_wb_pipe_reg <= 0;
mem_to_reg_wb_pipe_reg <= 0;
rd_wb_pipe_reg <= 0;
res_alu_wb_pipe_reg <= 0;
read_data_wb_pipe_reg <= 0;
instr_retired_wb_pipe_reg <= 0;
next_seq_pc_wb_pipe_reg <= 0;
use_link_reg_wb_pipe_reg <= 0;
end
else
begin
reg_wr_wb_pipe_reg <= reg_wr_wb_pipe_reg_i;
mem_to_reg_wb_pipe_reg <= mem_to_reg_wb_pipe_reg_i;
rd_wb_pipe_reg <= rd_wb_pipe_reg_i;
res_alu_wb_pipe_reg <= res_alu_wb_pipe_reg_i;
read_data_wb_pipe_reg <= read_data_wb_pipe_reg_i;
instr_retired_wb_pipe_reg <= valid_wb_pipe_reg_i;
next_seq_pc_wb_pipe_reg <= next_seq_pc_wb_pipe_reg_i;
use_link_reg_wb_pipe_reg <= use_link_reg_wb_pipe_reg_i;
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:10:59 06/07/2015
// Design Name: UART_LOOPBACK
// Module Name: /home/sadique/Work/Verilog/Spartan6/USB-uart/loopbacktest.v
// Project Name: USB-uart
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: UART_LOOPBACK
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module loopbacktest;
// Inputs
reg sys_clk;
reg RTS;
reg RX;
// Outputs
wire CTS;
wire TX;
// Instantiate the Unit Under Test (UUT)
UART_LOOPBACK uut (
.sys_clk(sys_clk),
.CTS(CTS),
.RTS(RTS),
.TX(TX),
.RX(RX)
);
initial begin
// Initialize Inputs
sys_clk = 0;
RTS = 0;
RX = 1;
//RxD_par = 0;
//RxD_start = 0;
// Wait 100 ns for global reset to finish
#5000;
// Add stimulus here
#0 RX = 0; //Start bit
#8680 RX = 0; //bit 0
#8680 RX = 1; //bit 1
#8680 RX = 0; //bit 2
#8680 RX = 1; //bit 3
#8680 RX = 0; //bit 4
#8680 RX = 1; //bit 5
#8680 RX = 0; //bit 6
#8680 RX = 0; //bit 7
#8680 RX = 1; //Stop bit
#8680 RX = 0; //Start bit
#8680 RX = 1; //bit 0
#8680 RX = 1; //bit 1
#8680 RX = 0; //bit 2
#8680 RX = 1; //bit 3
#8680 RX = 0; //bit 4
#8680 RX = 1; //bit 5
#8680 RX = 0; //bit 6
#8680 RX = 1; //bit 7
#8680 RX = 1; //Stop bit
#8680 RX = 0; //Start bit
#8680 RX = 1; //bit 0
#8680 RX = 1; //bit 1
#8680 RX = 0; //bit 2
#8680 RX = 1; //bit 3
#8680 RX = 0; //bit 4
#8680 RX = 1; //bit 5
#8680 RX = 0; //bit 6
#8680 RX = 1; //bit 7
#8680 RX = 1; //Stop bit
#8680 RX = 0; //Start bit
#8680 RX = 1; //bit 0
#8680 RX = 1; //bit 1
#8680 RX = 0; //bit 2
#8680 RX = 1; //bit 3
#8680 RX = 0; //bit 4
#8680 RX = 1; //bit 5
#8680 RX = 0; //bit 6
#8680 RX = 1; //bit 7
#8680 RX = 1; //Stop bit
#20000
#8680 RX = 0; //Start bit
#8680 RX = 1; //bit 0
#8680 RX = 1; //bit 1
#8680 RX = 0; //bit 2
#8680 RX = 1; //bit 3
#8680 RX = 0; //bit 4
#8680 RX = 1; //bit 5
#8680 RX = 0; //bit 6
#8680 RX = 1; //bit 7
#8680 RX = 1; //Stop bit
end
always begin
#2.5 sys_clk <= !sys_clk;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 3030; struct dsu { int par[MAXN]; void clear() { for (int i = 0; i < MAXN; ++i) par[i] = i; } int find(int x) { return par[x] == x ? x : par[x] = find(par[x]); } bool join(int u, int v) { if ((u = find(u)) == (v = find(v))) return false; par[v] = u; return true; } } dsu; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; ++i) cin >> a[i], a[i]--; int m; cin >> m; vector<pair<int, int>> moves; int step = 0; while (true) { dsu.clear(); int cst = 0; for (int i = 0; i < n; ++i) cst += dsu.join(i, a[i]); vector<int> b(n); for (int i = 0; i < n; ++i) b[a[i]] = i; if (cst < m) { int u = 0; int v = 1; while (dsu.find(u) == dsu.find(v)) v++; moves.emplace_back(u, v); swap(a[u], a[v]); } else if (cst > m) { int u = 0; while (a[u] == u) u++; int v = u + 1; while (dsu.find(v) != dsu.find(u)) v++; moves.emplace_back(u, v); swap(a[u], a[v]); } else break; } cout << moves.size() << n ; for (auto &p : moves) cout << p.first + 1 << << p.second + 1 << ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); int N, M; cin >> N >> M; using Interval = pair<int, int>; vector<Interval> intervals(N); for (int i = 0; i < N; i++) { cin >> intervals[i].first >> intervals[i].second; } int i = 0; int current_time = 1; for (int m = 0; m < M; m++) { int moment; cin >> moment; while (i < N && moment > current_time + intervals[i].first * intervals[i].second - 1) { current_time += intervals[i].first * intervals[i].second; i++; } assert(i < N); cout << i + 1 << n ; } return 0; } |
#include <bits/stdc++.h> const int t = 50; int f[t][t][t], g[t][t]; long long p[t]; int cnt; void mul(int c[t][t], int a[t][t], int b[t][t], int n) { int d[t][t]; memset(d, 0, sizeof d); for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) for (int k = 0; k < n; k++) d[i][k] ^= a[i][j] & b[j][k]; memcpy(c, d, sizeof d); } bool quick(long long m, int n) { int i, j, k, res[t], ans[t]; for (i = 0; i < n; i++) ans[i] = 1; for (i = 0; m; m >>= 1, i++) if (m & 1) { memset(res, 0, sizeof res); for (j = 0; j < n; j++) for (k = 0; k < n; k++) res[k] ^= ans[j] & f[i][j][k]; memcpy(ans, res, sizeof ans); } for (i = 0; i < n && ans[i]; i++) ; return i == n; } bool checker(long long m, int n) { if (!quick(m, n)) return false; for (int i = 0; i < cnt; i++) if (quick(p[i], n)) return false; return true; } int main() { int ans, i, j, n; long long s, m; srand(0x51ac); scanf( %d , &n); m = s = (1ll << n) - 1; for (cnt = 0, i = 2; i * (long long)i <= s; i++) if (s % i == 0) { p[cnt++] = m / i; for (; s % i == 0; s /= i) ; } if (s != 1) p[cnt++] = m / s; do { memset(f, 0, sizeof f); for (i = 1; i < n; i++) f[0][i][i - 1] = 1; for (f[0][0][n - 1] = i = 1; i < n; i++, j >>= 1) f[0][i][n - 1] = rand() & 1; for (i = 1; i < n; i++) mul(f[i], f[i - 1], f[i - 1], n); } while (!checker(m, n)); for (i = 0; i < n; i++) printf( %d , f[0][n - 1 - i][n - 1]); for (puts( ), i = 0; i < n; i++) printf( 1 ); return 0; } |
//------------------------------------------------------------------------------
// YF32 -- A small SOC implementation based on mlite (32-bit RISC CPU)
// @Taiwan
//------------------------------------------------------------------------------
//
// YF32 - A SOC implementation based on verilog ported mlite (32-bit RISC CPU)
// Copyright (C) 2003-2004 Yung-Fu Chen ()
//
//------------------------------------------------------------------------------
// FETURE
// . verilog ported mlite included
// . wishbone bus support
// . simple_pic (programmable interrupt controller)
// . most MIPS-I(TM) opcode support
// . do not support excption
// . do not support "unaligned memory accesses"
// . only user mode support
// . 32K byte ROM
// . 2K byte SRAM
// . UART/Timer are not fully tested yet
// . no internal tri-state bus
// TO DO
// . integrate UART
// . integrate LCD/VGA Controller
// . integrete PS/2 interface
//
//------------------------------------------------------------------------------
// Note:
// MIPS(R) is a registered trademark and MIPS I(TM) is a trademark of
// MIPS Technologies, Inc. in the United States and other countries.
// MIPS Technologies, Inc. does not endorse and is not associated with
// this project. OpenCores and Steve Rhoads are not affiliated in any way
// with MIPS Technologies, Inc.
//------------------------------------------------------------------------------
//
// FILE: alu.v (tranlate from alu.vhd from opencores.org)
//
// Vertsion: 1.0
//
// Date: 2004/03/22
//
// Author: Yung-Fu Chen ()
//
// MODIFICATION HISTORY:
// Date By Version Change Description
//============================================================
// 2004/03/22 yfchen 1.0 Translate from alu.vhd
// 2004/10/27 yfchen 1.2 minor coding style change
//------------------------------------------------------------------------------
//-------------------------------------------------------------------
// TITLE: Arithmetic Logic Unit
// AUTHOR: Steve Rhoads ()
// DATE CREATED: 2/8/01
// FILENAME: alu.vhd
// PROJECT: Plasma CPU core
// COPYRIGHT: Software placed into the public domain by the author.
// Software 'as is' without warranty. Author liable for nothing.
// DESCRIPTION:
// Implements the ALU.
//-------------------------------------------------------------------
`include "yf32_define.v"
module alu (a_in, b_in, alu_function, c_alu);
input [31:0] a_in ;
input [31:0] b_in ;
input [ 3:0] alu_function;
output [31:0] c_alu ;
// type alu_function_type is (alu_nothing, alu_add, alu_subtract,
// alu_less_than, alu_less_than_signed,
// alu_or, alu_and, alu_xor, alu_nor);
wire [32:0] aa ;
wire [32:0] bb ;
wire [32:0] sum ;
wire do_add ;
wire sign_ext;
assign do_add = (alu_function == `alu_add ) ? 1'b1 : 1'b0 ;
assign sign_ext = (alu_function == `alu_less_than) ? 1'b0 : 1'b1 ;
assign aa = {(a_in[31] & sign_ext), a_in} ;
assign bb = {(b_in[31] & sign_ext), b_in} ;
`ifdef alu_type_GENERIC
/*
wire [31:0] c_alu;
assign c_alu = (alu_function==`alu_add |
alu_function==`alu_subtract ) ? sum[31:0]:
(alu_function==`alu_less_than |
alu_function==`alu_less_than_signed) ? {31'b0, sum[32]}:
(alu_function==`alu_or ) ? a_in | b_in:
(alu_function==`alu_and ) ? a_in & b_in:
(alu_function==`alu_xor ) ? a_in ^ b_in:
(alu_function==`alu_nor ) ? ~(a_in | b_in):
32'b0;
*/
reg [31:0] c_alu;
always @(alu_function or sum or a_in or b_in ) begin
case(alu_function) // synopsys parallel_case
`alu_add : c_alu = sum[31:0] ;
`alu_subtract : c_alu = sum[31:0] ;
`alu_less_than : c_alu = {31'b0, sum[32]} ;
`alu_less_than_signed : c_alu = {31'b0, sum[32]} ;
`alu_or : c_alu = a_in | b_in ;
`alu_and : c_alu = a_in & b_in ;
`alu_xor : c_alu = a_in ^ b_in ;
`alu_nor : c_alu = ~(a_in | b_in) ;
default : c_alu = 32'b0 ;
endcase
end
`endif
`ifdef alu_type_TRISTATE
assign c_alu = (alu_function == `alu_add |
alu_function == `alu_subtract) ? sum[31:0] : {32{1'bz}} ;
assign c_alu = (alu_function == `alu_less_than |
alu_function == `alu_less_than_signed) ? {31'b0, sum[32]} : {32{1'bz}} ;
assign c_alu = (alu_function == `alu_or) ? a_in | b_in : {32{1'bz}} ;
assign c_alu = (alu_function == `alu_and) ? a_in & b_in : {32{1'bz}} ;
assign c_alu = (alu_function == `alu_xor) ? a_in ^ b_in : {32{1'bz}} ;
assign c_alu = (alu_function == `alu_nor) ? ~(a_in | b_in) : {32{1'bz}} ;
assign c_alu = (alu_function == `alu_nothing) ? `ZERO : {32{1'bz}} ;
`endif
`ifdef alu_adder_type_GENERIC
assign sum = (do_add)? aa+bb : aa-bb;
`endif
`ifdef alu_adder_type_ALTERA
//lpm_adder
// synthesis translate_off
lpm_add_sub lpm_add_sub_component (
.add_sub (do_add ),
.dataa (aa ),
.datab (bb ),
.result (sum ));
defparam
lpm_add_sub_component.lpm_width = 33,
lpm_add_sub_component.lpm_direction = "UNUSED",
lpm_add_sub_component.lpm_type = "LPM_ADD_SUB",
lpm_add_sub_component.lpm_hint = "ONE_INPUT_IS_CONSTANT=NO";
// synthesis translate_on
`endif
`ifdef alu_adder_type_DW
DW01_addsub #(33) DW_adder (
.A (aa ),
.B (bb ),
.CI (1'b0 )
.ADD_SUB(do_add ),
.SUM (sum ));
`endif
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by Wilson Snyder.
// bug823
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [2:0] in = crc[2:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] mask; // From test of Test.v
wire [3:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[3:0]),
.mask (mask[3:0]),
// Inputs
.clk (clk),
.in (in[2:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {60'h0, out & mask};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x out=%b mask=%b\n",$time, cyc, crc, out, mask);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
end
else if (cyc<10) begin
sum <= '0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'ha9d3a7a69d2bea75
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out, mask,
// Inputs
clk, in
);
input clk;
input [2:0] in;
output reg [3:0] out;
output reg [3:0] mask;
localparam [15:5] p = 11'h1ac;
always @(posedge clk) begin
// verilator lint_off WIDTH
out <= p[15 + in -: 5];
// verilator lint_on WIDTH
mask[3] <= ((15 + in - 5) < 12);
mask[2] <= ((15 + in - 5) < 13);
mask[1] <= ((15 + in - 5) < 14);
mask[0] <= ((15 + in - 5) < 15);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct vertex { long long inside, edge; int size = 1; vector<int> child; }; int ans = 0; multiset<long long> st; vertex g[100009]; void dfs(int v, bool flag, long long deep) { if (flag) { for (int i = 0; i < g[v].child.size(); i++) { dfs(g[v].child[i], 1, 0); g[v].size += g[g[v].child[i]].size; } return; } if (deep - g[v].inside > *st.begin()) flag = 1; st.insert(deep); for (int i = 0; i < g[v].child.size(); i++) { dfs(g[v].child[i], flag, deep + g[g[v].child[i]].edge); g[v].size += g[g[v].child[i]].size; } if (flag) ans += g[v].size; flag = 0; st.erase(deep); } int main() { ios_base::sync_with_stdio(0); int n; st.insert(100000000000000000); cin >> n; for (int i = 1; i <= n; i++) cin >> g[i].inside; for (int i = 2, c; i <= n; i++) { cin >> c >> g[i].edge; g[c].child.push_back(i); } dfs(1, 0, 0); cout << ans; return 0; } |
#include <bits/stdc++.h> int main(int argc, char *argv[]) { int a1, a2, a3, x; scanf( %d%d%d , &a1, &a2, &a3); x = a2; --a3; while (a3--) { x = a1 + a2; a1 = a2; a2 = x; } printf( %d n , x); return 0; } |
#include <bits/stdc++.h> using namespace std; int n; int a, b; vector<int> arr; vector<vector<int> > dp; void solve1(string x, int a, int b) { int n = x.length(); int l = n + 1; int r = -1; for (int i = 0; i < n; i++) { if (x[i] == 1 ) { l = min(l, i); r = max(r, i); } } if (l > r) { cout << 0 << endl; return; } int ans = a; int curr = 0; for (int i = l; i <= r; i++) { if (x[i] == 0 ) curr++; else { ans += min(a, curr * b); curr = 0; } } cout << ans << endl; } int solve(int idx, int prev, int sz) { if (idx == sz) { return prev == 1; } else if (idx > sz) { return 0; } if (dp[idx][prev] != -1) return dp[idx][prev]; int ans = INT_MAX; ans = min(ans, solve(idx + 1, 0, sz) + 2 * a); ans = min(ans, solve(idx + 2, 1, sz) + ((arr[idx] * b) + a) - (idx > 0 ? a * (1 - prev) : 0)); return dp[idx][prev] = ans; } void testcase(int tc) { cin >> a >> b; string x; cin >> x; solve1(x, a, b); return; n = x.length(); arr.clear(); int l = n + 1, r = -1; for (int i = 0; i < n; i++) { if (x[i] == 1 ) { l = i; break; } } for (int i = n - 1; i >= 0; i--) { if (x[i] == 1 ) { r = i; break; } } if (l > r || l == n + 1 || r == -1) { cout << 0 << endl; return; } int curr = 0; for (int i = l; i <= r; i++) { if (x[i] == 0 ) curr++; else { if (curr > 0) { arr.push_back(curr); } curr = 0; } } int sz = arr.size(); if (sz == 0) { cout << a << endl; return; } else { dp.clear(); dp.resize(sz + 9, vector<int>(4, -1)); cout << solve(0, 0, sz) << endl; return; } } int main() { ios::sync_with_stdio(false); cin.tie(0); int T; cin >> T; for (int i = 1; i <= T; i++) { testcase(i); } return 0; } |
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: acl_int_mult64s.v
// Megafunction Name(s):
// lpm_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 174 10/17/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_int_mult64s (
enable,
clock,
dataa,
datab,
result);
parameter INPUT1_WIDTH = 64;
parameter INPUT2_WIDTH = 64;
localparam INPUT1_WIDTH_WITH_SIGN = INPUT1_WIDTH < 64 ? INPUT1_WIDTH + 1 : INPUT1_WIDTH;
localparam INPUT2_WIDTH_WITH_SIGN = INPUT2_WIDTH < 64 ? INPUT2_WIDTH + 1 : INPUT2_WIDTH;
input enable;
input clock;
input [INPUT1_WIDTH_WITH_SIGN - 1 : 0] dataa;
input [INPUT2_WIDTH_WITH_SIGN - 1 : 0] datab;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) output reg [63:0] result;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [INPUT1_WIDTH_WITH_SIGN - 1 : 0] reg_dataa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [INPUT2_WIDTH_WITH_SIGN - 1 : 0] reg_datab;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [INPUT1_WIDTH_WITH_SIGN - 1 : 0] reg_dataa2;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [INPUT2_WIDTH_WITH_SIGN - 1 : 0] reg_datab2;
always@(posedge clock)
begin
if (enable)
begin
result <= reg_dataa2 * reg_datab2;
reg_dataa <= dataa;
reg_datab <= datab;
reg_dataa2 <= reg_dataa;
reg_datab2 <= reg_datab;
end
end
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "3"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "1"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "64"
// Retrieval info: PRIVATE: WidthB NUMERIC "64"
// Retrieval info: PRIVATE: WidthP NUMERIC "128"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "1"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: optimize NUMERIC "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=9"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "3"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "64"
// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "64"
// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "128"
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL "clken"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 64 0 INPUT NODEFVAL "dataa[63..0]"
// Retrieval info: USED_PORT: datab 0 0 64 0 INPUT NODEFVAL "datab[63..0]"
// Retrieval info: USED_PORT: result 0 0 128 0 OUTPUT NODEFVAL "result[127..0]"
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 64 0 dataa 0 0 64 0
// Retrieval info: CONNECT: @datab 0 0 64 0 datab 0 0 64 0
// Retrieval info: CONNECT: result 0 0 128 0 @result 0 0 128 0
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_mult64s.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_mult64s.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_mult64s.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_mult64s.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_mult64s_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_mult64s_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
#include <bits/stdc++.h> using namespace std; template <class T> inline T gcd(T a, T b) { while (b) { a %= b; swap(a, b); } return a; } template <class T> inline T lcm(T a, T b) { return a / gcd(a, b) * b; } inline int nxt() { int wow; scanf( %d , &wow); return wow; } inline long long int lxt() { long long int wow; scanf( %lld , &wow); return wow; } inline double dxt() { double wow; scanf( %lf , &wow); return wow; } int main() { int n = nxt(), a[100]; for (int i = 1; i <= n; i++) a[i] = nxt(); if (a[n] == 15) { puts( DOWN ); return 0; } if (a[n] == 0) { puts( UP ); return 0; } if (n == 1) { puts( -1 ); return 0; } if (a[n] > a[n - 1]) puts( UP ); else puts( DOWN ); return 0; } |
#include <bits/stdc++.h> using namespace std; int arr[101][1001]; int n, m; int g[101][101]; vector<int> col[1001]; set<int> row[101]; bool ans[101][101]; int main() { scanf( %d , &n), scanf( %d , &m); for (int i = 0; i < m; ++i) { int x, y; scanf( %d , &x), scanf( %d , &y); g[x][y] = g[y][x] = 1; } for (int i = 1; i <= n; ++i) g[i][i] = true; for (int i = 1; i <= n; ++i) { for (int j = i + 1; j <= n; ++j) { if (g[i][j] && !ans[i][j]) { for (int k = 0; k < 1001; ++k) if (col[k].size() == 0) { arr[i][k] = i; arr[j][k] = j; col[k].push_back(i), col[k].push_back(j); break; } else { bool ok = true; for (int l = 0; l < col[k].size(); ++l) { int cur = col[k][l]; if (!g[cur][i] || !g[cur][j]) { ok = false; break; } } if (ok) { arr[i][k] = i; arr[j][k] = j; for (int l = 0; l < col[k].size(); ++l) { int cur = col[k][l]; ans[cur][i] = ans[i][cur] = ans[j][cur] = ans[cur][j] = true; } col[k].push_back(i), col[k].push_back(j); break; } } ans[i][j] = true; ans[j][i] = true; } } } for (int i = 0; i < 1001; ++i) for (int j = 0; j < col[i].size(); ++j) row[col[i][j]].insert(i); for (int i = 1; i < 101; ++i) if (row[i].size() == 0) { for (int j = 0; j < 1001; ++j) if (col[j].size() == 0) { col[j].push_back(i); row[i].insert(j); break; } } for (int i = 1; i <= n; ++i) { printf( %d n , row[i].size()); for (set<int>::iterator it = row[i].begin(); it != row[i].end(); ++it) printf( %d %d n , i, (*it) + 1); } } |
module test();
typedef struct packed {
logic [31:0] sub_local;
} row_entry_t;
typedef struct packed {
logic [31:0] row_local;
row_entry_t sub;
row_entry_t [1:0] sub_list;
} row_t;
row_t main;
initial begin
main.row_local = 32'hCAFE;
main.sub.sub_local = 32'h00000001;
main.sub_list[0].sub_local = 32'hACE;
main.sub_list[1].sub_local = 32'hECA;
$display("main=0x%08X", main);
if (main !== 128'h0000cafe0000000100000eca00000ace) begin
$display("FAILED -- main != 128'h0000cafe0000000100000eca00000ace");
$finish;
end
$display("main.row_local=0x%08X", main.row_local);
$display("main.sub=0x%08X", main.sub);
$display("main.sub.sub_local=0x%08X", main.sub.sub_local);
if (main.sub.sub_local !== 32'h00000001) begin
$display("FAILED -- main.sub.sub_local != 32'h00000001");
$finish;
end
$display("main.sub_list[0].sub_local=0x%08X", main.sub_list[0].sub_local);
if (main.sub_list[0].sub_local !== 32'hACE) begin
$display("FAILED -- main.sub.sub_local != 32'h00000ace");
$finish;
end
$display("main.sub_list[1].sub_local=0x%08X", main.sub_list[1].sub_local);
if (main.sub_list[1].sub_local !== 32'hECA) begin
$display("FAILED -- main.sub.sub_local != 32'h00000eca");
$finish;
end
$display("PASSED");
$finish();
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, st, dr, mij, r, l12, l11, c12, c11; int l21, l22, c21, c22; int nr; void getldrept(int li, int ls, int ci, int cs) { int st, dr; int l1, c1, l2, c2; st = li; dr = ls; while (st < dr) { mij = (st + dr) / 2; cout << ? << li << << ci << << mij << << cs << n ; cin >> r; if (r) dr = mij; else st = mij + 1; } l2 = st; st = li; dr = l2; while (st < dr) { mij = (st + dr + 1) / 2; cout << ? << mij << << ci << << l2 << << cs << n ; cin >> r; if (r) st = mij; else dr = mij - 1; } l1 = st; st = ci; dr = cs; while (st < dr) { mij = (st + dr) / 2; cout << ? << l1 << << ci << << l2 << << mij << n ; cin >> r; if (r) dr = mij; else st = mij + 1; } c2 = st; st = ci; dr = c2; while (st < dr) { mij = (st + dr + 1) / 2; cout << ? << l1 << << mij << << l2 << << c2 << n ; cin >> r; if (r) st = mij; else dr = mij - 1; } c1 = st; if (nr == 1) { l11 = l1; l12 = l2; c11 = c1; c12 = c2; } else { l21 = l1; l22 = l2; c21 = c1; c22 = c2; } } int main() { cin >> n; nr = 1; getldrept(1, n, 1, n); nr = 2; if (l11 > 1) { cout << ? << 1 << << 1 << << l11 - 1 << << n << n ; cin >> r; if (r) { getldrept(1, l11 - 1, 1, n); cout << ! << l11 << << c11 << << l12 << << c12; cout << << l21 << << c21 << << l22 << << c22; return 0; } } if (l12 < n) { cout << ? << l12 + 1 << << 1 << << n << << n << n ; cin >> r; if (r) { getldrept(l12 + 1, n, 1, n); cout << ! << l11 << << c11 << << l12 << << c12; cout << << l21 << << c21 << << l22 << << c22; return 0; } } if (c11 > 1) { cout << ? << 1 << << 1 << << n << << c11 - 1 << n ; cin >> r; if (r) { getldrept(1, n, 1, c11 - 1); cout << ! << l11 << << c11 << << l12 << << c12; cout << << l21 << << c21 << << l22 << << c22; return 0; } } if (c12 < n) { cout << ? << 1 << << c12 + 1 << << n << << n << n ; cin >> r; if (r) { getldrept(1, n, c12 + 1, n); cout << ! << l11 << << c11 << << l12 << << c12; cout << << l21 << << c21 << << l22 << << c22; return 0; } } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYGATE4SD1_1_V
`define SKY130_FD_SC_LS__DLYGATE4SD1_1_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog wrapper for dlygate4sd1 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dlygate4sd1.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlygate4sd1_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dlygate4sd1 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlygate4sd1_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dlygate4sd1 base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYGATE4SD1_1_V
|
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