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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRTN_BLACKBOX_V
`define SKY130_FD_SC_MS__DLRTN_BLACKBOX_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlrtn (
Q ,
RESET_B,
D ,
GATE_N
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRTN_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_DLATCH_PR_BLACKBOX_V
`define SKY130_FD_SC_HVL__UDP_DLATCH_PR_BLACKBOX_V
/**
* udp_dlatch$PR: D-latch, gated clear direct / gate active high
* (Q output UDP)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__udp_dlatch$PR (
Q ,
D ,
GATE ,
RESET
);
output Q ;
input D ;
input GATE ;
input RESET;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_DLATCH_PR_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 7; const int M = 23; const int inf = 1e9 + 7; const long long base = 1e18; const double pi = acos(-1); const double ep = 1e-9; map<int, int> st; int pre[1 << M]; int cur[1 << M]; int n; int a[N]; int main() { cin >> n; for (int i = 1; i < n + 1; i++) { cin >> a[i]; st[a[i]] = i - 1; } for (int mask = 0; mask < 1 << M; mask++) cur[mask] = inf; cur[1] = 1; for (int i = 2; i < n + 1; i++) { for (int mask = 0; mask < 1 << (i - 1); mask++) { pre[mask] = cur[mask]; cur[mask] = inf; } for (int mask = 0; mask < 1 << (i - 1); mask++) { if (pre[mask] >= inf) continue; bool check = false; for (int j = 0; j + 1 < i; j++) { if ((mask & (1 << j)) && st.count(a[i] - a[j + 1]) && (mask & (1 << st[a[i] - a[j + 1]]))) { check = true; break; } } if (!check) continue; for (int j = 0; j + 1 < i; j++) if (mask & (1 << (j))) { int nxt = mask ^ (1 << j) ^ (1 << (i - 1)); cur[nxt] = min(cur[nxt], pre[mask]); } int nxt = mask ^ (1 << (i - 1)); cur[nxt] = min(cur[nxt], pre[mask] + (pre[mask] == __builtin_popcount(mask))); } } int ans = inf; for (int mask = 0; mask < 1 << n; mask++) ans = min(ans, cur[mask]); if (ans == inf) ans = -1; cout << ans << endl; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2014/12/04 10:19:43
// Design Name:
// Module Name: onetswitch_top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module onetswitch_top(
inout [14:0]DDR_addr,
inout [2:0]DDR_ba,
inout DDR_cas_n,
inout DDR_ck_n,
inout DDR_ck_p,
inout DDR_cke,
inout DDR_cs_n,
inout [3:0]DDR_dm,
inout [31:0]DDR_dq,
inout [3:0]DDR_dqs_n,
inout [3:0]DDR_dqs_p,
inout DDR_odt,
inout DDR_ras_n,
inout DDR_reset_n,
inout DDR_we_n,
inout FIXED_IO_ddr_vrn,
inout FIXED_IO_ddr_vrp,
inout [53:0]FIXED_IO_mio,
inout FIXED_IO_ps_clk,
inout FIXED_IO_ps_porb,
inout FIXED_IO_ps_srstb,
output [1:0] pl_led,
output pl_pmod
);
reg [23:0] cnt_0;
reg [23:0] cnt_1;
reg [23:0] cnt_2;
wire bd_fclk0_125m;
wire bd_fclk1_75m;
wire bd_fclk2_200m;
always@(posedge bd_fclk0_125m)
cnt_0 <= cnt_0 + 1'b1;
always@(posedge bd_fclk1_75m)
cnt_1 <= cnt_1 + 1'b1;
always@(posedge bd_fclk2_200m)
cnt_2 <= cnt_2 + 1'b1;
assign pl_led[0] = cnt_0[23];
assign pl_led[1] = cnt_1[23];
assign pl_pmod = cnt_2[23];
onets_7020_procsys_wrapper onets_7020_procsys_wrapper(
.FCLK_CLK0_125MHz (bd_fclk0_125m), //output bd_fclk0_125m,
.FCLK_CLK1_75MHz (bd_fclk1_75m), //output bd_fclk1_75m,
.FCLK_CLK2_200MHz (bd_fclk2_200m), //output bd_fclk2_200m,
.DDR_addr (DDR_addr), //inout [14:0]DDR_addr;
.DDR_ba (DDR_ba), //inout [2:0]DDR_ba;
.DDR_cas_n (DDR_cas_n), //inout DDR_cas_n;
.DDR_ck_n (DDR_ck_n), //inout DDR_ck_n;
.DDR_ck_p (DDR_ck_p), //inout DDR_ck_p;
.DDR_cke (DDR_cke), //inout DDR_cke;
.DDR_cs_n (DDR_cs_n), //inout DDR_cs_n;
.DDR_dm (DDR_dm), //inout [3:0]DDR_dm;
.DDR_dq (DDR_dq), //inout [31:0]DDR_dq;
.DDR_dqs_n (DDR_dqs_n), //inout [3:0]DDR_dqs_n;
.DDR_dqs_p (DDR_dqs_p), //inout [3:0]DDR_dqs_p;
.DDR_odt (DDR_odt), //inout DDR_odt;
.DDR_ras_n (DDR_ras_n), //inout DDR_ras_n;
.DDR_reset_n (DDR_reset_n), //inout DDR_reset_n;
.DDR_we_n (DDR_we_n), //inout DDR_we_n;
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn) , //inout FIXED_IO_ddr_vrn
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp), //inout FIXED_IO_ddr_vrp
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb), //inout FIXED_IO_ps_srstb
.FIXED_IO_ps_clk (FIXED_IO_ps_clk), //inout FIXED_IO_ps_clk
.FIXED_IO_ps_porb (FIXED_IO_ps_porb) //inout FIXED_IO_ps_porb
);
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_txcounters.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor () ////
//// - Novan Hartadi () ////
//// - Mahmud Galela () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_txcounters.v,v $
// Revision 1.6 2005/02/21 11:25:27 igorm
// Delayed CRC fixed.
//
// Revision 1.5 2002/04/22 14:54:14 mohor
// FCS should not be included in NibbleMinFl.
//
// Revision 1.4 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.3 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.4 2001/06/27 21:27:45 mohor
// Few typos fixed.
//
// Revision 1.2 2001/06/19 10:38:07 mohor
// Minor changes in header.
//
// Revision 1.1 2001/06/19 10:27:57 mohor
// TxEthMAC initial release.
//
//
//
`include "timescale.v"
module eth_txcounters (StatePreamble, StateIPG, StateData, StatePAD, StateFCS, StateJam,
StateBackOff, StateDefer, StateIdle, StartDefer, StartIPG, StartFCS,
StartJam, StartBackoff, TxStartFrm, MTxClk, Reset, MinFL, MaxFL, HugEn,
ExDfrEn, PacketFinished_q, DlyCrcEn, StateSFD, ByteCnt, NibCnt,
ExcessiveDefer, NibCntEq7, NibCntEq15, MaxFrame, NibbleMinFl, DlyCrcCnt
);
parameter Tp = 1;
input MTxClk; // Tx clock
input Reset; // Reset
input StatePreamble; // Preamble state
input StateIPG; // IPG state
input [1:0] StateData; // Data state
input StatePAD; // PAD state
input StateFCS; // FCS state
input StateJam; // Jam state
input StateBackOff; // Backoff state
input StateDefer; // Defer state
input StateIdle; // Idle state
input StateSFD; // SFD state
input StartDefer; // Defer state will be activated in next clock
input StartIPG; // IPG state will be activated in next clock
input StartFCS; // FCS state will be activated in next clock
input StartJam; // Jam state will be activated in next clock
input StartBackoff; // Backoff state will be activated in next clock
input TxStartFrm; // Tx start frame
input [15:0] MinFL; // Minimum frame length (in bytes)
input [15:0] MaxFL; // Miximum frame length (in bytes)
input HugEn; // Pakets bigger then MaxFL enabled
input ExDfrEn; // Excessive deferral enabled
input PacketFinished_q;
input DlyCrcEn; // Delayed CRC enabled
output [15:0] ByteCnt; // Byte counter
output [15:0] NibCnt; // Nibble counter
output ExcessiveDefer; // Excessive Deferral occuring
output NibCntEq7; // Nibble counter is equal to 7
output NibCntEq15; // Nibble counter is equal to 15
output MaxFrame; // Maximum frame occured
output NibbleMinFl; // Nibble counter is greater than the minimum frame length
output [2:0] DlyCrcCnt; // Delayed CRC Count
wire ExcessiveDeferCnt;
wire ResetNibCnt;
wire IncrementNibCnt;
wire ResetByteCnt;
wire IncrementByteCnt;
wire ByteCntMax;
reg [15:0] NibCnt;
reg [15:0] ByteCnt;
reg [2:0] DlyCrcCnt;
assign IncrementNibCnt = StateIPG | StatePreamble | (|StateData) | StatePAD
| StateFCS | StateJam | StateBackOff | StateDefer & ~ExcessiveDefer & TxStartFrm;
assign ResetNibCnt = StateDefer & ExcessiveDefer & ~TxStartFrm | StatePreamble & NibCntEq15
| StateJam & NibCntEq7 | StateIdle | StartDefer | StartIPG | StartFCS | StartJam;
// Nibble Counter
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
NibCnt <= #Tp 16'h0;
else
begin
if(ResetNibCnt)
NibCnt <= #Tp 16'h0;
else
if(IncrementNibCnt)
NibCnt <= #Tp NibCnt + 1'b1;
end
end
assign NibCntEq7 = &NibCnt[2:0];
assign NibCntEq15 = &NibCnt[3:0];
assign NibbleMinFl = NibCnt >= (((MinFL-3'h4)<<1) -1); // FCS should not be included in NibbleMinFl
assign ExcessiveDeferCnt = NibCnt[13:0] == 16'h17b7;
assign ExcessiveDefer = NibCnt[13:0] == 16'h17b7 & ~ExDfrEn; // 6071 nibbles
assign IncrementByteCnt = StateData[1] & ~ByteCntMax
| StateBackOff & (&NibCnt[6:0])
| (StatePAD | StateFCS) & NibCnt[0] & ~ByteCntMax;
assign ResetByteCnt = StartBackoff | StateIdle & TxStartFrm | PacketFinished_q;
// Transmit Byte Counter
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
ByteCnt[15:0] <= #Tp 16'h0;
else
begin
if(ResetByteCnt)
ByteCnt[15:0] <= #Tp 16'h0;
else
if(IncrementByteCnt)
ByteCnt[15:0] <= #Tp ByteCnt[15:0] + 1'b1;
end
end
assign MaxFrame = ByteCnt[15:0] == MaxFL[15:0] & ~HugEn;
assign ByteCntMax = &ByteCnt[15:0];
// Delayed CRC counter
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
DlyCrcCnt <= #Tp 3'h0;
else
begin
if(StateData[1] & DlyCrcCnt == 3'h4 | StartJam | PacketFinished_q)
DlyCrcCnt <= #Tp 3'h0;
else
if(DlyCrcEn & (StateSFD | StateData[1] & (|DlyCrcCnt[2:0])))
DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1;
end
end
endmodule
|
// Avalon_Test_Streaming.v
// Generated using ACDS version 16.1 196
`timescale 1 ps / 1 ps
module Avalon_Test_Streaming (
);
wire [0:0] st_source_bfm_src_valid; // st_source_bfm:src_valid -> st_sink_bfm:sink_valid
wire [31:0] st_source_bfm_src_data; // st_source_bfm:src_data -> st_sink_bfm:sink_data
wire st_source_bfm_src_ready; // st_sink_bfm:sink_ready -> st_source_bfm:src_ready
wire [0:0] st_source_bfm_src_channel; // st_source_bfm:src_channel -> st_sink_bfm:sink_channel
wire clock_source_bfm_clk_clk; // clock_source_bfm:clk -> [reset_source_bfm:clk, st_sink_bfm:clk, st_source_bfm:clk]
wire reset_source_bfm_reset_reset; // reset_source_bfm:reset -> [st_sink_bfm:reset, st_source_bfm:reset]
altera_avalon_clock_source #(
.CLOCK_RATE (50),
.CLOCK_UNIT ()
) clock_source_bfm (
.clk (clock_source_bfm_clk_clk) // clk.clk
);
altera_avalon_reset_source #(
.ASSERT_HIGH_RESET (1),
.INITIAL_RESET_CYCLES (10)
) reset_source_bfm (
.reset (reset_source_bfm_reset_reset), // reset.reset
.clk (clock_source_bfm_clk_clk) // clk.clk
);
altera_avalon_st_sink_bfm #(
.USE_PACKET (0),
.USE_CHANNEL (1),
.USE_ERROR (0),
.USE_READY (1),
.USE_VALID (1),
.USE_EMPTY (0),
.ST_SYMBOL_W (8),
.ST_NUMSYMBOLS (4),
.ST_CHANNEL_W (1),
.ST_ERROR_W (1),
.ST_EMPTY_W (2),
.ST_READY_LATENCY (0),
.ST_BEATSPERCYCLE (1),
.ST_MAX_CHANNELS (1),
.VHDL_ID (0)
) st_sink_bfm (
.clk (clock_source_bfm_clk_clk), // clk.clk
.reset (reset_source_bfm_reset_reset), // clk_reset.reset
.sink_data (st_source_bfm_src_data), // sink.data
.sink_valid (st_source_bfm_src_valid), // .valid
.sink_ready (st_source_bfm_src_ready), // .ready
.sink_channel (st_source_bfm_src_channel), // .channel
.sink_startofpacket (1'b0), // (terminated)
.sink_endofpacket (1'b0), // (terminated)
.sink_empty (2'b00), // (terminated)
.sink_error (1'b0) // (terminated)
);
altera_avalon_st_source_bfm #(
.USE_PACKET (0),
.USE_CHANNEL (1),
.USE_ERROR (0),
.USE_READY (1),
.USE_VALID (1),
.USE_EMPTY (0),
.ST_SYMBOL_W (8),
.ST_NUMSYMBOLS (4),
.ST_CHANNEL_W (1),
.ST_ERROR_W (1),
.ST_EMPTY_W (2),
.ST_READY_LATENCY (0),
.ST_BEATSPERCYCLE (1),
.ST_MAX_CHANNELS (1),
.VHDL_ID (0)
) st_source_bfm (
.clk (clock_source_bfm_clk_clk), // clk.clk
.reset (reset_source_bfm_reset_reset), // clk_reset.reset
.src_data (st_source_bfm_src_data), // src.data
.src_valid (st_source_bfm_src_valid), // .valid
.src_ready (st_source_bfm_src_ready), // .ready
.src_channel (st_source_bfm_src_channel), // .channel
.src_startofpacket (), // (terminated)
.src_endofpacket (), // (terminated)
.src_empty (), // (terminated)
.src_error () // (terminated)
);
endmodule
|
/*
* Copyright (c) 2000 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This module tests time variables
*/
module main;
time t;
initial begin
if (t !== 64'bx) begin
$display("FAILED -- t == %b", t);
$finish;
end
#35 t = $time;
#5 if (t !== 35) begin
$display("FAILED -- t == %b (should be 35)", t);
$finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
#include <bits/stdc++.h> const int S = 1 << 21; char ibuf[S], *iS, *iT, obuf[S], *oS = obuf, *oT = oS + S - 1; struct Flusher_ { ~Flusher_() { (fwrite(obuf, 1, oS - obuf, stdout), oS = obuf, void()); } } flusher_; template <class T> inline void read(T &x) { x = 0; register char c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, S, stdin), (iS == iT ? EOF : *iS++)) : *iS++); register bool f = 0; while (!isdigit(c)) f ^= c == - , c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, S, stdin), (iS == iT ? EOF : *iS++)) : *iS++); while (isdigit(c)) x = x * 10 + c - 0 , c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, S, stdin), (iS == iT ? EOF : *iS++)) : *iS++); if (f) x = -x; } template <class T> inline void readchar(T &x) { x = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, S, stdin), (iS == iT ? EOF : *iS++)) : *iS++); while (!isalpha(x)) x = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, S, stdin), (iS == iT ? EOF : *iS++)) : *iS++); } template <class T> inline void print(T x) { if (x < 0) (*oS++ = ( - ), oS == oT ? (fwrite(obuf, 1, oS - obuf, stdout), oS = obuf, void()) : void()), x = -x; if (x > 9) print(x / 10); (*oS++ = (x % 10 + 0 ), oS == oT ? (fwrite(obuf, 1, oS - obuf, stdout), oS = obuf, void()) : void()); } template <class T> inline void print(T x, char c) { print(x), (*oS++ = (c), oS == oT ? (fwrite(obuf, 1, oS - obuf, stdout), oS = obuf, void()) : void()); } const int N = 2e5 + 10, sqn = 1000; int n, m, k, ans, cnt, a[N], b[N], s[N]; struct sequence { int siz, ans; std::vector<int> vec, bln, tag; std::vector<std::array<short, (1 << 14)>> val; inline int left(int k) { return k * sqn; } inline int right(int k) { return std::min((int)vec.size() - 1, (k + 1) * sqn - 1); } void modify(int k, int x) { ::ans += ans, cnt -= (vec.back() ^ tag.back()) != 0; for (int i = bln[k] + 1; i <= bln.back(); i++) { ans -= val[i][tag[i]]; tag[i] ^= x; ans += val[i][tag[i]]; } if (bln.back()) for (int i = left(bln[k]); i <= right(bln[k]); i++) val[bln[k]][vec[i]]--; for (int i = k; i <= right(bln[k]); i++) { ans -= vec[i] == tag[bln[k]]; vec[i] ^= x; ans += vec[i] == tag[bln[k]]; } if (bln.back()) for (int i = left(bln[k]); i <= right(bln[k]); i++) val[bln[k]][vec[i]]++; ::ans -= ans, cnt += (vec.back() ^ tag.back()) != 0; } void init() { for (int i = 1; i < vec.size(); i++) vec[i] ^= vec[i - 1]; for (int i = 0; i < vec.size(); i++) ans += vec[i] == 0; for (int i = 0; i < vec.size(); i++) bln.push_back(i / sqn); tag.resize(bln.back() + 1); if (bln.back()) { val.resize(bln.back() + 1); for (int k = 0; k <= bln.back(); k++) { for (int i = left(k); i <= right(k); i++) val[k][vec[i]]++; } } ::ans += vec.size() - ans, cnt += (vec.back() ^ tag.back()) != 0; } } f[N]; void output() { print(cnt ? -1 : ans, n ); } int main() { read(n), read(k), read(m); for (int i = 1; i <= n; i++) read(a[i]); for (int i = 1; i <= n; i++) read(b[i]); for (int i = 1; i <= n + 1; i++) s[i] = a[i - 1] ^ b[i - 1] ^ a[i] ^ b[i]; for (int i = 1; i <= n + 1; i++) f[(i - 1) % k].vec.push_back(s[i]); for (int i = 0; i < k; i++) f[i].init(); output(); for (int c, p, x, v, i = 1; i <= m; i++) { readchar(c), read(p), read(x); if (c == a ) v = a[p] ^ x, a[p] = x; if (c == b ) v = b[p] ^ x, b[p] = x; f[p % k].modify(p / k, v); f[(p - 1) % k].modify((p - 1) / k, v); output(); } } |
#include <bits/stdc++.h> using namespace std; const int maxn = 25; const int maxm = 3000; char maze[maxn][maxn]; int g[maxn * maxn][maxn * maxn]; int n, m, N, M; int src, sink; long long ans; struct Node { int r, c, t; Node() {} Node(int r, int c, int t) : r(r), c(c), t(t) {} }; vector<Node> males, fmales; struct Edge { int u, v, c; Edge() {} Edge(int u, int v, int c) : u(u), v(v), c(c) {} }; struct MaxFlow { int n, m; int Now[maxm], Dfn[maxm]; vector<Edge> edges; vector<int> G[maxm]; void init(int n) { this->n = n; for (auto &x : G) x.clear(); edges.clear(); } void add(int u, int v, int c) { edges.push_back(Edge(u, v, c)); edges.push_back(Edge(v, u, 0)); m = ((int)((edges).size())); G[u].push_back(m - 2); G[v].push_back(m - 1); } int ISAP(int s, int flow) { if (s == sink) return flow; int v, tab = n, now = 0, vary; for (int i = 0; i < ((int)((G[s]).size())); i++) { Edge &e = edges[G[s][i]]; if (e.c > 0) { if (Dfn[s] == Dfn[v = e.v] + 1) vary = ISAP(v, min(flow - now, e.c)), now += vary, e.c -= vary, edges[G[s][i] ^ 1].c += vary; if (Dfn[src] == n) return now; if (e.c > 0) tab = min(tab, Dfn[v]); if (now == flow) break; } } if (now == 0) { if (--Now[Dfn[s]] == 0) Dfn[src] = n; ++Now[Dfn[s] = tab + 1]; } return now; } int getAns() { int flow = 0; memset(Dfn, 0, sizeof Dfn); memset(Now, 0, sizeof Now); Now[0] = n; while (Dfn[src] < n) flow += ISAP(src, 0x0f0f0f0f); return flow; } } solver; int idx(char x, int y) { return x * m + y; } bool cango(int x, int y) { return x >= 0 && x < n && y >= 0 && y < m; } int dx[] = {0, 0, -1, 1}; int dy[] = {-1, 1, 0, 0}; void calDist() { memset(g, 0x0f, sizeof g); for (int i = 0; i < n * m; i++) g[i][i] = 0; for (int x = 0; x < n; x++) for (int y = 0; y < m; y++) { if (maze[x][y] != . ) continue; int u = idx(x, y); for (int k = 0; k < 4; k++) { int nx = x + dx[k]; int ny = y + dy[k]; if (!cango(nx, ny) || maze[nx][ny] == # ) continue; int v = idx(nx, ny); g[u][v] = 1; } } for (int k = 0; k < n * m; k++) for (int i = 0; i < n * m; i++) for (int j = 0; j < n * m; j++) { if (g[i][k] == 0x0f0f0f0f || g[k][j] == 0x0f0f0f0f) continue; g[i][j] = min(g[i][j], g[i][k] + g[k][j]); } } bool check(long long mid) { src = 2 * N + 2 * n * m; sink = src + 1; solver.init(sink + 1); for (int j = 0; j < n; j++) for (int k = 0; k < m; k++) { if (maze[j][k] == # ) continue; int v = idx(j, k); int id1 = 2 * N + v * 2; int id2 = id1 + 1; solver.add(id1, id2, 1); } for (int i = 0; i < N; i++) { int x = males[i].r, y = males[i].c, t = males[i].t; int u = idx(x, y); solver.add(src, i, 1); for (int j = 0; j < n; j++) for (int k = 0; k < m; k++) { if (maze[j][k] == # ) continue; int v = idx(j, k); int id1 = 2 * N + v * 2; int id2 = id1 + 1; if (g[u][v] != 0x0f0f0f0f && 1.0 * g[u][v] * t <= mid) solver.add(i, id1, 1); } x = fmales[i].r, y = fmales[i].c, t = fmales[i].t; u = idx(x, y); solver.add(i + N, sink, 1); for (int j = 0; j < n; j++) for (int k = 0; k < m; k++) { if (maze[j][k] == # ) continue; int v = idx(j, k); int id1 = 2 * N + v * 2; int id2 = id1 + 1; if (g[u][v] != 0x0f0f0f0f && 1.0 * g[u][v] * t <= mid) solver.add(id2, i + N, 1); } } return solver.getAns() == N; } int main() { cin >> n >> m >> N >> M; for (int i = 0; i < n; i++) scanf( %s , maze[i]); int ok = 1; int r, c, t; scanf( %d%d%d , &r, &c, &t); r--, c--; if (N - M == 1) { fmales.push_back(Node(r, c, t)); } else if (M - N == 1) { males.push_back(Node(r, c, t)); } else { ok = 0; } for (int i = 0; i < N; i++) { scanf( %d%d%d , &r, &c, &t); r--, c--; males.push_back(Node(r, c, t)); } for (int i = 0; i < M; i++) { int r, c, t; scanf( %d%d%d , &r, &c, &t); r--, c--; fmales.push_back(Node(r, c, t)); } if (!ok) { puts( -1 ); return 0; } N = max(N, M); calDist(); long long L = 0, R = (long long)1e15; while (R - L > 0) { long long mid = (L + R) >> 1; if (check(mid)) R = mid; else L = mid + 1; } if (R != (long long)1e15) { printf( %lld n , R); } else puts( -1 ); return 0; } |
#include <bits/stdc++.h> using namespace std; int a[1500004]; int main() { int t, c; string s; cin >> t; for (int l = 0; l < t; l++) { cin >> s; c = 0; for (int i = 0; i < s.size(); i++) { if (s[i] == o && s[i + 1] == n && s[i + 2] == e || s[i - 1] == t && s[i] == w && s[i + 1] == o && s[i + 2] == n && s[i + 3] == e || s[i] == t && s[i + 1] == w && s[i + 2] == o && s[i + 3] != n || s[i] == t && s[i + 1] == w && s[i + 2] == o && s[i + 4] != e ) { s[i + 1] = 1 ; a[c] = i + 2; c++; } } cout << c << n ; for (int i = 0; i < c; i++) cout << a[i] << ; cout << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 35, M = 100005; int n, m, f, ans, e; char a[N][M]; int len[N], z[M], b[N][M], p[N][M]; vector<int> v[M]; void dfs(int pos) { if (f) return; z[pos] = 2; for (auto &i : v[pos]) if (!z[i]) dfs(i); else if (z[i] == 2) { f = 1; return; } z[pos] = 1; } bool check(int s, int t) { f = e = 0; z[0] = 0; v[0].clear(); for (int i = b[s][1]; i <= b[t][len[t]]; i++) v[i].clear(), z[i] = 0; for (int i = s; i <= t; i++) { v[0].push_back(b[i][1]); for (int j = s; j <= t; j++) { int l = 0; for (int k = 1; k <= len[i]; k++) { while (k + l <= len[i] && l + 1 <= len[j] && a[i][k + l] == a[j][l + 1]) ++l; if (l) { if (len[i] - k + 1 < len[j] && l == len[i] - k + 1) v[b[i][k]].push_back(b[j][l + 1]); if (len[j] < len[i] - k + 1 && l == len[j]) v[b[i][k]].push_back(b[i][k + l]); if (k > 1 && len[i] - k + 1 == len[j] && l == len[j]) v[b[i][k]].push_back(0); l = p[j][l]; } } } } if (!z[0]) dfs(0); if (f) return 0; for (int i = b[s][1]; i <= b[t][len[t]]; i++) if (!z[i]) { dfs(i); if (f) return 0; } return 1; } int main() { ios::sync_with_stdio(false); cin >> n; for (int i = 1; i <= n; i++) { cin >> (a[i] + 1); len[i] = strlen(a[i] + 1); for (int j = 1; j <= len[i]; j++) b[i][j] = ++m; } for (int i = 1; i <= n; i++) { int k = 0; for (int j = 2; j <= len[i]; j++) { while (k && a[i][k + 1] != a[i][j]) k = p[i][k]; if (a[i][k + 1] == a[i][j]) ++k; p[i][j] = k; } } int j = 1; for (int i = 1; i <= n; i++) { if (i > j) j = i; while (j <= n && check(i, j)) ++j; ans += j - i; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, s = 0; cin >> n; int arr[n]; for (int i = 0; i < n; i++) { cin >> arr[i]; s += arr[i]; } int count = 0, k = 0; for (int i = 0; i < n - 1; i++) { k += arr[i]; if (k == (s - k)) count++; } cout << count; } |
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 2, Question 2
*/
// Testbench for behavioral model for the decoder
// Import the modules that will be tested for in this testbench
`include "encoder_pl.v"
`include "decoder_pl.v"
`include "pipelinedec.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_pipeline();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the arbiter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUTs
// Output of stage 1
wire [18:0] c;
// Output of stage 2
wire [18:0] cx;
// Output of stage 3
wire [7:0] q;
//wire [10:0] rb;
// Declare "reg" signals: inputs to the DUTs
// 1st stage
reg [7:0] b;
reg [7:0] r_b;
reg [18:0] e;
reg [18:0] r_e;
// 2nd stage
reg [18:0] r_c;
reg [18:0] rr_e;
reg [7:0] rr_b;
//reg [15:1] err;
// 3rd stage
//reg [14:0] cx;
//reg [10:0] qx;
reg [18:0] r_qx;
reg [7:0] rb;
reg clk,reset;
reg [18:0] e2;
encoder enc (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_b,c);
decoder dec (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_qx,q);
large_xor xr (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_c,rr_e,cx);
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen
#10 clk = 0;
#10 clk = 1;
end
// Create the register (flip-flop) for the initial/1st stage
always@(posedge clk)
begin
if(reset)
begin
r_b<=0;
r_e<=0;
end
else
begin
r_e<=e;
r_b<=b;
end
end
// Create the register (flip-flop) for the 2nd stage
always@(posedge clk)
begin
if(reset)
begin
r_c<=0;
rr_e<=0;
rr_b<=0;
end
else
begin
r_c<=c;
rr_e<=r_e;
rr_b<=r_b;
end
end
// Create the register (flip-flop) for the 3rd stage
always@(posedge clk)
begin
if(reset)
begin
rb<=0;
end
else
begin
r_qx<=cx;
rb<=rr_b;
e2<=rr_e;
end
end
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
reset=1;
#20;
reset=0;
b = $random;
e = 19'b0000000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 19'b0000000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 19'b0000000001000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 19'b0000000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 19'b0000000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 19'b0000000100000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 19'b0000000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 19'b0000000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 19'b0000001000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 19'b0000000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#300;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////////////
// Company: Digilent Inc.
// Engineer: Andrew Skreen
//
// Create Date: 07/11/2012
// Module Name: digit_select
// Project Name: PmodGYRO_Demo
// Target Devices: Nexys3
// Tool versions: ISE 14.1
// Description: Selects current digit to display on SSD.
//
// Revision History:
// Revision 0.01 - File Created (Andrew Skreen)
// Revision 1.00 - Added Comments and Converted to Verilog (Josh Sackos)
//////////////////////////////////////////////////////////////////////////////////////////
// ==============================================================================
// Define Module
// ==============================================================================
module digit_select(
d1,
d2,
d3,
d4,
control,
digit
);
// ==============================================================================
// Port Declarations
// ==============================================================================
input [3:0] d1;
input [3:0] d2;
input [3:0] d3;
input [3:0] d4;
input [1:0] control;
output [3:0] digit;
// ==============================================================================
// Implementation
// ==============================================================================
// Assign digit to display on SSD cathodes
assign digit = (control == 2'b11) ? d1 :
(control == 2'b10) ? d2 :
(control == 2'b01) ? d3 :
d4;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 5; const int MAX = 1e9 + 5; int i, j, w1, w2, k, n, m, a[N], b[N], calca[N], calcb[N], temp; vector<pair<int, int> > ans, adasd; bool ctr(int s) { int set = 0; int p1 = 0; int p2 = 0; int last1 = 0; int last2 = 0; int lastt = 0; while (1) { if (w1 == last1 && w2 == last2) if (((p1 > p2 && lastt == 1) || (p2 > p1 && lastt == 2)) && p1 != p2) { temp = max(p1, p2); return true; } else return false; if (last2 + s <= w2 && b[last2 + s] < a[last1 + s]) { p2++; lastt = 2; last2 += s; last1 = lower_bound(a + 1, a + w1 + 1, b[last2]) - a - 1; } else if (last1 + s <= w1 && a[last1 + s] < b[last2 + s]) { p1++; lastt = 1; last1 += s; last2 = lower_bound(b + 1, b + w2 + 1, a[last1]) - b - 1; } else return false; } } int main() { cin >> n; int asdasdasda; for (int i = 1; i <= 200001; i++) a[i] = b[i] = 100000000; int x; for (int i = 1; i <= n; i++) { scanf( %d , &x); if (x == 1) a[++w1] = i; else b[++w2] = i; } for (int i = 1; i <= n; i++) if (ctr(i)) ans.push_back(make_pair(temp, i)); sort(ans.begin(), ans.end()); cout << ans.size() << n ; for (int i = 0; i <= (int)ans.size() - 1; i++) cout << ans[i].first << << ans[i].second << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFBBP_1_V
`define SKY130_FD_SC_HDLL__SDFBBP_1_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog wrapper for sdfbbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__sdfbbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfbbp_1 (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__sdfbbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK(CLK),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfbbp_1 (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__sdfbbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK(CLK),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFBBP_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O41A_TB_V
`define SKY130_FD_SC_LP__O41A_TB_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o41a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg A4;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
A4 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 A4 = 1'b0;
#100 B1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 A4 = 1'b1;
#280 B1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 A4 = 1'b0;
#460 B1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 B1 = 1'b1;
#660 A4 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 B1 = 1'bx;
#840 A4 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_lp__o41a dut (.A1(A1), .A2(A2), .A3(A3), .A4(A4), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O41A_TB_V
|
module latch_mem_wb (
input clock ,
input reset ,
input [ 5:0] stall ,
input mem_register_write_enable ,
output reg wb_register_write_enable ,
input [ 4:0] mem_register_write_address ,
output reg [ 4:0] wb_register_write_address ,
input [31:0] mem_register_write_data ,
output reg [31:0] wb_register_write_data ,
input mem_register_hi_write_enable,
output reg wb_register_hi_write_enable ,
input [31:0] mem_register_hi_write_data ,
output reg [31:0] wb_register_hi_write_data ,
input mem_register_lo_write_enable,
output reg wb_register_lo_write_enable ,
input [31:0] mem_register_lo_write_data ,
output reg [31:0] wb_register_lo_write_data
);
always @ (posedge clock) begin
if (reset == `RESET_ENABLE || (stall[4] == `STALL_ENABLE && stall[5] == `STALL_DISABLE)) begin
wb_register_write_enable <= `WRITE_DISABLE;
wb_register_write_address <= 5'b0 ;
wb_register_write_data <= 32'b0 ;
wb_register_hi_write_enable <= `WRITE_DISABLE;
wb_register_hi_write_data <= 32'b0 ;
wb_register_lo_write_enable <= `WRITE_DISABLE;
wb_register_lo_write_data <= 32'b0 ;
end
else if (stall[4] == `STALL_DISABLE) begin
wb_register_write_enable <= mem_register_write_enable ;
wb_register_write_address <= mem_register_write_address ;
wb_register_write_data <= mem_register_write_data ;
wb_register_hi_write_enable <= mem_register_hi_write_enable;
wb_register_hi_write_data <= mem_register_hi_write_data ;
wb_register_lo_write_enable <= mem_register_lo_write_enable;
wb_register_lo_write_data <= mem_register_lo_write_data ;
end
end
endmodule |
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.3 (win64) Build Mon Sep 28 20:06:43 MDT 2015
// Date : Wed Mar 30 14:50:00 2016
// Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/SKL/Desktop/ECE532/repo/streamed_encoder_ip_prj2/project_1.runs/mult_gen_1_synth_1/mult_gen_1_stub.v
// Design : mult_gen_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7a200tsbg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "mult_gen_v12_0_9,Vivado 2015.3" *)
module mult_gen_1(A, B, P)
/* synthesis syn_black_box black_box_pad_pin="A[11:0],B[13:0],P[32:0]" */;
input [11:0]A;
input [13:0]B;
output [32:0]P;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int arr[3000000], a[3000000]; vector<long long int> v; int main() { long long int n, ans = 0; cin >> n; for (long long int i = 0; i < n; i++) cin >> arr[i]; a[0] = 1; for (long long int i = 0; i < n; i++) { v.clear(); for (long long int j = 1; j * j <= arr[i]; j++) { if (arr[i] % j == 0) { v.push_back(j); if (j != arr[i] / j) v.push_back(arr[i] / j); } } sort(v.begin(), v.end()); for (long long int j = v.size() - 1; j >= 0; j--) { a[v[j]] = (a[v[j]] % 1000000007 + a[v[j] - 1] % 1000000007) % 1000000007; } } for (int i = 1; i <= 1800000; i++) { ans = (ans % 1000000007 + a[i] % 1000000007) % 1000000007; ans = (ans % 1000000007 + 1000000007) % 1000000007; } cout << ans << n ; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR2_BEHAVIORAL_V
`define SKY130_FD_SC_HD__NOR2_BEHAVIORAL_V
/**
* nor2: 2-input NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__nor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR2_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; long long int cost(long long int h[], long long int n, long long int a, long long int r, long long int m, long long int x) { long long int plus = 0, minus = 0; for (int i = 0; i < n; i++) { if (h[i] > x) { minus += h[i] - x; } else if (h[i] < x) { plus += x - h[i]; } } if (m > a + r) { return (a * plus + r * minus); } else { return (min(plus, minus) * m + (plus - min(plus, minus)) * a + (minus - min(plus, minus)) * r); } } int main() { long long int n, a, r, m; cin >> n >> a >> r >> m; long long int h[n], start = 0, end = 0; for (int i = 0; i < n; i++) { cin >> h[i]; end = max(end, h[i]); } long long int ans = 1e18; while (start <= end) { long long int mid = (start + end) >> 1, mid_1; long long int c_mid = cost(h, n, a, r, m, mid); if (c_mid < ans) { ans = c_mid; } mid_1 = mid + 1; long long int c_mid_1 = cost(h, n, a, r, m, mid_1); if (c_mid_1 > c_mid) { end = mid - 1; } else { start = mid + 1; } } cout << ans << n ; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DECAPKAPWR_6_V
`define SKY130_FD_SC_LP__DECAPKAPWR_6_V
/**
* decapkapwr: Decoupling capacitance filler on keep-alive rail.
*
* Verilog wrapper for decapkapwr with size of 6 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__decapkapwr.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__decapkapwr_6 (
KAPWR,
VPWR ,
VGND ,
VPB ,
VNB
);
input KAPWR;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__decapkapwr base (
.KAPWR(KAPWR),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__decapkapwr_6 ();
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__decapkapwr base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DECAPKAPWR_6_V
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module strobe_gen
( input clock,
input reset,
input enable,
input [7:0] rate, // Rate should be 1 LESS THAN your desired divide ratio
input strobe_in,
output wire strobe );
// parameter width = 8;
reg [7:0] counter;
assign strobe = ~|counter && enable && strobe_in;
always @(posedge clock)
if(reset | ~enable)
counter <= #1 8'd0;
else if(strobe_in)
if(counter == 0)
counter <= #1 rate;
else
counter <= #1 counter - 8'd1;
endmodule // strobe_gen
|
#include <bits/stdc++.h> using namespace std; vector<long long> v[3001]; long long visited[3001][3001]; long long poss[3001]; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n, m, k; cin >> n >> m >> k; pair<long long, long long> parent[n + 1][n + 1]; for (long long i = 0; i < m; i++) { long long a, b; cin >> a >> b; v[a].push_back(b); v[b].push_back(a); } set<tuple<long long, long long, long long>> s; for (long long i = 0; i < k; i++) { long long a, b, c; cin >> a >> b >> c; s.insert({a, b, c}); } queue<pair<long long, long long>> q; q.push({1, 1}); visited[1][1] = 1; parent[1][1] = {-1, -1}; poss[1] = 1; pair<long long, long long> last = {-1, -1}; while (!q.empty()) { pair<long long, long long> node = q.front(); if (node.second == n) { last = {node}; break; } q.pop(); for (auto c : v[node.second]) { if (visited[node.second][c] == 0 && !s.count({node.first, node.second, c})) { parent[node.second][c] = node; visited[node.second][c] = visited[node.first][node.second] + 1; poss[c] = 1; q.push({node.second, c}); } } } if (poss[n]) { vector<long long> ans; pair<long long, long long> start = last; while ((parent[start.first][start.second]) != parent[1][1]) { ans.push_back(start.second); start = parent[start.first][start.second]; } ans.push_back(start.second); reverse(ans.begin(), ans.end()); cout << ans.size() - 1 << n ; for (auto c : ans) cout << c << ; } else cout << -1 << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__XOR2_PP_SYMBOL_V
`define SKY130_FD_SC_MS__XOR2_PP_SYMBOL_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__xor2 (
//# {{data|Data Signals}}
input A ,
input B ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__XOR2_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline void Read(T &x) { x = 0; char c; while (!isdigit(c = getchar())) ; do { x = x * 10 + c - 0 ; } while (isdigit(c = getchar())); } long long read() { long long tmp; cin >> tmp; return tmp; } void giuncute() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); } void OF() { freopen( f .inp , r , stdin); freopen( f .out , w , stdout); } const long long MOD = 1e9 + 7, mxn = 5e3 + 2; long long n, a[mxn] = {0}, numNode[mxn] = {0}, p[mxn]; int down[mxn][mxn] = {{0}}, up[mxn][2] = {{0}}; long long Pow(long long u, long long v) { if (!v) return 1; long long tmp = Pow(u, v >> 1); (tmp *= tmp) %= MOD; if (v & 1) return (tmp * u) % MOD; return tmp; } int main() { giuncute(); cin >> n; numNode[1] = 1; for (long long i = 1; i <= n - 1; ++i) { cin >> a[i]; numNode[i + 1] = (numNode[i] * a[i]) % MOD; p[i] = Pow(a[i], MOD - 2); } for (long long i = 1; i <= n; ++i) down[i][1] = a[i], up[i][1] = 1; up[1][1] = 0; for (long long i = n - 1; i >= 1; --i) for (long long j = 2; j <= n - i; ++j) down[i][j] = (a[i] * down[i + 1][j - 1]) % MOD; long long p2 = Pow(2, MOD - 2); for (long long j = 1; j <= n * 2 - 2; ++j) { long long cnt_up = 0, cnt_down = 0; if (j != 1) for (long long i = 2; i <= n; ++i) { if (j > n + i - 2) continue; (up[i][j & 1] += up[i - 1][~j & 1]) %= MOD; if (j <= n && down[i - 1][j - 1]) (up[i][j & 1] += (down[i - 1][j - 1] * (((a[i - 1] - 1) * p[i - 1]) % MOD)) % MOD) %= MOD; } for (long long i = 1; i <= n; ++i) { up[i][~j & 1] = 0; if (j > n + i - 2) continue; (cnt_up += (numNode[i] * up[i][j & 1]) % MOD) %= MOD; if (j < n) (cnt_down += (numNode[i] * down[i][j]) % MOD) %= MOD; } cout << (((cnt_up + cnt_down) % MOD) * p2) % MOD << ; } } |
module conway #(
parameter WIDTH = 32,
parameter HEIGHT = 32
)(
in_states,
out_states
);
input [WIDTH*HEIGHT-1:0] in_states;
output [WIDTH*HEIGHT-1:0] out_states;
genvar r, c;
generate
for (c = 0; c < WIDTH; c=c+1) begin
assign out_states[c] = 0;
assign out_states[(HEIGHT-1)*WIDTH + c] = 0;
end
for (r = 1; r < HEIGHT-1; r=r+1) begin
assign out_states[r * WIDTH] = 0;
assign out_states[(r + 1) * WIDTH - 1] = 0;
for (c = 1; c < WIDTH-1; c=c+1) begin
wire cur_state_i;
wire [4:0] sum_i;
assign cur_state_i = in_states[r * WIDTH + c];
assign sum_i = in_states[r * WIDTH + c-WIDTH-1] + in_states[r * WIDTH + c-WIDTH] + in_states[r * WIDTH + c-WIDTH+1] + in_states[r * WIDTH + c-1] + in_states[r * WIDTH + c+1] + in_states[r * WIDTH + c+WIDTH-1] + in_states[r * WIDTH + c+WIDTH] + in_states[r * WIDTH + c+WIDTH+1];
wire eq2_i, eq3_i;
assign eq2_i = (sum_i == 2);
assign eq3_i = (sum_i == 3);
wire next_state_i;
assign next_state_i = (cur_state_i & (eq2_i | eq3_i)) | (~cur_state_i & eq3_i);
assign out_states[r * WIDTH + c] = next_state_i;
end
end
endgenerate
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SEDFXBP_BEHAVIORAL_V
`define SKY130_FD_SC_LS__SEDFXBP_BEHAVIORAL_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__sedfxbp (
Q ,
Q_N,
CLK,
D ,
DE ,
SCD,
SCE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire mux_out ;
wire de_d ;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD_delayed, SCE_delayed );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D_delayed, DE_delayed );
sky130_fd_sc_ls__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( awake && ( SCE_delayed === 1'b0 ) && ( DE_delayed === 1'b1 ) );
assign cond2 = ( awake && ( SCE_delayed === 1'b1 ) );
assign cond3 = ( awake && ( DE_delayed === 1'b1 ) && ( D_delayed !== SCD_delayed ) );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SEDFXBP_BEHAVIORAL_V |
/*
Teak synthesiser for the Balsa language
Copyright (C) 2007-2010 The University of Manchester
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
Andrew Bardsley <> (and others, see AUTHORS)
School of Computer Science, The University of Manchester
Oxford Road, MANCHESTER, M13 9PL, UK
*/
/*
amust-mapping.v : Teak tech mapping for Amust 180nm library
*/
// tkg_{and,or,nand,nor}[23] : 2/3 input AND/OR/NAND/NOR gates
module tkg_and2 (output o, input i0, i1);
and2x1 I0 (o, i0, i1);
endmodule
module tkg_and3 (output o, input i0, i1, i2);
and3x1 I0 (o, i0, i1, i2);
endmodule
module tkg_or2 (output o, input i0, i1);
or2x1 I0 (o, i0, i1);
endmodule
module tkg_or3 (output o, input i0, i1, i2);
or3x1 I0 (o, i0, i1, i2);
endmodule
module tkg_nand2 (output o, input i0, i1);
nand2x1 I0 (o, i0, i1);
endmodule
module tkg_nand3 (output o, input i0, i1, i2);
nand3x1 I0 (o, i0, i1, i2);
endmodule
module tkg_nor2 (output o, input i0, i1);
nor2x1 I0 (o, i0, i1);
endmodule
module tkg_nor3 (output o, input i0, i1, i2);
nor3x1 I0 (o, i0, i1, i2);
endmodule
// tkg_c[23] : 2/3 input symmetric C-elements
module tkg_c2 (output o, input i0, i1);
c2x1 I0 (o, i0, i1);
endmodule
module tkg_c3 (output o, input i0, i1, i2);
c3x1 I0 (o, i0, i1, i2);
endmodule
// tkg_c2r1 : 2 input symmetric C-element with active high reset
module tkg_c2r1 (output o, input i0, i1, r);
c2rax1 I0 (o, i0, i1, r);
endmodule
// tkg_c1u1 : asymmetric C-element with one 'symmetric' and one 'up' input
module tkg_c1u1 (output o, input s0, u0);
ao22x1 I0 (o, s0, u0, s0, o);
endmodule
// tkg_ao22 : AND-Ok -R-22. o = i0&i1 | i2&i3
module tkg_ao22 (output o, input i0, i1, i2, i3);
ao22x1 I0 (o, i0, i1, i2, i3);
endmodule
// tkg_ao222 : AND-OR-222. o = i0&i1 | i2&i3 | i4&i5
module tkg_ao222 (output o, input i0, i1, i2, i3, i4, i5);
ao222x1 I0 (o, i0, i1, i2, i3, i4, i5);
endmodule
// tkg_gnd : logic 0 connection
module tkg_gnd (output o);
gnd I0 (o);
endmodule
// tkg_inv : inverter
module tkg_inv (output o, input i);
invx1 I0 (o, i);
endmodule
// tkg_buff : non-inverting logical buffer
module tkg_buff (output o, input i);
feedx1 I0 (o, i);
endmodule
// tkg_mutex : mutual exclusion element. ag&bg is never true.
module tkg_mutex (input ar, br, output ag, bg);
mutex I0 (ar, br, ag, bg);
endmodule
|
#include <bits/stdc++.h> using namespace std; char buf[(1 << 22)], *p1 = buf, *p2 = buf; inline int read() { char c = (p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1 << 22, stdin), p1 == p2) ? EOF : *p1++); int x = 0, f = 1; while (c< 0 | c> 9 ) { if (c == - ) f = -1; c = (p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1 << 22, stdin), p1 == p2) ? EOF : *p1++); } while (c >= 0 && c <= 9 ) x = x * 10 + c - 0 , c = (p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1 << 22, stdin), p1 == p2) ? EOF : *p1++); return x * f; } const int maxn = 1e5 + 10; long long h[2][maxn], dp[2][maxn][2]; int main() { int n; while (~scanf( %d , &n)) { memset(dp, 0, sizeof dp); for (int i = 1; i <= n; i++) scanf( %d , &h[0][i]); for (int i = 1; i <= n; i++) scanf( %d , &h[1][i]); for (int i = 1; i <= n; i++) { for (int j = 0; j < 2; j++) { dp[j][i][0] = max(dp[j][i][0], max(dp[j][i - 1][0], max(dp[j][i - 1][1], max(dp[j ^ 1][i - 1][0], dp[j ^ 1][i - 1][1])))); dp[j][i][1] = max(dp[j][i][1], max(dp[j ^ 1][i - 1][1], max(dp[j][i - 1][0], dp[j ^ 1][i - 1][0])) + h[j][i]); } } printf( %lld n , max(dp[0][n][1], dp[1][n][1])); } return 0; } |
#include <bits/stdc++.h> using namespace std; void solve() { long long n, m; cin >> n >> m; long long start = 0, end = 6 * (n + m); while (start <= end) { long long mid = (start + end) / 2; long long val1 = (mid / 2) - (mid / 6); long long val2 = (mid / 3) - (mid / 6); if ((mid / 6) >= (max(n - val1, 0LL) + max(m - val2, 0LL))) { end = mid - 1; } else { start = mid + 1; } } cout << start << endl; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t; t = 1; while (t--) solve(); } |
#include <bits/stdc++.h> using namespace std; int main() { int n, k, l, r[200005], cnt = 0; bool valid[200005]; pair<int, int> p; pair<int, pair<int, int> > u; vector<int> v; vector<pair<int, pair<int, int> > > event; priority_queue<pair<int, int> > pq; scanf( %d %d , &n, &k); for (int i = 1; i <= n; i++) { scanf( %d %d , &l, &r[i]); event.push_back(make_pair(l, make_pair(0, i))); event.push_back(make_pair(r[i] + 1, make_pair(1, i))); } sort(event.begin(), event.end()); memset(valid, true, sizeof valid); for (int i = 0; i < (int)event.size(); i++) { u = event[i]; l = u.first; while (u.first == l) { if (u.second.first == 0) { pq.push(make_pair(r[u.second.second], u.second.second)); cnt++; } else if (valid[u.second.second]) { valid[u.second.second] = false; cnt--; } i++; if (i == (int)event.size()) break; u = event[i]; } i--; while (cnt > k) { p = pq.top(); pq.pop(); while (!valid[p.second]) { p = pq.top(); pq.pop(); } valid[p.second] = false; v.push_back(p.second); cnt--; } } printf( %d n , (int)v.size()); for (int i = 0; i < (int)v.size(); i++) { if (i) putchar( ); printf( %d , v[i]); } puts( ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; set<int> s; for (int i = 0; i < n; i++) { int t; cin >> t; s.insert(t); } int a, b; cin >> a >> b; int res = 0; while (a > b) { int mx = 1; set<int> toerase; for (set<int>::reverse_iterator it = s.rbegin(); it != s.rend(); ++it) { int curr = a % *it; if (a - curr >= b) { if (curr > mx) mx = curr; } else { toerase.insert(*it); } if (mx >= *it) break; } for (set<int>::iterator it = toerase.begin(); it != toerase.end(); ++it) { s.erase(*it); } a -= mx; res++; } cout << res; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, d; cin >> a >> b >> c >> d; if (2 * c < d || 2 * d < c || d >= b) cout << -1 ; else { cout << 2 * a << endl << 2 * b << endl; if (c > d) cout << c; else cout << d; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long i, n, r, a, q; void solve() { cin >> n; if (n == 4 || n == 1 || n == 2) { cout << -1 n ; return; } a = n / 3; r = n % 3; if (r == 1) { cout << n / 3 - 2 << 0 << 1 n ; return; } if (r == 2) { cout << n / 3 - 1 << 1 0 << n ; return; } cout << n / 3 << 0 << 0 << n ; } int main() { for (cin >> q; q--;) { solve(); } } |
#include <bits/stdc++.h> using namespace std; int main() { long long int a; cin >> a; while (1) { long long int t = a; long long int su = 0; while (t > 0) { su += t % 10; t /= 10; } if (su % 4 == 0) { cout << a; return 0; } a++; } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__PROBEC_P_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__PROBEC_P_BEHAVIORAL_PP_V
/**
* probec_p: Virtual current probe point.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__probec_p (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__PROBEC_P_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; int n, m; const int MAXN = 1000005; char a[MAXN], b[MAXN]; int mi[MAXN], ma[MAXN]; long long ans = 0; int trs(char a, char b) { int s = 0; if (a == R ) s += 6; else if (a == B ) s += 3; if (b == R ) s += 2; else if (b == B ) s += 1; return s; } int s[MAXN][10]; int main() { scanf( %s , a + 1); scanf( %s , b + 1); n = strlen(a + 1), m = strlen(b + 1); for (int i = 2; i <= m; i++) { for (int j = 0; j <= 9; j++) s[i][j] = s[i - 1][j]; if (b[i] != b[i - 1]) s[i][trs(b[i], b[i - 1])]++; } for (int i = 1; i <= n; i++) { if (i == 1) mi[i] = ma[i] = 1; else mi[i] = mi[i - 1], ma[i] = ma[i - 1]; if (i != 1 && a[i - 1] == b[mi[i]]) mi[i]++; if (i != 1 && ma[i] != m) ma[i]++; while (ma[i] != m && b[ma[i]] != a[i]) ma[i]++; ans += ma[i] - mi[i] + 1; if (i != 1) { ans -= s[ma[i]][trs(a[i - 1], a[i])] - s[mi[i] - 1][trs(a[i - 1], a[i])]; } } printf( %I64d n , ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A22O_BLACKBOX_V
`define SKY130_FD_SC_HDLL__A22O_BLACKBOX_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a22o (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A22O_BLACKBOX_V
|
/*
*
* Copyright (c) 2012-2013
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
module jtag_comm (
input rx_hash_clk,
input rx_golden_nonce_found,
input [59:0] rx_golden_nonce,
output reg tx_new_work,
output reg [55:0] tx_fixed_data = 56'd0,
output reg [159:0] tx_target_hash = 160'd0,
output reg [59:0] tx_start_nonce = 60'd0
);
// Configuration data
reg [56+160+60-1:0] current_job = 276'd0;
reg [55:0] fixed_data = 56'd0;
reg [159:0] target_hash = 160'd0;
reg [59:0] start_nonce = 60'd0;
reg new_work_flag = 1'b0;
// JTAG
wire jt_capture, jt_drck, jt_reset, jt_sel, jt_shift, jt_tck, jt_tdi, jt_update;
wire jt_tdo;
BSCAN_SPARTAN6 # (.JTAG_CHAIN(1)) jtag_blk (
.CAPTURE(jt_capture),
.DRCK(jt_drck),
.RESET(jt_reset),
.RUNTEST(),
.SEL(jt_sel),
.SHIFT(jt_shift),
.TCK(jt_tck),
.TDI(jt_tdi),
.TDO(jt_tdo),
.TMS(),
.UPDATE(jt_update)
);
reg [3:0] addr = 4'hF;
reg [37:0] dr;
reg checksum;
wire checksum_valid = ~checksum;
wire jtag_we = dr[36];
wire [3:0] jtag_addr = dr[35:32];
// Golden Nonce FIFO: from rx_hash_clk to TCK
reg [60:0] golden_nonce_buf, golden_nonce;
always @ (posedge rx_hash_clk)
begin
golden_nonce_buf <= {rx_golden_nonce_found, rx_golden_nonce};
golden_nonce <= golden_nonce_buf;
end
assign jt_tdo = dr[0];
always @ (posedge jt_tck or posedge jt_reset)
begin
if (jt_reset == 1'b1)
begin
dr <= 38'd0;
end
else if (jt_capture == 1'b1)
begin
// Capture-DR
checksum <= 1'b1;
dr[37:32] <= 6'd0;
addr <= 4'hF;
case (addr)
4'h0: dr[31:0] <= 32'h01000100;
4'h1: dr[31:0] <= target_hash[31:0];
4'h2: dr[31:0] <= target_hash[63:32];
4'h3: dr[31:0] <= target_hash[95:64];
4'h4: dr[31:0] <= target_hash[127:96];
4'h5: dr[31:0] <= target_hash[159:128];
4'h6: dr[31:0] <= fixed_data[31:0];
4'h7: dr[31:0] <= fixed_data[55:32];
4'h8: dr[31:0] <= start_nonce[31:0];
4'h9: dr[31:0] <= start_nonce[59:32];
4'hA: dr[31:0] <= 32'hFFFFFFFF;
4'hB: dr[31:0] <= 32'hFFFFFFFF;
4'hC: dr[31:0] <= 32'h55555555;
4'hD: dr[31:0] <= golden_nonce[31:0];
4'hE: dr[31:0] <= golden_nonce[60:32];
4'hF: dr[31:0] <= 32'hFFFFFFFF;
endcase
end
else if (jt_shift == 1'b1)
begin
dr <= {jt_tdi, dr[37:1]};
checksum <= checksum ^ jt_tdi;
end
else if (jt_update & checksum_valid)
begin
addr <= jtag_addr;
if (jtag_we)
begin
case (jtag_addr)
4'h1: target_hash[31:0] <= dr[31:0];
4'h2: target_hash[63:32] <= dr[31:0];
4'h3: target_hash[95:64] <= dr[31:0];
4'h4: target_hash[127:96] <= dr[31:0];
4'h5: target_hash[159:128] <= dr[31:0];
4'h6: fixed_data[31:0] <= dr[31:0];
4'h7: fixed_data[55:32] <= dr[23:0];
4'h8: start_nonce[31:0] <= dr[31:0];
4'h9: start_nonce[59:32] <= dr[27:0];
endcase
end
if (jtag_we && jtag_addr == 4'h9)
begin
current_job <= {dr[27:0], start_nonce[31:0], fixed_data, target_hash};
new_work_flag <= ~new_work_flag;
end
end
end
// Output Metastability Protection
// This should be sufficient, because work rarely changes and comes
// from a slower clock domain (rx_hash_clk is assumed to be fast).
reg [275:0] tx_buffer = 276'd0;
reg [2:0] tx_work_flag = 3'b0;
always @ (posedge rx_hash_clk)
begin
tx_buffer <= current_job;
{tx_start_nonce, tx_fixed_data, tx_target_hash} <= tx_buffer;
tx_work_flag <= {tx_work_flag[1:0], new_work_flag};
tx_new_work <= tx_work_flag[2] ^ tx_work_flag[1];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; int i, a, v, max, min, min1; cin >> a; max = min = a; for (i = 1; i < n; i++) { cin >> v; if (v > max) max = v; if (v < min) min = v; } cin >> a; min1 = a; for (i = 1; i < m; i++) { cin >> v; if (v < min1) min1 = v; } if ((2 * min < max) && (min1 > max)) { cout << max; return 0; } if ((2 * min) < min1 && min1 > max) { cout << (2 * min); return 0; } cout << -1 ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long i, j, k, t, l, r, n, m, p, a, b, c, d, flag; cin >> t; while (t--) { cin >> n; for (i = 0; i < n; i++) { cout << (i + 1) << ; } cout << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename A, typename B> string to_string(pair<A, B> p); template <typename A, typename B, typename C> string to_string(tuple<A, B, C> p); template <typename A, typename B, typename C, typename D> string to_string(tuple<A, B, C, D> p); string to_string(const string& s) { return + s + ; } string to_string(const char* s) { return to_string((string)s); } string to_string(bool b) { return (b ? true : false ); } string to_string(vector<bool> v) { bool first = true; string res = { ; for (int i = 0; i < static_cast<int>(v.size()); i++) { if (!first) { res += , ; } first = false; res += to_string(v[i]); } res += } ; return res; } template <size_t N> string to_string(bitset<N> v) { string res = ; for (size_t i = 0; i < N; i++) { res += static_cast<char>( 0 + v[i]); } return res; } template <typename A> string to_string(A v) { bool first = true; string res = { ; for (const auto& x : v) { if (!first) { res += , ; } first = false; res += to_string(x); } res += } ; return res; } template <typename A, typename B> string to_string(pair<A, B> p) { return ( + to_string(p.first) + , + to_string(p.second) + ) ; } template <typename A, typename B, typename C> string to_string(tuple<A, B, C> p) { return ( + to_string(get<0>(p)) + , + to_string(get<1>(p)) + , + to_string(get<2>(p)) + ) ; } template <typename A, typename B, typename C, typename D> string to_string(tuple<A, B, C, D> p) { return ( + to_string(get<0>(p)) + , + to_string(get<1>(p)) + , + to_string(get<2>(p)) + , + to_string(get<3>(p)) + ) ; } void debug_out() { cerr << endl; } template <typename Head, typename... Tail> void debug_out(Head H, Tail... T) { cerr << << to_string(H); debug_out(T...); } template <typename T> T inverse(T a, T m) { T u = 0, v = 1; while (a != 0) { T t = m / a; m -= t * a; swap(a, m); u -= t * v; swap(u, v); } assert(m == 1); return u; } template <typename T> class Modular { public: using Type = typename decay<decltype(T::value)>::type; constexpr Modular() : value() {} template <typename U> Modular(const U& x) { value = normalize(x); } template <typename U> static Type normalize(const U& x) { Type v; if (-mod() <= x && x < mod()) v = static_cast<Type>(x); else v = static_cast<Type>(x % mod()); if (v < 0) v += mod(); return v; } const Type& operator()() const { return value; } template <typename U> explicit operator U() const { return static_cast<U>(value); } constexpr static Type mod() { return T::value; } Modular& operator+=(const Modular& other) { if ((value += other.value) >= mod()) value -= mod(); return *this; } Modular& operator-=(const Modular& other) { if ((value -= other.value) < 0) value += mod(); return *this; } template <typename U> Modular& operator+=(const U& other) { return *this += Modular(other); } template <typename U> Modular& operator-=(const U& other) { return *this -= Modular(other); } Modular& operator++() { return *this += 1; } Modular& operator--() { return *this -= 1; } Modular operator++(int) { Modular result(*this); *this += 1; return result; } Modular operator--(int) { Modular result(*this); *this -= 1; return result; } Modular operator-() const { return Modular(-value); } template <typename U = T> typename enable_if<is_same<typename Modular<U>::Type, int>::value, Modular>::type& operator*=(const Modular& rhs) { value = normalize(static_cast<int64_t>(value) * static_cast<int64_t>(rhs.value)); return *this; } template <typename U = T> typename enable_if<is_same<typename Modular<U>::Type, int64_t>::value, Modular>::type& operator*=(const Modular& rhs) { int64_t q = static_cast<int64_t>(static_cast<long double>(value) * rhs.value / mod()); value = normalize(value * rhs.value - q * mod()); return *this; } template <typename U = T> typename enable_if<!is_integral<typename Modular<U>::Type>::value, Modular>::type& operator*=(const Modular& rhs) { value = normalize(value * rhs.value); return *this; } Modular& operator/=(const Modular& other) { return *this *= Modular(inverse(other.value, mod())); } template <typename U> friend const Modular<U>& abs(const Modular<U>& v) { return v; } template <typename U> friend bool operator==(const Modular<U>& lhs, const Modular<U>& rhs); template <typename U> friend bool operator<(const Modular<U>& lhs, const Modular<U>& rhs); template <typename U> friend std::istream& operator>>(std::istream& stream, Modular<U>& number); private: Type value; }; template <typename T> bool operator==(const Modular<T>& lhs, const Modular<T>& rhs) { return lhs.value == rhs.value; } template <typename T, typename U> bool operator==(const Modular<T>& lhs, U rhs) { return lhs == Modular<T>(rhs); } template <typename T, typename U> bool operator==(U lhs, const Modular<T>& rhs) { return Modular<T>(lhs) == rhs; } template <typename T> bool operator!=(const Modular<T>& lhs, const Modular<T>& rhs) { return !(lhs == rhs); } template <typename T, typename U> bool operator!=(const Modular<T>& lhs, U rhs) { return !(lhs == rhs); } template <typename T, typename U> bool operator!=(U lhs, const Modular<T>& rhs) { return !(lhs == rhs); } template <typename T> bool operator<(const Modular<T>& lhs, const Modular<T>& rhs) { return lhs.value < rhs.value; } template <typename T> Modular<T> operator+(const Modular<T>& lhs, const Modular<T>& rhs) { return Modular<T>(lhs) += rhs; } template <typename T, typename U> Modular<T> operator+(const Modular<T>& lhs, U rhs) { return Modular<T>(lhs) += rhs; } template <typename T, typename U> Modular<T> operator+(U lhs, const Modular<T>& rhs) { return Modular<T>(lhs) += rhs; } template <typename T> Modular<T> operator-(const Modular<T>& lhs, const Modular<T>& rhs) { return Modular<T>(lhs) -= rhs; } template <typename T, typename U> Modular<T> operator-(const Modular<T>& lhs, U rhs) { return Modular<T>(lhs) -= rhs; } template <typename T, typename U> Modular<T> operator-(U lhs, const Modular<T>& rhs) { return Modular<T>(lhs) -= rhs; } template <typename T> Modular<T> operator*(const Modular<T>& lhs, const Modular<T>& rhs) { return Modular<T>(lhs) *= rhs; } template <typename T, typename U> Modular<T> operator*(const Modular<T>& lhs, U rhs) { return Modular<T>(lhs) *= rhs; } template <typename T, typename U> Modular<T> operator*(U lhs, const Modular<T>& rhs) { return Modular<T>(lhs) *= rhs; } template <typename T> Modular<T> operator/(const Modular<T>& lhs, const Modular<T>& rhs) { return Modular<T>(lhs) /= rhs; } template <typename T, typename U> Modular<T> operator/(const Modular<T>& lhs, U rhs) { return Modular<T>(lhs) /= rhs; } template <typename T, typename U> Modular<T> operator/(U lhs, const Modular<T>& rhs) { return Modular<T>(lhs) /= rhs; } template <typename T, typename U> Modular<T> power(const Modular<T>& a, const U& b) { assert(b >= 0); Modular<T> x = a, res = 1; U p = b; while (p > 0) { if (p & 1) res *= x; x *= x; p >>= 1; } return res; } template <typename T> bool IsZero(const Modular<T>& number) { return number() == 0; } template <typename T> string to_string(const Modular<T>& number) { return to_string(number()); } template <typename T> std::ostream& operator<<(std::ostream& stream, const Modular<T>& number) { return stream << number(); } template <typename T> std::istream& operator>>(std::istream& stream, Modular<T>& number) { typename common_type<typename Modular<T>::Type, int64_t>::type x; stream >> x; number.value = Modular<T>::normalize(x); return stream; } constexpr int md = (int)1e9 + 7; using Mint = Modular<std::integral_constant<decay<decltype(md)>::type, md>>; template <typename T> class graph { public: struct edge { int from; int to; T cost; }; vector<edge> edges; vector<vector<int>> g; int n; graph(int _n) : n(_n) { g.resize(n); } virtual int add(int from, int to, T cost) = 0; }; template <typename T> class forest : public graph<T> { public: using graph<T>::edges; using graph<T>::g; using graph<T>::n; forest(int _n) : graph<T>(_n) {} int add(int from, int to, T cost = 1) { assert(0 <= from && from < n && 0 <= to && to < n); int id = (int)edges.size(); assert(id < n - 1); g[from].push_back(id); g[to].push_back(id); edges.push_back({from, to, cost}); return id; } }; template <typename T> class dfs_forest : public forest<T> { public: using forest<T>::edges; using forest<T>::g; using forest<T>::n; vector<int> pv; vector<int> pe; vector<int> order; vector<int> pos; vector<int> end; vector<int> sz; vector<int> root; vector<int> depth; vector<T> dist; dfs_forest(int _n) : forest<T>(_n) {} void init() { pv = vector<int>(n, -1); pe = vector<int>(n, -1); order.clear(); pos = vector<int>(n, -1); end = vector<int>(n, -1); sz = vector<int>(n, 0); root = vector<int>(n, -1); depth = vector<int>(n, -1); dist = vector<T>(n); } void clear() { pv.clear(); pe.clear(); order.clear(); pos.clear(); end.clear(); sz.clear(); root.clear(); depth.clear(); dist.clear(); } private: void do_dfs(int v) { pos[v] = (int)order.size(); order.push_back(v); sz[v] = 1; for (int id : g[v]) { if (id == pe[v]) { continue; } auto& e = edges[id]; int to = e.from ^ e.to ^ v; depth[to] = depth[v] + 1; dist[to] = dist[v] + e.cost; pv[to] = v; pe[to] = id; root[to] = (root[v] != -1 ? root[v] : to); do_dfs(to); sz[v] += sz[to]; } end[v] = (int)order.size() - 1; } void do_dfs_from(int v) { depth[v] = 0; dist[v] = T{}; root[v] = v; pv[v] = pe[v] = -1; do_dfs(v); } public: void dfs(int v, bool clear_order = true) { if (pv.empty()) { init(); } else { if (clear_order) { order.clear(); } } do_dfs_from(v); } void dfs_all() { init(); for (int v = 0; v < n; v++) { if (depth[v] == -1) { do_dfs_from(v); } } assert((int)order.size() == n); } }; template <typename T> class lca_forest : public dfs_forest<T> { public: using dfs_forest<T>::edges; using dfs_forest<T>::g; using dfs_forest<T>::n; using dfs_forest<T>::pv; using dfs_forest<T>::pos; using dfs_forest<T>::end; using dfs_forest<T>::depth; int h; vector<vector<int>> pr; lca_forest(int _n) : dfs_forest<T>(_n) {} inline void build_lca() { assert(!pv.empty()); int max_depth = 0; for (int i = 0; i < n; i++) { max_depth = max(max_depth, depth[i]); } h = 1; while ((1 << h) <= max_depth) { h++; } pr.resize(n); for (int i = 0; i < n; i++) { pr[i].resize(h); pr[i][0] = pv[i]; } for (int j = 1; j < h; j++) { for (int i = 0; i < n; i++) { pr[i][j] = (pr[i][j - 1] == -1 ? -1 : pr[pr[i][j - 1]][j - 1]); } } } inline bool anc(int x, int y) { return (pos[x] <= pos[y] && end[y] <= end[x]); } inline int go_up(int x, int up) { assert(!pr.empty()); up = min(up, (1 << h) - 1); for (int j = h - 1; j >= 0; j--) { if (up & (1 << j)) { x = pr[x][j]; if (x == -1) { break; } } } return x; } inline int lca(int x, int y) { assert(!pr.empty()); if (anc(x, y)) { return x; } if (anc(y, x)) { return y; } for (int j = h - 1; j >= 0; j--) { if (pr[x][j] != -1 && !anc(pr[x][j], y)) { x = pr[x][j]; } } return pr[x][0]; } }; template <typename T> class fenwick { public: vector<T> fenw; int n; fenwick(int _n) : n(_n) { fenw.resize(n); } void modify(int x, T v) { while (x < n) { fenw[x] += v; x |= (x + 1); } } T get(int x) { T v{}; while (x >= 0) { v += fenw[x]; x = (x & (x + 1)) - 1; } return v; } }; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n; cin >> n; dfs_forest<int> g(n); vector<int> deg(n); for (int i = 0; i < n - 1; i++) { int x, y; cin >> x >> y; --x; --y; g.add(x, y); ++deg[x]; ++deg[y]; } 42; g.dfs(0); vector<vector<int>> children(n); for (int i = 1; i < n; i++) { children[g.pv[i]].push_back(i); } 42; vector<int> num(n, -1); vector<int> low(n, -1); for (int i : g.order) { int sz = (int)children[i].size(); int from = (i == 0 ? -1 : max(0, num[i] - sz)); low[i] = from; int x = from; for (int j : children[i]) { if (x == num[i]) { ++x; } num[j] = x++; } } 42; vector<vector<int>> go(n); for (int i = 0; i < n; i++) { go[i].resize(deg[i]); } 42; go[0].resize(deg[0] + 1); 42; for (int i = 1; i < n; i++) { int j = g.pv[i]; int t = num[i]; go[i][t - low[i]] = j; go[j][t - low[j]] = i; } 42; vector<pair<int, int>> res; res.emplace_back(0, 0); 42; while (res.back().second >= 0) { int i = res.back().first; int t = res.back().second; int pos = t - low[i]; if (pos >= (int)go[i].size()) { res.emplace_back(i, low[i]); continue; } res.emplace_back(go[i][pos], t + 1); } 42; res.pop_back(); 42; cout << res.size() << n ; for (auto& p : res) { cout << p.first + 1 << << p.second << n ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DLATCH_PR_PP_PKG_S_BLACKBOX_V
`define SKY130_FD_SC_HS__UDP_DLATCH_PR_PP_PKG_S_BLACKBOX_V
/**
* udp_dlatch$PR_pp$PKG$s: D-latch, gated clear direct / gate active
* high (Q output UDP)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dlatch$PR_pp$PKG$s (
Q ,
D ,
GATE ,
RESET ,
SLEEP_B,
KAPWR ,
VGND ,
VPWR
);
output Q ;
input D ;
input GATE ;
input RESET ;
input SLEEP_B;
input KAPWR ;
input VGND ;
input VPWR ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DLATCH_PR_PP_PKG_S_BLACKBOX_V
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_dipsw_pio (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input [ 3: 0] in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 3: 0] d1_data_in;
reg [ 3: 0] d2_data_in;
wire [ 3: 0] data_in;
reg [ 3: 0] edge_capture;
wire edge_capture_wr_strobe;
wire [ 3: 0] edge_detect;
wire irq;
reg [ 3: 0] irq_mask;
wire [ 3: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({4 {(address == 0)}} & data_in) |
({4 {(address == 2)}} & irq_mask) |
({4 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata[3 : 0];
end
assign irq = |(edge_capture & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[0] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[0])
edge_capture[0] <= 0;
else if (edge_detect[0])
edge_capture[0] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[1] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[1])
edge_capture[1] <= 0;
else if (edge_detect[1])
edge_capture[1] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[2] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[2])
edge_capture[2] <= 0;
else if (edge_detect[2])
edge_capture[2] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[3] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[3])
edge_capture[3] <= 0;
else if (edge_detect[3])
edge_capture[3] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = d1_data_in ^ d2_data_in;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N_MAX = 1e5, V = (1 << 20); int n, x[N_MAX], t[N_MAX]; struct edge { int l, v; }; vector<edge> G[N_MAX]; long long cnt_tree[V + 1], total_tree[V + 1]; void add(int i, long long a, long long tree[]) { while (i <= V) { tree[i] += a; i += (i & -i); } } long long sum(int i, long long tree[]) { long long s = 0; while (i) { s += tree[i]; i -= (i & -i); } return s; } int ind(long long a, long long tree[]) { int idx = 0, mask = V; a--; while (mask && idx < V) { int t = idx + mask; if (a >= tree[t]) { idx = t; a -= tree[t]; } mask >>= 1; } return idx + 1; } long long T, sol[N_MAX]; void DFS(int v) { add(t[v], x[v], cnt_tree); add(t[v], (long long)x[v] * t[v], total_tree); int i = ind(T, total_tree); if (i > V) sol[v] = sum(V, cnt_tree); else sol[v] = sum(i - 1, cnt_tree) + (T - sum(i - 1, total_tree)) / i; long long m1 = -1, m2 = -1; for (edge e : G[v]) { if (T <= e.l) continue; T -= e.l; DFS(e.v); T += e.l; if (m1 < sol[e.v]) { m2 = m1; m1 = sol[e.v]; } else if (m2 < sol[e.v]) m2 = sol[e.v]; } if (v == 0) sol[v] = max(sol[v], m1); else sol[v] = max(sol[v], m2); add(t[v], -x[v], cnt_tree); add(t[v], -(long long)x[v] * t[v], total_tree); } int main() { ios_base::sync_with_stdio(false); cin >> n >> T; for (int i = 0; i < n; i++) cin >> x[i]; for (int i = 0; i < n; i++) cin >> t[i]; for (int i = 1; i <= n - 1; i++) { int p; edge e; cin >> p >> e.l; e.v = i; e.l *= 2; G[p - 1].push_back(e); } DFS(0); cout << sol[0] << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; vector<int> a; map<int, int> mp; for (int i = 0; i < n; i++) { int val; cin >> val; if (mp.find(val) == mp.end()) { mp[val]++; a.push_back(val); } } sort(a.begin(), a.end()); int i = 0, sum = 0; int g = a.size(); while (i < min(g, k)) { int x = a[i] - sum; cout << x << endl; sum += x; i++; } while (i < k) { cout << 0 << endl; i++; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O41A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__O41A_BEHAVIORAL_PP_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o41a (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O41A_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const long long inf = 1000000007; const int maxn = 300010; int vis[maxn], cnt[maxn]; long long sum[maxn]; int mod(int x, int u) { int ret = 0; for (int i = 2; i <= u; ++i) if (vis[i]) { ret += x % i; } return ret; } long long cal(int x) { long long ret = 0, xx = x; for (int i = 1;; ++i) { int d = x / (i + 1), u = x / i; if (u <= 500) { return ret + mod(x, u); } ret += xx * (cnt[u] - cnt[d]) - (sum[u] - sum[d]) * i; } return ret; } int main() { static int a[maxn]; static long long p[maxn]; int n, N = 300000; cin >> n; for (int i = 0; i < n; ++i) { scanf( %d , &a[i]); } for (int i = 0; i < n; i += 400) { int j = min(n, i + 400); for (int k = i; k < j; ++k) { long long ak = a[k]; p[k] = cal(a[k]) + ak * (cnt[N] - cnt[a[k]]); for (int kk = 0; kk < N; kk += a[k]) { int rig = min(kk + a[k] - 1, N); p[k] += (sum[rig] - sum[kk]) - (long long)kk * (cnt[rig] - cnt[kk]); } for (int kk = i; kk < k; ++kk) { p[k] += a[kk] % a[k] + a[k] % a[kk]; } } for (int k = i; k < j; ++k) { vis[a[k]] = 1; } for (int k = 1; k <= N; ++k) { cnt[k] = vis[k] + cnt[k - 1]; sum[k] = vis[k] * k + sum[k - 1]; } } long long pp = 0; for (int i = 0; i < n; ++i) { pp += p[i]; printf( %lld , pp); } puts( ); return 0; } |
#include <bits/stdc++.h> int a[100005]; int main() { int n; scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , &a[i]); int flag = -1; int sum = 0; int sum1 = 0; int ans = 1; for (int i = 1; i < n; i++) { if (a[i] == a[i - 1]) ans++; else { if (flag == -1) { flag = 1; sum = ans; ans = 1; } else { if (ans != sum) { printf( NO n ); return 0; } ans = 1; } } } if (flag == -1 || ans == sum) printf( YES n ); else printf( NO n ); return 0; } |
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Mon May 26 11:13:41 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode synth_stub /home/keith/Documents/VHDL-lib/top/stereo_radio/ip/bram/bram_stub.v
// Design : bram
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_2,Vivado 2014.1" *)
module bram(clka, wea, addra, dina, clkb, addrb, doutb)
/* synthesis syn_black_box black_box_pad_pin="clka,wea[0:0],addra[10:0],dina[15:0],clkb,addrb[10:0],doutb[15:0]" */;
input clka;
input [0:0]wea;
input [10:0]addra;
input [15:0]dina;
input clkb;
input [10:0]addrb;
output [15:0]doutb;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int SIZE = 1000; long long a, b, p, x; long long qpow(long long x, long long y, long long MOD) { long long res = 1; while (y) { if (y & 1) res = (res * x) % MOD; x = (x * x) % MOD; y = y >> 1; } return res; } int main() { scanf( %lld%lld%lld%lld , &a, &b, &p, &x); long long ans = 0; for (long long i = 1; i < p; i++) { long long tp = qpow(a, i, p); long long invt = qpow(tp, p - 2, p); long long invp = qpow(p - 1, p - 2, p); long long y = ((b * invt - i + p) % p * invp) % p; long long ty = (x - i) / (p - 1); if (i + y * (p - 1) > x) continue; long long anst = (ty - y) / p + 1; ans = ans + anst; } printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long n, ans = 0; cin >> n; vector<int> a(n + 5), b(n + 5), c(n + 5); map<long long, long long> m; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= n; i++) cin >> b[i], m[b[i]] = i; for (int i = 0; i < n; i++) c[i + 1] = m[a[i + 1]]; for (int i = 0; i < n - 1; i++) if (c[i + 2] > c[i + 1]) ans++; else break; cout << n - ans - 1; return 0; } |
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_Sys_nios2_qsys_0_mult_cell (
// inputs:
A_mul_src1,
A_mul_src2,
clk,
reset_n,
// outputs:
A_mul_cell_result
)
;
output [ 31: 0] A_mul_cell_result;
input [ 31: 0] A_mul_src1;
input [ 31: 0] A_mul_src2;
input clk;
input reset_n;
wire [ 31: 0] A_mul_cell_result;
wire [ 31: 0] A_mul_cell_result_part_1;
wire [ 15: 0] A_mul_cell_result_part_2;
wire mul_clr;
assign mul_clr = ~reset_n;
altera_mult_add the_altmult_add_part_1
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (A_mul_src1[15 : 0]),
.datab (A_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (A_mul_cell_result_part_1)
);
defparam the_altmult_add_part_1.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_1.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_1.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_1.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_1.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_1.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_1.input_source_a0 = "DATAA",
the_altmult_add_part_1.input_source_b0 = "DATAB",
the_altmult_add_part_1.lpm_type = "altera_mult_add",
the_altmult_add_part_1.multiplier1_direction = "ADD",
the_altmult_add_part_1.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_1.multiplier_register0 = "CLOCK0",
the_altmult_add_part_1.number_of_multipliers = 1,
the_altmult_add_part_1.output_register = "UNREGISTERED",
the_altmult_add_part_1.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_1.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_part_1.port_signa = "PORT_UNUSED",
the_altmult_add_part_1.port_signb = "PORT_UNUSED",
the_altmult_add_part_1.representation_a = "UNSIGNED",
the_altmult_add_part_1.representation_b = "UNSIGNED",
the_altmult_add_part_1.selected_device_family = "CYCLONEIVE",
the_altmult_add_part_1.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_1.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_1.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_1.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_1.signed_register_a = "UNREGISTERED",
the_altmult_add_part_1.signed_register_b = "UNREGISTERED",
the_altmult_add_part_1.width_a = 16,
the_altmult_add_part_1.width_b = 16,
the_altmult_add_part_1.width_result = 32;
altera_mult_add the_altmult_add_part_2
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (A_mul_src1[31 : 16]),
.datab (A_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (A_mul_cell_result_part_2)
);
defparam the_altmult_add_part_2.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_2.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_2.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_2.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_2.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_2.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_2.input_source_a0 = "DATAA",
the_altmult_add_part_2.input_source_b0 = "DATAB",
the_altmult_add_part_2.lpm_type = "altera_mult_add",
the_altmult_add_part_2.multiplier1_direction = "ADD",
the_altmult_add_part_2.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_2.multiplier_register0 = "CLOCK0",
the_altmult_add_part_2.number_of_multipliers = 1,
the_altmult_add_part_2.output_register = "UNREGISTERED",
the_altmult_add_part_2.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_2.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_part_2.port_signa = "PORT_UNUSED",
the_altmult_add_part_2.port_signb = "PORT_UNUSED",
the_altmult_add_part_2.representation_a = "UNSIGNED",
the_altmult_add_part_2.representation_b = "UNSIGNED",
the_altmult_add_part_2.selected_device_family = "CYCLONEIVE",
the_altmult_add_part_2.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_2.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_2.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_2.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_2.signed_register_a = "UNREGISTERED",
the_altmult_add_part_2.signed_register_b = "UNREGISTERED",
the_altmult_add_part_2.width_a = 16,
the_altmult_add_part_2.width_b = 16,
the_altmult_add_part_2.width_result = 16;
assign A_mul_cell_result = {A_mul_cell_result_part_1[31 : 16] +
A_mul_cell_result_part_2,
A_mul_cell_result_part_1[15 : 0]};
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2e6 + 11; int use[N], a[N], b[N]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; use[a[i]] = 1; } for (int j = 1; j <= n; j++) { cin >> b[j]; use[b[j]] = 1; } int kol = 0; for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) { int d = a[i] ^ b[j]; if (d <= 2000000 && use[d] == 1) kol++; } if (kol % 2 == 0) cout << Karen << endl; else cout << Koyomi << endl; } |
#include <bits/stdc++.h> using namespace std; const int inf = 100010; const int N = 100010; struct e { int v; e *nxt; } es[N << 1], *fir[N]; map<pair<int, int>, int> mp; struct node { int ls, rs; int l, r; int sum; int mid() { return (l + r) >> 1; } } nodes[N << 2]; int n, en, val[N]; int que[N], par[N], dep[N], root[N], seg[N], st[N], ed[N], top[N], sons[N], id[N]; int ln, cnt, tr; inline void init() { en = 0; memset(fir, 0, sizeof(fir)); } inline void add_e(int u, int v) { es[en].v = v; es[en].nxt = fir[u]; fir[u] = &es[en++]; } inline void newNode(int &id, int l, int r) { nodes[cnt].ls = nodes[cnt].rs = -1; nodes[cnt].l = l; nodes[cnt].r = r; id = cnt++; } void build(int &id, int l, int r) { newNode(id, l, r); if (l + 1 >= r) { nodes[id].sum = 1; return; } int mid = (l + r) >> 1; build(nodes[id].ls, l, mid); build(nodes[id].rs, mid, r); nodes[id].sum = nodes[nodes[id].ls].sum + nodes[nodes[id].rs].sum; } void initTree() { int l, r, u, v, i; e *cur; l = r = 0; tr = 1; que[r++] = tr; par[tr] = -1; dep[tr] = 0; while (l != r) { u = que[l++]; for (cur = fir[u]; cur; cur = cur->nxt) { if ((v = cur->v) != par[u]) { que[r++] = v; par[v] = u; dep[v] = dep[u] + 1; } } } for (i = 1; i <= n; i++) { sons[i] = 1; id[i] = -1; } for (i = r - 1; i >= 0; i--) { u = que[i]; if (par[u] >= 0) { sons[par[u]] += sons[u]; } } l = r = 0; que[r++] = tr; ln = cnt = 0; while (l != r) { u = que[l++]; st[ln] = dep[u]; top[ln] = u; while (u >= 0) { id[u] = ln; ed[ln] = dep[u]; seg[dep[u]] = u; int best; for (cur = fir[u], best = -1; cur; cur = cur->nxt) { if (id[v = cur->v] == -1) { if (best == -1 || (best >= 0 && sons[v] > sons[best])) { best = v; } } } if (best >= 0) { for (cur = fir[u]; cur; cur = cur->nxt) { if (id[v = cur->v] == -1 && best != v) { que[r++] = v; } } } u = best; } root[ln] = -1; build(root[ln], st[ln], ed[ln]); ln++; } } int S; void lqry(int &id, int ql, int qr) { if (id == -1) return; if (ql == qr) return; if (ql <= nodes[id].l && nodes[id].r <= qr) { S += nodes[id].sum; if (S > inf) S = inf; return; } if (nodes[id].l + 1 == nodes[id].r) { S += nodes[id].sum; if (S > inf) S = inf; return; } int mid = (nodes[id].l + nodes[id].r) >> 1; if (ql < mid) { lqry(nodes[id].ls, ql, qr); } if (qr > mid) { lqry(nodes[id].rs, ql, qr); } } void update(int id, int x, int y, int val) { if (id == -1) return; if (nodes[id].l + 1 == nodes[id].r) { nodes[id].sum = val; return; } int mid = (nodes[id].l + nodes[id].r) >> 1; if (mid <= x) update(nodes[id].rs, x, y, val); else if (mid >= y) update(nodes[id].ls, x, y, val); nodes[id].sum = nodes[nodes[id].ls].sum + nodes[nodes[id].rs].sum; if (nodes[id].sum > inf) nodes[id].sum = inf; } void qry(int u, int v) { while (id[u] != id[v]) { if (id[u] > id[v]) { swap(u, v); } int b = id[v]; lqry(root[b], st[b], dep[v]); v = par[top[b]]; if (mp.find(make_pair(top[b], par[top[b]])) != mp.end()) S += val[mp[make_pair(top[b], par[top[b]])]]; else S += val[mp[make_pair(par[top[b]], top[b])]]; if (S > inf) S = inf; } if (dep[u] > dep[v]) { swap(u, v); } lqry(root[id[u]], dep[u], dep[v]); } struct ee { int x, y; } edge[100010]; int main() { int m, x, y, ty; scanf( %d , &n); init(); for (int i = 1; i < n; i++) { scanf( %d%d , &x, &y); mp[make_pair(x, y)] = i; val[i] = 1; edge[i].x = x; edge[i].y = y; add_e(x, y); add_e(y, x); } initTree(); scanf( %d , &m); for (int i = 0; i < m; i++) { scanf( %d , &ty); if (ty == 3) { scanf( %d%d , &x, &y); S = 0; qry(x, y); if (S >= inf) printf( -1 n ); else printf( %d n , S); } else if (ty == 1) { scanf( %d , &x); int u = edge[x].x; int v = edge[x].y; val[x] = 1; if (dep[u] > dep[v]) { swap(u, v); } if (id[u] == id[v]) update(root[id[u]], dep[u], dep[u], 1); } else { scanf( %d , &x); int u = edge[x].x; int v = edge[x].y; val[x] = inf; if (dep[u] > dep[v]) { swap(u, v); } if (id[u] == id[v]) update(root[id[u]], dep[u], dep[v], inf); } } } |
#include <bits/stdc++.h> using namespace std; long long a[100010]; int main() { long long n, pos; while (cin >> n >> pos) { for (long long i = 0; i < n; i++) scanf( %I64d , &a[i]); sort(a, a + n); long long res1 = 0, res2, res; if (pos < a[0]) res1 = a[n - 2] - pos; else if (a[0] <= pos && pos <= a[n - 2]) res1 = min((pos - a[0]) * 2 + a[n - 2] - pos, (a[n - 2] - pos) * 2 + pos - a[0]); else if (pos > a[n - 2]) res1 = pos - a[0]; if (pos < a[1]) res2 = a[n - 1] - pos; else if (a[1] <= pos && pos <= a[n - 1]) res2 = min((pos - a[1]) * 2 + a[n - 1] - pos, (a[n - 1] - pos) * 2 + pos - a[1]); else if (pos > a[n - 1]) res2 = pos - a[1]; res = min(res1, res2); if (n == 1) res = 0; printf( %I64d n , res); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; long long t; cin >> t; while (t--) { long long n, x, m, i, flag = 0, a, b, l, r, sum = 2, ones = 0, zero = 0, output = 0, j; vector<pair<long long, long long> > v; cin >> n >> m; long long arr[n + 1][m + 1]; for (i = 1; i <= n; i++) { for (j = 1; j <= m; j++) { cin >> arr[i][j]; } } a = 0; sum = 2; flag = 0; while (flag == 0) { for (i = 1; i <= n; i++) { for (j = 1; j <= m; j++) { if ((i + j == sum) || (i + j == n + m - a)) v.push_back(make_pair(i, j)); } } while (v.size() > 0) { i = v[v.size() - 1].first; j = v[v.size() - 1].second; if (arr[i][j] == 0) zero++; else ones++; v.pop_back(); } output = output + min(zero, ones); zero = 0; ones = 0; a++; sum++; if (sum == n + m - a) break; else if (sum > (n + m - a)) break; } cout << output << n ; } return 0; } |
#include <bits/stdc++.h> struct book { int t, w; bool operator<(const book &b) const { return w < b.w; } } ones[102], twos[102]; int main() { int n; scanf( %d , &n); int nOnes = 0; int tWidthOnes = 0; int nTwos = 0; int tWidthTwos = 0; for (int i = 0; i < n; i++) { int t, w; scanf( %d %d , &t, &w); if (t == 1) { ones[nOnes].t = t; ones[nOnes++].w = w; tWidthOnes += w; } else { twos[nTwos].t = t; twos[nTwos++].w = w; tWidthTwos += w; } } std::sort(ones, ones + nOnes); std::sort(twos, twos + nTwos); int best = 1 << 30; for (int i = 1; i <= 1 * nOnes + 2 * nTwos; i++) { for (int j = 0; j <= i; j++) { if (j <= nOnes && (i - j) <= nTwos) { int botWidth = 1 * j + 2 * (i - j); int topWidth = 0; for (int k = 0; k < nOnes - j; k++) { topWidth += ones[k].w; } for (int k = 0; k < nTwos - (i - j); k++) { topWidth += twos[k].w; } if (topWidth <= botWidth) { if (botWidth < best) best = botWidth; } } } } printf( %d n , best); } |
#include <bits/stdc++.h> using namespace std; const int N = 1003; const int mod = 1e9 + 7; int a[N][N]; int c[N]; int n; int sum; int main() { int i, j; scanf( %d , &n); for (i = 0; i < n; i++) for (j = 0; j < n; j++) scanf( %d , &a[i][j]); for (i = 0; i < n; i++) sum += a[i][i] * a[i][i]; sum %= 2; int m; scanf( %d , &m); int op, x; while (m--) { scanf( %d , &op); if (op == 3) { printf( %d , sum); } else { scanf( %d , &x); sum = sum - a[x][x] + (a[x][x] ^ 1); a[x][x] ^= 1; sum &= 1; } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = (int)(1e5 + 1e1); const double PI = acos(-1.0); long long a, m, t; int main() { cin >> m >> a; if (a == 0 && m > 1) { cout << No solution ; return 0; } cout << a; for (int i = 1; i < m; i++) cout << 0; return 0; } |
//////////////////////////////////////////////////////////////////
////
////
//// CRCAHB CORE BLOCK
////
////
////
//// This file is part of the APB to I2C project
////
//// http://www.opencores.org/cores/apbi2c/
////
////
////
//// Description
////
//// Implementation of APB IP core according to
////
//// crcahb IP core specification document.
////
////
////
//// To Do: Things are right here but always all block can suffer changes
////
////
////
////
////
//// Author(s): - Julio Cesar
////
/////////////////////////////////////////////////////////////////
////
////
//// Copyright (C) 2009 Authors and OPENCORES.ORG
////
////
////
//// This source file may be used and distributed without
////
//// restriction provided that this copyright statement is not
////
//// removed from the file and that any derivative work contains
//// the original copyright notice and the associated disclaimer.
////
////
//// This source file is free software; you can redistribute it
////
//// and/or modify it under the terms of the GNU Lesser General
////
//// Public License as published by the Free Software Foundation;
//// either version 2.1 of the License, or (at your option) any
////
//// later version.
////
////
////
//// This source is distributed in the hope that it will be
////
//// useful, but WITHOUT ANY WARRANTY; without even the implied
////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
////
//// PURPOSE. See the GNU Lesser General Public License for more
//// details.
////
////
////
//// You should have received a copy of the GNU Lesser General
////
//// Public License along with this source; if not, download it
////
//// from http://www.opencores.org/lgpl.shtml
////
////
///////////////////////////////////////////////////////////////////
`define size ((DATA_SIZE/4) * (2 ** (type - 1)))
module bit_reversal
#(
parameter DATA_SIZE = 32
)
(
//OUTPUTS
output [DATA_SIZE - 1 : 0] data_out,
//INPUTS
input [DATA_SIZE - 1 : 0] data_in,
input [1 : 0] rev_type
);
//Bit reversing types
localparam NO_REVERSE = 2'b00;
localparam BYTE = 2'b01;
localparam HALF_WORD = 2'b10;
localparam WORD = 2'b11;
localparam TYPES = 4;
wire [DATA_SIZE - 1 : 0] data_reversed[0 : 3];
assign data_reversed[NO_REVERSE] = data_in; //bit order not affected
generate
genvar i, type;
for(type = 1 ; type < TYPES; type = type + 1)
for(i = 0; i < DATA_SIZE; i = i + 1)
begin
if(i < `size)
assign data_reversed[type][i] = data_in[`size*((i/`size) + 1) - 1 - i];
else
assign data_reversed[type][i] = data_in[`size*((i/`size) + 1) - 1 - (i%(`size*(i/`size)))];
end
endgenerate
//Output Mux
assign data_out = data_reversed[rev_type];
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<vector<int>> moves = {{0, 1}, {1, 0}, {-1, 0}, {0, -1}}; bool isValid(int a, int b, int x, int y) { return (a >= 0 && a < x) && (b >= 0 && b < y); } bool isPath(int n, int m, vector<string>& mat) { bool isPossible = false; int cnt = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (mat[i][j] == G ) cnt++; } } if (mat[n - 1][m - 1] == # && cnt > 0) return isPossible; vector<vector<bool>> vis(n, vector<bool>(m)); queue<pair<int, int>> q; q.push({n - 1, m - 1}); vis[n - 1][m - 1] = true; while (!q.empty()) { pair<int, int> curr = q.front(); q.pop(); if (mat[curr.first][curr.second] == G ) { cnt--; } for (int i = 0; i < 4; i++) { int nx = curr.first + moves[i][0]; int ny = curr.second + moves[i][1]; if (isValid(nx, ny, n, m) && mat[nx][ny] != # && !vis[nx][ny]) { q.push({nx, ny}); vis[nx][ny] = true; } } } isPossible = cnt <= 0 ? true : false; return isPossible; } int main() { int t; cin >> t; while (t--) { int n, m; cin >> n >> m; vector<string> mat(n); for (int i = 0; i < n; i++) { cin >> mat[i]; } bool isPossible = true; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (mat[i][j] == B ) { for (int k = 0; k < 4; k++) { int nx = i + moves[k][0]; int ny = j + moves[k][1]; if (isValid(nx, ny, n, m)) { if (mat[nx][ny] == G ) { isPossible = false; break; } else if (mat[nx][ny] == . ) { mat[nx][ny] = # ; } } } } if (!isPossible) break; } if (!isPossible) break; } if (!isPossible) { cout << No << endl; } else { isPossible = isPath(n, m, mat); if (!isPossible) cout << No << endl; else cout << Yes << endl; } } } |
/*
Register
========
This is the basic state element
Parameters
----------
| Parameter | Default | Explanation |
|-----------|:-------:|------------:|
| `WIDTH` | 32 | Bitwidth of the register |
| `INITIAL_VALUE` | 32'b0 | Value the register is initialized to, if applicable |
| `RESET_VALUE` | 32'b0 | Value the register takes when `reset` is signaled |
Interface
---------
+----------+
clock >---->|> |
| register |
reset >-----| |
enable >---->| |
in_data >---->| |>----> out_data
+----------+
Notes
-----
Priority: Reset > Enable
Aggressively set inputs/parameters to **don't cares** (for example 1'bX)
in order to correctly optimize the design.
*/
// ## Implementation
module Register (
clock, reset,
enable,
in_data, out_data
);
// ### Parameters
parameter
WIDTH = 32,
INITIAL_VALUE = {WIDTH{1'b0}},
RESET_VALUE = {WIDTH{1'b0}};
// ### I/O ports
input clock;
input reset;
input enable;
input [WIDTH-1:0] in_data;
output [WIDTH-1:0] out_data;
// ### Internal wires
(* EXTRACT_ENABLE = "yes", EXTRACT_RESET = "yes" *)
reg [WIDTH-1:0] register_value;
// ### Combinational logic
assign out_data = register_value;
// ### Initial values
initial begin
register_value = INITIAL_VALUE;
// WARNING:
// DO NOT USE 'output reg Out = Initial';
// Vivado 2013.4+ silently ignores this syntax for synthesis.
end
// ### Synchronous logic
always @ (posedge clock) begin
if (reset) register_value <= RESET_VALUE;
else if (enable) register_value <= in_data;
end
endmodule
|
#include<bits/stdc++.h> #define rep(i,st,en) for(int i=st;i<=en;i++) using namespace std; typedef long long ll; int t,x,y,i,n; int main() { scanf( %d ,&t); while(t--) { scanf( %d ,&n); rep(i,1,n)scanf( %d ,&x); printf( %d n ,3*n); rep(i,1,n/2) { x=2*i-1; y=2*i; printf( 2 %d %d n ,x,y); printf( 2 %d %d n ,x,y); printf( 1 %d %d n ,x,y); printf( 2 %d %d n ,x,y); printf( 2 %d %d n ,x,y); printf( 1 %d %d n ,x,y); } //TODO } return 0; } |
/*
RC4 PRGA module implementation
Copyright Groundworks Technologies 2012-2013
Author: Alfredo Ortega
This library is free software: you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation, either
version 3 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
`include "/home/guest/docto/FPGADesign/rc4-prbs/trunk/rc4.inc"
module rc4(clk,rst,output_ready,password_input,K);
input clk; // Clock
input rst; // Reset
input [7:0] password_input; // Password input
output output_ready; // Output valid
output [7:0] K; // Output port
wire clk, rst; // clock, reset
reg output_ready;
wire [7:0] password_input;
/* RC4 PRGA */
// Key
reg [7:0] key[0:`KEY_SIZE-1];
// S array
reg [7:0] S[0:256];
reg [9:0] discardCount;
// Key-scheduling state
`define KSS_KEYREAD 4'h0
`define KSS_KEYSCHED1 4'h1
`define KSS_KEYSCHED2 4'h2
`define KSS_KEYSCHED3 4'h3
`define KSS_CRYPTO 4'h4
`define KSS_CRYPTO2 4'h5
// Variable names from http://en.wikipedia.org/wiki/RC4
reg [3:0] KSState;
reg [7:0] i; // Counter
reg [7:0] j;
reg [7:0] K;
reg [7:0] tmp;
always @ (posedge clk or posedge rst)
begin
if (rst)
begin
i <= 8'h0;
KSState <= `KSS_KEYREAD;
output_ready <= 0;
j <= 0;
end
else
case (KSState)
`KSS_KEYREAD: begin // KSS_KEYREAD state: Read key from input
if (i == `KEY_SIZE)
begin
KSState <= `KSS_KEYSCHED1;
i<=8'h00;
end
else begin
i <= i+1;
key[i] <= password_input;
$display ("rc4: key[%d] = %08X",i,password_input);
end
end
/*
for i from 0 to 255
S[i] := i
endfor
*/
`KSS_KEYSCHED1: begin // KSS_KEYSCHED1: Increment counter for S initialization
S[i] <= i;
if (i == 8'hFF)
begin
KSState <= `KSS_KEYSCHED2;
i <= 8'h00;
end
else i <= i +1;
end
/*
j := 0
for i from 0 to 255
j := (j + S[i] + key[i mod keylength]) mod 256
swap values of S[i] and S[j]
endfor
*/
`KSS_KEYSCHED2: begin // KSS_KEYSCHED2: Initialize S array
j <= (j + S[i] + key[i % `KEY_SIZE]);
KSState <= `KSS_KEYSCHED3;
end
`KSS_KEYSCHED3: begin // KSS_KEYSCHED3: S array permutation
S[i]<=S[j];
S[j]<=S[i];
if (i == 8'hFF)
begin
KSState <= `KSS_CRYPTO;
i <= 8'h01;
j <= S[1];
discardCount <= 10'h0;
output_ready <= 0; // K not valid yet
end
else begin
i <= i + 1;
KSState <= `KSS_KEYSCHED2;
end
end
/*
i := 0
j := 0
while GeneratingOutput:
i := (i + 1) mod 256
j := (j + S[i]) mod 256
swap values of S[i] and S[j]
K := S[(S[i] + S[j]) mod 256]
output K
endwhile
*/
`KSS_CRYPTO: begin
S[i] <= S[j];
S[j] <= S[i]; // We can do this because of verilog.
tmp<=S[i]+S[j];
KSState <= `KSS_CRYPTO2;
output_ready <= 0;
end
`KSS_CRYPTO2: begin
K <= S[tmp];//S[ S[i]+S[j] ];
if (discardCount<10'h600) // discard first 1536 values - SSH RC4 compliant
discardCount<=discardCount+1;
else output_ready <= 1; // Valid K at output
i <= i+1;
// Here is the secret of 1-clock: we develop all possible values of j in the future
if (j==i+1)
j <= (j + S[i]);
else
if (i==255) j <= (j + S[0]);
else j <= (j + S[i+1]);
$display ("rc4: output = %08X",K);
KSState <= `KSS_CRYPTO;
end
default: begin
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MAJ3_TB_V
`define SKY130_FD_SC_LS__MAJ3_TB_V
/**
* maj3: 3-input majority vote.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__maj3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_ls__maj3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__MAJ3_TB_V
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 15266 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w512,
w513,
w64,
w449,
w7184,
w7633,
w15266;
assign w1 = i_data0;
assign w15266 = w7633 << 1;
assign w449 = w513 - w64;
assign w512 = w1 << 9;
assign w513 = w1 + w512;
assign w64 = w1 << 6;
assign w7184 = w449 << 4;
assign w7633 = w449 + w7184;
assign o_data0 = w15266;
//multiplier_block area estimate = 4630.34883442059;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// $Id: small_fifo.v 4761 2008-12-27 01:11:00Z jnaous $
//
// Module: small_fifo.v
// Project: UNET
// Description: small fifo with no fallthrough i.e. data valid after rd is high
//
// Change history:
// 7/20/07 -- Set nearly full to 2^MAX_DEPTH_BITS - 1 by default so that it
// goes high a clock cycle early.
// 11/2/09 -- Modified to have both prog threshold and almost full
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module small_fifo
#(parameter WIDTH = 72,
parameter MAX_DEPTH_BITS = 3,
parameter PROG_FULL_THRESHOLD = 2**MAX_DEPTH_BITS - 1
)
(
input [WIDTH-1:0] din, // Data in
input wr_en, // Write enable
input rd_en, // Read the next word
output reg [WIDTH-1:0] dout, // Data out
output full,
output nearly_full,
output prog_full,
output empty,
input reset,
input clk
);
parameter MAX_DEPTH = 2 ** MAX_DEPTH_BITS;
reg [WIDTH-1:0] queue [MAX_DEPTH - 1 : 0];
reg [MAX_DEPTH_BITS - 1 : 0] rd_ptr;
reg [MAX_DEPTH_BITS - 1 : 0] wr_ptr;
reg [MAX_DEPTH_BITS : 0] depth;
// Sample the data
always @(posedge clk)
begin
if (wr_en)
queue[wr_ptr] <= din;
if (rd_en)
dout <=
// synthesis translate_off
#1
// synthesis translate_on
queue[rd_ptr];
end
always @(posedge clk)
begin
if (reset) begin
rd_ptr <= 'h0;
wr_ptr <= 'h0;
depth <= 'h0;
end
else begin
if (wr_en) wr_ptr <= wr_ptr + 'h1;
if (rd_en) rd_ptr <= rd_ptr + 'h1;
if (wr_en & ~rd_en) depth <=
// synthesis translate_off
#1
// synthesis translate_on
depth + 'h1;
else if (~wr_en & rd_en) depth <=
// synthesis translate_off
#1
// synthesis translate_on
depth - 'h1;
end
end
//assign dout = queue[rd_ptr];
assign full = depth == MAX_DEPTH;
assign prog_full = (depth >= PROG_FULL_THRESHOLD);
assign nearly_full = depth >= MAX_DEPTH-1;
assign empty = depth == 'h0;
// synthesis translate_off
always @(posedge clk)
begin
if (wr_en && depth == MAX_DEPTH && !rd_en)
$display($time, " ERROR: Attempt to write to full FIFO: %m");
if (rd_en && depth == 'h0)
$display($time, " ERROR: Attempt to read an empty FIFO: %m");
end
// synthesis translate_on
endmodule // small_fifo
/* vim:set shiftwidth=3 softtabstop=3 expandtab: */
|
module RAM (
input wire rst,
input wire clk,
input wire[31:0] addrIn,
input wire[15:0] write,
input wire we,
output wire[15:0] read,
input wire re,
input wire[1:0] inMask,
input wire[1:0] outMask,
output wire ready,
output wire[10:0] lcdPins,
output wire[15:0] page,
input wire[3:0] switch,
output wire[31:0] bp0Addr, bp1Addr, bp2Addr, bp3Addr, bpAddr, keyboardAddr, irAddr,
output wire bp0En, bp1En, bp2En, bp3En, keyboardEn, irEn,
output wire[15:0] lcdIn
);
wire[31:0] addr = (re || we)? addrIn : 32'h00000000;
wire isStack = addr <= 32'hD000FFFF && addr >= 32'hD0000000;
wire isInstr = addr <= 32'h000FFFFF;
wire isLCD = addr == 32'hFFFF0000 || addr == 32'hFFFF0001;
wire isSwitch = addr == 32'hFFFF0002;
wire isFastMem = addr >= 32'hFFFF1000 && addr <= 32'hFFFF101F;
wire isBPRegs = addr >= 32'hFFFFF000 && addr <= 32'hFFFFF015;
wire isInt = addr >= 32'hFFFFFFF6 && addr <= 32'hFFFFFFFF;
wire isHeap = addr <= 32'h8FFFFFFF && addr >= 32'h10000000;
wire[15:0] romOut, ram1Out, ram2Out;
wire[1:0] addrLeast = {2{addr[0]}};
wire[7:0] write8 = (inMask == 2'b01)? write[7:0] :
(inMask == 2'b10)? write[15:8] :
write[7:0];
wire[15:0] write8S = outMask == (2'b01 ^ addrLeast)? {8'h00, write8} :
outMask == (2'b10 ^ addrLeast)? {write8, 8'h00} :
addrLeast? {write[7:0], write[15:8]} : write;
wire[15:0] mask = {{8{byteenable[1]}}, {8{byteenable[0]}}};
wire[1:0] byteenable = addrLeast? {outMask[0], outMask[1]}: outMask;
InstrROM rom (
.address (addr[10:1]),
.clock (clk),
.q (romOut)
);
wire[15:0] stackAddr = addr[15:0];
StackRAM ram1 (
.address (stackAddr[10:1]),
.clock (clk),
.data (write8S),
.wren (we && isStack),
.byteena(byteenable),
.q (ram1Out)
);
wire[30:0] heapAddr = addr[30:0];
HeapRAM ram2 (
.address (heapAddr[12:1]),
.clock (clk),
.data (write8S),
.wren (we && isHeap),
.byteena(byteenable),
.q (ram2Out)
);
reg[7:0] lcdData = 8'h00;
reg[2:0] lcdCtrl = 3'b000;
assign lcdPins = {lcdCtrl, lcdData};
assign lcdIn = ((write8S & mask) | ({5'b0, lcdCtrl, lcdData} & ~mask));
always @ (posedge clk) begin
if (rst) begin
lcdData <= 8'h00;
lcdCtrl <= 3'b000;
end else if (we && isLCD) begin
{lcdCtrl, lcdData} <= lcdIn[10:0];
end
end
reg[15:0] keyboardAddrHigh = 16'h0000;
reg[15:0] keyboardAddrLow = 16'h0000;
reg enKeyboard = 1;
assign keyboardAddr = {keyboardAddrHigh, keyboardAddrLow};
assign keyboardEn = enKeyboard;
reg[15:0] irAddrHigh = 16'h0000;
reg[15:0] irAddrLow = 16'h0000;
reg enIR = 1;
assign irAddr = {irAddrHigh, irAddrLow};
assign irEn = enIR;
wire[15:0] intEnWrite = (write8S & mask) | ({7'b0, enKeyboard, 7'b0, enIR} & ~mask);
always @ (posedge clk) begin
if (rst) begin
keyboardAddrHigh <= 16'h0000;
keyboardAddrLow <= 16'h0000;
enKeyboard <= 1'b0;
irAddrHigh <= 16'h0000;
irAddrLow <= 16'h0000;
enIR <= 1'b0;
end else if (we) begin
if (addr[31:1] == 31'h7FFFFFFB) begin // FFFFFFF6/7
enIR <= |(intEnWrite[7:0]);
enKeyboard <= |(intEnWrite[15:8]);
end else if (addr[31:1] == 31'h7FFFFFFC) // FFFFFFF8/9
irAddrLow <= (write8S & mask) | (irAddrLow & ~mask);
else if (addr[31:1] == 31'h7FFFFFFD) // FFFFFFFA/B
irAddrHigh <= (write8S & mask) | (irAddrHigh & ~mask);
else if (addr[31:1] == 31'h7FFFFFFE) // FFFFFFFC/D
keyboardAddrLow <= (write8S & mask) | (keyboardAddrLow & ~mask);
else if (addr[31:1] == 31'h7FFFFFFF) // FFFFFFFE/F
keyboardAddrHigh <= (write8S & mask) | (keyboardAddrHigh & ~mask);
end
end
reg[15:0] breakPoint0High, breakPoint0Low;
reg[15:0] breakPoint1High, breakPoint1Low;
reg[15:0] breakPoint2High, breakPoint2Low;
reg[15:0] breakPoint3High, breakPoint3Low;
reg[15:0] breakPointAddrHigh, breakPointAddrLow;
reg[3:0] enBreakPoints;
assign bp0Addr = {breakPoint0High, breakPoint0Low};
assign bp1Addr = {breakPoint1High, breakPoint1Low};
assign bp2Addr = {breakPoint2High, breakPoint2Low};
assign bp3Addr = {breakPoint3High, breakPoint3Low};
assign bpAddr = {breakPointAddrHigh, breakPointAddrLow};
assign bp0En = enBreakPoints[0];
assign bp1En = enBreakPoints[1];
assign bp2En = enBreakPoints[2];
assign bp3En = enBreakPoints[3];
wire[15:0] bpEnIn = ((write8S & mask) | ({12'b0, enBreakPoints} & ~mask));
always @ (posedge clk) begin
if (rst) begin
breakPoint0High <= 16'h0000;
breakPoint0Low <= 16'h0000;
breakPoint1High <= 16'h0000;
breakPoint1Low <= 16'h0000;
breakPoint2High <= 16'h0000;
breakPoint2Low <= 16'h0000;
breakPoint3High <= 16'h0000;
breakPoint3Low <= 16'h0000;
breakPointAddrHigh <= 16'h0000;
breakPointAddrLow <= 16'h0000;
enBreakPoints <= 4'b0000;
end
else if (we) begin
if (addr[31:1] == 31'h7FFFF800) // FFFFF000/1
enBreakPoints <= bpEnIn[3:0];
else if (addr[31:1] == 31'h7FFFF801) // FFFFF002/3
breakPoint0Low <= (write8S & mask) | (breakPoint0Low & ~mask);
else if (addr[31:1] == 31'h7FFFF802) // FFFFF004/5
breakPoint0High <= (write8S & mask) | (breakPoint0High & ~mask);
else if (addr[31:1] == 31'h7FFFF803) // FFFFF006/7
breakPoint1Low <= (write8S & mask) | (breakPoint1Low & ~mask);
else if (addr[31:1] == 31'h7FFFF804) // FFFFF008/9
breakPoint1High <= (write8S & mask) | (breakPoint1High & ~mask);
else if (addr[31:1] == 31'h7FFFF805) // FFFFF00A/B
breakPoint2Low <= (write8S & mask) | (breakPoint2Low & ~mask);
else if (addr[31:1] == 31'h7FFFF806) // FFFFF00C/D
breakPoint2High <= (write8S & mask) | (breakPoint2High & ~mask);
else if (addr[31:1] == 31'h7FFFF807) // FFFFF00E/F
breakPoint3Low <= (write8S & mask) | (breakPoint3Low & ~mask);
else if (addr[31:1] == 31'h7FFFF808) // FFFFF010/1
breakPoint3High <= (write8S & mask) | (breakPoint3High & ~mask);
else if (addr[31:1] == 31'h7FFFF809) // FFFFF012/3
breakPointAddrLow <= (write8S & mask) | (breakPointAddrLow & ~mask);
else if (addr[31:1] == 31'h7FFFF80A) // FFFFF014/5
breakPointAddrHigh <= (write8S & mask) | (breakPointAddrHigh & ~mask);
end
end
reg[15:0] fastMem [0:14];
assign page = fastMem[0];
integer i;
always @ (posedge clk) begin
if (rst) begin
for (i = 0; i <= 14; i = i + 1)
fastMem[i] <= 16'b0;
end else if (we && isFastMem)
fastMem[addr[4:1]] <= (write8S & mask) | (fastMem[addr[4:1]] & ~mask);;
end
wire[15:0] readNoSwap = isStack? ram1Out :
isHeap? ram2Out :
isInstr? romOut :
isSwitch? switch :
isFastMem? fastMem[addr[3:0]] :
16'h0000;
assign read = addr[0]? {readNoSwap[7:0], readNoSwap[15:8]} : readNoSwap;
reg isReading1 = 0;
reg isReading2 = 0;
reg regReady = 0;
assign ready = 1;
/*always @ (posedge clk)
begin
isReading1 <= re;
isReading2 <= isReading1;
if (isReading1 && !isReading2)
regReady <= 1;
else if (!isReading1 && isReading2)
regReady <= 0;
else if (isReading1 && isReading2)
regReady <= !regReady;
end*/
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, i, a, b, aux1, aux2, cs, cd, mij, rsp; char s[200005]; int u[200005], r[200005], l[200005], d[200005]; int main() { ios::sync_with_stdio(false); cin >> n; cin >> s; cin >> a >> b; if (abs(a) + abs(b) > n) { cout << -1; return 0; } if ((abs(a) + abs(b)) % 2 != n % 2) { cout << -1; return 0; } for (i = 0; i < n; i++) { if (s[i] == U ) u[i + 1]++; if (s[i] == D ) d[i + 1]++; if (s[i] == L ) l[i + 1]++; if (s[i] == R ) r[i + 1]++; } for (i = 1; i <= n; i++) { u[i] += u[i - 1]; r[i] += r[i - 1]; d[i] += d[i - 1]; l[i] += l[i - 1]; } if (u[n] - d[n] == b && r[n] - l[n] == a) { cout << 0; return 0; } rsp = n; for (i = 1; i <= n; i++) { cs = i; cd = n; while (cs <= cd) { mij = (cs + cd) >> 1; aux1 = r[i - 1]; aux1 -= l[i - 1]; aux1 += r[n] - r[mij]; aux1 -= l[n] - l[mij]; aux2 = u[i - 1]; aux2 -= d[i - 1]; aux2 += u[n] - u[mij]; aux2 -= d[n] - d[mij]; if (abs(aux1 - a) + abs(aux2 - b) <= mij - i + 1) { rsp = min(rsp, mij - i + 1); cd = mij - 1; } else cs = mij + 1; } } cout << rsp; } |
#include <bits/stdc++.h> using namespace std; long long a[200010]; long long vis[200010]; long long cnt[200010]; long long n; long long max_n = 0; void solve(long long pos) { vis[pos]++; long long temp1 = pos; long long temp2 = pos; long long step1 = 0; long long step2 = 0; while (temp1 <= max_n) { temp1 <<= 1; step1++; vis[temp1]++; cnt[temp1] += step1; } while (temp2) { if ((temp2 & 1) && (temp2 != 1)) { temp2 >>= 1; step2++; vis[temp2]++; cnt[temp2] += step2; long long temp3 = temp2; long long step3 = step2; while (temp3 <= max_n) { temp3 <<= 1; step3++; vis[temp3]++; cnt[temp3] += step3; } } else { temp2 >>= 1; step2++; vis[temp2]++; cnt[temp2] += step2; } } } int main() { scanf( %lld , &n); for (long long i = 1; i <= n; i++) { scanf( %lld , &a[i]); max_n = max(a[i], max_n); } memset(vis, 0, sizeof(vis)); memset(cnt, 0, sizeof(cnt)); for (long long i = 1; i <= n; i++) solve(a[i]); long long ans = 1 << 29; for (long long i = 1; i <= 2 * max_n - 1; i++) { if (vis[i] == n) ans = min(ans, cnt[i]); } printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; void SieveOfErat() { bool prime[1000001]; memset(prime, true, sizeof(prime)); for (long long p = 2; p * p <= 1000000; p++) { if (prime[p] == true) { for (long long i = p * 2; i <= 1000000; i += p) prime[i] = false; } } } long long gcd(long long x, long long y) { if (x == 0) { return y; } else return gcd(x % y, y); } long long n, m; vector<vector<long long> > v; vector<long long> res; signed main() { ios_base::sync_with_stdio(false); cin >> n >> m; v.assign(n, vector<long long>(m, 0)); for (long long i = 0; i < n; ++i) { for (long long j = 0; j < m; ++j) cin >> v[i][j]; } if (n < m) { for (long long i = 0; i < n; ++i) { long long mi = 600; for (long long j = 0; j < m; ++j) mi = min(mi, v[i][j]); if (mi == 0) continue; for (long long j = 0; j < mi; ++j) res.push_back(i + 1); for (long long j = 0; j < m; ++j) v[i][j] -= mi; } for (long long j = 0; j < m; ++j) { long long mi = 600; for (long long i = 0; i < n; ++i) mi = min(mi, v[i][j]); if (mi == 0) continue; for (long long i = 0; i < mi; ++i) res.push_back(-(j + 1)); for (long long i = 0; i < n; ++i) v[i][j] -= mi; } } else { for (long long j = 0; j < m; ++j) { long long mi = 600; for (long long i = 0; i < n; ++i) mi = min(mi, v[i][j]); if (mi == 0) continue; for (long long i = 0; i < mi; ++i) res.push_back(-(j + 1)); for (long long i = 0; i < n; ++i) v[i][j] -= mi; } for (long long i = 0; i < n; ++i) { long long mi = 600; for (long long j = 0; j < m; ++j) mi = min(mi, v[i][j]); if (mi == 0) continue; for (long long j = 0; j < mi; ++j) res.push_back(i + 1); for (long long j = 0; j < m; ++j) v[i][j] -= mi; } } long long sum = 0; for (long long i = 0; i < n; ++i) for (long long j = 0; j < m; ++j) sum += v[i][j]; if (sum > 0) { cout << -1 << endl; return 0; } cout << res.size() << n ; for (long long i = 0; i < res.size(); ++i) { if (res[i] > 0) cout << row << res[i] << n ; else cout << col << -res[i] << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, m, ans, w[300000], d[300000], a, b; int main() { ios_base::sync_with_stdio(0); cin >> n >> m; for (int i = 1; i <= n; i++) { w[i] = i; d[i] = 1; } ans = 1; for (int i = 1; i <= m; i++) { cin >> a >> b; while (a != w[a]) a = w[a]; while (b != w[b]) b = w[b]; if (a != b) { if (d[a] > d[b]) { w[b] = a; } else { w[a] = b; if (d[a] == d[b]) d[b]++; } } else ans = ans * 2 % 1000000009; cout << (ans + 1000000009 - 1) % 1000000009 << endl; } cin.get(); cin.get(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_SYMBOL_V
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_SYMBOL_V
/**
* lpflow_lsbuf_lh_isowell: Level-shift buffer, low-to-high, isolated
* well on input buffer, no taps,
* double-row-height cell.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
wire LOWLVPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int n; vector<pair<int, int> > v; long long dp[2][5001][51][51]; const long long oo = 1e16; int main() { cin >> n; v.resize(n); for (auto &x : v) cin >> x.first; int total = 0; for (auto &x : v) { cin >> x.second; total += x.second; } vector<int> bef(n, 1); sort(v.rbegin(), v.rend()); for (int i = 1; i < n; ++i) if (v[i - 1].first == v[i].first) bef[i] += bef[i - 1]; bef.push_back(1); v.push_back(make_pair(-1, -1)); for (int i = n; i >= 0; --i) { for (int rem = total; rem >= 0; --rem) { for (int g = 0; g <= i; ++g) { int me = bef[i]; for (int cg = 0; cg < me; ++cg) { long long ret = oo; if (i == n) { if (rem == 0) ret = 0; } else { const bool ch = v[i + 1].first != v[i].first; if (g > 0) { if (ch) ret = dp[1 & ~i][rem][g - 1 + cg][0]; else ret = dp[1 & ~i][rem][g - 1][cg]; } if (rem >= v[i].second) { if (ch) ret = min(ret, v[i].first + dp[1 & ~i][rem - v[i].second][g + cg + 1][0]); else ret = min( ret, v[i].first + dp[1 & ~i][rem - v[i].second][g][cg + 1]); } } dp[i & 1][rem][g][cg] = ret; } } } } pair<long long, long long> ans; long long res = -1; for (int i = 1; i <= total; ++i) { long long cur = dp[0][i][0][0]; if (cur == oo) continue; if (res == -1) { ans.first = cur; ans.second = i; res = 0; } else { if (ans.first * i <= cur * ans.second) continue; ans.first = cur; ans.second = i; } } res = ans.first * 10000; res = (res + ans.second - 1) / ans.second; int add = res % 10 > 0; res = res / 10 + add; cout << res << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FAHCIN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__FAHCIN_BEHAVIORAL_PP_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__fahcin (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire ci ;
wire xor0_out_SUM ;
wire pwrgood_pp0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT ;
wire pwrgood_pp1_out_COUT;
// Name Output Other arguments
not not0 (ci , CIN );
xor xor0 (xor0_out_SUM , A, B, ci );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND);
buf buf0 (SUM , pwrgood_pp0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, ci );
and and2 (b_ci , B, ci );
or or0 (or0_out_COUT , a_b, a_ci, b_ci );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_COUT, or0_out_COUT, VPWR, VGND);
buf buf1 (COUT , pwrgood_pp1_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__FAHCIN_BEHAVIORAL_PP_V |
//input control module;
//by jzc 20101022;
`timescale 1ns/1ns
module input_ctrl(
clk,
reset,
crc_check_wrreq,//data fifo;
crc_check_data,
crc_usedw,
crc_result_wrreq,//crc check fifo;
crc_result,
um2cdp_tx_enable,//to user module;
cdp2um_data_valid,
cdp2um_data,
input2output_wrreq,//to output control module;
input2output_data,
input2output_usedw,
um2cdp_path
);
input clk;
input reset;
input crc_check_wrreq;
input [138:0]crc_check_data;
output [7:0]crc_usedw;
input crc_result_wrreq;
input crc_result;
input um2cdp_tx_enable;
output cdp2um_data_valid;
output [138:0]cdp2um_data;
output input2output_wrreq;
output [138:0]input2output_data;
input [7:0]input2output_usedw;
input um2cdp_path; //added by mxl_ccz_lq_0423 to define the direction of packets(to CDP itself or to UM);
wire [7:0]crc_usedw;
reg cdp2um_data_valid;
reg [138:0]cdp2um_data;
reg input2output_wrreq;
reg [138:0]input2output_data;
reg [138:0]data_reg;//storage the data,judge the last 4 byte,discard the crc;
reg level2_fifo_rdreq;
wire [138:0]level2_fifo_q;
reg flag_fifo_rdreq;
wire flag_fifo_q;
wire flag_fifo_empty;
reg [1:0]current_state;
parameter idle=2'b0,
transmit=2'b01,
discard=2'b10,
over_4byte=2'b11;
always@(posedge clk or negedge reset)
if(!reset)
begin
level2_fifo_rdreq<=1'b0;
flag_fifo_rdreq<=1'b0;
cdp2um_data_valid<=1'b0;
current_state<=idle;
end
else
begin
case(current_state)
idle:
begin
flag_fifo_rdreq<=1'b0;
level2_fifo_rdreq<=1'b0;
cdp2um_data_valid<=1'b0;
input2output_wrreq<=1'b0;
if(um2cdp_tx_enable)//user module needs data;
begin
if((um2cdp_path == 1'b1 && input2output_usedw<8'd161) || um2cdp_path == 1'b0)//input_output_fifo can storage a full pkt or the packets are sent to UM;
begin
if(!flag_fifo_empty)//flag fifo is not empty;
begin
if(flag_fifo_q==1'b1)//the data is valid;
begin
flag_fifo_rdreq<=1'b1;
level2_fifo_rdreq<=1'b1;
//cdp2um_data_valid<=1'b1;
//cdp2um_data<=level2_fifo_q;
//input2output_wrreq<=1'b1;
//input2output_data<=level2_fifo_q;
current_state<=transmit;
end
else//the data is invalid,so discard;
begin
flag_fifo_rdreq<=1'b1;
level2_fifo_rdreq<=1'b1;
current_state<=discard;
end
end
else
begin
current_state<=idle;
end
end
else//can't storage a full pkt;
begin
current_state<=idle;
end
end
else//
begin
current_state<=idle;
end
end//end idle;
transmit:
begin
flag_fifo_rdreq<=1'b0;
level2_fifo_rdreq<=1'b0;
cdp2um_data_valid<=1'b0;
input2output_wrreq<=1'b0;
data_reg<=level2_fifo_q;
if(level2_fifo_q[138:136]==3'b101)//header;
begin
level2_fifo_rdreq<=1'b1;
cdp2um_data_valid<=1'b0;
cdp2um_data<=data_reg;
input2output_wrreq<=1'b0;
input2output_data<=data_reg;
current_state<=transmit;
end
else if(level2_fifo_q[138:136]==3'b110)//tail;
begin
level2_fifo_rdreq<=1'b0;
if(level2_fifo_q[135:132]>4'b0011)//the last word have >4bytes valid data;
begin
cdp2um_data_valid<=1'b1;
cdp2um_data<=data_reg;
input2output_wrreq<=1'b1;
input2output_data<=data_reg;
current_state<=over_4byte;
end
else if(level2_fifo_q[135:132]==4'b0011)
begin
cdp2um_data_valid<=1'b1;
cdp2um_data<=data_reg;
cdp2um_data[138:136]<=3'b110;
cdp2um_data[135:132]<=4'b1111;
input2output_wrreq<=1'b1;
input2output_data<=data_reg;
input2output_data[138:136]<=3'b110;
input2output_data[135:132]<=4'b1111;
current_state<=idle;
end
else
begin
cdp2um_data_valid<=1'b1;
cdp2um_data<=data_reg;
cdp2um_data[138:136]<=3'b110;
cdp2um_data[135:132]<=4'b1111-(4'b0011-level2_fifo_q[135:132]);
input2output_wrreq<=1'b1;
input2output_data<=data_reg;
input2output_data[138:136]<=3'b110;
input2output_data[135:132]<=4'b1111-(4'b0011-level2_fifo_q[135:132]);
current_state<=idle;
end
end
else//middle;
begin
level2_fifo_rdreq<=1'b1;
cdp2um_data_valid<=1'b1;
cdp2um_data<=data_reg;
input2output_wrreq<=1'b1;
input2output_data<=data_reg;
current_state<=transmit;
end
end//end transmit;
discard:
begin
flag_fifo_rdreq<=1'b0;
level2_fifo_rdreq<=1'b0;
if(level2_fifo_q[138:136]==3'b110)//tail;
begin
//level2_fifo_rdreq<=1'b1;
current_state<=idle;
end
else//middle;
begin
level2_fifo_rdreq<=1'b1;
current_state<=discard;
end
end
over_4byte:
begin
cdp2um_data_valid<=1'b1;
cdp2um_data<=data_reg;
cdp2um_data[135:132]<=data_reg[135:132]-4'b0100;
input2output_wrreq<=1'b1;
input2output_data<=data_reg;
input2output_data[135:132]<=data_reg[135:132]-4'b0100;
current_state<=idle;
end
default:
begin
current_state<=idle;
end
endcase//endcase;
end
level2_256_139 level2_256_139(//level2 data fifo;
.aclr(!reset),
.clock(clk),
.data(crc_check_data),
.rdreq(level2_fifo_rdreq),
.wrreq(crc_check_wrreq),
.q(level2_fifo_q),
.usedw(crc_usedw)
);
rx_64_1 rx_64_1(//crc check result fifo;
.aclr(!reset),
.clock(clk),
.data(crc_result),
.rdreq(flag_fifo_rdreq),
.wrreq(crc_result_wrreq),
.empty(flag_fifo_empty),
.q(flag_fifo_q)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DECAPKAPWR_PP_SYMBOL_V
`define SKY130_FD_SC_LP__DECAPKAPWR_PP_SYMBOL_V
/**
* decapkapwr: Decoupling capacitance filler on keep-alive rail.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__decapkapwr (
//# {{power|Power}}
input KAPWR,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DECAPKAPWR_PP_SYMBOL_V
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.7
// \ \ Application: MIG
// / / Filename: rd_bitslip.v
// /___/ /\ Date Last Modified: $Date: 2010/10/05 16:43:09 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// Shifts and delays data from ISERDES, in both memory clock and internal
// clock cycles. Used to uniquely shift/delay each byte to align all bytes
// in data word
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: rd_bitslip.v,v 1.1 2010/10/05 16:43:09 mishra Exp $
**$Date: 2010/10/05 16:43:09 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_7/data/dlib/virtex6/ddr3_sdram/verilog/rtl/phy/rd_bitslip.v,v $
******************************************************************************/
`timescale 1ps/1ps
module rd_bitslip #
(
parameter TCQ = 100
)
(
input clk,
input [1:0] bitslip_cnt,
input [1:0] clkdly_cnt,
input [5:0] din,
output reg [3:0] qout
);
reg din2_r;
reg [3:0] slip_out;
reg [3:0] slip_out_r;
reg [3:0] slip_out_r2;
reg [3:0] slip_out_r3;
//***************************************************************************
always @(posedge clk)
din2_r <= #TCQ din[2];
// Can shift data from ISERDES from 0-3 fast clock cycles
// NOTE: This is coded combinationally, in order to allow register to
// occur after MUXing of delayed outputs. Timing may be difficult to
// meet on this logic, if necessary, the register may need to be moved
// here instead, or another register added.
always @(bitslip_cnt or din or din2_r)
case (bitslip_cnt)
2'b00: // No slip
slip_out = {din[3], din[2], din[1], din[0]};
2'b01: // Slip = 0.5 cycle
slip_out = {din[4], din[3], din[2], din[1]};
2'b10: // Slip = 1 cycle
slip_out = {din[5], din[4], din[3], din[2]};
2'b11: // Slip = 1.5 cycle
slip_out = {din2_r, din[5], din[4], din[3]};
endcase
// Can delay up to 3 additional internal clock cycles - this accounts
// not only for delays due to DRAM, PCB routing between different bytes,
// but also differences within the FPGA - e.g. clock skew between different
// I/O columns, and differences in latency between different circular
// buffers or whatever synchronization method (FIFO) is used to get the
// data into the global clock domain
always @(posedge clk) begin
slip_out_r <= #TCQ slip_out;
slip_out_r2 <= #TCQ slip_out_r;
slip_out_r3 <= #TCQ slip_out_r2;
end
always @(posedge clk)
case (clkdly_cnt)
2'b00: qout <= #TCQ slip_out;
2'b01: qout <= #TCQ slip_out_r;
2'b10: qout <= #TCQ slip_out_r2;
2'b11: qout <= #TCQ slip_out_r3;
endcase
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T, typename U> inline void smin(T &a, U b) { if (a > b) a = b; } template <typename T, typename U> inline void smax(T &a, U b) { if (a < b) a = b; } inline void gn(long long &first) { int sg = 1; char c; while (((c = getchar()) < 0 || c > 9 ) && c != - ) ; c == - ? (sg = -1, first = 0) : (first = c - 0 ); while ((c = getchar()) >= 0 && c <= 9 ) first = first * 10 + c - 0 ; first *= sg; } inline void gn(int &first) { long long t; gn(t); first = t; } inline void gn(unsigned long long &first) { long long t; gn(t); first = t; } inline void gn(double &first) { double t; scanf( %lf , &t); first = t; } inline void gn(long double &first) { double t; scanf( %lf , &t); first = t; } int power(int a, int b, int m, int ans = 1) { for (; b; b >>= 1, a = 1LL * a * a % m) if (b & 1) ans = 1LL * ans * a % m; return ans; } int N, M, E, W; int dis[101000]; queue<int> Q; int pre[101000], edg[101000][3], cnt[101000], val[101000]; map<pair<int, int>, int> state, flag; vector<int> adj[101000]; int len = 0x3f3f3f3f, tot; void Dijk(int s) { memset(dis, 0x3f, sizeof(dis)); Q.push(s); dis[s] = 0; cnt[s] = 0; val[s] = W; while (!Q.empty()) { int u = Q.front(); Q.pop(); for (int i = 0; i < adj[u].size(); i++) { int v = adj[u][i], k; if (!state[pair<int, int>(u, v)]) k = val[u] + 1; else k = val[u] - 1; if (dis[v] > dis[u] + 1) { dis[v] = dis[u] + 1; pre[v] = u; val[v] = k; Q.push(v); } else if (dis[v] == dis[u] + 1 && val[v] > k) { val[v] = k; pre[v] = u; Q.push(v); } } } } int main() { int u, v, w; scanf( %d%d , &N, &M); for (int i = 0; i < M; i++) { scanf( %d%d%d , &u, &v, &w); adj[u].push_back(v); adj[v].push_back(u); state[pair<int, int>(u, v)] = w; state[pair<int, int>(v, u)] = w; edg[i][0] = u; edg[i][1] = v; edg[i][2] = w; W += w; } Dijk(1); u = N; while (u != 1) { flag[pair<int, int>(u, pre[u])] = 1; flag[pair<int, int>(pre[u], u)] = 1; u = pre[u]; } tot = 0; for (int i = 0; i < M; i++) { u = edg[i][0]; v = edg[i][1]; w = edg[i][2]; if (!flag[pair<int, int>(u, v)] && w == 1) tot++; else if (flag[pair<int, int>(u, v)] && w == 0) tot++; } printf( %d n , tot); for (int i = 0; i < M; i++) { u = edg[i][0]; v = edg[i][1]; w = edg[i][2]; if (!flag[pair<int, int>(u, v)] && w == 1) { printf( %d %d 0 n , u, v); } else if (flag[pair<int, int>(u, v)] && w == 0) { printf( %d %d 1 n , u, v); } } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, k, a[200], b[200], i, j, DP[3 * 10000]; int main() { cin >> n >> k; for (i = 1; i <= n; i++) cin >> a[i]; for (i = 1; i <= n; i++) cin >> b[i], b[i] *= k; for (j = 10000; j >= -10000; j--) DP[j + 10000] = -(10000 * 10000); DP[10000] = 0; for (i = 1; i <= n; i++) if (a[i] - b[i] > 0) { for (j = 10000; j >= -10000; j--) if (j + 10000 + a[i] - b[i] >= 0 && j + 10000 + a[i] - b[i] <= 2 * 10000) DP[j + 10000 + a[i] - b[i]] = max(DP[j + 10000] + a[i], DP[j + 10000 + a[i] - b[i]]); } else { for (j = -10000; j <= 10000; j++) if (j + 10000 + a[i] - b[i] >= 0 && j + 10000 + a[i] - b[i] <= 2 * 10000) DP[j + 10000 + a[i] - b[i]] = max(DP[j + 10000] + a[i], DP[j + 10000 + a[i] - b[i]]); } if (!DP[10000]) cout << -1 << endl; else cout << DP[10000] << endl; } |
/*
* Copyright (c) 2001 Peter Bain
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/* This is based on PR#124. */
`timescale 1ns/1ns
module paramtest(clk, dat);
parameter dat_width = 32;
input clk;
output [dat_width-1:0] dat;
reg [dat_width-1:0] dat;
reg [4-1:0] exp_dat;
parameter pay_init = 32'h01020304;
parameter pay_inc = 32'h01010101;
parameter cell_size = (53 * 8);
parameter transfers = cell_size/dat_width + ((cell_size%dat_width)?1:0);
initial begin
exp_dat = 0;
dat = 0;
end
initial begin
#10;
for (exp_dat = 0; exp_dat != 4'hf; exp_dat = exp_dat + 1) begin
dat <= exp_dat;
#1
if (dat !== exp_dat) begin
$display("ERROR: dat = %h, exp_dat = %h", dat, exp_dat);
end else begin
$display("OKAY: dat = %h, exp_dat = %h", dat, exp_dat);
end
end
end
endmodule
|
#include <bits/stdc++.h> #pragma gcc optimize( Ofast ) using namespace std; inline void input(int &_x) { _x = 0; int _tmp = 1; char _tc = getchar(); while ((_tc < 0 || _tc > 9 ) && _tc != - ) _tc = getchar(); if (_tc == - ) _tc = getchar(), _tmp = -1; while (_tc >= 0 && _tc <= 9 ) _x = _x * 10 + (_tc - 48), _tc = getchar(); _x *= _tmp; } int root[400009], tag[400009]; int aa[100009]; inline void build(int id, int l, int r) { if (l == r) { root[id] = aa[l]; return; } int mid = (l + r) >> 1; build((id << 1), l, mid); build((id << 1) + 1, mid + 1, r); root[id] = max(root[(id << 1)], root[(id << 1) + 1]); } inline void push(int id) { root[id] += tag[id]; tag[(id << 1)] += tag[id]; tag[(id << 1) + 1] += tag[id]; tag[id] = 0; } inline void modify(int id, int l, int r, int ql, int qr, int v) { if (tag[id]) push(id); if (ql <= l && r <= qr) { tag[id] += v; push(id); return; } if (qr < l || r < ql) return; int mid = (l + r) >> 1; modify((id << 1), l, mid, ql, qr, v); modify((id << 1) + 1, mid + 1, r, ql, qr, v); root[id] = max(root[(id << 1)], root[(id << 1) + 1]); } int n, m; vector<int> seg[100009]; bitset<100009> vis; inline bool cmp(int a, int b) { return aa[a] < aa[b]; } signed main() { int ma = -1; input(n); input(m); for (int i = 1; i < n + 1; ++i) input(aa[i]), ma = max(ma, aa[i]); vector<pair<int, int> > v(m), w; for (auto &i : v) input(i.first), input(i.second); for (int i = 1; i < n + 1; ++i) w.emplace_back(aa[i], i); sort((w).begin(), (w).end()); int ans = -1, p = 0; build(1, 1, n); for (int i = 1; i < n + 1; ++i) for (int j = 0; j < m; ++j) if (v[j].first <= i && i <= v[j].second) seg[i].emplace_back(j); for (int _ = 0; _ < n; ++_) { int i = w[_].second; if (ans > ma - (aa[i] - (int)(seg[i]).size())) continue; int cnt = 0; for (auto &j : seg[i]) modify(1, 1, n, v[j].first, v[j].second, -1), ++cnt; if (root[1] - (aa[i] - cnt) > ans) { ans = root[1] - (aa[i] - cnt); p = i; } for (auto &j : seg[i]) modify(1, 1, n, v[j].first, v[j].second, 1); } cout << ans << n << (int)(seg[p]).size() << n ; for (auto &i : seg[p]) cout << i + 1 << ; } |
#include <bits/stdc++.h> using namespace std; typedef long long arr64[200020]; int n, tn, tS, qS = 1; pair<int, long long> pr[200020]; arr64 pX, pY, K, B; int main() { long long s; scanf( %d%I64d , &n, &s); for (int i = 1; i <= n; i++) scanf( %d%d , &pr[i].first, &pr[i].second); sort(pr + 1, pr + n + 1); pr[++n] = make_pair((int)1e9, s); for (int i = 1; i <= n; i++) if (i == 1 || pr[i].first > pr[i - 1].first) { while (tn > 0 && pr[i].second <= pr[tn].second) tn--; pr[++tn] = pr[i]; } K[tS = 1] = pr[1].first; for (int i = 2; i <= tn; i++) { qS = min(qS, tS); while (qS < tS && (((pr[i].second - B[qS + 1]) / (K[qS + 1]) + ((pr[i].second - B[qS + 1]) % (K[qS + 1]) != 0)) < ((pr[i].second - B[qS]) / (K[qS]) + ((pr[i].second - B[qS]) % (K[qS]) != 0)) || ((pr[i].second - B[qS + 1]) / (K[qS + 1]) + ((pr[i].second - B[qS + 1]) % (K[qS + 1]) != 0)) == ((pr[i].second - B[qS]) / (K[qS]) + ((pr[i].second - B[qS]) % (K[qS]) != 0)) && (K[qS + 1] * ((pr[i].second - B[qS + 1]) / (K[qS + 1]) + ((pr[i].second - B[qS + 1]) % (K[qS + 1]) != 0)) + B[qS + 1] - pr[i].second) >= (K[qS] * ((pr[i].second - B[qS]) / (K[qS]) + ((pr[i].second - B[qS]) % (K[qS]) != 0)) + B[qS] - pr[i].second))) qS++; long long cX = ((pr[i].second - B[qS]) / (K[qS]) + ((pr[i].second - B[qS]) % (K[qS]) != 0)), cK = pr[i].first; long long cY = (K[qS] * ((pr[i].second - B[qS]) / (K[qS]) + ((pr[i].second - B[qS]) % (K[qS]) != 0)) + B[qS] - pr[i].second), cB = cY - cK * cX; if (i == tn) printf( %I64d n , cX); while (tS > 1 && cK * pX[tS - 1] + cB >= pY[tS - 1]) tS--; K[++tS] = cK, B[tS] = cB; pX[tS - 1] = (((B[tS - 1] - B[tS])) / ((K[tS] - K[tS - 1])) + (((B[tS - 1] - B[tS])) % ((K[tS] - K[tS - 1])) != 0)); pY[tS - 1] = cK * pX[tS - 1] + cB; } } |
#include <bits/stdc++.h> using namespace std; void Emsawy() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); } const double PI = acos(-1.0); const double eps = 1e-10; const long long mod = 1e9 + 7, oo = 1e9; int dx[]{1, -1, 0, 0, 1, -1, 1, -1}; int dy[]{0, 0, 1, -1, 1, -1, -1, 1}; vector<vector<pair<int, int> > > adj; int n, m, k, t; const int N = 4001; int L[N], R[N]; long dp[89][2002][89 * 2 + 10]; long go(int l, int r, int k) { long &ret = dp[k][l][n - r - l + 89]; if (ret != -oo) return ret; if (l <= (n - r)) { ret = -oo; if (r - l > k) ret = max(ret, go(l + k, r, k) - L[l] + L[l + k]); if (r - l > k + 1) ret = max(ret, go(l + k + 1, r, k + 1) - L[l] + L[l + k + 1]); return (ret == -oo ? ret = 0 : ret); } ret = oo; if (r - l > k) ret = min(ret, go(l, r - k, k) - (-R[r] + R[r - k])); if (r - l > k + 1) ret = min(ret, go(l, r - k - 1, k + 1) - (-R[r] + R[r - k - 1])); return (ret == oo ? ret = 0 : ret); } int main() { Emsawy(); while (cin >> n) { for (int i = 1; i <= n; i++) { cin >> L[i]; R[i] = L[i]; L[i] += L[i - 1]; } for (int i = n - 1; i >= 1; i--) R[i] += R[i + 1]; for (int i = 0; i < 89; i++) { for (int j = 0; j < 2002; j++) { for (int g = 0; g < 89 * 2 + 10; g++) { dp[i][j][g] = -oo; } } } n += 1; cout << go(0, n, 1) << endl; } return 0; } |
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.91
// \ \ Application: MIG
// / / Filename: phy_ck_iob.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 07:18:02 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// Clock forwarding to memory
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: phy_ck_iob.v,v 1.1 2011/06/02 07:18:02 mishra Exp $
**$Date: 2011/06/02 07:18:02 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/verilog/rtl/phy/phy_ck_iob.v,v $
******************************************************************************/
`timescale 1ps/1ps
module phy_ck_iob #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter WRLVL = "OFF", // Enable write leveling
parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2"
parameter REFCLK_FREQ = 300.0, // IODELAY Reference Clock freq (MHz)
parameter IODELAY_GRP = "IODELAY_MIG" // May be assigned unique name
// when mult IP cores in design
)
(
input clk_mem, // full rate core clock
input clk, // half rate core clock
input rst, // half rate core clk reset
output ddr_ck_p, // forwarded diff. clock to memory
output ddr_ck_n // forwarded diff. clock to memory
);
wire ck_p_odelay;
wire ck_p_oq;
wire ck_p_out;
//*****************************************************************
// Note on generation of Control/Address signals - there are
// several possible configurations that affect the configuration
// of the OSERDES and possible ODELAY for each output (this will
// also affect the CK/CK# outputs as well
// 1. DDR3, write-leveling: This is the simplest case. Use
// OSERDES without the ODELAY. Initially clock/control/address
// will be offset coming out of FPGA from DQ/DQS, but DQ/DQS
// will be adjusted so that DQS-CK alignment is established
// 2. DDR2 or DDR3 (no write-leveling): Both DQS and DQ will use
// ODELAY to delay output of OSERDES. To match this,
// CK/control/address must also delay their outputs using ODELAY
// (with delay = 0)
//*****************************************************************
OBUFDS u_obuf_ck
(
.O (ddr_ck_p),
.OB (ddr_ck_n),
.I (ck_p_out)
);
OSERDESE1 #
(
.DATA_RATE_OQ ("DDR"),
.DATA_RATE_TQ ("BUF"),
.DATA_WIDTH (4),
.DDR3_DATA (0),
.INIT_OQ (1'b0),
.INIT_TQ (1'b0),
.INTERFACE_TYPE ("DEFAULT"),
.ODELAY_USED (0),
.SERDES_MODE ("MASTER"),
.SRVAL_OQ (1'b0),
.SRVAL_TQ (1'b0),
.TRISTATE_WIDTH (1)
)
u_oserdes_ck_p
(
.OCBEXTEND (),
.OFB (),
.OQ (ck_p_oq),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.TQ (),
.CLK (clk_mem),
.CLKDIV (clk),
.CLKPERF (),
.CLKPERFDELAY (),
.D1 (1'b0),
.D2 (1'b1),
.D3 (1'b0),
.D4 (1'b1),
.D5 (),
.D6 (),
.ODV (1'b0),
.OCE (1'b1),
.RST (rst),
// Connect SHIFTIN1, SHIFTIN2 to 0 for simulation purposes
// (for all other OSERDES used in design, these are no-connects):
// ensures that CK/CK# outputs are not X at start of simulation
// Certain DDR2 memory models may require that CK/CK# be valid
// throughout simulation
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.TFB (),
.TCE (1'b1),
.WC (1'b0)
);
generate
if ((DRAM_TYPE == "DDR3") && (WRLVL == "ON")) begin: gen_ck_wrlvl
//*******************************************************
// CASE1: DDR3, write-leveling
//*******************************************************
assign ck_p_out = ck_p_oq;
end else begin: gen_ck_nowrlvl
//*******************************************************
// CASE2: No write leveling (DDR2 or DDR3)
//*******************************************************
assign ck_p_out = ck_p_odelay;
(* IODELAY_GROUP = IODELAY_GRP *) IODELAYE1 #
(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("O"),
.HIGH_PERFORMANCE_MODE ("TRUE"),
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.ODELAY_TYPE ("FIXED"),
.ODELAY_VALUE (0),
.REFCLK_FREQUENCY (REFCLK_FREQ),
.SIGNAL_PATTERN ("CLOCK")
)
u_iodelay_ck_p
(
.DATAOUT (ck_p_odelay),
.C (1'b0),
.CE (1'b0),
.DATAIN (),
.IDATAIN (),
.INC (1'b0),
.ODATAIN (ck_p_oq),
.RST (1'b0),
.T (),
.CNTVALUEIN (),
.CNTVALUEOUT (),
.CLKIN (),
.CINVCTRL (1'b0)
);
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, K; char maze[2010][2010]; int up[2010][2010], down[2010][2010]; struct Segtree { int key[2010 * 4], ans[2010 * 4]; void add(deque<pair<int, int> > &que, int pos, int val) { while (!que.empty() && val < que.back().second) que.pop_back(); que.push_back(make_pair(pos, val)); } void remove(deque<pair<int, int> > &que, int pos) { while (!que.empty() && que.front().first <= pos) que.pop_front(); } void cal(int l, int r, int step) { int mid = l + r >> 1; deque<pair<int, int> > qU, qD; int i = 0, j = 0; key[step] = 0; for (; j < m; j++) { int a, b; add(qU, j, mid - max(l - 1, up[mid][j])); if (mid < r) add(qD, j, b = (min(r + 1, down[mid + 1][j]) - mid - 1)); else add(qD, j, b = 0); key[step] = max(key[step], min(j - i + 1, qU.front().second + qD.front().second)); while (i < j && j - i + 1 > qU.front().second + qD.front().second) { remove(qU, i); remove(qD, i); i++; key[step] = max(key[step], min(j - i + 1, qU.front().second + qD.front().second)); } } } void build(int l, int r, int step) { cal(l, r, step); if (l == r) return; int mid = l + r >> 1; build(l, mid, step * 2); build(mid + 1, r, step * 2 + 1); ans[step] = max(key[step], max(ans[step * 2], ans[step * 2 + 1])); } void update(int l, int r, int pos, int step) { cal(l, r, step); if (l == r) return; int mid = l + r >> 1; if (pos <= mid) update(l, mid, pos, step * 2); else update(mid + 1, r, pos, step * 2 + 1); ans[step] = max(key[step], max(ans[step * 2], ans[step * 2 + 1])); } } tree; int main() { scanf( %d%d%d , &n, &m, &K); for (int i = 0; i < (n); i++) scanf( %s , maze[i]); for (int j = 0; j < (m); j++) up[0][j] = maze[0][j] == . ? -1 : 0; for (int i = 1; i < n; i++) for (int j = 0; j < (m); j++) up[i][j] = maze[i][j] == . ? up[i - 1][j] : i; for (int j = 0; j < (m); j++) down[n - 1][j] = maze[n - 1][j] == . ? n : n - 1; for (int i = n - 2; i >= 0; i--) for (int j = 0; j < (m); j++) down[i][j] = maze[i][j] == . ? down[i + 1][j] : i; tree.build(0, n - 1, 1); while (K--) { int x, y; scanf( %d%d , &x, &y); x--, y--; maze[x][y] = # ; up[0][y] = maze[0][y] == . ? -1 : 0; for (int i = 1; i < n; i++) up[i][y] = maze[i][y] == . ? up[i - 1][y] : i; down[n - 1][y] = maze[n - 1][y] == . ? n : n - 1; for (int i = n - 2; i >= 0; i--) down[i][y] = maze[i][y] == . ? down[i + 1][y] : i; tree.update(0, n - 1, x, 1); printf( %d n , tree.ans[1]); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int a[51], n; cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); int res = INT_MAX; for (int i = 1; i < n; i++) { res = min(res, a[i] - a[i - 1]); } cout << res << endl; } } |
/*
* Miller Encoder
*
* By our algorithm, Miller Encoder can operate in the lowest frequency
* to save the power dissipation
*
* This algorithm is also applied to FMo Encoder
*
* If enable Miller Encoder, disable FM0 Encoder and vice versa
*/
`timescale 1us / 1ns
module miller_enc
(
output miller_data,
output mil_complete,
input clk_mil,
input rst_for_new_package,
input clk_blf,
input send_data,
input en_fm0, // if en_fm0 = 0, enable miller encoder
input trext,
input st_enc,
input fg_complete
);
parameter GetData = 2'b00;
parameter DataP = 2'b01;
parameter DataN = 2'b10;
reg [1:0]ps;
reg [1:0]ns;
wire clk_blf_n;
wire en_mil_out;
wire m2o;
wire mp_complete;
wire me_start;
reg [5:0]mp_end;
reg [5:0]mp_cnt;
reg m_cnt;
reg m1o;
reg [1:0]data_select;
reg [1:0]fg_comp_cnt;
assign clk_blf_n = ~clk_blf;
assign en_mil_out = (mp_cnt > 6'h0)? 1'b1 : 1'b0;
assign miller_data = (en_mil_out & ~mil_complete)? m2o : 1'b0;
assign m2o = mp_complete? m1o : clk_blf;
assign mp_complete = (mp_cnt == mp_end)? 1'b1 : 1'b0;
assign me_start = (mp_cnt > mp_end - 6'h2)? 1'b1 : 1'b0;
always@(*) begin
if(~trext) mp_end = 6'h9;
else mp_end = 6'h21;
end
always@(posedge clk_mil or negedge rst_for_new_package) begin
if(~rst_for_new_package) mp_cnt <= 6'h0;
else begin
if(mp_cnt == mp_end) mp_cnt <= mp_cnt;
else if(~en_fm0 & st_enc) mp_cnt <= mp_cnt + 6'h1;
end
end
always@(posedge clk_mil or negedge rst_for_new_package) begin
if(~rst_for_new_package) m_cnt <= 1'b0;
else if(me_start) m_cnt <= m_cnt + 1'b1;
end
always@(posedge clk_mil or negedge rst_for_new_package) begin
if(~rst_for_new_package) ps <= GetData;
else if(st_enc) ps <= ns;
end
always@(*) begin
case(ps)
GetData : if(~en_fm0 & me_start) ns = DataP;
else ns = GetData;
DataP : if(~send_data) ns = DataP;
else begin
if(~m_cnt) ns = DataP;
else ns = DataN;
end
DataN : if(~send_data) ns = DataN;
else begin
if(~m_cnt) ns = DataN;
else ns = DataP;
end
default : ns = GetData;
endcase
end
always@(*) begin
case(ps)
GetData : data_select = 2'h0;
DataP : data_select = 2'h1;
DataN : data_select = 2'h2;
default : data_select = 2'h0;
endcase
end
always@(*) begin
case(data_select)
2'h0 : m1o = 1'b0;
2'h1 : m1o = clk_blf;
2'h2 : m1o = clk_blf_n;
default : m1o = 1'b0;
endcase
end
always@(posedge clk_mil or negedge rst_for_new_package) begin
if(~rst_for_new_package) fg_comp_cnt <= 2'b0;
else begin
if(fg_comp_cnt == 2'b11) fg_comp_cnt <= fg_comp_cnt;
else if(~en_fm0 & fg_complete) fg_comp_cnt <= fg_comp_cnt + 2'b1;
end
end
assign mil_complete = (fg_comp_cnt == 2'b11)? 1'b1 : 1'b0;
endmodule
|
#include <bits/stdc++.h> const int mxn = 100000 + 10; using namespace std; string s; string soln; int main() { cin >> s; int n = s.size(); for (int i = 0; i < n; i++) if (s[i] == . ) printf( 0 ); else { if (s[i + 1] == - ) printf( 2 ); else printf( 1 ); i++; } puts( ); } |
module tester;
reg rrst ;
reg [63:0] rdata ;
reg [31:0] rparameter_Block ;
reg [63:0] rparameter_Block2 ;
reg [7:0] rbmRequestType ;
reg [7:0] rbRequest ;
reg [15:0] rwValue ;
reg [15:0] rwIndex ;
reg [15:0] rwLength ;
reg renable ;
wire wbusy ;
wire [31:0] wdata_out;
wire [63:0] wdata_out2;
wire [15:0] wdata_out3;
reg rclk = 0;
always #1 rclk = !rclk;
always @(rclk)
begin
rdata [63:56] = rbmRequestType [7:0];
rdata [55:47]= rbRequest [7:0];
rdata [46:33] = rwValue [15:0];
rdata [32:16] = rwIndex [15:0];
rdata [15:0] = rwLength ;
end
initial begin
$dumpfile("tester.vcd");
$dumpvars(0,tester);
rrst = 1;
#5
rrst =0 ;
rdata = 0;
rparameter_Block = 1;
rparameter_Block2 = 12;
rbmRequestType [7:0] = 8'b10100001;
rbRequest = 8'h87 ;
rwValue = 0;
rwIndex = 0;
rwLength = 2;
renable = 1 ;
# 513 $finish;
end
control control_intance (
.busy (wbusy),
.clk (rclk),
.rst (rrst),
.data (rdata),
.data_out32 (wdata_out),
.data_out64 (wdata_out2),
.data_out16 (wdata_out3),
.parameter_Block32 (rparameter_Block),
.parameter_Block64 (rparameter_Block2),
.enable (renable)
);
endmodule |
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: drom32.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module drom32 (
address,
clock,
q);
input [11:0] address;
input clock;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({32{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../rom_data.mif",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../rom_data.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "32"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../rom_data.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL drom32.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL drom32.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL drom32.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL drom32.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL drom32_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL drom32_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1); template <class T> T sqr(T x) { return x * x; } template <class T> T alex(T x) { return (x > 0) ? x : -x; } template <class T> void read(T& x) { x = 0; T f = 1; char ch = getchar(); while ((ch < 48 || ch > 57) && ch != 45) ch = getchar(); if (ch == 45) f = -1, ch = getchar(); while (ch >= 48 && ch <= 57) x = x * 10 + ch - 48, ch = getchar(); x *= f; } int n, q; char s[200005]; int t[200005 << 1]; int st[200005], ed[200005], len; int tmp[200005 << 1], sa[200005 << 1], rnk[200005 << 1], sum[200005 << 1]; bool cmp(int* tmp, int x, int y, int l) { return tmp[x] == tmp[y] && tmp[x + l] == tmp[y + l]; } void getsa(int n, int m) { memset(sum, 0, sizeof(sum)); for (int i = (1); i <= (n); i++) sum[rnk[i] = t[i]]++; for (int i = (1); i <= (m); i++) sum[i] += sum[i - 1]; for (int i = (n); i >= (1); i--) sa[sum[rnk[i]]--] = i; for (int j = 1; j <= n; j <<= 1) { int p = 0; for (int i = (n); i >= (n - j + 1); i--) tmp[++p] = i; for (int i = (1); i <= (n); i++) if (sa[i] > j) tmp[++p] = sa[i] - j; memset(sum, 0, sizeof(sum)); for (int i = (1); i <= (n); i++) sum[rnk[tmp[i]]]++; for (int i = (1); i <= (max(n, m)); i++) sum[i] += sum[i - 1]; for (int i = (n); i >= (1); i--) sa[sum[rnk[tmp[i]]]--] = tmp[i]; for (int i = (1); i <= (n); i++) tmp[i] = rnk[i]; p = 1; rnk[sa[1]] = 1; for (int i = (2); i <= (n); i++) rnk[sa[i]] = p += !cmp(tmp, sa[i - 1], sa[i], j); } } int height[200005 << 1][20]; void getheight(int n) { for (int i = (1); i <= (n); i++) { int l = max(height[rnk[i - 1]][0] - 1, 0), j = sa[rnk[i] - 1]; while (i + l <= n && j + l <= n && t[i + l] == t[j + l]) l++; height[rnk[i]][0] = l; } for (int j = (1); j < (20); j++) for (int i = (1); i <= (n - (1 << j) + 1); i++) height[i][j] = min(height[i][j - 1], height[i + (1 << (j - 1))][j - 1]); } int _log2[200005 << 1]; int LCP(int x, int y) { if (x == y) return n - sa[x] + 1; if (x > y) swap(x, y); x++; int j = _log2[y - x + 1]; return min(height[x][j], height[y - (1 << j) + 1][j]); } struct Node { int idx, l, sign; Node() {} Node(int idx, int l, int sign) : idx(idx), l(l), sign(sign) {} }; int sum_bit[200005 << 1]; int lowbit(int x) { return x & (-x); } void insert(int v, int x) { for (int i = x; i <= len; i += lowbit(i)) sum_bit[i]++; } int ask(int l, int r) { int res = 0; for (int i = l - 1; i; i -= lowbit(i)) res -= sum_bit[i]; for (int i = r; i; i -= lowbit(i)) res += sum_bit[i]; return res; } vector<Node> que[200005]; int ans[500005]; void insert(int idx) { for (int i = (st[idx]); i <= (ed[idx]); i++) insert(1, rnk[i]); } int findl(int l, int r, int pos, int val) { while (l <= r) { int mid = (l + r) >> 1; if (LCP(mid, pos) >= val) r = mid - 1; else l = mid + 1; } return l; } int findr(int l, int r, int pos, int val) { while (l <= r) { int mid = (l + r) >> 1; if (LCP(pos, mid) >= val) l = mid + 1; else r = mid - 1; } return r; } int query(int idx) { int len2 = ed[idx] - st[idx] + 1; int l = findl(1, rnk[st[idx]] - 1, rnk[st[idx]], len2); int r = findr(rnk[st[idx]] + 1, len, rnk[st[idx]], len2); return ask(l, r); } int main() { read(n); read(q); int m = 26; len = 0; for (int i = (1); i <= (n); i++) { scanf( %s , s + 1); int l = strlen(s + 1); st[i] = len + 1; for (int k = (1); k <= (l); k++) t[++len] = s[k] - a + 1; ed[i] = len; t[++len] = ++m; } getsa(len, m); getheight(len); for (int i = (0); i <= (len); i++) _log2[i] = log2(i); for (int i = (1); i <= (q); i++) { int l, r, k; read(l); read(r); read(k); que[l - 1].push_back(Node(i, k, -1)); que[r].push_back(Node(i, k, 1)); } for (int i = (1); i <= (n); i++) { insert(i); for (int k = (0); k < (que[i].size()); k++) if (que[i][k].sign == -1) ans[que[i][k].idx] -= query(que[i][k].l); else ans[que[i][k].idx] += query(que[i][k].l); } for (int i = (1); i <= (q); i++) printf( %d n , ans[i]); return 0; } |
// Note: case_expr_{,non_}const.v should be modified in tandem to ensure both
// the constant and non-constant case evaluation logic is covered
module case_expr_non_const_top(
// expected to output all 1s
output reg a, b, c, d, e, f, g, h
);
reg x_1b0 = 1'b0;
reg x_1b1 = 1'b1;
reg signed x_1sb0 = 1'sb0;
reg signed x_1sb1 = 1'sb1;
reg [1:0] x_2b0 = 2'b0;
reg [1:0] x_2b11 = 2'b11;
reg signed [1:0] x_2sb01 = 2'sb01;
reg signed [1:0] x_2sb11 = 2'sb11;
reg [2:0] x_3b0 = 3'b0;
initial begin
case (x_2b0)
x_1b0: a = 1;
default: a = 0;
endcase
case (x_2sb11)
x_2sb01: b = 0;
x_1sb1: b = 1;
endcase
case (x_2sb11)
x_1sb0: c = 0;
x_1sb1: c = 1;
endcase
case (x_2sb11)
x_1b0: d = 0;
x_1sb1: d = 0;
default: d = 1;
endcase
case (x_2b11)
x_1sb0: e = 0;
x_1sb1: e = 0;
default: e = 1;
endcase
case (x_1sb1)
x_1sb0: f = 0;
x_2sb11: f = 1;
default: f = 0;
endcase
case (x_1sb1)
x_1sb0: g = 0;
x_3b0: g = 0;
x_2sb11: g = 0;
default: g = 1;
endcase
case (x_1sb1)
x_1sb0: h = 0;
x_1b1: h = 1;
x_3b0: h = 0;
x_2sb11: h = 0;
default: h = 0;
endcase
end
endmodule
|
module testbench;
localparam wide_width_lp = 16;
localparam narrow_width_lp = 4;
localparam els_lp = wide_width_lp / narrow_width_lp;
logic clk;
bsg_nonsynth_clock_gen
#(.cycle_time_p(1000))
clock_gen
(.o(clk));
logic reset;
bsg_nonsynth_reset_gen
#(.num_clocks_p(1)
,.reset_cycles_lo_p(4)
,.reset_cycles_hi_p(4)
)
reset_gen
(.clk_i(clk)
,.async_reset_o(reset)
);
logic [wide_width_lp-1:0] in_data_li;
logic in_v_li, in_ready_lo;
logic [narrow_width_lp-1:0] in_data_lo;
logic in_v_lo, in_yumi_li;
logic [narrow_width_lp-1:0] out_data_li;
logic out_v_li, out_ready_lo;
logic [wide_width_lp-1:0] out_data_lo;
logic out_v_lo, out_ready_li;
bsg_parallel_in_serial_out_passthrough
#(.width_p(narrow_width_lp), .els_p(els_lp))
DUT
(.clk_i(clk)
,.reset_i(reset)
,.data_i(in_data_li)
,.v_i(in_v_li)
,.ready_and_o(in_ready_lo)
,.data_o(in_data_lo)
,.v_o(in_v_lo)
,.ready_and_i(in_yumi_li)
);
assign out_data_li = in_data_lo;
assign out_v_li = in_v_lo;
assign in_yumi_li = out_ready_lo & out_v_li;
bsg_serial_in_parallel_out_full
#(.width_p(narrow_width_lp), .els_p(els_lp))
reverse
(.clk_i(clk)
,.reset_i(reset)
,.data_i(out_data_li)
,.v_i(out_v_li)
,.ready_o(out_ready_lo)
,.data_o(out_data_lo)
,.v_o(out_v_lo)
,.yumi_i(out_ready_li & out_v_lo)
);
// Input block
initial
begin
in_data_li = '0;
in_v_li = '0;
@(posedge clk);
@(negedge reset);
@(posedge clk);
for (integer i = 0; i < 100; i++)
begin
in_v_li = 1'b1;
@(negedge clk);
in_data_li = in_data_li + (in_ready_lo & in_v_li);
if (in_ready_lo & in_v_li)
$display("Sending %d", in_data_li);
end
end
// Checking block
logic [wide_width_lp-1:0] match_data_li;
initial
begin
out_ready_li = '0;
match_data_li = '0;
@(posedge clk);
@(negedge reset);
@(posedge clk);
for (integer i = 1; i < 101; i++)
begin
out_ready_li = 1'b1;
match_data_li = match_data_li + (out_ready_li & out_v_lo);
@(negedge clk);
assert(~(out_ready_li & out_v_lo) || match_data_li == out_data_lo);
if (out_ready_li & out_v_lo)
$display("Receiving %d", match_data_li);
end
$finish();
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1000000007; const int P[] = {2, 3, 5, 7, 13, 17, 19, 31, 61, 89, 107, 127, 521, 607, 1279, 2203, 2281, 3217, 4253, 4423, 9689, 9941, 11213, 19937, 21701, 23209, 44497, 86243, 110503, 132049, 216091, 756839, 859433, 1257787, 1398269, 2976221, 3021377, 6972593, 13466917, 20996011, 24036583}; long long expBySqr(long long x, long long n) { long long y = 1; for (; n != 0; n >>= 1) { if ((n & 1) == 1) { y = y * x % MOD; } x = x * x % MOD; } return y; } int main() { int n; scanf( %d , &n); int res = expBySqr(2LL, P[n - 1] - 1) % MOD; res = (res + MOD - 1) % MOD; printf( %d n , res); return 0; } |
// zhiyang ong
// andrew mattheisen
`timescale 1ns/10ps
`include "control.h"
module controltb;
reg [0:31] instr;
reg clk;
wire [0:4] aluop, rrdaddra, rrdaddrb, rwraddrd;
wire [0:2] ppp, regop, memop;
wire [0:1] ww;
wire [0:20] maddr;
wire reginmuxop, aluinmuxop;
wire [0:15] wbyteen;
wire [0:31] immediate;
control control1(instr,
aluop, ppp, ww,
memop, maddr, wbyteen,
regop, rrdaddra, rrdaddrb, rwraddrd,
reginmuxop,
aluinmuxop,
immediate);
always
begin
#5 clk=0;
#5 clk=1;
end // always
initial
begin
#5;
//wadd
instr=32'b00010001101010100101100000000000; // ADD
#10;
instr=32'b00010001101010100101101001000000; // ADD
#10;
instr=32'b00010001101010100101110000000000; // ADD
#10;
instr=32'b00010001101010100101110001000000; // ADD
#10;
instr=32'b00010001101010100101110010000000; // ADD
#10;
instr=32'b00010001101010100101110010001001; // AND
#10;
instr=32'b00000101101000000000000000000001; // LD
#10;
instr=32'b00100001101010100000010010001001; // VMV
#10;
instr=32'b00010001101010100000010100001000; // NOT
#10;
instr=32'b00010001101010100101110101001010; // OR
#10;
instr=32'b00010001101010100101110100001100; // PRM
#10;
instr=32'b00010001101010100101110101010000; // SLL
#10;
instr=32'b00010001101010100111110110010001; // SLLI
#10;
instr=32'b00010001101010100101110110010110; // SRA
#10;
instr=32'b00010001101010100111110110010111; // SRAI
#10;
instr=32'b00010001101010100101110110010100; // SRL
#10;
instr=32'b00010001101010100111110110010101; // SRLI
#10;
instr=32'b00001001101000000000000000000001; // ST
#10;
instr=32'b00010001101010100101111001000001; // SUB
#10;
instr=32'b00010001101010100101111101001011; // XOR
#10;
instr=32'b00000001101010100101110110001011; // NOP
#10;
$finish;
end // intial
initial
begin
$shm_open("tb.shm");
$shm_probe("AC");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7, N = 100007; int n; long long ts, tf, t, a[N], ans = (long long)1e18, id; int main() { cin >> ts >> tf >> t; cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; while (a[n] > tf - t) n--; a[++n] = tf - t + 1; long long cur = 0; for (int i = 1; i <= n; i++) { cur = max(cur, ts); if (ans > cur - (a[i] - 1)) { ans = cur - (a[i] - 1); id = a[i] - 1; } if (cur < a[i]) { cout << cur; return 0; } cur = max(cur, a[i]); cur += t; if (cur >= tf - t + 1) break; } cout << id; return 0; } |
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