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`include "assert.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 4;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("i64.const.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
reg reset = 0;
wire [63:0] result;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("i64.const_tb.vcd");
$dumpvars(0, cpu_tb);
#12
`assert(result, 42);
`assert(result_empty, 0);
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using pii = pair<int, int>; constexpr int N = 1e2 + 5; int n, m, k, g[N][N], ans = -1, id; unordered_set<int> dp[N][N]; char c; bool check(int i, int j, int val) { for (auto el : dp[i][j]) { if (ans == el + val) { ans -= val; return true; } } return false; } void Solve() { cin >> n >> m >> k; for (int i = 0; i < N; i++) for (int j = 0; j < N; j++) { dp[i][j].reserve(1024); dp[i][j].max_load_factor(0.25); } for (int i = 0; i < N; i++) dp[0][i] = {0}; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { cin >> c; g[i][j] = c - 0 ; } for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { for (auto el : dp[i - 1][j - 1]) dp[i][j].insert(el + g[i][j]); for (auto el : dp[i - 1][j + 1]) dp[i][j].insert(el + g[i][j]); } for (int i = 1; i <= m; i++) for (auto el : dp[n][i]) { if (!(el % (k + 1))) { if (ans < el) { ans = el; id = i; } } } cout << ans << n ; if (ans == -1) return; cout << id << n ; for (int i = n; i > 1; i--) { if (check(i - 1, id - 1, g[i][id])) { id = id - 1; cout << L ; } else if (check(i - 1, id + 1, g[i][id])) { id = id + 1; cout << R ; } } } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); Solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const long double PI = 3.14159265358979323846264338327950288419716939937510, EPS = 1e-9; const int MAX = 1 << 17; struct prav { long double a, b, c; }; pair<int, int> sred; long double Sq(long double x) { return x * x; } long double Dist(pair<int, int> a, pair<int, int> b) { return sqrt(Sq(a.first - b.first) + Sq(a.second - b.second)); } long double DistPrav(prav p, pair<int, int> toc) { return abs(p.a * toc.first + p.b * toc.second + p.c) / sqrt((Sq(p.a) + Sq(p.b))); } prav Pravac(pair<int, int> a, pair<int, int> b) { return prav{ (long double)b.second - a.second, (long double)a.first - b.first, (long double)b.first * a.second - (long double)a.first * b.second}; } pair<int, int> tocke[MAX]; int main() { int n; scanf( %d%d%d , &n, &sred.first, &sred.second); for (int i = 0; i < n; i++) scanf( %d%d , &tocke[i].first, &tocke[i].second); long double minn = 1e15, maxx = -1e15; for (int i = 0; i < n; i++) { long double dd = Dist(sred, tocke[i]); minn = min(minn, dd); maxx = max(maxx, dd); int slj = (i + 1) % n; if (Sq(Dist(tocke[i], tocke[slj])) + Sq(Dist(tocke[i], sred)) + EPS > Sq(Dist(tocke[slj], sred)) && Sq(Dist(tocke[i], tocke[slj])) + Sq(Dist(tocke[slj], sred)) + EPS > Sq(Dist(tocke[i], sred))) { minn = min(minn, DistPrav(Pravac(tocke[i], tocke[slj]), sred)); } } printf( %.15lf n , (double)((Sq(maxx) - Sq(minn)) * PI)); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYMETAL6S4S_TB_V
`define SKY130_FD_SC_LS__DLYMETAL6S4S_TB_V
/**
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
* horizontal route.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dlymetal6s4s.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_ls__dlymetal6s4s dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYMETAL6S4S_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFBBP_BLACKBOX_V
`define SKY130_FD_SC_LP__SDFBBP_BLACKBOX_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFBBP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 7, mod = 1e9 + 7; int dp[N], sum[N], i, n, m, j, k, nxt[N], v[N]; char a[N], b[N]; int main() { for (scanf( %s%s , a + 1, b + 1), n = strlen(a + 1), m = strlen(b + 1), i = 2; i <= m; ++i) { while (b[j + 1] != b[i] && j) j = nxt[j]; if (b[j + 1] == b[i]) j++; nxt[i] = j; } for (i = 1, j = 0; i <= n; ++i) { while (b[j + 1] != a[i] && j) j = nxt[j]; if (b[j + 1] == a[i]) j++; if (j == m) v[i] = 1, j = nxt[j]; } for (i = 1, j = -1; i <= n; ++i) { dp[i] = dp[i - 1]; if (v[i]) j = i - m + 1; if (j != -1) dp[i] += sum[j - 1] + j, dp[i] %= mod; sum[i] = (sum[i - 1] + dp[i]) % mod; } return 0 * printf( %d n , dp[n]); } |
#include <bits/stdc++.h> using namespace std; int n, m, x; void ans(int x1, int x2, int y1, int y2, int now) { if (x1 + 1 > x2 - 1 || y1 + 1 > y2 - 1) { cout << 0; return; } else { if (now + 1 == x) { if ((x2 - x1 - 1) == 1 || (y2 - y1 - 1) == 1) { if ((x2 - x1 - 1) == 1 && (y2 - y1 - 1) == 1) cout << 1; else cout << ((x2 - x1 - 1) + (y2 - y1 - 1) - 1) / 2; } else cout << ((x2 - x1 - 1) + (y2 - y1 - 1) - 2); } else ans(x1 + 1, x2 - 1, y1 + 1, y2 - 1, now + 1); } } int main() { cin >> n >> m >> x; if (n == 1 || m == 1) { if (n == 1 && m == 1) { if (x == 1) { cout << 1; } else cout << 0; return 0; } if (x == 1) { cout << (n + m) / 2; } else cout << 0; return 0; } if (x == 1) { cout << (n + m - 2); return 0; } ans(1, n, 1, m, 1); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05/30/2017 01:38:40 PM
// Design Name:
// Module Name: SHA1_core_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SHA1_core_tb(
);
reg clk,rst;
reg i_hash_in_start;
reg [31:0]i_hash_in;
reg msg_in_start;
reg [31:0]msgIn;
reg [9:0]msgLenBits;
wire msgOutDone;
wire [511:0]msgOut;
wire [159:0]i_hash_out;
wire i_hash_out_done;
wire digest_done;
wire [159:0]digest;
wire f_hash_done;
wire [31:0]f_hash_out;
Initial_Hash_In I1(clk,rst,i_hash_in_start,i_hash_in,i_hash_out_done,i_hash_out);
Msg_In M1(clk,rst,msg_in_start,msgIn,msgOutDone,msgOut);
SHA1_core S1(clk,rst,i_hash_out_done,i_hash_out,msgOutDone,msgLenBits,msgOut,digest_done,digest);
SHA1_out O1(clk,rst,digest_done,digest,f_hash_done,f_hash_out);
initial begin
clk = 0;
#5 rst = 0;
#10 rst = 1;
#10 i_hash_in_start = 1;
msg_in_start = 1;
msgLenBits = 24;
msgIn = 32'h61626300;
i_hash_in = 32'h67452301;
#10 msgIn = 0;
i_hash_in = 32'hefcdab89;
#10 msgIn = 0;
i_hash_in = 32'h98badcfe;
#10 msgIn = 0;
i_hash_in = 32'h10325476;
#10 msgIn = 0;
i_hash_in = 32'hc3d2e1f0;
#10 msgIn = 0;
#10 msgIn = 0;
#10 msgIn = 0;
#10 msgIn = 0;
#10 msgIn = 0;
#10 msgIn = 0;
#10 msgIn = 0;
#10 msgIn = 0;
#10 msgIn =0;
#6000 $finish;
end
always begin
#5 clk = ~clk;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long maxn = 100005; const long long p = 1e9 + 7; long long a[maxn], n, x, sum; long long st[maxn], top; vector<long long> v; inline long long read() { long long x = 0, f = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) f = -1; ch = getchar(); } while (isdigit(ch)) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } inline long long qpow(long long x, long long y) { long long res = 1; while (y) { if (y & 1) res = (res * x % p) % p; x = (x % p * x % p) % p; y >>= 1; } return res % p; } signed main() { n = read(); x = read(); for (long long i = 1; i <= n; i++) a[i] = read(), sum += a[i]; for (long long i = 1; i <= n; i++) st[++top] = sum - a[i]; sort(st + 1, st + n + 1); reverse(st + 1, st + n + 1); while (1) { long long res = st[top], cnt = 0; while (top > 0 && res == st[top]) cnt++, top--; if (cnt % x) { printf( %d , qpow(x, min(sum, res))); return 0; } else { cnt /= x; for (long long i = 1; i <= cnt; i++) st[++top] = res + 1; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int q; int cnt[1 << 20]; int trans(long long v) { int rt = 0; for (int i = 0; i < 18; i++, v /= 10) { if ((v % 10) & 1) { rt |= 1 << i; } } return rt; } void insert(long long v) { cnt[trans(v)]++; } void erase(long long v) { cnt[trans(v)]--; } int query(long long v) { int bit = 0; for (int i = 0; i < 18; i++, v /= 10) { if (v & 1) { bit |= 1 << i; } } return cnt[bit]; } int main() { cin >> q; while (q--) { char ch[10]; long long v; cin >> ch >> v; if (ch[0] == + ) { insert(v); } else if (ch[0] == - ) { erase(v); } else { cout << query(v) << endl; } } } |
//////////////////////////////////////////////////////////////////////
//// ////
//// spi_shift.v ////
//// ////
//// This file is part of the SPI IP core project ////
//// http://www.opencores.org/projects/spi/ ////
//// ////
//// Author(s): ////
//// - Simon Srot () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "spi_defines.v"
`include "timescale.v"
module spi_shift (clk, rst, latch, byte_sel, len, lsb, go,
pos_edge, neg_edge, rx_negedge, tx_negedge,
tip, last,
p_in, p_out, s_clk, s_in, s_out);
parameter Tp = 1;
input clk; // system clock
input rst; // reset
input [3:0] latch; // latch signal for storing the data in shift register
input [3:0] byte_sel; // byte select signals for storing the data in shift register
input [`SPI_CHAR_LEN_BITS-1:0] len; // data len in bits (minus one)
input lsb; // lbs first on the line
input go; // start stansfer
input pos_edge; // recognize posedge of sclk
input neg_edge; // recognize negedge of sclk
input rx_negedge; // s_in is sampled on negative edge
input tx_negedge; // s_out is driven on negative edge
output tip; // transfer in progress
output last; // last bit
input [31:0] p_in; // parallel in
output [`SPI_MAX_CHAR-1:0] p_out; // parallel out
input s_clk; // serial clock
input s_in; // serial in
output s_out; // serial out
reg s_out;
reg tip;
reg [`SPI_CHAR_LEN_BITS:0] cnt; // data bit count
reg [`SPI_MAX_CHAR-1:0] data; // shift register
wire [`SPI_CHAR_LEN_BITS:0] tx_bit_pos; // next bit position
wire [`SPI_CHAR_LEN_BITS:0] rx_bit_pos; // next bit position
wire rx_clk; // rx clock enable
wire tx_clk; // tx clock enable
assign p_out = data;
assign tx_bit_pos = lsb ? {!(|len), len} - cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1};
assign rx_bit_pos = lsb ? {!(|len), len} - (rx_negedge ? cnt + {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1} : cnt) :
(rx_negedge ? cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1});
assign last = !(|cnt);
assign rx_clk = (rx_negedge ? neg_edge : pos_edge) && (!last || s_clk);
assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last;
// Character bit counter
always @(posedge clk or posedge rst)
begin
if(rst)
cnt <= #Tp {`SPI_CHAR_LEN_BITS+1{1'b0}};
else
begin
if(tip)
cnt <= #Tp pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt;
else
cnt <= #Tp !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len};
end
end
// Transfer in progress
always @(posedge clk or posedge rst)
begin
if(rst)
tip <= #Tp 1'b0;
else if(go && ~tip)
tip <= #Tp 1'b1;
else if(tip && last && pos_edge)
tip <= #Tp 1'b0;
end
// Sending bits to the line
always @(posedge clk or posedge rst)
begin
if (rst)
s_out <= #Tp 1'b0;
else
s_out <= #Tp (tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out;
end
// Receiving bits from the line
always @(posedge clk or posedge rst)
begin
if (rst)
data <= #Tp {`SPI_MAX_CHAR{1'b0}};
`ifdef SPI_MAX_CHAR_128
else if (latch[0] && !tip)
begin
if (byte_sel[3])
data[31:24] <= #Tp p_in[31:24];
if (byte_sel[2])
data[23:16] <= #Tp p_in[23:16];
if (byte_sel[1])
data[15:8] <= #Tp p_in[15:8];
if (byte_sel[0])
data[7:0] <= #Tp p_in[7:0];
end
else if (latch[1] && !tip)
begin
if (byte_sel[3])
data[63:56] <= #Tp p_in[31:24];
if (byte_sel[2])
data[55:48] <= #Tp p_in[23:16];
if (byte_sel[1])
data[47:40] <= #Tp p_in[15:8];
if (byte_sel[0])
data[39:32] <= #Tp p_in[7:0];
end
else if (latch[2] && !tip)
begin
if (byte_sel[3])
data[95:88] <= #Tp p_in[31:24];
if (byte_sel[2])
data[87:80] <= #Tp p_in[23:16];
if (byte_sel[1])
data[79:72] <= #Tp p_in[15:8];
if (byte_sel[0])
data[71:64] <= #Tp p_in[7:0];
end
else if (latch[3] && !tip)
begin
if (byte_sel[3])
data[127:120] <= #Tp p_in[31:24];
if (byte_sel[2])
data[119:112] <= #Tp p_in[23:16];
if (byte_sel[1])
data[111:104] <= #Tp p_in[15:8];
if (byte_sel[0])
data[103:96] <= #Tp p_in[7:0];
end
`else
`ifdef SPI_MAX_CHAR_64
else if (latch[0] && !tip)
begin
if (byte_sel[3])
data[31:24] <= #Tp p_in[31:24];
if (byte_sel[2])
data[23:16] <= #Tp p_in[23:16];
if (byte_sel[1])
data[15:8] <= #Tp p_in[15:8];
if (byte_sel[0])
data[7:0] <= #Tp p_in[7:0];
end
else if (latch[1] && !tip)
begin
if (byte_sel[3])
data[63:56] <= #Tp p_in[31:24];
if (byte_sel[2])
data[55:48] <= #Tp p_in[23:16];
if (byte_sel[1])
data[47:40] <= #Tp p_in[15:8];
if (byte_sel[0])
data[39:32] <= #Tp p_in[7:0];
end
`else
else if (latch[0] && !tip)
begin
`ifdef SPI_MAX_CHAR_8
if (byte_sel[0])
data[`SPI_MAX_CHAR-1:0] <= #Tp p_in[`SPI_MAX_CHAR-1:0];
`endif
`ifdef SPI_MAX_CHAR_16
if (byte_sel[0])
data[7:0] <= #Tp p_in[7:0];
if (byte_sel[1])
data[`SPI_MAX_CHAR-1:8] <= #Tp p_in[`SPI_MAX_CHAR-1:8];
`endif
`ifdef SPI_MAX_CHAR_24
if (byte_sel[0])
data[7:0] <= #Tp p_in[7:0];
if (byte_sel[1])
data[15:8] <= #Tp p_in[15:8];
if (byte_sel[2])
data[`SPI_MAX_CHAR-1:16] <= #Tp p_in[`SPI_MAX_CHAR-1:16];
`endif
`ifdef SPI_MAX_CHAR_32
if (byte_sel[0])
data[7:0] <= #Tp p_in[7:0];
if (byte_sel[1])
data[15:8] <= #Tp p_in[15:8];
if (byte_sel[2])
data[23:16] <= #Tp p_in[23:16];
if (byte_sel[3])
data[`SPI_MAX_CHAR-1:24] <= #Tp p_in[`SPI_MAX_CHAR-1:24];
`endif
end
`endif
`endif
else
data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= #Tp rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long mult(long long a, long long b, long long p = 1000000007) { return ((a % p) * (b % p)) % p; } long long add(long long a, long long b, long long p = 1000000007) { return (a % p + b % p) % p; } long long fpow(long long n, long long k, long long p = 1000000007) { long long r = 1; for (; k; k >>= 1LL) { if (k & 1LL) r = mult(r, n, p); n = mult(n, n, p); } return r; } long long inv(long long a, long long p = 1000000007) { return fpow(a, p - 2, p); } void self_max(int &a, int &b) { a = max(a, b); } void self_min(int &a, int &b) { a = min(a, b); } bool isPrime(long int n) { if (n <= 1) return false; if (n <= 3) return true; if (n % 2 == 0 || n % 3 == 0) return false; for (int i = 5; i * i <= n; i = i + 6) if (n % i == 0 || n % (i + 2) == 0) return false; return true; } long long power(int first, unsigned int second, int p) { long long res = 1; first = first % p; while (second > 0) { if (second & 1) res = (res * first) % p; second = second >> 1; first = (first * first) % p; } return res; } void solve() { string s1, s2; cin >> s1 >> s2; int n = s1.length(); int m = s2.length(); vector<int> pos[26]; for (int i = 0; i < n; i++) { pos[s1[i] - a ].push_back(i); } int ans = 0, p, flag = 0, k; for (int i = 0; i < m; i++) { if ((int)pos[s2[i] - a ].size() == 0) { cout << -1 << n ; return; } else if (flag == 0) { p = pos[s2[i] - a ][0]; flag = 1; } else { auto t = upper_bound((pos[s2[i] - a ]).begin(), (pos[s2[i] - a ]).end(), p); k = t - pos[s2[i] - a ].begin(); if (k == (int)pos[s2[i] - a ].size()) { ans++; i--; flag = 0; } p = pos[s2[i] - a ][k]; } } ans++; cout << ans << n ; } int main() { ios::sync_with_stdio(false); cout << fixed << setprecision(20); cin.tie(0); cout.tie(0); int t = 1; cin >> t; while (t--) { solve(); } } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(NULL); int n, x; cin >> n; while (n--) { cin >> x; if (x < 3 || x == 4 || x == 5 || x == 8 || x == 11) cout << NO << endl; else cout << YES << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MX = 35; bitset<MX * MX> bs[MX * MX]; int n, a[MX][MX], m, sz, h, res; void impr() { for (int k = 0; k < m; k++) { cout << k << : << n ; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) cout << bs[k][((i)*n + (j))] << ; cout << n ; } cout << n ; } } int val(int i, int j, bitset<MX * MX> &bs) { return bs[((i)*n + (j))] ? -a[i][j] : a[i][j]; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; h = (n + 1) / 2; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) { cin >> a[i][j]; res += a[i][j]; } for (int i = 0; i < h; i++) for (int j = 0; j < h; j++) { for (int x = 0; x < h; x++) for (int y = 0; y < h; y++) bs[m][((i + x) * n + (j + y))] = 1; m++; } for (int i = 0; i < n * n; i++) { int ind = -1; for (int j = sz; j < m; j++) if (bs[j][i]) ind = j; if (ind == -1) continue; swap(bs[ind], bs[sz]); for (int j = 0; j < m; j++) if (j != sz && bs[j][i]) bs[j] ^= bs[sz]; sz++; } for (int mk = 0; mk < (1 << h); mk++) { bitset<MX * MX> act; for (int i = 0; i < h; i++) if (mk & (1 << i)) act ^= bs[h * (i + 1) - 1]; int p = 0; for (int i = 0; i < n; i++) p += val(i, h - 1, act); for (int j = 0; j < h - 1; j++) { bitset<MX *MX> a = act, b = act ^ bs[h * (h - 1) + j]; int x = val(h - 1, j, a) + val(h - 1, j + h, a); int y = val(h - 1, j, b) + val(h - 1, j + h, b); for (int i = 0; i < h - 1; i++) { int q = val(i, j, a) + val(i + h, j, a) + val(i, j + h, a) + val(i + h, j + h, a); x += max(q, -q); q = val(i, j, b) + val(i + h, j, b) + val(i, j + h, b) + val(i + h, j + h, b); y += max(q, -q); } p += max(x, y); } res = max(res, p); } cout << res << n ; return 0; } |
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Inverse_Clarke_Transform.v
// Created: 2014-09-08 14:12:04
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Inverse_Clarke_Transform
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Transform_dq_to_ABC/Inverse_Clarke_Transform
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Inverse_Clarke_Transform
(
alpha_voltage,
beta_voltage,
phase_voltages_0,
phase_voltages_1,
phase_voltages_2
);
input signed [17:0] alpha_voltage; // sfix18_En10
input signed [17:0] beta_voltage; // sfix18_En10
output signed [17:0] phase_voltages_0; // sfix18_En13
output signed [17:0] phase_voltages_1; // sfix18_En13
output signed [17:0] phase_voltages_2; // sfix18_En13
wire signed [35:0] voltage_phase_a; // sfix36_En26
wire signed [35:0] Gain1_out1; // sfix36_En26
wire signed [35:0] Gain_out1; // sfix36_En26
wire signed [35:0] voltage_phase_b; // sfix36_En26
wire signed [37:0] Add1_cast; // sfix38_En26
wire signed [37:0] Add1_cast_1; // sfix38_En26
wire signed [37:0] Add1_sub_cast; // sfix38_En26
wire signed [37:0] Add1_sub_temp; // sfix38_En26
wire signed [35:0] voltage_phase_c; // sfix36_En26
wire signed [35:0] Mux_out1 [0:2]; // sfix36_En26 [3]
wire signed [17:0] Current_Data_Type_out1 [0:2]; // sfix18_En13 [3]
// Inverse Clarke Transform
//
// Converts direct axis (alpha) component and the quadrature axis (beta) component to balanced three-phase quantities
// The alpha and beta components are dependent on time and speed.
// <S39>/Data Type Conversion
assign voltage_phase_a = {{2{alpha_voltage[17]}}, {alpha_voltage, 16'b0000000000000000}};
// <S39>/Gain1
assign Gain1_out1 = 56756 * beta_voltage;
// <S39>/Gain
assign Gain_out1 = {{3{alpha_voltage[17]}}, {alpha_voltage, 15'b000000000000000}};
// <S39>/Add
assign voltage_phase_b = Gain1_out1 - Gain_out1;
// <S39>/Add1
assign Add1_cast = Gain_out1;
assign Add1_cast_1 = - (Add1_cast);
assign Add1_sub_cast = Gain1_out1;
assign Add1_sub_temp = Add1_cast_1 - Add1_sub_cast;
assign voltage_phase_c = Add1_sub_temp[35:0];
// <S39>/Mux
assign Mux_out1[0] = voltage_phase_a;
assign Mux_out1[1] = voltage_phase_b;
assign Mux_out1[2] = voltage_phase_c;
// <S39>/Current_Data_Type
assign Current_Data_Type_out1[0] = ((Mux_out1[0][35] == 1'b0) && (Mux_out1[0][34:30] != 5'b00000) ? 18'sb011111111111111111 :
((Mux_out1[0][35] == 1'b1) && (Mux_out1[0][34:30] != 5'b11111) ? 18'sb100000000000000000 :
$signed(Mux_out1[0][30:13])));
assign Current_Data_Type_out1[1] = ((Mux_out1[1][35] == 1'b0) && (Mux_out1[1][34:30] != 5'b00000) ? 18'sb011111111111111111 :
((Mux_out1[1][35] == 1'b1) && (Mux_out1[1][34:30] != 5'b11111) ? 18'sb100000000000000000 :
$signed(Mux_out1[1][30:13])));
assign Current_Data_Type_out1[2] = ((Mux_out1[2][35] == 1'b0) && (Mux_out1[2][34:30] != 5'b00000) ? 18'sb011111111111111111 :
((Mux_out1[2][35] == 1'b1) && (Mux_out1[2][34:30] != 5'b11111) ? 18'sb100000000000000000 :
$signed(Mux_out1[2][30:13])));
assign phase_voltages_0 = Current_Data_Type_out1[0];
assign phase_voltages_1 = Current_Data_Type_out1[1];
assign phase_voltages_2 = Current_Data_Type_out1[2];
endmodule // controllerHdl_Inverse_Clarke_Transform
|
#include <bits/stdc++.h> using namespace std; template <typename T> void print1d(vector<T> &a) { for (long long int i = 0; i < a.size(); i++) { cout << a[i] << ; } cout << endl; } vector<long long int> divisor(long long int n) { vector<long long int> a; for (long long int i = 1; i * i <= n; i++) { if (n % i == 0) { if (n / i == i) a.push_back(i); else { a.push_back(i); a.push_back(n / i); } } } return a; } bool sortsecond(const pair<long long int, long long int> &a, const pair<long long int, long long int> &b) { return a.second < b.second; } bool isPrime(long long int n) { for (long long int i = 2; i * i <= n; i++) { if (n % i == 0) return false; } return true; } vector<string> split_string(const string &s, const string &delimiter) { vector<string> token; string ans; size_t end_point, start_point = 0, delim_length = delimiter.length(); while ((end_point = s.find(delimiter, start_point)) != string::npos) { ans = s.substr(start_point, end_point - start_point); start_point = end_point + delim_length; token.push_back(ans); } token.push_back(s.substr(start_point)); return token; } bool is_vowel(const char &a) { switch (a) { case a : case e : case i : case o : case u : case y : case A : case E : case I : case O : case U : return true; break; default: return false; break; } } void solve() { string delimiter = , ; string s; cin >> s; vector<string> e = split_string(s, delimiter); vector<long long int> a(e.size(), 0); for (long long int i = 0; i < e.size(); i++) { a[i] = stoi(e[i]); } sort(a.begin(), a.end()); auto it = std::unique(a.begin(), a.end()); a.resize(std::distance(a.begin(), it)); long long int c = a[0], k = a[0] + 1; for (long long int i = 1; i < a.size(); i++) { if (a[i] == k) k++; else { if (c + 1 == k) cout << c << , ; else cout << c << - << k - 1 << , ; c = a[i]; k = a[i] + 1; } } if (c + 1 == k) cout << c << endl; else cout << c << - << k - 1 << endl; } int32_t main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); ; solve(); return 0; } |
//This defines a very simple testbench for the instruction cacher.
//It is intended to work with "real world" access data in order to provide statistics for
//hits, misses, and whether the cache actually flipping works.
module instructioncache_tb();
reg [31:0] requestedAddresses [0:5000];
reg [31:0] addressCounter;
wire [31:0] selectedAddress;
wire [15:0] memDat;
reg clk;
wire rst;
wire wt;
wire [63:0] outWire;
wire [31:0] outAddr;
wire cachewt;
assign selectedAddress=requestedAddresses[addressCounter];
assign memDat=outAddr[15:0];
assign rst=0;
assign wt=0;
instructioncache icache(memDat, selectedAddress, clk, rst, wt, outWire, outAddr, cachewt);
reg [31:0] numMisses;
reg [31:0] numHits;
reg [31:0] numCycles;
reg [31:0] numwtCycles;
initial begin
addressCounter=0;
$readmemb("memaccess.txt", requestedAddresses);
clk=0;
numMisses=0;
numCycles=0;
numwtCycles=0;
numHits=0;
end
always begin
#1 clk=~clk;
end
always@(posedge cachewt) begin
numMisses<=numMisses+1;
end
always@(posedge clk) begin
numCycles<=numCycles+1;
if(~cachewt) begin
addressCounter<=addressCounter+1;
numHits=numHits+1;
end
else begin
numwtCycles<=numwtCycles+1;
end
end
initial begin
$display("Number of misses: %d", numMisses);
$display("Number of cycles: %d", numCycles);
$display("Number of cycles stalled: %d", numwtCycles);
$dumpfile("instructioncache_tb.vcd");
$dumpvars;
end
initial
#4000 $finish;
endmodule
|
//----------------------------------------------------------------------------
// DCR_IF Controller - DCR Bus Interface
//-----------------------------------------------------------------------------
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
// SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
// XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
// AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
// OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
// IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
// AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
// FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
// WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
// IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
// INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE.
//
// (c) Copyright 2004 Xilinx, Inc.
// All rights reserved.
//
//----------------------------------------------------------------------------
// Filename: dcr_if.v
//
// Description:
//
//
// Design Notes:
//
//-----------------------------------------------------------------------------
// Structure:
//
// -- dcr_if.v
//
//-----------------------------------------------------------------------------
// Author: CJN
// History:
// CJN
//-----------------------------------------------------------------------------
`timescale 1 ns / 100 ps
///////////////////////////////////////////////////////////////////////////////
// Module Declaration
///////////////////////////////////////////////////////////////////////////////
module dcr_if(
// DCR BUS
clk, // I
rst, // I
DCR_ABus, // I [0:9]
DCR_DBusIn, // I [0:31]
DCR_Read, // I
DCR_Write, // I
DCR_Ack, // O
DCR_DBusOut, // O [0:31]
// Registers
tft_base_addr, // O [0:10]
tft_dps_reg, // O
tft_on_reg // O
);
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input clk;
input rst;
input [0:9] DCR_ABus;
input [0:31] DCR_DBusIn;
input DCR_Read;
input DCR_Write;
output DCR_Ack;
output [0:31] DCR_DBusOut;
output [0:10] tft_base_addr;
output tft_dps_reg;
output tft_on_reg;
wire [0:31] DCR_DBusOut;
reg DCR_Ack;
///////////////////////////////////////////////////////////////////////////////
// Parameter Declarations
///////////////////////////////////////////////////////////////////////////////
parameter C_DCR_BASE_ADDR = 10'b00_0000_0000;
parameter C_DEFAULT_TFT_BASE_ADDR = 11'b000_0000_0000;
parameter C_DPS_INIT = 1'b1;
parameter C_ON_INIT = 1'b1;
///////////////////////////////////////////////////////////////////////////////
// Signal Declaration
///////////////////////////////////////////////////////////////////////////////
wire dcr_addr_hit;
wire [0:9] dcr_base_addr;
reg dcr_read_access;
reg [0:31] read_data;
reg [0:10] tft_base_addr;
reg tft_dps_reg;
reg tft_on_reg;
///////////////////////////////////////////////////////////////////////////////
// DCR Register Interface
///////////////////////////////////////////////////////////////////////////////
assign dcr_base_addr = C_DCR_BASE_ADDR;
assign dcr_addr_hit = (DCR_ABus[0:8] == dcr_base_addr[0:8]);
always @(posedge clk)
begin
dcr_read_access <= DCR_Read & dcr_addr_hit;
DCR_Ack <= (DCR_Read | DCR_Write) & dcr_addr_hit;
end
always @(posedge clk)
if (rst)
tft_base_addr <= C_DEFAULT_TFT_BASE_ADDR;
else if (DCR_Write & ~DCR_Ack & dcr_addr_hit & (DCR_ABus[9] == 1'b0))
tft_base_addr <= DCR_DBusIn[0:10];
always @(posedge clk)
if (rst) begin
tft_dps_reg <= C_DPS_INIT;
tft_on_reg <= C_ON_INIT;
end
else if (DCR_Write & ~DCR_Ack & dcr_addr_hit & (DCR_ABus[9] == 1'b1)) begin
tft_dps_reg <= DCR_DBusIn[30];
tft_on_reg <= DCR_DBusIn[31];
end
always @(posedge clk)
if (DCR_Read & dcr_addr_hit & ~DCR_Ack)
read_data <= (DCR_ABus[9] == 1'b0)? {tft_base_addr, 21'b0} :
{30'b0, tft_dps_reg, tft_on_reg};
assign DCR_DBusOut = (dcr_read_access)? read_data : DCR_DBusIn;
endmodule
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: bg5.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module bg5 (
address,
clock,
q);
input [13:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "/user6/spring14/vb2363/Desktop/sprites/sprites/bg5.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "16384"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "14"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "/user6/spring14/vb2363/Desktop/sprites/sprites/bg5.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 14 0 INPUT NODEFVAL "address[13..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 14 0 address 0 0 14 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL bg5.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg5.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg5.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg5.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg5_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg5_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
//-------------------------------------------------------------------
//-- sectones_tb.v
//-- Banco de pruebas para el secuenciador de 4 notas
//-------------------------------------------------------------------
//-- BQ August 2015. Written by Juan Gonzalez (Obijuan)
//-------------------------------------------------------------------
//-- GPL License
//-------------------------------------------------------------------
module secnotas_tb();
//-- Registro para generar la señal de reloj
reg clk = 0;
//-- Salidas de los canales
wire ch_out;
//-- Instanciar el componente y establecer el valor del divisor
//-- Se pone un valor bajo para simular (de lo contrario tardaria mucho)
secnotas #(.N0(4), .N1(3), .N2(2), .DUR(10))
dut(
.clk(clk),
.ch_out(ch_out)
);
//-- Generador de reloj. Periodo 2 unidades
always
# 1 clk <= ~clk;
//-- Proceso al inicio
initial begin
//-- Fichero donde almacenar los resultados
$dumpfile("secnotas_tb.vcd");
$dumpvars(0, secnotas_tb);
# 200 $display("FIN de la simulacion");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; int n, m, k, fa[N], cnt[N], vis[N]; vector<int> G[N]; vector<pair<int, int> > p, q[N]; int findset(int x) { return x == fa[x] ? x : fa[x] = findset(fa[x]); } void dfs(int x) { vis[x] = 1; for (auto it : G[x]) dfs(it); for (auto it : q[x]) if (vis[it.first]) cnt[it.second]++; vis[x] = 0; } int main() { scanf( %d%d , &n, &m); for (int i = 0; i <= n; i++) fa[i] = i; int opt, x, y; while (m--) { scanf( %d %d , &opt, &x); if (opt == 1) scanf( %d , &y), fa[x] = y, G[y].push_back(x); else if (opt == 2) p.push_back({findset(x), x}); else { scanf( %d , &y); q[x].push_back({p[y - 1].first, k}); q[p[y - 1].second].push_back({x, k}); k++; } } for (int i = 1; i <= n; i++) if (fa[i] == i) dfs(i); for (int i = 0; i < k; i++) printf( %s n , cnt[i] == 2 ? YES : NO ); return 0; } |
`default_nettype none
`include "core.h"
module execute_logic_decode(
input wire [4:0] iPREV_INST,
output wire [4:0] oNEXT_INST
);
function [4:0] func_logic_select;
input [4:0] func_logic_select_cmd;
begin
case(func_logic_select_cmd)
`EXE_LOGIC_BUFFER0 : func_logic_select = 5'h00;
`EXE_LOGIC_BUFFER1 : func_logic_select = 5'h01;
`EXE_LOGIC_AND : func_logic_select = 5'h04;
`EXE_LOGIC_OR : func_logic_select = 5'h05;
`EXE_LOGIC_XOR : func_logic_select = 5'h06;
`EXE_LOGIC_NOT : func_logic_select = 5'h02;
`EXE_LOGIC_NAND : func_logic_select = 5'h07;
`EXE_LOGIC_NOR : func_logic_select = 5'h08;
`EXE_LOGIC_XNOR : func_logic_select = 5'h09;
`EXE_LOGIC_TEST : func_logic_select = 5'h04;
`EXE_LOGIC_WBL : func_logic_select = 5'h10;
`EXE_LOGIC_WBH : func_logic_select = 5'h11;
`EXE_LOGIC_CLB : func_logic_select = 5'h0A;
`EXE_LOGIC_STB : func_logic_select = 5'h0B;
`EXE_LOGIC_CLW : func_logic_select = 5'h15;
`EXE_LOGIC_STW : func_logic_select = 5'h16;
`EXE_LOGIC_BITREV : func_logic_select = 5'h0C;
`EXE_LOGIC_BYTEREV : func_logic_select = 5'h0D;
`EXE_LOGIC_GETBIT : func_logic_select = 5'h0E;
`EXE_LOGIC_GETBYTE : func_logic_select = 5'h0F;
`EXE_LOGIC_LIL : func_logic_select = 5'h12;
`EXE_LOGIC_LIH : func_logic_select = 5'h01;
`EXE_LOGIC_ULIL : func_logic_select = 5'h14;
default
begin
func_logic_select = 5'h00;
end
endcase
end
endfunction
assign oNEXT_INST = func_logic_select(iPREV_INST);
endmodule
`default_nettype wire
|
/*module spi_rcv(CLK, SCK, MOSI, MISO, SSEL, LED);
input wire CLK, SCK, SSEL, MOSI;
output wire MISO, LED;
wire [7:0] MSG;
spi_slave spi1(.CLK(CLK),
.SCK(SCK),
.MOSI(MOSI),
.MISO(MISO),
.SSEL(SSEL),
.MSG(MSG));
assign LED = (MSG==8'b11111111);*/
module spi_rcv(clk,
led_gnd1, led_gnd2, //LED grounds
led6, led7, led8, led9, led10, led12, led13, led15, led16, led17, led18, led19, led20, led21,
led_second_tick
);
input wire clk;
output wire led_gnd1, led_gnd2;
output wire led6, led7, led8, led9, led10, led12, led13, led15, led16, led17, led18, led19, led20, led21;
output wire led_second_tick;
//clk - general clock 32768
reg [14:0] clk_div; initial clk_div <= 15'd0; //?? may be not implement
always @(posedge clk) clk_div <= clk_div + 1'b1;
wire divided_clk = clk_div[4];
reg divided_clk_prev;
always @(posedge clk) divided_clk_prev <= divided_clk;
wire divided_clk_posedge = ((divided_clk_prev==1'b0)&&(divided_clk==1'b1));
wire res;
pu_reset res_gen(.clk(clk), .res(res));
reg [3:0] gnd_sel;
always @(posedge clk) begin
if (res) begin
gnd_sel <= 4'b0001;
end else begin
if (divided_clk_posedge) gnd_sel <= {gnd_sel[2],gnd_sel[1],gnd_sel[0],gnd_sel[3]};
end
end
assign led_gnd1 = gnd_sel[0];
assign led_gnd2 = gnd_sel[2];
/*
wire [3:0] m = 0;
wire [3:0] mm;
wire [3:0] h;
wire [3:0] hh;
wire [6:0] s_m;
wire [6:0] s_mm;
wire [6:0] s_h;
wire [6:0] s_hh;
bcd2seg sseg_m( .sin(m), .sout(s_m));
bcd2seg sseg_mm(.sin(mm), .sout(s_mm));
bcd2seg sseg_h( .sin(h), .sout(s_h));
bcd2seg sseg_hh(.sin(hh), .sout(s_hh));
wire a1,b1,c1,d1,e1,f1,g1;
wire a2,b2,c2,d2,e2,f2,g2;
wire a3,b3,c3,d3,e3,f3,g3;
wire a4,b4,c4,d4,e4,f4,g4;
assign {g4, f4, e4, d4, c4, b4, a4} = s_m;
assign {g3, f3, e3, d3, c3, b3, a3} = s_mm;
assign {g2, f2, e2, d2, c2, b2, a2} = s_h;
assign {g1, f1, e1, d1, c1, b1, a1} = s_hh;
*/
//hide hour zero
//wire h_show = !(hh==0);
assign led6 = (led_gnd1 || led_gnd2) ? 1 : 0;//(led_gnd1&&(b1&&h_show)) || (led_gnd2&&(b1&&h_show)); // b1
assign led7 = (led_gnd1 || led_gnd2) ? 1 : 0;//(led_gnd1&&(a1&&h_show)) || (led_gnd2&&(g1&&h_show)); // a1/g1
assign led8 = (led_gnd1 || led_gnd2) ? 1 : 0;//(led_gnd1&&(d1&&h_show)) || (led_gnd2&&(e1&&h_show)); // d1/e1
assign led9 = (led_gnd1 || led_gnd2) ? 1 : 0;//(led_gnd1&&e2) || (led_gnd2&&(c1&&h_show)); // e2/c1
assign led10 = (led_gnd1 || led_gnd2) ? 1 : 0;//(led_gnd1&&g2) || (led_gnd2&&b2); // g2/b2
assign led12 = (led_gnd1 || led_gnd2) ? 1 : 0;//(led_gnd1&&d2) || (led_gnd2&&c2); // d2/c2
assign led13 = (led_gnd1 || led_gnd2) ? 1 : 0;//(led_gnd1&&f2) || (led_gnd2&&a2); // f2/a2
assign led15 = (led_gnd1 || led_gnd2) ? 1 : 0;//(led_gnd1&&a3) || (led_gnd2&&f3); // a3/f3
assign led16 = (led_gnd1 || led_gnd2) ? 1 : 0;//(led_gnd1&&b3) || (led_gnd2&&g3); // b3/g3
assign led17 = (led_gnd1 || led_gnd2) ? 1 : 0;//(led_gnd1&&c3) || (led_gnd2&&d3); // c3/d3
assign led18 = (led_gnd1 || led_gnd2) ? 1 : 0;//(led_gnd1&&e4) || ((led_gnd2)&&e3); // e3/e4 !!
assign led19 = (led_gnd1 || led_gnd2) ? 1 : 0;//(led_gnd1&&g4) || ((led_gnd2)&&b4); // g4/b4
assign led20 = (led_gnd1 || led_gnd2) ? 1 : 0;//(led_gnd1&&d4) || ((led_gnd2)&&c4); // d4/c4
assign led21 = (led_gnd1 || led_gnd2) ? 1 : 0;//(led_gnd1&&f4) || ((led_gnd2)&&a4); // f4/a4
//one second tick indicator
//assign led_second_tick = led_gnd1 && clk_div[14];
assign led_second_tick = 1;
endmodule
module pu_reset(clk, res);
input wire clk;
output wire res;
reg [3:0] res_cntr;
assign res = (res_cntr!=4'b1111);
wire [3:0] next_res_cntr = (res) ? res_cntr : res_cntr + 1'b1;
always @(posedge clk) res_cntr <= next_res_cntr;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long t1, t2, x1, x2, t0, y1, y2; cin >> t1 >> t2 >> x1 >> x2 >> t0; if (t1 == t2) cout << x1 << << x2 << endl; else if (t1 == t0) cout << x1 << << 0 << endl; else if (t2 == t0) cout << 0 << << x2 << endl; else { y1 = 0; y2 = x2; long double min_diff = t2 - t0; for (long long i = 1; i <= x1; i++) { long long j = ((t0 - t1) * i + (t2 - t0 - 1)) / (t2 - t0); if (j > x2) continue; long double temp = (t1 * i + t2 * j + 0.0) / (i + j + 0.0); long double diff = temp - t0; if (min_diff > diff) { min_diff = diff; y1 = i; y2 = j; } else if (min_diff == diff && i + j > y1 + y2) { y1 = i; y2 = j; } } cout << y1 << << y2 << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const long long N = 2e5 + 5; long long gcd(long long n, long long m) { if (n == 0) return m; else return gcd(m % n, n); } long long a[105], b[105]; vector<pair<long long, long long> > v1, v2; long long dp[103][60000]; long long go(long long pos, long long r) { if (r < 0) return -MOD; if (pos == v2.size()) { return 0; } long long &ans = dp[pos][r]; if (ans != -1) return ans; ans = go(pos + 1, r); if (r >= a[v2[pos].second]) { ans = max(ans, go(pos + 1, r + b[v2[pos].second]) + 1); } return ans; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); long long n, r; cin >> n >> r; for (long long i = 1; i <= n; i++) { cin >> a[i] >> b[i]; if (b[i] >= 0) { v1.push_back({a[i], b[i]}); } else { v2.push_back({-(a[i] + b[i]), i}); } } memset(dp, -1, sizeof(dp)); if (v1.size() > 0) { sort(v1.begin(), v1.end()); long long ans = 0; for (long long i = 0; i < v1.size(); i++) { if (r >= v1[i].first) { r += v1[i].second; ans++; } } if (v2.size() == 0) { cout << ans << endl; return 0; } sort(v2.begin(), v2.end()); long long k = go(0, r); cout << ans + k << endl; } else { sort(v2.begin(), v2.end()); cout << go(0, r) << endl; } } |
#include <bits/stdc++.h> using namespace std; string s, u; stack<char> t; vector<char> mins; int main() { cin >> s; u = ; int inicio = 0, tam = s.length(); char ant = z + 1; for (int i = tam - 1; i >= 0; i--) { ant = min(ant, s[i]); mins.push_back(ant); } reverse(mins.begin(), mins.end()); while (inicio < tam) { if (t.empty()) { t.push(s[inicio]); inicio++; } else { if (t.top() <= mins[inicio]) { u += t.top(); t.pop(); } else { t.push(s[inicio]); inicio++; } } } while (!t.empty()) { u += t.top(); t.pop(); } if (inicio < tam) { u += s[inicio]; } cout << u << n ; } |
(*
Copyright © 2006-2008 Russell O’Connor
Copyright © 2020 Vincent Semeria
Permission is hereby granted, free of charge, to any person obtaining a copy of
this proof and associated documentation files (the "Proof"), to deal in
the Proof without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
the Proof, and to permit persons to whom the Proof is furnished to do so,
subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Proof.
THE PROOF IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE PROOF OR THE USE OR OTHER DEALINGS IN THE PROOF.
*)
Require Export Coq.QArith.QArith.
Require Import CoRN.algebra.RSetoid.
Require Import MathClasses.interfaces.canonical_names.
Require Import MathClasses.interfaces.abstract_algebra.
Local Open Scope Q_scope.
Set Implicit Arguments.
(**
* Metric Space
We define a metric space over a setoid X by a ball relation B
where B e x y means that the distance between the two points
x and y is less than or equal to the rational number e ( d(x,y) <= e ).
We do not take the usual definition of a distance function d : X^2 -> R_+,
because constructively this function would have to be computable.
For example this would prevent us to define metrics on functions
d(f,g) := inf_x d(f(x), g(x))
where the infinimum does not always exist constructively.
By using ball propositions instead, we make the distance function partial,
it is not always defined. For topological applications, it is often enough
to bound the distance instead of computing it exactly, this is
precisely what the balls do.
Interestingly, this definition by balls also handles infinite distances,
by proving that forall e, not (B e x y). It generalizes the usual distance functions.
This definition uses rational numbers instead of real numbers,
which is simpler. It allows to define the real numbers as a certain metric
space, namely the Cauchy completion of the rational numbers.
Lastly, this definition could include one other property of the distance functions
e < d -> {B d x y}+{~B e x y}.
But those properties are only used late in the proofs, so we move them
as additional definitions in module Classification.v (stability and locatedness).
*)
Record is_MetricSpace {X : Type} (B: Q -> relation X) : Prop :=
{ msp_refl: forall e, 0 <= e -> Reflexive (B e)
; msp_sym: forall e, Symmetric (B e)
; msp_triangle: forall e1 e2 a b c, B e1 a b -> B e2 b c -> B (e1 + e2) a c
; msp_closed: forall e a b, (forall d, 0 < d -> B (e + d) a b) -> B e a b
; msp_nonneg : forall e a b, B e a b -> 0 <= e
; msp_stable : forall e a b, (~~B e a b) -> B e a b
}.
Record MetricSpace : Type :=
{ msp_car :> Type
; ball : Q -> msp_car -> msp_car -> Prop
; ball_e_wd : forall (e d : Q) (x y : msp_car),
e == d -> (ball e x y <-> ball d x y)
; msp : is_MetricSpace ball
}.
(* begin hide *)
Arguments ball [m].
Definition msp_eq {m:MetricSpace} (x y : msp_car m) : Prop
:= ball 0 x y.
Instance msp_Equiv (m : MetricSpace) : Equiv m := @msp_eq m.
Add Parametric Morphism {m:MetricSpace} : (@ball m)
with signature Qeq ==> (@msp_eq m) ==> (@msp_eq m) ==> iff as ball_wd.
Proof.
unfold msp_eq. split.
- intros.
assert (0+(x+0) == y).
{ rewrite Qplus_0_r, Qplus_0_l. exact H. }
apply (ball_e_wd m y0 y1 H3).
clear H H3 y.
apply (msp_triangle (msp m)) with (b:=x0).
apply (msp_sym (msp m)), H0.
apply (msp_triangle (msp m)) with (b:=x1).
exact H2. exact H1.
- intros.
assert (0+(y+0) == x).
{ rewrite Qplus_0_r, Qplus_0_l, H. reflexivity. }
apply (ball_e_wd m x0 x1 H3).
clear H H3 x.
apply (msp_triangle (msp m)) with (b:=y0).
exact H0. clear H0 x0.
apply (msp_triangle (msp m)) with (b:=y1).
exact H2.
apply (msp_sym (msp m)), H1.
Qed.
Lemma msp_eq_refl : forall {m:MetricSpace} (x : m),
msp_eq x x.
Proof.
intros. apply (msp_refl (msp m) (Qle_refl 0)).
Qed.
Lemma msp_eq_sym : forall {m:MetricSpace} (x y : m),
msp_eq x y -> msp_eq y x.
Proof.
intros. apply (msp_sym (msp m)), H.
Qed.
Lemma msp_eq_trans : forall {m:MetricSpace} (x y z : m),
msp_eq x y -> msp_eq y z -> msp_eq x z.
Proof.
unfold msp_eq. intros.
rewrite <- (ball_wd m (Qplus_0_r 0)
x x (msp_eq_refl x)
z z (msp_eq_refl z)).
exact (msp_triangle (msp m) _ _ _ y _ H H0).
Qed.
Add Parametric Relation {m:MetricSpace} : (msp_car m) msp_eq
reflexivity proved by (msp_eq_refl)
symmetry proved by (msp_eq_sym)
transitivity proved by (msp_eq_trans)
as msp_eq_rel.
(* end hide *)
Instance msp_Setoid (m : MetricSpace) : Setoid m := {}.
Definition msp_as_RSetoid : MetricSpace -> RSetoid
:= fun m => Build_RSetoid (msp_Setoid m).
Section Metric_Space.
(*
** Ball lemmas
*)
Variable X : MetricSpace.
(** These lemmas give direct access to the ball axioms of a metric space
*)
Lemma ball_refl : forall e (a:X), 0 <= e -> ball e a a.
Proof.
intros. apply (msp_refl (msp X) H).
Qed.
Lemma ball_sym : forall e (a b:X), ball e a b -> ball e b a.
Proof.
apply (msp_sym (msp X)).
Qed.
Lemma ball_triangle : forall e1 e2 (a b c:X),
ball e1 a b -> ball e2 b c -> ball (e1 + e2) a c.
Proof.
apply (msp_triangle (msp X)).
Qed.
Lemma ball_closed : forall e (a b:X),
(forall d, 0 < d -> ball (e + d) a b) -> ball e a b.
Proof.
apply (msp_closed (msp X)).
Qed.
Lemma ball_eq : forall (a b:X), (forall e, 0 < e -> ball e a b) -> msp_eq a b.
Proof.
intros. apply ball_closed.
intros. rewrite Qplus_0_l.
apply H, H0.
Qed.
Lemma ball_eq_iff : forall (a b:X),
(forall e, 0 < e -> ball e a b) <-> msp_eq a b.
Proof.
split.
apply ball_eq.
intros H e epos.
rewrite H. apply ball_refl.
apply Qlt_le_weak, epos.
Qed.
(** The ball constraint on a and b can always be weakened. Here are
two forms of the weakening lemma.
*)
Lemma ball_weak : forall e d (a b:X),
0 <= d -> ball e a b -> ball (e + d) a b.
Proof.
intros e d a b dpos B1.
eapply ball_triangle.
apply B1.
apply ball_refl. exact dpos.
Qed.
Hint Resolve ball_refl ball_triangle ball_weak : metric.
Lemma ball_weak_le : forall (e d:Q) (a b:X),
e <= d -> ball e a b -> ball d a b.
Proof.
intros e d a b Hed B1.
setoid_replace d with (e + (d-e)) by ring.
apply (ball_triangle _ _ _ b). exact B1.
apply ball_refl.
unfold Qminus. rewrite <- Qle_minus_iff. exact Hed.
Qed.
(* If d(x,y) is infinite and d(x,z) is finite, then d(z,y) is infinite. *)
Lemma ball_infinite
: forall (x y z : X) (e : Q),
(forall d : Q, ~ball d x y)
-> ball e x z
-> (forall d : Q, ~ball d z y).
Proof.
intros. intro abs.
apply (H (e+d)).
exact (ball_triangle e d x z y H0 abs).
Qed.
Lemma ball_stable : forall e (x y : X),
~~(ball e x y) -> ball e x y.
Proof.
intros. apply (msp_stable (msp X)), H.
Qed.
End Metric_Space.
(* begin hide *)
Hint Resolve ball_refl ball_sym ball_triangle ball_weak : metric.
(* end hide *)
|
#include <bits/stdc++.h> using namespace std; int dfs(int n) {} int main() { int n, k, x, y, a[200200], b[200200]; cin >> n >> k; vector<vector<int> > v(n, vector<int>()); for (int i = 0; i < n; i++) { cin >> a[i]; b[i] = a[i]; } for (int i = 0; i < k; i++) { cin >> x >> y; v[x - 1].push_back(y - 1); v[y - 1].push_back(x - 1); } sort(b, b + n); for (int i = 0; i < n; i++) { int x = i, res = lower_bound(b, b + n, a[i]) - b; for (int j = 0; j < v[i].size(); j++) if (a[v[i][j]] < a[i]) res--; cout << res << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; int n; double res; double x[60006], v[60006]; bool ok(double t) { double l, r; l = 1e-9; r = 1e9; for (int i = 1; i <= n; ++i) { double m = t * v[i]; l = max(l, x[i] - m); r = min(r, x[i] + m); } return (l <= r); } int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) cin >> x[i]; for (int i = 1; i <= n; ++i) cin >> v[i]; double l, r, mid; l = 0.0, r = 1e9; while (abs(l - r) > 1e-6) { mid = (l + r) / 2; if (ok(mid)) { res = mid; r = mid; } else l = mid; } cout << fixed << setprecision(20) << res; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_HL_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__LSBUFHV2HV_HL_PP_SYMBOL_V
/**
* lsbufhv2hv_hl: Level shifting buffer, High Voltage to High Voltage,
* Higher Voltage to Lower Voltage.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__lsbufhv2hv_hl (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input LOWHVPWR,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2HV_HL_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 200005, P = 1e9 + 7; int dp[N][3], val[3], n; int add(int a, int b) { return (a += b) >= P ? a - P : a; } int qpow(int a, int b) { int res = 1; while (b) { if (b & 1) res = 1ll * res * a % P; a = 1ll * a * a % P; b >>= 1; } return res; } int main() { string s; cin >> n >> s; s = % + s; int qs = count(s.begin(), s.end(), ? ); const int f3 = qpow(3, qs), inv3 = qpow(3, P - 2); for (int i = 1; i <= n; ++i) { if (s[i] == a ) { dp[i][1] = dp[i][2] = 0; dp[i][0] = 1; val[0] = add(val[0], 1); } else if (s[i] == b ) { dp[i][0] = dp[i][2] = 0; dp[i][1] = val[0]; val[1] = add(val[1], dp[i][1]); } else if (s[i] == c ) { dp[i][0] = dp[i][1] = 0; dp[i][2] = val[1]; val[2] = add(val[2], dp[i][2]); } else { dp[i][0] = inv3; dp[i][1] = (long long)inv3 * val[0] % P; dp[i][2] = (long long)inv3 * val[1] % P; val[0] = add(val[0], inv3); val[1] = add(val[1], dp[i][1]); val[2] = add(val[2], dp[i][2]); } } cout << (long long)val[2] * f3 % P << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long int N = 1e5; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long int tc = 1; for (long long int T = 1; T <= tc; T++) { long long int n; cin >> n; string s; cin >> s; long long int cnt = 0, flag = 0; for (long long int i = 0; i < n - 1; i++) { if (s[i] == s[i + 1] and s[i] != ? ) { flag = 1; break; } } if (flag) { cout << No n ; return 0; } if (s[0] == ? or s[n - 1] == ? ) { cout << Yes n ; return 0; } long long int tot = 0, ok = 0; char start = $ , end = $ ; for (long long int i = 0; i < n; i++) { if (s[i] != ? and flag == 0) { start = s[i]; } else if (s[i] == ? ) { cnt++; flag = 1; } else { end = s[i]; if (cnt == 1) { if (start == end) { ok = 1; break; } } else { ok = 1; break; } start = end; cnt = 0; flag = 0; } } if (ok) cout << Yes n ; else cout << No n ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND3_1_V
`define SKY130_FD_SC_HD__AND3_1_V
/**
* and3: 3-input AND.
*
* Verilog wrapper for and3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__and3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and3_1 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and3_1 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND3_1_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Varun Koyyalagunta.
// bug1015
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [1:0] i = crc[1:0];
logic [1:0] o [13:10] ;
Test test (/*AUTOINST*/
// Outputs
.o (o/*[1:0].[3:0]*/),
// Inputs
.i (i[1:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, 6'h0,o[13], 6'h0,o[12], 6'h0,o[11], 6'h0,o[10]};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x sum=%x\n",$time, cyc, crc, result, sum);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
end
else if (cyc<10) begin
sum <= '0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hb42b2f48a0a9375a
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test
(
output logic [1:0] o [3:0],
//but this works
//logic [N-1:0] o
input [1:0] i);
parameter N = 4;
logic [1:0] a [3:0]; initial a = '{2'h0,2'h1,2'h2,2'h3};
sub sub [N-1:0] (.o (o), // many-to-many
.a (a), // many-to-many
.i (i)); // many-to-one
endmodule
module sub
(
input logic [1:0] i,
input logic [1:0] a,
output logic [1:0] o
);
assign o = i + a;
endmodule
|
// This is the second part of a two-part test that checks that the argument to
// a $signed or $unsigned function is treated as a self-determined expression.
// This part performs tests where the argument is signed.
module pr2922063b;
reg signed [3:0] op1;
reg signed [2:0] op2;
reg [7:0] result;
reg fail;
task check_result;
input [7:0] value;
begin
$write("Expected %b, got %b", value, result);
if (result !== value) begin
$write(" *");
fail = 1;
end
$write("\n");
end
endtask
initial begin
fail = 0;
$display("-- Addition tests --");
op1 = 4'b1111; op2 = 3'b111;
result = 8'sd0 + $signed(op1 + op2);
check_result(8'b11111110);
result = 8'sd0 + $unsigned(op1 + op2);
check_result(8'b00001110);
op1 = 4'b1000; op2 = 3'b011;
result = 8'sd0 + $signed(op1 + op2);
check_result(8'b11111011);
result = 8'sd0 + $unsigned(op1 + op2);
check_result(8'b00001011);
$display("-- Multiply tests --");
op1 = 4'b0101; op2 = 3'b100;
result = 8'sd0 + $signed(op1 * op2);
check_result(8'b11111100);
result = 8'sd0 + $unsigned(op1 * op2);
check_result(8'b00001100);
op1 = 4'b0010; op2 = 3'b100;
result = 8'sd0 + $signed(op1 * op2);
check_result(8'b11111000);
result = 8'sd0 + $unsigned(op1 * op2);
check_result(8'b00001000);
$display("-- Left ASR tests --");
op1 = 4'b1010;
result = 8'sd0 + $signed(op1 <<< 1);
check_result(8'b00000100);
result = 8'sd0 + $unsigned(op1 <<< 1);
check_result(8'b00000100);
op1 = 4'b0101;
result = 8'sd0 + $signed(op1 <<< 1);
check_result(8'b11111010);
result = 8'sd0 + $unsigned(op1 <<< 1);
check_result(8'b00001010);
$display("-- Right ASR tests --");
op1 = 4'b0101;
result = 8'sd0 + $signed(op1 >>> 1);
check_result(8'b00000010);
result = 8'sd0 + $unsigned(op1 >>> 1);
check_result(8'b00000010);
op1 = 4'b1010;
result = 8'sd0 + $signed(op1 >>> 1);
check_result(8'b11111101);
result = 8'sd0 + $unsigned(op1 >>> 1);
check_result(8'b00001101);
if (fail)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T, typename U> inline void smin(T &a, U b) { if (a > b) a = b; } template <typename T, typename U> inline void smax(T &a, U b) { if (a < b) a = b; } template <typename T> inline void gn(T &first) { char c, sg = 0; while (c = getchar(), (c > 9 || c < 0 ) && c != - ) ; for ((c == - ? sg = 1, c = getchar() : 0), first = 0; c >= 0 && c <= 9 ; c = getchar()) first = (first << 1) + (first << 3) + c - 0 ; if (sg) first = -first; } template <class T, class T1> inline void gn(T &first, T1 &second) { gn(first); gn(second); } template <class T, class T1, class T2> inline void gn(T &first, T1 &second, T2 &z) { gn(first); gn(second); gn(z); } template <typename T> inline void print(T first) { if (first < 0) { putchar( - ); return print(-first); } if (first < 10) { putchar( 0 + first); return; } print(first / 10); putchar(first % 10 + 0 ); } template <typename T> inline void println(T first) { print(first), putchar( n ); } template <typename T> inline void printsp(T first) { print(first), putchar( ); } template <class T, class T1> inline void print(T first, T1 second) { printsp(first), println(second); } template <class T, class T1, class T2> inline void print(T first, T1 second, T2 z) { printsp(first), printsp(second), println(z); } int power(int a, int b, int m, int ans = 1) { for (; b; b >>= 1, a = 1LL * a * a % m) if (b & 1) ans = 1LL * ans * a % m; return ans; } int E, head[5050], to[5050], nxt[5050]; void init(int n) { E = 0; for (int i = 1; i <= n; i++) head[i] = -1; } void add_edge(int u, int v) { nxt[E] = head[u]; to[E] = v; head[u] = E++; } int dp[2][5050][5050], c[5050], d[5050]; int sz[5050]; void dfs(int u) { dp[1][u][0] = 0; dp[0][u][0] = 0; dp[1][u][1] = c[u] - d[u]; dp[0][u][1] = c[u]; sz[u] = 1; for (int e = head[u]; ~e; e = nxt[e]) { int v = to[e]; dfs(v); for (int i = sz[u] + sz[v]; i >= 1; i--) { for (int j = min(i, sz[v]); j >= 0 && i - j <= sz[u]; j--) { smin(dp[0][u][i], dp[0][u][i - j] + dp[0][v][j]); if (i && j < i) smin(dp[1][u][i], dp[1][u][i - j] + dp[1][v][j]); } } sz[u] += sz[v]; } for (int i = 1; i <= sz[u]; i++) smin(dp[1][u][i], dp[0][u][i]); } int main() { int n, b; gn(n, b); init(n); memset(dp, 0x3f, sizeof(dp)); for (int i = 1, first; i <= n; i++) { gn(c[i], d[i]); if (i > 1) { gn(first); add_edge(first, i); } } dfs(1); int ans = 0; for (int i = 1; i <= n; i++) if (dp[1][1][i] <= b) ans = i; println(ans); return 0; } |
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_hdiv(
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output reg pipe_ack_o,
input signed [11:0] x,
input signed [11:0] y,
input signed [17:0] tsx,
input signed [17:0] tsy,
input diff_x_positive,
input [16:0] diff_x,
input diff_y_positive,
input [16:0] diff_y,
input [10:0] dst_squarew,
output reg pipe_stb_o,
input pipe_ack_i,
output reg signed [11:0] x_f,
output reg signed [11:0] y_f,
output reg signed [17:0] tsx_f,
output reg signed [17:0] tsy_f,
output reg diff_x_positive_f,
output [16:0] diff_x_q,
output [16:0] diff_x_r,
output reg diff_y_positive_f,
output [16:0] diff_y_q,
output [16:0] diff_y_r
);
/* Divider bank */
reg start;
wire ready;
tmu2_divider17 d_x(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.start(start),
.dividend(diff_x),
.divisor({6'd0, dst_squarew}),
.ready(ready),
.quotient(diff_x_q),
.remainder(diff_x_r)
);
tmu2_divider17 d_y(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.start(start),
.dividend(diff_y),
.divisor({6'd0, dst_squarew}),
.ready(),
.quotient(diff_y_q),
.remainder(diff_y_r)
);
/* Forward */
always @(posedge sys_clk) begin
if(start) begin
x_f <= x;
y_f <= y;
tsx_f <= tsx;
tsy_f <= tsy;
diff_x_positive_f <= diff_x_positive;
diff_y_positive_f <= diff_y_positive;
end
end
/* Glue logic */
reg state;
reg next_state;
parameter IDLE = 1'b0;
parameter WAIT = 1'b1;
always @(posedge sys_clk) begin
if(sys_rst)
state = IDLE;
else
state = next_state;
end
assign busy = state;
always @(*) begin
next_state = state;
start = 1'b0;
pipe_stb_o = 1'b0;
pipe_ack_o = 1'b0;
case(state)
IDLE: begin
pipe_ack_o = 1'b1;
if(pipe_stb_i) begin
start = 1'b1;
next_state = WAIT;
end
end
WAIT: begin
if(ready) begin
pipe_stb_o = 1'b1;
if(pipe_ack_i)
next_state = IDLE;
end
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int digit[32]; long long dp[32][32][2]; long long dfs(int p, int k, bool tag) { int i; long long ret = 0; if (p == -1) return 1; if (~dp[p][k][tag]) return dp[p][k][tag]; if (!k) ret = (ret + dfs(p - 1, k, tag && !digit[p])) % 1000000007; else { ret = (ret + (dfs(p - 1, k, tag && !digit[p]) << (k - 1)) % 1000000007) % 1000000007; if (!tag || digit[p]) ret = (ret + (dfs(p - 1, k, tag) << (k - 1)) % 1000000007) % 1000000007; } if (!tag || digit[p]) ret = (ret + dfs(p - 1, k + 1, tag && digit[p])) % 1000000007; return dp[p][k][tag] = ret; } int main() { int k, p; while (cin >> k) { memset(dp, -1, sizeof(dp)); for (p = 0; k; k >>= 1) digit[p++] = (k & 1); cout << dfs(p - 1, 0, true) << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long inf = 1e16; const int maxn = 1e5; pair<long long, int> tree[4 * maxn + 11]; long long ans[maxn + 11]; long long minn[4 * maxn + 11], lazy[4 * maxn + 11]; set<pair<long long, int> > t; void push_up(int rt) { tree[rt] = min(tree[rt << 1], tree[rt << 1 | 1]); } void build(int rt, int l, int r) { if (l == r) { tree[rt] = make_pair(inf, l); return; } int mid = (l + r) >> 1; build(rt << 1, l, mid); build(rt << 1 | 1, mid + 1, r); push_up(rt); } void update(int rt, int l, int r, int pos, long long val) { if (l > pos || r < pos) return; if (l == r) { tree[rt] = make_pair(val, l); return; } int mid = (l + r) >> 1; update(rt << 1, l, mid, pos, val); update(rt << 1 | 1, mid + 1, r, pos, val); push_up(rt); } void Push_up(int rt) { minn[rt] = min(minn[rt << 1], minn[rt << 1 | 1]); } void push_down(int rt) { if (minn[rt << 1] < inf) { minn[rt << 1] -= lazy[rt]; lazy[rt << 1] += lazy[rt]; } if (minn[rt << 1 | 1] < inf) { minn[rt << 1 | 1] -= lazy[rt]; lazy[rt << 1 | 1] += lazy[rt]; } lazy[rt] = 0; minn[rt << 1] = max(minn[rt << 1], 0ll); minn[rt << 1 | 1] = max(minn[rt << 1 | 1], 0ll); } void update(int rt, int l, int r, int al, int ar, long long val) { if (l > ar || r < al) return; if (l >= al && r <= ar) { minn[rt] -= val; minn[rt] = max(minn[rt], 0ll); lazy[rt] += val; return; } int mid = (l + r) >> 1; if (lazy[rt]) push_down(rt); update(rt << 1, l, mid, al, ar, val); update(rt << 1 | 1, mid + 1, r, al, ar, val); Push_up(rt); } pair<long long, int> query(int rt, int l, int r, int al, int ar) { if (l > ar || r < al) return make_pair(inf, maxn + 1); if (l >= al && r <= ar) return tree[rt]; int mid = (l + r) >> 1; return min(query(rt << 1, l, mid, al, ar), query(rt << 1 | 1, mid + 1, r, al, ar)); } pair<long long, int> query(int rt, int l, int r) { int mid = (l + r) >> 1; if (l == r) return make_pair(minn[rt], l); if (lazy[rt]) push_down(rt); if (minn[rt << 1] <= minn[rt << 1 | 1]) return query(rt << 1, l, mid); return query(rt << 1 | 1, mid + 1, r); } void upd(int rt, int l, int r, int pos, long long val) { if (l > pos || r < pos) return; if (l == r) { minn[rt] = val; return; } int mid = (l + r) >> 1; if (lazy[rt]) push_down(rt); upd(rt << 1, l, mid, pos, val); upd(rt << 1 | 1, mid + 1, r, pos, val); Push_up(rt); } int main() { int n; long long p; cin >> n >> p; build(1, 1, n); for (int i = 1; i <= 4 * n; i++) minn[i] = inf, lazy[i] = 0; for (int i = 1; i <= n; i++) { long long x; cin >> x; update(1, 1, n, i, x); upd(1, 1, n, i, x); } int out = 0; queue<int> q; set<int> s; long long Pas = 0; long long res = p; while (out < n) { if (q.empty()) { pair<long long, int> pi = query(1, 1, n); Pas += pi.first; update(1, 1, n, 1, n, pi.first); s.insert(pi.second); q.push(pi.second); upd(1, 1, n, pi.second, inf); } else { int lef = *s.begin(); if (lef == 1) { Pas += p; res = p; update(1, 1, n, 1, n, p); ans[q.front()] = Pas; update(1, 1, n, q.front(), inf); s.erase(q.front()); q.pop(); out++; } else { pair<long long, int> pi = query(1, 1, n, 1, lef - 1); if (Pas + res > pi.first) { res -= pi.first - Pas; q.push(pi.second); upd(1, 1, n, pi.second, inf); s.insert(pi.second); } else { Pas += p; res = p; update(1, 1, n, 1, n, p); ans[q.front()] = Pas; update(1, 1, n, q.front(), inf); s.erase(q.front()); q.pop(); out++; } } } } for (int i = 1; i <= n; i++) cout << ans[i] << ; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Tecnológico de Costa Rica
// Engineer: Juan José Rojas Salazar
//
// Create Date: 30.07.2016 10:22:05
// Design Name:
// Module Name: V_NORM_FLOAT_TO_FIXED
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
//////////////////////////////////////////////////////////////////////////////////
module V_NORM_FLOAT_TO_FIXED(
//INPUTS
input wire CLK, //system clock
input wire [31:0] F, //VALOR BINARIO EN COMA FLOTANTE
input wire RST_FF, //system reset
input wire Begin_FSM_FF, //INICIA LA CONVERSION
//OUTṔUTS
output wire ACK_FF,//INDICA QUE LA CONVERSION FUE REALIZADA
output wire [31:0] RESULT // RESULTADO FINAL
);
wire Exp_out;
wire [7:0] Exp;
wire EN_REG1;
wire EN_REG2;
wire RST;
wire LOAD;
wire MS_1;
wire EN_MS_1;
wire MS_1_reg;
FSM_Convert_Float_To_Fixed FSM_CONVERT_FLOAT_FIXED(
.CLK(CLK), //system clock
.RST_FF(RST_FF), //system reset
.Exp_out(Exp_out),
.Begin_FSM_FF(Begin_FSM_FF), //inicia la maquina de estados
.Exp(Exp),
.EN_REG1(EN_REG1),
.LOAD(LOAD),
.MS_1(MS_1),
.ACK_FF(ACK_FF),
.EN_MS_1(EN_MS_1),
.EN_REG2(EN_REG2),
.RST(RST)
);
FF_D #(.P(1)) REG_MS_1V(
.CLK(CLK), //RELOJ DEL SISTEMA
.RST(RST), //RESET
.EN(EN_MS_1), //ENABLE
.D(MS_1), //ENTRADA
.Q(MS_1_reg) //SALIDA
);
Convert_Float_To_Fixed_V CONVERT_FLOAT_FIXED_V(
.CLK(CLK),
.FLOAT(F),
.EN_REG1(EN_REG1),
.LOAD(LOAD),
.MS_1(MS_1_reg),
.Exp_out(Exp_out),
.FIXED(RESULT),
.Exp(Exp),
.EN_REG2(EN_REG2),
.RST(RST)
);
endmodule |
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for wb_ram
*/
module test_wb_ram;
// Parameters
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 16;
parameter SELECT_WIDTH = 4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] adr_i = 0;
reg [DATA_WIDTH-1:0] dat_i = 0;
reg we_i = 0;
reg [SELECT_WIDTH-1:0] sel_i = 0;
reg stb_i = 0;
reg cyc_i = 0;
// Outputs
wire [DATA_WIDTH-1:0] dat_o;
wire ack_o;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
adr_i,
dat_i,
we_i,
sel_i,
stb_i,
cyc_i);
$to_myhdl(dat_o,
ack_o);
// dump file
$dumpfile("test_wb_ram.lxt");
$dumpvars(0, test_wb_ram);
end
wb_ram #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.SELECT_WIDTH(SELECT_WIDTH)
)
UUT (
.clk(clk),
.adr_i(adr_i),
.dat_i(dat_i),
.dat_o(dat_o),
.we_i(we_i),
.sel_i(sel_i),
.stb_i(stb_i),
.ack_o(ack_o),
.cyc_i(cyc_i)
);
endmodule
|
// =============================================================================
// COPYRIGHT NOTICE
// Copyright 2000-2001 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court (other locations)
// Hillsboro, OR 97124 web : http://www.latticesemi.com/
// U.S.A email:
// =============================================================================
// FILE DETAILS
// Project : pci_exp
// File : testcase.v
// Title : Loob Back Test using SERDES/PCSC
// Dependencies :
// Description : The following test checks if the interface between core and SERDES/PCS
// are OK. As connection is looped back on serial lines, the LTSSM
// will not move from congig state. This ensures TS orderset flow
// and then switching to "no_training" will make LTSSM to go to LO
// directly. Then TLP trafic is tested.
// =============================================================================
// REVISION HISTORY
// Version : 1.0
// Mod. Date : Sep 22, 2004
// Changes Made : Initial Creation
//
// Version : 2.0
// Mod. Date : May 2, 2006
// Changes Made : Modified for ECP3 PCIe x1
// =============================================================================
parameter TCNT = 'd25 ;
reg test_complete;
reg [9:0] stlp_size;
reg [9:0] stlp_size_r;
reg [9:0] rtlp_size;
reg [9:0] rtlp_size_r;
reg [31:0] seed;
reg [31:0] rand[0:1023];
reg [31:0] tlps_count;
reg test_flag1;
integer sp ;
integer rp ;
integer tp ;
integer xp ;
initial begin
// Test Started
$display("---INFO : Test test_ecp3 STARTED at Time %0t", $time);
RST_DUT;
//----------- for RTL sim ----------------
$display("---INFO TESTCASE : Forcing Detect Result at Time %0t", $time);
force u1_top.u1_pcs_pipe.ffs_pcie_con_0 = 1'b1; // Receiver detected
repeat (25) @ (posedge sys_clk_125);
$display("---INFO TESTCASE : Waiting for rxp_valid at Time %0t", $time);
wait (u1_top.u1_pcs_pipe.RxValid_0); //wait for lane sync
release u1_top.u1_pcs_pipe.ffs_pcie_con_0 ; //Receiver detected
$display("---INFO TESTCASE : Waiting for SM to go to CFG at Time %0t", $time);
wait ( u1_top.u1_dut.phy_ltssm_state == 4'd2); // wait for DUT Config state
repeat (200) @ (posedge sys_clk_125);
//--------------------------------------
$display("---INFO TESTCASE : Forcing LTSSM to L0 at Time %0t", $time);
`ifdef WISHBONE
wb_write (13'h100C, 32'h0000_0001) ; // Set no_pcie_train
`else
force no_pcie_train = 1'b1;
`endif
repeat (10) @ (posedge sys_clk_125);
wait (dl_up);
$display("---INFO TESTCASE : FCI is done, dl_up asserted at Time %0t", $time);
fork
test_complete = 1'b0 ;
begin
seed = 'd9;
// Send Packet from TX user Interface
for (sp = 0 ; sp < TCNT; sp = sp+1) begin
repeat (1) @ (posedge tb_sys_clk);
stlp_size_r = {$random(seed)} % 31;
stlp_size = (stlp_size_r <= 2) ? 3 : stlp_size_r;
rand[sp] = stlp_size ;
tbtx_mem_wr(3'd0, 32'hFFFF_FF80, stlp_size, 1'b0, 10'd0, 1'b0);
$display("---INFO : TLP No. %0d scheduled from TBTX at Time %0t", sp, $time);
end
end
begin
// Check Packet from RX user Interface
for (rp = 0 ; rp < TCNT; rp = rp+1) begin
repeat (1) @ (posedge tb_sys_clk);
rtlp_size = rand[rp];
tbrx_mem_wr(3'd0, 32'hFFFF_FF80, rtlp_size, 1'b0, 4'd0);
end
end
begin
tlps_count = 'd0;
for (tp = 0 ; tp < TCNT; tp = tp+1) begin
wait (rx_end) ;
$display("---INFO : TLP No. %0d received at TBRX at Time %0t", tp, $time);
tlps_count = tlps_count + 1;
repeat (2) @ (posedge tb_sys_clk);
end
end
// Wait until packet is received by RX TB
begin
wait (|tbrx_cmd_prsnt == 1'b1) ;
wait (|tbrx_cmd_prsnt == 1'b0) ;
test_complete = 1'b1 ;
end
join
end
always @(posedge tb_sys_clk) begin
if (tlps_count%30 == 0) begin
u_tbrx[0].ph_buf_status <= 1'b1;
u_tbrx[0].pd_buf_status <= 1'b1;
u_tbrx[0].nph_buf_status <= 1'b1;
u_tbrx[0].npd_buf_status <= 1'b1;
end
else if (tlps_count%30 == 2) begin
u_tbrx[0].ph_buf_status <= 1'b0;
u_tbrx[0].pd_buf_status <= 1'b0;
u_tbrx[0].nph_buf_status <= 1'b0;
u_tbrx[0].npd_buf_status <= 1'b0;
end
end
always @(posedge tb_sys_clk) begin
if (rx_st) begin
u_tbrx[0].ph_processed <= 1'b1;
u_tbrx[0].pd_processed <= 1'b1;
u_tbrx[0].nph_processed <= 1'b1;
u_tbrx[0].npd_processed <= 1'b1;
end
else if (rx_end) begin
u_tbrx[0].ph_processed <= 1'b0;
u_tbrx[0].pd_processed <= 1'b0;
u_tbrx[0].nph_processed <= 1'b0;
u_tbrx[0].npd_processed <= 1'b0;
end
end
always @(error or test_complete)
begin
// Test Completed
if ((error == 1'b0) && (test_complete == 1'b1) && (tlps_count == TCNT)) begin
repeat (10) @ (posedge tb_sys_clk);
$display("---INFO : Test test_ecp3 PASSED at Time %t", $time);
$finish;
end
if (error == 1'b1) begin
repeat (10) @ (posedge tb_sys_clk);
$display("---ERROR : Test test_ecp3 FAILED at Time %t", $time);
$finish;
end
end
// =============================================================================
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FAHCIN_FUNCTIONAL_V
`define SKY130_FD_SC_LP__FAHCIN_FUNCTIONAL_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__fahcin (
COUT,
SUM ,
A ,
B ,
CIN
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Local signals
wire ci ;
wire xor0_out_SUM;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT;
// Name Output Other arguments
not not0 (ci , CIN );
xor xor0 (xor0_out_SUM, A, B, ci );
buf buf0 (SUM , xor0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, ci );
and and2 (b_ci , B, ci );
or or0 (or0_out_COUT, a_b, a_ci, b_ci);
buf buf1 (COUT , or0_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__FAHCIN_FUNCTIONAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__EINVN_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__EINVN_FUNCTIONAL_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__einvn (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Name Output Other arguments
notif0 notif00 (Z , A, TE_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__EINVN_FUNCTIONAL_V |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon May 29 20:15:21 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_buffer_register_0_0 -prefix
// system_buffer_register_0_0_ system_buffer_register_0_0_stub.v
// Design : system_buffer_register_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "buffer_register,Vivado 2016.4" *)
module system_buffer_register_0_0(clk, val_in, val_out)
/* synthesis syn_black_box black_box_pad_pin="clk,val_in[31:0],val_out[31:0]" */;
input clk;
input [31:0]val_in;
output [31:0]val_out;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFRBP_1_V
`define SKY130_FD_SC_HD__SDFRBP_1_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for sdfrbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__sdfrbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sdfrbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__sdfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sdfrbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__sdfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFRBP_1_V
|
// DESCRIPTION: Verilator: Verilog Test module
// simplistic example, should choose 1st conditional generate and assign straight through
// the tool also compiles the special case and determines an error (replication value is 0)
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty.
// SPDX-License-Identifier: CC0-1.0
`timescale 1ns / 1ps
module t(data_i, data_o, single);
parameter op_bits = 32;
input [op_bits -1:0] data_i;
output [31:0] data_o;
input single;
//simplistic example, should choose 1st conditional generate and assign straight through
//the tool also compiles the special case and determines an error (replication value is 0
generate
if (op_bits == 32) begin : general_case
assign data_o = data_i;
// Test implicit signals
/* verilator lint_off IMPLICIT */
assign imp = single;
/* verilator lint_on IMPLICIT */
end
else begin : special_case
assign data_o = {{(32 -op_bits){1'b0}},data_i};
/* verilator lint_off IMPLICIT */
assign imp = single;
/* verilator lint_on IMPLICIT */
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long inf = 0x3f3f3f3f3f3f3f3f; int n, m, a[100010]; int tot[100010], Lpos = 1, Rpos = 0; long long f[100010], g[100010], MO; inline int read() { int x = 0, w = 0; char ch = 0; while (!isdigit(ch)) { w |= ch == - ; ch = getchar(); } while (isdigit(ch)) { x = (x << 1) + (x << 3) + (ch ^ 48); ch = getchar(); } return w ? -x : x; } void add(int x) { MO += (tot[x]++); } void del(int x) { MO -= (--tot[x]); } long long calc(int l, int r) { while (Lpos < l) del(a[Lpos++]); while (Lpos > l) add(a[--Lpos]); while (Rpos < r) add(a[++Rpos]); while (Rpos > r) del(a[Rpos--]); return MO; } void solve(int L, int R, int st, int ed) { if (st > ed || L > R) return; int M = (st + ed) >> 1; M = max(M, L + 1); long long temp = inf, pos = 0; for (int i = L; i <= R; i++) if (temp > g[i] + calc(i + 1, M)) temp = g[pos = i] + calc(i + 1, M); f[M] = temp; solve(L, pos, st, M - 1); solve(pos, R, M + 1, ed); } int main() { n = read(); m = read(); for (int i = 1; i <= n; i++) a[i] = read(); memset(g, 0x3f, sizeof g); g[0] = 0; while (m-- > 0) { solve(0, n - 1, 1, n); swap(f, g); } cout << g[n] << n ; } |
module qa_contents
#(
parameter WIDTH = 32,
parameter MWIDTH = 1
)
(
input wire clk,
input wire rst_n,
input wire [WIDTH-1:0] in_data,
input wire in_nd,
input wire [MWIDTH-1:0] in_m,
// Takes input messages to set taps.
input wire [`MSG_WIDTH-1:0] in_msg,
input wire in_msg_nd,
output wire [WIDTH-1:0] out_data,
output wire out_nd,
output wire [MWIDTH-1:0] out_m,
output wire [`MSG_WIDTH-1:0] out_msg,
output wire out_msg_nd,
output wire error
);
filterbank
#(`N_FILTERS, WIDTH, 1, `FILTER_LENGTH, `FILTERBANK_ID,
`FILTERBANK_MSG_BUFFER_LENGTH)
filterbank_0
(
.clk(clk),
.rst_n(rst_n),
.in_data(in_data),
.in_nd(in_nd),
.in_m(in_m),
.in_msg(in_msg),
.in_msg_nd(in_msg_nd),
.out_data(out_data),
.out_nd(out_nd),
.out_m(out_m),
.out_msg(out_msg),
.out_msg_nd(out_msg_nd),
.error(error)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long MOD = 1e9 + 7; bool a[100100]; void go() { long long int n; cin >> n; memset(a, true, sizeof(a)); for (int i = 2; i <= n; i++) { for (int j = i + 1; i * j <= n; j++) { if (j % i == 0) continue; a[j * i] = false; } } vector<int> ans; for (int i = 2; i <= n; i++) { if (a[i]) ans.push_back(i); } cout << ans.size() << endl; for (int i = 0; i < ans.size(); i++) cout << ans[i] << ; cout << endl; } int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); long long int t = 1; while (t--) go(); } |
#include <bits/stdc++.h> int main() { int n, m; scanf( %d %d , &n, &m); int msg1[n]; int msg2[m]; for (int i = 0; i < n; i++) { scanf( %d , &msg1[i]); } for (int i = 0; i < m; i++) { scanf( %d , &msg2[i]); } for (int i = 1; i < n; i++) { msg1[i] = msg1[i] + msg1[i - 1]; } for (int i = 1; i < m; i++) { msg2[i] = msg2[i] + msg2[i - 1]; } int count = 0; int i = 0, j = 0; while (i < n && j < m) { if (msg1[i] < msg2[j]) i++; else if (msg1[i] > msg2[j]) j++; else { i++; j++; count++; } } printf( %d , count); } |
#include <bits/stdc++.h> using namespace ::std; const long double PI = acos(-1); const long long MOD = 1000000000 + 7; long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } int add(int a, int b, int m = MOD) { return (a + b + m + m) % m; } int mul(long long a, long long b, int m = MOD) { return (a * b) % m; } long long pow_mod(long long a, long long b, long long m = MOD) { long long res = 1LL; a = a % m; while (b) { if (b & 1) res = mul(res, a, m); b >>= 1; a = mul(a, a, m); } return res; } long long fastexp(long long a, long long b) { long long res = 1LL; while (b) { if (b & 1) res = res * a; b >>= 1; a *= a; } return res; } int gcdExtendido(int a, int b, int *x, int *y) { if (a == 0) { *x = 0; *y = 1; return b; } int x1, y1; int gcd = gcdExtendido(b % a, a, &x1, &y1); *x = y1 - (b / a) * x1; *y = x1; return gcd; } int modInverso(int a, int m) { int x, y; int g = gcdExtendido(a, m, &x, &y); if (g != 1) return -1; else return (x % m + m) % m; } const int N = 200000 + 5; const int L = 2; const unsigned int B[] = {257, 311}; int n; string minimal(string s) { if (s.size() & 1) return s; string s1 = minimal(s.substr(0, s.size() / 2)); string s2 = minimal(s.substr(s.size() / 2, s.size() / 2)); if (s1 < s2) return s1 + s2; return s2 + s1; } int main() { string a, b; cin >> a >> b; if (minimal(a) == minimal(b)) puts( YES ); else puts( NO ); return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename Arg1> void __f(const char* name, Arg1&& arg1) { cerr << name << : << arg1 << std::endl; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cerr.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } bool ok(int x) { if (x < 0) return false; for (int i = 0; i * i <= x; i++) if (i * i == x) return true; return false; } int main() { int n; scanf( %d , &n); int mx = -10000000; for (int i = (0); i < (n); ++i) { int x; scanf( %d , &x); if (ok(x)) continue; mx = max(mx, x); } printf( %d n , mx); return 0; } |
#include <bits/stdc++.h> using namespace std; long long int n, h[100001], root[100001], par[100001][25], size[100001], dp_down_0[100001], dp_down_1[100001], dp_up_0[100001], dp_up_1[100001]; vector<pair<long long int, long long int> > v[100001]; long long int add(long long int x, long long int y) { return (x + y) % 1000000007; } long long int mul(long long int x, long long int y) { return (1LL * x * y) % 1000000007; } long long int sub(long long int x, long long int y) { return (x - y + 1000000007) % 1000000007; } long long int sq(long long int x) { return (1LL * x * x) % 1000000007; } void dfs_down(long long int cur, long long int p) { if (p != -1) h[cur] = h[p] + 1; par[cur][0] = p; for (long long int i = 1; i < 20; i++) { if (par[cur][i - 1] != -1) par[cur][i] = par[par[cur][i - 1]][i - 1]; } size[cur] = 1; for (long long int i = 0; i < v[cur].size(); i++) { long long int x = v[cur][i].first; if (x == p) continue; root[x] = add(root[cur], v[cur][i].second); dfs_down(x, cur); size[cur] += size[x]; dp_down_0[cur] = add(dp_down_0[cur], dp_down_0[x]); dp_down_0[cur] = add(dp_down_0[cur], mul(size[x], v[cur][i].second)); dp_down_1[cur] = add(dp_down_1[cur], mul(size[x], sq(v[cur][i].second))); dp_down_1[cur] = add(dp_down_1[cur], dp_down_1[x]); dp_down_1[cur] = add(dp_down_1[cur], mul(2, mul(v[cur][i].second, dp_down_0[x]))); } } void dfs_up(long long int cur, long long int p, long long int wt) { if (p != -1) { dp_up_0[cur] = add(dp_up_0[cur], dp_up_0[p]); dp_up_0[cur] = add(dp_up_0[cur], mul(n - size[p], wt)); long long int x = dp_down_0[p]; x = sub(x, dp_down_0[cur]); x = sub(x, mul(size[cur], wt)); dp_up_0[cur] = add(dp_up_0[cur], x); dp_up_0[cur] = add(dp_up_0[cur], mul(wt, size[p] - size[cur])); dp_up_1[cur] = add(dp_up_1[cur], dp_up_1[p]); dp_up_1[cur] = add(dp_up_1[cur], mul(n - size[p], sq(wt))); dp_up_1[cur] = add(dp_up_1[cur], mul(2, mul(wt, dp_up_0[p]))); x = dp_down_1[p]; x = sub(x, dp_down_1[cur]); x = sub(x, mul(2, mul(wt, dp_down_0[cur]))); x = sub(x, mul(size[cur], sq(wt))); long long int y = dp_down_0[p]; y = sub(y, dp_down_0[cur]); y = sub(y, mul(wt, size[cur])); dp_up_1[cur] = add(dp_up_1[cur], x); dp_up_1[cur] = add(dp_up_1[cur], mul(2, mul(wt, y))); dp_up_1[cur] = add(dp_up_1[cur], mul(sq(wt), size[p] - size[cur])); } for (long long int i = 0; i < v[cur].size(); i++) { long long int x = v[cur][i].first; if (x == p) continue; dfs_up(x, cur, v[cur][i].second); } } int lca(int v, int u) { if (h[v] < h[u]) swap(v, u); for (int i = 20 - 1; i >= 0; i--) { if (par[v][i] != -1 && h[par[v][i]] >= h[u]) { v = par[v][i]; } } if (v == u) return u; for (int i = 20 - 1; i >= 0; i--) { if (par[v][i] - par[u][i]) v = par[v][i], u = par[u][i]; } return par[v][0]; } long long int distance(long long int x, long long int y) { long long int ans = root[x]; ans = add(ans, root[y]); ans = sub(ans, mul(2, root[lca(x, y)])); return ans; } int main() { ios::sync_with_stdio(false); ; cin.tie(0); ; long long int i, j, q, x, y, ans, temp, z, lc, dist; memset(par, -1, sizeof par); cin >> n; for (i = 1; i <= n - 1; i++) { cin >> x >> y >> z; v[x].push_back(make_pair(y, z)); v[y].push_back(make_pair(x, z)); } dfs_down(1, -1); dfs_up(1, -1, 0); cin >> q; while (q--) { cin >> x >> y; dist = distance(x, y); lc = lca(x, y); if ((lc != x && lc != y) || lc == x) { ans = dp_down_1[y]; ans = add(ans, mul(sq(dist), size[y])); ans = add(ans, mul(2, mul(dist, dp_down_0[y]))); ans = mul(2, ans); ans = sub(ans, dp_down_1[x]); ans = sub(ans, dp_up_1[x]); cout << ans << n ; } else if (lc == y) { ans = dp_down_1[x]; temp = dp_up_1[x]; temp = sub(temp, dp_up_1[y]); temp = sub(temp, mul(2, mul(dist, dp_up_0[y]))); temp = sub(temp, mul(n - size[y], sq(dist))); ans = add(ans, temp); ans = mul(2, ans); ans = sub(ans, dp_down_1[x]); ans = sub(ans, dp_up_1[x]); cout << ans << n ; } else assert(false); } return 0; } |
// MM_slave.v
// This file was auto-generated as a prototype implementation of a module
// created in component editor. It ties off all outputs to ground and
// ignores all inputs. It needs to be edited to make it do something
// useful.
//
// This file will not be automatically regenerated. You should check it in
// to your version control system if you want to keep it.
`timescale 1 ps / 1 ps
module MM_slave (
input wire [7:0] avs_s0_address, // avs_s0.address
input wire avs_s0_read, // .read
output wire [31:0] avs_s0_readdata, // .readdata
input wire avs_s0_write, // .write
input wire [31:0] avs_s0_writedata, // .writedata
output wire avs_s0_waitrequest, // .waitrequest
input wire clock_clk, // clock.clk
input wire reset_reset, // reset.reset
output wire LED_OUT // LED_output.led_out
);
// TODO: Auto-generated HDL template
assign avs_s0_readdata = 32'b00000000000000000000000000000000;
// assign avs_s0_waitrequest = 1'b0;
// assign LED_OUT = 1'b0;
reg Reg_Status_Read;
reg Reg_Status_Write;
reg [31:0] data_in;
reg [31:0] data_out;
reg led_out;
//
//
//
assign avs_s0_waitrequest = Reg_Status_Read || Reg_Status_Write;
assign LED_OUT = led_out;
//
// WRITE LOGIC
//
always @(posedge clock_clk)
if (reset_reset) begin
data_in <= 32'b0;
data_out <= 32'b0;
Reg_Status_Write <= 1'b0;
end else if (!avs_s0_waitrequest && avs_s0_write) begin
Reg_Status_Write <= 1'b0;
led_out <= avs_s0_writedata[0];
data_in <= avs_s0_writedata;
end else begin
Reg_Status_Write <= 1'b0;
end
//
// READ LOGIC
//
always @(posedge clock_clk)
if (reset_reset) begin
Reg_Status_Read <= 1'b0;
end else if (!avs_s0_waitrequest && avs_s0_read) begin
Reg_Status_Read <= 1'b0;
end else begin
Reg_Status_Read <= 1'b0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; char getOtherValue(char val) { if (val == . ) return 0 ; if (val == 1 ) return 0 ; return 1 ; } int main() { int n, p; cin >> n >> p; string str; cin >> str; bool ok = false; for (int i = 0; i < n - p; ++i) { if (str[i] == . || str[i] != str[i + p]) { ok = true; if (str[i] == . ) { str[i] = getOtherValue(str[i + p]); } if (str[i + p] == . ) { str[i + p] = getOtherValue(str[i]); } break; } } if (ok) { for (int i = 0; i < n; ++i) { if (str[i] == . ) { str[i] = 0 ; } } cout << str; return 0; } cout << NO ; return 0; } |
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Read Data Response AXI3 Slave Converter
// Forwards and re-assembles split transactions.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// r_axi3_conv
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_r_axi3_conv #
(
parameter C_FAMILY = "none",
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_SUPPORT_SPLITTING = 1,
// Implement transaction splitting logic.
// Disabled whan all connected masters are AXI3 and have same or narrower data width.
parameter integer C_SUPPORT_BURSTS = 1
// Disabled when all connected masters are AxiLite,
// allowing logic to be simplified.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Command Interface
input wire cmd_valid,
input wire cmd_split,
output wire cmd_ready,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Throttling help signals.
wire cmd_ready_i;
wire pop_si_data;
wire si_stalling;
// Internal MI-side control signals.
wire M_AXI_RREADY_I;
// Internal signals for SI-side.
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID_I;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA_I;
wire [2-1:0] S_AXI_RRESP_I;
wire S_AXI_RLAST_I;
wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER_I;
wire S_AXI_RVALID_I;
wire S_AXI_RREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Handle interface handshaking:
//
// Forward data from MI-Side to SI-Side while a command is available. When
// the transaction has completed the command is popped from the Command FIFO.
//
//
/////////////////////////////////////////////////////////////////////////////
// Pop word from SI-side.
assign M_AXI_RREADY_I = ~si_stalling & cmd_valid;
assign M_AXI_RREADY = M_AXI_RREADY_I;
// Indicate when there is data available @ SI-side.
assign S_AXI_RVALID_I = M_AXI_RVALID & cmd_valid;
// Get SI-side data.
assign pop_si_data = S_AXI_RVALID_I & S_AXI_RREADY_I;
// Signal that the command is done (so that it can be poped from command queue).
assign cmd_ready_i = cmd_valid & pop_si_data & M_AXI_RLAST;
assign cmd_ready = cmd_ready_i;
// Detect when MI-side is stalling.
assign si_stalling = S_AXI_RVALID_I & ~S_AXI_RREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Simple AXI signal forwarding:
//
// USER, ID, DATA and RRESP passes through untouched.
//
// LAST has to be filtered to remove any intermediate LAST (due to split
// trasactions). LAST is only removed for the first parts of a split
// transaction. When splitting is unsupported is the LAST filtering completely
// completely removed.
//
/////////////////////////////////////////////////////////////////////////////
// Calculate last, i.e. mask from split transactions.
assign S_AXI_RLAST_I = M_AXI_RLAST &
( ~cmd_split | ( C_SUPPORT_SPLITTING == 0 ) );
// Data is passed through.
assign S_AXI_RID_I = M_AXI_RID;
assign S_AXI_RUSER_I = M_AXI_RUSER;
assign S_AXI_RDATA_I = M_AXI_RDATA;
assign S_AXI_RRESP_I = M_AXI_RRESP;
/////////////////////////////////////////////////////////////////////////////
// SI-side output handling
//
/////////////////////////////////////////////////////////////////////////////
// TODO: registered?
assign S_AXI_RREADY_I = S_AXI_RREADY;
assign S_AXI_RVALID = S_AXI_RVALID_I;
assign S_AXI_RID = S_AXI_RID_I;
assign S_AXI_RDATA = S_AXI_RDATA_I;
assign S_AXI_RRESP = S_AXI_RRESP_I;
assign S_AXI_RLAST = S_AXI_RLAST_I;
assign S_AXI_RUSER = S_AXI_RUSER_I;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 200005; const int INFTY = 1 << 30; int D, N, M; pair<int, int> pos[MAXN]; vector<int> S; int nxt[MAXN]; int main() { scanf( %d %d %d , &D, &N, &M); for (int i = 0; i < M; i++) scanf( %d %d , &pos[i].first, &pos[i].second); sort(pos, pos + M); pos[M] = make_pair(D, 0); for (int i = M - 1; i >= 0; i--) { while (!S.empty() && pos[S.back()].second > pos[i].second) S.pop_back(); nxt[i] = S.empty() ? M : S.back(); S.push_back(i); } long long ans = 0; int cur = N - pos[0].first; for (int i = 0; i < M; i++) { if (cur < 0) { printf( -1 n ); return 0; } int need = min(N, pos[nxt[i]].first - pos[i].first); int add = max(0, need - cur); ans += (long long)pos[i].second * add; cur += add - (pos[i + 1].first - pos[i].first); } if (cur < 0) printf( -1 n ); else printf( %I64d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; string s; cin >> s; vector<int> A(91, 0); for (int i = 0; s[i]; i++) { A[(int)s[i]]++; } for (int i = 65; i < 65 + k; i++) if (A[i] == 0) { cout << 0 ; return 0; } cout << k * (*min_element(A.begin() + 65, A.begin() + 65 + k)); return 0; } |
// Alt+C for commenting
// Alt+Shift+C for uncommenting
//==============================================================================
// Copyright (C) John-Philip Taylor
//
//
// This file is part of a library
//
// This file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>
//==============================================================================
module UART_Receiver #(
parameter N = 5,
parameter Full = 5'd29 // Clk / BAUD - 1
)(
input Clk,
input Reset,
output reg [7:0]Data,
output reg Ready, // 'low' means busy, and 'high' mean free.
input Ack,
// input softReset,
input Rx
);
//------------------------------------------------------------------------------
reg tRx;
reg tAck;
reg [ 7:0]Temp;
reg [N-1:0]Count;
reg [ 2:0]BitCount;
reg NewData;
//------------------------------------------------------------------------------
reg [1:0]State;
localparam Idle = 2'b00;
localparam StartBit = 2'b01;
localparam Receiving = 2'b11;
localparam Done = 2'b10;
//------------------------------------------------------------------------------
reg tReset;
//reg tSoftReset;
always @(posedge Clk) begin
// clock domain crossing.
tRx <= Rx;
tAck <= Ack;
tReset <= Reset;
// tSoftReset <= softReset;
if(tReset | tAck) begin
// if Reset the reinitialise everything.
Data <= 0;
Ready <= 0;
NewData <= 0;
Count <= 0;
State <= Idle;
//------------------------------------------------------------------------------
end else begin
if(Ready & tAck) Ready <= 1'b0; // set to 'low' to indicate not yet received data.
case(State)
Idle: begin
// if Rx line if idle.
if(~tRx) begin
Count <= {1'b0, Full[N-1:1]};
State <= StartBit; // successfully received startbit.
end
// if successfully received 8-bits of data.
if(NewData & ~tAck && ~Ready) begin
Data <= Temp;
Ready <= 1'b1; // set to 'high' to indicate new data received.
NewData <= 1'b0;
Count <= 1'b0;
end
end
//------------------------------------------------------------------------------
Done: begin
if(tRx) State <= Idle;
end
default:;
endcase
//------------------------------------------------------------------------------
if(~|Count) begin
case(State)
StartBit: begin
if(Rx) begin
State <= Idle;
end else begin
BitCount <= 0;
Count <= Full;
State <= Receiving;
end
end
//------------------------------------------------------------------------------
Receiving: begin
Temp <= {tRx, Temp[7:1]};
Count <= Full;
if(&BitCount) begin
NewData <= 1'b1;
State <= Done;
end
BitCount <= BitCount + 1'b1;
end
//------------------------------------------------------------------------------
default:;
endcase
end else begin
Count <= Count - 1'b1;
end
end
end
//------------------------------------------------------------------------------
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: i2c_buf.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: i2c_buf (io-to-cpu UCB buffer)
// Description: This is the interface from the UCB modules.
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Interface signal list declarations
////////////////////////////////////////////////////////////////////////
module i2c_buf (/*AUTOARG*/
// Outputs
iob_ucb_stall, req_ack_obj, req_ack_vld, int_obj, int_vld,
// Inputs
rst_l, clk, ucb_iob_vld, ucb_iob_data, rd_req_ack_dbl_buf,
rd_int_dbl_buf
);
// synopsys template
parameter UCB_IOB_WIDTH = 8;
parameter REG_WIDTH = 64; // size of control register in cluster
parameter REQ_ACK_BUF_WIDTH = 128; // control (64 bit) + data (64/128 bit)
parameter INT_BUF_WIDTH = 64; // interrupt packet width
////////////////////////////////////////////////////////////////////////
// Signal declarations
////////////////////////////////////////////////////////////////////////
// Global interface
input rst_l;
input clk;
// UCB interface
input ucb_iob_vld;
input [UCB_IOB_WIDTH-1:0] ucb_iob_data;
output iob_ucb_stall;
// i2c slow control/datapath interface
input rd_req_ack_dbl_buf;
output [REQ_ACK_BUF_WIDTH-1:0] req_ack_obj;
output req_ack_vld;
input rd_int_dbl_buf;
output [INT_BUF_WIDTH-1:0] int_obj;
output int_vld;
// Internal signals
wire indata_buf_vld;
wire [REG_WIDTH+63:0] indata_buf;
wire iob_ucb_stall_a1;
wire int_type;
wire req_ack_pending;
wire int_pending;
wire wr_req_ack_dbl_buf;
wire req_ack_dbl_buf_full;
wire wr_int_dbl_buf;
wire int_dbl_buf_full;
////////////////////////////////////////////////////////////////////////
// Code starts here
////////////////////////////////////////////////////////////////////////
/************************************************************
* Assemble inbound packet
************************************************************/
ucb_bus_in #(UCB_IOB_WIDTH, REG_WIDTH) ucb_bus_in (.rst_l(rst_l),
.clk(clk),
.vld(ucb_iob_vld),
.data(ucb_iob_data),
.stall(iob_ucb_stall),
.indata_buf_vld(indata_buf_vld),
.indata_buf(indata_buf),
.stall_a1(iob_ucb_stall_a1));
/************************************************************
* Decode inbound packet type
************************************************************/
// non-interrupt packet
assign req_ack_pending = ~int_type & indata_buf_vld;
// interrupt packet
assign int_type = ((indata_buf[`UCB_PKT_HI:`UCB_PKT_LO] == `UCB_INT) |
(indata_buf[`UCB_PKT_HI:`UCB_PKT_LO] == `UCB_INT_VEC) |
(indata_buf[`UCB_PKT_HI:`UCB_PKT_LO] == `UCB_RESET_VEC) |
(indata_buf[`UCB_PKT_HI:`UCB_PKT_LO] == `UCB_IDLE_VEC) |
(indata_buf[`UCB_PKT_HI:`UCB_PKT_LO] == `UCB_RESUME_VEC));
assign int_pending = int_type & indata_buf_vld;
assign iob_ucb_stall_a1 = (req_ack_pending & req_ack_dbl_buf_full) |
(int_pending & int_dbl_buf_full);
/************************************************************
* Double buffer to store non-interrupt packets
************************************************************/
assign wr_req_ack_dbl_buf = req_ack_pending & ~req_ack_dbl_buf_full;
dbl_buf #(REQ_ACK_BUF_WIDTH) req_ack_dbl_buf (.rst_l(rst_l),
.clk(clk),
.wr(wr_req_ack_dbl_buf),
.din(indata_buf[REQ_ACK_BUF_WIDTH-1:0]),
.rd(rd_req_ack_dbl_buf),
.dout(req_ack_obj),
.vld(req_ack_vld),
.full(req_ack_dbl_buf_full));
/************************************************************
* Double buffer to store interrupt packets
************************************************************/
assign wr_int_dbl_buf = int_pending & ~int_dbl_buf_full;
dbl_buf #(INT_BUF_WIDTH) int_dbl_buf (.rst_l(rst_l),
.clk(clk),
.wr(wr_int_dbl_buf),
.din(indata_buf[INT_BUF_WIDTH-1:0]),
.rd(rd_int_dbl_buf),
.dout(int_obj),
.vld(int_vld),
.full(int_dbl_buf_full));
endmodule // i2c_buf
|
#include <bits/stdc++.h> using namespace std; long long Pow[10005]; long long ans[10005]; int main() { long long N, X, now = 1, i, con = 0, t; Pow[0] = 1; for (i = 1; i <= 40; i++) Pow[i] = Pow[i - 1] * 2; scanf( %lld %lld , &X, &N); for (i = 40; i >= 0; i--) { while (X && X - (Pow[i] - 1) >= 0) { t = i; while (t--) ans[con++] = now; X -= (Pow[i] - 1); now += N; now++; } } printf( %lld n , con); for (i = 0; i < con; i++) printf( %lld , ans[i]); return 0; } |
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: mast_new.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module mast_new (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../sprites-new/masters_new.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../sprites-new/masters_new.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../sprites-new/masters_new.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL mast_new.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mast_new.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mast_new.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mast_new.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mast_new_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mast_new_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// megafunction wizard: %LPM_CONSTANT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_constant
// ============================================================
// File Name: lpm_constant4.v
// Megafunction Name(s):
// lpm_constant
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 222 10/21/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module lpm_constant4 (
result);
output [0:0] result;
wire [0:0] sub_wire0;
wire [0:0] result = sub_wire0[0:0];
lpm_constant lpm_constant_component (
.result (sub_wire0));
defparam
lpm_constant_component.lpm_cvalue = 0,
lpm_constant_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=SWAP",
lpm_constant_component.lpm_type = "LPM_CONSTANT",
lpm_constant_component.lpm_width = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
// Retrieval info: PRIVATE: JTAG_ID STRING "SWAP"
// Retrieval info: PRIVATE: Radix NUMERIC "10"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: Value NUMERIC "0"
// Retrieval info: PRIVATE: nBit NUMERIC "1"
// Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=SWAP"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
// Retrieval info: USED_PORT: result 0 0 1 0 OUTPUT NODEFVAL result[0..0]
// Retrieval info: CONNECT: result 0 0 1 0 @result 0 0 1 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_a_e
//
// Generated
// by: wig
// on: Mon Mar 22 12:42:23 2004
// cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../io.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_a_e.v,v 1.1 2004/04/06 11:05:03 wig Exp $
// $Date: 2004/04/06 11:05:03 $
// $Log: inst_a_e.v,v $
// Revision 1.1 2004/04/06 11:05:03 wig
// Adding result/io
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
//
// Generator: mix_0.pl Revision: 1.26 ,
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_a_e
//
// No `defines in this module
module inst_a_e
//
// Generated module inst_a
//
(
p_mix_sig_in_01_gi,
p_mix_sig_in_03_gi,
p_mix_sig_io_05_gc,
p_mix_sig_io_06_gc,
p_mix_sig_out_02_go,
p_mix_sig_out_04_go
);
// Generated Module Inputs:
input p_mix_sig_in_01_gi;
input [7:0] p_mix_sig_in_03_gi;
// Generated Module In/Outputs:
inout [5:0] p_mix_sig_io_05_gc;
inout [6:0] p_mix_sig_io_06_gc;
// Generated Module Outputs:
output p_mix_sig_out_02_go;
output [7:0] p_mix_sig_out_04_go;
// Generated Wires:
wire p_mix_sig_in_01_gi;
wire [7:0] p_mix_sig_in_03_gi;
wire [5:0] p_mix_sig_io_05_gc;
wire [6:0] p_mix_sig_io_06_gc;
wire p_mix_sig_out_02_go;
wire [7:0] p_mix_sig_out_04_go;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire sig_in_01; // __W_PORT_SIGNAL_MAP_REQ
wire [7:0] sig_in_03; // __W_PORT_SIGNAL_MAP_REQ
wire [5:0] sig_io_05; // __W_PORT_SIGNAL_MAP_REQ
wire [6:0] sig_io_06; // __W_PORT_SIGNAL_MAP_REQ
wire sig_out_02; // __W_PORT_SIGNAL_MAP_REQ
wire [7:0] sig_out_04; // __W_PORT_SIGNAL_MAP_REQ
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
assign sig_in_01 = p_mix_sig_in_01_gi; // __I_I_BIT_PORT
assign sig_in_03 = p_mix_sig_in_03_gi; // __I_I_BUS_PORT
assign sig_io_05 = p_mix_sig_io_05_gc; // __I_I_BUS_PORT
assign sig_io_06 = p_mix_sig_io_06_gc; // __I_I_BUS_PORT
assign p_mix_sig_out_02_go = sig_out_02; // __I_O_BIT_PORT
assign p_mix_sig_out_04_go = sig_out_04; // __I_O_BUS_PORT
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for inst_aa
inst_aa_e inst_aa(
.sig_in_01_p(sig_in_01),
.sig_in_03_p(sig_in_03),
.sig_io_out_05_p(sig_io_05),
.sig_io_out_06_p(sig_io_06),
.sig_out_02_p(sig_out_02),
.sig_out_04_p(sig_out_04)
);
// End of Generated Instance Port Map for inst_aa
// Generated Instance Port Map for inst_ab
inst_ab_e inst_ab(
);
// End of Generated Instance Port Map for inst_ab
// Generated Instance Port Map for inst_ac
inst_ac_e inst_ac(
);
// End of Generated Instance Port Map for inst_ac
endmodule
//
// End of Generated Module rtl of inst_a_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; string s; int cnt; int getdeal(long long c) { int ret = 0; while (c) { ret += c % 10; c /= 10; } return ret; } int main() { ios::sync_with_stdio(false); long long n; cin >> n; long long temp = 0; while (temp * 10 + 9 <= n) { temp = temp * 10 + 9; } cout << getdeal(temp) + getdeal(n - temp); } |
/*
This file is part of Fusion-Core-ISA.
Fusion-Core-ISA is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
Fusion-Core-ISA is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with Fusion-Core-ISA. If not, see <http://www.gnu.org/licenses/>.
*/
module RegisterFile(
/*Data*/
input[31:0] in_reg, //only one input needed
output reg[31:0] out_a,
output reg[31:0] out_b,
/*Addresses*/
input[4:0] addr_a, //used for input addresses
input[4:0] addr_b,
/*Control Lines*/
input rw, //rw == 1, then read; rw == 0, write
input clk, //clock for synchronous registers
input sel //chip select line, active low
);
/*Registers*/
//reg[31:0] reg_out_a; //for keeping verilog happy
//reg[31:0] reg_out_b;
reg [31:0] r0;
reg [31:0] r1;
reg [31:0] r2;
reg [31:0] r3;
reg [31:0] r4;
reg [31:0] r5;
reg [31:0] r6;
reg [31:0] r7;
reg [31:0] r8;
reg [31:0] r9;
reg [31:0] r10;
reg [31:0] r11;
reg [31:0] r12;
reg [31:0] r13;
reg [31:0] r14;
reg [31:0] r15;
reg [31:0] r16;
reg [31:0] r17;
reg [31:0] r18;
reg [31:0] r19;
reg [31:0] r20;
reg [31:0] r21;
reg [31:0] r22;
reg [31:0] r23;
reg [31:0] r24;
reg [31:0] r25;
reg [31:0] r26;
reg [31:0] r27;
reg [31:0] r28;
reg [31:0] r29;
reg [31:0] r30;
reg [31:0] r31;
initial //initialize all registers to 0
begin
r0 <= 32'b0;
r1 <= 32'b0;
r2 <= 32'b0;
r3 <= 32'b0;
r4 <= 32'b0;
r5 <= 32'b0;
r6 <= 32'b0;
r7 <= 32'b0;
r8 <= 32'b0;
r9 <= 32'b0;
r10 <= 32'b0;
r11 <= 32'b0;
r12 <= 32'b0;
r13 <= 32'b0;
r14 <= 32'b0;
r15 <= 32'b0;
r16 <= 32'b0;
r17 <= 32'b0;
r18 <= 32'b0;
r19 <= 32'b0;
r20 <= 32'b0;
r21 <= 32'b0;
r22 <= 32'b0;
r23 <= 32'b0;
r24 <= 32'b0;
r25 <= 32'b0;
r26 <= 32'b0;
r27 <= 32'b0;
r28 <= 32'b0;
r29 <= 32'b0;
r30 <= 32'b0;
r31 <= 32'b0;
end
always @(posedge clk)
if(rw == 0 && sel == 0)
begin
out_a <= 0;
out_b <= 0;
case(addr_a)
5'b00000: r0 = in_reg;
5'b00001: r1 <= in_reg;
5'b00010: r2 <= in_reg;
5'b00011: r3 <= in_reg;
5'b00100: r4 <= in_reg;
5'b00101: r5 <= in_reg;
5'b00110: r6 <= in_reg;
5'b00111: r7 <= in_reg;
5'b01000: r8 <= in_reg;
5'b01001: r9 <= in_reg;
5'b01010: r10 <= in_reg;
5'b01011: r11 <= in_reg;
5'b01100: r12 <= in_reg;
5'b01101: r13 <= in_reg;
5'b01110: r14 <= in_reg;
5'b01111: r15 <= in_reg;
5'b10000: r16 <= in_reg;
5'b10001: r17 <= in_reg;
5'b10010: r18 <= in_reg;
5'b10011: r19 <= in_reg;
5'b10100: r20 <= in_reg;
5'b10101: r21 <= in_reg;
5'b10110: r22 <= in_reg;
5'b10111: r23 <= in_reg;
5'b11000: r24 <= in_reg;
5'b11001: r25 <= in_reg;
5'b11010: r26 <= in_reg;
5'b11011: r27 <= in_reg;
5'b11100: r28 <= in_reg;
5'b11101: r29 <= in_reg;
5'b11110: r30 <= in_reg;
5'b11111: r31 <= in_reg;
endcase
end
else if(rw == 1 && sel == 0)
begin
case(addr_a)
5'b00000: out_a <= r0;
5'b00001: out_a <= r1;
5'b00010: out_a <= r2;
5'b00011: out_a <= r3;
5'b00100: out_a <= r4;
5'b00101: out_a <= r5;
5'b00110: out_a <= r6;
5'b00111: out_a <= r7;
5'b01000: out_a <= r8;
5'b01001: out_a <= r9;
5'b01010: out_a <= r10;
5'b01011: out_a <= r11;
5'b01100: out_a <= r12;
5'b01101: out_a <= r13;
5'b01110: out_a <= r14;
5'b01111: out_a <= r15;
5'b10000: out_a <= r16;
5'b10001: out_a <= r17;
5'b10010: out_a <= r18;
5'b10011: out_a <= r19;
5'b10100: out_a <= r20;
5'b10101: out_a <= r21;
5'b10110: out_a <= r22;
5'b10111: out_a <= r23;
5'b11000: out_a <= r24;
5'b11001: out_a <= r25;
5'b11010: out_a <= r26;
5'b11011: out_a <= r27;
5'b11100: out_a <= r28;
5'b11101: out_a <= r29;
5'b11110: out_a <= r30;
5'b11111: out_a <= r31;
endcase
case(addr_b)
5'b00000: out_b <= r0;
5'b00001: out_b <= r1;
5'b00010: out_b <= r2;
5'b00011: out_b <= r3;
5'b00100: out_b <= r4;
5'b00101: out_b <= r5;
5'b00110: out_b <= r6;
5'b00111: out_b <= r7;
5'b01000: out_b <= r8;
5'b01001: out_b <= r9;
5'b01010: out_b <= r10;
5'b01011: out_b <= r11;
5'b01100: out_b <= r12;
5'b01101: out_b <= r13;
5'b01110: out_b <= r14;
5'b01111: out_b <= r15;
5'b10000: out_b <= r16;
5'b10001: out_b <= r17;
5'b10010: out_b <= r18;
5'b10011: out_b <= r19;
5'b10100: out_b <= r20;
5'b10101: out_b <= r21;
5'b10110: out_b <= r22;
5'b10111: out_b <= r23;
5'b11000: out_b <= r24;
5'b11001: out_b <= r25;
5'b11010: out_b <= r26;
5'b11011: out_b <= r27;
5'b11100: out_b <= r28;
5'b11101: out_b <= r29;
5'b11110: out_b <= r30;
5'b11111: out_b <= r31;
endcase
end
else
begin
out_a <= 32'bz;
out_b <= 32'bz;
end
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Verilog code that really should be replaced with a generate
* statement, but it does not work with some free simulators.
* So I put it in a module so as not to make other code unreadable,
* and keep compatibility with as many simulators as possible.
*/
module hpdmc_oddr4 #(
parameter DDR_CLK_EDGE = "SAME_EDGE",
parameter INIT = 1'b0,
parameter SRTYPE = "SYNC"
) (
output [3:0] Q,
input C,
input CE,
input [3:0] D1,
input [3:0] D2,
input R,
input S
);
ODDR #(
.DDR_CLK_EDGE(DDR_CLK_EDGE),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr0 (
.Q(Q[0]),
.C(C),
.CE(CE),
.D1(D1[0]),
.D2(D2[0]),
.R(R),
.S(S)
);
ODDR #(
.DDR_CLK_EDGE(DDR_CLK_EDGE),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr1 (
.Q(Q[1]),
.C(C),
.CE(CE),
.D1(D1[1]),
.D2(D2[1]),
.R(R),
.S(S)
);
ODDR #(
.DDR_CLK_EDGE(DDR_CLK_EDGE),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr2 (
.Q(Q[2]),
.C(C),
.CE(CE),
.D1(D1[2]),
.D2(D2[2]),
.R(R),
.S(S)
);
ODDR #(
.DDR_CLK_EDGE(DDR_CLK_EDGE),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr3 (
.Q(Q[3]),
.C(C),
.CE(CE),
.D1(D1[3]),
.D2(D2[3]),
.R(R),
.S(S)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND2B_2_V
`define SKY130_FD_SC_LP__AND2B_2_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog wrapper for and2b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and2b_2 (
X ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and2b base (
.X(X),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and2b_2 (
X ,
A_N,
B
);
output X ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and2b base (
.X(X),
.A_N(A_N),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND2B_2_V
|
// megafunction wizard: %LPM_MUX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_MUX
// ============================================================
// File Name: cntmux.v
// Megafunction Name(s):
// LPM_MUX
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.0.0 Build 595 04/25/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module cntmux (
data0x,
data1x,
sel,
result);
input [3:0] data0x;
input [3:0] data1x;
input sel;
output [3:0] result;
wire [3:0] sub_wire0;
wire [3:0] sub_wire3 = data1x[3:0];
wire [3:0] result = sub_wire0[3:0];
wire [3:0] sub_wire1 = data0x[3:0];
wire [7:0] sub_wire2 = {sub_wire3, sub_wire1};
wire sub_wire4 = sel;
wire sub_wire5 = sub_wire4;
lpm_mux LPM_MUX_component (
.data (sub_wire2),
.sel (sub_wire5),
.result (sub_wire0)
// synopsys translate_off
,
.aclr (),
.clken (),
.clock ()
// synopsys translate_on
);
defparam
LPM_MUX_component.lpm_size = 2,
LPM_MUX_component.lpm_type = "LPM_MUX",
LPM_MUX_component.lpm_width = 4,
LPM_MUX_component.lpm_widths = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4"
// Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
// Retrieval info: USED_PORT: data0x 0 0 4 0 INPUT NODEFVAL "data0x[3..0]"
// Retrieval info: USED_PORT: data1x 0 0 4 0 INPUT NODEFVAL "data1x[3..0]"
// Retrieval info: USED_PORT: result 0 0 4 0 OUTPUT NODEFVAL "result[3..0]"
// Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL "sel"
// Retrieval info: CONNECT: @data 0 0 4 0 data0x 0 0 4 0
// Retrieval info: CONNECT: @data 0 0 4 4 data1x 0 0 4 0
// Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
// Retrieval info: CONNECT: result 0 0 4 0 @result 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL cntmux.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cntmux.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cntmux.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cntmux.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cntmux_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cntmux_bb.v FALSE
// Retrieval info: LIB_FILE: lpm
|
#include <bits/stdc++.h> using namespace std; inline void read(int &x) { x = 0; int f = 1; char ch = getchar(); for (; !isdigit(ch); ch = getchar()) if (ch == - ) f = -f; for (; isdigit(ch); ch = getchar()) x = (x << 1) + (x << 3) + (ch ^ 48); x *= f; } inline void print(int x) { if (x < 0) putchar( - ), x = -x; if (!x) return; print(x / 10), putchar((x % 10) ^ 48); } inline void write(int x) { if (!x) putchar( 0 ); else print(x); putchar( n ); } int n, ans[5], head[1000050], tot, mx[1000050], mx1[1000050], p, dep[1000050], d, vis[1000050], f[1000050]; struct edge { int to, nxt; } e[1000050 << 1]; void ins(int u, int v) { e[++tot] = (edge){v, head[u]}, head[u] = tot; } void dfs(int x, int fa) { dep[x] = dep[fa] + 1; int cnt = 0; f[x] = fa; for (int i = head[x]; i; i = e[i].nxt) if (e[i].to != fa && !vis[e[i].to]) { dfs(e[i].to, x), cnt++; if (!mx[x] || dep[mx[x]] < dep[mx[e[i].to]]) mx1[x] = mx[x], mx[x] = mx[e[i].to]; else if (dep[mx[e[i].to]] > dep[mx1[x]]) mx1[x] = mx[e[i].to]; } if (!cnt) mx[x] = x; if (cnt >= 2) { if (dep[x] > d) d = dep[x], p = x; else if (dep[x] == d && dep[mx1[x]] + dep[mx[x]] > dep[mx1[p]] + dep[mx[p]]) p = x; } } int main() { read(n); for (int i = 1, x, y; i < n; i++) read(x), read(y), ins(x, y), ins(y, x); dfs(1, 0), ans[1] = mx[p], ans[3] = mx1[p]; for (int i = head[p]; i; i = e[i].nxt) if (e[i].to != f[p] && (mx[e[i].to] == mx[p] || mx[e[i].to] == mx1[p])) vis[e[i].to] = 1; memset(mx, 0, sizeof mx), memset(mx1, 0, sizeof mx1); d = 0; dfs(p, 0), ans[2] = mx[p], ans[4] = mx1[p]; printf( %d %d n%d %d n , ans[1], ans[2], ans[3], ans[4]); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2111A_1_V
`define SKY130_FD_SC_MS__O2111A_1_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog wrapper for o2111a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o2111a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o2111a_1 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o2111a_1 (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2111A_1_V
|
#include <bits/stdc++.h> using namespace std; using ld = long double; using vi = vector<int>; using vll = vector<long long int>; using vd = vector<double>; using vvi = vector<vi>; int ctoi(char c) { return c - 0 ; } int slen(string s) { return s.length(); } int vsize(vi a) { return (int)a.size(); } int in() { int x; cin >> x; return x; } long long int n; void kmin(long long int n, long long int m) { long long int val = n / m; n = n - (val * m); long long int val1 = (m - n) * (val - 1) * (val) / 2; long long int val2 = n * val * (val + 1) / 2; long long int val3 = val1 + val2; cout << val3 << ; } void kmax(long long int n, long long int m) { n = n - (m - 1); long long int val = n * (n - 1) / 2; cout << val; cout << endl; } const int M = 1000000; long long int prime(long long int x) { for (long long int i = 2; i * i <= x; i++) { if (x % i == 0) return i; } return x; } vector<pair<long long int, long long int> > v; set<long long int> s; bool check(long long int x) { for (int i = 1; i < n; i++) { if (v[i].first % x != 0 && v[i].second % x != 0) { return 0; } } return 1; } void get_prime(long long int x) { if (x % 2 == 0) s.insert(2); while (x % 2 == 0) x = x / 2; for (int i = 3; i <= sqrt(x); i += 2) { if (x % i == 0) { s.insert(i); while (x % i == 0) x = x / i; } } if (x > 2) { s.insert(x); } } vll ar[1000000]; set<long long int> cycle; vll path; bool vis[1000000]; int isp(int x) { if (x < 2) return 0; for (int i = 2; i * i <= x; i++) if (x % i == 0) return 0; return 1; } void dfs(int n, int m, int x, int y, bool visited[105][105]) { if (x >= n || y >= m || x < 0 || y < 0 || visited[x][y]) return; visited[x][y] = true; cout << x + 1 << << y + 1 << n ; for (int i = 0; i < n; i++) dfs(n, m, i, y, visited); for (int i = 0; i < m; i++) dfs(n, m, x, i, visited); } void solve() { long long int n, m, ans; cin >> n >> m; if (n == m) { cout << 0; return; } long long int diff = (abs)(n - m); long long int i = 1; while (true) { ans = i * (i + 1) / 2; if (diff == ans) { ans = i; break; } if (diff < ans) { if (ans % 2 == diff % 2) { ans = i; break; } } i++; } cout << ans; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; long long int t = 1; cin >> t; while (t--) { solve(); cout << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; bool debug = 0; int n, m, k; int dx[4] = {0, 1, 0, -1}, dy[4] = {1, 0, -1, 0}; string direc = RDLU ; long long ln, lk, lm; void etp(bool f = 0) { puts(f ? YES : NO ); exit(0); } void addmod(int &x, int y, int mod = 1000000007) { assert(y >= 0); x += y; if (x >= mod) x -= mod; assert(x >= 0 && x < mod); } void et() { puts( -1 ); exit(0); } long long fastPow(long long x, long long y, int mod = 1000000007) { long long ans = 1; while (y > 0) { if (y & 1) ans = (x * ans) % mod; x = x * x % mod; y >>= 1; } return ans; } long long gcd1(long long x, long long y) { long long z = y; while (x % y != 0) { z = x % y; x = y; y = z; } return z; } const int B = 165; int nxt[41005][10], cnt; bool vis[20][41005]; unordered_map<bitset<B>, int> id; bitset<B> rid[41005]; long long dp[20][10][41005]; void init() { bitset<B> bs; bs.reset(); bs[0] = 1; id[bs] = ++cnt; rid[cnt] = bs; vis[0][1] = 1; for (int(i) = 1; (i) <= (int)(19); (i)++) { for (int u = 1; u <= cnt; u++) if (vis[i - 1][u]) { for (int(j) = 0; (j) < (int)(10); (j)++) { if (nxt[u][j] == 0) { if (j == 0) nxt[u][j] = u; else { bs.reset(); bs |= rid[u] >> j; bs |= rid[u] << j; for (int k = 1; k < j; k++) if (rid[u][k]) bs[j - k] = 1; if (id.count(bs)) nxt[u][j] = id[bs]; else { id[bs] = ++cnt; rid[cnt] = bs; nxt[u][j] = cnt; } } } vis[i][nxt[u][j]] = 1; } } } for (int(i) = 1; (i) <= (int)(cnt); (i)++) { int j = 0; for (; j < 10; j++) if (rid[i][j] == 1) break; for (; j < 10; j++) dp[0][j][i] = 1; } for (int(i) = 1; (i) <= (int)(19); (i)++) { for (int(k) = 1; (k) <= (int)(cnt); (k)++) if (vis[19 - i][k]) { for (int(j) = 0; (j) < (int)(10); (j)++) for (int(l) = 0; (l) < (int)(10); (l)++) { dp[i][l][k] += dp[i - 1][l][nxt[k][j]]; } } } } long long cal(long long x, int k) { if (x == 0) return 1; vector<int> bs; while (x) { bs.push_back(x % 10); x /= 10; } long long ans = 0; int u = 1; for (int i = (int)bs.size() - 1; ~i; i--) { for (int j = 0; j < bs[i] + (i == 0); j++) ans += dp[i][k][nxt[u][j]]; u = nxt[u][bs[i]]; } return ans; } void fmain(int ID) { init(); scanf( %d , &n); for (int(i) = 1; (i) <= (int)(n); (i)++) { long long l, r; scanf( %lld%lld%d , &l, &r, &k); printf( %lld n , cal(r, k) - cal(l - 1, k)); } } int main() { int t = 1; for (int(i) = 1; (i) <= (int)(t); (i)++) { fmain(i); } return 0; } |
module soc_system (
button_pio_external_connection_export,
clk_clk,
dipsw_pio_external_connection_export,
hps_0_h2f_reset_reset_n,
hps_0_hps_io_hps_io_emac1_inst_TX_CLK,
hps_0_hps_io_hps_io_emac1_inst_TXD0,
hps_0_hps_io_hps_io_emac1_inst_TXD1,
hps_0_hps_io_hps_io_emac1_inst_TXD2,
hps_0_hps_io_hps_io_emac1_inst_TXD3,
hps_0_hps_io_hps_io_emac1_inst_RXD0,
hps_0_hps_io_hps_io_emac1_inst_MDIO,
hps_0_hps_io_hps_io_emac1_inst_MDC,
hps_0_hps_io_hps_io_emac1_inst_RX_CTL,
hps_0_hps_io_hps_io_emac1_inst_TX_CTL,
hps_0_hps_io_hps_io_emac1_inst_RX_CLK,
hps_0_hps_io_hps_io_emac1_inst_RXD1,
hps_0_hps_io_hps_io_emac1_inst_RXD2,
hps_0_hps_io_hps_io_emac1_inst_RXD3,
hps_0_hps_io_hps_io_sdio_inst_CMD,
hps_0_hps_io_hps_io_sdio_inst_D0,
hps_0_hps_io_hps_io_sdio_inst_D1,
hps_0_hps_io_hps_io_sdio_inst_CLK,
hps_0_hps_io_hps_io_sdio_inst_D2,
hps_0_hps_io_hps_io_sdio_inst_D3,
hps_0_hps_io_hps_io_usb1_inst_D0,
hps_0_hps_io_hps_io_usb1_inst_D1,
hps_0_hps_io_hps_io_usb1_inst_D2,
hps_0_hps_io_hps_io_usb1_inst_D3,
hps_0_hps_io_hps_io_usb1_inst_D4,
hps_0_hps_io_hps_io_usb1_inst_D5,
hps_0_hps_io_hps_io_usb1_inst_D6,
hps_0_hps_io_hps_io_usb1_inst_D7,
hps_0_hps_io_hps_io_usb1_inst_CLK,
hps_0_hps_io_hps_io_usb1_inst_STP,
hps_0_hps_io_hps_io_usb1_inst_DIR,
hps_0_hps_io_hps_io_usb1_inst_NXT,
hps_0_hps_io_hps_io_spim1_inst_CLK,
hps_0_hps_io_hps_io_spim1_inst_MOSI,
hps_0_hps_io_hps_io_spim1_inst_MISO,
hps_0_hps_io_hps_io_spim1_inst_SS0,
hps_0_hps_io_hps_io_uart0_inst_RX,
hps_0_hps_io_hps_io_uart0_inst_TX,
hps_0_hps_io_hps_io_i2c0_inst_SDA,
hps_0_hps_io_hps_io_i2c0_inst_SCL,
hps_0_hps_io_hps_io_i2c1_inst_SDA,
hps_0_hps_io_hps_io_i2c1_inst_SCL,
hps_0_hps_io_hps_io_gpio_inst_GPIO09,
hps_0_hps_io_hps_io_gpio_inst_GPIO35,
hps_0_hps_io_hps_io_gpio_inst_GPIO40,
hps_0_hps_io_hps_io_gpio_inst_GPIO53,
hps_0_hps_io_hps_io_gpio_inst_GPIO54,
hps_0_hps_io_hps_io_gpio_inst_GPIO61,
led_pio_external_connection_export,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
reset_reset_n);
input [3:0] button_pio_external_connection_export;
input clk_clk;
input [3:0] dipsw_pio_external_connection_export;
output hps_0_h2f_reset_reset_n;
output hps_0_hps_io_hps_io_emac1_inst_TX_CLK;
output hps_0_hps_io_hps_io_emac1_inst_TXD0;
output hps_0_hps_io_hps_io_emac1_inst_TXD1;
output hps_0_hps_io_hps_io_emac1_inst_TXD2;
output hps_0_hps_io_hps_io_emac1_inst_TXD3;
input hps_0_hps_io_hps_io_emac1_inst_RXD0;
inout hps_0_hps_io_hps_io_emac1_inst_MDIO;
output hps_0_hps_io_hps_io_emac1_inst_MDC;
input hps_0_hps_io_hps_io_emac1_inst_RX_CTL;
output hps_0_hps_io_hps_io_emac1_inst_TX_CTL;
input hps_0_hps_io_hps_io_emac1_inst_RX_CLK;
input hps_0_hps_io_hps_io_emac1_inst_RXD1;
input hps_0_hps_io_hps_io_emac1_inst_RXD2;
input hps_0_hps_io_hps_io_emac1_inst_RXD3;
inout hps_0_hps_io_hps_io_sdio_inst_CMD;
inout hps_0_hps_io_hps_io_sdio_inst_D0;
inout hps_0_hps_io_hps_io_sdio_inst_D1;
output hps_0_hps_io_hps_io_sdio_inst_CLK;
inout hps_0_hps_io_hps_io_sdio_inst_D2;
inout hps_0_hps_io_hps_io_sdio_inst_D3;
inout hps_0_hps_io_hps_io_usb1_inst_D0;
inout hps_0_hps_io_hps_io_usb1_inst_D1;
inout hps_0_hps_io_hps_io_usb1_inst_D2;
inout hps_0_hps_io_hps_io_usb1_inst_D3;
inout hps_0_hps_io_hps_io_usb1_inst_D4;
inout hps_0_hps_io_hps_io_usb1_inst_D5;
inout hps_0_hps_io_hps_io_usb1_inst_D6;
inout hps_0_hps_io_hps_io_usb1_inst_D7;
input hps_0_hps_io_hps_io_usb1_inst_CLK;
output hps_0_hps_io_hps_io_usb1_inst_STP;
input hps_0_hps_io_hps_io_usb1_inst_DIR;
input hps_0_hps_io_hps_io_usb1_inst_NXT;
output hps_0_hps_io_hps_io_spim1_inst_CLK;
output hps_0_hps_io_hps_io_spim1_inst_MOSI;
input hps_0_hps_io_hps_io_spim1_inst_MISO;
output hps_0_hps_io_hps_io_spim1_inst_SS0;
input hps_0_hps_io_hps_io_uart0_inst_RX;
output hps_0_hps_io_hps_io_uart0_inst_TX;
inout hps_0_hps_io_hps_io_i2c0_inst_SDA;
inout hps_0_hps_io_hps_io_i2c0_inst_SCL;
inout hps_0_hps_io_hps_io_i2c1_inst_SDA;
inout hps_0_hps_io_hps_io_i2c1_inst_SCL;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO09;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO35;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO40;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO53;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO54;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO61;
output [7:0] led_pio_external_connection_export;
output [14:0] memory_mem_a;
output [2:0] memory_mem_ba;
output memory_mem_ck;
output memory_mem_ck_n;
output memory_mem_cke;
output memory_mem_cs_n;
output memory_mem_ras_n;
output memory_mem_cas_n;
output memory_mem_we_n;
output memory_mem_reset_n;
inout [31:0] memory_mem_dq;
inout [3:0] memory_mem_dqs;
inout [3:0] memory_mem_dqs_n;
output memory_mem_odt;
output [3:0] memory_mem_dm;
input memory_oct_rzqin;
input reset_reset_n;
endmodule
|
// Copyright (c) 2000-2011 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 25100 $
// $Date: 2011-09-01 18:44:19 +0000 (Thu, 01 Sep 2011) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// Dual-Ported BRAM (WRITE FIRST)
module BRAM2(CLKA,
ENA,
WEA,
ADDRA,
DIA,
DOA,
CLKB,
ENB,
WEB,
ADDRB,
DIB,
DOB
);
parameter PIPELINED = 0;
parameter ADDR_WIDTH = 1;
parameter DATA_WIDTH = 1;
parameter MEMSIZE = 1;
input CLKA;
input ENA;
input WEA;
input [ADDR_WIDTH-1:0] ADDRA;
input [DATA_WIDTH-1:0] DIA;
output [DATA_WIDTH-1:0] DOA;
input CLKB;
input ENB;
input WEB;
input [ADDR_WIDTH-1:0] ADDRB;
input [DATA_WIDTH-1:0] DIB;
output [DATA_WIDTH-1:0] DOB;
reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1] /* synthesis syn_ramstyle="no_rw_check" */ ;
reg [DATA_WIDTH-1:0] DOA_R;
reg [DATA_WIDTH-1:0] DOB_R;
reg [DATA_WIDTH-1:0] DOA_R2;
reg [DATA_WIDTH-1:0] DOB_R2;
`ifdef BSV_NO_INITIAL_BLOCKS
`else
// synopsys translate_off
integer i;
initial
begin : init_block
for (i = 0; i < MEMSIZE; i = i + 1) begin
RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
DOA_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOB_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOA_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOB_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
// synopsys translate_on
`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
always @(posedge CLKA) begin
if (ENA) begin
if (WEA) begin
RAM[ADDRA] <= `BSV_ASSIGNMENT_DELAY DIA;
DOA_R <= `BSV_ASSIGNMENT_DELAY DIA;
end
else begin
DOA_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRA];
end
end
DOA_R2 <= `BSV_ASSIGNMENT_DELAY DOA_R;
end
always @(posedge CLKB) begin
if (ENB) begin
if (WEB) begin
RAM[ADDRB] <= `BSV_ASSIGNMENT_DELAY DIB;
DOB_R <= `BSV_ASSIGNMENT_DELAY DIB;
end
else begin
DOB_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRB];
end
end
DOB_R2 <= `BSV_ASSIGNMENT_DELAY DOB_R;
end
// Output drivers
assign DOA = (PIPELINED) ? DOA_R2 : DOA_R;
assign DOB = (PIPELINED) ? DOB_R2 : DOB_R;
endmodule // BRAM2
|
#include <bits/stdc++.h> using namespace std; long long int n, k, dp[2009][2009], cnt; long long int solve(int pos, int mx) { if (pos == k) return 1; long long int &res = dp[pos][mx]; if (res != -1) return res; res = 0; int lim = mx; if (lim == 0) lim = 1; if (mx == 0) { for (int i = lim; i <= n; i += lim) { res += solve(pos + 1, i); res %= 1000000007; } } else { for (int i = lim; i <= n; i += lim) { if (i % mx == 0) { res += solve(pos + 1, i); res %= 1000000007; } } } return res; } int main() { cin >> n >> k; memset(dp, -1, sizeof(dp)); long long int ans = solve(0, 0); cout << ans << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21OI_PP_SYMBOL_V
`define SKY130_FD_SC_LS__A21OI_PP_SYMBOL_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a21oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21OI_PP_SYMBOL_V
|
/*
* University of Illinois/NCSA
* Open Source License
*
* Copyright (c) 2007-2014,The Board of Trustees of the University of
* Illinois. All rights reserved.
*
* Copyright (c) 2014 Matthew Hicks
*
* Developed by:
*
* Matthew Hicks in the Department of Computer Science
* The University of Illinois at Urbana-Champaign
* http://www.impedimentToProgress.com
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated
* documentation files (the "Software"), to deal with the
* Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute,
* sublicense, and/or sell copies of the Software, and to permit
* persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* Redistributions of source code must retain the above
* copyright notice, this list of conditions and the
* following disclaimers.
*
* Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the
* following disclaimers in the documentation and/or other
* materials provided with the distribution.
*
* Neither the names of Sam King, the University of Illinois,
* nor the names of its contributors may be used to endorse
* or promote products derived from this Software without
* specific prior written permission.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE CONTRIBUTORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS WITH THE SOFTWARE.
*/
`timescale 1ns/1ns
module unitTestNext();
reg clk;
wire rst;
reg start;
reg test_expr;
wire inv;
wire assert;
initial begin
clk = 1'b0;
start = 1'b0;
test_expr = 1'b0;
end
assign rst = 1'b0;
assign inv = 1'b0;
always begin
#10 clk = ~clk;
#10 clk = ~clk;
// Make sure missing start doesn't fire
test_expr = 1'b1;
#10 clk = ~clk;
#10 clk = ~clk;
test_expr = 1'b0;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
// Test to make sure test can fire early and stay late as long as it is valid at num cks
start = 1'b1;
#10 clk = ~clk;
#10 clk = ~clk;
start =1'b0;
#10 clk = ~clk;
#10 clk = ~clk;
test_expr = 1'b1;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
test_expr = 1'b0;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
// Test normal operation
start = 1'b1;
#10 clk = ~clk;
#10 clk = ~clk;
start = 1'b0;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
test_expr = 1'b1;
#10 clk = ~clk;
#10 clk = ~clk;
test_expr = 1'b0;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
// Test for assertion violations
start = 1'b1;
#10 clk = ~clk;
#10 clk = ~clk;
start = 1'b0;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
test_expr = 1'b1;
#10 clk = ~clk;
#10 clk = ~clk;
test_expr = 1'b0;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
// Test for overlapping starts
start = 1'b1;
#10 clk = ~clk;
#10 clk = ~clk;
start = 1'b0;
#10 clk = ~clk;
#10 clk = ~clk;
start = 1'b1;
#10 clk = ~clk;
#10 clk = ~clk;
start = 1'b0;
test_expr = 1'b1;
#10 clk = ~clk;
#10 clk = ~clk;
test_expr = 1'b0;
#10 clk = ~clk;
#10 clk = ~clk;
test_expr = 1'b1;
#10 clk = ~clk;
#10 clk = ~clk;
test_expr = 1'b0;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
end
ovl_next_wrapped onw(
.clk(clk),
.rst(rst),
.num_cks(3'd3),
.start_event(start),
.test_expr(test_expr),
.prevConfigInvalid(inv),
.out(assert)
);
endmodule |
#include <bits/stdc++.h> using namespace std; class TaskD { public: void solve(std::istream &in, std::ostream &out) { long long n; in >> n; vector<long long> a(n), b(n), sa(n), sb(n); for (auto &i : a) in >> i; for (auto &i : b) in >> i; for (long long i = 0; i < n; ++i) { sa[i] = a[i] - b[i]; sb[i] = b[i] - a[i]; } sort((sa).begin(), (sa).end()); sort((sb).begin(), (sb).end()); long long ans = 0; for (long long i = 0; i < n; ++i) { ans += (long long)(sa.end() - lower_bound((sa).begin(), (sa).end(), sb[i] + 1)); if (sb[i] < 0) ans -= 1; } out << ans / 2 << endl; } }; signed main() { TaskD solver; std::istream &in(std::cin); std::ostream &out(std::cout); solver.solve(in, out); return 0; } |
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
//dpram.v: Generic dual-ported RAM with optional single-stage or two-stage bypass.//
// //
// Author: Ameer M. Abdelhadi (, ) //
// SRAM-based Multi-ported RAMs; University of British Columbia (UBC), March 2013 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
module dpram
#( parameter MEMD = 16, // memory depth
parameter DATAW = 32, // data width
parameter BYPASS = 1 , // bypass? 0:none; 1: single-stage; 2: two-stage
parameter IZERO = 0 , // binary / Initial RAM with zeros (has priority over IFILE)
parameter IFILE = "" // initialization hex file (don't pass extension), optional
)( input clk , // clock
input WEnb , // write enable for each writing port
input [`log2(MEMD)-1:0] WAddr, // write addresses - packed from nWPORTS write ports
input [DATAW -1:0] WData, // write data - packed from nRPORTS read ports
input [`log2(MEMD)-1:0] RAddr, // read addresses - packed from nRPORTS read ports
output reg [DATAW -1:0] RData // read data - packed from nRPORTS read ports
);
wire [DATAW-1:0] RData_i; // read ram data (internal) - packed from nRPORTS read ports
mpram_gen #( .MEMD (MEMD ), // memory depth
.DATAW (DATAW ), // data width
.nRPORTS(1 ), // number of reading ports
.nWPORTS(1 ), // number of writing ports
.IZERO (IZERO ), // binary / Initial RAM with zeros (has priority over INITFILE)
.IFILE (IFILE )) // initializtion file, optional
dpram_inst ( .clk (clk ), // clock
.WEnb (WEnb ), // write enable for each writing port - in : [nWPORTS-1:0 ]
.WAddr (WAddr ), // write addresses - packed from nWPORTS write ports - in : [`log2(MEMD)*nWPORTS-1:0]
.WData (WData ), // write data - packed from nRPORTS read ports - out: [DATAW *nWPORTS-1:0]
.RAddr (RAddr ), // read addresses - packed from nRPORTS read ports - in : [`log2(MEMD)*nRPORTS-1:0]
.RData (RData_i)); // read data - packed from nRPORTS read ports - out: [DATAW *nRPORTS-1:0]
// registers; will be removed if unused
reg WEnb_r;
reg [`log2(MEMD)-1:0] WAddr_r;
reg [`log2(MEMD)-1:0] RAddr_r;
reg [DATAW-1:0] WData_r;
always @(posedge clk) begin
WEnb_r <= WEnb ;
WAddr_r <= WAddr;
RAddr_r <= RAddr;
WData_r <= WData; // bypass register
end
// bypass: single-staeg, two-stage (logic will be removed if unused)
wire bypass1,bypass2;
assign bypass1 = (BYPASS >= 1) && WEnb_r && (WAddr_r == RAddr_r);
assign bypass2 = (BYPASS == 2) && WEnb && (WAddr == RAddr_r);
// output mux (mux or mux inputs will be removed if unused)
always @*
if (bypass2) RData = WData ;
else if (bypass1) RData = WData_r;
else RData = RData_i;
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Low latency FIFO
// One cycle latency from all inputs to all outputs
// Storage implemented in registers, not memory.
module acl_ll_fifo(clk, reset, data_in, write, data_out, read, empty, full, almost_full);
/* Parameters */
parameter WIDTH = 32;
parameter DEPTH = 32;
parameter ALMOST_FULL_VALUE = 0;
/* Ports */
input clk;
input reset;
input [WIDTH-1:0] data_in;
input write;
output [WIDTH-1:0] data_out;
input read;
output empty;
output full;
output almost_full;
/* Architecture */
// One-hot write-pointer bit (indicates next position to write at),
// last bit indicates the FIFO is full
reg [DEPTH:0] wptr;
// Replicated copy of the stall / valid logic
reg [DEPTH:0] wptr_copy /* synthesis dont_merge */;
// FIFO data registers
reg [DEPTH-1:0][WIDTH-1:0] data;
// Write pointer updates:
wire wptr_hold; // Hold the value
wire wptr_dir; // Direction to shift
// Data register updates:
wire [DEPTH-1:0] data_hold; // Hold the value
wire [DEPTH-1:0] data_new; // Write the new data value in
// Write location is constant unless the occupancy changes
assign wptr_hold = !(read ^ write);
assign wptr_dir = read;
// Hold the value unless we are reading, or writing to this
// location
genvar i;
generate
for(i = 0; i < DEPTH; i++)
begin : data_mux
assign data_hold[i] = !(read | (write & wptr[i]));
assign data_new[i] = !read | wptr[i+1];
end
endgenerate
// The data registers
generate
for(i = 0; i < DEPTH-1; i++)
begin : data_reg
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
data[i] <= {WIDTH{1'b0}};
else
data[i] <= data_hold[i] ? data[i] :
data_new[i] ? data_in : data[i+1];
end
end
endgenerate
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
data[DEPTH-1] <= {WIDTH{1'b0}};
else
data[DEPTH-1] <= data_hold[DEPTH-1] ? data[DEPTH-1] : data_in;
end
// The write pointer
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
begin
wptr <= {{DEPTH{1'b0}}, 1'b1};
wptr_copy <= {{DEPTH{1'b0}}, 1'b1};
end
else
begin
wptr <= wptr_hold ? wptr :
wptr_dir ? {1'b0, wptr[DEPTH:1]} : {wptr[DEPTH-1:0], 1'b0};
wptr_copy <= wptr_hold ? wptr_copy :
wptr_dir ? {1'b0, wptr_copy[DEPTH:1]} : {wptr_copy[DEPTH-1:0], 1'b0};
end
end
// Outputs
assign empty = wptr_copy[0];
assign full = wptr_copy[DEPTH];
assign almost_full = wptr_copy[DEPTH - ALMOST_FULL_VALUE];
assign data_out = data[0];
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_arb_rd.v
*
* Date : 2012-11
*
* Description : Module that arbitrates between 2 read requests from 2 ports.
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_arb_rd(
rstn,
sw_clk,
qos1,
qos2,
prt_req1,
prt_req2,
prt_bytes1,
prt_bytes2,
prt_addr1,
prt_addr2,
prt_data1,
prt_data2,
prt_dv1,
prt_dv2,
prt_req,
prt_qos,
prt_addr,
prt_bytes,
prt_data,
prt_dv
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input rstn, sw_clk;
input [axi_qos_width-1:0] qos1,qos2;
input prt_req1, prt_req2;
input [addr_width-1:0] prt_addr1, prt_addr2;
input [max_burst_bytes_width:0] prt_bytes1, prt_bytes2;
output reg prt_dv1, prt_dv2;
output reg [max_burst_bits-1:0] prt_data1,prt_data2;
output reg prt_req;
output reg [axi_qos_width-1:0] prt_qos;
output reg [addr_width-1:0] prt_addr;
output reg [max_burst_bytes_width:0] prt_bytes;
input [max_burst_bits-1:0] prt_data;
input prt_dv;
parameter wait_req = 2'b00, serv_req1 = 2'b01, serv_req2 = 2'b10,wait_dv_low = 2'b11;
reg [1:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
state = wait_req;
prt_req = 1'b0;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_qos = 0;
end else begin
case(state)
wait_req:begin
state = wait_req;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_req = 0;
if(prt_req1 && !prt_req2) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(!prt_req1 && prt_req2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_req1 && prt_req2) begin
if(qos1 > qos2) begin
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end else if(qos1 < qos2) begin
prt_req = 1;
prt_addr = prt_addr2;
prt_qos = qos2;
prt_bytes = prt_bytes2;
state = serv_req2;
end else begin
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end
end
end
serv_req1:begin
state = serv_req1;
prt_dv2 = 1'b0;
if(prt_dv) begin
prt_dv1 = 1'b1;
prt_data1 = prt_data;
prt_req = 0;
if(prt_req2) begin
prt_req = 1;
prt_qos = qos2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end else begin
state = wait_dv_low;
//state = wait_req;
end
end
end
serv_req2:begin
state = serv_req2;
prt_dv1 = 1'b0;
if(prt_dv) begin
prt_dv2 = 1'b1;
prt_data2 = prt_data;
prt_req = 0;
if(prt_req1) begin
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end else begin
state = wait_dv_low;
//state = wait_req;
end
end
end
wait_dv_low:begin
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
state = wait_dv_low;
if(!prt_dv)
state = wait_req;
end
endcase
end /// if else
end /// always
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:16:07 08/01/2015
// Design Name: samcoupe
// Module Name: C:/Users/rodriguj/Documents/zxspectrum/zxuno/repositorio/cores/sam_coupe_spartan6/test1/tb_samcoupe.v
// Project Name: samcoupe
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: samcoupe
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_samcoupe;
// Inputs
reg clk24;
reg clk12;
reg clk6;
reg ear;
reg clkps2;
reg dataps2;
reg rst_n;
// Outputs
wire [1:0] r;
wire [1:0] g;
wire [1:0] b;
wire bright;
wire csync;
wire audio_out_left;
wire audio_out_right;
wire [18:0] sram_addr;
wire sram_we_n;
// Bidirs
wire [7:0] sram_data;
// Instantiate the Unit Under Test (UUT)
samcoupe uut (
.clk24(clk24),
.clk12(clk12),
.clk6(clk6),
.master_reset_n(rst_n),
.r(r),
.g(g),
.b(b),
.bright(bright),
.csync(csync),
.ear(ear),
.audio_out_left(audio_out_left),
.audio_out_right(audio_out_right),
.clkps2(clkps2),
.dataps2(dataps2),
.sram_addr(sram_addr),
.sram_data(sram_data),
.sram_we_n(sram_we_n)
);
sram_sim memoria (
.a(sram_addr[15:0]),
.d(sram_data),
.we_n(sram_we_n)
);
initial begin
// Initialize Inputs
clk24 = 1;
clk12 = 1;
clk6 = 1;
ear = 0;
clkps2 = 1;
dataps2 = 1;
rst_n = 0;
// Add stimulus here
#100;
rst_n = 1;
end
always begin
clk24 = #(1000/48.0) ~clk24;
end
always begin
clk12 = #(1000/24.0) ~clk12;
end
always begin
clk6 = #(1000/12.0) ~clk6;
end
endmodule
module sram_sim (
input wire [15:0] a,
inout wire [7:0] d,
input wire we_n
);
reg [7:0] m[0:65535];
reg [7:0] dout;
integer i;
initial begin
for (i=0;i<65536;i=i+1)
m[i] = {i[15:14],i[5:0]};
end
assign d = (we_n == 1'b0)? 8'hZZ : dout;
always @* begin
if (we_n == 1'b0) begin
#35;
m[a] = d;
end
end
always @* begin
if (we_n == 1'b1) begin
#45;
dout = m[a];
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2111A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__O2111A_BEHAVIORAL_PP_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o2111a (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , B1, C1, or0_out, D1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2111A_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const long long N = 2e5 + 5, inf = 998244353; long long n, k, i; long long A[N], B[N]; long long in[N], f[N]; inline long long expo(long long n, long long k, long long p = inf) { long long r = 1; for (; k; k >>= 1) { if (k & 1) r = r * n % p; n = n * n % p; } return r; } inline long long inv(long long a, long long p = inf) { return expo(a, p - 2, p); } vector<long long> BIT(N); void upd(long long first, long long val) { for (; first <= n; first += (first & -first)) BIT[first] += val; } long long q(long long first) { long long res = 0; for (; first > 0; first -= (first & -first)) res += BIT[first]; return res; } long long m[N]; signed main() { ios_base::sync_with_stdio(false); cin.tie(0); long long i, j, first, second, ans = 0, c = 0, a; cin >> n; for (i = 1; i < n + 1; i++) { cin >> A[i]; if (A[i] != -1) { m[A[i]] = 1; ans += c - q(A[i] - 1); upd(A[i], 1); c++; } } vector<long long> v; for (i = 1; i < n + 1; i++) if (!m[i]) v.emplace_back(i); ans += 1LL * (long long)v.size() * ((long long)v.size() - 1) % inf * inv(4) % inf; long long t = 0; c = 0; for (i = 1; i < n + 1; i++) { if (A[i] != -1) { a = lower_bound(v.begin(), v.end(), A[i]) - v.begin(); ans += c * ((long long)v.size() - a) % inf * inv((long long)v.size()) % inf; ans += a * ((long long)v.size() - c) % inf * inv((long long)v.size()) % inf; } else c++; } cout << ans % inf; } |
#include <bits/stdc++.h> using namespace std; const int inf = (int)1e9, maxn = (int)1e5 + 1; const double eps = (double)1e-8; const int mod = (int)1000000009; int n, a[1001], x, y, xx, yy, z, my, mx; vector<pair<int, bool> > b[3000]; string c, st; int main() { my = 1500; z = 1500; cin >> n; x = 0; y = 0; for (int i = 1; i <= n; i++) { cin >> a[i]; xx = x; yy = y; x += a[i]; if (i & 1) { y += a[i]; for (int j = yy; j < y; j++) b[z + j].push_back(make_pair(xx + j - yy, 1)); } else { y -= a[i]; for (int j = yy - 1; j >= y; j--) b[z + j].push_back(make_pair(xx + (yy - j - 1), 0)); } my = max(my, y + z); } st = ; for (int i = 0; i < x; i++) st += ; mx = x; for (int i = my - 1;; i--) { c = st; if (b[i].size() == 0) break; for (int j = 0; j < b[i].size(); j++) { if (b[i][j].second) c[b[i][j].first] = / ; else c[b[i][j].first] = char(92); } cout << c << endl; } return 0; } |
#include<bits/stdc++.h> using namespace std; #define int long long const int maxn = 2000005; int tag[maxn],summ[maxn]; int len[maxn]; int n,k; void push_up(int p){ summ[p] = summ[p<<1] + summ[p<<1|1]; } void push_down(int p,int l,int r){ if(tag[p] == 0) return; int x = tag[p]; tag[p] = 0; int mid = (l+r)>>1; tag[p<<1] += x,tag[p<<1|1] += x; summ[p<<1] += x * (mid - l + 1); summ[p<<1|1] += x * (r - mid); } void build(int l,int r,int p) { tag[p] = 0; if(l == r){ if(l == 1) summ[p] = 1; else summ[p] = 0; return; } int mid = (l+r)>>1; build(l,mid,p<<1); build(mid+1,r,p<<1|1); push_up(p); } void gai(int l,int r,int p,int ll,int rr,int z){ if(ll > rr) return; if(l != r) push_down(p,l,r); if(ll <= l && r <= rr){ summ[p] += (r - l + 1) * z; tag[p] += z; if(l != r) push_down(p,l,r); return; } int mid = (l+r)>>1; if(ll <= mid) gai(l,mid,p<<1,ll,rr,z); if(rr > mid) gai(mid+1,r,p<<1|1,ll,rr,z); push_up(p); } int cha(int l,int r,int p,int z){ // printf( %lld %lld %lld n ,l,r,summ[p]); if(l == r) return l; else push_down(p,l,r); int mid = (l+r)>>1; if(z <= summ[p<<1]){ return cha(l,mid,p<<1,z);//第z小 } z -= summ[p<<1]; return cha(mid+1,r,p<<1|1,z); } void chong(int l,int r,int p) { if(l == r) return; push_down(p,l,r); int mid = (l+r)>>1; chong(l,mid,p<<1); chong(mid+1,r,p<<1|1); } signed main() { scanf( %lld%lld ,&n,&k); for(int i=1;i<=n;++i) scanf( %lld ,&len[i]); sort(len + 1,len + n + 1); reverse(len + 1,len + n + 1); build(1,300000,1); int ans = 1e9; // for(int i=1;i<=n;++i) printf( %lld ,len[i]); // return 0; for(int i=1;i<=n+1;++i){ // printf( n n ); if(summ[1] >= k) { int ak = cha(1,300000,1,k); ans = min(ans,ak); //printf( %lld n ,ak); } if(n == i - 1) break; // chong(1,300000,1); int akk = cha(1,300000,1,1); gai(1,300000,1,akk,akk,-1);//直接-1 // printf( %lld n ,akk); // return 0; int x = len[i]; x --; akk += 2;//在这里减 if(x % 2 == 0){ gai(1,300000,1,akk,akk + x/2 - 1,2); } else{ // printf( %lld n ,akk); gai(1,300000,1,akk,akk + x/2-1,1);//3 gai(1,300000,1,akk,akk + x/2,1);//3 4 } } if(ans != 1e9) printf( %lld n ,ans-1); else printf( -1 ); } |
#include <bits/stdc++.h> using namespace std; long long mod = 1000000007; vector<long long> v(100004); vector<long long> t(100004, 0); int n; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); int bsearch(int r, int key) { int l = -1; while (r - l > 1) { int m = (r + l) / 2; if (t[m] >= key) { r = m; } else { l = m; } } return r; } int longest() { int length = 1; t[0] = v[0]; for (int i = 1; i < n; ++i) { if (v[i] < t[0]) t[0] = v[i]; else if (v[i] > t[length - 1]) { t[length] = v[i]; length++; } else { t[bsearch(length - 1, v[i])] = v[i]; } } return length; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; for (int i = 0; i < n; ++i) { cin >> v[i]; } cout << longest(); return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
wire [15:-16] sel2 = crc[31:0];
wire [80:-10] sel3 = {crc[26:0],crc};
wire [3:0] out21 = sel2[-3 : -6];
wire [3:0] out22 = sel2[{1'b0,crc[3:0]} - 16 +: 4];
wire [3:0] out23 = sel2[{1'b0,crc[3:0]} - 10 -: 4];
wire [3:0] out31 = sel3[-3 : -6];
wire [3:0] out32 = sel3[crc[5:0] - 6 +: 4];
wire [3:0] out33 = sel3[crc[5:0] - 6 -: 4];
// Aggregate outputs into a single result vector
wire [63:0] result = {40'h0, out21, out22, out23, out31, out32, out33};
reg [15:-16] sel1;
initial begin
// Path clearing
sel1 = 32'h12345678;
if (sel1 != 32'h12345678) $stop;
if (sel1[-13 : -16] != 4'h8) $stop;
if (sel1[3:0] != 4'h4) $stop;
if (sel1[4 +: 4] != 4'h3) $stop;
if (sel1[11 -: 4] != 4'h2) $stop;
end
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] sels=%x,%x,%x %x,%x,%x\n",$time, out21,out22,out23, out31,out32,out33);
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'hba7fe1e7ac128362
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// MBT 7/24/2014
//
// This is a launch/synchronization complex.
// The launch flop prevents combinational glitching.
// The two sync flops reduce probability of metastability.
// See MBT's note on async design and CDC.
//
// The three flops should be don't touched in synopsys
// and abutted in physical design to reduce chances of metastability.
//
// Use of reset is optional; it can be used to hold a known value during reset
// if for instance, the value is coming off chip.
//
// the code is structured this way because synopsys's
// support for hierarchical placement groups appears
// not to work for parameterized modules.
// so we must have a non-parameterized module
// in order to abut the three registers, which
// have two different clocks.
//
`define bsg_launch_sync_sync_unit_hard(EDGE,bits) \
\
module bsg_launch_sync_sync_``EDGE``_``bits``_unit \
(input iclk_i \
,input iclk_reset_i \
,input oclk_i \
,input [bits-1:0] iclk_data_i \
,output [bits-1:0] iclk_data_o \
,output [bits-1:0] oclk_data_o \
); \
\
genvar i; \
\
logic [bits-1:0] bsg_SYNC_LNCH_r; \
logic [bits-1:0] bsg_SYNC_2_r; \
\
assign iclk_data_o = bsg_SYNC_LNCH_r; \
assign oclk_data_o = bsg_SYNC_2_r; \
\
always_ff @(EDGE iclk_i) \
begin \
if (iclk_reset_i) \
bsg_SYNC_LNCH_r <= {bits{1'b0}}; \
else \
bsg_SYNC_LNCH_r <= iclk_data_i; \
end \
\
for (i = 0; i < bits; i = i + 1) \
begin : blss_unit \
SDFFYQ2D_X2N_A7P5PP96PTS_C16 hard_sync_int \
(.D (bsg_SYNC_LNCH_r[i]) \
,.CK (oclk_i) \
,.SI (1'b0) \
,.SE (1'b0) \
,.Q (bsg_SYNC_2_r[i]) \
); \
end \
\
endmodule
`BSG_ABSTRACT_MODULE(bsg_launch_sync_sync)
// bsg_launch_sync_sync_posedge_1_unit
`bsg_launch_sync_sync_unit_hard(posedge,1)
`bsg_launch_sync_sync_unit_hard(posedge,2)
`bsg_launch_sync_sync_unit_hard(posedge,3)
`bsg_launch_sync_sync_unit_hard(posedge,4)
`bsg_launch_sync_sync_unit_hard(posedge,5)
`bsg_launch_sync_sync_unit_hard(posedge,6)
`bsg_launch_sync_sync_unit_hard(posedge,7)
`bsg_launch_sync_sync_unit_hard(posedge,8)
// bsg_launch_sync_sync_negedge_1_unit
`bsg_launch_sync_sync_unit_hard(negedge,1)
`bsg_launch_sync_sync_unit_hard(negedge,2)
`bsg_launch_sync_sync_unit_hard(negedge,3)
`bsg_launch_sync_sync_unit_hard(negedge,4)
`bsg_launch_sync_sync_unit_hard(negedge,5)
`bsg_launch_sync_sync_unit_hard(negedge,6)
`bsg_launch_sync_sync_unit_hard(negedge,7)
`bsg_launch_sync_sync_unit_hard(negedge,8)
// warning: if you make this != 8, you need
// to modify other parts of this code
`define blss_max_block 8
// handle trailer bits
`define blss_if_clause(EDGE,num) if ((width_p % `blss_max_block) == num) begin: z \
bsg_launch_sync_sync_``EDGE``_``num``_unit blss \
(.iclk_i \
,.iclk_reset_i \
,.oclk_i \
,.iclk_data_i(iclk_data_i[width_p-1-:num]) \
,.iclk_data_o(iclk_data_o[width_p-1-:num]) \
,.oclk_data_o(oclk_data_o[width_p-1-:num]) \
); end
module bsg_launch_sync_sync #(parameter `BSG_INV_PARAM(width_p)
, parameter use_negedge_for_launch_p = 0)
(input iclk_i
, input iclk_reset_i
, input oclk_i
, input [width_p-1:0] iclk_data_i
, output [width_p-1:0] iclk_data_o // after launch flop
, output [width_p-1:0] oclk_data_o // after sync flops
);
genvar i;
// synopsys translate_off
initial assert (iclk_reset_i !== 'z)
else
begin
$error("%m iclk_reset should be connected");
$finish();
end
// synopsys translate_on
if (use_negedge_for_launch_p)
begin: n
for (i = 0; i < (width_p/`blss_max_block); i = i + 1)
begin : maxb
bsg_launch_sync_sync_negedge_8_unit blss
(.iclk_i
,.iclk_reset_i
,.oclk_i
,.iclk_data_i(iclk_data_i[i*`blss_max_block+:`blss_max_block])
,.iclk_data_o(iclk_data_o[i*`blss_max_block+:`blss_max_block])
,.oclk_data_o(oclk_data_o[i*`blss_max_block+:`blss_max_block])
);
end
`blss_if_clause(negedge,1) else
`blss_if_clause(negedge,2) else
`blss_if_clause(negedge,3) else
`blss_if_clause(negedge,4) else
`blss_if_clause(negedge,5) else
`blss_if_clause(negedge,6) else
`blss_if_clause(negedge,7)
end
else
begin: p
for (i = 0; i < (width_p/`blss_max_block); i = i + 1)
begin : maxb
bsg_launch_sync_sync_posedge_8_unit blss
(.iclk_i
,.iclk_reset_i
,.oclk_i
,.iclk_data_i(iclk_data_i[i*`blss_max_block+:`blss_max_block])
,.iclk_data_o(iclk_data_o[i*`blss_max_block+:`blss_max_block])
,.oclk_data_o(oclk_data_o[i*`blss_max_block+:`blss_max_block])
);
end
`blss_if_clause(posedge,1) else
`blss_if_clause(posedge,2) else
`blss_if_clause(posedge,3) else
`blss_if_clause(posedge,4) else
`blss_if_clause(posedge,5) else
`blss_if_clause(posedge,6) else
`blss_if_clause(posedge,7)
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_launch_sync_sync)
|
#include <bits/stdc++.h> using namespace std; int n; long long a, b, T; char s[500010]; long long pref[500010]; long long suff[500010]; int main() { cin >> n >> a >> b >> T; for (int i = 1; i <= n; ++i) { cin >> s[i]; } pref[1] = 0; for (int i = 2; i <= n; ++i) { pref[i] = a + pref[i - 1] + 1; if (s[i] == w ) { pref[i] += b; } } suff[n + 1] = 0; for (int i = n; i >= 2; --i) { suff[i] = a + 1 + suff[i + 1]; if (s[i] == w ) { suff[i] += b; } } int ans = 0; long long t = 1; if (s[1] == w ) { t += b; } if (T < t) { cout << 0; return 0; } T -= t; ++ans; for (int i = 2; i <= n; ++i) { if (pref[i] > T) { break; } ans = max(ans, i); long long t = T - pref[i] - (i - 1) * a; if (t < 0) { continue; } int l = i; int r = n + 1; while (l + 1 < r) { int m = (l + r) / 2; if (suff[m] <= t) { r = m; } else { l = m; } } ans = max(ans, i + n + 1 - r); } for (int i = n; i >= 2; --i) { if (suff[i] > T) { break; } ans = max(n - i + 2, ans); long long t = T - suff[i] - (n + 1 - i) * a; if (t < 0) { continue; } int l = 1, r = i; while (l + 1 < r) { int m = (l + r) / 2; if (pref[m] <= t) { l = m; } else { r = m; } } ans = max(ans, n - i + 1 + l); } cout << ans; return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize(3) using namespace std; struct IO { char buf[(1 << 20)], *p1, *p2; char pbuf[(1 << 20)], *pp; IO() : p1(buf), p2(buf), pp(pbuf) {} ~IO() { fwrite(pbuf, 1, pp - pbuf, stdout); } inline char gc() { if (p1 == p2) p2 = (p1 = buf) + fread(buf, 1, (1 << 20), stdin); return p1 == p2 ? : *p1++; } inline bool blank(char ch) { return ch == || ch == n || ch == r || ch == t ; } template <class T> inline void read(T &x) { double tmp = 1; bool sign = 0; x = 0; char ch = gc(); for (; !(ch >= 0 && ch <= 9 ); ch = gc()) if (ch == - ) sign = 1; for (; (ch >= 0 && ch <= 9 ); ch = gc()) x = x * 10 + (ch - 0 ); if (ch == . ) for (ch = gc(); (ch >= 0 && ch <= 9 ); ch = gc()) tmp /= 10.0, x += tmp * (ch - 0 ); if (sign) x = -x; } inline void read(char *s) { char ch = gc(); for (; blank(ch); ch = gc()) ; for (; !blank(ch); ch = gc()) *s++ = ch; *s = 0; } inline void read(char &c) { for (c = gc(); blank(c); c = gc()) ; } inline void push(const char &c) { if (pp - pbuf == (1 << 20)) fwrite(pbuf, 1, (1 << 20), stdout), pp = pbuf; *pp++ = c; } template <class T> inline void write(T x) { if (x < 0) x = -x, push( - ); static T sta[35]; T top = 0; do { sta[top++] = x % 10, x /= 10; } while (x); while (top) push(sta[--top] + 0 ); } template <class T> inline void write(T x, char lastChar) { write(x), push(lastChar); } } io; constexpr long long N = 1e5 + 5; constexpr double eps = 1e-6; long long n, k, m, d; long long id[64]; long long v[64]; long long Q; long long level(long long x) { long long ans = 0; while (x) { ans++; x >>= 1LL; } return ans; } signed main() { ios::sync_with_stdio(false), cin.tie(nullptr), cout.tie(nullptr); ; cin >> Q; while (Q--) { long long T; cin >> T; if (T == 1LL) { long long X, K; cin >> X >> K; long long l = level(X); long long M = (1LL << (l - 1LL)); v[l] += K % M; v[l] %= M; if (v[l] < 0) v[l] += M; } else if (T == 2) { long long X, K; cin >> X >> K; long long l = level(X); while (l < 64) { long long M = (1LL << (l - 1LL)); K %= M; v[l] += K % M; v[l] %= M; if (v[l] < 0) v[l] += M; id[l] += K % M; id[l] %= M; if (id[l] < 0) id[l] += M; l++; K *= 2; } } else { long long X; cin >> X; cout << X << ; long long l = level(X); long long M = 1LL << (l - 1LL); X -= M; long long rawid = (X + v[l] + M) % M; long long nowid = (rawid + id[l] + M) % M; while (M + rawid != 1LL) { rawid = (M + rawid) >> 1LL; M >>= 1LL; l--; rawid -= M; cout << M + (rawid - v[l] + M) % M << ; } cout << endl; } } return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; template <typename T> T sqr(T a) { return a * a; } template <typename T> int sign(T a) { if (a == 0) return 0; return (a > 0 ? 1 : -1); } template <typename T1, typename T2> T2 sum_mod(T1 x, T2 MOD) { if (x < 0) x += MOD; if (x >= MOD) x -= MOD; return x; } template <typename T1, typename T2> T2 mul_mod(T1 x, T2 MOD) { if (x < 0) return (abs(x) % MOD == 0 ? 0 : MOD - abs(x) % MOD); return x % MOD; } template <typename T> bool uax(T& a, const T b) { if (a < b) { a = b; return true; } return false; } template <typename T> bool uin(T& a, const T b) { if (a > b) { a = b; return true; } return false; } template <typename T1, typename T2> istream& operator>>(istream& in, pair<T1, T2>& p) { in >> p.first >> p.second; return in; } template <typename T1, typename T2> ostream& operator<<(ostream& out, pair<T1, T2>& p) { out << p.first << << p.second; return out; } const int LOG = 18; const int N = (int)1e5 + 7; const int MAXN = (int)2e3 + 7; const int MOD = (int)998244353; const int INF = (int)1e9 + 7; const int CONST = 300; const long long LINF = (int64_t)2e15; const long double PI = 3.1415926535897932384626433832795; const long double EPS = 1; string a[3]; vector<int> zfunc(const string& a, const string& b) { string s = a + # + b; int n = (int)s.size(); vector<int> z(n); int l = 0, r = 0; for (int i = 1; i < n; i++) { if (i <= r) z[i] = min(z[i - l], r - i + 1); while (i + z[i] < n && s[z[i]] == s[i + z[i]]) z[i]++; if (i + z[i] > r) l = i, r = i + z[i] - 1; } return z; } string unite(const string& a, const string& b) { auto v = zfunc(b, a); string res = a; for (int i = (int)b.size() + 1; i <= (int)a.size() + (int)b.size(); i++) { if (v[i] >= (int)b.size()) return res; if (v[i] + i == (int)a.size() + (int)b.size() + 1) { res += b.substr(v[i], (int)b.size() - v[i]); return res; } } return a + b; } int get(const string& a, const string& b, const string& c) { string s = unite(a, b); s = unite(s, c); return (int)s.size(); } int main() { double start = clock(); cout << fixed << setprecision(20); ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> a[0] >> a[1] >> a[2]; vector<int> perm = {0, 1, 2}; int ans = INF; do { uin(ans, get(a[perm[0]], a[perm[1]], a[perm[2]])); } while (next_permutation(perm.begin(), perm.end())); cout << ans; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EINVN_TB_V
`define SKY130_FD_SC_HDLL__EINVN_TB_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__einvn.v"
module top();
// Inputs are registered
reg A;
reg TE_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Z;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
TE_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 TE_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 TE_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 TE_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 TE_B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 TE_B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hdll__einvn dut (.A(A), .TE_B(TE_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Z(Z));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EINVN_TB_V
|
#include <bits/stdc++.h> const int N = 2e4 + 42, M = 1e6 + 61, LN = 16; struct edge { int to, next, w; } e[M << 1]; int head[M], cnt = 1, nc; void addedge(int x, int y, int z) { if (!y) return; e[++cnt] = (edge){y, x[head], z}, x[head] = cnt; e[++cnt] = (edge){x, y[head], 0}, y[head] = cnt; } int fa[N][LN], pt[N][LN], dep[N], eid[N]; std::vector<std::pair<int, int> > g[N]; void dfs(int x, int p) { x[fa][0] = p, x[pt][0] = ++nc; addedge(nc, x, 1e9); for (int i = 1; i < LN; i++) { x[fa][i] = x[fa][i - 1][fa][i - 1], x[pt][i] = ++nc; addedge(nc, x[pt][i - 1], 1e9), addedge(nc, x[fa][i - 1][pt][i - 1], 1e9); } for (auto [nx, id] : x[g]) if (nx != p) nx[eid] = id, nx[dep] = x[dep] + 1, dfs(nx, x); } int lca(int x, int y) { if (x[dep] < y[dep]) std::swap(x, y); for (int i = LN - 1; i >= 0; i--) if (x[fa][i][dep] >= y[dep]) x = x[fa][i]; if (x == y) return x; for (int i = LN - 1; i >= 0; i--) if (x[fa][i] != y[fa][i]) x = x[fa][i], y = y[fa][i]; return x[fa][0]; } int get(int x, int k) { for (int i = 0; i < LN; i++) if ((k >> i) & 1) x = x[fa][i]; return x; } void link(int p, int x, int y) { if (x == y) return; int sub = x[dep] - y[dep]; int k = 31 - __builtin_clz(sub); addedge(p, x[pt][k], 1e9); addedge(p, get(x, sub - (1 << k))[pt][k], 1e9); } int lv[M], cur[M]; bool bfs(int s, int t) { memset(lv, 0, sizeof lv); std::queue<int> q; for (s[lv] = 1, q.push(s); !q.empty(); q.pop()) for (int x = q.front(), i = x[cur] = x[head], nx; i; i = e[i].next) if (!(nx = e[i].to)[lv] && e[i].w) nx[lv] = x[lv] + 1, q.push(nx); return t[lv]; } int dfs(int s, int t, int f) { if (s == t || !f) return f; int r = 0, tt; for (int &i = s[cur], nx; i; i = e[i].next) if ((nx = e[i].to)[lv] == s[lv] + 1 && (tt = dfs(nx, t, std::min(f, (int)e[i].w)))) { e[i].w -= tt, e[i ^ 1].w += tt, r += tt, f -= tt; if (!f) return r; } if (f) s[lv] = 0; return r; } int dinic(int s, int t) { int r = 0; while (bfs(s, t)) r += dfs(s, t, 1e9); return r; } bool vis[M]; void dfs2(int x) { x[vis] = true; for (int i = x[head], nx; i; i = e[i].next) if (e[i].w && !(nx = e[i].to)[vis]) dfs2(nx); } std::vector<int> v1, v2; int n, m, S, T, c_pt[N]; int main() { scanf( %d%d , &n, &m), nc = n; for (int i = 1, x, y; i < n; i++) { scanf( %d%d , &x, &y); x[g].push_back({y, i}); y[g].push_back({x, i}); } dep[1] = 1, dfs(1, 0); S = ++nc, T = ++nc; for (int i = 1; i <= n; i++) addedge(i, T, 1); for (int i = 1, x, y; i <= m; i++) { scanf( %d%d , &x, &y); int l = lca(x, y), p = ++nc; c_pt[i] = p; addedge(S, p, 1); link(p, x, l), link(p, y, l); } printf( %d n , dinic(S, T)); dfs2(S); for (int i = 1; i <= m; i++) if (!c_pt[i][vis]) v1.push_back(i); for (int i = 2; i <= n; i++) if (i[vis]) v2.push_back(eid[i]); printf( %lu , v1.size()); for (int i : v1) printf( %d , i); puts( ); printf( %lu , v2.size()); for (int i : v2) printf( %d , i); puts( ); } |
#include <bits/stdc++.h> using namespace std; int main() { int n, j = 0, i, s, t; cin >> n; int a[n + 1]; for (i = 1; i <= n; i++) cin >> a[i]; s = a[1] + 2 * n - 1; for (i = 1; i < n; i++) s += abs(a[i] - a[i + 1]); cout << s; return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02:15:59 05/09/2015
// Design Name: interrupt
// Module Name: /media/BELGELER/Workspaces/Xilinx/processor/test_interrupt.v
// Project Name: processor
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: interrupt
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_interrupt;
// Inputs
reg clock;
reg IEN_d;
reg IOF_d;
reg RTI_d;
reg branch_d;
reg IRQ;
reg [11:0] PC;
// Outputs
wire branch_ISR;
wire [11:0] ISR_adr;
// Instantiate the Unit Under Test (UUT)
interrupt uut (
.clock(clock),
.IEN_d(IEN_d),
.IOF_d(IOF_d),
.RTI_d(RTI_d),
.branch_d(branch_d),
.IRQ(IRQ),
.PC(PC),
.branch_ISR(branch_ISR),
.ISR_adr(ISR_adr)
);
initial begin
// Initialize Inputs
clock = 0;
IEN_d = 0;
IOF_d = 0;
RTI_d = 0;
branch_d = 0;
IRQ = 0;
PC = 35;
// Wait 100 ns for global reset to finish
//#100;
#1;
IEN_d = 1;
#1;
IEN_d = 0;
#5;
IRQ = 1;
end
always #1 clock = !clock;
endmodule
|
/*------------------------------------------------------------------------
Purpose
Synchronous FIFO extended for hiding last 2 bytes (crc16 field of the
usb data packet).
------------------------------------------------------------------------*/
module usb_fifo_rcv #(
parameter ADDR_WIDTH=4,
parameter WDATA_WIDTH=0,
parameter RDATA_WIDTH=0
)
(
input clk,
input rst0_async,
input rst0_sync,
input wr_en,
input[(1<<WDATA_WIDTH)-1:0] wr_data,
input rd_en,
output[(1<<RDATA_WIDTH)-1:0] rd_data,
output fifo_full,
output fifo_empty
);
localparam FIFO_LENGTH= 1<<ADDR_WIDTH;
reg[FIFO_LENGTH-1:0] mem;
reg wr_shift;
reg[ADDR_WIDTH:WDATA_WIDTH] wr_addr_no2bytes;
reg[ADDR_WIDTH:WDATA_WIDTH] wr_addr;
reg[ADDR_WIDTH:RDATA_WIDTH] rd_addr;
//CONTROL
generate
genvar k;
for(k=0; k<(1<<RDATA_WIDTH); k=k+1)
begin:loopk
assign rd_data[k]= mem[ (rd_addr[ADDR_WIDTH-1:RDATA_WIDTH]<<
RDATA_WIDTH)+k ];
end
if(WDATA_WIDTH>RDATA_WIDTH)
begin
assign fifo_full= wr_addr[ADDR_WIDTH]!=rd_addr[ADDR_WIDTH] &
wr_addr[ADDR_WIDTH-1:WDATA_WIDTH]==
rd_addr[ADDR_WIDTH-1:WDATA_WIDTH] ? 1'b1 : 1'b0;
assign fifo_empty= wr_addr_no2bytes[ADDR_WIDTH:WDATA_WIDTH]==
rd_addr[ADDR_WIDTH:WDATA_WIDTH] ? 1'b1 : 1'b0;
end
else
begin
assign fifo_full= wr_addr[ADDR_WIDTH]!=rd_addr[ADDR_WIDTH] &
wr_addr[ADDR_WIDTH-1:RDATA_WIDTH]==
rd_addr[ADDR_WIDTH-1:RDATA_WIDTH] ? 1'b1 : 1'b0;
assign fifo_empty= wr_addr_no2bytes[ADDR_WIDTH:RDATA_WIDTH]==
rd_addr[ADDR_WIDTH:RDATA_WIDTH] ? 1'b1 : 1'b0;
end
endgenerate
always @(posedge clk, negedge rst0_async)
begin
if(!rst0_async)
begin
wr_shift<=1'b0;
wr_addr_no2bytes<={(ADDR_WIDTH-WDATA_WIDTH+1){1'b0}};
wr_addr<={(ADDR_WIDTH-WDATA_WIDTH+1){1'b0}};
rd_addr<={(ADDR_WIDTH-RDATA_WIDTH+1){1'b0}};
end
else
begin
if(!rst0_sync)
begin
wr_shift<=1'b0;
wr_addr_no2bytes<={(ADDR_WIDTH-WDATA_WIDTH+1){1'b0}};
wr_addr<={(ADDR_WIDTH-WDATA_WIDTH+1){1'b0}};
rd_addr<={(ADDR_WIDTH-RDATA_WIDTH+1){1'b0}};
end
else
begin
wr_shift<= wr_en & !fifo_full & wr_addr[3:0]==4'd15 ? 1'b1 :
wr_shift;
wr_addr_no2bytes<= wr_shift & wr_en &
!fifo_full ? wr_addr_no2bytes+1'b1:
wr_addr_no2bytes;
wr_addr<= wr_en & !fifo_full ? wr_addr+1'b1 : wr_addr;
rd_addr<= rd_en & !fifo_empty ? rd_addr+1'b1 : rd_addr;
end
end
end
//BUFFER
generate
genvar i,j;
for(i=0; i<(FIFO_LENGTH>>WDATA_WIDTH); i=i+1)
begin:loopi
for(j=i*(1<<WDATA_WIDTH) ; j<(i+1)*(1<<WDATA_WIDTH) ; j=j+1)
begin:loopj
always @(posedge clk, negedge rst0_async)
if(!rst0_async)
mem[j]<=1'b0;
else
mem[j]<= wr_addr[ADDR_WIDTH-1:WDATA_WIDTH]==i &
!fifo_full & wr_en ? wr_data[j%(1<<WDATA_WIDTH)] :
mem[j];
end
end
endgenerate
endmodule
|
`include "assert.vh"
module unpack_i64_tb ();
reg [79:0] in;
wire [63:0] out;
wire [ 3:0] len;
unpack_signed #(.N(64)) DUT(in, out, len);
initial begin
$dumpfile("unpack_i64_tb.vcd");
$dumpvars(0, unpack_i64_tb);
// Ignore unset bits after value
in = 80'h01xxxxxxxxxxxxxxxxxx;
#1
`assert(out, 1);
`assert(len, 1);
// Decode negative numbers
in = 80'hffffffffffffffffff01;
#1
`assert(out, -1);
`assert(len, 10);
// Ignore data after value
in = 80'h808080800cbc0b000000;
// in = 80'h808080800cdeadbeef00;
#1
`assert(out, 32'hc0000000);
`assert(len, 5);
in = 80'h80808080800c00808080;
#1
`assert(out, 64'h6000000000);
`assert(len, 6);
in = 80'h8080808080800c008080;
#1
`assert(out, 64'h300000000000);
`assert(len, 7);
in = 80'h808080808080800c0080;
#1
`assert(out, 64'h18000000000000);
`assert(len, 8);
in = 80'h80808080808080800c00;
#1
`assert(out, 64'h0c00000000000000);
`assert(len, 9);
in = 80'h8080808080808080c001;
#1
`assert(out, 64'hc000000000000000);
`assert(len, 10);
$display("ok");
$finish;
end
endmodule // unpack_u64_tb
|
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