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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A221OI_PP_SYMBOL_V
`define SKY130_FD_SC_LS__A221OI_PP_SYMBOL_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a221oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
input C1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A221OI_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int x, y, x1, y1; cin >> x >> y >> x1 >> y1; int X = abs(x1 - x), Y = abs(y1 - y); cout << max(X, Y); return 0; } |
/**
* Author: Evan Lavelle, Riverside Machines Ltd.
* Version: 0.1 (2007-05-22)
* Licence: This code is released into the public domain.
*
* Test implicit Verilog-95 style ports. According to 12.3.2 of the 2005
* LRM:
*
* "The port reference for each port in the list of ports at the top of each
* module declaration can be one of the following:
*
* A simple identifier or escaped identifier
* A bit-select of a vector declared within the module
* A part-select of a vector declared within the module
* A concatenation of any of the above
*
* The port expression is optional because ports can be defined that do not
* connect to anything internal to the module."
*
* The expected output is:
*
* sum[ 1] = 0101010101100000
* sum[ 2] = 0101010101100000
* sum[ 3] = 0101010101100000
* sum[ 4] = 0101010101100000
* sum[ 5] = 0101010101100000
* sum[ 6] = 0101010101100000
* sum[ 7] = 0101010101100000
* sum[ 8] = 0101010101100000
* sum[ 9] = 0101010101100000
* sum[ 10] = 0101010101100000
* sum[ 11] = 0101010101100000
* sum[ 12] = 0101010101100000
* sum[ 13] = 0101010101100000
* sum[ 14] = 0101010101100000
* sum[ 15] = 0101010101100000
* sum[ 16] = 0101010101100000
* sum[ 17] = 0101010101100000
* sum[ 18] = 0101010101100000
* sum[ 19] = 0101010101100000
* sum[ 20] = 0101010101100000
* sum[ 21] = 0101010101100000
* sum[ 22] = 0101010101100000
* sum[ 23] = 0101010101100000
*
*/
module test;
reg [15:0] sum[23:1];
wire [7:0] data = 1;
wire dummy1, dummy2;
wire [15:0] wire5, wire9, wire13, wire17, wire21;
initial
main;
task main;
integer i;
begin
for(i=1; i<=23; i=i+1)
sum[i] = 'h555f;
#2;
sum[5] = wire5;
sum[9] = wire9;
sum[13] = wire13;
sum[17] = wire17;
sum[21] = wire21;
for(i=1; i<=23; i=i+1)
$display("sum[%d] = %b", i, sum[i]);
end
endtask
m1 m1();
m2 m2(dummy1, dummy2);
m3 m3(dummy1, , dummy2);
m4 m4(data);
m5 m5(data, wire5);
m6 m6(dummy1, data);
m7 m7(data, );
m8 m8 (data);
m9 m9 (data, wire9);
m10 m10( , data);
m11 m11(data, );
m12 m12(data[0]);
m13 m13(data[0], wire13);
m14 m14( , data[0]);
m15 m15(data[0], );
m16 m16(data);
m17 m17(data, wire17);
m18 m18(dummy1, data);
m19 m19(data, );
m20 m20(data);
m21 m21(data, wire21);
m22 m22(dummy1, data);
m23 m23(data, );
endmodule
/* ----------------------------------------------------------------------------
* the test modules
* ------------------------------------------------------------------------- */
// 95, no ports
module m1;
initial #1 test.sum[1] = test.sum[1] + test.data;
endmodule
// 95, two ports, but neither has an internal connection
module m2(,);
initial #1 test.sum[2] = test.sum[2] + test.data;
endmodule
// 95, three ports, but none have an internal connection
module m3(,,);
initial #1 test.sum[3] = test.sum[3] + test.data;
endmodule
/* ----------------------------------------------------------------------------
* 95, one and two ports, with implicit and simple identifiers
* ------------------------------------------------------------------------- */
// 95, one implicit port, simple identifier
module m4(a);
input a;
wire [7:0] a;
initial #1 test.sum[4] = test.sum[4] + a;
endmodule
// 95, two implicit ports, simple identifiers
module m5(a, b);
input a;
output b;
wire [7:0] a;
reg [15:0] b;
initial #1 b <= test.sum[5] + a;
endmodule
// 95, two ports; the first has no internal connection; the second is implicit/
// simple
module m6(,a);
input a;
wire [7:0] a;
initial #1 test.sum[6] = test.sum[6] + a;
endmodule
// 95, two ports; the second has no internal connection; the first is implicit/
// simple
module m7(a,);
input a;
wire [7:0] a;
initial #1 test.sum[7] = test.sum[7] + a;
endmodule
/* ----------------------------------------------------------------------------
* 95, one and two ports, with implicit and extended identifiers
* ------------------------------------------------------------------------- */
// 95, one implicit port, extended identifier
module m8(\a );
input \a ;
wire [7:0] \a ;
initial #1 test.sum[8] = test.sum[8] + \a ;
endmodule
// 95, two implicit ports, extended identifiers
module m9(\a , \b );
input \a ;
output \b ;
wire [7:0] \a ;
reg [15:0] \b ;
initial #1 \b = test.sum[9] + \a ;
endmodule
// 95, two ports; the first has no internal connection; the second is implicit/
// extended
module m10(,\a );
input \a ;
wire [7:0] \a ;
initial #1 test.sum[10] = test.sum[10] + \a ;
endmodule
// 95, two ports; the second has no internal connection; the first is implicit/
// extended
module m11(\a ,);
input \a ;
wire [7:0] \a ;
initial #1 test.sum[11] = test.sum[11] + \a ;
endmodule
/* ----------------------------------------------------------------------------
* 95, one and two ports, with implicit and vector bit-select ports
* ------------------------------------------------------------------------- */
// 95, one implicit port, vector bit-select
module m12(a[0]);
input a;
wire [7:0] a;
initial #1 test.sum[12] = test.sum[12] + {test.data[7:1], a[0]};
endmodule
// 95, two implicit ports, vector bit-selects. the output is actually a part
// select, since ISE core dumps on the assign below, and doing anything
// else in -95 is difficult
module m13(a[0], b[15:0]);
input a;
output b;
wire [7:0] a;
reg [31:0] b;
reg [15:0] temp;
// assign test.wire13[15:1] = temp[15:1]; // drives the rest of wire13
initial begin
#1 temp = test.sum[13] + {test.data[7:1], a[0]};
b = temp; // drives wire13[0]
end
endmodule
// 95, two ports; the first has no internal connection; the second is implicit/
// vector bit-select
module m14(,a[0]);
input [7:0] a;
initial #1 test.sum[14] = test.sum[14] + {test.data[7:1], a[0]};
endmodule
// 95, two ports; the second has no internal connection; the first is implicit/
// vector bit-select
module m15(a[0],);
input [7:0] a;
initial #1 test.sum[15] = test.sum[15] + {test.data[7:1], a[0]};
endmodule
/* ----------------------------------------------------------------------------
* 95, one and two ports, with implicit and vector part-select ports
* ------------------------------------------------------------------------- */
// 95, one implicit port, vector bit-select
module m16(a[7:0]);
input a;
wire [15:0] a;
initial #1 test.sum[16] = test.sum[16] + {8'h00, a[7:0]};
endmodule
// 95, two implicit ports, vector bit-selects
module m17(a[7:0], b[15:0]);
input a;
output b;
wire [7:0] a;
reg [31:0] b;
initial #1 b[15:0] = test.sum[17] + a;
endmodule
// 95, two ports; the first has no internal connection; the second is implicit/
// vector part-select
module m18(,a[7:0]);
input [15:0] a;
initial #1 test.sum[18] = test.sum[18] + {8'h00, a[7:0]};
endmodule
// 95, two ports; the second has no internal connection; the first is implicit/
// vector part-select
module m19(a[7:0],);
input [15:0] a;
// initial #1 test.sum[19] = test.sum[19] + a;
initial #1 test.sum[19] = test.sum[19] + {8'h00, a[7:0]};
endmodule
/* ----------------------------------------------------------------------------
* 95, one and two ports, with ports which are a concatenation of a bit select
* and a 3-bit part select
* ------------------------------------------------------------------------- */
// 95, one implicit port, concatenation
module m20({a[7], a[6:0]});
input a;
wire [15:0] a;
initial #1 test.sum[20] = test.sum[20] + {8'h00, a[7:0]};
endmodule
// 95, two implicit ports, concatenations
module m21({a[7], a[6:0]}, {b[15], b[14:0]});
input a;
output b;
wire [7:0] a;
reg [15:0] b;
initial #1 b = test.sum[21] + {8'h00, a[7:0]};
endmodule
// 95, two ports; the first has no internal connection; the second is implicit/
// concatenation
module m22(,{a[7], a[6:0]});
input [15:0] a;
initial #1 test.sum[22] = test.sum[22] + {8'h00, a[7:0]};
endmodule
// 95, two ports; the second has no internal connection; the first is implicit/
// concatenation. note that both modelsim and ISE set the entire sum, and not
// just the top 8 bits, to all x's for 'test.sum[23] = test.sum[23] + a'
module m23({a[7], a[6:0]},);
input a;
wire [15:0] a;
initial #1 test.sum[23] = test.sum[23] + a[7:0];
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon May 22 19:34:37 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_clk_wiz_0_0 -prefix
// system_clk_wiz_0_0_ system_clk_wiz_0_0_sim_netlist.v
// Design : system_clk_wiz_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* NotValidForBitStream *)
module system_clk_wiz_0_0
(clk_out1,
locked,
clk_in1);
output clk_out1;
output locked;
input clk_in1;
(* IBUF_LOW_PWR *) wire clk_in1;
wire clk_out1;
wire locked;
system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz inst
(.clk_in1(clk_in1),
.clk_out1(clk_out1),
.locked(locked));
endmodule
module system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz
(clk_out1,
locked,
clk_in1);
output clk_out1;
output locked;
input clk_in1;
wire clk_in1;
wire clk_in1_system_clk_wiz_0_0;
wire clk_out1;
wire clk_out1_system_clk_wiz_0_0;
wire clkfbout_buf_system_clk_wiz_0_0;
wire clkfbout_system_clk_wiz_0_0;
wire locked;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_system_clk_wiz_0_0),
.O(clkfbout_buf_system_clk_wiz_0_0));
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk_in1),
.O(clk_in1_system_clk_wiz_0_0));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_out1_system_clk_wiz_0_0),
.O(clk_out1));
(* BOX_TYPE = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(44.625000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(75.000000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(5),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_system_clk_wiz_0_0),
.CLKFBOUT(clkfbout_system_clk_wiz_0_0),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_in1_system_clk_wiz_0_0),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_out1_system_clk_wiz_0_0),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(locked),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 15; const int LL = 1e9 + 15; const int SSS = 1e6 + 15; int dx[10] = {0, 1, -1, 1, -1, 2, -2, 2, -2}; int dy[10] = {0, 2, 2, -1, -1, 1, 1, -1, -1}; int n, ii, a[5010], ans[5010], mx, st[5010]; int main() { cin >> n; for (int i = 1; i <= n; ++i) { scanf( %d , &a[i]); mx = 0; ii = 0; for (int j = 1; j <= n; ++j) st[j] = 0; for (int j = i; j >= 1; --j) { ++st[a[j]]; if (st[a[j]] > mx || (st[a[j]] == mx && ii > a[j])) { mx = st[a[j]]; ii = a[j]; } ++ans[ii]; } } for (int i = 1; i <= n; ++i) printf( %d , ans[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long n, k; cin >> n >> k; long long r = (n * (n - 1)); r = (r >> 1); if (r > k) { for (long long i = 0; i < n; i++) { cout << 0 << << i << n ; } return 0; } cout << no solution n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; const long long int INF = 1e12; int n, k; int memo[101][101][101]; int solve(string &str, int i, int N, int _max) { _max = max(N, _max); int &a = memo[i][N][_max]; if (a != -1) return a; if (i == n) return a = (_max == k); if (str[i] != N ) { bool temp1 = solve(str, i + 1, 0, _max); if (str[i] == Y || temp1) return a = temp1; } return a = solve(str, i + 1, N + 1, _max); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); memset(memo, -1, sizeof(memo)); cin >> n >> k; string str; cin >> str; cout << (solve(str, 0, 0, 0) ? YES : NO ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n; cin >> n; vector<long long> p(n); vector<int> a(n), b(n); for (int i = 0; i < n; ++i) cin >> p[i]; for (int i = 0; i < n; ++i) cin >> a[i]; for (int i = 0; i < n; ++i) cin >> b[i]; vector<pair<long long, int>> one, two, three; for (int i = 0; i < n; ++i) { if (a[i] == 1 || b[i] == 1) one.push_back({p[i], i}); if (a[i] == 2 || b[i] == 2) two.push_back({p[i], i}); if (a[i] == 3 || b[i] == 3) three.push_back({p[i], i}); } sort(one.begin(), one.end()); sort(two.begin(), two.end()); sort(three.begin(), three.end()); vector<bool> vis(n, false); int p1 = 0, p2 = 0, p3 = 0; int si1 = one.size(), si2 = two.size(), si3 = three.size(); int m, c; cin >> m; for (int i = 0; i < m; ++i) { cin >> c; if (c == 1) { bool fl = false; for (int start = p1; start < si1; start++) { if (vis[one[start].second] == false) { cout << one[start].first << ; vis[one[start].second] = true; fl = true; p1 = start + 1; break; } } if (!fl) cout << -1 ; } else if (c == 2) { bool fl = false; for (int start = p2; start < si2; start++) { if (vis[two[start].second] == false) { cout << two[start].first << ; vis[two[start].second] = true; fl = true; p2 = start + 1; break; } } if (!fl) cout << -1 ; } else { bool fl = false; for (int start = p3; start < si3; start++) { if (vis[three[start].second] == false) { cout << three[start].first << ; vis[three[start].second] = true; fl = true; p3 = start + 1; break; } } if (!fl) cout << -1 ; } } } |
`timescale 1ns / 1ps
//
// KIA registers
//
`define KQSTAT 0
`define KQDATA 1
module KIA(
input CLK_I,
input RES_I,
input [0:0] ADR_I,
input WE_I,
input CYC_I,
input STB_I,
output ACK_O,
output [7:0] DAT_O,
input D_I,
input C_I
);
reg [7:0] queue[0:15];
reg [3:0] rp;
reg [3:0] wp;
wire [3:0] next_wp = wp+1;
wire queue_full = (next_wp == rp);
wire queue_empty = (rp == wp);
reg ack;
assign ACK_O = ack;
// STORY 0000
// We want the KIA to respond to bus transactions as close to a single cycle as
// possible. Since we're using fully synchronous bus logic, that actually means
// _two_ cycle turn-around. The CPU sets up the bus during cycle N, and we assert
// ACK_O during cycle N+1. The CPU would then commence the next cycle at N+2.
always @(posedge CLK_I) begin
if(~RES_I) begin
ack <= CYC_I & STB_I;
end else begin
ack <= 0;
end
end
// STORY 0000,0010,0020,0050
// When reading the status register, we want to put the contents of the queue
// status register on the data bus. The queue status register has the following
// bit-level mapping:
// Bit 0 0=queue is not empty; at least one byte is waiting to be read.
// 1=queue is empty.
//
// Bit 1 0=queue is not (yet) full; room for at least one byte remains.
// 1=queue is full. Any additional data coming from the peripheral
// will be dropped.
//
// When reading the head of the queue, we want a copy of the current data byte,
// if any.
//
// STORY 0030, 0050
// When the CPU writes to the keyboard queue head register, it pops the queue. We ignore the value
// actually written. If the queue is already empty, take no action.
wire kqstat_addressed = (ADR_I == `KQSTAT) & ack & ~WE_I;
wire kqdata_addressed = (ADR_I == `KQDATA) & ack & ~WE_I;
wire kqpop_addressed = (ADR_I == `KQDATA) & ack & WE_I & ~queue_empty;
wire [7:0] kqstat_value = {6'h00, queue_full, queue_empty};
wire [7:0] kqdata_value = queue[rp];
wire [3:0] next_rp = RES_I ? 4'h0 : (kqpop_addressed ? rp+1 : rp);
assign DAT_O = ({8{kqstat_addressed}} & kqstat_value) | ({8{kqdata_addressed}} & kqdata_value);
always @(posedge CLK_I) begin
rp <= next_rp;
end
// STORY 0010
// When receiving a character code from the PS/2 port, we want to shift it into
// a shift register for later processing. We know that the character code is
// fully received when we've received 11 bits, including a start and stop bit.
// We ignore parity bit.
//
// We synchronize the PS/2 clock against the system clock with cur_C. Without this
// synchrony, we end up missing clocking events, thus dropping bits from the port,
// thus creating a framing error. prev_C is used to detect negative edges on the
// PS/2 clock signal.
reg [10:0] sr;
reg cur_C;
reg prev_C;
reg [3:0] bits_received;
wire ps2clk_edge = ~cur_C && prev_C;
wire waiting_for_start_bit = bits_received == 0;
wire waiting_for_stop_bit = bits_received == 10;
wire is_start_bit = D_I == 0;
wire is_stop_bit = D_I == 1;
always @(posedge CLK_I) begin
if(~RES_I) begin
cur_C <= C_I;
if(ps2clk_edge && waiting_for_start_bit && is_start_bit) begin
sr <= {D_I, sr[10:1]};
bits_received <= bits_received+1;
end
if(ps2clk_edge && ~waiting_for_stop_bit && ~waiting_for_start_bit) begin
sr <= {D_I, sr[10:1]};
bits_received <= bits_received+1;
end
if(ps2clk_edge && waiting_for_stop_bit && is_stop_bit && ~queue_full) begin
queue[wp] <= sr[9:2];
wp <= next_wp;
bits_received <= 0;
end
if(ps2clk_edge && waiting_for_stop_bit && is_stop_bit && queue_full) begin
bits_received <= 0;
end
prev_C <= cur_C;
end else begin
sr <= 11'h7FF;
prev_C <= 1;
cur_C <= 1;
bits_received <= 0;
wp <= 0;
end
end
// STORY 0030,0040,0050
// We need a queue of bytes received to hold unread data. The queue is 16-elements deep. Thus,
// we need 4-bit addresses into the queue memory.
//
// The queue is considered full when writing a new byte threatens to overwrite the byte addressed
// by the read pointer.
//
// Likewise, the queue is considered empty when the read pointer matches the write pointer.
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O211AI_BEHAVIORAL_V
`define SKY130_FD_SC_HS__O211AI_BEHAVIORAL_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o211ai (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
// Local signals
wire C1 or0_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , C1, or0_out, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O211AI_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; int ask(int c, int d) { cout << ? << c << << d << endl; fflush(stdout); int x; cin >> x; return x; } void go(int a, int b) { cout << ! << a << << b << endl; fflush(stdout); exit(0); } bool same[50]; signed main() { int type = ask(0, 0); if (type == 0) { int ans = 0; for (int i = 29; i >= 0; i--) { int q = ask((1 << i), 0); if (q == 0) { continue; } if (q == 1) { ans += 0; } else { ans += (1 << i); } } go(ans, ans); } bool A, B; if (type == 1) { A = 1; B = 0; } else { A = 0; B = 1; } int ansA = 0, ansB = 0; for (int i = 29; i >= 0; i--) { int q = ask(ansA + (1 << i), ansB + (1 << i)); if (q == 0) { for (int pos = i; pos >= 0; pos--) { same[pos] = 1; } break; } if (A == 1) { if (q == 1) { same[i] = 1; } else { ansA += (1 << i); ansB += 0; int qq = ask(ansA, ansB); if (qq == 1) A = 1, B = 0; if (qq == -1) A = 0, B = 1; } } else { if (q == -1) { same[i] = 1; } else { ansA += 0; ansB += (1 << i); int qq = ask(ansA, ansB); if (qq == 1) A = 1, B = 0; if (qq == -1) A = 0, B = 1; } } } for (int i = 29; i >= 0; i--) { if (same[i]) { int q = ask(ansA + (1 << i), ansB); if (q == 0) { continue; } if (q == 1) { ansA += 0; ansB += 0; } else { ansA += (1 << i); ansB += (1 << i); } } } go(ansA, ansB); } |
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_8_b2s_rd_cmd_fsm.v
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_8_b2s_rd_cmd_fsm (
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
output wire s_arready ,
input wire s_arvalid ,
input wire [7:0] s_arlen ,
output wire m_arvalid ,
input wire m_arready ,
// signal to increment to the next mc transaction
output wire next ,
// signal to the fsm there is another transaction required
input wire next_pending ,
// Write Data portion has completed or Read FIFO has a slot available (not
// full)
input wire data_ready ,
// status signal for w_channel when command is written.
output wire a_push ,
output wire r_push
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// States
localparam SM_IDLE = 2'b00;
localparam SM_CMD_EN = 2'b01;
localparam SM_CMD_ACCEPTED = 2'b10;
localparam SM_DONE = 2'b11;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg [1:0] state;
// synthesis attribute MAX_FANOUT of state is 20;
reg [1:0] state_r1;
reg [1:0] next_state;
reg [7:0] s_arlen_r;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
// register for timing
always @(posedge clk) begin
if (reset) begin
state <= SM_IDLE;
state_r1 <= SM_IDLE;
s_arlen_r <= 0;
end else begin
state <= next_state;
state_r1 <= state;
s_arlen_r <= s_arlen;
end
end
// Next state transitions.
always @( * ) begin
next_state = state;
case (state)
SM_IDLE:
if (s_arvalid & data_ready) begin
next_state = SM_CMD_EN;
end else begin
next_state = state;
end
SM_CMD_EN:
///////////////////////////////////////////////////////////////////
// Drive m_arvalid downstream in this state
///////////////////////////////////////////////////////////////////
//If there is no fifo space
if (~data_ready & m_arready & next_pending) begin
///////////////////////////////////////////////////////////////////
//There is more to do, wait until data space is available drop valid
next_state = SM_CMD_ACCEPTED;
end else if (m_arready & ~next_pending)begin
next_state = SM_DONE;
end else if (m_arready & next_pending) begin
next_state = SM_CMD_EN;
end else begin
next_state = state;
end
SM_CMD_ACCEPTED:
if (data_ready) begin
next_state = SM_CMD_EN;
end else begin
next_state = state;
end
SM_DONE:
next_state = SM_IDLE;
default:
next_state = SM_IDLE;
endcase
end
// Assign outputs based on current state.
assign m_arvalid = (state == SM_CMD_EN);
assign next = m_arready && (state == SM_CMD_EN);
assign r_push = next;
assign a_push = (state == SM_IDLE);
assign s_arready = ((state == SM_CMD_EN) || (state == SM_DONE)) && (next_state == SM_IDLE);
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int tc; cin >> tc; int z; for (int t = 1; t <= tc; t++) { cin >> z; int a, s, d = 0; s = 0; a = 0; int x; for (int q = 1; q <= z; q++) { cin >> x; if (x % 3 == 0) a++; else if (x % 3 == 1) s++; else d++; } int total = a + (min(s, d)); int temp = min(s, d); s -= temp; d -= temp; total += (s / 3); total += (d / 3); cout << total << endl; } } |
#include <bits/stdc++.h> using namespace std; const int INF = INT_MAX; const int N = 2 * 1e3 + 10; const long double eps = 1e-9; const int mod = 998244353; char a[N][N]; int d[N][N], v[N][N], n, m; bool used[N][N]; void nxt(char c, int &x, int &y) { if (c == U ) --x; else if (c == D ) ++x; else if (c == R ) ++y; else --y; return; } int cx, cy; void fillcycle() { int x = cx, y = cy, cnt = 1; nxt(a[x][y], x, y); while (!(x == cx && y == cy)) { ++cnt; nxt(a[x][y], x, y); } x = cx, y = cy; d[x][y] = cnt; v[x][y] = 2; nxt(a[x][y], x, y); while (!(x == cx && y == cy)) { v[x][y] = 2; d[x][y] = cnt; nxt(a[x][y], x, y); } return; } void cycle(int x, int y) { while (!(x <= 0 || y <= 0 || x > n || y > m) && !used[x][y]) { v[x][y] = 0; used[x][y] = true; nxt(a[x][y], x, y); } if (x <= 0 || y <= 0 || x > n || y > m) return; if (v[x][y] != 0) return; cx = x; cy = y; fillcycle(); return; } void gg(int x, int y) { while (x > 0 && y > 0 && x <= n && y <= m && v[x][y] == 0) { v[x][y] = 1; nxt(a[x][y], x, y); } return; } void dfs(int x, int y) { int tx = x, ty = y; nxt(a[x][y], tx, ty); stack<pair<int, int> > vc; vc.push({x, y}); int c = 1; while (!(tx <= 0 || ty <= 0 || x > n || y > m) && d[tx][ty] == -1) { vc.push({tx, ty}); nxt(a[tx][ty], tx, ty); } if (tx <= 0 || ty <= 0 || x > n || y > m) c = 1; else c = d[tx][ty] + 1; while (!vc.empty()) { tx = vc.top().first; ty = vc.top().second; vc.pop(); d[tx][ty] = c; ++c; } return; } void solve() { cin >> n >> m; for (int i = 0; i <= n + 1; ++i) { fill(d[i], d[i] + m + 1, -1); fill(used[i], used[i] + m + 1, false); fill(v[i], v[i] + m + 1, -1); if (i > 0 && i <= n) { for (int j = 1; j <= m; ++j) cin >> a[i][j]; } } for (int i = 0; i <= n + 1; ++i) d[i][0] = d[i][m + 1] = 0; for (int i = 0; i <= m + 1; ++i) d[0][i] = d[n + 1][i] = 0; for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { if (!used[i][j]) { cycle(i, j); gg(i, j); } } } for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { if (d[i][j] == -1) dfs(i, j); } } int x = 1, y = 1, ans = -2; for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { if (ans < d[i][j]) ans = d[i][j], x = i, y = j; } } cout << x << << y << << ans << n ; return; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t = 1; cin >> t; while (t--) solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const long long LINF = 0x3f3f3f3f3f3f3f3fll; int main() { ios_base::sync_with_stdio(0); cin.tie(0); long long n, x, y; cin >> n >> x >> y; long long a1 = y - n + 1; if (a1 <= 0 or a1 * a1 + n - 1 < x) return cout << -1 << n , 0; cout << a1 << n ; for (int i = 0; i < n - 1; i++) cout << 1 << n ; exit(0); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_12_V
`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_12_V
/**
* lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
* rail.
*
* Verilog wrapper for lpflow_decapkapwr with size of 12 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_decapkapwr.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_decapkapwr_12 (
VPWR ,
KAPWR,
VGND ,
VPB ,
VNB
);
input VPWR ;
input KAPWR;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__lpflow_decapkapwr base (
.VPWR(VPWR),
.KAPWR(KAPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_decapkapwr_12 ();
// Voltage supply signals
supply1 VPWR ;
supply1 KAPWR;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__lpflow_decapkapwr base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_12_V
|
//------------------------------------------------------------------------------
// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//------------------------------------------------------------------------------
// ***************************
// * DO NOT MODIFY THIS FILE *
// ***************************
`timescale 1ps/1ps
module gtwizard_ultrascale_v1_7_1_reset_synchronizer # (
parameter FREQUENCY = 512
)(
input wire clk_in,
input wire rst_in,
output wire rst_out
);
// Use 5 flip-flops as a single synchronizer, and tag each declaration with the appropriate synthesis attribute to
// enable clustering. Each flip-flop in the synchronizer is asynchronously reset so that the downstream logic is also
// asynchronously reset but encounters no reset assertion latency. The removal of reset is synchronous, so that the
// downstream logic is also removed from reset synchronously. This module is designed for active-high reset use.
(* ASYNC_REG = "TRUE" *) reg rst_in_meta = 1'b0;
(* ASYNC_REG = "TRUE" *) reg rst_in_sync1 = 1'b0;
(* ASYNC_REG = "TRUE" *) reg rst_in_sync2 = 1'b0;
(* ASYNC_REG = "TRUE" *) reg rst_in_sync3 = 1'b0;
reg rst_in_out = 1'b0;
always @(posedge clk_in, posedge rst_in) begin
if (rst_in) begin
rst_in_meta <= 1'b1;
rst_in_sync1 <= 1'b1;
rst_in_sync2 <= 1'b1;
rst_in_sync3 <= 1'b1;
rst_in_out <= 1'b1;
end
else begin
rst_in_meta <= 1'b0;
rst_in_sync1 <= rst_in_meta;
rst_in_sync2 <= rst_in_sync1;
rst_in_sync3 <= rst_in_sync2;
rst_in_out <= rst_in_sync3;
end
end
assign rst_out = rst_in_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int test; cin >> test; while (test--) { int n, m; cin >> n >> m; int array[n]; for (int i = 0; i < n; i++) cin >> array[i]; int sum = 0; for (int i = 0; i < n; i++) { sum += array[i]; } double average = sum / double(n); double value = m / double(n); if (value <= average) cout << m << endl; else cout << average * n << endl; } } |
`timescale 1ns / 1ps
//**********************************************************************
// File: button_hold.v
// Module:button_hold
// by Robin zhang
//**********************************************************************
module button_hold(
rst,clk,out_status,pin_select,press_done
);
input rst;
input clk;
input [15:0] pin_select;
output [25:0] out_status;
output press_done;
reg [25:0] out_status;
reg [31:0] counter;
reg pull_done;
reg press_done;
always @(posedge clk or negedge rst)begin
if(!rst)
counter <= 'h0;
else
counter <= ((counter < 32'hFFFFFFFF) && pin_select != 'h0) ? (counter + 1'b1) : 'h0;
end
always@(posedge clk or negedge rst)begin
if(!rst)
out_status <= 26'h3ffffff;
else begin
case(pin_select[7:0])
8'h41 : out_status[0] <= pull_done;
8'h42 : out_status[1] <= pull_done;
8'h43 : out_status[2] <= pull_done;
8'h44 : out_status[3] <= pull_done;
8'h45 : out_status[4] <= pull_done;
8'h46 : out_status[5] <= pull_done;
8'h47 : out_status[6] <= pull_done;
8'h48 : out_status[7] <= pull_done;
8'h49 : out_status[8] <= pull_done;
8'h4a : out_status[9] <= pull_done;
8'h4b : out_status[10] <= pull_done;
8'h4c : out_status[11] <= pull_done;
8'h4d : out_status[12] <= pull_done;
8'h4e : out_status[13] <= pull_done;
8'h4f : out_status[14] <= pull_done;
8'h50 : out_status[15] <= pull_done;
8'h51 : out_status[16] <= pull_done;
8'h52 : out_status[17] <= pull_done;
8'h53 : out_status[18] <= pull_done;
8'h54 : out_status[19] <= pull_done;
8'h55 : out_status[20] <= pull_done;
8'h56 : out_status[21] <= pull_done;
8'h57 : out_status[22] <= pull_done;
8'h58 : out_status[23] <= pull_done;
8'h59 : out_status[24] <= pull_done;
8'h5a : out_status[25] <= pull_done;
default : out_status <= 26'h3ffffff;
endcase
end
end
always @(posedge clk or negedge rst)begin
if(!rst)
pull_done <= 1'bz;
else begin
pull_done <= ((pin_select[15:8] == 8'h53) && (counter < 'd3500000)) ? 1'b0
: ((pin_select[15:8] == 8'h4c) && (counter < 'd100000000)) ? 1'b0
: ((pin_select[15:8] == 8'h56) && (counter < 'd500000000)) ? 1'b0
: (pin_select[15:8] == 8'h44) ? 1'b0
: (pin_select[15:8] == 8'h48) ? 1'b1 : 1'bz;
end
end
always @(posedge clk or negedge rst)begin
if(!rst)
press_done <= 1'b0;
else
press_done <= ((pin_select[15:8] == 8'h53) && (counter > 'd3500000)) ? 1'b1
: ((pin_select[15:8] == 8'h4c) && (counter > 'd100000000)) ? 1'b1
: ((pin_select[15:8] == 8'h56) && (counter > 'd500000000)) ? 1'b1
: (pin_select[15:8] == 8'h44) ? 1'b1
: (pin_select[15:8] == 8'h48) ? 1'b1 : 1'b0;
end
endmodule |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:64777216 ) using namespace std; template <class T> inline T sqr(T x) { return x * x; } const double pi = acos(-1.0), eps = 1e-9; const int INF = 1000 * 1000 * 1000, MAXN = 1000005, MOD = 1000000007; const long long INFL = 1000000000000000000; long long n, m, cnt[MAXN][26]; string x, y; void prepare(string s) { if ((int)s.size() != 0) { freopen((s + .in ).c_str(), r , stdin); freopen((s + .out ).c_str(), w , stdout); } } long long gcd(long long a, long long b) { return (b) ? gcd(b, a % b) : a; } long long lca(long long a, long long b) { return a / gcd(a, b) * b; } void get_data() { cin >> n >> m >> x >> y; } void solve() { long long L = lca((int)x.size(), (int)y.size()); long long g = gcd((int)x.size(), (int)y.size()); long long ans = L; for (int i = 0; i < (int)y.size(); ++i) cnt[i % g][y[i] - a ]++; for (int j = 0; j < (int)x.size(); ++j) ans -= cnt[j % g][x[j] - a ]; cout << ans * (n * (int)x.size() / L); } int main() { prepare( ); get_data(); solve(); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__OR3_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__OR3_BEHAVIORAL_V
/**
* or3: 3-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__or3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A, C );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__OR3_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; int n, m, G[1005][1005], ans = 1000000000; char str[1005][1005]; bool vis[1005][1005]; int dfs(int x, int y, int wx, int wy) { vis[x][y] = true; if ((G[x + wx - 1][y + wy] - G[x - 1][y + wy] - G[x + wx - 1][y + 1 - 1] + G[x - 1][y + 1 - 1]) == wx * wy) return wx + dfs(x, y + 1, wx, wy); if ((G[x + wx][y + wy - 1] - G[x + 1 - 1][y + wy - 1] - G[x + wx][y - 1] + G[x + 1 - 1][y - 1]) == wx * wy) return wy + dfs(x + 1, y, wx, wy); return 0; } int main() { memset(vis, false, sizeof(vis)); scanf( %d%d n , &n, &m); int flag = 0, px, py; for (int i = 1; i <= n; i++) scanf( %s , str[i] + 1); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { if (str[i][j] == X ) { if (!flag) { flag = 1; px = i; py = j; } G[i][j] = G[i - 1][j] + G[i][j - 1] - G[i - 1][j - 1] + 1; } else G[i][j] = G[i - 1][j] + G[i][j - 1] - G[i - 1][j - 1]; } int tmp, wx, wy; for (tmp = px; str[tmp][py] == X ; tmp++) ; wx = tmp - px; for (int i = py; str[px][i] == X ; i++) if (dfs(px, py, wx, i - py + 1) + wx * (i - py + 1) == G[n][m]) ans = min(ans, wx * (i - py + 1)); for (tmp = py; str[px][tmp] == X ; tmp++) ; wy = tmp - py; for (int i = px; str[i][py] == X ; i++) if (dfs(px, py, i - px + 1, wy) + (i - px + 1) * wy == G[n][m]) ans = min(ans, (i - px + 1) * wy); if (ans <= n * m) printf( %d n , ans); else printf( -1 n ); return 0; } |
// megafunction wizard: %CRC Compiler v10.1%
// GENERATION: XML
// ============================================================
// Megafunction Name(s):
// altpcierd_rx_ecrc_128_altcrc
// ============================================================
// Generated by CRC Compiler 10.1 [Altera, IP Toolbench 1.3.0 Build 95]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2010 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
module altpcierd_rx_ecrc_128 (
clk,
data,
datavalid,
empty,
endofpacket,
reset_n,
startofpacket,
crcbad,
crcvalid);
input clk;
input [127:0] data;
input datavalid;
input [3:0] empty;
input endofpacket;
input reset_n;
input startofpacket;
output crcbad;
output crcvalid;
altpcierd_rx_ecrc_128_altcrc altpcierd_rx_ecrc_128_altcrc_inst(
.clk(clk),
.data(data),
.datavalid(datavalid),
.empty(empty),
.endofpacket(endofpacket),
.reset_n(reset_n),
.startofpacket(startofpacket),
.crcbad(crcbad),
.crcvalid(crcvalid));
endmodule
// =========================================================
// CRC Compiler Wizard Data
// ===============================
// DO NOT EDIT FOLLOWING DATA
// @Altera, IP Toolbench@
// Warning: If you modify this section, CRC Compiler Wizard may not be able to reproduce your chosen configuration.
//
// Retrieval info: <?xml version="1.0"?>
// Retrieval info: <MEGACORE title="CRC Compiler" version="10.1" build="95" iptb_version="1.3.0 Build 95" format_version="120" >
// Retrieval info: <NETLIST_SECTION class="altera.ipbu.flowbase.netlist.model.MVCModel" active_core="altpcierd_rx_ecrc_128_altcrc" >
// Retrieval info: <STATIC_SECTION>
// Retrieval info: <PRIVATES>
// Retrieval info: <NAMESPACE name = "parameterization">
// Retrieval info: <PRIVATE name = "p_wordsize" value="128" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_crccheck" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_inbuff" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_outbuff" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_lanes" value="16" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_fwdpipe" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_initvalue" value="0xFFFFFFFF" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_bckpipe" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_generator" value="1_0000_0100_1100_0001_0001_1101_1011_0111" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_lsb" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_symbol_lsb" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_true_output" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_reverse" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_start_offset" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_channels" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "g_optimize" value="speed" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "g_use_all_ones" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "g_datapath" value="128 bits" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "g_genname" value="CRC-32" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "g_negate_checksum" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_cbx_hdl_language" value="verilog" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "simgen_enable">
// Retrieval info: <PRIVATE name = "language" value="VERILOG" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "enabled" value="1" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "greybox">
// Retrieval info: <PRIVATE name = "gb_enabled" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "filename" value="altpcierd_rx_ecrc_128_syn.v" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "simgen">
// Retrieval info: <PRIVATE name = "filename" value="altpcierd_rx_ecrc_128.vo" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "serializer"/>
// Retrieval info: <NAMESPACE name = "settings">
// Retrieval info: <PRIVATE name = "DEVICE" value="AUTO" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "FAMILY" value="Stratix IV" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "quartus_settings">
// Retrieval info: <PRIVATE name = "DEVICE" value="AUTO" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "FAMILY" value="Stratix IV" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: </PRIVATES>
// Retrieval info: <FILES/>
// Retrieval info: <PORTS/>
// Retrieval info: <LIBRARIES/>
// Retrieval info: </STATIC_SECTION>
// Retrieval info: </NETLIST_SECTION>
// Retrieval info: </MEGACORE>
// =========================================================
// RELATED_FILES: altpcierd_rx_ecrc_128.v, altpcierd_rx_ecrc_128_altcrc.v;
// IPFS_FILES: altpcierd_rx_ecrc_128.vo;
// =========================================================
|
`timescale 1ns/1ps
module SensorFSM #(
parameter DataWidth = 8
) (
input Reset_n_i,
input Clk_i,
// top level
input Enable_i,
output reg CpuIntr_o,
output [2*DataWidth-1:0] SensorValue_o,
// to/from Measure-FSM
output reg MeasureFSM_Start_o,
input MeasureFSM_Done_i,
input [DataWidth-1:0] MeasureFSM_Byte0_i,
input [DataWidth-1:0] MeasureFSM_Byte1_i,
// parameters
input [2*DataWidth-1:0] ParamThreshold_i,
input [4*DataWidth-1:0] ParamCounterPreset_i
);
// Sensor FSM
localparam stDisabled = 2'b00;
localparam stIdle = 2'b01;
localparam stXfer = 2'b10;
localparam stNotify = 2'b11;
reg [1:0] SensorFSM_State;
reg [1:0] SensorFSM_NextState;
wire SensorFSM_TimerOvfl;
reg SensorFSM_TimerPreset;
reg SensorFSM_TimerEnable;
wire SensorFSM_DiffTooLarge;
reg SensorFSM_StoreNewValue;
/////////////////////////////////////////////////////////////////////////////
// Word Arithmetic
// interconnecting signals
wire [2*DataWidth-1:0] SensorValue;
reg [2*DataWidth-1:0] Word0;
wire [2*DataWidth-1:0] AbsDiffResult;
/////////////////////////////////////////////////////////////////////////////
// FSM //////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
SensorFSM_State <= stDisabled;
end
else
begin
SensorFSM_State <= SensorFSM_NextState;
end
end
always @(SensorFSM_State, Enable_i, SensorFSM_TimerOvfl, MeasureFSM_Done_i, SensorFSM_DiffTooLarge)
begin // process SensorFSM_CombProc
SensorFSM_NextState = SensorFSM_State;
// control signal default values
SensorFSM_TimerPreset = 1'b0;
SensorFSM_TimerEnable = 1'b0;
MeasureFSM_Start_o = 1'b0;
SensorFSM_StoreNewValue = 1'b0;
CpuIntr_o = 1'b0;
// next state and output logic
case (SensorFSM_State)
stDisabled: begin
if (Enable_i == 1'b1)
begin
SensorFSM_TimerPreset = 1'b1;
SensorFSM_NextState = stIdle;
end
end
stIdle: begin
if (Enable_i == 1'b0)
begin
SensorFSM_NextState = stDisabled;
end
else
if (SensorFSM_TimerOvfl == 1'b1)
begin
SensorFSM_NextState = stXfer;
MeasureFSM_Start_o = 1'b1;
end
else
begin
SensorFSM_TimerEnable = 1'b1; // timer running
end
end
stXfer: begin
if (MeasureFSM_Done_i == 1'b1)
begin
SensorFSM_TimerPreset = 1'b1;
if (SensorFSM_DiffTooLarge == 1'b1)
begin
SensorFSM_NextState = stNotify;
SensorFSM_StoreNewValue = 1'b1; // store new value
end
else
begin
SensorFSM_NextState = stIdle;
end
end
end
stNotify: begin
SensorFSM_TimerEnable = 1'b1; // timer running
SensorFSM_NextState = stIdle;
CpuIntr_o = 1'b1; // notify CPU
end
default: begin
end
endcase
end
/////////////////////////////////////////////////////////////////////////////
// Word Arithmetic //////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
reg [4*DataWidth-1:0] SensorFSM_Timer;
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
SensorFSM_Timer <= 32'd0;
end
else
begin
if (SensorFSM_TimerPreset)
begin
SensorFSM_Timer <= ParamCounterPreset_i;
end
else if (SensorFSM_TimerEnable)
begin
SensorFSM_Timer <= SensorFSM_Timer - 1'b1;
end
end
end
assign SensorFSM_TimerOvfl = (SensorFSM_Timer == 0) ? 1'b1 : 1'b0;
assign SensorValue = {MeasureFSM_Byte1_i, MeasureFSM_Byte0_i};
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
Word0 <= 16'd0;
end
else
begin
if (SensorFSM_StoreNewValue)
begin
Word0 <= SensorValue;
end
end
end
wire [2*DataWidth : 0] DiffAB;
wire [2*DataWidth-1 : 0] DiffBA;
assign DiffAB = {1'b0, SensorValue} - {1'b0, Word0};
assign DiffBA = Word0 - SensorValue;
assign AbsDiffResult = DiffAB[2*DataWidth] ? DiffBA : DiffAB[2*DataWidth-1 : 0];
assign SensorFSM_DiffTooLarge = (AbsDiffResult > ParamThreshold_i) ? 1'b1 : 1'b0;
assign SensorValue_o = Word0;
endmodule // SensorFSM
|
#include <bits/stdc++.h> using namespace std; const int inf(1010101010); int n, k; struct node_t { node_t(char edge, int h) : edge(edge), hier(0), pop(0), h(h) {} char edge; int hier, pop; int h; vector<node_t *> child; }; void ins(node_t *x, char *pos) { x->pop++; if (!pos[0]) { x->hier++; return; } for (__typeof((x->child).end()) it((x->child).begin()); it != ((x->child).end()); ++it) { node_t *y(*it); if (y->edge == pos[0]) { ins(y, ++pos); return; } } x->child.push_back(new node_t(pos[0], x->h + 1)), ins(x->child.back(), ++pos); } char bla[2005]; vector<vector<int> > mems; int new_mem() { mems.push_back(vector<int>()); return ((int)(mems).size()) - 1; } inline int tri(int x) { return x * (x - 1) / 2; } inline void chmax(int &x, int y) { x = max(x, y); } inline void merge(vector<int> &dst, vector<int> &erbij, int hh) { int cnt_bij(((int)(erbij).size()) - 1); dst.resize(((int)(dst).size()) + cnt_bij); for (int i(((int)(dst).size()) - 1); ~i; i--) { for (int bij(0); bij <= cnt_bij && bij <= i; bij++) { chmax(dst[i], dst[i - bij] + erbij[bij] + hh * (tri(i) - tri(i - bij) - tri(bij))); } } } int calc(node_t *x) { if (x->hier == 0 && ((int)(x->child).size()) == 1) return calc(x->child[0]); int pt(new_mem()); if (((int)(x->child).size()) == 0) { mems[pt].resize(x->pop + 1); for (int i(0); i <= (x->pop); i++) { mems[pt][i] = tri(i) * x->h; } } else { node_t *y0(x->child[0]); int y0pos(calc(y0)); mems[pt].assign((mems[y0pos]).begin(), (mems[y0pos]).end()); int ander(y0->pop); for (__typeof((x->child).end()) it((x->child).begin() + 1); it != ((x->child).end()); ++it) { node_t *y(*it); int ypos(calc(y)); merge(mems[pt], mems[ypos], x->h); ander += y->pop; } for (int i(ander + 1); i <= (ander + x->hier); i++) { mems[pt].push_back(mems[pt][ander] + (tri(i) - tri(ander)) * x->h); } } return pt; } void solve() { if (!(cin >> n >> k)) exit(0); node_t *root(new node_t( - , 0)); for (int i(0); i < (n); i++) { scanf( %s , bla), ins(root, bla); } int rr(calc(root)); cout << mems[rr][k] << endl; } int main() { while (1) solve(); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRSDFRTP_SYMBOL_V
`define SKY130_FD_SC_LP__SRSDFRTP_SYMBOL_V
/**
* srsdfrtp: Scan flop with sleep mode, inverted reset, non-inverted
* clock, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__srsdfrtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input SLEEP_B
);
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRSDFRTP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; vector<int> bomb[5005]; int n, m, st_time[5005], sol[5005], dist_min[5005]; int main() { cin >> n >> m; for (int i = 1; i <= n; ++i) dist_min[i] = 2 * 5005; int pos, val; for (int i = 1; i <= m; ++i) { cin >> pos >> val; bomb[pos].push_back(val); int comp = 0; if (val >= pos) comp = val - pos; else comp = n - (pos - val); if (val != pos) dist_min[pos] = min(dist_min[pos], comp); } for (int i = 1; i <= n; ++i) { int blen = bomb[i].size(); if (blen) st_time[i] = n * (blen - 1) + dist_min[i]; else st_time[i] = 0; } for (int i = 1; i <= n; ++i) { for (int j = 1; j <= n; ++j) if (!bomb[j].empty()) { if (j < i) sol[i] = max(sol[i], n - (i - j) + st_time[j]); else sol[i] = max(sol[i], j - i + st_time[j]); } cout << sol[i] << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m; int p[100]; char mm[100]; int main() { while (scanf( %d , &n) != EOF) { scanf( %s , &mm); int len = strlen(mm); m = 0; for (int i = 0; i < len; ++i) m = m * 10 + (mm[i] - 0 ); if (n == 0) { if (strlen(mm) != 1) puts( WRONG_ANSWER ); else if (m == 0) puts( OK ); else puts( WRONG_ANSWER ); } else { if (mm[0] == 0 ) { puts( WRONG_ANSWER ); return 0; } int x = n; memset(p, 0, sizeof(p)); while (x > 0) { p[x % 10]++; x /= 10; } int now = 0; for (int i = 1; i <= 9; ++i) if (p[i]) { now = i; p[i]--; break; } for (int i = 0; i <= 9; ++i) { while (p[i]) { now = now * 10 + i; p[i]--; } } if (now == m) puts( OK ); else puts( WRONG_ANSWER ); } } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, s, x, v, t, y, i, nr1, nr2, v1[100004], v2[100004], c[1000004], d[1000004]; long long st, dr, m, Min, Min1, x1, x2, a[100004], b[100004]; double nr; bool ok; int main() { scanf( %d %d , &n, &s); for (i = 1; i <= n; i++) { scanf( %d %d %d , &x, &v, &t); if (t == 1) { a[++nr1] = (1LL) * x * 5000000; v1[nr1] = v; } else { b[++nr2] = (1LL) * 1000000 * 5000000 - (1LL) * x * 5000000; v2[nr2] = v; } } st = 1; dr = (1LL) * 1000000 * 5000000; for (i = 1; i <= 1000000; i++) c[i] = 0; while (st <= dr) { m = (1LL) * ((0LL) + st + dr) / 2; ok = false; for (i = 1; i <= nr1; i++) { x1 = (0LL) + a[i] - (1LL) * v1[i] * m; if (x1 > 0) { x2 = (1LL) * x1 / s; if (((1LL) * x1 % s) != 0) x2 = (1LL) + x2; x2 = (0LL) + m - x2; if (x2 >= 0) { x1 = (0LL) + a[i] + (1LL) * x2 * (s - v1[i]); if (((1LL) * a[i] % 5000000) == 0) c[(1LL) * a[i] / 5000000]++; else c[(1LL) * a[i] / 5000000 + 1]++; if (((1LL) * x1 / 5000000) <= 1000000) c[(1LL) * x1 / 5000000 + 1]--; } } else c[1]++; } for (i = 1; i <= nr2 && ok == false; i++) { x1 = (0LL) + b[i] - (1LL) * v2[i] * m; if (x1 > 0) { x2 = (1LL) * x1 / s; if (((1LL) * x1 % s) != 0) x2 = (1LL) + x2; x2 = (0LL) + m - x2; if (x2 >= 0) { x1 = (0LL) + ((1LL) * 5000000 * 1000000 - b[i]) - (1LL) * x2 * (s - v2[i]); d[(1LL) * ((1LL) * 5000000 * 1000000 - b[i]) / 5000000 + 1]--; if ((((1LL) * x1 % 5000000) == 0) && (x1 > 0)) d[(1LL) * x1 / 5000000]++; else if ((((1LL) * x1 % 5000000) != 0) && (x1 > 0)) d[(1LL) * x1 / 5000000 + 1]++; else d[1]++; } } else d[1]++; } if (ok == false) { x = 0; y = 0; for (i = 1; i <= 1000000; i++) { x += c[i]; y += d[i]; if (x > 0 && y > 0) ok = true; c[i] = 0; d[i] = 0; } } if (ok == false) st = (0LL) + m + 1; else dr = (0LL) + m - 1; } nr = (1.0) * st / 5000000; printf( %.10f , nr); return 0; } |
#include <bits/stdc++.h> using namespace std; void run_case() { int n, k; cin >> n >> k; vector<int> A(n); for (int &a : A) { cin >> a; } vector<int> ans; for (int i = 1; i < n; i++) { ans.push_back(A[i - 1] - A[i]); } sort(ans.begin(), ans.end()); ; int res = A[n - 1] - A[0]; for (int i = 0; i < k - 1; i++) { res += ans[i]; } cout << res; } int main() { ios_base::sync_with_stdio(false); int test = 1; while (test--) { run_case(); cout << n ; } } |
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: sfifo_112x256_la.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sfifo_112x256_la (
aclr,
clock,
data,
rdreq,
wrreq,
almost_full,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [111:0] data;
input rdreq;
input wrreq;
output almost_full;
output empty;
output full;
output [111:0] q;
output [7:0] usedw;
wire [7:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [111:0] sub_wire3;
wire sub_wire4;
wire [7:0] usedw = sub_wire0[7:0];
wire empty = sub_wire1;
wire full = sub_wire2;
wire [111:0] q = sub_wire3[111:0];
wire almost_full = sub_wire4;
scfifo scfifo_component (
.clock (clock),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.usedw (sub_wire0),
.empty (sub_wire1),
.full (sub_wire2),
.q (sub_wire3),
.almost_full (sub_wire4),
.almost_empty (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.almost_full_value = 192,
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 112,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "192"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "112"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "112"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "192"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "112"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL "almost_full"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 112 0 INPUT NODEFVAL "data[111..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 112 0 OUTPUT NODEFVAL "q[111..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL "usedw[7..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 112 0 data 0 0 112 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 112 0 @q 0 0 112 0
// Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_112x256_la.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_112x256_la.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_112x256_la.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_112x256_la.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_112x256_la_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_112x256_la_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/* Module from the schematic_gui program written by Andreas Ehliar <>
This Verilog file is licensed under the CC0 license. */
module mux5 #(parameter WIREWIDTH = 1) (input wire [2:0] s,
input wire [WIREWIDTH:0] d0, d1, d2,d3, d4,
output reg [WIREWIDTH:0] o);
initial begin
$schematic_boundingbox(40,240);
$schematic_polygonstart;
$schematic_coord(10,10);
$schematic_coord(30,30);
$schematic_coord(30,210);
$schematic_coord(10,230);
$schematic_polygonend;
$schematic_linestart;
$schematic_coord(20,19);
$schematic_coord(20,10);
$schematic_lineend;
$schematic_connector(d0,0,40);
$schematic_connector(d1,0,80);
$schematic_connector(d2,0,120);
$schematic_connector(d3,0,160);
$schematic_connector(d4,0,200);
$schematic_connector(o,40,120);
$schematic_connector(s,20,0);
$schematic_symboltext("0", 20,40);
$schematic_symboltext("1", 20,80);
$schematic_symboltext("2", 20,120);
$schematic_symboltext("3", 20,160);
$schematic_symboltext("4", 20,200);
end
always @* begin
case(s)
0: o = d0;
1: o = d1;
2: o = d2;
3: o = d3;
default: o = d4;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int>::iterator IntIter; vector<long long>::iterator LLIter; int main(int argc, char *argv[]) { int i, j; int a[3][3]; for (i = 0; i < 3; i++) for (j = 0; j < 3; j++) cin >> a[i][j]; int b[3][3] = {1}; b[0][0] = (a[0][0] + a[0][1] + a[1][0]) % 2; b[0][1] = (a[0][0] + a[0][1] + a[0][2] + a[1][1]) % 2; b[0][2] = (a[0][1] + a[0][2] + a[1][2]) % 2; b[1][0] = (a[1][0] + a[0][0] + a[1][1] + a[2][0]) % 2; b[1][1] = (a[1][0] + a[1][1] + a[1][2] + a[0][1] + a[2][1]) % 2; b[1][2] = (a[1][1] + a[1][2] + a[0][2] + a[2][2]) % 2; b[2][0] = (a[2][0] + a[1][0] + a[2][1]) % 2; b[2][1] = (a[1][1] + a[2][0] + a[2][1] + a[2][2]) % 2; b[2][2] = (a[1][2] + a[2][1] + a[2][2]) % 2; for (i = 0; i < 3; i++) { for (j = 0; j < 3; j++) { if (b[i][j]) { cout << 0 ; } else { cout << 1 ; } } cout << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int M = 2010; int A[M][M]; int col[M]; int diag[M]; int main() { ios_base::sync_with_stdio(false); int i, j, k, n; char str[M]; scanf( %d , &n); for (i = 0; i < n; i++) { scanf( %s , str); for (j = 0; j < n; j++) A[i][j] = str[j] - 0 ; } int sum = 0; for (i = n - 1; i > 0; i--) { int inv = 0; for (j = 0; j < i; j++) { if (A[i][j] != (inv ^ col[j])) { inv ^= 1; sum++; diag[i] ^= 1; diag[j] ^= 1; col[j] ^= 1; } } } memset((col), (0), sizeof(col)); for (i = 0; i < n - 1; i++) { int inv = 0; for (j = n - 1; j > i; j--) { if (A[i][j] != (inv ^ col[j])) { inv ^= 1; sum++; diag[i] ^= 1; diag[j] ^= 1; col[j] ^= 1; } } } for (i = 0; i < n; i++) if (A[i][i] != diag[i]) sum++; printf( %d n , sum); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e6 + 5; constexpr int SQRT = 1000; struct query { int x, y, pos; short sqrt; bool operator<(const query &b) const { if (sqrt == b.sqrt) { return ((sqrt & 1) ^ y < b.y); } return sqrt < b.sqrt; } }; query que[MAXN]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n; cin >> n; for (int i = 0; i < n; i++) { cin >> que[i].x >> que[i].y; que[i].pos = i + 1, que[i].sqrt = que[i].x / SQRT; } sort(que, que + n); for (int i = 0; i < n; i++) { cout << que[i].pos << ; } cout << n ; } |
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module tx_chain
(input clock,
input reset,
input enable,
input wire [7:0] interp_rate,
input sample_strobe,
input interpolator_strobe,
input wire [31:0] freq,
input wire [15:0] i_in,
input wire [15:0] q_in,
output wire [15:0] i_out,
output wire [15:0] q_out
);
wire [15:0] bb_i, bb_q;
cic_interp cic_interp_i
( .clock(clock),.reset(reset),.enable(enable),
.rate(interp_rate),.strobe_in(interpolator_strobe),.strobe_out(sample_strobe),
.signal_in(i_in),.signal_out(bb_i) );
cic_interp cic_interp_q
( .clock(clock),.reset(reset),.enable(enable),
.rate(interp_rate),.strobe_in(interpolator_strobe),.strobe_out(sample_strobe),
.signal_in(q_in),.signal_out(bb_q) );
`define NOCORDIC_TX
`ifdef NOCORDIC_TX
assign i_out = bb_i;
assign q_out = bb_q;
`else
wire [31:0] phase;
phase_acc phase_acc_tx
(.clk(clock),.reset(reset),.enable(enable),
.strobe(sample_strobe),.freq(freq),.phase(phase) );
cordic tx_cordic_0
( .clock(clock),.reset(reset),.enable(sample_strobe),
.xi(bb_i),.yi(bb_q),.zi(phase[31:16]),
.xo(i_out),.yo(q_out),.zo() );
`endif
endmodule // tx_chain
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.3.1 (lin64) Build Thu Oct 30 16:30:39 MDT 2014
// Date : Wed Apr 8 20:38:45 2015
// Host : parallella running 64-bit Ubuntu 14.04.2 LTS
// Command : write_verilog -force -mode synth_stub
// /home/aolofsson/Work_all/parallella-hw/fpga/vivado/junk/junk.srcs/sources_1/ip/fifo_async_103x16/fifo_async_103x16_stub.v
// Design : fifo_async_103x16
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v12_0,Vivado 2014.3.1" *)
module fifo_async_104x16(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, empty, prog_full)
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[103:0],wr_en,rd_en,dout[103:0],full,empty,prog_full" */;
input rst;
input wr_clk;
input rd_clk;
input [103:0]din;
input wr_en;
input rd_en;
output [103:0]dout;
output full;
output empty;
output prog_full;
assign empty =1'b0;
assign prog_full =1'b0;
assign dout[103:0] =103'b0;
assign full =1'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m; bool reachable(vector<set<int>> g, int u, int v) { if (g[u].find(v) == g[u].end()) { for (auto x : g[u]) { if (g[x].find(v) != g[x].end()) return true; } } else { return true; } return false; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> m; set<pair<int, int>> edges; set<int> badnodes; while (m--) { int x, y; cin >> x >> y; --x; --y; edges.insert({x, y}); edges.insert({y, x}); badnodes.insert(x); badnodes.insert(y); } int c = 0; for (int u = 0; u < n; ++u) { if (badnodes.find(u) == badnodes.end()) c = u; } cout << n - 1 << endl; vector<set<int>> g(n); for (int u = 0; u < n; ++u) { if (u == c) continue; if (reachable(g, u, c)) continue; if (edges.find({u, c}) == edges.end()) { g[c].insert(u); g[u].insert(c); cout << c + 1 << << u + 1 << endl; } else { for (int v = 0; v < n; ++v) { if (edges.find({u, v}) == edges.end()) { g[u].insert(v); g[v].insert(u); cout << u + 1 << << v + 1 << endl; } } } } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A31O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__A31O_FUNCTIONAL_PP_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a31o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A31O_FUNCTIONAL_PP_V |
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Instruction Cache top level ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://opencores.org/project,or1k ////
//// ////
//// Description ////
//// Instantiation of all IC blocks. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// $Log: or1200_ic_top.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// No update
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
//
// Instruction cache top
//
module or1200_ic_top(
// Rst, clk and clock control
clk, rst,
// External i/f
icbiu_dat_o, icbiu_adr_o, icbiu_cyc_o, icbiu_stb_o, icbiu_we_o,
icbiu_sel_o, icbiu_cab_o, icbiu_dat_i, icbiu_ack_i, icbiu_err_i,
// Internal i/f
ic_en,
icqmem_adr_i, icqmem_cycstb_i, icqmem_ci_i, icqmem_sel_i, icqmem_tag_i,
icqmem_dat_o, icqmem_ack_o, icqmem_rty_o, icqmem_err_o, icqmem_tag_o,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// SPRs
spr_cs, spr_write, spr_dat_i
);
parameter dw = `OR1200_OPERAND_WIDTH;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// External I/F
//
output [dw-1:0] icbiu_dat_o;
output [31:0] icbiu_adr_o;
output icbiu_cyc_o;
output icbiu_stb_o;
output icbiu_we_o;
output [3:0] icbiu_sel_o;
output icbiu_cab_o;
input [dw-1:0] icbiu_dat_i;
input icbiu_ack_i;
input icbiu_err_i;
//
// Internal I/F
//
input ic_en;
input [31:0] icqmem_adr_i;
input icqmem_cycstb_i;
input icqmem_ci_i;
input [3:0] icqmem_sel_i;
input [3:0] icqmem_tag_i;
output [dw-1:0] icqmem_dat_o;
output icqmem_ack_o;
output icqmem_rty_o;
output icqmem_err_o;
output [3:0] icqmem_tag_o;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// SPR access
//
input spr_cs;
input spr_write;
input [31:0] spr_dat_i;
//
// Internal wires and regs
//
wire tag_v;
wire [`OR1200_ICTAG_W-2:0] tag;
wire [dw-1:0] to_icram;
wire [dw-1:0] from_icram;
wire [31:0] saved_addr;
wire [3:0] icram_we;
wire ictag_we;
wire [31:0] ic_addr;
wire icfsm_biu_read;
/* verilator lint_off UNOPTFLAT */
reg tagcomp_miss;
/* verilator lint_on UNOPTFLAT */
wire [`OR1200_ICINDXH:`OR1200_ICLS] ictag_addr;
wire ictag_en;
wire ictag_v;
wire ic_inv;
wire icfsm_first_hit_ack;
wire icfsm_first_miss_ack;
wire icfsm_first_miss_err;
wire icfsm_burst;
wire icfsm_tag_we;
reg ic_inv_q;
`ifdef OR1200_BIST
//
// RAM BIST
//
wire mbist_ram_so;
wire mbist_tag_so;
wire mbist_ram_si = mbist_si_i;
wire mbist_tag_si = mbist_ram_so;
assign mbist_so_o = mbist_tag_so;
`endif
//
// Simple assignments
//
assign icbiu_adr_o = ic_addr;
assign ic_inv = spr_cs & spr_write;
assign ictag_we = icfsm_tag_we | ic_inv;
assign ictag_addr = ic_inv ?
spr_dat_i[`OR1200_ICINDXH:`OR1200_ICLS] :
ic_addr[`OR1200_ICINDXH:`OR1200_ICLS];
assign ictag_en = ic_inv | ic_en;
assign ictag_v = ~ic_inv;
//
// Data to BIU is from ICRAM when IC is enabled or from LSU when
// IC is disabled
//
assign icbiu_dat_o = 32'h00000000;
//
// Bypases of the IC when IC is disabled
//
assign icbiu_cyc_o = (ic_en) ? icfsm_biu_read : icqmem_cycstb_i;
assign icbiu_stb_o = (ic_en) ? icfsm_biu_read : icqmem_cycstb_i;
assign icbiu_we_o = 1'b0;
assign icbiu_sel_o = (ic_en & icfsm_biu_read) ? 4'b1111 : icqmem_sel_i;
assign icbiu_cab_o = (ic_en) ? icfsm_burst : 1'b0;
assign icqmem_rty_o = ~icqmem_ack_o & ~icqmem_err_o;
assign icqmem_tag_o = icqmem_err_o ? `OR1200_ITAG_BE : icqmem_tag_i;
//
// CPU normal and error termination
//
assign icqmem_ack_o = ic_en ? (icfsm_first_hit_ack | icfsm_first_miss_ack) : icbiu_ack_i;
assign icqmem_err_o = ic_en ? icfsm_first_miss_err : icbiu_err_i;
//
// Select between claddr generated by IC FSM and addr[3:2] generated by LSU
//
assign ic_addr = (icfsm_biu_read) ? saved_addr : icqmem_adr_i;
//
// Select between input data generated by LSU or by BIU
//
assign to_icram = icbiu_dat_i;
//
// Select between data generated by ICRAM or passed by BIU
//
assign icqmem_dat_o = icfsm_first_miss_ack | !ic_en ? icbiu_dat_i : from_icram;
//
// Detect falling edge of IC invalidate signal
//
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst==`OR1200_RST_VALUE)
ic_inv_q <= 1'b0;
else
ic_inv_q <= ic_inv;
//
// Tag comparison
//
// During line invalidate, ensure it stays the same
always @(tag or saved_addr or tag_v) begin
if ((tag != saved_addr[31:`OR1200_ICTAGL]) | !tag_v)
tagcomp_miss = 1'b1;
else
tagcomp_miss = 1'b0;
end
//
// Instantiation of IC Finite State Machine
//
or1200_ic_fsm or1200_ic_fsm(
.clk(clk),
.rst(rst),
.ic_en(ic_en),
.icqmem_cycstb_i(icqmem_cycstb_i),
.icqmem_ci_i(icqmem_ci_i),
.tagcomp_miss(tagcomp_miss),
.biudata_valid(icbiu_ack_i),
.biudata_error(icbiu_err_i),
.start_addr(icqmem_adr_i),
.saved_addr(saved_addr),
.icram_we(icram_we),
.biu_read(icfsm_biu_read),
.first_hit_ack(icfsm_first_hit_ack),
.first_miss_ack(icfsm_first_miss_ack),
.first_miss_err(icfsm_first_miss_err),
.burst(icfsm_burst),
.tag_we(icfsm_tag_we)
);
//
// Instantiation of IC main memory
//
or1200_ic_ram or1200_ic_ram(
.clk(clk),
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_ram_si),
.mbist_so_o(mbist_ram_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.addr(ic_addr[`OR1200_ICINDXH:2]),
.en(ic_en),
.we(icram_we),
.datain(to_icram),
.dataout(from_icram)
);
//
// Instantiation of IC TAG memory
//
or1200_ic_tag or1200_ic_tag(
.clk(clk),
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_tag_si),
.mbist_so_o(mbist_tag_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.addr(ictag_addr),
.en(ictag_en),
.we(ictag_we),
.datain({ic_addr[31:`OR1200_ICTAGL], ictag_v}),
.tag_v(tag_v),
.tag(tag)
);
endmodule
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// NOTE: This is still WIP.
(* techmap_celltype = "$alu" *)
module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
//output [Y_WIDTH-1:0] CO;
output CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
wire [Y_WIDTH-1:0] AA = A_buf;
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
//wire [Y_WIDTH:0] C = {CO, CI};
wire [Y_WIDTH+1:0] COx;
wire [Y_WIDTH+1:0] C = {COx, CI};
/* Start implementation */
(* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
if(i==Y_WIDTH-1) begin
(* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b1111_0000_1110_0000), .sum_lutc_input("cin")) carry_end (.combout(COx[Y_WIDTH]), .dataa(1'b1), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[Y_WIDTH]));
assign CO = COx[Y_WIDTH];
end
else
fiftyfivenm_lcell_comb #(.lut_mask(16'b1001_0110_1110_1000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(COx[i+1]), .dataa(AA[i]), .datab(BB[i]), .datac(1'b1), .datad(1'b1), .cin(C[i+1]));
end: slice
endgenerate
/* End implementation */
assign X = AA ^ BB;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e3 + 10; long long q, x, v, u, w, ans; map<long long, long long> len; int main() { cin >> q; for (int i = 1; i <= q; i++) { cin >> x >> v >> u; if (x == 1) { cin >> w; while (v != u) { if (v > u) { len[v] += w; v = v / 2; } else { len[u] += w; u = u / 2; } } } else { ans = 0; while (v != u) { if (v > u) { ans += len[v]; v = v / 2; } else { ans += len[u]; u = u / 2; } } cout << ans << n ; } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__BUFBUF_BLACKBOX_V
`define SKY130_FD_SC_HD__BUFBUF_BLACKBOX_V
/**
* bufbuf: Double buffer.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__bufbuf (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__BUFBUF_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; unsigned long long int power(unsigned long long int n, unsigned long long int p) { unsigned long long int m = 1; while (p > 0) { m *= n; p--; } return m; } void sieveOfEratosthenes(int n, bool prime[]) { unsigned long long int i, p; for (i = 2; i <= n / 2; i++) { if (prime[i]) { for (p = i * i; p <= n; p += i) { prime[p] = false; } } } } void add_edge(int u, int v, vector<int> adj_list[]) { adj_list[u - 1].push_back(v - 1); adj_list[v - 1].push_back(u - 1); } int lcs(int brr[], int arr[], int size, int n) { int dp[size + 1][n + 1]; for (int i = 0; i <= size; ++i) { for (int j = 0; j <= n; ++j) { if (i == 0 || j == 0) dp[i][j] = 0; else if (brr[i - 1] == arr[j - 1]) dp[i][j] = dp[i - 1][j - 1] + 1; else dp[i][j] = max(dp[i][j - 1], dp[i - 1][j]); } } return dp[size][n]; } void kmagic(int n, int k, int arr[]) { int size = (int)1e4, count = 0; int brr[size + 1]; unordered_set<int> st; vector<int> v; for (int i = 0; i < size; ++i) brr[i] = -1; for (int i = 0; i < n; ++i) { if (st.find(arr[i]) == st.end()) { v.push_back(arr[i]); st.insert(arr[i]); } } count = k - v.size(); while (count > 0) { v.push_back(v[0]); count--; } if (st.size() <= k) { for (int i = 0; i < v.size(); ++i) { for (int j = i; j < size; j += k) brr[j] = v[i]; } cout << size << endl; for (int i = 0; i < size; ++i) cout << brr[i] << ; } else cout << -1 ; } int main(int argc, char const *argv[]) { int t, x, k, y, u, v, n, m, money, val, b, days, check = 0, points; ios_base::sync_with_stdio(false); cin.tie(NULL); string str; t = 1; cin >> t; while (t--) { int r, b, ox, oy, k; string s, t; cin >> n >> k; unordered_set<int> st; int heights[n]; for (int i = 0; i < n; ++i) cin >> heights[i]; kmagic(n, k, heights); cout << endl; } return 0; } |
#include <bits/stdc++.h> const int maxn = 2 * 100000; const int inf = 99999999; class array { public: int num; int left; int right; array() { left = right = inf; } } a[maxn + 1]; int queue[maxn + 1]; int head = 1, tail = 1; int main() { int n; scanf( %d , &n); int nowzero = 0; for (int i = 1; i <= n; i++) { scanf( %d , &a[i].num); if (!a[i].num) { nowzero = i; a[i].left = a[i].right = 0; for (int j = head; j < tail; j++) { a[queue[j]].right = nowzero - queue[j]; } tail = head; } else { if (nowzero) a[i].left = i - nowzero; queue[tail++] = i; } } for (int i = 1; i <= n; i++) printf( %d%c , a[i].left > a[i].right ? a[i].right : a[i].left, i == n ? n : ); return 0; } |
/*
* Copyright 2018-2022 F4PGA Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module RAM_TEST #(
parameter ADDR_WIDTH = 6,
parameter DATA_WIDTH = 1,
parameter IS_DUAL_PORT = 1,
parameter RANDOM_ITERATION_PER_LOOP = 10,
parameter LFSR_WIDTH = 16,
parameter LFSR_POLY = 16'hD008,
// How much to increment the address to move 1 full data width.
parameter ADDRESS_STEP = 1,
// Max address for this memory
parameter MAX_ADDRESS = 63
) (
input rst,
input clk,
// Memory connection
input [DATA_WIDTH-1:0] read_data,
output reg [DATA_WIDTH-1:0] write_data,
output reg write_enable,
output reg [ADDR_WIDTH-1:0] read_address,
output reg [ADDR_WIDTH-1:0] write_address,
// INIT ROM
// When the memory is first initialized, it is expected to match the ROM
// port.
input [DATA_WIDTH-1:0] rom_read_data,
output reg [ADDR_WIDTH-1:0] rom_read_address,
// When an iteration is complete, success will be 1 for 1 cycle
output reg loop_complete,
// If an error occurs during a test, error will be 1 for each cycle
// with an error.
output reg error,
// error_state will contain the state of test FSM when the error occured.
output reg [7:0] error_state,
// error_address will be the read address where the error occurred.
output reg [ADDR_WIDTH-1:0] error_address,
// expected_data will be the read value expected.
output reg [DATA_WIDTH-1:0] expected_data,
// actual_data will be the read value read.
output reg [DATA_WIDTH-1:0] actual_data
);
reg [7:0] state;
reg [DATA_WIDTH-1:0] test_value;
reg [$clog2(RANDOM_ITERATION_PER_LOOP)-1:0] rand_count;
localparam START = 8'd1,
VERIFY_INIT = 8'd2,
WRITE_ZEROS = 8'd3,
VERIFY_ZEROS = 8'd4,
WRITE_ONES = 8'd5,
VERIFY_ONES = 8'd6,
WRITE_10 = 8'd7,
VERIFY_10 = 8'd8,
WRITE_01 = 8'd9,
VERIFY_01 = 8'd10,
WRITE_RANDOM = 8'd11,
VERIFY_RANDOM = 8'd12,
RESTART_LOOP = 8'd13;
reg pause;
reg lfsr_reset;
reg wait_for_lfsr_reset;
reg [LFSR_WIDTH-1:0] lfsr_seed;
reg [LFSR_WIDTH-1:0] start_lfsr_seed;
wire [LFSR_WIDTH-1:0] rand_data;
LFSR #(
.WIDTH(LFSR_WIDTH),
.POLY(LFSR_POLY)
) lfsr (
.rst(lfsr_reset),
.clk(clk),
.seed(lfsr_seed),
.r(rand_data)
);
always @(posedge clk) begin
if(rst) begin
state <= START;
error <= 0;
write_enable <= 0;
lfsr_reset <= 1;
lfsr_seed <= 1;
end else begin
case(state)
START: begin
lfsr_reset <= 0;
state <= VERIFY_INIT;
read_address <= 0;
rom_read_address <= 0;
write_enable <= 0;
error <= 0;
end
VERIFY_INIT: begin
if(rom_read_data != read_data) begin
error <= 1;
error_state <= state;
error_address <= read_address;
expected_data <= rom_read_data;
actual_data <= read_data;
end else begin
error <= 0;
end
if(read_address + ADDRESS_STEP <= MAX_ADDRESS) begin
read_address <= read_address + ADDRESS_STEP;
rom_read_address <= rom_read_address + ADDRESS_STEP;
end else begin
read_address <= 0;
write_address <= 0;
write_enable <= 1;
write_data <= {DATA_WIDTH{1'b0}};
state <= WRITE_ZEROS;
end
end
WRITE_ZEROS: begin
loop_complete <= 0;
if(write_address + ADDRESS_STEP <= MAX_ADDRESS) begin
write_address <= write_address + ADDRESS_STEP;
end else begin
read_address <= 0;
write_address <= 0;
write_enable <= 0;
pause <= 1;
state <= VERIFY_ZEROS;
end
end
VERIFY_ZEROS: begin
if(pause) begin
pause <= 0;
end else begin
if(read_data != {DATA_WIDTH{1'b0}}) begin
error <= 1;
error_state <= state;
error_address <= read_address;
expected_data <= {DATA_WIDTH{1'b0}};
actual_data <= read_data;
end else begin
error <= 0;
end
if(read_address + ADDRESS_STEP <= MAX_ADDRESS) begin
read_address <= read_address + ADDRESS_STEP;
end else begin
read_address <= 0;
write_address <= 0;
write_enable <= 1;
write_data <= {DATA_WIDTH{1'b1}};
state <= WRITE_ONES;
end
end
end
WRITE_ONES: begin
// If dual port, data should still be zero.
if(IS_DUAL_PORT) begin
if(read_data != {DATA_WIDTH{1'b0}}) begin
error <= 1;
error_state <= state;
error_address <= read_address;
expected_data <= {DATA_WIDTH{1'b0}};
actual_data <= read_data;
end else begin
error <= 0;
end
end else begin
if(read_data != {DATA_WIDTH{1'b1}}) begin
error <= 1;
error_state <= state;
error_address <= read_address;
expected_data <= {DATA_WIDTH{1'b1}};
actual_data <= read_data;
end else begin
error <= 0;
end
end
if(write_address + ADDRESS_STEP <= MAX_ADDRESS) begin
read_address <= read_address + ADDRESS_STEP;
write_address <= write_address + ADDRESS_STEP;
end else begin
read_address <= 0;
write_address <= 0;
write_enable <= 0;
state <= VERIFY_ONES;
pause <= 1;
end
end
VERIFY_ONES: begin
if(pause) begin
pause <= 0;
end else begin
if(read_data != {DATA_WIDTH{1'b1}}) begin
error <= 1;
error_state <= state;
error_address <= read_address;
expected_data <= {DATA_WIDTH{1'b1}};
actual_data <= read_data;
end else begin
error <= 0;
end
if(read_address + ADDRESS_STEP <= MAX_ADDRESS) begin
read_address <= read_address + ADDRESS_STEP;
end else begin
state <= WRITE_RANDOM;
write_enable <= 1;
write_address <= 0;
lfsr_seed <= rand_data;
write_data <= rand_data[DATA_WIDTH-1:0];
read_address <= 0;
end
end
end
WRITE_RANDOM: begin
if(write_address + ADDRESS_STEP <= MAX_ADDRESS) begin
write_address <= write_address + ADDRESS_STEP;
write_data <= rand_data[DATA_WIDTH-1:0];
end else begin
read_address <= 0;
write_address <= 0;
write_enable <= 0;
state <= VERIFY_RANDOM;
// Return LFSR to state at beginning of WRITE_RANDOM.
lfsr_reset <= 1;
wait_for_lfsr_reset <= 1;
end
end
VERIFY_RANDOM: begin
if(wait_for_lfsr_reset) begin
wait_for_lfsr_reset <= 0;
lfsr_reset <= 1;
end else begin
lfsr_reset <= 0;
if(read_data != rand_data[DATA_WIDTH-1:0]) begin
error <= 1;
error_state <= state;
error_address <= read_address;
expected_data <= rand_data[DATA_WIDTH-1:0];
actual_data <= read_data;
end else begin
error <= 0;
end
if(read_address + ADDRESS_STEP <= MAX_ADDRESS) begin
read_address <= read_address + ADDRESS_STEP;
end else begin
state <= RESTART_LOOP;
end
end
end
RESTART_LOOP: begin
loop_complete <= 1;
error <= 0;
read_address <= 0;
write_address <= 0;
write_enable <= 1;
write_data <= {DATA_WIDTH{1'b0}};
state <= WRITE_ZEROS;
end
default: begin
state <= START;
error <= 0;
end
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FA_TB_V
`define SKY130_FD_SC_MS__FA_TB_V
/**
* fa: Full adder.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__fa.v"
module top();
// Inputs are registered
reg A;
reg B;
reg CIN;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire COUT;
wire SUM;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
CIN = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 CIN = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 CIN = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 CIN = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 CIN = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 CIN = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_ms__fa dut (.A(A), .B(B), .CIN(CIN), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .COUT(COUT), .SUM(SUM));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__FA_TB_V
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 , unroll-loops ) using namespace std; namespace { const int MOD107 = 1000000007; const int MOD998 = 998244353; using ll = long long; using ull = unsigned long long; using pii = pair<int, int>; using pll = pair<ll, ll>; template <class T> using minheap = priority_queue<T, vector<T>, greater<T>>; template <class T> using maxheap = priority_queue<T, vector<T>, less<T>>; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); struct Modular { private: long long MODVALUE = 0; long long val = 0; Modular initModular(long long val) const { return Modular(val, MODVALUE); } inline void validate() const {} inline void validate(const Modular& other) const {} public: explicit operator long long() const { return val; } template <class T> Modular& operator=(const T& other) { val = (other % MODVALUE + MODVALUE) % MODVALUE; return *this; } long long getMod() { return MODVALUE; } template <class T> void setMod(const T& MOD) { MODVALUE = MOD; } bool operator==(const Modular& other) const { validate(other); return val == other.val; } bool operator!=(const Modular& other) const { return !(*this == other); } Modular& operator+=(const Modular& other) { validate(other); val += other.val; if (val >= MODVALUE) val -= MODVALUE; return *this; } Modular operator+(const Modular& other) const { Modular tmp = *this; return tmp += other; } template <class T> Modular& operator+=(const T& other) { return *this += initModular(other); } template <class T> Modular operator+(const T& other) const { return *this + initModular(other); } template <class T> friend Modular operator+(const T& other, const Modular& m) { return m.initModular(other) + m; } Modular& operator++() { return *this += 1; } Modular operator++(int) { Modular tmp = *this; ++*this; return tmp; } Modular operator-() const { return initModular(-val); } Modular& operator-=(const Modular& other) { validate(other); val -= other.val; if (val < 0) val += MODVALUE; return *this; } Modular operator-(const Modular& other) const { Modular tmp = *this; return tmp -= other; } template <class T> Modular& operator-=(const T& other) { return *this -= initModular(other); } template <class T> Modular operator-(const T& other) const { return *this - initModular(other); } template <class T> friend Modular operator-(const T& other, const Modular& m) { return m.initModular(other) - m; } Modular& operator--() { return *this -= 1; } Modular operator--(int) { Modular tmp = *this; --*this; return tmp; } Modular& operator*=(const Modular& other) { validate(other); val *= other.val; val %= MODVALUE; if (val < 0) val += MODVALUE; return *this; } Modular operator*(const Modular& other) const { Modular tmp = *this; return tmp *= other; } template <class T> Modular& operator*=(const T& other) { return *this *= initModular(other); } template <class T> Modular operator*(const T& other) const { return *this * initModular(other); } template <class T> friend Modular operator*(const T& other, const Modular& m) { return m.initModular(other) * m; } Modular pow(long long power) const { Modular m = *this, ans = initModular(1); while (power) { if (power & 1) ans *= m; m *= m; power >>= 1; } return ans; } Modular pow(const Modular& other) const { return pow(other.val); } Modular inv() const { return pow(MODVALUE - 2); } Modular& operator/=(const Modular& other) { val *= other.inv().val; val %= MODVALUE; if (val < 0) val += MODVALUE; return *this; } Modular operator/(const Modular& other) const { Modular tmp = *this; return tmp /= other; } template <class T> Modular& operator/=(const T& other) { return *this /= initModular(other); } template <class T> Modular operator/(const T& other) const { return *this / initModular(other); } template <class T> friend Modular operator/(const T& other, const Modular& m) { return m.initModular(other) / m; } friend istream& operator>>(istream& in, Modular& m) { in >> m.val; m.val %= m.MODVALUE; if (m.val < 0) m.val += m.MODVALUE; return in; } friend ostream& operator<<(ostream& out, const Modular& m) { return out << m.val; } Modular() { val = 0; MODVALUE = 0; } Modular(long long val, long long MOD) : MODVALUE(MOD), val((val % MOD + MOD) % MOD) {} }; using Mint = Modular; inline ll binpow(ll b, ll p, ll mod) { b %= mod; ll ans = 1; for (; p > 0; p >>= 1) { if (p & 1) { ans *= b; ans %= mod; } b *= b; b %= mod; } return ans; } inline ll max(ll a, int b) { return (a > b ? a : b); } inline ll max(int a, ll b) { return (a > b ? a : b); } inline ll min(ll a, int b) { return (a < b ? a : b); } inline ll min(int a, ll b) { return (a < b ? a : b); } template <class T> inline bool chkmin(T& x, const T& y) { return y < x ? x = y, 1 : 0; } template <class T> inline bool chkmax(T& x, const T& y) { return x < y ? x = y, 1 : 0; } } // namespace namespace IO { struct InputWrapper { private: istream& in; public: template <class T> inline void _R(T& x) { in >> x; } template <class T1, class T2> inline void _R(pair<T1, T2>& x) { _R(x.first); _R(x.second); } template <class T> inline void _R(vector<T>& x) { for (auto& i : x) _R(i); } template <class T> inline void _R(deque<T>& x) { for (auto& i : x) _R(i); } inline void R() {} template <class T1, class... T2> inline void R(T1& x, T2&... y) { _R(x); R(y...); } template <class... T> inline void operator()(T&... x) { R(x...); } InputWrapper(istream& in) : in(in) {} } R(cin); struct OutputWrapper { private: ostream& out; public: template <class Container> inline void printContainer(const Container& x) { bool isFirst = 1; for (auto i : x) { if (!isFirst) out << ; isFirst = 0; _W(i); } } template <class T> inline void _W(const T& x) { out << x; } template <class T1, class T2> inline void _W(const pair<T1, T2>& p) { _W(p.first); _W( ); _W(p.second); } template <class... T> inline void _W(const vector<T...>& x) { printContainer(x); } template <class... T> inline void _W(const deque<T...>& x) { printContainer(x); } template <class... T> inline void _W(const forward_list<T...>& x) { printContainer(x); } template <class... T> inline void _W(const list<T...>& x) { printContainer(x); } template <class... T> inline void _W(const set<T...>& x) { printContainer(x); } template <class... T> inline void _W(const multiset<T...>& x) { printContainer(x); } template <class... T> inline void _W(const unordered_set<T...>& x) { printContainer(x); } template <class... T> inline void _W(const unordered_multiset<T...>& x) { printContainer(x); } template <class... T> inline void _W(const map<T...>& x) { printContainer(x); } template <class... T> inline void _W(const multimap<T...>& x) { printContainer(x); } template <class... T> inline void _W(const unordered_map<T...>& x) { printContainer(x); } template <class... T> inline void _W(const unordered_multimap<T...>& x) { printContainer(x); } inline void W() { out << n ; } template <class T> inline void W(const T& x) { _W(x); W(); } template <class T1, class... T2> inline void W(const T1& x, const T2&... y) { _W(x); _W( ); W(y...); } template <class... T> inline void operator()(const T&... x) { W(x...); } OutputWrapper(ostream& out) : out(out) {} } W(cout), D(cerr); } // namespace IO using namespace IO; namespace outputFormat { inline string Case(int tc) { return Case # + to_string(tc) + : ; } inline string YN(bool b) { return b ? Yes : No ; } } // namespace outputFormat using namespace outputFormat; namespace std { template <class T1, class T2> struct hash<pair<T1, T2>> { std::size_t operator()(pair<T1, T2> _) const { return hash<T1>{}(_.first) ^ hash<T2>{}(_.second); } }; } // namespace std int main() { int t; cin >> t; while (t--) { int n; R(n); string s, t; R(s, t); vector<vector<Mint>> cnt_table(n + 1, vector<Mint>(2 * n + 7, Mint(0, MOD107))), sum_table = cnt_table; vector<Mint*> cnt(n + 1), sum(n + 1); for (int i = 0; i <= n; i++) { cnt[i] = &cnt_table[i][n + 3]; sum[i] = &sum_table[i][n + 3]; } cnt[0][0] = 1; vector<vector<bool>> can(4, vector<bool>(n + 1, false)); for (int i = 1; i <= n; i++) { can[0][i] = s[i - 1] != 1 && t[i - 1] != 1 ; can[1][i] = s[i - 1] != 1 && t[i - 1] != 0 ; can[2][i] = s[i - 1] != 0 && t[i - 1] != 1 ; can[3][i] = s[i - 1] != 0 && t[i - 1] != 0 ; if (i % 2 == 1) swap(can[1][i], can[2][i]); } for (int i = 1; i <= n; i++) { for (int j = -i; j <= i; j++) { if (can[0][i]) { cnt[i][j] += cnt[i - 1][j]; sum[i][j] += sum[i - 1][j]; } if (can[1][i]) { cnt[i][j] += cnt[i - 1][j - 1]; sum[i][j] += sum[i - 1][j - 1] + cnt[i - 1][j - 1] * i * (abs(j) < abs(j - 1) ? +1 : -1); } if (can[2][i]) { cnt[i][j] += cnt[i - 1][j + 1]; sum[i][j] += sum[i - 1][j + 1] + cnt[i - 1][j + 1] * i * (abs(j) < abs(j + 1) ? +1 : -1); } if (can[3][i]) { cnt[i][j] += cnt[i - 1][j]; sum[i][j] += sum[i - 1][j]; } } } W(sum[n][0]); } return 0; } static auto __init__ = []() { ios::sync_with_stdio(false); cin.tie(0); cout << fixed << setprecision(10); return 42; }(); |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); int t; cin >> t; while (t--) { long long x, y; cin >> x >> y; if (x == y + 1) { cout << NO n ; } else { cout << YES n ; } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EDFXTP_BLACKBOX_V
`define SKY130_FD_SC_LS__EDFXTP_BLACKBOX_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__edfxtp (
Q ,
CLK,
D ,
DE
);
output Q ;
input CLK;
input D ;
input DE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__EDFXTP_BLACKBOX_V
|
`timescale 1ns/10ps
module vga_pll_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'outclk2'
output wire outclk_2,
// interface 'outclk3'
output wire outclk_3,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("normal"),
.number_of_clocks(4),
.output_clock_frequency0("25.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("40.000000 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("33.333333 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("100.000000 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_3, outclk_2, outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
module FpuFp64FromInt(
clk,
enable,
is32,
src,
dst
);
input clk;
input enable;
input is32;
input[63:0] src;
output[63:0] dst;
reg sgn;
reg sgnc;
reg[12:0] exa;
reg[12:0] exb;
reg[12:0] exc;
reg[12:0] exm;
reg[63:0] tFracA;
reg[63:0] tFracB;
reg[63:0] tFracC;
reg[63:0] tFracA1;
reg[63:0] tFracB1;
reg[63:0] tFracC1;
reg[63:0] tFracC2;
reg[63:0] tFracC2_A; //32
reg[63:0] tFracC2_B; //16
reg[63:0] tFracC2_C; //8
reg[63:0] tFracC2_D; //4
reg[63:0] tFracC2_E; //2
reg[12:0] tExc_A;
reg[12:0] tExc_B;
reg[12:0] tExc_C;
reg[12:0] tExc_D;
reg[12:0] tExc_E;
reg[63:0] tDst;
assign dst = tDst;
always @ (clk && enable)
begin
sgnc = 0;
if(is32)
begin
if(src[31])
begin
sgn = 1;
tFracC2[63:32] = 0;
tFracC2[31:0] = ~(src[31:0]);
exm = 1023 + 52;
end
else
begin
sgn = 0;
tFracC2[63:32] = 0;
tFracC2[31:0] = src[31:0];
exm = 1023 + 52;
end
end
else
begin
if(src[63])
begin
sgn = 1;
tFracC2[63:0] = ~(src[63:0]);
exm = 1023 + 52;
end
else
begin
sgn = 0;
tFracC2[63:0] = src[63:0];
exm = 1023 + 52;
end
end
if(tFracC2[52:0]==0)
begin
sgnc=0;
tFracC=0;
exc=0;
end
else
if(tFracC2[63:52]==0)
begin
if(tFracC2[52:21]==0)
begin
tFracC2_A=tFracC2<<32;
tExc_A=exm-32;
end
else
begin
tFracC2_A=tFracC2;
tExc_A=exm;
end
if(tFracC2_A[52:37]==0)
begin
tFracC2_B=tFracC2_A<<16;
tExc_B=tExc_A-16;
end
else
begin
tFracC2_B=tFracC2_A;
tExc_B=tExc_A;
end
if(tFracC2_B[52:45]==0)
begin
tFracC2_C=tFracC2_B<<8;
tExc_C=tExc_B-8;
end
else
begin
tFracC2_C=tFracC2_B;
tExc_C=tExc_B;
end
if(tFracC2_C[52:49]==0)
begin
tFracC2_D=tFracC2_C<<4;
tExc_D=tExc_C-4;
end
else
begin
tFracC2_D=tFracC2_C;
tExc_D=tExc_C;
end
if(tFracC2_D[52:51]==0)
begin
tFracC2_E=tFracC2_D<<2;
tExc_E=tExc_D-2;
end
else
begin
tFracC2_E=tFracC2_D;
tExc_E=tExc_D;
end
if(tFracC2_E[52]==0)
begin
tFracC=tFracC2_E<<1;
exc=tExc_E-1;
end
else
begin
tFracC=tFracC2_E;
exc=tExc_E;
end
end
else
begin
tFracC2_B=tFracC2;
tExc_B=exm;
if(tFracC2_B[63:60]!=0)
begin
tFracC2_C=tFracC2_B>>8;
tExc_C=tExc_B+8;
end
else
begin
tFracC2_C=tFracC2_B;
tExc_C=tExc_B;
end
if(tFracC2_C[59:56]!=0)
begin
tFracC2_D=tFracC2_C>>4;
tExc_D=tExc_C+4;
end
else
begin
tFracC2_D=tFracC2_C;
tExc_D=tExc_C;
end
if(tFracC2_D[55:54]==0)
begin
tFracC2_E=tFracC2_D>>2;
tExc_E=tExc_D+2;
end
else
begin
tFracC2_E=tFracC2_D;
tExc_E=tExc_D;
end
if(tFracC2_E[53])
begin
tFracC=tFracC2_E>>1;
exc=tExc_E+1;
end
else
begin
tFracC=tFracC2_E;
exc=tExc_E;
end
end
if(exc[12])
begin
tDst[63:0]=64'h0;
end
else if(exc[11])
begin
tDst[63]=sgnc;
tDst[62:0]=63'h7FF0_0000_0000_0000;
end
else
begin
tDst[63]=sgnc;
tDst[62:52]=exc[10:0];
tDst[51:0]=tFracC[51:0];
end
// dst=tDst;
end
always @ (posedge clk)
begin
// dst <= tDst;
end
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module controls 16x2 character LCD on the Altera DE2 Board. *
* *
******************************************************************************/
module niosII_system_character_lcd_0 (
// Inputs
clk,
reset,
address,
chipselect,
read,
write,
writedata,
// Bidirectionals
LCD_DATA,
// Outputs
LCD_ON,
LCD_BLON,
LCD_EN,
LCD_RS,
LCD_RW,
readdata,
waitrequest
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CURSOR_ON = 1'b1;
parameter BLINKING_ON = 1'b0;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input address;
input chipselect;
input read;
input write;
input [ 7: 0] writedata;
// Bidirectionals
inout [ 7: 0] LCD_DATA; // LCD Data bus 8 bits
// Outputs
output LCD_ON; // LCD Power ON/OFF
output LCD_BLON; // LCD Back Light ON/OFF
output LCD_EN; // LCD Enable
output LCD_RS; // LCD 0-Command/1-Data Select
output LCD_RW; // LCD 1-Read/0-Write Select
output [ 7: 0] readdata;
output waitrequest;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
localparam LCD_STATE_0_IDLE = 3'h0,
LCD_STATE_1_INITIALIZE = 3'h1,
LCD_STATE_2_START_CHECK_BUSY = 3'h2,
LCD_STATE_3_CHECK_BUSY = 3'h3,
LCD_STATE_4_BEGIN_TRANSFER = 3'h4,
LCD_STATE_5_TRANSFER = 3'h5,
LCD_STATE_6_COMPLETE = 3'h6;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire transfer_complete;
wire done_initialization;
wire init_send_command;
wire [ 8: 0] init_command;
wire send_data;
wire [ 7: 0] data_received;
// Internal Registers
reg initialize_lcd_display;
reg [ 7: 0] data_to_send;
reg rs;
reg rw;
// State Machine Registers
reg [ 2: 0] ns_lcd_controller;
reg [ 2: 0] s_lcd_controller;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
s_lcd_controller <= LCD_STATE_0_IDLE;
else
s_lcd_controller <= ns_lcd_controller;
end
always @(*)
begin
// Defaults
ns_lcd_controller = LCD_STATE_0_IDLE;
case (s_lcd_controller)
LCD_STATE_0_IDLE:
begin
if (initialize_lcd_display)
ns_lcd_controller = LCD_STATE_1_INITIALIZE;
else if (chipselect)
ns_lcd_controller = LCD_STATE_2_START_CHECK_BUSY;
else
ns_lcd_controller = LCD_STATE_0_IDLE;
end
LCD_STATE_1_INITIALIZE:
begin
if (done_initialization)
ns_lcd_controller = LCD_STATE_6_COMPLETE;
else
ns_lcd_controller = LCD_STATE_1_INITIALIZE;
end
LCD_STATE_2_START_CHECK_BUSY:
begin
if (transfer_complete == 1'b0)
ns_lcd_controller = LCD_STATE_3_CHECK_BUSY;
else
ns_lcd_controller = LCD_STATE_2_START_CHECK_BUSY;
end
LCD_STATE_3_CHECK_BUSY:
begin
if ((transfer_complete) && (data_received[7]))
ns_lcd_controller = LCD_STATE_2_START_CHECK_BUSY;
else if ((transfer_complete) && (data_received[7] == 1'b0))
ns_lcd_controller = LCD_STATE_4_BEGIN_TRANSFER;
else
ns_lcd_controller = LCD_STATE_3_CHECK_BUSY;
end
LCD_STATE_4_BEGIN_TRANSFER:
begin
if (transfer_complete == 1'b0)
ns_lcd_controller = LCD_STATE_5_TRANSFER;
else
ns_lcd_controller = LCD_STATE_4_BEGIN_TRANSFER;
end
LCD_STATE_5_TRANSFER:
begin
if (transfer_complete)
ns_lcd_controller = LCD_STATE_6_COMPLETE;
else
ns_lcd_controller = LCD_STATE_5_TRANSFER;
end
LCD_STATE_6_COMPLETE:
begin
ns_lcd_controller = LCD_STATE_0_IDLE;
end
default:
begin
ns_lcd_controller = LCD_STATE_0_IDLE;
end
endcase
end
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
initialize_lcd_display <= 1'b1;
else if (done_initialization)
initialize_lcd_display <= 1'b0;
end
always @(posedge clk)
begin
if (reset)
data_to_send <= 8'h00;
else if (s_lcd_controller == LCD_STATE_1_INITIALIZE)
data_to_send <= init_command[7:0];
else if (s_lcd_controller == LCD_STATE_4_BEGIN_TRANSFER)
data_to_send <= writedata[7:0];
end
always @(posedge clk)
begin
if (reset)
rs <= 1'b0;
else if (s_lcd_controller == LCD_STATE_1_INITIALIZE)
rs <= init_command[8];
else if (s_lcd_controller == LCD_STATE_2_START_CHECK_BUSY)
rs <= 1'b0;
else if (s_lcd_controller == LCD_STATE_4_BEGIN_TRANSFER)
rs <= address;
end
always @(posedge clk)
begin
if (reset)
rw <= 1'b0;
else if (s_lcd_controller == LCD_STATE_1_INITIALIZE)
rw <= 1'b0;
else if (s_lcd_controller == LCD_STATE_2_START_CHECK_BUSY)
rw <= 1'b1;
else if (s_lcd_controller == LCD_STATE_4_BEGIN_TRANSFER)
rw <= ~write;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign readdata = data_received;
assign waitrequest = chipselect & (s_lcd_controller != LCD_STATE_6_COMPLETE);
// Internal Assignments
assign send_data =
(s_lcd_controller == LCD_STATE_1_INITIALIZE) ? init_send_command :
(s_lcd_controller == LCD_STATE_3_CHECK_BUSY) ? 1'b1 :
(s_lcd_controller == LCD_STATE_5_TRANSFER) ? 1'b1 : 1'b0;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_character_lcd_communication Char_LCD_Comm (
// Inputs
.clk (clk),
.reset (reset),
.data_in (data_to_send),
.enable (send_data),
.rs (rs),
.rw (rw),
.display_on (1'b1),
.back_light_on (1'b1),
// Bidirectionals
.LCD_DATA (LCD_DATA),
// Outputs
.LCD_ON (LCD_ON),
.LCD_BLON (LCD_BLON),
.LCD_EN (LCD_EN),
.LCD_RS (LCD_RS),
.LCD_RW (LCD_RW),
.data_out (data_received),
.transfer_complete (transfer_complete)
);
altera_up_character_lcd_initialization Char_LCD_Init (
// Inputs
.clk (clk),
.reset (reset),
.initialize_LCD_display (initialize_lcd_display),
.command_was_sent (transfer_complete),
// Bidirectionals
// Outputs
.done_initialization (done_initialization),
.send_command (init_send_command),
.the_command (init_command)
);
defparam
Char_LCD_Init.CURSOR_ON = CURSOR_ON,
Char_LCD_Init.BLINKING_ON = BLINKING_ON;
endmodule
|
#include <bits/stdc++.h> using namespace std; inline long long read() { register long long w = 1, x = 0, ch = getchar(); for (; ch < 0 || ch > 9 ; ch = getchar()) if (ch == - ) w = -1; for (; ch >= 0 && ch <= 9 ; ch = getchar()) x = x * 10 + ch - 0 ; return x * w; } const long long MAXN = (long long)7e2 + 10; const long long MOD = (long long)1e9 + 7; const long long INF = 0x3f3f3f3f3f3f3f3f; char s[MAXN]; long long n, ans, digit[MAXN], Dec[MAXN], divv[MAXN][10], f[MAXN][MAXN][10][2]; inline void Init() { cin >> s + 1; n = strlen(s + 1); for (register long long i = 1; i <= n; i++) { digit[i] = s[i] - 0 ; } } inline void DP() { Dec[0] = 1; for (register long long i = 1; i <= n; i++) { Dec[i] = Dec[i - 1] * 10 % MOD; } for (register long long i = 0; i <= 9; i++) { f[0][0][i][1] = 1; } for (register long long i = 0; i < n; i++) { for (register long long j = 0; j <= i; j++) { for (register long long x = 1; x <= 9; x++) { for (register long long l = 0; l <= 1; l++) { for (register long long k = 0; k <= (l ? digit[i + 1] : 9); k++) { f[i + 1][j + (k >= x)][x][(k == digit[i + 1]) && l] += f[i][j][x][l]; f[i + 1][j + (k >= x)][x][(k == digit[i + 1]) && l] %= MOD; } } } } } for (register long long x = 1; x <= 9; x++) { for (register long long j = 1; j <= n; j++) { for (register long long i = j; i <= n; i++) divv[j][x] = (divv[j][x] + f[n][i][x][1] + f[n][i][x][0]) % MOD; } } for (register long long i = 1; i <= n; i++) { for (register long long x = 1; x <= 9; x++) { ans = (ans + (divv[i][x] - divv[i][x + 1] + MOD) % MOD * Dec[i - 1] % MOD * x % MOD) % MOD; } } printf( %lld n , ans); } signed main() { Init(); DP(); return 0; } |
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module ac97_framer(
input sys_clk,
input sys_rst,
/* to transceiver */
input down_ready,
output down_stb,
output reg down_sync,
output reg down_data,
/* frame data */
input en,
output reg next_frame,
input addr_valid,
input [19:0] addr,
input data_valid,
input [19:0] data,
input pcmleft_valid,
input [19:0] pcmleft,
input pcmright_valid,
input [19:0] pcmright
);
reg [7:0] bitcounter;
reg slot_bit;
always @(*) begin
case(bitcounter)
8'd16: slot_bit = addr[19];
8'd17: slot_bit = addr[18];
8'd18: slot_bit = addr[17];
8'd19: slot_bit = addr[16];
8'd20: slot_bit = addr[15];
8'd21: slot_bit = addr[14];
8'd22: slot_bit = addr[13];
8'd23: slot_bit = addr[12];
8'd24: slot_bit = addr[11];
8'd25: slot_bit = addr[10];
8'd26: slot_bit = addr[9];
8'd27: slot_bit = addr[8];
8'd28: slot_bit = addr[7];
8'd29: slot_bit = addr[6];
8'd30: slot_bit = addr[5];
8'd31: slot_bit = addr[4];
8'd32: slot_bit = addr[3];
8'd33: slot_bit = addr[2];
8'd34: slot_bit = addr[1];
8'd35: slot_bit = addr[0];
8'd36: slot_bit = data[19];
8'd37: slot_bit = data[18];
8'd38: slot_bit = data[17];
8'd39: slot_bit = data[16];
8'd40: slot_bit = data[15];
8'd41: slot_bit = data[14];
8'd42: slot_bit = data[13];
8'd43: slot_bit = data[12];
8'd44: slot_bit = data[11];
8'd45: slot_bit = data[10];
8'd46: slot_bit = data[9];
8'd47: slot_bit = data[8];
8'd48: slot_bit = data[7];
8'd49: slot_bit = data[6];
8'd50: slot_bit = data[5];
8'd51: slot_bit = data[4];
8'd52: slot_bit = data[3];
8'd53: slot_bit = data[2];
8'd54: slot_bit = data[1];
8'd55: slot_bit = data[0];
8'd56: slot_bit = pcmleft[19];
8'd57: slot_bit = pcmleft[18];
8'd58: slot_bit = pcmleft[17];
8'd59: slot_bit = pcmleft[16];
8'd60: slot_bit = pcmleft[15];
8'd61: slot_bit = pcmleft[14];
8'd62: slot_bit = pcmleft[13];
8'd63: slot_bit = pcmleft[12];
8'd64: slot_bit = pcmleft[11];
8'd65: slot_bit = pcmleft[10];
8'd66: slot_bit = pcmleft[9];
8'd67: slot_bit = pcmleft[8];
8'd68: slot_bit = pcmleft[7];
8'd69: slot_bit = pcmleft[6];
8'd70: slot_bit = pcmleft[5];
8'd71: slot_bit = pcmleft[4];
8'd72: slot_bit = pcmleft[3];
8'd73: slot_bit = pcmleft[2];
8'd74: slot_bit = pcmleft[1];
8'd75: slot_bit = pcmleft[0];
8'd76: slot_bit = pcmright[19];
8'd77: slot_bit = pcmright[18];
8'd78: slot_bit = pcmright[17];
8'd79: slot_bit = pcmright[16];
8'd80: slot_bit = pcmright[15];
8'd81: slot_bit = pcmright[14];
8'd82: slot_bit = pcmright[13];
8'd83: slot_bit = pcmright[12];
8'd84: slot_bit = pcmright[11];
8'd85: slot_bit = pcmright[10];
8'd86: slot_bit = pcmright[9];
8'd87: slot_bit = pcmright[8];
8'd88: slot_bit = pcmright[7];
8'd89: slot_bit = pcmright[6];
8'd90: slot_bit = pcmright[5];
8'd91: slot_bit = pcmright[4];
8'd92: slot_bit = pcmright[3];
8'd93: slot_bit = pcmright[2];
8'd94: slot_bit = pcmright[1];
8'd95: slot_bit = pcmright[0];
default: slot_bit = 1'bx;
endcase
end
reg in_slot;
always @(posedge sys_clk) begin
if(sys_rst) begin
bitcounter <= 8'd0;
down_sync <= 1'b0;
down_data <= 1'b0;
in_slot <= 1'b0;
end else begin
if(en)
next_frame <= 1'b0;
if(down_ready & en) begin
if(bitcounter == 8'd255)
next_frame <= 1'b1;
if(bitcounter == 8'd255)
down_sync <= 1'b1;
if(bitcounter == 8'd15)
down_sync <= 1'b0;
if(bitcounter == 8'd15)
in_slot <= 1'b1;
if(bitcounter == 8'd95)
in_slot <= 1'b0;
case({down_sync, in_slot})
2'b10: begin
/* Tag */
case(bitcounter[3:0])
4'h0: down_data <= 1'b1; // Frame valid
4'h1: down_data <= addr_valid; // Slot 1 valid
4'h2: down_data <= data_valid; // Slot 2 valid
4'h3: down_data <= pcmleft_valid; // Slot 3 valid
4'h4: down_data <= pcmright_valid; // Slot 4 valid
default: down_data <= 1'b0;
endcase
//$display("PCMRIGHT_V: %b", pcmright_valid);
end
2'b01:
/* Active slot */
down_data <= slot_bit;
default: down_data <= 1'b0;
endcase
bitcounter <= bitcounter + 8'd1;
end
end
end
assign down_stb = en;
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// Simple Asynchronous Serial Comm. Device ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/sasc/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: sasc_top.v,v 1.2 2006/03/30 02:47:07 rudi Exp $
//
// $Date: 2006/03/30 02:47:07 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: sasc_top.v,v $
// Revision 1.2 2006/03/30 02:47:07 rudi
// Thanks to Darren O'Connor of SPEC, Inc. for fixing a bug
// with the DPLL and data alignment:
//
// You were right that it was a problem with the dpll. I found
// that it was possible to get two baud clocks (rx_sio_ce) during
// one bit period. I fixed the problem by delaying the input data
// signal with a shift register and using that in the equations
// for the "change" variable that controls the DPLL FSM.
//
// Revision 1.1.1.1 2002/09/16 16:16:42 rudi
// Initial Checkin
//
//
//
//
//
//
//
//
`timescale 1ns / 100ps
/*
Serial IO Interface
===============================
RTS I Request To Send
CTS O Clear to send
TD I Transmit Data
RD O Receive Data
*/
module sasc_top( clk, rst_n,
// SIO
rxd_i, txd_o, cts_i, rts_o,
// External Baud Rate Generator
sio_ce, sio_ce_x4,
// Internal Interface
din_i, dout_o, re_i, we_i, full_o, empty_o);
input clk;
input rst_n;
input rxd_i;
output txd_o;
input cts_i;
output rts_o;
input sio_ce;
input sio_ce_x4;
input [7:0] din_i;
output [7:0] dout_o;
input re_i, we_i;
output full_o, empty_o;
///////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
parameter START_BIT = 1'b0,
STOP_BIT = 1'b1,
IDLE_BIT = 1'b1;
wire [7:0] txd_p;
reg load;
wire load_e;
reg [9:0] hold_reg;
wire txf_empty;
reg txd_o;
reg shift_en;
reg [3:0] tx_bit_cnt;
reg rxd_s, rxd_r;
wire start;
reg [3:0] rx_bit_cnt;
reg rx_go;
reg [9:0] rxr;
reg rx_valid, rx_valid_r;
wire rx_we;
wire rxf_full;
reg rts_o;
reg txf_empty_r;
reg shift_en_r;
reg rxd_r1;
reg change;
reg rx_sio_ce_d, rx_sio_ce_r1, rx_sio_ce_r2, rx_sio_ce;
reg [1:0] dpll_state, dpll_next_state;
reg [5:0] rxd_dly; //New input delay used to ensure no baud clocks
// occur twice in one baud period
///////////////////////////////////////////////////////////////////
//
// IO Fifo's
//
sasc_fifo4 tx_fifo( .clk( clk ),
.rst_n( rst_n ),
.clr( 1'b0 ),
.din( din_i ),
.we( we_i ),
.dout( txd_p ),
.re( load_e ),
.full( full_o ),
.empty( txf_empty )
);
sasc_fifo4 rx_fifo( .clk( clk ),
.rst_n( rst_n ),
.clr( 1'b0 ),
.din( rxr[9:2] ),
.we( rx_we ),
.dout( dout_o ),
.re( re_i ),
.full( rxf_full ),
.empty( empty_o )
);
///////////////////////////////////////////////////////////////////
//
// Transmit Logic
//
always @(posedge clk)
if(!rst_n) txf_empty_r <= 1'b1;
else
if(sio_ce) txf_empty_r <= txf_empty;
always @(posedge clk)
load <= !txf_empty_r & !shift_en & !cts_i;
assign load_e = load & sio_ce;
always @(posedge clk)
if(load_e) hold_reg <= {STOP_BIT, txd_p, START_BIT};
else
if(shift_en & sio_ce) hold_reg <= {IDLE_BIT, hold_reg[9:1]};
always @(posedge clk)
if(!rst_n) txd_o <= IDLE_BIT;
else
if(sio_ce)
if(shift_en | shift_en_r) txd_o <= hold_reg[0];
else txd_o <= IDLE_BIT;
always @(posedge clk)
if(!rst_n) tx_bit_cnt <= 4'h9;
else
if(load_e) tx_bit_cnt <= 4'h0;
else
if(shift_en & sio_ce) tx_bit_cnt <= tx_bit_cnt + 4'h1;
always @(posedge clk)
shift_en <= (tx_bit_cnt != 4'h9);
always @(posedge clk)
if(!rst_n) shift_en_r <= 1'b0;
else
if(sio_ce) shift_en_r <= shift_en;
///////////////////////////////////////////////////////////////////
//
// Recieve Logic
//
always @(posedge clk)
begin
rxd_dly[5:1] <= rxd_dly[4:0];
rxd_dly[0] <= rxd_i;
rxd_s <= rxd_dly[5]; // rxd_s = delay 1
rxd_r <= rxd_s; // rxd_r = delay 2
end
assign start = (rxd_r == IDLE_BIT) & (rxd_s == START_BIT);
always @(posedge clk)
if(!rst_n) rx_bit_cnt <= 4'ha;
else
if(!rx_go & start) rx_bit_cnt <= 4'h0;
else
if(rx_go & rx_sio_ce) rx_bit_cnt <= rx_bit_cnt + 4'h1;
always @(posedge clk)
rx_go <= (rx_bit_cnt != 4'ha);
always @(posedge clk)
rx_valid <= (rx_bit_cnt == 4'h9);
always @(posedge clk)
rx_valid_r <= rx_valid;
assign rx_we = !rx_valid_r & rx_valid & !rxf_full;
always @(posedge clk)
if(rx_go & rx_sio_ce) rxr <= {rxd_s, rxr[9:1]};
always @(posedge clk)
rts_o <= rxf_full;
///////////////////////////////////////////////////////////////////
//
// Reciever DPLL
//
// Uses 4x baud clock to lock to incoming stream
// Edge detector
always @(posedge clk)
if(sio_ce_x4) rxd_r1 <= rxd_s;
always @(posedge clk)
if(!rst_n)
change <= 1'b0;
else if ((rxd_dly[1] != rxd_r1) || (rxd_dly[1] != rxd_s))
change <= 1'b1;
else if(sio_ce_x4)
change <= 1'b0;
// DPLL FSM
always @(posedge clk or negedge rst_n)
if(!rst_n) dpll_state <= 2'h1;
else
if(sio_ce_x4) dpll_state <= dpll_next_state;
always @(dpll_state or change)
begin
rx_sio_ce_d = 1'b0;
case(dpll_state)
2'h0:
if(change) dpll_next_state = 3'h0;
else dpll_next_state = 3'h1;
2'h1:begin
rx_sio_ce_d = 1'b1;
if(change) dpll_next_state = 3'h3;
else dpll_next_state = 3'h2;
end
2'h2:
if(change) dpll_next_state = 3'h0;
else dpll_next_state = 3'h3;
2'h3:
if(change) dpll_next_state = 3'h0;
else dpll_next_state = 3'h0;
endcase
end
// Compensate for sync registers at the input - allign sio
// clock enable to be in the middle between two bit changes ...
always @(posedge clk)
rx_sio_ce_r1 <= rx_sio_ce_d;
always @(posedge clk)
rx_sio_ce_r2 <= rx_sio_ce_r1;
always @(posedge clk)
rx_sio_ce <= rx_sio_ce_r1 & !rx_sio_ce_r2;
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename A, typename B> string to_string(pair<A, B> p); template <typename A, typename B, typename C> string to_string(tuple<A, B, C> p); template <typename A, typename B, typename C, typename D> string to_string(tuple<A, B, C, D> p); string to_string(const string& second) { return + second + ; } string to_string(char c) { string second; second += c; return second; } string to_string(const char* second) { return to_string((string)second); } string to_string(bool b) { return (b ? 1 : 0 ); } string to_string(vector<bool> v) { bool first = true; string res = { ; for (long long i = 0; i < static_cast<long long>(v.size()); i++) { if (!first) { res += , ; } first = false; res += to_string(v[i]); } res += } ; return res; } template <size_t N> string to_string(bitset<N> v) { string res = ; for (size_t i = 0; i < N; i++) { res += static_cast<char>( 0 + v[i]); } return res; } template <typename A> string to_string(A v) { bool first = true; string res = { ; for (const auto& x : v) { if (!first) { res += , ; } first = false; res += to_string(x); } res += } ; return res; } template <typename A, typename B> string to_string(pair<A, B> p) { return ( + to_string(p.first) + , + to_string(p.second) + ) ; } template <typename A, typename B, typename C> string to_string(tuple<A, B, C> p) { return ( + to_string(get<0>(p)) + , + to_string(get<1>(p)) + , + to_string(get<2>(p)) + ) ; } template <typename A, typename B, typename C, typename D> string to_string(tuple<A, B, C, D> p) { return ( + to_string(get<0>(p)) + , + to_string(get<1>(p)) + , + to_string(get<2>(p)) + , + to_string(get<3>(p)) + ) ; } void debug_out() { cerr << n ; } template <typename Head, typename... Tail> void debug_out(Head H, Tail... T) { cerr << << to_string(H); debug_out(T...); } void Clearing_out() { return; } template <typename Head, typename... Tail> void Clearing_out(Head& H, Tail&... T) { H.clear(); Clearing_out(T...); } struct custom_hash { static uint64_t splitmix64(uint64_t x) { x += 0x9e3779b97f4a7c15; x = (x ^ (x >> 30)) * 0xbf58476d1ce4e5b9; x = (x ^ (x >> 27)) * 0x94d049bb133111eb; return x ^ (x >> 31); } size_t operator()(uint64_t x) const { static const uint64_t FIXED_RANDOM = chrono::steady_clock::now().time_since_epoch().count(); return splitmix64(x + FIXED_RANDOM); } }; void time() { cerr << Time elapsed: << 1.0 * clock() / CLOCKS_PER_SEC << s. n ; } void hi() { static long long i = 0; cerr << Check Point : << ++i << n ; return; } long long stoi1(string str) { bool negative; if (str[0] == - ) { negative = true; str = str.substr(1); } else { negative = false; } long long n = str.length(); long long number = 0; long long pos = 1; for (long long i = n - 1; i >= 0; i--) { number = number + (str[i] - 0 ) * pos; pos = pos * 10; } if (negative) number = -number; return number; } long long power(long long a, long long n) { long long res = 1; while (n > 0) { if (n % 2 != 0) { res = res * a; n--; } else if (n % 2 == 0) { a = a * a; n = n / 2; } } return res; } pair<long long, long long> min(vector<long long> v, bool first = true) { bool last = !first; long long mini = 1000000000000000007; long long mini_index = -1; long long n = (long long)v.size(); for (long long i = 0; i < n; i++) { if ((mini > v[i] && first) || (mini >= v[i] && last)) { mini = v[i]; mini_index = i; } } return {mini_index, mini}; } pair<long long, long long> max(vector<long long> v, bool first = true) { bool last = !first; long long maxi = -1000000000000000007; long long maxi_index = -1; long long n = (long long)v.size(); for (long long i = 0; i < n; i++) { if ((maxi < v[i] && first) || (maxi <= v[i] && last)) { maxi = v[i]; maxi_index = i; } } return {maxi_index, maxi}; } long long sum(vector<long long> v, long long start = 0, long long last = -1) { if (last == -1) last = (long long)v.size() - 1; long long ans = 0; for (long long i = start; i <= last; i++) { ans = ans + v[i]; } return ans; } long long len(vector<long long> v) { return (long long)v.size(); } long long rand(long long a, long long b) { return a + rand() % (b - a + 1); } vector<long long> generate_random_vector() { vector<long long> v; long long n = rand(10, 20); set<long long> used; for (long long i = 0; i < n; ++i) { long long x; do { x = rand(10, 1000); } while (used.count(x)); v.push_back(x); used.insert(x); } return v; } const long long max_size = 1e6 + 10000; const double eps = 1e-18; signed main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t; t = 1; while (t--) { long long n; cin >> n; vector<long long> v(n); for (long long i = 0; i < n; i++) { cin >> v[i]; } vector<vector<long long>> v1(n); long long new_index = 0; v1[new_index].push_back(v[0]); new_index++; vector<long long> v_back; v_back.push_back(-v[0]); for (long long i = 1; i < n; i++) { long long index = lower_bound(v_back.begin(), v_back.end(), -v[i]) - v_back.begin(); if (index == (long long)v_back.size()) { v1[new_index].push_back(v[i]); v_back.push_back(-v[i]); new_index++; continue; } else { v1[index].push_back(v[i]); v_back[index] = -v[i]; } } for (auto x : v1) { if (x.size() == 0) continue; for (auto y : x) { cout << y << ; } cout << n ; } } time(); return 0; } |
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact :
//-------------------------------------------------------------------
// Filename : cabac_mvd_neigh_2p_18x8.v
// Author : guo yong
// Created : 2013-07
// Description : cabac memory for top macroblock mvd
//
//-------------------------------------------------------------------
`include "enc_defines.v"
`define MEM_TOP_DEPTH 9
module cabac_mvd_top_2p_18xMB_X_TOTAL(
//input
clk ,
r_en ,
r_addr ,
w_en ,
w_addr ,
w_data ,
//output
r_data
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input clk ; //clock signal
input r_en ; //read enable signal
input [`MEM_TOP_DEPTH-1:0] r_addr ; //read address of memory
input w_en ; //write enable signal
input [`MEM_TOP_DEPTH-1:0] w_addr ; //write address of memory
input [2*(`FMV_WIDTH+1)-1:0] w_data ; //write data of memory, {mb_type_top, chroma_mode_top, cbp_top} = {4, 4, 9}
output [2*(`FMV_WIDTH+1)-1:0] r_data ; //read data from memory
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
rf_2p #(.Addr_Width(`MEM_TOP_DEPTH), .Word_Width(18))
rf_2p_mvd_top_18xMB_X_TOTAL (
.clka ( clk ),
.cena_i ( ~r_en ),
.addra_i ( r_addr ),
.dataa_o ( r_data ),
.clkb ( clk ),
.cenb_i ( ~w_en ),
.wenb_i ( ~w_en ),
.addrb_i ( w_addr ),
.datab_i ( w_data )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T1, typename T2> inline void chkmin(T1 &x, T2 y) { if (x > y) x = y; } template <typename T1, typename T2> inline void chkmax(T1 &x, T2 y) { if (x < y) x = y; } inline int readChar(); template <class T = int> inline T readInt(); template <class T> inline void writeInt(T x, char end = 0); inline void writeChar(int x); inline void writeWord(const char *s); static const int buf_size = 4096; inline int getChar() { static char buf[buf_size]; static int len = 0, pos = 0; if (pos == len) { pos = 0, len = fread(buf, 1, buf_size, stdin); } if (pos == len) { return -1; } return buf[pos++]; } inline int readChar() { int c = getChar(); while (c <= 32) { c = getChar(); } return c; } template <class T> inline T readInt() { int s = 1, c = readChar(); T x = 0; if (c == - ) s = -1, c = getChar(); while ( 0 <= c && c <= 9 ) x = x * 10 + c - 0 , c = getChar(); return s == 1 ? x : -x; } static int write_pos = 0; static char write_buf[buf_size]; inline void writeChar(int x) { if (write_pos == buf_size) fwrite(write_buf, 1, buf_size, stdout), write_pos = 0; write_buf[write_pos++] = x; } template <class T> inline void writeInt(T x, char end) { if (x < 0) writeChar( - ), x = -x; char s[24]; int n = 0; while (x || !n) s[n++] = 0 + x % 10, x /= 10; while (n--) writeChar(s[n]); if (end) writeChar(end); } inline void writeWord(const char *s) { while (*s) writeChar(*s++); } struct Flusher { ~Flusher() { if (write_pos) fwrite(write_buf, 1, write_pos, stdout), write_pos = 0; } } flusher; using namespace std; const int MAXN = 100228; int n, m; int a[MAXN], ans[MAXN], lp[MAXN]; vector<pair<int, int> > vq[MAXN]; int main() { n = readInt(), m = readInt(); for (int i = 0; i < n; ++i) { lp[i] = -1; } for (int i = 0; i < m; ++i) { int l = readInt(), r = readInt(); l--, r--; lp[r] = l; } int q = readInt(); for (int i = 0; i < q; ++i) { int x = readInt(), y = readInt(); x--, y--; vq[y].push_back({x, i}); } for (int i = 0; i < n; ++i) { a[i] = i; } for (int i = 0; i < n; ++i) { int x = lp[i]; for (int j = 0; j <= x; ++j) { a[j] = a[j] >= x ? i : a[j]; } for (auto p : vq[i]) { ans[p.second] = a[p.first]; } } for (int i = 0; i < q; ++i) { writeInt(ans[i] + 1, n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; using ull = unsigned long long; using ld = long double; template <typename T> ostream& operator<<(ostream& os, const vector<T>& v) { for (const auto& x : v) os << x << ; return os << n ; } template <typename T> void operator>>(istream& is, vector<T>& v) { for (auto& x : v) is >> x; } ll power(ll a, ll n) { if (n == 0) { return 1; } ll sqrt_a = pow(a, n / 2); if (n % 2 == 1) { return sqrt_a * sqrt_a * a; } else { return sqrt_a * sqrt_a; } } template <typename T> T sign(T a) { if (a < 0) return -1; if (a > 0) return 1; return 0; } template <typename T> T log_2(T n) { T i = 1; T j = 0; while (i < n) { i *= 2; ++j; } return j; } template <typename T> T mod(T a, T b) { T ans = a % b; return ans < 0 ? ans + b : ans; } ll gcd(ll a, ll b) { while (b) { a %= b; swap(a, b); } return a; } ll lcm(ll a, ll b) { return a / gcd(a, b) * b; } class Node { public: char symbol; bool passed = false; vector<ll> neighbores = vector<ll>(); }; template <typename T> class Compare { public: bool operator()(T& a, T& b) { if (a.first < b.first) { return true; } else if (a.first == b.first) { return a.second < b.second; } else { return false; } } }; vector<ll> divs(ll n) { vector<ll> ans; while (n != 1) { for (ll i = 2; i <= n; ++i) { if (n % i == 0) { ans.push_back(i); n /= i; break; } } } return ans; } void solve() { ll a, b, c; cin >> a >> b >> c; if (a < c) { cout << 1 ; } else { cout << -1 ; } if (b * a > c) { cout << b << n ; } else { cout << -1 n ; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ll t; cin >> t; while (t--) { solve(); } } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 1.01E6; vector<int> ans[MAXN]; char C[MAXN]; int A[MAXN]; int B[MAXN]; int n, top1, top2; int main(void) { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> (C + 1), n = strlen(C + 1); for (int i = 1; i <= n; ++i) { if (C[i] == 0 ) { if (top2 == 0) A[++top1] = i, ans[i].push_back(i); else { int nowPos = B[top2--]; ans[nowPos].push_back(i), A[++top1] = nowPos; } } else { if (top1 == 0) return puts( -1 ) * 0; int nowPos = A[top1--]; ans[nowPos].push_back(i), B[++top2] = nowPos; } } if (top2) return puts( -1 ) * 0; int o = 0; cout << top1 << n ; for (int i = 1; i <= top1; ++i) { int id = A[i]; cout << ans[id].size() << ; for (int a : ans[id]) cout << a << ; cout << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int mod = (int)1e9 + 7, maxn = (int)1e5 + 5; int a[maxn], d[maxn]; int mpow(int A, int N) { int ret = 1; while (N) { if (N & 1) ret = (ret * 1ll * A) % mod; A = (A * 1ll * A) % mod; N >>= 1; } return ret; } int main() { ios_base::sync_with_stdio(0); cin.clear(); int n; cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); int ans = 0; for (int i = maxn - 1; i > 0; i--) { int sz = 0; for (int j = 1; j * j <= i; j++) { if (i % j) continue; if (j != i) d[sz++] = j; if (j != 1 && j * j != i) d[sz++] = i / j; } sort(d, d + sz); int lim = lower_bound(a, a + n, i) - a; int cur = (mpow(sz + 1, n - lim) - mpow(sz, n - lim) + mod) % mod; for (int j = sz - 1; j >= 0; j--) { int idx = lower_bound(a, a + lim, d[j]) - a; cur = (cur * 1ll * mpow(j + 1, lim - idx)) % mod; lim = idx; } ans = (ans + cur) % mod; } cout << ans; } |
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate case with labels of x and z. Should be match
module main ();
reg error;
reg [2:0] val1,val2;
reg [2:0] result ;
always @( val1 )
case (val1)
3'b000: result = 0;
3'b001: result = 1 ;
3'b010: result = 2;
3'bx11: result = 4;
3'bz11: result = 5;
endcase
initial
begin
error = 0;
#1;
val1 = 3'b0;
#1;
if(result !== 0)
begin
$display("FAILED case 3.8D - case (expr) lab1: ");
error = 1;
end
#1;
val1 = 3'b001;
#1;
if(result !== 1)
begin
$display("FAILED case 3.8D - case (expr) lab2: ");
error = 1;
end
#1 ;
val1 = 3'b010;
#1;
if(result !== 2)
begin
$display("FAILED case 3.8D - case (expr) lab3: ");
error = 1;
end
#1 ;
val1 = 3'bz11;
#1;
if(result !== 5)
begin
$display("FAILED case 3.8D - case (expr) lab5: ");
error = 1;
end
#1 ;
val1 = 3'bx11;
#1;
if(result !== 4)
begin
$display("FAILED case 3.8D - case (expr) lab4: ");
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); const long long maxn = 3e6; const long long mod = 1e9 + 7; const long double PI = acos((long double)-1); long long pw(long long a, long long b, long long md = mod) { long long res = 1; while (b) { if (b & 1) { res = (a * res) % md; } a = (a * a) % md; b >>= 1; } return (res); } int n; long long l[maxn], r[maxn]; int32_t main() { ios::sync_with_stdio(false), cin.tie(0), cout.tie(0); cin >> n; for (int i = 0; i < n; i++) cin >> l[i]; for (int i = 0; i < n; i++) cin >> r[i]; long long p = 1, q = 0, sum = 0, sm = 0; for (int i = 0; i < n; i++) { if (i) { long long a = max(0LL, min(r[i], r[i - 1]) - max(l[i], l[i - 1]) + 1); long long b = (r[i] - l[i] + 1) * (r[i - 1] - l[i - 1] + 1) % mod; p = ((b - a + mod) % mod * pw(b, mod - 2)) % mod; } sum = (sum + p) % mod; sm = (sm + pw(p, 2) + (2LL * (p - 1) * (q - 1)) % mod + mod) % mod; q = p; } long long ans = (sum * (sum + 1) - sm + mod * 100LL) % mod; for (int i = 2; i < n; i++) { long long a = max(0LL, min({r[i], r[i - 1], r[i - 2]}) - max({l[i], l[i - 1], l[i - 2]}) + 1); long long b = max(0LL, r[i - 2] - l[i - 2] + 1); b = (b * max(0LL, r[i - 1] - l[i - 1] + 1)) % mod; b = (b * max(0LL, r[i] - l[i] + 1)) % mod; p = (a * pw(b, mod - 2)) % mod; ans = (ans + 2 * p) % mod; } cout << ans << n ; return (0); } |
#include <bits/stdc++.h> using namespace std; string a, b; int t; string ssort(string x) { if (x.size() & 1) return x; int len = x.size() / 2; string xx, yy; xx = ssort(x.substr(0, len)); yy = ssort(x.substr(len, len)); if (xx < yy) return xx + yy; else return yy + xx; } signed main() { cin >> a >> b; if (a == b) { printf( YES n ); return 0; } if (ssort(a) == ssort(b)) printf( YES n ); else printf( NO n ); } |
#include <bits/stdc++.h> using namespace std; int main(int argc, char* argv[]) { char dt[1002]; memset(dt, 0, sizeof(dt)); char gr[1002]; memset(gr, 0, sizeof(gr)); cin >> dt >> gr; int n = strlen(dt); int m = strlen(gr); map<char, int> dtc; map<char, int> gtc; for (int i = 0; i < n; ++i) { dtc[dt[i]]++; } for (int i = 0; i < m; ++i) { gtc[gr[i]]++; } int res = 0; map<char, int>::iterator it; for (it = gtc.begin(); it != gtc.end(); ++it) { char val = it->first; if (dtc[val] == 0) { cout << -1; return 0; } if (dtc[val] >= gtc[val]) res += gtc[val]; else res += dtc[val]; } cout << res << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFSTP_1_V
`define SKY130_FD_SC_HDLL__SDFSTP_1_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfstp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__sdfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfstp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfstp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFSTP_1_V
|
module top (
input wire i_clk,
input wire i_clkb,
input wire i_rst,
input wire i_ce,
output wire o_q1,
output wire o_q2,
input wire [11:0] io
);
// BUFGs
wire clk;
wire clkb;
BUFG bufg_1 (.I(i_clk), .O(clk));
BUFG bufg_2 (.I(i_clkb), .O(clkb));
// Generate IDDR cases
wire [11:0] q1;
wire [11:0] q2;
assign o_q1 = |q1;
assign o_q2 = |q2;
genvar sa, e, i, sr, inv;
generate begin
// SRTYPE
for (sa = 0; sa < 2; sa = sa + 1) begin
localparam SRTYPE = (sa != 0) ? "SYNC" : "ASYNC";
localparam sa_idx = sa;
IDDR_2CLK # (
.SRTYPE(SRTYPE)
) iddr_sr_type (
.C(clk), .CB(clkb), .CE(i_ce), .Q1(q1[sa_idx]), .Q2(q2[sa_idx]),
.D(io[sa_idx])
);
end
// DDR_CLK_EDGE
for (e = 0; e < 3; e = e + 1) begin
localparam EDGE = (e == 0) ? "SAME_EDGE" :
(e == 1) ? "SAME_EDGE_PIPELINED" :
/*(e == 2) ?*/ "OPPOSITE_EDGE";
localparam e_idx = 2 + e;
IDDR_2CLK # (
.DDR_CLK_EDGE(EDGE)
) iddr_edge (
.C(clk), .CB(clkb), .CE(i_ce), .Q1(q1[e_idx]), .Q2(q2[e_idx]),
.D(io[e_idx])
);
end
// Set, Reset or neither
for (sr = 0; sr < 3; sr = sr + 1) begin
localparam sr_idx = 5 + sr;
wire r;
wire s;
assign r = ((sr & 1) != 0) ? i_rst : 1'b0;
assign s = ((sr & 2) != 0) ? i_rst : 1'b0;
IDDR_2CLK iddr_sr (
.C(clk), .CB(clkb), .CE(i_ce), .Q1(q1[sr_idx]), .Q2(q2[sr_idx]),
.R(r), .S(s),
.D(io[sr_idx])
);
end
// INIT_Q1, INIT_Q2
for (i = 0; i < 2; i = i + 1) begin
localparam i_idx = 8 + i;
IDDR_2CLK # (
.INIT_Q1(i == 1),
.INIT_Q2(i != 1)
) iddr_init (
.C(clk), .CB(clkb), .CE(i_ce), .Q1(q1[i_idx]), .Q2(q2[i_idx]),
.D(io[i_idx])
);
end
// Inverted D
for (inv = 0; inv < 2; inv = inv + 1) begin
localparam inv_idx = 10 + inv;
IDDR_2CLK # (
.IS_D_INVERTED(inv != 0)
) iddr_inverted (
.C(clk), .CB(clkb), .CE(i_ce), .Q1(q1[inv_idx]), .Q2(q2[inv_idx]),
.D(io[inv_idx])
);
end
end endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; const int mod = 1e9 + 7; const int maxm = 2e5 + 5; const long long inf = 0x3f3f3f3f3f3f3f3f; int xx[] = {0, 0, 1, -1}; int yy[] = {1, -1, 0, 0}; int N, M, K; vector<pair<int, long long> > vec[maxn]; vector<int> V; vector<long long> S; int vis[maxn]; long long value[maxn]; void dfs(int u, int p, long long s) { if (vis[u]) { S.push_back(value[u] ^ s); return; } vis[u] = 1; V.push_back(u); value[u] = s; for (int i = 0; i < vec[u].size(); i++) { int v = vec[u][i].first; long long w = vec[u][i].second; if (v == p) continue; dfs(v, u, s ^ w); } } long long ans; void work() { int i2 = 0; long long A = 0; for (int j = 0; j < S.size(); j++) A |= S[j]; for (int i = 0; i < 60; i++) { int s = -1; for (int j = i2; j < S.size(); j++) { long long v = S[j]; if (v & (1ll << i)) { s = j; } } if (s == -1) continue; swap(S[i2], S[s]); for (int j = i2 + 1; j < S.size(); j++) { long long &v = S[j]; if (v & (1ll << i)) { v ^= S[i2]; } } i2++; } for (int i = 0; i < 60; i++) { if (A & (1ll << i)) { ans += (1ll << i) % mod * ((1ll << i2 - 1) % mod) % mod * (1ll * V.size() * (V.size() - 1) / 2 % mod); ans %= mod; } else { int X = 0, Y = 0; for (int j = 0; j < V.size(); j++) { int v = V[j]; if (value[v] & (1ll << i)) { X++; } else Y++; } ans += 1ll * X * Y % mod * ((1ll << i2) % mod) % mod * ((1ll << i) % mod); ans %= mod; } } } int main(int argc, char *argv[]) { if (argc > 1) { freopen(argv[1], r , stdin); } cin >> N >> M; for (int i = 0; i < M; i++) { int a, b; long long c; scanf( %d%d%lld , &a, &b, &c); vec[b].push_back(make_pair(a, c)); vec[a].push_back(make_pair(b, c)); } for (int i = 1; i <= N; i++) { V.clear(); S.clear(); if (vis[i]) continue; dfs(i, 0, 0); work(); } cout << ans << endl; return 0; } |
// +----------------------------------------------------------------------------
// GNU General Public License
// -----------------------------------------------------------------------------
// This file is part of uDLX (micro-DeLuX) soft IP-core.
//
// uDLX is free soft IP-core: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// uDLX soft core is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with uDLX. If not, see <http://www.gnu.org/licenses/>.
// +----------------------------------------------------------------------------
// PROJECT: uDLX core Processor
// ------------------------------------------------------------------------------
// FILE NAME : if_id.v
// KEYWORDS : instruction fetch, decode, pipeline, register
// -----------------------------------------------------------------------------
// PURPOSE : Fetch/Decode pipeline registers
// -----------------------------------------------------------------------------
module if_id_reg
#(
parameter PC_DATA_WIDTH = 20,
parameter INSTRUCTION_WIDTH = 32
)(
input clk, // Clock
input rst_n, // Asynchronous reset active low
input en,
input stall, // Indicates a stall insertion on the datapath
input flush, // Force flush in pipeline registers
input [INSTRUCTION_WIDTH-1:0] inst_mem_data_in, // SRAM input data
input [PC_DATA_WIDTH-1:0] pc_in, // Value of Program Counter
output reg [PC_DATA_WIDTH-1:0] new_pc_out, // Updated value of the Program Counter
output reg [INSTRUCTION_WIDTH-1:0] instruction_reg_out // CPU core fetched instruction
);
always@(posedge clk or negedge rst_n)begin
if(!rst_n) begin
new_pc_out <= 0;
instruction_reg_out <= 0;
end else if((!stall)&en)begin
new_pc_out <= pc_in;
// if(flush)begin
// instruction_reg_out <= 0;
// end
// else begin
instruction_reg_out <= inst_mem_data_in;
// end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O41A_BEHAVIORAL_V
`define SKY130_FD_SC_LS__O41A_BEHAVIORAL_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o41a (
X ,
A1,
A2,
A3,
A4,
B1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
and and0 (and0_out_X, or0_out, B1 );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O41A_BEHAVIORAL_V |
module autoinst_vertrees_slv
(/*AUTOARG*/
// Outputs
i2c_mst_data, i2c_read, i2c_slv_scl_out, i2c_slv_sda_out, i2c_spc_scl_state, i2c_start,
i2c_strobe, slv_bit_st, slv_put, i2c_spc_scl_fall, i2c_spc_sda_state, i2c_spc_start,
i2c_spc_stop,
// Inputs
ck_ref, i2c_slv_data, i2c_slv_scl_in, i2c_slv_sda_in, r_i2c_spc_scl_low, rpt_hold, rpt_sda,
rst_ref, test_mode
);
input ck_ref; // To u_spc of i2c_slv_pin_ctrl.v, ...
input [7:0] i2c_slv_data; // To u_misc of ddc_slv_misc.v
input i2c_slv_scl_in; // To u_spc of i2c_slv_pin_ctrl.v
input i2c_slv_sda_in; // To u_spc of i2c_slv_pin_ctrl.v
input [4:0] r_i2c_spc_scl_low; // To u_spc of i2c_slv_pin_ctrl.v
input rpt_hold; // To u_misc of ddc_slv_misc.v
input rpt_sda; // To u_misc of ddc_slv_misc.v
input rst_ref; // To u_spc of i2c_slv_pin_ctrl.v, ...
input test_mode; // To u_spc of i2c_slv_pin_ctrl.v
output [7:0] i2c_mst_data; // From u_misc of ddc_slv_misc.v
output i2c_read; // From u_misc of ddc_slv_misc.v
output i2c_slv_scl_out; // From u_spc of i2c_slv_pin_ctrl.v
output i2c_slv_sda_out; // From u_spc of i2c_slv_pin_ctrl.v
output i2c_spc_scl_state; // From u_spc of i2c_slv_pin_ctrl.v
output i2c_start; // From u_misc of ddc_slv_misc.v
output i2c_strobe; // From u_misc of ddc_slv_misc.v
output slv_bit_st; // From u_misc of ddc_slv_misc.v
output slv_put; // From u_misc of ddc_slv_misc.v
output i2c_spc_scl_fall; // From u_spc of i2c_slv_pin_ctrl.v
output i2c_spc_sda_state; // From u_spc of i2c_slv_pin_ctrl.v
output i2c_spc_start; // From u_spc of i2c_slv_pin_ctrl.v
output i2c_spc_stop; // From u_spc of i2c_slv_pin_ctrl.v
endmodule // ddc_slv
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; set<int> s; for (int i = 0; i < n; i++) { int x; cin >> x; if (x != 0) s.insert(x); } cout << s.size(); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKBUF_PP_SYMBOL_V
`define SKY130_FD_SC_LS__CLKBUF_PP_SYMBOL_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__clkbuf (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKBUF_PP_SYMBOL_V
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for priority_encoder
*/
module test_priority_encoder;
// Parameters
localparam WIDTH = 32;
localparam LSB_HIGH_PRIORITY = 0;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [WIDTH-1:0] input_unencoded = 0;
// Outputs
wire output_valid;
wire [$clog2(WIDTH)-1:0] output_encoded;
wire [WIDTH-1:0] output_unencoded;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
input_unencoded
);
$to_myhdl(
output_valid,
output_encoded,
output_unencoded
);
// dump file
$dumpfile("test_priority_encoder.lxt");
$dumpvars(0, test_priority_encoder);
end
priority_encoder #(
.WIDTH(WIDTH),
.LSB_HIGH_PRIORITY(LSB_HIGH_PRIORITY)
)
UUT (
.input_unencoded(input_unencoded),
.output_valid(output_valid),
.output_encoded(output_encoded),
.output_unencoded(output_unencoded)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; struct SegTree { const int INF = 1e9; vector<pair<int, int>> max_vc; vector<int> add; int h = 1; pair<int, int> combine(pair<int, int> a, pair<int, int> b) { if (a.first == b.first) return {a.first, a.second + b.second}; else return max(a, b); } void push(int i) { max_vc[i].first += add[i]; if (i < h) { add[2 * i] += add[i]; add[2 * i + 1] += add[i]; } add[i] = 0; } SegTree(int n, int v) { while (h < n) h <<= 1; max_vc.resize(2 * h, {v, 1}); add.resize(2 * h, 0); for (int i = h - 1; i > 0; --i) max_vc[i] = combine(max_vc[2 * i], max_vc[2 * i + 1]); } void recAdd(int a, int b, int v, int i, int ia, int ib) { push(i); if (ib < a || b < ia) return; if (a <= ia && ib <= b) { add[i] += v; push(i); } else { int im = (ia + ib) >> 1; recAdd(a, b, v, 2 * i, ia, im); recAdd(a, b, v, 2 * i + 1, im + 1, ib); max_vc[i] = combine(max_vc[2 * i], max_vc[2 * i + 1]); } } pair<int, int> recGet(int a, int b, int i, int ia, int ib) { push(i); if (ib < a || b < ia) return {-INF, 0}; if (a <= ia && ib <= b) return max_vc[i]; int im = (ia + ib) >> 1; return combine(recGet(a, b, 2 * i, ia, im), recGet(a, b, 2 * i + 1, im + 1, ib)); } void addInt(int a, int b, int v) { recAdd(a, b, v, 1, 0, h - 1); } pair<int, int> getInt(int a, int b) { return recGet(a, b, 1, 0, h - 1); } }; int pre[300005], b[300005]; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; SegTree seg(n, 0); vector<pair<int, int>> maxes; long long res = 0; for (int i = 1; i <= n; ++i) { int a; cin >> a; pre[i] = max(pre[i - 1], b[a]); b[a] = i; int p = pre[i] + 1; seg.addInt(p, i, 1); seg.addInt(i, i, -a); pair<int, int> maxes_add = {a, i}; while ((!maxes.empty()) && (maxes.back().first <= a)) { seg.addInt(maxes.back().second, maxes_add.second - 1, -(a - maxes.back().first)); maxes_add.second = maxes.back().second; maxes.pop_back(); } maxes.push_back(maxes_add); pair<int, int> sub = seg.getInt(p, i); if (sub.first == 0) res += sub.second; } cout << res << n ; } |
//*****************************************************************************
// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: iodrp_controller.v
// /___/ /\ Date Last Modified: $Date: 2010/11/26 18:25:50 $
// \ \ / \ Date Created: Mon Feb 9 2009
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: Xilinx reference design for IODRP controller for v0.9 device
//
//Reference:
//
// Revision: Date: Comment
// 1.0: 02/06/09: Initial version for MIG wrapper.
// 1.1: 02/01/09: updates to indentations.
// 1.2: 02/12/09: changed non-blocking assignments to blocking ones
// for state machine always block. Also, assigned
// intial value to load_shift_n to avoid latch
// End Revision
//*******************************************************************************
`timescale 1ps/1ps
module iodrp_controller(
input wire [7:0] memcell_address,
input wire [7:0] write_data,
output reg [7:0] read_data,
input wire rd_not_write,
input wire cmd_valid,
output wire rdy_busy_n,
input wire use_broadcast,
input wire sync_rst,
input wire DRP_CLK,
output reg DRP_CS,
output wire DRP_SDI, //output to IODRP SDI pin
output reg DRP_ADD,
output reg DRP_BKST,
input wire DRP_SDO //input from IODRP SDO pin
);
reg [7:0] memcell_addr_reg; // Register where memcell_address is captured during the READY state
reg [7:0] data_reg; // Register which stores the write data until it is ready to be shifted out
reg [7:0] shift_through_reg; // The shift register which shifts out SDO and shifts in SDI.
// This register is loaded before the address or data phase, but continues
// to shift for a writeback of read data
reg load_shift_n; // The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO
reg addr_data_sel_n; // The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg
reg [2:0] bit_cnt; // The counter for which bit is being shifted during address or data phase
reg rd_not_write_reg;
reg AddressPhase; // This is set after the first address phase has executed
reg capture_read_data;
(* FSM_ENCODING="one-hot" *) reg [2:0] state, nextstate;
wire [7:0] data_out_mux; // The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg
wire DRP_SDI_pre; // added so that DRP_SDI output is only active when DRP_CS is active
localparam READY = 3'h0;
localparam DECIDE = 3'h1;
localparam ADDR_PHASE = 3'h2;
localparam ADDR_TO_DATA_GAP = 3'h3;
localparam ADDR_TO_DATA_GAP2 = 3'h4;
localparam ADDR_TO_DATA_GAP3 = 3'h5;
localparam DATA_PHASE = 3'h6;
localparam ALMOST_READY = 3'h7;
localparam IOI_DQ0 = 5'h01;
localparam IOI_DQ1 = 5'h00;
localparam IOI_DQ2 = 5'h03;
localparam IOI_DQ3 = 5'h02;
localparam IOI_DQ4 = 5'h05;
localparam IOI_DQ5 = 5'h04;
localparam IOI_DQ6 = 5'h07;
localparam IOI_DQ7 = 5'h06;
localparam IOI_DQ8 = 5'h09;
localparam IOI_DQ9 = 5'h08;
localparam IOI_DQ10 = 5'h0B;
localparam IOI_DQ11 = 5'h0A;
localparam IOI_DQ12 = 5'h0D;
localparam IOI_DQ13 = 5'h0C;
localparam IOI_DQ14 = 5'h0F;
localparam IOI_DQ15 = 5'h0E;
localparam IOI_UDQS_CLK = 5'h1D;
localparam IOI_UDQS_PIN = 5'h1C;
localparam IOI_LDQS_CLK = 5'h1F;
localparam IOI_LDQS_PIN = 5'h1E;
//synthesis translate_off
reg [32*8-1:0] state_ascii;
always @ (state) begin
case (state)
READY :state_ascii <= "READY";
DECIDE :state_ascii <= "DECIDE";
ADDR_PHASE :state_ascii <= "ADDR_PHASE";
ADDR_TO_DATA_GAP :state_ascii <= "ADDR_TO_DATA_GAP";
ADDR_TO_DATA_GAP2 :state_ascii <= "ADDR_TO_DATA_GAP2";
ADDR_TO_DATA_GAP3 :state_ascii <= "ADDR_TO_DATA_GAP3";
DATA_PHASE :state_ascii <= "DATA_PHASE";
ALMOST_READY :state_ascii <= "ALMOST_READY";
endcase // case(state)
end
//synthesis translate_on
/*********************************************
* Input Registers
*********************************************/
always @ (posedge DRP_CLK) begin
if(state == READY) begin
memcell_addr_reg <= memcell_address;
data_reg <= write_data;
rd_not_write_reg <= rd_not_write;
end
end
assign rdy_busy_n = (state == READY);
/*********************************************
* Shift Registers / Bit Counter
*********************************************/
assign data_out_mux = addr_data_sel_n ? memcell_addr_reg : data_reg;
always @ (posedge DRP_CLK) begin
if(sync_rst)
shift_through_reg <= 8'b0;
else begin
if (load_shift_n) //Assume the shifter is either loading or shifting, bit 0 is shifted out first
shift_through_reg <= data_out_mux;
else
shift_through_reg <= {DRP_SDO, shift_through_reg[7:1]};
end
end
always @ (posedge DRP_CLK) begin
if (((state == ADDR_PHASE) | (state == DATA_PHASE)) & !sync_rst)
bit_cnt <= bit_cnt + 1;
else
bit_cnt <= 3'b000;
end
always @ (posedge DRP_CLK) begin
if(sync_rst) begin
read_data <= 8'h00;
// capture_read_data <= 1'b0;
end
else begin
// capture_read_data <= (state == DATA_PHASE);
// if(capture_read_data)
if(state == ALMOST_READY)
read_data <= shift_through_reg;
// else
// read_data <= read_data;
end
end
always @ (posedge DRP_CLK) begin
if(sync_rst) begin
AddressPhase <= 1'b0;
end
else begin
if (AddressPhase) begin
// Keep it set until we finish the cycle
AddressPhase <= AddressPhase && ~(state == ALMOST_READY);
end
else begin
// set the address phase when ever we finish the address phase
AddressPhase <= (state == ADDR_PHASE) && (bit_cnt == 3'b111);
end
end
end
/*********************************************
* DRP Signals
*********************************************/
always @ (posedge DRP_CLK) begin
DRP_ADD <= (nextstate == ADDR_PHASE);
DRP_CS <= (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE);
if (state == READY)
DRP_BKST <= use_broadcast;
end
// assign DRP_SDI_pre = (DRP_CS)? shift_through_reg[0] : 1'b0; //if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance
// assign DRP_SDI = (rd_not_write_reg & DRP_CS & !DRP_ADD)? DRP_SDO : DRP_SDI_pre; //If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance
assign DRP_SDI = shift_through_reg[0]; // The new read method only requires that we shift out the address and the write data
/*********************************************
* State Machine
*********************************************/
always @ (*) begin
addr_data_sel_n = 1'b0;
load_shift_n = 1'b0;
case (state)
READY: begin
if(cmd_valid)
nextstate = DECIDE;
else
nextstate = READY;
end
DECIDE: begin
load_shift_n = 1;
addr_data_sel_n = 1;
nextstate = ADDR_PHASE;
end
ADDR_PHASE: begin
if(&bit_cnt)
if (rd_not_write_reg)
if (AddressPhase)
// After the second pass go to end of statemachine
nextstate = ALMOST_READY;
else
// execute a second address phase for the read access.
nextstate = DECIDE;
else
nextstate = ADDR_TO_DATA_GAP;
else
nextstate = ADDR_PHASE;
end
ADDR_TO_DATA_GAP: begin
load_shift_n = 1;
nextstate = ADDR_TO_DATA_GAP2;
end
ADDR_TO_DATA_GAP2: begin
load_shift_n = 1;
nextstate = ADDR_TO_DATA_GAP3;
end
ADDR_TO_DATA_GAP3: begin
load_shift_n = 1;
nextstate = DATA_PHASE;
end
DATA_PHASE: begin
if(&bit_cnt)
nextstate = ALMOST_READY;
else
nextstate = DATA_PHASE;
end
ALMOST_READY: begin
nextstate = READY;
end
default: begin
nextstate = READY;
end
endcase
end
always @ (posedge DRP_CLK) begin
if(sync_rst)
state <= READY;
else
state <= nextstate;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 1; long double pi = 3.141592653589793238; int main() { long long t; cin >> t; while (t--) { long long x; cin >> x; long double ans; long double n = 2.0000000000000 * (long double)x; long double angle = (180.000000000000000 - 360.00000000000000 / n) / 2.00000000000000; angle = angle * pi / 180.000000000000; long double side = (long double)0.500000000000 / (long double)cosl(angle); if (x % 2 != 0) { ans = (long double)2.000000000 * side; } else { side = side * (long double)sinl(angle); ans = (long double)2.000000000 * side; } cout << to_string(ans) << n ; } } |
// Test array variables inside a constant function
module constfunc14();
function [7:0] concat1(input [7:0] value);
reg [3:0] tmp[1:2];
begin
{tmp[1], tmp[2]} = {value[3:0], value[7:4]};
{concat1[3:0], concat1[7:4]} = {tmp[2], tmp[1]};
end
endfunction
function [7:0] concat2(input [7:0] value);
reg [3:0] tmp[1:2];
begin
{tmp[1], tmp[3]} = {value[3:0], value[7:4]};
{concat2[3:0], concat2[7:4]} = {tmp[3], tmp[1]};
end
endfunction
function [7:0] concat3(input [7:0] value);
reg [3:0] tmp[1:2];
begin
{tmp['bx], tmp[1]} = {value[3:0], value[7:4]};
{concat3[3:0], concat3[7:4]} = {tmp['bx], tmp[1]};
end
endfunction
localparam res1 = concat1(8'ha5);
localparam res2 = concat2(8'ha5);
localparam res3 = concat2(8'ha5);
reg failed = 0;
initial begin
$display("%h", res1); if (res1 !== 8'h5a) failed = 1;
$display("%h", res2); if (res2 !== 8'h5x) failed = 1;
$display("%h", res3); if (res3 !== 8'h5x) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21BA_4_V
`define SKY130_FD_SC_LP__O21BA_4_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog wrapper for o21ba with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o21ba.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o21ba_4 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o21ba_4 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21BA_4_V
|
#include <bits/stdc++.h> using namespace std; template <typename T> T BigMod(T b, T p, T m) { if (p == 0) return 1; if (p % 2 == 0) { T s = BigMod(b, p / 2, m); return ((s % m) * (s % m)) % m; } return ((b % m) * (BigMod(b, p - 1, m) % m)) % m; } template <typename T> T ModInv(T b, T m) { return BigMod(b, m - 2, m); } template <typename T> T gcd(T a, T b) { if (!b) return a; return gcd(b, a % b); } int a[1004]; vector<int> v; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int t, i, j, e, n, k, l, ed, res, p, y, n1, n2, sum, cnt, dif, idx, x, m, val, cst, st, sz; cin >> x; for (i = 1; i <= x; i++) { cin >> a[i]; if (i > 1) v.push_back(a[i] - a[i - 1]); } bool fl = 0; sz = v.size(); for (i = 0; i <= sz - 1; i++) { if (i > 0) { if (v[i] == v[i - 1]) continue; fl = 1; break; } } if (fl) cout << a[x] << endl; else cout << a[x] + v[sz - 1] << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__XOR2_TB_V
`define SKY130_FD_SC_HVL__XOR2_TB_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__xor2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hvl__xor2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__XOR2_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPVGND2_PP_SYMBOL_V
`define SKY130_FD_SC_LS__TAPVGND2_PP_SYMBOL_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__tapvgnd2 (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPVGND2_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const int N = 1e5 + 4; const long long MOD = 998244353; bool ans[2 * N]; long long POW(long long base, long long exponent) { long long result = 1; while (exponent > 0) { if (exponent % 2 == 1) result = (result * base) % MOD; exponent = exponent >> 1; base = (base * base) % MOD; } return result; } long long Inv(long long x) { return POW(x, MOD - 2); } void BFS(int s, vector<int> &d, vector<int> edge[]) { d[s] = 0; queue<int> q; q.push(s); while (!q.empty()) { int v = q.front(); q.pop(); for (auto to : edge[v]) { if (d[to] == (int)1e9) { d[to] = d[v] + 1; q.push(to); } } } } int main() { std::ios::sync_with_stdio(false); cin.tie(0); int t; cin >> t; while (t--) { int n; cin >> n; int a[n]; for (int i = 0; i < n; i++) cin >> a[i]; int l = 0, r = n - 1, ls = 0, rs = 0, al = 0, b = 0, mv = 0; while (l <= r) { if (mv & 1) { rs = 0; while (rs <= ls and r >= l) rs += a[r--]; b += rs; mv++; } else { ls = 0; while (ls <= rs and l <= r) ls += a[l++]; al += ls; mv++; } } cout << mv << << al << << b << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); string s; char big = a ; string s1 = ; cin >> s; for (int i = s.size() - 1; i >= 0; i--) { if (int(s[i]) >= int(big)) { s1 += s[i]; big = s[i]; } } reverse(s1.begin(), s1.end()); cout << s1; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFRBP_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__DFRBP_PP_BLACKBOX_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFRBP_PP_BLACKBOX_V
|
/*******************************************************************
Company: UNSW
Original Author: Lingkan Gong
Project Name: XPCIe
Create Date: 15/07/2011
Design Name: adder
*******************************************************************/
`timescale 1ns/1ns
module adder
(
input clk ,
input rst ,
input [31:0] ain ,
input [31:0] bin ,
output reg [31:0] result ,
output reg [31:0] statistic
);
//-------------------------------------------------------------------
// Signal Declaration
//-------------------------------------------------------------------
reg [31:0] result_last;
//-------------------------------------------------------------------
// Main Computation
//-------------------------------------------------------------------
/* the result & result_last register */
always @(posedge clk or posedge rst) begin
if (rst) begin
result <= 32'h0;
result_last <= 32'h0;
end else begin
result <= ain + bin;
result_last <= result;
end
end
/* the statistic register */
always @(posedge clk or posedge rst) begin
if (rst) begin
statistic[31:16] <= 16'hc001;
statistic[15:0] <= 16'h0;
end else begin
if ( result != result_last ) begin
statistic[15:0] <= statistic[15:0] + 16'h1;
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2BB2AI_BEHAVIORAL_V
`define SKY130_FD_SC_HD__O2BB2AI_BEHAVIORAL_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__o2bb2ai (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire nand1_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
nand nand1 (nand1_out_Y, nand0_out, or0_out);
buf buf0 (Y , nand1_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2BB2AI_BEHAVIORAL_V |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:16777216 ) using namespace std; int n, k; char g[3][100005]; bool f; bool isval(int i, int j) { if (j >= n) return true; if (j < 0) return false; if (g[i][j] == X ) return false; return true; } void dfs(int i, int j, int t) { if (j >= n) f = true; else { g[i][j] = X ; if (j + k > t && isval((i + 1) % 2, j + k)) dfs((i + 1) % 2, (j + k), t + 1); if (j + 1 > t && isval(i, j + 1)) dfs(i, j + 1, t + 1); if (j - 1 > t && isval(i, j - 1)) dfs(i, (j - 1), t + 1); } } int main() { cin >> n >> k; for (int i = 0; i < 2; i++) cin >> g[i]; f = 0; dfs(0, 0, 0); if (!f) cout << NO << endl; else cout << YES << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int a[222], b[222]; int main() { int n, ans = 0; cin >> n; int p, q, r, s; for (int i = 0; i < n; i++) cin >> a[i] >> b[i]; for (int i = 0; i < n; i++) { p = q = r = s = 0; for (int j = 0; j < n; j++) { if (j == i) continue; if (a[j] > a[i] && b[j] == b[i]) p++; if (a[j] < a[i] && b[j] == b[i]) q++; if (a[j] == a[i] && b[j] > b[i]) r++; if (a[j] == a[i] && b[j] < b[i]) s++; } if (p && q && r && s) ans++; } cout << ans; return 0; } |
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: sun.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sun (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../sprites/sun.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../sprites/sun.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../sprites/sun.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sun.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sun.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sun.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sun.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sun_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sun_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; map<int, int> card; void init() { for (int i = 6, j = 1; i < 15; i++, j++) card.insert(make_pair(i, j)); } int isCard(char num) { int res = 0; if (num >= 0 && num <= 9 ) res = num - 0 ; else { if (num == T ) res = 10; else if (num == J ) res = 11; else if (num == Q ) res = 12; else if (num == K ) res = 13; else res = 14; } return res; } int main() { char mn; string s; cin >> s; mn = s[0]; cin >> s; int id[2]; char ch[2]; id[0] = isCard(s[0]); ch[0] = s[1]; cin >> s; id[1] = isCard(s[0]); ch[1] = s[1]; map<int, bool> mp; mp.insert(make_pair(mn, true)); if (mp.find(ch[0]) != mp.end() && mp.find(ch[1]) == mp.end()) cout << YES ; else if (mp.find(ch[0]) == mp.end() && mp.find(ch[1]) != mp.end()) cout << NO ; else if (ch[0] != ch[1]) cout << NO ; else if (id[0] > id[1]) cout << YES ; else cout << NO ; return 0; } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module feedforward_dadd_64ns_64ns_64_5_full_dsp
#(parameter
ID = 0,
NUM_STAGE = 5,
din0_WIDTH = 64,
din1_WIDTH = 64,
dout_WIDTH = 64
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [63:0] a_tdata;
wire b_tvalid;
wire [63:0] b_tdata;
wire r_tvalid;
wire [63:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
feedforward_ap_dadd_3_full_dsp_64 feedforward_ap_dadd_3_full_dsp_64_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1==='bx ? 'b0 : din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1==='bx ? 'b0 : din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Wed Sep 20 21:12:07 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_auto_pc_2_stub.v
// Design : zqynq_lab_1_design_auto_pc_2
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awregion, s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb,
s_axi_wlast, s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready,
s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock,
s_axi_arcache, s_axi_arprot, s_axi_arregion, s_axi_arqos, s_axi_arvalid, s_axi_arready,
s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr,
m_axi_awprot, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid,
m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot,
m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awregion[3:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [31:0]m_axi_awaddr;
output [2:0]m_axi_awprot;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [31:0]m_axi_araddr;
output [2:0]m_axi_arprot;
output m_axi_arvalid;
input m_axi_arready;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; int arr[n]; for (int i = 0; i < n; i++) { cin >> arr[i]; } if (arr[0] < arr[n - 1]) { cout << YES << endl; } else cout << NO << endl; } } |
`include "../include/tune.v"
// PentEvo project (c) NedoPC 2010
//
// generates horizontal vga sync, double the rate of TV horizontal sync
//
// KVIK PHEEKS just to double HSYNC not scan-doubling
// beginning of every other vga_hsync coincides with beginning of tv_hsync
// length is HSYNC_END clocks @ 28mhz
module vga_synch(
input clk,
output reg vga_hsync,
output reg scanout_start,
input wire hsync_start
);
// localparam HSYNC_BEG = 9'd00;
// localparam HSYNC_END = 10'd96;
// localparam SCANOUT_BEG = 10'd112;
localparam HSYNC_END = 10'd106;
localparam SCANOUT_BEG = 10'd159;
localparam HPERIOD = 10'd896;
reg [9:0] hcount;
initial
begin
hcount = 9'd0;
vga_hsync = 1'b0;
end
always @(posedge clk)
begin
if( hsync_start )
hcount <= 10'd2;
else if ( hcount==(HPERIOD-9'd1) )
hcount <= 10'd0;
else
hcount <= hcount + 9'd1;
end
always @(posedge clk)
begin
if( !hcount )
vga_hsync <= 1'b1;
else if( hcount==HSYNC_END )
vga_hsync <= 1'b0;
end
always @(posedge clk)
begin
if( hcount==SCANOUT_BEG )
scanout_start <= 1'b1;
else
scanout_start <= 1'b0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long N = 2e5 + 5; long long n, x, y, z, ans; long long a[N], b[N], par[N], sz[N]; long long get(long long x) { if (par[x] == x) return x; return par[x] = get(par[x]); } void merge(long long x, long long y) { long long root_a = get(x); long long root_b = get(y); if (root_a == root_b) { return; } if (sz[root_a] < sz[root_b]) { par[root_a] = par[root_b]; sz[root_b] += sz[root_a]; } else { par[root_b] = par[root_a]; sz[root_a] += sz[root_b]; } } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long t = 1; while (t--) { long long n; for (long long i = 0; i < N; i++) { par[i] = i; sz[i] = 1; } cin >> n; for (long long i = 1; i < n + 1; i++) cin >> a[i]; for (long long i = 1; i < n + 1; i++) cin >> b[i]; for (long long i = 1; i < n + 1; i++) { long long left = i - b[i]; long long right = i + b[i]; long long p1 = get(i); if (left >= 1) { long long p2 = get(left); if (p1 != p2) merge(p1, p2); } if (right <= n) { long long p2 = get(right); if (p1 != p2) merge(p1, p2); } } long long f = 0; for (long long i = 1; i < n + 1; i++) { long long p1 = get(i); long long p2 = get(a[i]); if (p1 != p2) f = 1; } if (f) cout << NO n ; else cout << YES n ; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2BB2O_1_V
`define SKY130_FD_SC_HS__A2BB2O_1_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog wrapper for a2bb2o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a2bb2o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a2bb2o_1 (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a2bb2o_1 (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2BB2O_1_V
|
#include <bits/stdc++.h> using namespace std; int II() { int q; scanf( %d , &q); return q; } void solve() { long long N, M; cin >> N >> M; long long ar[N + 10], br[N + 10], cr[N + 10]; for (long long i = 1; i <= N; i++) { cin >> ar[i] >> br[i] >> cr[i]; } long long mi = M, mx = M; ar[0] = 0; for (long long i = 1; i <= N; i++) { long long q = ar[i] - ar[i - 1]; mi = max(mi - q, br[i]); mx = min(mx + q, cr[i]); if (mi > cr[i] or mx < br[i]) { cout << NO << endl; return; } } cout << YES << endl; } int32_t main() { long long tt; cin >> tt; long long cas = 1; while (tt--) { solve(); } } |
#include <bits/stdc++.h> using namespace std; inline bool invowel(char ch) { ch = tolower(ch); return (ch == a || ch == e || ch == i || ch == o || ch == u ); } inline bool isprime(int n) { if (n < 2 || (n % 2 == 0 && n != 2)) return false; for (int i = 3; i * i <= n; i += 2) if (n % i == 0) return false; return true; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); int t; t = 1; while (t--) { int n, i; cin >> n; vector<int> x(n), y(n); for (i = 0; i < n; i++) { cin >> x[i] >> y[i]; } if (n & 1) { cout << No n ; break; } for (i = 0; i < n / 2; i++) { if (x[0] + x[n / 2] != x[i] + x[i + n / 2] || y[0] + y[n / 2] != y[i] + y[i + n / 2]) { cout << No n ; return 0; } } cout << Yes n ; } return 0; } |
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