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#include <bits/stdc++.h> using namespace std; char str[1000000]; int len; bool yes(char s[3], int ls, int le) { while (true) { start: int mid = le - ls - 1, i; if (le != len - 1) { if (s[0] != s[1]) return 0; } int c[3] = {0}, sd[2]; c[(s[1] - 0 ) ^ 1] += len - le - 1; for (i = ls + 1; i < le; i++) { if (str[i] == s[0]) return 0; } c[(s[0] - 0 ) ^ 1] += mid; for (i = 0; i < ls; i++) { if (str[i] == ? ) c[2]++; else c[str[i] - 0 ]++; } if (len & 1) sd[0] = len / 2 - 1, sd[1] = sd[0] + 1; else sd[0] = len / 2 - 1, sd[1] = sd[0]; if (s[0] != s[1]) { if (c[s[1] - 0 ] > sd[s[1] - 0 ]) return 0; if (c[s[0] - 0 ] > sd[s[0] - 0 ]) { if (str[ls] == ? ) { for (i = ls - 1; i >= 0; i--) { if (str[i] == ? || str[i] == s[0]) break; } if (i >= 0) { ls = i; goto start; } } return 0; } } else { if (s[0] == 0 ) { if (c[0] + c[2] < sd[0]) return 0; } else { if (c[1] + c[2] < sd[1]) return 0; } } return 1; } } bool ok(char s[3]) { int i, ls, le; for (le = len - 1; le >= 0; le--) { if (str[le] == s[1] || str[le] == ? ) break; } if (le <= 0) return 0; for (ls = le - 1; ls >= 0; ls--) { if (str[ls] == s[0] || str[ls] == ? ) break; } if (ls < 0) return 0; return yes(s, ls, le); } void run() { len = strlen(str); if (ok( 00 )) printf( 00 n ); if (ok( 01 )) printf( 01 n ); if (ok( 10 )) printf( 10 n ); if (ok( 11 )) printf( 11 n ); } int main() { scanf( %s , str); run(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long n, m, dx, dy, ans = 0, a, b; map<long long, int> num; double k; scanf( %lld%lld%lld%lld , &n, &m, &dx, &dy); long long x, y; for (int i = 0; i < m; i++) { scanf( %lld%lld , &x, &y); k = ((dy * x - dx * y) % n + n) % n; num[k]++; if (ans < num[k]) { a = x; b = y; ans = num[k]; } } printf( %lld %lld n , a, b); return 0; } |
#include <bits/stdc++.h> using namespace std; vector<long long int> small; vector<long long int> large; long long int largest(long long int digits, long long int sum) { long long int i; if (digits == 0) return sum; for (i = 9; i >= 0; i--) { if (sum >= i) { large.push_back(i); sum = sum - i; break; } } return largest(digits - 1, sum); } long long int smallest(long long int digits, long long int sum) { long long int i; if (digits == 0) return sum; for (i = 0; i <= 9; i++) { if (sum >= i && ((sum - i) <= 9 * (digits - 1))) { small.push_back(i); sum = sum - i; break; } } return smallest(digits - 1, sum); } int main() { long long int i, j, t, n, m, temp, sum1, sum; cin >> n >> sum; sum1 = sum; for (i = 1; i <= 9; i++) { if (sum >= i && ((sum - i) <= 9 * (n - 1))) { small.push_back(i); sum = sum - i; break; } } temp = smallest(n - 1, sum); if (temp > 0 || sum1 == 0) { if (sum1 == 0 && n == 1) cout << 0 << ; else cout << -1 << ; } else { for (i = 0; i < small.size(); i++) cout << small[i]; cout << ; } temp = largest(n, sum1); if (temp > 0 || sum1 == 0) { if (sum1 == 0 && n == 1) cout << 0 << endl; else cout << -1 << endl; } else { for (i = 0; i < large.size(); i++) cout << large[i]; cout << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21BO_4_V
`define SKY130_FD_SC_HD__A21BO_4_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21bo with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a21bo.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a21bo_4 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a21bo_4 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21BO_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O22AI_BLACKBOX_V
`define SKY130_FD_SC_HS__O22AI_BLACKBOX_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o22ai (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O22AI_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; bool endline = false; template <class T> istream& operator>>(istream& inp, vector<T>& v) { for (auto& it : v) inp >> it; return inp; } template <class T> ostream& operator<<(ostream& out, vector<T>& v) { for (auto& it : v) out << it << (endline ? n : ); return out; } template <class T, class U> istream& operator>>(istream& inp, pair<T, U>& v) { inp >> v.first >> v.second; return inp; } template <class T, class U> ostream& operator<<(ostream& out, pair<T, U>& v) { out << v.first << << v.second; return out; } void debug() { cout << endl; } template <typename H, typename... T> void debug(H a, T... b) { cout << a << ; debug(b...); } void FAST_IO(string filein = , string fileout = ) { if (fopen(filein.c_str(), r )) { freopen(filein.c_str(), r , stdin); freopen(fileout.c_str(), w , stdout); } cin.tie(0), cout.tie(0)->sync_with_stdio(0); } void Hollwo_Pelw(); signed main() { FAST_IO( .inp , .out ); int testcases = 1; for (int test = 1; test <= testcases; test++) { Hollwo_Pelw(); } return 0; } const int allmod[3] = {(int)1e9 + 7, 998244353, (int)1e9 + 9}; const int mod = allmod[1]; const int MAXN = 1e6 + 6; const int inf = 2e9; const long long linf = 1e18; long long n; void dofirst() { cout << First << endl; for (long long i = 1; i <= n; i++) cout << i << ; for (long long i = 1; i <= n; i++) cout << i << ; cout << endl; } vector<long long> pr[MAXN], adj[MAXN]; void addedge(long long u, long long v) { adj[u].push_back(v), adj[v].push_back(u); } long long vis[MAXN]; void dfs(long long u, long long c) { vis[u] = c; for (auto v : adj[u]) if (!vis[v]) dfs(v, 3 - c); } void check(long long v) { long long sum = 0; for (long long i = 1; i <= 2 * n; i++) if (vis[i] == v) sum += i; if (sum % (2 * n) == 0) { for (long long i = 1; i <= 2 * n; i++) if (vis[i] == v) cout << i << ; cout << endl; } } void dosecond() { cout << Second << endl; for (long long i = 1, p; i <= 2 * n; i++) cin >> p, pr[p].push_back(i); for (long long i = 1; i <= n; i++) addedge(pr[i][0], pr[i][1]), addedge(i, i + n); for (long long i = 1; i <= 2 * n; i++) if (!vis[i]) dfs(i, 1); check(1); check(2); } void getverdict() { long long x; cin >> x; if (!x) exit(0); } void Hollwo_Pelw() { cin >> n; if (n % 2 == 0) { dofirst(); } else { dosecond(); } getverdict(); } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { long long a, b, n, m; cin >> a >> b >> n >> m; if (m <= min(a, b) && n + m <= a + b) cout << Yes << endl; else cout << No << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long a[60][60], b[60][60], n, m; int main() { cin >> n >> m; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { cin >> a[i][j]; } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { cin >> b[i][j]; } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { long long mn = min(a[i][j], b[i][j]); long long mx = max(a[i][j], b[i][j]); a[i][j] = mn; b[i][j] = mx; } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { if (a[i][j] <= a[i][j - 1] || a[i][j] <= a[i - 1][j]) return cout << Impossible , 0; if (b[i][j] <= b[i][j - 1] || b[i][j] <= b[i - 1][j]) return cout << Impossible , 0; } } cout << Possible ; return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; const int N = 1e6 + 7; const int INF = 1e9 + 7; int n, m; int mid = 0; int ile[70]; long long mnoz = 1; long long ans = 0; bitset<128> maska; void backtrack(int poz = 1) { ans += mnoz; if (poz > mid) return; for (int i = poz; i <= mid; i++) { if (!ile[i]) continue; bitset<128> old_mask = maska; bitset<128> pom = (maska >> i) | (maska << (m - i)); if ((pom & maska).count() == 0) { int old_mnoz = mnoz; maska = maska | pom; mnoz = mnoz * ile[i]; if (mnoz > INF) mnoz %= INF; backtrack(i + 1); maska = old_mask; mnoz = old_mnoz; } } } void solve() { cin >> m >> m >> n; mid = (m + 1) / 2; for (int i = 0; i < n; i++) { int temp; cin >> temp; temp = temp % m; temp = min(temp, m - temp); ile[temp]++; } maska[0] = 1; backtrack(); cout << ans % INF << n ; } int main() { ios::sync_with_stdio(0); cin.tie(0); int t = 1; while (t--) { solve(); } } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2019 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
//======================================================================
module t;
integer file;
integer r_i;
byte r_upb[20:10];
byte r_dnb[20:10];
reg [13:0] r_ups[20:10];
reg [13:0] r_dns[10:20];
reg [30:0] r_upi[20:10];
reg [30:0] r_dni[10:20];
reg [61:0] r_upq[20:10];
reg [61:0] r_dnq[10:20];
reg [71:0] r_upw[20:10];
reg [71:0] r_dnw[10:20];
task clear;
// Initialize memories to zero,
// avoid differences between 2-state and 4-state.
r_i = ~0;
foreach (r_upb[i]) r_upb[i] = ~0;
foreach (r_dnb[i]) r_dnb[i] = ~0;
foreach (r_ups[i]) r_ups[i] = ~0;
foreach (r_dns[i]) r_dns[i] = ~0;
foreach (r_upi[i]) r_upi[i] = ~0;
foreach (r_dni[i]) r_dni[i] = ~0;
foreach (r_upq[i]) r_upq[i] = ~0;
foreach (r_dnq[i]) r_dnq[i] = ~0;
foreach (r_upw[i]) r_upw[i] = ~0;
foreach (r_dnw[i]) r_dnw[i] = ~0;
// Open file
$fclose(file);
file = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_fread.mem"}, "r");
if ($feof(file)) $stop;
endtask
task dump;
$write("Dump:");
$write("\n r_i:"); $write(" %x",r_i);
$write("\n r_upb:"); foreach (r_upb[i]) $write(" %x", r_upb[i]);
$write("\n r_dnb:"); foreach (r_dnb[i]) $write(" %x", r_dnb[i]);
$write("\n r_ups:"); foreach (r_ups[i]) $write(" %x", r_ups[i]);
$write("\n r_dns:"); foreach (r_dns[i]) $write(" %x", r_dns[i]);
$write("\n r_upi:"); foreach (r_upi[i]) $write(" %x", r_upi[i]);
$write("\n r_dni:"); foreach (r_dni[i]) $write(" %x", r_dni[i]);
$write("\n r_upq:"); foreach (r_upq[i]) $write(" %x", r_upq[i]);
$write("\n r_dnq:"); foreach (r_dnq[i]) $write(" %x", r_dnq[i]);
$write("\n r_upw:"); foreach (r_upw[i]) $write(" %x", r_upw[i]);
$write("\n r_dnw:"); foreach (r_dnw[i]) $write(" %x", r_dnw[i]);
$write("\n\n");
endtask
integer code;
initial begin
clear;
code = $fread(r_i, file); `checkd(code, 4);
code = $fread(r_upb, file); `checkd(code, 11);
code = $fread(r_dnb, file); `checkd(code, 11);
code = $fread(r_ups, file); `checkd(code, 22);
code = $fread(r_dns, file); `checkd(code, 22);
code = $fread(r_upi, file); `checkd(code, 44);
code = $fread(r_dni, file); `checkd(code, 44);
code = $fread(r_upq, file); `checkd(code, 88);
code = $fread(r_dnq, file); `checkd(code, 88);
code = $fread(r_upw, file); `checkd(code, 99);
code = $fread(r_dnw, file); `checkd(code, 99);
dump;
clear;
code = $fread(r_upb, file, 15); `checkd(code, 6);
// Bug where fread in if() broke.
if ($fread(r_ups, file, 15, 2) != 4) $stop;
dump;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool even(long long int x) { return (x % 2 == 0); } bool odd(long long int x) { return (x % 2 != 0); } vector<int> sieve(int n) { bool prime[n + 1]; memset(prime, true, sizeof(prime)); for (int p = 2; p * p <= n; p++) { if (prime[p] == true) { for (int i = p * p; i <= n; i += p) prime[i] = false; } } vector<int> v; for (int p = 2; p <= n; p++) if (prime[p]) v.push_back(p); return v; } long long gcd(long long int a, long long int b) { if (b == 0) return a; return gcd(b, a % b); } bool isprime(long long n) { if (n == 1) return false; if (n == 2 || n == 3) return true; if (n % 2 == 0 || n % 3 == 0) return false; for (long long i = 5; i * i <= n; i = i + 6) { if (n % i == 0 || n % (i + 2) == 0) return false; } return true; } long long lcm(int a, int b) { return (a / gcd(a, b)) * b; } bool compare(pair<int, int> p1, pair<int, int> p2) { if (p1.first == p2.first) return p1.second <= p2.second; else return p1.first > p2.first; } vector<int> presum(vector<long long int> v) { vector<int> res(v.size()); res[0] = v[0]; for (int i = 1; i < v.size(); i++) { res[i] = res[i - 1] + v[i]; } return res; } void precision(int a) { cout << setprecision(a) << fixed; } int main() { int t; cin >> t; while (t--) { int f = 0; int n; cin >> n; string s; cin >> s; int l = 0, r = 0; for (int i = 0; i < n; i++) { int a = 0, b = 0; for (int j = i; j < n; j++) { if (s[j] == a ) a++; if (s[j] == b ) b++; if (a == b && (a != 0 && b != 0)) { l = i; r = j; f = 1; break; } } if (f == 1) break; } if (f == 1) cout << l + 1 << << r + 1 << endl; else cout << -1 -1 << endl; } } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long q; cin >> q; while (q--) { long long a, b, m; cin >> a >> b >> m; if (a == b) { cout << 1 << << a << n ; continue; } bool ok = 0; long long dif = 0; long long p = a, i = 1ll; while (p <= b) { if (b - p <= ((1ll << (i - 1ll)) * m) && b - p >= (1ll << (i - 1ll))) { ok = 1; dif = b - p - (1ll << (i - 1ll)); break; } i++; p = (p * 2ll); } if (!ok) { cout << (-1) << n ; continue; } long long s1 = min(dif, m - 1); dif -= s1; cout << i + 1 << ; long long res[55]; res[0] = a; for (long long j = 1ll; j < i; j++) { long long sss = 0; for (long long u = 0; u < j; u++) sss += res[u]; sss += min((dif / (1ll << (i - j - 1ll))), m - 1ll); dif -= min((dif / (1ll << (i - j - 1ll))), m - 1ll) * (long long)((1ll << (i - j - 1ll))); sss++; res[j] = sss; } long long sss = 0; for (long long u = 0; u < i; u++) sss += res[u]; sss += s1; sss++; res[i] = sss; for (long long j = 0; j <= i; j++) cout << res[j] << ; cout << n ; } return 0; } |
#include <bits/stdc++.h> int main() { int l, r, a, count; scanf( %d%d%d , &l, &r, &a); count = 0; while (count < a) { if (l > (r + a)) { r = r + a; goto x; } if (r > (l + a)) { l = l + a; goto x; } if (l < r) { l++; count++; } if (l == r) { if ((a - count) % 2 == 0) { l = l + (a - count) / 2; r = r + (a - count) / 2; goto x; } else { l = l + (a - count - 1) / 2; r = r + (a - count - 1) / 2; goto x; } } if (r < l) { r++; count++; } } x: if (l <= r) printf( %d , 2 * l); else printf( %d , 2 * r); return 0; } |
// EE 471 Lab 3, Beck Pang, Spring 2015
// combine SRAM and ALU together
// @require:
// Instruction formula is formed by 3 bit control, 5 bit for address of A
// 5 bit for address of B
// fetch instructions and data into SRAM, and then move to register file
module DE1_SoCPhaseII (CLOCK_50, LEDR, SW, KEY);
input CLOCK_50; // connect to system 50 MHz clock
output [9:0] LEDR;
input [9:0] SW;
input [3:0] KEY;
reg [2:0] ps, ns;
wire [15:0] data;
reg [7:0] count; // 0~255
reg WrEn, regWR;
reg [10:0] adx;
reg [15:0] store;
reg [2:0] control;
wire rst, fetchStart;
reg [4:0] readAdx0, readAdx1, writeAdx;
reg [31:0] writeData;
wire [31:0] readOutput0, readOutput1;
wire [2:0] opcode;
wire [4:0] regAdx0, regAdx1;
reg [31:0] busA, busB;
wire [31:0] busOut;
wire zero, overflow, carryout, negative;
assign fetchStart = SW[6]; // fetch starts when SW[6] turns on
assign rst = SW[9];
assign data = WrEn ? 16'bZ : store; // control the tri-state
assign LEDR[3:0] = {zero, overflow, carryout, negative};
SRAM2Kby16 memory(CLOCK_50, adx, WrEn, data);
registerFile regs(CLOCK_50, readAdx0, readAdx1, writeAdx, regWR, writeData, readOutput0, readOutput1);
ALUnit logicUnit(CLOCK_50, control, busA, busB, busOut, zero, overflow, carryout, negative);
InstrucDecoder getInstruc(data, opcode, regAdx0, regAdx1);
parameter loadData = 3'b000, loadInstr = 3'b001, transfer = 3'b010,
fetch = 3'b011, decode = 3'b100, execute = 3'b101, writeBack = 3'b110, nul = 3'bx;
always @(posedge CLOCK_50)
case (SW[6:4])
loadData : begin // write data into SRAM. Active low Write Enable
WrEn = 0;
regWR = 1;
writeAdx = 0;
writeData = 0;
readAdx0 = 0;
readAdx1 = 16;
control = 0;
adx = count[6:0] + 8'h80;
store = 7'b1111111 - count[6:0];
// if (fetchStart)
// ps = fetch;
// else if (count[6:0] == 7'b1111111)
// ps = loadInstr;
// else
// ps = loadData;
end
loadInstr: begin // create instruction and data address using counter
WrEn = 0;
regWR = 1;
adx = count[6:0];
// count[6:4] is opcode, {1'b0, count[3:0]} the address of A, {1'b1, count[3:0]} the address of B,
store = {count[6:4], {1'b0, count[3:0]}, {1'b1, count[3:0]}, 3'b0};
// if (fetchStart)
// ns = fetch;
// else if (count[6:0] == 7'b1111111)
// ns = transfer;
// else
// ns = loadInstr;
end
transfer : begin // write data into register file
WrEn = 1;
regWR = 0;
adx = count[4:0] + 8'h80;
readAdx0 = 0;
readAdx1 = 16;
control = 0;
writeAdx = count[4:0];
writeData= {{16{data[15]}}, data};
// if (fetchStart)
// ns = fetch;
// else
// ns = transfer;
end
fetch : begin // read from register file to ALU
if(count[0]) begin
WrEn = 1;
regWR = 1;
adx = count[7:1];
readAdx0 = regAdx0;
readAdx1 = regAdx1;
control = opcode;
busA = readOutput0;
busB = readOutput1;
//ns = writeBack;
//end
/*decode : begin
WrEn = 1;
regWR = 1;
adx = adx;
readAdx0 = regAdx0;
readAdx1 = regAdx1;
control = opcode;
ns = execute;
end
execute : begin
WrEn = 1;
regWR = 1;
adx = adx;
readAdx0 = regAdx0;
readAdx1 = regAdx1;
control = opcode;
busA = readOutput0;
busB = readOutput1;
ns = writeBack;
end*/
//writeBack: begin
end else begin
WrEn = 1;
regWR = 0;
writeAdx = regAdx0;
writeData= busOut;
//if (fetchStart)
//ns= fetch;
//else
//ns= execute;
end
// execute:begin
// WrEn = 1;
// regWR = 0;
// readAdx0 = count[4:0];
// readAdx1 = 5'h10 + count[4:0];
// adx = 8'h80 + count[3:0];
// if(!fetchStart)
// ns = loadData;
// else
// ns = execute;
end
default : begin
WrEn = 1'bx;
regWR = 1'bx;
ns = nul;
end
endcase
always @(posedge CLOCK_50) begin
if (rst) begin
//ps <= loadData;
count <= 8'b0;
end
else begin
//ps <= ns;
count <= count + 1'b1;
end
end
endmodule
// vlog "./sourceCode/DE1_SoCPhaseII.v"
// vlog "./sourceCode/Implementation/mux2_1.sv"
// vlog "./sourceCode/Implementation/mux4_1.sv"
// vlog "./sourceCode/Implementation/mux8_1.sv"
// vlog "./sourceCode/Implementation/mux32_1.sv"
// vlog "./sourceCode/Implementation/register.sv"
// vlog "./sourceCode/Implementation/registerSingle.sv"
// vlog "./sourceCode/Implementation/DFlipFlop.sv"
// vlog "./sourceCode/Implementation/counter.v"
// vlog "./sourceCode/Implementation/decoder5_32.sv"
// vlog "./sourceCode/Implementation/decoder8_256.sv"
// vlog "./sourceCode/Implementation/decoder11_2048.sv"
// vlog "./sourceCode/InstrucDecoder.v"
// vlog "./sourceCode/SRAM2Kby16.v"
// vlog "./sourceCode/registerFile.sv"
// vlog "./sourceCode/ALUnit.sv"
// vlog "./sourceCode/addition.v"
// vlog "./sourceCode/subtract.v"
// vlog "./sourceCode/andGate.v"
// vlog "./sourceCode/orGate.v"
// vlog "./sourceCode/xorGate.v"
// vlog "./sourceCode/setLT.v"
// vlog "./sourceCode/shiftll.v"
// vlog "./sourceCode/adder_subtractor.v"
// vlog "./sourceCode/flag.v"
// vlog "./sourceCode/adder16b.v"
// vlog "./sourceCode/adder4b.v"
// vlog "./sourceCode/fullAdder1b.v"
// vlog "./sourceCode/lookAhead4b.v"
module DE1_SoCPhaseII_Testbench();
reg CLOCK_50; // connect to system 50 MHz clock
wire [9:0] LEDR;
reg [9:0] SW;
reg [3:0] KEY;
DE1_SoCPhaseII dut (CLOCK_50, LEDR, SW, KEY);
// Set up the clocking
parameter CLOCK_PERIOD = 100;
initial CLOCK_50 = 1;
always begin
#(CLOCK_PERIOD / 2);
CLOCK_50 = ~CLOCK_50;
end
// Set up the inputs to the design
integer i;
initial begin
@(posedge CLOCK_50);
SW[9] <= 1; @(posedge CLOCK_50);
SW[8:0] <= 9'b0; @(posedge CLOCK_50);
SW[9] <= 0; @(posedge CLOCK_50);
@(posedge CLOCK_50);
for (i = 0; i < 300; i = i + 1) begin
@(posedge CLOCK_50);
end
SW[6] <= 1; @(posedge CLOCK_50);
for (i = 0; i < 19; i = i + 1) begin
@(posedge CLOCK_50);
end
SW[6] <= 0; @(posedge CLOCK_50);
SW[6] <= 1; @(posedge CLOCK_50);
for (i = 0; i < 18; i = i + 1) begin
@(posedge CLOCK_50);
end
SW[6] <= 0; @(posedge CLOCK_50);
SW[6] <= 1; @(posedge CLOCK_50);
for (i = 0; i < 17; i = i + 1) begin
@(posedge CLOCK_50);
end
SW[6] <= 0; @(posedge CLOCK_50);
SW[6] <= 1; @(posedge CLOCK_50);
for (i = 0; i < 16; i = i + 1) begin
@(posedge CLOCK_50);
end
$stop;
end
endmodule |
#include <bits/stdc++.h> using namespace std; int main() { long int n, k, a[222], i; cin >> n >> k; for (i = 1; i <= 2 * n + 1; i++) { cin >> a[i]; } for (i = 2; i <= 2 * n; i += 2) { if ((a[i] - a[i - 1] > 1) && (a[i] - a[i + 1] > 1) && k > 0) { a[i]--; k--; } } for (i = 1; i <= 2 * n + 1; i++) { cout << a[i] << ; } cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; long long const INF = 1e18; long long s[300100], a[300100]; int n, k; int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n >> k; for (int i = 1; i <= n; i++) cin >> a[i]; s[n + 1] = 0; for (int i = n; i >= 1; i--) s[i] = s[i + 1] + a[i]; s[0] = s[1]; sort(s + 2, s + n + 1); long long res = 0; for (int i = n; i >= n - k + 2; i--) res = res + s[i]; res += s[1]; cout << res << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long mo = 1e9 + 7; const int maxi = 1e6 + 6; long long a[maxi], x[maxi], b[maxi]; int n; long long t; int sum[maxi]; int los[maxi]; int ll[maxi]; int main() { cin >> n >> t; for (int i = 1; i <= n; i++) scanf( %lld , &a[i]); for (int i = 1; i <= n; i++) { scanf( %lld , &x[i]); sum[x[i] - 1]++; sum[i - 1]--; } for (int i = n; i > 0; i--) sum[i] += sum[i + 1]; for (int i = 1; i <= n; i++) if (x[i] < i || x[i] < x[i - 1]) return !printf( No n ); for (int i = 1; i <= n; i++) if (sum[i] > 0) b[i] = a[i + 1] + t; else b[i] = a[i] + t; for (int i = 2; i <= n; i++) if (b[i] <= b[i - 1]) b[i] = b[i - 1] + 1; for (int i = 2; i <= n; i++) if (a[i] + t > b[i - 1]) los[i] = 1; for (int i = 1; i <= n; i++) ll[i] = ll[i - 1] + los[i]; for (int i = 1; i <= n; i++) if (x[i] < n && x[i] - i > 0 && ll[x[i] + 1] - ll[i] == 0) return !printf( No n ); printf( Yes n ); for (int i = 1; i <= n; i++) printf( %lld , b[i]); printf( n ); return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// Use this file as a template for submitting bugs, etc.
// This module takes a single clock input, and should either
// $write("*-* All Finished *-*\n");
// $finish;
// on success, or $stop.
//
// The code as shown applies a random vector to the Test
// module, then calculates a CRC on the Test module's outputs.
//
// **If you do not wish for your code to be released to the public
// please note it here, otherwise:**
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by ____YOUR_NAME_HERE____.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h4afe43fb79d7b71e
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in
);
// Replace this module with the device under test.
//
// Change the code in the t module to apply values to the inputs and
// merge the output values into the result vector.
input clk;
input [31:0] in;
output reg [31:0] out;
always @(posedge clk) begin
out <= in;
end
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:clk_gen:1.0
// IP Revision: 0
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module kuuga_test_harness_clk_gen_0_0 (
clk,
sync_rst
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
output wire clk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 sync_rst RST" *)
output wire sync_rst;
clk_gen #(
.CLOCK_PERIOD(10),
.INITIAL_RESET_CLOCK_CYCLES(250),
.RESET_POLARITY(1)
) inst (
.clk(clk),
.clk_n(),
.clk_p(),
.sync_rst(sync_rst)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { vector<int> v; int total, num, i, koita = 0; scanf( %d , &total); for (i = 0; i < total; i++) { scanf( %d , &num); v.push_back(num); } int maximum = v[0]; int minimum = v[0]; for (i = 1; i < total; i++) { num = v[i]; if (num > maximum) { maximum = num; koita++; } if (num < minimum) { minimum = num; koita++; } } printf( %d n , koita); return 0; } |
//======================================================================
//
// tb_gcm.v
// --------
// Testbench for the GCM core top level wrapper.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2016, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
//------------------------------------------------------------------
// Test module.
//------------------------------------------------------------------
module tb_gcm();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter DEBUG = 0;
parameter CLK_HALF_PERIOD = 2;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
// The address map.
parameter ADDR_NAME0 = 8'h00;
parameter ADDR_NAME1 = 8'h01;
parameter ADDR_VERSION = 8'h02;
parameter ADDR_CTRL = 8'h08;
parameter CTRL_INIT_VALUE = 8'h01;
parameter CTRL_NEXT_VALUE = 8'h02;
parameter ADDR_STATUS = 8'h09;
parameter STATUS_READY_BIT = 0;
parameter STATUS_VALID_BIT = 1;
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [31 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg tb_clk;
reg tb_reset_n;
reg tb_cs;
reg tb_we;
reg [7 : 0] tb_address;
reg [31 : 0] tb_write_data;
wire [31 : 0] tb_read_data;
wire tb_error;
reg [31 : 0] read_data;
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
gcm dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
.cs(tb_cs),
.we(tb_we),
.address(tb_address),
.write_data(tb_write_data),
.read_data(tb_read_data)
);
//----------------------------------------------------------------
// clk_gen
//
// Clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD tb_clk = !tb_clk;
end // clk_gen
//----------------------------------------------------------------
// sys_monitor
//
// Generates a cycle counter and displays information about
// the dut as needed.
//----------------------------------------------------------------
always
begin : sys_monitor
#(2 * CLK_HALF_PERIOD);
cycle_ctr = cycle_ctr + 1;
end
//----------------------------------------------------------------
// dump_dut_state()
//
// Dump the state of the dump when needed.
//----------------------------------------------------------------
task dump_dut_state;
begin
$display("State of DUT");
$display("------------");
$display("Inputs and outputs:");
$display("cs = 0x%01x, we = 0x%01x",
dut.cs, dut.we);
$display("address = 0x%02x", dut.address);
$display("write_data = 0x%08x, read_data = 0x%08x",
dut.write_data, dut.read_data);
$display("tmp_read_data = 0x%08x", dut.tmp_read_data);
$display("");
$display("Control and status:");
$display("");
end
endtask // dump_dut_state
//----------------------------------------------------------------
// reset_dut()
//
// Toggles reset to force the DUT into a well defined state.
//----------------------------------------------------------------
task reset_dut;
begin
$display("*** Toggle reset.");
tb_reset_n = 0;
#(4 * CLK_HALF_PERIOD);
tb_reset_n = 1;
end
endtask // reset_dut
//----------------------------------------------------------------
// init_sim()
//
// Initialize all counters and testbed functionality as well
// as setting the DUT inputs to defined values.
//----------------------------------------------------------------
task init_sim;
begin
cycle_ctr = 32'h0;
error_ctr = 32'h0;
tc_ctr = 32'h0;
tb_clk = 0;
tb_reset_n = 0;
tb_cs = 0;
tb_we = 0;
tb_address = 6'h0;
tb_write_data = 32'h0;
end
endtask // init_dut
//----------------------------------------------------------------
// display_test_result()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_result;
begin
if (error_ctr == 0)
begin
$display("*** All %02d test cases completed successfully.", tc_ctr);
end
else
begin
$display("*** %02d test cases completed.", tc_ctr);
$display("*** %02d errors detected during testing.", error_ctr);
end
end
endtask // display_test_result
//----------------------------------------------------------------
// wait_ready()
//
// Wait for the ready flag in the dut to be set.
// (Actually we wait for either ready or valid to be set.)
//
// Note: It is the callers responsibility to call the function
// when the dut is actively processing and will in fact at some
// point set the flag.
//----------------------------------------------------------------
task wait_ready;
begin
read_data = 0;
while (read_data == 0)
begin
read_word(ADDR_STATUS);
end
end
endtask // wait_ready
//----------------------------------------------------------------
// write_word()
//
// Write the given word to the DUT using the DUT interface.
//----------------------------------------------------------------
task write_word(input [7 : 0] address,
input [31 : 0] word);
begin
if (DEBUG)
begin
$display("*** Writing 0x%08x to 0x%02x.", word, address);
$display("");
end
tb_address = address;
tb_write_data = word;
tb_cs = 1;
tb_we = 1;
#(CLK_PERIOD);
tb_cs = 0;
tb_we = 0;
end
endtask // write_word
//----------------------------------------------------------------
// read_word()
//
// Read a data word from the given address in the DUT.
// the word read will be available in the global variable
// read_data.
//----------------------------------------------------------------
task read_word(input [7 : 0] address);
begin
tb_address = address;
tb_cs = 1;
tb_we = 0;
#(CLK_PERIOD);
read_data = tb_read_data;
tb_cs = 0;
if (DEBUG)
begin
$display("*** Reading 0x%08x from 0x%02x.", read_data, address);
$display("");
end
end
endtask // read_word
//----------------------------------------------------------------
// check_name_version()
//
// Read the name and version from the DUT.
//----------------------------------------------------------------
task check_name_version;
reg [31 : 0] name0;
reg [31 : 0] name1;
reg [31 : 0] version;
begin
read_word(ADDR_NAME0);
name0 = read_data;
read_word(ADDR_NAME1);
name1 = read_data;
read_word(ADDR_VERSION);
version = read_data;
$display("DUT name: %c%c%c%c%c%c%c%c",
name0[31 : 24], name0[23 : 16], name0[15 : 8], name0[7 : 0],
name1[31 : 24], name1[23 : 16], name1[15 : 8], name1[7 : 0]);
$display("DUT version: %c%c%c%c",
version[31 : 24], version[23 : 16], version[15 : 8], version[7 : 0]);
end
endtask // check_name_version
//----------------------------------------------------------------
// gcm_tests()
//----------------------------------------------------------------
task gcm_tests;
begin : gcm_tests
$display("*** Testcases for gcm functionality started.");
$display("*** Testcases for gcm functionality completed.");
end
endtask // gcm_tests
//----------------------------------------------------------------
// gcm_test
// The main test functionality.
//----------------------------------------------------------------
initial
begin : gcm_test
$display(" -- Testbench for gcm started --");
init_sim();
reset_dut();
check_name_version();
gcm_tests();
display_test_result();
$display(" -- Testbench for gcm done. --");
$finish;
end // gcm_test
endmodule // tb_gcm
//======================================================================
// EOF tb_gcm.v
//======================================================================
|
#include <bits/stdc++.h> using namespace std; vector<long long> primes; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); int n, q; cin >> n >> q; vector<pair<int, int> > ans; int tmp(-1); vector<bool> state; for (int i = 0; i < n; ++i) { int x; cin >> x; if (tmp <= x) { if (!i) tmp = x; else { ans.push_back(make_pair(tmp, x)); tmp = x; state.push_back(true); } } else { ans.push_back(make_pair(x, tmp)); state.push_back(false); } } int nw = n - 1; while (q--) { long long y; cin >> y; if (!y) cout << n ; else { if (y < n) { if (state[y - 1]) cout << ans[y - 1].first << << ans[y - 1].second << n ; else cout << ans[y - 1].second << << ans[y - 1].first << n ; } else { y -= n; if (!y) cout << tmp << << ans[0].first << n ; else cout << tmp << << ans[y % nw].first << n ; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long N = 1e6 + 25; const long long INF = 1e15 + 7; const long long mod = 998244353; long long dp[N]; long long binpow(long long a, long long b) { a %= mod; long long res = 1; while (b > 0) { if (b & 1) res = res * a % mod; a = a * a % mod; b >>= 1; } return res; } long long mult(long long a, long long b) { return (a % mod * b % mod) % mod; } long long add(long long a, long long b) { a += b; if (a >= mod) return a - mod; return a; } long long sub(long long a, long long b) { a -= b; if (a < 0) return a + mod; return a; } long long inverse(long long a) { return binpow(a, mod - 2); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t; cin >> t; while (t--) { long long n, m; cin >> n >> m; vector<pair<long long, long long> > ans; char a[n + 2][m + 3]; for (long long i = 0; i < n; i++) { for (long long j = 0; j < m; j++) cin >> a[i][j]; } for (long long i = 0; i < n - 1; i++) { for (long long j = 0; j < m - 1; j++) { vector<pair<long long, long long> > z, o; if (a[i][j] == 0 ) z.push_back(make_pair(i, j)); else o.push_back(make_pair(i, j)); if (a[i][j + 1] == 0 ) z.push_back(make_pair(i, j + 1)); else o.push_back(make_pair(i, j + 1)); if (a[i + 1][j] == 0 ) z.push_back(make_pair(i + 1, j)); else o.push_back(make_pair(i + 1, j)); if (a[i + 1][j + 1] == 0 ) z.push_back(make_pair(i + 1, j + 1)); else o.push_back(make_pair(i + 1, j + 1)); if (o.size() == 0) continue; if (o.size() == 4) { ans.push_back(make_pair(i, j)); ans.push_back(make_pair(i, j + 1)); ans.push_back(make_pair(i + 1, j)); ans.push_back(make_pair(i + 1, j + 1)); ans.push_back(make_pair(i + 1, j)); ans.push_back(make_pair(i, j + 1)); ans.push_back(make_pair(i, j)); ans.push_back(make_pair(i, j + 1)); ans.push_back(make_pair(i + 1, j + 1)); ans.push_back(make_pair(i, j)); ans.push_back(make_pair(i + 1, j)); ans.push_back(make_pair(i + 1, j + 1)); } if (o.size() == 3) { for (long long k = 0; k < 3; k++) ans.push_back(o[k]); } if (o.size() == 2) { ans.push_back(o[0]); ans.push_back(z[0]); ans.push_back(z[1]); ans.push_back(o[1]); ans.push_back(z[0]); ans.push_back(z[1]); } if (o.size() == 1) { ans.push_back(o[0]); ans.push_back(z[1]); ans.push_back(z[2]); pair<long long, long long> p = o[0]; o.pop_back(); o.push_back(z[1]); o.push_back(z[2]); z.pop_back(); z.pop_back(); z.push_back(p); ans.push_back(o[0]); ans.push_back(z[0]); ans.push_back(z[1]); ans.push_back(o[1]); ans.push_back(z[0]); ans.push_back(z[1]); } a[i][j] = 0 ; a[i + 1][j] = 0 ; a[i][j + 1] = 0 ; a[i + 1][j + 1] = 0 ; } } cout << ans.size() / 3 << endl; for (long long i = 0; i < ans.size(); i += 3) { cout << ans[i].first + 1 << << ans[i].second + 1 << << ans[i + 1].first + 1 << << ans[i + 1].second + 1 << << ans[i + 2].first + 1 << << ans[i + 2].second + 1 << endl; } } } |
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module sw_pio (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 7: 0] in_port;
input reset_n;
wire clk_en;
wire [ 7: 0] data_in;
wire [ 7: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {{{32 - 8}{1'b0}},read_mux_out};
end
assign data_in = in_port;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLCLKP_1_V
`define SKY130_FD_SC_HVL__DLCLKP_1_V
/**
* dlclkp: Clock gate.
*
* Verilog wrapper for dlclkp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__dlclkp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dlclkp_1 (
GCLK,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK(CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dlclkp_1 (
GCLK,
GATE,
CLK
);
output GCLK;
input GATE;
input CLK ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK(CLK)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLCLKP_1_V
|
#include <bits/stdc++.h> using namespace std; int n, m, tab[105][105], pot[30]; int licz(int numer) { int wyn = 0; for (int i = (0); i <= ((m)-1); ++i) { int a = 0, b = 0; for (int j = (0); j <= ((n)-1); ++j) { a += (tab[j][i] != tab[j][numer]); b += (tab[j][i] == tab[j][numer]); } wyn += min(a, b); } return wyn; } int licz2(int a) { for (int i = (0); i <= ((n)-1); ++i) { tab[i][m] = a % 2; a /= 2; } return licz(m); } void jebaj() { pot[0] = 1; for (int i = (1); i <= (20); ++i) pot[i] = pot[i - 1] * 2; int k; cin >> n >> m >> k; for (int i = (0); i <= ((n)-1); ++i) for (int j = (0); j <= ((m)-1); ++j) cin >> tab[i][j]; int res = 1000; if (n > k) { for (int i = (0); i <= ((k + 1) - 1); ++i) { res = min(res, licz(i)); } } else { for (int i = (0); i <= ((pot[n]) - 1); ++i) { res = min(res, licz2(i)); } } if (res > k) { cout << -1 n ; return; } cout << res << n ; return; } int main() { ios_base::sync_with_stdio(0); int t; t = 1; for (int i = (0); i <= ((t)-1); ++i) jebaj(); } |
// bfloat16
// TODO: Write tests and fix obvious bugs first.
module FP16BAddSubS0Of5(
input clk,
input rst,
input [15:0] arg_0,
input [15:0] arg_1,
input arg_2,
output [15:0] ret_0,
output [15:0] ret_1,
output ret_2,
output ret_3);
wire [15:0] x;
wire [15:0] y;
wire is_sub;
wire ys;
wire yys;
wire [15:0] yy;
wire diff_sign;
wire [7:0] xe;
wire [7:0] ye;
wire swap;
wire neg_lhs;
wire neg_rhs;
wire [15:0] lhs;
wire [15:0] rhs;
assign x = arg_0;
assign y = arg_1;
assign is_sub = arg_2;
assign ys = y[15];
assign yys = is_sub ? ~ys : ys;
assign yy = {yys, y[14:0]};
assign xe = x[14:7];
assign ye = y[14:7];
assign diff_sign = x[15] ^ yy[15];
assign swap = xe < ye;
assign lhs = swap ? yy : x;
assign rhs = swap ? x : yy;
assign neg_lhs = diff_sign ? lhs[15] : 0;
assign neg_rhs = diff_sign ? rhs[15] : 0;
assign ret_0 = lhs;
assign ret_1 = rhs;
assign ret_2 = neg_lhs;
assign ret_3 = neg_rhs;
endmodule // FP16BAddSubS0Of5
module FP16BAddSubS1Of5(
input clk,
input rst,
input [15:0] arg_0,
input [15:0] arg_1,
input arg_2,
input arg_3,
output ret_0,
output ret_1,
output [14:0] ret_2,
output [14:0] ret_3,
output [7:0] ret_4,
output ret_5,
output ret_6);
wire [15:0] x;
wire [15:0] y;
wire xn;
wire yn;
wire [7:0] xe;
wire [7:0] ye;
wire x1;
wire y1;
wire [6:0] xf;
wire [6:0] yf;
wire [14:0] xr;
wire [14:0] xrn;
wire [14:0] yr10;
wire [8:0] d;
wire [14:0] yr1;
wire [14:0] yr2;
wire [14:0] yr4;
wire [14:0] yr8;
wire [14:0] yrn;
assign x = arg_0;
assign y = arg_1;
assign xn = arg_2;
assign yn = arg_3;
assign xe = x[14:7];
assign ye = y[14:7];
assign xf = x[6:0];
assign yf = y[6:0];
assign x1 = xe > 0;
assign y1 = ye > 0;
assign xr = {x1, xf, 7'b0};
assign xrn = xn ? ~xr : xr;
assign yr10 = {y1, yf, 7'b0};
assign d = xe - ye;
// barrel shifter to adjust y.
assign yr1 = d[0:0] ? {1'b0, yr10[14:1]} : yr10;
assign yr2 = d[1:1] ? {2'b0, yr1[14:2]} : yr1;
assign yr4 = d[2:2] ? {4'b0, yr2[14:4]} : yr2;
assign yr8 = d[3:3] ? {8'b0, yr4[14:8]} : yr4;
assign yrn = yn ? ~yr8 : yr8;
assign ret_0 = x[15];
assign ret_1 = y[15];
assign ret_2 = xrn;
assign ret_3 = yrn;
assign ret_4 = xe;
assign ret_5 = xn;
assign ret_6 = yn;
endmodule // FP16BAddSubS1Of5
module FP16BAddSubS2Of5(
input clk,
input rst,
input arg_0,
input arg_1,
input [14:0] arg_2,
input [14:0] arg_3,
input [7:0] arg_4,
input arg_5,
input arg_6,
output [15:0] ret_0,
output ret_1,
output ret_2,
output [7:0] ret_3,
output ret_4,
output ret_5);
wire xn;
wire yn;
wire [15:0] rxy;
wire diff_sign;
wire [15:0] r_final;
assign xn = arg_5;
assign yn = arg_6;
assign diff_sign = (xn != yn);
assign rxy = arg_2 + arg_3;
assign r_final = diff_sign ? (rxy + 1) : rxy;
assign ret_0 = r_final;
assign ret_1 = arg_0;
assign ret_2 = arg_1;
assign ret_3 = arg_4;
assign ret_4 = arg_5;
assign ret_5 = arg_6;
endmodule // FP16BAddSubS2Of5
module FP16BAddSubS3Of5(
input clk,
input rst,
input [15:0] arg_0,
input arg_1,
input arg_2,
input [7:0] arg_3,
input arg_4,
input arg_5,
output [14:0] ret_0,
output ret_1,
output ret_2,
output [7:0] ret_3,
output ret_4,
output ret_5,
output ret_6);
wire [15:0] r;
wire xs;
wire ys;
wire [7:0] e;
wire xn;
wire yn;
wire diff_sign;
wire with_carry;
wire neg;
wire [14:0] neg_r;
wire [14:0] half_r;
wire [14:0] r_diff;
wire [14:0] r_same;
wire [14:0] r_final;
wire [7:0] eplus;
wire [7:0] e_final;
assign r = arg_0;
assign xs = arg_1;
assign ys = arg_2;
assign e = arg_3;
assign xn = arg_4;
assign yn = arg_5;
assign diff_sign = (xn != yn);
assign with_carry = r[15:15];
assign neg_r = (~r) + 1;
assign half_r = r[15:1];
assign neg = diff_sign & !with_carry;
assign eplus = e + 1;
assign r_diff = with_carry ? r[14:0] : neg_r;
assign r_same = with_carry ? half_r : r[14:0];
assign r_final = diff_sign ? r_diff : r_same;
assign e_final = (!diff_sign && with_carry) ? eplus : e;
assign ret_0 = r_final;
assign ret_1 = xs;
assign ret_2 = ys;
assign ret_3 = e_final;
assign ret_4 = neg;
assign ret_5 = xn;
assign ret_6 = yn;
endmodule // FP16BAddSubS3Of5
module FP16BAddSubS4Of5(
input clk,
input rst,
input [14:0] arg_0,
input arg_1,
input arg_2,
input [7:0] arg_3,
input arg_4,
input arg_5,
input arg_6,
output [15:0] ret_0);
wire [15:0] r;
wire xs;
wire ys;
wire [7:0] e;
wire [7:0] e_final;
wire [8:0] e_l0adjust;
wire underflow;
wire [7:0] e_adjust;
wire neg;
wire xn;
wire yn;
wire [7:0] rr;
wire [6:0] r_final;
wire [15:0] r8;
wire [15:0] r4;
wire [15:0] r2;
wire [15:0] r1;
wire [3:0] l0count;
wire s;
assign r = arg_0;
assign xs = arg_1;
assign ys = arg_2;
assign e = arg_3;
assign neg = arg_4;
assign xn = arg_5;
assign yn = arg_6;
assign s = (xn == yn) ? xs : (yn ? (neg ^ xs): (neg ^ ys));
assign r8 = (r[14:7] == 0) ? {r[6:0], 8'b0} : r;
assign r4 = (r8[14:11] == 0) ? {r8[10:0], 4'b0} : r8;
assign r2 = (r4[14:13] == 0) ? {r4[12:0], 2'b0} : r4;
assign r1 = (r2[14:14] == 0) ? {r2[13:0], 1'b0} : r2;
assign l0count = {r[14:7] == 0, r8[14:11] == 0, r4[14:13] == 0, r2[14:14] == 0};
assign rr = (xn == yn) ? r[14:7] : r1;
assign e_l0adjust = e - l0count;
assign underflow = e_l0adjust[8:8];
assign e_adjust = underflow ? 0 : e_l0adjust[7:0];
assign e_final = (xn == yn) ? e : e_adjust[7:0];
assign r_final = underflow ? 0 : rr[6:0];
assign ret_0 = {s, e_final, r_final};
endmodule // FP16BAddSubS4Of5
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_core_pcie_brams_7x.v
// Version : 1.10
// Description : pcie bram wrapper
// arrange and connect brams
// implement address decoding, datapath muxing and pipeline stages
//
// banks of brams are used for 1,2,4,8,18 brams
// brams are stacked for other values of NUM_BRAMS
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
module pcie_core_pcie_brams_7x
#(
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1, // PCIe Link Speed : 1 - 2.5 GT/s; 2 - 5.0 GT/s
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08, // PCIe Link Width : 1 / 2 / 4 / 8
parameter IMPL_TARGET = "HARD", // the implementation target : HARD, SOFT
// the number of BRAMs to use
// supported values are:
// 1,2,4,8,18
parameter NUM_BRAMS = 0,
// BRAM read address latency
//
// value meaning
// ====================================================
// 0 BRAM read address port sample
// 1 BRAM read address port sample and a pipeline stage on the address port
parameter RAM_RADDR_LATENCY = 1,
// BRAM read data latency
//
// value meaning
// ====================================================
// 1 no BRAM OREG
// 2 use BRAM OREG
// 3 use BRAM OREG and a pipeline stage on the data port
parameter RAM_RDATA_LATENCY = 1,
// BRAM write latency
// The BRAM write port is synchronous
//
// value meaning
// ====================================================
// 0 BRAM write port sample
// 1 BRAM write port sample plus pipeline stage
parameter RAM_WRITE_LATENCY = 1
)
(
input user_clk_i,
input reset_i,
input wen,
input [12:0] waddr,
input [71:0] wdata,
input ren,
input rce,
input [12:0] raddr,
output [71:0] rdata
);
// turn on the bram output register
localparam DOB_REG = (RAM_RDATA_LATENCY > 1) ? 1 : 0;
// calculate the data width of the individual brams
localparam [6:0] WIDTH = ((NUM_BRAMS == 1) ? 72 :
(NUM_BRAMS == 2) ? 36 :
(NUM_BRAMS == 4) ? 18 :
(NUM_BRAMS == 8) ? 9 :
4
);
parameter TCQ = 1;
wire wen_int;
wire [12:0] waddr_int;
wire [71:0] wdata_int;
wire ren_int;
wire [12:0] raddr_int;
wire [71:0] rdata_int;
//synthesis translate_off
initial
begin
$display("[%t] %m NUM_BRAMS %0d DOB_REG %0d WIDTH %0d RAM_WRITE_LATENCY %0d RAM_RADDR_LATENCY %0d RAM_RDATA_LATENCY %0d",
$time, NUM_BRAMS, DOB_REG, WIDTH, RAM_WRITE_LATENCY, RAM_RADDR_LATENCY, RAM_RDATA_LATENCY);
case (NUM_BRAMS)
1,2,4,8,18:;
default:
begin
$display("[%t] %m Error NUM_BRAMS %0d not supported", $time, NUM_BRAMS);
$finish;
end
endcase // case(NUM_BRAMS)
case (RAM_RADDR_LATENCY)
0,1:;
default:
begin
$display("[%t] %m Error RAM_READ_LATENCY %0d not supported", $time, RAM_RADDR_LATENCY);
$finish;
end
endcase // case (RAM_RADDR_LATENCY)
case (RAM_RDATA_LATENCY)
1,2,3:;
default:
begin
$display("[%t] %m Error RAM_READ_LATENCY %0d not supported", $time, RAM_RDATA_LATENCY);
$finish;
end
endcase // case (RAM_RDATA_LATENCY)
case (RAM_WRITE_LATENCY)
0,1:;
default:
begin
$display("[%t] %m Error RAM_WRITE_LATENCY %0d not supported", $time, RAM_WRITE_LATENCY);
$finish;
end
endcase // case(RAM_WRITE_LATENCY)
end
//synthesis translate_on
// model the delays for ram write latency
generate if (RAM_WRITE_LATENCY == 1) begin : wr_lat_2
reg wen_q;
reg [12:0] waddr_q;
reg [71:0] wdata_q;
always @(posedge user_clk_i) begin
if (reset_i)
begin
wen_q <= #TCQ 1'b0;
waddr_q <= #TCQ 13'b0;
// Disable Reset on Data Path @ BRAM i/f as I/O come from PCIe HB.
// wdata_q <= #TCQ 72'b0;
end
else
begin
wen_q <= #TCQ wen;
waddr_q <= #TCQ waddr;
wdata_q <= #TCQ wdata;
end
end
assign wen_int = wen_q;
assign waddr_int = waddr_q;
assign wdata_int = wdata_q;
end // if (RAM_WRITE_LATENCY == 1)
else if (RAM_WRITE_LATENCY == 0) begin : wr_lat_1
assign wen_int = wen;
assign waddr_int = waddr;
assign wdata_int = wdata;
end
endgenerate
// model the delays for ram read latency
generate if (RAM_RADDR_LATENCY == 1) begin : raddr_lat_2
reg ren_q;
reg [12:0] raddr_q;
always @(posedge user_clk_i) begin
if (reset_i)
begin
ren_q <= #TCQ 1'b0;
raddr_q <= #TCQ 13'b0;
end
else
begin
ren_q <= #TCQ ren;
raddr_q <= #TCQ raddr;
end // else: !if(reset_i)
end
assign ren_int = ren_q;
assign raddr_int = raddr_q;
end // block: rd_lat_addr_2
else begin : raddr_lat_1
assign ren_int = ren;
assign raddr_int = raddr;
end
endgenerate
generate if (RAM_RDATA_LATENCY == 3) begin : rdata_lat_3
reg [71:0] rdata_q;
always @(posedge user_clk_i) begin
// Disable Reset on Data Path @ BRAM i/f as I/O come from PCIe HB.
//if (reset_i)
//begin
// rdata_q <= #TCQ 72'b0;
//end
//else
//begin
rdata_q <= #TCQ rdata_int;
//end // else: !if(reset_i)
end
assign rdata = rdata_q;
end // block: rd_lat_data_3
else begin : rdata_lat_1_2
assign rdata = rdata_int;
end
endgenerate
// instantiate the brams
generate
genvar ii;
for (ii = 0; ii < NUM_BRAMS; ii = ii + 1) begin : brams
pcie_core_pcie_bram_7x #(
.LINK_CAP_MAX_LINK_WIDTH(LINK_CAP_MAX_LINK_WIDTH),
.LINK_CAP_MAX_LINK_SPEED(LINK_CAP_MAX_LINK_SPEED),
.IMPL_TARGET (IMPL_TARGET),
.DOB_REG (DOB_REG),
.WIDTH (WIDTH)
)
ram (
.user_clk_i(user_clk_i),
.reset_i(reset_i),
.wen_i(wen_int),
.waddr_i(waddr_int),
.wdata_i(wdata_int[(((ii + 1) * WIDTH) - 1): (ii * WIDTH)]),
.ren_i(ren_int),
.raddr_i(raddr_int),
.rdata_o(rdata_int[(((ii + 1) * WIDTH) - 1): (ii * WIDTH)]),
.rce_i(rce)
);
end
endgenerate
endmodule // pcie_brams_7x
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRBN_FUNCTIONAL_V
`define SKY130_FD_SC_MS__DLRBN_FUNCTIONAL_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr/sky130_fd_sc_ms__udp_dlatch_pr.v"
`celldefine
module sky130_fd_sc_ms__dlrbn (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N
);
// Module ports
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
// Local signals
wire RESET ;
wire intgate;
wire buf_Q ;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intgate, GATE_N );
sky130_fd_sc_ms__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, intgate, RESET);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRBN_FUNCTIONAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKINV_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__CLKINV_BEHAVIORAL_V
/**
* clkinv: Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__clkinv (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKINV_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; long long int INF = (long long int)1e16; int n, m, r; vector<int> s, b; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); s.clear(); b.clear(); cin >> n >> m >> r; int x, y; int bax = INT_MAX; int bay = INT_MIN; for (int i = 0; i < n; i++) { cin >> x; bax = min(bax, x); } for (int i = 0; i < m; i++) { cin >> y; bay = max(bay, y); } int bht = r / bax; int cost = bht * bay + r % bax; cout << max(cost, r) << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); int n, d, i, j, k, s, t, ans; cin >> n >> d; s = 0; for (i = 0; i < n; i++) { cin >> t; s += t; } if (s + (n - 1) * 10 > d) ans = -1; else ans = (d - s) / 5; cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename Arg1> void __f(const char* name, Arg1&& arg1) { cerr << name << : << arg1 << std::endl; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cerr.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } const int L = 1e7 + 7; map<long long, long long> counter; int lps[L]; void pre() { lps[1] = 1; for (int i = 2; i < 10000001; ++i) { if (lps[i]) continue; for (int j = i; j <= 10000000; j += i) { lps[j] = i; } } return; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n, ans = 0; cin >> n; int tmp = sqrt(n); if (n % 2 == 0) { cout << n / 2; return 0; } for (long long i = 3; i <= tmp + 1; i += 2) { if (n % i == 0) { cout << (n - i) / 2 + 1; return 0; } } cout << 1 ; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFXTP_FUNCTIONAL_V
`define SKY130_FD_SC_HS__DFXTP_FUNCTIONAL_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_df_p_pg/sky130_fd_sc_hs__u_df_p_pg.v"
`celldefine
module sky130_fd_sc_hs__dfxtp (
VPWR,
VGND,
Q ,
CLK ,
D
);
// Module ports
input VPWR;
input VGND;
output Q ;
input CLK ;
input D ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hs__u_df_p_pg `UNIT_DELAY u_df_p_pg0 (buf_Q , D, CLK, VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFXTP_FUNCTIONAL_V |
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_sync_reset.v
//
// *Module Description:
// Generic reset synchronizer for the openMSP430
//
// *Author(s):
// - Olivier Girard,
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
module omsp_sync_reset (
// OUTPUTs
rst_s, // Synchronized reset
// INPUTs
clk, // Receiving clock
rst_a // Asynchronous reset
);
// OUTPUTs
//=========
output rst_s; // Synchronized reset
// INPUTs
//=========
input clk; // Receiving clock
input rst_a; // Asynchronous reset
//=============================================================================
// 1) SYNCHRONIZER
//=============================================================================
reg [1:0] data_sync;
always @(posedge clk or posedge rst_a)
if (rst_a) data_sync <= 2'b11;
else data_sync <= {data_sync[0], 1'b0};
assign rst_s = data_sync[1];
endmodule // omsp_sync_reset
|
#include <bits/stdc++.h> using namespace std; int n, m, a[100005], b[2005], d[100005], z[100005], L[100005]; inline void upd(int &a, int b) { if (a < b) a = b; } int main(void) { while (cin >> n >> m) { for (int i = int(1); i <= int(n); i++) cin >> a[i]; for (int i = int(1); i <= int(m); i++) cin >> b[i]; sort(a + 1, a + n + 1); sort(b + 1, b + m + 1); memset(d, 0, sizeof d), memset(z, 0, sizeof z), memset(L, 0, sizeof L); for (int i = int(1); i <= int(n); i++) { if (i > 1 && a[i] - 1 == a[i - 1]) L[i] = L[i - 1]; else L[i] = i; int x = upper_bound(b + 1, b + m + 1, a[i]) - b; upd(d[i], z[L[i] - 1]); for (int j = int(x - 1); j >= int(1); j--) { if (i <= a[i] - b[j]) break; upd(d[i], z[L[i - a[i] + b[j]] - 1] + x - j); } upd(z[i], max(z[i - 1], d[i])); for (int j = int(x); j <= int(m); j++) { if (i + b[j] - a[i] > n) break; upd(z[i + b[j] - a[i]], d[i] + j - x + 1); } } cout << z[n] << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; ll BASE_NUM = 998244353; class UnionFindTree { map<ll, ll> union_tree_data; public: UnionFindTree() {} UnionFindTree(vector<ll> verticals) { for (auto v : verticals) { union_tree_data[v] = v; } } void add_vertical(ll v) { union_tree_data[v] = v; } void reset() { for (auto &pair : union_tree_data) { pair.second = pair.first; } } long long find(long long N) { if (union_tree_data[N] == N) { return N; } else { return union_tree_data[N] = find(union_tree_data[N]); } } bool same(long long x, long long y) { return find(x) == find(y); } void union_tree(long long x, long long y) { x = find(x); y = find(y); if (x == y) return; union_tree_data[x] = y; } }; class edge { public: ll from, to, cost; bool operator<(const edge &another) const { return cost < another.cost; }; bool operator>(const edge &another) const { return cost > another.cost; }; }; class MST { UnionFindTree uft; public: priority_queue<edge, vector<edge>, greater<edge>> que; vector<edge> result; ll cost = 0; MST(vector<ll> &nodes, vector<edge> &edges) : uft(nodes) { for (auto e : edges) { que.push(e); } while (!que.empty()) { edge e; e = que.top(); if (!uft.same(e.from, e.to)) { uft.union_tree(e.from, e.to); result.push_back(e); cost += e.cost; } que.pop(); } } }; int main() { ll n; vector<pair<ll, ll>> towns; vector<ll> costs; vector<ll> ks; vector<edge> edges; cin >> n; for (int i = 0; i < n; i++) { pair<ll, ll> p; cin >> p.first >> p.second; towns.push_back(p); } for (int i = 0; i < n; i++) { ll c; cin >> c; costs.push_back(c); } for (int i = 0; i < n; i++) { ll k; cin >> k; ks.push_back(k); } for (int i = 0; i < n; i++) { for (int j = i + 1; j < n; j++) { edges.push_back({i, j, (abs(towns[i].first - towns[j].first) + abs(towns[i].second - towns[j].second)) * (ks[i] + ks[j])}); } } for (int i = 0; i < n; i++) { edges.push_back({i, n, costs[i]}); } vector<ll> nodes(n + 1); for (int i = 0; i < n + 1; i++) { nodes[i] = i; } MST mst(nodes, edges); vector<ll> stations; vector<pair<ll, ll>> connections; for (auto e : mst.result) { if (e.to == n) { stations.push_back(e.from); } else { connections.push_back(make_pair(e.from, e.to)); } } cout << mst.cost << n ; cout << stations.size() << n ; for (int i = 0; i < stations.size(); i++) { if (i == 0) { cout << stations[i] + 1; } else { cout << << stations[i] + 1; } } cout << n ; cout << connections.size() << n ; for (int i = 0; i < connections.size(); i++) { cout << connections[i].first + 1 << << connections[i].second + 1 << n ; } cout << flush; return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// Also check that SystemC is ordering properly
// verilator lint_on IMPERFECTSCH
module t (/*AUTOARG*/
// Outputs
o1, o8, o16, o32, o64, o65, o128, o513, o1a2, o94a3, obv1, obv16, obv1_vlt, obv16_vlt,
// Inputs
clk, i1, i8, i16, i32, i64, i65, i128, i513, i1a2, i94a3, ibv1, ibv16, ibv1_vlt, ibv16_vlt
);
input clk;
input i1;
input [7:0] i8;
input [15:0] i16;
input [31:0] i32;
input [63:0] i64;
input [64:0] i65;
input [127:0] i128;
input [512:0] i513;
input i1a2 [1:0];
input [93:0] i94a3 [2:0];
output logic o1;
output logic [7:0] o8;
output logic [15:0] o16;
output logic [31:0] o32;
output logic [63:0] o64;
output logic [64:0] o65;
output logic [127:0] o128;
output logic [512:0] o513;
output logic o1a2 [1:0];
output logic [93:0] o94a3 [2:0];
input [0:0] ibv1 /*verilator sc_bv*/;
input [15:0] ibv16 /*verilator sc_bv*/;
input [0:0] ibv1_vlt;
input [15:0] ibv16_vlt;
output logic [0:0] obv1 /*verilator sc_bv*/;
output logic [15:0] obv16 /*verilator sc_bv*/;
output logic [0:0] obv1_vlt;
output logic [15:0] obv16_vlt;
always @ (posedge clk) begin
o1 <= i1;
o8 <= i8;
o16 <= i16;
o32 <= i32;
o64 <= i64;
o65 <= i65;
o128 <= i128;
o513 <= i513;
obv1 <= ibv1;
obv16 <= ibv16;
obv1_vlt <= ibv1_vlt;
obv16_vlt <= ibv16_vlt;
o1a2 <= i1a2;
o94a3 <= i94a3;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, a, b, mas[30], summ[100005]; long long sum, countt; string s; map<pair<char, long long>, int> matr; int main() { ios_base::sync_with_stdio(false); cin.tie(0); for (int i = 0; i < 26; ++i) cin >> mas[i]; cin >> s; for (int i = 0; i < s.size(); ++i) { if (matr.count(make_pair(s[i], sum))) countt += matr[make_pair(s[i], sum)]; sum += mas[s[i] - a ]; matr[make_pair(s[i], sum)]++; } cout << countt; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long MOD = (long long)(1e9 + 7); const long long INF = (long long)(1e9 + 10); const int MAXN = (int)(2e5 + 5); int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); string caso; cin >> caso; while (caso == start ) { int a = 0, b = 1; cout << ? << a << << b << endl; char aux; cin >> aux; while (aux == y ) { a = b; b = a * 2; cout << ? << a << << b << endl; cin >> aux; } int x = a, y = b; while (y - x > 1) { int med = (x + y) / 2; cout << ? << med << << b << endl; cin >> aux; if (aux == y ) y = med; else x = med; } cout << ! << y << endl; cin >> caso; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MOD = (int)1e9 + 7; const int INF = (int)1e9; const long long LINF = (long long)1e18; const long double PI = acos((long double)-1); const long double EPS = 1e-9; long long gcd(long long a, long long b) { long long r; while (b) { r = a % b; a = b; b = r; } return a; } long long lcm(long long a, long long b) { return a / gcd(a, b) * b; } long long fpow(long long n, long long k, int p = MOD) { long long r = 1; for (; k; k >>= 1) { if (k & 1) r = r * n % p; n = n * n % p; } return r; } template <class T> void setmin(T& a, T val) { if (a > val) a = val; } template <class T> void setmax(T& a, T val) { if (a < val) a = val; } void addmod(long long& a, long long val, int p = MOD) { if ((a = (a + val)) >= p) a -= p; } void submod(long long& a, long long val, int p = MOD) { if ((a = (a - val)) < 0) a += p; } int mult(int a, int b, int p = MOD) { return (long long)a * b % p; } int inv(int a, int p = MOD) { return fpow(a, p - 2, p); } const int N = 100005; int main() { ios::sync_with_stdio(false); cin.tie(0); int t; cin >> t; while (t--) { long long n, m; cin >> n >> m; long long wtotal = n * m / 2, btotal = n * m / 2; if ((n * m) % 2) wtotal++; long long x1, y1, x2, y2; cin >> x1 >> y1 >> x2 >> y2; long long x3, y3, x4, y4; cin >> x3 >> y3 >> x4 >> y4; long long k1 = abs(x2 - x1 + 1) * abs(y2 - y1 + 1), k2 = abs(x4 - x3 + 1) * abs(y4 - y3 + 1); long long black = k1 / 2; if ((x1 + y1) % 2 && k1 % 2) black++; wtotal += black; btotal -= black; long long white = k2 / 2; if ((x3 + y3) % 2 == 0 && k2 % 2) white++; btotal += white; wtotal -= white; long long x5 = max(x1, x3); long long y5 = max(y1, y3); long long x6 = min(x2, x4); long long y6 = min(y2, y4); if (y5 > y6 || x5 > x6) cout << wtotal << << btotal << n ; else { long long bext = abs(x6 - x5 + 1) * abs(y6 - y5 + 1); long long b = bext / 2; if ((x5 + y5) % 2 && bext % 2) b++; cout << wtotal - b << << btotal + b << n ; } } return 0; } |
// Copyright (c) 2015 CERN
// @author Maciej Suminski <>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// 'wait on' & 'wait until' test
module vhdl_wait_test;
logic [1:0] a, b;
vhdl_wait dut(a, b);
always @(posedge b[0]) begin
$display("wait 1 acknowledged");
// complete "wait 2"
a[1] = 1'b0;
end
always @(posedge b[1]) begin
$display("wait 2 acknowledged");
end
initial begin
// complete "wait 1"
a = 2'b00;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t, i; cin >> t; while (t--) { int flag = 0; string s, t, p; cin >> s >> t >> p; int a[26] = {0}; if (s.length() > t.length()) { flag = 0; } else { for (i = 0; i < min(t.length(), s.length()) + 1; i++) { if (s[i] != t[i]) { for (int j = 0; j < p.length(); j++) { if (p[j] == t[i]) { string d = ; d = d + p[j]; s.insert(i, d); p.erase(p.begin() + j); flag = 0; break; } } if (flag == 1) { cout << NO n ; break; } } } } if (s == t && flag == 0) cout << YES n ; else if (flag == 0) cout << NO n ; } } |
#include <bits/stdc++.h> using namespace std; class Graph { public: vector<vector<int> > adjList; vector<int> indegree; Graph(int v) { adjList.resize(v); indegree.resize(v, 0); } void add(int u, int v) { adjList[u].push_back(v); indegree[v]++; } }; struct subset { int rank; int parent; }; int find(subset subsets[], int i) { if (subsets[i].parent != i) subsets[i].parent = find(subsets, subsets[i].parent); return subsets[i].parent; } void Union(subset subsets[], int x, int y) { int xroot = find(subsets, x); int yroot = find(subsets, y); if (subsets[xroot].rank > subsets[yroot].rank) { subsets[yroot].parent = xroot; } else if (subsets[xroot].rank < subsets[yroot].rank) { subsets[xroot].parent = yroot; } else { subsets[yroot].parent = xroot; subsets[xroot].rank++; } } bool TopologicalSort(Graph const &graph, vector<int> &ans, int v, subset subsets[]) { vector<int> indegree = graph.indegree; queue<int> S; for (int i = 0; i < v; i++) { if (!indegree[i]) { S.push(i); ans[find(subsets, i)] = 1; } } while (!S.empty()) { int n = S.front(); S.pop(); for (int m : graph.adjList[n]) { indegree[m] -= 1; ans[find(subsets, m)] = ans[find(subsets, n)] + 1; if (!indegree[m]) { S.push(m); } } } for (int i = 0; i < v; i++) { if (indegree[i]) { return false; } } return true; } int main() { int n, m; cin >> n >> m; subset *subsets = new subset[n + m]; for (int v = 0; v < n + m; v++) { subsets[v].parent = v; subsets[v].rank = 0; } Graph graph(n + m); char input[n][m]; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> input[i][j]; if (input[i][j] == = ) { Union(subsets, i, j + n); } } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { int x = find(subsets, i); int y = find(subsets, j + n); if (input[i][j] == < ) { graph.add(x, y); } else if (input[i][j] == > ) { graph.add(y, x); } } } vector<int> ans(n + m); if (TopologicalSort(graph, ans, n + m, subsets)) { cout << YES << endl; for (int i = 0; i < n; i++) { cout << ans[find(subsets, i)] << ; } cout << endl; for (int i = n; i < m + n; i++) { cout << ans[find(subsets, i)] << ; } cout << endl; } else { cout << NO << endl; } } |
#include <bits/stdc++.h> using namespace std; namespace red { inline long long read() { long long x = 0; char ch, f = 1; for (ch = getchar(); (ch < 0 || ch > 9 ) && ch != - ; ch = getchar()) ; if (ch == - ) f = 0, ch = getchar(); while (ch >= 0 && ch <= 9 ) { x = (x << 1) + (x << 3) + ch - 0 ; ch = getchar(); } return f ? x : -x; } const long long N = 1e6 + 10, inf = 1e9 + 7, base = 131, mod = 1e9 + 7; long long n, m, t, ret; char a[N], b[N], s[N]; long long nxt[N], f[N], g[N]; long long pw[N], ha[N], hs[N]; inline void prepare(char *a, long long *f) { long long len = max(n, m); for (long long i = pw[0] = 1; i <= len; ++i) pw[i] = pw[i - 1] * base % mod; for (long long i = 1; i <= n; ++i) ha[i] = (ha[i - 1] * base + a[i]) % mod; for (long long i = 1; i <= m; ++i) hs[i] = (hs[i - 1] * base + s[i]) % mod; for (long long i = 1; i <= n; ++i) { long long l = i, r = n; while (l <= r) { long long t1 = (ha[((l + r) >> 1)] - ha[i - 1] * pw[((l + r) >> 1) - i + 1] % mod + mod) % mod; long long t2 = hs[((l + r) >> 1) - i + 1]; if (t1 == t2) f[i] = ((l + r) >> 1) - i + 1, l = ((l + r) >> 1) + 1; else r = ((l + r) >> 1) - 1; } f[i] = min(f[i], m - 1); } } struct BIT { long long tr[N]; BIT() { memset(tr, 0, sizeof(tr)); } inline void update(long long p, long long k) { for (p++; p < N; p += p & (-p)) tr[p] += k; } inline long long query(long long p) { long long ret = 0; for (p++; p; p -= p & (-p)) ret += tr[p]; return ret; } } bit[2]; inline void main() { n = read(), m = read(); scanf( %s%s%s , a + 1, b + 1, s + 1); prepare(a, f); reverse(s + 1, s + m + 1); reverse(b + 1, b + n + 1); prepare(b, g); reverse(g + 1, g + n + 1); for (long long i = n; i; --i) { bit[0].update(g[i], 1); bit[1].update(g[i], g[i]); if (i + m - 1 <= n) { bit[0].update(g[i + m - 1], -1); bit[1].update(g[i + m - 1], -g[i + m - 1]); } if (!f[i]) continue; long long v = m - f[i]; ret += bit[1].query(m) - bit[1].query(v - 1); ret -= (bit[0].query(m) - bit[0].query(v - 1)) * (v - 1); } printf( %lld n , ret); } } // namespace red signed main() { red::main(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_DFF_P_PP_PG_N_SYMBOL_V
`define SKY130_FD_SC_HDLL__UDP_DFF_P_PP_PG_N_SYMBOL_V
/**
* udp_dff$P_pp$PG$N: Positive edge triggered D flip-flop
* (Q output UDP).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__udp_dff$P_pp$PG$N (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_DFF_P_PP_PG_N_SYMBOL_V
|
#include <bits/stdc++.h> const int maxi = 2000000000; const int maxq = 1000000000; const double eps = 1e-10; const double pi = 3.1415926535897932; const double inf = 1e+18; const int mo = 1000000007; using namespace std; long long l, r; int main() { cin >> l >> r; if (l == r) { puts( 0 ); return 0; } for (int i = 62; i >= 0; i--) { if ((1ll << (i)) > l && (1ll << (i)) <= r) { cout << (1ll << (i + 1)) - 1 << endl; return 0; } if ((1ll << (i)) <= l) { l -= (1ll << (i)); r -= (1ll << (i)); } } return 0; } |
//
// Copyright (c) 1999 Peter Monta ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
module main;
reg [3:0] a;
wire [3:0] b;
assign b = ~a;
initial begin
a = 4'b0110;
#1;
if (b===4'b1001)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
module top;
integer chr, fd, code;
reg [14*8:1] str;
initial begin
// Put a string into the file.
fd = $fopen("work/test.txt", "w");
if (fd == 0) begin
$display("Failed to open test file for writing!");
$finish;
end
$fdisplay(fd, "Hello World!");
$fclose(fd);
// Now read it back and verify that $ungetc() and other things work.
fd = $fopen("work/test.txt", "r");
if (fd == 0) begin
$display("Failed to open test file for reading!");
$finish;
end
chr = $fgetc(fd);
if (chr != "H") begin
$display("Failed first character read!");
$finish;
end
code = $ungetc(chr, fd);
if (code == -1) begin
$display("Failed to ungetc() character!");
$finish;
end
chr = $fgetc(fd);
if (chr != "H") begin
$display("Failed first character reread!");
$finish;
end
code = $ungetc(chr, fd);
if (code == -1) begin
$display("Failed to ungetc() character (2)!");
$finish;
end
code = $fgets(str, fd);
if (code == 0) begin
$display("Failed to read characters!");
$finish;
end
if (str[13*8:9] != "Hello World!") begin
$display("Read wrong characters!");
$finish;
end
$fclose(fd);
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { char puzzel[600]; vector<string> Puz; int m, n; int stp; int len = 0, judge = 0; int prevstp; int prevlen; int minv = 1000; int maxv = -9; int flag = 0; scanf( %d%d , &m, &n); for (int i = 0; i < m; i++) { scanf( %s , puzzel); Puz.push_back(puzzel); } for (int i = 0; i < m; i++) { for (int j = 0; j < n; j++) { if (Puz[i][j] == X ) { stp = j; len++; for (int k = j; k < n - 1; k++) { if (Puz[i][k + 1] == X ) { len++; } else { break; } } if (flag == 0) { flag = 1; prevlen = len; prevstp = stp; len = 0; } else { if (prevstp == stp && prevlen == len) { prevstp = stp; prevlen = len; len = 0; } else { judge = 1; } } break; } } } if (judge == 1) { printf( NO n ); } else if (flag == 1) { printf( YES n ); } return 0; } |
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_data_in (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 7: 0] in_port;
input reset_n;
wire clk_en;
wire [ 7: 0] data_in;
wire [ 7: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME :
//DEPARTMENT : IC Design / Verification
//AUTHOR : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH [32,16] : width of the data : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy :
//Clock Domains :
//Critical Timing :
//Test Features :
//Asynchronous I/F :
//Scan Methodology :
//Instantiations :
//Synthesizable (y/n) :
//Other :
//-FHDR------------------------------------------------------------------------
module fifo_tx
#(
parameter integer DWIDTH = 9,
parameter integer AWIDTH = 6
)
(
input clock, reset, wr_en, rd_en,
input [DWIDTH-1:0] data_in/* synthesis syn_noprune */,
output reg f_full,write_tx,f_empty,
output [DWIDTH-1:0] data_out/* synthesis syn_noprune */,
output reg [AWIDTH-1:0] counter/* synthesis syn_noprune */
);
reg [AWIDTH-1:0] wr_ptr/* synthesis syn_noprune */;
reg [AWIDTH-1:0] rd_ptr/* synthesis syn_noprune */;
reg [1:0] state_data_write;
reg [1:0] next_state_data_write;
reg [1:0] state_data_read;
reg [1:0] next_state_data_read;
//reg [AWIDTH-1:0] counter_writer/* synthesis syn_noprune */;
//reg [AWIDTH-1:0] counter_reader/* synthesis syn_noprune */;
/****************************************/
always@(*)
begin
next_state_data_write = state_data_write;
case(state_data_write)
2'd0:
begin
if(wr_en && !f_full)
begin
next_state_data_write = 2'd1;
end
else
begin
next_state_data_write = 2'd0;
end
end
2'd1:
begin
if(wr_en)
begin
next_state_data_write = 2'd1;
end
else
begin
next_state_data_write = 2'd2;
end
end
2'd2:
begin
next_state_data_write = 2'd0;
end
default:
begin
next_state_data_write = 2'd0;
end
endcase
end
/****************************************/
always@(*)
begin
next_state_data_read = state_data_read;
case(state_data_read)
2'd0:
begin
if(counter > 6'd0)
begin
next_state_data_read = 2'd1;
end
else
begin
next_state_data_read = 2'd0;
end
end
2'd1:
begin
if(rd_en && !f_empty)
begin
next_state_data_read = 2'd2;
end
else
begin
next_state_data_read = 2'd1;
end
end
2'd2:
begin
if(rd_en)
begin
next_state_data_read = 2'd2;
end
else
begin
next_state_data_read = 2'd3;
end
end
2'd3:
begin
next_state_data_read = 2'd0;
end
default:
begin
next_state_data_read = 2'd0;
end
endcase
end
//Write pointer
always@(posedge clock or negedge reset)
begin
if (!reset)
begin
wr_ptr <= {(AWIDTH){1'b0}};
state_data_write <= 2'd0;
end
else
begin
state_data_write <= next_state_data_write;
case(state_data_write)
2'd0:
begin
wr_ptr <= wr_ptr;
end
2'd1:
begin
wr_ptr <= wr_ptr;
end
2'd2:
begin
wr_ptr <= wr_ptr + 6'd1;
end
default:
begin
wr_ptr <= wr_ptr;
end
endcase
end
end
//FULL - EMPTY COUNTER
always@(posedge clock or negedge reset)
begin
if (!reset)
begin
f_full <= 1'b0;
f_empty <= 1'b0;
counter <= {(AWIDTH){1'b0}};
end
else
begin
if(state_data_write == 2'd2)
begin
counter <= counter + 6'd1;
end
else
begin
if(counter > 6'd0 && state_data_read == 2'd3)
counter <= counter - 6'd1;
else
counter <= counter;
end
if(counter == 6'd63)
begin
f_full <= 1'b1;
end
else
begin
f_full <= 1'b0;
end
if(counter == 6'd0)
begin
f_empty <= 1'b1;
end
else
begin
f_empty <= 1'b0;
end
end
end
//Read pointer
always@(posedge clock or negedge reset)
begin
if (!reset)
begin
rd_ptr <= {(AWIDTH){1'b0}};
write_tx <= 1'b0;
state_data_read <= 2'd0;
end
else
begin
state_data_read <= next_state_data_read;
case(state_data_read)
2'd0:
begin
write_tx<= 1'b0;
end
2'd1:
begin
if(rd_en && !f_empty)
begin
rd_ptr <= rd_ptr + 6'd1;
end
else
begin
rd_ptr <= rd_ptr;
end
write_tx<= 1'b1;
end
2'd2:
begin
write_tx<= 1'b0;
end
2'd3:
begin
write_tx<= 1'b0;
end
default:
begin
rd_ptr <= rd_ptr;
end
endcase
end
end
mem_data mem_dta_fifo_tx(
.clock(clock),
.reset(reset),
.data_in(data_in),
.wr_ptr(wr_ptr),
.rd_ptr(rd_ptr),
.data_out(data_out)
);
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:100000000000000 ) using namespace std; long long n, cnt[5], fct[1000001]; pair<long long, long long> dp[1000001]; string st; map<char, int> mp; long long pw(long long a, long long b) { if (b == 0) return 1; if (b == 1) return a; long long ret = pw(a, b / 2); (ret *= ret) %= 1000000007; if (b & 1) (ret *= a) % 1000000007; return ret; } pair<long long, long long> rec(int lef) { if (lef == 0) return make_pair(0, 1); if (~dp[lef].first) return dp[lef]; pair<long long, long long> ret = make_pair(0, 0); for (int i = 0; i < 4; i++) { pair<long long, long long> tmp = rec(lef - 1); tmp.first += cnt[i]; if (tmp.first == ret.first) (ret.second += tmp.second) %= 1000000007; else if (tmp.first > ret.first) ret = tmp; } return dp[lef] = ret; } int main() { cin >> n >> st; mp[ A ] = 0; mp[ C ] = 1; mp[ G ] = 2; mp[ T ] = 3; fct[0] = fct[1] = 1; for (int i = 0; i < st.size(); i++) cnt[mp[st[i]]]++; for (int i = 2; i < 1000001; i++) fct[i] = (fct[i - 1] * i) % 1000000007; memset((dp), (-1), sizeof(dp)); pair<long long, long long> x = rec(n); cout << x.second << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, Q, x, y, z, kk; int dis[500005], head[500005], father[500005], top[500005], q[500005]; bool vis[500005]; int far[500005], heavyson[500005], rak[500005], sum[500005], leaf[500005], ans, d[500005]; struct Tree { int nxt, to, step; } e[500005]; inline bool cmp(int u, int v) { return dis[u] - dis[father[top[u]]] > dis[v] - dis[father[top[v]]]; } inline void link(int x, int y, int z) { e[++kk].nxt = head[x]; e[kk].to = y; e[kk].step = z; head[x] = kk; } inline int bfs(int S) { int left1 = 1; int right1 = 1; q[left1] = S; memset(d, 0, sizeof(d)); memset(vis, false, sizeof(vis)); vis[S] = true; while (left1 <= right1) { int u = q[left1++]; for (int i = head[u]; i; i = e[i].nxt) { int v = e[i].to; if (vis[v]) continue; vis[v] = true; q[++right1] = v; d[v] = d[u] + e[i].step; } } int kkk = 0; for (int i = 1; i <= n; i++) { if (d[i] > d[kkk]) kkk = i; } return kkk; } void dfs1(int u, int fa) { far[u] = dis[u]; for (int i = head[u]; i; i = e[i].nxt) { int v = e[i].to; if (v == fa) continue; father[v] = u; dis[v] = dis[u] + e[i].step; dfs1(v, u); if (!heavyson[u] || far[u] < far[v]) heavyson[u] = v, far[u] = far[v]; } } void dfs2(int u, int first) { top[u] = first; if (!heavyson[u]) { leaf[++leaf[0]] = u; return; } dfs2(heavyson[u], first); for (int i = head[u]; i; i = e[i].nxt) { int v = e[i].to; if (v == father[u] || v == heavyson[u]) continue; dfs2(v, v); } } inline int solve(int x, int y) { if (rak[top[x]] <= 2 * y - 1) return sum[min(y * 2 - 1, leaf[0])]; int u = x; while (rak[top[u]] > y * 2 - 1) u = father[top[u]]; return sum[y * 2 - 1] - min(min(sum[y * 2 - 1] - sum[y * 2 - 2], far[u] - dis[u]), dis[u]) + far[x] - dis[u]; } int main() { scanf( %d%d , &n, &Q); for (int i = 1; i < n; i++) { scanf( %d%d%d , &x, &y, &z); link(x, y, z); link(y, x, z); } int first = bfs(1); int root = bfs(first); dfs1(root, -1); dfs2(root, root); sort(leaf + 1, leaf + leaf[0] + 1, cmp); for (int i = 1; i <= leaf[0]; i++) { rak[top[leaf[i]]] = i; sum[i] = sum[i - 1] + dis[leaf[i]] - dis[father[top[leaf[i]]]]; } while (Q--) { scanf( %d%d , &x, &y); x = ((x + ans - 1) % n) + 1; y = ((y + ans - 1) % n) + 1; printf( %d n , ans = solve(x, y)); } return 0; } |
#include <bits/stdc++.h> template <class T> T gcd(T a, T b) { T r; while (b != 0) { r = a % b; a = b; b = r; } return a; } template <class T> T lcm(T a, T b) { return a / gcd(a, b) * b; } using namespace std; const long long MOD = 1e9 + 7; vector<int> p, q; long long res[200005]; void act() { long long a, b, c, d, cnt = 0; cin >> a >> b >> c >> d; for (int i = 1; i <= c; i++) p.push_back(2); for (int i = 1; i <= a; i++) p.push_back(0); for (int i = 1; i <= d; i++) q.push_back(3); for (int i = 1; i <= b; i++) q.push_back(1); if (p.size() <= q.size()) swap(p, q); for (int i = 0; i < p.size(); i++) { res[++cnt] = p[i]; if (i < q.size()) res[++cnt] = q[i]; } for (int i = 1; i < cnt; i++) if (abs(res[i] - res[i + 1]) != 1) { cout << NO << n ; return; } cout << YES << n ; for (int i = 1; i <= cnt; i++) cout << res[i] << ; } int main() { int t = 1; while (t--) act(); } |
/*
* c4puter northbridge - DRAM controller to Wishbone glue
* Copyright (C) 2017 Chris Pavlina
*
* Wishbone to DDR3 glue
* from MicroBlaze MCS to DDR3 glue
* (C) Copyright 2012 Silicon On Inspiration
* www.sioi.com.au
* 86 Longueville Road
* Lane Cove 2066
* New South Wales
* AUSTRALIA
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
* You should have received a copy of the GNU Lesser General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module drac_wb_adapter (
// DRAC interface
output drac_srd_o,
output drac_swr_o,
output [33:5] drac_sa_o,
output [255:0] drac_swdat_o,
output [31:0] drac_smsk_o,
input [255:0] drac_srdat_i,
input drac_srdy_i,
input clk150,
// Wishbone slave
input [35:0] wb_adr_i,
input wb_we_i,
input [3:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
input [31:0] wb_dat_i,
output [31:0] wb_dat_o,
output wb_ack_o,
input clk75,
input reset
);
reg [31:0] rdat;
reg [255:0] wdat;
reg [31:0] msk;
reg [33:2] addr;
reg rdy1 = 1'b0;
reg rdy2 = 1'b0;
reg read = 1'b0;
reg write = 1'b0;
reg wb_stb_delay = 1'b0;
always @(posedge clk75) begin
if (wb_stb_i && !wb_stb_delay && wb_we_i) begin
case (wb_adr_i[2:0])
3'b000: wdat[31:0] <= wb_dat_i;
3'b001: wdat[63:32] <= wb_dat_i;
3'b010: wdat[95:64] <= wb_dat_i;
3'b011: wdat[127:96] <= wb_dat_i;
3'b100: wdat[159:128] <= wb_dat_i;
3'b101: wdat[191:160] <= wb_dat_i;
3'b110: wdat[223:192] <= wb_dat_i;
3'b111: wdat[255:224] <= wb_dat_i;
endcase
case (wb_adr_i[2:0])
3'b000: msk <= 32'hFFFFFFF0;
3'b001: msk <= 32'hFFFFFF0F;
3'b010: msk <= 32'hFFFFF0FF;
3'b011: msk <= 32'hFFFF0FFF;
3'b100: msk <= 32'hFFF0FFFF;
3'b101: msk <= 32'hFF0FFFFF;
3'b110: msk <= 32'hF0FFFFFF;
3'b111: msk <= 32'h0FFFFFFF;
endcase
end
if (wb_stb_i && !wb_stb_delay) begin
addr[33:2] <= wb_adr_i[31:0];
end
end
always @(posedge clk75 or posedge reset) begin
if (reset) begin
read <= 1'b0;
write <= 1'b0;
rdy2 <= 1'b0;
wb_stb_delay <= 1'b0;
end else begin
wb_stb_delay <= wb_stb_i;
if (wb_stb_i && !wb_stb_delay && !wb_we_i) begin
read <= 1'b1;
end else if (wb_stb_i && !wb_stb_delay && wb_we_i) begin
write <= 1'b1;
end
if (rdy1) begin
read <= 1'b0;
write <= 1'b0;
rdy2 <= 1'b1;
end
if (rdy2) begin
rdy2 <= 1'b0;
end
end
end
always @(posedge clk150 or posedge reset) begin
if (reset) begin
rdy1 <= 1'b0;
end else begin
if (drac_srdy_i) begin
rdy1 <= 1'b1;
end
if (rdy2) begin
rdy1 <= 1'b0;
end
if (drac_srdy_i) case (addr[4:2])
3'b000: rdat <= drac_srdat_i[31:0];
3'b001: rdat <= drac_srdat_i[63:32];
3'b010: rdat <= drac_srdat_i[95:64];
3'b011: rdat <= drac_srdat_i[127:96];
3'b100: rdat <= drac_srdat_i[159:128];
3'b101: rdat <= drac_srdat_i[191:160];
3'b110: rdat <= drac_srdat_i[223:192];
3'b111: rdat <= drac_srdat_i[255:224];
endcase
end
end
assign wb_dat_o = rdat;
assign wb_ack_o = rdy2;
assign drac_srd_o = read;
assign drac_swr_o = write;
assign drac_swdat_o = wdat;
assign drac_smsk_o = msk;
assign drac_sa_o = addr[33:5];
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mod = 998244353; template <typename T> void chkmin(T &x, T y) { if (y < x) x = y; } template <typename T> void chkmax(T &x, T y) { if (y > x) x = y; } template <typename T> void upd(T &x, T y) { if ((x += y) >= mod) x -= mod; } int n, m, K, N, sl, fh, a[510][510]; int rd() { sl = 0; fh = 1; char ch = getchar(); while (ch < 0 || 9 < ch) { if (ch == - ) fh = -1; ch = getchar(); } while ( 0 <= ch && ch <= 9 ) sl = sl * 10 + ch - 0 , ch = getchar(); return sl * fh; } int main() { ios::sync_with_stdio(false); K = rd(); for (N = 1; N <= K; N <<= 1) ; a[1][1] = a[1][2] = a[1][3] = (N << 1) - 1; a[3][1] = a[3][2] = a[3][3] = (N << 1) - 1; a[2][3] = a[3][4] = K; a[2][1] = N; a[2][2] = N << 1; n = 3; m = 4; printf( %d %d n , n, m); for (int i = 1; i <= n; ++i, puts( )) for (int j = 1; j <= m; ++j) printf( %d , a[i][j]); return 0; } |
#include <bits/stdc++.h> using namespace std; char str[5003]; int num[5003][2]; int main() { while (~scanf( %s , str + 1)) { memset(num, 0, sizeof(num)); int len = strlen(str + 1); for (int i = 1; i <= len; i++) { num[i][0] = num[i - 1][0]; num[i][1] = num[i - 1][1]; if (str[i] == a ) num[i][0]++; else num[i][1]++; } int ans = len + 1; for (int i = 1; i <= len + 1; ++i) { for (int j = i; j <= len + 1; ++j) { int x1 = 0, x2 = 0, x3 = 0; if (i > 1) x1 = num[i - 1][1] - num[0][1]; if (j > i) x2 = num[j - 1][0] - num[i - 1][0]; if (j <= len) x3 = num[len][1] - num[j - 1][1]; ans = min(ans, x1 + x2 + x3); } } printf( %d n , len - ans); } return 0; } |
// Copyright (C) 2005 Peio Azkarate,
// Copyright (C) 2006 Jeff Carr,
// Copyleft GPL v2
module pcidec_new (clk_i, nrst_i, ad_i, cbe_i, idsel_i, bar0_i, memEN_i,
pciadrLD_i, adrcfg_o, adrmem_o, adr_o, cmd_o);
// General
input clk_i;
input nrst_i;
// pci
input [31:0] ad_i;
input [3:0] cbe_i;
input idsel_i;
// control
input [31:25] bar0_i;
input memEN_i;
input pciadrLD_i;
output adrcfg_o;
output adrmem_o;
output [24:1] adr_o;
output [3:0] cmd_o;
reg [31:0] adr;
reg [3:0] cmd;
reg idsel_s;
wire a1;
//+-------------------------------------------------------------------------+
//| Load PCI Signals |
//+-------------------------------------------------------------------------+
always @( negedge nrst_i or posedge clk_i )
begin
if( nrst_i == 0 )
begin
adr <= 23'b1111_1111_1111_1111_1111_111;
cmd <= 3'b111;
idsel_s <= 1'b0;
end
else
if ( pciadrLD_i == 1 )
begin
adr <= ad_i;
cmd <= cbe_i;
idsel_s <= idsel_i;
end
end
assign adrmem_o = (
( memEN_i == 1'b1 ) &&
( adr [31:25] == bar0_i ) &&
( adr [1:0] == 2'b00 ) &&
( cmd [3:1] == 3'b011 )
) ? 1'b1 : 1'b0;
assign adrcfg_o = (
( idsel_s == 1'b1 ) &&
( adr [1:0] == 2'b00 ) &&
( cmd [3:1] == 3'b101 )
) ? 1'b1 : 1'b0;
assign a1 = ~ ( cbe_i [3] && cbe_i [2] );
assign adr_o = {adr [24:2], a1};
assign cmd_o = cmd;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DIODE_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__DIODE_PP_BLACKBOX_V
/**
* diode: Antenna tie-down diode.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__diode (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DIODE_PP_BLACKBOX_V
|
module grom_top
(input i_Clk, // Main Clock
input i_Switch_1, // SW1 button
output o_LED_1,
output o_LED_2,
output o_LED_3,
output o_LED_4,
// Segment1 is upper digit, Segment2 is lower digit
output o_Segment1_A,
output o_Segment1_B,
output o_Segment1_C,
output o_Segment1_D,
output o_Segment1_E,
output o_Segment1_F,
output o_Segment1_G,
//
output o_Segment2_A,
output o_Segment2_B,
output o_Segment2_C,
output o_Segment2_D,
output o_Segment2_E,
output o_Segment2_F,
output o_Segment2_G
);
wire [7:0] display_out;
wire hlt;
grom_computer computer(.clk(i_Clk),.reset(i_Switch_1),.hlt(hlt),.display_out(display_out));
hex_to_7seg upper_digit
(.i_Clk(i_Clk),
.i_Value(display_out[7:4]),
.o_Segment_A(o_Segment1_A),
.o_Segment_B(o_Segment1_B),
.o_Segment_C(o_Segment1_C),
.o_Segment_D(o_Segment1_D),
.o_Segment_E(o_Segment1_E),
.o_Segment_F(o_Segment1_F),
.o_Segment_G(o_Segment1_G));
hex_to_7seg lower_digit
(.i_Clk(i_Clk),
.i_Value(display_out[3:0]),
.o_Segment_A(o_Segment2_A),
.o_Segment_B(o_Segment2_B),
.o_Segment_C(o_Segment2_C),
.o_Segment_D(o_Segment2_D),
.o_Segment_E(o_Segment2_E),
.o_Segment_F(o_Segment2_F),
.o_Segment_G(o_Segment2_G));
assign o_LED_1 = hlt;
assign o_LED_2 = 1'b0;
assign o_LED_3 = 1'b1;
assign o_LED_4 = 1'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> vec(n); for (int i = 0; i < n; ++i) cin >> vec[i]; int sum = accumulate(vec.begin(), vec.end(), 0); if ((sum / 100) % 2 != 0) { cout << NO n ; return 0; } sum /= 2; int num_one = count(vec.begin(), vec.end(), 100); int num_two = count(vec.begin(), vec.end(), 200); int curr = 0; while (curr <= sum && num_two > 0) { curr += 200; num_two--; } if (curr == sum) { cout << YES n ; return 0; } if (curr > sum) curr -= 200; while (curr != sum && num_one > 0) { curr += 100; num_one--; } if (curr == sum) cout << YES n ; else cout << NO n ; } |
#include <bits/stdc++.h> using namespace std; const int N = 2005; const int M = 1 << 16; bitset<N> mp[M]; int a[N], sum, rk[N], k, n; priority_queue<pair<int, int> > que; void dfs(int s, int t) { if (s == 0) return; int r = 0; for (; t * k < N && mp[s][t * k]; r++, t *= k) { } for (int i = 0; i < n; i++) { if (s & (1 << i)) rk[i] += r; } for (int i = 0; i < n; i++) { if (s & (1 << i) && t >= a[i] && mp[s - (1 << i)][t - a[i]]) { dfs(s - (1 << i), t - a[i]); return; } } } int main() { sum = 0; scanf( %d%d , &n, &k); for (int i = 0; i < n; i++) { scanf( %d , a + i); sum += a[i]; } mp[0][0] = 1; for (int s = 1; s < (1 << n); s++) { for (int i = 0; i < n; i++) { if (s & (1 << i)) mp[s] |= mp[s - (1 << i)] << a[i]; } for (int i = sum / k; i >= 1; i--) { if (mp[s][i * k]) mp[s][i] = 1; } } if (!mp[(1 << n) - 1][1]) { puts( NO ); return 0; } puts( YES ); dfs((1 << n) - 1, 1); for (int i = 0; i < n; i++) { que.push({rk[i], a[i]}); } while (que.size() != 1) { pair<int, int> u = que.top(); que.pop(); pair<int, int> v = que.top(); que.pop(); printf( %d %d n , u.second, v.second); u.second += v.second; while (u.second % k == 0) { u.second /= k; u.first--; } que.push(u); } } |
#include <bits/stdc++.h> using namespace std; const int maxn = 3e5 + 10; int n, b[maxn]; pair<int, int> a[maxn]; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i].first); a[i].second = i; } sort(a + 1, a + 1 + n); reverse(a + 1, a + 1 + n); for (int i = 1; i <= n; i++) { b[i] = a[i].second * 2 - 1; if (i > 1) printf( %d %d n , b[i], b[i - 1]); } int res, cur = n, des; for (int i = 1; i <= n; i++) { res = a[i].second * 2; des = i + a[i].first - 1; if (des >= cur) { b[++cur] = res; printf( %d %d n , res, b[cur - 1]); } else printf( %d %d n , res, b[des]); } } |
#include <bits/stdc++.h> using namespace std; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long k; cin >> k; long long res[4][4]; for (long long i = 0; i < 4; ++i) { for (long long j = 0; j < 4; ++j) { if (i == 1 && j == 2) { res[i][j] = (1 << 17); } else if (i == 2 && j == 1) { res[i][j] = (1 << 17); } else if ((i + j) == 3) { res[i][j] = k; } else if (i == 3 && j == 3) { res[i][j] = k; } else { res[i][j] = (k + (1 << 17)); } } } cout << 4 << << 4 << endl; for (long long i = 0; i < 4; ++i) { for (long long j = 0; j < 4; ++j) { cout << res[i][j] << ; } cout << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; int a[110]; for (int i = 0; i < n; i++) { cin >> a[i]; } int i, one, two, j, ans = 0; for (i = 0; i < k; i++) { for (one = 0, two = 0, j = i; j < n; j += k) { if (a[j] == 1) one++; else two++; } ans += min(one, two); } cout << ans; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O311A_M_V
`define SKY130_FD_SC_LP__O311A_M_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog wrapper for o311a with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o311a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o311a_m (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o311a_m (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O311A_M_V
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2012, Ameer M. Abdelhadi; . All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// bcd7seg.v: BCD 7-segment Decoder //
// //
// Ameer M.S. Abdelhadi (; ), Sept. 2012 //
////////////////////////////////////////////////////////////////////////////////////
module bcd7seg (
input [3:0] bcd,
output reg [6:0] seg
);
always @(*) begin
case(bcd)
4'h0 : seg = 7'b1000000;
4'h1 : seg = 7'b1111001;
4'h2 : seg = 7'b0100100;
4'h3 : seg = 7'b0110000;
4'h4 : seg = 7'b0011001;
4'h5 : seg = 7'b0010010;
4'h6 : seg = 7'b0000010;
4'h7 : seg = 7'b1111000;
4'h8 : seg = 7'b0000000;
4'h9 : seg = 7'b0011000;
default: seg = 7'bXXXXXXX;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = 1e9; int n, m; char a[5555][5555]; int r[5555][5555]; int c[5555]; int ans = 0; int main() { int i, j; cin >> n >> m; for (i = 1; i <= n; ++i) { getchar(); for (j = 1; j <= m; ++j) { a[i][j] = getchar(); } } for (i = n; i >= 1; --i) for (j = m; j >= 1; --j) { if (a[i][j] == 0 ) r[i][j] = 0; else r[i][j] = r[i][j + 1] + 1; } for (j = 1; j <= m; ++j) { int k = 0; for (i = 1; i <= m; ++i) { c[i] = 0; } for (i = 1; i <= n; ++i) { c[r[i][j]]++; if (r[i][j]) k++; } for (i = 1; i <= m; ++i) { if (c[i]) ans = max(ans, i * k); k -= c[i]; } } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; const int mod = 7 + (int)1e9; long long process(string s) { for (int i = 0; i < s.size(); i++) s[i] = (s[i] - 0 ) % 2 + 0 ; return stoll(s); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n; char c; map<long long, int> m; cin >> n; while (n--) { string a; cin >> c >> a; if (c == + ) { m[process(a)]++; } else if (c == - ) { m[process(a)]--; } else if (c == ? ) { cout << m[stoll(a)] << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; int n, m, a, b, c, p[100010], cnt; bool vis[100010], ed; vector<pair<int, int> > V[100010]; int powmod(int x, int y) { int res = 1, cro = x; while (y) { if (y % 2) res = 1ll * res * cro % mod; cro = 1ll * cro * cro % mod; y /= 2; } return res; } void dfs(int x) { vis[x] = 1; for (int i = 0; i < V[x].size(); i++) { int y = V[x][i].first; int z = V[x][i].second; if (vis[y]) { if (p[y] != p[x] ^ z) ed = 1; continue; } else { p[y] = p[x] ^ z; vis[y] = 1; dfs(y); } } } int main() { scanf( %d%d , &n, &m); while (m--) { scanf( %d%d%d , &a, &b, &c); V[a].push_back(make_pair(b, c ^ 1)); V[b].push_back(make_pair(a, c ^ 1)); } ed = 0; for (int i = 1; i <= n; i++) { if (!vis[i]) { dfs(i); cnt++; } } if (ed) puts( 0 ); else printf( %d , powmod(2, cnt - 1)); } |
#include <bits/stdc++.h> using namespace std; void solution() { long long n; cin >> n; vector<vector<long long>> v(n, vector<long long>(n, 0)); if (n % 2 != 0) { v[n - 1][(n - 1) / 2] = 1; v[(n - 1) / 2][n - 1] = 1; } for (long long i = 0; i < n; i++) { for (long long j = 0; j < n; j++) { if (i == j || i == n - j - 1) v[i][j] = 1; cout << v[i][j] << ; } cout << n ; } } int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long t; cin >> t; while (t--) solution(); } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n; cin >> n; string s; for (int i = 1; i <= n; i++) { string str; ostringstream temp; temp << i; s += temp.str(); } cout << s[n - 1] << endl; } |
#include <bits/stdc++.h> using namespace std; int n, m; long long a[100005]; long long sum1[100005], sum2[100005]; int main() { memset(sum1, 0, sizeof(sum1)); memset(sum2, 0, sizeof(sum2)); cin >> n; for (int i = 1; i <= n; ++i) { cin >> a[i]; sum1[i] = sum1[i - 1] + a[i]; } sort(a + 1, a + n + 1); for (int i = 1; i <= n; ++i) { sum2[i] = sum2[i - 1] + a[i]; } cin >> m; for (int i = 0; i < m; ++i) { int q, l, r; cin >> q >> l >> r; if (q == 1) { cout << sum1[r] - sum1[l - 1] << endl; } else { cout << sum2[r] - sum2[l - 1] << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; inline long long rd() { char c; while (c = getchar(), c < 0 || c > 9 ) ; long long X = c - 48; while (c = getchar(), c >= 0 && c <= 9 ) X = X * 10 + c - 48; return X; } template <class T> inline void print(T x) { if (x < 0) { putchar( - ); return print(-x); } if (x < 10) { putchar( 0 + x); return; } print(x / 10); putchar(x % 10 + 0 ); } string s; void solve(int n, vector<int> &a) { if (n == 1) { s = B ; return; } vector<int> idx(n + 1); s = string(n, B ); for (__typeof(0) i = (0) - ((0) > (n)); i != (n) - ((0) > (n)); i += 1 - (((0) > (n)) << 1)) idx[a[i]] = i; for (__typeof(n + 1) i = (n + 1) - ((n + 1) > (1)); i != (1) - ((n + 1) > (1)); i += 1 - (((n + 1) > (1)) << 1)) { for (int j = idx[i] - i; j >= 0; j -= i) { if (a[j] > i and s[j] == B ) { s[idx[i]] = A ; break; } } for (int j = idx[i] + i; j < n; j += i) { if (a[j] > i and s[j] == B ) { s[idx[i]] = A ; break; } } } } int32_t main() { int n; cin >> n; vector<int> a(n); for (int &i : a) cin >> i; solve(n, a); cout << s << n ; return 0; } |
// Check behaviour with out-of-range and undefined array indices
// on LHS of procedural continuous (net) assignment.
module top;
wire [1:0] array1[2:1];
wire [1:0] array2[1:0];
reg [1:0] var1;
assign array1[1] = 2'd0;
assign array1[2] = 2'd0;
assign array2[0] = 2'd0;
assign array2[1] = 2'd0;
`ifdef __ICARUS__
wire real array3[2:1];
wire real array4[1:0];
real var2;
assign array3[1] = 0.0;
assign array3[2] = 0.0;
assign array4[0] = 0.0;
assign array4[1] = 0.0;
`endif
reg failed;
initial begin
failed = 0;
force array1[0] = 2'd1;
#1 $display("array = %h %h", array1[2], array1[1]);
if ((array1[1] !== 2'd0) || (array1[2] !== 2'd0)) failed = 1;
release array1[0];
force array1[1] = 2'd1;
#1 $display("array = %h %h", array1[2], array1[1]);
if ((array1[1] !== 2'd1) || (array1[2] !== 2'd0)) failed = 1;
release array1[1];
force array1[2] = var1;
var1 = 2'd1;
#1 $display("array = %h %h", array1[2], array1[1]);
if ((array1[1] !== 2'd0) || (array1[2] !== 2'd1)) failed = 1;
var1 = 2'd2;
#1 $display("array = %h %h", array1[2], array1[1]);
if ((array1[1] !== 2'd0) || (array1[2] !== 2'd2)) failed = 1;
release array1[2];
force array1[3] = var1;
#1 $display("array = %h %h", array1[2], array1[1]);
if ((array1[1] !== 2'd0) || (array1[2] !== 2'd0)) failed = 1;
release array1[3];
force array2['bx] = 2'd1;
#1 $display("array = %h %h", array2[1], array2[0]);
if ((array2[0] !== 2'd0) || (array2[1] !== 2'd0)) failed = 1;
release array2['bx];
`ifdef __ICARUS__
force array3[0] = 1.0;
#1 $display("array = %0g %0g", array3[2], array3[1]);
if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1;
release array3[0];
force array3[1] = 1.0;
#1 $display("array = %0g %0g", array3[2], array3[1]);
if ((array3[1] != 1.0) || (array3[2] != 0.0)) failed = 1;
release array3[1];
force array3[2] = var2;
var2 = 1.0;
#1 $display("array = %0g %0g", array3[2], array3[1]);
if ((array3[1] != 0.0) || (array3[2] != 1.0)) failed = 1;
var2 = 2.0;
#1 $display("array = %0g %0g", array3[2], array3[1]);
if ((array3[1] != 0.0) || (array3[2] != 2.0)) failed = 1;
release array3[2];
force array3[3] = var2;
#1 $display("array = %0g %0g", array3[2], array3[1]);
if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1;
release array3[3];
force array4['bx] = 1.0;
#1 $display("array = %0g %0g", array4[1], array4[0]);
if ((array4[0] != 0.0) || (array4[1] != 0.0)) failed = 1;
release array4['bx];
`endif
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0); const double eps = 1e-6; vector<int> mp[105], ans; char s[105][105]; int len[105], tmp[30]; queue<int> q; bool solve(int x, int y) { for (int i = 0; i < len[x] && i < len[y]; i++) { if (s[x][i] != s[y][i]) { mp[s[x][i] - a ].push_back(s[y][i] - a ); tmp[s[y][i] - a ]++; return true; } } if (len[x] > len[y]) return false; } bool ok() { for (int i = 0; i < 26; i++) if (tmp[i] == 0) { ans.push_back(i); q.push(i); } while (!q.empty()) { int u = q.front(); q.pop(); for (int i = 0; i < mp[u].size(); i++) { int v = mp[u][i]; tmp[v]--; if (tmp[v] == 0) { q.push(v); ans.push_back(v); } } } return ans.size() == 26; } int main() { int n; while (~scanf( %d , &n)) { for (int i = 1; i <= n; i++) { scanf( %s , s[i]); len[i] = strlen(s[i]); } bool flag = 0; for (int i = 1; i <= n; i++) for (int j = i + 1; j <= n; j++) if (!solve(i, j)) flag = 1; if ((!flag) && ok()) { for (int i = 0; i < 26; i++) printf( %c , ans[i] + a ); printf( n ); } else printf( Impossible n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main(void) { int n, max = 0; string a[100]; cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) { int count = 0; for (int j = 0; j < n; j++) { if (i != j) { if (a[i].compare(a[j]) == 0) count++; } } if (count > max) max = count; } cout << max + 1; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m; char s[1008][1008], last[1008][1008]; int a[58][58]; int flag[58], x[58], y[58]; int ans, tot; bool in[8][8]; struct Tprogram { void open() { freopen( 1.in , r , stdin); freopen( 1.out , w , stdout); } void close() {} void init() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) scanf( %s , &s[i][1]); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { if (s[i][j] != . && !a[i][j]) a[i][j] = a[i + 1][j] = a[i][j + 1] = a[i + 1][j + 1] = ++tot; if (s[i][j] != . ) { int t = s[i][j]; t = t <= B ? t - 64 : t - 94; if (!x[t]) x[t] = a[i][j]; else y[t] = a[i][j]; } } } void dfs(int c, int d) { if (d > 14) { memset(in, 0, sizeof(in)); for (int i = 1; i <= 28; i++) if (!in[flag[x[i]]][flag[y[i]]]) in[flag[x[i]]][flag[y[i]]] = in[flag[y[i]]][flag[x[i]]] = 1; else return; ++ans; if (ans == 1) { for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { if (a[i][j]) last[i][j] = flag[a[i][j]] - 1 + 0 ; else last[i][j] = . ; } } return; } if (flag[d]) dfs(c, d + 1); else { flag[d] = c; for (int i = d + 1; i <= 14; i++) if (!flag[i]) { flag[i] = c; dfs(c + 1, d + 1); flag[i] = 0; } flag[d] = 0; } } void work() { dfs(1, 1); printf( %d n , ans * 5040); for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) printf( %c , last[i][j]); printf( n ); } } } Program; int main() { Program.init(); Program.work(); return 0; } |
#include <bits/stdc++.h> int main() { int n, w, cnt1, cnt2; scanf( %d , &n); cnt1 = cnt2 = 0; while (n-- > 0) { scanf( %d , &w); if (w == 100) cnt1++; else cnt2++; } printf( %s n , cnt1 % 2 == 0 && (cnt2 % 2 == 0 || cnt1 >= 2) ? YES : NO ); return 0; } |
//////////////////////////////////////////////////////////////////
// //
// 8KBytes SRAM configured with boot software //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Holds just enough software to get the system going. //
// The boot loader fits into this 8KB embedded SRAM on the //
// FPGA and enables it to load large applications via the //
// serial port (UART) into the DDR3 memory //
// //
// Author(s): //
// - Conor Santifort, //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
module boot_mem32 #(
parameter WB_DWIDTH = 32,
parameter WB_SWIDTH = 4,
parameter MADDR_WIDTH = 12
)(
input i_wb_clk, // WISHBONE clock
input [31:0] i_wb_adr,
input [WB_SWIDTH-1:0] i_wb_sel,
input i_wb_we,
output [WB_DWIDTH-1:0] o_wb_dat,
input [WB_DWIDTH-1:0] i_wb_dat,
input i_wb_cyc,
input i_wb_stb,
output o_wb_ack,
output o_wb_err
);
wire start_write;
wire start_read;
`ifdef AMBER_WISHBONE_DEBUG
reg [7:0] jitter_r = 8'h0f;
reg [1:0] start_read_r = 'd0;
`else
reg start_read_r = 'd0;
`endif
wire [WB_DWIDTH-1:0] read_data;
wire [WB_DWIDTH-1:0] write_data;
wire [WB_SWIDTH-1:0] byte_enable;
wire [MADDR_WIDTH-1:0] address;
// Can't start a write while a read is completing. The ack for the read cycle
// needs to be sent first
`ifdef AMBER_WISHBONE_DEBUG
assign start_write = i_wb_stb && i_wb_we && !(|start_read_r) && jitter_r[0];
`else
assign start_write = i_wb_stb && i_wb_we && !(|start_read_r);
`endif
assign start_read = i_wb_stb && !i_wb_we && !start_read_r;
`ifdef AMBER_WISHBONE_DEBUG
always @( posedge i_wb_clk )
jitter_r <= {jitter_r[6:0], jitter_r[7] ^ jitter_r[4] ^ jitter_r[1]};
always @( posedge i_wb_clk )
if (start_read)
start_read_r <= {3'd0, start_read};
else if (o_wb_ack)
start_read_r <= 'd0;
else
start_read_r <= {start_read_r[2:0], start_read};
`else
always @( posedge i_wb_clk )
start_read_r <= start_read;
`endif
assign o_wb_err = 1'd0;
assign write_data = i_wb_dat;
assign byte_enable = i_wb_sel;
assign o_wb_dat = read_data;
assign address = i_wb_adr[MADDR_WIDTH+1:2];
`ifdef AMBER_WISHBONE_DEBUG
assign o_wb_ack = i_wb_stb && ( start_write || start_read_r[jitter_r[1]] );
`else
assign o_wb_ack = i_wb_stb && ( start_write || start_read_r );
`endif
// ------------------------------------------------------
// Instantiate SRAMs
// ------------------------------------------------------
//
`ifdef XILINX_FPGA
xs6_sram_4096x32_byte_en
#(
// This file holds a software image used for FPGA simulations
// This pre-processor syntax works with both the simulator
// and ISE, which I couldn't get to work with giving it the
// file name as a define.
`ifdef BOOT_MEM_PARAMS_FILE
`include `BOOT_MEM_PARAMS_FILE
`else
`ifdef BOOT_LOADER_ETHMAC
`include "boot-loader-ethmac_memparams32.v"
`else
// default file
`include "boot-loader_memparams32.v"
`endif
`endif
)
`endif
`ifndef XILINX_FPGA
generic_sram_byte_en
#(
.DATA_WIDTH ( WB_DWIDTH ),
.ADDRESS_WIDTH ( MADDR_WIDTH )
)
`endif
u_mem (
.i_clk ( i_wb_clk ),
.i_write_enable ( start_write ),
.i_byte_enable ( byte_enable ),
.i_address ( address ), // 2048 words, 32 bits
.o_read_data ( read_data ),
.i_write_data ( write_data )
);
// =======================================================================================
// =======================================================================================
// =======================================================================================
// Non-synthesizable debug code
// =======================================================================================
//synopsys translate_off
`ifdef XILINX_SPARTAN6_FPGA
`ifdef BOOT_MEM_PARAMS_FILE
initial
$display("Boot mem file is %s", `BOOT_MEM_PARAMS_FILE );
`endif
`endif
//synopsys translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e3 + 10; const int MOD = 1e9 + 7; long long bit[maxn], n, k; long long sum(int i) { long long s = 0; while (i > 0) { s += bit[i]; s %= MOD; i -= i & -i; } return s; } void add(int i, long long x) { while (i <= n) { bit[i] += x; bit[i] %= MOD; i += i & -i; } } long long dp[maxn]; long long a[maxn]; long long quick_mod(long long a, long long b) { long long ans = 1; a %= MOD; while (b) { if (b & 1) { ans = ans * a % MOD; b--; } b >>= 1; a = a * a % MOD; } return ans; } long long C(long long n, long long m) { if (m > n) return 0; long long ans = 1; for (int i = 1; i <= m; i++) { long long a = (n + i - m) % MOD; long long b = i % MOD; ans = ans * (a * quick_mod(b, MOD - 2) % MOD) % MOD; } return ans; } long long Lucas(long long n, long long m) { if (m == 0) return 1; return C(n % MOD, m % MOD) * Lucas(n / MOD, m / MOD) % MOD; } long long combine[maxn]; void init_combine() { for (int i = 1; i <= n; i++) combine[i] = Lucas(k + i - 1, i); } int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n >> k; for (int i = 1; i <= n; i++) { cin >> a[i]; } dp[1] = a[1]; init_combine(); for (int i = 2; i <= n; i++) { dp[i] = a[i]; for (int j = 1; j <= i - 1; j++) { dp[i] += (combine[j] * a[i - j]) % MOD; dp[i] %= MOD; } } for (int i = 1; i <= n; i++) cout << dp[i] << ; cout << endl; return 0; } |
//-----------------------------------------------------------------
// RISC-V Core
// V1.0.1
// Ultra-Embedded.com
// Copyright 2014-2019
//
//
//
// License: BSD
//-----------------------------------------------------------------
//
// Copyright (c) 2014-2019, Ultra-Embedded.com
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer
// in the documentation and/or other materials provided with the
// distribution.
// - Neither the name of the author nor the names of its contributors
// may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
// SUCH DAMAGE.
//-----------------------------------------------------------------
module riscv_alu
(
// Inputs
input [ 3:0] alu_op_i
,input [ 31:0] alu_a_i
,input [ 31:0] alu_b_i
// Outputs
,output [ 31:0] alu_p_o
);
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
`include "riscv_defs.v"
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [31:0] result_r;
reg [31:16] shift_right_fill_r;
reg [31:0] shift_right_1_r;
reg [31:0] shift_right_2_r;
reg [31:0] shift_right_4_r;
reg [31:0] shift_right_8_r;
reg [31:0] shift_left_1_r;
reg [31:0] shift_left_2_r;
reg [31:0] shift_left_4_r;
reg [31:0] shift_left_8_r;
wire [31:0] sub_res_w = alu_a_i - alu_b_i;
//-----------------------------------------------------------------
// ALU
//-----------------------------------------------------------------
always @ (alu_op_i or alu_a_i or alu_b_i or sub_res_w)
begin
shift_right_fill_r = 16'b0;
shift_right_1_r = 32'b0;
shift_right_2_r = 32'b0;
shift_right_4_r = 32'b0;
shift_right_8_r = 32'b0;
shift_left_1_r = 32'b0;
shift_left_2_r = 32'b0;
shift_left_4_r = 32'b0;
shift_left_8_r = 32'b0;
case (alu_op_i)
//----------------------------------------------
// Shift Left
//----------------------------------------------
`ALU_SHIFTL :
begin
if (alu_b_i[0] == 1'b1)
shift_left_1_r = {alu_a_i[30:0],1'b0};
else
shift_left_1_r = alu_a_i;
if (alu_b_i[1] == 1'b1)
shift_left_2_r = {shift_left_1_r[29:0],2'b00};
else
shift_left_2_r = shift_left_1_r;
if (alu_b_i[2] == 1'b1)
shift_left_4_r = {shift_left_2_r[27:0],4'b0000};
else
shift_left_4_r = shift_left_2_r;
if (alu_b_i[3] == 1'b1)
shift_left_8_r = {shift_left_4_r[23:0],8'b00000000};
else
shift_left_8_r = shift_left_4_r;
if (alu_b_i[4] == 1'b1)
result_r = {shift_left_8_r[15:0],16'b0000000000000000};
else
result_r = shift_left_8_r;
end
//----------------------------------------------
// Shift Right
//----------------------------------------------
`ALU_SHIFTR, `ALU_SHIFTR_ARITH:
begin
// Arithmetic shift? Fill with 1's if MSB set
if (alu_a_i[31] == 1'b1 && alu_op_i == `ALU_SHIFTR_ARITH)
shift_right_fill_r = 16'b1111111111111111;
else
shift_right_fill_r = 16'b0000000000000000;
if (alu_b_i[0] == 1'b1)
shift_right_1_r = {shift_right_fill_r[31], alu_a_i[31:1]};
else
shift_right_1_r = alu_a_i;
if (alu_b_i[1] == 1'b1)
shift_right_2_r = {shift_right_fill_r[31:30], shift_right_1_r[31:2]};
else
shift_right_2_r = shift_right_1_r;
if (alu_b_i[2] == 1'b1)
shift_right_4_r = {shift_right_fill_r[31:28], shift_right_2_r[31:4]};
else
shift_right_4_r = shift_right_2_r;
if (alu_b_i[3] == 1'b1)
shift_right_8_r = {shift_right_fill_r[31:24], shift_right_4_r[31:8]};
else
shift_right_8_r = shift_right_4_r;
if (alu_b_i[4] == 1'b1)
result_r = {shift_right_fill_r[31:16], shift_right_8_r[31:16]};
else
result_r = shift_right_8_r;
end
//----------------------------------------------
// Arithmetic
//----------------------------------------------
`ALU_ADD :
begin
result_r = (alu_a_i + alu_b_i);
end
`ALU_SUB :
begin
result_r = sub_res_w;
end
//----------------------------------------------
// Logical
//----------------------------------------------
`ALU_AND :
begin
result_r = (alu_a_i & alu_b_i);
end
`ALU_OR :
begin
result_r = (alu_a_i | alu_b_i);
end
`ALU_XOR :
begin
result_r = (alu_a_i ^ alu_b_i);
end
//----------------------------------------------
// Comparision
//----------------------------------------------
`ALU_LESS_THAN :
begin
result_r = (alu_a_i < alu_b_i) ? 32'h1 : 32'h0;
end
`ALU_LESS_THAN_SIGNED :
begin
if (alu_a_i[31] != alu_b_i[31])
result_r = alu_a_i[31] ? 32'h1 : 32'h0;
else
result_r = sub_res_w[31] ? 32'h1 : 32'h0;
end
default :
begin
result_r = alu_a_i;
end
endcase
end
assign alu_p_o = result_r;
endmodule
|
module aludec(funct, aluop, alucontrol, signd, multseld);
input [5:0] funct;
input [3:0] aluop;
output reg [2:0] alucontrol;
output reg signd, multseld;
always @(*) begin
case(aluop)
4'b0000: begin alucontrol <= 3'b010; signd <= 1'b1; multseld <= 1'b0; end // add (for lw/sw/addi)
4'b0010: begin
case(funct) // R-type instructions
6'b100000: begin alucontrol <= 3'b010; signd <= 1'b1; multseld <= 1'b0; end // add
6'b100001: begin alucontrol <= 3'b010; signd <= 1'b0; multseld <= 1'b0; end // addu
6'b100010: begin alucontrol <= 3'b110; signd <= 1'b1; multseld <= 1'b0; end // sub
6'b100011: begin alucontrol <= 3'b110; signd <= 1'b0; multseld <= 1'b0; end // subu
6'b100100: begin alucontrol <= 3'b000; signd <= 1'b1; multseld <= 1'b0; end // and
6'b100101: begin alucontrol <= 3'b001; signd <= 1'b1; multseld <= 1'b0; end // or
6'b101010: begin alucontrol <= 3'b111; signd <= 1'b1; multseld <= 1'b0; end // slt
6'b101011: begin alucontrol <= 3'b111; signd <= 1'b0; multseld <= 1'b0; end // sltu
6'b100110: begin alucontrol <= 3'b011; signd <= 1'b1; multseld <= 1'b0; end // xor
6'b011000: begin alucontrol <= 3'bxxx; signd <= 1'b1; multseld <= 1'b1; end // mult
6'b011001: begin alucontrol <= 3'bxxx; signd <= 1'b0; multseld <= 1'b1; end // multu
default: begin alucontrol <= 3'bxxx; signd <= 1'b0; multseld <= 1'b0; end // ???
endcase
end
4'b0001: begin alucontrol <= 3'b110; signd <= 1'b1; multseld <= 1'b0; end // sub (for beq)
4'b0011: begin alucontrol <= 3'b001; signd <= 1'b1; multseld <= 1'b0; end // or (for ori)
4'b0100: begin alucontrol <= 3'b000; signd <= 1'b1; multseld <= 1'b0; end // andi
4'b0101: begin alucontrol <= 3'b011; signd <= 1'b1; multseld <= 1'b0; end // xori
4'b0110: begin alucontrol <= 3'b111; signd <= 1'b1; multseld <= 1'b0; end // slti
4'b0111: begin alucontrol <= 3'b011; signd <= 1'b0; multseld <= 1'b0; end // addiu
4'b1000: begin alucontrol <= 3'b111; signd <= 1'b0; multseld <= 1'b0; end // sltiu
default: begin alucontrol <= 3'bxxx; signd <= 1'b0; multseld <= 1'b0; end
endcase
end
endmodule |
#include <bits/stdc++.h> #pragma GCC optimize(2) using namespace std; const int maxn = 2e5 + 10, mod = 1e9 + 7, inf = 0x3f3f3f3f; int n, a[maxn]; int main() { ios::sync_with_stdio(0); cin.tie(0); int _t; cin >> _t; while (_t--) { cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; bool isok = true; sort(a + 1, a + 1 + n); for (int i = 2; i <= n; i++) if (a[i] - a[i - 1] > 1) isok = false; (isok ? cout << YES n : cout << NO n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int a, b, c, d; int ansa, ansb, ansc; int read() { int x = 0, f = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = x * 10 + c - 0 ; c = getchar(); } return x * f; } int main() { a = read(); b = read(); c = read(); d = read(); if (c * 2 < d || d * 2 < c || a <= d || b <= d) { printf( -1 ); return 0; } printf( %d n%d n%d , a * 2, b * 2, min(c * 2, d * 2)); return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = 0x7f7f7f7f; int main() { string s; cin >> s; int ans = 0; stack<char> S; for (int i = 0; i < s.length(); i++) { if (S.empty()) { S.push(s[i]); } else if (S.top() == s[i]) { ans++; S.pop(); } else { S.push(s[i]); } } if (ans % 2 == 0) cout << No << endl; else cout << Yes << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int dx[4] = {1, 0, -1, 0}, dy[4] = {0, 1, 0, -1}; const long long linf = 4000000000000000000LL; const long long inf = 998244353; const long double pi = 3.1415926535; long long maximum(long long x, long long y) { if (x > y) return x; return y; } long long minimum(long long x, long long y) { if (x < y) return x; return y; } void pv(vector<int> a) { for (auto& x : a) cout << x << ; cout << n ; } void pv(vector<long long> a) { for (auto& x : a) cout << x << ; cout << n ; } void pv(vector<vector<int> > a) { for (int i = (0); i < (a.size()); ++i) { cout << i << n ; pv(a[i]); cout << n ; } } void pv(vector<vector<long long> > a) { for (int i = (0); i < (a.size()); ++i) { cout << i << n ; pv(a[i]); } cout << n ; } void pv(vector<string> a) { for (auto& x : a) cout << x << n ; cout << n ; } int modInverse(int a, int m) { int m0 = m; int y = 0, x = 1; if (m == 1) return 0; while (a > 1) { int q = a / m; int t = m; m = a % m, a = t; t = y; y = x - q * y; x = t; } if (x < 0) x += m0; return x; } long long power(long long x, long long y) { long long k = 1 << 30; long long z = 1; while (k != 0) { z *= z; z %= inf; if (y >= k) { z *= x; z %= inf; y -= k; } k >>= 1; } return z; } long double area(pair<int, int> x, pair<int, int> y, pair<int, int> z) { return ((long long)x.second * y.first + (long long)y.second * z.first + (long long)z.second * x.first - (long long)x.first * y.second - (long long)y.first * z.second - (long long)z.first * x.second) / 2.0; } bool clockwise(pair<int, int> x, pair<int, int> y, pair<int, int> z) { return area(x, y, z) > 0; } struct point { long double x, y; }; long double area(point x, point y, point z) { return (x.y * y.x + y.y * z.x + z.y * x.x - x.x * y.y - y.x * z.y - z.x * x.y) / 2.0; } bool clockwise(point x, point y, point z) { return area(x, y, z) > 0; } int gcd(int a, int b) { if (a > b) swap(a, b); if (a == 0) return b; return gcd(a, b % a); } int popcount(int a) { int count = 0; while (a != 0) { count += (a % 2); a >>= 1; } return count; } long long choose(long long n, long long r) { long long p = 1, k = 1; if (n - r < r) r = n - r; if (r != 0) { while (r) { p *= n; k *= r; long long m = gcd(p, k); p /= m; k /= m; n--; r--; } } else p = 1; return p; } vector<long long> prefix_hash(string& a, vector<long long>& powers) { int n = int(a.size()); vector<long long> prefix(n + 1); for (int i = (0); i < (n); ++i) prefix[i + 1] = (prefix[i] + powers[i] * (a[i] - a + 1)) % inf; return prefix; } void setIO(string second) { ios_base::sync_with_stdio(0); cin.tie(0); } int n; vector<vector<int> > adj; vector<int> v; void dfs(int i, int p) { v[i] = 1; for (auto& x : adj[i]) { if (x != p) dfs(x, i); } } int main() { setIO( test3 ); cin >> n; adj.resize(n); for (int i = (0); i < (n); ++i) { int a; cin >> a; adj[--a].push_back(i); adj[i].push_back(a); } int ans = 0; v.resize(n); for (int i = (0); i < (n); ++i) { if (!v[i]) { ans++; dfs(i, -1); } } cout << ans << n ; } |
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW: readmemb function - data file length less than array
//
//
module main ();
reg [7:0] array [0:7];
reg error ;
reg [3:0] count;
initial
begin
error = 0;
/* pre init the array to all zeroes. */
for(count = 0; count <= 7; count = count + 1)
array[count] = 8'h0;
$readmemb("ivltests/readmemb2.dat",array);
for(count = 0; count <= 3; count = count + 1)
begin
if(array[count[2:0]] !== count)
begin
error = 1;
$display("FAILED - array[count] == %h, s/b %h",
array[count],count);
end
end
if(array[4] !== 8'h0)
begin
error = 1;
$display("FAILED - array[4] == %h, s/b 0",
array[count]);
end
if(error == 0)
$display("PASSED\n");
$finish ;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long maxn = 2e5 + 10; const long long inf = 1e18; const long long mod = 1e9 + 7; long long n, q; long long a[maxn]; long long cost(long long g) { long long ans = 0; for (long long i = 1; i <= n; i++) { if (a[i] < g) ans += g - a[i]; else ans += min(a[i] % g, g - a[i] % g); } return ans; } long long ans = inf; void DO(long long x) { if (x <= 1) return; for (long long i = 2; i <= sqrt(x); i++) if (x % i == 0) { ans = min(ans, cost(i)); while (x % i == 0) x /= i; } if (x > 1) ans = min(ans, cost(x)); } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; for (long long i = 1; i <= n; i++) cin >> a[i]; random_shuffle(a + 1, a + n + 1); for (long long i = 1; i <= 10; i++) DO(a[i] - 1), DO(a[i]), DO(a[i] + 1); for (long long i = n / 3; i <= n / 3 + 15; i++) DO(a[i] - 1), DO(a[i]), DO(a[i] + 1); for (long long i = 2 * n / 3; i <= 2 * n / 3 + 15; i++) DO(a[i] - 1), DO(a[i]), DO(a[i] + 1); for (long long i = n; i >= n - 10; i--) DO(a[i] - 1), DO(a[i]), DO(a[i] + 1); cout << ans; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; const int mod = 1e9 + 7; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, m; long long ans = 0; cin >> n >> m; for (int i = 1; i <= n; i++) { ans += ((i % 5) + m) / 5; } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; class Solution { public: long long count(long long _m, long long _x) { if (_m < 3) { return max(0LL, _m); } m = _m; x = _x; vector<pair<long long, int>> cnts = factorize(m); long long res = 0; search(0, 1, cnts, res); return res; } private: map<long long, vector<pair<long long, int>>> fs; long long m, x; long long gcd(long long x, long long y) { while (x != 0) { y %= x; swap(x, y); } return y; } vector<pair<long long, int>>& factorize(long long n) { if (fs.count(n) > 0) { return fs[n]; } vector<pair<long long, int>>& res = fs[n]; for (long long i = 2; i * i <= n; ++i) { int cnt = 0; while (n % i == 0) { ++cnt; n /= i; } if (cnt > 0) { res.emplace_back(i, cnt); } } if (n > 1) { res.emplace_back(n, 1); } return res; } void search(int i, long long dv, vector<pair<long long, int>>& cnts, long long& ans) { if (i >= cnts.size()) { vector<pair<long long, int>> dvcnts; dvcnts.reserve(cnts.size()); for (auto& pc : cnts) { if (pc.second <= 1) { continue; } dvcnts.emplace_back(pc.first, pc.second - 1); } long long phi = dv; for (auto& pc : cnts) { long long p = pc.first; int c = pc.second; if (c == 0) { continue; } dvcnts = merge(dvcnts, factorize(p - 1)); phi = phi - phi / p; } ans += phi / calcPeriod(x % dv, dv, dvcnts); return; } long long p = fs[m][i].first; long long n = fs[m][i].second; for (int j = 0; j <= n; ++j) { cnts[i].second = j; search(i + 1, dv, cnts, ans); dv *= p; } } vector<pair<long long, int>> merge(vector<pair<long long, int>>& list1, vector<pair<long long, int>>& list2) { vector<pair<long long, int>> res; res.reserve(list1.size() + list2.size()); int n = list1.size(), m = list2.size(); int i = 0, j = 0; while (i < n && j < m) { if (list1[i].first < list2[j].first) { res.emplace_back(list1[i].first, list1[i].second); ++i; } else if (list1[i].first > list2[j].first) { res.emplace_back(list2[j].first, list2[j].second); ++j; } else { res.emplace_back(list1[i].first, list1[i].second + list2[j].second); ++i; ++j; } } while (i < n) { res.emplace_back(list1[i].first, list1[i].second); ++i; } while (j < m) { res.emplace_back(list2[j].first, list2[j].second); ++j; } return res; } long long calcPeriod(long long x, long long mod, vector<pair<long long, int>>& factors) { long long phi = 1; for (auto& pc : factors) { long long p = pc.first; int c = pc.second; for (int i = 0; i < c; ++i) { phi *= p; } } long long res = 1; for (auto& pc : factors) { long long p = pc.first; int c = pc.second; long long base = phi; for (int i = 0; i < c; ++i) { base /= p; } long long val = powM(x, base, mod); int j = c; for (int i = 1; i <= c; ++i) { if (val == 1) { j = i - 1; break; } val = powM(val, p, mod); } res *= powI(p, j); } return res; } long long mulM(long long a, long long b, long long m) { long long res = 0; while (b > 0) { if (b & 0x1) { res = (res + a) % m; } a = (a + a) % m; b >>= 1; } return res; } long long powM(long long x, long long e, long long m) { long long res = 1; while (e > 0) { if (e & 0x1) { res = mulM(res, x, m); } x = mulM(x, x, m); e >>= 1; } return res; } long long powI(long long x, long long e) { long long res = 1; for (int i = 0; i < e; ++i) { res *= x; } return res; } }; int main(int argc, char** argv) { ios::sync_with_stdio(false); cin.tie(0); long long m, x; cin >> m >> x; Solution sol; cout << sol.count(m, x) << endl; return 0; } |
#include <bits/stdc++.h> #include <unordered_map> #include <unordered_set> using namespace std; #define endl n #define ll long long #define sz(s) (int)(s.size()) #define INF 0x3f3f3f3f3f3f3f3fLL #define all(v) v.begin(),v.end() #define watch(x) cout<<(#x)<< = <<x<<endl const int dr[] { -1, -1, 0, 1, 1, 1, 0, -1 }; const int dc[] { 0, 1, 1, 1, 0, -1, -1, -1 }; #if __cplusplus >= 201402L template<typename T> vector<T> create(size_t n) { return vector<T>(n); } template<typename T, typename ... Args> auto create(size_t n, Args ... args) { return vector<decltype(create<T>(args...))>(n, create<T>(args...)); } #endif void run() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); #ifndef ONLINE_JUDGE freopen( input.in , r , stdin); #else //freopen( groups.in , r , stdin); #endif } const int N = 1e5 + 9; int l[N], r[N]; ll dp[N][2]; vector<vector<int>> adj; ll dfs(int node, int par, bool b) { ll &rt = dp[node][b]; if (~rt) return rt; rt = 0; int myVal = (b ? r[node] : l[node]); for (int ch : adj[node]) if (ch != par) rt += max(dfs(ch, node, 0) + abs(l[ch] - myVal), dfs(ch, node, 1) + abs(r[ch] - myVal)); return rt; } int main() { run(); int T; cin >> T; while (T--) { int n; cin >> n; memset(dp, -1, (sizeof dp[0]) * (n + 1)); for (int i = 1; i <= n; i++) cin >> l[i] >> r[i]; adj = vector<vector<int>>(n + 1); for (int i = 1; i < n; i++) { int u, v; cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); } cout << max(dfs(1, -1, 0), dfs(1, -1, 1)) << endl; } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR2_BEHAVIORAL_V
`define SKY130_FD_SC_LS__NOR2_BEHAVIORAL_V
/**
* nor2: 2-input NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__nor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR2_BEHAVIORAL_V |
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 3369 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w32,
w33,
w4096,
w4129,
w264,
w4393,
w1024,
w3369;
assign w1 = i_data0;
assign w1024 = w1 << 10;
assign w264 = w33 << 3;
assign w32 = w1 << 5;
assign w33 = w1 + w32;
assign w3369 = w4393 - w1024;
assign w4096 = w1 << 12;
assign w4129 = w33 + w4096;
assign w4393 = w4129 + w264;
assign o_data0 = w3369;
//multiplier_block area estimate = 6832.425686575;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve(); int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); solve(); return 0; } const int inf = 2e9; const long long linf = 2e18; const long long mod = 998244353; const int N = 2e5 + 100; vector<int> g[N]; struct Elem { int value, node, pos; }; Elem merge(Elem a, Elem b) { if (a.value < b.value) return b; else return a; } struct T { vector<Elem> t; vector<int> u; T(const vector<Elem> &a) { t.assign(4 * a.size(), {0, 0}); u.assign(4 * a.size(), 0); build(a, 0, 0, a.size()); } void build(const vector<Elem> &a, int v, int l, int r) { if (r - l == 1) { t[v] = a[l]; return; } build(a, v * 2 + 1, l, (l + r) >> 1); build(a, v * 2 + 2, (l + r) >> 1, r); t[v] = merge(t[v * 2 + 1], t[v * 2 + 2]); } void push(int v, int l, int r) { if (r - l == 1) { t[v].value += u[v]; u[v] = 0; return; } t[v].value += u[v]; u[v * 2 + 1] += u[v]; u[v * 2 + 2] += u[v]; u[v] = 0; } Elem get(int v, int l, int r, int vl, int vr) { push(v, l, r); if (vl >= r || vr <= l) return {-inf, -1}; if (vl <= l && r <= vr) return t[v]; if (r - l == 1) { return t[v]; } return merge(get(v * 2 + 1, l, (l + r) >> 1, vl, vr), get((v * 2 + 2), (l + r) >> 1, r, vl, vr)); } void upd(int v, int l, int r, int vl, int vr, int d) { push(v, l, r); if (vl >= r || vr <= l) return; if (vl <= l && r <= vr) { u[v] += d; push(v, l, r); return; } int m = (l + r) >> 1; upd(v * 2 + 1, l, m, vl, vr, d); upd(v * 2 + 2, m, r, vl, vr, d); t[v] = merge(t[v * 2 + 1], t[v * 2 + 2]); } }; vector<Elem> leaves; pair<int, int> segments[N]; int par[N]; pair<int, int> dfs(int v, int depth = 1) { if (g[v].size() == 1 && par[v] != -1) { int pos = leaves.size(); leaves.push_back({depth, v, pos}); return {leaves.size() - 1, leaves.size() - 1}; } for (auto u : g[v]) { if (par[v] == u) continue; par[u] = v; auto [l, r] = dfs(u, depth + 1); segments[v].first = min(segments[v].first, l); segments[v].second = max(segments[v].second, r); } return segments[v]; } int marked[N]; void solve() { int n, k; cin >> n >> k; fill(par, par + n, -1); for (int i = 0; i < n; i++) segments[i] = {inf, -inf}; for (int i = 0; i < n - 1; i++) { int t1, t2; cin >> t1 >> t2; t1--; t2--; g[t1].push_back(t2); g[t2].push_back(t1); } dfs(0); T t(leaves); int unmarked = n; long long best = -1ll * (n / 2) * (n - n / 2); for (int i = 1; i <= k; i++) { if (i > leaves.size()) { long long rmax = max((long long)leaves.size(), (long long)min(i, n / 2)); best = max(best, rmax * (n - rmax)); continue; } Elem e = t.get(0, 0, leaves.size(), 0, leaves.size()); t.upd(0, 0, leaves.size(), e.pos, e.pos + 1, -inf); int v = e.node; marked[v] = true; unmarked--; v = par[v]; while (!marked[v]) { marked[v] = true; unmarked--; t.upd(0, 0, leaves.size(), segments[v].first, segments[v].second + 1, -1); if (par[v] == -1) break; v = par[v]; } long long bmax = min(n / 2, unmarked); best = max(best, 1ll * i * (n - i) - bmax * (n - bmax)); } cout << best << n ; } |
#include <bits/stdc++.h> using namespace std; int n, a[200011], c[200011], isc[200011], cn, pow2[200011] = {1}, seen[200011]; int main() { int ans = 1, mod = 1e9 + 7; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , a + i); pow2[i] = pow2[i - 1] * 2LL % mod; } for (int i = 1; i <= n; i++) { if (seen[i] < 0) continue; ++cn; int j; for (j = i; seen[j] >= 0; j = a[j]) seen[j] = -cn, ++c[cn]; if (seen[j] == -cn) isc[cn] = 1; if (isc[cn]) { int clen = 1; for (int k = a[j]; seen[k] == -cn && k != j; k = a[k]) ++clen; ans = (ans * 1LL * (pow2[clen] - 2 + mod) % mod) % mod; ans = (ans * 1LL * pow2[c[cn] - clen]) % mod; } else { ans = (ans * 1LL * pow2[c[cn]]) % mod; } } printf( %d n , ans); return 0; } |
// File: ./ex-target/WordContextProduct.v
// Generated by MyHDL 1.0dev
// Date: Mon Oct 5 14:11:53 2015
`timescale 1ns/10ps
module WordContextProduct (
y,
y_dword_vec,
y_dcontext_vec,
word_embv,
context_embv
);
// Word-context embeddings product and derivative model.
//
// :param y: return relu(dot(word_emb, context_emb)) as fixbv
// :param y_dword_vec: return d/dword relu(dot(word_emb, context_emb)) as vector of fixbv
// :param y_dcontext_vec: return d/dcontext relu(dot(word_emb, context_emb)) as vector of fixbv
// :param word_embv: word embedding vector of fixbv
// :param context_embv: context embedding vector of fixbv
// :param embedding_dim: embedding dimensionality
// :param leaky_val: factor for leaky ReLU, 0.0 without
// :param fix_min: fixbv min value
// :param fix_max: fixbv max value
// :param fix_res: fixbv resolution
output signed [15:0] y;
reg signed [15:0] y;
output [47:0] y_dword_vec;
reg [47:0] y_dword_vec;
output [47:0] y_dcontext_vec;
reg [47:0] y_dcontext_vec;
output [47:0] word_embv;
wire [47:0] word_embv;
output [47:0] context_embv;
wire [47:0] context_embv;
wire [47:0] y_dot_dword_vec;
reg signed [15:0] y_dot;
reg signed [15:0] y_relu_dx;
wire [47:0] y_dot_dcontext_vec;
wire signed [15:0] y_dot_dword_list [0:3-1];
wire signed [15:0] y_dot_dcontext_list [0:3-1];
wire signed [15:0] dot_a_list [0:3-1];
wire signed [15:0] dot_b_list [0:3-1];
assign context_embv[48-1:32] = None;
assign context_embv[32-1:16] = None;
assign context_embv[16-1:0] = None;
assign word_embv[48-1:32] = None;
assign word_embv[32-1:16] = None;
assign word_embv[16-1:0] = None;
always @(dot_a_list[0], dot_a_list[1], dot_a_list[2], dot_b_list[0], dot_b_list[1], dot_b_list[2]) begin: WORDCONTEXTPRODUCT_DOT_DOT
reg signed [32-1:0] y_sum;
integer j;
y_sum = fixbv(0.0);
for (j=0; j<3; j=j+1) begin
y_sum = (y_sum + (dot_a_list[j] * dot_b_list[j]));
end
y_dot = fixbv(y_sum);
end
assign y_dot_dword_vec = context_embv;
assign y_dot_dcontext_vec = word_embv;
always @(y_dot) begin: WORDCONTEXTPRODUCT_RELU_RELU
reg signed [16-1:0] zero;
reg signed [16-1:0] leaky;
if ((y_dot > zero)) begin
y = y_dot;
end
else begin
y = fixbv((leaky * y_dot));
end
end
always @(y_dot) begin: WORDCONTEXTPRODUCT_RELU_RELU_DX
reg signed [16-1:0] zero;
reg signed [16-1:0] leaky;
reg signed [16-1:0] one;
if ((y_dot > zero)) begin
y_relu_dx = one;
end
else begin
y_relu_dx = leaky;
end
end
always @(y_relu_dx, y_dot_dword_list[0], y_dot_dword_list[1], y_dot_dword_list[2]) begin: WORDCONTEXTPRODUCT_WCPROD_DWORD
integer j;
reg signed [16-1:0] prod;
for (j=0; j<3; j=j+1) begin
prod = fixbv((y_relu_dx * y_dot_dword_list[j]));
y_dword_vec[((j + 1) * 16)-1:(j * 16)] = prod;
end
end
always @(y_relu_dx, y_dot_dcontext_list[0], y_dot_dcontext_list[1], y_dot_dcontext_list[2]) begin: WORDCONTEXTPRODUCT_WCPROD_DCONTEXT
integer j;
reg signed [16-1:0] prod;
for (j=0; j<3; j=j+1) begin
prod = fixbv((y_relu_dx * y_dot_dcontext_list[j]));
y_dcontext_vec[((j + 1) * 16)-1:(j * 16)] = prod;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 7; int n, lim, a[N], mn[N], mx[N], suf[N]; long long ans; int main() { scanf( %d%d , &n, &lim); for (int i = 1; i <= lim; i++) mn[i] = n + 1; for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); mn[a[i]] = min(mn[a[i]], i); mx[a[i]] = max(mx[a[i]], i); } int L = lim, R = 1, pre = mx[1]; for (int i = 1; i < lim; i++) { pre = max(pre, mx[i]); if (pre > mn[i + 1]) { L = i; break; } } if (L == lim) { cout << 1ll * lim * (lim + 1) / 2; return 0; } pre = mn[lim]; for (int i = lim; i > 1; i--) { pre = min(pre, mn[i]); if (mx[i - 1] > pre) { R = i; break; } } ans = lim - R + 2; suf[lim] = mn[lim]; for (int i = lim - 1; i >= R; i--) suf[i] = min(suf[i + 1], mn[i]); pre = mx[1]; for (int i = 1, j = R; i <= L; i++) { pre = max(pre, mx[i]); while (j <= lim && pre > suf[j]) j++; ans += lim - j + 2; if (j == i + 1) ans--; } cout << ans; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////
//
// This file is part of Descrypt Ztex Bruteforcer
// Copyright (C) 2014 Alexey Osipov <giftsungiv3n at gmail dot com>
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
////////////////////////////////////////////////////////////////////////
module IP(
input [63:0] Din,
output [63:0] Dout
);
assign Dout = {Din[6], Din[14], Din[22], Din[30], Din[38], Din[46], Din[54], Din[62], Din[4], Din[12], Din[20], Din[28], Din[36], Din[44], Din[52], Din[60], Din[2], Din[10], Din[18], Din[26], Din[34], Din[42], Din[50], Din[58], Din[0], Din[8], Din[16], Din[24], Din[32], Din[40], Din[48], Din[56], Din[7], Din[15], Din[23], Din[31], Din[39], Din[47], Din[55], Din[63], Din[5], Din[13], Din[21], Din[29], Din[37], Din[45], Din[53], Din[61], Din[3], Din[11], Din[19], Din[27], Din[35], Din[43], Din[51], Din[59], Din[1], Din[9], Din[17], Din[25], Din[33], Din[41], Din[49], Din[57]};
endmodule
module IP_1(
input [63:0] Din,
output [63:0] Dout
);
assign Dout = {Din[24], Din[56], Din[16], Din[48], Din[8], Din[40], Din[0], Din[32], Din[25], Din[57], Din[17], Din[49], Din[9], Din[41], Din[1], Din[33], Din[26], Din[58], Din[18], Din[50], Din[10], Din[42], Din[2], Din[34], Din[27], Din[59], Din[19], Din[51], Din[11], Din[43], Din[3], Din[35], Din[28], Din[60], Din[20], Din[52], Din[12], Din[44], Din[4], Din[36], Din[29], Din[61], Din[21], Din[53], Din[13], Din[45], Din[5], Din[37], Din[30], Din[62], Din[22], Din[54], Din[14], Din[46], Din[6], Din[38], Din[31], Din[63], Din[23], Din[55], Din[15], Din[47], Din[7], Din[39]};
endmodule
|
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