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#include <bits/stdc++.h> long long int dx[] = {-2, -2, -1, 1, 2, 2, 1, -1}; long long int dy[] = {-1, 1, 2, 2, 1, -1, -2, -2}; using namespace std; bool comp(long long int x, long long int y) { return abs(x) > abs(y); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int te = 1; cin >> te; while (te--) { long long int n; cin >> n; long long int arr[n]; long long int mxi = -INT_MAX; for (long long int i = 0; i < n; i++) cin >> arr[i], mxi = max(mxi, arr[i]); sort(arr, arr + n, comp); if (mxi < 0) { cout << arr[n - 1] * arr[n - 2] * arr[n - 3] * arr[n - 4] * arr[n - 5] << n ; continue; } long long int ans = arr[0] * arr[1] * arr[2] * arr[3] * arr[4]; if (ans < 0) { for (long long int i = 5; i < n; i++) { for (long long int j = 0; j < 5; j++) { long long int tmp = arr[i]; for (long long int k = 0; k < 5; k++) { if (k != j) tmp *= arr[k]; } ans = max(ans, tmp); } } } cout << ans << endl; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O22A_TB_V
`define SKY130_FD_SC_HS__O22A_TB_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o22a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 A1 = 1'b1;
#160 A2 = 1'b1;
#180 B1 = 1'b1;
#200 B2 = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 A1 = 1'b0;
#280 A2 = 1'b0;
#300 B1 = 1'b0;
#320 B2 = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 B2 = 1'b1;
#440 B1 = 1'b1;
#460 A2 = 1'b1;
#480 A1 = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 B2 = 1'bx;
#560 B1 = 1'bx;
#580 A2 = 1'bx;
#600 A1 = 1'bx;
end
sky130_fd_sc_hs__o22a dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O22A_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A311OI_2_V
`define SKY130_FD_SC_MS__A311OI_2_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog wrapper for a311oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a311oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a311oi_2 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a311oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a311oi_2 (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a311oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A311OI_2_V
|
// Constructs a frame given the data to transmit. Saves writing this
// assignment in three separate places.
//
function [10:0] framed;
input [7:0] data;
// One START bit, LOW. 8 data bits and two STOP bits, HIGH. LSB on RHS
framed = {2'b11, data, 1'b0};
endfunction
module UART (
clk,
reset, // To reset, this should be HIGH when clk RISES
tx_line, // The external line between devices driven by this UART
tx_data, // The data to be transmitted
tx_request, // RISING edge while tx_state is IDLE causes transmission to be initiated
);
input clk;
input reset;
output tx_line;
input [7:0] tx_data;
input tx_request;
parameter TX_STATE_IDLE = 0;
parameter TX_STATE_TRANSMITTING = 1;
parameter CLK_RATE = 12*1000*1000;
parameter BAUD_RATE = 9600;
// For baud rates lower than 9600, check that `tx_countdown` has enough bits
// to store CLK_DIV.
// When `clk` is 12 MHz, dividing by 1250 yields exactly 9600 bps
parameter CLK_DIV = CLK_RATE / BAUD_RATE;
// The frame currently being transmitted. If this is changed during a
// transmission then it will screw up the transmission but that's OK because
// the driver should *not* do that.
reg [10:0] frame = framed (8'h00);
// The bit position in `frame` that is being driven on tx_line right now
reg [3:0] frame_bit_id = 0;
reg tx_state = TX_STATE_IDLE;
reg [11:0] tx_countdown = CLK_DIV;
assign tx_line = frame [frame_bit_id];
always @ (posedge clk) begin
if (reset) begin
frame = framed (8'h00);
frame_bit_id = 0;
tx_state = TX_STATE_IDLE;
end
case (tx_state)
// If the transmitter is not currently transmitting a frame..
TX_STATE_IDLE: begin
// If a request to send a frame has been received..
// FIXME: This is a bit poo. The frame will be sent multiple times if
// `tx_request` is not driven low before the frame is sent
if (tx_request) begin
frame = framed (tx_data);
frame_bit_id = 0;
tx_countdown = CLK_DIV;
tx_state = TX_STATE_TRANSMITTING;
end
end
TX_STATE_TRANSMITTING: begin
tx_countdown = tx_countdown - 1;
// `tx_line` has been driven for a whole bit period when `tx_countdown`
// reaches zero. `frame_bit_id` therefore indicates the bit position
// within frame that has *been* transmitted.
if (tx_countdown == 0) begin
if (frame_bit_id != 10) begin
frame_bit_id = frame_bit_id + 1;
tx_countdown = CLK_DIV;
end else begin
tx_state = TX_STATE_IDLE;
end
end
end // TX_STATE_TRANSMITTING
endcase // tx_state
end // posedge clk
endmodule
|
#include <bits/stdc++.h> using namespace std; string s; char ok[100] = { A , H , I , M , O , T , U , V , W , X , Y }; int main() { while (cin >> s) { if (s.length() == 1) { int flag = 0; for (int i = 0; i <= 10; i++) { if (s[0] == ok[i]) { puts( YES ); flag = 1; break; } } if (!flag) puts( NO ); continue; } else { int flag = 1, half = s.length() / 2, flag1 = 0; int len = s.length(); for (int i = 0; i < half; i++) { if (s[i] != s[len - 1 - i]) { flag = 0; break; } else { int x = 0; for (int j = 0; j <= 10; j++) { x += s[i] == ok[j]; } if (x == 0) { flag = 0; break; } } } if (len % 2 == 1) { for (int i = 0; i <= 10; i++) { if (s[half] == ok[i]) { flag1 = 1; break; } } } else flag1 = 1; printf( %s n , flag == 1 && flag1 == 1 ? YES : NO ); } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EINVP_BLACKBOX_V
`define SKY130_FD_SC_MS__EINVP_BLACKBOX_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__einvp (
Z ,
A ,
TE
);
output Z ;
input A ;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__EINVP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int N, M, K, P[105]; int main() { scanf( %d %d %d , &N, &M, &K); for (int i = 0; i < K; i++) scanf( %d , &P[i]); int ans = 0; for (int i = 0; i < N; i++) { for (int j = 0; j < M; j++) { int x; scanf( %d , &x); int idx; for (int k = 0; k < K; k++) if (x == P[k]) { idx = k; break; } for (int k = idx; k > 0; k--) P[k] = P[k - 1]; P[0] = x; ans += idx + 1; } } printf( %d n , ans); return 0; } |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file obc_lower.v when simulating
// the core, obc_lower. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module obc_lower(
clka,
wea,
addra,
dina,
douta
);
input clka;
input [0 : 0] wea;
input [9 : 0] addra;
input [7 : 0] dina;
output [7 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(10),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(0),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(1024),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(1024),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2014 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
wire [4:0] in = crc[4:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out),
// Inputs
.clk (clk),
.in (in[4:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {63'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h7a7bd4ee927e7cc3
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in
);
//bug718
input clk;
input logic [4:0] in;
output logic out;
always @(posedge clk) begin
out <= in inside {5'b1_1?1?};
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, ans = 0; cin >> n >> m; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { int a, b; cin >> a >> b; ; if (a == 1 || b == 1) ans++; } cout << ans; return 0; } |
#include <bits/stdc++.h> #define ll long long int #define ii pair<int,int> #define int long long int using namespace std; const int inf = 0x3f3f3f3f; int32_t main() { int t; scanf( %lld ,&t); while(t--) { int n, m, x; scanf( %lld%lld%lld ,&n,&m,&x); --x; int c = (x/n); int r = (x%n); int ans = r*m+c; printf( %lld n ,ans+1); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, m, b, mn1 = 1000000, mn2 = 0, temp; cin >> n >> m >> b; for (int i = 0; i < n; i++) { int x; cin >> x; mn1 = min(mn1, x); } for (int i = 0; i < m; i++) { int x; cin >> x; mn2 = max(mn2, x); } if (mn1 < mn2) { temp = b / mn1; b -= mn1 * temp; b += temp * mn2; } cout << b << n ; } |
#include <bits/stdc++.h> using namespace std; int main() { int t_; cin >> t_; while (t_--) { int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; i++) { cin >> a[i]; } int turns = 0; int alice = 0; int bob = n - 1; int alice_candies = 0; int bob_candies = 0; int alice_candies_previous = 0; int bob_candies_previous = 0; while (alice <= bob) { turns++; alice_candies_previous = 0; while (alice <= bob && alice_candies_previous <= bob_candies_previous) { alice_candies += a[alice]; alice_candies_previous += a[alice]; alice++; } if (alice <= bob) { turns++; bob_candies_previous = 0; while (alice <= bob && bob_candies_previous <= alice_candies_previous) { bob_candies += a[bob]; bob_candies_previous += a[bob]; bob--; } } } cout << turns << << alice_candies << << bob_candies << endl; } return 0; } |
// file: dcm.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
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// (individually and collectively, "Critical
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// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____80.000______0.000______50.0______450.000____150.000
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "dcm,clk_wiz_v3_6,{component_name=dcm,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module dcm
(// Clock in ports
input CLK_IN,
// Clock out ports
output CLK_OUT
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN));
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire psdone_unused;
wire locked_int;
wire [7:0] status_int;
wire clkfb;
wire clk0;
wire clkfx;
DCM_SP
#(.CLKDV_DIVIDE (2.000),
.CLKFX_DIVIDE (5),
.CLKFX_MULTIPLY (4),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (10.0),
.CLKOUT_PHASE_SHIFT ("NONE"),
.CLK_FEEDBACK ("1X"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE"))
dcm_sp_inst
// Input clock
(.CLKIN (clkin1),
.CLKFB (clkfb),
// Output clocks
.CLK0 (clk0),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (clkfx),
.CLKFX180 (),
.CLKDV (),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (locked_int),
.STATUS (status_int),
.RST (1'b0),
// Unused pin- tie low
.DSSEN (1'b0));
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfb),
.I (clk0));
BUFG clkout1_buf
(.O (CLK_OUT),
.I (clkfx));
endmodule
|
//****************************************************************************/
// Arty CM0 "DesignStart"
// RTL IMPLEMENTATION, Synchronous Version
//
// Copyright (C) yyyy Ronan Barzic -
// Date : Tue Nov 17 16:37:55 2015
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,MA 02110-1301,USA.
//
//
// Filename : arty_mmcm_sim.v
//
// Description : A behavioural model from the MMCM (Xilinx) clock component
//
//
//
//****************************************************************************/
module arty_mmcm (/*AUTOARG*/
// Outputs
clk_50m, locked,
// Inputs
clk_in, resetn
);
input clk_in;
output clk_50m;
input resetn;
output locked;
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg clk_50m;
reg locked;
// End of automatics
/*AUTOWIRE*/
always @(posedge clk_in or negedge resetn) begin
if(resetn == 1'b0) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
clk_50m <= 1'h0;
// End of automatics
end
else begin
clk_50m <= !clk_50m;
end
end
always @(posedge clk_50m or negedge resetn) begin
if(resetn == 1'b0) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
locked = 1'h0;
// End of automatics
end
else begin
locked <= 1'b1;
end
end
endmodule // arty_mmcm_sim
/*
Local Variables:
verilog-library-directories:(
"."
)
End:
*/
|
#include <bits/stdc++.h> using namespace std; long long n, m, a[1000005], ans = 0; inline long long read() { long long red = 0, f_f = 1; char ch = getchar(); while (ch > 9 || ch < 0 ) { if (ch == - ) f_f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) red = red * 10 + ch - 0 , ch = getchar(); return red * f_f; } signed main() { n = (1ll << read()), m = read(); for (long long i = 0; i < n; i++) a[i] = read(), ans += a[i]; printf( %.6lf n , 1.0 * ans / n); while (m--) { long long x = read(), y = read(); ans -= a[x]; a[x] = y; ans += a[x]; printf( %.6lf n , 1.0 * ans / n); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O211A_SYMBOL_V
`define SKY130_FD_SC_HD__O211A_SYMBOL_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o211a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O211A_SYMBOL_V
|
//altiobuf_out CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" DEVICE_FAMILY="Cyclone V" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" PSEUDO_DIFFERENTIAL_MODE="TRUE" USE_DIFFERENTIAL_MODE="TRUE" USE_OE="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN1="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN2="FALSE" USE_TERMINATION_CONTROL="FALSE" datain dataout dataout_b
//VERSION_BEGIN 14.1 cbx_altiobuf_out 2015:01:07:18:05:53:SJ cbx_mgl 2015:01:07:18:10:28:SJ cbx_stratixiii 2015:01:07:18:05:54:SJ cbx_stratixv 2015:01:07:18:05:54:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus II License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = cyclonev_io_obuf 2 cyclonev_pseudo_diff_out 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module hps_sdram_p0_clock_pair_generator
(
datain,
dataout,
dataout_b) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obuf_ba_oe;
wire [0:0] wire_obufa_o;
wire [0:0] wire_obufa_oe;
wire [0:0] wire_pseudo_diffa_o;
wire [0:0] wire_pseudo_diffa_obar;
wire [0:0] wire_pseudo_diffa_oebout;
wire [0:0] wire_pseudo_diffa_oein;
wire [0:0] wire_pseudo_diffa_oeout;
wire [0:0] oe_w;
cyclonev_io_obuf obuf_ba_0
(
.i(wire_pseudo_diffa_obar),
.o(wire_obuf_ba_o[0:0]),
.obar(),
.oe(wire_obuf_ba_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obuf_ba_0.bus_hold = "false",
obuf_ba_0.open_drain_output = "false",
obuf_ba_0.lpm_type = "cyclonev_io_obuf";
assign
wire_obuf_ba_oe = {(~ wire_pseudo_diffa_oebout[0])};
cyclonev_io_obuf obufa_0
(
.i(wire_pseudo_diffa_o),
.o(wire_obufa_o[0:0]),
.obar(),
.oe(wire_obufa_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_0.bus_hold = "false",
obufa_0.open_drain_output = "false",
obufa_0.lpm_type = "cyclonev_io_obuf";
assign
wire_obufa_oe = {(~ wire_pseudo_diffa_oeout[0])};
cyclonev_pseudo_diff_out pseudo_diffa_0
(
.dtc(),
.dtcbar(),
.i(datain),
.o(wire_pseudo_diffa_o[0:0]),
.obar(wire_pseudo_diffa_obar[0:0]),
.oebout(wire_pseudo_diffa_oebout[0:0]),
.oein(wire_pseudo_diffa_oein[0:0]),
.oeout(wire_pseudo_diffa_oeout[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dtcin(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
assign
wire_pseudo_diffa_oein = {(~ oe_w[0])};
assign
dataout = wire_obufa_o,
dataout_b = wire_obuf_ba_o,
oe_w = 1'b1;
endmodule //hps_sdram_p0_clock_pair_generator
//VALID FILE
|
#include <bits/stdc++.h> using namespace std; template <typename _T> inline void read(_T &f) { f = 0; _T fu = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) { fu = -1; } c = getchar(); } while (c >= 0 && c <= 9 ) { f = (f << 3) + (f << 1) + (c & 15); c = getchar(); } f *= fu; } template <typename T> void print(T x) { if (x < 0) putchar( - ), x = -x; if (x < 10) putchar(x + 48); else print(x / 10), putchar(x % 10 + 48); } template <typename T> void print(T x, char t) { print(x); putchar(t); } const int md = 998244353; inline int add(int x, int y) { x += y; if (x >= md) x -= md; return x; } inline int sub(int x, int y) { x -= y; if (x < 0) x += md; return x; } inline int mul(int x, int y) { return 1ll * x * y % md; } inline int fpow(int x, int y) { int ans = 1; while (y) { if (y & 1) ans = mul(ans, x); y >>= 1; x = mul(x, x); } return ans; } namespace Poly { vector<int> rev, roots, one(1, 1); vector<int> operator+(vector<int> a, vector<int> b) { int n = max((int)a.size(), (int)b.size()); a.resize(n); b.resize(n); for (int i = 0; i < n; i++) { a[i] = add(a[i], b[i]); } return a; } vector<int> operator-(vector<int> a, vector<int> b) { int n = max((int)a.size(), (int)b.size()); a.resize(n); b.resize(n); for (int i = 0; i < n; i++) { a[i] = sub(a[i], b[i]); } return a; } void getRevRoot(int base) { int n = 1 << base; rev.resize(n); roots.resize(n); for (int i = 1; i < n; i++) rev[i] = (rev[i >> 1] >> 1) | ((i & 1) << (base - 1)); for (int mid = 1; mid < n; mid <<= 1) { int wn = fpow(3, (md - 1) / (mid << 1)); roots[mid] = 1; for (int i = 1; i < mid; i++) roots[mid + i] = mul(roots[mid + i - 1], wn); } } void ntt(vector<int> &a, int base) { int n = 1 << base; for (int i = 0; i < n; i++) if (i < rev[i]) swap(a[i], a[rev[i]]); for (int mid = 1; mid < n; mid <<= 1) { for (int i = 0; i < n; i += (mid << 1)) { for (int j = 0; j < mid; j++) { int x = a[i + j], y = mul(a[i + j + mid], roots[mid + j]); a[i + j] = add(x, y); a[i + j + mid] = sub(x, y); } } } } vector<int> operator*(vector<int> a, vector<int> b) { int base = 0, n = (int)a.size() + (int)b.size() - 1; while ((1 << base) < n) ++base; a.resize(1 << base); b.resize(1 << base); getRevRoot(base); ntt(a, base); ntt(b, base); for (int i = 0; i < (1 << base); i++) a[i] = mul(a[i], b[i]); reverse(a.begin() + 1, a.end()); ntt(a, base); a.resize(n); int inv = fpow(1 << base, md - 2); for (int i = 0; i < n; i++) { a[i] = mul(a[i], inv); } return a; } } // namespace Poly using Poly::operator*; const int N = 1e5 + 5; vector<int> f, g, tmp; int fac[N], inv[N]; int n; long long m; int main() { read(n); read(m); f.resize(n + 1); tmp.resize(n + 1); fac[0] = 1; for (int i = 1; i <= n; i++) fac[i] = mul(fac[i - 1], i); inv[n] = fpow(fac[n], md - 2); for (int i = n; i >= 1; i--) inv[i - 1] = mul(inv[i], i); for (int i = 0; i <= n; i++) read(f[i]), tmp[i] = inv[i]; for (int i = 0; i <= n; i++) f[i] = mul(f[i], fac[i]); reverse(f.begin(), f.end()); g = f * tmp; g.resize(n + 1); reverse(g.begin(), g.end()); for (int i = 0; i <= n; i++) g[i] = mul(mul(g[i], inv[i]), fpow(fpow(i + 1, m % (md - 1)), md - 2)); for (int i = 1; i <= n; i += 2) tmp[i] = md - tmp[i]; for (int i = 0; i <= n; i++) g[i] = mul(g[i], fac[i]); reverse(g.begin(), g.end()); f = g * tmp; f.resize(n + 1); reverse(f.begin(), f.end()); for (int i = 0; i <= n; i++) f[i] = mul(f[i], inv[i]), print(f[i], i == n ? n : ); return 0; } |
#include <bits/stdc++.h> using namespace std; void c_p_c() {} int main(int argc, char const *argv[]) { c_p_c(); ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; int n; string arr; cin >> n >> arr; int cnt = 0; if (n == 1) { cout << cnt << endl; cout << arr << endl; return 0; } for (int i = 1; i < n; i++) { if (arr[i] == arr[i - 1] && arr[i] == arr[i + 1]) { cnt++; if (arr[i] == R ) arr[i] = G ; else if (arr[i] == G ) arr[i] = R ; else { arr[i] = G ; } i++; } else if (arr[i] == arr[i - 1]) { cnt++; if (arr[i] == R && arr[i + 1] == B ) { arr[i] = G ; i++; } else if (arr[i] == R && arr[i + 1] == G ) { arr[i] = B ; i++; } else if (arr[i] == G && arr[i + 1] == R ) { arr[i] = B ; i++; } else if (arr[i] == G && arr[i + 1] == B ) { arr[i] = R ; i++; } else if (arr[i] == B && arr[i + 1] == G ) { arr[i] = R ; i++; } else if (arr[i] == B && arr[i + 1] == R ) { arr[i] = G ; i++; } else { if (arr[i - 1] == R ) arr[i] = G ; else if (arr[i - 1] == G ) arr[i] = R ; else arr[i] = R ; } } } cout << cnt << endl; cout << arr << endl; } |
//======================================================================
//
// blockmem2r1w.v
// --------------
// Synchronous block memory with two read ports and one write port.
// The data size is the same for both read and write operations.
//
// The memory is used in the modexp core.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module blockmem2r1w(
input wire clk,
input wire [07 : 0] read_addr0,
output wire [31 : 0] read_data0,
input wire [07 : 0] read_addr1,
output wire [31 : 0] read_data1,
input wire wr,
input wire [07 : 0] write_addr,
input wire [31 : 0] write_data
);
reg [31 : 0] mem [0 : 255];
reg [31 : 0] tmp_read_data0;
reg [31 : 0] tmp_read_data1;
assign read_data0 = tmp_read_data0;
assign read_data1 = tmp_read_data1;
always @ (posedge clk)
begin : reg_mem
if (wr)
mem[write_addr] <= write_data;
tmp_read_data0 <= mem[read_addr0];
tmp_read_data1 <= mem[read_addr1];
end
endmodule // blockmem2r1w
//======================================================================
// EOF blockmem2r1w.v
//======================================================================
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2111O_TB_V
`define SKY130_FD_SC_MS__A2111O_TB_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a2111o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg D1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
D1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 D1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 C1 = 1'b1;
#280 D1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 C1 = 1'b0;
#460 D1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 D1 = 1'b1;
#660 C1 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 D1 = 1'bx;
#840 C1 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ms__a2111o dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .D1(D1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2111O_TB_V
|
#include <bits/stdc++.h> using namespace std; const int M = (int)1e5 + 5; int n; int a[M]; int q, ans[M]; vector<pair<int, int> > ps[M]; int pas[M], las[M], llas[M], mfr[M]; struct SEGMENT1 { int val[M * 4]; void update(int L, int R, int p, int l, int r, int v) { if (L == l && R == r) { val[p] += v; return; } int mid = (L + R) >> 1; if (mid >= r) update(L, mid, p << 1, l, r, v); else if (mid < l) update(mid + 1, R, p << 1 | 1, l, r, v); else update(L, mid, p << 1, l, mid, v), update(mid + 1, R, p << 1 | 1, mid + 1, r, v); } int query(int L, int R, int p, int x) { if (L == R) return val[p]; int mid = (L + R) >> 1; if (mid >= x) return val[p] + query(L, mid, p << 1, x); else return val[p] + query(mid + 1, R, p << 1 | 1, x); } } T1; struct SEGMENT2 { int val[M * 4]; void update(int L, int R, int p, int x, int v) { val[p] += v; if (L == R) return; int mid = (L + R) >> 1; if (mid >= x) update(L, mid, p << 1, x, v); else update(mid + 1, R, p << 1 | 1, x, v); } int query(int L, int R, int p, int l, int r) { if (L == l && R == r) return val[p]; int mid = (L + R) >> 1; if (mid >= r) return query(L, mid, p << 1, l, r); else if (mid < l) return query(mid + 1, R, p << 1 | 1, l, r); else return query(L, mid, p << 1, l, mid) + query(mid + 1, R, p << 1 | 1, mid + 1, r); } } T2; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); scanf( %d , &q); for (int i = 1, l, r; i <= q; i++) scanf( %d %d , &l, &r), ps[r].push_back(pair<int, int>(l, i)); for (int i = 1, x, len; i <= n; i++) { x = a[i]; len = i - las[x]; if (len != pas[x] && pas[x] != las[x]) { if (mfr[x] < llas[x]) T1.update(1, n, 1, mfr[x] + 1, llas[x], 1); mfr[x] = llas[x]; } pas[x] = len; if (las[x] != 0) T2.update(1, n, 1, las[x], -1); T2.update(1, n, 1, i, 1); llas[x] = las[x]; las[x] = i; for (int j = 0, up = ps[i].size(), c1, c2, l, id; j < up; j++) { l = ps[i][j].first; id = ps[i][j].second; c1 = T2.query(1, n, 1, l, i); c2 = T1.query(1, n, 1, l); if (c1 != c2) ans[id] = c1; else ans[id] = c1 + 1; } } for (int i = 1; i <= q; i++) printf( %d n , ans[i]); return 0; } |
module test ;
wire a;
reg sel,in0, in1;
reg error;
assign a = sel ? in1 : in0 ;
initial
begin
error = 0;
#1;
sel = 0;
in0 = 0;
in1 = 0;
#1;
if(a !== 0)
begin
$display("FAILED - (1) Mux error sel=0, in0=in0=0 yet out != 0");
$display("sel=%b,in0=%b,in1=%b,out=%b",
sel,in0,in1,a);
error = 1;
end
#1;
in0 = 1;
#1;
if(a !== 1)
begin
$display("FAILED - (2) Mux error sel=0, in0=1,in1=0 yet out != 1");
$display("sel=%b,in0=%b,in1=%b,out=%b",
sel,in0,in1,a);
error = 1;
end
#1;
sel = 1;
#1;
if(a !== 0)
begin
$display("FAILED - (3) Mux error sel=1, in0=1,in1=0 yet out != 0");
$display("sel=%b,in0=%b,in1=%b,out=%b",
sel,in0,in1,a);
error = 1;
end
#1;
in1 = 1;
#1;
if(a !== 1)
begin
$display("FAILED - (5) Mux error sel=1, in0=1,in1=1 yet out != 1");
$display("sel=%b,in0=%b,in1=%b,out=%b",
sel,in0,in1,a);
error = 1;
end
#1;
in0 = 0;
#1;
if(a !== 1)
begin
$display("FAILED - (6) Mux error sel=1, in0=0,in1=1 yet out != 1");
$display("sel=%b,in0=%b,in1=%b,out=%b",
sel,in0,in1,a);
error = 1;
end
#1;
in1 = 0;
sel = 1'bx;
#1;
if(a !== 0)
begin
$display("FAILED - (8) Mux error sel=X, in0=0,in1=0 yet out != 0");
$display("sel=%b,in0=%b,in1=%b,out=%b",
sel,in0,in1,a);
error = 1;
end
#1;
in0 = 1;
in1 = 1;
sel = 1'bx;
#1;
if(a !== 1)
begin
$display("FAILED - (9) Mux error sel=X, in0=1,in1=1 yet out != 1");
$display("sel=%b,in0=%b,in1=%b,out=%b",
sel,in0,in1,a);
error = 1;
end
if(error === 0)
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 17; int n; vector<int> adj[(1 << MAX_N) + 9]; bool used[(1 << MAX_N) + 9]; int cnt[(1 << MAX_N) + 9]; vector<int> vRoot; vector<int> ans; void buildCnt(int x) { used[x] = true; cnt[x] = 1; for (int y : adj[x]) { if (!used[y]) { buildCnt(y); cnt[x] += cnt[y]; } } used[x] = false; } void findRoot(int x, vector<int>& vRoot) { used[x] = true; for (int y : adj[x]) { if (!used[y]) { findRoot(y, vRoot); } } if ((1 << n) - 2 - cnt[x] == (1 << n - 1) - 1) { vRoot.push_back(x); } else { for (int y : adj[x]) { if (!used[y]) { if (cnt[y] == (1 << n - 1) - 1) { vRoot.push_back(x); break; } } } } used[x] = false; } bool checkTree1(int x, int depth) { used[x] = true; bool result = false; if (cnt[x] != (1 << depth) - 1) { result = false; } else if (depth == 1) { result = true; } else { result = true; for (int y : adj[x]) { if (!used[y]) { if (!checkTree1(y, depth - 1)) { result = false; break; } } } } used[x] = false; return result; } int checkTree2(int x, int depth) { used[x] = true; int result = -1; if (cnt[x] != (1 << depth) - 2) { result = -1; } else if (depth == 2) { result = x; } else { vector<pair<int, int>> children; for (int y : adj[x]) { if (!used[y]) { children.push_back(make_pair(cnt[y], y)); } } sort(children.begin(), children.end()); if (children.size() == 2) { int tmp = checkTree2(children[0].second, depth - 1); if (tmp != -1 && checkTree1(children[1].second, depth - 1)) { result = tmp; } else { result = -1; } } else if (children.size() == 3) { if (checkTree1(children[0].second, depth - 2) && checkTree1(children[1].second, depth - 2) && checkTree1(children[2].second, depth - 1)) { result = x; } else { result = -1; } } else { result = -1; } } used[x] = false; return result; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n; for (int i = 1; i <= (1 << n) - 3; i++) { int x; int y; cin >> x >> y; adj[x].push_back(y); adj[y].push_back(x); } buildCnt(1); findRoot(1, vRoot); for (int root : vRoot) { buildCnt(root); int x = checkTree2(root, n); if (x != -1) { ans.push_back(x); } } sort(ans.begin(), ans.end()); cout << ans.size() << n ; for (int x : ans) { cout << x << ; } cout << n ; return 0; } |
#include <bits/stdc++.h> int main(void) { int n, m; char g[1000][1000]; int min_row = 1000, max_row = -1; int min_col = 1000, max_col = -1; scanf( %d %d , &n, &m); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { scanf( %c , &g[i][j]); if (g[i][j] == B ) { min_row = std::min(min_row, i); max_row = std::max(max_row, i); min_col = std::min(min_col, j); max_col = std::max(max_col, j); } } } if (max_row == -1) { puts( 1 ); } else { int missing_from_rect = 0; for (int i = min_row; i <= max_row; i++) { for (int j = min_col; j <= max_col; j++) { missing_from_rect += (g[i][j] == W ); } } const int n_rows = (max_row - min_row + 1); const int n_cols = (max_col - min_col + 1); bool feasible = true; int additional = 0; if (n_rows > n_cols) { const int needed = n_rows - n_cols; if (n_cols + needed > m) { feasible = false; } else { additional = needed * n_rows; } } else if (n_rows < n_cols) { const int needed = n_cols - n_rows; if (n_rows + needed > n) { feasible = false; } else { additional = needed * n_cols; } } if (feasible) { printf( %d n , missing_from_rect + additional); } else { puts( -1 ); } } return 0; } |
`ifndef _SPI_MASTER_V
`define _SPI_MASTER_V
module spi_master #(
parameter CLK_DIVIDE=3 // divide clk by 2^CLK_DIVIDE to get spi_sclk
) (
input clk, // 50 MHz system clk
input reset,
input spi_start,
input [7:0] spi_data,
output spi_fin,
output spi_csn,
output spi_sdo,
output spi_sclk // max 10 MHz clk
);
`define SPI_MASTER_SM_W 2
localparam STATE_IDLE = `SPI_MASTER_SM_W'h0;
localparam STATE_SEND = `SPI_MASTER_SM_W'h1;
localparam STATE_HOLD = `SPI_MASTER_SM_W'h2;
localparam STATE_DONE = `SPI_MASTER_SM_W'h3;
reg [`SPI_MASTER_SM_W-1:0] spi_sm_state;
reg [CLK_DIVIDE-1:0] clk_divider;
reg [7:0] spi_data_shift;
reg [2:0] shift_counter;
assign spi_csn = ((spi_sm_state==STATE_IDLE) && (spi_start==1'b0)) ? 1'b1 : 1'b0;
assign spi_sdo = spi_data_shift[7];
assign spi_sclk = ((spi_sm_state==STATE_SEND) && (clk_divider[CLK_DIVIDE-1]==1'b1)) ? 1'b1 : 1'b0;
assign spi_fin = (spi_sm_state==STATE_DONE) ? 1'b1 : 1'b0;
always @(posedge clk or posedge reset) begin
if (reset) begin
spi_sm_state <= STATE_IDLE;
spi_data_shift <= 'b0;
clk_divider <= 'b0;
shift_counter <= 'b0;
end else begin
case (spi_sm_state)
STATE_IDLE: begin
if (spi_start==1'b1) begin
spi_sm_state <= STATE_SEND;
spi_data_shift <= spi_data;
clk_divider <= 'b0;
shift_counter <= 'b0;
end
end
STATE_SEND: begin
clk_divider <= clk_divider + 1;
if (clk_divider == {CLK_DIVIDE{1'b1}}) begin
shift_counter <= shift_counter + 1;
spi_data_shift <= {spi_data_shift[6:0], 1'b0};
if (shift_counter==3'b111) begin
spi_sm_state <= STATE_HOLD;
end
end
end
STATE_HOLD: begin
clk_divider <= clk_divider + 1;
if (clk_divider == {CLK_DIVIDE{1'b1}}) begin
spi_sm_state <= STATE_DONE;
end
end
STATE_DONE: begin
if (spi_start==1'b0) begin
spi_sm_state <= STATE_IDLE;
end
end
default:
spi_sm_state <= STATE_IDLE;
endcase
end
end
endmodule
`endif
|
#include <bits/stdc++.h> int main() { int t, s, q; scanf( %d %d %d , &t, &s, &q); int j = 0; while (s < t) { s *= q; j++; } printf( %d n , j); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5; vector<int> G[MAXN + 5]; int maxFrom[MAXN + 5], down[MAXN + 5], up[MAXN + 5]; int id[MAXN + 5], sz[MAXN + 5], diam[MAXN + 5]; bool flag[MAXN + 5]; int ID; int n, m, Q; map<int, int> cnt; vector<int> accSum[MAXN + 5]; vector<double> accWeightedSum[MAXN + 5]; vector<int> vals[MAXN + 5]; map<pair<int, int>, double> oldAns; void dfs(int u, int p = -1) { id[u] = ID; sz[ID]++; down[u] = 0; flag[u] = 1; for (int v : G[u]) { if (v == p) continue; dfs(v, u); down[u] = max(down[u], 1 + down[v]); } } void dfs2(int u, int p = -1, int parentWithoutme = 0) { if (~p) up[u] = 1 + parentWithoutme; else up[u] = 0; maxFrom[u] = max(up[u], down[u]); diam[ID] = max(diam[ID], maxFrom[u]); cnt[maxFrom[u]]++; vector<int> paths = {up[u], 0}; for (int v : G[u]) { if (v == p) continue; paths[1] = max(paths[1], 1 + down[v]); if (paths[0] < paths[1]) swap(paths[0], paths[1]); } for (int v : G[u]) { if (v == p) continue; dfs2(v, u, ((paths[0] != (1 + down[v])) ? paths[0] : paths[1])); } } void calc(int u) { cnt.clear(); ID = u; dfs(u); dfs2(u); accSum[ID].resize(cnt.size() + 1); accWeightedSum[ID].resize(cnt.size() + 1); accSum[ID][0] = 0; accWeightedSum[ID][0] = 0; int i = 0; for (auto p : cnt) { vals[ID].push_back(p.first); accSum[ID][i + 1] = accSum[ID][i] + p.second; accWeightedSum[ID][i + 1] = accWeightedSum[ID][i] + p.first * (1. * p.second / sz[ID]); i++; } } int main() { int c, c2; scanf( %d%d%d , &n, &m, &Q); for (c = 0; c < m; c++) { int u, v; scanf( %d%d , &u, &v); u--; v--; G[u].push_back(v); G[v].push_back(u); } for (c = 0; c < n; c++) { if (flag[c]) continue; calc(c); } for (c = 0; c < Q; c++) { int u, v; scanf( %d%d , &u, &v); u--; v--; if (id[u] == id[v]) printf( -1 n ); else { if (id[u] > id[v]) swap(u, v); if (oldAns.count({id[u], id[v]}) > 0) { printf( %.9f n , oldAns[{id[u], id[v]}]); } else { if (sz[id[u]] > sz[id[v]]) swap(u, v); int minDiam = max(diam[id[u]], diam[id[v]]); double ret = 0; int j = 0; for (int x : vals[id[u]]) { int i = lower_bound(vals[id[v]].begin(), vals[id[v]].end(), minDiam - x) - vals[id[v]].begin(); double f = 1. * (accSum[id[u]][j + 1] - accSum[id[u]][j]) / sz[id[u]]; ret += f * (accWeightedSum[id[v]].back() - accWeightedSum[id[v]][i] + (x + 1.0) * (sz[id[v]] - accSum[id[v]][i]) / sz[id[v]]); ret += f * (1. * accSum[id[v]][i] / sz[id[v]]) * minDiam; j++; } if (id[u] > id[v]) swap(u, v); oldAns[{id[u], id[v]}] = ret; printf( %.9f n , ret); } } } return 0; } |
#include <bits/stdc++.h> using namespace std; void solve() { long long int n, m, k, kk, x, y; cin >> n >> m >> k; kk = k; long long int a[m]; for (long long int i = 0; i < m; i++) a[i] = 9999999999; for (long long int i = 0; i < n; i++) { cin >> x >> y; a[x - 1] = min(a[x - 1], y); } for (long long int i = 0; i < m; i++) { if (a[i] >= kk) kk = 0; else kk -= a[i]; if (kk == 0) break; } cout << k - kk; return; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long int t = 1; while (t--) solve(); cerr << n << Time elapsed : << clock() * 1000.0 / CLOCKS_PER_SEC << ms n ; } |
#include <bits/stdc++.h> using namespace std; long long int gcd(long long int a, long long int b) { return b == 0 ? a : gcd(b, a % b); } long long int power(long long int x, long long int n) { long long int result = 1; while (n > 0) { if (n % 2 == 1) result = (result * x) % 1000000007; x = (x * x) % 1000000007; n = n / 2; } return result % 1000000007; } bool isPrime(long long int n) { if (n <= 1) return false; if (n <= 3) return true; if (n % 2 == 0 || n % 3 == 0) return false; for (long long int i = 5; i * i <= n; i = i + 6) if (n % i == 0 || n % (i + 2) == 0) return false; return true; } long long int inv(long long int a, long long int m) { return power(a, m - 2); } long long int lcm(long long int a, long long int b) { return a * b / (gcd(a, b)); } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long int t; cin >> t; while (t--) { long long int index = -1, res = -1; string str; cin >> str; long long int n = str.length(), ans = -1; for (long long int i = 0; i < n; i++) { if (str[i] == R ) { index = max(index, i - res); res = i; } } index = max(index, n - res); cout << index << n ; } } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n; cin >> n; vector<pair<long long, long long> > p; for (long long i = 0; i < n; i++) { double x, y; cin >> x >> y; p.push_back(make_pair(x, y)); } set<pair<double, double> > s; set<double> e; long long c; for (long long i = 0; i < n; i++) { for (long long j = i + 1; j < n; j++) { double x1 = p[i].first; double y1 = p[i].second; double x2 = p[j].first; double y2 = p[j].second; if ((x2 - x1) != 0) { double m = (y2 - y1) / (x2 - x1); double c = y1 - m * (x1); s.insert(make_pair(m, c)); } else { e.insert(x1); } } } set<pair<double, double> >::iterator it; vector<long long> r; long long k = 0; long long w = 0; set<pair<double, double> >::iterator itr; itr = s.begin(); it = s.begin(); it++; while (it != s.end()) { long long u = 0; pair<double, double> gg = *it; pair<double, double> hh = *itr; while (gg.first == hh.first) { u++; it++; itr++; gg = *it; hh = *itr; } if (u != 0) { w = w + ((u + 1) * u) / 2; } it++; itr++; } c = e.size(); long long total = s.size() + c; total = (total * (total - 1)) / 2; w = w + ((c - 1) * c) / 2; cout << (total - w); return 0; } |
module mojo_top(
// 50MHz clock input
input clk,
// Input from reset button (active low)
input rst_n,
// cclk input from AVR, high when AVR is ready
input cclk,
// Outputs to the 8 onboard LEDs
output[7:0]led,
// AVR SPI connections
output spi_miso,
input spi_ss,
input spi_mosi,
input spi_sck,
// AVR ADC channel select
output [3:0] spi_channel,
// Serial connections
input avr_tx, // AVR Tx => FPGA Rx
output avr_rx, // AVR Rx => FPGA Tx
input avr_rx_busy, // AVR Rx buffer full
output R0,
output G0,
output B0,
output R1,
output G1,
output B1,
output A,
output B,
output C,
output D,
output MATCLK,
output MATLAT,
output MATOE
);
wire rst = ~rst_n; // make reset active high
// these signals should be high-z when not used
assign spi_miso = 1'bz;
assign avr_rx = 1'bz;
assign spi_channel = 4'bzzzz;
assign led[6:0] = 7'b0;
wire [7:0] tx_data;
wire new_tx_data;
wire tx_busy;
wire [7:0] rx_data;
wire new_rx_data;
reg [23:0] counter10;
always @ (posedge clk or posedge rst)
begin
if (rst)
begin
counter10 <= 0;
end
else
begin
counter10 <= counter10 + 1;
end
end
assign led[7] = counter10[23];
avr_interface avr_interface (
.clk(clk),
.rst(rst),
.cclk(cclk),
.spi_miso(spi_miso),
.spi_mosi(spi_mosi),
.spi_sck(spi_sck),
.spi_ss(spi_ss),
.spi_channel(spi_channel),
.tx(avr_rx), // FPGA tx goes to AVR rx
.rx(avr_tx),
.channel(4'd15), // invalid channel disables the ADC
.new_sample(),
.sample(),
.sample_channel(),
.tx_data(tx_data),
.new_tx_data(new_tx_data),
.tx_busy(tx_busy),
.tx_block(avr_rx_busy),
.rx_data(rx_data),
.new_rx_data(new_rx_data)
);
message_printer helloWorldPrinter (
.clk(clk),
.rst(rst),
.tx_data(tx_data),
.new_tx_data(new_tx_data),
.tx_busy(tx_busy),
.rx_data(rx_data),
.new_rx_data(new_rx_data)
);
rgbmatrix rgbmatrix (
.clk(clk),
.rst(rst),
.R0(R0),
.G0(G0),
.B0(B0),
.R1(R1),
.G1(G1),
.B1(B1),
.A(A),
.B(B),
.C(C),
.D(D),
.MATCLK(MATCLK),
.MATLAT(MATLAT),
.MATOE(MATOE)
);
endmodule |
#include <bits/stdc++.h> using namespace std; struct masivs { long long in; long long out; long long poz; }; masivs mas[100005]; long long i, j, k, n, m, a, b, c; vector<pair<pair<long long, long long>, long long> > ab; int main() { std::cin.sync_with_stdio(false); std::cin.tie(0); cin >> n >> m; i = 0; while (i < n) { mas[i].poz = i; i++; } i = 0; while (i < m) { cin >> a >> b >> c; a--; b--; mas[a].in += c; mas[b].out += c; k = min(mas[a].in, mas[a].out); mas[a].in -= k; mas[a].out -= k; k = min(mas[b].in, mas[b].out); mas[b].in -= k; mas[b].out -= k; i++; } j = 0; i = 0; while (i < n) { while (mas[i].in) { while (mas[j].out == 0) { j++; } k = min(mas[i].in, mas[j].out); ab.push_back({{i + 1, j + 1}, k}); mas[i].in -= k; mas[j].out -= k; } i++; } cout << ab.size() << n ; for (j = 0; j < ab.size(); j++) { cout << ab[j].first.first << << ab[j].first.second << << ab[j].second << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int n; vector<int> v[1010]; int main() { scanf( %d , &n); for (int i = 0; i < n; ++i) { int aux, aux2; scanf( %d , &aux); for (int j = 0; j < aux; ++j) { scanf( %d , &aux2); v[i].push_back(aux2); } sort(v[i].begin(), v[i].end()); } int r = 0; for (int i = 0; i < n; ++i) { int pnt1 = 0, pnt2 = 0; int pr = (i - 1 + n) % n, ne = (i + 1) % n; for (int j = 0; j < v[i].size() - 1; ++j) { int q1 = 0, q2 = 0; while (pnt1 < v[pr].size() && v[pr][pnt1] < v[i][j]) pnt1++; while (pnt1 < v[pr].size() && v[pr][pnt1] < v[i][j + 1]) pnt1++, q1++; while (pnt2 < v[ne].size() && v[ne][pnt2] < v[i][j]) pnt2++; while (pnt2 < v[ne].size() && v[ne][pnt2] < v[i][j + 1]) pnt2++, q2++; if (q1 != q2) r++; } } printf( %d n , r); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const int N = 1e5 + 1; int n, m; vector<int> adj[N]; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); int rand(int x) { return uniform_int_distribution<int>(0, x - 1)(rng); } int d[N]; bool inq[N]; bool vis3[N]; bool ok = true; void dfs3(int id) { inq[id] = true; vis3[id] = true; for (auto x : adj[id]) { if (!vis3[x]) { dfs3(x); } else if (!inq[x]) ok = false; } inq[id] = false; } bool arin(int x) { for (int i = 1; i <= n; i++) vis3[i] = inq[i] = false; ok = true; dfs3(x); return ok; } bool vis[N]; vector<int> ch[N]; int par[N]; int dx[N], dy[N]; int cs[N]; int up[N]; void dfs(int id) { vis[id] = true; up[id] = id; for (auto x : adj[id]) { if (!vis[x]) { d[x] = d[id] + 1; par[x] = id; ch[id].push_back(x); cs[id] = x; dfs(x); } else { dx[x]--; dx[id]++; if (d[up[id]] > d[x]) up[id] = x; } } for (auto x : ch[id]) { if (d[up[x]] < d[up[id]]) up[id] = up[x]; } } int dfs4(int id) { int duh = dx[id]; for (auto x : ch[id]) duh += dfs4(x); dy[id] = duh; return duh; } bool good[N]; int rt; void dfs2(int id) { if (dy[id] <= 1) good[id] = good[up[id]]; if (id == rt) good[id] = true; for (auto x : ch[id]) { dfs2(x); } } void solve() { cin >> n >> m; for (int i = 1; i <= n; i++) { adj[i].clear(); ch[i].clear(); dx[i] = dy[i] = 0; good[i] = false; } for (int i = 1; i <= m; i++) { int u, v; cin >> u >> v; adj[u].push_back(v); } int x = 0; for (int i = 1; i <= 100; i++) { x = rand(n) + 1; if (arin(x)) break; x = 0; } if (x == 0) { cout << -1 n ; return; } for (int i = 1; i <= n; i++) vis[i] = false; d[x] = 0; dfs(x); rt = x; dfs4(x); dfs2(x); int cnt = 0; for (int i = 1; i <= n; i++) if (good[i]) cnt++; if (cnt * 5 < n) { cout << -1 n ; return; } for (int i = 1; i <= n; i++) if (good[i]) cout << i << ; cout << n ; } int main() { ios::sync_with_stdio(false); cin.tie(0); int t; cin >> t; while (t--) solve(); } |
#include <bits/stdc++.h> using namespace std; mt19937 rnd(chrono::steady_clock::now().time_since_epoch().count()); mt19937 rnf(2106); const int N = 1000006, INF = 1000000009; int n; int a[N]; int dp[N][2]; int p[N][2]; void minh(int& x, int& px, int y, int u) { if (y < x) { x = y; px = u; } } bool solv() { dp[1][0] = dp[1][1] = -INF; for (int i = 2; i <= n; ++i) dp[i][0] = dp[i][1] = INF; for (int i = 1; i < n; ++i) { if (a[i] < a[i + 1]) { minh(dp[i + 1][0], p[i + 1][0], dp[i][0], 0); } if (dp[i][0] < a[i + 1]) { minh(dp[i + 1][0], p[i + 1][0], a[i], 0); } if (dp[i][0] < -a[i + 1]) { minh(dp[i + 1][1], p[i + 1][1], a[i], 0); } if (-a[i] < a[i + 1]) { minh(dp[i + 1][0], p[i + 1][0], dp[i][1], 1); } if (-a[i] < -a[i + 1]) { minh(dp[i + 1][1], p[i + 1][1], dp[i][1], 1); } if (dp[i][1] < a[i + 1]) { minh(dp[i + 1][0], p[i + 1][0], -a[i], 1); } if (dp[i][1] < -a[i + 1]) { minh(dp[i + 1][1], p[i + 1][1], -a[i], 1); } } if (dp[n][0] != INF || dp[n][1] != INF) { int u; if (dp[n][0] != INF) u = 0; else u = 1; for (int i = n; i >= 1; --i) { if (u == 1) a[i] *= -1; u = p[i][u]; } cout << YES n ; for (int i = 1; i <= n; ++i) cout << a[i] << ; cout << n ; return true; } cout << NO n ; return false; } bool solv0() { for (int x = 0; x < (1 << n); ++x) { for (int i = 1; i <= n; ++i) { if ((x & (1 << (i - 1)))) a[i] *= -1; } bool z = true; for (int i = 1; i <= n; ++i) { for (int j = i + 1; j <= n; ++j) { for (int k = j + 1; k <= n; ++k) { if (a[i] > a[j] && a[j] > a[k]) { z = false; break; } } if (!z) break; } if (!z) break; } if (z) { return true; for (int i = 1; i <= n; ++i) { if ((x & (1 << (i - 1)))) a[i] *= -1; } return true; } for (int i = 1; i <= n; ++i) { if ((x & (1 << (i - 1)))) a[i] *= -1; } } return false; } int main() { ios_base::sync_with_stdio(false), cin.tie(0); int tt = 100; cin >> tt; while (tt--) { cin >> n; for (int i = 1; i <= n; ++i) cin >> a[i]; solv(); } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EINVP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__EINVP_BEHAVIORAL_PP_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__einvp (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_TE;
// Name Output Other arguments
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_TE, TE, VPWR, VGND );
notif1 notif10 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_TE);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__EINVP_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int mod = 998244353; const int N = 132007; int n, a, b; int rev[N], fac[N], finv[N], f[N], g[N], h[N]; inline int qpow(int x, int k, int r = 1) { for (; k; k >>= 1, x = 1ll * x * x % mod) if (k & 1) r = 1ll * r * x % mod; return r; } inline void ntt(int *a, int len, int opt) { for (int i = 0; i < len; ++i) if (i < rev[i]) swap(a[i], a[rev[i]]); for (int i = 1; i < len; i <<= 1) { int wn = qpow(3, (mod - 1) / (i << 1)); for (int j = 0; j < len; j += i << 1) { int w = 1; for (int k = 0; k < i; ++k, w = 1ll * w * wn % mod) { int x = a[j + k], y = 1ll * a[j + k + i] * w % mod; a[j + k] = (x + y) % mod; a[j + k + i] = (x - y + mod) % mod; } } } if (~opt) return; reverse(a + 1, a + len); const int inv = qpow(len, mod - 2); for (int i = 0; i < len; ++i) a[i] = 1ll * a[i] * inv % mod; } void solve(int n) { if (!n) return g[1] = 1, void(); int t = n - 1 >> 1, mid = n + 1 >> 1, len = 1, bit = 0; for (; len <= n + 2; len <<= 1, ++bit) ; solve(t); for (int i = 0; i < len; ++i) rev[i] = rev[i >> 1] >> 1 | (i & 1) << bit - 1; for (int i = f[0] = 1; i <= mid; ++i) f[i] = 1ll * f[i - 1] * mid % mod; for (int i = 0; i <= mid; ++i) f[i] = 1ll * f[i] * finv[i] % mod, h[i] = 1ll * g[i] * fac[i] % mod; for (int i = mid + 1; i < len; ++i) f[i] = h[i] = 0; reverse(f, f + mid + 2); ntt(f, len, 1); ntt(h, len, 1); for (int i = 0; i < len; ++i) h[i] = 1ll * f[i] * h[i] % mod; ntt(h, len, -1); for (int i = 0; i <= mid; ++i) h[i] = 1ll * h[i + mid + 1] * finv[i] % mod; for (int i = mid + 1; i < len; ++i) h[i] = 0; ntt(g, len, 1); ntt(h, len, 1); for (int i = 0; i < len; ++i) g[i] = 1ll * g[i] * h[i] % mod; ntt(g, len, -1); if (n & 1) return; for (int i = mid + mid + 1; i < len; ++i) g[i] = 0; for (int i = len - 1; i; --i) g[i] = (g[i - 1] + 1ll * g[i] * n) % mod; } inline int C(int n, int m) { return 1ll * fac[n] * finv[m] % mod * finv[n - m] % mod; } int main() { scanf( %d%d%d , &n, &a, &b); long long ans = 0; if (a == b && a == 1) return printf( %d n , n == 1) & 0; if (a + b > n + 1 || !a || !b) return printf( %d n , 0) & 0; for (int i = fac[0] = 1; i <= n; ++i) fac[i] = 1ll * fac[i - 1] * i % mod; finv[n] = qpow(fac[n], mod - 2); for (int i = n; i; --i) finv[i - 1] = 1ll * finv[i] * i % mod; solve(n - 2); return printf( %lld n , 1ll * g[a + b - 2] * C(a + b - 2, a - 1) % mod) & 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast,unroll-loops,no-stack-protector ) using namespace std; int n, k, nrr = 1, t[502 * 1005]; string s; struct point { double x, y; int ind; point() {} point(const point& a) { x = a.x, y = a.y; ind = a.ind; } point(double _x, double _y) { x = _x; y = _y; } point& operator-(point& a) { point* r = new point(*this); r->x -= a.x, r->y -= a.y; return *r; } point& operator+(point& a) { point* r = new point(*this); r->x += a.x, r->y += a.y; return *r; } point& operator*(double val) { point* r = new point(*this); r->x *= val, r->y *= val; return *r; } point& operator/(double val) { point* r = new point(*this); r->x /= val, r->y /= val; return *r; } bool operator<(const point& a) const { if (fabs(x - a.x) < 1e-9) { if (fabs(y - a.y) < 1e-9) return false; return y < a.y; } return x < a.x; } bool operator==(const point& a) const { if (fabs(x - a.x) < 1e-9) if (fabs(y - a.y) < 1e-9) return true; return false; } }; template <class T> ostream& operator<<(ostream& out, vector<T> v) { out << v.size() << n ; for (auto e : v) out << e << ; return out; } ostream& operator<<(ostream& out, point p) { return out << p.x << << p.y; } double dx[] = {1, -1, -1, 1}; double dy[] = {1, -1, 1, -1}; long double dist(point a, point b) { long double X = a.x - b.x; long double Y = a.y - b.y; return sqrt(X * X + Y * Y); } struct circle { point o; double r; circle() {} bool operator==(circle& c) { if (fabs(c.r - r) > 1e-9) return false; if (fabs(c.o.x - o.x) > 1e-9) return false; if (fabs(c.o.y - o.y) > 1e-9) return false; return true; } vector<point> intersect(circle c) { long double p, h, a, area, d; d = dist(o, c.o); if (d > r + c.r) return {}; if (d < fabs(r - c.r)) return {}; a = 0.5 * (d + (r * r - c.r * c.r) / d); h = sqrt(r * r - a * a); point B = o + (c.o - o) * a / d; point aa = c.o - o; point ff(-aa.y, aa.x); aa = ff * h / d; return {B + aa, B - aa}; } }; struct seg { point a, b; }; istream& operator>>(istream& in, point& p) { return in >> p.x >> p.y; } istream& operator>>(istream& in, circle& c) { return in >> c.o >> c.r; } istream& operator>>(istream& in, seg& s) { return in >> s.a >> s.b; } long double area(point a, point b, point c) { return a.x * b.y + b.x * c.y + c.x * a.y - a.y * b.x - b.y * c.x - c.y * a.x; return (b.x - a.x) * (c.y - a.y) - (c.x - a.x) * (b.y - a.y); } circle c[550]; bool use[502 * 1000]; int C, V, E; point pts[500 * 1000]; int sz = 0; int get_p(point p) { pts[++sz] = p; pts[sz].ind = sz; } void dfs2(int k) { use[k] = 1; if (k == t[k]) C++; if (!use[t[k]]) dfs2(t[k]); } inline int par(int k) { if (k == t[k]) return k; return t[k] = par(t[k]); } set<point> inters; void unite(int i, int j) { t[par(i)] = par(j); } int main() { ios_base::sync_with_stdio(false); cin >> n; for (int i = 0; i <= 502 * 502; i++) t[i] = i; for (int i = 1; i <= n; i++) cin >> c[i]; for (int i = 1; i <= n; i++) for (int j = i + 1; j <= n; j++) { if (c[i] == c[j]) swap(c[j], c[n]), n--, j--; } for (int i = 1; i <= n; i++) { inters.clear(); for (int j = 1; j <= n; j++) { if (i == j) continue; auto in = c[i].intersect(c[j]); for (auto p : in) { inters.insert(p); } } int init; for (auto i : inters) { sz++; pts[sz] = i; pts[sz].ind = sz; if (!(i == *inters.begin())) unite(sz, init); else init = sz; } E += inters.size(); if (inters.size() == 0) C++; } V = sz; int u = 0; for (int i = 1; i <= sz; i++) pts[i].ind = i; sort(pts + 1, pts + sz + 1); for (int i = 1; i <= sz; i++, u++) { int j = i + 1; while (j <= sz && pts[i] == pts[j]) { unite(pts[i].ind, pts[j].ind); j++; } i = j - 1; } for (int i = 1; i <= V; i++) if (t[i] == i) C++; V = u; cerr << V : << V << n ; cerr << E : << E << n ; cout << E - V + C + 1 << n ; } |
#include <bits/stdc++.h> using namespace std; const long double EPS = 1E-9; const int INF = (int)1E9; const long long INF64 = (long long)1E18; const long double PI = 2 * acos(.0); int main() { bool cumple[1005]; for (int i = 0; i < (int)(1005); i++) cumple[i] = false; string word; cin >> word; int n = (word).size(); for (int i = 2; i <= n / 2; i++) { cumple[i] = 1; for (int j = 2; i * j <= n; j++) { cumple[i * j] = 1; } } int cont1 = 0; for (int i = 1; i < (int)(n + 1); i++) { if (cumple[i] == 1) cont1++; } int numWord[50]; memset(numWord, 0, sizeof(numWord)); for (int i = 0; i < (int)(n); i++) numWord[word[i] - a ]++; int maxPos = -1, maxi = -1; for (int i = 0; i < (int)(50); i++) { if (maxi < numWord[i]) { maxi = numWord[i]; maxPos = i; } } if (maxi < cont1) cout << NO << endl; else { string rege; rege.append(n, ? ); for (int i = 1; i < (int)(n + 1); i++) if (cumple[i] == 1) rege[i - 1] = a + maxPos; numWord[maxPos] -= cont1; int cont = 0, wpos = 0; while (wpos < n) { if (rege[wpos] == ? ) { if (numWord[cont] > 0) { rege[wpos] = ( a + cont); numWord[cont]--; } else cont++; } else wpos++; } cout << YES << endl; cout << rege << endl; } return 0; } |
//-----------------------------------------------------
// Design Name : hw1_A_testbench
// File Name : hw1_A_testbench.v
// Function : This program will test hw1_A.v
// Coder : hydai
//-----------------------------------------------------
`timescale 1 ns/1 ns
`include "hw1_A.v"
module hw1_A_testbench ;
reg [15:0] data;
reg [6:0] control;
reg clk, rst_n;
wire [15:0] R0, R1, R2, R3;
hw1_A testA(data,
control,
clk,
rst_n,
R0,
R1,
R2,
R3);
initial begin
#0 rst_n = 1'b0; clk = 1'b0;
$display ("====================================================================");
$display ("Simulate hw1_A");
$display ("Time %t status", $time);
$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
rst_n, data, control, R0, R1, R2, R3);
#20 rst_n = 1'b1;
$display ("====================================================================");
$display ("Time %t status", $time);
$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
rst_n, data, control, R0, R1, R2, R3);
// Data <- 0x1234
#20 data = 16'h1234;
$display ("====================================================================");
$display ("Time %t status", $time);
$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
rst_n, data, control, R0, R1, R2, R3);
// R1 <- Data(0x1234)
#20 control = 7'b111_0010;
$display ("====================================================================");
$display ("Time %t status", $time);
$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
rst_n, data, control, R0, R1, R2, R3);
// Data <- 0x8888
#20 data = 16'h8888;
$display ("====================================================================");
$display ("Time %t status", $time);
$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
rst_n, data, control, R0, R1, R2, R3);
// R2 <- Data(0x8888)
#20 control = 7'b111_0100;
$display ("====================================================================");
$display ("#### R1 = 0x1234");
$display ("Time %t status", $time);
$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
rst_n, data, control, R0, R1, R2, R3);
// Pass R2
#20 control = 7'b010_0000;
$display ("====================================================================");
$display ("#### R2 = 0x8888");
$display ("Time %t status", $time);
$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
rst_n, data, control, R0, R1, R2, R3);
// Pass R1; Save passing value to R1
#20 control = 7'b001_0010;
$display ("====================================================================");
$display ("Time %t status", $time);
$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
rst_n, data, control, R0, R1, R2, R3);
// Save passing value to R2; Pass Null
#20 control = 7'b100_0100;
$display ("====================================================================");
$display ("Time %t status", $time);
$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
rst_n, data, control, R0, R1, R2, R3);
// Pass R1
#20 control = 7'b001_0000;
$display ("====================================================================");
$display ("Time %t status", $time);
$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
rst_n, data, control, R0, R1, R2, R3);
// Save passing value to R3; Pass R1
#20 control = 7'b001_1000;
$display ("====================================================================");
$display ("Time %t status", $time);
$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
rst_n, data, control, R0, R1, R2, R3);
// Save passing value to R0; Pass Null
#20 control = 7'b100_0001;
$display ("====================================================================");
$display ("Time %t status", $time);
$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
rst_n, data, control, R0, R1, R2, R3);
#20
$display ("====================================================================");
$display ("Time %t status", $time);
$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
rst_n, data, control, R0, R1, R2, R3);
$display ("====================================================================");
#40 $finish;
end
always begin
#10 clk = ~clk;
end
initial begin
$fsdbDumpfile("hw1_A_testbench.fsdb");
$fsdbDumpvars;
end
endmodule // End of Module hw1_A_testbench
|
module top;
reg pass = 1'b1;
reg in;
wire bf1, bf2, nt1, nt2, pd1, pd2, pu1, pu2;
initial begin
// $monitor(bf1, bf2,, nt1, nt2,, pd1, pd2,, pu1, pu2,, in);
#1;
if (bf1 !== 1'bx && bf2 !== 1'bx) begin
$display("Buffer failed, expected 2'bxx, got %b%b", bf1, bf2);
pass = 1'b0;
end
if (nt1 !== 1'bx && nt2 !== 1'bx) begin
$display("Inverter (not) failed, expected 2'bxx, got %b%b", nt1, nt2);
pass = 1'b0;
end
if (pd1 !== 1'b0 && pd2 !== 1'b0) begin
$display("Pull down failed, expected 2'b00, got %b%b", pd1, pd2);
pass = 1'b0;
end
if (pu1 !== 1'b1 && pu2 !== 1'b1) begin
$display("Pull up failed, expected 2'b11, got %b%b", pu1, pu2);
pass = 1'b0;
end
in = 1'b0;
#1;
if (bf1 !== 1'b0 && bf2 !== 1'b0) begin
$display("Buffer failed, expected 2'b00, got %b%b", bf1, bf2);
pass = 1'b0;
end
if (nt1 !== 1'b1 && nt2 !== 1'b1) begin
$display("Inverter (not) failed, expected 2'b11, got %b%b", nt1, nt2);
pass = 1'b0;
end
if (pd1 !== 1'b0 && pd2 !== 1'b0) begin
$display("Pull down failed, expected 2'b00, got %b%b", pd1, pd2);
pass = 1'b0;
end
if (pu1 !== 1'b1 && pu2 !== 1'b1) begin
$display("Pull up failed, expected 2'b11, got %b%b", pu1, pu2);
pass = 1'b0;
end
in = 1'b1;
#1;
if (bf1 !== 1'b1 && bf2 !== 1'b1) begin
$display("Buffer failed, expected 2'b11, got %b%b", bf1, bf2);
pass = 1'b0;
end
if (nt1 !== 1'b0 && nt2 !== 1'b0) begin
$display("Inverter (not) failed, expected 2'b00, got %b%b", nt1, nt2);
pass = 1'b0;
end
if (pd1 !== 1'b0 && pd2 !== 1'b0) begin
$display("Pull down failed, expected 2'b00, got %b%b", pd1, pd2);
pass = 1'b0;
end
if (pu1 !== 1'b1 && pu2 !== 1'b1) begin
$display("Pull up failed, expected 2'b11, got %b%b", pu1, pu2);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
buf (bf1, bf2, in);
not (nt1, nt2, in);
pulldown (pd1, pd2);
pullup (pu1, pu2);
endmodule
|
#include <bits/stdc++.h> inline long long read() { char c; long long x; for (c = getchar(); !isdigit(c); c = getchar()) ; for (x = 0; isdigit(c); c = getchar()) { x = x * 10 + c - 0 ; } return x; } const int N = 2e5 + 5; int n, q, d[N], f[N]; long long a[N], b[N], c[N], s[N]; std::multiset<long long> set[N], all; void modify(int u, int sgn, int flag) { int v = f[u]; if (!set[v].empty()) { if (flag || sgn < 0) { all.erase(all.find(*set[v].begin() + c[v])); all.erase(all.find(*set[v].rbegin() + c[v])); } } if (sgn == 1) { set[v].insert(b[u] + s[u]); } if (sgn == -1) { set[v].erase(set[v].find(b[u] + s[u])); } if (!set[v].empty()) { if (flag || sgn > 0) { assert(!set[v].empty()); all.insert(*set[v].begin() + c[v]); all.insert(*set[v].rbegin() + c[v]); } } } int main() { n = read(); q = read(); for (int u = 1; u <= n; u++) { a[u] = read(); d[u] = 1; } for (int u = 1; u <= n; u++) { f[u] = read(); d[f[u]]++; } for (int u = 1; u <= n; u++) { c[u] = a[u] / (d[u] + 1); b[u] = a[u] - c[u] * d[u]; s[f[u]] += c[u]; } for (int u = 1; u <= n; u++) { modify(u, 1, 1); } for (int i = 0; i < q; i++) { int opt = read(); if (opt == 1) { int u = read(), v = read(); modify(u, -1, 0); modify(f[u], -1, 0); modify(f[f[u]], -1, 0); d[f[u]]--; s[f[u]] -= c[u]; s[f[f[u]]] -= c[f[u]]; c[f[u]] = a[f[u]] / (d[f[u]] + 1); b[f[u]] = a[f[u]] - c[f[u]] * d[f[u]]; s[f[f[u]]] += c[f[u]]; modify(u, 2, 0); modify(f[u], 1, 0); modify(f[f[u]], 1, 0); f[u] = v; modify(u, -2, 0); modify(f[u], -1, 0); modify(f[f[u]], -1, 0); d[f[u]]++; s[f[u]] += c[u]; s[f[f[u]]] -= c[f[u]]; c[f[u]] = a[f[u]] / (d[f[u]] + 1); b[f[u]] = a[f[u]] - c[f[u]] * d[f[u]]; s[f[f[u]]] += c[f[u]]; modify(u, 1, 0); modify(f[u], 1, 0); modify(f[f[u]], 1, 0); } else if (opt == 2) { int u = read(); printf( %lld n , b[u] + c[f[u]] + s[u]); } else { printf( %lld %lld n , *all.begin(), *all.rbegin()); } } return 0; } |
// Double-input register (Reconfigurable Computing Lab 0 Problem 3)
// Author: Mark Blanco
// Date: 8/4/2017
module register(
ridxA,
widxA,
wdataA,
weA,
ridxB,
widxB,
wdataB,
weB,
clk,
reset,
rdataA,
rdataB
);
// Inputs:
input wire [4:0] ridxA; // Read index
input wire [4:0] widxA; // Write index
input wire [31:0] wdataA;// Input data
input wire weA; // Write enable
input wire [4:0] ridxB; // Read index
input wire [4:0] widxB; // Write index
input wire [31:0] wdataB;// Input data
input wire weB; // Write enable
input wire clk; // Clock
input wire reset; // Reset
// Outputs:
output wire [31:0] rdataA;
output wire [31:0] rdataB;
// Internal State/Storage
reg [31:0] mem [31:0]; // 32-bit array (mem) repeated 32 times
reg [31:0] i; // Counter for for loop
// Helper task to reset all reg entries to 0
task resetReg;
begin
for ( i = 0; i < 32; i = i + 1) begin
mem[i] = 32'b0;
end
end
endtask
task writeB;
begin
if (widxB == 32'b0 | !weB) begin
// Don't do anything
end
else begin
mem[widxB] = wdataB;
end
end
endtask
task writeA;
begin
if (widxA == 32'b0 | !weA) begin
// Don't do anything
end
else begin
mem[widxA] = wdataA;
end
end
endtask
// Start all of the entries zeroed out.
initial begin
resetReg;
end
// Continuously assign the read port to the selected read address
assign rdataA = mem[ridxA];
assign rdataB = mem[ridxB];
// Monitor for posedge clk and write as appropriate
always @ (posedge clk) begin
if (reset) begin
resetReg;
end
// Otherwise perform synchronous write of data is write is enabled
// Give write port B priority if both enables are asserted to the same address
else begin
if ((widxA == widxB) & weB) begin
writeB;
end
else begin
writeB;
writeA;
end
end
end
endmodule |
#include <bits/stdc++.h> using namespace std; int fastMax(int x, int y) { return (((y - x) >> (32 - 1)) & (x ^ y)) ^ y; } int fastMin(int x, int y) { return (((y - x) >> (32 - 1)) & (x ^ y)) ^ x; } void solve() { long long int x, y, z; cin >> x >> y >> z; long long int x1, y1, z1; cin >> x1 >> y1 >> z1; long long int a1, a2, a3, a4, a5, a6; cin >> a1 >> a2 >> a3 >> a4 >> a5 >> a6; long long int ans = 0; if (x > x1) ans += a6; else if (x < 0) ans += a5; if (y > y1) ans += a2; else if (y < 0) ans += a1; if (z > z1) ans += a4; else if (z < 0) ans += a3; cout << ans << endl; } signed main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long int t; t = 1; while (t--) solve(); } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This is the dac physical interface (drives samples from the low speed clock to the
// dac clock domain.
`timescale 1ns/100ps
module axi_ad9739a_if (
// dac interface
dac_clk_in_p,
dac_clk_in_n,
dac_clk_out_p,
dac_clk_out_n,
dac_data_out_a_p,
dac_data_out_a_n,
dac_data_out_b_p,
dac_data_out_b_n,
// internal resets and clocks
dac_rst,
dac_clk,
dac_div_clk,
dac_status,
// data interface
dac_data_00,
dac_data_01,
dac_data_02,
dac_data_03,
dac_data_04,
dac_data_05,
dac_data_06,
dac_data_07,
dac_data_08,
dac_data_09,
dac_data_10,
dac_data_11,
dac_data_12,
dac_data_13,
dac_data_14,
dac_data_15);
// parameters
parameter PCORE_DEVICE_TYPE = 0;
// dac interface
input dac_clk_in_p;
input dac_clk_in_n;
output dac_clk_out_p;
output dac_clk_out_n;
output [13:0] dac_data_out_a_p;
output [13:0] dac_data_out_a_n;
output [13:0] dac_data_out_b_p;
output [13:0] dac_data_out_b_n;
// internal resets and clocks
input dac_rst;
output dac_clk;
output dac_div_clk;
output dac_status;
// data interface
input [15:0] dac_data_00;
input [15:0] dac_data_01;
input [15:0] dac_data_02;
input [15:0] dac_data_03;
input [15:0] dac_data_04;
input [15:0] dac_data_05;
input [15:0] dac_data_06;
input [15:0] dac_data_07;
input [15:0] dac_data_08;
input [15:0] dac_data_09;
input [15:0] dac_data_10;
input [15:0] dac_data_11;
input [15:0] dac_data_12;
input [15:0] dac_data_13;
input [15:0] dac_data_14;
input [15:0] dac_data_15;
// internal registers
reg dac_status = 'd0;
// internal signals
wire dac_clk_in_s;
wire dac_div_clk_s;
// dac status
always @(posedge dac_div_clk) begin
if (dac_rst == 1'b1) begin
dac_status <= 1'd0;
end else begin
dac_status <= 1'd1;
end
end
// dac data output serdes(s) & buffers
ad_serdes_out #(
.SERDES(1),
.DATA_WIDTH(14),
.DEVICE_TYPE (PCORE_DEVICE_TYPE))
i_serdes_out_data_a (
.rst (dac_rst),
.clk (dac_clk),
.div_clk (dac_div_clk),
.data_s0 (dac_data_00[15:2]),
.data_s1 (dac_data_02[15:2]),
.data_s2 (dac_data_04[15:2]),
.data_s3 (dac_data_06[15:2]),
.data_s4 (dac_data_08[15:2]),
.data_s5 (dac_data_10[15:2]),
.data_s6 (dac_data_12[15:2]),
.data_s7 (dac_data_14[15:2]),
.data_out_p (dac_data_out_a_p),
.data_out_n (dac_data_out_a_n));
// dac data output serdes(s) & buffers
ad_serdes_out #(
.SERDES(1),
.DATA_WIDTH(14),
.DEVICE_TYPE (PCORE_DEVICE_TYPE))
i_serdes_out_data_b (
.rst (dac_rst),
.clk (dac_clk),
.div_clk (dac_div_clk),
.data_s0 (dac_data_01[15:2]),
.data_s1 (dac_data_03[15:2]),
.data_s2 (dac_data_05[15:2]),
.data_s3 (dac_data_07[15:2]),
.data_s4 (dac_data_09[15:2]),
.data_s5 (dac_data_11[15:2]),
.data_s6 (dac_data_13[15:2]),
.data_s7 (dac_data_15[15:2]),
.data_out_p (dac_data_out_b_p),
.data_out_n (dac_data_out_b_n));
// dac clock output serdes & buffer
ad_serdes_out #(
.SERDES(1),
.DATA_WIDTH(1),
.DEVICE_TYPE (PCORE_DEVICE_TYPE))
i_serdes_out_clk (
.rst (dac_rst),
.clk (dac_clk),
.div_clk (dac_div_clk),
.data_s0 (1'b1),
.data_s1 (1'b0),
.data_s2 (1'b1),
.data_s3 (1'b0),
.data_s4 (1'b1),
.data_s5 (1'b0),
.data_s6 (1'b1),
.data_s7 (1'b0),
.data_out_p (dac_clk_out_p),
.data_out_n (dac_clk_out_n));
// dac clock input buffers
IBUFGDS i_dac_clk_in_ibuf (
.I (dac_clk_in_p),
.IB (dac_clk_in_n),
.O (dac_clk_in_s));
BUFG i_dac_clk_in_gbuf (
.I (dac_clk_in_s),
.O (dac_clk));
BUFR #(.BUFR_DIVIDE("4")) i_dac_div_clk_rbuf (
.CLR (1'b0),
.CE (1'b1),
.I (dac_clk_in_s),
.O (dac_div_clk_s));
BUFG i_dac_div_clk_gbuf (
.I (dac_div_clk_s),
.O (dac_div_clk));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; int f[100001], d[40], sor[100001]; int n, kq; bool solve(int a, int b, int &x, int &y) { if (a % 2 != b % 2) return false; y = (a + b) / 2; x = (a - b) / 2; return true; } int main() { scanf( %d , &n); kq = -1; for (int i = 3; i < n + 1; i++) { memset(d, false, sizeof(d)); for (int j = 2; j * j <= 2 * i; j++) if ((2 * i) % j == 0) { int x, y; if (solve((2 * i) / j, j - 1, x, y)) { d[sor[y] ^ sor[x - 1]] = true; if (i == n && sor[y] == sor[x - 1]) if (kq == -1 || j < kq) kq = j; } } for (int j = 0; j < 40; j++) if (!d[j]) { f[i] = j; sor[i] = sor[i - 1] ^ j; if (i == n && f[i] == 0) kq = -1; break; } } cout << kq << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long N = 1e6 + 7; struct node { long long l, r, i; }; bool cmp(node &a, node &b) { return a.l < b.l; } int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t; t = 1; cin >> t; while (t--) { long long n; cin >> n; long long x, y; bool flag = 0; vector<long long> ans(n); vector<node> a; for (long long i = 0; i < n; i++) { cin >> x >> y; a.push_back({x, y, i}); } sort((a).begin(), (a).end(), cmp); long long p = -1; x = a[0].r; for (long long i = 1; i < n; i++) { if (x < a[i].l) { p = i; break; } x = max(x, a[i].r); } if (p == -1) cout << -1 << n ; else { for (long long i = 0; i < p; i++) ans[a[i].i] = 1; for (long long i = p; i < n; i++) ans[a[i].i] = 2; for (auto i : ans) cout << i << ; cout << n ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; vector<string> s; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; s.resize(n); for (int i = 0; i < n; i++) { cin >> s[i]; } int ans = 0; for (int i = 0; i < 7; i++) { int cnt = 0; for (int j = 0; j < n; j++) { if (s[j][i] == 1 ) cnt++; } ans = max(ans, cnt); } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; void think() { long long n, m; cin >> n >> m; vector<long long> v(n); for (long long i = 0; i < n; i++) { cin >> v[i]; } long long ans = 0; for (long long i = 0; i < m; i++) { long long x, y; cin >> x >> y; ans += min(v[x - 1], v[y - 1]); } cout << ans << n ; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; long long testcase = 1; while (testcase--) { think(); } return 0; } |
// part of NeoGS project
//
// (c) NedoPC 2007-2013
//
// this is dma "one-shot" fifo: after each 512 bytes both written and read back, it must be initialized by means of 'init'
//
module dma_fifo_oneshot(
input wire clk,
input wire rst_n,
input wire wr_stb, // write strobe: writes data from wd to the current wptr, increments wptr
input wire rd_stb, // read strobe: increments rptr
output wire wdone, // write done - all 512 bytes are written (end of write operation)
output wire w511, // write almost done -- at address 511
output wire rdone, // read done - all 512 bytes are read (end of read operation)
output wire empty, // fifo empty: when wptr==rptr (rd_stb must not be issued when empty is active, otherwise everytrhing desyncs)
input wire [7:0] wd, // data to be written
output wire [7:0] rd // data just read from rptr address
);
reg [9:0] wptr;
reg [9:0] rptr;
always @(posedge clk, negedge rst_n)
if( !rst_n )
wptr = 10'd0;
else if( wr_stb )
wptr <= wptr + 10'd1;
assign w511 = &wptr[8:0];
always @(posedge clk, negedge rst_n)
if( !rst_n )
rptr = 10'd0;
else if( rd_stb )
rptr <= rptr + 10'd1;
assign wdone = wptr[9];
assign rdone = rptr[9];
assign empty = ( wptr==rptr );
mem512b fifo512_oneshot_mem512b
(
.clk(clk),
.rdaddr(rptr[8:0]),
.dataout(rd),
.re(rd_stb),
.wraddr(wptr[8:0]),
.datain(wd),
.we(wr_stb)
);
endmodule
|
#include <bits/stdc++.h> using std::cin; using std::cout; struct Item { int parent; int count; }; int Find(int x, std::vector<Item>* items) { if (items->at(x).parent == x) { return x; } return items->at(x).parent = Find(items->at(x).parent, items); } void Unite(int x, int y, std::vector<Item>* items) { assert(x == Find(x, items)); assert(y == Find(y, items)); if (items->at(x).count < items->at(y).count) { std::swap(x, y); } items->at(y).parent = x; items->at(x).count += items->at(y).count; } int main() { std::ios_base::sync_with_stdio(false); int N, M; cin >> N >> M; std::vector<std::pair<int, int>> A(N); std::vector<Item> items(N); for (int i = 0; i < N; ++i) { int a; cin >> a; A[i].first = a; A[i].second = i; items[i].parent = i; items[i].count = 1; } std::vector<std::vector<int>> gr(N); for (int i = 0; i < M; ++i) { int a, b; cin >> a >> b; --a; --b; gr[a].push_back(b); gr[b].push_back(a); } std::sort(A.begin(), A.end()); int64_t answer = 0; std::vector<int> visited(N, false); for (int index = N - 1; index >= 0; --index) { int value = A[index].first; int vertex = A[index].second; int64_t sum = 0, sum_sq = 0; for (int neib : gr[vertex]) { int x = Find(vertex, &items); int y = Find(neib, &items); if (x == y) { continue; } if (!visited[y]) { continue; } sum += items[y].count; sum_sq += (int64_t)items[y].count * items[y].count; Unite(x, y, &items); } answer += (int64_t)value * (sum * sum - sum_sq + 2 * sum); visited[Find(vertex, &items)] = true; } long double result = (long double)answer / ((int64_t)N * (N - 1)); cout.precision(6); cout << std::fixed << result << n ; return 0; } |
// Name: WcaReadByteReg.v
//
// Copyright(c) 2013 Loctronix Corporation
// http://www.loctronix.com
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
module WcaReadByteReg
(
input wire reset, //Active Hi
input wire clock, //System clock, should be synchronous with WcaRegbus
input wire enableIn, //Allows input if specified.
input wire [7:0] in, //Register Input.
output wire [7:0] Q, //Current state of the register.
//Internal Interface.
input wire [11:0] rbusCtrl, // Address and control lines(12 total) { addr[7:0], readEnable, writeEnable, dataStrobe, clkbus}
inout wire [7:0] rbusData // Tri-state I/O data.
);
parameter my_addr = 0;
parameter AllowWriteOnRead = 1'b0;
wire addrValid = (my_addr == rbusCtrl[11:4]);
wire read = addrValid & rbusCtrl[3];
wire enable = enableIn & (~addrValid | AllowWriteOnRead);
// Only allow latching when addres is not valid. If preparing for a read, everything must be stable.
WcaRegCore8 sr( .Data(in), .Enable( enable ), .Aclr(reset), .Clock(clock), .Q(Q));
//Place data on the buss if reading.
assign rbusData = (read ) ? Q : 8'bz;
endmodule // WcaReadByteReg
|
// MBT 7/7/2016
//
// 1 read-port, 1 write-port ram
//
// reads are synchronous
//
// although we could merge this with normal bsg_mem_1r1w
// and select with a parameter, we do not do this because
// it's typically a very big change to the instantiating code
// to move to/from sync/async, and we want to reflect this.
//
`include "bsg_defines.v"
module bsg_mem_1r1w_sync #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter harden_p=0
, parameter disable_collision_warning_p=0
, parameter enable_clock_gating_p=0
)
(input clk_i
, input reset_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [`BSG_SAFE_MINUS(width_p, 1):0] w_data_i
// currently unused
, input r_v_i
, input [addr_width_lp-1:0] r_addr_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] r_data_o
);
wire clk_lo;
if (enable_clock_gating_p)
begin
bsg_clkgate_optional icg
(.clk_i( clk_i )
,.en_i( w_v_i | r_v_i )
,.bypass_i( 1'b0 )
,.gated_clock_o( clk_lo )
);
end
else
begin
assign clk_lo = clk_i;
end
bsg_mem_1r1w_sync_synth
#(.width_p(width_p)
,.els_p(els_p)
,.read_write_same_addr_p(read_write_same_addr_p)
,.harden_p(harden_p)
) synth
(.clk_i( clk_lo )
,.reset_i
,.w_v_i
,.w_addr_i
,.w_data_i
,.r_v_i
,.r_addr_i
,.r_data_o
);
//synopsys translate_off
initial
begin
// we warn if els_p >= 16 because it is a good candidate for hardening
// and we warn for width_p >= 128 because this starts to add up to some real memory
if ((els_p >= 16) || (width_p >= 128) || (width_p*els_p > 256))
$display("## %L: instantiating width_p=%d, els_p=%d, read_write_same_addr_p=%d, harden_p=%d (%m)",width_p,els_p,read_write_same_addr_p,harden_p);
if (disable_collision_warning_p)
$display("## %L: disable_collision_warning_p is set; you should not have this on unless you have broken code. fix it!\n");
end
always_ff @(posedge clk_lo)
if (w_v_i)
begin
assert ((reset_i === 'X) || (reset_i === 1'b1) || (w_addr_i < els_p))
else $error("Invalid address %x to %m of size %x\n", w_addr_i, els_p);
assert ((reset_i === 'X) || (reset_i === 1'b1) || ~(r_addr_i == w_addr_i && w_v_i && r_v_i && !read_write_same_addr_p && !disable_collision_warning_p))
else
begin
$error("X'ing matched read address %x (%m)",r_addr_i);
end
end
//synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1r1w_sync)
|
// megafunction wizard: %RAM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: memoria.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.0.0 Build 200 06/17/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module memoria (
address,
clock,
data,
wren,
q);
input [15:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "65536"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "16"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "65536"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 16 0 INPUT NODEFVAL "address[15..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 16 0 address 0 0 16 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL memoria.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL memoria.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL memoria.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL memoria.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL memoria_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL memoria_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:28:18 08/24/2011
// Design Name:
// Module Name: q15_add
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module qadd #(
//Parameterized values
parameter Q = 15,
parameter N = 32
)
(
input [N-1:0] a,
input [N-1:0] b,
output [N-1:0] c
);
reg [N-1:0] res;
assign c = res;
always @(a,b) begin
// both negative or both positive
if(a[N-1] == b[N-1]) begin // Since they have the same sign, absolute magnitude increases
res[N-2:0] = a[N-2:0] + b[N-2:0]; // So we just add the two numbers
res[N-1] = a[N-1]; // and set the sign appropriately... Doesn't matter which one we use,
// they both have the same sign
// Do the sign last, on the off-chance there was an overflow...
end // Not doing any error checking on this...
// one of them is negative...
else if(a[N-1] == 0 && b[N-1] == 1) begin // subtract a-b
if( a[N-2:0] > b[N-2:0] ) begin // if a is greater than b,
res[N-2:0] = a[N-2:0] - b[N-2:0]; // then just subtract b from a
res[N-1] = 0; // and manually set the sign to positive
end
else begin // if a is less than b,
res[N-2:0] = b[N-2:0] - a[N-2:0]; // we'll actually subtract a from b to avoid a 2's complement answer
if (res[N-2:0] == 0)
res[N-1] = 0; // I don't like negative zero....
else
res[N-1] = 1; // and manually set the sign to negative
end
end
else begin // subtract b-a (a negative, b positive)
if( a[N-2:0] > b[N-2:0] ) begin // if a is greater than b,
res[N-2:0] = a[N-2:0] - b[N-2:0]; // we'll actually subtract b from a to avoid a 2's complement answer
if (res[N-2:0] == 0)
res[N-1] = 0; // I don't like negative zero....
else
res[N-1] = 1; // and manually set the sign to negative
end
else begin // if a is less than b,
res[N-2:0] = b[N-2:0] - a[N-2:0]; // then just subtract a from b
res[N-1] = 0; // and manually set the sign to positive
end
end
end
endmodule
|
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
//*******************************************************************************************
//Author: ZhiYoong Foo ()
//Last Modified: Feb 25 2014
//Description: MBUS Timer Block Example
// Synthesize Block
//Update History: Feb 25 2014 - First commit
//*******************************************************************************************
module timer
(
//**************************************
//Power Domain
//Input - Layer Controller
//Output - N/A
//**************************************
//Signals
//Input
CLK,
TIMER_RESETn,
TIMER_EN,
TIMER_ROI,
TIMER_SAT,
TIMER_CLR_IRQ,
//Output
TIMER_VAL,
TIMER_IRQ
);
input CLK;
input TIMER_RESETn;
input TIMER_EN;
input [7:0] TIMER_SAT;
input TIMER_ROI;
input TIMER_CLR_IRQ;
output reg [7:0] TIMER_VAL;
output reg TIMER_IRQ;
reg [7:0] next_TIMER_VAL;
reg next_TIMER_IRQ;
always @* begin
if (~TIMER_RESETn) begin
next_TIMER_VAL <= 8'h00;
end
else if (TIMER_EN) begin
if (TIMER_VAL == TIMER_SAT) begin
if (TIMER_ROI) begin
next_TIMER_VAL <= 8'h00;
end
else begin
next_TIMER_VAL <= TIMER_VAL;
end
end
else begin
next_TIMER_VAL <= TIMER_VAL +1;
end // else: !if(TIMER_VAL == TIMER_SAT)
end // if (TIMER_EN)
else begin
next_TIMER_VAL <= 8'h00;
end // else: !if(TIMER_EN)
end
always @* begin
if (~TIMER_RESETn) begin
next_TIMER_IRQ <= 1'b0;
end
else if (TIMER_CLR_IRQ) begin
next_TIMER_IRQ <= 1'b0;
end
else if ((next_TIMER_VAL == TIMER_SAT) && (next_TIMER_VAL != TIMER_VAL)) begin
next_TIMER_IRQ <= 1'b1;
end
end
always @(posedge CLK or negedge TIMER_RESETn) begin
if (~TIMER_RESETn) begin
TIMER_VAL <= `SD 8'h00;
TIMER_IRQ <= `SD 1'b0;
end
else begin
TIMER_VAL <= `SD next_TIMER_VAL;
TIMER_IRQ <= `SD next_TIMER_IRQ;
end
end
endmodule // timer
|
#include <bits/stdc++.h> using namespace std; int ls, cc; char s[1111111], a[1111111]; int main() { gets(s), ls = strlen(s), cc = 0, a[0] = # ; for (int i = 0; i < ls; ++i) { a[++cc] = s[i]; while (cc > 1 && a[cc - 1] != a[cc]) cc -= 2; } for (int i = 1; i <= cc; ++i) putchar(a[i]); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR3B_1_V
`define SKY130_FD_SC_HDLL__OR3B_1_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog wrapper for or3b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__or3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__or3b_1 (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__or3b_1 (
X ,
A ,
B ,
C_N
);
output X ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR3B_1_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 2e5 + 10; long long spf[MAXN]; long long min1[MAXN]; long long min2[MAXN]; void sieve() { spf[1] = 1; for (int i = 2; i < MAXN; i++) spf[i] = i; for (int i = 4; i < MAXN; i += 2) spf[i] = 2; for (int i = 3; i * i < MAXN; i++) { if (spf[i] == i) { for (int j = i * i; j < MAXN; j += i) if (spf[j] == j) spf[j] = i; } } } vector<pair<int, int>> getFactorization(int x) { vector<pair<int, int>> ret; while (x != 1) { int cur = spf[x]; int cnt = 0; while (x && spf[x] == cur) { ++cnt; x = x / spf[x]; } ret.push_back({cur, cnt}); } return ret; } void solve() { int n; cin >> n; vector<int> arr(n); for (auto &a : arr) { cin >> a; } sieve(); memset(min1, -1, sizeof(min1)); memset(min2, -1, sizeof(min2)); vector<int> many(MAXN, 0); for (int i = 0; i < n; ++i) { int x = arr[i]; vector<pair<int, int>> fact = getFactorization(x); for (auto ff : fact) { int p = ff.first; int c = ff.second; if (min1[p] == -1) { min1[p] = c; } else if (min2[p] == -1) { int m = min1[p]; if (c <= m) { min1[p] = c; min2[p] = m; } else { min1[p] = m; min2[p] = c; } } else { int m1 = min1[p]; int m2 = min2[p]; if (c <= m1) { min1[p] = c; min2[p] = m1; } else if (c <= m2) { min2[p] = m2; } } ++many[p]; } } long long res = 1; for (int i = 2; i < MAXN; ++i) { if (many[i] == n) { res *= pow(1ll * i, min2[i]); } else if (many[i] == n - 1) { res *= pow(1ll * i, min1[i]); } } cout << res << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; int t; t = 1; while (t--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long MAXN = 1e5 + 5; char C[MAXN][20][20]; long long aans[MAXN]; struct node { long long u, v, val, way; node() {} node(long long a, long long b, long long c) { u = a; v = b; val = c; } }; vector<node> v; vector<int> vv[MAXN]; long long fa[MAXN * 10]; bool cmp(node a, node b) { return a.val < b.val; } long long getf(long long x) { if (x == fa[x]) return x; else return fa[x] = getf(fa[x]); } void add(long long a, long long b) { fa[getf(a)] = getf(fa[b]); } void dfs(long long x, long long fa) { long long len = vv[x].size(); for (long long i = 0; i < len; i++) { long long to = vv[x][i]; if (to != fa) { cout << to << << x << endl; dfs(to, x); } } } int main() { long long n, m, k, w; cin >> n >> m >> k >> w; for (long long k1 = 1; k1 <= k; k1++) { for (long long i = 1; i <= n; i++) { cin >> C[k1][i] + 1; } } for (long long k1 = 1; k1 <= k; k1++) { for (long long k2 = k1 + 1; k2 <= k; k2++) { long long num = 0; for (long long i = 1; i <= n; i++) { for (long long j = 1; j <= m; j++) { if (C[k1][i][j] != C[k2][i][j]) num++; } } v.push_back(node(k1, k2, num * w)); } } for (long long i = 1; i <= k; i++) { v.push_back(node(0, i, n * m)); } long long ans = 0; for (long long i = 1; i <= k; i++) { fa[i] = i; } sort(v.begin(), v.end(), cmp); for (long long i = 0; i < v.size(); i++) { long long aa = v[i].u, cc = v[i].val; long long bb = v[i].v; if (getf(aa) != getf(bb)) { add(aa, bb); ans += cc; vv[aa].push_back(bb); vv[bb].push_back(aa); } } cout << ans << endl; dfs(0, 0); } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:59:33 04/09/2015
// Design Name:
// Module Name: GCD
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module GCD(input [31:0] a, input [31:0] b, input reset, input clk, output reg [31:0] gcd, output reg isDone
);
reg [31:0] nextInputA;
reg [31:0] nextInputB;
reg [31:0] inputA;
reg [31:0] inputB;
reg [31:0] nextExponent;
reg [31:0] exponent;
reg [31:0] nextGcd;
reg nextIsDone;
initial begin
nextInputA = 0;
nextInputB = 0;
inputA = 0;
inputB = 0;
nextExponent = 0;
exponent = 0;
nextIsDone = 0;
isDone = 0;
nextGcd = 0;
gcd = 0;
end
always @(posedge clk) begin
inputA <= nextInputA;
inputB <= nextInputB;
exponent <= nextExponent;
isDone <= nextIsDone;
gcd <= nextGcd;
end
always @(*) begin
nextInputA = inputA;
nextInputB = inputB;
nextIsDone = isDone;
nextExponent = exponent;
nextGcd = gcd;
if (reset == 1) begin
nextInputA = 0;
nextInputB = 0;
nextExponent = 0;
nextIsDone = 0;
end
else begin
if (inputA == 0) begin
nextInputA = a;
nextInputB = b;
end
else begin
if ((inputA == inputB) & isDone == 0 & inputA > 0) begin
nextGcd = inputA << exponent;
nextIsDone = 1;
end
else begin
if ((inputA[0] == 0) & (inputB [0] == 0)) begin
nextExponent = exponent + 1;
nextInputA = inputA >> 1;
nextInputB = inputB >> 1;
end
else begin
nextExponent = exponent;
if (inputA[0] == 0) begin
nextInputA = inputA >> 1;
end
else begin
if (inputB[0] == 0) begin
nextInputB = inputB >> 1;
end
else begin
if (inputA > inputB) begin
nextInputA = (inputA - inputB) >> 1;
end
else begin
nextInputB = (inputB - inputA) >> 1;
end
end
end
end
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2005; bool can = 1; char arr[N][N]; int n, m, vis[N][N], dp[N][N]; bool valid(pair<int, int> a) { return min(a.first, a.second) > -1 && a.first < n && a.second < m && arr[a.first][a.second] != # ; } pair<int, int> get_next(pair<int, int> a) { if (arr[a.first][a.second] == < ) return {a.first, a.second - 1}; if (arr[a.first][a.second] == > ) return {a.first, a.second + 1}; if (arr[a.first][a.second] == ^ ) return {a.first - 1, a.second}; return {a.first + 1, a.second}; } void dfs(pair<int, int> u) { vis[u.first][u.second] = 1; pair<int, int> c = get_next(u); if (valid(c)) { if (vis[c.first][c.second] == 0) dfs(c); else if (vis[c.first][c.second] == 1) { can = 0; return; } } vis[u.first][u.second] = 2; } bool go(pair<int, int> u) { vis[u.first][u.second] = 1; pair<int, int> c = get_next(u); bool ret = 1; if (valid(c)) { if (vis[c.first][c.second] == 0) ret &= go(c); else ret = 0; } return ret; } int solve(pair<int, int> u) { if (!valid(u)) return 0; if (~dp[u.first][u.second]) return dp[u.first][u.second]; pair<int, int> c = get_next(u); return dp[u.first][u.second] = solve(c) + 1; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> m; memset(dp, -1, sizeof(dp)); for (int i = 0; i < n; ++i) for (int j = 0; j < m; ++j) cin >> arr[i][j]; for (int i = 0; i < n; ++i) for (int j = 0; j < m; ++j) if (!vis[i][j] && valid({i, j})) dfs({i, j}); if (can) { vector<pair<int, pair<int, int>>> v; for (int i = 0; i < n; ++i) for (int j = 0; j < m; ++j) v.push_back({solve({i, j}), {i, j}}); sort(v.rbegin(), v.rend()); if (v.size() == 1 || v[0].first == 0) cout << v[0].first; else { int ans1 = v[0].first, ans2 = v[0].first - 1; memset(vis, 0, sizeof(vis)); go(v[0].second); for (int i = 1; i < v.size(); ++i) { if (v[i].first < v[i - 1].first) break; if (go(v[i].second)) { ans2 = ans1; break; } } cout << ans1 + ans2; } } else cout << -1; return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 2e9; int n; pair<int, int> p[25]; int dis[25][25]; int dp[1 << 24 | 1]; int pre[1 << 24 | 1]; int main() { scanf( %d%d%d , &p[0].first, &p[0].second, &n); for (int i = 1; i <= n; ++i) { scanf( %d%d , &p[i].first, &p[i].second); } for (int i = 0; i <= n; ++i) for (int j = i; j <= n; ++j) { dis[i][j] = dis[j][i] = pow(p[i].first - p[j].first, 2) + pow(p[i].second - p[j].second, 2); } for (int m = 1; m < (1 << n); ++m) { dp[m] = INF; } dp[0] = 0; for (int m = 0; m < (1 << n); ++m) { if (dp[m] == INF) continue; for (int i = 1; i <= n; ++i) { if (m & 1 << (i - 1)) continue; for (int j = 1; j <= n; ++j) { if (m & 1 << (j - 1)) continue; if (dp[m | (1 << i - 1) | (1 << j - 1)] > dp[m] + dis[0][i] + dis[i][j] + dis[j][0]) { dp[m | (1 << i - 1) | (1 << j - 1)] = dp[m] + dis[0][i] + dis[i][j] + dis[j][0]; pre[m | (1 << i - 1) | (1 << j - 1)] = m; } } break; } } printf( %d n , dp[(1 << n) - 1]); int num = (1 << n) - 1; while (num) { printf( 0 ); int t = pre[num] ^ num; for (int i = 0; i < n; ++i) { if (t & (1 << i)) { printf( %d , i + 1); } } num = pre[num]; } printf( 0 n ); return 0; } |
#include <bits/stdc++.h> using namespace std; struct point { double x, y; point() { x = y = 0.0; } point(double A, double B) { x = A, y = B; } double operator*(point B) { return x * B.x + y * B.y; } point turn(double A) { return point(x * cos(A) - y * sin(A), y * cos(A) + x * sin(A)); } } zero, e, s, t; double ans, L1, L2, L3, L4, ev, ew, sv, r; double dis(point &A, point &B) { return sqrt(((B.x - A.x) * (B.x - A.x)) + ((B.y - A.y) * (B.y - A.y))); } bool check(double mid) { double A, B, C; t = e.turn(ew * mid); L2 = dis(t, zero); L4 = sqrt(((L2) * (L2)) - ((r) * (r))); C = acos(t * s / L1 / L2); A = acos(r / L1); B = acos(r / L2); if (A + B - C > 1e-8) { if (sv * mid - dis(s, t) > 1e-8) return true; return false; } else { C -= A + B; if (sv * mid - C * r - L3 - L4 > 1e-8) return true; return false; } } int main() { scanf( %lf%lf%lf , &e.x, &e.y, &ev); double R = dis(e, zero); ew = ev / R; scanf( %lf%lf%lf%lf , &s.x, &s.y, &sv, &r); L1 = dis(s, zero); L3 = sqrt(((L1) * (L1)) - ((r) * (r))); double l = 0, r = dis(s, e); while (r - l > 1e-8) { double mid = (l + r) / 2.0; if (check(mid)) ans = mid, r = mid; else l = mid; } printf( %lf n , ans); return 0; } |
///////////////////////////////////////////////////////////////////////////////
//
// Copyright 2010-2012 by Michael A. Morris, dba M. A. Morris & Associates
//
// All rights reserved. The source code contained herein is publicly released
// under the terms and conditions of the GNU Lesser Public License. No part of
// this source code may be reproduced or transmitted in any form or by any
// means, electronic or mechanical, including photocopying, recording, or any
// information storage and retrieval system in violation of the license under
// which the source code is released.
//
// The souce code contained herein is free; it may be redistributed and/or
// modified in accordance with the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either version 2.1 of
// the GNU Lesser General Public License, or any later version.
//
// The souce code contained herein is freely released WITHOUT ANY WARRANTY;
// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
// PARTICULAR PURPOSE. (Refer to the GNU Lesser General Public License for
// more details.)
//
// A copy of the GNU Lesser General Public License should have been received
// along with the source code contained herein; if not, a copy can be obtained
// by writing to:
//
// Free Software Foundation, Inc.
// 51 Franklin Street, Fifth Floor
// Boston, MA 02110-1301 USA
//
// Further, no use of this source code is permitted in any form or means
// without inclusion of this banner prominently in any derived works.
//
// Michael A. Morris
// Huntsville, AL
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
///////////////////////////////////////////////////////////////////////////////
// Company: M. A. Morris & Associates
// Engineer: Michael A. Morris
//
// Create Date: 19:48:02 07/10/2010
// Design Name: Fast 2-bit Booth Multiplier
// Module Name: Booth_Multiplier_2x.v
// Project Name: Booth_Multiplier
// Target Devices: Spartan-3AN
// Tool versions: Xilinx ISE 10.1 SP3
//
// Description:
//
// This module implements a parameterized multiplier which uses a Modified
// Booth algorithm for its implementation. The implementation is based on the
// algorithm described in "Computer Organization", Hamacher et al, McGraw-
// Hill Book Company, New York, NY, 1978, ISBN: 0-07-025681-0.
//
// Compared to the standard, 1-bit at a time Booth algorithm, this modified
// Booth multiplier algorithm shifts the multiplier 2 bits at a time. Thus,
// this algorithm will compute a 2's complement product twice as fast as the
// standard algorithm.
//
// Dependencies:
//
// Revision:
//
// 0.01 10G11 MAM File Created
//
// 1.00 10J06 MAM Corrected the sign extension/guards required to
// yield the correct product. Sign extension is needed
// to insure that carries from the least significant
// partial product propagate into the most significant
// partial products at each stage. Thus, the number
// of extra bits required is equal to 1 plus the shift
// required in the partial products. In this implemen-
// tation, the number of extra bits is 2: one for the
// sign and one for the shift (±2).
//
// 1.10 10J09 MAM Made correction to the parameterized equation for
// the Guard bit. The paramterization of Prod[pN-1]
// incorrect for a Booth Multiplier for a 2-bits at a
// time multiplier. The bit shifted into the Guard bit
// is always Prod[1]. Thus, the change was made. The
// parameterization works for pN == 2, but fails for
// values of pN greater than 2.
//
// 1.11 10J09 MAM Changed parameterization from a power of 2 to the
// number of bits representing the inputs. Allows the
// use of widths not representable as integer power of
// 2 such as 5. At present, the implementation does
// allow odd lengths for the inputs. To accomodate odd
// lengths an adjustment of the product register to
// the nearest even length is required. Also required
// is a compensation of the the output to account for
// the extra bit in the input. The number of cycles
// required for an odd length is the same that needed
// for the next larger even length since this imple-
// mentation is for multiplication 2 bits at a time.
//
// Additional Comments:
//
// The basic operations follow those of the standard Booth multiplier except
// that the transitions are being tracked across 2 bits plus the guard bit.
// The result is that the operations required are 0, ±1, and ±2 times the
// multiplicand (M). That is:
//
// Prod[2:0] Operation
// 000 Prod <= (Prod + 0*M) >> 2;
// 001 Prod <= (Prod + 1*M) >> 2;
// 010 Prod <= (Prod + 1*M) >> 2;
// 011 Prod <= (Prod + 2*M) >> 2;
// 100 Prod <= (Prod - 2*M) >> 2;
// 101 Prod <= (Prod - 1*M) >> 2;
// 110 Prod <= (Prod - 1*M) >> 2;
// 111 Prod <= (Prod - 0*M) >> 2;
//
// The operations in this table can be seen as direct extensions of the four
// conditions used in the standard Booth algorithm. The first and last terms
// simply indicate to skip over runs of 1s and 0s. The terms 001 and 110 are
// indicative of the 01 (+1) and 10 (-1) operations of the standard Booth al-
// gorithm. The terms 010 (+2,-1) and 101 (-2,+1) reduce to the operations
// noted in the table, namely ±1*M, respectively. The terms 011 (+2,0) and
// 100 (-2, 0) are the two new operations required for this modified Booth
// algorithm.
//
// The algorithm could be extended to any number of bits as required by noting
// that as more bits are added to the left, the number of terms (operations)
// required increases. Addding another bit, i.e. a 3-bit Booth recoding, means
// that the operations required of the adder/partial product are 0, ±1, ±2,
// and ±4. The guard bits provided for the sign bit accomodates the ±2 opera-
// tion required for the 2-bit modified booth algorithm. Adding a third bit
// means that a third guard bit will be required for the sign bit to insure
// that there is no overflow in the partial product when ±4 is the operation.
//
// A better implementation might be to consider implementing two simultaneous
// 2-bit partial products at a time, and combining the partial products after
// they are computed with an appropriate 2-bit shift in the rightmost partial
// product. This approach can be used to trade off complexity for speed. In
// the limit, this approach leads to the implementation of a parallel multi-
// plier. State-of-the-Art parallel multipliers are generally built in this
// manner, but they use arrays of small elements to compute the partial pro-
// ducts in a parallel manner. Typically these partial product generators are
// built around arrays of dual 2-bit inputs and 4-bit output adders with fast
// carry-propagate output carry generators.
//
///////////////////////////////////////////////////////////////////////////////
module Booth_Multiplier_2x #(
parameter N = 16 // Width = N: multiplicand & multiplier
)(
input Rst, // Reset
input Clk, // Clock
input Ld, // Load Registers and Start Multiplier
input [(N - 1):0] M, // Multiplicand
input [(N - 1):0] R, // Multiplier
output reg Valid, // Product Valid
output reg [((2*N) - 1):0] P // Product <= M * R
);
///////////////////////////////////////////////////////////////////////////////
//
// Local Parameters
//
localparam pNumCycles = ((N + 1)/2); // No. of cycles required for product
///////////////////////////////////////////////////////////////////////////////
//
// Declarations
//
reg [4:0] Cntr; // Operation Counter
reg [2:0] Booth; // Booth Recoding Field
reg Guard; // Shift Bit for Booth Recoding
reg [(N + 1):0] A; // Multiplicand w/ guards
reg [(N + 1):0] S; // Adder w/ guards
wire [(N + 1):0] Hi; // Upper Half of Product w/ guards
reg [((2*N) + 1):0] Prod; // Double Length Product w/ guards
///////////////////////////////////////////////////////////////////////////////
//
// Implementation
//
always @(posedge Clk)
begin
if(Rst)
Cntr <= #1 0;
else if(Ld)
Cntr <= #1 pNumCycles;
else if(|Cntr)
Cntr <= #1 (Cntr - 1);
end
// Multiplicand Register
// includes 2 bits to guard sign of multiplicand in the event the most
// negative value is provided as the input.
always @(posedge Clk)
begin
if(Rst)
A <= #1 0;
else if(Ld)
A <= #1 {{2{M[(N - 1)]}}, M};
end
// Compute Upper Partial Product: (N + 2) bits in width
always @(*) Booth <= {Prod[1:0], Guard}; // Booth's Multiplier Recoding fld
assign Hi = Prod[((2*N) + 1):N]; // Upper Half of the Product Register
always @(*)
begin
case(Booth)
3'b000 : S <= Hi; // Prod <= (Prod + 0*A) >> 2;
3'b001 : S <= Hi + A; // Prod <= (Prod + 1*A) >> 2;
3'b010 : S <= Hi + A; // Prod <= (Prod + 1*A) >> 2;
3'b011 : S <= Hi + {A, 1'b0}; // Prod <= (Prod + 2*A) >> 2;
3'b100 : S <= Hi - {A, 1'b0}; // Prod <= (Prod - 2*A) >> 2;
3'b101 : S <= Hi - A; // Prod <= (Prod - 1*A) >> 2;
3'b110 : S <= Hi - A; // Prod <= (Prod - 1*A) >> 2;
3'b111 : S <= Hi; // Prod <= (Prod - 0*A) >> 2;
endcase
end
// Double Length Product Register
// Multiplier, R, is loaded into the least significant half on load, Ld.
// Shifted right two places as the product is computed iteratively.
always @(posedge Clk)
begin
if(Rst)
Prod <= #1 0;
else if(Ld)
Prod <= #1 R;
else if(|Cntr) // Shift right two bits
Prod <= #1 {{2{S[(N + 1)]}}, S, Prod[(N - 1):2]};
end
always @(posedge Clk)
begin
if(Rst)
Guard <= #1 0;
else if(Ld)
Guard <= #1 0;
else if(|Cntr)
Guard <= #1 Prod[1];
end
// Assign the product less the two guard bits to the output port
// A double right shift is required since the output product is stored
// into a synchronous register on the last cycle of the multiply.
always @(posedge Clk)
begin
if(Rst)
P <= #1 0;
else if(Cntr == 1)
P <= #1 {S, Prod[(N - 1):2]};
end
// Count the number of shifts
// This implementation does not use any optimizations to perform multiple
// bit shifts to skip over runs of 1s or 0s.
always @(posedge Clk)
begin
if(Rst)
Valid <= #1 0;
else
Valid <= #1 (Cntr == 1);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long maxx = 1e6 + 7; const long long maxn = 1e6 + 7; const long long mod = 998244353; const long long maxs = 500000 + 7; const long long maxm = 400000 + 7; const long long maxk = 1008 + 7; const long long maxw = 100 + 7; const long long maxh = 100 + 7; const double pi = 3.1415926; const long long ten = 10; const long long ooi = 1000000; const long long ool = 1e18 + 7; const long double eps = 1e-8; const int apsz = 26; int seq[maxn]; int n; void init() { cin >> n; for (long long i = (1); i <= (n); i++) { cin >> seq[i]; } sort(seq + 1, seq + 1 + n); } void solve() { int ans = 0; int i = 1; int nowd = 1; while (i <= n) { while (i <= n && seq[i] < nowd) i++; if (i == n + 1) break; ans++; nowd++, i++; } cout << ans << endl; } int main(void) { ios::sync_with_stdio(false); cout.tie(0); cin.tie(0); init(); solve(); return 0; } |
//----------------------------------------------------------------------
// Title : Demo testbench
// Project : Virtex-5 Embedded Tri-Mode Ethernet MAC Wrapper
// File : configuration_tb.v
// Version : 1.8
//-----------------------------------------------------------------------------
//
// (c) Copyright 2004-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------
// Description: Management
//
// This testbench will control the speed settings of the
// EMAC block (if required) by driving the Tie-off vector.
//----------------------------------------------------------------------
`timescale 1ps / 1ps
module configuration_tb
(
reset,
//----------------------------------------------------------------
// Host Interface: host_clk is always required
//----------------------------------------------------------------
host_clk,
//----------------------------------------------------------------
// Test Bench Semaphores
//----------------------------------------------------------------
emac0_configuration_busy,
emac0_monitor_finished_1g,
emac0_monitor_finished_100m,
emac0_monitor_finished_10m,
emac1_configuration_busy,
emac1_monitor_finished_1g,
emac1_monitor_finished_100m,
emac1_monitor_finished_10m,
monitor_error_emac0
);
// port declarations
output reg reset;
output reg host_clk;
output reg emac0_configuration_busy;
input emac0_monitor_finished_1g;
input emac0_monitor_finished_100m;
input emac0_monitor_finished_10m;
output reg emac1_configuration_busy;
input emac1_monitor_finished_1g;
input emac1_monitor_finished_100m;
input emac1_monitor_finished_10m;
input monitor_error_emac0;
//--------------------------------------------------------------------
// HOSTCLK driver
//--------------------------------------------------------------------
// Drive HOSTCLK at one third the frequency of GTX_CLK
initial
begin
host_clk <= 1'b0;
#2000;
forever
begin
host_clk <= 1'b1;
#12000;
host_clk <= 1'b0;
#12000;
end
end
//------------------------------------------------------------------
// Testbench Configuration
//------------------------------------------------------------------
initial
begin : tb_configuration
$display("Timing checks are not valid");
reset <= 1'b1;
// test bench semaphores
emac0_configuration_busy <= 0;
emac1_configuration_busy <= 0;
#200000
emac0_configuration_busy <= 1;
emac1_configuration_busy <= 1;
// Reset the core
$display("Resetting the design...");
reset <= 1'b1;
#
reset <= 1'b0;
#200000
$display("Timing checks are valid");
#15000000
#100000
emac0_configuration_busy <= 0;
// wait for EMAC0 1Gb/s frames to complete
wait (emac0_monitor_finished_1g == 1);
#100000
if (monitor_error_emac0 == 1'b1)
begin
$display("*************************");
$display("ERROR: Simulation Failed.");
$display("*************************");
end
else begin
$display("****************************");
$display("PASS: Simulation Successful.");
$display("****************************");
end
// Our work here is done
$display("Simulation Complete.");
$stop;
end // tb_configuration
//------------------------------------------------------------------
// If the simulation is still going after 2 ms
// then something has gone wrong
//------------------------------------------------------------------
initial
begin : p_end_simulation
#
$display("** ERROR: Testbench timed out");
$stop;
end // p_end_simulation
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; long long a[n]; for (int i = 0; i < n; ++i) { cin >> a[i]; while (a[i] % 2 == 0) a[i] /= 2; while (a[i] % 3 == 0) a[i] /= 3; } int flag = 0; for (int i = 1; i < n; ++i) { if (a[i] != a[0]) { flag = 1; break; } } if (flag == 1) cout << NO ; else cout << YES ; } |
#include <bits/stdc++.h> using namespace std; long n, k, ar[200000]; long long reach[777777]; long long q; long long ans[777777]; multiset<long long> bst; multiset<long long>::iterator it; int main() { ios_base::sync_with_stdio(0); cin >> n >> k; for (int i = 1; i <= n; i++) cin >> ar[i]; reach[0] = 1; for (int i = 1; i <= 666666; i++) reach[i] = 0; for (int i = 1; i <= n; i++) for (int j = 555555; j + 1; --j) if (reach[j]) reach[j + ar[i]] = 1; ans[0] = 0; bst.insert(0); for (int i = 1; i <= 666666; i++) { ans[i] = 1e18; if (i > k && ans[i - k - 1] < 1e18) { it = bst.find(ans[i - k - 1]); bst.erase(it); } if (reach[i] == 0) continue; if (bst.size() == 0) continue; it = bst.begin(); q = (*it); ans[i] = q + 1; bst.insert(ans[i]); } q = 666666; while (ans[q] > 1e17) --q; cout << q << << ans[q] << endl; cin.get(); cin.get(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); string s1; cin >> s1; string s2; cin >> s2; string s3; cin >> s3; vector<pair<char, int> > cnt(26); for (int i = int(0); i < int(int(s1.size())); i++) { char c = s1[i]; int pos = tolower(c) - a ; cnt[pos].second += 0; cnt[pos].first = c; } for (int i = int(0); i < int(int(s2.size())); i++) { char c = s2[i]; int pos = tolower(c) - a ; cnt[pos].second += 0; cnt[pos].first = c; } for (int i = int(0); i < int(int(s3.size())); i++) { char c = s3[i]; int pos = tolower(c) - a ; cnt[pos].second += 1; cnt[pos].first = c; } for (int i = int(0); i < int(int(s1.size())); i++) { for (int j = int(0); j < int(26); j++) { if (s1[i] == cnt[j].first) { cnt[j].second -= 1; } } } for (int i = int(0); i < int(int(s2.size())); i++) { for (int j = int(0); j < int(26); j++) { if (s2[i] == cnt[j].first) { cnt[j].second -= 1; } } } for (int i = int(0); i < int(26); i++) { if (cnt[i].second < 0 || cnt[i].second > 0) { cout << NO ; return 0; } } cout << YES ; } |
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact :
//-------------------------------------------------------------------
// Filename : md_ram.v
// Author : Yanheng Lu
// Created : 2014-09-01
// Description : mode decision(pre_intra) 8x8 ram
//------------------------------------------------------------------
module md_ram (
clk ,
wdata ,
waddr ,
we ,
rd ,
raddr ,
rdata
);
// ********************************************
//
// Input/Output DECLARATION
//
// ********************************************
input clk ;
input [31:0] wdata ;
input [3:0] waddr ;
input we ;
input rd ;
input [3:0] raddr ;
output [31:0] rdata ;
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
rf_2p #(.Addr_Width(4), .Word_Width(32))
rf_2p_32x16 (
.clka ( clk ),
.cena_i ( ~rd ),
.addra_i ( raddr ),
.dataa_o ( rdata ),
.clkb ( clk ),
.cenb_i ( ~we ),
.wenb_i ( ~we ),
.addrb_i ( waddr ),
.datab_i ( wdata )
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_PP_BLACKBOX_V
/**
* lpflow_isobufsrckapwr: Input isolation, noninverted sleep on
* keep-alive power rail.
*
* X = (!A | SLEEP)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_isobufsrckapwr (
X ,
SLEEP,
A ,
KAPWR,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input SLEEP;
input A ;
input KAPWR;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; void hi() { static long long i = 0; cout << Check Point : << ++i << n ; return; } signed main() { ios::sync_with_stdio(0); cin.tie(0); long long t; t = 1; while (t--) { string str; cin >> str; long long n = str.length(); stack<char> stk; for (long long i = 0; i < n; i++) { if (!stk.empty() && ((stk.top() == + && str[i] == + ) || ((stk.top() == - && str[i] == - )))) { stk.pop(); } else { stk.push(str[i]); } } if (stk.empty()) { cout << Yes << n ; } else { cout << No << n ; } } return 0; } |
// This tests SystemVerilog casting support
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
// Extended by Maciej Suminski
module test();
// variables used in casting
byte var_08;
shortint var_16;
int var_32;
longint var_64;
real var_real;
// error counter
bit err = 0;
initial begin
var_08 = byte'(4'sh5); if (var_08 != 8'sh05) begin $display("FAILED -- var_08 = 'h%0h != 8'h05", var_08); err=1; end
var_16 = shortint'(var_08); if (var_16 != 16'sh05) begin $display("FAILED -- var_16 = 'h%0h != 16'h05", var_16); err=1; end
var_32 = int'(var_16); if (var_32 != 32'sh05) begin $display("FAILED -- var_32 = 'h%0h != 32'h05", var_32); err=1; end
var_64 = longint'(var_32); if (var_64 != 64'sh05) begin $display("FAILED -- var_64 = 'h%0h != 64'h05", var_64); err=1; end
var_real = 13.4; var_08 = byte'(var_real); if (var_08 != 13) begin $display("FAILED -- var_08 = %d != 13", var_08); err=1; end
var_real = 14.5; var_16 = shortint'(var_real); if (var_16 != 15) begin $display("FAILED -- var_16 = %d != 15", var_16); err=1; end
var_real = 15.6; var_32 = int'(var_real); if (var_32 != 16) begin $display("FAILED -- var_32 = %d != 16", var_32); err=1; end
var_real = -15.6; var_64 = longint'(var_real); if (var_64 != -16) begin $display("FAILED -- var_64 = %d != -16", var_64); err=1; end
if (!err) $display("PASSED");
end
endmodule // test
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O211A_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__O211A_PP_BLACKBOX_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o211a (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O211A_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long ans, heavy; string s; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> s; for (int i = 0; i <= (int)s.size() - 5; i++) { if (s.substr(i, 5) == heavy ) { heavy++; } else if (s.substr(i, 5) == metal ) { ans += heavy; } } cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, pos, ans = 10000000000000000; long long a[3000 + 5], b[3000 + 5], f[3000 + 5][3000 + 5], Min[3000 + 5]; long long read() { char c; long long x = 0, f = 1; c = getchar(); while (c > 9 || c < 0 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = (x << 3) + (x << 1) + c - 0 ; c = getchar(); } return x * f; } signed main() { n = read(); for (register long long i = 1; i <= n; ++i) a[i] = read() - i, b[i] = a[i]; sort(b + 1, b + n + 1); pos = unique(b + 1, b + n + 1) - b - 1; for (register long long i = 1; i <= n; ++i) { for (register long long j = 1; j <= pos; ++j) f[i][j] = Min[j] + abs(a[i] - b[j]); Min[0] = 10000000000000000; for (register long long j = 1; j <= pos; ++j) Min[j] = min(Min[j - 1], f[i][j]); } for (register long long i = 1; i <= pos; ++i) ans = min(ans, f[n][i]); printf( %lld , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; long long inf = 2147483647; const long long ll = 9223372036854775807, ninf = 1000000000; const double eps = 1e-6; const long long nll = 1000000000000000000; vector<int> node[200005]; vector<int> num; int deg[200005] = {}; void dfs(int x) { for (int i = 0; i < node[x].size(); i++) { dfs(node[x][i]); } num.push_back(x); } int A[200005] = {}; int main() { int a; while (cin >> a) { int r = 1; for (int i = 1; i <= a; i++) { cin >> A[i]; deg[A[i]]++; if (A[i]) { deg[i]++; node[A[i]].push_back(i); } else { r = i; } } if (a % 2 == 0) { cout << NO << n ; continue; } dfs(r); vector<int> ans1, ans2; cout << YES << n ; for (int i = 0; i < num.size(); i++) { int now = num[i]; if (deg[now] % 2 == 0) { ans2.push_back(now); deg[A[now]]--; } else { ans1.push_back(now); } } for (int i = 0; i < ans2.size(); i++) { cout << ans2[i] << n ; } reverse(ans1.begin(), ans1.end()); for (int i = 0; i < ans1.size(); i++) { cout << ans1[i] << n ; } } return 0; } |
/*
*
* Copyright (c) 2013
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
/* Calculates the hash of the given public key.
* Will use the compressed public key.
*/
module address_hash (
input clk,
input rx_reset,
input [255:0] rx_x,
input [255:0] rx_y,
output tx_done,
output [159:0] tx_hash
);
reg ripe_reset = 1'b1;
wire sha_done;
wire [255:0] sha_hash;
sha256 sha256_blk (
.clk (clk),
.rx_reset (rx_reset),
.rx_public_key ({7'h1, rx_y[0], rx_x}),
.tx_done (sha_done),
.tx_hash (sha_hash)
);
ripemd160 ripemd160_blk (
.clk (clk),
.rx_reset (rx_reset | ripe_reset),
.rx_hash (sha_hash),
.tx_done (tx_done),
.tx_hash (tx_hash)
);
always @ (posedge clk)
begin
if (rx_reset)
ripe_reset <= 1'b1;
else if (sha_done)
ripe_reset <= 1'b0;
end
endmodule
|
// 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9
// 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0
//----------------------------------------------------------------------------------------
//
// The MIT License (MIT)
// Copyright (c) 2016 Enrique Sedano ()
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this
// software and associated documentation files (the "Software"), to deal in the Software
// without restriction, including without limitation the rights to use, copy, modify,
// merge, publish, distribute, sublicense, and/or sell copies of the Software, and to
// permit persons to whom the Software is furnished to do so, subject to the following
// conditions:
//
// The above copyright notice and this permission notice shall be included in all copies
// or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
// PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
// CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
// OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
//
//----------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------
//
// This module is a member of
// ____ __
// _ __/ __ \__ ______/ /_ __
// | | / / /_/ / / / / __ / / / /
// | |/ / _, _/ /_/ / /_/ / /_/ /
// |___/_/ |_|\__,_/\__,_/\__, /
// /____/ v 0.0 - Development
//
// Module: dpth_regfile.v
// Version: 1.0
// Description:
// Register file.
//----------------------------------------------------------------------------------------
`include "defines.vh"
module dpth_regfile (
//------------------------------
// Top level control signals
//------------------------------
input wire clk,
//------------------------------
// Input data
//------------------------------
input wire [2:0] rd_at,
input wire [2:0] wr_at,
input wire wr_en,
input wire [`REG_BITS] din,
//------------------------------
// Output data
//------------------------------
output wire [`REG_BITS] dout
);
reg [`REG_BITS] data [2:0];
always @(posedge clk)
begin
if (wr_en == 1'b1)
data[wr_at] <= din;
end
assign dout = data[rd_at];
endmodule
//----------------------------------------------------------------------------------------
// Trivia:
//----------------------------------------------------------------------------------------
// 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9
// 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> a(n + n - 1); int sum = 0; for (int i = 0; i < n + n - 1; i++) { cin >> a[i]; sum += a[i]; } sort(a.begin(), a.end()); for (int i = 0; i < n + n - 2; i += 2) { if (a[i] < 0 && a[i + 1] < 0) { sum -= a[i] + a[i]; sum -= a[i + 1] + a[i + 1]; a[i] = -a[i]; a[i + 1] = -a[i + 1]; } else if (a[i] < 0) { if (-a[i] > a[i + 1]) { sum -= a[i] + a[i]; sum -= a[i + 1] + a[i + 1]; a[i] = -a[i]; a[i + 1] = -a[i + 1]; } } else { break; } } if (n % 2) { sort(a.begin(), a.end()); if (a[0] < 0) { sum -= a[0] + a[0]; } } cout << sum << endl; return 0; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_ddr_impctl_pulldown.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_ddr_impctl_pulldown(tclk ,ctu_global_snap ,ctu_io_sscan_in
,ctu_io_sscan_se ,ctu_io_sscan_update ,ctu_io_sscan_out ,rclk ,z ,
deltabit ,hard_reset_n ,clk_dis_l ,from_csr ,we_csr ,si ,se ,vdd18
,pad ,to_csr ,so );
output [7:0] z ;
output [7:0] to_csr ;
input [7:0] from_csr ;
output ctu_io_sscan_out ;
output deltabit ;
output so ;
input tclk ;
input ctu_global_snap ;
input ctu_io_sscan_in ;
input ctu_io_sscan_se ;
input ctu_io_sscan_update ;
input rclk ;
input hard_reset_n ;
input clk_dis_l ;
input we_csr ;
input si ;
input se ;
input vdd18 ;
inout pad ;
supply1 vdd ;
supply0 vss ;
wire [7:0] z_post ;
wire [7:0] d ;
wire [7:0] net67 ;
wire clk ;
wire net087 ;
wire above ;
wire global_reset_n ;
wire sodr_l ;
wire sodr ;
wire sos_l ;
wire bypass ;
wire oe_out ;
wire net057 ;
wire updclk ;
wire clk_en_l ;
wire sclk ;
wire net083 ;
wire avgcntr_rst ;
bw_u1_nand2_4x I28_1_ (
.z (net67[6] ),
.b (z_post[2] ),
.a (z_post[1] ) );
bw_u1_inv_10x I29_7_ (
.z (z[7] ),
.a (net67[0] ) );
bw_u1_inv_10x I29_0_ (
.z (z[0] ),
.a (net67[7] ) );
bw_u1_nand2_4x I28_2_ (
.z (net67[5] ),
.b (z_post[3] ),
.a (z_post[2] ) );
bw_io_impctl_ddr_dnrcn I241 (
.cbd ({d } ),
.si (si ),
.vdd18 (vdd18 ),
.so (sodr ),
.pad (pad ),
.sclk (sclk ),
.oe (oe_out ),
.above (above ),
.clk (clk ),
.se (se ),
.global_reset_n (global_reset_n ) );
bw_u1_inv_10x I29_1_ (
.z (z[1] ),
.a (net67[6] ) );
bw_u1_nand2_4x I28_3_ (
.z (net67[4] ),
.b (z_post[4] ),
.a (z_post[3] ) );
bw_u1_inv_10x I29_2_ (
.z (z[2] ),
.a (net67[5] ) );
bw_u1_nand2_4x I28_4_ (
.z (net67[3] ),
.b (z_post[5] ),
.a (z_post[4] ) );
bw_u1_inv_10x I29_3_ (
.z (z[3] ),
.a (net67[4] ) );
bw_u1_nand2_4x I28_5_ (
.z (net67[2] ),
.b (z_post[6] ),
.a (z_post[5] ) );
bw_u1_inv_8x I21 (
.z (so ),
.a (net083 ) );
bw_io_impctl_clkgen I24 (
.se (se ),
.oe_out (oe_out ),
.updclk (updclk ),
.so_l (net083 ),
.si_l (sos_l ),
.clk (clk ), /// changed from rclk
.synced_upd_imped (ctu_io_sscan_update ),
.bypass (bypass ),
.global_reset_n (global_reset_n ),
.hard_reset_n (hard_reset_n ),
.sclk (sclk ),
.reset_l (vdd ),
.avgcntr_rst (avgcntr_rst ) );
bw_u1_inv_10x I29_4_ (
.z (z[4] ),
.a (net67[3] ) );
bw_u1_nand2_4x I28_6_ (
.z (net67[1] ),
.b (z_post[7] ),
.a (z_post[6] ) );
bw_u1_ckenbuf_6x I30 (
.clk (clk ),
.rclk (rclk ),
.en_l (clk_en_l ),
.tm_l (net087 ) );
bw_u1_inv_4x I32 (
.z (sodr_l ),
.a (sodr ) );
bw_io_impctl_smachine_new I33 (
.z_post ({z_post } ),
.from_csr ({from_csr } ),
.to_csr ({to_csr } ),
.d ({d } ),
.deltabit (deltabit ),
.ctu_io_sscan_se (ctu_io_sscan_se ),
.updclk (updclk ),
.we_csr (we_csr ),
.l2clk (rclk ),
.ctu_io_sscan_in (ctu_io_sscan_in ),
.above (above ),
.bypass (bypass ),
.config_pmos (vss ),
.global_reset_n (global_reset_n ),
.hard_reset_n (hard_reset_n ),
.ctu_global_snap (ctu_global_snap ),
.sclk (sclk ),
.avgcntr_rst (avgcntr_rst ),
.so (net057 ),
.se (se ),
.si_l (sodr_l ),
.io_ctu_sscan_out (net077 ),
.tclk (tclk ),
.ctu_io_sscan_update (ctu_io_sscan_update ),
.clk_en_l (clk_en_l ) );
bw_u1_scanl_2x I153 (
.sd (net077 ),
.ck (tclk ),
.so (ctu_io_sscan_out ) );
bw_u1_inv_10x I29_5_ (
.z (z[5] ),
.a (net67[2] ) );
bw_u1_nand2_4x I28_7_ (
.z (net67[0] ),
.b (deltabit ),
.a (z_post[7] ) );
bw_u1_inv_10x I46 (
.z (clk_en_l ),
.a (clk_dis_l ) );
bw_u1_inv_4x I48 (
.z (net087 ),
.a (se ) );
bw_u1_inv_4x I49 (
.z (sos_l ),
.a (net057 ) );
bw_u1_nand2_4x I28_0_ (
.z (net67[7] ),
.b (z_post[1] ),
.a (z_post[0] ) );
bw_u1_inv_10x I29_6_ (
.z (z[6] ),
.a (net67[1] ) );
endmodule
|
#include <bits/stdc++.h> using namespace std; int mod; struct EDGE { int to, nxt; } box[101000 * 2]; int h[101000], top, f1[101000], f2[101000]; void add(int u, int v) { box[top].to = v; box[top].nxt = h[u]; h[u] = top++; } int dp[610][610]; int dfs(int a, int b) { if (dp[a][b] + 1) return dp[a][b]; int p = h[a]; dp[a][b] = 0; while (p != -1) { dp[a][b] = (dp[a][b] + dfs(box[p].to, b)) % mod; p = box[p].nxt; } return dp[a][b]; } long long ni(long long i) { int n = mod - 2; long long res = 1; while (n) { if (n & 1) res = res * i % mod; i = i * i % mod; n >>= 1; } return res; } int ss[610], sn[610], c1, c2; int mat[610][610]; int main() { int n, m; scanf( %d%d%d , &n, &m, &mod); memset(dp, -1, sizeof(dp)); memset(h, -1, sizeof(h)); for (int i = 1; i <= m; i++) { int a, b; scanf( %d%d , &a, &b); f1[a] = 1; f2[b] = 1; add(a, b); } for (int i = 1; i <= n; i++) dp[i][i] = 1; for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if (dp[i][j] == -1) dfs(i, j); } } for (int i = 1; i <= n; i++) { if (!f1[i]) sn[c1++] = i; if (!f2[i]) ss[c2++] = i; } for (int i = 0; i < c1; i++) { for (int j = 0; j < c1; j++) { mat[i][j] = dp[ss[i]][sn[j]]; } } long long ans = 1; for (int j = 0; j < c1; j++) { int r; for (r = j; r < c1; r++) { if (mat[r][j]) break; } if (r == c1) { ans = 0; break; } for (int k = j; k < c1; k++) swap(mat[j][k], mat[r][k]); if (r != j) ans = -ans; for (int i = 0; i < c1; i++) { if (i == j) continue; long long a = mat[i][j], b = mat[j][j]; for (int k = 0; k < c1; k++) { mat[i][k] = (mat[i][k] * b - mat[j][k] * a) % mod; } ans = ans * ni(b) % mod; } } for (int i = 0; i < c1; i++) ans = (ans * mat[i][i]) % mod; printf( %I64d n , (ans + mod) % mod); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O211A_BLACKBOX_V
`define SKY130_FD_SC_HDLL__O211A_BLACKBOX_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o211a (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O211A_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; struct edge { long long a, b, w, ind; }; const int LEN = 100100; const long long INF = 100000000000000; int n, m, s, t, use[LEN], use1[LEN], ans[LEN], timer, tin[LEN], fup[LEN]; vector<edge> ar[LEN], ar1[LEN], ar2[LEN]; edge ed[LEN]; long long dist[LEN], dist1[LEN], min_dist, a, b, l; set<pair<long long, int> > q; void deixtra(long long (&dist)[LEN], vector<edge> (&ar)[LEN], int s); void get_gate(int v, int ind); int main() { scanf( %i %i %i %i , &n, &m, &s, &t); s--; t--; for (int i = 0; i < m; i++) { scanf( %I64d %I64d %I64d , &a, &b, &l); ed[i].w = l; ed[i].ind = i; ed[i].a = b - 1; ed[i].b = a - 1; ar1[b - 1].push_back(ed[i]); swap(ed[i].a, ed[i].b); ar[a - 1].push_back(ed[i]); } deixtra(dist, ar, s); deixtra(dist1, ar1, t); min_dist = dist[t]; for (int i = 0; i < m; i++) if (dist[ed[i].a] + ed[i].w + dist1[ed[i].b] == min_dist) { ar2[ed[i].a].push_back(ed[i]); swap(ed[i].a, ed[i].b); ar2[ed[i].a].push_back(ed[i]); swap(ed[i].a, ed[i].b); } get_gate(t, -1); for (int i = 0; i < m; i++) if (ans[i]) printf( YES n ); else if (dist[ed[i].a] + ed[i].w + dist1[ed[i].b] - min_dist + 1 < ed[i].w) printf( CAN %I64d n , dist[ed[i].a] + ed[i].w + dist1[ed[i].b] - min_dist + 1); else printf( NO n ); return 0; } void deixtra(long long (&dist)[LEN], vector<edge> (&ar)[LEN], int s) { int x, to, len; pair<long long, int> u; for (int i = 0; i < n; i++) dist[i] = INF; dist[s] = 0; q.insert(make_pair(0, s)); while (!q.empty()) { x = q.begin()->second; q.erase(q.begin()); for (int i = 0; i < ar[x].size(); i++) { to = ar[x][i].b; len = ar[x][i].w; if (dist[to] > dist[x] + len) { q.erase(make_pair(dist[to], to)); dist[to] = dist[x] + len; q.insert(make_pair(dist[to], to)); } } } } void get_gate(int v, int ind) { int u; tin[v] = fup[v] = timer++; use1[v] = 1; for (int i = 0; i < ar2[v].size(); i++) { if (ar2[v][i].ind == ind) continue; u = ar2[v][i].b; if (use1[u]) fup[v] = min(fup[v], tin[u]); else { get_gate(u, ar2[v][i].ind); fup[v] = min(fup[v], fup[u]); if (fup[u] > tin[v]) ans[ar2[v][i].ind] = 1; } } } |
#include <bits/stdc++.h> using namespace std; int main() { int a[3], b[3]; int k, d; cin >> a[0] >> a[1] >> a[2] >> k; for (int i = 0; i < 3; i++) { a[i]--; b[i] = 0; } sort(a, a + 3); for (int i = 0; i < 3; i++) { d = k / (3 - i); for (int j = i; j < 3; j++) { int t = min(a[i], d); b[j] += t; a[j] -= t; k -= t; if (d % (3 - i) > j && a[j]) { k--; b[j]++; a[j]--; } } } cout << (long long)(b[0] + 1) * (b[1] + 1) * (b[2] + 1); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__HA_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__HA_PP_BLACKBOX_V
/**
* ha: Half adder.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__ha (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__HA_PP_BLACKBOX_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21.02.2016 16:25:28
// Design Name:
// Module Name: SPI_SLAVE
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SPI_SLAVE#
(
parameter integer m = 15 // Data packet size
)
(
input wire RST,
input wire GCLK,
input wire SCLK,
output wire MISO,
input wire MOSI,
input wire SS,
input wire [m-1:0] DIN,
output reg [m-1:0] DOUT
);
reg [m-1:0] RXSHIFT = 0;
reg [m-1:0] TXSHIFT = 0;
reg in_progress = 1'b0;
assign MISO = TXSHIFT[m-1];
wire foo;
assign foo = SCLK | SS;
always @(negedge foo) begin
if (in_progress == 1'b1) begin
TXSHIFT <= TXSHIFT<<1;
end
else begin
TXSHIFT <= DIN;
end
end
always @(posedge GCLK) begin
in_progress <= (SS == 1'b1) ? 1'b0 : 1'b1;
end
always @(posedge SS) begin
DOUT <= (RST == 1'b1) ? 0 : RXSHIFT;
end
always @(posedge SCLK) begin
RXSHIFT <= (SS == 1'b1) ? 0 : RXSHIFT<<1 | MOSI;
end
endmodule |
#include <bits/stdc++.h> using namespace std; int l[50000]; int p[50000]; pair<pair<double, int>, int> prod[50000]; int main() { std::ios_base::sync_with_stdio(false); int n; cin >> n; for (int i = 0; i < n; i++) { cin >> l[i] >> p[i]; if (p[i] == 100) prod[i].first.first = -1000000000; else prod[i].first.first = -l[i] * p[i] * 1.0 / (100 - p[i]); prod[i].first.second = p[i]; prod[i].second = i; } sort(prod, prod + n); double F = l[prod[0].second] * p[prod[0].second] / 100.0; double E = l[prod[0].second]; for (int i = 1; i < n; i++) { E = E + l[prod[i].second] + (1 - p[prod[i].second] / 100.0) * F; F += p[prod[i].second] / 100.0 * l[prod[i].second]; } cout << setprecision(25) << E << endl; return 0; } |
// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29441 $
// $Date: 2012-08-27 21:58:03 +0000 (Mon, 27 Aug 2012) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
// Depth 2 FIFO
module FIFO2(CLK,
RST,
D_IN,
ENQ,
FULL_N,
D_OUT,
DEQ,
EMPTY_N,
CLR);
parameter width = 1;
parameter guarded = 1;
input CLK ;
input RST ;
input [width - 1 : 0] D_IN;
input ENQ;
input DEQ;
input CLR ;
output FULL_N;
output EMPTY_N;
output [width - 1 : 0] D_OUT;
reg full_reg;
reg empty_reg;
reg [width - 1 : 0] data0_reg;
reg [width - 1 : 0] data1_reg;
assign FULL_N = full_reg ;
assign EMPTY_N = empty_reg ;
assign D_OUT = data0_reg ;
// Optimize the loading logic since state encoding is not power of 2!
wire d0di = (ENQ && ! empty_reg ) || ( ENQ && DEQ && full_reg ) ;
wire d0d1 = DEQ && ! full_reg ;
wire d0h = ((! DEQ) && (! ENQ )) || (!DEQ && empty_reg ) || ( ! ENQ &&full_reg) ;
wire d1di = ENQ & empty_reg ;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
data0_reg = {((width + 1)/2) {2'b10}} ;
data1_reg = {((width + 1)/2) {2'b10}} ;
empty_reg = 1'b0;
full_reg = 1'b1;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
always@(posedge CLK /* or `BSV_RESET_EDGE RST */)
begin
if (RST == `BSV_RESET_VALUE)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end // if (RST == `BSV_RESET_VALUE)
else
begin
if (CLR)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end // if (CLR)
else if ( ENQ && ! DEQ ) // just enq
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
full_reg <= `BSV_ASSIGNMENT_DELAY ! empty_reg ;
end
else if ( DEQ && ! ENQ )
begin
full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
empty_reg <= `BSV_ASSIGNMENT_DELAY ! full_reg;
end // if ( DEQ && ! ENQ )
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
always@(posedge CLK /* or `BSV_RESET_EDGE RST */ )
begin
// Following section initializes the data registers which
// may be desired only in some situations.
// Uncomment to initialize array
/*
if (RST == `BSV_RESET_VALUE)
begin
data0_reg <= `BSV_ASSIGNMENT_DELAY {width {1'b0}} ;
data1_reg <= `BSV_ASSIGNMENT_DELAY {width {1'b0}} ;
end
else
*/
begin
data0_reg <= `BSV_ASSIGNMENT_DELAY
{width{d0di}} & D_IN | {width{d0d1}} & data1_reg | {width{d0h}} & data0_reg ;
data1_reg <= `BSV_ASSIGNMENT_DELAY
d1di ? D_IN : data1_reg ;
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if (RST == ! `BSV_RESET_VALUE)
begin
if ( ! empty_reg && DEQ )
begin
deqerror = 1;
$display( "Warning: FIFO2: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! full_reg && ENQ && (!DEQ || guarded) )
begin
enqerror = 1;
$display( "Warning: FIFO2: %m -- Enqueuing to a full fifo" ) ;
end
end
end // always@ (posedge CLK)
// synopsys translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); long long n; cin >> n; vector<pair<long long, long long>> a((size_t)n); for (long long i = 0; i < n; i++) { cin >> a[i].first; a[i].second = i; } sort(a.rbegin(), a.rend()); vector<long long> b((size_t)n); for (long long i = 0; i < n; i++) { b[i] = a[i].second * 2; if (i >= 1) { cout << b[i - 1] + 1 << << b[i] + 1 << n ; } } for (long long i = 0; i < n; i++) { cout << a[i].second * 2 + 1 + 1 << << b[i + a[i].first - 1] + 1 << n ; if (i + a[i].first - 1 == (long long)b.size() - 1) { b.push_back(a[i].second * 2 + 1); } } return 0; } |
/*
########################################################################
MASTER ENABLE, CLOCKS, CHIP-ID
########################################################################
*/
`include "elink_regmap.v"
module ecfg_elink (/*AUTOARG*/
// Outputs
txwr_gated_access, etx_soft_reset, erx_soft_reset, clk_config,
chipid,
// Inputs
clk, por_reset, txwr_access, txwr_packet
);
parameter RFAW = 6; // 32 registers for now
parameter PW = 104; // 32 registers for now
parameter ID = 12'h000;
parameter DEFAULT_CHIPID = 12'h808;
/******************************/
/*Clock/reset */
/******************************/
input clk;
input por_reset; // POR "hard reset"
/******************************/
/*REGISTER ACCESS */
/******************************/
input txwr_access;
input [PW-1:0] txwr_packet;
/******************************/
/*FILTERED WRITE FOR TX FIFO */
/******************************/
output txwr_gated_access;
/******************************/
/*Outputs */
/******************************/
output etx_soft_reset; // tx soft reset (level)
output erx_soft_reset; // rx soft reset (level)
output [15:0] clk_config; // clock settings (for pll)
output [11:0] chipid; // chip-id for Epiphany
/*------------------------CODE BODY---------------------------------------*/
//registers
reg [1:0] ecfg_reset_reg;
reg [15:0] ecfg_clk_reg;
reg [11:0] ecfg_chipid_reg;
reg [31:0] mi_dout;
//wires
wire ecfg_read;
wire ecfg_write;
wire ecfg_clk_write;
wire ecfg_chipid_write;
wire ecfg_reset_write;
wire mi_en;
wire [31:0] mi_addr;
wire [31:0] mi_din;
packet2emesh pe2 (
// Outputs
.access_out (),
.write_out (mi_we),
.datamode_out (),
.ctrlmode_out (),
.dstaddr_out (mi_addr[31:0]),
.data_out (mi_din[31:0]),
.srcaddr_out (),
// Inputs
.packet_in (txwr_packet[PW-1:0])
);
/*****************************/
/*ADDRESS DECODE LOGIC */
/*****************************/
assign mi_en = txwr_access &
(mi_addr[31:20]==ID) &
(mi_addr[10:8]==3'h2);
//read/write decode
assign ecfg_write = mi_en & mi_we;
assign ecfg_read = mi_en & ~mi_we;
//Config write enables
assign ecfg_reset_write = ecfg_write & (mi_addr[RFAW+1:2]==`E_RESET);
assign ecfg_clk_write = ecfg_write & (mi_addr[RFAW+1:2]==`E_CLK);
assign ecfg_chipid_write = ecfg_write & (mi_addr[RFAW+1:2]==`E_CHIPID);
/*****************************/
/*FILTER ACCESS */
/*****************************/
assign txwr_gated_access = txwr_access & ~(ecfg_reset_write |
ecfg_clk_write |
ecfg_chipid_write);
//###########################
//# RESET REG (ASYNC)
//###########################
always @ (posedge clk or posedge por_reset)
if(por_reset)
ecfg_reset_reg[1:0] <= 'b0;
else if (ecfg_reset_write)
ecfg_reset_reg[1:0] <= mi_din[1:0];
assign etx_soft_reset = ecfg_reset_reg[0];
assign erx_soft_reset = ecfg_reset_reg[1];
//###########################
//# CCLK/LCLK (PLL)
//###########################
//TODO: implement!
always @ (posedge clk or posedge por_reset)
if(por_reset)
ecfg_clk_reg[15:0] <= 16'h573;//all clocks on at lowest speed
else if (ecfg_clk_write)
ecfg_clk_reg[15:0] <= mi_din[15:0];
assign clk_config[15:0] = ecfg_clk_reg[15:0];
//###########################
//# CHIPID
//###########################
always @ (posedge clk or posedge por_reset)
if(por_reset)
ecfg_chipid_reg[11:0] <= DEFAULT_CHIPID;
else if (ecfg_chipid_write)
ecfg_chipid_reg[11:0] <= mi_din[11:0];
assign chipid[11:0]=ecfg_chipid_reg[5:2];
endmodule // ecfg_elink
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
module sram_ctrl_a(
input clk,
input clr,
input go,
input halt,
output reg we,
output [17:0] sram_addr,
output [2:0] pattern,
output reg en
);
reg[2:0] state;
parameter START = 4'b0000, ADDROUT = 4'b0001, DATAOUT = 4'b0010,
WRITE = 4'b0011, TEST1 = 4'b0100, WAIT_AND_GO = 4'b0101, READ = 4'b0110,
TEST2 = 4'b0111, HALT = 4'b1000;
reg [17:0] addrv;
reg [2:0] patternv;
assign sram_addr = addrv;
assign pattern = patternv;
always @(posedge clk or posedge clr)
begin
if (clr == 1)
begin
state <= START;
addrv = 0;
patternv = 0;
we <= 1;
en <= 0;
end
else
case(state)
START:
begin
we <= 1;
if (go == 1)
begin
addrv = 0;
en <= 1;
state <= ADDROUT;
end
else
state <= START;
end
ADDROUT:
begin
state <= DATAOUT;
we <= 1;
end
DATAOUT:
begin
state <= WRITE;
we <= 0;
end
WRITE:
begin
state <= TEST1;
we <= 1;
end
TEST1:
begin
we <= 1;
if (halt == 1)
state <= HALT;
else
begin
addrv = addrv + 1;
if (addrv == 0)
begin
state <= WAIT_AND_GO;
en <= 0;
end
else
state <= ADDROUT;
end
end
WAIT_AND_GO:
begin
we <= 1;
if (go == 1)
state <= WAIT_AND_GO;
else
state <= READ;
end
READ:
begin
we <= 1;
if (go == 1)
begin
state <= TEST2;
addrv = addrv + 1;
end
else
state <= READ;
end
TEST2:
begin
we <= 1;
if (addrv == 0)
begin
patternv = patternv + 1;
state <= START;
end
else
state <= WAIT_AND_GO;
end
HALT:
begin
state <= HALT;
end
default;
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRTN_PP_SYMBOL_V
`define SKY130_FD_SC_MS__DLRTN_PP_SYMBOL_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlrtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE_N ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRTN_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 5e5 + 5; int n, k, a[maxn], b[maxn]; void work(long long g); long long as, ct; int main() { scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) scanf( %d , a + i); for (int i = 1; i <= n; i++) scanf( %d , b + i); long long l = 0, r = 1e12, mid, ot; while (l < r) { work(mid = l + r >> 1); if (ct >= k) r = mid, ot = mid; else l = mid + 1; } work(ot), printf( %lld n , as + 2 * k * ot); return 0; } void work(long long g) { priority_queue<pair<long long, int> > q; as = ct = 0; long long tp; for (int i = 1; i <= n; i++) { q.push({g - a[i], 1}); if ((tp = b[i] - q.top().first - g) <= 0) { as += tp, ct += q.top().second, q.pop(), q.push({b[i] - g, 0}); } } } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:20:54 03/06/2016
// Design Name: sumcomp4
// Module Name: C:/XilinxP/Practica1/sumcomp4_test.v
// Project Name: Practica1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: sumcomp4
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module sumcomp4_test;
// Inputs
reg x0;
reg x1;
reg x2;
reg x3;
reg y0;
reg y1;
reg y2;
reg y3;
// Outputs
wire S0;
wire S1;
wire S2;
wire S3;
// Instantiate the Unit Under Test (UUT)
sumcomp4 uut (
.x0(x0),
.x1(x1),
.x2(x2),
.x3(x3),
.y0(y0),
.y1(y1),
.y2(y2),
.y3(y3),
.S0(S0),
.S1(S1),
.S2(S2),
.S3(S3)
);
initial begin
$display("...");
// Initialize Inputs
x0 = 0;
x1 = 0;
x2 = 0;
x3 = 0;
y0 = 0;
y1 = 0;
y2 = 0;
y3 = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
x0 = 1; x1 = 1; x2 = 0; x3 = 1; y0 = 1; y1 = 0; y2 = 1; y3 = 0; //1011 + 0101
#50;
$display("x = %b%b%b%b, y = %b%b%b%b, z = %b%b%b%b", x3, x2, x1, x0, y3, y2, y1, y0, S3, S2, S1, S0);
x0 = 0; x1 = 1; x2 = 0; x3 = 1; y0 = 1; y1 = 0; y2 = 1; y3 = 1; //1010 + 1101
#50;
$display("x = %b%b%b%b, y = %b%b%b%b, z = %b%b%b%b", x3, x2, x1, x0, y3, y2, y1, y0, S3, S2, S1, S0);
x0 = 1; x1 = 1; x2 = 1; x3 = 1; y0 = 0; y1 = 1; y2 = 1; y3 = 1; //1111 + 1110
#50;
$display("x = %b%b%b%b, y = %b%b%b%b, z = %b%b%b%b", x3, x2, x1, x0, y3, y2, y1, y0, S3, S2, S1, S0);
x0 = 1; x1 = 1; x2 = 1; x3 = 1; y0 = 1; y1 = 1; y2 = 1; y3 = 1; //1111 + 1111
#50;
$display("x = %b%b%b%b, y = %b%b%b%b, z = %b%b%b%b", x3, x2, x1, x0, y3, y2, y1, y0, S3, S2, S1, S0);
x0 = 0; x1 = 0; x2 = 0; x3 = 1; y0 = 0; y1 = 0; y2 = 1; y3 = 0; //1000 + 0100
#50;
$display("x = %b%b%b%b, y = %b%b%b%b, z = %b%b%b%b", x3, x2, x1, x0, y3, y2, y1, y0, S3, S2, S1, S0);
x0 = 0; x1 = 1; x2 = 0; x3 = 1; y0 = 1; y1 = 0; y2 = 0; y3 = 0; //1010 + 0001
#50;
$display("x = %b%b%b%b, y = %b%b%b%b, z = %b%b%b%b", x3, x2, x1, x0, y3, y2, y1, y0, S3, S2, S1, S0);
x0 = 1; x1 = 1; x2 = 1; x3 = 1; y0 = 0; y1 = 0; y2 = 0; y3 = 0; //1111 + 0000
#50;
$display("x = %b%b%b%b, y = %b%b%b%b, z = %b%b%b%b", x3, x2, x1, x0, y3, y2, y1, y0, S3, S2, S1, S0);
x0 = 0; x1 = 1; x2 = 1; x3 = 0; y0 = 1; y1 = 0; y2 = 0; y3 = 1; //0110 + 1001
#50;
$display("x = %b%b%b%b, y = %b%b%b%b, z = %b%b%b%b", x3, x2, x1, x0, y3, y2, y1, y0, S3, S2, S1, S0);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int N; pair<int, int> P[105]; int main() { cin >> N; for (int i = 1; i <= N; i++) cin >> P[i].first >> P[i].second; int K; cin >> K; for (int i = 1; i <= N; i++) if (K >= P[i].first && K <= P[i].second) { cout << N - i + 1 << n ; return 0; } return 0; } |
module tb_comm_fpga_fx2_v1_stub;
reg clk_in;
reg reset_in;
wire fx2FifoSel_out;
reg [7:0] fx2Data_in;
wire [7:0] fx2Data_out;
wire fx2Data_sel;
wire fx2Read_out;
reg fx2GotData_in;
wire fx2Write_out;
reg fx2GotRoom_in;
wire fx2PktEnd_out;
wire [6:0] chanAddr_out;
wire [7:0] h2fData_out;
wire h2fValid_out;
reg h2fReady_in;
reg [7:0] f2hData_in;
reg f2hValid_in;
wire f2hReady_out;
initial begin
$from_myhdl(
clk_in,
reset_in,
fx2Data_in,
fx2GotData_in,
fx2GotRoom_in,
h2fReady_in,
f2hData_in,
f2hValid_in
);
$to_myhdl(
fx2FifoSel_out,
fx2Data_out,
fx2Data_sel,
fx2Read_out,
fx2Write_out,
fx2PktEnd_out,
chanAddr_out,
h2fData_out,
h2fValid_out,
f2hReady_out
);
end
comm_fpga_fx2_v1_stub dut(
clk_in,
reset_in,
fx2FifoSel_out,
fx2Data_in,
fx2Data_out,
fx2Data_sel,
fx2Read_out,
fx2GotData_in,
fx2Write_out,
fx2GotRoom_in,
fx2PktEnd_out,
chanAddr_out,
h2fData_out,
h2fValid_out,
h2fReady_in,
f2hData_in,
f2hValid_in,
f2hReady_out
);
endmodule
|
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