text stringlengths 59 71.4k |
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#include <bits/stdc++.h> using namespace std; template <class T> bool chmax(T &a, const T &b) { if (a < b) { a = b; return 1; } return 0; } template <class T> bool chmin(T &a, const T &b) { if (a > b) { a = b; return 1; } return 0; } template <class T> ostream &operator<<(ostream &os, const vector<T> &t) { os << [ ; for (__typeof((t).begin()) it = (t).begin(); it != (t).end(); it++) { if (it != t.begin()) os << , ; os << *it; } os << ] ; return os; } template <class T> ostream &operator<<(ostream &os, const set<T> &t) { os << { ; for (__typeof((t).begin()) it = (t).begin(); it != (t).end(); it++) { if (it != t.begin()) os << , ; os << *it; } os << } ; return os; } template <class S, class T> ostream &operator<<(ostream &os, const pair<S, T> &t) { return os << ( << t.first << , << t.second << ) ; } template <class S, class T> pair<S, T> operator+(const pair<S, T> &s, const pair<S, T> &t) { return pair<S, T>(s.first + t.first, s.second + t.second); } template <class S, class T> pair<S, T> operator-(const pair<S, T> &s, const pair<S, T> &t) { return pair<S, T>(s.first - t.first, s.second - t.second); } namespace geom { enum { TRUE = 1, FALSE = 0, BORDER = -1 }; const long double INF = 1e8; long double EPS = 1e-6; const long double PI = 3.1415926535897932384626; inline int sig(const long double &x) { return (abs(x) < EPS ? 0 : x > 0 ? 1 : -1); } inline int less(const long double &x, const long double &y) { return sig(x - y) ? x < y : BORDER; } inline long double norm(const complex<long double> &p) { return p.real() * p.real() + p.imag() * p.imag(); } inline long double inp(const complex<long double> &a, const complex<long double> &b) { return (conj(a) * b).real(); } inline long double outp(const complex<long double> &a, const complex<long double> &b) { return (conj(a) * b).imag(); } inline complex<long double> unit(const complex<long double> &p) { return p / abs(p); } inline complex<long double> proj(const complex<long double> &s, const complex<long double> &t) { return t * inp(s, t) / norm(t); } inline int ccw(const complex<long double> &s, const complex<long double> &t, const complex<long double> &p, int adv = 0) { int res = sig(outp(t - s, p - s)); if (res || !adv) return res; if (sig(inp(t - s, p - s)) < 0) return -2; if (sig(inp(s - t, p - t)) < 0) return 2; return 0; } } // namespace geom using namespace geom; int f = 0; namespace std { bool operator<(const complex<long double> &a, const complex<long double> &b) { return sig(a.real() - b.real()) ? a.real() < b.real() : a.imag() + EPS < b.imag(); } bool operator==(const complex<long double> &a, const complex<long double> &b) { return abs(a - b) < EPS; } istream &operator>>(istream &is, complex<long double> &p) { long double x, y; is >> x >> y; p = complex<long double>(x, y); return is; } } // namespace std int n, m; complex<long double> p, q, v, w; long double vmax, ct; long double dist(complex<long double> v, complex<long double> wind, long double t) { if (abs(v) > EPS) v = unit(v); long double l = 0, r = 1e10; for (int _ = 0; _ < (int)(100); _++) { long double mid = (l + r) / 2; long double vx = v.real() * mid; long double vy = v.imag() * mid; if ((vx * vx + vy * vy) <= vmax * vmax) l = mid; else r = mid; } return abs(v * l) * t; } int check(long double t) { complex<long double> s = q + v * min<long double>(t, ct) + w * max<long double>(t - ct, 0); complex<long double> vec = p - s; return dist(vec, v, min<long double>(t, ct)) + dist(vec, w, max<long double>(t - ct, 0)) >= abs(vec); } int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> q >> p; cin >> vmax >> ct; cin >> v >> w; long double l = 0, r = 1e10; for (int _ = 0; _ < (int)(100); _++) { long double mid = (l + r) / 2; if (check(mid)) r = mid; else l = mid; } printf( %.20f n , (double)l); return 0; } |
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
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// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
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// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Filename: trace_buffer.v
// Description: Trace port buffer
//-----------------------------------------------------------------------------
// Structure: This section shows the hierarchical structure of
// pss_wrapper.
//
// --processing_system7
// |
// --trace_buffer
//-----------------------------------------------------------------------------
module processing_system7_v5_3_trace_buffer #
(
parameter integer FIFO_SIZE = 128,
parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
parameter integer C_DELAY_CLKS = 12
)
(
input wire TRACE_CLK,
input wire RST,
input wire TRACE_VALID_IN,
input wire [3:0] TRACE_ATID_IN,
input wire [31:0] TRACE_DATA_IN,
output wire TRACE_VALID_OUT,
output wire [3:0] TRACE_ATID_OUT,
output wire [31:0] TRACE_DATA_OUT
);
//------------------------------------------------------------
// Architecture section
//------------------------------------------------------------
// function called clogb2 that returns an integer which has the
// value of the ceiling of the log base 2.
function integer clogb2 (input integer bit_depth);
integer i;
integer temp_log;
begin
temp_log = 0;
for(i=bit_depth; i > 0; i = i>>1)
clogb2 = temp_log;
temp_log=temp_log+1;
end
endfunction
localparam DEPTH = clogb2(FIFO_SIZE-1);
wire [31:0] reset_zeros;
reg [31:0] trace_pedge; // write enable for FIFO
reg [31:0] ti;
reg [31:0] tom;
reg [3:0] atid;
reg [31:0] trace_fifo [FIFO_SIZE-1:0];//Memory
reg [4:0] dly_ctr;
reg [DEPTH-1:0] fifo_wp;
reg [DEPTH-1:0] fifo_rp;
reg fifo_re;
wire fifo_empty;
wire fifo_full;
reg fifo_full_reg;
assign reset_zeros = 32'h0;
// Pipeline Stage for Traceport ATID ports
always @(posedge TRACE_CLK) begin
// process pedge_ti
// rising clock edge
if((RST == 1'b1)) begin
atid <= reset_zeros;
end
else begin
atid <= TRACE_ATID_IN;
end
end
assign TRACE_ATID_OUT = atid;
/////////////////////////////////////////////
// Generate FIFO data based on TRACE_VALID_IN
/////////////////////////////////////////////
generate
if (USE_TRACE_DATA_EDGE_DETECTOR == 0) begin : gen_no_data_edge_detector
/////////////////////////////////////////////
// memory update process
// Update memory when positive edge detected and FIFO not full
always @(posedge TRACE_CLK) begin
if (TRACE_VALID_IN == 1'b1 && fifo_full_reg != 1'b1) begin
trace_fifo[fifo_wp] <= TRACE_DATA_IN;
end
end
// fifo write pointer
always @(posedge TRACE_CLK) begin
// process
if(RST == 1'b1) begin
fifo_wp <= {DEPTH{1'b0}};
end
else if(TRACE_VALID_IN ) begin
if(fifo_wp == (FIFO_SIZE - 1)) begin
if (fifo_empty) begin
fifo_wp <= {DEPTH{1'b0}};
end
end
else begin
fifo_wp <= fifo_wp + 1;
end
end
end
/////////////////////////////////////////////
// Generate FIFO data based on data edge
/////////////////////////////////////////////
end else begin : gen_data_edge_detector
/////////////////////////////////////////////
// purpose: check for pos edge on any trace input
always @(posedge TRACE_CLK) begin
// process pedge_ti
// rising clock edge
if((RST == 1'b1)) begin
ti <= reset_zeros;
trace_pedge <= reset_zeros;
end
else begin
ti <= TRACE_DATA_IN;
trace_pedge <= (~ti & TRACE_DATA_IN);
//trace_pedge <= ((~ti ^ TRACE_DATA_IN)) & ~ti;
// posedge only
end
end
// memory update process
// Update memory when positive edge detected and FIFO not full
always @(posedge TRACE_CLK) begin
if(|(trace_pedge) == 1'b1 && fifo_full_reg != 1'b1) begin
trace_fifo[fifo_wp] <= trace_pedge;
end
end
// fifo write pointer
always @(posedge TRACE_CLK) begin
// process
if(RST == 1'b1) begin
fifo_wp <= {DEPTH{1'b0}};
end
else if(|(trace_pedge) == 1'b1) begin
if(fifo_wp == (FIFO_SIZE - 1)) begin
if (fifo_empty) begin
fifo_wp <= {DEPTH{1'b0}};
end
end
else begin
fifo_wp <= fifo_wp + 1;
end
end
end
end
endgenerate
always @(posedge TRACE_CLK) begin
tom <= trace_fifo[fifo_rp] ;
end
// // fifo write pointer
// always @(posedge TRACE_CLK) begin
// // process
// if(RST == 1'b1) begin
// fifo_wp <= {DEPTH{1'b0}};
// end
// else if(|(trace_pedge) == 1'b1) begin
// if(fifo_wp == (FIFO_SIZE - 1)) begin
// fifo_wp <= {DEPTH{1'b0}};
// end
// else begin
// fifo_wp <= fifo_wp + 1;
// end
// end
// end
// fifo read pointer update
always @(posedge TRACE_CLK) begin
if(RST == 1'b1) begin
fifo_rp <= {DEPTH{1'b0}};
fifo_re <= 1'b0;
end
else if(fifo_empty != 1'b1 && dly_ctr == 5'b00000 && fifo_re == 1'b0) begin
fifo_re <= 1'b1;
if(fifo_rp == (FIFO_SIZE - 1)) begin
fifo_rp <= {DEPTH{1'b0}};
end
else begin
fifo_rp <= fifo_rp + 1;
end
end
else begin
fifo_re <= 1'b0;
end
end
// delay counter update
always @(posedge TRACE_CLK) begin
if(RST == 1'b1) begin
dly_ctr <= 5'h0;
end
else if (fifo_re == 1'b1) begin
dly_ctr <= C_DELAY_CLKS-1;
end
else if(dly_ctr != 5'h0) begin
dly_ctr <= dly_ctr - 1;
end
end
// fifo empty update
assign fifo_empty = (fifo_wp == fifo_rp) ? 1'b1 : 1'b0;
// fifo full update
assign fifo_full = (fifo_wp == FIFO_SIZE-1)? 1'b1 : 1'b0;
always @(posedge TRACE_CLK) begin
if(RST == 1'b1) begin
fifo_full_reg <= 1'b0;
end
else if (fifo_empty) begin
fifo_full_reg <= 1'b0;
end else begin
fifo_full_reg <= fifo_full;
end
end
// always @(posedge TRACE_CLK) begin
// if(RST == 1'b1) begin
// fifo_full_reg <= 1'b0;
// end
// else if ((fifo_wp == FIFO_SIZE-1) && (|(trace_pedge) == 1'b1)) begin
// fifo_full_reg <= 1'b1;
// end
// else begin
// fifo_full_reg <= 1'b0;
// end
// end
//
assign TRACE_DATA_OUT = tom;
assign TRACE_VALID_OUT = fifo_re;
endmodule
|
#include <bits/stdc++.h> using namespace std; void err(istream_iterator<string> it) {} template <typename T, typename... Args> void err(istream_iterator<string> it, T a, Args... args) { cerr << *it << = << a << endl; err(++it, args...); } long long powMod(long long x, long long y) { long long p = 1; while (y) { if (y % 2) { p = (p * x) % ((long long)1e9 + 7); } y /= 2; x = (x * x) % ((long long)1e9 + 7); } return p; } long long CpowMod(long long x, long long y, long long w) { long long p = 1; while (y) { if (y % 2) { p = (p * x) % w; } y /= 2; x = (x * x) % w; } return p; } long long invMod(long long x) { return powMod(x, ((long long)1e9 + 7) - 2); } long long CinvMod(long long x, long long w) { return CpowMod(x, w - 2, w); } long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } void solve() { long long n; cin >> n; long long ans = 1; for (long long i = 1; i <= n - 1; i++) { if (i != n / 2) ans *= i; } cout << ans << endl; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cout.precision(20); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 10; int pref[N]; vector<int> v; int fsoma(int l, int r) { l--; int ans = pref[r]; if (l >= 0) ans -= pref[l]; return ans; } long long n, k, l; void rbest(pair<int, int> &a, pair<int, int> b) { if (b.first > a.first or (a.first == b.first and b.second < a.second)) a = b; } pair<int, int> comb(pair<int, int> a, pair<int, int> b) { return {a.first + b.first, a.second + b.second}; } vector<pair<int, int>> dp(n); pair<int, int> rec(int i) { if (i >= 0) return dp[i]; return {0, 0}; } pair<int, int> f(int c) { dp = vector<pair<int, int>>(n); for (int i = 0; i < n; i++) { rbest(dp[i], rec(i - 1)); rbest(dp[i], comb(rec(i - l), {fsoma(i - (l - 1), i) - c, 1})); } return dp[n - 1]; } long long solve(vector<int> &_v) { v = _v; for (int i = 0; i < (int)(v.size()); i++) { pref[i] = v[i]; if (i) pref[i] += pref[i - 1]; } int lo = 0, hi = l + 1; while (lo < hi) { int mid = (lo + hi) / 2; if (f(mid).second <= k) hi = mid; else lo = mid + 1; } auto par = f(lo); return pref[(int)(v.size()) - 1] - (par.first + lo * k); } int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n >> k >> l; string s; cin >> s; vector<int> v1((int)(s.size())), v2((int)(s.size())); for (int i = 0; i < (int)(s.size()); i++) { if (s[i] >= A and s[i] <= Z ) { v1[i] = 1; } else { v2[i] = 1; } } cout << min(solve(v1), solve(v2)) << n ; } |
#include <bits/stdc++.h> using namespace std; const long long limita = 998244353; long long n, v[200], st, dr, mij, mul, ans, maxDegree; long long GCD(long long x, long long y) { if (y != 0) return GCD(y, x % y); else return x; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; for (int i = 1; i <= n; i++) { cin >> v[i]; } for (int i = 1; i <= n; i++) { ans = 180 / GCD(180LL, v[i]); mul = 0; st = 1; dr = limita / ans; while (st <= dr) { mij = (st + dr) / 2; maxDegree = (mij * ans - 2) * 180 / (mij * ans); if (maxDegree >= v[i]) { dr = mij - 1; mul = mij; } else st = mij + 1; } if (mul == 0) cout << -1 << n ; else cout << mul * ans << n ; } } |
#include <cstdio> #include <cstdlib> #include <cstring> #include <cmath> #include <ctime> #include <iostream> #include <algorithm> #include <queue> #include <map> #include <set> #include <vector> #include <string> #include <stack> #include <numeric> #include <cassert> #define endl n #define sp #define pb push_back #define mp make_pair #define ff first #define ss second using namespace std; typedef long long ll; typedef pair<int,int> pii; typedef pair<ll,ll> pll; const int maxn = 2e5+5; set<pair<int,char>> adj[maxn]; int main(){ ios_base::sync_with_stdio(false);cin.tie(nullptr);cout.tie(nullptr);cerr.tie(nullptr); int n,m;cin>>n>>m; set<pii> cift, samecift; for(int q=0;q<m;q++){ char t;cin>>t; if(t == + ){ int u,v;char c;cin>>u>>v>>c; pair<int,char> p = {v,c}; adj[u].emplace(v,c); auto it = adj[v].lower_bound({u,0}); if(it != adj[v].end() && it->ff == u){ int setu = min(u,v); int setv = max(u,v); cift.emplace(setu,setv); if(it->ss == c){ samecift.emplace(setu,setv); } } } else if(t == - ){ int u,v;cin>>u>>v; auto it = adj[u].lower_bound({v,0}); assert(it != adj[u].end()); adj[u].erase(it); int setu = min(u,v); int setv = max(u,v); auto it2 = cift.find({setu,setv}); if(it2 != cift.end()){ cift.erase(it2); it2 = samecift.find({setu,setv}); if(it2 != samecift.end()){ samecift.erase(it2); } } } else{ int k;cin>>k; if(k&1){ if(cift.size()){ cout << YES << endl; } else cout << NO << endl; } else{ if(samecift.size()){ cout << YES << endl; } else{ cout << NO << endl; } } } } } |
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
`define ENABLE_VCD
module tb_fmlbrg();
reg clk;
initial clk = 1'b0;
always #5 clk = ~clk;
reg rst;
reg [19:1] wb_adr_i;
reg [2:0] wb_cti_i;
reg [15:0] wb_dat_i;
wire [15:0] wb_dat_o;
reg [1:0] wb_sel_i;
reg wb_cyc_i;
reg wb_stb_i;
reg wb_we_i;
wire wb_ack_o;
wire [19:0] fml_adr;
wire fml_stb;
wire fml_we;
reg fml_ack;
wire [1:0] fml_sel;
wire [15:0] fml_dw;
reg [15:0] fml_dr;
reg dcb_stb;
reg [19:0] dcb_adr;
wire [15:0] dcb_dat;
wire dcb_hit;
/* Process FML requests */
reg [2:0] fml_wcount;
reg [2:0] fml_rcount;
initial begin
fml_ack = 1'b0;
fml_wcount = 0;
fml_rcount = 0;
end
always @(posedge clk) begin
if(fml_stb & (fml_wcount == 0) & (fml_rcount == 0)) begin
fml_ack <= 1'b1;
if(fml_we) begin
$display("%t FML W addr %x data %x", $time, fml_adr, fml_dw);
fml_wcount <= 7;
end else begin
fml_dr = 16'hbeef;
$display("%t FML R addr %x data %x", $time, fml_adr, fml_dr);
fml_rcount <= 7;
end
end else
fml_ack <= 1'b0;
if(fml_wcount != 0) begin
#1 $display("%t FML W continuing %x / %d", $time, fml_dw, fml_wcount);
fml_wcount <= fml_wcount - 1;
end
if(fml_rcount != 0) begin
fml_dr = #1 {13'h1eba, fml_rcount};
$display("%t FML R continuing %x / %d", $time, fml_dr, fml_rcount);
fml_rcount <= fml_rcount - 1;
end
end
fmlbrg #(
.fml_depth (20), // 8086 can only address 1 MB
.cache_depth (10) // 1 Kbyte cache
) dut (
.sys_clk(clk),
.sys_rst(rst),
.wb_adr_i(wb_adr_i),
.wb_cti_i(wb_cti_i),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_sel_i(wb_sel_i),
.wb_cyc_i(wb_cyc_i),
.wb_stb_i(wb_stb_i),
.wb_we_i(wb_we_i),
.wb_ack_o(wb_ack_o),
.fml_adr(fml_adr),
.fml_stb(fml_stb),
.fml_we(fml_we),
.fml_ack(fml_ack),
.fml_sel(fml_sel),
.fml_do(fml_dw),
.fml_di(fml_dr),
.dcb_stb(dcb_stb),
.dcb_adr(dcb_adr),
.dcb_dat(dcb_dat),
.dcb_hit(dcb_hit)
);
task waitclock;
begin
@(posedge clk);
#1;
end
endtask
task wbwrite;
input [19:1] address;
input [1:0] sel;
input [15:0] data;
integer i;
begin
wb_adr_i = address;
wb_cti_i = 3'b000;
wb_dat_i = data;
wb_sel_i = sel;
wb_cyc_i = 1'b1;
wb_stb_i = 1'b1;
wb_we_i = 1'b1;
i = 0;
while(~wb_ack_o) begin
i = i+1;
waitclock;
end
waitclock;
$display("WB Write: %x=%x sel=%b acked in %d clocks", address, data, sel, i);
wb_adr_i = 19'hx;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
end
endtask
task wbread;
input [19:1] address;
integer i;
begin
wb_adr_i = address;
wb_cti_i = 3'b000;
wb_cyc_i = 1'b1;
wb_stb_i = 1'b1;
wb_we_i = 1'b0;
i = 0;
while(~wb_ack_o) begin
i = i+1;
waitclock;
end
$display("WB Read : %x=%x acked in %d clocks", address, wb_dat_o, i);
waitclock;
wb_adr_i = 19'hx;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
end
endtask
task wbwriteburst;
input [19:1] address;
input [15:0] data;
integer i;
begin
wb_adr_i = address;
wb_cti_i = 3'b010;
wb_dat_i = data;
wb_sel_i = 2'b11;
wb_cyc_i = 1'b1;
wb_stb_i = 1'b1;
wb_we_i = 1'b1;
i = 0;
while(~wb_ack_o) begin
i = i+1;
waitclock;
end
waitclock;
$display("WB Write: %x=%x acked in %d clocks", address, data, i);
wb_dat_i = data+1;
waitclock;
wb_dat_i = data+2;
waitclock;
wb_dat_i = data+3;
wb_cti_i = 3'b111;
waitclock;
wb_adr_i = 19'hx;
wb_cti_i = 3'b000;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
end
endtask
task wbreadburst;
input [19:1] address;
integer i;
begin
wb_adr_i = address;
wb_cti_i = 3'b010;
wb_cyc_i = 1'b1;
wb_stb_i = 1'b1;
wb_we_i = 1'b0;
i = 0;
while(~wb_ack_o) begin
i = i+1;
waitclock;
end
$display("WB Read : %x=%x acked in %d clocks", address, wb_dat_o, i);
waitclock;
$display("read burst(1): %x", wb_dat_o);
waitclock;
$display("read burst(2): %x", wb_dat_o);
waitclock;
wb_cti_i = 3'b111;
$display("read burst(3): %x", wb_dat_o);
waitclock;
wb_adr_i = 19'hx;
wb_cti_i = 3'b000;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
end
endtask
always begin
`ifdef ENABLE_VCD
$dumpfile("fmlbrg.vcd");
$dumpvars(0, dut);
`endif
rst = 1'b1;
wb_adr_i = 19'd0;
wb_dat_i = 16'd0;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
dcb_stb = 1'b0;
dcb_adr = 20'd0;
waitclock;
rst = 1'b0;
waitclock;
$display("Testing: read miss");
wbread(19'h0);
$display("Testing: write hit");
wbwrite(19'h0, 2'b11, 16'h5678);
wbread(19'h0);
$display("Testing: read miss on a dirty line");
wbread(19'h01000);
$display("Testing: read hit");
wbread(19'h01004);
$display("Testing: write miss");
wbwrite(19'h0, 2'b11, 16'hface);
wbread(27'h0);
wbread(27'h4);
$display("Testing: read burst");
wbreadburst(19'h40);
$display("Testing: write burst");
wbwriteburst(19'h40, 16'hcaf0);
$display("Testing: read burst");
wbreadburst(19'h40);
$display("Testing: DCB miss");
dcb_adr = 20'hfeba;
dcb_stb = 1'b1;
waitclock;
$display("Result: hit=%b dat=%x", dcb_hit, dcb_dat);
$display("Testing: DCB hit");
dcb_adr = 20'h0;
dcb_stb = 1'b1;
waitclock;
$display("Result: hit=%b dat=%x", dcb_hit, dcb_dat);
$display("Testing: DCB hit");
dcb_adr = 20'h0;
dcb_stb = 1'b1;
waitclock;
$display("Result: hit=%b dat=%x", dcb_hit, dcb_dat);
$display("Testing: DCB hit");
dcb_adr = 20'h1;
dcb_stb = 1'b1;
waitclock;
$display("Result: hit=%b dat=%x", dcb_hit, dcb_dat);
$display("Testing: DCB hit");
dcb_adr = 20'h2;
dcb_stb = 1'b1;
waitclock;
$display("Result: hit=%b dat=%x", dcb_hit, dcb_dat);
$stop;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 300005; int n; int ans = 300005, pos = 1; long long tnow, wnow; struct node { long long t, w; } a[N]; priority_queue<long long, vector<long long>, greater<long long> > q; bool cmp(node a, node b) { return a.t > b.t; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %lld%lld , &a[i].t, &a[i].w); tnow = a[1].t; wnow = a[1].w; a[1].t = 0; sort(a + 1, a + 1 + n, cmp); while (1) { while (pos <= n && a[pos].t > tnow) { q.push(a[pos].w - a[pos].t + 1); pos++; } ans = min(ans, (int)q.size() + 1); if (!q.size() || tnow < q.top()) break; tnow -= q.top(); q.pop(); } printf( %d n , ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O311A_TB_V
`define SKY130_FD_SC_LP__O311A_TB_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o311a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_lp__o311a dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O311A_TB_V
|
/////////////////////////////////////////////////////////////////////////
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
// SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
// XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
// AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
// OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
// IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
// AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
// FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
// WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
// IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
// INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE.
//
// (c) Copyright 2004 Xilinx, Inc.
// All rights reserved.
//
/////////////////////////////////////////////////////////////////////////
module dual_ps2_ioadapter (
ps2_clk_rx_1, // O
ps2_clk_rx_2, // O
ps2_clk_tx_1, // I
ps2_clk_tx_2, // I
ps2_d_rx_1, // O
ps2_d_rx_2, // O
ps2_d_tx_1, // I
ps2_d_tx_2, // I
ps2_mouse_clk_I, // I
ps2_mouse_clk_O, // O
ps2_mouse_clk_T, // O
ps2_mouse_data_I, // I
ps2_mouse_data_O, // O
ps2_mouse_data_T, // O
ps2_keyb_clk_I, // I
ps2_keyb_clk_O, // O
ps2_keyb_clk_T, // O
ps2_keyb_data_I, // I
ps2_keyb_data_O, // O
ps2_keyb_data_T // O
);
output ps2_clk_rx_1;
output ps2_clk_rx_2;
input ps2_clk_tx_1;
input ps2_clk_tx_2;
output ps2_d_rx_1;
output ps2_d_rx_2;
input ps2_d_tx_1;
input ps2_d_tx_2;
input ps2_mouse_clk_I;
output ps2_mouse_clk_O;
output ps2_mouse_clk_T;
input ps2_mouse_data_I;
output ps2_mouse_data_O;
output ps2_mouse_data_T;
input ps2_keyb_clk_I;
output ps2_keyb_clk_O;
output ps2_keyb_clk_T;
input ps2_keyb_data_I;
output ps2_keyb_data_O;
output ps2_keyb_data_T;
// PS/2 Assignments
assign ps2_clk_rx_1 = ps2_mouse_clk_I;
assign ps2_clk_rx_2 = ps2_keyb_clk_I;
assign ps2_d_rx_1 = ps2_mouse_data_I;
assign ps2_d_rx_2 = ps2_keyb_data_I;
assign ps2_mouse_clk_O = 1'b0;
assign ps2_mouse_clk_T = ~ps2_clk_tx_1;
assign ps2_mouse_data_O = 1'b0;
assign ps2_mouse_data_T = ~ps2_d_tx_1;
assign ps2_keyb_clk_O = 1'b0;
assign ps2_keyb_clk_T = ~ps2_clk_tx_2;
assign ps2_keyb_data_O = 1'b0;
assign ps2_keyb_data_T = ~ps2_d_tx_2;
endmodule // dual_ps2_ioadapter
|
module ram(input [11:0] adr, input we,
inout [31:0] data);
reg [31:0]ram[11:0];
integer i = 0;
//Op Codes
parameter NOP = 4'b0000;
parameter LOAD = 4'b0001;
parameter STORE = 4'b0010;
parameter BRANCH = 4'b0011;
parameter XOR = 4'b0100;
parameter ADD = 4'b0101;
parameter ROTATE = 4'b0110;
parameter SHIFT = 4'b0111;
parameter HALT = 4'b1000;
parameter COMPLEMENT = 4'b1001;
//Condition Codes
parameter ALWAYS = 4'b0000;
parameter PARITY = 4'b0001;
parameter EVEN = 4'b0010;
parameter CARRY = 4'b0011;
parameter NEGATIVE = 4'b0100;
parameter ZERO = 4'b0101;
parameter NOCARRY = 4'b0110;
parameter POSITIVE = 4'b0111;
//first 8 regs
parameter reg0 = 12'b000000000_000;
parameter reg1 = 12'b000000000_001;
parameter reg2 = 12'b000000000_010;
parameter reg3 = 12'b000000000_011;
parameter reg4 = 12'b000000000_100;
parameter reg5 = 12'b000000000_101;
parameter reg6 = 12'b000000000_110;
parameter reg7 = 12'b000000000_111;
//first 8 data memory locations
parameter mem0 = 12'b000001_111111;
parameter mem1 = 12'b000010_111111;
parameter mem2 = 12'b000011_111111;
parameter mem3 = 12'b000100_111111;
parameter mem4 = 12'b000101_111111;
parameter mem5 = 12'b000110_111111;
parameter mem6 = 12'b000111_111111;
parameter mem7 = 12'b001000_111111;
//first 10 instruction memory locations
parameter is0 = 12'b000000_000000;
parameter is1 = 12'b000000_000001;
parameter is2 = 12'b000000_000010;
parameter is3 = 12'b000000_000011;
parameter is4 = 12'b000000_000100;
parameter is5 = 12'b000000_000101;
parameter is6 = 12'b000000_000110;
parameter is7 = 12'b000000_000111;
parameter is8 = 12'b000000_001000;
parameter is9 = 12'b000000_001001;
//source types
parameter REG = 1'b0;
parameter MEM = 1'b0;
parameter IMM = 1'b1;
//for bits 24 adn 25 when not using a branch op
parameter xx = 2'b00;
//for when destinaation address is not being used during a branch op
parameter addressx = 12'b000000_000000;
//common immediates
parameter imm0 = 12'b000000_000000;
parameter imm1 = 12'b000000_000001;
assign data = (we) ? 'bz : ram[adr];
initial begin
for(i = 0; i< 12; i = i +1) begin
ram[i] = 'd0;
end
ram[is0] = {reg0,mem0,xx,REG,MEM,LOAD}; //load number in memory0 to reg 0
ram[is1] = {addressx,is5,ZERO,BRANCH}; //if reg0 is 0 then branch to store/end of program
ram[is2] = {reg0,imm1,xx,REG,IMM,SHIFT}; //shift reg0 to the right by 1
ram[is3] = {reg1,imm1,xx,REG,IMM,ADD}; //add 1 to answer (reg1)
ram[is4] = {addressx,is1,ALWAYS,BRANCH};//branch/loop back to check if reg0 is 0
ram[is5] = {mem1,reg1,xx,MEM,REG,STORE}; //if it is 0 store answer from reg1 in mem1
ram[is6] = {addressx,addressx,xx,xx,HALT}; //Halt
ram[mem0] = 'b11010100_00001101_11011111_11001100; //18 1's answer should be 10010
end
always@(adr or we) begin
if(we) begin
ram[adr] = data;
end
end
endmodule
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:hls:zbroji:1.0
// IP Revision:
(* X_CORE_INFO = "zbroji_top,Vivado 2013.4" *)
(* CHECK_LICENSE_TYPE = "ZynqDesign_zbroji_0_0,zbroji_top,{}" *)
(* CORE_GENERATION_INFO = "ZynqDesign_zbroji_0_0,zbroji_top,{x_ipProduct=Vivado 2013.4,x_ipVendor=xilinx.com,x_ipLibrary=hls,x_ipName=zbroji,x_ipVersion=1.0,x_ipCoreRevision=,x_ipLanguage=VHDL,C_S_AXI_HLS_ZBROJI_PERIPH_BUS_ADDR_WIDTH=6,C_S_AXI_HLS_ZBROJI_PERIPH_BUS_DATA_WIDTH=32}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module ZynqDesign_zbroji_0_0 (
s_axi_HLS_ZBROJI_PERIPH_BUS_AWADDR,
s_axi_HLS_ZBROJI_PERIPH_BUS_AWVALID,
s_axi_HLS_ZBROJI_PERIPH_BUS_AWREADY,
s_axi_HLS_ZBROJI_PERIPH_BUS_WDATA,
s_axi_HLS_ZBROJI_PERIPH_BUS_WSTRB,
s_axi_HLS_ZBROJI_PERIPH_BUS_WVALID,
s_axi_HLS_ZBROJI_PERIPH_BUS_WREADY,
s_axi_HLS_ZBROJI_PERIPH_BUS_BRESP,
s_axi_HLS_ZBROJI_PERIPH_BUS_BVALID,
s_axi_HLS_ZBROJI_PERIPH_BUS_BREADY,
s_axi_HLS_ZBROJI_PERIPH_BUS_ARADDR,
s_axi_HLS_ZBROJI_PERIPH_BUS_ARVALID,
s_axi_HLS_ZBROJI_PERIPH_BUS_ARREADY,
s_axi_HLS_ZBROJI_PERIPH_BUS_RDATA,
s_axi_HLS_ZBROJI_PERIPH_BUS_RRESP,
s_axi_HLS_ZBROJI_PERIPH_BUS_RVALID,
s_axi_HLS_ZBROJI_PERIPH_BUS_RREADY,
interrupt,
aclk,
aresetn
);
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS AWADDR" *)
input wire [5 : 0] s_axi_HLS_ZBROJI_PERIPH_BUS_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS AWVALID" *)
input wire s_axi_HLS_ZBROJI_PERIPH_BUS_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS AWREADY" *)
output wire s_axi_HLS_ZBROJI_PERIPH_BUS_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS WDATA" *)
input wire [31 : 0] s_axi_HLS_ZBROJI_PERIPH_BUS_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS WSTRB" *)
input wire [3 : 0] s_axi_HLS_ZBROJI_PERIPH_BUS_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS WVALID" *)
input wire s_axi_HLS_ZBROJI_PERIPH_BUS_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS WREADY" *)
output wire s_axi_HLS_ZBROJI_PERIPH_BUS_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS BRESP" *)
output wire [1 : 0] s_axi_HLS_ZBROJI_PERIPH_BUS_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS BVALID" *)
output wire s_axi_HLS_ZBROJI_PERIPH_BUS_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS BREADY" *)
input wire s_axi_HLS_ZBROJI_PERIPH_BUS_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS ARADDR" *)
input wire [5 : 0] s_axi_HLS_ZBROJI_PERIPH_BUS_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS ARVALID" *)
input wire s_axi_HLS_ZBROJI_PERIPH_BUS_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS ARREADY" *)
output wire s_axi_HLS_ZBROJI_PERIPH_BUS_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS RDATA" *)
output wire [31 : 0] s_axi_HLS_ZBROJI_PERIPH_BUS_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS RRESP" *)
output wire [1 : 0] s_axi_HLS_ZBROJI_PERIPH_BUS_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS RVALID" *)
output wire s_axi_HLS_ZBROJI_PERIPH_BUS_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS RREADY" *)
input wire s_axi_HLS_ZBROJI_PERIPH_BUS_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT" *)
output wire interrupt;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
input wire aresetn;
zbroji_top #(
.C_S_AXI_HLS_ZBROJI_PERIPH_BUS_ADDR_WIDTH(6),
.C_S_AXI_HLS_ZBROJI_PERIPH_BUS_DATA_WIDTH(32)
) inst (
.s_axi_HLS_ZBROJI_PERIPH_BUS_AWADDR(s_axi_HLS_ZBROJI_PERIPH_BUS_AWADDR),
.s_axi_HLS_ZBROJI_PERIPH_BUS_AWVALID(s_axi_HLS_ZBROJI_PERIPH_BUS_AWVALID),
.s_axi_HLS_ZBROJI_PERIPH_BUS_AWREADY(s_axi_HLS_ZBROJI_PERIPH_BUS_AWREADY),
.s_axi_HLS_ZBROJI_PERIPH_BUS_WDATA(s_axi_HLS_ZBROJI_PERIPH_BUS_WDATA),
.s_axi_HLS_ZBROJI_PERIPH_BUS_WSTRB(s_axi_HLS_ZBROJI_PERIPH_BUS_WSTRB),
.s_axi_HLS_ZBROJI_PERIPH_BUS_WVALID(s_axi_HLS_ZBROJI_PERIPH_BUS_WVALID),
.s_axi_HLS_ZBROJI_PERIPH_BUS_WREADY(s_axi_HLS_ZBROJI_PERIPH_BUS_WREADY),
.s_axi_HLS_ZBROJI_PERIPH_BUS_BRESP(s_axi_HLS_ZBROJI_PERIPH_BUS_BRESP),
.s_axi_HLS_ZBROJI_PERIPH_BUS_BVALID(s_axi_HLS_ZBROJI_PERIPH_BUS_BVALID),
.s_axi_HLS_ZBROJI_PERIPH_BUS_BREADY(s_axi_HLS_ZBROJI_PERIPH_BUS_BREADY),
.s_axi_HLS_ZBROJI_PERIPH_BUS_ARADDR(s_axi_HLS_ZBROJI_PERIPH_BUS_ARADDR),
.s_axi_HLS_ZBROJI_PERIPH_BUS_ARVALID(s_axi_HLS_ZBROJI_PERIPH_BUS_ARVALID),
.s_axi_HLS_ZBROJI_PERIPH_BUS_ARREADY(s_axi_HLS_ZBROJI_PERIPH_BUS_ARREADY),
.s_axi_HLS_ZBROJI_PERIPH_BUS_RDATA(s_axi_HLS_ZBROJI_PERIPH_BUS_RDATA),
.s_axi_HLS_ZBROJI_PERIPH_BUS_RRESP(s_axi_HLS_ZBROJI_PERIPH_BUS_RRESP),
.s_axi_HLS_ZBROJI_PERIPH_BUS_RVALID(s_axi_HLS_ZBROJI_PERIPH_BUS_RVALID),
.s_axi_HLS_ZBROJI_PERIPH_BUS_RREADY(s_axi_HLS_ZBROJI_PERIPH_BUS_RREADY),
.interrupt(interrupt),
.aclk(aclk),
.aresetn(aresetn)
);
endmodule
|
// ----------------------------------------------------------------------------
// Module: alu.v
// Project: MOS 6502 Processor
// Author: George Castillo
// Date: Sat Jul 8 15:31:17 2017
//
// Description: Arithmetic-logic unit for the MOS 6502 processor.
//
// Usage: The ALU is used by the processor to perform the majority of its
// arithmetic functions. Some details about the implementation follow.
//
// Control Signals:
// ADD = 3'b000
// SR = 3'b001
// AND = 3'b010
// OR = 3'b011
// XOR = 3'b100
//
// Logical and arithmetic operations do not distinguish between the A and B
// inputs. However, the right shift operation assumes exclusive use of the
// A input.
// ----------------------------------------------------------------------------
module alu
(
input [2:0] alu_control,
input [7:0] alu_AI,
input [7:0] alu_BI,
input alu_carry_in,
output reg [7:0] alu_Y,
output reg alu_carry_out,
output reg alu_overflow
);
`include "params.vh"
// --- Miscellaneous Signals
reg [8:0] add_result; // 9-bits to keep track of the carry
reg add_carry_out;
reg add_overflow;
reg sr_carry_out;
// Mux out the intended operation
always @(*) begin
case ( alu_control )
ADD: begin
add_result = {1'b0, alu_AI} + {1'b0, alu_BI} + {8'd0, alu_carry_in};
add_carry_out = add_result[8];
alu_Y = add_result[7:0];
alu_overflow = add_overflow;
end
SR: begin
alu_Y = {alu_carry_in, alu_AI[7:1]};
sr_carry_out = alu_AI[0];
alu_overflow = 1'b0;
end
AND: begin
alu_Y = alu_AI & alu_BI;
alu_overflow = 1'b0;
end
OR: begin
alu_Y = alu_AI | alu_BI;
alu_overflow = 1'b0;
end
XOR: begin
alu_Y = alu_AI ^ alu_BI;
alu_overflow = 1'b0;
end
default: begin end
endcase // case ( ctrl )
end
// Mux out the carry bit - note that only ADD and SR have any effect on this
// value
always @(*) begin
case ( alu_control )
ADD: begin
alu_carry_out = add_carry_out;
end
SR: begin
alu_carry_out = sr_carry_out;
end
default: begin
alu_carry_out = 1'b0;
end
endcase // case ( alu_control )
end
// Compute the overflow output
always @(*) begin
// The overflow condition is logically
//
// ((NOT A[7] AND NOT B[7]) AND ADD[7]) OR (A[7] AND B[7] AND NOT ADD[7])
//
// Which is equivalent to
//
// (A[7] XNOR B[7]) AND (A[7] XOR ADD[7])
add_overflow = (~(alu_AI[7] ^ alu_BI[7])) & (alu_AI[7] ^ alu_Y[7]);
end
endmodule // alu
|
//altera message_off 10230
`timescale 1 ps / 1 ps
module alt_mem_ddrx_list
# (
// module parameter port list
parameter
CTL_LIST_WIDTH = 3, // number of dram commands that can be tracked at a time
CTL_LIST_DEPTH = 8,
CTL_LIST_INIT_VALUE_TYPE = "INCR", // INCR, ZERO
CTL_LIST_INIT_VALID = "VALID" // VALID, INVALID
)
(
// port list
ctl_clk,
ctl_reset_n,
// pop free list
list_get_entry_valid,
list_get_entry_ready,
list_get_entry_id,
list_get_entry_id_vector,
// push free list
list_put_entry_valid,
list_put_entry_ready,
list_put_entry_id
);
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// pop free list
input list_get_entry_ready;
output list_get_entry_valid;
output [CTL_LIST_WIDTH-1:0] list_get_entry_id;
output [CTL_LIST_DEPTH-1:0] list_get_entry_id_vector;
// push free list
output list_put_entry_ready;
input list_put_entry_valid;
input [CTL_LIST_WIDTH-1:0] list_put_entry_id;
// -----------------------------
// port type declaration
// -----------------------------
reg list_get_entry_valid;
wire list_get_entry_ready;
reg [CTL_LIST_WIDTH-1:0] list_get_entry_id;
reg [CTL_LIST_DEPTH-1:0] list_get_entry_id_vector;
wire list_put_entry_valid;
reg list_put_entry_ready;
wire [CTL_LIST_WIDTH-1:0] list_put_entry_id;
// -----------------------------
// signal declaration
// -----------------------------
reg [CTL_LIST_WIDTH-1:0] list [CTL_LIST_DEPTH-1:0];
reg list_v [CTL_LIST_DEPTH-1:0];
reg [CTL_LIST_DEPTH-1:0] list_vector;
wire list_get = list_get_entry_valid & list_get_entry_ready;
wire list_put = list_put_entry_valid & list_put_entry_ready;
// -----------------------------
// module definition
// -----------------------------
// generate interface signals
always @ (*)
begin
// connect interface signals to list head & tail
list_get_entry_valid = list_v[0];
list_get_entry_id = list[0];
list_get_entry_id_vector = list_vector;
list_put_entry_ready = ~list_v[CTL_LIST_DEPTH-1];
end
// list put & get management
integer i;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
for (i = 0; i < CTL_LIST_DEPTH; i = i + 1'b1)
begin
// initialize every entry
if (CTL_LIST_INIT_VALUE_TYPE == "INCR")
begin
list [i] <= i;
end
else
begin
list [i] <= {CTL_LIST_WIDTH{1'b0}};
end
if (CTL_LIST_INIT_VALID == "VALID")
begin
list_v [i] <= 1'b1;
end
else
begin
list_v [i] <= 1'b0;
end
end
list_vector <= {CTL_LIST_DEPTH{1'b0}};
end
else
begin
// get request code must be above put request code
if (list_get)
begin
// on a get request, list is shifted to move next entry to head
for (i = 1; i < CTL_LIST_DEPTH; i = i + 1'b1)
begin
list_v [i-1] <= list_v [i];
list [i-1] <= list [i];
end
list_v [CTL_LIST_DEPTH-1] <= 0;
for (i = 0; i < CTL_LIST_DEPTH;i = i + 1'b1)
begin
if (i == list [1])
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
end
if (list_put)
begin
// on a put request, next empty list entry is written
if (~list_get)
begin
// put request only
for (i = 1; i < CTL_LIST_DEPTH; i = i + 1'b1)
begin
if ( list_v[i-1] & ~list_v[i])
begin
list_v [i] <= 1'b1;
list [i] <= list_put_entry_id;
end
end
if (~list_v[0])
begin
list_v [0] <= 1'b1;
list [0] <= list_put_entry_id;
for (i = 0; i < CTL_LIST_DEPTH;i = i + 1'b1)
begin
if (i == list_put_entry_id)
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
end
end
else
begin
// put & get request on same cycle
for (i = 1; i < CTL_LIST_DEPTH; i = i + 1'b1)
begin
if (list_v[i-1] & ~list_v[i])
begin
list_v [i-1] <= 1'b1;
list [i-1] <= list_put_entry_id;
end
end
// if (~list_v[0])
// begin
// $display("error - list underflow");
// end
for (i = 0; i < CTL_LIST_DEPTH;i = i + 1'b1)
begin
if (list_v[0] & ~list_v[1])
begin
if (i == list_put_entry_id)
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
else
begin
if (i == list [1])
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
end
end
end
end
end
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize(3, Ofast , inline ) using namespace std; const long long INF(0x3f3f3f3f3f3f3f3fll); const long long inf(0x3f3f3f3f); template <typename T> void read(T &res) { bool flag = false; char ch; while (!isdigit(ch = getchar())) (ch == - ) && (flag = true); for (res = ch - 48; isdigit(ch = getchar()); res = (res << 1) + (res << 3) + ch - 48) ; flag && (res = -res); } template <typename T> void Out(T x) { if (x < 0) putchar( - ), x = -x; if (x > 9) Out(x / 10); putchar(x % 10 + 0 ); } long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } long long lcm(long long a, long long b) { return a * b / gcd(a, b); } long long pow_mod(long long x, long long n, long long mod) { long long res = 1; while (n) { if (n & 1) res = res * x % mod; x = x * x % mod; n >>= 1; } return res; } long long fact_pow(long long n, long long p) { long long res = 0; while (n) { n /= p; res += n; } return res; } long long mult(long long a, long long b, long long p) { a %= p; b %= p; long long r = 0, v = a; while (b) { if (b & 1) { r += v; if (r > p) r -= p; } v <<= 1; if (v > p) v -= p; b >>= 1; } return r; } long long quick_pow(long long a, long long b, long long p) { long long r = 1, v = a % p; while (b) { if (b & 1) r = mult(r, v, p); v = mult(v, v, p); b >>= 1; } return r; } bool CH(long long a, long long n, long long x, long long t) { long long r = quick_pow(a, x, n); long long z = r; for (long long i = 1; i <= t; i++) { r = mult(r, r, n); if (r == 1 && z != 1 && z != n - 1) return true; z = r; } return r != 1; } bool Miller_Rabin(long long n) { if (n < 2) return false; if (n == 2) return true; if (!(n & 1)) return false; long long x = n - 1, t = 0; while (!(x & 1)) { x >>= 1; t++; } srand(time(NULL)); long long o = 8; for (long long i = 0; i < o; i++) { long long a = rand() % (n - 1) + 1; if (CH(a, n, x, t)) return false; } return true; } long long exgcd1(long long a, long long b, long long &x, long long &y) { if (!b) { x = 1, y = 0; return a; } long long t = exgcd1(b, a % b, y, x); y -= a / b * x; return t; } long long get_inv(long long a, long long mod) { long long x, y; long long d = exgcd1(a, mod, x, y); return d == 1 ? (x % mod + mod) % mod : -1; } void exgcd(long long a, long long b, long long &x, long long &y) { if (!b) { x = 1, y = 0; return; } exgcd(b, a % b, x, y); long long t = x; x = y, y = t - (a / b) * y; } long long INV(long long a, long long b) { long long x, y; return exgcd(a, b, x, y), (x % b + b) % b; } long long crt(long long x, long long p, long long mod) { return INV(p / mod, mod) * (p / mod) * x; } long long FAC(long long x, long long a, long long b) { if (!x) return 1; long long ans = 1; for (long long i = 1; i <= b; i++) if (i % a) ans *= i, ans %= b; ans = pow_mod(ans, x / b, b); for (long long i = 1; i <= x % b; i++) if (i % a) ans *= i, ans %= b; return ans * FAC(x / a, a, b) % b; } long long C(long long n, long long m, long long a, long long b) { long long N = FAC(n, a, b), M = FAC(m, a, b), Z = FAC(n - m, a, b), sum = 0, i; for (i = n; i; i = i / a) sum += i / a; for (i = m; i; i = i / a) sum -= i / a; for (i = n - m; i; i = i / a) sum -= i / a; return N * pow_mod(a, sum, b) % b * INV(M, b) % b * INV(Z, b) % b; } long long exlucas(long long n, long long m, long long p) { long long t = p, ans = 0, i; for (i = 2; i * i <= p; i++) { long long k = 1; while (t % i == 0) { k *= i, t /= i; } ans += crt(C(n, m, i, k), p, k), ans %= p; } if (t > 1) ans += crt(C(n, m, t, t), p, t), ans %= p; return ans % p; } const long long N = 1e6 + 10; long long tree[N << 2]; long long n, m; long long a[N], sum[N]; map<long long, long long> pos; long long lowbit(long long x) { return x & (-x); } void add(long long pos, long long val) { while (pos <= n) { tree[pos] ^= val; pos += lowbit(pos); } } long long get(long long pos) { long long res = 0; while (pos) { res ^= tree[pos]; pos -= lowbit(pos); } return res; } long long get_sum(long long l, long long r) { return get(r) ^ get(l - 1); } struct Q { long long l, r, ans, id; bool operator<(const Q &a) const { return r < a.r; } } q[N]; bool cmp(Q a, Q b) { return a.id < b.id; } signed main() { std::ios::sync_with_stdio(false); cin.tie(0), cout.tie(0); cin >> n; for (long long i = 1; i <= n; i++) cin >> a[i], sum[i] = sum[i - 1] ^ a[i]; cin >> m; for (long long i = 1; i <= m; i++) cin >> q[i].l >> q[i].r, q[i].id = i; sort(q + 1, q + 1 + m); long long now = 1; for (long long i = 1; i <= m; i++) { long long l = q[i].l, r = q[i].r, id = q[i].id; while (now <= r) { if (pos[a[now]]) add(pos[a[now]], a[now]); pos[a[now]] = now; add(pos[a[now]], a[now]); now++; } q[i].ans = (sum[r] ^ sum[l - 1]) ^ get_sum(l, r); } sort(q + 1, q + 1 + m, cmp); for (long long i = 1; i <= m; i++) cout << q[i].ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 100; struct node { int x, y; } point[maxn]; bool check(node a, node b, node c, node d) { if (a.x - b.x == c.x - d.x && a.y - b.y == c.y - d.y) return true; return false; } int main() { int n; cin >> n; for (int i = 0; i < n; ++i) cin >> point[i].x >> point[i].y; if (n & 1) { cout << nO << endl; } else { bool flag = true; for (int i = 0; i < n; ++i) { if (!check(point[(i + 1) % n], point[i], point[(i + n / 2) % n], point[(i + n / 2 + 1) % n])) flag = false; } if (flag) cout << YES << endl; else cout << nO << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYMETAL6S2S_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__DLYMETAL6S2S_PP_BLACKBOX_V
/**
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
* horizontal route.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlymetal6s2s (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYMETAL6S2S_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; inline long long add(long long x, long long y) { x += y; if (x >= 1000000007) x -= 1000000007; return x; } inline long long sub(long long x, long long y) { x -= y; if (x < 0) x += 1000000007; return x; } inline long long mul(long long x, long long y) { return ((x % 1000000007) * (y % 1000000007)) % 1000000007; } inline long long pwr(long long a, long long b) { long long x = 1LL; while (b) { if (b & 1) x = mul(x, a); a = mul(a, a); b >>= 1; } return x; } bool CHK(long long n) { if (n == 1) return 0; if (n == 2 or n == 3) return 1; if (n % 2 == 0 or n % 3 == 0) return 0; for (long long i = 5; i * i <= n; i += 6) if (n % i == 0 or n % (i + 2) == 0) return 0; return 1; } int main() { ios_base::sync_with_stdio(false), cin.tie(NULL); long long n = 0; cin >> n; string s; cin >> s; long long cnt = 0; for (long long i = 0; i < n - 1; i++) { if (s[i] == * ) continue; if (s[i] == s[i + 1]) cnt++, s[i + 1] = * ; } cout << cnt << n ; for (long long i = 0; i < n; i++) { if (s[i] == * and i != n - 1) { if (s[i - 1] == R and s[i + 1] == G ) s[i] = B ; else if (s[i - 1] == G and s[i + 1] == B ) s[i] = R ; else if (s[i - 1] == R and s[i + 1] == B ) s[i] = G ; else if (s[i - 1] == R and s[i + 1] == R ) s[i] = G ; else if (s[i - 1] == B and s[i + 1] == B ) s[i] = G ; else if (s[i - 1] == G and s[i + 1] == G ) s[i] = R ; else if (s[i - 1] == G and s[i + 1] == R ) s[i] = B ; else if (s[i - 1] == B and s[i + 1] == G ) s[i] = R ; else if (s[i - 1] == B and s[i + 1] == R ) s[i] = G ; } else if (s[i] == * and i == n - 1) { if (s[i - 1] == R ) s[i] = G ; else if (s[i - 1] == B ) s[i] = G ; else if (s[i - 1] == G ) s[i] = B ; } } for (auto u : s) cout << u; return 0; } |
#include <bits/stdc++.h> using namespace std; unsigned long long n, k, c, a, b, d; multiset<unsigned long long> vn; multiset<unsigned long long> vk; unsigned long long mod = 1e9 + 7; unsigned long long sum = 0; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cin >> n >> k >> c; for (int i = 1; i <= n; i++) { cin >> a >> b; vn.insert(a), vk.insert(b); d = c * (b - a); sum = (sum + d) % mod; } multiset<unsigned long long>::iterator it; while (vn.size() > 0 && vk.size() > 0) { if (*vn.begin() <= *vk.begin()) { sum = (k + sum) % mod; vn.erase(vn.find(*vn.begin())); } else { if ((*vn.begin() - *vk.begin()) * c < k) { int t; for (it = vk.begin(); it != vk.end(); it++) { if ((*it) >= *vn.begin()) break; t = (*it); } sum = (sum + (*vn.begin() - t) * c) % mod; vn.erase(vn.find(*vn.begin())); vk.erase(vk.find(t)); } else { vk.erase(*vk.begin()); } } } cout << sum % mod << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int a[1010]; int main() { int n, k; scanf( %d%d , &n, &k); for (int i = 0; i < n; i++) scanf( %d , &a[i]); sort(a, a + n); int ans = 0; for (int i = 0; i < n; i++) { if (a[i] <= k * 2) { k = max(k, a[i]); continue; } else { k = k * 2; ans++; i--; } } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> int const maxl = 22; int const maxm = 2520; long long f[maxl][maxm + 4][50][2]; int a[maxl]; std::vector<int> alcm; long long plcm[maxm + 4][10]; long long kth[maxm + 4]; long long l, r; int gcd(int x, int y) { return !y ? x : gcd(y, x % y); } int lcm(int x, int y) { if (!x) return y; if (!y) return x; return x * y / gcd(x, y); } void init() { for (int i2 = 0, t2 = 1; i2 < 4; i2++, t2 *= 2) for (int i3 = 0, t3 = 1; i3 < 3; i3++, t3 *= 3) for (int i5 = 0, t5 = 1; i5 < 2; i5++, t5 *= 5) for (int i7 = 0, t7 = 1; i7 < 2; i7++, t7 *= 7) alcm.push_back(t2 * t3 * t5 * t7); std::sort(alcm.begin(), alcm.end()); for (int i = 0; i <= maxm; i++) for (int j = 0; j < 10; j++) plcm[i][j] = lcm(i, j); for (int i = 0; i < (int)alcm.size(); i++) kth[alcm[i]] = i; } int get_len(long long x) { int ret = 0; for (; x; x /= 10) a[ret++] = x % 10; return ret; } long long calc(long long x) { int n = get_len(x); for (int i = 0; i <= n; i++) for (int j = 0; j < maxm; j++) for (int k = 0; k < (int)alcm.size(); k++) for (int l = 0; l < 2; l++) f[i][j][k][l] = 0; f[0][0][0][0] = 1; for (int i = 0; i < n; i++) for (int j = 0; j < maxm; j++) for (int k = 0; k < (int)alcm.size(); k++) for (int l = 0; l < 2; l++) { if (!f[i][j][k][l]) continue; int up = (l ? 9 : a[n - i - 1]); for (int ti = 0; ti <= up; ti++) { int last = l || (ti < a[n - i - 1]); f[i + 1][(j * 10 + ti) % maxm][kth[plcm[alcm[k]][ti]]][last] += f[i][j][k][l]; } } long long ans = 0; for (int i = 0; i < maxm; i++) for (int k = 0; k < (int)alcm.size(); k++) for (int l = 0; l < 2; l++) if (!(i % alcm[k])) ans += f[n][i][k][l]; return ans; } int main() { std::ios::sync_with_stdio(false); init(); int T; std::cin >> T; while (T--) { std::cin >> l >> r; std::cout << calc(r) - calc(l - 1) << n ; } } |
#include <bits/stdc++.h> using namespace std; long long vis[1009]; vector<long long> v[1000]; long long th, n; void dfs(long long s) { if (vis[s]) return; vis[s] = 1; for (long long i = 0; i < v[s].size(); i++) { if (s <= n) th++; dfs(v[s][i]); } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long i, j, k, m, l, a, prothom = 1, kake, ans = 0; cin >> n >> m; for (i = 1; i <= n; i++) { cin >> k; while (k--) { cin >> a; v[a + n].push_back(i); v[i].push_back(a + n); } } for (i = 1; i <= n; i++) { if (vis[i] == 0) { ans++; dfs(i); } } if (ans == n && th == 0) cout << n << endl; else cout << ans - 1 << endl; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPMET1_PP_SYMBOL_V
`define SKY130_FD_SC_HS__TAPMET1_PP_SYMBOL_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__tapmet1 (
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPMET1_PP_SYMBOL_V
|
#include <bits/stdc++.h> int findMaximalK(int n); using namespace std; int main() { int n, b, p, x, y; cin >> n >> b >> p; y = n * p; x = 0; int remaining = n; while (remaining > 1) { int doingMatch = pow(2, findMaximalK(remaining)); x += doingMatch * b + doingMatch / 2; int passToNextRound = remaining - doingMatch / 2; remaining = passToNextRound; } cout << x << << y; } int findMaximalK(int n) { int count = 0; while (n > 1) { n /= 2; count++; } return count; } |
#include <bits/stdc++.h> using namespace std; int N; bool indegree[200010]; int a[200010]; bool visited[200010]; vector<pair<int, int> > ans; int main() { int i, j, k; scanf( %d , &N); for (i = (0); i < (N); i++) scanf( %d , a + i); for (i = (0); i < (N); i++) a[i]--; memset((visited), 0, sizeof(visited)); ; memset((indegree), 0, sizeof(indegree)); ; for (i = (0); i < (N); i++) indegree[a[i]] = true; bool f = false; for (i = (0); i < (N); i++) { if (indegree[i]) continue; f = true; int x = i; while (!visited[x]) { visited[x] = true; indegree[x] = true; x = a[x]; } ans.push_back(make_pair(i, x)); } for (i = (0); i < (N); i++) { if (visited[i]) continue; int x = i; while (!visited[x]) { visited[x] = true; x = a[x]; } ans.push_back(make_pair(i, i)); } if (!f && ans.size() < 2) { printf( 0 n ); return 0; } ans.push_back(ans[0]); printf( %d n , ans.size() - 1); for (i = (0); i < (ans.size() - 1); i++) printf( %d %d n , ans[i].second + 1, ans[i + 1].first + 1); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = (int)1e5 + 5; int n; pair<long long, int> t[N]; long long tree[4 * N], dp[N], v[N]; int rnk[N]; inline void update(int idx, long long val, int st, int en, int root) { if (idx < st || idx > en) return; if (st == en) { tree[root] = max(tree[root], val); return; } int mid = (st + en) >> 1; update(idx, val, st, mid, root * 2); update(idx, val, mid + 1, en, root * 2 + 1); tree[root] = max(tree[root * 2], tree[root * 2 + 1]); } inline long long query(int L, int R, int st, int en, int root) { if (L > en || R < st) return 0; if (st >= L && en <= R) return tree[root]; int mid = (st + en) >> 1; return max(query(L, R, st, mid, root * 2), query(L, R, mid + 1, en, root * 2 + 1)); } map<long long, int> m; int main() { cin >> n; for (int i = 0; i < n; i++) { int h, r; scanf( %d %d , &r, &h); v[i] = 1LL * r * r * h; m[v[i]]; } int id = 0; for (auto &x : m) x.second = id++; for (int i = 0; i < n; i++) { int rnk = m[v[i]]; dp[i] = v[i]; long long best = query(0, rnk - 1, 0, n - 1, 1); dp[i] += best; update(rnk, dp[i], 0, n - 1, 1); } long long ret = 0; for (int i = 0; i < n; i++) ret = max(ret, dp[i]); cout << fixed << setprecision(12) << acos(-1) * ret << n ; } |
#include <bits/stdc++.h> using namespace std; const int N = 1000010; int pre[N], rak[N]; int find(int first) { if (pre[first] == -1) return first; return pre[first] = find(pre[first]); } void unions(int first, int second) { first = find(first); second = find(second); if (first == second) return; if (rak[first] < rak[second]) swap(first, second); rak[first] += rak[second]; pre[second] = first; } vector<pair<int, int> > rows[N], col[N]; void scc(int n, int m) { memset(pre, -1, sizeof(pre)); fill(rak, rak + N, 1); for (int i = 1; i <= n; i++) { sort(rows[i].begin(), rows[i].end()); for (int j = 1; j < m; j++) { if (rows[i][j - 1].first == rows[i][j].first) unions((i - 1) * m + rows[i][j - 1].second, (i - 1) * m + rows[i][j].second); } } for (int j = 1; j <= m; j++) { sort(col[j].begin(), col[j].end()); for (int i = 1; i < n; i++) { if (col[j][i - 1].first == col[j][i].first) unions((col[j][i - 1].second - 1) * m + j, (col[j][i].second - 1) * m + j); } } } vector<int> edges[N]; int deg[N], ans[N]; stack<int> stk; void topo(int n, int m) { for (int i = 1; i <= n; i++) { for (int j = 1; j < m; j++) { if (rows[i][j - 1].first < rows[i][j].first) { int first = find((i - 1) * m + rows[i][j - 1].second); int second = find((i - 1) * m + rows[i][j].second); edges[first].push_back(second); deg[second]++; } } } for (int j = 1; j <= m; j++) { for (int i = 1; i < n; i++) { if (col[j][i - 1].first < col[j][i].first) { int first = find((col[j][i - 1].second - 1) * m + j); int second = find((col[j][i].second - 1) * m + j); edges[first].push_back(second); deg[second]++; } } } n = n * m; for (int i = 1; i <= n; i++) if (!deg[i] && pre[i] == -1) stk.push(i), ans[i] = 1; while (!stk.empty()) { int u = stk.top(); stk.pop(); for (int i = 0; i < edges[u].size(); i++) { int first = edges[u][i]; ans[first] = max(ans[first], ans[u] + 1); deg[first]--; if (!deg[first]) stk.push(first); } } } int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 1, first; i <= n; i++) { for (int j = 1; j <= m; j++) { scanf( %d , &first); rows[i].push_back(make_pair(first, j)); col[j].push_back(make_pair(first, i)); } } scc(n, m); topo(n, m); for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { printf( %d%c , ans[find((i - 1) * m + j)], (j == m) ? n : ); } } return 0; } |
// test_simulation_techmap_and_19_tech.v
module f1_TECH_AND18(input [17:0] in, output out);
assign out = ∈
endmodule
module f1_TECH_AND4(input [3:0] in, output out);
assign out = ∈
endmodule
// test_simulation_techmap_and_5_tech.v
module f2_TECH_AND5(input [4:0] in, output out);
assign out = ∈
endmodule
// test_simulation_techmap_nand_19_tech.v
module f3_TECH_NAND18(input [17:0] in, output out);
assign out = ~(&in);
endmodule
module f3_TECH_NAND4(input [3:0] in, output out);
assign out = ~(&in);
endmodule
module f3_TECH_NAND2(input [1:0] in, output out);
assign out = ~(&in);
endmodule
// test_simulation_techmap_nand_2_tech.v
module f4_TECH_NAND18(input [17:0] in, output out);
assign out = ~(&in);
endmodule
module f4_TECH_NAND4(input [3:0] in, output out);
assign out = ~(&in);
endmodule
module f4_TECH_NAND2(input [1:0] in, output out);
assign out = ~(&in);
endmodule
// test_simulation_techmap_nand_5_tech.v
module f5_TECH_NAND18(input [17:0] in, output out);
assign out = ~(&in);
endmodule
module f5_TECH_NAND4(input [3:0] in, output out);
assign out = ~(&in);
endmodule
module f5_TECH_NAND2(input [1:0] in, output out);
assign out = ~(&in);
endmodule
// test_simulation_techmap_nor_19_tech.v
module f6_TECH_NOR18(input [17:0] in, output out);
assign out = ~(|in);
endmodule
module f6_TECH_NOR4(input [3:0] in, output out);
assign out = ~(|in);
endmodule
module f6_TECH_NOR2(input [1:0] in, output out);
assign out = ~(|in);
endmodule
// test_simulation_techmap_nor_2_tech.v
module f7_TECH_NOR18(input [17:0] in, output out);
assign out = ~(|in);
endmodule
module f7_TECH_NOR4(input [3:0] in, output out);
assign out = ~(|in);
endmodule
module f7_TECH_NOR2(input [1:0] in, output out);
assign out = ~(|in);
endmodule
// test_simulation_techmap_nor_5_tech.v
module f8_TECH_NOR18(input [17:0] in, output out);
assign out = ~(|in);
endmodule
module f8_TECH_NOR4(input [3:0] in, output out);
assign out = ~(|in);
endmodule
module f8_TECH_NOR2(input [1:0] in, output out);
assign out = ~(|in);
endmodule
// test_simulation_techmap_or_19_tech.v
module f9_TECH_OR18(input [17:0] in, output out);
assign out = |in;
endmodule
module f9_TECH_OR4(input [3:0] in, output out);
assign out = |in;
endmodule
// test_simulation_techmap_or_5_tech.v
module f10_TECH_OR5(input [4:0] in, output out);
assign out = |in;
endmodule
// test_simulation_techmap_xnor_2_tech.v
module f11_TECH_XOR5(input [4:0] in, output out);
assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4];
endmodule
module f11_TECH_XOR2(input [1:0] in, output out);
assign out = in[0] ^ in[1];
endmodule
// test_simulation_techmap_xnor_5_tech.v
module f12_TECH_XOR5(input [4:0] in, output out);
assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4];
endmodule
module f12_TECH_XOR2(input [1:0] in, output out);
assign out = in[0] ^ in[1];
endmodule
// test_simulation_techmap_xor_19_tech.v
module f13_TECH_XOR2(input [1:0] in, output out);
assign out = in[0] ^ in[1];
endmodule
// test_simulation_techmap_xor_2_tech.v
module f14_TECH_XOR5(input [4:0] in, output out);
assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4];
endmodule
module f14_TECH_XOR2(input [1:0] in, output out);
assign out = in[0] ^ in[1];
endmodule
// test_simulation_techmap_xor_5_tech.v
module f15_TECH_XOR5(input [4:0] in, output out);
assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4];
endmodule
module f15_TECH_XOR2(input [1:0] in, output out);
assign out = in[0] ^ in[1];
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKBUF_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__CLKBUF_FUNCTIONAL_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__clkbuf (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKBUF_FUNCTIONAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:19:08 12/01/2010
// Design Name:
// Module Name: sd_dma
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sd_dma(
input [3:0] SD_DAT,
inout SD_CLK,
input CLK,
input SD_DMA_EN,
output SD_DMA_STATUS,
output SD_DMA_SRAM_WE,
output SD_DMA_NEXTADDR,
output [7:0] SD_DMA_SRAM_DATA,
input SD_DMA_PARTIAL,
input [10:0] SD_DMA_PARTIAL_START,
input [10:0] SD_DMA_PARTIAL_END
);
reg [10:0] SD_DMA_STARTr;
reg [10:0] SD_DMA_ENDr;
reg SD_DMA_PARTIALr;
always @(posedge CLK) SD_DMA_PARTIALr <= SD_DMA_PARTIAL;
reg SD_DMA_DONEr;
reg[1:0] SD_DMA_DONEr2;
initial begin
SD_DMA_DONEr2 = 2'b00;
SD_DMA_DONEr = 1'b0;
end
always @(posedge CLK) SD_DMA_DONEr2 <= {SD_DMA_DONEr2[0], SD_DMA_DONEr};
wire SD_DMA_DONE_rising = (SD_DMA_DONEr2[1:0] == 2'b01);
reg [1:0] SD_DMA_ENr;
initial SD_DMA_ENr = 2'b00;
always @(posedge CLK) SD_DMA_ENr <= {SD_DMA_ENr[0], SD_DMA_EN};
wire SD_DMA_EN_rising = (SD_DMA_ENr [1:0] == 2'b01);
reg SD_DMA_STATUSr;
assign SD_DMA_STATUS = SD_DMA_STATUSr;
reg SD_DMA_CLKMASKr = 1'b1;
// we need 1042 cycles (startbit + 1024 nibbles + 16 crc + stopbit)
reg [10:0] cyclecnt;
initial cyclecnt = 11'd0;
reg SD_DMA_SRAM_WEr;
initial SD_DMA_SRAM_WEr = 1'b1;
assign SD_DMA_SRAM_WE = (cyclecnt < 1025 && SD_DMA_STATUSr) ? SD_DMA_SRAM_WEr : 1'b1;
reg SD_DMA_NEXTADDRr;
assign SD_DMA_NEXTADDR = (cyclecnt < 1025 && SD_DMA_STATUSr) ? SD_DMA_NEXTADDRr : 1'b0;
reg[7:0] SD_DMA_SRAM_DATAr;
assign SD_DMA_SRAM_DATA = SD_DMA_SRAM_DATAr;
// we have 4 internal cycles per SD clock, 8 per RAM byte write
reg [2:0] clkcnt;
initial clkcnt = 3'b000;
reg [1:0] SD_CLKr;
initial SD_CLKr = 2'b11;
always @(posedge CLK)
if(SD_DMA_EN_rising) SD_CLKr <= 2'b11;
else SD_CLKr <= {SD_CLKr[0], clkcnt[1]};
assign SD_CLK = SD_DMA_CLKMASKr ? 1'bZ : SD_CLKr[1];
always @(posedge CLK) begin
if(SD_DMA_EN_rising) begin
SD_DMA_STATUSr <= 1'b1;
SD_DMA_STARTr <= (SD_DMA_PARTIALr ? SD_DMA_PARTIAL_START : 11'h0);
SD_DMA_ENDr <= (SD_DMA_PARTIALr ? SD_DMA_PARTIAL_END : 11'd1024);
end
else if (SD_DMA_DONE_rising) SD_DMA_STATUSr <= 1'b0;
end
always @(posedge CLK) begin
if(SD_DMA_EN_rising) begin
SD_DMA_CLKMASKr <= 1'b0;
end
else if (SD_DMA_DONEr) begin
SD_DMA_CLKMASKr <= 1'b1;
end
end
always @(posedge CLK) begin
if(cyclecnt == 1042) SD_DMA_DONEr <= 1;
else SD_DMA_DONEr <= 0;
end
always @(posedge CLK) begin
if(SD_DMA_EN_rising || !SD_DMA_STATUSr) begin
clkcnt <= 0;
end else begin
if(SD_DMA_STATUSr) begin
clkcnt <= clkcnt + 1;
end
end
end
always @(posedge CLK) begin
if(SD_DMA_EN_rising || !SD_DMA_STATUSr) cyclecnt <= 0;
else if(clkcnt[1:0] == 2'b10) cyclecnt <= cyclecnt + 1;
end
// we have 8 clk cycles to complete one RAM write
// (4 clk cycles per SD_CLK; 2 SD_CLK cycles per byte)
always @(posedge CLK) begin
if(SD_DMA_STATUSr) begin
case(clkcnt[2:0])
3'h0: begin
SD_DMA_SRAM_DATAr[7:4] <= SD_DAT;
if(cyclecnt>SD_DMA_STARTr && cyclecnt <= SD_DMA_ENDr) SD_DMA_NEXTADDRr <= 1'b1;
end
3'h1:
SD_DMA_NEXTADDRr <= 1'b0;
3'h2:
if(cyclecnt>=SD_DMA_STARTr && cyclecnt < SD_DMA_ENDr) SD_DMA_SRAM_WEr <= 1'b0;
// 3'h3:
3'h4:
SD_DMA_SRAM_DATAr[3:0] <= SD_DAT;
// 3'h5:
// 3'h6:
3'h7:
SD_DMA_SRAM_WEr <= 1'b1;
endcase
end
end
endmodule
|
module LcdBridge(rst_n, clk, rs, rw, e, d, cs, sck, mosi, miso);
input rst_n, clk, cs, sck, mosi;
output rs, rw, e, miso;
// d is bidirectional port
inout [7:0] d;
wire [7:0] outData;
wire dFlag; // if dFlag == 1, d is output
assign d = dFlag ? outData : 8'bzzzz_zzzz;
wire [7:0] ctl, data, ret_data;
wire divClk;
ClockGenerator gen(rst_n, clk, divClk);
LcdController lcd(rst_n, divClk, cs, ctl, dFlag, d, outData, rs, rw, e, data, ret_data);
SpiSlave spi(rst_n, cs, sck, mosi, miso, ctl, data, ret_data);
endmodule
// divide clk
module ClockGenerator(rst_n, clk, divClk);
input rst_n, clk;
output reg divClk;
parameter clkDiv = 8'b0001_1111; // clkDiv = 32, 64fs
reg [7:0] clkCount;
always @(posedge clk)
begin
if (~rst_n)
begin
divClk <= 1'b0;
clkCount <= 8'b0;
end
else if (clkCount == clkDiv)
begin
divClk <= ~divClk;
clkCount <= 8'b0;
end
else
clkCount <= clkCount + 8'b1;
end
endmodule
// LCD Controller
module LcdController(rst_n, clk, trigger, ctl, dFlag, in_d, out_d, rs, rw, e, data, ret_data);
input rst_n, clk, trigger;
input [7:0] ctl, data;
output reg rs, rw, e;
output reg [7:0] ret_data;
// bidirectional port
output reg dFlag;
input [7:0] in_d;
output reg [7:0] out_d;
reg [4:0] tsp1;
parameter minTsp1 = 30;
reg [7:0] tpw;
parameter minTpw = 150;
reg [3:0] thd;
parameter minThd = 20;
reg [3:0] trest;
parameter minTrest = 250;
// FSM
// general
parameter sIdle = 4'b0000;
// write
parameter sWriteSetup = 4'b0010;
parameter sWriteEnable = 4'b0011;
parameter sWriteDisable = 4'b0100;
parameter sWriteRelease = 4'b0101;
// read
parameter sReadSetup = 4'b0110;
parameter sReadEnable = 4'b0111;
parameter sReadDisable = 4'b1000;
parameter sReadRelease = 4'b1001;
// states
reg [3:0] nextState;
reg [3:0] prevState;
// output setup for states
always @(posedge clk)
begin
if (rst_n)
begin
case (prevState)
sIdle:
begin
rs <= 1'b0; // cmd
rw <= 1'b1; // write
e <= 1'b0; // disable
dFlag <= 1'b1; // output d
out_d <= 8'b0000_0000;
end
sWriteSetup:
begin
rs <= ctl[1];
rw <= ctl[0]; // this should be 1 here
e <= 1'b0;
dFlag <= 1'b1; // output d
out_d <= data; // write to d
end
sWriteEnable:
begin
rs <= ctl[1];
rw <= ctl[0]; // this should be 1 here
e <= 1'b1; // enable
dFlag <= 1'b1; // output d
out_d <= data; // write to d
end
sWriteDisable:
begin
rs <= ctl[1];
rw <= ctl[0]; // this should be 1 here
e <= 1'b0; // disable
dFlag <= 1'b1; // output d
out_d <= data; // write to d
end
sWriteRelease:
begin
rs <= 1'b0; // cmd
rw <= 1'b1; // write
e <= 1'b0;
dFlag <= 1'b1; // output d
out_d <= 8'b0000_0000;
end
sReadSetup:
begin
rs <= ctl[1];
rw <= ctl[0]; // should be 0 here
e <= 1'b0;
dFlag <= 1'b0; // input d
out_d <= 8'b0000_0000;
end
sReadEnable:
begin
rs <= ctl[1];
rw <= ctl[0]; // should be 0 here
e <= 1'b1;
dFlag <= 1'b0; // input d
out_d <= 8'b0000_0000;
end
sReadDisable:
begin
rs <= ctl[1];
rw <= ctl[0]; // should be 0 here
e <= 1'b0;
ret_data <= in_d; // read from d, TO DO: switch to dff
dFlag <= 1'b0; // input d
out_d <= 8'b0000_0000;
end
sReadRelease:
begin
rs <= 1'b0; // cmd
rw <= 1'b1; // write
e <= 1'b0;
dFlag <= 1'b1; // output d
out_d <= 8'b0000_0000;
end
endcase
end
end
// FSM
always @(posedge clk)
if (rst_n)
begin
case (prevState)
sIdle:
begin
if (trigger)
if (ctl[0])
nextState <= sWriteSetup;
else
nextState <= sReadSetup;
else
nextState <= sIdle;
end
sWriteSetup:
begin
if (tsp1 == 5'b0)
begin
tsp1 <= minTsp1;
nextState <= sWriteEnable;
end
else
begin
tsp1 <= tsp1 - 5'b1;
nextState <= sWriteSetup;
end
end
sWriteEnable:
begin
if (tpw == 8'b0)
begin
tpw <= minTpw;
nextState <= sWriteDisable;
end
else
begin
tpw <= tpw - 8'b1;
nextState <= sWriteEnable;
end
end
sWriteDisable:
begin
if (thd == 4'b0)
begin
thd <= minThd;
nextState <= sWriteRelease;
end
else
begin
thd <= thd - 4'b1;
nextState <= sWriteDisable;
end
end
sWriteRelease:
begin
if (trest == 4'b0)
begin
trest <= minTrest;
nextState <= sIdle;
end
else
begin
trest <= trest - 4'b1;
nextState <= sWriteRelease;
end
end
sReadSetup:
begin
if (tsp1 == 5'b0)
begin
tsp1 <= minTsp1;
nextState <= sReadEnable;
end
else
begin
tsp1 <= tsp1 - 5'b1;
nextState <= sReadSetup;
end
end
sReadEnable:
begin
if (tpw == 8'b0)
begin
tpw <= minTpw;
nextState <= sReadDisable;
end
else
begin
tpw <= tpw - 8'b1;
nextState <= sReadEnable;
end
end
sReadDisable:
begin
if (thd == 4'b0)
begin
thd <= minThd;
nextState <= sReadRelease;
end
else
begin
thd <= thd - 4'b1;
nextState <= sReadDisable;
end
end
sReadRelease:
begin
if (trest == 4'b0)
begin
trest <= minTrest;
nextState <= sIdle;
end
else
begin
trest <= trest - 4'b1;
nextState <= sReadRelease;
end
end
endcase
end
// state trigger
always @(posedge clk)
begin
if (~rst_n)
prevState <= sIdle;
else
prevState <= nextState;
end
endmodule
module SpiSlave(rst_n, cs, sck, mosi, miso, ctl, data, ret_data);
input rst_n, cs, sck, mosi;
input [7:0] ret_data;
output reg [7:0] ctl, data;
output reg miso;
reg [3:0] i;
reg [2:0] j;
always @(negedge rst_n or posedge cs or negedge sck)
begin
if (~rst_n)
begin
miso <= 1'b0;
i <= 4'b1111;
j <= 3'b111;
end
else if (cs)
begin
miso <= 1'b0;
i <= 4'b1111;
j <= 3'b111;
end
else if (i > 4'b0111)
begin
miso <= 1'b0;
ctl[j] <= mosi;
j <= j - 3'b1;
i <= i - 4'b1;
end
else
begin
miso <= ret_data[i];
data[i] <= mosi;
i <= i - 4'b1;
end
end
endmodule
|
#include <bits/stdc++.h> template <typename C> int sz(const C &c) { return c.size(); } using namespace std; int main() { iostream::sync_with_stdio(false); int64_t n; cin >> n; int k; cin >> k; int64_t maxV = 0; int maxI = 1; int64_t maxC = 0; for (int i = 1; i <= k; ++i) { int64_t a; cin >> a; if (a * (n / a) > maxV) { maxV = a * (n / a); maxI = i; maxC = n / a; } } cout << maxI << << maxC << n ; } |
#include <bits/stdc++.h> using namespace std; struct _IO { _IO() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); } } _io; const long long maxn = 3e5 + 10, mod = 1e9 + 7; template <typename... T> long long madd(T... args) { long long res = 0; for (auto i : {args...}) { res = (res + ((i % mod + mod) % mod)) % mod; } return res % mod; } template <typename... T> long long mmul(T... args) { long long res = 1; for (auto i : {args...}) { res = (res * ((i % mod + mod) % mod)) % mod; } return res % mod; } long long qpow(long long a, long long b) { long long res = 1; while (b) { if (b & 1) res *= a; a *= a; b >>= 1; } return res; } long long mpow(long long a, long long b) { long long res = 1; while (b) { if (b & 1) res = (res * a) % mod; a = (a * a) % mod; b >>= 1; } return res % mod; } long long _inv(long long x) { return mpow(x, mod - 2); } long long dsufa[maxn], fa[maxn], cnt[maxn]; vector<pair<long long, long long> > query; vector<long long> edge[maxn]; deque<long long> res; long long findfa(long long x) { return x == dsufa[x] ? x : (dsufa[x] = findfa(dsufa[x])); } bool mer(long long x, long long y) { x = findfa(x); y = findfa(y); if (x == y) return 0; dsufa[x] = y; return 1; } void dfs(long long u, long long p) { for (auto v : edge[u]) { if (v == p) continue; fa[v] = u; dfs(v, u); } } void path(long long x, long long y) { deque<long long> a(1, x), b(1, y); res.clear(); while (fa[x] != x) { x = fa[x]; a.push_front(x); } while (fa[y] != y) { y = fa[y]; b.push_front(y); } long long len = min(a.size(), b.size()); long long idx = 0; for (; idx < len && a[idx] == b[idx]; ++idx) ; res.push_back(a[idx - 1]); for (long long i = idx; i < b.size(); ++i) res.push_back(b[i]); for (long long i = idx; i < a.size(); ++i) res.push_front(a[i]); } void solve() { long long n, m; cin >> n >> m; for (long long i = 1; i <= n; ++i) dsufa[i] = i; for (long long i = 1; i <= m; ++i) { long long x, y; cin >> x >> y; if (mer(x, y)) { edge[x].push_back(y); edge[y].push_back(x); } } dfs(1, 1); long long q; cin >> q; for (long long i = 1; i <= q; ++i) { long long x, y; cin >> x >> y; query.push_back({x, y}); ++cnt[x]; ++cnt[y]; } bool ok = 1; long long oddcnt = 0; for (long long i = 1; i <= n; ++i) { if (cnt[i] & 1) { ok = 0; ++oddcnt; } } if (!ok) { cout << NO n ; cout << oddcnt / 2 << n ; } else { cout << YES n ; for (auto vec : query) { long long x = vec.first, y = vec.second; path(x, y); cout << res.size() << n ; for (long long i = 0; i < res.size(); ++i) cout << res[i] << n [i == (long long)res.size() - 1]; } } } int main() { long long T = 1; while (T--) solve(); return 0; } |
`timescale 1ns/1ps
module SensorFSM #(
parameter DataWidth = 8
) (
input Reset_n_i,
input Clk_i,
// top level
input Enable_i,
output reg CpuIntr_o,
output [2*DataWidth-1:0] SensorValue_o,
// to/from Measure-FSM
output reg MeasureFSM_Start_o,
input MeasureFSM_Done_i,
input [DataWidth-1:0] MeasureFSM_Byte0_i,
input [DataWidth-1:0] MeasureFSM_Byte1_i,
// parameters
input [2*DataWidth-1:0] ParamThreshold_i,
input [2*DataWidth-1:0] ParamCounterPreset_i
);
// Sensor FSM
localparam stDisabled = 2'b00;
localparam stIdle = 2'b01;
localparam stXfer = 2'b10;
localparam stNotify = 2'b11;
reg [1:0] SensorFSM_State;
reg [1:0] SensorFSM_NextState;
wire SensorFSM_TimerOvfl;
reg SensorFSM_TimerPreset;
reg SensorFSM_TimerEnable;
wire SensorFSM_DiffTooLarge;
reg SensorFSM_StoreNewValue;
/////////////////////////////////////////////////////////////////////////////
// Word Arithmetic
// interconnecting signals
wire [2*DataWidth-1:0] SensorValue;
reg [2*DataWidth-1:0] Word0;
wire [2*DataWidth-1:0] AbsDiffResult;
/////////////////////////////////////////////////////////////////////////////
// FSM //////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
SensorFSM_State <= stDisabled;
end
else
begin
SensorFSM_State <= SensorFSM_NextState;
end
end
always @(SensorFSM_State, Enable_i, SensorFSM_TimerOvfl, MeasureFSM_Done_i, SensorFSM_DiffTooLarge)
begin // process SensorFSM_CombProc
SensorFSM_NextState = SensorFSM_State;
// control signal default values
SensorFSM_TimerPreset = 1'b1;
SensorFSM_TimerEnable = 1'b0;
MeasureFSM_Start_o = 1'b0;
SensorFSM_StoreNewValue = 1'b0;
CpuIntr_o = 1'b0;
// next state and output logic
case (SensorFSM_State)
stDisabled: begin
if (Enable_i == 1'b1)
begin
SensorFSM_NextState = stIdle;
SensorFSM_TimerPreset = 1'b0;
SensorFSM_TimerEnable = 1'b1; // start timer
end
end
stIdle: begin
SensorFSM_TimerPreset = 1'b0;
SensorFSM_TimerEnable = 1'b1; // timer running
if (Enable_i == 1'b0)
begin
SensorFSM_NextState = stDisabled;
end
else
if (SensorFSM_TimerOvfl == 1'b1)
begin
SensorFSM_NextState = stXfer;
MeasureFSM_Start_o = 1'b1;
end
end
stXfer: begin
if (MeasureFSM_Done_i == 1'b1)
begin
if (SensorFSM_DiffTooLarge == 1'b1)
begin
SensorFSM_NextState = stNotify;
SensorFSM_TimerPreset = 1'b0;
SensorFSM_TimerEnable = 1'b1; // timer running
SensorFSM_StoreNewValue = 1'b1; // store new value
end
else
begin
SensorFSM_NextState = stIdle;
end
end
end
stNotify: begin
SensorFSM_TimerPreset = 1'b1;
SensorFSM_TimerEnable = 1'b0; // preset timer
SensorFSM_NextState = stIdle;
CpuIntr_o = 1'b1; // notify CPU
end
default: begin
end
endcase
end
/////////////////////////////////////////////////////////////////////////////
// Word Arithmetic //////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
reg [2*DataWidth-1:0] SensorFSM_Timer;
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
SensorFSM_Timer <= 16'd0;
end
else
begin
if (SensorFSM_TimerPreset)
begin
SensorFSM_Timer <= ParamCounterPreset_i;
end
else if (SensorFSM_TimerEnable)
begin
SensorFSM_Timer <= SensorFSM_Timer - 1'b1;
end
end
end
assign SensorFSM_TimerOvfl = (SensorFSM_Timer == 0) ? 1'b1 : 1'b0;
assign SensorValue = {MeasureFSM_Byte1_i, MeasureFSM_Byte0_i};
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
Word0 <= 16'd0;
end
else
begin
if (SensorFSM_StoreNewValue)
begin
Word0 <= SensorValue;
end
end
end
wire [2*DataWidth : 0] DiffAB;
wire [2*DataWidth-1 : 0] DiffBA;
assign DiffAB = {1'b0, SensorValue} - {1'b0, Word0};
assign DiffBA = Word0 - SensorValue;
assign AbsDiffResult = DiffAB[2*DataWidth] ? DiffBA : DiffAB[2*DataWidth-1 : 0];
assign SensorFSM_DiffTooLarge = (AbsDiffResult > ParamThreshold_i) ? 1'b1 : 1'b0;
assign SensorValue_o = Word0;
endmodule // SensorFSM
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__FILL_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__FILL_PP_SYMBOL_V
/**
* fill: Fill cell.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__fill (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__FILL_PP_SYMBOL_V
|
`include "bsg_defines.v"
module bsg_mem_1rw_sync_mask_write_var #
(parameter `BSG_INV_PARAM(width_p)
,parameter `BSG_INV_PARAM(mask_width_p)
,parameter `BSG_INV_PARAM(els_p)
,parameter chunk_size_lp = width_p / mask_width_p
,parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p))
(input clk_i
,input reset_i
,input [width_p-1:0] data_i
,input [width_p-1:0] w_mask_i
,input [addr_width_lp-1:0] addr_i
,input v_i
,input w_i
,output [width_p-1:0] data_o);
always_ff @(posedge clk_i)
assert((width_p % mask_width_p) == 0)
else $error("%m: partial masking is not supported");
genvar i;
for (i = 0; i < chunk_size_lp; i++) begin
bsg_mem_1rw_sync #
(.width_p(mask_width_p)
,.els_p(els_p))
mem
(.clk_i(clk_i)
,.reset_i(reset_i)
,.data_i(data_i[(i+1)*mask_width_p-1:i*mask_width_p])
,.addr_i(addr_i)
,.v_i(v_i)
,.w_i(w_i & w_mask_i[i*mask_width_p])
,.data_o(data_o[(i+1)*mask_width_p-1:i*mask_width_p]));
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1rw_sync_mask_write_var)
|
#include <bits/stdc++.h> using namespace std; int n = 0, a, tc; int p[100005]; vector<int> cho[6][100005]; int sum[6]; int ret = 0; void doit(int x, int cur) { if (x == n - 1) { ret += cho[x + 5 - n][cur].size(); return; } for (int i = 0; i < cho[x + 5 - n][cur].size(); i++) { int ti = cho[x + 5 - n][cur][i]; for (int j = 0; j < n - x - 1; j++) { sum[n - 1 - j] = sum[n - 1 - j] * 10 + ti % 10; ti /= 10; } doit(x + 1, sum[x + 1]); for (int j = 0; j < n - x - 1; j++) { sum[n - 1 - j] /= 10; } } } int main() { scanf( %d , &tc); for (int i = 0; i <= 100000; i++) p[i] = 1; p[0] = p[1] = 0; for (int i = 2; i <= 100000; i++) if (p[i] == 1) { int ti = i; for (int j = 0; j < 5; j++) { cho[5 - j][ti].push_back(i); ti /= 10; } for (int j = i + i; j <= 100000; j += i) p[j] = 0; } while (tc--) { scanf( %d , &a); int ti = a; ret = 0; n = 0; while (ti > 0) { sum[n] = ti % 10; ti /= 10; n++; } for (int i = 0; i < n / 2; i++) swap(sum[i], sum[n - 1 - i]); doit(1, sum[1]); printf( %d n , ret); } } |
#include <bits/stdc++.h> using namespace std; const int INF = 1000 * 1000 * 1000 + 7; const long long LINF = 1LL * INF * INF; const int MAX = 1e5 + 7; const double PI = acos(-1.); const double EPS = 1e-7; const int MOD = 998244353; const int MAXF = 1000000000; int dx[] = {1, -1, 0, 0}; int dy[] = {0, 0, -1, 1}; bool isInField(int x, int y) { return 1 <= x && x <= MAXF && 1 <= y && y <= MAXF; } bool isWhite(int x, int y) { return x % 2 == y % 2; } void solve() { int black, white; cin >> black >> white; map<pair<int, int>, int> was; vector<pair<int, int> > ans; int sX = 200000, sY = 200000; if (black > white) { sX++; --black; } else { --white; } ans.emplace_back(sX, sY); was[{sX, sY}] = 1; while (black > 0 && white > 0) { --black; --white; ++sX; ans.emplace_back(sX, sY); was[{sX, sY}] = 1; ++sX; ans.emplace_back(sX, sY); was[{sX, sY}] = 1; } for (int i = 0; i < (((int)ans.size())); ++i) { int x = ans[i].first; int y = ans[i].second; for (int j = 0; j < (4); ++j) { int a = x + dx[j]; int b = y + dy[j]; if (black > 0) { if (!was.count({a, b}) && !isWhite(a, b)) { --black; ans.emplace_back(a, b); was[{a, b}] = 1; } } else if (white > 0) { if (!was.count({a, b}) && isWhite(a, b)) { --white; ans.emplace_back(a, b); was[{a, b}] = 1; } } } } if (black != 0 || white != 0) { cout << NO n ; return; } cout << YES n ; for (auto [x, y] : ans) { cout << x << << y << endl; } } int main() { ios_base::sync_with_stdio(0); int q; cin >> q; while (q--) { solve(); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFBBP_1_V
`define SKY130_FD_SC_LS__SDFBBP_1_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog wrapper for sdfbbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__sdfbbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfbbp_1 (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ls__sdfbbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK(CLK),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfbbp_1 (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__sdfbbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK(CLK),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFBBP_1_V
|
#include <bits/stdc++.h> using namespace std; int read() { int s = 0; char c = getchar(), lc = + ; while (c < 0 || 9 < c) lc = c, c = getchar(); while ( 0 <= c && c <= 9 ) s = s * 10 + c - 0 , c = getchar(); return lc == - ? -s : s; } void write(int x) { if (x < 0) { putchar( - ); x = -x; } if (x < 10) putchar(x + 0 ); else { write(x / 10); putchar(x % 10 + 0 ); } } void print(int x, char c = n ) { write(x); putchar(c); } void output(int x, int y) { print(x, ); print(y); } signed main(signed Recall, char *_902_[]) { (void)Recall, (void)_902_; int n = read(); if (n % 4 >= 2) puts( NO ); else { puts( YES ); for (int i = 0; i < n / 4; i++) { int x = i * 4; output(x + 1, x + 2); output(x + 3, x + 4); output(x + 1, x + 4); output(x + 2, x + 3); if (n & 1) output(x + 1, n); if (n & 1) output(x + 2, n); output(x + 1, x + 3); output(x + 2, x + 4); if (n & 1) output(x + 4, n); if (n & 1) output(x + 3, n); } for (int i = 0; i < n / 4; i++) for (int j = i + 1; j < n / 4; j++) { int x = i * 4, y = j * 4; output(x + 1, y + 1); output(x + 2, y + 2); output(x + 1, y + 2); output(x + 2, y + 1); output(x + 1, y + 3); output(x + 2, y + 4); output(x + 1, y + 4); output(x + 2, y + 3); output(x + 3, y + 1); output(x + 4, y + 2); output(x + 3, y + 2); output(x + 4, y + 1); output(x + 3, y + 3); output(x + 4, y + 4); output(x + 3, y + 4); output(x + 4, y + 3); } } return 0; } |
// megafunction wizard: %LPM_ADD_SUB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_ADD_SUB
// ============================================================
// File Name: add.v
// Megafunction Name(s):
// LPM_ADD_SUB
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.1.0 Build 186 12/03/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module add (
clock,
dataa,
datab,
result);
input clock;
input [8:0] dataa;
input [8:0] datab;
output [8:0] result;
wire [8:0] sub_wire0;
wire [8:0] result = sub_wire0[8:0];
lpm_add_sub LPM_ADD_SUB_component (
.clock (clock),
.dataa (dataa),
.datab (datab),
.result (sub_wire0)
// synopsys translate_off
,
.aclr (),
.add_sub (),
.cin (),
.clken (),
.cout (),
.overflow ()
// synopsys translate_on
);
defparam
LPM_ADD_SUB_component.lpm_direction = "ADD",
LPM_ADD_SUB_component.lpm_hint = "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
LPM_ADD_SUB_component.lpm_pipeline = 1,
LPM_ADD_SUB_component.lpm_representation = "SIGNED",
LPM_ADD_SUB_component.lpm_type = "LPM_ADD_SUB",
LPM_ADD_SUB_component.lpm_width = 9;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: Function NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: Overflow NUMERIC "0"
// Retrieval info: PRIVATE: RadixA NUMERIC "10"
// Retrieval info: PRIVATE: RadixB NUMERIC "10"
// Retrieval info: PRIVATE: Representation NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: nBit NUMERIC "9"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "9"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 9 0 INPUT NODEFVAL "dataa[8..0]"
// Retrieval info: USED_PORT: datab 0 0 9 0 INPUT NODEFVAL "datab[8..0]"
// Retrieval info: USED_PORT: result 0 0 9 0 OUTPUT NODEFVAL "result[8..0]"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 9 0 dataa 0 0 9 0
// Retrieval info: CONNECT: @datab 0 0 9 0 datab 0 0 9 0
// Retrieval info: CONNECT: result 0 0 9 0 @result 0 0 9 0
// Retrieval info: GEN_FILE: TYPE_NORMAL add.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL add.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL add.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL add.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL add_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL add_bb.v FALSE
// Retrieval info: LIB_FILE: lpm
|
#include <bits/stdc++.h> using namespace std; string inc[6] = { 011112 , 103231 , 110121 , 121011 , ,112101 , 211110 }; string near[6] = { 1234 , 0254 , 0153 , 4520 , 3510 , 4321 }; int opp[6] = {5, 3, 4, 1, 2, 0}; char t[7], s[7]; string t_p; bool seen[6]; set<string> se; void dfs(int x, int v) { seen[x] = true; t[v] = s[x]; if (v == 5) { t_p = min((string)t, t_p); } else { for (int i = 0; i < 6; i++) { if (inc[x][i] == 1 && !seen[i]) { dfs(i, v + 1); } } } seen[x] = false; } int X[4] = {1, 2, 3, 4}, Y[4] = {0, 1, 5, 3}, Z[4] = {0, 2, 5, 4}; void cycle(int* r) { int x = t[r[0]]; t[r[0]] = t[r[1]]; t[r[1]] = t[r[2]]; t[r[2]] = t[r[3]]; t[r[3]] = x; } int main() { t[6] = 0 ; while (cin >> s) { se.clear(); sort(s, s + 6); do { for (int i = 0; i < 6; i++) t[i] = s[i]; t_p = ZZZZZZ ; for (int i = 0; i < 4; i++) { for (int j = 0; j < 4; j++) { for (int k = 0; k < 4; k++) { t_p = min((string)t, t_p); cycle(X); } cycle(Y); } cycle(Z); } se.insert(t_p); } while (next_permutation(s, s + 6)); cout << se.size() << endl; } } |
#include <bits/stdc++.h> using namespace std; vector<int> x_coord, y_coord; vector<vector<int>> adj; vector<bool> used; int n; void dfs(int v) { used[v] = true; for (auto u : adj[v]) { if (!used[u]) { used[u] = true; dfs(u); } } } int main() { scanf( %d , &n); x_coord.resize(n); y_coord.resize(n); adj.resize(n); for (int i = 0; i < n; i++) { scanf( %d%d , &x_coord[i], &y_coord[i]); for (int j = 0; j < i; j++) { if (x_coord[j] == x_coord[i] || y_coord[j] == y_coord[i]) { adj[i].push_back(j); adj[j].push_back(i); } } } used.resize(n, false); int cnt = 0; for (int i = 0; i < n; i++) { if (!used[i]) { cnt++; dfs(i); } } printf( %d n , cnt - 1); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 501; int n, k; int C[N]; bool Dp[N][N][N]; vector<int> Ans; int main() { scanf( %d%d , &n, &k); for (int i = 0; i < n; i++) scanf( %d , C + i); Dp[n][0][0] = true; for (int idx = n - 1; idx >= 0; idx--) for (int Sum = 0; Sum <= k; Sum++) for (int X = 0; X <= k; X++) { Dp[idx][Sum][X] |= Dp[idx + 1][Sum][X]; Dp[idx][Sum][X] |= (Sum >= C[idx] && Dp[idx + 1][Sum - C[idx]][X]); Dp[idx][Sum][X] |= (Sum >= C[idx] && X >= C[idx] && Dp[idx + 1][Sum - C[idx]][X - C[idx]]); } for (int X = 0; X <= k; X++) if (Dp[0][k][X]) Ans.push_back(X); printf( %d n , Ans.size()); for (auto x : Ans) printf( %d , x); puts( ); return 0; } |
#include <bits/stdc++.h> using namespace std; long long dx[] = {1, 0, -1, 0}; long long dy[] = {0, 1, 0, -1}; bool myComparison1(const pair<long long, long long> &a, const pair<long long, long long> &b) { return a.second < b.second; } bool myComparison2(const pair<long long, long long> &a, const pair<long long, long long> &b) { if (a.first == b.first) { return (a.second < b.second); } return (a.first < b.first); } long long gcd(long long x, long long y) { if (y == 0) return x; else return gcd(y, x % y); } long long expo(long long n, long long m, long long p) { long long r = 1; n = n % p; while (m > 0) { if (m % 2) r = (r * n) % p; n = (n * n) % p; m = m / 2; } return r % p; } bool isPrime(long long n) { if (n <= 1) return false; if (n <= 3) return true; if (n % 2 == 0 || n % 3 == 0) return false; for (long long i = 5; i * i <= n; i = i + 6) if (n % i == 0 || n % (i + 2) == 0) return false; return true; } vector<long long> z_function(string s) { long long n = (long long)s.length(); vector<long long> z(n); for (long long i = 1, l = 0, r = 0; i < n; ++i) { if (i <= r) z[i] = min(r - i + 1, z[i - l]); while (i + z[i] < n && s[z[i]] == s[i + z[i]]) ++z[i]; if (i + z[i] - 1 > r) l = i, r = i + z[i] - 1; } return z; } long long distance(long long x, long long y) { return (sqrt(x * 2 + y * 2)); } int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long n; cin >> n; vector<long long> x, y; for (long long i = 0; i < n; i++) { long long c, d; cin >> c >> d; x.push_back(c); y.push_back(d); } long long max = -1; long long X = 0, Y = 0; for (long long i = 0; i < n; i++) { if (x[i] + y[i] > max) { X = x[i]; Y = y[i]; max = X + Y; } } cout << max; } |
#include <bits/stdc++.h> using namespace std; const int N = 105; const int inf = 10000000; int n, k; int l[N], r[N]; int main() { scanf( %d%d , &n, &k); int midx = (k + 1) / 2, midy = (k + 1) / 2; for (int i = 0; i < n; i++) { int m, ans = inf, x, y1, y2; scanf( %d , &m); for (int row = 1; row <= k; row++) { if (l[row] == 0 && r[row] == 0) { for (int a = 1; a + m - 1 <= k; a++) { int tot = 0, b = a + m - 1; for (int col = a; col <= b; col++) { tot += abs(row - midx) + abs(col - midy); } if (tot < ans) ans = tot, x = row, y1 = a, y2 = b; } } else { if (l[row] > m) { int tot = 0, a = l[row] - m, b = l[row] - 1; for (int col = a; col <= b; col++) { tot += abs(row - midx) + abs(col - midy); } if (tot < ans) ans = tot, x = row, y1 = a, y2 = b; } if (r[row] + m <= k) { int tot = 0, a = r[row] + 1, b = r[row] + m; for (int col = a; col <= b; col++) tot += abs(row - midx) + abs(col - midy); if (tot < ans) ans = tot, x = row, y1 = a, y2 = b; } } } if (ans == inf) puts( -1 ); else { printf( %d %d %d n , x, y1, y2); if (r[x] == 0 && l[x] == 0) l[x] = y1, r[x] = y2; else l[x] = min(l[x], y1), r[x] = max(r[x], y2); } } return 0; } |
#include <bits/stdc++.h> using namespace std; int a[150], b[150]; void put(int x, int y[]) { if (x == 1) y[1] = 1; else if (x == 2) { y[1] = 3; y[2] = 4; } else { for (int i = 1; i <= x - 1; i++) y[i] = 2; y[x] = x - 2; } } int main() { int n, m; scanf( %d%d , &n, &m); put(n, a); put(m, b); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { printf( %d , a[i] * b[j]); if (j == m) printf( n ); else printf( ); } return 0; } |
module packet_builder #(parameter NUM_CHAN = 1)(
// System
input rxclk,
input reset,
input [31:0] adctime,
input [3:0] channels,
// ADC side
input [15:0]chan_fifodata,
input [NUM_CHAN:0]chan_empty,
input [9:0]chan_usedw,
output reg [3:0]rd_select,
output reg chan_rdreq,
// FX2 side
output reg WR,
output reg [15:0]fifodata,
input have_space,
input wire [31:0]rssi_0, input wire [31:0]rssi_1, input wire [31:0]rssi_2,
input wire [31:0]rssi_3, output wire [7:0] debugbus,
input [NUM_CHAN:0] underrun);
// States
`define IDLE 3'd0
`define HEADER1 3'd1
`define HEADER2 3'd2
`define TIMESTAMP 3'd3
`define FORWARD 3'd4
`define MAXPAYLOAD 504
`define PAYLOAD_LEN 8:0
`define TAG 12:9
`define MBZ 15:13
`define CHAN 4:0
`define RSSI 10:5
`define BURST 12:11
`define DROPPED 13
`define UNDERRUN 14
`define OVERRUN 15
reg [NUM_CHAN:0] overrun;
reg [2:0] state;
reg [8:0] read_length;
reg [8:0] payload_len;
reg tstamp_complete;
reg [3:0] check_next;
wire [31:0] true_rssi;
wire [4:0] true_channel;
wire ready_to_send;
assign debugbus = {chan_empty[0], rd_select[0], have_space,
(chan_usedw >= 10'd504), (chan_usedw ==0),
ready_to_send, state[1:0]};
assign true_rssi = (rd_select[1]) ? ((rd_select[0]) ? rssi_3:rssi_2) :
((rd_select[0]) ? rssi_1:rssi_0);
assign true_channel = (check_next == 4'd0 ? 5'h1f : {1'd0, check_next - 4'd1});
//assign true_channel = (check_next == NUM_CHAN ? 5'h1f : {1'd0,check_next});
assign ready_to_send = (chan_usedw >= 10'd504) || (chan_usedw == 0) ||
((rd_select == NUM_CHAN)&&(chan_usedw > 0));
always @(posedge rxclk)
begin
if (reset)
begin
overrun <= 0;
WR <= 0;
rd_select <= 0;
chan_rdreq <= 0;
tstamp_complete <= 0;
check_next <= 0;
state <= `IDLE;
end
else case (state)
`IDLE: begin
chan_rdreq <= #1 0;
//check if the channel is full
if(~chan_empty[check_next])
begin
if (have_space)
begin
//transmit if the usb buffer have space
//check if we should send
if (ready_to_send)
state <= #1 `HEADER1;
overrun[check_next] <= 0;
end
else
begin
state <= #1 `IDLE;
overrun[check_next] <= 1;
end
rd_select <= #1 check_next;
end
check_next <= #1 (check_next == channels ? 4'd0 : check_next + 4'd1);
end //end of `IDLE
`HEADER1: begin
fifodata[`PAYLOAD_LEN] <= #1 9'd504;
payload_len <= #1 9'd504;
fifodata[`TAG] <= #1 0;
fifodata[`MBZ] <= #1 0;
WR <= #1 1;
state <= #1 `HEADER2;
read_length <= #1 0;
end
`HEADER2: begin
fifodata[`CHAN] <= #1 true_channel;
fifodata[`RSSI] <= #1 true_rssi[5:0];
fifodata[`BURST] <= #1 0;
fifodata[`DROPPED] <= #1 0;
fifodata[`UNDERRUN] <= #1 (check_next == 0) ? 1'b0 : underrun[true_channel];
fifodata[`OVERRUN] <= #1 (check_next == 0) ? 1'b0 : overrun[true_channel];
state <= #1 `TIMESTAMP;
end
`TIMESTAMP: begin
fifodata <= #1 (tstamp_complete ? adctime[31:16] : adctime[15:0]);
tstamp_complete <= #1 ~tstamp_complete;
if (~tstamp_complete)
chan_rdreq <= #1 1;
state <= #1 (tstamp_complete ? `FORWARD : `TIMESTAMP);
end
`FORWARD: begin
read_length <= #1 read_length + 9'd2;
fifodata <= #1 (read_length >= payload_len ? 16'hDEAD : chan_fifodata);
if (read_length >= `MAXPAYLOAD)
begin
WR <= #1 0;
state <= #1 `IDLE;
chan_rdreq <= #1 0;
end
else if (read_length == payload_len - 4)
chan_rdreq <= #1 0;
end
default: begin
//handling error state
state <= `IDLE;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRSDFXTP_1_V
`define SKY130_FD_SC_LP__SRSDFXTP_1_V
/**
* srsdfxtp: Scan flop with sleep mode, non-inverted clock,
* single output.
*
* Verilog wrapper for srsdfxtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__srsdfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__srsdfxtp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SLEEP_B,
KAPWR ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SLEEP_B;
input KAPWR ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__srsdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SLEEP_B(SLEEP_B),
.KAPWR(KAPWR),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__srsdfxtp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SLEEP_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SLEEP_B;
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__srsdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SLEEP_B(SLEEP_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRSDFXTP_1_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n][2]; for (int i = 0; i < n; i++) { cin >> a[i][0] >> a[i][1]; } int sum1 = 0; int sum2 = 0; for (int i = 0; i < n; i++) { if (abs(sum1 + a[i][0] - sum2) <= 500) { sum1 += a[i][0]; a[i][0] = -1; } else { sum2 += a[i][1]; } } if (abs(sum1 - sum2) > 500) { cout << -1 ; } else { for (int i = 0; i < n; i++) { if (a[i][0] == -1) { cout << A ; } else { cout << G ; } } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O211AI_BLACKBOX_V
`define SKY130_FD_SC_LS__O211AI_BLACKBOX_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o211ai (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O211AI_BLACKBOX_V
|
//================================================================--
// Design Unit : sn7402 (behaviour)
//
// File Name : behaviour.v
//
// Purpose : model of TTL SN7402 quad and IC
//
// Author : Daniel Guenther, Vancouver Island University
//
// Environmant : Icarus
//-------------------------------------------------------------------
// Revision List
// Version Author Date Changes
// 1.0 Daniel Guenther Nov 10 2016 filled in wire connections
//================================================================--
module sn7402 (P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14);
output reg P1, P4, P10, P13;
input P2, P3, P5, P6, P8, P9, P11, P12, P7, P14;
always @(P2, P3, P7, P14) begin
if ((P14 == 1'b 1) && (P7 == 1'b 0)) begin
P1 = ~(P2 | P3);
end
end
always @(P5, P6, P7, P14) begin
if ((P14 == 1'b 1) && (P7 == 1'b 0)) begin
P4 = ~(P5 | P6);
end
end
always @(P8, P9, P7, P14) begin
if ((P14 == 1'b 1) && (P7 == 1'b 0)) begin
P10 = ~(P8 | P9);
end
end
always @(P11, P12, P7, P14) begin
if ((P14 == 1'b 1) && (P7 == 1'b 0)) begin
P13 = ~(P11 | P12);
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:06:45 03/31/2015
// Design Name:
// Module Name: Adder64
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Adder64(
input [63:0] A,
input [63:0] B,
input C0,
output [3:0] P,
output [3:0] G,
output [63:0] sum,
output SF,
output CF,
output OF,
output PF,
output ZF
);
wire[15:0] _p_,_g_;
wire[4:0] C;
wire[3:0] _sf_,_cf_,_of_,_pf_,_zf_;
pg_to_PG pgtoPG(_p_,_g_,P,G);
ParallelCarry4 PC(P,G,C0,C);
Adder16
a1(A[15: 0],B[15: 0],C[0],_p_[ 3: 0],_g_[ 3: 0],sum[15: 0],_sf_[0],_cf_[0],_of_[0],_pf_[0],_zf_[0]),
a2(A[31:16],B[31:16],C[1],_p_[ 7: 4],_g_[ 7: 4],sum[31:16],_sf_[1],_cf_[1],_of_[1],_pf_[1],_zf_[1]),
a3(A[47:32],B[47:32],C[2],_p_[11: 8],_g_[11: 8],sum[47:32],_sf_[2],_cf_[2],_of_[2],_pf_[2],_zf_[2]),
a4(A[63:48],B[63:48],C[3],_p_[15:12],_g_[15:12],sum[63:48],_sf_[3],_cf_[3],_of_[3],_pf_[3],_zf_[3]);
assign SF=_sf_[3],
CF=C[4],
OF=_of_[3],
PF=^_pf_[3:0],
ZF= ~|(~_zf_[3:0]);
endmodule
|
module voice(clk, gate, note, pitch, lfo_sig, lfo_depth, lfo_depth_fine, wave_form, signal_out);
input wire clk;
input wire gate;
input wire [6:0] note;
input wire [7:0] lfo_sig;
input wire [6:0] lfo_depth;
input wire [6:0] lfo_depth_fine;
input wire [13:0] pitch;
output wire [7:0] signal_out;
//input wire [31:0] adder;
input wire [2:0] wave_form;
// wave_forms
parameter SAW = 3'b000;
parameter SQUARE = 3'b001; //with PWM
parameter TRIANGLE = 3'b010;
parameter SINE = 3'b011;
parameter RAMP = 3'b100;
parameter SAW_TRI = 3'b101;
parameter NOISE = 3'b110;
parameter UNDEF = 3'b111;
wire [31:0] adder_center;
note_pitch2dds transl1(.clk(clk), .note(note), .pitch(pitch), .lfo_sig(lfo_sig), .lfo_depth(lfo_depth), .lfo_depth_fine(lfo_depth_fine), .adder(adder_center));
wire [31:0] vco_out;
dds #(.WIDTH(32)) vco(.clk(clk), .adder(adder_center), .signal_out(vco_out));
wire [7:0] saw_out = vco_out[31:31-7];
wire [7:0] square_out = (vco_out[31:31-7] > 127) ? 8'b11111111 : 1'b00000000;
wire [7:0] tri_out = (saw_out>8'd191) ? 7'd127 + ((saw_out << 1) - 9'd511) :
(saw_out>8'd063) ? 8'd255 - ((saw_out << 1) - 7'd127) : 7'd127 + (saw_out << 1);
//SINE table
wire [7:0] sine_out;
sine sine_rom(.address(vco_out[31:31-7]),
.q(sine_out),
.clock(clk));
wire [7:0] ramp_out = -saw_out;
wire [7:0] saw_tri_out = (saw_out > 7'd127) ? -saw_out : 8'd127 + saw_out;
//noise
reg [7:0] noise_reg;
wire [7:0] noise_out = noise_reg;
wire [7:0] noise_sig;
//16000 hz GENERATOR
wire clk16000;
frq1divmod1 divider1(clk, 25'd1563, clk16000); //50000000 / 16000 / 2 = 1563
reg [1:0] clk16000_prev=2'b00;
always @(posedge clk) clk16000_prev <= {clk16000_prev[0], clk16000};
wire clk16000_posege = (clk16000_prev==2'b01);
rndx #(.WIDTH(8)) random8(.clk(clk), .signal_out(noise_sig));
always @(posedge clk) begin
if (clk16000_posege) begin
noise_reg <= noise_sig;
end
end
//signal_out
assign signal_out = (wave_form == SAW) ? saw_out :
(wave_form == SQUARE) ? square_out :
(wave_form == TRIANGLE) ? tri_out :
(wave_form == SINE) ? sine_out :
(wave_form == RAMP) ? ramp_out :
(wave_form == SAW_TRI) ? saw_tri_out :
(wave_form == NOISE) ? noise_out : 8'd127;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 10, mod = 1e9 + 7; const long long infl = LLONG_MAX / 2; int n, ans, h[N]; vector<int> g[N], L; void dfs(int u = 0, int p = -1) { bool leaf = 1; for (int x : g[u]) if (x - p) { h[x] = h[u] + 1; dfs(x, u); leaf = 0; } if (leaf) L.push_back(h[u]); if (h[u] == 1) { sort(L.begin(), L.end()); int now = 0; for (int i = 0; i < L.size(); ++i) { now = max(now + 1, L[i]); } ans = max(ans, now - 1); L.clear(); } } int main() { cin >> n; for (int i = 0; i < n - 1; ++i) { int u, v; scanf( %d %d , &u, &v); --u; --v; g[u].push_back(v); g[v].push_back(u); } dfs(); cout << ans + 1; } |
#include <bits/stdc++.h> using namespace std; int main() { double n, m, a; cin >> n >> m >> a; cout << (long long)(ceil(n / a) * ceil(m / a)); return 0; } |
#include <bits/stdc++.h> using namespace std; inline void io() {} int main() { ios_base::sync_with_stdio(false); cin.tie(); cout.tie(); cout << fixed << setprecision(8); long long int n, a, b, c = 0, k; cin >> a >> b >> n; for (int i = 0; i < 10; i++) { if (((a * 10) + i) % b == 0) { c++; k = (a * 10) + i; break; } } if (c == 1) { cout << k; for (int i = 1; i < n; i++) { cout << 0 ; } } else { cout << -1 ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; for (int i = 1; i <= 500; i++) putchar( 9 ); for (int i = 1; i <= 500; i++) putchar( 0 ); putchar( 1 ); putchar( n ); for (int i = 1; i <= 501; i++) putchar( 9 ); return 0; } |
// Zhiyang Ong
// Andrew Mattheisen
// EE577b Troy WideWord Processor Project
// make module match terms in module defn'
module pipe2(aluop_in, aluop_out,
ww_in, ww_out,
memEn_in, memEn_out,
memWrEn_in, memWrEn_out,
memAddr_in, memAddr_out,
wbyteen_in, wbyteen_out,
regwren_in, regwren_out,
rwraddrd_in, rwraddrd_out,
reginmuxop_in, reginmuxop_out,
aluinmuxop_in, aluinmuxop_out,
immediate_in, immediate_out,
wrdata, hz1data,
instruction_in, instruction_out,
clk,
reset);
// INPUTS
input [0:4] aluop_in;
input [0:1] ww_in;
input memEn_in, memWrEn_in;
input [0:20] memAddr_in;
input [0:15] wbyteen_in;
input regwren_in;
input [0:4] rwraddrd_in;
input reginmuxop_in;
input aluinmuxop_in;
input [0:127] immediate_in;
input [0:127] wrdata;
input [0:31] instruction_in;
input clk, reset;
// OUTPUTS
output [0:4] aluop_out;
output [0:1] ww_out;
output memWrEn_out;
output memEn_out;
output [0:20] memAddr_out;
output [0:15] wbyteen_out;
output regwren_out;
output [0:4] rwraddrd_out;
output reginmuxop_out;
output aluinmuxop_out;
output [0:127] immediate_out;
output [0:127] hz1data;
output [0:31] instruction_out;
//REGISTERS
reg [0:4] aluop_out;
reg [0:2] ppp_out;
reg [0:1] ww_out;
reg memWrEn_out;
reg memEn_out;
reg [0:20] memAddr_out;
reg [0:15] wbyteen_out;
reg regwren_out;
reg [0:4] rwraddrd_out;
reg reginmuxop_out;
reg aluinmuxop_out;
reg [0:127]immediate_out;
reg [0:127] hz1data;
reg [0:31] instruction_out;
always @ (posedge clk)
begin
if (reset == 1'b1)
begin
aluop_out<=5'b0;
ww_out<=2'b0;
memWrEn_out<=1'b0;
memEn_out<=1'b0;
memAddr_out<=21'b0;
wbyteen_out<=16'b0;
regwren_out<=1'b0;
rwraddrd_out<=5'b0;
reginmuxop_out<=1'b0;
aluinmuxop_out<=1'b0;
immediate_out<=128'b0;
hz1data<=128'b0;
instruction_out<=32'b0;
end
else
begin
aluop_out<=aluop_in;
ww_out<=ww_in;
memWrEn_out<=memWrEn_in;
memEn_out<=memEn_in;
memAddr_out<=memAddr_in;
wbyteen_out<=wbyteen_in;
regwren_out<=regwren_in;
rwraddrd_out<=rwraddrd_in;
reginmuxop_out<=reginmuxop_in;
aluinmuxop_out<=aluinmuxop_in;
immediate_out<=immediate_in;
hz1data<=wrdata;
instruction_out<=instruction_in;
end
end // always @ (posedge clk);
endmodule
|
#include <bits/stdc++.h> using namespace std; struct Timer { chrono::time_point<chrono::high_resolution_clock> start, end; chrono::duration<float> dur; Timer() { start = chrono::high_resolution_clock::now(); } ~Timer() { end = chrono::high_resolution_clock::now(); dur = end - start; cout << nTime Elapsed : << dur.count() << s n ; } }; long long int sum() { return 0; } template <typename T, typename... Args> T sum(T a, Args... args) { return a + sum(args...); } template <int D, typename T> struct Vec : public vector<Vec<D - 1, T>> { static_assert(D >= 1, Vector dimension must be greater than zero! ); template <typename... Args> Vec(int n = 0, Args... args) : vector<Vec<D - 1, T>>(n, Vec<D - 1, T>(args...)) {} }; template <typename T> struct Vec<1, T> : public vector<T> { Vec(int n = 0, T val = T()) : vector<T>(n, val) {} }; template <typename T> class SieveEuler { public: vector<T> primes; vector<T> lp; inline SieveEuler(int MAX = 1000000) { lp.resize(MAX + 1, 0); for (long long int i = 2; i <= MAX; i++) { if (lp[i] == 0) { lp[i] = i; primes.push_back(i); } for (int j = 0; j < primes.size() && i * primes[j] <= MAX && primes[j] <= lp[i]; ++j) { if (primes[j] == lp[i]) { lp[i * primes[j]] = primes[j]; } else { lp[i * primes[j]] = primes[j]; } } } } }; long long int EulerPhi(long long int n) { long long int result = n; for (long long int i = 2; i * i <= n; i++) { if (n % i == 0) { while (n % i == 0) n /= i; result -= result / i; } } if (n > 1) result -= result / n; return result; } template <typename T> vector<vector<T>> matmul(const vector<vector<T>>& a, const vector<vector<T>>& b) { int n = a.size(), m = b[0].size(), k = b.size(); vector<vector<T>> c(n, vector<T>(m)); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { for (int l = 0; l < k; l++) c[i][j] += (a[i][k] * b[k][j]); } } return c; } template <typename T> bool isPrime(T n) { if (n <= 1) return false; else if (n == 2 || n == 3) return true; else if (n % 2 == 0 || n % 3 == 0) return false; T x = 5; T p = 2; while (x * x <= n) { if (n % x == 0) return true; x += p; p = 6 - p; } return true; } template <typename T> class Graph { public: struct edge { int from, to; T cost; }; vector<edge> edgeList; vector<vector<int>> adj; int n; Graph(int _n) : n(_n) { adj.resize(n + 1); } void add(int from, int to) { adj[to].push_back(from); adj[from].push_back(to); } void solve(int m) { int cnt = 0; for (int i = 1; i <= n; i++) { cnt += (adj[i].size() == 1); } cout << setprecision(9) << 2 * ((double)m / cnt) << n ; } }; bool isSubsequenceString(string x, string y) { int i = 0, j = 0; while (i < x.length() && j < y.length()) x[i] == y[j] ? i++, j++ : i++; return (j == y.length()); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int testCases = 1; while (testCases--) { int n, m; cin >> n >> m; Graph<int> g(n); for (int i = 1; i <= n - 1; i++) { int u, v; cin >> u >> v; g.add(u, v); } g.solve(m); } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DECAPHETAP_2_V
`define SKY130_FD_SC_LS__DECAPHETAP_2_V
/**
*
* Verilog wrapper for decaphetap with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__decaphetap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__decaphetap_2 (
VPWR,
VGND,
VPB
);
input VPWR;
input VGND;
input VPB ;
sky130_fd_sc_ls__decaphetap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__decaphetap_2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
sky130_fd_sc_ls__decaphetap base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DECAPHETAP_2_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
parameter ONE = 1;
wire [17:10] bitout;
reg [7:0] allbits;
reg [15:0] onebit;
sub #(1)
sub0 (allbits, onebit[1:0], bitout[10]),
sub1 (allbits, onebit[3:2], bitout[11]),
sub2 (allbits, onebit[5:4], bitout[12]),
sub3 (allbits, onebit[7:6], bitout[13]),
sub4 (allbits, onebit[9:8], bitout[14]),
sub5 (allbits, onebit[11:10], bitout[15]),
sub6 (allbits, onebit[13:12], bitout[16]),
sub7 (allbits, onebit[15:14], bitout[17]);
integer x;
always @ (posedge clk) begin
//$write("%x\n", bitout);
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
allbits <= 8'hac;
onebit <= 16'hc01a;
end
if (cyc==2) begin
if (bitout !== 8'h07) $stop;
allbits <= 8'hca;
onebit <= 16'h1f01;
end
if (cyc==3) begin
if (bitout !== 8'h41) $stop;
if (sub0.bitout !== 1'b1) $stop;
if (sub1.bitout !== 1'b0) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
`ifdef USE_INLINE
`define INLINE_MODULE /*verilator inline_module*/
`else
`define INLINE_MODULE /*verilator public_module*/
`endif
module sub (input [7:0] allbits, input [1:0] onebit, output bitout);
`INLINE_MODULE
parameter integer P = 0;
initial if (P != 1) $stop;
assign bitout = (^ onebit) ^ (^ allbits);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_POWER_HVC_WPAD_PP_SYMBOL_V
`define SKY130_FD_IO__TOP_POWER_HVC_WPAD_PP_SYMBOL_V
/**
* top_power_hvc_wpad: A power pad with an ESD high-voltage clamp.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_power_hvc_wpad (
//# {{data|Data Signals}}
inout P_PAD ,
//# {{control|Control Signals}}
inout AMUXBUS_A ,
inout AMUXBUS_B ,
//# {{power|Power}}
inout VSWITCH ,
inout DRN_HVC ,
inout OGC_HVC ,
inout P_CORE ,
inout SRC_BDY_HVC,
inout VCCD ,
inout VCCHIB ,
inout VDDA ,
inout VDDIO ,
inout VDDIO_Q ,
inout VSSA ,
inout VSSD ,
inout VSSIO ,
inout VSSIO_Q
);
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_POWER_HVC_WPAD_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; cout << s; for (int i = s.size() - 1; i >= 0; i--) { cout << s[i]; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A22O_4_V
`define SKY130_FD_SC_HS__A22O_4_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a22o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a22o_4 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a22o_4 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A22O_4_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long n, m; cin >> n >> m; if (m % 2 == 1) { bool f = true; long ptr = (m + 1) / 2; long p1 = ptr - 1, p2 = ptr; for (long i = 1; i <= n; i++) { if (f && p2 <= m) { cout << p2 << n ; p2++; f = false; } else if (p1 >= 1) { cout << p1 << n ; p1--; f = true; } else { i--; f = !f; p1 = ptr - 1; p2 = ptr; } } } else { bool f = true; long ptr = (m + 1) / 2; if (n >= 2) cout << ptr << n << ptr + 1 << n ; else cout << ptr; long p1 = ptr - 1; long p2 = ptr + 2; for (long i = 3; i <= n; i++) { if (f && p1 >= 1) { cout << p1 << n ; p1--; f = false; } else if (p2 <= m) { cout << p2 << n ; p2++; f = true; } else { i++; if (i < n) cout << ptr << n << ptr + 1 << n ; else cout << ptr << n ; p1 = ptr - 1; p2 = ptr + 2; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int T; cin >> T; while (T--) { int a; cin >> a; if (a % 2 == 0) cout << a - 1 << ; else cout << a << ; } } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module convolve_kernel_fcud
#(parameter
ID = 2,
NUM_STAGE = 4,
din0_WIDTH = 32,
din1_WIDTH = 32,
dout_WIDTH = 32
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [31:0] a_tdata;
wire b_tvalid;
wire [31:0] b_tdata;
wire r_tvalid;
wire [31:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
convolve_kernel_ap_fmul_2_max_dsp_32 convolve_kernel_ap_fmul_2_max_dsp_32_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O221A_BEHAVIORAL_V
`define SKY130_FD_SC_LP__O221A_BEHAVIORAL_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__o221a (
X ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
and and0 (and0_out_X, or0_out, or1_out, C1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O221A_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; const bool online_judge = true; const long long inf = 1LL << 60; long long toInt(string s) { long long res; stringstream ss; ss << s; ss >> res; return res; } string toString(long long n) { stringstream ss; ss << n; return ss.str(); } long long w, h; vector<string> f; typedef struct { long long x; long long y; long long dp; long long cp; } state; state memo[55][55][5][5]; long long dx[4] = {0, 1, 0, -1}; long long dy[4] = {-1, 0, 1, 0}; long long ex[4] = {-1, 0, 1, 0}; long long ey[4] = {0, -1, 0, 1}; state solve(long long y, long long x, long long dp, long long cp) { if (memo[y][x][dp][cp].x != -1) return memo[y][x][dp][cp]; state ans; long long nx = x + dx[dp]; long long ny = y + dy[dp]; long long mx = x + ex[(dp + (cp ? 2 : 0)) % 4]; long long my = y + ey[(dp + (cp ? 2 : 0)) % 4]; if (f[ny][nx] == f[y][x]) { ans = solve(ny, nx, dp, cp); } else if (f[my][mx] == f[y][x]) { ans = solve(my, mx, dp, cp); } else { char c = f[ny][nx]; if (c == 0 ) { if (cp == 0) { ans.y = y; ans.x = x; ans.dp = dp; ans.cp = 1; } else { ans.y = y; ans.x = x; ans.dp = (dp + 1) % 4; ans.cp = 0; } } else { ans.x = nx; ans.y = ny; ans.dp = dp; ans.cp = cp; } } memo[y][x][dp][cp] = ans; return ans; } void run() { long long m, n; cin >> m >> n; for (long long _ = 0; _ < m; _++) { string tmp; cin >> tmp; f.push_back(tmp); } w = f[0].size(); h = m; for (long long i = 0; i < m; i++) { f[i] = 0 + f[i] + 0 ; } f.insert(f.begin(), string(w + 2, 0 )); f.push_back(string(w + 2, 0 )); for (long long i = 1; i <= h; i++) { for (long long j = 1; j <= w; j++) { for (long long dp = 0; dp <= 3; dp++) { for (long long cp = 0; cp <= 1; cp++) { memo[i][j][dp][cp].x = -1; } } } } for (long long i = 1; i <= h; i++) { for (long long j = 1; j <= w; j++) { for (long long dp = 0; dp <= 3; dp++) { for (long long cp = 0; cp <= 1; cp++) { solve(i, j, dp, cp); } } } } long long x = 1, y = 1, dp = 1, cp = 0; while (n--) { state next = memo[y][x][dp][cp]; x = next.x; y = next.y; dp = next.dp; cp = next.cp; } cout << f[y][x] << endl; } int main(int argc, char *argv[]) { run(); return 0; } |
#include <bits/stdc++.h> int main() { long long l3, l4, l5; std::cin >> l3 >> l4 >> l5; long double pi = 3.141592653589793238462643383279; long double v3 = 1.0 / 3.0 * l3 * l3 * sqrtl(3.0) / 4.0 * l3 * sqrtl(2.0 / 3); long double v4 = 1.0 / 3.0 * l4 * l4 * l4 * sqrtl(2) / 2; long double v5 = 1.0 / 3.0 * l5 * l5 * sqrtl(25 + 10 * sqrtl(5)) / 4 * l5 * sqrtl(4 * sinl(pi / 5) * sinl(pi / 5) - 1) / (2 * sinl(pi / 5)); std::cout.precision(10); return std::cout << std::fixed << v3 + v4 + v5, 0; } |
/*
Testbench for Average Filter
By Hsiang-Yi Chung
February, 2016
*/
`timescale 1 ns / 1 ps
module tb_avg_filter;
reg [11:0] in;
reg [10:0] dummy;
reg clk;
wire out_ready;
wire [11:0] out1;
wire [11:0] out2;
reg [16:0] test;
reg [5:0] i,j;
reg [16:0] tb_result1, tb_result2;
Average_Filter filter (.in(in), .clk(clk), .reset_n(1'b1), .out_ready(out_ready), .out1(out1), .out2(out2));
initial begin
test = 0;
for (j = 0; j < 16; j = j + 1) begin
for (i = 0; i < 16; i = i + 1) begin
in = $random;
test = test + in;
if(i == 7) begin
tb_result1 = test >> 3;
test = 0;
end else if (i == 15) begin
tb_result2 = test >> 3;
test = 0;
end
if(out_ready) begin
if((tb_result1 == out1) && (tb_result2 == out2))
$display("Correct: tb_result1 = %d, Out1 = %d, tb_result2 = %d, Out2 = %d. ", tb_result1, out1, tb_result2, out2);
else
$display("Error: tb_result1 = %d, Out1 = %d, tb_result2 = %d, Out2 = %d. ", tb_result1, out1, tb_result2, out2);
end
@(posedge clk);
@(posedge clk);
end
end
#1000 $finish;
end
initial begin
clk = 0;
forever #25 clk = ~clk; //50ns clock period (twice the 10Mhz ADC sampling rate)
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T, size_t N> long long SIZE(const T (&t)[N]) { return N; } template <typename T> long long SIZE(const T &t) { return t.size(); } string to_string(const string s, long long x1 = 0, long long x2 = 1e9) { return + ((x1 < s.size()) ? s.substr(x1, x2 - x1 + 1) : ) + ; } string to_string(const char *s) { return to_string((string)s); } string to_string(const bool b) { return (b ? true : false ); } string to_string(const char c) { return string({c}); } template <size_t N> string to_string(const bitset<N> &b, long long x1 = 0, long long x2 = 1e9) { string t = ; for (long long __iii__ = min(x1, SIZE(b)), __jjj__ = min(x2, SIZE(b) - 1); __iii__ <= __jjj__; ++__iii__) { t += b[__iii__] + 0 ; } return + t + ; } template <typename A, typename... C> string to_string(const A(&v), long long x1 = 0, long long x2 = 1e9, C... coords); long long l_v_l_v_l = 0, t_a_b_s = 0; template <typename A, typename B> string to_string(const pair<A, B> &p) { l_v_l_v_l++; string res = ( + to_string(p.first) + , + to_string(p.second) + ) ; l_v_l_v_l--; return res; } template <typename A, typename... C> string to_string(const A(&v), long long x1, long long x2, C... coords) { long long rnk = rank<A>::value; string tab(t_a_b_s, ); string res = ; bool first = true; if (l_v_l_v_l == 0) res += n ; res += tab + [ ; x1 = min(x1, SIZE(v)), x2 = min(x2, SIZE(v)); auto l = begin(v); advance(l, x1); auto r = l; advance(r, (x2 - x1) + (x2 < SIZE(v))); for (auto e = l; e != r; e = next(e)) { if (!first) { res += , ; } first = false; l_v_l_v_l++; if (e != l) { if (rnk > 1) { res += n ; t_a_b_s = l_v_l_v_l; }; } else { t_a_b_s = 0; } res += to_string(*e, coords...); l_v_l_v_l--; } res += ] ; if (l_v_l_v_l == 0) res += n ; return res; } void dbgm() { ; } template <typename Heads, typename... Tails> void dbgm(Heads H, Tails... T) { cerr << to_string(H) << | ; dbgm(T...); } void FIO() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); } const long long N = 2e5 + 6; int32_t main() { FIO(); long long tc; cin >> tc; while (tc--) { long long n, m; cin >> m >> n; vector<vector<long long> > a(m, vector<long long>(n)); vector<long long> v(n, -1); for (long long i = 0; i < m; i++) { for (long long j = 0; j < n; j++) { cin >> a[i][j]; v[j] = max(v[j], a[i][j]); } } long long ans = 1e18; for (long long i = 0; i < n; i++) ans = min(ans, v[i]); if (n <= m) { long long val = -1; for (long long i = 0; i < m; i++) { sort(a[i].begin(), a[i].end()); val = max(val, a[i][n - 2]); } ans = min(ans, val); } cout << ans << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; vector<long long> graph[100005]; vector<pair<long long, long long> > graph_p[100005]; vector<pair<long long, long long> > op; vector<long long> vis(100005, 0); long long power(long long x, long long y) { long long res = 1; x = x % 1000000009; if (x == 0) return 0; while (y > 0) { if (y & 1) res = ((res % 1000000009) * (x % 1000000009)) % 1000000009; y = y >> 1; x = ((x % 1000000009) * (x % 1000000009)) % 1000000009; } return res; } void init_graph(long long n, long long m) { cin >> n >> m; for (long long i = 1; i <= m; i++) { long long a, b; cin >> a >> b; graph[a].push_back(b); graph[b].push_back(a); } } void sieve(long long n) { bool prime[n + 1]; memset(prime, true, sizeof(prime)); for (long long p = 2; p * p <= n; p++) { if (prime[p] == true) { for (long long i = p * p; i <= n; i += p) prime[i] = false; } } } long long n, h, l[2000005], r[2000005], ans; long long sum[2000005], de[2000005]; void we_have_choices() { cin >> n >> h; for (long long i = 1; i <= n; i++) { cin >> l[i] >> r[i]; sum[i] = sum[i - 1] + r[i] - l[i]; if (i == 1) de[i] = 0; else de[i] = de[i - 1] + l[i] - r[i - 1]; } for (long long i = 1; i <= n; i++) { long long pos = lower_bound(de + i, de + n + 1, de[i] + h) - de; ans = max(ans, sum[pos - 1] - sum[i - 1] + h); } cout << ans << n ; } int32_t main() { ios_base::sync_with_stdio(false), cin.tie(nullptr); ; long long t = 1; while (t--) we_have_choices(); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND3_FUNCTIONAL_V
`define SKY130_FD_SC_HD__NAND3_FUNCTIONAL_V
/**
* nand3: 3-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__nand3 (
Y,
A,
B,
C
);
// Module ports
output Y;
input A;
input B;
input C;
// Local signals
wire nand0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y, B, A, C );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND3_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; int t, n, k; char s[4000]; int opx[4000]; int opy[4000]; int count2; void Reverse(char *s, int a, int b) { for (int i = a, j = b; i < j; i++, j--) { char c = s[i]; s[i] = s[j]; s[j] = c; } } int main() { cin >> t; while (t--) { cin >> n >> k; cin >> s; int count1 = 0; while (count1 < 2 * k - 3) { if (s[count1] == ( ) { for (int i = count1 + 1; i < n; i++) { if (s[i] == ) ) { count2++; opx[count2] = count1 + 2; opy[count2] = i + 1; Reverse(s, count1 + 1, i); break; } } } else { for (int i = count1 + 1; i < n; i++) { if (s[i] == ( ) { count2++; opx[count2] = count1 + 1; opy[count2] = i + 1; Reverse(s, count1, i); break; } } } count1 += 2; } while (count1 < n && s[count1] == ( ) count1++; while (count1 < n) { int count3 = count1; while (count3 < n && s[count3] == ) ) count3++; if (count3 < n) { count2++; opx[count2] = count1 + 1; opy[count2] = count3 + 1; Reverse(s, count1, count3); count1++; } else { break; } } cout << count2 << endl; for (int i = 1; i <= count2; i++) { cout << opx[i] << << opy[i] << endl; } count2 = 0; } } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t, n; cin >> t; while (t--) { string A, B; cin >> n; cin >> A >> B; int f = 1; for (int i = 0; i < n; ++i) { if (A[i] > B[i]) f = 0; } if (!f) { cout << -1 << n ; continue; } int ans = 0; for (int i = 0; i < 26; ++i) { bitset<27> good; for (int j = 0; j < n; ++j) { if (A[j] == B[j]) continue; if (B[j] == char( a + i)) { good[A[j] - a ] = 1; } } ans += good.count(); for (int j = 0; j < n; ++j) { if (A[j] == B[j]) continue; if (good[A[j] - a ] == 1) A[j] = char( a + i); } } cout << ans << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int z[100001]; int main() { string s; int T, a, b; cin >> s; for (a = 1; a < s.size(); a++) { z[a] = z[a - 1] + (s[a] == s[a - 1]); } for (cin >> T; T--; cout << z[b - 1] - z[a - 1] << endl) cin >> a >> b; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, x; set<int> ase; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &x); if (ase.size() >= x) { ase.insert(x); } else { cout << i << endl; return 0; } } cout << -1 << endl; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND3_TB_V
`define SKY130_FD_SC_HS__AND3_TB_V
/**
* and3: 3-input AND.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__and3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 B = 1'b1;
#160 C = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 B = 1'b0;
#260 C = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 C = 1'b1;
#380 B = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 C = 1'bx;
#480 B = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hs__and3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND3_TB_V
|
//----------------------------------------------------------------------------
//-- Prueba de tranmision 3. Transmision periódica del caracter K, cada
//-- 250ms
//----------------------------------------------------------------------------
//-- (C) BQ. September 2015. Written by Juan Gonzalez (Obijuan)
//-- GPL license
//----------------------------------------------------------------------------
//-- Although this transmitter has been written from the scratch, it has been
//-- inspired by the one developed in the swapforth proyect by James Bowman
//--
//-- https://github.com/jamesbowman/swapforth
//--
//----------------------------------------------------------------------------
`default_nettype none
`include "baudgen.vh"
`include "divider.vh"
//--- Modulo que envia un caracter cunado load esta a 1
module baudtx3(input wire clk, //-- Reloj del sistema (12MHz en ICEstick)
output wire tx //-- Salida de datos serie (hacia el PC)
);
//-- Parametro: velocidad de transmision
parameter BAUD = `B115200;
parameter DELAY = `T_250ms;
//-- Registro de 10 bits para almacenar la trama a enviar:
//-- 1 bit start + 8 bits datos + 1 bit stop
reg [9:0] shifter;
//-- Reloj para la transmision
wire clk_baud;
//-- Señal de carga periodica
wire load;
//-- Señal de load sincronizada con clk_baud
reg load2;
//-- Registro de desplazamiento, con carga paralela
//-- Cuando DTR es 0, se carga la trama
//-- Cuando DTR es 1 se desplaza hacia la derecha, y se
//-- introducen '1's por la izquierda
always @(posedge clk_baud)
if (load2 == 0)
shifter <= {"K",2'b01};
else
shifter <= {1'b1, shifter[9:1]};
//-- Sacar por tx el bit menos significativo del registros de desplazamiento
//-- Cuando estamos en modo carga (dtr == 0), se saca siempre un 1 para
//-- que la linea este siempre a un estado de reposo. De esta forma en el
//-- inicio tx esta en reposo, aunque el valor del registro de desplazamiento
//-- sea desconocido
assign tx = (load2) ? shifter[0] : 1;
//-- Sincronizar la señal load con clk_baud
//-- Si no se hace, 1 de cada X caracteres enviados tendrá algún bit
//-- corrupto (en las pruebas con la icEstick salian mal 1 de cada 13 aprox
always @(posedge clk_baud)
load2 <= load;
//-- Divisor para obtener el reloj de transmision
divider #(BAUD)
BAUD0 (
.clk_in(clk),
.clk_out(clk_baud)
);
//-- Divisor para generar la señal de carga periodicamente
divider #(DELAY)
DIV0 (
.clk_in(clk),
.clk_out(load)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cout.precision(10); int n; cin >> n; if (n % 2) { cout << black n ; } else { cout << white n ; cout << 1 << << 2 << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, flag = 0, i, j; cin >> a >> b >> c; for (i = 0; i <= c; i++) { for (j = 0; j <= c; j++) { if (a * i + b * j == c) { flag = 1; break; } } if (flag == 1) break; } if (flag == 1) cout << Yes n ; else cout << No n ; } |
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const int N = 510; int m; long long n, ans; int cnt, head[N]; struct edge { int to, next; } e[1010]; void ade(int u, int v) { e[++cnt] = (edge){v, head[u]}; head[u] = cnt; } long long getsize(long long num) { if (num > n) return 0; long long tl = num, tr = num; int m1 = 0, m2 = 0; while (tl * 2 <= n) tl = tl * 2, m1++; while (tr * 2 + 1 <= n) tr = tr * 2 + 1, m2++; if (tl <= tr) return (1 << (m2 + 1)) - 1; else return (1 << (m2 + 1)) - 1 + n - tl + 1; } map<int, int> vis; int tot; long long val[N]; void build(int x) { val[vis[x]] = 1; int to = x << 1; if (to <= n && vis[to]) { build(to); ade(vis[x], vis[to]); ade(vis[to], vis[x]); } else val[vis[x]] += getsize(to); to = x << 1 | 1; if (to <= n && vis[to]) { build(to); ade(vis[x], vis[to]); ade(vis[to], vis[x]); } else val[vis[x]] += getsize(to); } int bk[N]; void dfs(int now, long long w) { bk[now] = 1; for (int i = head[now]; i; i = e[i].next) { int to = e[i].to; if (bk[to]) continue; dfs(to, w); ans = (ans + w * val[to] % mod) % mod; } bk[now] = 0; } int main() { cin >> n >> m; if (!m) { ans = n * n % mod; ans = (ans % mod + mod) % mod; printf( %lld n , ans); } else { for (int i = 1; i <= m; i++) { int a, b; cin >> a >> b; if (!vis[a]) vis[a] = ++tot; if (!vis[b]) vis[b] = ++tot; ade(vis[a], vis[b]); ade(vis[b], vis[a]); while (a) { a >>= 1; if (!vis[a]) vis[a] = ++tot; } while (b) { b >>= 1; if (!vis[b]) vis[b] = ++tot; } } build(1); for (int i = 1; i <= tot; i++) dfs(i, val[i]); for (int i = 1; i <= tot; i++) ans = (ans + val[i] * val[i] % mod) % mod; printf( %lld n , ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> void print_array(T arr[], int size_arr) { for (int i = (0); i < (size_arr); i++) { cout << arr[i]; if (i == size_arr - 1) cout << endl; else cout << ; } } template <typename T> void print_vector(vector<T> v) { for (int i = (0); i < (v.size()); i++) { cout << v[i]; if (i == v.size() - 1) cout << endl; else cout << ; } } template <typename T> void memset_array(T arr[], T value, int size_arr) { for (int i = (0); i < (size_arr); i++) { arr[i] = value; } } bool compare_lexical_string(string a, string b) { for (int i = (0); i < (min(a.length(), b.length())); i++) { if (a[i] != b[i]) return a[i] < b[i]; } return a.length() < b.length(); } struct lex_string { bool operator()(string a, string b) { return compare_lexical_string(a, b); } }; int main() { ios_base::sync_with_stdio(0); cin.tie(0); long long b, d, s; cin >> b >> d >> s; long long max_num, min_num; max_num = max(b, max(d, s)); min_num = min(b, min(d, s)); if (max_num == min_num) cout << 0 << endl; else { if (max_num == b) { long long count = 0; if (d < b) count += b - 1 - d; if (s < b) count += b - 1 - s; cout << count << endl; } else if (max_num == d) { if (d == s) cout << d - 1 - b << endl; else { cout << 2 * d - 2 - b - s << endl; } } else { cout << s - 1 - b + s - 1 - d << endl; } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XOR3_1_V
`define SKY130_FD_SC_HDLL__XOR3_1_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog wrapper for xor3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__xor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__xor3_1 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__xor3_1 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XOR3_1_V
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_eb_e
//
// Generated
// by: wig
// on: Thu Jul 6 05:51:58 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../autoopen.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_eb_e.v,v 1.4 2006/07/10 07:30:09 wig Exp $
// $Date: 2006/07/10 07:30:09 $
// $Log: inst_eb_e.v,v $
// Revision 1.4 2006/07/10 07:30:09 wig
// Updated more testcasess.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of inst_eb_e
//
// No user `defines in this module
module inst_eb_e
//
// Generated Module inst_eb
//
(
s_eo2
);
// Generated Module Inputs:
input s_eo2;
// Generated Wires:
wire s_eo2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_eba
inst_eba_e inst_eba (
);
// End of Generated Instance Port Map for inst_eba
endmodule
//
// End of Generated Module rtl of inst_eb_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; const int N = 3000 + 5; int n, m; int l[N][N], r[N][N], cnt[N], fen[N]; char s[N][N]; vector<int> del[N]; void up(int x, int k) { cnt[x] += k; for (; x; x -= x & -x) fen[x] += k; } int get(int x) { int res = 0; for (; x < N; x += x & -x) res += fen[x]; return res; } long long start(int x, int y) { memset(fen, 0, sizeof(fen)); memset(cnt, 0, sizeof(cnt)); for (int i = 1; i <= n; i++) del[i].clear(); long long ans = 0; int go = x; while (x <= n and y >= 1) { for (auto u : del[x]) up(u, -1); if (s[x][y] == . ) { for (int i = go; i < x; i++) if (cnt[i]) up(i, -1); go = x + 1; x++; y--; continue; } up(x, +1); if (x + l[x][y] <= n) del[x + l[x][y]].push_back(x); int len = min(r[x][y], x - go + 1); ans += get(x - len + 1); x++; y--; } return ans; } int main() { scanf( %d %d , &n, &m); for (int i = 1; i <= n; i++) { scanf( %s , s[i] + 1); for (int j = 1; j <= m; j++) { l[i][j] = s[i][j] == z ? l[i][j - 1] + 1 : 0; } for (int j = m; j >= 1; j--) { r[i][j] = s[i][j] == z ? r[i][j + 1] + 1 : 0; } } long long ans = 0; for (int i = 1; i <= m; i++) { ans += start(1, i); } for (int i = 2; i <= n; i++) { ans += start(i, m); } printf( %lld n , ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR4_TB_V
`define SKY130_FD_SC_HS__OR4_TB_V
/**
* or4: 4-input OR.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__or4.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg D;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 C = 1'b1;
#200 D = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 C = 1'b0;
#320 D = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 D = 1'b1;
#440 C = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 D = 1'bx;
#560 C = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hs__or4 dut (.A(A), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR4_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR2_2_V
`define SKY130_FD_SC_HS__OR2_2_V
/**
* or2: 2-input OR.
*
* Verilog wrapper for or2 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__or2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or2_2 (
X ,
A ,
B ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
sky130_fd_sc_hs__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or2_2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR2_2_V
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int N = 1e6 + 5; long long dp[105], cnt[105], b[N], a[N]; void add(long long &a, long long b) { a += b; if (a >= mod) a -= mod; } struct Mat { long long t[101][101]; Mat() { memset(t, 0, sizeof t); } } I; int m; Mat operator*(Mat a, Mat b) { Mat c; for (int i = 0; i < m; i++) for (int j = 0; j < m; j++) { long long t = 0; for (int k = 0; k < m; k++) { add(c.t[i][j], a.t[i][k] * b.t[k][j] % mod); } } return c; } Mat Pow(Mat a, int b) { Mat c = I; while (b) { if (b & 1) c = c * a; a = a * a; b >>= 1; } return c; } int main() { int n, l, x; cin >> n >> l >> m; for (int i = 0; i < m; i++) dp[i] = 0, cnt[i] = 0; for (int i = 1; i <= n; i++) scanf( %d , &x), dp[x % m]++; for (int i = 1; i <= n; i++) scanf( %lld , &a[i]), cnt[a[i] % m]++; for (int i = 1; i <= n; i++) scanf( %lld , &b[i]); for (int i = 0; i < m; i++) I.t[0][i] = dp[i]; Mat pi; for (int i = 0; i < m; i++) for (int j = 0; j < m; j++) pi.t[i][j] = cnt[(m - i + j) % m]; Mat ans = Pow(pi, l - 2); for (int i = 0; i < m; i++) cnt[i] = 0, dp[i] = 0; for (int i = 1; i <= n; i++) { cnt[(a[i] + b[i]) % m]++; } for (int i = 0; i < m; i++) for (int j = 0; j < m; j++) add(dp[(j + i) % m], ans.t[0][j] * cnt[i] % mod); printf( %lld n , dp[0]); } |
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for i2s_tx
*/
module test_i2s_tx;
// Parameters
parameter WIDTH = 16;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [WIDTH-1:0] input_l_tdata = 0;
reg [WIDTH-1:0] input_r_tdata = 0;
reg input_tvalid = 0;
reg sck = 0;
reg ws = 0;
// Outputs
wire input_tready;
wire sd;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_l_tdata,
input_r_tdata,
input_tvalid,
sck,
ws);
$to_myhdl(input_tready,
sd);
// dump file
$dumpfile("test_i2s_tx.lxt");
$dumpvars(0, test_i2s_tx);
end
i2s_tx #(
.WIDTH(WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
.input_l_tdata(input_l_tdata),
.input_r_tdata(input_r_tdata),
.input_tvalid(input_tvalid),
.input_tready(input_tready),
.sck(sck),
.ws(ws),
.sd(sd)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[1505]; int main() { ios::sync_with_stdio(false), cin.tie(0); int n; cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; } bool isEven = true; for (int i = 1; i <= n; i++) { for (int j = i + 1; j <= n; j++) { if (a[i] > a[j]) { isEven ^= 1; } } } int q; cin >> q; for (int qq = 0; qq < q; qq++) { int l, r; cin >> l >> r; int len = r - l + 1; isEven ^= ((len * (len - 1)) / 2) % 2; cout << (isEven ? even : odd ) << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int DN = 3e5 + 5; int n, m, sol, f, cnt, mi = 1e9, sum; char ch[6], a[5][5], car; string s[DN], r[DN]; void solve1() { cnt++; sum = 0; int f, mi; for (int i = 1; i <= n; i++) { f = 0; for (int j = 1; j <= m; j++) { car = a[i % 2][j % 2]; if (s[i][j] != car) f++; r[i][j] = car; } mi = f; f = 0; for (int j = 1; j <= m; j++) { car = a[i % 2][1 - j % 2]; if (s[i][j] != car) f++; } if (f < mi) { mi = f; for (int j = 1; j <= m; j++) { car = a[i % 2][1 - j % 2]; r[i][j] = car; } } sum += mi; } } void solve2() { cnt++; sum = 0; int f, mi; for (int j = 1; j <= m; j++) { f = 0; for (int i = 1; i <= n; i++) { car = a[i % 2][j % 2]; if (s[i][j] != car) f++; r[i][j] = car; } mi = f; f = 0; for (int i = 1; i <= n; i++) { car = a[1 - i % 2][j % 2]; if (s[i][j] != car) f++; } if (f < mi) { mi = f; for (int i = 1; i <= n; i++) { car = a[1 - i % 2][j % 2]; r[i][j] = car; } } sum += mi; } } void solve() { cnt = 0; ch[1] = A ; ch[2] = G ; ch[3] = C ; ch[4] = T ; do { a[0][0] = ch[1]; a[0][1] = ch[2]; a[1][0] = ch[3]; a[1][1] = ch[4]; solve1(); if (sum < mi) { mi = sum; f = cnt; } if (sum == sol) return; solve2(); if (sum < mi) { mi = sum; f = cnt; } if (sum == sol) return; } while (next_permutation(ch + 1, ch + 5)); sol = mi; } int main() { cin.sync_with_stdio(false); cout.sync_with_stdio(false); cin >> n >> m; for (int i = 0; i <= n; i++) getline(cin, s[i]); for (int i = 1; i <= n; i++) { s[i] = + s[i]; r[i] = s[i]; } solve(); solve(); for (int i = 1; i <= n; i++) r[i].erase(r[i].begin()); for (int i = 1; i <= n; i++) cout << r[i] << n ; } |
#include <bits/stdc++.h> using namespace std; long long n, i, j, ans = 0; long long a, b; const long long M = (long long)1E9 + 7; long long power(long long x, long long y) { long long res = 1; x %= M; while (y) { if (y % 2) res = (res * x) % M; y = y >> 1; x = (x * x) % M; } return res % M; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); string s; cin >> s; b = power(2LL, (long long)s.length() - 1); long long x = 1; for (i = (long long)s.length() - 1; i >= 0; i--) { if (s[i] == 1 ) a += x; x *= 2; if (x > M) x %= M; a %= M; } cout << (a * b) % M; } |
#include <bits/stdc++.h> using namespace std; int n, m; int dp[800][800][10]; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { int x, y; scanf( %d%d , &x, &y); dp[x][y][1]++; dp[y][x][1]++; } for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) if (i != j) for (int q = 1; q <= n; q++) if (q != i && q != j) { dp[i][j][2] += dp[i][q][1] * dp[j][q][1]; } for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) if (i != j) { for (int q = 1; q <= n; q++) if (q != i && q != j) { dp[i][j][3] += dp[i][q][2] * dp[j][q][1] + dp[i][q][1] * dp[j][q][2] - dp[i][j][1] * dp[i][q][1] * dp[i][q][1] - dp[i][j][1] * dp[j][q][1] * dp[j][q][1]; } dp[i][j][3] /= 2; } long long sum = 0; for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) if (i != j && dp[i][j][3] != 0 && dp[i][j][2] != 0) { for (int q = 1; q <= n; q++) if (q != i && q != j && dp[i][q][1] != 0 && dp[j][q][1] != 0) { sum += dp[i][j][3]; sum -= dp[j][q][2] - dp[i][j][1] + dp[i][q][2] - dp[i][j][1]; } } printf( %lld , sum / 10); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, a[110], b[110], sum = 0; pair<int, int> dp[110][11000], q = {-1, -1}; pair<int, int> Rec(int i, int W) { if (i == n) { if (W >= sum) return {0, 0}; else return {1e9, 1e9}; } if (dp[i][W] != q) return dp[i][W]; pair<int, int> Res1 = {1e9, 1e9}, Res2 = {1e9, 1e9}; Res1 = {0 + Rec(i + 1, W).first, a[i] + Rec(i + 1, W).second}; Res2 = {1 + Rec(i + 1, W + b[i]).first, 0 + Rec(i + 1, W + b[i]).second}; return dp[i][W] = min(Res1, Res2); } int main() { memset(dp, -1, sizeof(dp)); cin >> n; for (int i = 0; i < n; i++) cin >> a[i], sum += a[i]; for (int i = 0; i < n; i++) cin >> b[i]; cout << Rec(0, 0).first << << Rec(0, 0).second; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A32OI_1_V
`define SKY130_FD_SC_MS__A32OI_1_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog wrapper for a32oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a32oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a32oi_1 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a32oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a32oi_1 (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a32oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A32OI_1_V
|
#include <bits/stdc++.h> using namespace std; using ll = long long; template <typename A, typename B = A> using pr = pair<A, B>; int main() { ios::sync_with_stdio(false), cin.tie(nullptr); cout << fixed << setprecision(10); int sy, a, b; cin >> sy >> a >> b; sy = -sy; int n; cin >> n; vector<pr<int>> segs(n); for (auto &[x, y] : segs) cin >> y >> x; sort((segs).begin(), (segs).end()); vector<ll> pref(n + 1); for (int i = 0; i < n; i++) pref[i + 1] = pref[i] + segs[i].first - segs[i].second; int q; cin >> q; while (q--) { int x, y; cin >> x >> y; auto get = [&](int k) { return (k - x) * double(y) / (sy + y); }; double x1 = x + get(a); double x2 = x + get(b); auto find = [&](double x) { return int(upper_bound((segs).begin(), (segs).end(), pr<int>{ceil(x + 1e-6), -1}) - segs.begin()); }; int i1 = find(x1); int i2 = find(x2); double sum = 0; if (i2 != i1) { sum += pref[i2] - pref[i1 + 1]; if (i1 != -1) sum += min<double>(segs[i1].first - segs[i1].second, segs[i1].first - x1); if (i2 != n) sum += max<double>(0, x2 - segs[i2].second); } else { int i = i2; if (i != -1 && i != n) sum += max<double>(0, min<double>(segs[i].first, x2) - max<double>(segs[i].second, x1)); } cout << sum * (sy + y) / y << n ; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV3SD1_1_V
`define SKY130_FD_SC_MS__CLKDLYINV3SD1_1_V
/**
* clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
* stage gate.
*
* Verilog wrapper for clkdlyinv3sd1 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__clkdlyinv3sd1.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__clkdlyinv3sd1_1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__clkdlyinv3sd1 base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__clkdlyinv3sd1_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__clkdlyinv3sd1 base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV3SD1_1_V
|
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