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#include <bits/stdc++.h> using namespace std; long long arr[105], k; int n; bool check(long long x) { long long sum = 0; for (int i = 0; i < n; i++) { sum += (arr[i] + x - 1LL) / x; } return x * sum <= k; } int main(int argc, char const *argv[]) { cin >> n >> k; for (int i = 0; i < n; i++) cin >> arr[i], k += arr[i]; long long ans = 0; for (long long i = 1; i <= sqrt(k) + 1; i++) { if (check(i)) ans = max(ans, i); if (check(k / i)) ans = max(ans, k / i); } cout << ans << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLRTP_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__DLRTP_PP_SYMBOL_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__dlrtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLRTP_PP_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:04:15 03/13/2015
// Design Name:
// Module Name: PreProcessX
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module PreProcessX(
input [31:0] z_preprocess,
input [3:0] Opcode,
input [31:0] b_adder,
input [7:0] InsTagIn,
input clock,
output [31:0] FinalSum,
output Done,
output [31:0] z_postprocess,
output [3:0] Opcode_out,
output [7:0] InsTagOut
);
reg [31:0] a_adder_reg = 32'h3f800000;
wire [31:0] a_adder;
assign a_adder = a_adder_reg;
wire idle_Special,idle_Allign,idle_AddState,idle_NormaliseSum;
wire [3:0] Opcode_Special,Opcode_Allign,Opcode_AddState,Opcode_NormaliseSum;
wire [31:0] z_postSpecial,z_postAllign,z_postAddState,z_postNormaliseSum;
wire [31:0] sout_Special,sout_Allign,sout_AddState,sout_NormaliseSum;
wire [35:0] cout_Special,cout_Allign;
wire [35:0] zout_Special,zout_Allign;
wire [7:0] difference_Special;
wire [27:0] sum_AddState,sum_NormaliseSum;
wire [31:0] FinalSum_Idle1,FinalSum_Idle2,FinalSum_Idle3;
wire [7:0] InsTagSpecial,InsTagAllign,InsTagAdder,InsTagNormaliseAdder;
SpecialAddProcess Add1 (
.z_preSpecial(z_preprocess),
.Opcode(Opcode),
.cin_Special(a_adder),
.zin_Special(b_adder),
.InsTagIn(InsTagIn),
.clock(clock),
.idle_Special(idle_Special),
.difference_Special(difference_Special),
.cout_Special(cout_Special),
.zout_Special(zout_Special),
.sout_Special(sout_Special),
.Opcode_Special(Opcode_Special),
.z_postSpecial(z_postSpecial),
.InsTagSpecial(InsTagSpecial)
);
AllignAdderProcess Add2 (
.z_postSpecial(z_postSpecial),
.Opcode_Special(Opcode_Special),
.idle_Special(idle_Special),
.cout_Special(cout_Special),
.zout_Special(zout_Special),
.sout_Special(sout_Special),
.difference_Special(difference_Special),
.InsTagSpecial(InsTagSpecial),
.clock(clock),
.idle_Allign(idle_Allign),
.cout_Allign(cout_Allign),
.zout_Allign(zout_Allign),
.sout_Allign(sout_Allign),
.Opcode_Allign(Opcode_Allign),
.z_postAllign(z_postAllign),
.InsTagAllign(InsTagAllign)
);
AddProcess Add3 (
.z_postAllign(z_postAllign),
.Opcode_Allign(Opcode_Allign),
.idle_Allign(idle_Allign),
.cout_Allign(cout_Allign),
.zout_Allign(zout_Allign),
.sout_Allign(sout_Allign),
.InsTagAllign(InsTagAllign),
.clock(clock),
.idle_AddState(idle_AddState),
.sout_AddState(sout_AddState),
.sum_AddState(sum_AddState),
.Opcode_AddState(Opcode_AddState),
.z_postAddState(z_postAddState),
.InsTagAdder(InsTagAdder)
);
NormaliseAdderProcess Add4 (
.z_postAddState(z_postAddState),
.Opcode_AddState(Opcode_AddState),
.idle_AddState(idle_AddState),
.sout_AddState(sout_AddState),
.sum_AddState(sum_AddState),
.InsTagAdder(InsTagAdder),
.clock(clock),
.idle_NormaliseSum(idle_NormaliseSum),
.sout_NormaliseSum(sout_NormaliseSum),
.sum_NormaliseSum(sum_NormaliseSum),
.Opcode_NormaliseSum(Opcode_NormaliseSum),
.z_postNormaliseSum(z_postNormaliseSum),
.InsTagNormaliseAdder(InsTagNormaliseAdder)
);
PackAdderProcess Add5 (
.z_postNormaliseSum(z_postNormaliseSum),
.Opcode_NormaliseSum(Opcode_NormaliseSum),
.idle_NormaliseSum(idle_NormaliseSum),
.sout_NormaliseSum(sout_NormaliseSum),
.sum_NormaliseSum(sum_NormaliseSum),
.InsTagNormaliseAdder(InsTagNormaliseAdder),
.clock(clock),
.sout_PackSum(FinalSum),
.Done(Done),
.z_postPack(z_postprocess),
.Opcode_Pack(Opcode_out),
.InsTagPack(InsTagOut)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; bool ch1(int t, int da, int db, int a, int b, int x) { for (int i = 0; i <= t - 1; i++) { for (int j = 0; j <= t - 1; j++) { if (((a - i * da + b - j * db == x) && (a - i * da >= 0 && b - j * db >= 0)) || a - i * da == x || b - j * db == x) return true; } } return false; } int main() { int x, a, b, t, da, db, total; cin >> x >> t >> a >> b >> da >> db; total = a + b; if (x > total) cout << NO n ; else if (x == 0) cout << YES n ; else { if (ch1(t, da, db, a, b, x)) { cout << YES n ; } else { cout << NO n ; } } return 0; } |
#include <bits/stdc++.h> int main() { int n, i, cnt1 = 0, cnt2 = 0, cnt3 = 0, cnt4 = 0, cnt5 = 0, cnt6 = 0; char x[10]; scanf( %d , &n); for (i = 0; i < n; i++) { scanf( %s , x); if (x[0] == p ) { cnt1++; } else if (x[0] == g ) { cnt2++; } else if (x[0] == b ) { cnt3++; } else if (x[0] == o ) { cnt4++; } else if (x[0] == r ) { cnt5++; } else if (x[0] == y ) { cnt6++; } } printf( %d n , 6 - n); if (cnt1 == 0) { printf( Power n ); } if (cnt2 == 0) { printf( Time n ); } if (cnt3 == 0) { printf( Space n ); } if (cnt4 == 0) { printf( Soul n ); } if (cnt5 == 0) { printf( Reality n ); } if (cnt6 == 0) { printf( Mind n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, q, a[300010], f[300010], ans[300010], g[300010]; struct edge { long long v, next; } e[300010 << 1]; long long eid, p[300010]; void insert(long long u, long long v) { e[++eid] = {v, p[u]}; p[u] = eid; } long long dep[300010], cnt, c[300010], d[300010], siz[300010]; pair<long long, long long> b[300010]; void dfs(long long u, long long f) { siz[u] = 1; c[u] = ++cnt, d[cnt] = u; dep[u] = dep[f] + 1; b[u] = make_pair(dep[u], c[u]); for (int i = p[u]; i; i = e[i].next) { long long v = e[i].v; if (v == f) continue; dfs(v, u); siz[u] += siz[v]; } } void dfs1(long long u, long long f) { g[u] += g[f]; for (int i = p[u]; i; i = e[i].next) { long long v = e[i].v; if (v == f) continue; dfs1(v, u); } } int main() { ios::sync_with_stdio(false); cin >> n; for (int i = 1; i < n; ++i) { long long u, v; cin >> u >> v; insert(u, v); insert(v, u); } dfs(1, 0); sort(b + 1, b + n + 1); cin >> q; while (q--) { long long v, d, x; cin >> v >> d >> x; a[c[v]] += x, a[c[v] + siz[v]] -= x; long long l = lower_bound(b + 1, b + n + 1, make_pair(dep[v] + d + 1, c[v])) - b; long long r = lower_bound(b + 1, b + n + 1, make_pair(dep[v] + d + 1, c[v] + siz[v])) - b; f[l] -= x, f[r] += x; } for (int i = 1; i <= n; ++i) a[i] += a[i - 1], f[i] += f[i - 1]; for (int i = 1; i <= n; ++i) g[d[b[i].second]] = f[i]; dfs1(1, 0); for (int i = 1; i <= n; ++i) ans[d[i]] += a[i]; for (int i = 1; i <= n; ++i) cout << ans[i] + g[i] << ; cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAX_ROW = 2000 + 7; const int MAX_COLUMN = 200 + 7; const int BASE = 2807; const int MOD = 1e7 + 7; int n, m; char TableA[MAX_ROW][MAX_COLUMN], TableB[MAX_COLUMN][MAX_ROW]; int HashA[MAX_ROW][MAX_COLUMN], HashB[MAX_COLUMN][MAX_ROW], Pow2807[MAX_ROW], HashFinding[MOD]; int GetHash(const int& L, const int& R, const int H[]) { return (1LL * H[R] - 1LL * H[L - 1] * Pow2807[R - L + 1] + 1LL * MOD * MOD) % MOD; } int main() { ios::sync_with_stdio(false); cout.tie(0), cin.tie(0); Pow2807[0] = 1; for (int i = 1; i < MAX_ROW; ++i) Pow2807[i] = 1LL * Pow2807[i - 1] * BASE % MOD; scanf( %d%d , &n, &m); for (int i = 1; i <= n; ++i) scanf( %s , TableA[i] + 1); for (int j = 1; j <= m; ++j) scanf( %s , TableB[j] + 1); for (int i = 1; i <= n; ++i) for (int j = 1; j <= m; ++j) HashA[i][j] = (1LL * HashA[i][j - 1] * BASE + TableA[i][j]) % MOD; for (int i = 1; i <= m; ++i) for (int j = 1; j <= n; ++j) HashB[i][j] = (1LL * HashB[i][j - 1] * BASE + TableB[i][j]) % MOD; for (int j = 1; j <= (n - m + 1); ++j) { int HashBase = 0; for (int k = j; k <= (j + m - 1); ++k) HashBase = (1LL * HashBase * Pow2807[m] + GetHash(1, m, HashA[k])) % MOD; HashFinding[HashBase] = j; } for (int j = 1; j <= (n - m + 1); ++j) { int HashTest = 0; for (int i = 1; i <= m; ++i) HashTest = (1LL * HashTest * Pow2807[m] + GetHash(j, j + m - 1, HashB[i])) % MOD; if (HashFinding[HashTest]) { cout << HashFinding[HashTest] << << j << n ; return 0; } } cout << Error 404! n ; return 0; } |
/*
ORSoC GFX accelerator core
Copyright 2012, ORSoC, Per Lenander, Anton Fosselius.
CLIPPING/SCISSORING MODULE
This file is part of orgfx.
orgfx is free software: you can redistribute it and/or modify
it under the terms of the GNU Lesser General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
orgfx is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public License
along with orgfx. If not, see <http://www.gnu.org/licenses/>.
*/
/*
This module performs clipping by applying the current cliprect and the target size.
This module also performs z-buffer culling (requires reading from memory)
*/
module gfx_clip(clk_i, rst_i,
clipping_enable_i, zbuffer_enable_i,
zbuffer_base_i, target_size_x_i, target_size_y_i,
clip_pixel0_x_i, clip_pixel0_y_i, clip_pixel1_x_i, clip_pixel1_y_i, //clip pixel 0 and pixel 1
raster_pixel_x_i, raster_pixel_y_i, raster_u_i, raster_v_i, flat_color_i, raster_write_i, ack_o, // from raster
cuvz_pixel_x_i, cuvz_pixel_y_i, cuvz_pixel_z_i, cuvz_u_i, cuvz_v_i, cuvz_color_i, cuvz_write_i, // from cuvz
cuvz_a_i, // from cuvz
z_ack_i, z_addr_o, z_data_i, z_sel_o, z_request_o, wbm_busy_i, // from/to wbm reader
pixel_x_o, pixel_y_o, pixel_z_o, u_o, v_o, a_o, // to fragment
bezier_factor0_i, bezier_factor1_i, bezier_factor0_o, bezier_factor1_o, // bezier calculations
color_o, write_o, ack_i // from/to fragment
);
parameter point_width = 16;
input clk_i;
input rst_i;
input clipping_enable_i;
input zbuffer_enable_i;
input [31:2] zbuffer_base_i;
input [point_width-1:0] target_size_x_i;
input [point_width-1:0] target_size_y_i;
//clip pixels
input [point_width-1:0] clip_pixel0_x_i;
input [point_width-1:0] clip_pixel0_y_i;
input [point_width-1:0] clip_pixel1_x_i;
input [point_width-1:0] clip_pixel1_y_i;
// From cuvz
input [point_width-1:0] cuvz_pixel_x_i;
input [point_width-1:0] cuvz_pixel_y_i;
input signed [point_width-1:0] cuvz_pixel_z_i;
input [point_width-1:0] cuvz_u_i;
input [point_width-1:0] cuvz_v_i;
input [7:0] cuvz_a_i;
input [31:0] cuvz_color_i;
input cuvz_write_i;
// From raster
input [point_width-1:0] raster_pixel_x_i;
input [point_width-1:0] raster_pixel_y_i;
input [point_width-1:0] raster_u_i;
input [point_width-1:0] raster_v_i;
input [31:0] flat_color_i;
input raster_write_i;
output reg ack_o;
// Interface against wishbone master (reader)
input z_ack_i;
output [31:2] z_addr_o;
input [31:0] z_data_i;
output reg [3:0] z_sel_o;
output reg z_request_o;
input wbm_busy_i;
// To fragment
output reg [point_width-1:0] pixel_x_o;
output reg [point_width-1:0] pixel_y_o;
output reg [point_width-1:0] pixel_z_o;
output reg [point_width-1:0] u_o;
output reg [point_width-1:0] v_o;
output reg [7:0] a_o;
input [point_width-1:0] bezier_factor0_i;
input [point_width-1:0] bezier_factor1_i;
output reg [point_width-1:0] bezier_factor0_o;
output reg [point_width-1:0] bezier_factor1_o;
output reg [31:0] color_o;
output reg write_o;
input ack_i;
//
// State machine
reg [1:0] state;
parameter wait_state = 2'b00, z_read_state = 2'b01, write_pixel_state = 2'b10;
// Calculate address of target pixel
// Addr[31:2] = Base + (Y*width + X) * ppb
wire [31:0] pixel_offset = (target_size_x_i*cuvz_pixel_y_i + {16'h0, cuvz_pixel_x_i}) << 1; // 16 bit
assign z_addr_o = zbuffer_base_i + pixel_offset[31:2];
wire [31:0] z_value_at_target32;
wire signed [point_width-1:0] z_value_at_target = z_value_at_target32[point_width-1:0];
// Memory to color converter
memory_to_color memory_proc(
.color_depth_i (2'b01),
.mem_i (z_data_i),
.mem_lsb_i (cuvz_pixel_x_i[1:0]),
.color_o (z_value_at_target32),
.sel_o ()
);
// Forward texture coordinates, color, alpha etc
always @(posedge clk_i or posedge rst_i)
if(rst_i)
begin
u_o <= 1'b0;
v_o <= 1'b0;
bezier_factor0_o <= 1'b0;
bezier_factor1_o <= 1'b0;
pixel_x_o <= 1'b0;
pixel_y_o <= 1'b0;
pixel_z_o <= 1'b0;
color_o <= 1'b0;
a_o <= 1'b0;
z_sel_o <= 4'b1111;
end
else
begin
// Implement a MUX, send data from either the raster or from the cuvz module to the fragment processor
if(raster_write_i)
begin
u_o <= raster_u_i;
v_o <= raster_v_i;
a_o <= 8'hff;
color_o <= flat_color_i;
pixel_x_o <= raster_pixel_x_i;
pixel_y_o <= raster_pixel_y_i;
pixel_z_o <= 1'b0;
end
// If the cuvz module is being used, more parameters needs to be forwarded
else if(cuvz_write_i)
begin
u_o <= cuvz_u_i;
v_o <= cuvz_v_i;
a_o <= cuvz_a_i;
color_o <= cuvz_color_i;
pixel_x_o <= cuvz_pixel_x_i;
pixel_y_o <= cuvz_pixel_y_i;
pixel_z_o <= cuvz_pixel_z_i;
bezier_factor0_o <= bezier_factor0_i;
bezier_factor1_o <= bezier_factor1_i;
end
end
// Check if we should discard this pixel due to failing depth check
wire fail_z_check = z_value_at_target > cuvz_pixel_z_i;
// Check if we should discard this pixel due to falling outside render target/clip rect
wire outside_target = raster_write_i ? (raster_pixel_x_i >= target_size_x_i) | (raster_pixel_y_i >= target_size_y_i) :
(cuvz_pixel_x_i >= target_size_x_i) | (cuvz_pixel_y_i >= target_size_y_i);
wire outside_clip = raster_write_i ? (raster_pixel_x_i < clip_pixel0_x_i) | (raster_pixel_y_i < clip_pixel0_y_i) | (raster_pixel_x_i >= clip_pixel1_x_i) | (raster_pixel_y_i >= clip_pixel1_y_i) :
(cuvz_pixel_x_i < clip_pixel0_x_i) | (cuvz_pixel_y_i < clip_pixel0_y_i) | (cuvz_pixel_x_i >= clip_pixel1_x_i) | (cuvz_pixel_y_i >= clip_pixel1_y_i);
wire discard_pixel = outside_target | (clipping_enable_i & outside_clip);
// Check if there is a write signal
wire write_i = raster_write_i | cuvz_write_i;
// Acknowledge when a command has completed
always @(posedge clk_i or posedge rst_i)
// reset, init component
if(rst_i)
begin
ack_o <= 1'b0;
write_o <= 1'b0;
z_request_o <= 1'b0;
z_sel_o <= 4'b1111;
end
// Else, set outputs for next cycle
else
begin
case (state)
wait_state:
begin
if(write_i)
ack_o <= discard_pixel;
else
ack_o <= 1'b0;
if(write_i & zbuffer_enable_i)
z_request_o <= ~discard_pixel;
else if(write_i)
write_o <= ~discard_pixel;
end
// Do a depth check. If it fails, discard pixel, ack and go back to wait. If it succeeds, go to write state
z_read_state:
if(z_ack_i)
begin
write_o <= ~fail_z_check;
ack_o <= fail_z_check;
z_request_o <= 1'b0;
end
else
z_request_o <= ~wbm_busy_i | z_request_o;
// ack, then go back to wait state when the next module is ready
write_pixel_state:
begin
write_o <= 1'b0;
if(ack_i)
ack_o <= 1'b1;
end
endcase
end
// State machine
always @(posedge clk_i or posedge rst_i)
// reset, init component
if(rst_i)
state <= wait_state;
// Move in statemachine
else
case (state)
wait_state:
if(write_i & ~discard_pixel)
begin
if(zbuffer_enable_i)
state <= z_read_state;
else
state <= write_pixel_state;
end
z_read_state:
if(z_ack_i)
state <= fail_z_check ? wait_state : write_pixel_state;
write_pixel_state:
if(ack_i)
state <= wait_state;
endcase
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 100100, M = 32401000, S = 90, oo = 1000000000; int i, j, k, n, m, ch, ff; int s[N]; int F[M]; void R(int &x) { ff = x = 0; while (ch < 0 || 9 < ch) { if (ch == - ) ff = 1; ch = getchar(); } while ( 0 <= ch && ch <= 9 ) x = x * 10 + ch - 0 , ch = getchar(); if (ff) x = -x; } int P(int l, int r, int k) { int t = 0; l--; r--; k--; t = (l * S * 2 + n - r - l + S) * S + k; return t; } int min(const int &x, const int &y) { if (x < y) return x; return y; } int max(const int &x, const int &y) { if (x > y) return x; return y; } int f(int l, int r, int k, int o) { if (r - l + 1 < k) return 0; if (o == 1) { int ans = f(l, r - k, k, 0) - s[r] + s[r - k]; if (r - l + 1 >= k + 1) ans = min(ans, f(l, r - k - 1, k + 1, 0) - s[r] + s[r - k - 1]); return ans; } else { int t = P(l, r, k); if (F[t] < oo) return F[t]; int ans; ans = s[l + k - 1] - s[l - 1] + f(l + k, r, k, 1); if (r - l + 1 >= k + 1) ans = max(ans, s[l + k] - s[l - 1] + f(l + k + 1, r, k + 1, 1)); return F[t] = ans; } } int main() { memset(F, 60, sizeof F); R(n); for (i = 1; i <= n; i++) R(s[i]), s[i] += s[i - 1]; printf( %d n , f(1, n, 1, 0)); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__NOR3_FUNCTIONAL_PP_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__nor3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , C, A, B );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR3_FUNCTIONAL_PP_V |
/*
* Copyright (c) 1998 Philips Semiconductors ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module test();
MUX_REG_8x8 PAGE_REG_B3 (
.CLK (CLK),
/*
.IN (DATA_RES[31:24]),
.OUT (PAGE[31:24]),
.EN_IN (EN_B3),
.EN_OUT (PAGE_SEL),
*/
.TC (),
.TD (),
.TQ ());
endmodule
|
module problem3(out, in1, in2);
output [9:0] out;
input [4:0] in1, in2;
wire [4:0] pp1, pp2, pp3, pp4, pp5;
wire c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15, c16, c17, c18, c19, c20, c21, c22, c23, c24, c25, c26;
wire s2, s4, s5, s7, s8, s9, s11, s12, s13, s15, s16, s17, s19, s20, s21, s23, s24, s25;
assign pp1 = {in1[4] && in2[0], in1[3] && in2[0], in1[2] && in2[0], in1[1] && in2[0], in1[0] && in2[0]};
assign pp2 = {in1[4] && in2[1], in1[3] && in2[1], in1[2] && in2[1], in1[1] && in2[1], in1[0] && in2[1]};
assign pp3 = {in1[4] && in2[2], in1[3] && in2[2], in1[2] && in2[2], in1[1] && in2[2], in1[0] && in2[2]};
assign pp4 = {in1[4] && in2[3], in1[3] && in2[3], in1[2] && in2[3], in1[1] && in2[3], in1[0] && in2[3]};
assign pp5 = {in1[4] && in2[4], in1[3] && in2[4], in1[2] && in2[4], in1[1] && in2[4], in1[0] && in2[4]};
assign out[0] = pp1[0];
CPA CPA1(out[1], c1, pp1[1], pp2[0], 1'b0);
CPA CPA2(s2, c2, pp1[2], pp2[1], c1);
CPA CPA3(out[2], c3, s2, pp3[0], c2);
CPA CPA4(s4, c4, pp1[3], pp2[2], c3);
CPA CPA5(s5, c5, s4, pp3[1], c4);
CPA CPA6(out[3], c6, s5, pp4[0], c5);
CPA CPA7(s7, c7, pp1[4], pp2[3], c6);
CPA CPA8(s8, c8, s7, pp3[2], c7);
CPA CPA9(s9, c9, s8, pp4[1], c8);
CPA CPA10(out[4], c10, s9, pp5[0], c9);
CPA CPA11(s11, c11, pp1[4], pp2[4], c10);
CPA CPA12(s12, c12, s11, pp3[3], c11);
CPA CPA13(s13, c13, s12, pp4[2], c12);
CPA CPA14(out[5], c14, s13, pp5[1], c13);
CPA CPA15(s15, c15, pp1[4], pp2[4], c14);
CPA CPA16(s16, c16, s15, pp3[4], c15);
CPA CPA17(s17, c17, s16, pp4[3], c16);
CPA CPA18(out[6], c18, s17, pp5[2], c17);
CPA CPA19(s19, c19, pp1[4], pp2[4], c18);
CPA CPA20(s20, c20, s19, pp3[4], c19);
CPA CPA21(s21, c21, s20, pp4[4], c20);
CPA CPA22(out[7], c22, s21, pp5[3], c21);
CPA CPA23(s23, c23, pp1[4], pp2[4], c22);
CPA CPA24(s24, c24, s23, pp3[4], c23);
CPA CPA25(s25, c25, s24, pp4[4], c24);
CPA CPA26(out[8], c26, s25, pp5[4], c25);
assign out[9] = c26;
endmodule
|
#include <bits/stdc++.h> using namespace std; bool ask(int a, int b, int c, int d) { cout << ? << a << << b << << c << << d << endl; fflush(stdout); string response; cin >> response; if (response == BAD ) { exit(0); } else if (response == YES ) return true; else return false; } int main() { int n; cin >> n; int x = 1, y = 1; string ans1 = , ans2 = ; for (int i = 0; i < n - 1; ++i) { if (ask(x + 1, y, n, n)) { x++; ans1.push_back( D ); } else { y++; ans1.push_back( R ); } } x = n, y = n; for (int i = 0; i < n - 1; ++i) { if (ask(1, 1, x, y - 1)) { y--; ans2.push_back( R ); } else { x--; ans2.push_back( D ); } } reverse((ans2).begin(), (ans2).end()); string finalans = ans1 + ans2; cout << ! << finalans << endl; fflush(stdout); return 0; } |
#include <bits/stdc++.h> using namespace std; int dx[] = {0, -1, 0, 1}; int dy[] = {1, 0, -1, 0}; int c[2010][2010], edge[2010]; long double s[2010], C[2010][2010]; int main(int argc, char *argv[]) { int n, k; scanf( %d%d , &n, &k); for (int i = (1); i <= (n); ++i) { C[i][0] = 1; for (int j = (1); j <= (i); ++j) C[i][j] = C[i][j - 1] * (i - j + 1) / j; } for (int i = (1); i <= (n - 1); ++i) for (int j = (i + 1); j <= (n); ++j) { scanf( %d , &c[i][j]); c[j][i] = c[i][j]; } long double m = 0; for (int i = (1); i <= (n); ++i) { edge[i] = 0; for (int j = (1); j <= (n); ++j) if (c[i][j] >= 0 && i != j) edge[i]++; s[i] = 0; if (edge[i] < k) continue; s[i] = C[edge[i]][k]; m += s[i]; } long double ans = 0; for (int i = (1); i <= (n); ++i) { if (edge[i] <= 0) continue; long double p = (s[i] * k) / (m * edge[i]); long double sum = 0; for (int j = (1); j <= (n); ++j) if (c[i][j] >= 0 && i != j) sum += (long double)c[i][j]; ans += sum * p; } ans = ans + 1e-5; printf( %I64d n , (long long)ans); return 0; } |
#include <bits/stdc++.h> size_t solve(const std::vector<std::string>& c) { const size_t n = c.size(); size_t count = 0; for (size_t i = 0; i < n; ++i) { for (size_t j = 0; j < n; ++j) { for (size_t k = j + 1; k < n; ++k) { if (c[i][j] == C && c[i][k] == C ) ++count; if (c[j][i] == C && c[k][i] == C ) ++count; } } } return count; } int main() { size_t n; std::cin >> n; std::vector<std::string> c(n); for (size_t i = 0; i < n; ++i) std::cin >> c[i]; std::cout << solve(c) << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; namespace jyy { const int mod = 998244353, N = 600010; const double eps = 1e-8; inline int read() { static int x = 0, f = 1; x = 0, f = 1; static char ch = getchar(); while (ch < 0 || ch > 9 ) { (ch == - ) ? f *= -1 : f; ch = getchar(); } while (ch >= 0 && ch <= 9 ) x = x * 10 + int(ch - 48), ch = getchar(); return x * f; } inline void fw(int x) { if (x < 0) putchar( - ), x = -x; x >= 10 ? fw(x / 10), 1 : 0; putchar(char(x % 10 + 48)); } inline int qmo(int x) { return x + ((x >> 31) & mod); } inline int ksm(int x, int y) { int tmp = 1; for (; y; y >>= 1, x = 1ll * x * x % mod) if (y & 1) tmp = 1ll * tmp * x % mod; return tmp; } inline int inv(int x) { return ksm(x, mod - 2); } int tot, head[N], fa[N]; struct edge { int to, next; } dat[N * 2]; void add_edge(int x, int y) { dat[++tot] = (edge){y, head[x]}, head[x] = tot; } inline int find(int x) { return fa[x] ? fa[x] = find(fa[x]) : x; } inline int merge(int x, int y) { return find(x) != find(y) ? fa[find(x)] = find(y), 0 : 1; } inline int low(int x) { return x & -x; } int ifac[N], fac[N]; inline void init(int x) { fac[0] = ifac[0] = 1; for (int i = 1; i <= x; i++) fac[i] = 1ll * fac[i - 1] * i % mod; ifac[x] = inv(fac[x]); for (int i = x - 1; i >= 1; i--) ifac[i] = 1ll * ifac[i + 1] * (i + 1) % mod; } inline int C(int x, int y) { return (x < y || y < 0 || x < 0) ? 0 : 1ll * fac[x] * ifac[y] % mod * ifac[x - y] % mod; } } // namespace jyy using namespace jyy; int pd[N], n, R[N], a[N], vis[N], dep[N], m, b[N]; char c[N]; void dfs(int x, int f) { vis[x] = 1; dep[x] = dep[f] + 1; fa[x] = f; for (int i = head[x]; i; i = dat[i].next) { int t = dat[i].to; if (t == f || vis[t]) continue; dfs(t, x); } } void work(int x, int y) { deque<int> q1, q2; while (dep[x] > dep[y]) q1.push_back(x), x = fa[x]; while (dep[x] < dep[y]) q2.push_front(y), y = fa[y]; while (x != y) q1.push_back(x), q2.push_front(y), x = fa[x], y = fa[y]; q1.push_back(x); cout << q1.size() + q2.size() << endl; while (q1.size()) printf( %d , q1.front()), q1.pop_front(); while (q2.size()) printf( %d , q2.front()), q2.pop_front(); puts( ); } void solve() { n = read(), m = read(); for (int i = 1, x, y; i <= m; i++) x = read(), y = read(), add_edge(x, y), add_edge(y, x); dfs(1, 0); int q = read(); for (int i = 1; i <= q; i++) { a[i] = read(), b[i] = read(); pd[a[i]] ^= 1; pd[b[i]] ^= 1; } int cnt = 0; for (int i = 1; i <= n; i++) cnt += pd[i]; if (cnt) { puts( NO ); cout << cnt / 2 << endl; return; } puts( YES ); for (int i = 1; i <= q; i++) { work(a[i], b[i]); } } int main() { int T = 1; while (T--) solve(); } |
#include <bits/stdc++.h> using namespace std; int main() { int x, y, x1, y1, a, b, c, d, e; cin >> x >> y >> x1 >> y1; a = x1 - x; b = y1 - y; { if (a < 0) { c = (-1) * a; } else c = a; } { if (b < 0) { d = (-1) * b; } else d = b; } e = max(d, c); cout << e; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, q, a[210000], b[210000]; int tree[210000]; char Getchar() { static char now[1 << 20], *S, *T; if (T == S) { T = (S = now) + fread(now, 1, 1 << 20, stdin); if (T == S) return EOF; } return *S++; } int read() { int x = 0, f = 1; char ch = Getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = Getchar(); } while (ch <= 9 && ch >= 0 ) x = x * 10 + ch - 0 , ch = Getchar(); return x * f; } void update(int x, int y) { for (; x <= n; x += x & -x) tree[x] ^= y; } int getnum(int x) { int res = 0; for (; x; x -= x & -x) res ^= tree[x]; return res; } struct Linear_Basis { int cnt, v[30]; void clr() { cnt = 0; memset(v, 0, sizeof(v)); } void ins(int x, int lim = 29) { if (cnt == 30) return; for (int i = lim; i >= 0 && x; i--) if (x & (1 << i)) { if (v[i]) x ^= v[i]; else { v[i] = x; cnt++; break; } } } void merge(const Linear_Basis &a) { for (int i = 29; i >= 0; i--) if (a.v[i]) ins(a.v[i], i); } } tmp, t[810000]; void pushup(int now) { t[now] = t[now << 1]; t[now].merge(t[now << 1 | 1]); } void build(int now, int l, int r) { if (l == r) { t[now].clr(); t[now].ins(b[l]); return; } int mid = (l + r) >> 1; build(now << 1, l, mid); build(now << 1 | 1, mid + 1, r); pushup(now); } void change(int now, int l, int r, int x) { if (l == r) { t[now].clr(); t[now].ins(b[l]); return; } int mid = (l + r) >> 1; if (x <= mid) change(now << 1, l, mid, x); else change(now << 1 | 1, mid + 1, r, x); pushup(now); } void query(int now, int l, int r, int x, int y) { if (l == x && r == y) { tmp.merge(t[now]); return; } int mid = (l + r) >> 1; if (y <= mid) query(now << 1, l, mid, x, y); else if (x > mid) query(now << 1 | 1, mid + 1, r, x, y); else { query(now << 1, l, mid, x, mid); query(now << 1 | 1, mid + 1, r, mid + 1, y); } } int main() { n = read(); q = read(); for (int i = 1; i <= n; i++) { a[i] = read(); b[i] = a[i - 1] ^ a[i]; update(i, b[i]); } build(1, 1, n); int op, l, r, x; while (q--) { op = read(); l = read(); r = read(); if (op == 1) { x = read(); update(l, x); update(r + 1, x); b[l] ^= x; b[r + 1] ^= x; change(1, 1, n, l); if (r < n) change(1, 1, n, r + 1); } else { tmp.clr(); tmp.ins(getnum(l)); if (l < r) query(1, 1, n, l + 1, r); printf( %d n , 1 << tmp.cnt); } } return 0; } |
#include <bits/stdc++.h> using namespace std; void solve(long long int arr[], long long int n, long long int l) { for (int i = 1; i < n; i++) { arr[i] = min(arr[i], 2 * arr[i - 1]); } long long int exp[n]; for (int i = 0; i < n; i++) { exp[i] = 1LL << i; } long long int ans = LLONG_MAX; long long int val = 0; for (int i = n - 1; i >= 0; i--) { long long int currentAns = val + (l + exp[i] - 1) / exp[i] * arr[i]; ans = min(ans, currentAns); long long int x = l / exp[i]; l -= x * exp[i]; val += x * arr[i]; } cout << ans << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int t = 1; while (t--) { long long int n, l; cin >> n >> l; long long int arr[n]; for (int i = 0; i < n; i++) { cin >> arr[i]; } solve(arr, n, l); } } |
#include <bits/stdc++.h> using namespace std; string itos(int x) { stringstream ss; ss << x; return ss.str(); } int n, m, res, bestlone; map<string, vector<int> > m1; string str; int main() { ios_base::sync_with_stdio(false); cin >> n >> m; for (int i = 0, x; i < n; i++) { cin >> str >> x; string t = str; if (not m1.count(str)) m1[str] = vector<int>(); m1[str].push_back(x); } for (auto &x : m1) sort(x.second.begin(), x.second.end(), greater<int>()); for (auto x : m1) { string str = x.first; string t = str; reverse(t.begin(), t.end()); vector<int> &v = x.second; if (str > t) continue; else if (str == t) { for (int i = 0; i < v.size(); i += 2) { if (i + 1 < v.size()) { int x = v[i], y = v[i + 1]; if (x < 0) break; else if (y < 0) { if (x + y > 0) { bestlone = max(bestlone, -y); res += x + y; } else bestlone = max(bestlone, x); } else res += x + y; } else { int x = v[i]; if (x < 0) break; bestlone = max(bestlone, x); } } } else { vector<int> &v2 = m1[t]; for (int i = 0; i < v.size() && i < v2.size(); i++) { if (v[i] + v2[i] < 0) break; else res += v[i] + v2[i]; } } } res += bestlone; cout << res << endl; return 0; } |
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: player1.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module player1 (
address,
clock,
q);
input [10:0] address;
input clock;
output [2:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "player1.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1190"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
// Retrieval info: PRIVATE: WidthData NUMERIC "3"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "player1.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1190"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "3"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 3 0 OUTPUT NODEFVAL "q[2..0]"
// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 3 0 @q_a 0 0 3 0
// Retrieval info: GEN_FILE: TYPE_NORMAL player1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL player1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL player1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL player1.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL player1_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL player1_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPVGND_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__TAPVGND_FUNCTIONAL_PP_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection 1
* row down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__tapvgnd (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPVGND_FUNCTIONAL_PP_V |
// ============================================================================
// Copyright (c) 2010
// ============================================================================
//
// Permission:
//
//
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods.
// ============================================================================
//
// ReConfigurable Computing Group
//
// web: http://www.ecs.umass.edu/ece/tessier/rcg/
//
//
// ============================================================================
// Major Functions/Design Description:
//
//
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |RCG |05/10/2011 |
// ============================================================================
//include "NF_2.1_defines.v"
//include "registers.v"
//include "reg_defines_reference_router.v"
module generic_cntr_regs
#(
parameter UDP_REG_SRC_WIDTH = 2,
parameter TAG = 0, // Tag to match against
parameter REG_ADDR_WIDTH = 5, // Width of block addresses
parameter NUM_REGS_USED = 8, // How many registers
parameter REG_START_ADDR = 0, // Address of the first counter
parameter INPUT_WIDTH = 1, // Width of each update request
parameter MIN_UPDATE_INTERVAL = 8, // Clocks between successive inputs
parameter REG_WIDTH = `CPCI_NF2_DATA_WIDTH, // How wide should each counter be?
parameter RESET_ON_READ = 0,
// Don't modify the parameters below. They are used to calculate the
// widths of the various register inputs/outputs.
parameter REG_END_ADDR = REG_START_ADDR + NUM_REGS_USED, // address of last counter + 1
parameter UPDATES_START = REG_START_ADDR * INPUT_WIDTH, // first bit of the updates vector
parameter UPDATES_END = REG_END_ADDR * INPUT_WIDTH // bit after last bit of the updates vector
)
(
input reg_req_in,
input reg_ack_in,
input reg_rd_wr_L_in,
input [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in,
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in,
input [UDP_REG_SRC_WIDTH-1:0] reg_src_in,
output reg reg_req_out,
output reg reg_ack_out,
output reg reg_rd_wr_L_out,
output reg [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_out,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_out,
output reg [UDP_REG_SRC_WIDTH-1:0] reg_src_out,
// --- update interface
input [UPDATES_END - 1:UPDATES_START] updates,
input [REG_END_ADDR-1:REG_START_ADDR] decrement, // if 1 then subtract the update, else add.
input clk,
input reset
);
`LOG2_FUNC
`CEILDIV_FUNC
// ------------- Internal parameters --------------
localparam MIN_CYCLE_TIME = NUM_REGS_USED + 1;
// Calculate the number of updates we can see in a single cycle through the
// RAM.
//
// This should be:
// ceil(MIN_CYCLE_TIME / MIN_UPDATE_INTERVAL)
localparam UPDATES_PER_CYCLE = ceildiv(MIN_CYCLE_TIME, MIN_UPDATE_INTERVAL);
localparam LOG_UPDATES_PER_CYCLE = log2(UPDATES_PER_CYCLE);
// Calculate how much storage to allocate for each delta
//
// A single update requires INPUT_WIDTH bits of storage
// In the worst case we would add the updates and get a total of
// (2^INPUT_WIDTH - 1) * UPDATES_PER_CYCLE
// This can be represented in:
// log2( (2^INPUT_WIDTH - 1) * UPDATES_PER_CYCLE )
// = INPUT_WIDTH + log2(UPDATES_PER_CYCLE)
// we add one for sign extension.
localparam DELTA_WIDTH = INPUT_WIDTH + LOG_UPDATES_PER_CYCLE + 1;
localparam RESET = 0,
NORMAL = 1;
// ------------- Wires/reg ------------------
reg [REG_WIDTH-1:0] reg_file [REG_START_ADDR:REG_END_ADDR-1];
wire [REG_ADDR_WIDTH-1:0] addr, addr_d1;
wire [`UDP_REG_ADDR_WIDTH-REG_ADDR_WIDTH-1:0] tag_addr;
reg [REG_ADDR_WIDTH-1:0] reg_cnt;
wire [REG_ADDR_WIDTH-1:0] reg_cnt_nxt;
wire [REG_ADDR_WIDTH-1:0] reg_file_rd_addr;
reg [REG_ADDR_WIDTH-1:0] reg_file_rd_addr_ram;
wire [REG_ADDR_WIDTH-1:0] reg_file_wr_addr;
reg [DELTA_WIDTH-1:0] deltas[REG_START_ADDR:REG_END_ADDR-1];
wire [DELTA_WIDTH-1:0] delta;
wire [DELTA_WIDTH-1:0] update[REG_START_ADDR:REG_END_ADDR-1];
wire [REG_WIDTH-1:0] reg_file_out;
reg [REG_WIDTH-1:0] reg_file_in;
reg reg_file_wr_en;
reg [REG_ADDR_WIDTH-1:0] reg_cnt_d1;
reg reg_rd_req_good_d1, reg_wr_req_good_d1;
reg [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in_d1;
reg [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in_d1;
reg reg_req_in_d1;
reg reg_ack_in_d1;
reg reg_rd_wr_L_in_d1;
reg [UDP_REG_SRC_WIDTH-1:0] reg_src_in_d1;
integer i;
reg state;
// -------------- Logic --------------------
assign addr = reg_addr_in[REG_ADDR_WIDTH-1:0];
assign addr_d1 = reg_addr_in_d1[REG_ADDR_WIDTH-1:0];
assign tag_addr = reg_addr_in[`UDP_REG_ADDR_WIDTH - 1:REG_ADDR_WIDTH];
assign addr_good = addr < REG_END_ADDR && addr >= REG_START_ADDR;
assign tag_hit = tag_addr == TAG;
assign reg_rd_req_good = (tag_hit && addr_good && reg_req_in && reg_rd_wr_L_in);
assign reg_wr_req_good = (tag_hit && addr_good && reg_req_in && ~reg_rd_wr_L_in);
assign reg_cnt_nxt = (reg_cnt==REG_END_ADDR-1'b1) ? REG_START_ADDR : reg_cnt + 1'b1;
assign delta = deltas[reg_cnt_d1];
assign reg_file_rd_addr = reg_rd_req_good ? addr : reg_cnt;
assign reg_file_wr_addr = (state == RESET
? reg_cnt
: (reg_wr_req_good_d1 || reg_rd_req_good_d1)
? addr_d1 : reg_cnt_d1);
// choose when and what to write in the ram
always @(*) begin
reg_file_in = reg_file_out + {{(REG_WIDTH - DELTA_WIDTH){delta[DELTA_WIDTH-1]}}, delta};
reg_file_wr_en = 0;
if(state == RESET || (reg_rd_req_good_d1 && RESET_ON_READ)) begin
reg_file_wr_en = 1;
reg_file_in = 0;
end
else if(!reg_wr_req_good_d1 && !reg_rd_req_good_d1) begin
reg_file_wr_en = 1;
end
else if(reg_wr_req_good_d1) begin
reg_file_in = reg_data_in_d1;
reg_file_wr_en = 1;
end
end // always @ (*)
// Generate the individual update lines from the updates vector
//
// Note: I have the ugly bit selection because ModelSim doesn't seem to
// like parameters used in :+ selects! :-(
generate
genvar j;
for (j = REG_START_ADDR; j < REG_END_ADDR; j = j + 1) begin : update_gen
assign update[j] = {{(DELTA_WIDTH - INPUT_WIDTH){1'b0}}, updates[(j + 1) * INPUT_WIDTH - 1 : j * INPUT_WIDTH]};
end
endgenerate
/*********** RAM *************/
always @(posedge clk) begin
// write to the register file
if(reg_file_wr_en) begin
reg_file[reg_file_wr_addr] <= reg_file_in;
end
reg_file_rd_addr_ram <= reg_file_rd_addr;
end
assign reg_file_out = reg_file[reg_file_rd_addr_ram];
/****************************/
// State machine that handles register access from the CPU
always @(posedge clk) begin
if(reset) begin
reg_cnt <= REG_START_ADDR;
reg_rd_req_good_d1 <= 0;
reg_wr_req_good_d1 <= 0;
reg_req_in_d1 <= 0;
reg_ack_out <= 0;
reg_req_out <= 0;
state <= RESET;
for (i = REG_START_ADDR; i < REG_END_ADDR; i = i + 1) begin
deltas[i] <= 0;
end
end // if (reset)
else begin
reg_cnt_d1 <= reg_cnt;
if(state == RESET) begin
reg_cnt <= reg_cnt_nxt;
if(reg_cnt == REG_END_ADDR-1'b1) begin
state <= NORMAL;
end
end
else begin
/*********************************************************************
* first stage - read bram, latch reg req signals
*/
reg_cnt <= (reg_rd_req_good || reg_wr_req_good) ? reg_cnt : reg_cnt_nxt;
reg_rd_req_good_d1 <= reg_rd_req_good;
reg_wr_req_good_d1 <= reg_wr_req_good;
reg_addr_in_d1 <= reg_addr_in;
reg_data_in_d1 <= reg_data_in;
reg_req_in_d1 <= reg_req_in;
reg_ack_in_d1 <= reg_ack_in;
reg_rd_wr_L_in_d1 <= reg_rd_wr_L_in;
reg_src_in_d1 <= reg_src_in;
// synthesis translate_off
if(reg_ack_in && (reg_rd_req_good || reg_wr_req_good)) begin
$display("%t %m ERROR: Register request already ack even though", $time);
$display("it should be destined to this module. This can happen");
$display("if two modules have aliased register addresses.");
$stop;
end
// synthesis translate_on
/********************************************************************
* second stage - output rd req or do write req or delta update
*/
reg_ack_out <= reg_rd_req_good_d1 || reg_wr_req_good_d1 || reg_ack_in_d1;
reg_data_out <= reg_rd_req_good_d1 ? reg_file_out : reg_data_in_d1;
reg_addr_out <= reg_addr_in_d1;
reg_req_out <= reg_req_in_d1;
reg_rd_wr_L_out <= reg_rd_wr_L_in_d1;
reg_src_out <= reg_src_in_d1;
/*******************************************************************
* update the deltas
*/
for (i = REG_START_ADDR; i < REG_END_ADDR; i = i + 1) begin
// if we just update the register corresponding to this delta then
// clear it.
if ((i==reg_cnt_d1) // this delta was committed to reg_file
&& !reg_wr_req_good_d1 // we didn't write in this cycle
&& !(reg_rd_req_good_d1 && RESET_ON_READ) // we didn't read and reset
) begin
deltas[i] <= decrement[i] ? -update[i] : update[i];
end
else begin
deltas[i] <= decrement[i] ? deltas[i] - update[i] : deltas[i] + update[i];
end
end // for (i = REG_START_ADDR; i < REG_END_ADDR; i = i + 1)
end // else: !if(state == RESET)
end // else: !if(reset)
end // always @ (posedge clk)
endmodule
|
/*
* Copyright 2010, Aleksander Osman, . All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are
* permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module timer(
input CLK_I,
input RST_I,
input [31:2] ADR_I,
input CYC_I,
input STB_I,
input WE_I,
output reg RTY_O,
output reg interrupt_o
);
reg [27:0] counter;
always @(posedge CLK_I) begin
if(RST_I == 1'b1) begin
RTY_O <= 1'b0;
interrupt_o <= 1'b0;
counter <= 28'd0;
end
else if(counter == 28'h00FFFFF) begin
if(ADR_I == { 27'b1111_1111_1111_1111_1111_1111_111, 3'b001 } && CYC_I == 1'b1 && STB_I == 1'b1 && WE_I == 1'b0 && interrupt_o == 1'b1) begin
RTY_O <= 1'b1;
interrupt_o <= 1'b0;
counter <= 28'd0;
end
else begin
interrupt_o <= 1'b1;
end
end
else begin
RTY_O <= 1'b0;
counter <= counter + 28'd1;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21AI_1_V
`define SKY130_FD_SC_HS__O21AI_1_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog wrapper for o21ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o21ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o21ai_1 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o21ai_1 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21AI_1_V
|
#include <bits/stdc++.h> using namespace std; string s; string p; int a[2005]; int A[2005]; int ans[2005]; int dp[2005][2005]; int main() { cin >> s >> p; memset(a, -1, sizeof(a)); a[0] = 0; for (int i = 0; i < s.size(); i++) { for (int j = p.size() - 1; j >= 0; j--) { if (s[i] == p[j]) a[j + 1] = a[j]; } a[0] = i + 1; A[i + 1] = a[p.size()]; } for (int i = 1; i <= s.size(); i++) { for (int j = 0; j <= i; j++) { dp[i][j] = dp[i - 1][j]; if (A[i] >= 0 && j - (i - A[i] - p.size()) >= 0 && j - (i - A[i] - p.size()) <= A[i]) dp[i][j] = max(dp[A[i]][j - (i - A[i] - p.size())] + 1, dp[i][j]); } } for (int i = 0; i <= s.size(); i++) ans[i] = dp[s.size()][i]; for (int i = 0; i <= s.size(); i++) cout << ans[i] << ; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DIODE_FUNCTIONAL_V
`define SKY130_FD_SC_LS__DIODE_FUNCTIONAL_V
/**
* diode: Antenna tie-down diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__diode (
DIODE
);
// Module ports
input DIODE;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DIODE_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; std::ostream& operator<<(std::ostream& os, pair<int, int> p) { os << p.first << , << p.second; return os; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { long long int l, r; cin >> l >> r; if (l * 2 > r) { cout << -1 << << -1 << n ; continue; } else { cout << l << << 2 * l << n ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; void sol(); int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, k; cin >> n >> k; long long ml = 1, ans = 0; vector<int> ls(n); map<long long, int> pre, mp; mp[0] = 1; vector<long long> an; while (ml < 1e15) { if (!pre[ml]) an.push_back(ml), pre[ml] = 1; else break; ml *= k; if ((ml > 1e15 || -ml > 1e15) || (ml % k != 0)) break; } for (int &x : ls) cin >> x; long long sm = 0ll; for (int x : ls) { sm += x; for (long long y : an) if (mp[sm - y]) ans += mp[sm - y]; mp[sm]++; } cout << ans; } |
#include<bits/stdc++.h> #define pb push_back #define x first #define y second #define all(a) (a).begin(), (a).end() using namespace std; typedef long long ll; typedef pair<int, int> ii; const int maxn = 3e5 + 5; int n, m, X; ll A[maxn]; int par[maxn]; set<pair<ll, ii>> adj[maxn]; map<ii, int> pos; set<pair<ll, int>> s; int exists = 1; int find(int x) {return (x == par[x]) ? x : par[x] = find(par[x]);} int merge(int x, int y) { x = find(x), y = find(y); if(x == y) return 0; if(adj[x].size() < adj[y].size()) swap(x, y); par[y] = x; s.erase({A[y], y}); s.erase({A[x], x}); A[x] += A[y]; A[x] -= X; s.insert({A[x], x}); if(A[x] < 0) exists = 0; for(auto p : adj[y]) adj[x].insert(p); return 1; } int main() { scanf( %d %d %d , &n, &m, &X); for(int i = 0;i < n;i++) scanf( %lld , A + i); for(int i = 0;i < n;i++) par[i] = i; for(int i = 0;i < m;i++) { int x, y; scanf( %d %d , &x, &y); x--, y--; if(x > y) swap(x, y); pos[{x, y}] = i + 1; adj[x].insert({A[y], {x, y}}); adj[y].insert({A[x], {x, y}}); } vector<int> ans; for(int i = 0;i < n;i++) s.insert({A[i], i}); for(int i = 0;i < n - 1;i++) { auto it1 = s.end();it1--; auto p1 = *it1; while(1) { auto it2 = adj[p1.y].end();it2--; auto p2 = *it2; int flag = merge(p2.y.x, p2.y.y); if(flag) { ans.pb(pos[{p2.y.x, p2.y.y}]); break; } adj[p1.y].erase(it2); } if(!exists) {printf( NO n );return 0;} } printf( YES n ); for(int i : ans) printf( %d n , i); return 0; } |
#include <bits/stdc++.h> using namespace std; void solve(const vector<int>& pearl) { vector<pair<int, int>> ans; ans.reserve(pearl.size()); set<int> app; int l = 0; for (int i = 0; i < pearl.size(); i++) { int cur = pearl[i]; if (app.find(cur) != end(app)) { ans.push_back(make_pair(l + 1, i + 1)); l = i + 1; set<int>().swap(app); } else app.insert(cur); } if (l != pearl.size()) { if (l == 0) { printf( -1 n ); return; } ans[ans.size() - 1].second = pearl.size(); } printf( %d n , ans.size()); for (const auto& a : ans) printf( %d %d n , a.first, a.second); } int main() { int n; scanf( %d , &n); vector<int> pearl(n); for (int i = 0; i < n; i++) scanf( %d , &pearl[i]); solve(pearl); } |
/* lab2_part3.v - 4-bit to decimal (0..15)
*
* Copyright (c) 2014, Artem Tovbin <arty99 at gmail dot com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module lab2_part3 (SW, LEDG, LEDR);
input [17:0] SW;
output [8:0] LEDR, LEDG;
assign LEDR[8:0] = SW[8:0];
wire c1, c2, c3;
fulladder A0 (SW[0], SW[4], SW[8], LEDG[0], c1);
fulladder A1 (SW[1], SW[5], c1, LEDG[1], c2);
fulladder A2 (SW[2], SW[6], c2, LEDG[2], c3);
fulladder A3 (SW[3], SW[7], c3, LEDG[3], LEDG[4]);
endmodule
module fulladder (a, b, ci, s, co);
input a, b, ci;
output co, s;
wire d;
assign d = a ^ b;
assign s = d ^ ci;
assign co = (b & ~d) | (d & ci);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int k; cin >> k; string str, s; cin >> str; s = str; for (long long int i = 1; i < k; i++) str = str + s; map<char, vector<long long int>> pos; long long int i = 0; for (auto c : str) { pos[c].push_back(i); i++; } long long int n; cin >> n; char c; long long int p; while (n--) { cin >> p >> c; str[pos[c][p - 1]] = 0; pos[c].erase(pos[c].begin() + (p - 1)); } for (auto c : str) if (c) cout << c; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); int tt; cin >> tt; while (tt--) { int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; ++i) { cin >> a[i]; } int ans = 0; sort(a.begin(), a.end()); for (int i = 0, j = 0; j < n; j++) { if (j - i + 1 >= a[j]) { ++ans; i = j + 1; } } cout << ans << n ; } return 0; } |
/////////////////////////////////////////////////////////////////////
//// ////
//// Discrete Cosine Transform, DCT unit block ////
//// ////
//// Author: Richard Herveille ////
//// ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: dctub.v,v 1.3 2002/10/31 12:50:03 rherveille Exp $
//
// $Date: 2002/10/31 12:50:03 $
// $Revision: 1.3 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: dctub.v,v $
// Revision 1.3 2002/10/31 12:50:03 rherveille
// *** empty log message ***
//
// Revision 1.2 2002/10/23 09:06:59 rherveille
// Improved many files.
// Fixed some bugs in Run-Length-Encoder.
// Removed dependency on ud_cnt and ro_cnt.
// Started (Motion)JPEG hardware encoder project.
//
//synopsys translate_off
//`include "timescale.v"
//synopsys translate_on
module dctub(clk, ena, ddgo, x, y, ddin,
dout0, dout1, dout2, dout3, dout4, dout5, dout6, dout7);
parameter coef_width = 16;
parameter di_width = 8;
parameter [2:0] v = 3'h0;
//
// inputs & outputs
//
input clk;
input ena;
input ddgo; // double delayed go strobe
input [2:0] x, y;
input [di_width:1] ddin; // delayed data input
output [11:0] dout0, dout1, dout2, dout3, dout4, dout5, dout6, dout7;
//
// module body
//
// Hookup DCT units
dctu #(coef_width, di_width, v, 3'h0)
dct_unit_0 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(x),
.y(y),
.ddin(ddin),
.dout(dout0)
);
dctu #(coef_width, di_width, v, 3'h1)
dct_unit_1 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(x),
.y(y),
.ddin(ddin),
.dout(dout1)
);
dctu #(coef_width, di_width, v, 3'h2)
dct_unit_2 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(x),
.y(y),
.ddin(ddin),
.dout(dout2)
);
dctu #(coef_width, di_width, v, 3'h3)
dct_unit_3 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(x),
.y(y),
.ddin(ddin),
.dout(dout3)
);
dctu #(coef_width, di_width, v, 3'h4)
dct_unit_4 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(x),
.y(y),
.ddin(ddin),
.dout(dout4)
);
dctu #(coef_width, di_width, v, 3'h5)
dct_unit_5 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(x),
.y(y),
.ddin(ddin),
.dout(dout5)
);
dctu #(coef_width, di_width, v, 3'h6)
dct_unit_6 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(x),
.y(y),
.ddin(ddin),
.dout(dout6)
);
dctu #(coef_width, di_width, v, 3'h7)
dct_unit_7 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(x),
.y(y),
.ddin(ddin),
.dout(dout7)
);
endmodule
|
// patterngenerator.v
`timescale 1ns / 1ps
module patterngenerator
(
// avalon clock interface
input csi_clock_clk,
input csi_clock_reset,
// avalon mm slave: status/control
input avs_ctrl_address,
input avs_ctrl_read,
output [31:0]avs_ctrl_readdata,
input avs_ctrl_write,
input [31:0]avs_ctrl_writedata,
// avalon mm slave: command memory
input [7:0]avs_data_address,
input avs_data_write,
input [1:0]avs_data_byteenable,
input [15:0]avs_data_writedata,
// pattern generator interface
input clkena,
input trigger,
output [4:0]pgout
);
/* avalon 16 bit register file
0 w control register
0 r status register
1 w period register
control register:
bit 7: enable pattern generator
bit 2: enable loop
bit 1: enable external trigger
bit 0: start single sequence
*/
// control regisdter bits
reg ctrl_ena;
reg ctrl_ext;
reg ctrl_loop;
reg ctrl_start;
wire start;
wire enable;
wire ena_loop;
wire ena_ext;
wire set_start;
wire running;
reg [15:0]period;
reg [15:0]loopcnt;
wire [7:0]seq_address;
wire [15:0]seq_command;
// --- control register programming ---------------------------------------
always @(posedge csi_clock_clk or posedge csi_clock_reset)
begin
if (csi_clock_reset)
begin
{ ctrl_ena, ctrl_loop, ctrl_ext, ctrl_start } <= 4'b0000;
period <= 0;
end
else if (avs_ctrl_write)
begin
case (avs_ctrl_address)
0: { ctrl_ena, ctrl_loop, ctrl_ext, ctrl_start }
<= { avs_ctrl_writedata[7], avs_ctrl_writedata[2:0] };
1: period <= avs_ctrl_writedata[15:0];
endcase
end
else if (clkena) ctrl_start <= 0;
end
assign avs_ctrl_readdata =
avs_ctrl_address ? { 16'd0, period } : { 31'd0, running };
assign enable = ctrl_ena;
assign ena_ext = ctrl_ext;
assign ena_loop = ctrl_loop;
assign set_start = ctrl_start;
// --- trigger generator --------------------------------------------------
wire trig_loop = loopcnt == 0;
always @(posedge csi_clock_clk or posedge csi_clock_reset)
begin
if (csi_clock_reset) loopcnt <= 0;
else if (clkena)
begin
if (ena_loop)
begin
if (trig_loop) loopcnt <= period; else loopcnt <= loopcnt - 1;
end
else loopcnt <= 0;
end
end
assign start = set_start || (ena_loop && trig_loop) || (ena_ext && trigger);
pg_ram ram
(
// avalon port
.clock (csi_clock_clk),
.wren (avs_data_write),
.wraddress (avs_data_address),
.byteena_a (avs_data_byteenable),
.data (avs_data_writedata),
// pattern generator port
.rdaddress (seq_address),
.q (seq_command)
);
pg_sequencer pg
(
.clk(csi_clock_clk),
.sync(clkena),
.reset(csi_clock_reset),
.enable(enable),
.start(start),
.running(running),
.pgout(pgout),
.ip(seq_address),
.cmd(seq_command)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int n = 5000; const long long mod = 998244353; long long f[n + 10][n + 10]; int main() { int a, b, c; for (int i = 1; i < n + 10; i++) { for (int j = 1; j < n + 10; j++) { if (i == 1) f[i][j] = j + 1; else if (j < i) f[i][j] = f[j][i]; else { (f[i][j] += j * f[i - 1][j - 1] % mod) %= mod; (f[i][j] += f[i - 1][j]) %= mod; } } } while (scanf( %d%d%d , &a, &b, &c) != EOF) { long long ans = ((f[a][b] * f[b][c]) % mod) * f[c][a] % mod; printf( %lld n , ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); string s; cin >> s; long long l = s.length(); vector<char> s1; long long pos = -1; for (long long i = 0; i < l; i++) { if (s[i] == a ) pos = i; else s1.push_back(s[i]); } long long l2 = s1.size(); long long ri = l - 1 - pos; long long le = l2 - ri; if (l2 % 2 != 0 || le > ri) cout << :( ; else { long long j = l2 / 2; bool flag = true; for (long long i = 0; i < j; i++) { if (s1[i] != s1[i + j]) { flag = false; break; } } if (!flag) cout << :( ; else { for (long long i = 0; i < l - j; i++) cout << s[i]; } } } |
///////////////////////////////////////////////////////////////////////////////
//
// Project: Aurora Module Generator version 2.2
//
// Date: $Date: 2004/11/08 16:19:25 $
// Tag: $Name: i+H-38+78751 $
// File: $RCSfile: channel_init_sm.ejava,v $
// Rev: $Revision: 1.1.6.2 $
//
// Company: Xilinx
// Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
//
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
// APPLICATION OR STANDARD, XILINX IS MAKING NO
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE.
//
// (c) Copyright 2004 Xilinx, Inc.
// All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////
//
// CHANNEL_INIT_SM
//
// Author: Nigel Gulstone
// Xilinx - Embedded Networking System Engineering Group
//
// Description: the CHANNEL_INIT_SM module is a state machine for managing channel
// bonding and verification.
//
// The channel init state machine is reset until the lane up signals
// of all the lanes that constitute the channel are asserted. It then
// requests channel bonding until the lanes have been bonded and
// checks to make sure the bonding was successful. Channel bonding is
// skipped if there is only one lane in the channel. If bonding is
// unsuccessful, the lanes are reset.
//
// After the bonding phase is complete, the state machine sends
// verification sequences through the channel until it is clear that
// the channel is ready to be used. If verification is successful,
// the CHANNEL_UP signal is asserted. If it is unsuccessful, the
// lanes are reset.
//
// After CHANNEL_UP goes high, the state machine is quiescent, and will
// reset only if one of the lanes goes down, a hard error is detected, or
// a general reset is requested.
//
// This module supports 1 4-byte lane designs
//
`timescale 1 ns / 10 ps
module CHANNEL_INIT_SM
(
// MGT Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
// Aurora Lane Interface
CHANNEL_BOND_LOAD,
GOT_A,
GOT_V,
RESET_LANES,
// System Interface
USER_CLK,
RESET,
CHANNEL_UP,
START_RX,
// Idle and Verification Sequence Generator Interface
DID_VER,
GEN_VER,
// Channel Error Management Interface
RESET_CHANNEL
);
`define DLY #1
//***********************************Port Declarations*******************************
// MGT Interface
input CH_BOND_DONE;
output EN_CHAN_SYNC;
// Aurora Lane Interface
input CHANNEL_BOND_LOAD;
input [0:3] GOT_A;
input GOT_V;
output RESET_LANES;
// System Interface
input USER_CLK;
input RESET;
output CHANNEL_UP;
output START_RX;
// Idle and Verification Sequence Generator Interface
input DID_VER;
output GEN_VER;
// Channel Init State Machine Interface
input RESET_CHANNEL;
//***************************External Register Declarations***************************
reg START_RX;
//***************************Internal Register Declarations***************************
reg free_count_done_r;
reg [0:15] verify_watchdog_r;
reg all_lanes_v_r;
reg got_first_v_r;
reg [0:15] v_count_r;
reg bad_v_r;
reg [0:2] rxver_count_r;
reg [0:7] txver_count_r;
// State registers
reg wait_for_lane_up_r;
reg verify_r;
reg ready_r;
//*********************************Wire Declarations**********************************
wire free_count_1_r;
wire free_count_2_r;
wire insert_ver_c;
wire verify_watchdog_done_r;
wire rxver_3d_done_r;
wire txver_8d_done_r;
wire reset_lanes_c;
// Next state signals
wire next_verify_c;
wire next_ready_c;
//*********************************Main Body of Code**********************************
//________________Main state machine for bonding and verification________________
// State registers
always @(posedge USER_CLK)
if(RESET|RESET_CHANNEL)
begin
wait_for_lane_up_r <= `DLY 1'b1;
verify_r <= `DLY 1'b0;
ready_r <= `DLY 1'b0;
end
else
begin
wait_for_lane_up_r <= `DLY 1'b0;
verify_r <= `DLY next_verify_c;
ready_r <= `DLY next_ready_c;
end
// Next state logic
assign next_verify_c = wait_for_lane_up_r |
(verify_r & (!rxver_3d_done_r|!txver_8d_done_r));
assign next_ready_c = (verify_r & txver_8d_done_r & rxver_3d_done_r)|
ready_r;
// Output Logic
// Channel up is high as long as the Global Logic is in the ready state.
assign CHANNEL_UP = ready_r;
// Turn the receive engine on as soon as all the lanes are up.
always @(posedge USER_CLK)
if(RESET) START_RX <= `DLY 1'b0;
else START_RX <= `DLY !wait_for_lane_up_r;
// Generate the Verification sequence when in the verify state.
assign GEN_VER = verify_r;
//__________________________Channel Reset _________________________________
// Some problems during channel bonding and verification require the lanes to
// be reset. When this happens, we assert the Reset Lanes signal, which gets
// sent to all Aurora Lanes. When the Aurora Lanes reset, their LANE_UP signals
// go down. This causes the Channel Error Detector to assert the Reset Channel
// signal.
assign reset_lanes_c = (verify_r & verify_watchdog_done_r)|
(verify_r & bad_v_r & !rxver_3d_done_r)|
(RESET_CHANNEL & !wait_for_lane_up_r)|
RESET;
// synthesis translate_off
defparam reset_lanes_flop_i.INIT = 1'b1;
// synthesis translate_on
FD reset_lanes_flop_i
(
.D(reset_lanes_c),
.C(USER_CLK),
.Q(RESET_LANES)
);
//___________________________Watchdog timers____________________________________
// We create a free counter out of SRLs to count large values without excessive cost.
// synthesis translate_off
defparam free_count_1_i.INIT = 16'h8000;
// synthesis translate_on
SRL16 free_count_1_i
(
.Q(free_count_1_r),
.A0(1'b1),
.A1(1'b1),
.A2(1'b1),
.A3(1'b1),
.CLK(USER_CLK),
.D(free_count_1_r)
);
// synthesis translate_off
defparam free_count_2_i.INIT = 16'h8000;
// synthesis translate_on
SRL16E free_count_2_i
(
.Q(free_count_2_r),
.A0(1'b1),
.A1(1'b1),
.A2(1'b1),
.A3(1'b1),
.CLK(USER_CLK),
.CE(free_count_1_r),
.D(free_count_2_r)
);
// Finally we have logic that registers a pulse when both the inner and the
// outer SRLs have a bit in their last position. This should map to carry logic
// and a register.
always @(posedge USER_CLK)
free_count_done_r <= `DLY free_count_2_r & free_count_1_r;
// We use the freerunning count as a CE for the verify watchdog. The
// count runs continuously so the watchdog will vary between a count of 4096
// and 3840 cycles - acceptable for this application.
always @(posedge USER_CLK)
if(free_count_done_r | !verify_r)
verify_watchdog_r <= `DLY {verify_r,verify_watchdog_r[0:14]};
assign verify_watchdog_done_r = verify_watchdog_r[15];
//_____________________________Channel Bonding_______________________________
// We don't use channel bonding for the single lane case, so we tie the
// EN_CHAN_SYNC signal low.
assign EN_CHAN_SYNC = 1'b0;
//________________________________Verification__________________________
// Vs need to appear on all lanes simultaneously.
always @(posedge USER_CLK)
all_lanes_v_r <= `DLY GOT_V;
// Vs need to be decoded by the aurora lane and then checked by the
// Global logic. They must appear periodically.
always @(posedge USER_CLK)
if(!verify_r) got_first_v_r <= `DLY 1'b0;
else if(all_lanes_v_r) got_first_v_r <= `DLY 1'b1;
assign insert_ver_c = all_lanes_v_r & !got_first_v_r | (v_count_r[15] & verify_r);
// Shift register for measuring the time between V counts.
always @(posedge USER_CLK)
v_count_r <= `DLY {insert_ver_c,v_count_r[0:14]};
// Assert bad_v_r if a V does not arrive when expected.
always @(posedge USER_CLK)
bad_v_r <= `DLY (v_count_r[15] ^ all_lanes_v_r) & got_first_v_r;
// Count the number of Ver sequences received. You're done after you receive four.
always @(posedge USER_CLK)
if((v_count_r[15] & all_lanes_v_r) |!verify_r)
rxver_count_r <= `DLY {verify_r,rxver_count_r[0:1]};
assign rxver_3d_done_r = rxver_count_r[2];
// Count the number of Ver sequences transmitted. You're done after you send eight.
always @(posedge USER_CLK)
if(DID_VER |!verify_r)
txver_count_r <= `DLY {verify_r,txver_count_r[0:6]};
assign txver_8d_done_r = txver_count_r[7];
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the ALU
// Import the modules that will be tested for in this testbench
`include "arrmul.v"
`include "control.h"
// IMPORTANT: To run this, try: ncverilog -f alu.f +gui
module tb_arrmul();
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the ALU
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// result output signal
wire [0:127] res;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// reg_A
reg [0:127] r_A;
// reg_B
reg [0:127] r_B;
// Control signal bits - ww; ctrl_ww
reg [0:1] c_ww;
/**
* Control signal bits - determine which arithmetic or logic
* operation to perform; alu_op
*/
reg [0:4] a_op;
// Bus/Signal to contain the expected output/result
reg [0:127] e_r;
// ============================================================
// Defining constants: parameter [name_of_constant] = value;
//parameter size_of_input = 6'd32;
// ============================================================
/**
* Instantiate an instance of alu() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "rg"
*/
arrmul am (
// instance_name(signal name),
// Signal name can be the same as the instance name
// alu (reg_A,reg_B,ctrl_ppp,ctrl_ww,alu_op,result)
r_A,r_B,c_ww,a_op,res);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
// aluwmuleu AND w8
r_A=128'h0402030405060708f00a0b0cff0eff00;
r_B=128'h03010202030303031004f505ff09fe10;
e_r=128'h000c0006000f00150f000a87fe01fd02;
c_ww=`w8;
a_op=`aluwmuleu;
#10
// aluwmuleu AND w8
r_A=128'hff02030405060708f00a0b0cff0eff00;
r_B=128'hfe010202030303031004f505ff09fe10;
e_r=128'hfd020006000f00150f000a87fe01fd02;
c_ww=`w8;
a_op=`aluwmuleu;
#10
// aluwmuleu AND w8
r_A=128'hf502030405060708f00a0b0cff0eff00;
r_B=128'h0b010202030303031004f505ff09fe10;
e_r=128'h0a870006000f00150f000a87fe01fd02;
c_ww=`w8;
a_op=`aluwmuleu;
#10
// aluwmuleu AND w8
r_A=128'h1002030405060708f00a0b0cff0eff00;
r_B=128'hf0010202030303031004f505ff09fe10;
e_r=128'h0f000006000f00150f000a87fe01fd02;
c_ww=`w8;
a_op=`aluwmuleu;
#10
// aluwmuleu AND w8
r_A=128'h0402030405060708f00a0b0cff0eff00;
r_B=128'h00010202030303031004f505ff09fe10;
e_r=128'h00000006000f00150f000a87fe01fd02;
c_ww=`w8;
a_op=`aluwmuleu;
#10
// aluwmuleu AND w16
r_A=128'h000100020000ffff000f10bff103ffff;
r_B=128'h000200040006ffff000c100000120014;
e_r=128'h0000000200000000000000b40010f236;
c_ww=`w16;
a_op=`aluwmuleu;
// ======================================
#10
// aluwmulou AND w8
r_A=128'h0102030405060708090aff0c0dff0fff;
r_B=128'h01010202030303031004040508000fff;
e_r=128'h00020008001200180028003c0000fe01;
c_ww=`w8;
a_op=`aluwmulou;
#10
// aluwmulou AND w16
r_A=128'h0001000200000008000f10bff103ffff;
r_B=128'h0002000400060008000c001000120014;
e_r=128'h000000080000004000010bf00013ffec;
c_ww=`w16;
a_op=`aluwmulou;
// ======================================
#10
// aluwmulos AND w8
/*
r_A=128'h010330405060708090aff0c0dff0ff02;
r_B=128'h01fa0202030303031004040508000f08;
*/
r_A=128'h0180010501f9015301040100013c0100;
r_B=128'h017f010901fa010001fd01f101b80100;
e_r=128'hc080002d002a0000fff40000ef200000;
c_ww=`w8;
a_op=`aluwmulos;
#10
// aluwmulos AND w16
r_A=128'h1111000211118000111120541111fff9;
r_B=128'hffff0004ffff7fffffff0000fffffffd;
e_r=128'h00000008c00080000000000000000015;
c_ww=`w16;
a_op=`aluwmulos;
// ======================================
#10
// aluwmules AND w8
/*
r_A=128'h0180010501f9015301040100013c0100;
r_B=128'h017f010901fa010001fd01f101b80100;
*/
r_A=128'h80010501f9015301040100013c010001;
r_B=128'h7f010901fa010001fd01f101b8010001;
e_r=128'hc080002d002a0000fff40000ef200000;
c_ww=`w8;
a_op=`aluwmules;
#10
// aluwmules AND w16
/*
r_A=128'h1111000211118000111120541111fff9;
r_B=128'hffff0004ffff7fffffff0000fffffffd;
*/
r_A=128'h000211118000111120541111fff91111;
r_B=128'h0004ffff7fffffff0000fffffffdffff;
e_r=128'h00000008c00080000000000000000015;
c_ww=`w16;
a_op=`aluwmules;
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPVPWRVGND_PP_SYMBOL_V
`define SKY130_FD_SC_MS__TAPVPWRVGND_PP_SYMBOL_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__tapvpwrvgnd (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPVPWRVGND_PP_SYMBOL_V
|
/*============================================================================
This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point
Arithmetic Package, Release 1, by John R. Hauser.
Copyright 2019 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module
recFNToFN#(parameter expWidth = 3, parameter sigWidth = 3) (
input [(expWidth + sigWidth):0] in,
output [(expWidth + sigWidth - 1):0] out
);
`include "HardFloat_localFuncs.vi"
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
localparam [expWidth:0] minNormExp = (1<<(expWidth - 1)) + 2;
localparam normDistWidth = clog2(sigWidth);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire isNaN, isInf, isZero, sign;
wire signed [(expWidth + 1):0] sExp;
wire [sigWidth:0] sig;
recFNToRawFN#(expWidth, sigWidth)
recFNToRawFN(in, isNaN, isInf, isZero, sign, sExp, sig);
// FIX provided by John Hauser.
// if the input is recoded infinity with x in sig and exp fields,
// isSubnormal also turns x, and fractOut becomes x.
// wire isSubnormal = (sExp < minNormExp);
wire isSubnormal =
((sExp>>(expWidth - 2) == 'b010) && (sExp[(expWidth - 3):0] <= 1))
|| (sExp>>(expWidth - 1) == 'b00);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire [(normDistWidth - 1):0] denormShiftDist = minNormExp - 1 - sExp;
wire [(expWidth - 1):0] expOut =
(isSubnormal ? 0 : sExp - minNormExp + 1)
| (isNaN || isInf ? {expWidth{1'b1}} : 0);
wire [(sigWidth - 2):0] fractOut =
isSubnormal ? (sig>>1)>>denormShiftDist : isInf ? 0 : sig;
assign out = {sign, expOut, fractOut};
endmodule
|
#include <bits/stdc++.h> int mat[1010][1010]; int counts = 0; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) scanf( %d , &mat[i][j]); } counts = 0; for (int i = 1; i <= n; i++) counts += mat[i][i]; counts %= 2; int m; scanf( %d , &m); for (int i = 1; i <= m; i++) { int a; scanf( %d , &a); if (a == 1 || a == 2) { int b; scanf( %d , &b); mat[b][b] = 1 - mat[b][b]; counts = 1 - counts; } else printf( %d , counts); } printf( n ); return 0; } |
// $Id: tc_cfg_bus_ifc.v 1833 2010-03-22 23:18:22Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// configuration bus interface module
module tc_cfg_bus_ifc
(clk, reset, cfg_node_addrs, cfg_req, cfg_write, cfg_addr, cfg_write_data,
cfg_read_data, cfg_done, active, req, write, node_addr_match, reg_addr,
write_data, read_data, done);
`include "c_functions.v"
`include "c_constants.v"
// number of bits in address that are considered base address
parameter cfg_node_addr_width = 10;
// width of register selector part of control register address
parameter cfg_reg_addr_width = 6;
// width of configuration bus addresses
localparam cfg_addr_width = cfg_node_addr_width + cfg_reg_addr_width;
// number of distinct base addresses to which this node replies
parameter num_cfg_node_addrs = 2;
// width of control register data
parameter cfg_data_width = 32;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
// node addresses assigned to this node
input [0:num_cfg_node_addrs*cfg_node_addr_width-1] cfg_node_addrs;
// config register access pending
input cfg_req;
// config register access is write access
input cfg_write;
// select config register to access
input [0:cfg_addr_width-1] cfg_addr;
// data to be written to selected config register for write accesses
input [0:cfg_data_width-1] cfg_write_data;
// contents of selected config register for read accesses
output [0:cfg_data_width-1] cfg_read_data;
wire [0:cfg_data_width-1] cfg_read_data;
// config register access complete
output cfg_done;
wire cfg_done;
// interface logic activity indicator (e.g. for clock gating)
output active;
wire active;
// request to client logic
output req;
wire req;
// write indicator for current request
output write;
wire write;
// which of the configured node addresses matched?
output [0:num_cfg_node_addrs-1] node_addr_match;
wire [0:num_cfg_node_addrs-1] node_addr_match;
// register address
output [0:cfg_reg_addr_width-1] reg_addr;
wire [0:cfg_reg_addr_width-1] reg_addr;
// data to be written to register (if write request)
output [0:cfg_data_width-1] write_data;
wire [0:cfg_data_width-1] write_data;
// contents of selected register (if read request)
input [0:cfg_data_width-1] read_data;
// completion indicator for current request
input done;
wire cfg_stop;
wire cfg_active_s, cfg_active_q;
assign cfg_active_s = (cfg_active_q | cfg_req) & ~cfg_stop;
c_dff
#(.width(1),
.reset_type(reset_type))
cfg_activeq
(.clk(clk),
.reset(reset),
.d(cfg_active_s),
.q(cfg_active_q));
assign active = cfg_active_q;
wire cfg_active_dly_s, cfg_active_dly_q;
assign cfg_active_dly_s
= cfg_active_q ? (cfg_active_q & ~cfg_stop) : cfg_active_dly_q;
c_dff
#(.width(1),
.reset_type(reset_type))
cfg_active_dlyq
(.clk(clk),
.reset(reset),
.d(cfg_active_dly_s),
.q(cfg_active_dly_q));
wire cfg_active_rise;
assign cfg_active_rise = cfg_active_q & ~cfg_active_dly_q;
wire cfg_req_s, cfg_req_q;
assign cfg_req_s = cfg_active_q ? cfg_active_rise : cfg_req_q;
c_dff
#(.width(1),
.reset_type(reset_type))
cfg_reqq
(.clk(clk),
.reset(reset),
.d(cfg_req_s),
.q(cfg_req_q));
assign req = cfg_req_q;
wire cfg_write_s, cfg_write_q;
assign cfg_write_s
= cfg_active_q ? (cfg_active_rise ? cfg_write : cfg_write_q) : cfg_write_q;
c_dff
#(.width(1),
.reset_type(reset_type))
cfg_writeq
(.clk(clk),
.reset(1'b0),
.d(cfg_write_s),
.q(cfg_write_q));
assign write = cfg_write_q;
wire cfg_do_write;
assign cfg_do_write = cfg_req_q & cfg_write_q;
wire [0:cfg_addr_width-1] cfg_addr_s, cfg_addr_q;
assign cfg_addr_s
= cfg_active_q ? (cfg_active_rise ? cfg_addr : cfg_addr_q) : cfg_addr_q;
c_dff
#(.width(cfg_addr_width),
.reset_type(reset_type))
cfg_addrq
(.clk(clk),
.reset(1'b0),
.d(cfg_addr_s),
.q(cfg_addr_q));
assign reg_addr = cfg_addr_q[cfg_node_addr_width:cfg_addr_width-1];
wire [0:cfg_node_addr_width-1] cfg_node_addr_q;
assign cfg_node_addr_q = cfg_addr_q[0:cfg_node_addr_width-1];
wire [0:num_cfg_node_addrs-1] cfg_node_addr_match;
genvar naddr;
generate
for(naddr = 0; naddr < num_cfg_node_addrs; naddr = naddr + 1)
begin:naddrs
assign cfg_node_addr_match[naddr]
= (cfg_node_addr_q ==
cfg_node_addrs[naddr*cfg_node_addr_width:
(naddr+1)*cfg_node_addr_width-1]);
end
endgenerate
assign node_addr_match = cfg_node_addr_match;
wire [0:cfg_data_width-1] cfg_data_s, cfg_data_q;
assign cfg_data_s = cfg_active_q ?
(cfg_active_rise ?
cfg_write_data :
(done ? read_data : cfg_data_q)) :
cfg_data_q;
c_dff
#(.width(cfg_data_width),
.reset_type(reset_type))
cfg_dataq
(.clk(clk),
.reset(1'b0),
.d(cfg_data_s),
.q(cfg_data_q));
assign write_data = cfg_data_q;
assign cfg_read_data = cfg_data_q;
wire cfg_done_s, cfg_done_q;
assign cfg_done_s = cfg_active_q ? done : cfg_done_q;
c_dff
#(.width(1),
.reset_type(reset_type))
cfg_doneq
(.clk(clk),
.reset(reset),
.d(cfg_done_s),
.q(cfg_done_q));
assign cfg_done = cfg_done_q;
assign cfg_stop = cfg_done_q | (cfg_req_q & ~|cfg_node_addr_match);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, tot, a[100010], ans[100010]; vector<pair<int, int> > q[100010]; set<int> s; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1, l, x; i <= m; i++) { scanf( %d%d , &l, &x); q[l].emplace_back(i, x); } s.insert(0); tot = 1; for (int i = 1; i <= n; i++) { if (s.count(a[i])) tot = 1ll * tot * 2 % 1000000007; else { vector<int> v; for (int u : s) v.push_back(u ^ a[i]); for (int u : v) s.insert(u); } for (auto &p : q[i]) ans[p.first] = s.count(p.second) ? tot : 0; } for (int i = 1; i <= m; i++) printf( %d n , ans[i]); } |
#include <bits/stdc++.h> using namespace std; int32_t main() { long long t = 1; while (t--) { long long n, d; cin >> n >> d; vector<long long> temp(n); vector<long long> temp2(n); for (long long i = 0; i < n; i++) { cin >> temp[i]; } for (long long i = 0; i < n; i++) { cin >> temp2[i]; } long long i = 0; long long j = n - 1; if (d == 1) { cout << 1 << endl; continue; } long long score = temp[d - 1] + temp2[0]; long long ans = d; while (i < d - 1) { if (temp[i] + temp2[j] <= score) { ans--; i++; j--; } else { i++; } } cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int sum(long int c) { int somme = 0; while (c) { somme = somme + c % 10; c = c / 10; } return (somme); } int main() { long int k, c = 19; cin >> k; while (k) { if (sum(c) == 10) k--; c += 9; } cout << c - 9; return 0; } |
#include <bits/stdc++.h> using namespace std; int n; string a; void convA() { int c = 0, r = 0; int i; for (i = 1; a[i] != C ; i++) { r *= 10; r += a[i] - 0 ; } i++; for (; i < a.size(); i++) { c *= 10; c += a[i] - 0 ; } vector<int> ans; while (c != 0) { if (c % 26 == 0) { ans.push_back(26); c--; } else ans.push_back(c % 26); c /= 26; } for (int i = ans.size() - 1; i >= 0; i--) { char ab = ans[i] + ( A - 1); cout << ab; } cout << r; cout << endl; } void convB() { vector<int> ans; int i; for (i = 0; a[i] >= A && a[i] <= Z ; i++) { if (a[i] == Z ) ans.push_back(26); else ans.push_back(a[i] - A + 1); } int c = 0, r; for (int j = 0; j < ans.size(); j++) { c += ans[j] * pow(26, ans.size() - j - 1); } cout << R ; for (; i < a.size(); i++) cout << a[i]; cout << C << c << endl; } int main() { ios::sync_with_stdio(false); cin >> n; for (int i = 0; i < n; i++) { cin >> a; bool RC = false, k = false; if (a.size() >= 4) { if (a[0] == R && !(a[1] >= A && a[1] <= Z )) RC = true; else RC = false; for (int i = 2; RC && i < a.size(); i++) { if (a[i] >= A && a[i] <= Z && k) { RC = false; break; } if (a[i] == C && !k) k = true; } if (RC && k) convA(); } if (!RC || !k) convB(); } } |
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module srl
#(parameter WIDTH=18)
(input clk,
input write,
input [WIDTH-1:0] in,
input [3:0] addr,
output [WIDTH-1:0] out);
genvar i;
generate
for (i=0;i<WIDTH;i=i+1)
begin : gen_srl
SRL16E
srl16e(.Q(out[i]),
.A0(addr[0]),.A1(addr[1]),.A2(addr[2]),.A3(addr[3]),
.CE(write),.CLK(clk),.D(in[i]));
end
endgenerate
endmodule // srl
|
#include <bits/stdc++.h> using namespace std; const double Pi = acos(-1.0); const int Inf = 0x3f3f3f3f; const int MAXN = 2e5 + 10; inline int read() { register int x = 0, f = 1, ch = getchar(); while (!isdigit(ch)) f = ch == - ? -1 : 1, ch = getchar(); while (isdigit(ch)) x = x * 10 + ch - 48, ch = getchar(); return x * f; } inline long long readll() { register long long x = 0, f = 1, ch = getchar(); while (!isdigit(ch)) f = ch == - ? -1 : 1, ch = getchar(); while (isdigit(ch)) x = x * 10 + ch - 48, ch = getchar(); return x * f; } struct Edge1 { int u, v, d; Edge1(int u_ = 0, int v_ = 0, int d_ = 0) { u = u_, v = v_, d = d_; } } e[MAXN << 1]; struct Edge2 { int x, y; bool s; }; struct Node { int f[35]; inline void Insert(int x) { for (int i = 30; i >= 0; --i) if (x & (1 << i)) { if (!f[i]) { f[i] = x; return; } x ^= f[i]; } } inline int Query(int x) { for (int i = 30; i >= 0; --i) if ((x ^ f[i]) < x) x ^= f[i]; return x; } } n1; map<pair<int, int>, int> mp; vector<Edge1> v[MAXN << 2]; int n, m, c, Q, tim; int st[MAXN << 1], ed[MAXN << 1]; int qx[MAXN], qy[MAXN]; int fa[MAXN], f[MAXN], dep[MAXN]; inline int Find_fa(int x) { return fa[x] == x ? x : Find_fa(fa[x]); } inline int Find_dis(int x) { return fa[x] == x ? 0 : f[x] ^ Find_dis(fa[x]); } inline void Insert(int k, int l, int r, int x, int y, Edge1 e1) { if (x <= l && r <= y) { v[k].push_back(e1); return; } int mid = (l + r) >> 1; if (x <= mid) Insert(k << 1, l, mid, x, y, e1); if (y > mid) Insert(k << 1 | 1, mid + 1, r, x, y, e1); } inline void Solve(int k, int l, int r, Node G) { stack<Edge2> stk; for (int i = 0; i < (int)v[k].size(); ++i) { int x = v[k][i].u, y = v[k][i].v, d = v[k][i].d; int ex = Find_fa(x), ey = Find_fa(y); d ^= Find_dis(x) ^ Find_dis(y); if (ex == ey) G.Insert(d); else { if (dep[ex] > dep[ey]) swap(ex, ey), swap(x, y); Edge2 cur = (Edge2){ex, ey, 0}; fa[ex] = ey; f[ex] = d; if (dep[ex] == dep[ey]) ++dep[ey], cur.s = 1; stk.push(cur); } } if (l == r) printf( %d n , G.Query(Find_dis(qx[l]) ^ Find_dis(qy[l]))); else { int mid = (l + r) >> 1; Solve(k << 1, l, mid, G); Solve(k << 1 | 1, mid + 1, r, G); } while (!stk.empty()) f[fa[stk.top().x] = stk.top().x] = 0, dep[stk.top().y] -= stk.top().s, stk.pop(); } int main() { n = read(); m = read(); for (int i = 1; i <= n; ++i) fa[i] = i; for (int i = 1; i <= m; ++i) { int u = read(), v = read(), d = read(); mp[make_pair(u, v)] = i; st[i] = 1; ed[i] = -1; e[i] = Edge1(u, v, d); } c = m; tim = 1; Q = read(); for (int i = 1, opt, x, y, z; i <= Q; ++i) { opt = read(); x = read(); y = read(); if (opt == 1) { z = read(); mp[make_pair(x, y)] = ++c; st[c] = tim; ed[c] = -1; e[c] = Edge1(x, y, z); } else if (opt == 2) ed[mp[make_pair(x, y)]] = tim - 1; else qx[tim] = x, qy[tim] = y, ++tim; } --tim; for (int i = 1; i <= c; ++i) { if (ed[i] == -1) ed[i] = tim; if (st[i] <= ed[i]) Insert(1, 1, tim, st[i], ed[i], e[i]); } Solve(1, 1, tim, n1); return 0; } |
#include <bits/stdc++.h> using namespace std; int pp(int n) { for (int i = 2; i <= floor(sqrt(n)); i++) { if (n % i == 0) return i; } return 1; } void solve() { long long int n, k; cin >> n >> k; if (k > n) cout << max(0ll, n - k / 2) << endl; else cout << max(0ll, (k - 1) / 2) << endl; } int main() { int t = 1; while (t--) solve(); } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; struct Edge { long long int from, to, cap, flow, index; Edge(long long int from, long long int to, long long int cap, long long int flow, long long int index) : from(from), to(to), cap(cap), flow(flow), index(index) {} }; struct PushRelabel { long long int N; vector<vector<Edge>> G; vector<long long> excess; vector<long long int> dist, active, count; queue<long long int> Q; PushRelabel(long long int N) : N(N), G(N), excess(N), dist(N), active(N), count(2 * N) {} void AddEdge(long long int from, long long int to, long long int cap) { G[from].push_back(Edge(from, to, cap, 0, G[to].size())); if (from == to) G[from].back().index++; G[to].push_back(Edge(to, from, 0, 0, G[from].size() - 1)); } void Enqueue(long long int v) { if (!active[v] && excess[v] > 0) { active[v] = true; Q.push(v); } } void Push(Edge &e) { long long int amt = min(excess[e.from], e.cap - e.flow); if (dist[e.from] <= dist[e.to] || amt == 0) return; e.flow += amt; G[e.to][e.index].flow -= amt; excess[e.to] += amt; excess[e.from] -= amt; Enqueue(e.to); } void Gap(long long int k) { for (long long int v = 0; v < N; v++) { if (dist[v] < k) continue; count[dist[v]]--; dist[v] = max(dist[v], N + 1); count[dist[v]]++; Enqueue(v); } } void Relabel(long long int v) { count[dist[v]]--; dist[v] = 2 * N; for (long long int i = 0; i < G[v].size(); i++) if (G[v][i].cap - G[v][i].flow > 0) dist[v] = min(dist[v], dist[G[v][i].to] + 1); count[dist[v]]++; Enqueue(v); } void Discharge(long long int v) { for (long long int i = 0; excess[v] > 0 && i < G[v].size(); i++) Push(G[v][i]); if (excess[v] > 0) { if (count[dist[v]] == 1) Gap(dist[v]); else Relabel(v); } } long long GetMaxFlow(long long int s, long long int t) { count[0] = N - 1; count[N] = 1; dist[s] = N; active[s] = active[t] = true; for (long long int i = 0; i < G[s].size(); i++) { excess[s] += G[s][i].cap; Push(G[s][i]); } while (!Q.empty()) { long long int v = Q.front(); Q.pop(); active[v] = false; Discharge(v); } long long totflow = 0; for (long long int i = 0; i < G[s].size(); i++) totflow += G[s][i].flow; return totflow; } }; void solve() { long long int n; cin >> n; long long int m; cin >> m; long long int x; cin >> x; vector<array<long long int, 3>> edge(m); for (long long int i = 0; i < m; i++) { cin >> edge[i][0]; edge[i][0]--; cin >> edge[i][1]; edge[i][1]--; cin >> edge[i][2]; } long double low = 0; long double high = 1e9; for (long long int i = 0; i < 100; i++) { long double mid = (low + high) / (long double)2; PushRelabel G(n); for (auto e : edge) { G.AddEdge(e[0], e[1], (long long int)(e[2] / mid)); } if (G.GetMaxFlow(0, n - 1) >= x) { low = mid; } else { high = mid; } } long double avg = (low + high) / (long double)2; cout << fixed << setprecision(9) << (long double)x * avg << n ; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); solve(); cerr << Time : << 1000 * ((long double)clock()) / (long double)CLOCKS_PER_SEC << ms n ; return 0; } |
// part of NeoGS project
//
// (c) NedoPC 2007-2008
//
// modelling is in tb_dma2.*
module dma_sequencer(
clk,
rst_n,
addr,
wd,
rd,
req,
rnw,
ack,
done,
dma_req,
dma_addr,
dma_rnw,
dma_wd,
dma_rd,
dma_ack,
dma_end
);
parameter DEVNUM = 4;
input clk;
input rst_n;
input [20:0] addr [1:DEVNUM];
input [7:0] wd [1:DEVNUM];
output reg [7:0] rd;
input [DEVNUM:1] req;
input [DEVNUM:1] rnw;
output reg dma_req;
output reg dma_rnw;
output reg [20:0] dma_addr;
output reg [7:0] dma_wd;
input [7:0] dma_rd;
input dma_ack;
input dma_end;
output reg [DEVNUM:1] ack;
output reg [DEVNUM:1] done;
reg [DEVNUM:1] muxbeg;
reg [DEVNUM:1] muxend;
reg [DEVNUM:1] muxend_in;
reg [DEVNUM:1] pri_in;
reg [DEVNUM:1] pri_out;
integer i;
always @*
for(i=1;i<=DEVNUM;i=i+1)
begin
pri_in[i] = (i==1) ? pri_out[DEVNUM] : pri_out[i-1];
pri_out[i] = ( pri_in[i] & (~req[i]) ) | muxend[i];
muxbeg[i] = pri_in[i] & req[i];
muxend_in[i] = muxbeg[i] & dma_ack;
end
always @(posedge clk, negedge rst_n)
begin
if( !rst_n )
begin
muxend[1] <= 1'b1;
for(i=2;i<=DEVNUM;i=i+1)
muxend[i] <= 1'b0;
end
else if( dma_ack )
begin
for(i=1;i<=DEVNUM;i=i+1)
muxend[i] <= muxend_in[i];
end
end
always @*
begin
rd = dma_rd;
dma_req = 1'b0;
for(i=1;i<=DEVNUM;i=i+1)
dma_req = dma_req | req[i];
dma_wd = 8'd0;
for(i=1;i<=DEVNUM;i=i+1)
dma_wd = dma_wd | ( (muxbeg[i]==1'b1) ? wd[i] : 8'd0 );
dma_addr = 21'd0;
for(i=1;i<=DEVNUM;i=i+1)
dma_addr = dma_addr | ( (muxbeg[i]==1'b1) ? addr[i] : 21'd0 );
dma_rnw = 1'b0;
for(i=1;i<=DEVNUM;i=i+1)
dma_rnw = dma_rnw | ( (muxbeg[i]==1'b1) ? rnw[i] : 1'b0 );
for(i=1;i<=DEVNUM;i=i+1)
ack[i] = (muxbeg[i]==1'b1) ? dma_ack : 1'b0;
for(i=1;i<=DEVNUM;i=i+1)
done[i] = (muxend[i]==1'b1) ? dma_end : 1'b0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void add(int& a, int b) { a += b; a = min(a, 100000000); } const int MX = 300005; int root[MX]; bool is_left[MX]; vector<int> nodes[MX]; int left_size[MX], right_size[MX]; int ans = 0; char s[MX]; vector<int> comps[MX]; int main() { int n, k; ignore = scanf( %d %d , &n, &k); ignore = scanf( %s , s + 1); for (int i = 1; i <= k; i++) { int c; ignore = scanf( %d , &c); while (c--) { int x; ignore = scanf( %d , &x); comps[x].push_back(i); } } for (int i = 1; i <= k; i++) { root[i] = i; is_left[i] = false; nodes[i].push_back(i); right_size[i] = 1; } for (int i = 1; i <= n; i++) { if (comps[i].size() == 1) { int x = comps[i][0]; ans -= min(left_size[root[x]], right_size[root[x]]); if (s[i] == 0 ) { if (is_left[x]) { add(right_size[root[x]], MX); } else { add(left_size[root[x]], MX); } } else { if (is_left[x]) { add(left_size[root[x]], MX); } else { add(right_size[root[x]], MX); } } ans += min(left_size[root[x]], right_size[root[x]]); } else if (comps[i].size() == 2) { int x = comps[i][0], y = comps[i][1]; if (root[x] != root[y]) { ans -= min(left_size[root[x]], right_size[root[x]]); ans -= min(left_size[root[y]], right_size[root[y]]); if (nodes[root[x]].size() > nodes[root[y]].size()) { swap(x, y); } if ((is_left[x] == is_left[y]) != (s[i] == 1 )) { for (int v : nodes[root[x]]) is_left[v] = !is_left[v]; swap(left_size[root[x]], right_size[root[x]]); } add(left_size[root[y]], left_size[root[x]]); add(right_size[root[y]], right_size[root[x]]); for (int v : nodes[root[x]]) { nodes[root[y]].push_back(v); root[v] = root[y]; } ans += min(left_size[root[x]], right_size[root[x]]); } } printf( %d n , ans); } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A22OI_PP_SYMBOL_V
`define SKY130_FD_SC_HS__A22OI_PP_SYMBOL_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a22oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A22OI_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); long long n, m, ans = 999999999999999999, mn = 123456789000LL; cin >> n >> m; long long x = n; vector<pair<long long, long long> > v; long long cnt = 0; for (long long i = 2; i <= sqrt(m); i++) { if (m % i == 0) { cnt = 0; while (m % i == 0) { cnt++; m = m / i; } v.push_back({i, cnt}); } } if (m > 1) { mn = 1; v.push_back({m, 1}); } for (int i = 0; i < v.size(); i++) { long long y = x; long long temp = 0; while (y) { temp += y / v[i].first; y = y / v[i].first; } temp = temp / v[i].second; ans = min(temp, ans); } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; vector<string> s; vector<pair<int, int> > v; int gf = 0; int x[9] = {-1, -1, -1, 0, 1, 1, 1, 0, 0}; int y[9] = {-1, 0, 1, 1, 1, 0, -1, -1, 0}; void dfs(int a, int b, int le) { if (gf) return; if (le == 8 || (a == 0 && b == 7)) { gf = 1; return; } int a1, b1, i, j, k, x1, y1, flag, x2, y2; for (i = 0; i < 9; i++) { flag = 0; a1 = a + x[i], b1 = b + y[i]; if (a1 >= 0 && a1 < 8 && b1 >= 0 && b1 < 8) { for (k = 0; k < v.size(); k++) { x1 = v[k].first + (le + 1); y1 = v[k].second; x2 = v[k].first + (le); y2 = v[k].second; if ((a1 == x1 && b1 == y1) || (a1 == x2 && b1 == y2)) flag = 1; } if (flag == 0) dfs(a1, b1, le + 1); } } } int main() { string st; int i; for (i = 0; i < 8; i++) { cin >> st; s.push_back(st); } int j; for (i = 0; i < 8; i++) { for (j = 0; j < 8; j++) { if (s[i][j] == S ) v.push_back(make_pair(i, j)); } } dfs(7, 0, 0); if (gf) cout << WIN << n ; else cout << LOSE << n ; return 0; } |
#include <bits/stdc++.h> int x, y, u, v, d = 1, a, b; int main() { for (scanf( %d%d , &a, &b); a; b /= 4, d *= 2, --a) { if (b % 4 == 0) u = y, v = x; else if (b % 4 == 1) u = x, v = y + d; else if (b % 4 == 2) u = x + d, v = y + d; else u = 2 * d - y - 1, v = d - x - 1; x = u, y = v; } printf( %d %d n , x, y); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O41AI_BEHAVIORAL_V
`define SKY130_FD_SC_HD__O41AI_BEHAVIORAL_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__o41ai (
Y ,
A1,
A2,
A3,
A4,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O41AI_BEHAVIORAL_V |
//--------------------------------------------------------------------------------
// transmitter.vhd
//
// Copyright (C) 2006 Michael Poppitz
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details: http://www.sump.org/projects/analyzer/
//
// Takes 32bit (one sample) and sends it out on the serial port.
// End of transmission is signalled by taking back the busy flag.
// Supports xon/xoff flow control.
//
//--------------------------------------------------------------------------------
//
// 12/29/2010 - Verilog Version + cleanups created by Ian Davis - mygizmos.org
//
`timescale 1ns/100ps
module transmitter #(
parameter [31:0] FREQ = 100000000;
parameter [31:0] BAUDRATE = 115200;
parameter BITLENGTH = FREQ / BAUDRATE;
)(
input wire clock,
input wire trxClock,
input wire reset,
input wire [3:0] disabledGroups,
input wire write, // Data write request
input wire [31:0] wrdata, // Write data
input wire id, // ID output request
input wire xon, // Flow control request
input wire xoff, // Resume output request
output wire tx, // Serial tx data
output reg busy // Busy flag
);
localparam TRUE = 1'b1;
localparam FALSE = 1'b0;
//
// Registers...
//
reg [31:0] sampled_wrdata, next_sampled_wrdata;
reg [3:0] sampled_disabledGroups, next_sampled_disabledGroups;
reg [3:0] bits, next_bits;
reg [2:0] bytesel, next_bytesel;
reg paused, next_paused;
reg byteDone, next_byteDone;
reg next_busy;
reg [9:0] txBuffer, next_txBuffer;
assign tx = txBuffer[0];
reg [9:0] counter, next_counter; // Big enough for FREQ/BAUDRATE (100Mhz/115200 ~= 868)
wire counter_zero = ~|counter;
reg writeByte;
//
// Byte select mux...
//
reg [7:0] byte;
reg disabled;
always
begin
byte = 0;
disabled = 0;
case (bytesel[1:0]) // synthesys parallel_case
2'h0 : begin byte = sampled_wrdata[ 7: 0]; disabled = sampled_disabledGroups[0]; end
2'h1 : begin byte = sampled_wrdata[15: 8]; disabled = sampled_disabledGroups[1]; end
2'h2 : begin byte = sampled_wrdata[23:16]; disabled = sampled_disabledGroups[2]; end
2'h3 : begin byte = sampled_wrdata[31:24]; disabled = sampled_disabledGroups[3]; end
endcase
end
//
// Send one byte...
//
always @ (posedge clock)
begin
counter <= next_counter;
bits <= next_bits;
byteDone <= next_byteDone;
txBuffer <= next_txBuffer;
end
always
begin
next_bits = bits;
next_byteDone = byteDone;
next_txBuffer = txBuffer;
next_counter = counter;
if (writeByte)
begin
next_counter = BITLENGTH;
next_bits = 0;
next_byteDone = FALSE;
next_txBuffer = {1'b1,byte,1'b0}; // 8 bits, no parity, 1 stop bit (8N1)
end
else if (counter_zero)
begin
next_counter = BITLENGTH;
next_txBuffer = {1'b1,txBuffer[9:1]};
if (bits == 4'hA)
next_byteDone = TRUE;
else next_bits = bits + 1'b1;
end
else if (trxClock)
next_counter = counter + 1'b1;
end
//
// Control FSM for sending 32 bit words...
//
parameter [1:0] IDLE = 0, SEND = 1, POLL = 2;
reg [1:0] state, next_state;
always @ (posedge clock or posedge reset)
if (reset) begin
state <= IDLE;
sampled_wrdata <= 32'h0;
sampled_disabledGroups <= 4'h0;
bytesel <= 3'h0;
busy <= FALSE;
paused <= FALSE;
end else begin
state <= next_state;
sampled_wrdata <= next_sampled_wrdata;
sampled_disabledGroups <= next_sampled_disabledGroups;
bytesel <= next_bytesel;
busy <= next_busy;
paused <= next_paused;
end
always
begin
next_state = state;
next_sampled_wrdata = sampled_wrdata;
next_sampled_disabledGroups = sampled_disabledGroups;
next_bytesel = bytesel;
next_busy = (state != IDLE) || write || paused;
next_paused = xoff | (paused & !xon); // set on xoff, reset on xon
writeByte = FALSE;
case(state) // when write is '1', data will be available with next cycle
IDLE :
begin
next_sampled_wrdata = wrdata;
next_sampled_disabledGroups = disabledGroups;
next_bytesel = 2'h0;
if (write)
next_state = SEND;
else if (id) // send our signature/ID code (in response to the query command)
begin
next_sampled_wrdata = 32'h534c4131; // "SLA1"
next_sampled_disabledGroups = 4'b0000;
next_state = SEND;
end
end
SEND :
begin
writeByte = TRUE;
next_bytesel = bytesel+1'b1;
next_state = POLL;
end
POLL :
begin
if (byteDone && !paused)
next_state = (bytesel[2]) ? IDLE : SEND;
end
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MAJ3_BEHAVIORAL_V
`define SKY130_FD_SC_LP__MAJ3_BEHAVIORAL_V
/**
* maj3: 3-input majority vote.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__maj3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out ;
wire and1_out ;
wire or1_out_X;
// Name Output Other arguments
or or0 (or0_out , B, A );
and and0 (and0_out , or0_out, C );
and and1 (and1_out , A, B );
or or1 (or1_out_X, and1_out, and0_out);
buf buf0 (X , or1_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__MAJ3_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; template <typename T> T gcd(T x, T y) { if (x < y) swap(x, y); while (y > 0) { T f = x % y; x = y; y = f; } return x; } const int maxn = 100007; int BLOCKSIZE = 250; set<int> s[maxn]; int a[maxn]; int nxt[maxn]; int prv[maxn]; int n, m; long long b[maxn]; int d[maxn]; int lst[maxn]; long long query(int block, int R) { int iBlockStart = block * BLOCKSIZE; int iBlockEnd = min((block + 1) * BLOCKSIZE, n); int idx = upper_bound(d + iBlockStart, d + iBlockEnd, R, [](int i, int j) { return i < nxt[j]; }) - d; if (idx == iBlockStart) return 0; return b[idx - 1]; } void updateBlock(int block) { int iBlockStart = block * BLOCKSIZE; int iBlockEnd = min((block + 1) * BLOCKSIZE, n); sort(d + iBlockStart, d + iBlockEnd, [](int i, int j) { return nxt[i] < nxt[j]; }); b[iBlockStart] = nxt[d[iBlockStart]] - d[iBlockStart]; for (int i = iBlockStart + 1; i < iBlockEnd; i++) b[i] = b[i - 1] + nxt[d[i]] - d[i]; } int main(int argc, char *argv[]) { std::cin.sync_with_stdio(false); std::cin.tie(nullptr); cin >> n >> m; { for (int i = 0; i < n; i++) nxt[i] = n, prv[i] = -1, d[i] = i; memset(lst, -1, sizeof(lst)); for (int i = 0; i < n; i++) { cin >> a[i]; int pr = lst[a[i]]; if (pr != -1) { nxt[pr] = i; prv[i] = pr; } lst[a[i]] = i; s[a[i]].insert(i); } for (int i = 0; i * BLOCKSIZE < n; i++) updateBlock(i); for (int i = 0; i < m; i++) { int op; cin >> op; if (op == 1) { int p, x; cin >> p >> x; p--; if (a[p] == x) continue; if (nxt[p] != n) prv[nxt[p]] = prv[p]; if (prv[p] != -1) { nxt[prv[p]] = nxt[p]; if (prv[p] / BLOCKSIZE != p / BLOCKSIZE) updateBlock(prv[p] / BLOCKSIZE); } s[a[p]].erase(p); a[p] = x; nxt[p] = n; prv[p] = -1; auto it = s[x].emplace(p).first; bool updatedNext = false; if (it != s[x].begin()) { int pr = *prev(it); int nx = nxt[pr]; nxt[pr] = p; prv[p] = pr; if (pr / BLOCKSIZE != p / BLOCKSIZE) updateBlock(pr / BLOCKSIZE); if (nx != n) { prv[nx] = p; nxt[p] = nx; updatedNext = true; } } if (!updatedNext) { auto nxiter = next(it); if (nxiter != s[x].end()) { int nx = *nxiter; prv[nx] = p; nxt[p] = nx; } } updateBlock(p / BLOCKSIZE); } else { int l, r, R; cin >> l >> r; l--; r--; R = r; long long res = 0; for (; l <= r && l % BLOCKSIZE; l++) if (nxt[l] <= R) res += nxt[l] - l; for (; l <= r && (r + 1) % BLOCKSIZE; r--) if (nxt[r] <= R) res += nxt[r] - r; if (l <= r) { for (int i = l / BLOCKSIZE, j = r / BLOCKSIZE; i <= j; i++) { res += query(i, R); } } cout << res << endl; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; int max(int a, int b) { if (a > b) return a; else return b; } int main() { long int x, y, z, w, mx; cin >> x >> y >> z >> w; mx = max(w, max(z, max(x, y))); if (mx == w) { cout << (mx - z) << << (mx - y) << << (mx - x); } else if (mx == z) { cout << (mx - w) << << (mx - y) << << (mx - x); } else if (mx == y) { cout << (mx - z) << << (mx - w) << << (mx - x); } else { cout << (mx - z) << << (mx - y) << << (mx - w); } return 0; } |
#include <bits/stdc++.h> using namespace std; bool cmp(pair<int, int> p1, pair<int, int> p2) { return (p1.first < p2.first) || (p1.first == p2.first && p1.second > p2.second); } int main() { bool b[200000]; int t[200000]; int n; cin >> n; for (int i = 1; i <= n; ++i) { cin >> t[i]; b[i] = true; } int answer = 1; for (int i = 2; i <= n; ++i) { if (t[i] == 0) { ++answer; continue; } if (b[t[i]]) b[t[i]] = false; else ++answer; } cout << answer; } |
#include <bits/stdc++.h> using namespace std; namespace WorkSpace { const int max_num = 100010; unsigned int F[max_num >> 1]; void Main() { register int N; scanf( %d , &N); if (N & 1) { printf( 0 n ); return; } static char S[max_num]; register int Half = N >> 1; scanf( %s , S + 1); F[0] = 1; register int Num = 0; for (register int i = 1; i <= N; ++i) { if (S[i] == ? ) { for (register int j = i >> 1; j && j >= i - Half; --j) F[j] += F[j - 1]; } else ++Num; } register unsigned int ans = F[Half]; for (register int i = 0; i < Half - Num; ++i) ans *= 25; printf( %u n , ans); } } // namespace WorkSpace int main() { WorkSpace ::Main(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxv = 1.5e7; const int bit = 29; int cnt[maxv] = {}; int go[maxv][2] = {}; int tot = 1; void add(int v, int d, int val) { cnt[v]++; if (d == -1) return; if (!go[v][(val >> d) & 1]) go[v][(val >> d) & 1] = ++tot; add(go[v][(val >> d) & 1], d - 1, val); } void get(int v, int d, int val, int& t_a) { assert(cnt[v]); cnt[v]--; if (d == -1) return; for (int k = ((val >> d) & 1), l = 0; l < 2; k = 1 - k, ++l) if (go[v][k]) { get(go[v][k], d - 1, val, t_a); if (!cnt[go[v][k]]) go[v][k] = 0; t_a += (k << d); return; } } int main() { int n; cin >> n; vector<int> msg(n); for (int& i : msg) cin >> i; for (int i = 0; i < n; i++) { int x; cin >> x; add(1, bit, x); } for (int i : msg) { int out = 0; get(1, bit, i, out); assert((i ^ out) >= 0); cout << (i ^ out) << ; } return 0; } |
// File: FullAdderViaHAs_TBV.v
// Generated by MyHDL 0.10
// Date: Tue Aug 21 12:52:20 2018
`timescale 1ns/10ps
module FullAdderViaHAs_TBV (
);
// myHDL -> Verilog Testbench for module "FullAdderViaHAs"
reg x1 = 0;
reg x2 = 0;
wire s;
wire c;
wire [7:0] x1TVals;
wire [7:0] x2TVals;
reg cin = 0;
wire [7:0] cinTVals;
wire FullAdderViaHAs0_0_s_HA1HA2;
wire FullAdderViaHAs0_0_c_HA1CL;
wire FullAdderViaHAs0_0_c_HA2CL;
assign x1TVals = 8'd15;
assign x2TVals = 8'd51;
assign cinTVals = 8'd85;
always @(x2, c, s, cin, x1) begin: FULLADDERVIAHAS_TBV_PRINT_DATA
$write("%h", x1);
$write(" ");
$write("%h", x2);
$write(" ");
$write("%h", cin);
$write(" ");
$write("%h", s);
$write(" ");
$write("%h", c);
$write("\n");
end
assign FullAdderViaHAs0_0_s_HA1HA2 = (x1 ^ x2);
assign FullAdderViaHAs0_0_c_HA1CL = (x1 & x2);
assign s = (cin ^ FullAdderViaHAs0_0_s_HA1HA2);
assign FullAdderViaHAs0_0_c_HA2CL = (cin & FullAdderViaHAs0_0_s_HA1HA2);
assign c = (FullAdderViaHAs0_0_c_HA1CL | FullAdderViaHAs0_0_c_HA2CL);
initial begin: FULLADDERVIAHAS_TBV_STIMULES
integer i;
for (i=0; i<8; i=i+1) begin
x1 <= x1TVals[i];
x2 <= x2TVals[i];
cin <= cinTVals[i];
# 1;
end
$finish;
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:12:04 10/30/2011
// Design Name: M_uxa_ps2_fifo
// Module Name: /Users/kc5tja/tmp/kestrel/2/nexys2/uxa/ps2io/T_uxa_ps2_fifo.v
// Project Name: ps2io
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: M_uxa_ps2_fifo
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module T_uxa_ps2_fifo;
// Inputs
reg [7:0] d_i;
reg we_i;
reg wp_inc_i;
reg rp_inc_i;
reg sys_clk_i;
reg sys_reset_i;
// Outputs
wire [7:0] q_o;
wire full_o;
wire data_available_o;
// Instantiate the Unit Under Test (UUT)
M_uxa_ps2_fifo uut (
.d_i(d_i),
.we_i(we_i),
.wp_inc_i(wp_inc_i),
.q_o(q_o),
.rp_inc_i(rp_inc_i),
.full_o(full_o),
.data_available_o(data_available_o),
.sys_clk_i(sys_clk_i),
.sys_reset_i(sys_reset_i)
);
always begin
#40 sys_clk_i <= ~sys_clk_i;
end
initial begin
// Initialize Inputs
d_i = 0;
we_i = 0;
wp_inc_i = 0;
rp_inc_i = 0;
sys_clk_i = 0;
sys_reset_i = 0;
// Asserting reset should bring our outputs to
// well-known states.
#80 sys_reset_i = 1;
#80 sys_reset_i = 0;
#80 if (full_o != 0) begin
$display("Unexpectedly full queue");
end
if (data_available_o != 0) begin
$display("Unexpected data in the queue");
end
// Writing a single byte to the queue should
// result in q_o seeing the changes. This is
// because both read and write pointers should
// match.
#160 d_i <= 8'b10110111; we_i <= 1;
#80 we_i <= 0;
#80 if (full_o != 0) begin
$display("A single byte shouldn't fill up a 16-deep queue.");
$stop;
end
if (data_available_o != 0) begin
$display("Write pointer hasn't been incremented yet, so data available flag should be false.");
$stop;
end
if (q_o != 8'hB7) begin
$display("Data stored doesn't match that which is retrievable.");
$stop;
end
// Related to the above tests, bumping the write
// pointer should result in data available indication.
wp_inc_i <= 1;
#80 wp_inc_i <= 0;
#80 if (data_available_o != 1) begin
$display("Write pointer bumped; data should now be available.");
$stop;
end
// Related to the above tests again, bumping the read
// pointer should result in an unknown q_o state, and
// data_available_o going false (since we've read all
// available known data).
rp_inc_i <= 1;
#80 rp_inc_i <= 0;
#80 if (data_available_o != 0) begin
$display("We read all available data; no more should exist.");
$stop;
end
if (q_o != 8'bxxxxxxxx) begin
$display("Bus should be in unknown state.");
$stop;
end
// For our next test, let's attempt to push 20 values into
// the queue. We'll just push the values 1 through 20.
// The queue should indicate that data is both available and
// that the queue is full.
#160 we_i <= 1; d_i <= 8'd1;
#80 we_i <= 0; wp_inc_i <= 1;
#80 we_i <= 1; d_i <= 8'd2; wp_inc_i <= 0;
#80 we_i <= 0; wp_inc_i <= 1;
#80 we_i <= 1; d_i <= 8'd3; wp_inc_i <= 0;
#80 we_i <= 0; wp_inc_i <= 1;
#80 we_i <= 1; d_i <= 8'd4; wp_inc_i <= 0;
#80 we_i <= 0; wp_inc_i <= 1;
#80 we_i <= 1; d_i <= 8'd5; wp_inc_i <= 0;
#80 we_i <= 0; wp_inc_i <= 1;
#80 we_i <= 1; d_i <= 8'd6; wp_inc_i <= 0;
#80 we_i <= 0; wp_inc_i <= 1;
#80 we_i <= 1; d_i <= 8'd7; wp_inc_i <= 0;
#80 we_i <= 0; wp_inc_i <= 1;
#80 we_i <= 1; d_i <= 8'd8; wp_inc_i <= 0;
#80 we_i <= 0; wp_inc_i <= 1;
#80 we_i <= 1; d_i <= 8'd9; wp_inc_i <= 0;
#80 we_i <= 0; wp_inc_i <= 1;
#80 we_i <= 1; d_i <= 8'd10; wp_inc_i <= 0;
#80 we_i <= 0; wp_inc_i <= 1;
#80 we_i <= 1; d_i <= 8'd11; wp_inc_i <= 0;
#80 we_i <= 0; wp_inc_i <= 1;
#80 we_i <= 1; d_i <= 8'd12; wp_inc_i <= 0;
#80 we_i <= 0; wp_inc_i <= 1;
#80 we_i <= 1; d_i <= 8'd13; wp_inc_i <= 0;
#80 we_i <= 0; wp_inc_i <= 1;
#80 we_i <= 1; d_i <= 8'd14; wp_inc_i <= 0;
#80 we_i <= 0; wp_inc_i <= 1;
#80 we_i <= 1; d_i <= 8'd15; wp_inc_i <= 0;
#80 we_i <= 0; wp_inc_i <= 1;
// At this point, full_o should be asserted. But,
// we're stress-testing the circuit, so we ignore it.
// Keep on pushing values.
#80 we_i <= 1; d_i <= 8'd16; wp_inc_i <= 0;
#80 we_i <= 0; wp_inc_i <= 1;
#80 we_i <= 1; d_i <= 8'd17; wp_inc_i <= 0;
#80 we_i <= 0; wp_inc_i <= 1;
#80 we_i <= 1; d_i <= 8'd18; wp_inc_i <= 0;
#80 we_i <= 0; wp_inc_i <= 1;
#80 we_i <= 1; d_i <= 8'd19; wp_inc_i <= 0;
#80 we_i <= 0; wp_inc_i <= 1;
#80 we_i <= 1; d_i <= 8'd20; wp_inc_i <= 0;
#80 we_i <= 0; wp_inc_i <= 1;
#80 wp_inc_i <= 0; if (full_o != 1) begin
$display("Hungry hippo is hungry. Queue should be packed.");
$stop;
end
if (data_available_o != 1) begin
$display("A full queue always has data available.");
end
// Now, if we read back these values, we should see
// the sequence 1..15.
if (q_o != 8'd1) begin
$display("Data byte 1 invalid."); $stop;
end
rp_inc_i <= 1; #80 rp_inc_i <= 0; #80;
if (full_o != 0) begin
$display("We read one byte from the queue; we shouldn't be full anymore."); $stop;
end
if (q_o != 8'd2) begin
$display("Data byte 2 invalid."); $stop;
end
rp_inc_i <= 1; #80 rp_inc_i <= 0; #80;
if (q_o != 8'd3) begin
$display("Data byte 3 invalid."); $stop;
end
rp_inc_i <= 1; #80 rp_inc_i <= 0; #80;
if (q_o != 8'd4) begin
$display("Data byte 4 invalid."); $stop;
end
rp_inc_i <= 1; #80 rp_inc_i <= 0; #80;
if (q_o != 8'd5) begin
$display("Data byte 5 invalid."); $stop;
end
rp_inc_i <= 1; #80 rp_inc_i <= 0; #80;
if (q_o != 8'd6) begin
$display("Data byte 6 invalid."); $stop;
end
rp_inc_i <= 1; #80 rp_inc_i <= 0; #80;
if (q_o != 8'd7) begin
$display("Data byte 7 invalid."); $stop;
end
rp_inc_i <= 1; #80 rp_inc_i <= 0; #80;
if (q_o != 8'd8) begin
$display("Data byte 8 invalid."); $stop;
end
rp_inc_i <= 1; #80 rp_inc_i <= 0; #80;
if (q_o != 8'd9) begin
$display("Data byte 9 invalid."); $stop;
end
rp_inc_i <= 1; #80 rp_inc_i <= 0; #80;
if (q_o != 8'd10) begin
$display("Data byte 10 invalid."); $stop;
end
rp_inc_i <= 1; #80 rp_inc_i <= 0; #80;
if (q_o != 8'd11) begin
$display("Data byte 11 invalid."); $stop;
end
rp_inc_i <= 1; #80 rp_inc_i <= 0; #80;
if (q_o != 8'd12) begin
$display("Data byte 12 invalid."); $stop;
end
rp_inc_i <= 1; #80 rp_inc_i <= 0; #80;
if (q_o != 8'd13) begin
$display("Data byte 13 invalid."); $stop;
end
rp_inc_i <= 1; #80 rp_inc_i <= 0; #80;
if (q_o != 8'd14) begin
$display("Data byte 14 invalid."); $stop;
end
rp_inc_i <= 1; #80 rp_inc_i <= 0; #80;
if (q_o != 8'd15) begin
$display("Data byte 15 invalid."); $stop;
end
rp_inc_i <= 1; #80 rp_inc_i <= 0; #80;
if (data_available_o != 0) begin
$display("We read all available bytes. No more should be available."); $stop;
end
if (full_o != 0) begin
$display("We read all bytes from the queue; we shouldn't be full anymore."); $stop;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int i, a[n]; long long int c = 0, ans = 0; for (i = 0; i < n; i++) { cin >> a[i]; c += a[i]; } for (i = 1; i <= 5; i++) { if ((c + i) % (n + 1) != 1) ans++; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int a, b, c, d, p; int main() { cin >> a >> b >> c >> d; d -= c - 1; a -= c; b -= c; if (d == 2) { a--; b--; p = 3; } if (d == 1) { if (a) { a--; p = 1; } else { b--; p = 2; } } if (a < 0 || b < 0 || d > 2 || d < 0) cout << -1 ; else { if (p & 2) cout << 7 ; for (; a > 0; a--) cout << 4 ; for (; c > 0; c--) cout << 47 ; for (; b > 0; b--) cout << 7 ; if (p & 1) cout << 4 ; } return 0; } |
/*
* Copyright (C) 2015-2016 Harmon Instruments, LLC
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/
*
*/
`timescale 1ns / 1ps
// p = (a*b) +- (c*d)
// 4 cycle pipe, (3 for sub)
module dual_mult_add
(
input clock,
input ce,
input sub, // 1: (a*b) - (c*d), 0: (a*b) + (c*d)
input signed [24:0] a,
input signed [17:0] b,
input signed [24:0] c,
input signed [17:0] d,
output signed [47:0] p
);
wire [47:0] pc;
dsp48_wrap_f #(.AREG(1), .BREG(1)) m0
(
.clock(clock),
.ce1(ce),
.ce2(1'b1),
.cem(1'b1),
.cep(1'b1),
.a(a),
.b(b),
.c(48'h0),
.d(25'h0),
.mode(5'd0),
.pcin(48'h0),
.pcout(pc),
.p()
);
dsp48_wrap_f #(.AREG(2), .BREG(2)) m1
(
.clock(clock),
.ce1(ce),
.ce2(1'b1),
.cem(1'b1),
.cep(1'b1),
.a(c),
.b(d),
.c(48'b0),
.d(25'b0),
.mode({3'b001,sub,sub}),
.pcin(pc),
.pcout(),
.p(p)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A32O_BLACKBOX_V
`define SKY130_FD_SC_LS__A32O_BLACKBOX_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a32o (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A32O_BLACKBOX_V
|
module clock_display(
in_clk,
tens_hours,
hours,
tens_minutes,
minutes,
tens_seconds,
seconds,
segment_sel,
seven_seg_out
);
// ports
input in_clk;
input [3:0] tens_hours, hours, tens_minutes, minutes, tens_seconds, seconds;
output [5:0] segment_sel;
output [6:0] seven_seg_out;
// registers and wires
reg [5:0] segment_sel;
reg [3:0] digit;
wire [3:0] bcd;
// logic
initial
digit <= 4'h0;
always @ (posedge in_clk) begin
if (digit == 4'h5)
digit <= 4'h0;
else
digit <= digit + 1;
end
always @ (digit) begin
case (digit)
4'h0: segment_sel <= 6'b100000;
4'h1: segment_sel <= 6'b010000;
4'h2: segment_sel <= 6'b001000;
4'h3: segment_sel <= 6'b000100;
4'h4: segment_sel <= 6'b000010;
4'h5: segment_sel <= 6'b000001;
default: segment_sel <= 6'b000000;
endcase
end
clock_mux u1(
digit,
tens_hours,
hours,
tens_minutes,
minutes,
tens_seconds,
seconds,
bcd
);
bcd_to_seven_seg(
bcd,
seven_seg_out
);
endmodule
// module declaraation
module clock_mux(
sel,
in0,
in1,
in2,
in3,
in4,
in5,
mux_out
);
// ports
input [3:0] sel, in0, in1, in2, in3, in4, in5;
output [3:0] mux_out;
// wires
reg [3:0] mux_out;
// code
always @ (sel) begin
case (sel)
4'h0: mux_out <= in0;
4'h1: mux_out <= in1;
4'h2: mux_out <= in2;
4'h3: mux_out <= in3;
4'h4: mux_out <= in4;
4'h5: mux_out <= in5;
default: mux_out <= 4'h0;
endcase
end
endmodule
module bcd_to_seven_seg(
bcd,
seven_seg
);
input [3:0] bcd;
output [6:0] seven_seg;
reg [6:0] seven_seg;
always @ (bcd) begin
case (bcd)
4'h0: seven_seg <= 7'b1111110;
4'h1: seven_seg <= 7'b0110000;
4'h2: seven_seg <= 7'b1101101;
4'h3: seven_seg <= 7'b1111001;
4'h4: seven_seg <= 7'b0110011;
4'h5: seven_seg <= 7'b1011011;
4'h6: seven_seg <= 7'b1011111;
4'h7: seven_seg <= 7'b1110000;
4'h8: seven_seg <= 7'b1111111;
4'h9: seven_seg <= 7'b1111011;
default: seven_seg <= 7'b0000000;
endcase
end
endmodule
|
`timescale 1 ns / 1 ps
//////////////////////////////////////////////////////////////////////////////////
// Company: AGH UST
// Engineer: Wojciech Gredel, Hubert Górowski
//
// Create Date:
// Design Name:
// Module Name: Player
// Project Name: DOS_Mario
// Target Devices: Basys3
// Tool versions: Vivado 2016.1
// Description:
// This module displays player
//
// Dependencies:
//
// Revision:
// Revision 0.01 - Module created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Player
#( parameter
SMALL = 40,
BIG = 80
)
(
input wire [9:0] xpos,
input wire [8:0] ypos,
input wire direction,
input wire size,
input wire fire,
input wire [9:0] hcount_in,
input wire hsync_in,
input wire [9:0] vcount_in,
input wire vsync_in,
input wire blnk_in,
input wire rst,
input wire clk,
input wire [23:0] rgb_in,
input wire [23:0] rom_data,
output reg [10:0] rom_addr,
output reg [9:0] hcount_out,
output reg hsync_out,
output reg [9:0] vcount_out,
output reg vsync_out,
output reg [23:0] rgb_out,
output reg blnk_out
);
localparam ALFA_COLOR = 24'hA3_49_A4;
localparam YRES = 480;
localparam PLAYER_WIDTH = 40;
reg [5:0] player_height;
reg [5:0] player_height_nxt;
reg [23:0] rgb_nxt;
reg [10:0] rom_addr_nxt;
always @(posedge clk or posedge rst) begin
if(rst)
rom_addr <= #1 0;
else
rom_addr <= #1 rom_addr_nxt;
end
always @(posedge clk or posedge rst) begin
if(rst) begin
rgb_out <= #1 0;
hcount_out <= #1 0;
hsync_out <= #1 0;
vcount_out <= #1 0;
vsync_out <= #1 0;
blnk_out <= #1 0;
end
else begin
rgb_out <= #1 rgb_nxt;
hcount_out <= #1 hcount_in;
hsync_out <= #1 hsync_in;
vcount_out <= #1 vcount_in;
vsync_out <= #1 vsync_in;
blnk_out <= #1 blnk_in;
end
end
always @* begin
if(size)
player_height_nxt = BIG;
else
player_height_nxt = SMALL;
end
always@(posedge clk or posedge rst) begin
if(rst) begin
player_height = SMALL;
end
else begin
player_height = player_height_nxt;
end
end
always @* begin
if(direction) begin
rom_addr_nxt = PLAYER_WIDTH*(vcount_in -(YRES - ypos - player_height)) + (PLAYER_WIDTH - 1 - (hcount_in - xpos + 1));
end
else begin
rom_addr_nxt = PLAYER_WIDTH*(vcount_in -(YRES - ypos - player_height)) + ((hcount_in - xpos + 1));
end
end
always @*
begin
if(((YRES - 1 - vcount_in) < (ypos + player_height)) && ((YRES - 1 - vcount_in) >= ypos) && (hcount_in < (xpos+PLAYER_WIDTH) ) && ((xpos) <= hcount_in)) begin
if(rom_data == ALFA_COLOR)
rgb_nxt = rgb_in;
else
rgb_nxt = rom_data;
end
else begin
rgb_nxt = rgb_in;
end
end
endmodule |
#include <bits/stdc++.h> using namespace std; using LL = long long; using pii = pair<int, int>; using UI = unsigned int; const int mod = 1e9 + 7; const int inf = 0x3f3f3f3f; const double EPS = 1e-8; const double PI = acos(-1.0); const int N = 5e5 + 10; const int M = N + (1 << 20); int n, a[N][2]; int deg[1 << 20]; bool vis[N << 1]; vector<pii> G[M]; vector<int> ans; void dfs(int x, int idx) { pii p; while (G[x].size()) { p = G[x].back(); G[x].pop_back(); if (!vis[p.second]) { vis[p.second] = 1; dfs(p.first, p.second); } } if (idx != -1) { ans.emplace_back(idx); } } void add_edge(int x, int y, int idx) { G[x].emplace_back(y, idx); G[y].emplace_back(x, idx); } bool ok(int k) { int mask = (1 << k) - 1; for (int i = (0); i < ((1 << k)); ++i) { deg[i] = 0; } for (int i = (0); i < ((1 << k) + n); ++i) { G[i].clear(); } int x, y, z; int offset = 1 << k; for (int i = (0); i < (n); ++i) { x = a[i][0] & mask; y = a[i][1] & mask; deg[x] += 1; deg[y] += 1; add_edge(x, i + offset, i << 1); add_edge(y, i + offset, i << 1 | 1); } for (int i = (0); i < (1 << k); ++i) { if (deg[i] & 1) return 0; } for (int i = (0); i < (n << 1); ++i) { vis[i] = 0; } ans.clear(); for (int i = (0); i < (n + (1 << k)); ++i) { if (G[i].size()) { dfs(i, -1); break; } } if (ans.size() < n * 2) { return 0; } printf( %d n , k); for (int i = (0); i < (ans.size()); ++i) { printf( %d , ans[i] + 1); } puts( ); return 1; } int main() { scanf( %d , &n); for (int i = (0); i < (n); ++i) { scanf( %d %d , &a[i][0], &a[i][1]); } for (int i = (20); i > (0); --i) { if (ok(i)) { return 0; } } puts( 0 ); for (int i = (1); i < (n + 1); ++i) { printf( %d %d , i * 2 - 1, i * 2); } puts( ); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR4B_TB_V
`define SKY130_FD_SC_LS__OR4B_TB_V
/**
* or4b: 4-input OR, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__or4b.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg D_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
D_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D_N = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D_N = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D_N = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D_N = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D_N = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_ls__or4b dut (.A(A), .B(B), .C(C), .D_N(D_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR4B_TB_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 5; const int N = 2 * maxn; int n, m, a[maxn]; int v[N]; void jl(int x) { for (int i = x; i < N; i += i & -i) { v[i]++; } } long long s(int x) { long long sum = 0; for (int i = x; i > 0; i -= i & -i) { sum += v[i]; } return sum; } long long cal(int k) { memset(v, 0, sizeof(v)); jl(n + 1); int dp = 0; long long sum = 0; for (int i = 0; i < n; i++) { if (a[i] <= k) dp -= 1; else dp += 1; sum += s(dp + n); jl(dp + n + 1); } return sum; } int main() { scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) scanf( %d , &a[i]); cout << cal(m - 1) - cal(m) << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n], i; double ans = 0.0f; for (i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); if (n % 2 == 0) { for (i = 0; i < n; i = i + 2) { ans = ans + ((a[i + 1] * a[i + 1]) - (a[i] * a[i])); } } else { ans = ans + a[0] * a[0]; for (i = 1; i < n; i = i + 2) { ans = ans + ((a[i + 1] * a[i + 1]) - (a[i] * a[i])); } } double pi = asin(1) * 2; cout << fixed << setprecision(10) << ans * pi << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int a = 0, b = 1023, c, n; char op; cin >> n; for (int i = 0; i < n; ++i) { cin >> op >> c; switch (op) { case | : a |= c; b |= c; break; case & : a &= c; b &= c; break; case ^ : a ^= c; b ^= c; break; } } int r = 0, nd = 1023, xr = 0; for (int i = 0; i < 10; ++i) { int p = (a >> i) & 1; int q = (b >> i) & 1; if (!p && !q) { nd ^= (1 << i); } else if (p && !q) { xr |= (1 << i); } else if (p && q) { r |= (1 << i); } } int s = 3; if (nd == 1023) s--; if (xr == 0) s--; if (r == 0) s--; cout << s << endl; if (nd != 1023) cout << & << nd << endl; if (xr != 0) cout << ^ << xr << endl; if (r != 0) cout << | << r << endl; return 0; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's IC RAMs ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Instantiation of Instruction cache data rams ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_ic_ram.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Minor update:
// Coding style changed.
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_ic_ram(
// Clock and reset
clk, rst,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Internal i/f
addr, en, we, datain, dataout
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_ICINDX;
//
// I/O
//
input clk;
input rst;
input [aw-1:0] addr;
input en;
input [3:0] we;
input [dw-1:0] datain;
output [dw-1:0] dataout;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
`ifdef OR1200_NO_IC
//
// Insn cache not implemented
//
assign dataout = {dw{1'b0}};
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`else
//
// Instantiation of IC RAM block
//
or1200_spram #
(
.aw(`OR1200_ICINDX),
.dw(32)
)
ic_ram0
(
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.clk(clk),
.ce(en),
.we(we[0]),
//.oe(1'b1),
.addr(addr),
.di(datain),
.doq(dataout)
);
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { int n, x; cin >> n >> x; vector<pair<int, int> > v; for (int i = 0; i < n; i++) { int k, l; cin >> k >> l; v.push_back(make_pair(k, l)); } int j = 0, ma = -1, b = 0; for (int i = 0; i < n; i++) { b = max(b, v[i].first); if ((v[i].first - v[i].second) > ma) { ma = max(v[i].first - v[i].second, ma); j = v[i].first; } else if ((v[i].first - v[i].second) == ma) { if (v[i].first > j) { j = v[i].first; } } } if (b >= x) { cout << 1 << endl; } else if (ma > 0) { if ((x - b) % ma == 0) { cout << (x - b) / ma + 1 << endl; } else { cout << (x - b) / ma + 2 << endl; } } else { cout << -1 << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string a, s; cin >> a >> s; sort(s.begin(), s.end()); reverse(s.begin(), s.end()); int k = 0; for (int i = 0; i < a.size() && i < s.size(); i++) { bool found = false; for (int j = k; j < a.size(); j++) { if (s[i] > a[j]) { a[j] = s[i]; found = true; k = j; break; } } if (!found) break; } cout << a << endl; } |
/*============================================================================
This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point
Arithmetic Package, Release 1, by John R. Hauser.
Copyright 2019 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
`include "HardFloat_consts.vi"
`include "HardFloat_specialize.vi"
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module
test_iNToRecFN#(
parameter intWidth = 1, parameter expWidth = 3, parameter sigWidth = 3
);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
parameter maxNumErrors = 20;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
localparam formatWidth = expWidth + sigWidth;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
reg [(`floatControlWidth - 1):0] control;
reg signedIn;
reg [2:0] roundingMode;
reg [(intWidth - 1):0] in;
reg [(formatWidth - 1):0] expectOut;
reg [4:0] expectExceptionFlags;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire [formatWidth:0] recExpectOut;
fNToRecFN#(expWidth, sigWidth)
fNToRecFN_expectOut(expectOut, recExpectOut);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire [formatWidth:0] recOut;
wire [4:0] exceptionFlags;
iNToRecFN#(intWidth, expWidth, sigWidth)
iNToRecFN(control, signedIn, in, roundingMode, recOut, exceptionFlags);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire sameOut;
sameRecFN#(expWidth, sigWidth)
same_recOut(recOut, recExpectOut, sameOut);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
integer errorCount, count, partialCount;
initial begin
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
$fwrite('h80000002, "Testing 'i%0dToRecF%0d'", intWidth, formatWidth);
if (
$fscanf('h80000000, "%h %h %h", control, signedIn, roundingMode)
< 3
) begin
$fdisplay('h80000002, ".\n--> Invalid test-cases input.");
`finish_fail;
end
$fdisplay(
'h80000002,
"control %H, signed %0d, rounding mode %0d:",
control,
signedIn,
roundingMode
);
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
errorCount = 0;
count = 0;
partialCount = 0;
begin :TestLoop
while (
$fscanf(
'h80000000, "%h %h %h", in, expectOut, expectExceptionFlags
) == 3
) begin
#1;
partialCount = partialCount + 1;
if (partialCount == 10000) begin
count = count + 10000;
$fdisplay('h80000002, "%0d...", count);
partialCount = 0;
end
if (
!sameOut || (exceptionFlags !== expectExceptionFlags)
) begin
if (errorCount == 0) begin
$display(
"Errors found in 'i%0dToRecF%0d', control %H, signed %0d, rounding mode %0d:",
intWidth,
formatWidth,
control,
signedIn,
roundingMode
);
end
$write("%H => %H %H", in, recOut, exceptionFlags);
if (formatWidth > 64) begin
$write("\n\t");
end else begin
$write(" ");
end
$display(
"expected %H %H", recExpectOut, expectExceptionFlags);
errorCount = errorCount + 1;
if (errorCount == maxNumErrors) disable TestLoop;
end
#1;
end
end
count = count + partialCount;
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
if (errorCount) begin
$fdisplay(
'h80000002,
"--> In %0d tests, %0d errors found.",
count,
errorCount
);
`finish_fail;
end else if (count == 0) begin
$fdisplay('h80000002, "--> Invalid test-cases input.");
`finish_fail;
end else begin
$display(
"In %0d tests, no errors found in 'i%0dToRecF%0d', control %H, signed %0d, rounding mode %0d.",
count,
intWidth,
formatWidth,
control,
signedIn,
roundingMode
);
end
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
$finish;
end
endmodule
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module test_i32ToRecF16;
test_iNToRecFN#(32, 5, 11) test_i32ToRecF16();
endmodule
module test_i32ToRecF32;
test_iNToRecFN#(32, 8, 24) test_i32ToRecF32();
endmodule
module test_i32ToRecF64;
test_iNToRecFN#(32, 11, 53) test_i32ToRecF64();
endmodule
module test_i32ToRecF128;
test_iNToRecFN#(32, 15, 113) test_i32ToRecF128();
endmodule
module test_i64ToRecF16;
test_iNToRecFN#(64, 5, 11) test_i64ToRecF16();
endmodule
module test_i64ToRecF32;
test_iNToRecFN#(64, 8, 24) test_i64ToRecF32();
endmodule
module test_i64ToRecF64;
test_iNToRecFN#(64, 11, 53) test_i64ToRecF64();
endmodule
module test_i64ToRecF128;
test_iNToRecFN#(64, 15, 113) test_i64ToRecF128();
endmodule
|
#include <bits/stdc++.h> using namespace std; char s[505][505]; int main() { int n, m; cin >> n >> m; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { scanf( %c , &s[i][j]); } } bool ok = 1; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { if (s[i][j] == W ) { if (s[i + 1][j] == . ) s[i + 1][j] = D ; else if (s[i + 1][j] == S ) ok = 0; if (s[i - 1][j] == . ) s[i - 1][j] = D ; else if (s[i - 1][j] == S ) ok = 0; if (s[i][j + 1] == . ) s[i][j + 1] = D ; else if (s[i][j + 1] == S ) ok = 0; if (s[i][j - 1] == . ) s[i][j - 1] = D ; else if (s[i][j - 1] == S ) ok = 0; if (!ok) { cout << No << endl; return 0; } } } } cout << Yes << endl; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { printf( %c , s[i][j]); } printf( n ); } } |
#include <bits/stdc++.h> using namespace std; const int N = 405; char mp[30], s[N], a[5], b[5]; int L, n, m, e[N][N], nxd[30], nxs[30], flg[30], lim[N], tmp[N], mx[2]; vector<int> ans; bool chk(int pos, int v, int x, bool ff) { if (lim[pos] != -1 && lim[pos] != flg[v]) return 0; for (int i = 1; i <= n; i++) if (e[x][i] && e[x][i + n]) return 0; for (int i = 1; i <= n; i++) tmp[i] = (e[x][i] ? 0 : (e[x][i + n] ? 1 : -1)); if (ff) { for (int i = 1; i <= n; i++) { if (pos + i > n) break; int t = max(lim[pos + i], tmp[pos + i]); if (t == -1) break; if (mx[t] < s[pos + i] - a + 1) return 0; if (mx[t] > s[pos + i] - a + 1) break; } } for (int i = 1; i <= n; i++) { lim[i] = max(lim[i], tmp[i]); } return 1; } int main() { scanf( %s , mp + 1); L = strlen(mp + 1); memset(lim, -1, sizeof(lim)); memset(mx, -1, sizeof(mx)); for (int i = 1; i <= L; i++) { flg[i] = mp[i] == V ; mx[flg[i]] = i; } for (int i = 1; i <= L; i++) for (int j = i + 1; j <= L; j++) if (flg[i] != flg[j]) { nxd[i] = j; break; } for (int i = 1; i <= L; i++) for (int j = i + 1; j <= L; j++) if (flg[i] == flg[j]) { nxs[i] = j; break; } cin >> n >> m; for (int i = 1; i <= m; i++) { int x, y; scanf( %d%s%d%s , &x, a, &y, b); int a1 = a[0] == V , b1 = b[0] == V ; e[x + a1 * n][y + b1 * n] = 1; e[y + !b1 * n][x + !a1 * n] = 1; } scanf( %s , s + 1); for (int k = 1; k <= n * 2; k++) for (int i = 1; i <= n * 2; i++) for (int j = 1; j <= n * 2; j++) e[i][j] |= (e[i][k] & e[k][j]); bool ff = 1; for (int i = 1; i <= n; i++) { int mn = ff ? s[i] - a + 1 : 1; if (chk(i, mn, i + flg[mn] * n, ff)) { ans.push_back(mn); } else if (mn < L && flg[mn] == flg[mn + 1] && chk(i, mn + 1, i + flg[mn + 1] * n, 0)) { ans.push_back(mn + 1), ff = 0; } else if (nxd[mn] && chk(i, nxd[mn], i + flg[nxd[mn]] * n, 0)) { ans.push_back(nxd[mn]), ff = 0; } else if (nxs[mn] && nxs[mn] > nxd[mn] && chk(i, nxs[mn], i + flg[nxs[mn]] * n, 0)) { ans.push_back(nxs[mn]), ff = 0; } else { return puts( -1 ), 0; } } for (int i = 0; i <= n - 1; i++) printf( %c , ans[i] + a - 1); puts( ); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:22:18 05/13/2015
// Design Name:
// Module Name: MemoryManagerUnit
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MemoryManagerUnit(
input clk, //very slow clock
input clk_50M,
input[14:0] MemAddr,
input MemWrite,
input MemRead,
input SaveHalf,
input LoadHalf,
input[31:0] MemWriteData,
input ChipSelect,
output[31:0] MemReadData,
output reg MemOK,
output hsync, //ÐÐͬ²½ÐźÅ
output vsync, //³¡Í¬²½ÐźÅ
output vga_r,
output vga_g,
output vga_b
);
/*
reg clk;
reg clk_50M;
initial begin
clk = 0;
clk_50M = 0;
end
always#10 begin
clk_50M = ~clk_50M;
end
always#10 begin
clk = ~clk;
end
*/
parameter width = 40;
parameter height = 25;
parameter screenBase = 14'h3000;
initial begin
MemOK <= 0;
end
always @(posedge clk) begin
MemOK <= (MemRead | MemWrite) & ChipSelect;
end
wire[14:0] ZBadr;
wire[15:0] outB;
Memory Mem (
.clk(clk_50M),
.adrA(MemAddr),
.adrB(ZBadr),
.we(MemWrite&ChipSelect),
.data(MemWriteData),
.sh(SaveHalf),
.lh(LoadHalf),
.outA(MemReadData),
.outB(outB)
);
reg[15:0] ZBcode;
wire [9:0] xpos,ypos;
wire valid;
vga_dis vga (
.clk(clk_50M), //input
.rst_n(1'b1),
.ZBcode(ZBcode),
.valid(valid), //output
.xpos(xpos[9:0]),
.ypos(ypos[9:0]),
.hsync(hsync),
.vsync(vsync),
.vga_r(vga_r),
.vga_g(vga_g),
.vga_b(vga_b)
);
wire[14:0] offset;
assign ZBadr = screenBase+offset;
wire[14:0] lineBase;
assign lineBase = ypos[9:4]*width;
assign offset =(xpos[9:4]== width-1)?(
(ypos[3:0]==4'hf)?(
(ypos[9:4]==height-1)? 10'd0 : (lineBase + xpos[9:4] +1)
) : lineBase
) : (lineBase + xpos[9:4] + 1);
always @(posedge clk_50M) begin
if(xpos[3:0] == 4'he && valid) begin
ZBcode <= outB;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 150, M = 150, OO = 0x3f3f3f3f; int n, arr[2005], temp, ans; void DFS(int u) { temp++; if (arr[u] == -1) return; DFS(arr[u]); } int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %d , arr + i); } for (int i = 1; i <= n; ++i) { temp = 0; DFS(i); ans = max(ans, temp); } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; void solve() { long long int n, x; cin >> n >> x; long long int a[n]; set<long long int> s; long long int sum = 0; for (long long int i = 0; i < n; i++) { cin >> a[i]; s.insert(a[i]); sum += a[i]; } long long int y = *(s.begin()); if (s.size() == 1 && y == x) { cout << 0 << n ; return; } if (s.find(x) != s.end()) { cout << 1 << n ; return; } if (sum == n * x) { cout << 1 << n ; return; } cout << 2 << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; cout.precision(20); long long int t = 1; cin >> t; for (long long int i = 1; i <= t; i++) { if (0) cout << Case # << i << : ; solve(); } } |
#include <bits/stdc++.h> using namespace std; const int N = (1 << 18); const double PI = acos(-1.0); char s[N]; int lA, lB; int a[N], b[N]; int inB[110][N]; int S, B; struct cpx { double x, y; cpx(double p = 0, double q = 0) : x(p), y(q) {} cpx operator+(cpx &o) { return cpx(x + o.x, y + o.y); } cpx operator-(cpx &o) { return cpx(x - o.x, y - o.y); } cpx operator*(cpx &o) { return cpx(x * o.x - y * o.y, x * o.y + y * o.x); } } u[N], v[N]; void fft(cpx *a, int n, int f) { int i, j, k; for (i = j = 0; i < n; ++i) { if (i > j) swap(a[i], a[j]); for (k = n >> 1; (j ^= k) < k; k >>= 1) ; } for (i = 1; i < n; i <<= 1) { cpx wn(cos(PI / i), f * sin(PI / i)); for (j = 0; j < n; j += i << 1) { cpx w(1, 0); for (k = 0; k < i; ++k, w = w * wn) { cpx x = a[j + k], y = w * a[i + j + k]; a[j + k] = x + y; a[i + j + k] = x - y; } } } if (f == -1) for (i = 0; i < n; ++i) a[i].x /= n, a[i].y /= n; } void work(int *a, int A, int id) { int n = 1; while (n <= A + lB) n <<= 1; for (int i = 0; i < A; ++i) u[i] = cpx(a[i], 0); for (int i = A; i < n; ++i) u[i] = cpx(0, 0); for (int i = 0; i < A - 1 - i; ++i) swap(u[i], u[A - 1 - i]); for (int i = 0; i < lB; ++i) v[i] = cpx(b[i], 0); for (int i = lB; i < n; ++i) v[i] = cpx(0, 0); fft(u, n, 1), fft(v, n, 1); for (int i = 0; i < n; ++i) u[i] = u[i] * v[i]; fft(u, n, -1); for (int i = 0; i < lB; ++i) inB[id][i] = (A - round(u[i].x)) / 2; } int main() { scanf( %s , s); lA = strlen(s); for (int i = 0; i < lA; ++i) a[i] = (s[i] == 1 ? 1 : -1); scanf( %s , s); lB = strlen(s); for (int i = 0; i < lB; ++i) b[i] = (s[i] == 1 ? 1 : -1); S = sqrt(lA * log2(lA)); B = ceil(1. * lA / S); for (int i = 0; i < B; ++i) { int l = i * S, r = min(lA, l + S); work(a + l, r - l, i); } int q; scanf( %d , &q); while (q--) { int l, r, len, res = 0; scanf( %d %d %d , &l, &r, &len); int p = l / S, q = (l + len - 1) / S; if (p == q) { for (int i = l; i < l + len; ++i) res += (a[i] != b[i - l + r]); } else { for (int i = l; i < (p + 1) * S; ++i) res += (a[i] != b[i - l + r]); for (int i = p + 1; i < q; ++i) res += (inB[i][(i + 1) * S - 1 - l + r]); for (int i = q * S; i < l + len; ++i) res += (a[i] != b[i - l + r]); } printf( %d n , res); } } |
#include <bits/stdc++.h> using namespace std; int tab[205]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { int n; cin >> n; vector<int> V; for (int i = 0; i < n; i++) { int x; cin >> x; tab[x] = 1; V.push_back(x); } vector<int> V2; bool b = 1; for (int i : V) { b = 0; for (int j = i + 1; j <= 2 * n; j++) { if (tab[j] == 0) { tab[j] = 1; b = 1; V2.push_back(j); break; } } if (!b) { break; } } if (!b) { cout << -1 n ; } else { for (int i = 0; i < n; i++) { cout << min(V[i], V2[i]) << << max(V[i], V2[i]) << ; } cout << n ; } for (int i = 0; i <= 2 * n; i++) { tab[i] = 0; } } } |
#include <bits/stdc++.h> #define int long long int const int INF = 1e9 + 7; using namespace std; const int m = 1e9 + 7; signed main() { ios_base::sync_with_stdio(false); cin.tie(0); int t; cin >> t; while (t--) { int n; cin >> n; string a[n], b[n]; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) cin >> b[i]; for (int j = 0; j < n; j++) { if (a[0][j] != b[0][j]) { for (int i = 0; i < n; i++) { a[i][j] ^= 1; } } } for (int i = 1; i < n; i++) { for (int j = 1; j < n; j++) { if (a[i][j] != b[i][j]) { for (int j = 0; j < n; j++) a[i][j] ^= 1; } } } bool ans = true; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) if (a[i][j] != b[i][j]) { ans = false; break; } if (ans == false) break; } if (ans) cout << YES n ; else cout << NO n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 1005; int numb[MAXN], numw[MAXN]; int dp[MAXN][2]; string s[MAXN]; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); for (int i = 0; i < MAXN; i++) dp[i][0] = dp[i][1] = -1; int n, m, x, y; cin >> n >> m >> x >> y; for (int i = 0; i < n; i++) cin >> s[i]; for (int t = 0; t < m; t++) { int num = 0; for (int i = 0; i < n; i++) if (s[i][t] == # ) num++; numb[t] = num; numw[t] = n - num; } for (int t = 1; t < m; t++) numb[t] += numb[t - 1], numw[t] += numw[t - 1]; for (int t = x - 1; t < m; t++) { for (int j = x; j <= y && t - j + 1 >= 0; j++) { if (t - j + 1 == 0) { if (dp[t][0] == -1) dp[t][0] = 1e9; if (dp[t][1] == -1) dp[t][1] = 1e9; dp[t][0] = min(dp[t][0], numb[t]); dp[t][1] = min(dp[t][1], numw[t]); continue; } if (dp[t - j][0] != -1) { if (dp[t][1] == -1) dp[t][1] = 1e9; dp[t][1] = min(dp[t][1], dp[t - j][0] + (numw[t] - numw[t - j])); } if (dp[t - j][1] != -1) { if (dp[t][0] == -1) dp[t][0] = 1e9; dp[t][0] = min(dp[t][0], dp[t - j][1] + (numb[t] - numb[t - j])); } } } cout << min(dp[m - 1][0], dp[m - 1][1]) << n ; } |
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const int N = 200500; void solve() { long long n, k; cin >> n >> k; if ((n + k) % 2 == 0 && n >= k && (n + k) / 2 >= (k * (k + 1)) / 2) { cout << YES n ; } else cout << NO n ; } int main() { ios::sync_with_stdio(false); int q = 1; cin >> q; for (int i = 1; i <= q; i++) { solve(); } } |
#include <bits/stdc++.h> using namespace std; int n, V[171]; void cauta(int p) { vector<pair<int, int> > Queries; int res, st = 2, dr = n; for (int m = dr; m >= st; --m) { cout << ? ; for (int i = 1; i <= n; ++i) { if (i != p) cout << 1 ; else cout << n - m + 2 << ; } cout << n ; cout.flush(); cin >> res; if (res == 0) { V[p] = m; } else { if (V[res]) { V[p] = V[res] - 1 + m - n; } else if (res != p) Queries.push_back({res, n - m + 1}); } } if (!V[p]) V[p] = 1; for (auto it : Queries) V[it.first] = it.second + V[p]; } int gaseste(int dif) { cout << ? ; for (int i = 1; i < n; ++i) { if (dif > 0) cout << 1 ; else cout << -dif + 1 << ; } if (dif > 0) cout << dif + 1 << n ; else cout << 1 n ; cout.flush(); int rep = 0; cin >> rep; return rep; } void solve() { cin >> n; int v, st = 0, dr = 0; for (int i = -n + 1; i < n; ++i) { if (!i) continue; v = gaseste(i); V[v] = i; if (!v) { if (i > 0 && !dr) dr = i; } if (v && i < 0 && !st) st = -i; } V[n] = st + 1; for (int i = 1; i < n; ++i) V[i] += V[n]; cout << ! ; for (int i = 1; i <= n; ++i) { cout << V[i] << ; V[i] = 0; } cout << n ; cout.flush(); } int main() { cin.tie(0); ios_base::sync_with_stdio(0); int te = 1; while (te--) solve(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A21OI_1_V
`define SKY130_FD_SC_HS__A21OI_1_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog wrapper for a21oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a21oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a21oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a21oi_1 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A21OI_1_V
|
#include <bits/stdc++.h> using namespace std; const int N = 500, INF = 1 << 30; int nxt[N], a[N][N], n, x, Rank[N][N], now; char s[10]; queue<int> q; void init() { scanf( %d , &n); for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) scanf( %d , &a[i][j]); puts( B ); fflush(stdout); scanf( %s , s); if (s[0] == I ) { for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) a[i][j] = -a[i][j]; } scanf( %d , &x); if (x > n) for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) a[i][j] = -a[i][j]; } bool cmp(int x, int y) { return a[now][x - n] > a[now][y - n]; } void prework() { for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) Rank[i][j] = j + n; now = i; sort(Rank[i] + 1, Rank[i] + 1 + n, cmp); q.push(i); } for (int i = 1; i <= n; i++) a[0][i] = a[i][0] = INF; for (int i = 1; i <= n; i++) nxt[i] = nxt[i + n] = Rank[i][0] = 0; while (!q.empty()) { int x = q.front(); q.pop(); if (x == 0) continue; while (nxt[x] == 0) { int girl = Rank[x][++*Rank[x]]; if (a[x][girl - n] < a[nxt[girl]][girl - n]) nxt[nxt[girl]] = 0, q.push(nxt[girl]), nxt[girl] = x, nxt[x] = girl; } } } void work() { prework(); for (int i = 1;; i++) { if (x == -1 || x == -2) return; printf( %d n , nxt[x]); fflush(stdout); scanf( %d , &x); } } int main() { int T; scanf( %d , &T); while (T--) { init(); work(); } return 0; } |
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build Thu Jun 14 20:03:12 MDT 2018
// Date : Tue Sep 17 15:50:55 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ gcd_block_design_auto_pc_0_stub.v
// Design : gcd_block_design_auto_pc_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_17_axi_protocol_converter,Vivado 2018.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awprot, m_axi_awvalid,
m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready, m_axi_bresp,
m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, m_axi_arvalid, m_axi_arready,
m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [3:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [3:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [31:0]m_axi_awaddr;
output [2:0]m_axi_awprot;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [31:0]m_axi_araddr;
output [2:0]m_axi_arprot;
output m_axi_arvalid;
input m_axi_arready;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
#include <bits/stdc++.h> int a[1000005]; double tt; int main() { int n, i, t; double vb, vs, x, y, d; while (scanf( %d %lf %lf , &n, &vb, &vs) != EOF) { t = 2; for (i = 1; i <= n; i++) { scanf( %d , &a[i]); } scanf( %lf %lf , &x, &y); d = a[2] / vb + sqrt((x - a[2]) * (x - a[2]) + y * y) / vs; for (i = 2; i <= n; i++) { tt = a[i] / vb + sqrt((x - a[i]) * (x - a[i]) + y * y) / vs; if (tt <= d) { d = tt; t = i; } } printf( %d n , t); } return 0; } |
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0); const double eps = 1e-8; const int inf = 0x7FFFFFFF; template <class T> void show(T a, int n) { for (int i = 0; i < n; ++i) cout << a[i] << ; cout << endl; } template <class T> void show(T a, int r, int l) { for (int i = 0; i < r; ++i) show(a[i], l); cout << endl; } int k[7]; int main() { int i, j, ans; int a, b, c, x, y, z; cin >> a >> b >> c >> x >> y >> z; for (i = 0; i < 6; i++) cin >> k[i]; ans = 0; if (a > x) { ans += k[5]; } else if (a < 0) ans += k[4]; if (b > y) ans += k[1]; else if (b < 0) ans += k[0]; if (c > z) ans += k[3]; else if (c < 0) ans += k[2]; cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; signed main() { std ::ios_base ::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long n; cin >> n; string s; cin >> s; long long a[2] = {0}; for (long long i = 0; i < n; i++) a[s[i] - 48]++; if (a[0] == a[1]) { cout << 2 n << s[0] << ; for (long long i = 1; i < n; i++) cout << s[i]; } else { cout << 1 n << s; } } |
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