text stringlengths 59 71.4k |
|---|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__BUFBUF_BLACKBOX_V
`define SKY130_FD_SC_LS__BUFBUF_BLACKBOX_V
/**
* bufbuf: Double buffer.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__bufbuf (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__BUFBUF_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /STACK:200000000 ) const double EPS = 1E-9; const int INF = 1000000000; const long long INF64 = (long long)1E18; const double PI = 3.1415926535897932384626433832795; char s[2100][2100]; int ans[2100]; int main() { int n, m, k; scanf( %d%d%d n , &n, &m, &k); for (int i = 0; i < (int)(n); i++) gets(s[i]); for (int i = 0; i < (int)(n); i++) for (int j = 0; j < (int)(m); j++) { if (s[i][j] == . || s[i][j] == D ) continue; if (s[i][j] == U ) { if (i % 2 == 1) continue; ans[j]++; continue; } int nj; if (s[i][j] == L ) nj = j - i; else nj = j + i; if (0 <= nj && nj < m) ans[nj]++; } for (int i = 0; i < (int)(m); i++) printf(i ? %d : %d , ans[i]); puts( ); return 0; } |
#include <bits/stdc++.h> long long mod = 1e9 + 7, mod2 = 998244353; using namespace std; long long fac[10000000]; long long gcd(long long x, long long y) { if (y == 0) return x; return gcd(y, x % y); } long long fexp(long long a, long long b, long long m) { long long ans = 1; while (b) { if (b & 1) ans = ans * a % m; b /= 2; a = a * a % m; } return ans; } long long inverse(long long a, long long p) { return fexp(a, p - 2, p); } long long ncr(long long n, long long r, long long p) { if (r == 0) return 1; return (fac[n] * inverse(fac[n - r], p) % p * inverse(fac[r], p) % p) % p; } vector<long long> za(string s) { long long n = s.size(); vector<long long> z(n); long long x = 0, y = 0, p = 0; for (long long i = 1; i < n; i++) { z[i] = max(p, min(z[i - x], y - i + 1)); while (i + z[i] < n && s[z[i]] == s[i + z[i]]) { x = i; y = i + z[i]; z[i]++; } } return z; } void subset(long long a[], long long k) { for (int i = 1; i < pow(2, k); i++) { for (int j = 0; j < k; j++) { if (i & 1 << j) { cout << a[j] << ; } } cout << n ; ; } } vector<long long> pr(string s) { long long n = s.length(); vector<long long> pi(n); for (int i = 1; i < n; i++) { int j = pi[i - 1]; while (j > 0 && s[i] != s[j]) j = pi[j - 1]; if (s[i] == s[j]) j++; pi[i] = j; } return pi; } long long d[100005]; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long n, s, l, r, x = 0; cin >> n >> s; for (long long i = 1; i < n; i++) { cin >> l >> r; d[l]++; d[r]++; } for (long long i = 1; i <= n; i++) { if (d[i] == 1) x++; } cout << fixed << setprecision(50) << ((2 * s) / (1.0 * x)); } |
#include <bits/stdc++.h> using namespace std; vector<pair<long long int, long long int> > dis(100005), edge; long long int cnt[100005]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int t = 0, n, e, x, y, z, i, j, k, g, q, ans = 0, sum = 0, c = 0, h; cin >> n >> t; for (i = 1; i <= n; i++) { cin >> x; dis[i].first = x; dis[i].second = i; } sort(dis.begin() + 1, dis.begin() + n + 1); if (dis[1].first != 0) { cout << -1 n ; return 0; } if (n == 1) { cout << 0 n ; return 0; } if (dis[1].first == dis[2].first) { cout << -1 n ; return 0; } vector<long long int> v1, v2; v1.push_back(dis[1].second); i = 2; long long int next = 1; while (i <= n) { for (j = i; j <= n; j++) { if (dis[j].first != next) break; v2.push_back(dis[j].second); } i = j; long long int s1 = v1.size(); long long int s2 = v2.size(); for (j = 0, k = 0; j < s2 && k < s1;) { if (cnt[v1[k]] == t) { k++; continue; } edge.push_back(make_pair(v1[k], v2[j])); cnt[v1[k]]++; cnt[v2[j]]++; if (cnt[v1[k]] == t) k++; j++; } if (j != s2) { cout << -1 n ; return 0; } v1.clear(); next++; for (j = 0; j < s2; j++) { v1.push_back(v2[j]); } v2.clear(); } ans = edge.size(); cout << ans << n ; for (i = 0; i < edge.size(); i++) { cout << edge[i].first << << edge[i].second << n ; } return 0; } |
#include <bits/stdc++.h> #define ll long long using namespace std; int main() { int t; cin>>t; int arra[10] = { 0, 3, 17, 151, 1117, 11941, 117653, 1219837, 12176537, 132176537 }; int arrb[10] = {0, 7, 23, 191, 1181, 12071, 129837, 1329837, 13298373, 143298373 }; while(t--) { int a, b, c, x=0, y=0, z = 0; cin>>a>>b>>c; if(a==c || b == c) { x = pow(10, a- 1); y = pow(10, b- 1); } else { z = arra[c]; x = z * arra[a- c+ 1]; y = z * arrb[b- c+ 1]; } cout<<x<< <<y<<endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR2_4_V
`define SKY130_FD_SC_HD__NOR2_4_V
/**
* nor2: 2-input NOR.
*
* Verilog wrapper for nor2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor2_4 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor2_4 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR2_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O22AI_SYMBOL_V
`define SKY130_FD_SC_HVL__O22AI_SYMBOL_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__o22ai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O22AI_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09/14/2014 05:34:33 PM
// Design Name:
// Module Name: delta_sigma
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module delta_sigma(
input [15:0] din,
input clk_i,
output reg dout
);
// PWM module to take in PWM data and play it out on a one line speaker
// mainly taken from:
// http://www.fpga4fun.com/PWM_DAC.html
// sigma delta PWM
reg [16:0] PWM_accumulator;
always @(posedge clk_i) begin
PWM_accumulator[16:0] = PWM_accumulator[15:0] + {~din[15], din[14:0]}; // plus sigma
dout = PWM_accumulator[16];
//PWM_accumulator[16] = 0; // delta : subtract 256
end
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2013.4
// Copyright (C) 2013 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4_MulnS_0(clk, ce, a, b, p);
input clk;
input ce;
input[16 - 1 : 0] a; // synthesis attribute keep a "true"
input[8 - 1 : 0] b; // synthesis attribute keep b "true"
output[24 - 1 : 0] p;
reg[16 - 1 : 0] a_reg;
reg[8 - 1 : 0] b_reg;
wire [24 - 1 : 0] tmp_product;
reg[24 - 1 : 0] buff0;
reg[24 - 1 : 0] buff1;
assign p = buff1;
assign tmp_product = a_reg * b_reg;
always @ (posedge clk) begin
if (ce) begin
a_reg <= a;
b_reg <= b;
buff0 <= tmp_product;
buff1 <= buff0;
end
end
endmodule
`timescale 1 ns / 1 ps
module nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4_MulnS_0 nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4_MulnS_0_U(
.clk( clk ),
.ce( ce ),
.a( din0 ),
.b( din1 ),
.p( dout ));
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
`include "verilated.v"
`define STRINGIFY(x) `"x`"
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [63:0] crc;
integer fd;
integer fdtmp;
t_case_write1_tasks tasks ();
integer cyc; initial cyc=0;
always @ (posedge clk) begin
$fwrite(fd, "[%0d] crc=%x ", cyc, crc);
tasks.big_case(fd, crc[31:0]);
$fwrite(fd, "\n");
end
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%x\n",$time, cyc, crc);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc==1) begin
crc <= 64'h00000000_00000097;
$write("%s", {"Open ", `STRINGIFY(`TEST_OBJ_DIR), "/t_case_write1_logger.log\n"});
fdtmp = $fopen({`STRINGIFY(`TEST_OBJ_DIR), "/t_case_write1_logger.log"}, "w");
fd <= fdtmp;
end
if (cyc==90) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void snum(long long &x) { scanf( %lld , &x); } void snum(long long &x, long long &y) { scanf( %lld %lld , &x, &y); } void snum(long long &x, long long &y, long long &z) { scanf( %lld %lld %lld , &x, &y, &z); } vector<long long> adj[100100]; long long outDegree[100100]; long long out[100100]; bool vis[100100]; void dfs(long long u) { vis[u] = true; long long aux = 0; for (long long i = 0; i < adj[u].size(); i++) { long long v = adj[u][i]; if (!vis[v]) { aux++; dfs(v); } } out[u] = outDegree[u] = aux; } long long n; long long cant[100100]; long long need[100100]; void bfs() { deque<long long> q; for (long long i = 0; i < n; i++) { if (outDegree[i] == 0) { q.push_back(i); cant[i]++; } } while (!q.empty()) { long long u = q.front(); q.pop_front(); for (long long i = 0; i < adj[u].size(); i++) { long long v = adj[u][i]; outDegree[v]--; if (outDegree[v] >= 0) { cant[v] += cant[u]; } if (outDegree[v] == 0) { q.push_back(v); } } } } void doit() { snum(n); for (long long i = 0; i < n - 1; i++) { long long x; snum(x); x--; adj[i + 1].push_back(x); adj[x].push_back(i + 1); } dfs(0); bfs(); for (long long i = 0; i < n; i++) { need[cant[i]]++; } for (long long i = 1; i <= n; i++) { long long x = need[i]; for (long long j = 0; j < x; j++) { printf( %lld , i); } } } int main() { long long T = 1; while (T--) { doit(); } return 0; } |
/****************************************
MIST1032SA
OoO Processor
for Open Design Computer Project
Takahiro Ito @cpu_labs
****************************************/
`include "core.h"
`default_nettype none
module execute_port0(
//System
input wire iCLOCK,
input wire inRESET,
//Free
input wire iFREE_RESTART,
//Previous
input wire iPREVIOUS_EX_BRANCH_VALID,
input wire [5:0] iPREVIOUS_EX_BRANCH_COMMIT_TAG,
input wire [4:0] iPREVIOUS_EX_BRANCH_CMD,
input wire [3:0] iPREVIOUS_EX_BRANCH_CC,
input wire [4:0] iPREVIOUS_EX_BRANCH_FLAG,
input wire [31:0] iPREVIOUS_EX_BRANCH_SOURCE,
input wire [31:0] iPREVIOUS_EX_BRANCH_PC,
output wire oPREVIOUS_EX_BRANCH_LOCK,
//Jump
output wire oJUMP_ACTIVE,
output wire [31:0] oJUMP_ADDR,
//SWI
output wire oSWI_ACTIVE,
output wire [10:0] oSWI_NUMBER,
//Interrupt Return
output wire oINTR_ACTIVE,
output wire [31:0] oINTR_ADDR,
//IDTS
output wire oIDTS_ACTIVE,
output wire [31:0] oIDTS_R_ADDR,
output wire [5:0] oIDTR_COMMIT_TAG,
//NEXTUNIT - SCHEDULER1
output wire oSCHE1_EX_BRANCH_VALID,
output wire [5:0] oSCHE1_EX_BRANCH_COMMIT_TAG,
//Scheduler2
output wire oSCHE2_EX_BRANCH_VALID,
output wire [5:0] oSCHE2_EX_BRANCH_COMMIT_TAG
);
wire iRESET_SYNC = 1'b0;
wire [31:0] branch_addr;
wire jump_valid;
wire not_jump_valid;
wire ib_valid;
wire idts_valid;
wire halt_valid;
execute_branch EXECUTE_BRANCH(
.iDATA_0(32'h0), //non use
.iDATA_1(iPREVIOUS_EX_BRANCH_SOURCE),
.iPC(iPREVIOUS_EX_BRANCH_PC - 32'h00000004),
.iFLAG(iPREVIOUS_EX_BRANCH_FLAG),
.iCC(iPREVIOUS_EX_BRANCH_CC),
.iCMD(iPREVIOUS_EX_BRANCH_CMD),
.oBRANCH_ADDR(branch_addr),
.oJUMP_VALID(jump_valid),
.oNOT_JUMP_VALID(not_jump_valid),
.oIB_VALID(ib_valid),
.oIDTS_VALID(idts_valid),
.oHALT_VALID(halt_valid)
);
reg b_busy;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_busy <= 1'b0;
end
else if(iRESET_SYNC || iFREE_RESTART)begin
b_busy <= 1'b0;
end
else begin
if(!b_busy)begin
b_busy <= iPREVIOUS_EX_BRANCH_VALID && (jump_valid || ib_valid || idts_valid || halt_valid);
end
end
end
reg b_stage_valid;
reg [31:0] b_branch_addr;
reg b_jump_valid;
reg b_not_jump_valid;
reg b_ib_valid;
reg b_idts_valid;
reg b_halt_valid;
reg [5:0] b_commit_tag;
reg [31:0] b_pcr;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_stage_valid <= 1'b0;
b_branch_addr <= 32'h0;
b_jump_valid <= 1'b0;
b_not_jump_valid <= 1'b0;
b_ib_valid <= 1'b0;
b_idts_valid <= 1'b0;
b_halt_valid <= 1'b0;
b_commit_tag <= 6'h0;
b_pcr <= 32'h0;
end
else if(iRESET_SYNC || iFREE_RESTART)begin
b_stage_valid <= 1'b0;
b_branch_addr <= 32'h0;
b_jump_valid <= 1'b0;
b_not_jump_valid <= 1'b0;
b_ib_valid <= 1'b0;
b_idts_valid <= 1'b0;
b_halt_valid <= 1'b0;
b_commit_tag <= 6'h0;
b_pcr <= 32'h0;
end
else begin
b_stage_valid <= !b_busy && iPREVIOUS_EX_BRANCH_VALID;
b_branch_addr <= branch_addr;
b_jump_valid <= jump_valid;
b_not_jump_valid <= not_jump_valid;
b_ib_valid <= ib_valid;
b_idts_valid <= idts_valid;
b_halt_valid <= halt_valid;
b_commit_tag <= iPREVIOUS_EX_BRANCH_COMMIT_TAG;
b_pcr <= iPREVIOUS_EX_BRANCH_PC;
end
end
//Output Assign
assign oPREVIOUS_EX_BRANCH_LOCK = b_busy;
assign oJUMP_ACTIVE = b_stage_valid && b_jump_valid && !b_idts_valid && !b_ib_valid && !b_halt_valid;
assign oJUMP_ADDR = b_branch_addr;
assign oINTR_ACTIVE = b_ib_valid;
assign oINTR_ADDR = b_branch_addr;
assign oIDTS_ACTIVE = b_idts_valid;
assign oIDTS_R_ADDR = b_branch_addr;
assign oIDTR_COMMIT_TAG = b_commit_tag;
assign oSWI_ACTIVE = b_halt_valid;
assign oSWI_NUMBER = iPREVIOUS_EX_BRANCH_SOURCE[9:0];
assign oSCHE1_EX_BRANCH_VALID = b_stage_valid;
assign oSCHE1_EX_BRANCH_COMMIT_TAG = b_commit_tag;
assign oSCHE2_EX_BRANCH_VALID = b_stage_valid;
assign oSCHE2_EX_BRANCH_COMMIT_TAG = b_commit_tag;
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; const int N = 80, Inf = 0x3f3f3f3f; int n, f[N][N][N][2]; int pos[3][N], num[3][N]; char s[N]; inline int getid(char ch) { if (ch == V ) return 0; if (ch == K ) return 1; return 2; } inline int move(int i, int j, int k, int id) { return max(0, num[0][id] - i) + max(0, num[1][id] - j) + max(0, num[2][id] - k) - 1; } int main() { ios::sync_with_stdio(false); cin >> n >> s + 1; for (int i = 1; i <= n; ++i) { int now = getid(s[i]); for (int j = 0; j < 3; ++j) num[j][i] = num[j][i - 1]; pos[now][++num[now][i]] = i; } memset(f, 0x3f, sizeof f); f[0][0][0][0] = 0; for (int i = 0; i <= num[0][n]; ++i) for (int j = 0; j <= num[1][n]; ++j) for (int k = 0; k <= num[2][n]; ++k) for (int fl = 0; fl < 2; ++fl) { if (i < num[0][n]) f[i + 1][j][k][1] = min(f[i + 1][j][k][1], f[i][j][k][fl] + move(i, j, k, pos[0][i + 1])); if (j < num[1][n] && !fl) f[i][j + 1][k][0] = min(f[i][j + 1][k][0], f[i][j][k][fl] + move(i, j, k, pos[1][j + 1])); if (k < num[2][n]) f[i][j][k + 1][0] = min(f[i][j][k + 1][0], f[i][j][k][fl] + move(i, j, k, pos[2][k + 1])); } cout << min(f[num[0][n]][num[1][n]][num[2][n]][0], f[num[0][n]][num[1][n]][num[2][n]][1]) << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int pos[1 << 12], num[1 << 12]; int p[1 << 12], q[1 << 12]; void maintain(int x, int y) { for (;;) { int t = pos[q[x] ^ num[x]]; if (t == x) return; else if (t == y) { swap(p[x], p[y]); swap(pos[p[x]], pos[p[y]]); return; } swap(q[y], q[t]); swap(p[x], p[y]); swap(pos[p[x]], pos[p[y]]); swap(p[x], p[t]); swap(pos[p[x]], pos[p[t]]); x = t; } } int fir[1 << 12]; int main() { int n; scanf( %d , &n); int s = 0; for (int i = 0; i < (1 << n); i++) { scanf( %d , &fir[i]); s ^= fir[i]; } if (s) { puts( Fou ); return 0; } for (int i = 0; i < (1 << n); i++) p[i] = q[i] = pos[i] = i; for (int i = 0; i < (1 << n) - 1; i++) { num[i + 1] ^= (num[i] ^ fir[i]); num[i] = fir[i]; maintain(i, i + 1); } puts( Shi ); for (int i = 0; i < (1 << n); i++) printf( %d , p[i]); printf( n ); for (int i = 0; i < (1 << n); i++) printf( %d , q[i]); printf( n ); return 0; } |
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_frame_length_adjust
*/
module test_axis_frame_length_adjust_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
reg status_ready = 0;
reg [15:0] length_min = 0;
reg [15:0] length_max = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
wire status_valid;
wire status_frame_pad;
wire status_frame_truncate;
wire [15:0] status_frame_length;
wire [15:0] status_frame_original_length;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_axis_tdata,
s_axis_tkeep,
s_axis_tvalid,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tready,
status_ready,
length_min,
length_max
);
$to_myhdl(
s_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tvalid,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
status_valid,
status_frame_pad,
status_frame_truncate,
status_frame_length,
status_frame_original_length
);
// dump file
$dumpfile("test_axis_frame_length_adjust_64.lxt");
$dumpvars(0, test_axis_frame_length_adjust_64);
end
axis_frame_length_adjust #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Status
.status_valid(status_valid),
.status_ready(status_ready),
.status_frame_pad(status_frame_pad),
.status_frame_truncate(status_frame_truncate),
.status_frame_length(status_frame_length),
.status_frame_original_length(status_frame_original_length),
// Configuration
.length_min(length_min),
.length_max(length_max)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX = 1e6 + 10; int n, m, q, pos[MAX], bit[MAX], res[MAX], XOR[MAX]; pair<int, int> cache[MAX], a[MAX], b[MAX]; struct Node { int lef, rig, tt; bool operator<(const Node& other) const { return this->lef < other.lef; } }; Node query[MAX]; void up(int i) { int val = a[i].first; while (i <= n) { bit[i] ^= val; i += i & (-i); } } int get(int i) { int res = 0; while (i) { res ^= bit[i]; i -= i & (-i); } return res; } int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %d , &cache[i].first); a[i].first = cache[i].first; cache[i].second = i; } sort(cache + 1, cache + 1 + n); for (int i = 1; i <= n; ++i) { if (i == 1 || cache[i].first > cache[i - 1].first) ++m; a[cache[i].second].second = m; } for (int i = 1; i <= n; ++i) { b[i] = pair<int, int>(pos[a[i].second], i); pos[a[i].second] = i; XOR[i] = XOR[i - 1] ^ a[i].first; } sort(b + 1, b + 1 + n); scanf( %d , &q); for (int i = 1; i <= q; ++i) { scanf( %d %d , &query[i], &query[i].rig); query[i].tt = i; } sort(query + 1, query + 1 + q); int j = 1; for (int i = 1; i <= q; ++i) { while (j <= n && b[j].first < query[i].lef) up(b[j++].second); res[query[i].tt] = XOR[query[i].rig] ^ XOR[query[i].lef - 1]; res[query[i].tt] ^= get(query[i].rig) ^ get(query[i].lef - 1); } for (int i = 1; i <= q; ++i) printf( %d n , res[i]); return 0; } |
// author: xay5421 // created: Mon May 3 17:34:21 2021 #include<bits/stdc++.h> #define rep(i,a,b) for(int i=(a);i<=(b);++i) #define per(i,a,b) for(int i=(a);i>=(b);--i) using namespace std; typedef long long LL; const LL INFLL=0X3F3F3F3F3F3F3F3FLL; const int N=200005; int n,Q,_w[N],_v[N],id[N],_id[N]; LL _a[N],sw0[N*4][18],sv0[N*4][18],sw1[N*4][18]; void bud(int k1,int k2,int k3,int k4,int k5){ if(k2>k5||k3<k4)return; if(k2==k3){ rep(k,1,17){ if(_w[id[k2]]<(1<<k)){ sw0[k1][k]=_a[id[k2]]*_w[id[k2]]; sv0[k1][k]=_a[id[k2]]*_v[id[k2]]; } sw1[k1][k]=INFLL; if(_w[id[k2]]>=(1<<(k-1))&&_w[id[k2]]<(1<<k)&&_a[id[k2]]){ sw1[k1][k]=_w[id[k2]]; } } return; } int mid=(k2+k3)>>1; bud(k1*2,k2,mid,k4,k5),bud(k1*2+1,mid+1,k3,k4,k5); rep(k,1,17){ sw0[k1][k]=sw0[k1*2][k]+sw0[k1*2+1][k]; sv0[k1][k]=sv0[k1*2][k]+sv0[k1*2+1][k]; if(sw1[k1*2][k]<sw0[k1*2][k-1]+sw1[k1*2+1][k]){ sw1[k1][k]=sw1[k1*2][k]; }else{ sw1[k1][k]=sw0[k1*2][k-1]+sw1[k1*2+1][k]; } } } void add(int x,int y){ _a[x]+=y; bud(1,1,n,_id[x],_id[x]); } LL rem,vv; int _k; void clip(){ while(_k>0&&(1<<(_k-1))>rem)--_k; } void qry(int k1,int k2,int k3){ if(k2==k3){ LL tt=min(_a[id[k2]],rem/_w[id[k2]]); rem-=tt*_w[id[k2]]; vv+=tt*_v[id[k2]]; return; } int mid=(k2+k3)>>1; clip(); if(sw0[k1][_k]<=rem){ rem-=sw0[k1][_k]; vv+=sv0[k1][_k]; return; } if(sw1[k1][_k]>rem&&sw0[k1][_k-1]<=rem){ rem-=sw0[k1][_k-1]; vv+=sv0[k1][_k-1]; return; } qry(k1*2,k2,mid); clip(); qry(k1*2+1,mid+1,k3); } void sol(LL x){ _k=17,rem=x,vv=0; clip(); qry(1,1,n); printf( %lld n ,vv); } int main(){ #ifdef xay5421 freopen( a.in , r ,stdin); #endif scanf( %d%d ,&n,&Q); rep(i,1,n){ scanf( %lld%d%d ,&_a[i],&_w[i],&_v[i]); id[i]=i; } sort(id+1,id+1+n,[&](int x,int y){return _v[x]^_v[y]?_v[x]>_v[y]:_w[x]<_w[y];}); rep(i,1,n)_id[id[i]]=i; bud(1,1,n,1,n); while(Q--){ int t; scanf( %d ,&t); if(t==1){ int x,y; scanf( %d%d ,&x,&y); add(y,x); }else if(t==2){ int x,y; scanf( %d%d ,&x,&y); add(y,-x); }else{ LL x; scanf( %lld ,&x); sol(x); } } return 0; } |
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/13.1/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_handshake_clock_crosser.v $
// $Revision: #1 $
// $Date: 2013/08/11 $
// $Author: swbranch $
//------------------------------------------------------------------------------
// Clock crosser module with handshaking mechanism
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_handshake_clock_crosser
#(
parameter DATA_WIDTH = 8,
BITS_PER_SYMBOL = 8,
USE_PACKETS = 0,
// ------------------------------
// Optional signal widths
// ------------------------------
USE_CHANNEL = 0,
CHANNEL_WIDTH = 1,
USE_ERROR = 0,
ERROR_WIDTH = 1,
VALID_SYNC_DEPTH = 2,
READY_SYNC_DEPTH = 2,
USE_OUTPUT_PIPELINE = 1,
// ------------------------------
// Derived parameters
// ------------------------------
SYMBOLS_PER_BEAT = DATA_WIDTH / BITS_PER_SYMBOL,
EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
input in_clk,
input in_reset,
input out_clk,
input out_reset,
output in_ready,
input in_valid,
input [DATA_WIDTH - 1 : 0] in_data,
input [CHANNEL_WIDTH - 1 : 0] in_channel,
input [ERROR_WIDTH - 1 : 0] in_error,
input in_startofpacket,
input in_endofpacket,
input [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] in_empty,
input out_ready,
output out_valid,
output [DATA_WIDTH - 1 : 0] out_data,
output [CHANNEL_WIDTH - 1 : 0] out_channel,
output [ERROR_WIDTH - 1 : 0] out_error,
output out_startofpacket,
output out_endofpacket,
output [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] out_empty
);
// ------------------------------
// Payload-specific widths
// ------------------------------
localparam PACKET_WIDTH = (USE_PACKETS) ? 2 + EMPTY_WIDTH : 0;
localparam PCHANNEL_W = (USE_CHANNEL) ? CHANNEL_WIDTH : 0;
localparam PERROR_W = (USE_ERROR) ? ERROR_WIDTH : 0;
localparam PAYLOAD_WIDTH = DATA_WIDTH +
PACKET_WIDTH +
PCHANNEL_W +
EMPTY_WIDTH +
PERROR_W;
wire [PAYLOAD_WIDTH - 1: 0] in_payload;
wire [PAYLOAD_WIDTH - 1: 0] out_payload;
// ------------------------------
// Assign in_data and other optional sink interface
// signals to in_payload.
// ------------------------------
assign in_payload[DATA_WIDTH - 1 : 0] = in_data;
generate
// optional packet inputs
if (PACKET_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH - 1 :
DATA_WIDTH
] = {in_startofpacket, in_endofpacket};
end
// optional channel input
if (USE_CHANNEL) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
DATA_WIDTH + PACKET_WIDTH
] = in_channel;
end
// optional empty input
if (EMPTY_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
] = in_empty;
end
// optional error input
if (USE_ERROR) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
] = in_error;
end
endgenerate
// --------------------------------------------------
// Pipe the input payload to our inner module which handles the
// actual clock crossing
// --------------------------------------------------
altera_avalon_st_clock_crosser
#(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (PAYLOAD_WIDTH),
.FORWARD_SYNC_DEPTH (VALID_SYNC_DEPTH),
.BACKWARD_SYNC_DEPTH (READY_SYNC_DEPTH),
.USE_OUTPUT_PIPELINE (USE_OUTPUT_PIPELINE)
) clock_xer (
.in_clk (in_clk ),
.in_reset (in_reset ),
.in_ready (in_ready ),
.in_valid (in_valid ),
.in_data (in_payload ),
.out_clk (out_clk ),
.out_reset (out_reset ),
.out_ready (out_ready ),
.out_valid (out_valid ),
.out_data (out_payload )
);
// --------------------------------------------------
// Split out_payload into the output signals.
// --------------------------------------------------
assign out_data = out_payload[DATA_WIDTH - 1 : 0];
generate
// optional packet outputs
if (USE_PACKETS) begin
assign {out_startofpacket, out_endofpacket} =
out_payload[DATA_WIDTH + PACKET_WIDTH - 1 : DATA_WIDTH];
end else begin
// avoid a "has no driver" warning.
assign {out_startofpacket, out_endofpacket} = 2'b0;
end
// optional channel output
if (USE_CHANNEL) begin
assign out_channel = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
DATA_WIDTH + PACKET_WIDTH
];
end else begin
// avoid a "has no driver" warning.
assign out_channel = 1'b0;
end
// optional empty output
if (EMPTY_WIDTH) begin
assign out_empty = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
];
end else begin
// avoid a "has no driver" warning.
assign out_empty = 1'b0;
end
// optional error output
if (USE_ERROR) begin
assign out_error = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
];
end else begin
// avoid a "has no driver" warning.
assign out_error = 1'b0;
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value.
// --------------------------------------------------
function integer log2ceil;
input integer val;
integer i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE rev.B2 compliant I2C Master byte-controller ////
//// ////
//// ////
//// Author: Richard Herveille ////
//// ////
//// www.asics.ws ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: i2c_master_byte_ctrl.v,v 1.1 2008-11-08 13:15:10 sfielding Exp $
//
// $Date: 2008-11-08 13:15:10 $
// $Revision: 1.1 $
// $Author: sfielding $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.7 2004/02/18 11:40:46 rherveille
// Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command.
//
// Revision 1.6 2003/08/09 07:01:33 rherveille
// Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
// Fixed a potential bug in the byte controller's host-acknowledge generation.
//
// Revision 1.5 2002/12/26 15:02:32 rherveille
// Core is now a Multimaster I2C controller
//
// Revision 1.4 2002/11/30 22:24:40 rherveille
// Cleaned up code
//
// Revision 1.3 2001/11/05 11:59:25 rherveille
// Fixed wb_ack_o generation bug.
// Fixed bug in the byte_controller statemachine.
// Added headers.
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "i2c_master_defines.v"
module i2c_master_byte_ctrl (
clk, rst, nReset, ena, clk_cnt, start, stop, read, write, ack_in, din,
cmd_ack, ack_out, dout, i2c_busy, i2c_al, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen );
//
// inputs & outputs
//
input clk; // master clock
input rst; // synchronous active high reset
input nReset; // asynchronous active low reset
input ena; // core enable signal
input [15:0] clk_cnt; // 4x SCL
// control inputs
input start;
input stop;
input read;
input write;
input ack_in;
input [7:0] din;
// status outputs
output cmd_ack;
reg cmd_ack;
output ack_out;
reg ack_out;
output i2c_busy;
output i2c_al;
output [7:0] dout;
// I2C signals
input scl_i;
output scl_o;
output scl_oen;
input sda_i;
output sda_o;
output sda_oen;
//
// Variable declarations
//
// statemachine
parameter [4:0] ST_IDLE = 5'b0_0000;
parameter [4:0] ST_START = 5'b0_0001;
parameter [4:0] ST_READ = 5'b0_0010;
parameter [4:0] ST_WRITE = 5'b0_0100;
parameter [4:0] ST_ACK = 5'b0_1000;
parameter [4:0] ST_STOP = 5'b1_0000;
// signals for bit_controller
reg [3:0] core_cmd;
reg core_txd;
wire core_ack, core_rxd;
// signals for shift register
reg [7:0] sr; //8bit shift register
reg shift, ld;
// signals for state machine
wire go;
reg [2:0] dcnt;
wire cnt_done;
//
// Module body
//
// hookup bit_controller
i2c_master_bit_ctrl bit_controller (
.clk ( clk ),
.rst ( rst ),
.nReset ( nReset ),
.ena ( ena ),
.clk_cnt ( clk_cnt ),
.cmd ( core_cmd ),
.cmd_ack ( core_ack ),
.busy ( i2c_busy ),
.al ( i2c_al ),
.din ( core_txd ),
.dout ( core_rxd ),
.scl_i ( scl_i ),
.scl_o ( scl_o ),
.scl_oen ( scl_oen ),
.sda_i ( sda_i ),
.sda_o ( sda_o ),
.sda_oen ( sda_oen )
);
// generate go-signal
assign go = (read | write | stop) & ~cmd_ack;
// assign dout output to shift-register
assign dout = sr;
// generate shift register
always @(posedge clk or negedge nReset)
if (!nReset)
sr <= #1 8'h0;
else if (rst)
sr <= #1 8'h0;
else if (ld)
sr <= #1 din;
else if (shift)
sr <= #1 {sr[6:0], core_rxd};
// generate counter
always @(posedge clk or negedge nReset)
if (!nReset)
dcnt <= #1 3'h0;
else if (rst)
dcnt <= #1 3'h0;
else if (ld)
dcnt <= #1 3'h7;
else if (shift)
dcnt <= #1 dcnt - 3'h1;
assign cnt_done = ~(|dcnt);
//
// state machine
//
reg [4:0] c_state; // synopsis enum_state
always @(posedge clk or negedge nReset)
if (!nReset)
begin
core_cmd <= #1 `I2C_CMD_NOP;
core_txd <= #1 1'b0;
shift <= #1 1'b0;
ld <= #1 1'b0;
cmd_ack <= #1 1'b0;
c_state <= #1 ST_IDLE;
ack_out <= #1 1'b0;
end
else if (rst | i2c_al)
begin
core_cmd <= #1 `I2C_CMD_NOP;
core_txd <= #1 1'b0;
shift <= #1 1'b0;
ld <= #1 1'b0;
cmd_ack <= #1 1'b0;
c_state <= #1 ST_IDLE;
ack_out <= #1 1'b0;
end
else
begin
// initially reset all signals
core_txd <= #1 sr[7];
shift <= #1 1'b0;
ld <= #1 1'b0;
cmd_ack <= #1 1'b0;
case (c_state) // synopsys full_case parallel_case
ST_IDLE:
if (go)
begin
if (start)
begin
c_state <= #1 ST_START;
core_cmd <= #1 `I2C_CMD_START;
end
else if (read)
begin
c_state <= #1 ST_READ;
core_cmd <= #1 `I2C_CMD_READ;
end
else if (write)
begin
c_state <= #1 ST_WRITE;
core_cmd <= #1 `I2C_CMD_WRITE;
end
else // stop
begin
c_state <= #1 ST_STOP;
core_cmd <= #1 `I2C_CMD_STOP;
end
ld <= #1 1'b1;
end
ST_START:
if (core_ack)
begin
if (read)
begin
c_state <= #1 ST_READ;
core_cmd <= #1 `I2C_CMD_READ;
end
else
begin
c_state <= #1 ST_WRITE;
core_cmd <= #1 `I2C_CMD_WRITE;
end
ld <= #1 1'b1;
end
ST_WRITE:
if (core_ack)
if (cnt_done)
begin
c_state <= #1 ST_ACK;
core_cmd <= #1 `I2C_CMD_READ;
end
else
begin
c_state <= #1 ST_WRITE; // stay in same state
core_cmd <= #1 `I2C_CMD_WRITE; // write next bit
shift <= #1 1'b1;
end
ST_READ:
if (core_ack)
begin
if (cnt_done)
begin
c_state <= #1 ST_ACK;
core_cmd <= #1 `I2C_CMD_WRITE;
end
else
begin
c_state <= #1 ST_READ; // stay in same state
core_cmd <= #1 `I2C_CMD_READ; // read next bit
end
shift <= #1 1'b1;
core_txd <= #1 ack_in;
end
ST_ACK:
if (core_ack)
begin
if (stop)
begin
c_state <= #1 ST_STOP;
core_cmd <= #1 `I2C_CMD_STOP;
end
else
begin
c_state <= #1 ST_IDLE;
core_cmd <= #1 `I2C_CMD_NOP;
// generate command acknowledge signal
cmd_ack <= #1 1'b1;
end
// assign ack_out output to bit_controller_rxd (contains last received bit)
ack_out <= #1 core_rxd;
core_txd <= #1 1'b1;
end
else
core_txd <= #1 ack_in;
ST_STOP:
if (core_ack)
begin
c_state <= #1 ST_IDLE;
core_cmd <= #1 `I2C_CMD_NOP;
// generate command acknowledge signal
cmd_ack <= #1 1'b1;
end
endcase
end
endmodule
|
//#############################################################################
//# Function: Aligns positive edge of slow clock to fast clock #
//# !!!Assumes clocks are aligned and synchronous!!! #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
/*
* ___________ ___________
* __/ \___________/ \ SLOWCLK
* __ __ __ __ __ __
* _/ \__/ \__/ \__/ \__/ \__/ \__/ FASTCLK
* ___________ _________
* ___/ 1 1 \_0_____0____/ CLK45
* ____________ ___
* ______/ 1 1 \___0____0___/ CLK90
*
* ____ ______
* \________________/ \________ FIRSTEDGE
*
*/
module oh_edgealign (/*AUTOARG*/
// Outputs
firstedge,
// Inputs
fastclk, slowclk
);
input fastclk;
input slowclk;
output firstedge;
reg clk45;
reg clk90;
reg firstedge;
always @ (negedge fastclk)
clk45 <= slowclk;
always @ (posedge fastclk)
begin
clk90 <= clk45;
firstedge <= ~clk45 & clk90;
end
endmodule // oh_edgealign
|
#include <bits/stdc++.h> using namespace std; const long long mod = 998244353; void ingraph(vector<long long> graph[], long long m) { long long x, y; for (long long i = 0; i < m; i++) { cin >> x >> y; x--, y--; graph[x].push_back(y); graph[y].push_back(x); } } long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } long long lcm(long long a, long long b) { return a * b / gcd(a, b); } long long modmulti(long long a, long long b) { return ((a % mod) * 1ll * (b % mod)) % mod; } long long modadd(long long a, long long b) { long long asdfgh = ((a % mod) + (b % mod) + mod + mod) % mod; asdfgh = (asdfgh + mod) % mod; return asdfgh; } long long modpower(long long a, long long n) { if (n == 0) return 1; if (n == 1) return a % mod; long long b = modpower(a, n / 2); b = modmulti(b, b); if (n % 2 == 0) return b; return modmulti(a, b); } long long modinv(long long a) { return modpower(a, mod - 2); } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); long long t; cin >> t; while (t--) { long long n; cin >> n; long long sum = 0; vector<long long> vec; for (long long i = 1; i <= n; i = i * 2) { vec.push_back(i); n = n - i; } if (n > 0) { vec.push_back(n); } sort(vec.begin(), vec.end()); cout << (long long)(vec).size() - 1 << n ; for (long long i = 1; i < (long long)(vec).size(); i++) cout << vec[i] - vec[i - 1] << ; cout << n ; } return 0; } |
//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.4 (win64) Build Tue Nov 18 18:29:27 MST 2014
//Date : Thu May 19 21:55:14 2016
//Host : YINGCAIDONG1779 running 64-bit Service Pack 1 (build 7601)
//Command : generate_target system_wrapper.bd
//Design : system_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module system_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
system system_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb));
endmodule
|
#include <bits/stdc++.h> const int N = 1e5 + 10; const int LOGN = 20; long long ans; int n; int pre[N << 1], to[N << 1], head[N], wcnt; long long dis[N]; int val[N], fa[N]; int dep[N]; int table[LOGN][N << 1]; int LOG2[N << 1]; int idcnt; int st[N]; inline int minp(int x, int y) { return (dep[x] < dep[y]) ? x : y; } inline void swap(int &x, int &y) { int t = x; x = y; y = t; } template <class T> inline T max(const T &x, const T &y) { return (x < y) ? y : x; } inline void addedge(int u, int v) { wcnt++; pre[wcnt] = head[u]; head[u] = wcnt; to[wcnt] = v; } inline void add2edge(int u, int v) { addedge(u, v); addedge(v, u); } void init() { int i, j, k; for (i = int(2); i <= int(idcnt); i++) LOG2[i] = LOG2[i >> 1] + 1; for (i = k = 1; k <= idcnt; i++, k <<= 1) for (j = 1; j <= int(idcnt - k); j++) table[i][j] = minp(table[i - 1][j], table[i - 1][j + k]); } inline long long getdis(int x, int y) { int l, r, k, z; l = st[x]; r = st[y]; if (l > r) swap(l, r); k = LOG2[r - l + 1]; z = minp(table[k][l], table[k][r - (1 << k) + 1]); return dis[x] + dis[y] - 2 * dis[z] + val[z]; } struct Node { int x, y; long long d; Node() { x = y = 0; d = -1; } Node(int x, int y) : x(x), y(y) { d = getdis(x, y); } bool operator<(const Node &b) const { return d < b.d; } Node operator+(const Node &b) const { if (d == -1) return b; else if (b.d == -1) return *this; Node res = max(*this, b); res = max(res, Node(x, b.x)); res = max(res, Node(x, b.y)); res = max(res, Node(y, b.x)); res = max(res, Node(y, b.y)); return res; } }; Node sum[N], g[N]; void predfs(int u) { int i; table[0][st[u] = ++idcnt] = u; dis[u] = dis[fa[u]] + val[u]; for (i = head[u]; i; i = pre[i]) if (fa[u] ^ to[i]) { fa[to[i]] = u; dep[to[i]] = dep[u] + 1; predfs(to[i]); table[0][++idcnt] = u; } } void dfs1(int u) { int i; sum[u] = Node(u, u); for (i = head[u]; i; i = pre[i]) if (fa[u] ^ to[i]) { dfs1(to[i]); sum[u] = sum[u] + sum[to[i]]; } } void dfs2(int u) { static Node pref[N], suff[N]; static int son[N]; int i, sn = 0; for (i = head[u]; i; i = pre[i]) if (fa[u] ^ to[i]) son[++sn] = to[i]; pref[0] = suff[sn + 1] = g[u] + Node(u, u); for (i = 1; i <= int(sn); i++) pref[i] = pref[i - 1] + sum[son[i]]; for (i = int(sn); i; i--) suff[i] = suff[i + 1] + sum[son[i]]; for (i = 1; i <= int(sn); i++) g[son[i]] = pref[i - 1] + suff[i + 1]; for (i = int(0); i <= int(sn + 1); i++) pref[i] = suff[i] = Node(); if (u > 1) ans = max(ans, sum[u].d + g[u].d); for (i = head[u]; i; i = pre[i]) if (fa[u] ^ to[i]) dfs2(to[i]); } int main() { int i; int u, v; scanf( %d , &n); for (i = 1; i <= int(n); i++) scanf( %d , &val[i]); for (i = 1; i <= int(n - 1); i++) { scanf( %d %d , &u, &v); add2edge(u, v); } predfs(1); init(); dfs1(1); ans = sum[1].d; dfs2(1); printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { if (b == 0) return a; return gcd(b, a % b); } void solve() { int a, b, n; cin >> a >> b >> n; bool aturn = true; while (n > 0) { int x; if (aturn) { x = gcd(a, n); aturn = false; } else { x = gcd(b, n); aturn = true; } n -= x; } if (aturn == false) cout << 0 << n ; else cout << 1 << n ; } int main(void) { ios_base::sync_with_stdio(false); cin.tie(NULL); solve(); return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; constexpr int LG = 60; int N; long long int ai, bi, bs; long long int x[LG + 1]; inline bool ins(long long int v) { for (int i = LG; i >= 0; --i) { if (!((v >> i) & 1)) continue; if (x[i]) { v ^= x[i]; } else { for (int j = i - 1; j >= 0; --j) if ((v >> j) & 1) v ^= x[j]; for (int j = i + 1; j <= LG; ++j) if ((x[j] >> i) & 1) x[j] ^= v; x[i] = v; return true; } } return false; } int main() { ios::sync_with_stdio(false); cin.tie(NULL); cin >> N; int s = 0; for (int i = 0; i < N; ++i) { cin >> ai >> bi; bs ^= bi, ai ^= bi; if (ins(ai)) ++s; } for (int i = LG; i >= 0; --i) if ((bs >> i) & 1) bs ^= x[i]; if (bs) cout << 1/1 n ; else cout << (1ll << s) - 1 << / << (1ll << s) << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUX2_SYMBOL_V
`define SKY130_FD_SC_HDLL__MUX2_SYMBOL_V
/**
* mux2: 2-input multiplexer.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__mux2 (
//# {{data|Data Signals}}
input A0,
input A1,
output X ,
//# {{control|Control Signals}}
input S
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUX2_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int i, i0, n, m, a[105]; bool vis[100]; vector<int> ans; int main() { while (scanf( %d , &n) != EOF) { for (i = 0; i < n; i++) scanf( %d , &a[i]); sort(a, a + n); for (i = 0; i < n; i++) { if (a[i] == 0) { ans.push_back(a[i]); vis[0] = 1; break; } } for (i = 0; i < n; i++) { if (a[i] < 10 && a[i] != 0) { ans.push_back(a[i]); vis[1] = 1; break; } } for (i = 0; i < n; i++) { if (a[i] < 100 && a[i] % 10 == 0 && a[i] >= 10) { ans.push_back(a[i]); vis[2] = 1; break; } } for (i = 0; i < n; i++) { if (a[i] == 100) { ans.push_back(a[i]); vis[3] = 1; break; } } if (vis[1] == 0 && vis[2] == 0) { for (i = 0; i < n; i++) if (a[i] < 100 && a[i] >= 10) { ans.push_back(a[i]); break; } } printf( %d n , ans.size()); for (i = 0; i < ans.size(); i++) { printf( %d , ans[i]); if (ans.size() - 1 == i) printf( n ); else printf( ); } } return 0; } |
`define ADDER_WIDTH 128
`define DUMMY_WIDTH 128
`define 3_LEVEL_ADDER
module adder_tree_top (
clk,
isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1,
sum,
);
input clk;
input [`ADDER_WIDTH+0-1:0] isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1;
output [`ADDER_WIDTH :0] sum;
reg [`ADDER_WIDTH :0] sum;
wire [`ADDER_WIDTH+3-1:0] sum0;
wire [`ADDER_WIDTH+2-1:0] sum0_0, sum0_1;
wire [`ADDER_WIDTH+1-1:0] sum0_0_0, sum0_0_1, sum0_1_0, sum0_1_1;
reg [`ADDER_WIDTH+0-1:0] sum0_0_0_0, sum0_0_0_1, sum0_0_1_0, sum0_0_1_1, sum0_1_0_0, sum0_1_0_1, sum0_1_1_0, sum0_1_1_1;
adder_tree_branch L1_0(sum0_0, sum0_1, sum0 );
defparam L1_0.EXTRA_BITS = 2;
adder_tree_branch L2_0(sum0_0_0, sum0_0_1, sum0_0 );
adder_tree_branch L2_1(sum0_1_0, sum0_1_1, sum0_1 );
defparam L2_0.EXTRA_BITS = 1;
defparam L2_1.EXTRA_BITS = 1;
adder_tree_branch L3_0(sum0_0_0_0, sum0_0_0_1, sum0_0_0);
adder_tree_branch L3_1(sum0_0_1_0, sum0_0_1_1, sum0_0_1);
adder_tree_branch L3_2(sum0_1_0_0, sum0_1_0_1, sum0_1_0);
adder_tree_branch L3_3(sum0_1_1_0, sum0_1_1_1, sum0_1_1);
defparam L3_0.EXTRA_BITS = 0;
defparam L3_1.EXTRA_BITS = 0;
defparam L3_2.EXTRA_BITS = 0;
defparam L3_3.EXTRA_BITS = 0;
always @(posedge clk) begin
sum0_0_0_0 <= isum0_0_0_0;
sum0_0_0_1 <= isum0_0_0_1;
sum0_0_1_0 <= isum0_0_1_0;
sum0_0_1_1 <= isum0_0_1_1;
sum0_1_0_0 <= isum0_1_0_0;
sum0_1_0_1 <= isum0_1_0_1;
sum0_1_1_0 <= isum0_1_1_0;
sum0_1_1_1 <= isum0_1_1_1;
`ifdef 3_LEVEL_ADDER
sum <= sum0;
`endif
`ifdef 2_LEVEL_ADDER
sum <= sum0_0;
`endif
end
endmodule
module adder_tree_branch(a,b,sum);
parameter EXTRA_BITS = 0;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] a;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] b;
output [`ADDER_WIDTH+EXTRA_BITS:0] sum;
assign sum = a + b;
endmodule |
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int MN = 200010; int exp(int x, int n) { int ret = 1; while (n) { if (n & 1) ret = 1LL * ret * x % mod; x = 1LL * x * x % mod; n >>= 1; } return ret; } int inv(int x) { return exp(x, mod - 2); } int fact[MN], invf[MN]; int comb(int n, int k) { if (n < k) return 0; return 1LL * fact[n] * invf[k] % mod * invf[n - k] % mod; } int S(int n, int k) { int ret = 0; for (int i = 0; i < k; i++) { ret += 1LL * comb(k, i) * (i % 2 ? mod - 1 : 1) % mod * exp(k - i, n) % mod; ret %= mod; } ret = 1LL * ret * invf[k] % mod; return ret; } int N, K; int W[MN]; int main() { fact[0] = 1; for (int i = 1; i < MN; i++) { fact[i] = 1LL * fact[i - 1] * i % mod; } for (int i = 0; i < MN; i++) { invf[i] = inv(fact[i]); } scanf( %d %d , &N, &K); int sum = 0; for (int i = 0; i < N; i++) { scanf( %d , &W[i]); sum += W[i]; sum %= mod; } int ans = 1LL * ((S(N, K) + 1LL * (N - 1) * S(N - 1, K) % mod) % mod) * sum % mod; printf( %d , ans); } |
#include <bits/stdc++.h> static int v1[100001]; static int v2[100001]; int comp(const void *elem1, const void *elem2) { return *((const int *)elem2) - *((const int *)elem1); } int main(void) { int k, r, n; scanf( %d %d %d , &n, &k, &r); k--; r--; for (int i = 0; i < n; ++i) { int a; scanf( %d , &a); v1[i] = a; } for (int i = 0; i < n; ++i) { int a; scanf( %d , &a); v2[i] = a; } qsort(v1 + k, r - k + 1, sizeof(int), comp); qsort(v2 + k, r - k + 1, sizeof(int), comp); for (int i = 0; i < n; ++i) { if (v1[i] != v2[i]) { printf( LIE ); return 0; } } printf( TRUTH ); return 0; } |
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } long long lcm(long long a, long long b) { return a / gcd(a, b) * b; } double PI = 3.1415926536; const int inf = 1e9 + 7; long long MAX(long long a, long long b) { return a > b ? a : b; } long long MIN(long long a, long long b) { return a > b ? b : a; } inline bool ispalindrome(string s) { int n = s.length(), i = 0, j = n - 1; while (i <= j) { if (s[i] != s[j]) return false; i++, j--; } return true; } inline bool isprime(long long n) { if (n % 2 == 0) return false; for (int i = 3; i * i <= n; i += 2) if (n % i == 0) return false; return true; } void solve() { int n, k; cin >> n >> k; queue<int> q; set<int> vals; for (int i = 0; i < n; ++i) { int id; cin >> id; if (!vals.count(id)) { if (int(q.size()) >= k) { int cur = q.front(); q.pop(); vals.erase(cur); } vals.insert(id); q.push(id); } } vector<int> res; while (!q.empty()) { res.push_back(q.front()); q.pop(); } reverse(res.begin(), res.end()); cout << res.size() << n ; for (auto it : res) cout << it << ; cout << n ; } int main() { ios::sync_with_stdio(false); cin.tie(0); int t = 1; for (int i = 1; i <= t; i++) { solve(); cout << n ; } return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC target( avx,avx2,fma ) using namespace std; long long gcd(long long a, long long b) { return (b == 0) ? a : gcd(b, a % b); } long long lcm(long long a, long long b) { return ((a * b) / (gcd(a, b))); } bool compare(const pair<long long, long long> &a, const pair<long long, long long> &b) { return a.second < b.second; } long long ceil(long long a, long long b) { return (a + b - 1) / b; } long long binpowmod(long long a, long long b, long long m) { long long res = 1; while (b > 0) { if (b & 1) { res = ((res % m) * (a % m)) % m; } a = ((a % m) * (a % m)) % m; b >>= 1; } res %= m; return res; } long long binpow(long long a, long long b) { long long res = 1; while (b > 0) { if (b & 1) { res = ((res) * (a)); } a = ((a) * (a)); b >>= 1; } return res; } void swap(long long *a, long long *b) { long long temp = *a; *a = *b; *b = temp; } long long sum_digits(long long x) { long long s = 0; while (x) { s += (x % 10); x /= 10; } return s; } bool is_perfect_square(long long n) { return (floor(double(sqrt(n))) == ceil(double(sqrt(n)))); } vector<int> pr; void prime() { const int N = 10000000; int lp[N + 1] = {0}; for (int i = 2; i <= N; ++i) { if (lp[i] == 0) { lp[i] = i; pr.push_back(i); } for (int j = 0; j < (int)pr.size() && pr[j] <= lp[i] && i * pr[j] <= N; ++j) lp[i * pr[j]] = pr[j]; } } long long bs(vector<long long> &arr, long long l, long long r, long long x) { long long mid = 0; if (r >= l) { mid = l + (r - l) / 2; if (arr[mid] == x) return mid; if (arr[mid] > x) return bs(arr, l, mid - 1, x); return bs(arr, mid + 1, r, x); } return -1; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; std::vector<long long> v; int c1 = 0, c2 = 0; for (int i = (0); i < (n); i++) { int x; cin >> x; if (x == 1) c1++; else c2++; } if (c1 == 0) v = std::vector<long long>(n, 2); else if (c2 == 0) v = std::vector<long long>(n, 1); else { v.push_back(2); c2--; v.push_back(1); c1--; while ((c2)--) v.push_back(2); while ((c1)--) v.push_back(1); } for (int i = (0); i < (n); i++) cout << v[i] << ; } |
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* Matrix Arbiter
*
* See Dally/Towles (p.359) for implementation details and full description
*
* Multistage Options
* ==================
*
* [multistage=0] Arbiter state is updated whenever a request is granted.
*
* [multistage=1] This arbiter is meant for situations where the initial
* request must progress through multiple stages of arbitration. An
* additional input to the arbiter (success) ensures that the state of
* the arbiter is only updated if the request is finally granted (at the
* last stage of arbitration).
*
* || This assumes 'success' is produced before the end of the current clock
* || cycle.
*
* [multistage=2] Used in situations where multistage=1 would be, but when
* 'success' is not available until the next clock cycle.
*
* Prioritised inputs
* ==================
*
* [priority_support = 0 | 1]
*
* Input requested are prioritized by associated 'req_priority' input,
* may be anything from a single bit to N-bits wide.
*
* e.g. for 16 priority levels:
*
* parameter priority_support = 1;
* parameter type priority_type = bit unsigned [3:0];
*
* Note: The priority input is ignored if the associated request is
* not asserted.
*
*/
//#################################
// NOT IMPLEMENTED YET:
//
// - parameter GRANT_HOLD
// don't update matrix state until request
// assoc. with current grant is released
// - winning request will hold grant for as long as it is asserted
//
// - parameter PRIORITIZE first F inputs -
// inputs 0..F are priority inputs
// input 0 will be granted if requested
// input 1 will be granted (if input 0 is not asserted)
// ..etc to input F
//
// weighted arbiter,....
module comb_matrix_arb_next_state (state, grant, new_state);
parameter size=4;
input [size*size-1:0] state;
input [size-1:0] grant;
output [size*size-1:0] new_state;
genvar i,j;
generate
for (i=0; i<size; i=i+1) begin:ol2
for (j=0; j<size; j=j+1) begin:il2
assign new_state[j*size+i]= (state[j*size+i]&&!grant[j])||(grant[i]);
end
end
endgenerate
endmodule // comb_matrix_arb_next_state
module matrix_arb (request, req_priority, max_priority, grant, success, clk, rst_n);
parameter size= 4;
parameter multistage = 0;
parameter grant_hold = 0;
parameter priority_support = 0;
//parameter type priority_type = bit unsigned [3:0]; // e.g. 16-levels of priority
input [size-1:0] request;
input priority_type req_priority [size-1:0]; // optional
output priority_type max_priority;
output [size-1:0] grant;
input success;
input clk, rst_n;
genvar i,j;
logic [size-1:0] req;
logic [size-1:0] newgrant;
logic [size*size-1:0] next_state, current_state;
logic [size-1:0] pri [size-1:0];
logic [size*size-1:0] new_state;
logic [size*size-1:0] state;
logic update;
genvar r;
integer k;
priority_type highest_pri;
// #########################################
// Support for Prioritized Requests
// #########################################
assign max_priority = highest_pri;
// always@(posedge clk) begin
// $display ("%m: req=%b, grant=%b", req, grant);
// end
always_comb
begin
// if (priority_support && $bits(priority_type)>1) begin
if (priority_support) begin
highest_pri='0;
for (k=0; k<size; k++) begin
if (request[k] && (req_priority[k]>highest_pri)) highest_pri=req_priority[k];
end
end
end
generate
if (priority_support) begin
//
// determine what is highest priority request
// filter out any request with lower priority
//
for (r=0; r<size; r++) begin:ll
assign req[r]=request[r] && (req_priority[r]>=highest_pri);
end
end else begin // if (priority_support)
assign req=request;
end
endgenerate
// ##########################################
// Generate grants
// ##########################################
generate
for (i=0; i<size; i=i+1) begin:ol1
// generate grant i
for (j=0; j<size; j=j+1) begin:il1
if (j==i)
// request i wins if requesting and....
assign pri[i][j]=req[i];
else
// ....no other request with higher priority
if (j>i)
// j beats i
assign pri[i][j]=!(req[j]&&state[j*size+i]);
else
// !(i beats j)
assign pri[i][j]=!(req[j]&&!state[i*size+j]);
end
assign grant[i]=&pri[i];
end
endgenerate
generate
if (multistage==2) begin
assign state = success ? next_state : current_state;
end else begin
assign state = current_state;
end
endgenerate
//
// calculate next matrix state based on current requests and grants
//
comb_matrix_arb_next_state #(size) calc_next (.*);
always@(posedge clk) begin
if (!rst_n) begin
current_state<='1; //-1;
next_state<='1; //-1;
end else begin
// **************************************************
// Multistage Arbiter with Late Success Notification (multistage==2)
// **************************************************
if (multistage==2) begin
update<=|req;
if (|req) begin
// This 'next_state' will only be used on next clock cycle if
// 'success' is asserted
next_state <= new_state;
end
if (update) begin
current_state <= state;
end
end else begin
// ************************************
// Multistage Arbiter (multistage==1)
// ************************************
// check request was ultimately successful before updating arbiter state
// we know about success before the next clock cycle.
if ((multistage==1)&!success) begin
// request was not ultimately successful, don't update priorities
end else begin
// **********************************
// Basic Arbiter (multistage==0)
// **********************************
// Update state whenever at least one request has been made
if (|req) begin
current_state<=new_state;
end
end
end
end
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Project: Aurora 64B/66B
// Company: Xilinx
//
//
//
// (c) Copyright 2008 - 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
///////////////////////////////////////////////////////////////////////////////
//
// Width and clock rate converter
//
// Description: This module is used as a shim between the Aurora protocol and
// the gtx in the 64B66B protocol.It is required to convert data
// at 16 from gtx to 32 into the aurora.
/////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module aurora_64b66b_25p4G_WIDTH_CONVERSION #
(
parameter INPUT_WIDTH =2,
parameter OUTPUT_WIDTH=4
)
(
//Output to the Aurora Protocol interface
DATA_OUT,
//Input from the GTX
DATA_IN,
// Sync header from GTX Interface
HEADER_IN,
DATAVALID_IN,
// Sync header to Aurora
HEADER_OUT,
DATAVALID_OUT,
//Clock and reset
USER_CLK,
ENABLE,
RESET
);
`define DLY #1
//***********************************Port Declarations*******************************
input RESET;
input USER_CLK;
input ENABLE;
input [INPUT_WIDTH*8-1:0] DATA_IN;
output [OUTPUT_WIDTH*8-1:0] DATA_OUT;
output [1:0] HEADER_OUT;
output DATAVALID_OUT;
//*****************************MGT Interface**************************
input [1:0] HEADER_IN;
input DATAVALID_IN;
//*****************************External Register Declarations**************************
reg [OUTPUT_WIDTH*8-1:0] DATA_OUT;
reg [1:0] HEADER_OUT;
//*****************************Internal Register Declarations**************************
reg [INPUT_WIDTH*8-1:0] data_in_r;
reg [INPUT_WIDTH*8-1:0] data_in_r2;
reg [1:0] header_in_r;
reg [1:0] header_in_r2;
reg datavalid_r;
reg datavalid_r2;
reg datavalid_neg_r;
reg datavalid_pos_r;
reg state;
//*****************************Beginning of Code *************************
always @(posedge USER_CLK)
begin
data_in_r <= `DLY DATA_IN;
data_in_r2 <= `DLY data_in_r;
header_in_r <= `DLY HEADER_IN;
header_in_r2 <= `DLY header_in_r;
end
always @(posedge USER_CLK)
begin
datavalid_r <= `DLY DATAVALID_IN;
datavalid_r2 <= `DLY datavalid_r;
end
always @(posedge USER_CLK)
begin
if(RESET)
state <= `DLY 1'b1;
else if (ENABLE && datavalid_r2 && !datavalid_neg_r)
state <= `DLY 1'b0;
else if (ENABLE && !datavalid_r2 && !datavalid_neg_r)
state <= `DLY 1'b1;
end
always @(posedge USER_CLK)
if(ENABLE)
begin
datavalid_pos_r <= `DLY datavalid_r;
end
always @(negedge USER_CLK)
begin
datavalid_neg_r <= `DLY datavalid_r;
end
always @(posedge USER_CLK)
if(RESET) DATA_OUT <= `DLY 32'b0;
else if(ENABLE)
begin
if(state)
DATA_OUT <= `DLY {data_in_r2,data_in_r};
else if(!state)
DATA_OUT <= `DLY {data_in_r,DATA_IN};
end
always @(posedge USER_CLK)
if (RESET) HEADER_OUT <= `DLY 2'b0;
else if(ENABLE)
begin
if(!state)
HEADER_OUT <= `DLY header_in_r;
else if(state)
HEADER_OUT <= `DLY header_in_r2;
end
assign DATAVALID_OUT = datavalid_pos_r;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFRTN_BEHAVIORAL_V
`define SKY130_FD_SC_HD__DFRTN_BEHAVIORAL_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hd__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dfrtn (
Q ,
CLK_N ,
D ,
RESET_B
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
reg notifier ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_N_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intclk, CLK_N_delayed );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, intclk, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFRTN_BEHAVIORAL_V |
/*
*
* Copyright (c) 2011
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`include "main_pll.v"
//`include "main_pll_2x.v"
`include "sha-256-functions.v"
`include "sha256_transform.v"
`include "serial.v" // replaces virtual_wire
`include "raw7seg.v"
`timescale 1ns/1ps
module fpgaminer_top (osc_clk, RxD, TxD, anode, segment, disp_switch);
// The LOOP_LOG2 parameter determines how unrolled the SHA-256
// calculations are. For example, a setting of 1 will completely
// unroll the calculations, resulting in 128 rounds and a large, fast
// design.
//
// A setting of 2 will result in 64 rounds, with half the size and
// half the speed. 3 will be 32 rounds, with 1/4th the size and speed.
// And so on.
//
// Valid range: [0, 5]
`ifdef CONFIG_LOOP_LOG2
parameter LOOP_LOG2 = `CONFIG_LOOP_LOG2;
`else
parameter LOOP_LOG2 = 5;
`endif
// No need to adjust these parameters
localparam [5:0] LOOP = (6'd1 << LOOP_LOG2);
// The nonce will always be larger at the time we discover a valid
// hash. This is its offset from the nonce that gave rise to the valid
// hash (except when LOOP_LOG2 == 0 or 1, where the offset is 131 or
// 66 respectively).
localparam [31:0] GOLDEN_NONCE_OFFSET = (32'd1 << (7 - LOOP_LOG2)) + 32'd1;
input osc_clk;
////
reg [255:0] state = 0;
reg [511:0] data = 0;
reg [31:0] nonce = 32'h00000000;
//// PLL
wire hash_clk;
`ifndef SIM
main_pll pll_blk (.CLKIN_IN(osc_clk), .CLK0_OUT(hash_clk));
// main_pll pll_blk (.CLKIN_IN(osc_clk), .CLK2X_OUT(hash_clk));
`else
assign hash_clk = osc_clk;
`endif
//// Hashers
wire [255:0] hash, hash2;
reg [5:0] cnt = 6'd0;
reg feedback = 1'b0;
sha256_transform #(.LOOP(LOOP)) uut (
.clk(hash_clk),
.feedback(feedback),
.cnt(cnt),
.rx_state(state),
.rx_input(data),
.tx_hash(hash)
);
sha256_transform #(.LOOP(LOOP)) uut2 (
.clk(hash_clk),
.feedback(feedback),
.cnt(cnt),
.rx_state(256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667),
.rx_input({256'h0000010000000000000000000000000000000000000000000000000080000000, hash}),
.tx_hash(hash2)
);
//// Virtual Wire Control
reg [255:0] midstate_buf = 0, data_buf = 0;
wire [255:0] midstate_vw, data2_vw;
input RxD;
serial_receive serrx (.clk(hash_clk), .RxD(RxD), .midstate(midstate_vw), .data2(data2_vw));
//// Virtual Wire Output
reg [31:0] golden_nonce = 0;
reg serial_send;
wire serial_busy;
output TxD;
serial_transmit sertx (.clk(hash_clk), .TxD(TxD), .send(serial_send), .busy(serial_busy), .word(golden_nonce));
//// Control Unit
reg is_golden_ticket = 1'b0;
reg feedback_d1 = 1'b1;
wire [5:0] cnt_next;
wire [31:0] nonce_next;
wire feedback_next;
`ifndef SIM
wire reset;
assign reset = 1'b0;
`else
reg reset = 1'b0; // NOTE: Reset is not currently used in the actual FPGA; for simulation only.
`endif
assign cnt_next = reset ? 6'd0 : (LOOP == 1) ? 6'd0 : (cnt + 6'd1) & (LOOP-1);
// On the first count (cnt==0), load data from previous stage (no feedback)
// on 1..LOOP-1, take feedback from current stage
// This reduces the throughput by a factor of (LOOP), but also reduces the design size by the same amount
assign feedback_next = (LOOP == 1) ? 1'b0 : (cnt_next != {(LOOP_LOG2){1'b0}});
assign nonce_next =
reset ? 32'd0 :
feedback_next ? nonce : (nonce + 32'd1);
always @ (posedge hash_clk)
begin
`ifdef SIM
//midstate_buf <= 256'h2b3f81261b3cfd001db436cfd4c8f3f9c7450c9a0d049bee71cba0ea2619c0b5;
//data_buf <= 256'h00000000000000000000000080000000_00000000_39f3001b6b7b8d4dc14bfc31;
//nonce <= 30411740;
`else
midstate_buf <= midstate_vw;
data_buf <= data2_vw;
`endif
cnt <= cnt_next;
feedback <= feedback_next;
feedback_d1 <= feedback;
// Give new data to the hasher
state <= midstate_buf;
data <= {384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000, nonce_next, data_buf[95:0]};
nonce <= nonce_next;
// Check to see if the last hash generated is valid.
is_golden_ticket <= (hash2[255:224] == 32'h00000000) && !feedback_d1;
if(is_golden_ticket)
begin
// TODO: Find a more compact calculation for this
if (LOOP == 1)
golden_nonce <= nonce - 32'd131;
else if (LOOP == 2)
golden_nonce <= nonce - 32'd66;
else
golden_nonce <= nonce - GOLDEN_NONCE_OFFSET;
if (!serial_busy) serial_send <= 1;
end // if (is_golden_ticket)
else
serial_send <= 0;
`ifdef SIM
if (!feedback_d1)
$display ("nonce: %8x\nhash2: %64x\n", nonce, hash2);
`endif
end
// die debuggenlichten
input disp_switch;
output [7:0] segment;
output [3:0] anode;
wire [7:0] segment_data;
// inverted signals, so 1111.. to turn it off
assign segment = disp_switch? segment_data : {8{1'b1}};
// raw7seg disp(.clk(hash_clk), .segment(segment_data), .anode(anode), .word({midstate_vw[15:0], data2_vw[15:0]}));
raw7seg disp(.clk(hash_clk), .segment(segment_data), .anode(anode), .word(golden_nonce));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 41; int n, m, q, cs; char a[N][N]; int s[N][N]; int dp[N][N][N][N]; int main() { memset(dp, 0, sizeof(int) * N * N * N * N); cin >> n >> m >> q; for (int i = 0; i < n; ++i) { cin.ignore(); for (int j = 0; j < m; ++j) { cin >> a[i + 1][j + 1]; } } for (int i = 1; i <= n; ++i) { s[i][0] = 0; for (int j = 1; j <= m; ++j) { s[i][j] = (a[i][j] == 0 ? s[i][j - 1] + 1 : 0); } } for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { for (int k = i; k <= n; ++k) { for (int l = j; l <= m; ++l) { dp[i][j][k][l] = dp[i][j][k - 1][l] + dp[i][j][k][l - 1] - dp[i][j][k - 1][l - 1]; int mn = l - j + 1; for (int i1 = k; i1 >= i; --i1) { mn = min(mn, s[i1][l]); dp[i][j][k][l] += mn; } if (dp[i][j][k][l] < 0) return cout << i << << j << << k << << l, 0; } } } } for (int i = 0; i < q; ++i) { int a, b, c, d; cin >> a >> b >> c >> d; cout << dp[a][b][c][d] << endl; } } |
#include <bits/stdc++.h> using namespace std; int main(int argc, char *argv[]) { map<int, int> set; int n, a, b, check1, check2, temp; cin >> n >> a >> b; int arr[n]; vector<int> check; for (int i = int(0); i <= int(n - 1); i++) { cin >> arr[i]; set[arr[i]] = -1; } if (a == b) { for (int i = int(0); i <= int(n - 1); i++) { if (set[a - arr[i]] == 0) { cout << NO << endl; return 0; } } cout << YES << endl; for (int i = int(0); i <= int(n - 1); i++) { cout << 0 ; } return 0; } for (int i = int(0); i <= int(n - 1); i++) { if (set[arr[i]] != -1) continue; check.clear(); check.push_back(arr[i]); check1 = a - arr[i]; check2 = b - arr[i]; bool f = false; while (!f) { if (set[check1] == -1 && set[check2] == -1) { check.push_back(check1); check.push_back(check2); temp = check1; check1 = a - check2; check2 = b - temp; } else if (set[check1] == -1) { check.push_back(check1); f = 1; for (int i = int(0); i <= int(check.size() - 1); i++) { set[check.at(i)] = 1; } } else if (set[check2] == -1) { check.push_back(check2); f = 1; for (int i = int(0); i <= int(check.size() - 1); i++) { set[check.at(i)] = 2; } } else { cout << NO << endl; return 0; } } } cout << YES << endl; for (int i = int(0); i <= int(n - 1); i++) { cout << set[arr[i]] - 1 << ; } return EXIT_SUCCESS; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: California State University San Bernardino
// Engineer: Bogdan Kravtsov
//
// Create Date: 13:46:10 10/03/2016
// Module Name: PC_tb
// Project Name: MIPS
// Description: Testing MIPS PC implementation in verilog.
//
// Dependencies: PC.v
//
////////////////////////////////////////////////////////////////////////////////
module PC_tb;
// Declare inputs.
reg [31:0] npc;
reg clk;
// Declare outputs.
wire [31:0] pcout;
// Instantiate the PC module.
PC pc (.clk(clk), .npc(npc), .PC(pcout));
initial begin
// Initialize inputs.
npc = 0;
clk = 0;
// Test values.
#20;
npc = npc + 1;
#20;
npc = npc + 1;
#20;
npc = npc + 1;
#20;
npc = npc + 1;
#20;
npc = npc + 1;
// Terminate.
#40 $finish;
end
// Display values.
always @ (posedge clk)
begin
$display("At t = %0d\tnpc = %h\t\tpc = %h", $time, npc, pcout);
end
// Clock.
initial begin
forever begin
#10 clk = ~clk;
end
end
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_controller1 (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 7: 0] in_port;
input reset_n;
wire clk_en;
wire [ 7: 0] data_in;
wire [ 7: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg negate;
reg enable;
wire [31:0] datA = crc[31:0];
wire [31:0] datB = crc[63:32];
// Predict result
wire [63:0] muled = (negate ? (- {32'h0,datA} * {32'h0,datB})
: ( {32'h0,datA} * {32'h0,datB}));
reg [63:0] muled_d1;
reg [63:0] muled_d2;
reg [63:0] muled_d3;
reg [63:0] muled_d4;
reg enable_d1;
reg enable_d2;
reg enable_d3;
always @ (posedge clk) enable_d1 <= enable;
always @ (posedge clk) enable_d2 <= enable_d1;
always @ (posedge clk) enable_d3 <= enable_d2;
always @ (posedge clk) if (enable) muled_d1 <= muled;
always @ (posedge clk) if (enable_d1) muled_d2 <= muled_d1;
always @ (posedge clk) if (enable_d2) muled_d3 <= muled_d2;
always @ (posedge clk) if (enable_d3) muled_d4 <= muled_d3;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [64:0] product_d4; // From test of t_math_synmul_mul.v
// End of automatics
t_math_synmul_mul test (/*AUTOINST*/
// Outputs
.product_d4 (product_d4[64:0]),
// Inputs
.clk (clk),
.enable (enable),
.negate (negate),
.datA (datA[31:0]),
.datB (datB[31:0]));
integer cycs_enabled; initial cycs_enabled = 0;
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x e=%x n=%x a*b=%x synmul=%x\n",$time, cyc,
crc, enable, negate, muled_d4, product_d4[63:0]);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
negate <= 1'b0; // Negation not currently supported
// Always enable in low cycle counts to clear out the pipe
//enable <= 1'b1; // 100% activity factor
enable <= (cyc<10 || cyc[4]); // 50% activity factor
//enable <= (cyc<10 || cyc[4]&cyc[3]); // 25% activity factor
if (enable) cycs_enabled=cycs_enabled+1;
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
end
else begin
if (product_d4[63:0] !== muled_d4) begin
$write("[%0t] BAD product, got=%x exp=%x\n",$time, product_d4[63:0], muled_d4);
$stop;
end
if (cyc==99) begin
if (crc !== 64'hc77bb9b3784ea091) $stop;
end
`ifndef SIM_CYCLES
`define SIM_CYCLES 99
`endif
if (cyc==`SIM_CYCLES) begin
$write("- Cycles=%0d, Activity factor=%0d%%\n", cyc, ((cycs_enabled*100)/cyc));
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; string s; cin >> s; bool arr[26] = {false}; for (int i = 0; i < k; i++) { char c; cin >> c; arr[c - a ] = true; } long long ans = 0; long long co = 0; for (int i = 0; i < n; i++) { int x; x = s[i] - a ; if (arr[s[i] - a ] == true) co++; else { ans += (co * (co + 1)) / 2; co = 0; } } ans += (co * (co + 1)) / 2; cout << ans; } |
`timescale 1ns / 1ps
/* gayle.v
Copyright (C) 2016-2017, Stephen J. Leary
All rights reserved.
This file is part of TF328 (Terrible Fire CD32 RAM + IDE BOARD)
TF530 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
TF530 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with TF530. If not, see <http://www.gnu.org/licenses/>.
*/
module gayle(
input CLKCPU,
input RESET,
input DS,
input CS,
input RW,
input IDE_INT,
output INT2,
input A18,
input [1:0] A,
input D7,
output DOUT7
);
parameter GAYLE_ID_VAL = 4'hd;
reg data_out = 1'b0;
reg [3:0] gayleid = GAYLE_ID_VAL;
reg intena = 1'b0;
reg intlast = 1'b0;
reg ds_d = 1'b0;
// $DE1000
localparam GAYLE_ID_RD = {1'b1,2'h1,1'b1};
localparam GAYLE_ID_WR = {1'b1,2'h1,1'b0};
// $DA8000
localparam GAYLE_STAT_RD = {3'h0,1'b1};
localparam GAYLE_STAT_WR = {3'h0,4'h0,1'b0};
// $DA9000
localparam GAYLE_INTCHG_RD = {3'h1,1'b1};
localparam GAYLE_INTCHG_WR = {3'h1,1'b0};
// $DAA000
localparam GAYLE_INTENA_RD = {3'h2,1'b1};
localparam GAYLE_INTENA_WR = {3'h2,1'b0};
wire INT_CHNG;
wire INT_CHNG_ACCESS = {CS,A18,A,RW} != {1'b0,GAYLE_INTCHG_WR};
FDCPE #(.INIT(1'b1))
INT_CHNG_FF (
.Q(INT_CHNG), // Data output
.C(~DS), // Clock input
.CE(~INT_CHNG_ACCESS), // CLOCK ENABLE
.CLR(~RESET), // Asynchronous clear input
.D(D7 & INT_CHNG), // Data input
.PRE(IDE_INT != intlast) // Asynchronous set input
);
always @(posedge CLKCPU) begin
intlast <= IDE_INT;
ds_d <= DS;
if (RESET == 1'b0) begin
// resetting to low ensures that the next cycle
// after reset is disasserted is not a bus cycle.
intena <= 1'b0;
gayleid <= 4'hD;
end else begin
if ((CS | DS | ~ds_d) == 1'b0) begin
case ({A18,A,RW})
GAYLE_STAT_RD: data_out <= IDE_INT;
GAYLE_INTCHG_RD: data_out <= INT_CHNG;
GAYLE_ID_RD: begin
data_out <= gayleid[3];
gayleid <= {gayleid[2:0],1'b0};
end
GAYLE_ID_WR: gayleid <= 4'hD;
GAYLE_INTENA_RD: data_out <= INT_CHNG;
GAYLE_INTENA_WR: intena <= D7;
default: data_out <= 'b0;
endcase
end
end
end
assign INT2 = INT_CHNG & intena;
assign DOUT7 = data_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, m, k; cin >> n >> m >> k; vector<long long> v; for (int i = 0; i < n; i++) { long long x; cin >> x; v.push_back(x); } long long sum = 0; int i; for (i = n - 1; i >= 0; i--) { sum += v[i]; if (sum > k) { sum = 0; i++; m--; if (m == 0) { break; } } } if (i < 0) i = 0; cout << n - i; return 0; } |
//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_tv_in_put O 1 reg
// axi_out_tvalid O 1 reg
// axi_out_tdata O 608 reg
// axi_out_tstrb O 76 reg
// axi_out_tkeep O 76 reg
// axi_out_tlast O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// tv_in_put I 608 reg
// axi_out_tready I 1
// EN_tv_in_put I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkTV_Xactor(CLK,
RST_N,
tv_in_put,
EN_tv_in_put,
RDY_tv_in_put,
axi_out_tvalid,
axi_out_tdata,
axi_out_tstrb,
axi_out_tkeep,
axi_out_tlast,
axi_out_tready);
input CLK;
input RST_N;
// action method tv_in_put
input [607 : 0] tv_in_put;
input EN_tv_in_put;
output RDY_tv_in_put;
// value method axi_out_m_tvalid
output axi_out_tvalid;
// value method axi_out_m_tid
// value method axi_out_m_tdata
output [607 : 0] axi_out_tdata;
// value method axi_out_m_tstrb
output [75 : 0] axi_out_tstrb;
// value method axi_out_m_tkeep
output [75 : 0] axi_out_tkeep;
// value method axi_out_m_tlast
output axi_out_tlast;
// value method axi_out_m_tdest
// value method axi_out_m_tuser
// action method axi_out_m_tready
input axi_out_tready;
// signals for module outputs
wire [607 : 0] axi_out_tdata;
wire [75 : 0] axi_out_tkeep, axi_out_tstrb;
wire RDY_tv_in_put, axi_out_tlast, axi_out_tvalid;
// ports of submodule tv_xactor_f_data
wire [760 : 0] tv_xactor_f_data$D_IN, tv_xactor_f_data$D_OUT;
wire tv_xactor_f_data$CLR,
tv_xactor_f_data$DEQ,
tv_xactor_f_data$EMPTY_N,
tv_xactor_f_data$ENQ,
tv_xactor_f_data$FULL_N;
// rule scheduling signals
wire CAN_FIRE_axi_out_m_tready,
CAN_FIRE_tv_in_put,
WILL_FIRE_axi_out_m_tready,
WILL_FIRE_tv_in_put;
// action method tv_in_put
assign RDY_tv_in_put = tv_xactor_f_data$FULL_N ;
assign CAN_FIRE_tv_in_put = tv_xactor_f_data$FULL_N ;
assign WILL_FIRE_tv_in_put = EN_tv_in_put ;
// value method axi_out_m_tvalid
assign axi_out_tvalid = tv_xactor_f_data$EMPTY_N ;
// value method axi_out_m_tdata
assign axi_out_tdata = tv_xactor_f_data$D_OUT[760:153] ;
// value method axi_out_m_tstrb
assign axi_out_tstrb = tv_xactor_f_data$D_OUT[152:77] ;
// value method axi_out_m_tkeep
assign axi_out_tkeep = tv_xactor_f_data$D_OUT[76:1] ;
// value method axi_out_m_tlast
assign axi_out_tlast = tv_xactor_f_data$D_OUT[0] ;
// action method axi_out_m_tready
assign CAN_FIRE_axi_out_m_tready = 1'd1 ;
assign WILL_FIRE_axi_out_m_tready = 1'd1 ;
// submodule tv_xactor_f_data
FIFO2 #(.width(32'd761), .guarded(32'd1)) tv_xactor_f_data(.RST(RST_N),
.CLK(CLK),
.D_IN(tv_xactor_f_data$D_IN),
.ENQ(tv_xactor_f_data$ENQ),
.DEQ(tv_xactor_f_data$DEQ),
.CLR(tv_xactor_f_data$CLR),
.D_OUT(tv_xactor_f_data$D_OUT),
.FULL_N(tv_xactor_f_data$FULL_N),
.EMPTY_N(tv_xactor_f_data$EMPTY_N));
// submodule tv_xactor_f_data
assign tv_xactor_f_data$D_IN =
{ tv_in_put, 153'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF } ;
assign tv_xactor_f_data$ENQ = EN_tv_in_put ;
assign tv_xactor_f_data$DEQ = tv_xactor_f_data$EMPTY_N && axi_out_tready ;
assign tv_xactor_f_data$CLR = 1'b0 ;
endmodule // mkTV_Xactor
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O32AI_FUNCTIONAL_V
`define SKY130_FD_SC_LS__O32AI_FUNCTIONAL_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o32ai (
Y ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A3, A1, A2 );
nor nor1 (nor1_out , B1, B2 );
or or0 (or0_out_Y, nor1_out, nor0_out);
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O32AI_FUNCTIONAL_V |
//--------------------------------------------------------------------------------
// stage.vhd
//
// Copyright (C) 2006 Michael Poppitz
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details: http://www.sump.org/projects/analyzer/
//
// Programmable 32 channel trigger stage. It can operate in serial
// and parallel mode. In serial mode any of the input channels
// can be used as input for the 32bit shift register. Comparison
// is done using the value and mask registers on the input in
// parallel mode and on the shift register in serial mode.
// If armed and 'level' has reached the configured minimum value,
// the stage will start to check for a match.
// The match and run output signal delay can be configured.
// The stage will disarm itself after a match occured or when reset is set.
//
// The stage supports "high speed demux" operation in serial and parallel
// mode. (Lower and upper 16 channels contain a 16bit sample each.)
//
// Matching is done using a pipeline. This should not increase the minimum
// time needed between two dependend trigger stage matches, because the
// dependence is evaluated in the last pipeline step.
// It does however increase the delay for the capturing process, but this
// can easily be software compensated. (By adjusting the before/after ratio.)
//--------------------------------------------------------------------------------
//
// 12/29/2010 - Ian Davis (IED) - Verilog version, changed to use LUT based
// masked comparisons, and other cleanups created - mygizmos.org
//
`timescale 1ns/100ps
module stage(
clock, reset, dataIn, validIn,
wrenb, din,
wrConfig, config_data,
arm, demux_mode, level,
// outputs...
run, match);
parameter TRUE = 1'b1;
parameter FALSE = 1'b0;
input clock, reset;
input validIn;
input [31:0] dataIn; // Channel data...
input wrenb; // LUT update write enb
input [7:0] din; // LUT update data. All 8 LUT's are updated simultaneously.
input wrConfig; // Write the trigger config register
input [31:0] config_data; // Data to write into trigger config regs
input arm;
input demux_mode;
input [1:0] level;
output run;
output match;
//
// Registers...
//
reg [27:0] configRegister, next_configRegister;
reg [15:0] counter, next_counter;
reg [31:0] shiftRegister, next_shiftRegister;
reg match32Register, next_match32Register;
reg run, next_run;
reg match, next_match;
//
// Useful decodes...
//
wire cfgStart = configRegister[27];
wire cfgSerial = configRegister[26];
wire [4:0] cfgChannel = configRegister[24:20];
wire [1:0] cfgLevel = configRegister[17:16];
wire [15:0] cfgDelay = configRegister[15:0];
//
// Handle mask, value & config register write requests
//
always @ (posedge clock)
begin
configRegister = next_configRegister;
end
always @*
begin
#1;
next_configRegister = (wrConfig) ? config_data[27:0] : configRegister;
end
//
// Use shift register or dataIn depending on configuration...
//
wire [31:0] testValue = (cfgSerial) ? shiftRegister : dataIn;
//
// Do LUT table based comparison...
//
wire [7:0] matchLUT;
trigterm_4bit byte0 (testValue[3:0], clock, wrenb, din[0], dout0, matchLUT[0]);
trigterm_4bit byte1 (testValue[7:4], clock, wrenb, din[1], dout1, matchLUT[1]);
trigterm_4bit byte2 (testValue[11:8], clock, wrenb, din[2], dout2, matchLUT[2]);
trigterm_4bit byte3 (testValue[15:12], clock, wrenb, din[3], dout3, matchLUT[3]);
trigterm_4bit byte4 (testValue[19:16], clock, wrenb, din[4], dout4, matchLUT[4]);
trigterm_4bit byte5 (testValue[23:20], clock, wrenb, din[5], dout5, matchLUT[5]);
trigterm_4bit byte6 (testValue[27:24], clock, wrenb, din[6], dout6, matchLUT[6]);
trigterm_4bit byte7 (testValue[31:28], clock, wrenb, din[7], dout7, matchLUT[7]);
wire matchL16 = &matchLUT[3:0];
wire matchH16 = &matchLUT[7:4];
//
// In demux mode only one half must match, in normal mode both words must match...
//
always @(posedge clock)
begin
match32Register = next_match32Register;
end
always @*
begin
#1;
if (demux_mode)
next_match32Register = matchL16 | matchH16;
else next_match32Register = matchL16 & matchH16;
end
//
// Select serial channel based on cfgChannel...
//
wire serialChannelL16 = dataIn[{1'b0,cfgChannel[3:0]}];
wire serialChannelH16 = dataIn[{1'b1,cfgChannel[3:0]}];
//
// Shift in bit from selected channel whenever dataIn is ready...
always @(posedge clock)
begin
shiftRegister = next_shiftRegister;
end
always @*
begin
#1;
next_shiftRegister = shiftRegister;
if (validIn)
if (demux_mode) // in demux mode two bits come in per sample
next_shiftRegister = {shiftRegister,serialChannelH16,serialChannelL16};
else next_shiftRegister = {shiftRegister, (cfgChannel[4]) ? serialChannelH16 : serialChannelL16};
end
//
// Trigger state machine...
//
parameter [1:0]
OFF = 2'h0,
ARMED = 2'h1,
MATCHED = 2'h2;
reg [1:0] state, next_state;
initial state = OFF;
always @(posedge clock or posedge reset)
begin
if (reset)
begin
state = OFF;
counter = 0;
match = FALSE;
run = FALSE;
end
else
begin
state = next_state;
counter = next_counter;
match = next_match;
run = next_run;
end
end
always @*
begin
#1;
next_state = state;
next_counter = counter;
next_match = FALSE;
next_run = FALSE;
case (state) // synthesis parallel_case
OFF :
begin
if (arm) next_state = ARMED;
end
ARMED :
begin
next_counter = cfgDelay;
if (match32Register && (level >= cfgLevel))
next_state = MATCHED;
end
MATCHED :
begin
if (validIn)
begin
next_counter = counter-1'b1;
if (~|counter)
begin
next_run = cfgStart;
next_match = ~cfgStart;
next_state = OFF;
end
end
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 10, K = 105, MOD = 998244353; int p[N][K], dp[N][K], a[N], ans[N] = {1}; int n, k, len; int sum(int l, int r, int x) { l = max(l, 1); r = min(r, n); return p[r][x] - p[l - 1][x]; } int main() { cin >> n >> k >> len; for (int i = 1; i <= n; i++) { cin >> a[i]; if (a[i] == -1) a[i]++; p[i][a[i]]++; for (int j = 0; j <= k; j++) { p[i][j] += p[i - 1][j]; } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= k; j++) { if (a[i] == 0 || a[i] == j) { dp[i][j] = ans[i - 1]; if (sum(i - len + 1, i, j) + sum(i - len + 1, i, 0) == len) { dp[i][j] -= ans[i - len] - dp[i - len][j]; if (dp[i][j] < 0) dp[i][j] += MOD; if (dp[i][j] >= MOD) dp[i][j] -= MOD; } } } for (int j = 1; j <= k; j++) { ans[i] += dp[i][j]; if (ans[i] >= MOD) ans[i] -= MOD; } } cout << ans[n] << n ; } |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : V5-Block Plus for PCI Express
// File : tlm_rx_data_snk_bar.v
//--------------------------------------------------------------------------------
//--------------------------------------------------------------------------------
/*****************************************************************************
* Description : Rx Data Sink bar hit communication
*
* Hierarchical :
*
* Functional :
* Contructs the bar check fields, and passes hit information on
*
****************************************************************************/
`timescale 1ns/1ps
`ifndef TCQ
`define TCQ 1
`endif
`ifndef AS
module tlm_rx_data_snk_bar #(
parameter DW = 32, // Data width
parameter BARW = 7) // BAR-hit width
(
input clk_i,
input reset_i,
output reg [63:0] check_raddr_o,
output reg check_rmem32_o,
output reg check_rmem64_o,
output reg check_rio_o,
output reg check_rdev_id_o,
output reg check_rbus_id_o,
output reg check_rfun_id_o,
input [BARW-1:0] check_rhit_bar_i,
input check_rhit_i,
output [BARW-1:0] check_rhit_bar_o,
output check_rhit_o,
output check_rhit_src_rdy_o,
output check_rhit_ack_o,
output check_rhit_lock_o,
input [31:0] addr_lo_i, // 32b addr high word
input [31:0] addr_hi_i, // 32b addr high word
input [8:0] fulltype_oh_i, // Packet data type
input [2:0] routing_i, // routing
input mem64_i, // 64b memory access?
input [15:0] req_id_i, // requester ID
input [15:0] req_id_cpl_i, // req ID when pkt == cpl
input eval_check_i, // latch the formatting check
input rhit_lat3_i, // Is BAR-hit latency 3 clocks?
input legacy_mode_i
);
localparam CHECK_IO_BAR_HIT_EN = 1'b1;
//---------------------------------------------------------------------------
// PCI Express constants
//---------------------------------------------------------------------------
// Bit taps for one-hot Full Type
localparam MEM_BIT = 8;
localparam ADR_BIT = 7;
localparam MRD_BIT = 6;
localparam MWR_BIT = 5;
localparam MLK_BIT = 4;
localparam IO_BIT = 3;
localparam CFG_BIT = 2;
localparam MSG_BIT = 1;
localparam CPL_BIT = 0;
// Route
localparam ROUTE_BY_ID = 3'b010;
wire [63:0] addr_64b = {addr_hi_i, addr_lo_i};
reg [63:0] check_raddr_d;
reg check_rmem32_d;
reg check_rmem64_d;
reg check_rmemlock_d;
reg check_rmemlock_d1a;
reg check_rio_d;
reg check_rdev_id_d;
reg check_rbus_id_d;
reg check_rfun_id_d;
reg eval_check_q1, eval_check_q2, eval_check_q3, eval_check_q4;
reg sent_check_q2, sent_check_q3, sent_check_q4;
reg lock_check_q2, lock_check_q3, lock_check_q4;
// Check if endpoint is the correct recipient
//---------------------------------------------------------------------------
// On every request received, except implicitly routed messages, check if:
// 1. the endpoint is the right recipient by passing to the CMM for checking:
// . for Mem, IO and Cfg: the destination addr (checked with BARs)
// . for Messages:
// a. the req_id, if TLP was routed by ID
// b. the address, if TLP was routed by addr
// c. if dest is not RC, the endpoint is the implicit recipient
// . for Completions: the req_id
// 2. the type is valid
// 3. for Messages: msg_code and routing are valid
//
// Since the invalid type won't trigger the 1. check, it will be detected by
// the non assertion of check_rhit_i by the CMM
// => check 2. is redundant with check 1.
//
// Note: Future possible enhancement
// . check 3. may also be merged with 1., but that will affect the timing of
// the live check_*_o signals provided to the CMM
// => to be considered if those outputs get registered
//
// No need to check:
// . silently dropped: Unlock
// . passed on : User messages (Vendor_Defined)
//---------------------------------------------------------------------------
// Timing is tight here at 250 MHz -> split the calculations out from the CE
// and return to 0
// This also allows for a blocking default assignment, which makes the code
// easier to follow
always @* begin
check_raddr_d = (fulltype_oh_i[MSG_BIT] ? {req_id_i,48'h0} : 0) |
(fulltype_oh_i[CPL_BIT] ? {req_id_cpl_i,48'h0} : 0) |
(fulltype_oh_i[ADR_BIT] ? addr_64b : 0);
check_rbus_id_d = (fulltype_oh_i[MSG_BIT] && (routing_i == ROUTE_BY_ID)) ||
fulltype_oh_i[CPL_BIT];
check_rdev_id_d = (fulltype_oh_i[MSG_BIT] && (routing_i == ROUTE_BY_ID)) ||
fulltype_oh_i[CPL_BIT];
check_rfun_id_d = (fulltype_oh_i[MSG_BIT] && (routing_i == ROUTE_BY_ID)) ||
fulltype_oh_i[CPL_BIT];
check_rmem32_d = fulltype_oh_i[MEM_BIT] && !mem64_i;
check_rmem64_d = fulltype_oh_i[MEM_BIT] && mem64_i;
check_rmemlock_d= fulltype_oh_i[MLK_BIT];
check_rio_d = fulltype_oh_i[IO_BIT] && CHECK_IO_BAR_HIT_EN;
// No checks on CFG: CMM captures bus and dev ids for that function
end
always @(posedge clk_i) begin
if (eval_check_i) begin
check_raddr_o <= #`TCQ check_raddr_d;
end
end
always @(posedge clk_i) begin
if (reset_i) begin
check_rmem32_o <= #`TCQ 0;
check_rmem64_o <= #`TCQ 0;
check_rmemlock_d1a <= #`TCQ 0;
check_rio_o <= #`TCQ 0;
check_rbus_id_o <= #`TCQ 0;
check_rdev_id_o <= #`TCQ 0;
check_rfun_id_o <= #`TCQ 0;
// Our calculation from above is ready
end else if (eval_check_i) begin
check_rmem32_o <= #`TCQ check_rmem32_d;
check_rmem64_o <= #`TCQ check_rmem64_d;
check_rmemlock_d1a <= #`TCQ check_rmemlock_d;
check_rio_o <= #`TCQ check_rio_d;
check_rbus_id_o <= #`TCQ check_rbus_id_d;
check_rdev_id_o <= #`TCQ check_rdev_id_d;
check_rfun_id_o <= #`TCQ check_rfun_id_d;
// these signals all imply src_rdy, return to zero
end else begin
check_rmem32_o <= #`TCQ 0;
check_rmem64_o <= #`TCQ 0;
check_rmemlock_d1a <= #`TCQ 0;
check_rio_o <= #`TCQ 0;
check_rbus_id_o <= #`TCQ 0;
check_rdev_id_o <= #`TCQ 0;
check_rfun_id_o <= #`TCQ 0;
end
end
// Need a pipe to time the return back from the CMM, since
// 32 and 64 signal the CMM to start calculating at
// different times
// Eval is when the check is occuring
// Sent is if we actually sent one (and expect a response)
//---------------------------------------------------------
always @(posedge clk_i) begin
eval_check_q1 <= #`TCQ eval_check_i;
eval_check_q2 <= #`TCQ eval_check_q1;
eval_check_q3 <= #`TCQ eval_check_q2;
eval_check_q4 <= #`TCQ eval_check_q3;
sent_check_q2 <= #`TCQ eval_check_q1 &&
(check_rmem32_o ||
check_rmem64_o ||
check_rio_o ||
check_rbus_id_o ||
check_rdev_id_o ||
check_rfun_id_o);
sent_check_q3 <= #`TCQ sent_check_q2;
sent_check_q4 <= #`TCQ sent_check_q3;
lock_check_q2 <= #`TCQ check_rmemlock_d1a;
lock_check_q3 <= #`TCQ lock_check_q2;
lock_check_q4 <= #`TCQ lock_check_q3;
end
// Values from the CMM
assign check_rhit_bar_o = check_rhit_bar_i;
assign check_rhit_o = check_rhit_i;
// Result of our internal timing circuit
assign check_rhit_src_rdy_o = rhit_lat3_i ? eval_check_q4 : eval_check_q3;
assign check_rhit_ack_o = rhit_lat3_i ? sent_check_q4 : sent_check_q3;
assign check_rhit_lock_o = rhit_lat3_i ? lock_check_q4 : lock_check_q3;
endmodule
`endif
|
// $Id: c_gather.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// module for extracting a set of bits from an input word (result is
// concatenation of these bits)
//==============================================================================
module c_gather
(data_in, data_out);
// width of input word
parameter in_width = 32;
function automatic integer pop_count(input [0:in_width-1] argument);
integer i;
begin
pop_count = 0;
for(i = 0; i < in_width; i = i + 1)
pop_count = pop_count + argument[i];
end
endfunction
// mask specifying which bits to extract
parameter [0:in_width-1] mask = {in_width{1'b1}};
// width of result
localparam out_width = pop_count(mask);
// input word
input [0:in_width-1] data_in;
// result
output [0:out_width-1] data_out;
reg [0:out_width-1] data_out;
integer idx1, idx2;
always @(data_in)
begin
idx2 = 0;
for(idx1 = 0; idx1 < in_width; idx1 = idx1 + 1)
if(mask[idx1] == 1'b1)
begin
data_out[idx2] = data_in[idx1];
idx2 = idx2 + 1;
end
end
endmodule
|
module test(out);
output out;
`define wow
`define nest_one
`define second_nest
`define nest_two
`ifdef wow
initial $display("wow is defined");
`ifdef nest_one
initial $display("nest_one is defined");
`ifdef nest_two
initial $display("nest_two is defined");
`else
initial $display("nest_two is not defined");
`endif
`else
initial $display("nest_one is not defined");
`endif
`else
initial $display("wow is not defined");
`ifdef second_nest
initial $display("second_nest is defined");
`else
initial $display("second_nest is not defined");
`endif
`endif
endmodule
// Local Variables:
// verilog-auto-lineup: all
// verilog-auto-endcomments: t
// verilog-auto-indent-on-newline: t
// verilog-auto-lineup: all
// verilog-auto-newline: nil
// verilog-case-indent: 2
// verilog-highlight-p1800-keywords: nil
// verilog-indent-begin-after-if: t
// verilog-indent-level: 2
// verilog-indent-level-behavioral: 2
// verilog-indent-level-declaration: 2
// verilog-indent-level-directive: 2
// verilog-indent-level-module: 2
// verilog-minimum-comment-distance: 40
// verilog-tab-always-indent: t
// End:
|
#include <bits/stdc++.h> using namespace std; long long fact[1000010]; long long m = 1e9 + 7; long long me(long long a, long long b, long long m) { long long ans = 1; while (b > 0) { if (b % 2 == 1) { ans = (ans % m * a % m) % m; } a = (a * a) % m; b /= 2; } return ans % m; } bool check(long long x, long long a, long long b) { while (x > 0) { int dg = x % 10; if (dg != a && dg != b) return false; x /= 10; } return true; } long long ncr(long long n, long long r) { long long fn = fact[n]; long long tf = fact[r] * fact[n - r]; tf = tf % m; tf = me(tf, m - 2, m); fn = (tf % m * fn % m) % m; return fn % m; } int main() { fact[0] = 1; for (long long i = 1; i <= 1000001; i++) { fact[i] = (fact[i - 1] * i) % m; } int n, a, b; cin >> a >> b >> n; if (a == b) { if (check(n * a, a, b)) { cout << 1 n ; } else cout << 0 n ; return 0; } long long ans = 0; for (long long i = 0; i <= n; i++) { long long tmp = i * a + (n - i) * b; if (check(tmp, a, b)) { ans += ncr(n, i); ans %= m; } } cout << ans << n ; return 0; } |
// PentEvo project (c) NedoPC 2012
//
// SPI hub: arbitrating between AVR and Z80 accesses to SDcard via SPI.
`include "../include/tune.v"
module spihub(
input wire fclk,
input wire rst_n,
// pins to SDcard
output reg sdcs_n,
output wire sdclk,
output wire sddo,
input wire sddi,
// zports SDcard iface
input wire zx_sdcs_n_val,
input wire zx_sdcs_n_stb,
input wire zx_sd_start,
input wire [7:0] zx_sd_datain,
output wire [7:0] zx_sd_dataout,
// slavespi SDcard iface
input wire avr_lock_in,
output reg avr_lock_out,
input wire avr_sdcs_n,
input wire avr_sd_start,
input wire [7:0] avr_sd_datain,
output wire [7:0] avr_sd_dataout
);
// spi2 module control
wire [7:0] sd_datain;
wire [7:0] sd_dataout;
wire sd_start;
// single dataout to all ifaces
assign zx_sd_dataout = sd_dataout;
assign avr_sd_dataout = sd_dataout;
// spi2 module itself
spi2 spi2(
.clock(fclk),
.sck(sdclk),
.sdo(sddo ),
.sdi(sddi ),
.start(sd_start ),
.din (sd_datain ),
.dout (sd_dataout),
.speed(2'b00)
);
// control locking/arbitrating between ifaces
always @(posedge fclk, negedge rst_n)
if( !rst_n )
avr_lock_out <= 1'b0;
else // posedge fclk
begin
if( sdcs_n )
avr_lock_out <= avr_lock_in;
end
// control cs_n to SDcard
always @(posedge fclk, negedge rst_n)
if( !rst_n )
sdcs_n <= 1'b1;
else // posedge fclk
begin
if( avr_lock_out )
sdcs_n <= avr_sdcs_n;
else // !avr_lock_out
if( zx_sdcs_n_stb )
sdcs_n <= zx_sdcs_n_val;
end
// control start and outgoing data to spi2
assign sd_start = avr_lock_out ? avr_sd_start : zx_sd_start;
//
assign sd_datain = avr_lock_out ? avr_sd_datain : zx_sd_datain;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02/13/2016 08:25:37 PM
// Design Name:
// Module Name: Multiplier
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Multiplier(
input [3:0] A,
input [3:0] B,
output [7:0] R
);
wire P00, P01, P02, P03, P10, P11, P12, P13, P20, P21, P22, P23, P30, P31, P32, P33;
assign P00 = A[0] & B[0];
assign P01 = A[1] & B[0];
assign P02 = A[2] & B[0];
assign P03 = A[3] & B[0];
assign P10 = A[0] & B[1];
assign P11 = A[1] & B[1];
assign P12 = A[2] & B[1];
assign P13 = A[3] & B[1];
assign P20 = A[0] & B[2];
assign P21 = A[1] & B[2];
assign P22 = A[2] & B[2];
assign P23 = A[3] & B[2];
assign P30 = A[0] & B[3];
assign P31 = A[1] & B[3];
assign P32 = A[2] & B[3];
assign P33 = A[3] & B[3];
wire [3:0] Part1_2;
wire [3:0] Part2_3;
wire Cout1_2, Cout2_3;
FullAdder Part1 (
.A({1'b0, P03, P02, P01}),
.B({P13, P12, P11, P10}),
.Operation(1'b0),
.S(Part1_2),
.Cout(Cout1_2)
);
FullAdder Part2 (
.A({P23, P22, P21, P20}),
.B({Cout1_2, Part1_2[3:1]}),
.Operation(1'b0),
.S(Part2_3),
.Cout(Cout2_3)
);
wire [3:0] temp;
FullAdder Part3 (
.A({P33, P32, P31, P30}),
.B({Cout2_3, Part2_3[3:1]}),
.Operation(1'b0),
.S(temp ),
.Cout(R[7])
);
assign R[6:3] = temp;
assign R[0] = P00;
assign R[1] = Part1_2[0];
assign R[2] = Part2_3[0];
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; int ind = 0; vector<int> v; scanf( %d , &n); for (int i = 0; i < n; i++) { int temp; scanf( %d , &temp); v.push_back(temp); } sort(v.begin(), v.end()); for (int i = 0; i < n; i++) { if (v[i] - ind == 1) { ind++; } else { break; } } printf( %d , ind + 1); } |
#include <bits/stdc++.h> using namespace std; template <typename T> inline bool chkmin(T &a, const T &b) { return a > b ? a = b, 1 : 0; } template <typename T> inline bool chkmax(T &a, const T &b) { return a < b ? a = b, 1 : 0; } const int oo = 0x3f3f3f3f; const int maxn = 200100; int n; int a[maxn + 5][2]; bool bbig[maxn + 5]; bool take[maxn + 5][2]; int delta[maxn + 5][2]; int pos[maxn + 5]; bool vis[maxn + 5]; long long income[2]; inline void pick(bool player, int id) { income[player] += a[id][player]; vis[id] = 1; } int main() { scanf( %d , &n); for (int i = (0), i_end_ = (n); i < i_end_; ++i) scanf( %d%d%d%d , a[i], a[i] + 1, a[n + i], a[n + i] + 1); for (int i = (0), i_end_ = (n); i < i_end_; ++i) { delta[i][0] = a[i][0] - a[n + i][1]; delta[i][1] = a[i][1] - a[n + i][0]; if (a[n + i][0] + a[n + i][1] >= a[i][0] + a[i][1]) bbig[i] = 1; for (int j = (0), j_end_ = (2); j < j_end_; ++j) take[i][j] = !(delta[i][j] <= 0 && -delta[i][!j] >= delta[i][j]); } for (int i = (0), i_end_ = (n << 1); i < i_end_; ++i) pos[i] = i; sort(pos, pos + (n << 1), [&](int first, int second) { return a[first][0] + a[first][1] > a[second][0] + a[second][1]; }); int p[2] = {0, 0}; for (int i = (0), i_end_ = (n << 1); i < i_end_; ++i) { bool now = i & 1; while (p[now] < (n << 1)) { int first = pos[p[now]]; if (!vis[first]) { if (first >= n) { if (vis[first - n]) { pick(now, first); break; } } else if (take[first][now]) { pick(now, first); if (bbig[first]) pick(!now, first + n); else break; } } ++p[now]; } } printf( %I64d n , income[0] - income[1]); return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, k, A, B, ans = 0; long long fmin() { long long pros = (n - (n / k)) * A; if (B < pros) { n = n / k; return B; } else { n = n / k; return pros; } } int main() { cin >> n; cin >> k; cin >> A; cin >> B; if (k == 1) { cout << (n - 1) * A; return 0; } while (n != 1) { if (n >= k) { if (n % k == 0) { ans += fmin(); } else { long long t = (n % k); n = n - t; ans += (A * t); } } else { ans = ans + (n - 1) * A; n = 1; } } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; long long int a[200005], b[200005], c[200005]; class Myfirst { private: string *name; long long int *age; public: long long int gcd(long long int a, long long int b) { if (b == 0) return a; a %= b; return gcd(b, a); } long long int exte_gcd(long long int a, long long int b, long long int &x, long long int &y) { if (b == 0) { x = 1; y = 0; return a; } long long int x1, y1; long long int d = exte_gcd(b, a % b, x1, y1); x = y1; y = x1 - y1 * (a / b); return d; } long long int powe(long long int d, long long int s) { if (s == 1) return d; else if (s == 0) return 1; else { long long int u, v = d; for (u = 1; u < s; u++) d = d * v; return d; } } long long int count_divisors(long long int b) { long long int i, count = 0, n = 1; for (i = 2; i * i <= b; i++) { count = 0; if (b % i == 0) { while (b % i == 0) { b = b / i; count++; } n = n * (count + 1); } } if (b > 1) n = 2 * n; return n; } long long int bigmod(long long int a, long long int b, long long int mod) { if (b == 0) return 1; long long int x = bigmod(a, b / 2, mod); x = (x * x) % mod; if (b % 2) x = (x * a) % mod; return x; } long long int phi(long long int n) { double result = n; for (long long int p = 2; p * p <= n; ++p) { if (n % p == 0) { while (n % p == 0) n /= p; result *= (1.0 - (1.0 / (double)p)); } } if (n > 1) result *= (1.0 - (1.0 / (double)n)); return (long long int)result; } void solve() { long long int t; t = 1; while (t--) { long long int n, m, k, i, j, A, B; cin >> n; for (i = 1; i <= n; i++) cin >> a[i]; cin >> m; for (i = 1; i <= m; i++) cin >> b[i]; cin >> k; for (i = 1; i <= k; i++) cin >> c[i]; cin >> A >> B; sort(a + 1, a + n + 1); sort(b + 1, b + m + 1); sort(c + 1, c + k + 1); double ans; ans = ((c[1] * 1.0) / b[m]) * ((A * 1.0) / B); ans += 1.0; ans = sqrt(1.0 / ans); cout << setprecision(10); cout << ans * a[n]; } } }; int main() { Myfirst *prg = new Myfirst(); prg->solve(); } |
// pr_region_default_Top_0.v
// Generated using ACDS version 17.1 240
`timescale 1 ps / 1 ps
module pr_region_default_Top_0 (
input wire clock, // clock.clk
output wire [5:0] io_M_AXI_0_AWID, // io_M_AXI_0.awid
output wire [31:0] io_M_AXI_0_AWUSER, // .awuser
output wire [31:0] io_M_AXI_0_AWADDR, // .awaddr
output wire [7:0] io_M_AXI_0_AWLEN, // .awlen
output wire [2:0] io_M_AXI_0_AWSIZE, // .awsize
output wire [1:0] io_M_AXI_0_AWBURST, // .awburst
output wire io_M_AXI_0_AWLOCK, // .awlock
output wire [3:0] io_M_AXI_0_AWCACHE, // .awcache
output wire [2:0] io_M_AXI_0_AWPROT, // .awprot
output wire [3:0] io_M_AXI_0_AWQOS, // .awqos
output wire io_M_AXI_0_AWVALID, // .awvalid
input wire io_M_AXI_0_AWREADY, // .awready
output wire [5:0] io_M_AXI_0_ARID, // .arid
output wire [31:0] io_M_AXI_0_ARUSER, // .aruser
output wire [31:0] io_M_AXI_0_ARADDR, // .araddr
output wire [7:0] io_M_AXI_0_ARLEN, // .arlen
output wire [2:0] io_M_AXI_0_ARSIZE, // .arsize
output wire [1:0] io_M_AXI_0_ARBURST, // .arburst
output wire io_M_AXI_0_ARLOCK, // .arlock
output wire [3:0] io_M_AXI_0_ARCACHE, // .arcache
output wire [2:0] io_M_AXI_0_ARPROT, // .arprot
output wire [3:0] io_M_AXI_0_ARQOS, // .arqos
output wire io_M_AXI_0_ARVALID, // .arvalid
input wire io_M_AXI_0_ARREADY, // .arready
output wire [511:0] io_M_AXI_0_WDATA, // .wdata
output wire [63:0] io_M_AXI_0_WSTRB, // .wstrb
output wire io_M_AXI_0_WLAST, // .wlast
output wire io_M_AXI_0_WVALID, // .wvalid
input wire io_M_AXI_0_WREADY, // .wready
input wire [5:0] io_M_AXI_0_RID, // .rid
input wire [31:0] io_M_AXI_0_RUSER, // .ruser
input wire [511:0] io_M_AXI_0_RDATA, // .rdata
input wire [1:0] io_M_AXI_0_RRESP, // .rresp
input wire io_M_AXI_0_RLAST, // .rlast
input wire io_M_AXI_0_RVALID, // .rvalid
output wire io_M_AXI_0_RREADY, // .rready
input wire [5:0] io_M_AXI_0_BID, // .bid
input wire [31:0] io_M_AXI_0_BUSER, // .buser
input wire [1:0] io_M_AXI_0_BRESP, // .bresp
input wire io_M_AXI_0_BVALID, // .bvalid
output wire io_M_AXI_0_BREADY, // .bready
input wire [6:0] io_S_AVALON_address, // io_S_AVALON.address
output wire [31:0] io_S_AVALON_readdata, // .readdata
input wire io_S_AVALON_chipselect, // .chipselect
input wire io_S_AVALON_write, // .write
input wire io_S_AVALON_read, // .read
input wire [31:0] io_S_AVALON_writedata, // .writedata
input wire reset // reset.reset
);
Top top_0 (
.clock (clock), // input, width = 1, clock.clk
.reset (reset), // input, width = 1, reset.reset
.io_S_AVALON_address (io_S_AVALON_address), // input, width = 7, io_S_AVALON.address
.io_S_AVALON_readdata (io_S_AVALON_readdata), // output, width = 32, .readdata
.io_S_AVALON_chipselect (io_S_AVALON_chipselect), // input, width = 1, .chipselect
.io_S_AVALON_write (io_S_AVALON_write), // input, width = 1, .write
.io_S_AVALON_read (io_S_AVALON_read), // input, width = 1, .read
.io_S_AVALON_writedata (io_S_AVALON_writedata), // input, width = 32, .writedata
.io_M_AXI_0_AWID (io_M_AXI_0_AWID), // output, width = 6, io_M_AXI_0.awid
.io_M_AXI_0_AWUSER (io_M_AXI_0_AWUSER), // output, width = 32, .awuser
.io_M_AXI_0_AWADDR (io_M_AXI_0_AWADDR), // output, width = 32, .awaddr
.io_M_AXI_0_AWLEN (io_M_AXI_0_AWLEN), // output, width = 8, .awlen
.io_M_AXI_0_AWSIZE (io_M_AXI_0_AWSIZE), // output, width = 3, .awsize
.io_M_AXI_0_AWBURST (io_M_AXI_0_AWBURST), // output, width = 2, .awburst
.io_M_AXI_0_AWLOCK (io_M_AXI_0_AWLOCK), // output, width = 1, .awlock
.io_M_AXI_0_AWCACHE (io_M_AXI_0_AWCACHE), // output, width = 4, .awcache
.io_M_AXI_0_AWPROT (io_M_AXI_0_AWPROT), // output, width = 3, .awprot
.io_M_AXI_0_AWQOS (io_M_AXI_0_AWQOS), // output, width = 4, .awqos
.io_M_AXI_0_AWVALID (io_M_AXI_0_AWVALID), // output, width = 1, .awvalid
.io_M_AXI_0_AWREADY (io_M_AXI_0_AWREADY), // input, width = 1, .awready
.io_M_AXI_0_ARID (io_M_AXI_0_ARID), // output, width = 6, .arid
.io_M_AXI_0_ARUSER (io_M_AXI_0_ARUSER), // output, width = 32, .aruser
.io_M_AXI_0_ARADDR (io_M_AXI_0_ARADDR), // output, width = 32, .araddr
.io_M_AXI_0_ARLEN (io_M_AXI_0_ARLEN), // output, width = 8, .arlen
.io_M_AXI_0_ARSIZE (io_M_AXI_0_ARSIZE), // output, width = 3, .arsize
.io_M_AXI_0_ARBURST (io_M_AXI_0_ARBURST), // output, width = 2, .arburst
.io_M_AXI_0_ARLOCK (io_M_AXI_0_ARLOCK), // output, width = 1, .arlock
.io_M_AXI_0_ARCACHE (io_M_AXI_0_ARCACHE), // output, width = 4, .arcache
.io_M_AXI_0_ARPROT (io_M_AXI_0_ARPROT), // output, width = 3, .arprot
.io_M_AXI_0_ARQOS (io_M_AXI_0_ARQOS), // output, width = 4, .arqos
.io_M_AXI_0_ARVALID (io_M_AXI_0_ARVALID), // output, width = 1, .arvalid
.io_M_AXI_0_ARREADY (io_M_AXI_0_ARREADY), // input, width = 1, .arready
.io_M_AXI_0_WDATA (io_M_AXI_0_WDATA), // output, width = 512, .wdata
.io_M_AXI_0_WSTRB (io_M_AXI_0_WSTRB), // output, width = 64, .wstrb
.io_M_AXI_0_WLAST (io_M_AXI_0_WLAST), // output, width = 1, .wlast
.io_M_AXI_0_WVALID (io_M_AXI_0_WVALID), // output, width = 1, .wvalid
.io_M_AXI_0_WREADY (io_M_AXI_0_WREADY), // input, width = 1, .wready
.io_M_AXI_0_RID (io_M_AXI_0_RID), // input, width = 6, .rid
.io_M_AXI_0_RUSER (io_M_AXI_0_RUSER), // input, width = 32, .ruser
.io_M_AXI_0_RDATA (io_M_AXI_0_RDATA), // input, width = 512, .rdata
.io_M_AXI_0_RRESP (io_M_AXI_0_RRESP), // input, width = 2, .rresp
.io_M_AXI_0_RLAST (io_M_AXI_0_RLAST), // input, width = 1, .rlast
.io_M_AXI_0_RVALID (io_M_AXI_0_RVALID), // input, width = 1, .rvalid
.io_M_AXI_0_RREADY (io_M_AXI_0_RREADY), // output, width = 1, .rready
.io_M_AXI_0_BID (io_M_AXI_0_BID), // input, width = 6, .bid
.io_M_AXI_0_BUSER (io_M_AXI_0_BUSER), // input, width = 32, .buser
.io_M_AXI_0_BRESP (io_M_AXI_0_BRESP), // input, width = 2, .bresp
.io_M_AXI_0_BVALID (io_M_AXI_0_BVALID), // input, width = 1, .bvalid
.io_M_AXI_0_BREADY (io_M_AXI_0_BREADY) // output, width = 1, .bready
);
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:%version
// \ \ Application: MIG
// / / Filename: mig_7series_v2_3_poc_pd.v
// /___/ /\ Date Last Modified: $$
// \ \ / \ Date Created:Tue 15 Jan 2014
// \___\/\___\
//
//Device: Virtex-7
//Design Name: DDR3 SDRAM
//Purpose: IDDR used as phase detector. The pos_edge and neg_edge stuff
// prevents any noise that could happen when the phase shift clock is very
// nearly aligned to the fabric clock.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v2_3_poc_pd #
(parameter POC_USE_METASTABLE_SAMP = "FALSE",
parameter SIM_CAL_OPTION = "NONE",
parameter TCQ = 100)
(/*AUTOARG*/
// Outputs
pd_out,
// Inputs
iddr_rst, clk, kclk, mmcm_ps_clk
);
input iddr_rst;
input clk;
input kclk;
input mmcm_ps_clk;
wire q1;
IDDR #
(.DDR_CLK_EDGE ("OPPOSITE_EDGE"),
.INIT_Q1 (1'b0),
.INIT_Q2 (1'b0),
.SRTYPE ("SYNC"))
u_phase_detector
(.Q1 (q1),
.Q2 (),
.C (mmcm_ps_clk),
.CE (1'b1),
.D (kclk),
.R (iddr_rst),
.S (1'b0));
// Path from q1 to xxx_edge_samp must be constrained to be less than 1/4 cycle. FIXME
reg pos_edge_samp;
generate if (SIM_CAL_OPTION == "NONE" || POC_USE_METASTABLE_SAMP == "TRUE") begin : no_eXes
always @(posedge clk) pos_edge_samp <= #TCQ q1;
end else begin : eXes
reg q1_delayed;
reg rising_clk_seen;
always @(posedge mmcm_ps_clk) begin
rising_clk_seen <= 1'b0;
q1_delayed <= 1'bx;
end
always @(posedge clk) begin
rising_clk_seen = 1'b1;
if (rising_clk_seen) q1_delayed <= q1;
end
always @(posedge clk) begin
pos_edge_samp <= q1_delayed;
end
end endgenerate
reg pd_out_r;
always @(posedge clk) pd_out_r <= #TCQ pos_edge_samp;
output pd_out;
assign pd_out = pd_out_r;
endmodule // mic_7series_v2_3_poc_pd
|
#include <bits/stdc++.h> using namespace std; int main() { long long l1, r1, l2, r2, k, l, r; cin >> l1 >> r1 >> l2 >> r2 >> k; l = max(l1, l2); r = min(r1, r2); if (r < l) cout << 0; else if (l <= k && k <= r) cout << r - l; else cout << r - l + 1 << endl; return 0; } |
#include <bits/stdc++.h> using std::cin; using std::cout; using std::endl; const int maxn = 200005; long long a[maxn], b[maxn]; int n; int ans, base; std::map<std::pair<long long, long long>, int> mmp; long long gcd(long long x, long long y) { return y == 0 ? x : gcd(y, x % y); } int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= n; i++) cin >> b[i]; for (int i = 1; i <= n; i++) { if (a[i] == 0) { if (b[i] == 0) base++; } else { long long temp1 = b[i], temp2 = a[i]; if (temp1 < 0) temp1 = -temp1, temp2 = -temp2; else if (temp1 == 0) temp2 = 0; long long g = gcd(llabs(temp1), llabs(temp2)); if (g) temp1 /= g, temp2 /= g; mmp[std::make_pair(temp1, temp2)]++; } } for (auto it : mmp) { ans = std::max(ans, it.second); } cout << ans + base << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2005, K = 55, mod = 998244353; int n, k, b[N], f[2 * K][N], g[2 * K][N], C[N][N]; int main() { scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) scanf( %d , &b[i]); f[k][0] = 1; for (int i = 1; i <= n; i++) { memset(g, 0, sizeof(g)); for (int j = max(0, k - b[i - 1]); j <= 2 * k; j++) { int j2 = j + b[i - 1] - b[i] + 1, x = j + b[i - 1] - k; if (x < 0 || x > n || j2 > 2 * k) continue; for (int d = max(0, -j2); d < i; d++) { if (j2 < 0) (g[0][d + j2] += f[j][d]) %= mod; else (g[j2][d] += f[j][d]) %= mod; } } for (int j = 0; j < 2 * k; j++) for (int d = 1; d <= i; d++) (g[j + 1][d - 1] += g[j][d]) %= mod; for (int j = max(0, k - b[i - 1]); j <= 2 * k; j++) { int j2 = j + b[i - 1] - b[i], x = j + b[i - 1] - k; if (x < 0 || x > n || j2 < 0 || j2 > 2 * k) continue; for (int d = 0; d < i; d++) { (g[j2][d] += 1ll * f[j][d] * (d + x) % mod) %= mod; (g[j2][d + 1] += 1ll * f[j][d] * (d + 1) % mod) %= mod; } } swap(f, g); } C[0][0] = 1; for (int i = 1; i <= n; i++) { C[i][0] = C[i][i] = 1; for (int j = 1; j < n; j++) C[i][j] = (C[i - 1][j - 1] + C[i - 1][j]) % mod; } int ans = 0; for (int j = 0; j <= 2 * k; j++) { int x = b[n] + j - k; if (x < 0 || x > n) continue; for (int d = 0; d <= n - x; d++) (ans += 1ll * f[j][d] * C[n - x][d] % mod) %= mod; } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long mod = (1e9 + 7); const long long inf = (1e18 + 3); const long long N = 1e7 + 5; void no() { cout << -1 ; exit(0); } void yes() { cout << YES ; exit(0); } long long powmod(long long a, long long b) { long long res = 1; a %= mod; assert(b >= 0); for (; b; b >>= 1) { if (b & 1) res = res * a % mod; a = a * a % mod; } return res; } long long inv(long long a) { return powmod(a, mod - 2); } long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } long long mul(long long a, long long b) { return a * b % mod; } long long add(long long a, long long b) { return (a + b) % mod; } long long sub(long long a, long long b) { return (a - b + mod) % mod; } int main() { string s; cin >> s; long long cnt = 1, res = 0; for (auto i : s) { if (i == a ) cnt <<= 1, cnt %= mod; else res = add(res, cnt - 1); } cout << res; return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; int q, n, a[505]; int main() { cin >> q; while (q--) { cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; bool pd = 1; for (int i = 1; i < n; i++) { int xx = a[i] + 1; if (xx > n) xx = 1; if (xx != a[i + 1]) { pd = 0; break; } } if (pd) { cout << YES << endl; continue; } pd = 1; for (int i = 1; i < n; i++) { int xx = a[i] - 1; if (xx == 0) xx = n; if (xx != a[i + 1]) { pd = 0; break; } } if (pd) cout << YES << endl; else cout << NO << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long int s, x, y, a, b = 0; cin >> s >> x; int f = 1; if (s < x) f = 0; if (s == x) b = 2; y = s - x; if (y % 2 == 1) f = 0; if (f) { y /= 2, a = 1; while (x > 0 || y > 0) { if (x % 2 == 1) { if (y % 2 == 0) a *= 2; else f = 0; } x /= 2, y /= 2; } } a *= f; cout << a - b << endl; } |
// hub_mem
/*
-------------------------------------------------------------------------------
Copyright 2014 Parallax Inc.
This file is part of the hardware description for the Propeller 1 Design.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/
module hub_mem
(
input clk_cog,
input ena_bus,
input w,
input [3:0] wb,
input [13:0] a,
input [31:0] d,
output [31:0] q
);
// 8192 x 32 ram with byte-write enables ($0000..$7FFF)
reg [7:0] ram3 [8191:0];
reg [7:0] ram2 [8191:0];
reg [7:0] ram1 [8191:0];
reg [7:0] ram0 [8191:0];
reg [7:0] ram_q3;
reg [7:0] ram_q2;
reg [7:0] ram_q1;
reg [7:0] ram_q0;
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[3])
ram3[a[12:0]] <= d[31:24];
if (ena_bus && !a[13])
ram_q3 <= ram3[a[12:0]];
end
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[2])
ram2[a[12:0]] <= d[23:16];
if (ena_bus && !a[13])
ram_q2 <= ram2[a[12:0]];
end
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[1])
ram1[a[12:0]] <= d[15:8];
if (ena_bus && !a[13])
ram_q1 <= ram1[a[12:0]];
end
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[0])
ram0[a[12:0]] <= d[7:0];
if (ena_bus && !a[13])
ram_q0 <= ram0[a[12:0]];
end
// 4096 x 32 rom containing character definitions ($8000..$BFFF)
(* ram_init_file = "hub_rom_low.hex" *) reg [31:0] rom_low [4095:0];
reg [31:0] rom_low_q;
always @(posedge clk_cog)
if (ena_bus && a[13:12] == 2'b10)
rom_low_q <= rom_low[a[11:0]];
// 4096 x 32 rom containing sin table, log table, booter, and interpreter ($C000..$FFFF)
(* ram_init_file = "hub_rom_high.hex" *) reg [31:0] rom_high [4095:0];
reg [31:0] rom_high_q;
always @(posedge clk_cog)
if (ena_bus && a[13:12] == 2'b11)
rom_high_q <= rom_high[a[11:0]];
// memory output mux
reg [1:0] mem;
always @(posedge clk_cog)
if (ena_bus)
mem <= a[13:12];
assign q = !mem[1] ? {ram_q3, ram_q2, ram_q1, ram_q0}
: !mem[0] ? rom_low_q // comment out this line for DE0-Nano (sacrifices character rom to fit device)
: rom_high_q;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg _ranit;
reg [2:0] xor3;
reg [1:0] xor2;
reg [0:0] xor1;
reg [2:0] ma, mb;
reg [9:0] mc;
reg [4:0] mr1;
reg [30:0] mr2;
reg [67:0] sh1;
reg [67:0] shq;
wire foo, bar; assign {foo,bar} = 2'b1_0;
// surefire lint_off STMINI
initial _ranit = 0;
wire [4:0] cond_check = (( xor2 == 2'b11) ? 5'h1
: (xor2 == 2'b00) ? 5'h2
: (xor2 == 2'b01) ? 5'h3
: 5'h4);
wire ctrue = 1'b1 ? cond_check[1] : cond_check[0];
wire cfalse = 1'b0 ? cond_check[1] : cond_check[0];
wire cif = cond_check[2] ? cond_check[1] : cond_check[0];
wire cifn = (!cond_check[2]) ? cond_check[1] : cond_check[0];
wire [4:0] doubleconc = {1'b0, 1'b1, 1'b0, cond_check[0], 1'b1};
wire zero = 1'b0;
wire one = 1'b1;
wire [5:0] rep6 = {6{one}};
// verilator lint_off WIDTH
localparam [3:0] bug764_p11 = 1'bx;
// verilator lint_on WIDTH
always @ (posedge clk) begin
if (!_ranit) begin
_ranit <= 1;
if (rep6 != 6'b111111) $stop;
if (!one) $stop;
if (~one) $stop;
if (( 1'b0 ? 3'h3 : 1'b0 ? 3'h2 : 1'b1 ? 3'h1 : 3'h0) !== 3'h1) $stop;
// verilator lint_off WIDTH
if (( 8'h10 + 1'b0 ? 8'he : 8'hf) !== 8'he) $stop; // + is higher than ?
// verilator lint_on WIDTH
// surefire lint_off SEQASS
xor1 = 1'b1;
xor2 = 2'b11;
xor3 = 3'b111;
// verilator lint_off WIDTH
if (1'b1 & | (!xor3)) $stop;
// verilator lint_on WIDTH
if ({1{xor1}} != 1'b1) $stop;
if ({4{xor1}} != 4'b1111) $stop;
if (!(~xor1) !== ~(!xor1)) $stop;
if ((^xor1) !== 1'b1) $stop;
if ((^xor2) !== 1'b0) $stop;
if ((^xor3) !== 1'b1) $stop;
if (~(^xor2) !== 1'b1) $stop;
if (~(^xor3) !== 1'b0) $stop;
if ((^~xor1) !== 1'b0) $stop;
if ((^~xor2) !== 1'b1) $stop;
if ((^~xor3) !== 1'b0) $stop;
if ((~^xor1) !== 1'b0) $stop;
if ((~^xor2) !== 1'b1) $stop;
if ((~^xor3) !== 1'b0) $stop;
xor1 = 1'b0;
xor2 = 2'b10;
xor3 = 3'b101;
if ((^xor1) !== 1'b0) $stop;
if ((^xor2) !== 1'b1) $stop;
if ((^xor3) !== 1'b0) $stop;
if (~(^xor2) !== 1'b0) $stop;
if (~(^xor3) !== 1'b1) $stop;
if ((^~xor1) !== 1'b1) $stop;
if ((^~xor2) !== 1'b0) $stop;
if ((^~xor3) !== 1'b1) $stop;
if ((~^xor1) !== 1'b1) $stop;
if ((~^xor2) !== 1'b0) $stop;
if ((~^xor3) !== 1'b1) $stop;
// X propagation
if (!1'bx !== 1'bx) $stop;
if (~2'bx !== 2'bx) $stop;
if (-2'bx !== 2'bx) $stop;
if ((2'bxx + 2'b1) !== 2'bxx) $stop;
if ((2'bxx - 2'b1) !== 2'bxx) $stop;
if ((2'bxx * 2'b1) !== 2'bxx) $stop;
if ((2'bxx / 2'b1) !== 2'bxx) $stop;
if ((2'bxx % 2'b1) !== 2'bxx) $stop;
if ((2'sbxx * 2'sb1) !== 2'bxx) $stop;
if ((2'sbxx / 2'sb1) !== 2'bxx) $stop;
if ((2'sbxx % 2'sb1) !== 2'bxx) $stop;
if ((1'bx & 1'b1) !== 1'bx) $stop;
if ((1'bx & 1'b0) !== 1'b0) $stop;
if ((1'bx | 1'b0) !== 1'bx) $stop;
if ((1'bx | 1'b1) !== 1'b1) $stop;
if ((1'bx && 1'b1) !== 1'bx) $stop;
if ((1'bx && 1'b0) !== 1'b0) $stop;
if ((1'bx || 1'b0) !== 1'bx) $stop;
if ((1'bx || 1'b1) !== 1'b1) $stop;
if ((2'bxx ^ 2'b1) !== 2'bxx) $stop;
if ((2'bxx > 2'b1) !== 1'bx) $stop;
if ((2'bxx < 2'b1) !== 1'bx) $stop;
if ((2'bxx == 2'b1) !== 1'bx) $stop;
if ((2'bxx <= 2'b1) !== 1'bx) $stop;
if ((2'bxx >= 2'b1) !== 1'bx) $stop;
if ((2'sbxx <= 2'sb1) !== 1'bx) $stop;
if ((2'sbxx >= 2'sb1) !== 1'bx) $stop;
ma = 3'h3;
mb = 3'h4;
mc = 10'h5;
mr1 = ma * mb; // Lint ASWESB: Assignment width mismatch
mr2 = 30'h5 * mc; // Lint ASWESB: Assignment width mismatch
if (mr1 !== 5'd12) $stop;
if (mr2 !== 31'd25) $stop; // Lint CWECBB: Comparison width mismatch
sh1 = 68'hf_def1_9abc_5678_1234;
shq = sh1 >> 16;
if (shq !== 68'hf_def1_9abc_5678) $stop;
shq = sh1 << 16; // Lint ASWESB: Assignment width mismatch
if (shq !== 68'h1_9abc_5678_1234_0000) $stop;
// surefire lint_on SEQASS
// Test display extraction widthing
$display("[%0t] %x %x %x(%d)", $time, shq[2:0], shq[2:0]<<2, xor3[2:0], xor3[2:0]);
// bug736
//verilator lint_off WIDTH
if ((~| 4'b0000) != 4'b0001) $stop;
if ((~| 4'b0010) != 4'b0000) $stop;
if ((~& 4'b1111) != 4'b0000) $stop;
if ((~& 4'b1101) != 4'b0001) $stop;
//verilator lint_on WIDTH
// bug764
//verilator lint_off WIDTH
// X does not sign extend
if (bug764_p11 !== 4'b000x) $stop;
if (~& bug764_p11 !== 1'b1) $stop;
//verilator lint_on WIDTH
// However IEEE 2017 5.7.1 says for constants that smaller-sizes do extend
if (4'bx !== 4'bxxxx) $stop;
if (4'bz !== 4'bzzzz) $stop;
if (4'b1 !== 4'b0001) $stop;
if ((0 -> 0) != 1'b1) $stop;
if ((0 -> 1) != 1'b1) $stop;
if ((1 -> 0) != 1'b0) $stop;
if ((1 -> 1) != 1'b1) $stop;
if ((0 <-> 0) != 1'b1) $stop;
if ((0 <-> 1) != 1'b0) $stop;
if ((1 <-> 0) != 1'b0) $stop;
if ((1 <-> 1) != 1'b1) $stop;
// bug2912
// verilator lint_off WIDTH
if (2'(~1'b1) != 2'b10) $stop;
// verilator lint_on WIDTH
$write("*-* All Finished *-*\n");
$finish;
end
end
reg [63:0] m_data_pipe2_r;
reg [31:0] m_corr_data_w0, m_corr_data_w1;
reg [7:0] m_corr_data_b8;
initial begin
m_data_pipe2_r = 64'h1234_5678_9abc_def0;
{m_corr_data_b8, m_corr_data_w1, m_corr_data_w0} = { m_data_pipe2_r[63:57], 1'b0, //m_corr_data_b8 [7:0]
m_data_pipe2_r[56:26], 1'b0, //m_corr_data_w1 [31:0]
m_data_pipe2_r[25:11], 1'b0, //m_corr_data_w0 [31:16]
m_data_pipe2_r[10:04], 1'b0, //m_corr_data_w0 [15:8]
m_data_pipe2_r[03:01], 1'b0, //m_corr_data_w0 [7:4]
m_data_pipe2_r[0], 3'b000 //m_corr_data_w0 [3:0]
};
if (m_corr_data_w0 != 32'haf36de00) $stop;
if (m_corr_data_w1 != 32'h1a2b3c4c) $stop;
if (m_corr_data_b8 != 8'h12) $stop;
end
endmodule
|
/*
* Copyright (c) 2008 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`include "defines.v"
module zbt_cntrl (
`ifdef DEBUG
output reg [2:0] cnt,
output op,
`endif
// Wishbone slave interface
input wb_clk_i,
input wb_rst_i,
input [15:0] wb_dat_i,
output reg [15:0] wb_dat_o,
input [19:1] wb_adr_i,
input wb_we_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output reg wb_ack_o,
// Pad signals
output sram_clk_,
output reg [20:0] sram_addr_,
inout [31:0] sram_data_,
output reg sram_we_n_,
output reg [ 3:0] sram_bw_,
output reg sram_cen_,
output sram_adv_ld_n_
);
// Registers and nets
reg [31:0] wr;
wire nload;
`ifndef DEBUG
reg [ 2:0] cnt;
wire op;
`endif
// Continuous assignments
assign op = wb_stb_i & wb_cyc_i;
assign nload = (|cnt || wb_ack_o);
assign sram_clk_ = wb_clk_i;
assign sram_adv_ld_n_ = 1'b0;
assign sram_data_ = (op && wb_we_i) ? wr : 32'hzzzzzzzz;
// Behaviour
// cnt
always @(posedge wb_clk_i)
cnt <= wb_rst_i ? 3'b0
: { cnt[1:0], nload ? 1'b0 : op };
// wb_ack_o
always @(posedge wb_clk_i)
wb_ack_o <= wb_rst_i ? 1'b0 : (wb_ack_o ? op : cnt[2]);
// wb_dat_o
always @(posedge wb_clk_i)
wb_dat_o <= cnt[2] ? (wb_adr_i[1] ? sram_data_[31:16]
: sram_data_[15:0]) : wb_dat_o;
// sram_addr_
always @(posedge wb_clk_i)
sram_addr_ <= op ? { 3'b0, wb_adr_i[19:2] } : sram_addr_;
// sram_we_n_
always @(posedge wb_clk_i)
sram_we_n_ <= wb_we_i ? (nload ? 1'b1 : !op) : 1'b1;
// sram_bw_
always @(posedge wb_clk_i)
sram_bw_ <= wb_adr_i[1] ? { ~wb_sel_i, 2'b11 }
: { 2'b11, ~wb_sel_i };
// sram_cen_
always @(posedge wb_clk_i)
sram_cen_ <= wb_rst_i ? 1'b1 : !op;
// wr
always @(posedge wb_clk_i)
wr <= op ? (wb_adr_i[1] ? { wb_dat_i, 16'h0 }
: { 16'h0, wb_dat_i }) : wr;
endmodule
|
`include "defines.v"
module HRbridge16
#(parameter addr = 4'b0000) //No. 0 connect router, port 0
(
input `control_w port_l0_i,
input `control_w port_l1_i,
input `control_w port_g0_i,
input `control_w port_g1_i,
output `control_w port_l0_o,
output `control_w port_l1_o,
output `control_w port_g0_o,
output `control_w port_g1_o,
input `control_w FIFO_l0_i,
input `control_w FIFO_l1_i,
input `control_w FIFO_g0_i,
input `control_w FIFO_g1_i,
output `control_w FIFO_l0_o,
output `control_w FIFO_l1_o,
output `control_w FIFO_g0_o,
output `control_w FIFO_g1_o,
input bfull_l0_i,
input bfull_l1_i,
input bfull_g0_i,
input bfull_g1_i,
input clk,
input rst,
output deQ_l0_o,
output deQ_l1_o,
output deQ_g0_o,
output deQ_g1_o,
output enQ_l0_o,
output enQ_l1_o,
output enQ_g0_o,
output enQ_g1_o
);
wire `control_w port_l0_0, port_l1_0, port_g0_0, port_g1_0;
assign port_l0_0 = rst ? `control_n'h0 : port_l0_i;
assign port_l1_0 = rst ? `control_n'h0 : port_l1_i;
assign port_g0_0 = rst ? `control_n'h0 : port_g0_i;
assign port_g1_0 = rst ? `control_n'h0 : port_g1_i;
// global logic
reg localRR;
reg [1:0] globalRR;
initial begin
localRR = 0;
globalRR = 0;
end
/************* STAGE 1 *************/
reg `control_w port_l0_r, port_l1_r, port_g0_r, port_g1_r;
wire `control_w port_l0_1, port_l1_1, port_g0_1, port_g1_1;
always @(posedge clk) begin
port_l0_r <= port_l0_0;
port_l1_r <= port_l1_0;
port_g0_r <= port_g0_0;
port_g1_r <= port_g1_0;
end
wire prod_l0, prod_l1, prod_g0, prod_g1, prod_g2, prod_g3; // if the coming signal productve
assign prod_l0 = port_l0_r[`valid_f] & (port_l0_r[`dest_f] >= 4);
assign prod_l1 = port_l1_r[`valid_f] & (port_l1_r[`dest_f] >= 4);
assign prod_g0 = port_g0_r[`valid_f] & (port_g0_r[`dest_f] < 4);
assign prod_g1 = port_g1_r[`valid_f] & (port_g1_r[`dest_f] < 4);
wire req_swap_l0_g0 = prod_l0 & bfull_l0_i & prod_g0 & bfull_g0_i;
wire req_swap_l0_g1 = prod_l0 & bfull_l0_i & prod_g1 & bfull_g1_i;
wire req_swap_l1_g0 = prod_l1 & bfull_l1_i & prod_g0 & bfull_g0_i;
wire req_swap_l1_g1 = prod_l1 & bfull_l1_i & prod_g1 & bfull_g1_i;
wire swap_l0_g0 = req_swap_l0_g0;
wire swap_l0_g1 = ~swap_l0_g0 & req_swap_l0_g1;
wire swap_l1_g0 = ~swap_l0_g0 & req_swap_l1_g0;
wire swap_l1_g1 = ~swap_l1_g0 & ~swap_l0_g1 & req_swap_l1_g1;
wire swap_l0 = swap_l0_g0 | swap_l0_g1;
wire swap_l1 = swap_l1_g0 | swap_l1_g1;
wire swap_g0 = swap_l0_g0 | swap_l1_g0;
wire swap_g1 = swap_l0_g1 | swap_l1_g1;
// data into the buffer
assign FIFO_l0_o = port_l0_r;
assign FIFO_l1_o = port_l1_r;
assign FIFO_g0_o = port_g0_r;
assign FIFO_g1_o = port_g1_r;
assign enQ_l0_o = (prod_l0 & ~bfull_l0_i) | swap_l0_g0 | swap_l0_g1;
assign enQ_l1_o = (prod_l1 & ~bfull_l1_i) | swap_l1_g0 | swap_l1_g1;
assign enQ_g0_o = (prod_g0 & ~bfull_g0_i) | swap_l0_g0 | swap_l1_g0;
assign enQ_g1_o = (prod_g1 & ~bfull_g1_i) | swap_l0_g1 | swap_l1_g1;
// data from buffer to output
// data from local buffer tp global output
wire pref_l0 = (FIFO_l0_i[`dest_f] >= 4 && FIFO_l0_i[`dest_f] <= 9)? 0 : 1;
wire pref_l1 = (FIFO_l1_i[`dest_f] >= 4 && FIFO_l1_i[`dest_f] <= 9)? 0 : 1;
wire req_inj_l0_g0 = (~pref_l0 & (~port_g0_r[`valid_f] | enQ_g0_o) & ~swap_l0 & ~swap_g0 & FIFO_l0_i[`valid_f]) | swap_l0_g0;
wire req_inj_l0_g1 = (pref_l0 & (~port_g1_r[`valid_f] | enQ_g1_o) & ~swap_l0 & ~swap_g1 & FIFO_l0_i[`valid_f]) | swap_l0_g1;
wire req_inj_l1_g0 = (~pref_l1 & (~port_g0_r[`valid_f] | enQ_g0_o) & ~swap_l1 & ~swap_g0 & FIFO_l1_i[`valid_f]) | swap_l1_g0;
wire req_inj_l1_g1 = (pref_l1 & (~port_g1_r[`valid_f] | enQ_g1_o) & ~swap_l1 & ~swap_g1 & FIFO_l1_i[`valid_f]) | swap_l1_g1;
wire inj_l0_g0 = req_inj_l0_g0;
wire inj_l0_g1 = req_inj_l0_g1 & ~inj_l0_g0;
wire inj_l1_g0 = req_inj_l1_g0 & ~inj_l0_g0;
wire inj_l1_g1 = req_inj_l1_g1 & ~inj_l0_g1 & ~inj_l1_g0;
assign port_g0_1 = inj_l0_g0? FIFO_l0_i : (inj_l1_g0? FIFO_l1_i : (enQ_g0_o? 0 : port_g0_r));
assign port_g1_1 = inj_l0_g1? FIFO_l0_i : (inj_l1_g1? FIFO_l1_i : (enQ_g1_o? 0 : port_g1_r));
assign deQ_l0_o = inj_l0_g0 | inj_l0_g1;
assign deQ_l1_o = inj_l1_g0 | inj_l1_g1;
// data from global buffer to local output
wire pref_g0 = (FIFO_g0_i[`dest_f] == 0 || FIFO_g0_i[`dest_f] == 3)? 0 : 1;
wire pref_g1 = (FIFO_g1_i[`dest_f] == 0 || FIFO_g1_i[`dest_f] == 3)? 0 : 1;
wire req_inj_g0_l0 = (~pref_g0 & (~port_l0_r[`valid_f] | enQ_l0_o) & ~swap_l0 & ~swap_g0 & FIFO_g0_i[`valid_f]) | swap_l0_g0;
wire req_inj_g1_l0 = (~pref_g1 & (~port_l0_r[`valid_f] | enQ_l0_o) & ~swap_l0 & ~swap_g1 & FIFO_g1_i[`valid_f]) | swap_l0_g1;
wire req_inj_g0_l1 = (pref_g0 & (~port_l1_r[`valid_f] | enQ_l1_o) & ~swap_l1 & ~swap_g0 & FIFO_g0_i[`valid_f]) | swap_l1_g0;
wire req_inj_g1_l1 = (pref_g1 & (~port_l1_r[`valid_f] | enQ_l1_o) & ~swap_l1 & ~swap_g1 & FIFO_g1_i[`valid_f]) | swap_l1_g1;
wire inj_g0_l0 = req_inj_g0_l0;
wire inj_g1_l0 = req_inj_g1_l0 & ~inj_g0_l0;
wire inj_g0_l1 = req_inj_g0_l1;
wire inj_g1_l1 = req_inj_g1_l1 & ~inj_g0_l1;
assign port_l0_1 = inj_g0_l0? FIFO_g0_i :
(inj_g1_l0? FIFO_g1_i :
(enQ_l0_o? 0 : port_l0_r));
assign port_l1_1 = inj_g0_l1? FIFO_g0_i :
(inj_g1_l1? FIFO_g1_i :
(enQ_l1_o? 0 : port_l1_r));
assign deQ_g0_o = inj_g0_l0 | inj_g0_l1;
assign deQ_g1_o = inj_g1_l0 | inj_g1_l1;
/*********** STAGE 2 ***************/
reg `control_w port_l0_r1, port_l1_r1, port_g0_r1, port_g1_r1;
always @ (posedge clk) begin
port_l0_r1 <= port_l0_1;
port_l1_r1 <= port_l1_1;
port_g0_r1 <= port_g0_1;
port_g1_r1 <= port_g1_1;
end
assign port_l0_o = port_l0_r1;
assign port_l1_o = port_l1_r1;
assign port_g0_o = port_g0_r1;
assign port_g1_o = port_g1_r1;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND3_4_V
`define SKY130_FD_SC_HS__AND3_4_V
/**
* and3: 3-input AND.
*
* Verilog wrapper for and3 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__and3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__and3_4 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
sky130_fd_sc_hs__and3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__and3_4 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__and3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND3_4_V
|
#include <bits/stdc++.h> using namespace std; int log(int x) { return 32 - __builtin_clz(x) - 1; } int log(long long x) { return 64 - __builtin_clzll(x) - 1; } int n; int main() { cin >> n; if (n % 2 == 0) { cout << NO ; return 0; } cout << YES n ; bool add = false; for (int i = 1; i < 2 * n; i += 2, add = !add) cout << i + add << ; add = true; for (int i = 1; i < 2 * n; i += 2, add = !add) cout << i + add << ; } |
#include <bits/stdc++.h> using namespace std; struct problem { long long ts, tl, ss, sl, p; } pro[1005]; pair<long long, double> f[1005][1566]; int n, t; bool cmp(problem a, problem b) { return a.tl * a.p * (1000000 - b.p) < b.tl * b.p * (1000000 - a.p); } bool better(pair<long long, double> &a, pair<long long, double> &b) { if (a.first != b.first) return a.first > b.first; return a.second < b.second; } void dp() { for (int i = (0); i <= (n + 1); i++) for (int j = (0); j <= (t); j++) f[i][j].first = -1; f[1][0] = make_pair(0, 0); for (int i = (1); i <= (n); i++) for (int j = (0); j <= (t); j++) if (f[i][j].first > -1) { if (better(f[i][j], f[i + 1][j])) f[i + 1][j] = f[i][j]; pair<long long, double> P; long long nj; if (j + pro[i].ts <= t) { nj = j + pro[i].ts; P = make_pair(f[i][j].first + pro[i].ss, f[i][j].second + pro[i].ts * 1000000); if (better(P, f[i + 1][nj])) f[i + 1][nj] = P; } if (j + pro[i].ts + pro[i].tl <= t) { nj = j + pro[i].ts + pro[i].tl; P.first = f[i][j].first + pro[i].ss + pro[i].sl * (1000000 - pro[i].p); P.second = pro[i].ts * 1000000 + (1000000 - pro[i].p) * (pro[i].tl + j) + f[i][j].second * pro[i].p / 1.0 / 1000000; if (better(P, f[i + 1][nj])) f[i + 1][nj] = P; } } pair<long long, double> res = make_pair(0, 0); for (int j = (0); j <= (t); j++) if (better(f[n + 1][j], res)) { res = f[n + 1][j]; } printf( %.10lf %.10lf n , res.first / 1000000.0, res.second / 1000000.0); } long long str_ll(string &s) { long long x = 0; int pos = -1; for (int i = 0; i < (s.length()); i++) { if (s[i] == . ) { pos = i + 1; } else x = x * 10 + s[i] - 0 ; } if (pos != -1) for (int i = 0; i < (6 - s.length() + pos); i++) x = x * 10; return x; } int main() { cin >> n >> t; for (int i = (1); i <= (n); i++) { double p; cin >> pro[i].ss >> pro[i].sl >> pro[i].ts >> pro[i].tl >> p; pro[i].ss *= 1000000; pro[i].p = (p * 1000000 + 0.5); } sort(pro + 1, pro + n + 1, cmp); dp(); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFSBP_BEHAVIORAL_V
`define SKY130_FD_SC_LP__SDFSBP_BEHAVIORAL_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_lp__udp_dff_ps_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_lp__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_lp__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( SET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFSBP_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2111O_M_V
`define SKY130_FD_SC_LP__A2111O_M_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog wrapper for a2111o with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a2111o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2111o_m (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2111o_m (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2111O_M_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XNOR3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__XNOR3_FUNCTIONAL_PP_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__xnor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xnor0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xnor xnor0 (xnor0_out_X , A, B, C );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xnor0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__XNOR3_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; char s[55]; int l; int df[55][10]; int f(int pos, int c) { if (pos == l) return 1; if (df[pos][c] != -1) return df[pos][c]; int res = 0; int nn = c + s[pos]; res += f(pos + 1, nn / 2); if (nn & 1) res += f(pos + 1, (nn + 1) / 2); return df[pos][c] = res; } bool good() { for (int i = 1; i < l; i++) { int nn = s[i] + s[i - 1]; if (nn & 1) { if (nn / 2 != s[i] && (nn + 1) / 2 != s[i]) return false; } else { if (nn / 2 != s[i]) return false; } } return true; } int main() { memset(df, -1, sizeof(df)); scanf( %s , s); l = strlen(s); for (int i = 0; i < l; i++) s[i] -= 0 ; long long ans = 0; for (int i = 0; i < 10; i++) ans += f(1, i); if (good()) ans--; cout << ans << endl; return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [11:0] in_a;
reg [31:0] sel;
wire [2:0] out_x;
extractor #(4,3) extractor (
// Outputs
.out (out_x),
// Inputs
.in (in_a),
.sel (sel));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d %x %x %x\n", cyc, in_a, sel, out_x);
if (cyc==1) begin
in_a <= 12'b001_101_111_010;
sel <= 32'd0;
end
if (cyc==2) begin
sel <= 32'd1;
if (out_x != 3'b010) $stop;
end
if (cyc==3) begin
sel <= 32'd2;
if (out_x != 3'b111) $stop;
end
if (cyc==4) begin
sel <= 32'd3;
if (out_x != 3'b101) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module extractor (/*AUTOARG*/
// Outputs
out,
// Inputs
in, sel
);
parameter IN_WIDTH=8;
parameter OUT_WIDTH=2;
input [IN_WIDTH*OUT_WIDTH-1:0] in;
output [OUT_WIDTH-1:0] out;
input [31:0] sel;
wire [OUT_WIDTH-1:0] out = selector(in,sel);
function [OUT_WIDTH-1:0] selector;
input [IN_WIDTH*OUT_WIDTH-1:0] inv;
input [31:0] selv;
integer i;
begin
selector = 0;
for (i=0; i<OUT_WIDTH; i=i+1) begin
selector[i] = inv[selv*OUT_WIDTH+i];
end
end
endfunction
endmodule
|
#include <bits/stdc++.h> template <typename T, typename U> inline void swap(T &a, U &b) { a = a ^ b; b = a ^ b; a = a ^ b; } inline void swap(int &a, int &b) { a = a ^ b; b = a ^ b; a = a ^ b; } inline void swap(long long &a, long long &b) { a = a ^ b; b = a ^ b; a = a ^ b; } template <typename T, typename U> inline void smax(T &a, U b) { if (b > a) a = b; } template <typename T, typename U> inline void smin(T &a, U b) { if (b < a) a = b; } inline int gcd(int a, int b) { if (a < b) swap(a, b); while (b > 0) { a %= b; swap(a, b); } return a; } long long nchose(int a, int b) { long long ans = 1; smax(a, b - a); int p = 2; for (int i = (b - a + 1); i <= (b); i++) { ans *= (long long)i; while (p <= a && ans % p == 0) ans /= p++; } return ans; } using namespace std; static long long MOD = 1000000007; unsigned char rev(unsigned char c) { unsigned char res = 0, p1 = 1, p2 = 128; while (p2 != 0) { res += (p1 & c) > 0 ? p2 : 0; p2 /= 2; p1 *= 2; } return res; } int main() { unsigned char c, last = 0; scanf( %c , &c); while (c != 0 && c != n ) { last = rev(last) - rev(c); cout << (int)last << endl; last = c; scanf( %c , &c); } } |
#include <bits/stdc++.h> using namespace std; template <typename T> T gcd(T a, T b) { while (b) { T c = a % b; a = b; b = c; } return a; } template <typename T> T lcm(T a, T b) { assert(a / gcd(a, b) <= numeric_limits<T>::max() / b); return a * (b / gcd(a, b)); } class out { public: template <typename T> out &operator()(const T &t) { cout << t << ; return *this; } template <typename T1, typename T2> out &operator()(const pair<T1, T2> &t) { cout << ( << t.first << , << t.second << ) << ; return *this; } }; template <typename iter> void print(iter beg, iter end) { for_each(beg, end, out()); cout << endl; } long n; long h[100000]; long g[100000]; long r = 0; void algo() { for (long i = 1; i < n; ++i) { g[i] = max(g[i - 1], h[i - 1]); } long t = h[n - 1]; for (long i = n - 1; i >= 0; --i) { t = min(t, h[i]); if (t >= g[i]) { ++r; } } } int main() { cin >> n; for (long i = 0; i < n; ++i) { cin >> h[i]; } algo(); cout << r; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, ans = 0; cin >> n; pair<int, int> arr[n]; for (int i = 0; i < n; i++) cin >> arr[i].first >> arr[i].second; sort(arr, arr + n); for (int i = 0; i < n; i++) { if (arr[i].second >= ans) { ans = arr[i].second; } else { ans = arr[i].first; } } cout << ans; return 0; } |
//----------------------------------------------------------------------------
//-- Asynchronous serial receiver Unit
//------------------------------------------
//-- (C) BQ. December 2015. Written by Juan Gonzalez (Obijuan)
//-- GPL license
//----------------------------------------------------------------------------
//-- Tested at all the standard baudrates:
//--
//----------------------------------------------------------------------------
//-- Although this transmitter has been written from the scratch, it has been
//-- inspired by the one developed in the swapforth proyect by James Bowman
//--
//-- https://github.com/jamesbowman/swapforth
//--
//----------------------------------------------------------------------------
`default_nettype none
`include "baudgen.vh"
//-- Serial receiver unit module
module uart_rx #(
parameter BAUDRATE = `B115200 //-- Default baudrate
)(
input wire clk, //-- System clock (12MHz in the ICEstick)
input wire rstn, //-- Reset (Active low)
input wire rx, //-- Serial data input
output reg rcv, //-- Data is available (1)
output reg [7:0] data //-- Data received
);
//-- Transmission clock
wire clk_baud;
//-- Control signals
reg bauden; //-- Enable the baud generator
reg clear; //-- Clear the bit counter
reg load; //-- Load the received character into the data register
//-------------------------------------------------------------------
//-- DATAPATH
//-------------------------------------------------------------------
//-- The serial input is registered in order to follow the
//-- synchronous design rules
reg rx_r;
always @(posedge clk)
rx_r <= rx;
//-- Baud generator
baudgen_rx #(BAUDRATE)
baudgen0 (
.rstn(rstn),
.clk(clk),
.clk_ena(bauden),
.clk_out(clk_baud)
);
//-- Bit counter
reg [3:0] bitc;
always @(posedge clk)
if (clear)
bitc <= 4'd0;
else if (clear == 0 && clk_baud == 1)
bitc <= bitc + 1;
//-- Shift register for storing the received bits
reg [9:0] raw_data;
always @(posedge clk)
if (clk_baud == 1) begin
raw_data <= {rx_r, raw_data[9:1]};
end
//-- Data register. Store the character received
always @(posedge clk)
if (rstn == 0)
data <= 0;
else if (load)
data <= raw_data[8:1];
//-------------------------------------------
//-- CONTROLLER (Finite state machine)
//-------------------------------------------
//-- Receiver states
localparam IDLE = 2'd0; //-- IDLEde reposo
localparam RECV = 2'd1; //-- Receiving data
localparam LOAD = 2'd2; //-- Storing the character received
localparam DAV = 2'd3; //-- Data is available
//-- fsm states
reg [1:0] state;
reg [1:0] next_state;
//-- Transition between states
always @(posedge clk)
if (!rstn)
state <= IDLE;
else
state <= next_state;
//-- Control signal generation and next states
always @(*) begin
//-- Default values
next_state = state; //-- Stay in the same state by default
bauden = 0;
clear = 0;
load = 0;
case(state)
//-- Idle state
//-- Remain in this state until a start bit is received in rx_r
IDLE: begin
clear = 1;
rcv = 0;
if (rx_r == 0)
next_state = RECV;
end
//-- Receiving state
//-- Turn on the baud generator and wait for the serial package to be received
RECV: begin
bauden = 1;
rcv = 0;
if (bitc == 4'd10)
next_state = LOAD;
end
//-- Store the received character in the data register (1 cycle)
LOAD: begin
load = 1;
rcv = 0;
next_state = DAV;
end
//-- Data Available (1 cycle)
DAV: begin
rcv = 1;
next_state = IDLE;
end
default:
rcv = 0;
endcase
end
endmodule
|
/***********************************************************************
Incorrect direction non-detection test case
Copyright (C) 2001 Eric LaForest,
Licenced under GPL
***********************************************************************/
module CPU (data, address, rw, clock, reset);
inout [15:0] data;
output [15:0] address;
// This should be an output really....
input rw;
input clock, reset;
reg [15:0] data, address; // XXX error on data
reg rw; // error on rw
// I presume these should not be allowed to occur....
always @(posedge clock) begin
rw <= 1'b1;
end
always @(negedge clock) begin
rw <= 1'b0;
end
endmodule
module BENCH ();
reg [15:0] address, data;
reg rw, clock, reset;
CPU fm (address, data, rw, clock, reset);
initial begin
clock <= 0;
reset <= 1;
#1000;
$finish;
end
always begin
# 10 clock <= ~clock;
end
endmodule
|
/*
* BCH Encode/Decoder Modules
*
* Copyright 2014 - Russ Dill <>
* Distributed under 2-clause BSD license as contained in COPYING file.
*/
`timescale 1ns / 1ps
`include "bch_defs.vh"
/* serial inversionless */
module bch_sigma_bma_noinv #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE
) (
input clk,
input start,
input [`BCH_SYNDROMES_SZ(P)-1:0] syndromes,
input ack_done,
output reg done = 0,
output ready,
output reg [`BCH_SIGMA_SZ(P)-1:0] sigma = 0,
output reg [`BCH_ERR_SZ(P)-1:0] err_count = 0
);
`include "bch.vh"
localparam TCQ = 1;
localparam M = `BCH_M(P);
localparam T = `BCH_T(P);
reg [`BCH_SIGMA_SZ(P)-M-1:0] beta = 0;
wire [`BCH_SIGMA_SZ(P)-1:0] sigma_next;
wire [M-1:0] d_r;
reg d_r_nonzero = 0;
reg [M-1:0] d_p = 0;
wire [T:0] sigma_serial;
wire [T:2] beta_serial;
reg dead_cycle = 0;
reg start_cycle = 0;
reg penult_cycle = 0;
reg last_cycle = 0;
reg last_cycle1 = 0;
reg start1 = 0;
reg start2 = 0;
reg after_start2 = 0;
reg run = 0;
reg run1 = 0;
reg last_cycle1_first = 0;
reg run2 = 0;
reg first = 0;
reg last = 0;
wire [M-1:0] syn1 = syndromes[0+:M];
reg syn1_nonzero;
reg busy = 0;
reg bsel_thresh = 0;
reg [`BCH_ERR_SZ(P)-1:0] err_count_next = 0;
reg bsel = 0;
wire [`BCH_ERR_SZ(P)-1:0] bch_n;
counter #(T+1) u_bch_n_counter(
.clk(clk),
.reset(start),
.ce(start2),
.count(bch_n)
);
wire [log2(M-1)-1:0] count;
localparam COUNT_END = M > 4 ? lfsr_count(log2(M-1), M - 4) : 1;
if (M > 4) begin
lfsr_counter #(log2(M-1)) u_cycle_counter(
.clk(clk),
.reset(start_cycle),
.ce(run),
.count(count)
);
end else begin
reg _count = 0;
assign count = _count;
always @(posedge clk)
_count <= #TCQ start_cycle;
end
wire [(2*T-1)*M-1:0] syn_shuffled;
bch_syndrome_shuffle #(P) u_bch_syndrome_shuffle(
.clk(clk),
.start(start),
.ce(last_cycle1),
.syndromes(syndromes),
.syn_shuffled(syn_shuffled)
);
assign ready = !busy && (!done || ack_done);
function [M*(T+1)-1:0] reg_shift;
input [M*(T+1)-1:0] r;
integer i;
begin
for (i = 0; i < T + 1; i = i + 1)
reg_shift[i*M+:M] = {r[i*M+:M-1], r[i*M+M-1]};
end
endfunction
always @(posedge clk) begin
if (dead_cycle || start) begin
run1 <= #TCQ 1;
run2 <= #TCQ 0;
run <= #TCQ 1;
start1 <= #TCQ 1;
start2 <= #TCQ 0;
start_cycle <= #TCQ 1;
dead_cycle <= #TCQ 0;
end else if (last_cycle) begin
run1 <= #TCQ 0;
run2 <= #TCQ run1 && !last;
run <= #TCQ run1 && !last;
start1 <= #TCQ 0;
start2 <= #TCQ run1 && !last;
start_cycle <= #TCQ run1 && !last;
dead_cycle <= #TCQ run2;
end else begin
start1 <= #TCQ 0;
start2 <= #TCQ 0;
start_cycle <= #TCQ 0;
dead_cycle <= #TCQ 0;
end
if (start)
first <= #TCQ 1;
else if (dead_cycle)
first <= #TCQ 0;
last_cycle1_first <= #TCQ first && run1 && penult_cycle;
last_cycle1 <= #TCQ run1 && penult_cycle;
if (start)
last <= #TCQ 0;
else if (dead_cycle)
last <= #TCQ bch_n == T - 1;
if (!start && last_cycle && run1 && last)
done <= #TCQ 1;
else if (ack_done)
done <= #TCQ 0;
if (start)
busy <= #TCQ 1;
else if (last_cycle && run1 && last)
busy <= #TCQ 0;
penult_cycle <= #TCQ count == COUNT_END;
last_cycle <= #TCQ penult_cycle;
after_start2 <= #TCQ start2;
if (after_start2) begin
bsel_thresh <= #TCQ bch_n >= err_count;
err_count_next <= #TCQ 2 * bch_n - err_count + 1;
end
/* Mix run2/last_cycle into bsel so we can avoid the
* dead cycle control signal */
bsel <= run2 && penult_cycle && bsel_thresh && d_r_nonzero;
if (last_cycle1_first) begin
/* d_r(0) = 1 + S_1 * x */
/* sigma stores syn1 for us, but its shifiting it around */
d_p <= #TCQ syn1_nonzero ? reg_shift(sigma[M+:M]) : 1;
err_count <= #TCQ syn1_nonzero;
end else if (bsel) begin
d_p <= #TCQ d_r;
err_count <= #TCQ err_count_next;
end
if (start2)
d_r_nonzero <= #TCQ |d_r;
if (start)
syn1_nonzero <= #TCQ syn1[0];
else if (!syn1_nonzero)
/* Sigma[1] keeps and shifts syn1 for us during the first cycle */
syn1_nonzero <= #TCQ sigma_serial[1];
/* LUT5 */
if (start)
sigma <= #TCQ {syn1, {M-1{1'b0}}, 1'b1};
else if (dead_cycle)
sigma <= #TCQ sigma_next;
else
sigma <= #TCQ reg_shift(sigma);
/* LUT5 with CE */
if (run) begin
if (last_cycle1_first)
/* beta(1)(x) = syn1 ? x^2 : x^3 */
beta <= #TCQ {!syn1_nonzero, {M-1{1'b0}}, syn1_nonzero, {M{1'b0}}};
else if (bsel)
beta <= #TCQ reg_shift(sigma);
else
beta <= #TCQ beta << 1;
end
end
/* d_r = summation (sigma_i^(r) * S_(2 * r - i + 1))[0..t] */
serial_standard_multiplier #(M, T+1) d_r_multiplier(
.clk(clk),
.reset(start || dead_cycle),
.ce(run1),
.parallel_in(syn_shuffled[0+:M*(T+1)]),
.serial_in(sigma_serial),
.out(d_r)
);
/* sigma^(r)(x) = d_p * sigma^(r-1)(x) - d_r * beta^(r)(x) */
genvar i;
for (i = 0; i < T + 1; i = i + 1) begin : SERIAL
assign sigma_serial[i] = sigma[i*M+M-1];
end
/* 2 * M / 4 slices = 7 slices */
for (i = 0; i < 2; i = i + 1) begin : SIGMA1
/* LUT3 + reset */
serial_standard_multiplier #(M) sigma_multiplier (
.clk(clk),
.reset(last_cycle1),
.ce(1'b1),
.parallel_in(d_p),
.serial_in(sigma_serial[i]),
.out(sigma_next[i*M+:M])
);
end
/* (T - 1) * M / 4 slices = 39 */
for (i = 2; i < T + 1; i = i + 1) begin : SIGMA2
assign beta_serial[i] = beta[(i-1)*M+M-1];
/* LUT5 + reset */
serial_standard_multiplier #(M, 2) sigma_multiplier (
.clk(clk),
.reset(last_cycle1),
.ce(1'b1),
.parallel_in({d_p, d_r}),
.serial_in({sigma_serial[i], beta_serial[i]}),
.out(sigma_next[i*M+:M])
);
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 17:15:04 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W16 ( add_sub, in1, in2, res );
input [15:0] in1;
input [15:0] in2;
output [16:0] res;
input add_sub;
wire n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46,
n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60,
n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74,
n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88,
n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, n101,
n102, n103, n104, n105, n106, n107, n108, n109, n110;
NAND2XLTS U51 ( .A(n33), .B(n87), .Y(n89) );
XOR2X1TS U52 ( .A(n62), .B(in2[11]), .Y(n94) );
NAND2X1TS U53 ( .A(n71), .B(in1[13]), .Y(n87) );
NAND2X1TS U54 ( .A(n74), .B(n36), .Y(n58) );
NAND2BX1TS U55 ( .AN(in2[13]), .B(n59), .Y(n74) );
NAND2X1TS U56 ( .A(n67), .B(n36), .Y(n68) );
CMPR32X2TS U57 ( .A(n100), .B(in1[6]), .C(n99), .CO(n55), .S(res[6]) );
OR2X2TS U58 ( .A(n51), .B(n35), .Y(n34) );
INVX4TS U59 ( .A(n35), .Y(n36) );
NOR2X4TS U60 ( .A(n53), .B(in2[8]), .Y(n57) );
INVX4TS U61 ( .A(add_sub), .Y(n35) );
CLKINVX6TS U62 ( .A(in2[1]), .Y(n44) );
CLKINVX6TS U63 ( .A(in2[3]), .Y(n42) );
CLKINVX6TS U64 ( .A(in2[0]), .Y(n43) );
INVX8TS U65 ( .A(in2[2]), .Y(n41) );
NAND2BX2TS U66 ( .AN(in2[11]), .B(n61), .Y(n67) );
NOR2XLTS U67 ( .A(n61), .B(n35), .Y(n62) );
INVX2TS U68 ( .A(n78), .Y(n77) );
NOR2X4TS U69 ( .A(n67), .B(in2[12]), .Y(n59) );
NOR2X4TS U70 ( .A(n65), .B(in2[10]), .Y(n61) );
AO21X2TS U71 ( .A0(n33), .A1(n70), .B0(n72), .Y(n37) );
NAND2X2TS U72 ( .A(n76), .B(in1[15]), .Y(n78) );
XNOR2X2TS U73 ( .A(n58), .B(in2[14]), .Y(n73) );
NOR2X2TS U74 ( .A(n59), .B(n35), .Y(n60) );
ADDFHX2TS U75 ( .A(n56), .B(in1[7]), .CI(n55), .CO(n97), .S(res[7]) );
OAI31X1TS U76 ( .A0(in2[2]), .A1(in2[1]), .A2(in2[0]), .B0(n36), .Y(n106) );
NAND2X2TS U77 ( .A(n83), .B(n82), .Y(n85) );
NOR2X2TS U78 ( .A(n73), .B(in1[14]), .Y(n81) );
NAND2X2TS U79 ( .A(n73), .B(in1[14]), .Y(n82) );
NOR2X2TS U80 ( .A(n39), .B(n86), .Y(n38) );
INVX2TS U81 ( .A(n86), .Y(n33) );
NAND2X2TS U82 ( .A(n69), .B(in1[12]), .Y(n90) );
OR2X2TS U83 ( .A(n69), .B(in1[12]), .Y(n46) );
XNOR2X2TS U84 ( .A(n68), .B(in2[12]), .Y(n69) );
NOR2BX2TS U85 ( .AN(in1[5]), .B(n110), .Y(n99) );
NAND2BXLTS U86 ( .AN(in1[5]), .B(n110), .Y(res[5]) );
XNOR2X2TS U87 ( .A(n50), .B(in2[5]), .Y(n110) );
NAND2BXLTS U88 ( .AN(in1[4]), .B(n109), .Y(res[4]) );
OAI21XLTS U89 ( .A0(in2[1]), .A1(n102), .B0(n101), .Y(res[1]) );
OAI21XLTS U90 ( .A0(in2[2]), .A1(n104), .B0(n103), .Y(res[2]) );
OAI21XLTS U91 ( .A0(in2[3]), .A1(n106), .B0(n105), .Y(res[3]) );
XOR2X1TS U92 ( .A(n108), .B(in2[4]), .Y(n109) );
OR2X1TS U93 ( .A(in2[0]), .B(in1[0]), .Y(res[0]) );
XNOR2X1TS U94 ( .A(n34), .B(in2[7]), .Y(n56) );
OAI21X1TS U95 ( .A0(n74), .A1(in2[14]), .B0(n36), .Y(n75) );
AO21X2TS U96 ( .A0(n79), .A1(n45), .B0(n77), .Y(res[16]) );
NAND2X2TS U97 ( .A(n45), .B(n78), .Y(n80) );
OR2X2TS U98 ( .A(n76), .B(in1[15]), .Y(n45) );
NOR2X2TS U99 ( .A(n49), .B(n35), .Y(n50) );
AFHCONX4TS U100 ( .A(in1[10]), .B(n95), .CI(n96), .CON(n93), .S(res[10]) );
AOI21X4TS U101 ( .A0(n91), .A1(n38), .B0(n37), .Y(n84) );
XNOR2X1TS U102 ( .A(n79), .B(n80), .Y(res[15]) );
OAI21X4TS U103 ( .A0(n84), .A1(n81), .B0(n82), .Y(n79) );
XNOR2X2TS U104 ( .A(n75), .B(in2[15]), .Y(n76) );
AFHCONX4TS U105 ( .A(in1[8]), .B(n98), .CI(n97), .CON(n63), .S(res[8]) );
AFHCINX4TS U106 ( .CIN(n63), .B(n64), .A(in1[9]), .S(res[9]), .CO(n96) );
NOR2X8TS U107 ( .A(n47), .B(in2[6]), .Y(n51) );
NAND2X4TS U108 ( .A(n47), .B(add_sub), .Y(n48) );
NAND2X8TS U109 ( .A(n49), .B(n40), .Y(n47) );
AFHCINX4TS U110 ( .CIN(n93), .B(n94), .A(in1[11]), .S(res[11]), .CO(n91) );
NOR2X8TS U111 ( .A(n107), .B(in2[4]), .Y(n49) );
XOR2X4TS U112 ( .A(n60), .B(in2[13]), .Y(n71) );
NAND2BX4TS U113 ( .AN(in2[7]), .B(n51), .Y(n53) );
NAND2BX4TS U114 ( .AN(in2[9]), .B(n57), .Y(n65) );
INVX2TS U115 ( .A(in2[5]), .Y(n40) );
NOR2X2TS U116 ( .A(n71), .B(in1[13]), .Y(n86) );
INVX2TS U117 ( .A(n90), .Y(n70) );
INVX2TS U118 ( .A(n46), .Y(n39) );
XNOR2X1TS U119 ( .A(n48), .B(in2[6]), .Y(n100) );
XNOR2X1TS U120 ( .A(n54), .B(in2[8]), .Y(n98) );
NAND2X1TS U121 ( .A(n53), .B(n36), .Y(n54) );
XOR2X1TS U122 ( .A(n52), .B(in2[9]), .Y(n64) );
NOR2X1TS U123 ( .A(n57), .B(n35), .Y(n52) );
XNOR2X1TS U124 ( .A(n92), .B(n91), .Y(res[12]) );
NAND2X1TS U125 ( .A(n46), .B(n90), .Y(n92) );
XOR2X1TS U126 ( .A(n89), .B(n88), .Y(res[13]) );
AOI21X1TS U127 ( .A0(n91), .A1(n46), .B0(n70), .Y(n88) );
XOR2X1TS U128 ( .A(n85), .B(n84), .Y(res[14]) );
INVX2TS U129 ( .A(n81), .Y(n83) );
NAND4X8TS U130 ( .A(n44), .B(n43), .C(n42), .D(n41), .Y(n107) );
INVX2TS U131 ( .A(n87), .Y(n72) );
NAND2X1TS U132 ( .A(n65), .B(n36), .Y(n66) );
XNOR2X1TS U133 ( .A(n66), .B(in2[10]), .Y(n95) );
NAND2X1TS U134 ( .A(in2[0]), .B(n36), .Y(n102) );
AOI21X1TS U135 ( .A0(in2[1]), .A1(n102), .B0(in1[1]), .Y(n101) );
OAI21X1TS U136 ( .A0(in2[1]), .A1(in2[0]), .B0(n36), .Y(n104) );
AOI21X1TS U137 ( .A0(in2[2]), .A1(n104), .B0(in1[2]), .Y(n103) );
AOI21X1TS U138 ( .A0(in2[3]), .A1(n106), .B0(in1[3]), .Y(n105) );
NAND2X1TS U139 ( .A(n107), .B(n36), .Y(n108) );
initial $sdf_annotate("Approx_adder_LOALPL6_syn.sdf");
endmodule
|
#include <bits/stdc++.h> using namespace std; using LL = long long; int main() { ios::sync_with_stdio(false); cin.tie(0); int n; cin >> n; LL sum = 0; for (int i = 0; i < n; ++i) { LL a; cin >> a; sum += a; } LL base = 1LL * (1 + n) * n / 2; LL add = (sum - base) / n; sum -= base + add * n; for (int i = 0; i < sum; ++i) cout << i + 1 + add + 1 << ; for (int i = sum; i < n; ++i) cout << i + 1 + add << ; cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; struct node { int x, id; friend bool operator<(node a, node b) { if (a.x == b.x) return a.id < b.id; return a.x < b.x; } } a[200005]; priority_queue<node> Q; struct edge { int s, e; } ans[2000005]; int id; int main() { int n, s; while (scanf( %d %d , &n, &s) != EOF) { int i, j, k; for (i = 1; i <= n; ++i) { scanf( %d , &a[i].x); a[i].id = i; Q.push(a[i]); } node x; id = 0; while (!Q.empty()) { x = Q.top(); Q.pop(); j = 0; for (i = 0; i < x.x && (!Q.empty()); ++i) { a[j] = Q.top(); Q.pop(); ans[id].s = x.id; ans[id].e = a[j].id; a[j].x--; j++; id++; } if (i == x.x) { --j; while (j >= 0) { if (a[j].x) { Q.push(a[j]); } j--; } } else { s = 0; break; } } if (s == 0) { puts( No ); } else { puts( Yes ); printf( %d n , id); for (i = 0; i < id; ++i) { printf( %d %d n , ans[i].s, ans[i].e); } } } return 0; } |
#include <bits/stdc++.h> using namespace std; vector<int> g[2000]; int vis[2000]; vector<pair<int, int> > cyc; void dfs(int x, int scc) { if (vis[x] > 0) { return; } vis[x] = 1; int j; for (int i = 0; i < g[x].size(); i++) { for (j = 0; j < g[g[x][i]].size(); j++) { if (g[g[x][i]][j] == x) { g[g[x][i]].erase(g[g[x][i]].begin() + j); } } if (vis[g[x][i]] > 0) { cyc.push_back(make_pair(x, g[x][i])); } dfs(g[x][i], scc); } return; } int main() { int n, i, j, x, y, t, u; cin >> n; for (i = 0; i < n - 1; i++) { cin >> x >> y; x--; y--; g[x].push_back(y); g[y].push_back(x); } memset(vis, 0, sizeof(vis)); int scc = 0, days = 0; cyc.clear(); vector<int> store; store.clear(); for (i = 0; i < n; i++) { if (vis[i] == 0) { scc++; store.push_back(i); dfs(i, scc); } } if (scc == 1) { cout << 0 n ; return 0; } j = 1; vector<pair<pair<int, int>, pair<int, int> > > v; v.clear(); for (i = 0; i < cyc.size(); i++) { v.push_back(make_pair(make_pair(cyc[i].first + 1, cyc[i].second + 1), make_pair(store[j - 1] + 1, store[j] + 1))); j++; } cout << v.size() << n ; for (i = 0; i < v.size(); i++) { cout << v[i].first.first << << v[i].first.second << << v[i].second.first << << v[i].second.second << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const unsigned long long mod = 1000000007; int main() { int x, y; unsigned long long n = 0; cin >> x >> y; unsigned long long t = 0; int power = 2; for (int p = 0; p < 2200; p++) { if (power > y) break; t += y + 1 - power; power += 2; } for (int i = 1; i < x; i++) { y = min(i, x - i); n += y; } n *= t; cout << n; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND4B_BLACKBOX_V
`define SKY130_FD_SC_HDLL__NAND4B_BLACKBOX_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nand4b (
Y ,
A_N,
B ,
C ,
D
);
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND4B_BLACKBOX_V
|
//-----------------------------------------------------------------------------
// File : wb_slave_mem_master.v
// Creation date : 27.07.2017
// Creation time : 14:40:19
// Description : Used to test wishbone cpu wrapper from both master and slave side.
// Created by : TermosPullo
// Tool : Kactus2 3.4.110 32-bit
// Plugin : Verilog generator 2.0e
// This file was generated based on IP-XACT component tut.fi:communication.bridge.test:wb_cpu.bench:1.0
// whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/communication.bridge.test/wb_cpu.bench/1.0/wb_cpu.bench.1.0.xml
//-----------------------------------------------------------------------------
module wb_slave_mem_master #(
parameter ADDR_WIDTH = 16, // The width of the address.
parameter DATA_WIDTH = 32, // The width of both input and output data.
parameter DATA_COUNT = 8, // How many values there are in the register array.
parameter BASE_ADDRESS = 'h0F00 // The first referred address of the master.
) (
// Interface: memory_interface
// Used to test the bridge from controller side.
input [DATA_WIDTH-1:0] mem_data_i, // Data to bridge.
input mem_slave_rdy, // Bridge has executed the transfer.
output reg [ADDR_WIDTH-1:0] mem_address_o, // Target address of a peripheral operation.
output reg [DATA_WIDTH-1:0] mem_data_o, // Data from bridge.
output reg mem_master_rdy, // Data is provided and transfer can be executed.
output reg mem_we_o, // Controllers writes = 1, Controller reads = 0.
// Interface: wb_slave
// Used to test the bridge from the slave side.
input [ADDR_WIDTH-1:0] wb_adr_i, // The address of the data.
input wb_cyc_i, // Asserted by master for transfer.
input [DATA_WIDTH-1:0] wb_dat_i, // Data from master to slave.
input wb_stb_i, // Asserted, when this specific slave is selected.
input wb_we_i, // Write = 1, Read = 0.
output reg wb_ack_o, // Slave asserts acknowledge.
output reg [DATA_WIDTH-1:0] wb_dat_o, // Data from slave to master.
output reg wb_err_o, // Indicates abnormal cycle termination.
// Interface: wb_system
// Grouping for wishbone system signals. The clock and reset are used for all logic
// in this module.
input clk_i, // The mandatory clock, as this is synchronous logic.
input rst_i // The mandatory reset, as this is synchronous logic.
);
// WARNING: EVERYTHING ON AND ABOVE THIS LINE MAY BE OVERWRITTEN BY KACTUS2!!!
localparam AUB = 8;
localparam AU_IN_DATA = DATA_WIDTH/AUB;
// The master state.
reg [1:0] master_state;
// The available states.
parameter [1:0]
S_MASTER_INIT_WRITE = 2'd0,
S_MASTER_WAIT_WRITE = 2'd1,
S_MASTER_INIT_READ = 2'd2,
S_MASTER_WAIT_READ = 2'd3;
reg [DATA_WIDTH-1:0] test_values [DATA_COUNT-1:0];
// Used to index data to data io.
reg [DATA_COUNT:0] value_iterator;
always @(posedge clk_i or posedge rst_i) begin
if(rst_i == 1'b1) begin
// Initialize test_values with data.
test_values[0] = 32'h00000000;
test_values[1] = 32'h10001111;
test_values[2] = 32'h20002222;
test_values[3] = 32'h30003333;
test_values[4] = 32'h40004444;
test_values[5] = 32'h50005555;
test_values[6] = 32'h60006666;
test_values[7] = 32'h70007777;
// Start with testing write.
master_state <= S_MASTER_INIT_WRITE;
// Outputs are zero by default.
mem_address_o <= 0;
mem_data_o <= 0;
mem_master_rdy <= 0;
mem_we_o <= 0;
value_iterator <= 0;
end
else begin
if (master_state == S_MASTER_INIT_WRITE) begin
mem_master_rdy <= 1;
mem_we_o <= 1;
mem_data_o <= test_values[value_iterator];
master_state <= S_MASTER_WAIT_WRITE;
mem_address_o <= ( value_iterator * AU_IN_DATA ) + BASE_ADDRESS;
end
else if (master_state == S_MASTER_WAIT_WRITE) begin
mem_master_rdy <= 0;
if ( mem_slave_rdy == 1 ) begin
master_state <= S_MASTER_INIT_READ;
end
end
else if (master_state == S_MASTER_INIT_READ) begin
mem_master_rdy <= 1;
mem_we_o <= 0;
master_state <= S_MASTER_WAIT_READ;
mem_address_o <= ( value_iterator * AU_IN_DATA ) + BASE_ADDRESS;
end
else if (master_state == S_MASTER_WAIT_READ) begin
mem_master_rdy <= 0;
if ( mem_slave_rdy == 1 ) begin
master_state <= S_MASTER_INIT_WRITE;
// It was read from the same address as was written, so it should be the same data.
if (test_values[value_iterator] != mem_data_i) begin
$display("ERROR: Wrong answer from wrapper: %X Expected: %X", mem_data_i, test_values[value_iterator]);
$stop;
end
if (value_iterator >= DATA_COUNT) begin
$display("SIMULATION COMPLETE");
$stop;
end
value_iterator <= value_iterator + 1;
end
end
else
$display("ERROR: Unkown master_state: %d", master_state);
end
end
// Used to index AUBs to data io.
integer memory_index;
// The slave state.
reg [0:0] slave_state;
// The available states.
parameter [0:0]
S_WAIT = 1'd0, // Waiting for cyc_i & stb_i
S_DEASSERT = 1'd1; // Deassert acknowledgement.
localparam MEMORY_SIZE = DATA_COUNT*4;
reg [AUB-1:0] memory [MEMORY_SIZE-1:0];
always @(posedge clk_i or posedge rst_i) begin
if(rst_i == 1'b1) begin
wb_ack_o <= 0; // Obviously, there is nothing to acknowledge by default.
wb_dat_o <= 0; // No output by default.
wb_err_o <= 0; // No error by default.
slave_state <= S_WAIT; // Wait signals from the masters at reset.
end
else begin
if (slave_state == S_WAIT) begin
// Wait signal from the master.
if (wb_cyc_i == 1 && wb_stb_i == 1) begin
// Master ok, check the address.
if (wb_adr_i < BASE_ADDRESS + MEMORY_SIZE && wb_adr_i >= BASE_ADDRESS) begin
// The specified address in accessible -> proceed.
wb_ack_o <= 1;
if (wb_we_i == 1) begin
// Writing: Pick every byte from the input and place them to correct addresses.
for (memory_index = 0; memory_index < AU_IN_DATA; memory_index = memory_index + 1) begin
memory[wb_adr_i - BASE_ADDRESS + memory_index] <= wb_dat_i[(memory_index*AUB)+:AUB];
end
end
else begin
// Reading: Pick every byte from correct addresses and place them to the output.
for (memory_index = 0; memory_index < AU_IN_DATA; memory_index = memory_index + 1) begin
wb_dat_o[(memory_index*AUB)+:AUB] <= memory[wb_adr_i - BASE_ADDRESS + memory_index];
end
end
end
else begin
// The specified address out-of-scope -> error!
wb_err_o <= 1;
end
// Next thing is to deassert.
slave_state <= S_DEASSERT;
end
end
else if (slave_state == S_DEASSERT) begin
// Deassert acknowlegement, get ready to receive next one.
wb_ack_o <= 0;
wb_err_o <= 0;
slave_state <= S_WAIT;
end
else
$display("ERROR: Unkown slave_state: %d", slave_state);
end
end
endmodule
|
#include <bits/stdc++.h> double A[1005][1005]; void guass(int n) { int i, j; for (i = 0; i < n - 1; i++) { double f = A[i + 1][i] / A[i][i]; for (j = i; j < n; j++) { if (j > i + 2) break; A[i + 1][j] -= f * A[i][j]; } A[i + 1][n] -= f * A[i][n]; } for (i = n - 1; i >= 0; i--) { if (i + 1 < n) A[i][n] -= A[i + 1][n] * A[i][i + 1]; A[i][n] /= A[i][i]; } } int main() { int n, m, x, y, cnt; while (~scanf( %d%d%d%d , &n, &m, &x, &y)) { for (; x < n; x++) { for (int i = 1; i <= m; i++) { cnt = 2 + (i > 1) + (i < m); A[i - 1][i - 1] = ((double)(cnt - 1)) / cnt; if (i > 1) A[i - 1][i - 2] = (-1.0) / cnt; if (i < m) A[i - 1][i] = (-1.0) / cnt; A[i - 1][m] = A[i - 1][m] / cnt + 1; } guass(m); } printf( %.10f n , A[y - 1][m]); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A22OI_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__A22OI_PP_SYMBOL_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__a22oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A22OI_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; char s[131100]; int cal(int l, int r, char t) { int cnt = 0; for (int i = l; i <= r; i++) { if (s[i] != t) cnt++; } return cnt; } int dfs(int l, int r, char t) { if (l == r) return cal(l, r, t); int ret = 1e9; int mid = (l + r) >> 1; ret = min(ret, dfs(l, mid, t + 1) + cal(mid + 1, r, t)); ret = min(ret, dfs(mid + 1, r, t + 1) + cal(l, mid, t)); return ret; } int main() { int _; scanf( %d , &_); while (_--) { int n; scanf( %d , &n); scanf( %s , s); char temp = a ; printf( %d n , dfs(0, n - 1, temp)); } return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: California State University San Bernardino
// Engineer: Bogdan Kravtsov
//
// Create Date: 14:34:17 10/03/2016
// Module Name: IF_ID_tb
// Project Name: MIPS
// Description: Testing MIPS IF_ID register implementation in verilog.
//
// Dependencies: IF_ID.v
//
////////////////////////////////////////////////////////////////////////////////
module IF_ID_tb;
// Declare inputs.
reg clk;
reg [31:0] npc;
reg [31:0] instr;
// Declare outputs.
wire [31:0] instrout;
wire [31:0] npcout;
// Instantiate the IF_ID module.
IF_ID ifid(.clk(clk), .npc(npc), .instr(instr), .instrout(instrout),
.npcout(npcout));
initial begin
// Initialize inputs.
clk = 0;
npc = 0;
instr = 0;
// Test values.
npc = 32'h44444440;
instr = 32'hA0A0A0A0;
#10;
npc = 32'h22220022;
instr = 32'hFFFFFFFF;
#10;
npc = 32'h08080808;
instr = 32'hBBCCBBCC;
#10;
npc = 32'h78FF23A0;
instr = 32'h88905FBC;
// Terminate;
#10 $finish;
end
// Monitor values.
initial begin
$monitor("Time = %0d\tclk = %0d\tnpc = %8h \t instr = %8h\t\tnpcout = %8h\tinstrout = %8h",
$time, clk, npc, instr, npcout, instrout);
end
// Clock.
initial begin
forever begin
#10 clk = ~clk;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FILL_DIODE_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__FILL_DIODE_BEHAVIORAL_PP_V
/**
* fill_diode: Fill diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__fill_diode (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__FILL_DIODE_BEHAVIORAL_PP_V |
/*
Screen Memory is 4kB
It is expected that an ISR will be used to update the screen memory during output.
*/
module ModFbMem(clock, reset,
pixCellIx, cellData1, cellData2,
busAddr, busData, busOE, busWR, busHold);
/* verilator lint_off UNUSED */
input clock;
input reset;
input[13:0] pixCellIx;
output[31:0] cellData1;
output[31:0] cellData2;
input[39:0] busAddr;
inout[31:0] busData;
input busOE;
input busWR;
output busHold;
reg tBusHold; //IO Hold State
reg[31:0] tBusData; //Output Data
wire tBusCSel; //Bus Chip-Select (Addr Matches)
assign busHold = (busOE && tBusCSel) ? tBusHold : 1'bZ;
assign busData = (busOE && tBusCSel) ? tBusData : 32'hZZZZ_ZZZZ;
// assign busHold = 1'bZ;
// assign busData = 32'hZZZZ_ZZZZ;
assign tBusCSel = (busAddr[39:16]==24'hA0_A000) ||
(busAddr[39:16]==24'h00_ACA0) ||
(busAddr[39:16]==24'h00_ACA1);
// wire[13:0] tReadAddr;
// assign tReadAddr = (busOE && tBusCSel) ? busAddr[15:2] : pixCellIx;
// assign tReadAddr = pixCellIx;
reg[13:0] tPixCellIx; //base cell index
// reg[13:0] tPixCellNextIx; //base cell index
//reg[31:0] scrCell1A[0:4095]; //Screen Memory (1/2 32kB)
//reg[31:0] scrCell1B[0:4095]; //Screen Memory (1/2 32kB)
//reg[31:0] scrCell2A[0:1023]; //Screen Memory (1/2 8kB)
//reg[31:0] scrCell2B[0:1023]; //Screen Memory (1/2 8kB)
// (* ram_style="block" *) reg[31:0] scrCell1A[0:2047]; //Screen Memory (1/2 32kB)
// (* ram_style="block" *) reg[31:0] scrCell1B[0:2047]; //Screen Memory (1/2 32kB)
// (* ram_style="block" *) reg[31:0] scrCell2A[0:511]; //Screen Memory (1/2 8kB)
// (* ram_style="block" *) reg[31:0] scrCell2B[0:511]; //Screen Memory (1/2 8kB)
// (* ram_style="block" *) reg[31:0] scrCell1A[0:1023];
// (* ram_style="block" *) reg[31:0] scrCell1B[0:1023];
(* ram_style="block" *) reg[31:0] scrCell1A[0:511];
(* ram_style="block" *) reg[31:0] scrCell1B[0:511];
reg[31:0] scrRegCtrl[7:0]; //Control Registers
reg scrIs320; //use 320x240 64 bit cells
reg scrCellNoRead;
reg[31:0] tCell1;
reg[31:0] tCell2;
reg[31:0] tNextCell1;
reg[31:0] tNextCell2;
assign cellData1 = tCell1;
assign cellData2 = tCell2;
always @ (clock)
begin
tBusHold = 1;
tBusData = 0;
if(busOE && tBusCSel)
begin
if(busAddr[15:8]==255)
begin
// scrRegCtrl[busAddr[4:2]] <= busData;
tBusHold=0;
case(busAddr[6:2])
0: tBusData = scrRegCtrl[0];
1: tBusData = scrRegCtrl[1];
2: tBusData = scrRegCtrl[2];
3: tBusData = scrRegCtrl[3];
8: tBusData = {18'h0, pixCellIx};
endcase
end
else
begin
// tPixCellNextIx = busAddr[15:2];
// tBusHold = tPixCellIx != tPixCellNextIx;
tBusHold = tPixCellIx != busAddr[15:2];
tBusData = busAddr[2] ? tCell2 : tCell1;
end
end
end
always @ (posedge clock)
begin
// tPixCellIx <= pixCellIx;
tCell1 <= tNextCell1;
tCell2 <= tNextCell2;
tPixCellIx <= pixCellIx;
if(tBusCSel && busWR && !busOE)
begin
// scrCellNoRead <= 1;
scrCellNoRead <= 0;
if(busAddr[15:8]==255)
begin
scrRegCtrl[busAddr[4:2]] <= busData;
end
else
begin
// $display("%X %X", busAddr, busData);
if(busAddr[2])
scrCell1B[busAddr[11:3]] <= busData;
else
scrCell1A[busAddr[11:3]] <= busData;
end
end
end
always @ (posedge clock)
begin
// if(!busWR)
// begin
// scrCellNoRead <= 0;
// tNextCell1 <= scrCell1A[tReadAddr[10:1]];
// tNextCell2 <= scrCell1B[tReadAddr[10:1]];
// end
tNextCell1 <= scrCell1A[pixCellIx[9:1]];
tNextCell2 <= scrCell1B[pixCellIx[9:1]];
end
endmodule
|
// Quartus Prime Verilog Template
// Single port RAM with single read/write address and initial contents
// specified with an initial block
module phyIniCommand0_and
#(parameter DATA_WIDTH=16, parameter ADDR_WIDTH=4)
(
input [(DATA_WIDTH-1):0] data,
input [(ADDR_WIDTH-1):0] addr,
input we, clk,
output [(DATA_WIDTH-1):0] q
);
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
// Variable to hold the registered read address
reg [ADDR_WIDTH-1:0] addr_reg;
// Specify the initial contents. You can also use the $readmemb
// system task to initialize the RAM variable from a text file.
// See the $readmemb template page for details.
initial
begin : INIT
$readmemb("C:/altera/16.0/myProjects/PHYctrl_100Mbps_Slave_max10/ram_init0_and.txt", ram);
end
always @ (posedge clk)
begin
// Write
if (we)
ram[addr] <= data;
addr_reg <= addr;
end
// Continuous assignment implies read returns NEW data.
// This is the natural behavior of the TriMatrix memory
// blocks in Single Port mode.
assign q = ram[addr_reg];
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: syncfifo_512x72.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 197 01/19/2011 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module syncfifo_512x72 (
aclr,
clock,
data,
rdreq,
wrreq,
almost_empty,
empty,
full,
q);
input aclr;
input clock;
input [71:0] data;
input rdreq;
input wrreq;
output almost_empty;
output empty;
output full;
output [71:0] q;
wire sub_wire0;
wire sub_wire1;
wire [71:0] sub_wire2;
wire sub_wire3;
wire empty = sub_wire0;
wire full = sub_wire1;
wire [71:0] q = sub_wire2[71:0];
wire almost_empty = sub_wire3;
scfifo scfifo_component (
.clock (clock),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.empty (sub_wire0),
.full (sub_wire1),
.q (sub_wire2),
.almost_empty (sub_wire3),
.almost_full (),
.sclr (),
.usedw ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.almost_empty_value = 5,
scfifo_component.intended_device_family = "Stratix IV",
scfifo_component.lpm_numwords = 512,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 72,
scfifo_component.lpm_widthu = 9,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "5"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "512"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "0"
// Retrieval info: PRIVATE: Width NUMERIC "72"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "72"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "5"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "72"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL "almost_empty"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 72 0 INPUT NODEFVAL "data[71..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 72 0 OUTPUT NODEFVAL "q[71..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 72 0 data 0 0 72 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 72 0 @q 0 0 72 0
// Retrieval info: GEN_FILE: TYPE_NORMAL syncfifo_512x72.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL syncfifo_512x72.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL syncfifo_512x72.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL syncfifo_512x72.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL syncfifo_512x72_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL syncfifo_512x72_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* PAL/DAC controller for VGA
* Copyright (C) 2010 Zeus Gomez Marmolejo <>
*
* VGA FML support
* Copyright (C) 2013 Charley Picker <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga_pal_dac_fml (
input clk, // 100 Mhz clock
input rst,
input enable_pal_dac,
// VGA PAL/DAC input signals
input horiz_sync_pal_dac_i,
input vert_sync_pal_dac_i,
input video_on_h_pal_dac_i,
input video_on_v_pal_dac_i,
input [7:0] character_pal_dac_i,
// VGA PAL/DAC configuration signals
input shift_reg1, // if set: 320x200
input graphics_alpha, // if not set: 640x400 text mode
// attribute_ctrl
input [3:0] pal_addr,
input pal_we,
output [7:0] pal_read,
input [7:0] pal_write,
// dac_regs
input dac_we,
input [1:0] dac_read_data_cycle,
input [7:0] dac_read_data_register,
output [3:0] dac_read_data,
input [1:0] dac_write_data_cycle,
input [7:0] dac_write_data_register,
input [3:0] dac_write_data,
// VGA PAL/DAC output signals
// VGA pad signals
output reg [3:0] vga_red_o,
output reg [3:0] vga_green_o,
output reg [3:0] vga_blue_o,
output reg horiz_sync,
output vert_sync,
// retrace signals
output v_retrace,
output vh_retrace
);
// Registers and nets
wire video_on_v;
reg [1:0] video_on_h_p;
wire video_on;
wire [3:0] attr;
wire [7:0] index;
wire [7:0] index_pal;
reg [7:0] index_gm;
wire video_on_h;
reg [1:0] horiz_sync_p;
wire [3:0] red;
wire [3:0] green;
wire [3:0] blue;
// Module instances
vga_palette_regs_fml palette_regs (
.clk (clk),
.attr (attr),
.index (index_pal),
.address (pal_addr),
.write (pal_we),
.read_data (pal_read),
.write_data (pal_write)
);
vga_dac_regs_fml dac_regs (
.clk (clk),
.index (index),
.red (red),
.green (green),
.blue (blue),
.write (dac_we),
.read_data_cycle (dac_read_data_cycle),
.read_data_register (dac_read_data_register),
.read_data (dac_read_data),
.write_data_cycle (dac_write_data_cycle),
.write_data_register (dac_write_data_register),
.write_data (dac_write_data)
);
// Continuous assignments
assign video_on_v = video_on_v_pal_dac_i;
assign vert_sync = vert_sync_pal_dac_i;
assign video_on = video_on_h && video_on_v;
assign attr = character_pal_dac_i[3:0];
assign index = (graphics_alpha & shift_reg1) ? index_gm : index_pal;
assign video_on_h = video_on_h_p[1];
assign v_retrace = !video_on_v;
assign vh_retrace = v_retrace | !video_on_h;
// index_gm
always @(posedge clk)
if (rst)
begin
index_gm <= 8'h0;
end
else
if (enable_pal_dac)
begin
index_gm <= character_pal_dac_i;
end
// Horiz sync
always @(posedge clk)
if (rst)
begin
{ horiz_sync, horiz_sync_p } <= 3'b0;
end
else
if (enable_pal_dac)
begin
{ horiz_sync, horiz_sync_p } <= { horiz_sync_p[1:0], horiz_sync_pal_dac_i };
end
// Video_on pipe
always @(posedge clk)
if (rst)
begin
video_on_h_p <= 2'b0;
end
else
if (enable_pal_dac)
begin
video_on_h_p <= { video_on_h_p[0], video_on_h_pal_dac_i };
end
// Colour signals
always @(posedge clk)
if (rst)
begin
vga_red_o <= 4'b0;
vga_green_o <= 4'b0;
vga_blue_o <= 4'b0;
end
else
if (enable_pal_dac)
begin
vga_blue_o <= video_on ? blue : 4'h0;
vga_green_o <= video_on ? green : 4'h0;
vga_red_o <= video_on ? red : 4'h0;
end
endmodule
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.