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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2111O_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__A2111O_PP_BLACKBOX_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a2111o (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2111O_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A211OI_PP_SYMBOL_V
`define SKY130_FD_SC_HD__A211OI_PP_SYMBOL_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a211oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input C1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A211OI_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 3e5; int n, ans; int Dpos[N + 3]; char str[N + 10], Nstr[N + 10]; int main() { scanf( %d%s , &n, str + 1); int Ncnt = 0, Ned = n, Nmin = 0; for (int i = 1; i <= n; i++) { if (str[i] == ( ) Ncnt++; else Ncnt--; if (Nmin > Ncnt) { Nmin = Ncnt; Ned = i; } } if (Ncnt) printf( 0 n1 1 n ), exit(0); int Npos = 1; for (int i = Ned + 1; i <= n; i++) Dpos[Npos] = i, Nstr[Npos++] = str[i]; for (int i = 1; i <= Ned; i++) Dpos[Npos] = i, Nstr[Npos++] = str[i]; for (int i = 1, Icnt = 0; i <= n; i++) { if (Nstr[i] == ( ) Icnt++; else Icnt--; if (!Icnt) ans++; } int fans = ans; int ansl = 1, ansr = 1; for (int i = 1; i <= n;) { int Pcnt = 0; int j; for (j = i; j <= n; j++) { if (Nstr[j] == ( ) Pcnt++; else Pcnt--; if (!Pcnt) break; } vector<pair<int, int> > vec; Pcnt = 0; int Ptot = 0; for (int k = i + 1; k < j; k++) { if (Nstr[k] == ( ) Pcnt++; else Pcnt--; if (Pcnt == 0) { if (vec.empty()) vec.push_back(make_pair(i + 1, k)); else vec.push_back(make_pair(vec.back().second + 1, k)); } } for (auto it : vec) { int L = it.first, R = it.second; int Kcnt = 0, Ktot = 0; for (int k = L + 1; k <= R - 1; k++) { if (Nstr[k] == ( ) Kcnt++; else Kcnt--; if (!Kcnt) Ktot++; } if (ans < fans - 1 + 2 + Ktot) { ans = fans - 1 + 2 + Ktot; ansl = L; ansr = R; } } Ptot = vec.size(); if (ans < Ptot + 1) { ans = Ptot + 1; ansl = i; ansr = j; } i = j + 1; } ansl = Dpos[ansl]; ansr = Dpos[ansr]; if (ansl > ansr) swap(ansl, ansr); printf( %d n%d %d n , ans, ansl, ansr); return 0; } |
// This file is part of Verilog-65c816.
//
// Copyright 2017 by FPGApeeps
//
// Verilog-65c816 is free software: you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// Verilog-65c816 is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with Verilog-65c816. If not, see <http://www.gnu.org/licenses/>.
`include "src/inc/cpu_defines.v"
`include "src/inc/cpu_enums.v"
// A possible change to the ports would be to use a shared wire for input
// AND output data. This could be a good idea for connecting to memory
// outside the FPGA.
module Cpu(input wire clk, input wire rst, input wire enable,
input wire [`CPU_DATA_MSB_POS:0] data_in,
// If we're requesting a read or write
output reg req_rdwr,
// If req_rdwr == 1, then are we requesting a read or a write?
//
// Here would be a good place to use an enum if this project were
// written in SystemVerilog.
//
// Values used with this output reg are `ENUM__CPU_WH_RDWR__READ and
// `ENUM__CPU_WH_RDWR__WRITE, which are defined "src/inc/cpu_enums.v"
output reg which_rdwr,
// Address we want to read from or write to
//output reg [`CPU_FAR_ADDR_MSB_POS:0] addr,
// Just try a 16-bit address space for now. We will switch to a 24-bit
// address space later.
output reg [`CPU_ACTUAL_ADDR_MSB_POS:0] addr,
output reg [`CPU_DATA_MSB_POS:0] data_out);
// Parameters
`include "src/inc/generic_params.v"
`include "src/inc/cpu_state_params.v"
`include "src/inc/cpu_opcode_params.v"
// Buffer MSB positions
parameter __state_msb_pos = `_ENUM_MP__CPU_STATE;
// which_rdwr stuff
parameter __wh_rdwr__read = `ENUM__CPU_WH_RDWR__READ;
parameter __wh_rdwr__write = `ENUM__CPU_WH_RDWR__WRITE;
`include "src/inc/cpu_reg_params.v"
`include "src/inc/cpu_debug_params.v"
// Internal buffers
//reg [__buf_byte_msb_pos:0] __data_in_buf;
reg [__buf_byte_msb_pos:0] __opcode;
// State machine thing
reg [__state_msb_pos:0] __state;
reg [__state_msb_pos + 1:0] __state_enum_counter;
// Use the X macro pretending we have enums here.
`define X(enum_reg) enum_reg,
reg [__state_msb_pos:0]
`_LIST_OF_CPU_STATES
// This is necessary because of how the X macro is set up (having a
// comma at the end)
__st__dummy;
`undef X
initial
begin
__state_enum_counter = 0;
// Use the X macro pretending we have enums here.
//`define X(enum_reg) set_state_enum_reg(enum_reg);
`define X(enum_reg) \
enum_reg = __state_enum_counter; \
__state_enum_counter = __state_enum_counter + 1;
`_LIST_OF_CPU_STATES
`undef X
end
// Processor Registers
// The accumulator
reg [__reg_c_msb_pos:0] __reg_c;
// __reg_x is NOT a regular expression!
reg [__reg_index_big_msb_pos:0] __reg_x, __reg_y;
// Stack Pointer (SP)
reg [__reg_sp_msb_pos:0] __reg_sp;
// Program Counter (PC)
reg [__reg_pc_msb_pos:0] __reg_pc;
// Tasks
task prep_load;
input [`CPU_ACTUAL_ADDR_MSB_POS:0] some_addr;
begin
req_rdwr <= __true;
which_rdwr <= __wh_rdwr__read;
addr <= some_addr;
end
endtask
task prep_store;
input [`CPU_ACTUAL_ADDR_MSB_POS:0] some_addr;
input [`CPU_DATA_MSB_POS:0] some_data_out;
begin
req_rdwr <= __true;
which_rdwr <= __wh_rdwr__write;
addr <= some_addr;
data_out <= some_data_out;
end
endtask
// Completely unnecessary task
task disab_req_rdwr;
req_rdwr <= __false;
endtask
task debug_show_state;
case (__state)
`define X(enum_reg) \
enum_reg: \
begin \
$display(`"enum_reg\n\n`"); \
end
`_LIST_OF_CPU_STATES
`undef X
default:
begin
$display("Final __state\n");
end
endcase
endtask
always @ (posedge clk)
begin
if (!rst)
begin
debug_show_state();
if (enable)
begin
$display("CPU ENabled!");
end
else // if (!enable)
begin
$display("CPU DISabled!");
end
end
// Reset signal
if (rst)
begin
// Clear outputs
//req_rdwr <= __false;
disab_req_rdwr();
//which_rdwr <= __wh_rdwr__read;
addr <= `_CPU_ACTUAL_ADDR_WIDTH'h0000;
data_out <= `_CPU_DATA_WIDTH'h00;
// Clear internal buffers
//__data_in_buf <= 0;
__opcode <= 0;
// Clear processor registers
{__reg_c, __reg_x, __reg_y, __reg_sp, __reg_pc} <= 0;
//__reg_c <= 0;
//__reg_x <= 2;
//__reg_y <= 5;
//__reg_sp <= 16'h9001;
//__reg_pc <= 16'h2329;
// Initial state
__state <= __st_emu__reset;
end
else if (enable)
begin
case (__state)
__st_emu__reset:
begin
//__state <= __st_testing__test_load_0;
__state <= __st_testing__test_store_0;
end
// Test an 8-bit load
__st_testing__test_load_0:
begin
__state <= __state + 1;
prep_load(__debug_addr_0);
end
// Test another 8-bit load
__st_testing__test_load_1:
begin
__state <= __state + 1;
$display("data_in: %h\n\n", data_in);
//__opcode <= data_in;
__reg_c[__reg_b_msb_pos:__reg_b_lsb_pos] <= data_in;
prep_load(__debug_addr_1);
end
__st_testing__test_load_2:
begin
__state <= __state + 1;
$display("data_in: %h\n\n", data_in);
//__opcode <= data_in;
__reg_c[__reg_a_msb_pos:__reg_a_lsb_pos] <= data_in;
//disab_req_rdwr();
prep_load(__debug_addr_2);
end
__st_testing__test_load_3:
begin
__state <= __st_testing__done;
$display("data_in: %h\n\n", data_in);
//__opcode <= data_in;
__reg_x[__reg_index_hi_msb_pos:__reg_index_hi_lsb_pos]
<= data_in;
disab_req_rdwr();
end
// Test an 8-bit store
__st_testing__test_store_0:
begin
__state <= __state + 1;
prep_store(__debug_addr_0, `_CPU_DATA_WIDTH'h45);
end
__st_testing__test_store_1:
begin
__state <= __state + 1;
//__state <= __st_testing__test_load_0;
prep_store(__debug_addr_1, `_CPU_DATA_WIDTH'h87);
end
__st_testing__test_store_2:
begin
__state <= __st_testing__test_load_0;
prep_store(__debug_addr_2, `_CPU_DATA_WIDTH'haa);
end
default:
begin
$display("%h, %h\t\t%h, %h\t\t%h, %h, %h, %h, %h\n",
data_in, data_out,
__state, __opcode,
__reg_c, __reg_x, __reg_y, __reg_sp, __reg_pc);
$finish;
end
endcase
end
end
endmodule
|
module pr_region_alternate_mm_bridge_0 #(
parameter DATA_WIDTH = 32,
parameter SYMBOL_WIDTH = 8,
parameter HDL_ADDR_WIDTH = 10,
parameter BURSTCOUNT_WIDTH = 1,
parameter PIPELINE_COMMAND = 1,
parameter PIPELINE_RESPONSE = 1
) (
input wire clk, // clk.clk
input wire m0_waitrequest, // m0.waitrequest
input wire [DATA_WIDTH-1:0] m0_readdata, // .readdata
input wire m0_readdatavalid, // .readdatavalid
output wire [BURSTCOUNT_WIDTH-1:0] m0_burstcount, // .burstcount
output wire [DATA_WIDTH-1:0] m0_writedata, // .writedata
output wire [HDL_ADDR_WIDTH-1:0] m0_address, // .address
output wire m0_write, // .write
output wire m0_read, // .read
output wire [3:0] m0_byteenable, // .byteenable
output wire m0_debugaccess, // .debugaccess
input wire reset, // reset.reset
output wire s0_waitrequest, // s0.waitrequest
output wire [DATA_WIDTH-1:0] s0_readdata, // .readdata
output wire s0_readdatavalid, // .readdatavalid
input wire [BURSTCOUNT_WIDTH-1:0] s0_burstcount, // .burstcount
input wire [DATA_WIDTH-1:0] s0_writedata, // .writedata
input wire [HDL_ADDR_WIDTH-1:0] s0_address, // .address
input wire s0_write, // .write
input wire s0_read, // .read
input wire [3:0] s0_byteenable, // .byteenable
input wire s0_debugaccess // .debugaccess
);
endmodule
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 17872 $
// $Date: 2009-09-18 14:32:56 +0000 (Fri, 18 Sep 2009) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// A separate module which instantiates a simple reset combining primitive.
// The primitive is simply an AND gate.
module ResetEither(A_RST,
B_RST,
RST_OUT
) ;
input A_RST;
input B_RST;
output RST_OUT;
assign RST_OUT = A_RST & B_RST ;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DECAP_4_V
`define SKY130_FD_SC_LS__DECAP_4_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog wrapper for decap with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__decap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__decap_4 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__decap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__decap_4 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__decap base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DECAP_4_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Instruction TLB ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Instantiation of ITLB. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_immu_tlb.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Minor update:
// Bugs fixed, coding style changed.
//
// Revision 1.9 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.8 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.6.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.6 2002/10/28 16:34:32 mohor
// RAMs wrong connected to the BIST scan chain.
//
// Revision 1.5 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.4 2002/08/14 06:23:50 lampret
// Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run.
//
// Revision 1.3 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.2 2002/01/28 01:16:00 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
//
// Insn TLB
//
module or1200_immu_tlb(
// Rst and clk
clk, rst,
// I/F for translation
tlb_en, vaddr, hit, ppn, uxe, sxe, ci,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// SPR access
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// I/F for translation
//
input tlb_en;
input [aw-1:0] vaddr;
output hit;
output [31:`OR1200_IMMU_PS] ppn;
output uxe;
output sxe;
output ci;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// SPR access
//
input spr_cs;
input spr_write;
input [31:0] spr_addr;
input [31:0] spr_dat_i;
output [31:0] spr_dat_o;
//
// Internal wires and regs
//
wire [`OR1200_ITLB_TAG] vpn;
wire v;
wire [`OR1200_ITLB_INDXW-1:0] tlb_index;
wire tlb_mr_en;
wire tlb_mr_we;
wire [`OR1200_ITLBMRW-1:0] tlb_mr_ram_in;
wire [`OR1200_ITLBMRW-1:0] tlb_mr_ram_out;
wire tlb_tr_en;
wire tlb_tr_we;
wire [`OR1200_ITLBTRW-1:0] tlb_tr_ram_in;
wire [`OR1200_ITLBTRW-1:0] tlb_tr_ram_out;
// BIST
`ifdef OR1200_BIST
wire itlb_mr_ram_si;
wire itlb_mr_ram_so;
wire itlb_tr_ram_si;
wire itlb_tr_ram_so;
`endif
//
// Implemented bits inside match and translate registers
//
// itlbwYmrX: vpn 31-19 v 0
// itlbwYtrX: ppn 31-13 uxe 7 sxe 6
//
// itlb memory width:
// 19 bits for ppn
// 13 bits for vpn
// 1 bit for valid
// 2 bits for protection
// 1 bit for cache inhibit
//
// Enable for Match registers
//
assign tlb_mr_en = tlb_en | (spr_cs & !spr_addr[`OR1200_ITLB_TM_ADDR]);
//
// Write enable for Match registers
//
assign tlb_mr_we = spr_cs & spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR];
//
// Enable for Translate registers
//
assign tlb_tr_en = tlb_en | (spr_cs & spr_addr[`OR1200_ITLB_TM_ADDR]);
//
// Write enable for Translate registers
//
assign tlb_tr_we = spr_cs & spr_write & spr_addr[`OR1200_ITLB_TM_ADDR];
//
// Output to SPRS unit
//
assign spr_dat_o = (!spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR]) ?
{vpn, tlb_index, {`OR1200_ITLB_TAGW-7{1'b0}}, 1'b0, 5'b00000, v} :
(!spr_write & spr_addr[`OR1200_ITLB_TM_ADDR]) ?
{ppn, {`OR1200_IMMU_PS-8{1'b0}}, uxe, sxe, {4{1'b0}}, ci, 1'b0} :
32'h00000000;
//
// Assign outputs from Match registers
//
assign {vpn, v} = tlb_mr_ram_out;
//
// Assign to Match registers inputs
//
assign tlb_mr_ram_in = {spr_dat_i[`OR1200_ITLB_TAG], spr_dat_i[`OR1200_ITLBMR_V_BITS]};
//
// Assign outputs from Translate registers
//
assign {ppn, uxe, sxe, ci} = tlb_tr_ram_out;
//
// Assign to Translate registers inputs
//
assign tlb_tr_ram_in = {spr_dat_i[31:`OR1200_IMMU_PS],
spr_dat_i[`OR1200_ITLBTR_UXE_BITS],
spr_dat_i[`OR1200_ITLBTR_SXE_BITS],
spr_dat_i[`OR1200_ITLBTR_CI_BITS]};
//
// Generate hit
//
assign hit = (vpn == vaddr[`OR1200_ITLB_TAG]) & v;
//
// TLB index is normally vaddr[18:13]. If it is SPR access then index is
// spr_addr[5:0].
//
assign tlb_index = spr_cs ? spr_addr[`OR1200_ITLB_INDXW-1:0] : vaddr[`OR1200_ITLB_INDX];
`ifdef OR1200_BIST
assign itlb_mr_ram_si = mbist_si_i;
assign itlb_tr_ram_si = itlb_mr_ram_so;
assign mbist_so_o = itlb_tr_ram_so;
`endif
//
// Instantiation of ITLB Match Registers
//
or1200_spram #
(
.aw(6),
.dw(14)
)
itlb_mr_ram
(
.clk(clk),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(itlb_mr_ram_si),
.mbist_so_o(itlb_mr_ram_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.ce(tlb_mr_en),
.we(tlb_mr_we),
//.oe(1'b1),
.addr(tlb_index),
.di(tlb_mr_ram_in),
.doq(tlb_mr_ram_out)
);
//
// Instantiation of ITLB Translate Registers
//
or1200_spram #
(
.aw(6),
.dw(22)
)
itlb_tr_ram
(
.clk(clk),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(itlb_tr_ram_si),
.mbist_so_o(itlb_tr_ram_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.ce(tlb_tr_en),
.we(tlb_tr_we),
//.oe(1'b1),
.addr(tlb_index),
.di(tlb_tr_ram_in),
.doq(tlb_tr_ram_out)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; double PI = acos(-1); double EPS = 1e-7; int INF = 1000000000; int MOD = 1000000007; int MAXINT = 2147483647; long long INFLL = 1000000000000000000LL; long long MAXLL = 9223372036854775807LL; int mx[8] = {-1, 1, 0, 0, -1, -1, 1, 1}; int my[8] = {0, 0, -1, 1, -1, 1, -1, 1}; int x, k, p; double per; int lim = (1 << 8) - 1; double dp[205][235][2][1 << 8]; bool vs[205][235][2][1 << 8]; double go(int pos, int cons, int t, int mask) { if (vs[pos][cons][t][mask]) return dp[pos][cons][t][mask]; vs[pos][cons][t][mask] = 1; double &ret = dp[pos][cons][t][mask]; ret = 0.0; if (pos == 0) { if (mask == 0) { if (t == 1) return ret = 8; else return ret = 8 + cons; } else { int co = 0; while (mask % 2 == 0) { co++; mask /= 2; } return ret = co; } } if (mask < lim) { ret += (1.0 - per) * go(pos - 1, cons, t, mask + 1); } else { if (t == 0) ret += (1.0 - per) * go(pos - 1, 1, 1, 0); else ret += (1.0 - per) * go(pos - 1, cons, 0, 0); } bool d = mask & (1 << 7); if (d) mask -= (1 << 7); if (d == t) { ret += per * go(pos - 1, cons + 1, d, 2 * mask); } else { ret += per * go(pos - 1, 1, d, 2 * mask); } return ret; } int main() { scanf( %d%d%d , &x, &k, &p); per = (double)p / 100.0; int mask = 0; int cons = 0; bool t = (x & (1 << 8)); for (int(a) = (0); (a) <= (30); (a)++) { if (a <= 7) { if (x & (1 << a)) mask += (1 << a); } else { if (t && ((x & (1 << a)) > 0)) cons++; if (t && ((x & (1 << a)) == 0)) break; if (!t && ((x & (1 << a)) == 0)) cons++; if (!t && ((x & (1 << a)) > 0)) break; } } printf( %.10lf n , go(k, cons, t, mask)); } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); int n, p, a[100000], sum = 0; cin >> n >> p; for (int i = 0; i < n; i++) { cin >> a[i]; sum += a[i]; sum %= p; } sum = (sum + p - (a[0] % p)) % p; int cur = a[0] % p, ans = cur + sum; for (int i = 1; i < n - 1; ++i) { cur = (cur + a[i]) % p, sum = (sum + p - (a[i] % p)) % p; ans = max(ans, cur + sum); } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 5; int ls[N << 2], rs[N << 2], rt[N << 2], sum[N << 2]; int rcnt; void update(int &rt, int l, int r, int pos) { if (rt == 0) rt = ++rcnt; if (l == r) { sum[rt]++; return; } int mid = (l + r) >> 1; if (pos <= mid) { update(ls[rt], l, mid, pos); } else { update(rs[rt], mid + 1, r, pos); } sum[rt] = sum[ls[rt]] + sum[rs[rt]]; } int query(int &rt, int l, int r, int ql, int qr) { if (rt == 0) return 0; if (ql <= l && qr >= r) return sum[rt]; int mid = (l + r) >> 1, res = 0; if (ql <= mid) res += query(ls[rt], l, mid, ql, qr); if (qr > mid) res += query(rs[rt], mid + 1, r, ql, qr); return res; } int n, k; struct node { int x, r, f; bool operator<(const node &z) const { return r > z.r; } } a[N]; const int low = 1000000000; int main() { scanf( %d %d , &n, &k); for (int i = 1; i <= n; ++i) { scanf( %d %d %d , &a[i].x, &a[i].r, &a[i].f); } sort(a + 1, a + n + 1); long long ans = 0; for (int i = 1; i <= n; ++i) { for (int j = a[i].f - k; j <= a[i].f + k; ++j) { if (j < 1 || j > 10000) continue; ans += query(rt[j], 1, low, max(1, a[i].x - a[i].r), min(low, a[i].x + a[i].r)); } update(rt[a[i].f], 1, low, a[i].x); } cout << ans << endl; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2004 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [67:0] q;
reg signed [67:0] qs;
initial begin
q = 68'he_12345678_9abcdef0 ** 68'h3;
if (q != 68'hcee3cb96ce96cf000) $stop;
//
q = 68'he_12345678_9abcdef0 ** 68'h5_6789abcd_ef012345;
if (q != 68'h0) $stop;
//
qs = 68'she_12345678_9abcdef0 ** 68'sh3;
if (qs != 68'shcee3cb96ce96cf000) $stop;
//
qs = 68'she_12345678_9abcdef0 ** 68'sh5_6789abcd_ef012345;
if (qs != 68'h0) $stop;
end
reg [67:0] left;
reg [67:0] right;
wire [67:0] outu = left ** right;
wire signed [67:0] outs = $signed(left) ** $signed(right);
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("%d %x %x %x %x\n", cyc, left, right, outu, outs);
`endif
if (cyc==1) begin
left <= 68'h1;
right <= '0;
end
if (cyc==2) begin
if (outu != 68'h1) $stop;
if (outs != 68'h1) $stop;
end
if (cyc==3) begin
left <= 68'he_12345678_9abcdef0;
right <= 68'h3;
end
if (cyc==4) begin
if (outu != 68'hcee3cb96ce96cf000) $stop;
if (outs != 68'hcee3cb96ce96cf000) $stop;
end
if (cyc==5) begin
left <= 68'he_12345678_9abcdef0;
right <= 68'h5_6789abcd_ef012345;
end
if (cyc==6) begin
if (outu != 68'h0) $stop;
if (outs != 68'h0) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
///////////
// This is a wrapper around the vfabric_counter block, which
// makes it into a nice form to get hooked up in our virtual
// fabric
module vfabric_multiport_counter(
clock, resetn, i_start, i_counter_reset,
i_global_size, i_local_size, i_group_size, i_limiter_settings,
i_return_data, i_return_valid,
o_global_id_2, o_global_id_2_valid, i_global_id_2_stall,
o_global_id_1, o_global_id_1_valid, i_global_id_1_stall,
o_global_id_0, o_global_id_0_valid, i_global_id_0_stall,
o_local_id_2, o_local_id_2_valid, i_local_id_2_stall,
o_local_id_1, o_local_id_1_valid, i_local_id_1_stall,
o_local_id_0, o_local_id_0_valid, i_local_id_0_stall,
o_local_id_3, o_local_id_3_valid, i_local_id_3_stall,
o_group_id_2, o_group_id_2_valid, i_group_id_2_stall,
o_group_id_1, o_group_id_1_valid, i_group_id_1_stall,
o_group_id_0, o_group_id_0_valid, i_group_id_0_stall,
o_scalar_group_id, o_scalar_group_id_valid, i_scalar_group_id_stall
);
parameter DATA_WIDTH=32;
input clock;
input resetn;
input i_start;
input i_counter_reset, i_return_valid;
input [DATA_WIDTH-1:0] i_return_data;
input [3*DATA_WIDTH-1:0] i_global_size;
input [3*DATA_WIDTH-1:0] i_local_size;
input [3*DATA_WIDTH-1:0] i_group_size;
input [DATA_WIDTH-1:0] i_limiter_settings;
output [DATA_WIDTH-1:0] o_global_id_2, o_global_id_1, o_global_id_0;
output o_global_id_2_valid, o_global_id_1_valid, o_global_id_0_valid;
input i_global_id_2_stall, i_global_id_1_stall, i_global_id_0_stall;
output [DATA_WIDTH-1:0] o_local_id_2, o_local_id_1, o_local_id_0, o_local_id_3;
output o_local_id_2_valid, o_local_id_1_valid, o_local_id_0_valid, o_local_id_3_valid;
input i_local_id_2_stall, i_local_id_1_stall, i_local_id_0_stall, i_local_id_3_stall;
output [DATA_WIDTH-1:0] o_group_id_2, o_group_id_1, o_group_id_0;
output o_group_id_2_valid, o_group_id_1_valid, o_group_id_0_valid;
input i_group_id_2_stall, i_group_id_1_stall, i_group_id_0_stall;
output [DATA_WIDTH-1:0] o_scalar_group_id;
output o_scalar_group_id_valid;
input i_scalar_group_id_stall;
wire [DATA_WIDTH-1:0] my_global_size[2:0];
wire [DATA_WIDTH-1:0] my_local_size[2:0];
wire [DATA_WIDTH-1:0] my_group_size[2:0];
wire [DATA_WIDTH-1:0] my_global_id[2:0];
wire [DATA_WIDTH-1:0] my_local_id[2:0];
wire [DATA_WIDTH-1:0] my_group_id[2:0];
wire [DATA_WIDTH-1:0] my_scalar_local_id;
wire [DATA_WIDTH-1:0] my_scalar_group_id;
wire [DATA_WIDTH-1:0] my_local_id_3;
wire counter_valid;
wire counter_stall;
assign my_global_size[2] = i_global_size[3*DATA_WIDTH-1:2*DATA_WIDTH];
assign my_global_size[1] = i_global_size[2*DATA_WIDTH-1:DATA_WIDTH];
assign my_global_size[0] = i_global_size[DATA_WIDTH-1:0];
assign my_local_size[2] = i_local_size[3*DATA_WIDTH-1:2*DATA_WIDTH];
assign my_local_size[1] = i_local_size[2*DATA_WIDTH-1:DATA_WIDTH];
assign my_local_size[0] = i_local_size[DATA_WIDTH-1:0];
assign my_group_size[2] = i_group_size[3*DATA_WIDTH-1:2*DATA_WIDTH];
assign my_group_size[1] = i_group_size[2*DATA_WIDTH-1:DATA_WIDTH];
assign my_group_size[0] = i_group_size[DATA_WIDTH-1:0];
assign my_local_id_3 = {my_scalar_group_id[2:0], my_scalar_local_id[28:0]};
vfabric_counter counter_0(
.clock(clock),
.resetn(resetn),
.i_start(i_start),
.i_counter_reset(i_counter_reset),
.i_local_size(my_local_size),
.i_global_size(my_global_size),
.i_group_size(my_group_size),
// The counter values to output to fabric (if needed)
.local_id(my_local_id),
.global_id(my_global_id),
.group_id(my_group_id),
.scalar_local_id(my_scalar_local_id),
.scalar_group_id(my_scalar_group_id),
.o_dataout_valid(counter_valid),
.i_dataout_stall(counter_stall)
);
defparam counter_0.WIDTH = DATA_WIDTH;
wire [DATA_WIDTH-1:0] limiter_data;
wire limiter_valid, limiter_stall;
wire [12*DATA_WIDTH-1:0] mega_counter;
wire [12*DATA_WIDTH-1:0] mega_dataout;
assign mega_counter = {my_local_id_3, my_local_id_3,
my_global_id[2], my_global_id[1], my_global_id[0],
my_local_id[2], my_local_id[1], my_local_id[0],
my_group_id[2], my_group_id[1], my_group_id[0],
my_scalar_group_id};
fanout_splitter mega_splitter(.clock(clock), .resetn(resetn),
.i_datain(mega_counter), .i_datain_valid(counter_valid),
.o_datain_stall(counter_stall), .o_dataout(mega_dataout),
.i_dataout_stall({i_local_id_3_stall, limiter_stall,
i_global_id_2_stall, i_global_id_1_stall, i_global_id_0_stall,
i_local_id_2_stall, i_local_id_1_stall, i_local_id_0_stall,
i_group_id_2_stall, i_group_id_1_stall, i_group_id_0_stall,
i_scalar_group_id_stall}),
.o_dataout_valid({o_local_id_3_valid, limiter_valid,
o_global_id_2_valid, o_global_id_1_valid, o_global_id_0_valid,
o_local_id_2_valid, o_local_id_1_valid, o_local_id_0_valid,
o_group_id_2_valid, o_group_id_1_valid, o_group_id_0_valid,
o_scalar_group_id_valid}));
defparam mega_splitter.DATA_WIDTH = 12*DATA_WIDTH;
defparam mega_splitter.NUM_FANOUTS = 12;
assign o_scalar_group_id = mega_dataout[DATA_WIDTH-1:0];
assign o_group_id_0 = mega_dataout[2*DATA_WIDTH-1:DATA_WIDTH];
assign o_group_id_1 = mega_dataout[3*DATA_WIDTH-1:2*DATA_WIDTH];
assign o_group_id_2 = mega_dataout[4*DATA_WIDTH-1:3*DATA_WIDTH];
assign o_local_id_0 = mega_dataout[5*DATA_WIDTH-1:4*DATA_WIDTH];
assign o_local_id_1 = mega_dataout[6*DATA_WIDTH-1:5*DATA_WIDTH];
assign o_local_id_2 = mega_dataout[7*DATA_WIDTH-1:6*DATA_WIDTH];
assign o_global_id_0 = mega_dataout[8*DATA_WIDTH-1:7*DATA_WIDTH];
assign o_global_id_1 = mega_dataout[9*DATA_WIDTH-1:8*DATA_WIDTH];
assign o_global_id_2 = mega_dataout[10*DATA_WIDTH-1:9*DATA_WIDTH];
assign limiter_data = mega_dataout[11*DATA_WIDTH-1:10*DATA_WIDTH];
assign o_local_id_3 = mega_dataout[12*DATA_WIDTH-1:11*DATA_WIDTH];
vfabric_limiter limiter0(.clock(clock), .resetn(resetn),
.i_datain(limiter_data), .i_datain_valid(limiter_valid),
.o_datain_stall(limiter_stall),
.i_return_data(i_return_data), .i_return_valid(i_return_valid),
.i_counter_reset(i_counter_reset), .i_limiter_settings(i_limiter_settings));
defparam limiter0.DATA_WIDTH = DATA_WIDTH;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A41OI_TB_V
`define SKY130_FD_SC_MS__A41OI_TB_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a41oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg A4;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
A4 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 A4 = 1'b0;
#100 B1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 A4 = 1'b1;
#280 B1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 A4 = 1'b0;
#460 B1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 B1 = 1'b1;
#660 A4 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 B1 = 1'bx;
#840 A4 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ms__a41oi dut (.A1(A1), .A2(A2), .A3(A3), .A4(A4), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A41OI_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__A21OI_FUNCTIONAL_PP_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__a21oi (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21OI_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; #define _ ios_base::sync_with_stdio(0);cin.tie(0); #define endl n typedef long long ll; const int INF = 0x3f3f3f3f; const ll LINF = 0x3f3f3f3f3f3f3f3fll; int main(){ _ int n; cin >> n; vector<int> a(n); for(int& i : a) cin >> i; auto oa = a; sort(oa.begin(), oa.end()); auto it = unique(oa.begin(), oa.end()); oa.resize(distance(oa.begin(), it)); map<int,int> mp; int m = oa.size(); for(int i = 0; i < m; i++) mp[oa[i]] = i; for(auto& i : a) i = mp[i]; vector<vector<int>> ct(m); for(int i = 0; i < n; i++) ct[a[i]].push_back(i); vector<vector<int>> g(n); for(int i = 0; i < n-1; i++) { int u, v; cin >> u >> v; u--, v--; g[u].push_back(v); g[v].push_back(u); } int time = 0; vector<int> in(n,-1), out(n); function<void(int)> tour = [&] (int v) { in[v] = time; for(auto u : g[v]) if(in[u] == -1) tour(u); out[v] = time++; }; tour(0); auto very_bad = [&] () { cout << 0 << endl; exit(0); }; vector<int> sum(n+1, 0); auto update = [&] (int l, int r, int x) { sum[l] += x, sum[r + 1] -= x; }; for(int i = 0; i < m; i++) if(ct[i].size() > 1) { vector<pair<int,int>> aux; for(auto u : ct[i]) aux.push_back({out[u], u}); sort(aux.begin(), aux.end()); set<int> cur; int anc = -1, nanc = 0; for(auto [outt, u] : aux) { int l = in[u], r = out[u]; if(nanc and r > out[anc]) very_bad(); auto itl = cur.lower_bound(l); auto itr = cur.upper_bound(r); if(itl != itr) { anc = u, nanc++; if(itl != cur.begin() or itr != cur.end()) very_bad(); } if(nanc > 2) very_bad(); cur.insert(r); } if(nanc == 0) { for(auto u : ct[i]) update(in[u], out[u], 1); } else { bool found = false; int good_child = -1; for(auto u : g[anc]) if(out[u] < out[anc]) { int l = in[u], r = out[u]; auto itl = cur.lower_bound(l); auto itr = cur.upper_bound(r); if(itl != itr) { if(found) very_bad(); found = true; good_child = u; } } update(0, n-1, 1); update(in[good_child], out[good_child], -1); for(auto u : ct[i]) if(u != anc) { update(in[u], out[u], 1); } } } int ans = 0; for(int i = 0; i < n; i++) { if(i) sum[i] += sum[i-1]; if(!sum[i]) { ans++; } } cout << ans << endl; return 0; } |
/*
* 16-bit bitwise rotate module for Zet
* Copyright (C) 2008-2010 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module zet_rxr16 (
input [15:0] x,
input ci,
input [ 4:0] y,
input e,
output reg [15:0] w,
output reg co
);
always @(x or ci or y or e)
case (y)
default: {co,w} <= {ci,x};
5'd01: {co,w} <= e ? {x[0], ci, x[15:1]} : {ci, x[0], x[15:1]};
5'd02: {co,w} <= e ? {x[ 1:0], ci, x[15: 2]} : {ci, x[ 1:0], x[15: 2]};
5'd03: {co,w} <= e ? {x[ 2:0], ci, x[15: 3]} : {ci, x[ 2:0], x[15: 3]};
5'd04: {co,w} <= e ? {x[ 3:0], ci, x[15: 4]} : {ci, x[ 3:0], x[15: 4]};
5'd05: {co,w} <= e ? {x[ 4:0], ci, x[15: 5]} : {ci, x[ 4:0], x[15: 5]};
5'd06: {co,w} <= e ? {x[ 5:0], ci, x[15: 6]} : {ci, x[ 5:0], x[15: 6]};
5'd07: {co,w} <= e ? {x[ 6:0], ci, x[15: 7]} : {ci, x[ 6:0], x[15: 7]};
5'd08: {co,w} <= e ? {x[ 7:0], ci, x[15: 8]} : {ci, x[ 7:0], x[15: 8]};
5'd09: {co,w} <= e ? {x[ 8:0], ci, x[15: 9]} : {ci, x[ 8:0], x[15: 9]};
5'd10: {co,w} <= e ? {x[ 9:0], ci, x[15:10]} : {ci, x[ 9:0], x[15:10]};
5'd11: {co,w} <= e ? {x[10:0], ci, x[15:11]} : {ci, x[10:0], x[15:11]};
5'd12: {co,w} <= e ? {x[11:0], ci, x[15:12]} : {ci, x[11:0], x[15:12]};
5'd13: {co,w} <= e ? {x[12:0], ci, x[15:13]} : {ci, x[12:0], x[15:13]};
5'd14: {co,w} <= e ? {x[13:0], ci, x[15:14]} : {ci, x[13:0], x[15:14]};
5'd15: {co,w} <= e ? {x[14:0], ci, x[15]} : {ci, x[14:0], x[15]};
5'd16: {co,w} <= {x,ci};
endcase
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, a[27], sum, gcd; int odd; int _gcd(int x, int y) { if (x == 0 or x == y) return y; if (x > y) swap(x, y); while (y % x) { y %= x; swap(x, y); } return x; } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , a + i); if (a[i] & 1) odd++; sum += a[i]; gcd = _gcd(gcd, a[i]); } if (odd > 1) { printf( %d n , 0); int k = 0; string s(sum, 0 ); for (int i = 0; i < n; i++) { int j = 0; while (j < a[i]) { s[j + k] = a + i; j++; } k += a[i]; } cout << s << endl; return 0; } for (int i = 0; i < n; i++) a[i] /= gcd; sum /= gcd; printf( %d n , gcd); if (odd) { string s(sum, 0 ); int k = 0; for (int i = 0; i < n; i++) { int j = 0; while (j < a[i] / 2) { s[j + k] = a + i; s[sum - 1 - j - k] = a + i; j++; } if (a[i] & 1) odd = i; k += a[i] / 2; } s[k] = odd + a ; for (int i = 0; i < gcd; i++) cout << s; cout << endl; } else { string s(sum, 0 ); string t(sum, 0 ); int k = 0; for (int i = 0; i < n; i++) { int j = 0; while (j < a[i]) { s[j + k] = a + i; t[sum - 1 - j - k] = a + i; t[sum - 1 - j - k] = a + i; j++; } k += a[i]; } for (int i = 0; i < gcd / 2; i++) cout << s << t; cout << endl; } } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:34:40 11/07/2015
// Design Name: Encoder
// Module Name: C:/Users/Camilo/Documents/Xilinx_Workspace/Transflineal/enconder_tst.v
// Project Name: Transflineal
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Encoder
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module enconder_tst;
// Inputs
reg [15:0] Theta;
reg [15:0] Ref;
reg [31:0] DataIn;
// Outputs
wire [7:0] Address;
wire [31:0] DataOut;
// Instantiate the Unit Under Test (UUT)
Encoder uut (
.Theta(Theta),
.Ref(Ref),
.DataIn(DataIn),
.Address(Address),
.DataOut(DataOut)
);
initial begin
// Initialize Inputs
Theta = 45;
Ref = 45;
DataIn = 1234;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#10;
Theta = 47;
#10;
Theta = 48;
#10;
Theta = 43;
#10;
Theta = 40;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct node { int t, n; } a[200005]; int cmp(const void* a, const void* b) { node* aa = (node*)a; node* bb = (node*)b; if (aa->n > bb->n) { return 1; } else if (aa->n == bb->n) { return bb->t - aa->t; } else { return -1; } } int main() { int n, k; while (~scanf( %d%d , &n, &k)) { int i; for (i = 0; i < n; i++) { scanf( %d , &a[i].n); a[i].t = 1; } for (i = 0; i < n; i++) { scanf( %d , &a[i + n].n); a[i + n].n = k - a[i + n].n; a[i + n].t = 2; } int s1 = 0, s2 = 0; qsort(a, 2 * n, sizeof(a[0]), cmp); for (i = 0; i < 2 * n; i++) { if (a[i].t == 2) { s2++; } else { if (s2) { s2--; s1++; } } } printf( 1 %d n , s1); } return 0; } |
//////////////////////////////////////////////////////////////////////////////
/// Copyright (c) 2014, Ajit Mathew <>
/// All rights reserved.
///
// Redistribution and use in source and binary forms, with or without modification,
/// are permitted provided that the following conditions are met:
///
/// * Redistributions of source code must retain the above copyright notice,
/// this list of conditions and the following disclaimer.
/// * Redistributions in binary form must reproduce the above copyright notice,
/// this list of conditions and the following disclaimer in the documentation and/or
/// other materials provided with the distribution.
///
/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
/// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
/// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
/// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
/// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
/// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
/// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
/// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
/// POSSIBILITY OF SUCH DAMAGE.
///
///
/// * http://opensource.org/licenses/MIT
/// * http://copyfree.org/licenses/mit/license.txt
///
//////////////////////////////////////////////////////////////////////////////
module counter
#(
parameter N=1, // counter width
M=1 // modM
)
(
input wire clk, reset,
output wire max_tck,
output wire [N-1:0] q
);
reg [N-1:0] x;
wire [N-1:0] x_n;
always @(posedge clk)
if (reset)
x <= 0;
else
x <= x_n;
assign x_n = (x==(M-1)) ? 0 : x + 1;
assign q = x;
assign max_tck = (x==(M-1)) ? 1'b1 : 1'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; int num = 0; int cnt[1000] = {0}; int candidate[400005] = {0}; string s; bool check(int added) { if (added % 2) return false; if (n % (added + num)) return false; if ((n / (added + num)) % 2 == 0) return false; return true; } int main() { cin >> n >> s; for (int i = 0; i < n; ++i) cnt[s[i]]++; for (int i = 0; i < 200; ++i) { if (cnt[i] % 2) { cnt[i] -= 1; candidate[num++] = i; } } if (num == 0) { string before = ; string after = ; for (int j = 40; j < 130; ++j) { while (cnt[j] >= 2) { cnt[j] -= 2; before += j; after += j; } } cout << 1 << endl; reverse(before.begin(), before.end()); cout << before + after << endl; return 0; } int added = 0; while (!check(added)) ++added; for (int i = 40; i < 130; ++i) { if (!added) break; if (cnt[i] > added) { for (int j = 0; j < added; ++j) candidate[num++] = i; cnt[i] -= added; added = 0; } else { for (int j = 0; j < cnt[i]; ++j) candidate[num++] = i; added -= cnt[i]; cnt[i] = 0; } } cout << num << endl; for (int i = 0; i < num; ++i) { string before = ; string after = ; after += char(candidate[i]); int remain = (n / num) - 1; for (int j = 40; j < 130; ++j) { if (!remain) break; if (cnt[j] >= remain) { for (int k = 0; k < remain / 2; ++k) { before += char(j); after += char(j); } cnt[j] -= remain; remain = 0; } else { for (int k = 0; k < cnt[j] / 2; ++k) { before += char(j); after += char(j); } remain -= cnt[j]; cnt[j] = 0; } } reverse(before.begin(), before.end()); cout << before + after << ; } return 0; } |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : pcie_bram_top_v6.v
// Version : 2.4
//--
//-- Description: BlockRAM top level module for Virtex6 PCIe Block
//--
//--
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module pcie_bram_top_v6
#(
parameter DEV_CAP_MAX_PAYLOAD_SUPPORTED = 0,
parameter VC0_TX_LASTPACKET = 31,
parameter TLM_TX_OVERHEAD = 24,
parameter TL_TX_RAM_RADDR_LATENCY = 1,
parameter TL_TX_RAM_RDATA_LATENCY = 2,
parameter TL_TX_RAM_WRITE_LATENCY = 1,
parameter VC0_RX_LIMIT = 'h1FFF,
parameter TL_RX_RAM_RADDR_LATENCY = 1,
parameter TL_RX_RAM_RDATA_LATENCY = 2,
parameter TL_RX_RAM_WRITE_LATENCY = 1
)
(
input user_clk_i,
input reset_i,
input mim_tx_wen,
input [12:0] mim_tx_waddr,
input [71:0] mim_tx_wdata,
input mim_tx_ren,
input mim_tx_rce,
input [12:0] mim_tx_raddr,
output [71:0] mim_tx_rdata,
input mim_rx_wen,
input [12:0] mim_rx_waddr,
input [71:0] mim_rx_wdata,
input mim_rx_ren,
input mim_rx_rce,
input [12:0] mim_rx_raddr,
output [71:0] mim_rx_rdata
);
// TX calculations
localparam MPS_BYTES = ((DEV_CAP_MAX_PAYLOAD_SUPPORTED == 0) ? 128 :
(DEV_CAP_MAX_PAYLOAD_SUPPORTED == 1) ? 256 :
(DEV_CAP_MAX_PAYLOAD_SUPPORTED == 2) ? 512 :
1024 );
localparam BYTES_TX = (VC0_TX_LASTPACKET + 1) * (MPS_BYTES + TLM_TX_OVERHEAD);
localparam ROWS_TX = 1;
localparam COLS_TX = ((BYTES_TX <= 4096) ? 1 :
(BYTES_TX <= 8192) ? 2 :
(BYTES_TX <= 16384) ? 4 :
(BYTES_TX <= 32768) ? 8 :
18
);
// RX calculations
localparam ROWS_RX = 1;
localparam COLS_RX = ((VC0_RX_LIMIT < 'h0200) ? 1 :
(VC0_RX_LIMIT < 'h0400) ? 2 :
(VC0_RX_LIMIT < 'h0800) ? 4 :
(VC0_RX_LIMIT < 'h1000) ? 8 :
18
);
initial begin
$display("[%t] %m ROWS_TX %0d COLS_TX %0d", $time, ROWS_TX, COLS_TX);
$display("[%t] %m ROWS_RX %0d COLS_RX %0d", $time, ROWS_RX, COLS_RX);
end
pcie_brams_v6 #(.NUM_BRAMS (COLS_TX),
.RAM_RADDR_LATENCY(TL_TX_RAM_RADDR_LATENCY),
.RAM_RDATA_LATENCY(TL_TX_RAM_RDATA_LATENCY),
.RAM_WRITE_LATENCY(TL_TX_RAM_WRITE_LATENCY))
pcie_brams_tx
(
.user_clk_i(user_clk_i),
.reset_i(reset_i),
.waddr(mim_tx_waddr),
.wen(mim_tx_wen),
.ren(mim_tx_ren),
.rce(mim_tx_rce),
.wdata(mim_tx_wdata),
.raddr(mim_tx_raddr),
.rdata(mim_tx_rdata)
);
pcie_brams_v6 #(.NUM_BRAMS (COLS_RX),
.RAM_RADDR_LATENCY(TL_RX_RAM_RADDR_LATENCY),
.RAM_RDATA_LATENCY(TL_RX_RAM_RDATA_LATENCY),
.RAM_WRITE_LATENCY(TL_RX_RAM_WRITE_LATENCY))
pcie_brams_rx
(
.user_clk_i(user_clk_i),
.reset_i(reset_i),
.waddr(mim_rx_waddr),
.wen(mim_rx_wen),
.ren(mim_rx_ren),
.rce(mim_rx_rce),
.wdata(mim_rx_wdata),
.raddr(mim_rx_raddr),
.rdata(mim_rx_rdata)
);
endmodule // pcie_bram_top
|
module LCD(
input clk,
input rst,
input [127:0] upRow,
input [127:0] doRow,
output e,
output rs,
output rw,
output [3:0] sf
);
reg [23:0] count = 0;
reg refresh;
reg [5:0] Code;
assign {e, rs, rw, sf} = {refresh, Code};
// count
always@(posedge clk, posedge rst)
begin
if(rst) count <= count;
else count <= (count[23:17] < 78) ? count+1 : 0;
end
// LCD
always@(posedge clk, posedge rst)
begin
if(rst) Code <= 6'h10;
else begin
case(count[23:17])
0 : Code <= 6'h03; // power-on
1 : Code <= 6'h03;
2 : Code <= 6'h03;
3 : Code <= 6'h02;
4 : Code <= 6'h02; // function set
5 : Code <= 6'h08;
6 : Code <= 6'h00; // entry
7 : Code <= 6'h06;
8 : Code <= 6'h00; // display on/off
9 : Code <= 6'h0C;
10: Code <= 6'h00; // clear display
11: Code <= 6'h01;
12: Code <= {2'b10,upRow[127:124]};
13: Code <= {2'b10,upRow[123:120]};
14: Code <= {2'b10,upRow[119:116]};
15: Code <= {2'b10,upRow[115:112]};
16: Code <= {2'b10,upRow[111:108]};
17: Code <= {2'b10,upRow[107:104]};
18: Code <= {2'b10,upRow[103:100]};
19: Code <= {2'b10,upRow[99 :96 ]};
20: Code <= {2'b10,upRow[95 :92 ]};
21: Code <= {2'b10,upRow[91 :88 ]};
22: Code <= {2'b10,upRow[87 :84 ]};
23: Code <= {2'b10,upRow[83 :80 ]};
24: Code <= {2'b10,upRow[79 :76 ]};
25: Code <= {2'b10,upRow[75 :72 ]};
26: Code <= {2'b10,upRow[71 :68 ]};
27: Code <= {2'b10,upRow[67 :64 ]};
28: Code <= {2'b10,upRow[63 :60 ]};
29: Code <= {2'b10,upRow[59 :56 ]};
30: Code <= {2'b10,upRow[55 :52 ]};
31: Code <= {2'b10,upRow[51 :48 ]};
32: Code <= {2'b10,upRow[47 :44 ]};
33: Code <= {2'b10,upRow[43 :40 ]};
34: Code <= {2'b10,upRow[39 :36 ]};
35: Code <= {2'b10,upRow[35 :32 ]};
36: Code <= {2'b10,upRow[31 :28 ]};
37: Code <= {2'b10,upRow[27 :24 ]};
38: Code <= {2'b10,upRow[23 :20 ]};
39: Code <= {2'b10,upRow[19 :16 ]};
40: Code <= {2'b10,upRow[15 :12 ]};
41: Code <= {2'b10,upRow[11 :8 ]};
42: Code <= {2'b10,upRow[7 :4 ]};
43: Code <= {2'b10,upRow[3 :0 ]};
44: Code <= 6'b001100;
45: Code <= 6'b000000;
46: Code <= {2'b10,doRow[127:124]};
47: Code <= {2'b10,doRow[123:120]};
48: Code <= {2'b10,doRow[119:116]};
49: Code <= {2'b10,doRow[115:112]};
50: Code <= {2'b10,doRow[111:108]};
51: Code <= {2'b10,doRow[107:104]};
52: Code <= {2'b10,doRow[103:100]};
53: Code <= {2'b10,doRow[99 :96 ]};
54: Code <= {2'b10,doRow[95 :92 ]};
55: Code <= {2'b10,doRow[91 :88 ]};
56: Code <= {2'b10,doRow[87 :84 ]};
57: Code <= {2'b10,doRow[83 :80 ]};
58: Code <= {2'b10,doRow[79 :76 ]};
59: Code <= {2'b10,doRow[75 :72 ]};
60: Code <= {2'b10,doRow[71 :68 ]};
61: Code <= {2'b10,doRow[67 :64 ]};
62: Code <= {2'b10,doRow[63 :60 ]};
63: Code <= {2'b10,doRow[59 :56 ]};
64: Code <= {2'b10,doRow[55 :52 ]};
65: Code <= {2'b10,doRow[51 :48 ]};
66: Code <= {2'b10,doRow[47 :44 ]};
67: Code <= {2'b10,doRow[43 :40 ]};
68: Code <= {2'b10,doRow[39 :36 ]};
69: Code <= {2'b10,doRow[35 :32 ]};
70: Code <= {2'b10,doRow[31 :28 ]};
71: Code <= {2'b10,doRow[27 :24 ]};
72: Code <= {2'b10,doRow[23 :20 ]};
73: Code <= {2'b10,doRow[19 :16 ]};
74: Code <= {2'b10,doRow[15 :12 ]};
75: Code <= {2'b10,doRow[11 :8 ]};
76: Code <= {2'b10,doRow[7 :4 ]};
77: Code <= {2'b10,doRow[3 :0 ]};
default: Code <= 6'h10;
endcase
end
end
// refresh
always@(posedge clk, posedge rst)
begin
if(rst) refresh <= 1;
else refresh <= count[16];
end
endmodule |
#include <bits/stdc++.h> using namespace std; vector<vector<int>> adj; bool vis[200000 + 9]; int cntnode; map<int, int> colorcnt; int c[200000 + 9]; int mx; void dfs(int node) { if (vis[node]) { return; } cntnode++; colorcnt[c[node]]++; mx = max(mx, colorcnt[c[node]]); vis[node] = 1; for (int i = 0; i < (int)adj[node].size(); i++) { int ch = adj[node][i]; dfs(ch); } } int main() { int n, m, k; cin >> n >> m >> k; adj.resize(n); for (int i = 0; i < n; i++) { cin >> c[i]; } for (int i = 0; i < m; i++) { int x, y; cin >> x >> y; adj[x - 1].push_back(y - 1); adj[y - 1].push_back(x - 1); } int sum = 0; for (int i = 0; i < n; i++) { cntnode = 0; colorcnt.clear(); mx = 0; if (!vis[i]) { dfs(i); } sum += (cntnode - mx); } cout << sum; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND3_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__NAND3_PP_BLACKBOX_V
/**
* nand3: 3-input NAND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nand3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND3_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A2BB2O_BLACKBOX_V
`define SKY130_FD_SC_HDLL__A2BB2O_BLACKBOX_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a2bb2o (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A2BB2O_BLACKBOX_V
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
/**
* Reference:
* Nestoras Tzartzanis, EE 577B Verilog Example, Jan 25, 1996
* http://www-scf.usc.edu/~ee577/tutorial/verilog/counter.v
*/
// Behavioral model for the 32-bit program counter
module program_counter2 (next_pc,rst,clk);
// Output signals...
// Incremented value of the program counter
output [0:31] next_pc;
// ===============================================================
// Input signals
// Clock signal for the program counter
input clk;
// Reset signal for the program counter
input rst;
/**
* May also include: branch_offset[n:0], is_branch
* Size of branch offset is specified in the Instruction Set
* Architecture
*/
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg [0:31] next_pc; // Output signals
reg [0:31] temp_pc; // Output signals
// ===============================================================
always @(posedge clk)
begin
// If the reset signal sis set to HIGH
if(rst)
begin
// Set its value to ZERO
next_pc<=32'd0;
temp_pc<=32'd0;
end
else
begin
temp_pc<=temp_pc+32'd4;
next_pc<=temp_pc>>2;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct seg { vector<int> id; map<pair<int, int>, int> st; int getid(int l, int r) { int L = lower_bound(id.begin(), id.end(), l) - id.begin(); int R = upper_bound(id.begin(), id.end(), r) - id.begin() - 1; if (L > R) return -1; return st[make_pair(L, R)]; } } tr[20000]; vector<pair<int, int> > res; int cur; int merge(int x, int y) { if (x == -1 || y == -1) return max(x, y); else { res.emplace_back(x, y); cur++; return cur; } } int blk, tot, Tid = 0; int n, q, a[5000], Id[5000], l[5000], r[5000]; int solve(int l, int r, vector<int> id) { Tid++; int k; tr[k = Tid].id = id; if (l == r) { tr[Tid].st[pair<int, int>(0, 0)] = id[0]; return Tid; } int mid = (l + r) >> 1; vector<int> lid, rid; for (auto x : id) if (a[x] <= mid) lid.push_back(x); else rid.push_back(x); int ls = solve(l, mid, lid), rs = solve(mid + 1, r, rid); for (int i = 0; i < id.size(); i++) for (int j = i; j < id.size(); j++) tr[k].st[pair<int, int>(i, j)] = merge(tr[ls].getid(id[i], id[j]), tr[rs].getid(id[i], id[j])); return k; } int main() { scanf( %d%d , &n, &q); blk = sqrt(q); cur = n; for (int i = 1; i <= (tot = n / blk); i++) l[i] = r[i - 1] + 1, r[i] = i * blk; if (tot * blk != n) l[++tot] = r[tot - 1] + 1, r[tot] = n; for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i <= tot; i++) { vector<int> id; for (int j = 1; j <= n; j++) if (l[i] <= a[j] && a[j] <= r[i]) id.push_back(j); Id[i] = solve(l[i], r[i], id); } vector<int> ans; for (int l, r; q--;) { scanf( %d%d , &l, &r); int rest = -1; for (int i = 1; i <= tot; i++) rest = merge(rest, tr[Id[i]].getid(l, r)); ans.push_back(rest); } printf( %d n , cur); for (auto x : res) printf( %d %d n , x.first, x.second); for (int x : ans) printf( %d , x); } |
#include <bits/stdc++.h> using namespace std; struct no { int r; int l; int p; }; int main() { int n; double v; double a[110]; double b[110]; cin >> n >> v; for (int i = 0; i < n; i++) { cin >> a[i]; } for (int i = 0; i < n; i++) { cin >> b[i]; if (b[i] == 0) { cout << 0.0 << endl; return 0; } } double cu = a[0], ni = b[0]; double aa = 0; for (int i = 1; i < n; i++) { if (b[i] / a[i] < ni / cu) { cu = a[i]; ni = b[i]; } } aa = ni / cu; double ans = 0; for (int i = 0; i < n; i++) ans += aa * a[i]; if (ans > v) ans = v; cout << ans << endl; return 0; } |
module single_register(datain, dataout, clk, clr, WE);
input [31:0] datain;
output [31:0] dataout;
input clk, clr, WE;
reg [31:0] register;
always @(posedge clk or posedge clr)
begin
if(clr)
register = 0;
else
if(WE == 1)
register = datain;
end
assign dataout = register;
endmodule
module single_register_Testbench;
reg [31:0] inputA;
wire [31:0] result;
reg clk, clr, WE;
single_register UUT(inputA,result, clk, clr, WE);
initial begin
clk = 0;
clr = 0;
WE = 1;
#20 inputA = 12;
clk = !clk;
#40 inputA = 24;
clk = !clk;
#40 inputA = 36;
clk = !clk;
WE = 0;
#40 inputA = 48;
clk = !clk;
clr = 1;
#40 inputA = 1024;
clk = !clk;
clr = 0;
#40 inputA = 2048;
clk = !clk;
WE = 1;
#40 inputA = 4096;
clk = !clk;
#40 inputA = 12345;
clk = !clk;
end
endmodule
module mux4to1(datain0, datain1, datain2, datain3, dataout, select);
input [31:0] datain0, datain1, datain2, datain3;
input[1:0] select;
output [31:0] dataout;
reg [31:0] dataout;
always@(datain0 or datain1 or datain2 or datain3 or select)
begin
case(select)
2'b00: dataout = datain0;
2'b01: dataout = datain1;
2'b10: dataout = datain2;
2'b11: dataout = datain3;
endcase
end
endmodule
module mux4to1_Testbench;
reg [31:0] inputA;
reg [31:0] inputB;
reg [31:0] inputC;
reg [31:0] inputD;
reg [1:0] select;
wire [31:0] result;
mux4to1 UUT(inputA,inputB, inputC, inputD, result, select);
initial begin
inputA = 1;
inputB = 2;
inputC = 3;
inputD = 4;
#20 select = 0;
#40 select = 1;
#40 select = 2;
#40 select = 3;
end
endmodule
module signextd(datain, dataout);
input [15:0] datain;
output [31:0] dataout;
reg [31:0] dataout;
integer i;
always @ (datain)
begin
dataout = $signed(datain);
end
endmodule
module signextd_Testbench;
reg [15:0] inputA;
wire [31:0] result;
signextd UTT(inputA,result);
initial begin
#20 inputA = 1234;
#40 inputA = 64000;
#40 inputA = 35;
end
endmodule
module shiftleft2(datain, dataout);
input [31:0] datain;
output [31:0] dataout;
reg [31:0] dataout;
always @ (datain)
begin
dataout = datain * 4;
end
endmodule
module shiftleft2_Testbench;
reg [31:0] inputA;
wire [31:0] result;
shiftleft2 UUT(inputA,result);
initial begin
#20 inputA = 32'b0000_0000_0000_0000_1010_1010_1010_1010;
#40 inputA = 32'b0000_0000_0000_0000_1111_1111_1111_1111;
#40 inputA = 32'b1110_1110_1110_1110_1110_1110_1110_1110;
#40 inputA = 32'b1001_1001_1001_1001_0110_0110_0110_0110;
#40 inputA = 32'b0000_1000_0001_0000_0100_0010_0010_0101;
#40 inputA = 32'b0000_1111_0000_1111_0000_1111_0000_1111;
#40 inputA = 32'b1111_0000_1111_0000_1111_0000_1111_0000;
#40 inputA = 32'b0110_0011_1100_0110_0011_1100_0110_0011;
end
initial
#340 $stop;
endmodule
/* concatenate pcin[31-28] with datain[27-0] to form a jump address*/
module concatenate4to28(datain, pcin, pcout);
input [31:0] datain, pcin;
output [31:0] pcout;
reg [31:0] pcout;
always @ (datain or pcin)
begin
pcout = {pcin[31:28],datain[27:0]};
end
endmodule
module concatenate4to28_Testbench;
reg [31:0] inputA, inputB;
wire [31:0] result;
concatenate4to28 UUT(inputA, inputB, result);
initial begin
#20 inputA = 32'b0000_0000_0000_0000_1010_1010_1010_1010;
inputB = 32'b0000_0000_0000_0000_1111_1111_1111_1111;
#40 inputA = 32'b1110_1110_1110_1110_1110_1110_1110_1110;
inputB = 32'b1001_1001_1001_1001_0110_0110_0110_0110;
#40 inputA = 32'b0000_1000_0001_0000_0100_0010_0010_0101;
inputB = 32'b0000_1111_0000_1111_0000_1111_0000_1111;
#40 inputA = 32'b1111_0000_1111_0000_1111_0000_1111_0000;
inputB = 32'b0110_0011_1100_0110_0011_1100_0110_0011;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A222OI_SYMBOL_V
`define SKY130_FD_SC_HD__A222OI_SYMBOL_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a222oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
input C1,
input C2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A222OI_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXBN_PP_SYMBOL_V
`define SKY130_FD_SC_LP__DLXBN_PP_SYMBOL_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlxbn (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{clocks|Clocking}}
input GATE_N,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXBN_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long int t; cin >> t; while (t--) { long long int n, k; cin >> n >> k; long long int arr[n]; long long int i; for (i = 0; i <= n - 1; i++) { cin >> arr[i]; } long long int temp = k; vector<long long int> v; long long int sum = 0; for (i = 0; i <= n - 1; i++) { sum = sum + arr[i]; if (sum % 2 != 0 && temp > 1) { v.push_back(i); sum = 0; temp--; } } if (sum % 2 == 0) { cout << NO << n ; } else { v.push_back(n - 1); cout << YES << n ; for (i = 0; i < v.size(); i++) { cout << v[i] + 1 << ; } cout << n ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int n; int ar[50][50]; int dp[51][51]; bool leaf[50]; vector<int> adj[50]; vector<int> adjw[50]; vector<int> leafs; int bad; vector<int> pos; int go(int rem, int now) { if (rem == 0) { return 0; } if (dp[rem][now] != -1) { return dp[rem][now]; } int low = 0; int high = 12500000; while (low < high) { int mid = (low + high + 1) / 2; int temp = rem; for (int i = 0; i < n; i++) { if (!leaf[i] || i == now) { continue; } int cur = 0; while (temp > 0 && ar[now][i] + go(rem - cur - 1, i) >= mid) { cur++; temp--; } } if (temp == 0) { low = mid; } else { high = mid - 1; } } dp[rem][now] = low; return low; } void dfs(int now, int from) { if (leaf[now]) { leafs.push_back(now); } for (int i = 0; i < pos.size(); i++) { if (now == pos[i]) { bad++; } } for (int i = 0; i < adj[now].size(); i++) { int to = adj[now][i]; if (to != from) { dfs(to, now); } } } void dfs(int now, int from, int root, int dist) { ar[root][now] = dist; for (int i = 0; i < adj[now].size(); i++) { int to = adj[now][i]; if (to != from) { dfs(to, now, root, dist + adjw[now][i]); } } } int main() { std::ios::sync_with_stdio(false); cin.tie(0); cin >> n; int maxw = 0; for (int i = 1; i < n; i++) { int a, b, w; cin >> a >> b >> w; a--; b--; adj[a].push_back(b); adj[b].push_back(a); adjw[a].push_back(w); adjw[b].push_back(w); } for (int i = 0; i < n; i++) { dfs(i, -1, i, 0); } for (int i = 0; i <= 50; i++) { for (int j = 0; j <= 50; j++) { dp[i][j] = -1; } } for (int i = 0; i < n; i++) { leaf[i] = adj[i].size() == 1; } int start, m; cin >> start >> m; start--; for (int i = 0; i < m; i++) { int x; cin >> x; x--; pos.push_back(x); } int ans = 12500000; for (int i = 0; i < adj[start].size(); i++) { leafs.clear(); leafs.resize(0); bad = 0; dfs(adj[start][i], start); if (bad == 0) { continue; } int low = 0; int high = 1250000; while (low < high) { int mid = (low + high + 1) / 2; int temp = bad; for (int z = 0; z < leafs.size(); z++) { int cl = leafs[z]; if (cl == start) { continue; } int cur = 0; while (temp > 0 && ar[start][cl] + go(m - cur - 1, cl) >= mid) { cur++; temp--; } } if (temp == 0) { low = mid; } else { high = mid - 1; } } ans = min(ans, low); } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int m = 1e9 + 7; int p = 31; int main() { ios_base::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); ; long long t = 1; cin >> t; while (t--) { long long w, h; cin >> w >> h; long long k1, k2, k3, k4; cin >> k1; vector<long long> points_h1; for (int i = 0; i < k1; i++) { long long x; cin >> x; points_h1.push_back(x); } cin >> k2; vector<long long> points_h2; for (int i = 0; i < k2; i++) { long long x; cin >> x; points_h2.push_back(x); } cin >> k3; vector<long long> points_v1; for (int i = 0; i < k3; i++) { long long x; cin >> x; points_v1.push_back(x); } cin >> k4; vector<long long> points_v2; for (int i = 0; i < k4; i++) { long long x; cin >> x; points_v2.push_back(x); } long long ans = max({w * (points_v1[points_v1.size() - 1] - points_v1[0]), w * (points_v2[points_v2.size() - 1] - points_v2[0]), h * (points_h1[points_h1.size() - 1] - points_h1[0]), h * (points_h2[points_h2.size() - 1] - points_h2[0])}); cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int cur[100005]; int mark[100005]; int sol[400005]; int csol; int n, m; vector<int> E[100005]; inline void dfs(int u, int up) { mark[u] = 1; csol++; sol[csol] = u; cur[u] ^= 1; int last = 0; for (int i = 0; i < E[u].size(); i++) if (E[u][i] != up && mark[E[u][i]] == 0) { if (up == 0 && last != 0) { csol++; sol[csol] = u; cur[u] ^= 1; } dfs(E[u][i], u); last = 1; if (up != 0) { csol++; sol[csol] = u; cur[u] ^= 1; } } if (cur[u]) if (up != 0) { csol++; sol[csol] = up; csol++; sol[csol] = u; cur[u] ^= 1; cur[up] ^= 1; } else { csol++; sol[csol] = u; cur[u] ^= 1; } } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { int p, k; scanf( %d%d , &p, &k); E[p].push_back(k); E[k].push_back(p); } for (int i = 1; i <= n; i++) scanf( %d , &cur[i]); int st = 0; for (int i = 1; i <= n; i++) if (cur[i]) st = i; if (st == 0) { printf( 0 n ); return 0; } dfs(st, 0); int ok = 1; for (int i = 1; i <= n; i++) if (cur[i]) ok = 0; if (ok) { printf( %d n , csol); for (int i = 1; i <= csol; i++) printf( %d , sol[i]); } else printf( -1 n ); } |
#include <bits/stdc++.h> using namespace std; const int maxn = 210; const double eps = 1e-9; int n; int lsh[maxn * 2], ln, K; map<int, int> mt; int To[maxn]; int li[maxn], ri[maxn]; double f[2][maxn][maxn]; double ans[maxn][maxn]; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d%d , &li[i], &ri[i]); lsh[++ln] = li[i]; lsh[++ln] = ri[i]; } sort(lsh + 1, lsh + ln + 1); lsh[0] = lsh[1] - 1; K = 0; for (int i = 1; i <= ln; i++) { if (lsh[i] != lsh[i - 1]) { To[mt[lsh[i]] = ++K] = lsh[i]; } } for (int i = 1; i <= n; i++) { li[i] = mt[li[i]], ri[i] = mt[ri[i]]; } for (int i = 1; i <= n; i++) { for (int x = li[i]; x < ri[i]; x++) { double inow = (double)(To[x + 1] - To[x]) / (To[ri[i]] - To[li[i]]); memset(f, 0, sizeof(f)); int now = 1; f[now][0][0] = 1.0; for (int j = 1; j <= n; j++) { if (i == j) { continue; } int L = To[li[j]], R = To[ri[j]]; now = !now; if (x < li[j]) { for (int x1 = 0; x1 < j; x1++) { for (int x2 = 0; x2 < j - x1; x2++) { if (f[!now][x1][x2] > eps) { double tmp = f[!now][x1][x2]; f[!now][x1][x2] = 0; f[now][x1][x2] += tmp; } } } } else if (ri[j] <= x) { for (int x1 = 0; x1 < j; x1++) { for (int x2 = 0; x2 < j - x1; x2++) { if (f[!now][x1][x2] > eps) { double tmp = f[!now][x1][x2]; f[!now][x1][x2] = 0; f[now][x1 + 1][x2] += tmp; } } } } else { double p1 = (double)(To[x] - L) / (R - L), p2 = (double)(To[x + 1] - To[x]) / (R - L), p3 = (double)(R - To[x + 1]) / (R - L); for (int x1 = 0; x1 < j; x1++) { for (int x2 = 0; x2 < j - x1; x2++) { if (f[!now][x1][x2] > eps) { double tmp = f[!now][x1][x2]; f[!now][x1][x2] = 0; f[now][x1 + 1][x2] += tmp * p1; f[now][x1][x2 + 1] += tmp * p2; f[now][x1][x2] += tmp * p3; } } } } } for (int x1 = 0; x1 < n; x1++) { for (int x2 = 0; x2 < n - x1; x2++) { if (f[now][x1][x2] > eps) { double tmp = f[now][x1][x2], temp = 1.0 / (x2 + 1.0); for (int l = 0; l <= x2; l++) { ans[i][x1 + l + 1] += inow * tmp * temp; } } } } } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { printf( %.10lf , ans[i][j]); } printf( n ); } return 0; } |
// File clk.vhd translated with vhd2vl v2.4 VHDL to Verilog RTL translator
// vhd2vl settings:
// * Verilog Module Declaration Style: 1995
// vhd2vl is Free (libre) Software:
// Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
// http://www.ocean-logic.com
// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
// Modifications (C) 2010 Shankar Giri
// Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL
// http://doolittle.icarus.com/~larry/vhd2vl/
//
// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting
// Verilog for correctness, ideally with a formal verification tool.
//
// You are welcome to redistribute vhd2vl under certain conditions.
// See the license (GPLv2) file included with the source for details.
// The result of translation follows. Its copyright status should be
// considered unchanged from the original VHDL.
// no timescale needed
module clk(
reset,
preset,
qreset,
sysclk,
dsysclk,
esysclk,
ival
);
input reset, preset, qreset, sysclk, dsysclk, esysclk;
input [31:0] ival;
wire reset;
wire preset;
wire qreset;
wire sysclk;
wire dsysclk;
wire esysclk;
wire [31:0] ival;
reg [10 + 3:0] foo;
reg [2:0] baz;
reg [4:7 - 1] egg;
always @(posedge reset or posedge sysclk) begin
if((reset != 1'b 0)) begin
foo <= {(((10 + 3))-((0))+1){1'b1}};
end else begin
foo <= ival[31:31 - ((10 + 3))];
end
end
always @(negedge preset or negedge dsysclk) begin
if((preset != 1'b 1)) begin
baz <= {3{1'b0}};
end else begin
baz <= ival[2:0];
end
end
always @(negedge qreset or negedge esysclk) begin
if((qreset != 1'b 1)) begin
egg <= {(((7 - 1))-((4))+1){1'b0}};
end else begin
egg <= ival[6:4];
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int x[4]; int y[4]; int ii[4] = {1, -1, 0, 0}; int jj[4] = {0, 0, -1, 1}; int main() { ios_base::sync_with_stdio(0); int x1, x2, x3, y1, y2, y3; for (int i = 1; i <= 3; i++) { cin >> x[i] >> y[i]; } set<pair<int, int>> s; long long xx = 0, yy = 0; long long d = 1e9; for (int j = 0; j <= 1000; j++) { for (int i = 0; i <= 1000; i++) { if (abs(x[1] - i) + abs(y[1] - j) + abs(x[2] - i) + abs(y[2] - j) + abs(x[3] - i) + abs(y[3] - j) < d) { xx = i; yy = j; d = abs(x[1] - i) + abs(y[1] - j) + abs(x[2] - i) + abs(y[2] - j) + abs(x[3] - i) + abs(y[3] - j); } } } for (int t = 1; t <= 3; t++) { int i, j; i = xx; j = yy; s.insert({x[t], y[t]}); while (i != x[t] || j != y[t]) { s.insert({i, j}); for (int e = 0; e < 4; e++) { if (abs(i - x[t]) > abs(i + ii[e] - x[t]) || abs(j - y[t]) > abs(j + jj[e] - y[t])) { i += ii[e]; j += jj[e]; break; } } } } cout << s.size() << n ; for (auto p : s) { cout << p.first << << p.second << n ; } } |
(** * Priqueue: Priority Queues *)
(** A _priority queue_ is an abstract data type with the following operations:
- [ empty: priqueue ]
- [ insert: key -> priqueue -> priqueue ]
- [ delete_max: priqueue -> option (key * priqueue) ]
The idea is that you can find (and remove) the highest-priority element.
Priority queues have applications in:
- Discrete-event simulations: The highest-priority event is the
one whose scheduled time is the earliest. Simulating one event
causes new events to be scheduled in the future.
- Sorting: _heap sort_ puts all the elements in a priority queue,
then removes them one at a time.
- Computational geometry: algorithms such as _convex hull_ use
priority queues.
- Graph algorithms: Dijkstra's algorithm for finding the shortest path
uses a priority queue.
We will be considering _mergeable_ priority queues, with one
additional operator:
- [ merge: priqueue -> priqueue -> priqueue ]
The classic data structure for priority queues is the "heap", a balanced
binary tree in which the the key at any node is _bigger_ than all the
keys in nodes below it. With heaps, [empty] is constant time,
[insert] and [delete_max] are logN time. But [merge] takes NlogN
time, as one must take all the elements out of one queue and
insert them into the other queue.
Another way to do priority queues is by _balanced binary search trees_
(such as red-black trees); again, [empty] is constant time,
[insert] and [delete_max] are logN time, and [merge] takes NlogN
time, as one must take all the elements out of one queue and
insert them into the other queue.
In the _Binom_ chapter we will examine an algorithm in which
[empty] is constant time, [insert], [delete_max], and [merge]
are logN time.
In _this_ chapter we will consider a much simpler (and slower)
implementation, using unsorted lists, in which:
- [empty] takes constant time
- [insert] takes constant time
- [delete_max] takes linear time
- [merge] takes linear time
*)
(* ################################################################# *)
(** * Module Signature *)
(** This is the "signature" of a correct implementation of priority queues
where the keys are natural numbers. Using [nat] for the key type is
a bit silly, since the comparison function Nat.ltb takes linear time
in the value of the numbers! But you have already seen in the
[Extract] chapter how to define these kinds of algorithms
on key types that have efficient comparisons, so in this chapter
(and the [Binom] chapter) we simply won't worry about the
time per comparison. *)
From VFA Require Import Perm.
Module Type PRIQUEUE.
Parameter priqueue: Type.
Definition key := nat.
Parameter empty: priqueue.
Parameter insert: key -> priqueue -> priqueue.
Parameter delete_max: priqueue -> option (key * priqueue).
Parameter merge: priqueue -> priqueue -> priqueue.
Parameter priq: priqueue -> Prop.
Parameter Abs: priqueue -> list key -> Prop.
Axiom can_relate: forall p, priq p -> exists al, Abs p al.
Axiom abs_perm: forall p al bl,
priq p -> Abs p al -> Abs p bl -> Permutation al bl.
Axiom empty_priq: priq empty.
Axiom empty_relate: Abs empty nil.
Axiom insert_priq: forall k p, priq p -> priq (insert k p).
Axiom insert_relate:
forall p al k, priq p -> Abs p al -> Abs (insert k p) (k::al).
Axiom delete_max_None_relate:
forall p, priq p -> (Abs p nil <-> delete_max p = None).
Axiom delete_max_Some_priq:
forall p q k, priq p -> delete_max p = Some(k,q) -> priq q.
Axiom delete_max_Some_relate:
forall (p q: priqueue) k (pl ql: list key), priq p ->
Abs p pl ->
delete_max p = Some (k,q) ->
Abs q ql ->
Permutation pl (k::ql) /\ Forall (ge k) ql.
Axiom merge_priq: forall p q, priq p -> priq q -> priq (merge p q).
Axiom merge_relate:
forall p q pl ql al,
priq p -> priq q ->
Abs p pl -> Abs q ql -> Abs (merge p q) al ->
Permutation al (pl++ql).
End PRIQUEUE.
(** Take some time to consider whether this is the right specification!
As always, if we get the specification wrong, then proofs of
"correctness" are not so useful.
*)
(* ################################################################# *)
(** * Implementation *)
Module List_Priqueue <: PRIQUEUE.
(** Now we are responsible for providing [Definitions] of all
those [Parameters], and proving [Theorems] for all those [Axioms],
so that the values in the [Module] match the types in
the [Module Type]. If we try to [End List_Priqueue] before
everything is provided, we'll get an error. Uncomment the next
line and try it!
*)
(* End List_Priqueue. *)
(* ================================================================= *)
(** ** Some Preliminaries *)
(** A copy of the [select] function from Selection.v, but
getting the max element instead of the min element: *)
Fixpoint select (i: nat) (l: list nat) : nat * list nat :=
match l with
| nil => (i, nil)
| h::t => if i >=? h
then let (j, l') := select i t in (j, h::l')
else let (j,l') := select h t in (j, i::l')
end.
(** **** Exercise: 3 stars (select_perm_and_friends) *)
Lemma select_perm: forall i l,
let (j,r) := select i l in
Permutation (i::l) (j::r).
Proof. (* Copy your proof from Selection.v, and change one character. *)
intros i l; revert i.
induction l; intros; simpl in *.
(* FILL IN HERE *) Admitted.
Lemma select_biggest_aux:
forall i al j bl,
Forall (fun x => j >= x) bl ->
select i al = (j,bl) ->
j >= i.
Proof. (* Copy your proof of [select_smallest_aux] from Selection.v, and edit. *)
(* FILL IN HERE *) Admitted.
Theorem select_biggest:
forall i al j bl, select i al = (j,bl) ->
Forall (fun x => j >= x) bl.
Proof. (* Copy your proof of [select_smallest] from Selection.v, and edit. *)
intros i al; revert i; induction al; intros; simpl in *.
(* FILL IN HERE *) admit.
bdestruct (i >=? a).
*
destruct (select i al) eqn:?H.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ================================================================= *)
(** ** The Program *)
Definition key := nat.
Definition priqueue := list key.
Definition empty : priqueue := nil.
Definition insert (k: key)(p: priqueue) := k::p.
Definition delete_max (p: priqueue) :=
match p with
| i::p' => Some (select i p')
| nil => None
end.
Definition merge (p q: priqueue) : priqueue := p++q.
(* ################################################################# *)
(** * Predicates on Priority Queues *)
(* ================================================================= *)
(** ** The Representation Invariant *)
(** In this implementation of priority queues as unsorted lists,
the representation invariant is trivial. *)
Definition priq (p: priqueue) := True.
(** The abstraction relation is trivial too. *)
Inductive Abs': priqueue -> list key -> Prop :=
Abs_intro: forall p, Abs' p p.
Definition Abs := Abs'.
(* ================================================================= *)
(** ** Sanity Checks on the Abstraction Relation *)
Lemma can_relate : forall p, priq p -> exists al, Abs p al.
Proof.
intros. exists p; constructor.
Qed.
(** When the [Abs] relation says, "priority queue [p] contains elements [al]",
it is free to report the elements in any order. It could even relate [p]
to two different lists [al] and [bl], as long as one is a permutation of
the other. *)
Lemma abs_perm: forall p al bl,
priq p -> Abs p al -> Abs p bl -> Permutation al bl.
Proof.
intros.
inv H0. inv H1. apply Permutation_refl.
Qed.
(* ================================================================= *)
(** ** Characterizations of the Operations on Queues *)
Lemma empty_priq: priq empty.
Proof. constructor. Qed.
Lemma empty_relate: Abs empty nil.
Proof. constructor. Qed.
Lemma insert_priq: forall k p, priq p -> priq (insert k p).
Proof. intros; constructor. Qed.
Lemma insert_relate:
forall p al k, priq p -> Abs p al -> Abs (insert k p) (k::al).
Proof. intros. unfold insert. inv H0. constructor. Qed.
Lemma delete_max_Some_priq:
forall p q k, priq p -> delete_max p = Some(k,q) -> priq q.
Proof. constructor. Qed.
(** **** Exercise: 2 stars (simple_priq_proofs) *)
Lemma delete_max_None_relate:
forall p, priq p ->
(Abs p nil <-> delete_max p = None).
Proof.
(* FILL IN HERE *) Admitted.
Lemma delete_max_Some_relate:
forall (p q: priqueue) k (pl ql: list key), priq p ->
Abs p pl ->
delete_max p = Some (k,q) ->
Abs q ql ->
Permutation pl (k::ql) /\ Forall (ge k) ql.
Proof.
(* FILL IN HERE *) Admitted.
Lemma merge_priq:
forall p q, priq p -> priq q -> priq (merge p q).
Proof. intros. constructor. Qed.
Lemma merge_relate:
forall p q pl ql al,
priq p -> priq q ->
Abs p pl -> Abs q ql -> Abs (merge p q) al ->
Permutation al (pl++ql).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End List_Priqueue.
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_prp_rx_fifo # (
parameter P_FIFO_DATA_WIDTH = 128,
parameter P_FIFO_DEPTH_WIDTH = 5
)
(
input clk,
input rst_n,
input wr_en,
input [P_FIFO_DEPTH_WIDTH-1:0] wr_addr,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
input [P_FIFO_DEPTH_WIDTH:0] rear_full_addr,
input [P_FIFO_DEPTH_WIDTH:0] rear_addr,
input [5:4] alloc_len,
output full_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
input free_en,
input [5:4] free_len,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 0; //128 bits
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_empty_addr;
wire [P_FIFO_DEPTH_WIDTH:0] w_valid_space;
wire [P_FIFO_DEPTH_WIDTH:0] w_invalid_space;
wire [P_FIFO_DEPTH_WIDTH:0] w_invalid_front_addr;
assign w_invalid_front_addr = {~r_front_addr[P_FIFO_DEPTH_WIDTH], r_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign w_invalid_space = w_invalid_front_addr - rear_full_addr;
assign full_n = (w_invalid_space >= alloc_len);
assign w_valid_space = rear_addr - r_front_empty_addr;
assign empty_n = (w_valid_space >= free_len);
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
r_front_empty_addr <= 0;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
if (free_en == 1)
r_front_empty_addr <= r_front_empty_addr + free_len;
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "36Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH/2;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH/2;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 8;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = wr_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], wr_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb36sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb36sdp_1(
.DO (rd_data[P_FIFO_DATA_WIDTH-1:LP_READ_WIDTH]),
.DI (wr_data[P_FIFO_DATA_WIDTH-1:LP_WRITE_WIDTH]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 10; const int INF = 2147000000; int n, k; int a[maxn][maxn]; int b[maxn], vis[maxn]; int ans = INF; int make(int num) { int res = 0; for (int i = 1; i <= k; i++) { int c = b[i]; res = res * 10 + a[num][c]; } return res; } void solve() { int Max = -INF, Min = INF; for (int i = 1; i <= n; i++) { int res = make(i); Max = max(Max, res); Min = min(Min, res); } ans = min(ans, Max - Min); } void dfs(int cur) { if (cur == k + 1) { solve(); return; } for (int i = 1; i <= k; i++) { if (!vis[i]) { vis[i] = 1; b[cur] = i; dfs(cur + 1); vis[i] = 0; } } } int main() { scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) { for (int j = 1; j <= k; j++) { char c; scanf( %c , &c); a[i][j] = c - 0 ; } } memset(vis, 0, sizeof(vis)); dfs(1); printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long n; while (scanf( %I64d , &n) != EOF) { long long x, y, l, h, mid; l = 0, h = 1e18 + 7; while (l < h - 1) { mid = (l + h) >> 1; if (n / (3 * mid) >= mid + 1) l = mid; else h = mid; } x = 2 * l; y = 0; long long ret = n - 3 * l * (l + 1); l++; if (ret >= 1) { x++; y += 2; if (ret <= l) { x -= ret - 1; y += 2 * (ret - 1); } else { x -= l - 1; y += 2 * (l - 1); if (ret <= 2 * l) { x -= 2 * (ret - l); } else { x -= 2 * l; if (ret <= 3 * l) { x -= ret - 2 * l; y -= 2 * (ret - 2 * l); } else { x -= l; y -= 2 * l; if (ret <= 4 * l) { x += ret - 3 * l; y -= 2 * (ret - 3 * l); } else { x += l; y -= 2 * l; if (ret <= 5 * l) { x += 2 * (ret - 4 * l); } else { x += 2 * l; x += ret - 5 * l; y += 2 * (ret - 5 * l); } } } } } } printf( %I64d %I64d n , x, y); } return 0; } |
Require Import Coq.Program.Basics.
Require Import MathClasses.interfaces.canonical_names.
Require Import TypeclassHierarchy.Util.FunctionSetoid.
(* math-classes uses (=) to denote equivalence, but we will use it for equality *)
Infix "=" := eq : type_scope.
Notation "(=)" := eq (only parsing) : mc_scope.
Notation "( x =)" := (eq x) (only parsing) : mc_scope.
Notation "(= x )" := (λ y, eq y x) (only parsing) : mc_scope.
(* Notation "(≠)" := (λ x y, ¬x = y) (only parsing) : mc_scope. *)
(* Notation "x ≠ y":= (¬x = y): type_scope. *)
(* Notation "( x ≠)" := (λ y, x ≠ y) (only parsing) : mc_scope. *)
(* Notation "(≠ x )" := (λ y, y ≠ x) (only parsing) : mc_scope. *)
(**
A functor contains data in such a way that a function can be applied uniformly
across the contained objects.
The functor follows three (classical) laws:
- fmap id = id
- fmap (g ∘ h) = (fmap g) ∘ (fmap h)
We additionally require that fmap is proper with respect to the equivalence
relation on functions, i.e. if f and g are extensionally equal, fmap f and
fmap g are as well.
A lot of the notation (e.g. setoid/extensional equality) is desugared here,
because Coq has trouble inferring the types.
We use Type rather than Set, as Functors must live in Set+1, and we want to be able to compose Functors.
*)
Class Functor (F : Type -> Type) : Type :=
{ fmap : forall {X Y : Type}, (X -> Y) -> F X -> F Y
; fmap_proper :
forall {A B : Type}, Proper ((@extensional_equality A B) ==>
(@extensional_equality (F A) (F B))) (@fmap A B)
; fmap_identity :
forall {A : Type}, @extensional_equality (F A) (F A) (@fmap A A id) id
; fmap_composition :
forall {A B C: Type} (h : A -> B) (g : B -> C),
@extensional_equality (F A) (F C) (@fmap A C (g ∘ h)) (@fmap B C g ∘ @fmap A B h)
}.
Arguments fmap {F} {Functor} {X} {Y} _ _.
(**
An apply is a halfway point between functor and applicative/bind. It's not very
useful in and of itself, but exists to unify the notation between binds and
applicatives.
In addition to the functor laws, an apply follows one more:
- ap g (ap f a) = ap (ap (fmap (∘) g) f) a
*)
Class Apply (F : Type -> Type) : Type :=
{ apply_functor : Functor F
; ap : forall {A B : Type}, F (A -> B) -> F A -> F B
; apply_composition :
forall {A B C : Type} (f : F (A -> B)) (g : F (B -> C)) (a : F A),
@ap B C g (@ap A B f a) = @ap A C (ap (fmap (∘) g) f) a
}.
(**
An applicative is a functor that also allows for both applying functions inside
the functor to arguments inside the functor, and embedding arbitrary objects in
the functor.
In addition to the apply laws, an applicative follows three others:
- ap (pure id) v = v
- ap (pure f) (pure x) = pure (f x)
- ap u (pure y) = ap (pure (fun f => f y)) u
- ap u (ap v w) = ap (pure (∘)) (ap u (ap v w))
As always, lot of the notation (e.g. setoid/extensional equality) is desugared
to reduce the need for (slow and somewhat unreliable) type inference.
In particular, we often have the following let clause:
"app := @ap F applicative_apply" which specializes the "ap" method to the
current functor. If this is confusing, just think of "app" as "ap".
*)
Class Applicative (F : Type -> Type) : Type :=
{ applicative_apply : Apply F
; pure : forall {A : Type}, A -> F A
(* ; pure_proper : *)
(* forall {A B : Type}, Proper (@extensional_equality A (F A)) (@pure A) *)
; ap_identity :
forall {A : Type} (a : F A),
@ap F applicative_apply A A (@pure (A -> A) id) a = a
; ap_homomorphism :
forall {A B : Type} (f : A -> B) (a : A),
let app := @ap F applicative_apply A B
in @app (@pure (A -> B) f) (@pure A a) = @pure B (f a)
; ap_interchange :
forall {A B : Type} (f : F (A -> B)) (a : A),
let app := @ap F applicative_apply
in @app A B f (pure a) = @app (A -> B) B (@pure ((A -> B) -> B) (fun g => g a)) f
; ap_composition :
forall {A B C : Type} (f : F (A -> B)) (g : F (B -> C)) (a : F A),
let app := @ap F applicative_apply
(* TODO: fill in more implicit args. I don't understand the types :( *)
in app B C g (app A B f a) = app A C (ap (ap (pure (∘)) g) f) a
}.
(**
A bind is an apply with an additional operation that takes the output of
one computation and feeds it into the next, composing the two in a chain.
In addition to the apply laws, binds must follow one other:
- bind (bind x f) g = bind x (fun y => bind (f y) g)
*)
Class Bind (F : Type -> Type) : Type :=
{ bind_apply : Apply F
; bind : forall {A B : Type}, F A -> (A -> F B) -> F B
; bind_associative :
forall {A B C : Type} (x : F A) (f : A -> F B) (g : B -> F C),
@bind B C (@bind A B x f) g = @bind A C x (fun y => @bind B C (f y) g)
}.
(**
A monad is a lot of things, but really just an applicative and a bind together.
It supports chaining of functions, and embedding of objects into the type
constructor.
In addition to the laws provided by apply and bind, it has identities:
- bind (pure x) f = f x
- bind x pure = x
*)
Class Monad (M : Type -> Type) : Type :=
{ monad_applicative : Applicative M
; monad_bind : Bind M
; monad_id_left : forall {A B : Type} (f : A -> M B) (x : A), bind (pure x) f = f x
; monad_id_right : forall {A B : Type} (f : A -> M B) (x : M A), bind x pure = x
}. |
#include <bits/stdc++.h> #pragma warning(disable : 4996) #pragma comment(linker, /STACK:336777216 ) using namespace std; int IT_MAX = 1 << 17; const long long MOD = 1000000007; const int INF = 0x1f3f3f3f; const long long LL_INF = 1034567890123456789ll; const double PI = acos(-1); const double ERR = 1E-11; multiset<int> Sx; int in[100050]; int main() { int N, K, i, j; scanf( %d %d , &N, &K); for (i = 1; i <= N; i++) scanf( %d , &in[i]); int ans = -1; vector<int> Va; for (i = 1, j = 1; i <= N; i++) { while (j <= N) { if (Sx.empty()) { Sx.insert(in[j++]); continue; } auto it1 = Sx.begin(); auto it2 = Sx.end(); it2--; if (abs(in[j] - *it1) > K || abs(in[j] - *it2) > K) break; Sx.insert(in[j++]); } if (ans < j - i) { ans = j - i; Va.clear(); } if (ans == j - i) Va.push_back(i); Sx.erase(Sx.lower_bound(in[i])); } printf( %d %d n , ans, (int)Va.size()); for (auto it : Va) printf( %d %d n , it, it + ans - 1); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m; char s[1100][1100]; bool a[1100][1010]; bool canDraw(int x, int y, int level) { int i = level; { if (x + i < 0 || x + i >= n) return false; if (y + i < 0 || y + i >= m) return false; if (s[x + i][y] == . ) return false; if (s[x][y + i] == . ) return false; } i = -level; { if (x + i < 0 || x + i >= n) return false; if (y + i < 0 || y + i >= m) return false; if (s[x + i][y] == . ) return false; if (s[x][y + i] == . ) return false; } return true; } void Draw(int x, int y, int level) { for (int i = -level; i <= level; i++) { a[x][y + i] = true; a[x + i][y] = true; } } int ans; int xx[11000000]; int yy[11000000]; int ll[10100000]; int main(int argc, char const *argv[]) { while (cin >> n >> m) { ans = 0; for (int i = 0; i < n; i++) { scanf( %s , s[i]); } for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { int level = 0; for (level = 0; level <= max(n, m); level++) { if (!canDraw(i, j, level)) break; } if (level > 1) { Draw(i, j, level - 1); xx[ans] = i; yy[ans] = j; ll[ans] = level - 1; ans++; } } for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { if (s[i][j] == * && a[i][j] == false) { ans = -1; } } if (ans == -1) { printf( -1 n ); } else { printf( %d n , ans); for (int i = 0; i < ans; i++) printf( %d %d %d n , xx[i] + 1, yy[i] + 1, ll[i]); } } } |
#include <bits/stdc++.h> using namespace std; vector<int> getPrimes(int n) { vector<bool> sieve(n + 1, true); sieve[0] = sieve[1] = false; for (int i = 2; i * i <= n; i++) if (sieve[i]) for (int j = i * i; j <= n; j += i) sieve[j] = false; vector<int> primes; for (int i = 2; i <= n; i++) if (sieve[i]) primes.push_back(i); return primes; } void storePrimes(int n, unordered_map<int, int> &m, vector<int> &primes) { for (int p : primes) { if (p * p > n) break; while (n % p == 0) { m[p]++; n /= p; } if (n == 1) break; } if (n > 1) m[n]++; } void removePrimes(int n, unordered_map<int, int> &m, vector<int> &primes) { for (int p : primes) { if (p * p > n) break; while (n % p == 0) { m[p]--; n /= p; } if (n == 1) break; } if (n > 1) m[n]--; } bool isAtleast(unordered_map<int, int> &m1, unordered_map<int, int> &m2) { for (auto it = m2.begin(); it != m2.end(); it++) { int num = it->first, freq = it->second; if (m1.find(num) == m1.end() or m1[num] < freq) return false; } return true; } void printMap(unordered_map<int, int> &m) { for (auto it = m.begin(); it != m.end(); it++) cout << it->first << : << it->second << n ; } long long int solve(int arr[], int n, int k) { vector<int> primes = getPrimes(1000003); unordered_map<int, int> mapK, currMap; storePrimes(k, mapK, primes); int i = 0, j = 0; long long int count = 0; while (j < n) { storePrimes(arr[j], currMap, primes); if (isAtleast(currMap, mapK)) { while (i <= j and isAtleast(currMap, mapK)) { count += (n - j); removePrimes(arr[i], currMap, primes); i++; } } j++; } return count; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, k; cin >> n >> k; int arr[n]; for (int i = 0; i < n; i++) cin >> arr[i]; long long int ans = solve(arr, n, k); cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; struct data { int x, y; } v[300005]; inline bool cmp(data d1, data d2) { if (d1.x != d2.x) return d1.x < d2.x; return d1.y < d2.y; } inline bool cmp2(data d1, data d2) { return d1.y < d2.y; } int n; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &v[i].x); v[i].y = i; } sort(v + 1, v + n + 1, cmp); int minv = 0; for (int i = 1; i <= n; i++) { if (minv < v[i].x) { minv = v[i].x + 1; } else { v[i].x = minv; minv++; } } sort(v + 1, v + n + 1, cmp2); for (int i = 1; i <= n; i++) printf( %d , v[i].x); return 0; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Data TLB ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Instantiation of DTLB. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_dmmu_tlb.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.7 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.6 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.4.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.4 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.3 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.2 2002/01/28 01:16:00 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
//
// Data TLB
//
module or1200_dmmu_tlb(
// Rst and clk
clk, rst,
// I/F for translation
tlb_en, vaddr, hit, ppn, uwe, ure, swe, sre, ci,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// SPR access
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// I/F for translation
//
input tlb_en;
input [aw-1:0] vaddr;
output hit;
output [31:`OR1200_DMMU_PS] ppn;
output uwe;
output ure;
output swe;
output sre;
output ci;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// SPR access
//
input spr_cs;
input spr_write;
input [31:0] spr_addr;
input [31:0] spr_dat_i;
output [31:0] spr_dat_o;
//
// Internal wires and regs
//
wire [`OR1200_DTLB_TAG] vpn;
wire v;
wire [`OR1200_DTLB_INDXW-1:0] tlb_index;
wire tlb_mr_en;
wire tlb_mr_we;
wire [`OR1200_DTLBMRW-1:0] tlb_mr_ram_in;
wire [`OR1200_DTLBMRW-1:0] tlb_mr_ram_out;
wire tlb_tr_en;
wire tlb_tr_we;
wire [`OR1200_DTLBTRW-1:0] tlb_tr_ram_in;
wire [`OR1200_DTLBTRW-1:0] tlb_tr_ram_out;
`ifdef OR1200_BIST
//
// RAM BIST
//
wire mbist_mr_so;
wire mbist_tr_so;
wire mbist_mr_si = mbist_si_i;
wire mbist_tr_si = mbist_mr_so;
assign mbist_so_o = mbist_tr_so;
`endif
//
// Implemented bits inside match and translate registers
//
// dtlbwYmrX: vpn 31-19 v 0
// dtlbwYtrX: ppn 31-13 swe 9 sre 8 uwe 7 ure 6
//
// dtlb memory width:
// 19 bits for ppn
// 13 bits for vpn
// 1 bit for valid
// 4 bits for protection
// 1 bit for cache inhibit
//
// Enable for Match registers
//
assign tlb_mr_en = tlb_en | (spr_cs & !spr_addr[`OR1200_DTLB_TM_ADDR]);
//
// Write enable for Match registers
//
assign tlb_mr_we = spr_cs & spr_write & !spr_addr[`OR1200_DTLB_TM_ADDR];
//
// Enable for Translate registers
//
assign tlb_tr_en = tlb_en | (spr_cs & spr_addr[`OR1200_DTLB_TM_ADDR]);
//
// Write enable for Translate registers
//
assign tlb_tr_we = spr_cs & spr_write & spr_addr[`OR1200_DTLB_TM_ADDR];
//
// Output to SPRS unit
//
assign spr_dat_o = (spr_cs & !spr_write & !spr_addr[`OR1200_DTLB_TM_ADDR]) ?
{vpn, tlb_index & {`OR1200_DTLB_INDXW{v}}, {`OR1200_DTLB_TAGW-7{1'b0}}, 1'b0, 5'b00000, v} :
(spr_cs & !spr_write & spr_addr[`OR1200_DTLB_TM_ADDR]) ?
{ppn, {`OR1200_DMMU_PS-10{1'b0}}, swe, sre, uwe, ure, {4{1'b0}}, ci, 1'b0} :
32'h00000000;
//
// Assign outputs from Match registers
//
assign {vpn, v} = tlb_mr_ram_out;
//
// Assign to Match registers inputs
//
assign tlb_mr_ram_in = {spr_dat_i[`OR1200_DTLB_TAG], spr_dat_i[`OR1200_DTLBMR_V_BITS]};
//
// Assign outputs from Translate registers
//
assign {ppn, swe, sre, uwe, ure, ci} = tlb_tr_ram_out;
//
// Assign to Translate registers inputs
//
assign tlb_tr_ram_in = {spr_dat_i[31:`OR1200_DMMU_PS],
spr_dat_i[`OR1200_DTLBTR_SWE_BITS],
spr_dat_i[`OR1200_DTLBTR_SRE_BITS],
spr_dat_i[`OR1200_DTLBTR_UWE_BITS],
spr_dat_i[`OR1200_DTLBTR_URE_BITS],
spr_dat_i[`OR1200_DTLBTR_CI_BITS]};
//
// Generate hit
//
assign hit = (vpn == vaddr[`OR1200_DTLB_TAG]) & v;
//
// TLB index is normally vaddr[18:13]. If it is SPR access then index is
// spr_addr[5:0].
//
assign tlb_index = spr_cs ? spr_addr[`OR1200_DTLB_INDXW-1:0] : vaddr[`OR1200_DTLB_INDX];
//
// Instantiation of DTLB Match Registers
//
or1200_spram_64x14 dtlb_mr_ram(
.clk(clk),
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_mr_si),
.mbist_so_o(mbist_mr_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.ce(tlb_mr_en),
.we(tlb_mr_we),
.oe(1'b1),
.addr(tlb_index),
.di(tlb_mr_ram_in),
.doq(tlb_mr_ram_out)
);
//
// Instantiation of DTLB Translate Registers
//
or1200_spram_64x24 dtlb_tr_ram(
.clk(clk),
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_tr_si),
.mbist_so_o(mbist_tr_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.ce(tlb_tr_en),
.we(tlb_tr_we),
.oe(1'b1),
.addr(tlb_index),
.di(tlb_tr_ram_in),
.doq(tlb_tr_ram_out)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> void __p(T a) { cout << a; } template <typename T, typename F> void __p(pair<T, F> a) { cout << { ; __p(a.first); cout << , ; __p(a.second); cout << } n ; } template <typename T> void __p(std::vector<T> a) { cout << { ; for (auto it = a.begin(); it < a.end(); it++) __p(*it), cout << ,} n [it + 1 == a.end()]; } template <typename T, typename... Arg> void __p(T a1, Arg... a) { __p(a1); __p(a...); } template <typename Arg1> void __f(const char *name, Arg1 &&arg1) { cout << name << : ; __p(arg1); cout << n ; } template <typename Arg1, typename... Args> void __f(const char *names, Arg1 &&arg1, Args &&...args) { int bracket = 0, i = 0; for (;; i++) if (names[i] == , && bracket == 0) break; else if (names[i] == ( ) bracket++; else if (names[i] == ) ) bracket--; const char *comma = names + i; cout.write(names, comma - names) << : ; __p(arg1); cout << | ; __f(comma + 1, args...); } void setIO(string s = ) { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin.exceptions(cin.failbit); if (((int)(s).size())) { freopen((s + .in ).c_str(), r , stdin); freopen((s + .out ).c_str(), w , stdout); } } const int dx[] = {1, 0, 0, -1}; const int dy[] = {0, -1, 1, 0}; const char C[] = { D , L , R , U }; signed main() { setIO(); int n, m, K; cin >> n >> m >> K; if (K & 1) return cout << IMPOSSIBLE , 0; char a[n][m]; int dis[n][m]; int si = -1, sj = -1; for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { cin >> a[i][j]; dis[i][j] = 1e9; if (a[i][j] == X ) { si = i, sj = j; dis[si][sj] = 0; } } } priority_queue<pair<int, array<int, 2> > > q; q.push({0, {si, sj}}); while (((int)(q).size())) { int res = -q.top().first, i = q.top().second[0], j = q.top().second[1]; q.pop(); if (res != dis[i][j]) continue; for (int k = 0; k < 4; ++k) { int ni = i + dx[k], nj = j + dy[k]; if (ni >= 0 && ni < n && nj >= 0 && nj < m && a[ni][nj] != * ) { if (dis[ni][nj] > dis[i][j] + 1) { dis[ni][nj] = dis[i][j] + 1; q.push({-dis[ni][nj], {ni, nj}}); } } } } int i = si, j = sj; string ans; for (int x = K - 1; x >= 0; --x) { for (int k = 0; k < 4; ++k) { int ni = i + dx[k], nj = j + dy[k]; if (ni >= 0 && ni < n && nj >= 0 && nj < m && a[ni][nj] != * ) { if (dis[ni][nj] <= x) { i = ni, j = nj; ans.push_back(C[k]); break; } } } } if (((int)(ans).size()) < K) { return cout << IMPOSSIBLE , 0; } cout << ans; } |
#include <bits/stdc++.h> using namespace std; char ans[300][300]; string s; int cnt[300]; int bal[300]; int n, m; void f(int l, int r, int ll, int rr) { if (l + 1 == r) { for (int i = 0; i < n / 2 - bal[r]; ++i) { ans[n / 2 + i][ll] = | ; ans[n / 2 - i][ll] = | ; ans[n / 2 + i][rr] = | ; ans[n / 2 - i][rr] = | ; } ans[bal[l] - 1][ll] = + ; ans[n - bal[l]][ll] = + ; ans[bal[l] - 1][rr] = + ; ans[n - bal[l]][rr] = + ; ans[bal[l] - 1][ll + 1] = - ; ans[n - bal[l]][ll + 1] = - ; ans[bal[l] - 1][rr - 1] = - ; ans[n - bal[l]][rr - 1] = - ; if (ll + 4 != rr) { throw 1; } return; } int q = l; int bl = 0; for (q = l; q <= r; ++q) { if (s[q] == [ ) { ++bl; } else { --bl; } if (bl == 0) { break; } } if (q == r) { for (int i = 0; i < n / 2 - bal[r]; ++i) { ans[n / 2 + i][ll] = | ; ans[n / 2 - i][ll] = | ; ans[n / 2 + i][rr] = | ; ans[n / 2 - i][rr] = | ; } ans[bal[l] - 1][ll] = + ; ans[n - bal[l]][ll] = + ; ans[bal[l] - 1][rr] = + ; ans[n - bal[l]][rr] = + ; ans[bal[l] - 1][ll + 1] = - ; ans[n - bal[l]][ll + 1] = - ; ans[bal[l] - 1][rr - 1] = - ; ans[n - bal[l]][rr - 1] = - ; f(l + 1, r - 1, ll + 1, rr - 1); return; } int qq = ll + q - l + (cnt[q] - cnt[l]) * 3; f(l, q, ll, qq); f(q + 1, r, qq + 1, rr); } int main() { memset(ans, , sizeof(ans)); int qwe; cin >> qwe; cin >> s; int bl = 0; int mx = 0; for (int i = 0; i < s.size(); ++i) { if (s[i] == [ ) { ++bl; mx = max(mx, bl); } else { if (s[i - 1] == [ ) { cnt[i] = 1; } --bl; } bal[i] = bl; cnt[i] += i > 0 ? cnt[i - 1] : 0; } n = mx * 2 + 1; m = s.size() + cnt[s.size() - 1] * 3; f(0, s.size() - 1, 0, m - 1); for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { cout << ans[i][j]; } cout << endl; } } |
/*
Copyright (c) 2014-2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream UART
*/
module uart_tx #
(
parameter DATA_WIDTH = 8
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire input_axis_tvalid,
output wire input_axis_tready,
/*
* UART interface
*/
output wire txd,
/*
* Status
*/
output wire busy,
/*
* Configuration
*/
input wire [15:0] prescale
);
reg input_axis_tready_reg = 0;
reg txd_reg = 1;
reg busy_reg = 0;
reg [DATA_WIDTH:0] data_reg = 0;
reg [18:0] prescale_reg = 0;
reg [3:0] bit_cnt = 0;
assign input_axis_tready = input_axis_tready_reg;
assign txd = txd_reg;
assign busy = busy_reg;
always @(posedge clk) begin
if (rst) begin
input_axis_tready_reg <= 0;
txd_reg <= 1;
prescale_reg <= 0;
bit_cnt <= 0;
busy_reg <= 0;
end else begin
if (prescale_reg > 0) begin
input_axis_tready_reg <= 0;
prescale_reg <= prescale_reg - 1;
end else if (bit_cnt == 0) begin
input_axis_tready_reg <= 1;
busy_reg <= 0;
if (input_axis_tvalid) begin
input_axis_tready_reg <= ~input_axis_tready_reg;
prescale_reg <= (prescale << 3)-1;
bit_cnt <= DATA_WIDTH+1;
data_reg <= {1'b1, input_axis_tdata};
txd_reg <= 0;
busy_reg <= 1;
end
end else begin
if (bit_cnt > 1) begin
bit_cnt <= bit_cnt - 1;
prescale_reg <= (prescale << 3)-1;
{data_reg, txd_reg} <= {1'b0, data_reg};
end else if (bit_cnt == 1) begin
bit_cnt <= bit_cnt - 1;
prescale_reg <= (prescale << 3);
txd_reg <= 1;
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, j, k, a, b; pair<int, int> c[300005]; map<pair<long long, long long>, long long> m; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; for (int i = 0; i < n; i++) { cin >> a >> b; c[i] = make_pair(a, b); m[c[i]] = i; if (a > b) { k++; } } sort(c, c + n); j = n - k; if (k > j) { cout << k << n ; for (int i = 0; i < n; i++) { if (c[i].first > c[i].second) { cout << m[c[i]] + 1 << ; } } } else { cout << j << n ; for (int i = n - 1; i >= 0; i--) { if (c[i].first < c[i].second) { cout << m[c[i]] + 1 << ; } } } cout << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; long long read() { long long x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = (x << 3) + (x << 1) + (ch ^ 48); ch = getchar(); } return x * f; } long long n, w, b, x, c[1005], cost[1005], f[1005][10005], C, a[10005], tot; long long cmp(long long x, long long y) { return x > y; } signed main() { n = read(); w = read(); b = read(); x = read(); for (long long i = 1; i <= n; i++) c[i] = read(), C += c[i]; for (long long i = 1; i <= n; i++) cost[i] = read(); memset(f, -0x3f, sizeof(f)); f[0][0] = w; for (long long i = 1; i <= n; i++) { if (i != 1) for (long long j = 0; j <= C; j++) f[i][j] = min(f[i - 1][j] + x, w + b * j); else for (long long j = 0; j <= C; j++) f[i][j] = f[i - 1][j]; tot = 0; for (long long k = 1; k <= c[i]; k *= 2) { a[++tot] = k; c[i] -= k; } if (c[i]) a[++tot] = c[i]; sort(a + 1, a + tot + 1, cmp); for (long long k = 1; k <= tot; k++) { for (long long j = C; j >= a[k]; j--) { if (f[i][j - a[k]] >= cost[i] * a[k]) f[i][j] = max(f[i][j], f[i][j - a[k]] - cost[i] * a[k]); } } } long long ans = 0; for (long long i = C; i >= 0; i--) { if (f[n][i] >= 0) { ans = i; break; } } cout << ans << endl; return 0; } |
`timescale 1ns/10ps
module RotarySim;
reg clock;
reg reset;
reg [11:0] inst;
reg inst_en;
reg [1:0] rotary;
wire rotary_left_status;
wire rotary_right_status;
initial begin
#0 $dumpfile(`VCDFILE);
#0 $dumpvars;
#10000 $finish;
end
initial begin
#0 clock = 1;
forever #2 clock = ~clock;
end
initial begin
#0 reset = 0;
#1 reset = 1;
#4 reset = 0;
end
initial begin
#0.1 inst_en = 0;
// Test each instruction.
#8 inst = {`Rotary_RDLS,8'bxxxxxxxx};
inst_en = 1;
rotary = 2'b00;
#4 inst = {`Rotary_NOP,8'bxxxxxxxx};
inst_en = 1;
#5 rotary = 2'b01;
#30 rotary = 2'b11;
#30 rotary = 2'b00;
#7 inst = {`Rotary_RDLS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Rotary_NOP,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Rotary_RDLS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Rotary_NOP,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Rotary_RDRS,8'bxxxxxxxx};
inst_en = 1;
rotary = 2'b00;
#4 inst = {`Rotary_NOP,8'bxxxxxxxx};
inst_en = 1;
#5 rotary = 2'b10;
#30 rotary = 2'b11;
#30 rotary = 2'b00;
#7 inst = {`Rotary_RDRS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Rotary_NOP,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Rotary_RDRS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Rotary_NOP,8'bxxxxxxxx};
inst_en = 1;
// Test disabled instruction.
#4 rotary = 2'b01;
#30 rotary = 2'b11;
#30 rotary = 2'b00;
#8 inst = {`Rotary_RDLS,8'bxxxxxxxx};
inst_en = 0;
#4 inst = {`Rotary_RDLS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Rotary_RDLS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Rotary_NOP,8'bxxxxxxxx};
inst_en = 1;
// Test bad instruction.
#4 inst = {8'hF,8'hAA};
inst_en = 1;
#4 inst = {`Rotary_RDRS,8'bxxxxxxxx};
inst_en = 1;
#4 reset = 1;
#8 reset = 0;
#4 inst = {`Rotary_RDRS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Rotary_NOP,8'bxxxxxxxx};
inst_en = 1;
// Test multiple left turns before one read.
#4 rotary = 2'b01;
#30 rotary = 2'b11;
#30 rotary = 2'b00;
#8 rotary = 2'b01;
#30 rotary = 2'b11;
#30 rotary = 2'b00;
#8 rotary = 2'b01;
#30 rotary = 2'b11;
#30 rotary = 2'b00;
#8 inst = {`Rotary_RDLS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Rotary_RDLS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Rotary_NOP,8'bxxxxxxxx};
inst_en = 1;
// Test multiple right turns before one read.
#4 rotary = 2'b10;
#30 rotary = 2'b11;
#30 rotary = 2'b00;
#8 rotary = 2'b10;
#30 rotary = 2'b11;
#30 rotary = 2'b00;
#8 rotary = 2'b10;
#30 rotary = 2'b11;
#30 rotary = 2'b00;
#8 inst = {`Rotary_RDRS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Rotary_RDRS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Rotary_NOP,8'bxxxxxxxx};
inst_en = 1;
// Test multiple left turns before one read. Some of the turns are caused by bounces.
#4 rotary = 2'b01;
#18 rotary = 2'b00;
#2 rotary = 2'b01;
#18 rotary = 2'b00;
#2 rotary = 2'b01;
#30 rotary = 2'b11;
#30 rotary = 2'b00;
#8 inst = {`Rotary_RDLS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Rotary_RDLS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Rotary_NOP,8'bxxxxxxxx};
inst_en = 1;
// Test multiple right turns before one read. Some of the turns are caused by bounces.
#4 rotary = 2'b10;
#18 rotary = 2'b00;
#2 rotary = 2'b10;
#18 rotary = 2'b00;
#2 rotary = 2'b10;
#30 rotary = 2'b11;
#30 rotary = 2'b00;
#8 inst = {`Rotary_RDRS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Rotary_RDRS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Rotary_NOP,8'bxxxxxxxx};
inst_en = 1;
end
Rotary
rotary (.clock(clock),
.reset(reset),
.inst(inst),
.inst_en(inst_en),
.rotary(rotary),
.rotary_left_status(rotary_left_status),
.rotary_right_status(rotary_right_status));
endmodule // RotarySim
|
#include <bits/stdc++.h> using namespace std; void Input_Preparing() {} void Processing() { int a, b; cin >> a >> b; cout << min(a, b) << << (max(a, b) - min(a, b)) / 2; } int main() { std::cin.tie(0)->sync_with_stdio(0); ; Processing(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O22A_PP_SYMBOL_V
`define SKY130_FD_SC_MS__O22A_PP_SYMBOL_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o22a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O22A_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9 + 23; const int MOD = 1e9 + 7; const int N = 1000 + 10; int brow[N], bcol[N]; int main() { ios_base::sync_with_stdio(0); int n, m; cin >> n >> m; for (int i = 0; i < (m); ++i) { int x, y; cin >> x >> y; brow[x] = true; bcol[y] = true; } int ans = 0; for (int i = (2); i < (n); ++i) { if (i == n - i + 1) ans += !brow[i] || !bcol[i]; else { ans += !brow[i]; ans += !bcol[i]; } } cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T, typename U> inline void smin(T &a, U b) { if (a > b) a = b; } template <typename T, typename U> inline void smax(T &a, U b) { if (a < b) a = b; } template <class T> inline void gn(T &first) { char c, sg = 0; while (c = getchar(), (c > 9 || c < 0 ) && c != - ) ; for ((c == - ? sg = 1, c = getchar() : 0), first = 0; c >= 0 && c <= 9 ; c = getchar()) first = (first << 1) + (first << 3) + c - 0 ; if (sg) first = -first; } template <class T> inline void print(T first) { if (first < 0) { putchar( - ); return print(-first); } if (first < 10) { putchar( 0 + first); return; } print(first / 10); putchar(first % 10 + 0 ); } template <class T, class T1> inline void gn(T &first, T1 &second) { gn(first); gn(second); } template <class T, class T1, class T2> inline void gn(T &first, T1 &second, T2 &z) { gn(first); gn(second); gn(z); } template <class T> inline void println(T first) { print(first); putchar( n ); } template <class T> inline void printsp(T first) { print(first); putchar( ); } template <class T1, class T2> inline void print(T1 x1, T2 x2) { printsp(x1), println(x2); } template <class T1, class T2, class T3> inline void print(T1 x1, T2 x2, T3 x3) { printsp(x1), printsp(x2), println(x3); } template <class T1, class T2, class T3, class T4> inline void print(T1 x1, T2 x2, T3 x3, T4 x4) { printsp(x1), printsp(x2), printsp(x3), println(x4); } int son[400400][2], pa[400400], sz[400400]; long long sum[400400]; long long ans; struct SplayTree { int root; void init(int first) { root = first; sz[first] = 1; sum[first] = first; } void push_up(int first) { sum[first] = first + sum[son[first][0]] + sum[son[first][1]]; sz[first] = 1 + sz[son[first][0]] + sz[son[first][1]]; } void rot(int first, int d) { int second = pa[first], z = pa[second]; son[second][!d] = son[first][d]; pa[son[first][d]] = second; pa[first] = pa[second]; if (son[z][0] == second) son[z][0] = first; else if (son[z][1] == second) son[z][1] = first; pa[second] = first; son[first][d] = second; push_up(second); } void splay(int first, int g) { while (pa[first] != g) { if (pa[pa[first]] == g) rot(first, son[pa[first]][0] == first); else { int second = pa[first], z = pa[second]; int d = (son[z][0] == second); son[second][d] == first ? rot(first, !d) : rot(second, d); rot(first, d); } } push_up(first); if (g == 0) root = first, pa[first] = 0; } void insert(int first, int second) { if (second < first) { if (son[first][0]) insert(son[first][0], second); else son[first][0] = second, pa[second] = first; } else { if (son[first][1]) insert(son[first][1], second); else son[first][1] = second, pa[second] = first; } push_up(first); } long long insert1(int first, int f) { son[first][0] = son[first][1] = 0; sz[first] = 1; insert(root, first); splay(first, 0); if (!f) return -(long long)first * sz[son[first][0]] + sum[son[first][0]]; return -sum[son[first][1]] + (long long)first * sz[son[first][1]]; } void get(int first, vector<int> &vec) { if (son[first][0]) get(son[first][0], vec); vec.push_back(first); if (son[first][1]) get(son[first][1], vec); } } tree[400400]; int id[400400], pos[400400]; int nxt[400400]; int find_nxt(int u) { return u == nxt[u] ? u : nxt[u] = find_nxt(nxt[u]); } void merge(int u, int v, int f = 0) { if (sz[tree[u].root] < sz[tree[v].root]) swap(u, v), f = 1; vector<int> vec; tree[v].get(tree[v].root, vec); if (!f) reverse(vec.begin(), vec.end()); for (int i = 0; i < vec.size(); i++) { ans += tree[u].insert1(vec[i], f); id[pos[vec[i]]] = u; } } int main() { int n; gn(n); for (int i = 1; i < 400400; i++) nxt[i] = i; for (int i = 1; i <= n; i++) tree[i].init(i); for (int i = 0, a, b; i < n; i++) { gn(a, b); int aa = a; a = find_nxt(a); ans += (long long)(a - aa) * b; pos[b] = a; id[a] = b; nxt[a] = a + 1; if (nxt[a - 1] > a - 1) merge(id[a - 1], id[a]); if (nxt[a + 1] > a + 1) merge(id[a], id[a + 1]); println(ans); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYGATE4SD2_SYMBOL_V
`define SKY130_FD_SC_HD__DLYGATE4SD2_SYMBOL_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlygate4sd2 (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYGATE4SD2_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const long long inf = (long long)1e18; const long long mod = (long long)1e9 + 7; const double eps = (double)1e-9; const double pi = acos(-1.0); const int dx[] = {0, 0, 1, 0, -1}; const int dy[] = {0, 1, 0, -1, 0}; const int N = 100500; int n, x, y, a, b, T; long long k; multiset<long long> st, st1; long long check(int j) { st1 = st; long long ans = 0; for (int i = 1; i <= j; ++i) if (i % a == 0 && i % b == 0) { ans += *st1.begin() * (x + y); st1.erase(st1.begin()); } for (int i = 1; i <= j; ++i) if (i % a == 0 && i % b != 0) { ans += *st1.begin() * x; st1.erase(st1.begin()); } for (int i = 1; i <= j; ++i) if (i % b == 0 && i % a != 0) { ans += *st1.begin() * y; st1.erase(st1.begin()); } return -ans; } void solve() { cin >> n; st.clear(); for (int i = 1; i <= n; ++i) { long long x; cin >> x; st.insert(-x / 100); } cerr << st.size() << endl; cin >> x >> a >> y >> b >> k; if (x < y) swap(x, y), swap(a, b); int l = 1, r = n; while (l <= r) { int md = (l + r) >> 1; if (check(md) >= k) r = md - 1; else l = md + 1; } if (r == n) r = -2; cout << r + 1 << endl; } int main() { cin.tie(NULL); cout.tie(NULL); ios_base::sync_with_stdio(false); cin >> T; while (T--) solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; bool done[123][123]; char s[123][123]; vector<pair<pair<long long, long long>, long long int> > v; int main() { long long int n, m; scanf( %lld%lld , &n, &m); for (int i = 0; i < n; ++i) for (int j = 0; j < m; ++j) { done[i][j] = false; scanf( %c , &s[i][j]); } for (int i = 1; i < n - 1; ++i) for (int j = 1; j < m - 1; ++j) if (s[i][j] != . ) { if (s[i - 1][j] == * && s[i + 1][j] == * && s[i][j - 1] == * && s[i][j + 1] == * ) { long long int up = 0, dn = 0, lt = 0, rt = 0; for (int k = i - 1; k >= 0; k--) if (s[k][j] == . ) break; else up++; for (int k = i + 1; k < n; k++) if (s[k][j] == . ) break; else dn++; for (int k = j - 1; k >= 0; k--) if (s[i][k] == . ) break; else lt++; for (int k = j + 1; k < m; k++) if (s[i][k] == . ) break; else rt++; long long int mn = min(up, min(dn, min(lt, rt))); if (mn) { v.push_back( make_pair(pair<long long, long long>(i + 1, j + 1), mn)); int k, cnt; cnt = mn; done[i][j] = true; for (k = i - 1; cnt; k--, cnt--) done[k][j] = true; cnt = mn; for (k = i + 1; cnt; k++, cnt--) done[k][j] = true; cnt = mn; for (k = j - 1; cnt; k--, cnt--) done[i][k] = true; cnt = mn; for (k = j + 1; cnt; k++, cnt--) done[i][k] = true; } } } for (int i = 0; i < n; ++i) for (int j = 0; j < m; ++j) if (s[i][j] == * && done[i][j] == false) { printf( -1 n ); return 0; } printf( %lld n , (long long int)v.size()); for (int i = 0; i != (long long int)v.size(); ++i) printf( %lld %lld %lld n , v[i].first.first, v[i].first.second, v[i].second); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, q; unordered_map<int, pair<int, int>> resi[50 * 3 + 2]; struct FLOW { int n, *pre, *dist; FLOW(int n) : n(n) { pre = (int *)malloc((n + 2) * sizeof(int)); dist = (int *)malloc((n + 2) * sizeof(int)); } ~FLOW() { free(pre); free(dist); } pair<int, int> SAP() { int flow = 0, cost = 0; for (; SPFA();) { for (int i = n + 1; i != n; i = pre[i]) { assert(resi[pre[i]].count(i)); resi[pre[i]][i].first -= pre[n]; if (resi[i].count(pre[i])) resi[i][pre[i]].first += pre[n]; else resi[i][pre[i]] = make_pair(pre[n], -resi[pre[i]][i].second); } flow += pre[n]; cost += pre[n] * dist[n + 1]; } return make_pair(flow, cost); } bool SPFA() { int nn = n + 2, q[nn + 1]; bool v[nn]; int h = 0, l = 1, x; for (int i = 0; i < nn; i++) dist[i] = (50 * 50 * 50); memset(pre, -1, nn * sizeof(int)); memset(v, false, nn * sizeof(bool)); dist[n] = 0, pre[n] = -1; q[0] = n, v[n] = true; while (l != 0) { x = q[h]; v[q[h]] = false; l--; h = (h + 1) % nn; for (unordered_map<int, pair<int, int>>::const_iterator ix = resi[x].begin(); ix != resi[x].end(); ix++) { if (ix->second.first == 0) continue; int i = ix->first, p = ix->second.second; if (dist[x] + p < dist[i]) { dist[i] = dist[x] + p; pre[i] = x; if (!v[i]) v[q[(h + l++) % nn] = i] = true; } } } if (pre[n + 1] != -1) { int flow = (50 * 50 * 50); for (int i = n + 1; i != n; i = pre[i]) if (resi[pre[i]][i].first < flow) flow = resi[pre[i]][i].first; pre[n] = flow; } return pre[n + 1] != -1; } }; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> q; int arr[n][2], t, l, r, v; for (int i = 0; i < n; i++) arr[i][0] = 1, arr[i][1] = n; for (int iq = 0; iq < q; iq++) { cin >> t >> l >> r >> v; if (t == 1) for (int i = l - 1; i < r; i++) arr[i][0] = max(arr[i][0], v); else if (t == 2) for (int i = l - 1; i < r; i++) arr[i][1] = min(arr[i][1], v); } for (int i = 0; i < n; i++) { resi[3 * n][i] = make_pair(1, 0); resi[2 * n + i][3 * n + 1] = make_pair(n, 2 * i + 1); for (int j = 0; j < n; j++) resi[n + i][2 * n + j] = make_pair(1, 0); for (int j = arr[i][0] - 1; j < arr[i][1]; j++) resi[i][n + j] = make_pair(1, 0); } FLOW flow(3 * n); pair<int, int> ans = flow.SAP(); if (ans.first != n) cout << -1 << endl; else cout << ans.second << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int qmin(int a, int b) { return (a < b) ? a : b; } int qmax(int a, int b) { return (a > b) ? a : b; } int n, m, k; int x[555], y[555]; int xl[555], xr[555], yl[555], yr[555]; set<int> stx, sty; map<int, int> mpx; int xpos[1010]; vector<int> l[1010], r[1010]; multiset<pair<int, int> > y_seg_l; bool check(int now) { for (int i = 0; i < 1001; i++) l[i].clear(), r[i].clear(); for (int i = 0; i < k; i++) xl[i] = qmax(x[i] - now, 1), xr[i] = qmin(x[i] + now, n), yl[i] = qmax(y[i] - now, 1), yr[i] = qmin(y[i] + now, m); stx.clear(), sty.clear(); for (int i = 0; i < k; i++) stx.insert(xl[i]), stx.insert(xr[i] + 1); stx.insert(1), stx.insert(n + 1); int cnt = 0; for (set<int>::iterator it = stx.begin(); it != stx.end(); it++, cnt++) mpx[*it] = cnt, xpos[cnt] = *it; for (int i = 0; i < k; i++) l[mpx[xl[i]]].push_back(i), r[mpx[xr[i] + 1]].push_back(i); y_seg_l.clear(); int xxl = n + 1, xxr = 0, yyl = m + 1, yyr = 0; y_seg_l.insert(make_pair(0, 0)); y_seg_l.insert(make_pair(m + 1, m + 1)); for (int i = 0; i < cnt - 1; i++) { for (int j = 0; j < (int)r[i].size(); j++) { multiset<pair<int, int> >::iterator it = y_seg_l.lower_bound(make_pair(yl[r[i][j]], yr[r[i][j]])); y_seg_l.erase(it); } for (int j = 0; j < (int)l[i].size(); j++) y_seg_l.insert(make_pair(yl[l[i][j]], yr[l[i][j]])); int nr = 0; int nyl = m + 1, nyr = 0; for (set<pair<int, int> >::iterator it = y_seg_l.begin(); it != y_seg_l.end(); it++) { if (it->first > nr + 1) nyl = qmin(nyl, nr + 1), nyr = qmax(nyr, it->first - 1); nr = qmax(nr, it->second); } if (nyr > 0) { xxl = qmin(xxl, xpos[i]); xxr = qmax(xxr, xpos[i + 1] - 1); } yyl = qmin(yyl, nyl); yyr = qmax(yyr, nyr); } if (xxr == 0) return 1; return ((xxr - xxl + 1) <= (now + now + 1)) && ((yyr - yyl + 1) <= (now + now + 1)); } int main() { ios::sync_with_stdio(false); cin >> n >> m >> k; for (int i = 0; i < k; i++) cin >> x[i] >> y[i]; int lb = 0, ub = 1e9; while (lb <= ub) { int mid = (lb + ub) >> 1; if (check(mid)) ub = mid - 1; else lb = mid + 1; } cout << lb << endl; return 0; } |
module top
(
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
parameter SRL_COUNT = 4;
parameter PRESCALER = 4; // 100000
// Uart loopback
assign tx = rx;
// ============================================================================
// Reset
reg [3:0] rst_sr;
wire rst;
initial rst_sr <= 4'hF;
always @(posedge clk)
if (sw[0]) rst_sr <= 4'hF;
else rst_sr <= rst_sr >> 1;
assign rst = rst_sr[0];
// ============================================================================
// Clock prescaler
reg [32:0] ps_cnt = 0;
wire ps_tick = ps_cnt[32];
always @(posedge clk)
if (rst || ps_tick)
ps_cnt <= PRESCALER - 2;
else
ps_cnt <= ps_cnt - 1;
// ============================================================================
// SRL32 testers
wire sim_error = sw[2];
wire [SRL_COUNT-1:0] srl_q;
wire [SRL_COUNT-1:0] error;
genvar i;
generate for(i=0; i<SRL_COUNT; i=i+1) begin
wire [4:0] srl_a;
wire srl_d;
wire srl_sh;
srl_init_tester #
(
.PATTERN (32'hF27828DB)
)
tester
(
.clk (clk),
.rst (rst),
.ce (ps_tick),
.srl_sh (srl_sh),
.srl_d (srl_d),
.srl_q (srl_q[i] ^ sim_error),
.srl_a (srl_a),
.error (error[i])
);
SRLC32E #
(
.INIT (32'hF27828DB)
)
srl
(
.CLK (clk),
.CE (srl_sh),
.A (srl_a),
.D (srl_d),
.Q (srl_q[i])
);
end endgenerate
// ============================================================================
// Error latch
reg [SRL_COUNT:0] error_lat = 0;
always @(posedge clk)
if (rst)
error_lat <= 0;
else
error_lat <= error_lat | error;
// ============================================================================
// Create a non-GND/VCC source for additional LED outputs.
// This is a side affect of the ROI disallowing GND/VCC connections to synth
// IO pads.
wire net_0;
LUT2 #(.INIT(4'hC)) lut_0 (.I0(|sw), .I1(&sw), .O(net_0));
// LEDs
genvar j;
generate for(j=0; j<8; j=j+1) begin
if (j < SRL_COUNT) begin
assign led[j ] = (sw[1]) ? error_lat[j] : error[j];
assign led[j+8] = srl_q[j];
end else begin
assign led[j ] = net_0;
assign led[j+8] = net_0;
end
end endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int x[505], r[505]; int main() { int i; x[0] = 0; r[0] = 1000000; double dd; int d; for (i = 1; i <= 300; i++) { r[i] = 300 - i + 1; dd = 2 * sqrt(double(r[i - 1])) * sqrt(double(r[i])); d = int(dd + 3); x[i] = x[i - 1] + d; } x[301] = x[300] + 10000; r[301] = 1000000; printf( 302 ); for (i = 0; i < 302; i++) { printf( n%d %d , x[i], r[i]); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, k, a; cin >> n >> k; list<int> lst; map<int, bool> vis; for (int i = 0; i < n; i++) { cin >> a; if (lst.size() < k) { if (vis.find(a) == vis.end()) { lst.push_front(a); vis[a] = true; } continue; } if (vis.find(a) == vis.end() || vis[a] == false) { vis[a] = true; vis[lst.back()] = false; lst.pop_back(); lst.push_front(a); } } cout << lst.size() << endl; for (auto it = lst.begin(); it != lst.end(); it++) cout << (*it) << ; cout << endl; return 0; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// usbSlaveCyc2Wrap_usb1t11.v ////
//// ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// Top level module wrapper.
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
module usbSlaveCyc2Wrap_usb1t11(
clk_i,
rst_i,
address_i,
data_i,
data_o,
we_i,
strobe_i,
ack_o,
irq,
usbClk,
USBWireVPin,
USBWireVMin,
USBWireVPout,
USBWireVMout,
USBWireOE_n,
USBFullSpeed,
USBDPlusPullup,
USBDMinusPullup,
vBusDetect
);
input clk_i;
input rst_i;
input [7:0] address_i;
input [7:0] data_i;
output [7:0] data_o;
input we_i;
input strobe_i;
output ack_o;
output irq;
input usbClk;
input USBWireVPin /* synthesis useioff=1 */;
input USBWireVMin /* synthesis useioff=1 */;
output USBWireVPout /* synthesis useioff=1 */;
output USBWireVMout /* synthesis useioff=1 */;
output USBWireOE_n /* synthesis useioff=1 */;
output USBFullSpeed /* synthesis useioff=1 */;
output USBDPlusPullup;
output USBDMinusPullup;
input vBusDetect;
wire clk_i;
wire rst_i;
wire [7:0] address_i;
wire [7:0] data_i;
wire [7:0] data_o;
wire irq;
wire usbClk;
wire USBWireDataOutTick;
wire USBWireDataInTick;
wire USBFullSpeed;
//internal wiring
wire slaveSOFRxedIntOut;
wire slaveResetEventIntOut;
wire slaveResumeIntOut;
wire slaveTransDoneIntOut;
wire slaveNAKSentIntOut;
wire slaveVBusDetIntOut;
wire USBWireCtrlOut;
wire [1:0] USBWireDataIn;
wire [1:0] USBWireDataOut;
assign irq = slaveSOFRxedIntOut | slaveResetEventIntOut |
slaveResumeIntOut | slaveTransDoneIntOut |
slaveNAKSentIntOut | slaveVBusDetIntOut;
assign USBWireDataIn = {USBWireVPin, USBWireVMin};
assign {USBWireVPout, USBWireVMout} = USBWireDataOut;
assign USBWireOE_n = ~USBWireCtrlOut;
//Parameters declaration:
defparam usbSlaveInst.EP0_FIFO_DEPTH = 64;
defparam usbSlaveInst.EP0_FIFO_ADDR_WIDTH = 6;
defparam usbSlaveInst.EP1_FIFO_DEPTH = 64;
defparam usbSlaveInst.EP1_FIFO_ADDR_WIDTH = 6;
defparam usbSlaveInst.EP2_FIFO_DEPTH = 64;
defparam usbSlaveInst.EP2_FIFO_ADDR_WIDTH = 6;
defparam usbSlaveInst.EP3_FIFO_DEPTH = 64;
defparam usbSlaveInst.EP3_FIFO_ADDR_WIDTH = 6;
usbSlave usbSlaveInst (
.clk_i(clk_i),
.rst_i(rst_i),
.address_i(address_i),
.data_i(data_i),
.data_o(data_o),
.we_i(we_i),
.strobe_i(strobe_i),
.ack_o(ack_o),
.usbClk(usbClk),
.slaveSOFRxedIntOut(slaveSOFRxedIntOut),
.slaveResetEventIntOut(slaveResetEventIntOut),
.slaveResumeIntOut(slaveResumeIntOut),
.slaveTransDoneIntOut(slaveTransDoneIntOut),
.slaveNAKSentIntOut(slaveNAKSentIntOut),
.slaveVBusDetIntOut(slaveVBusDetIntOut),
.USBWireDataIn(USBWireDataIn),
.USBWireDataInTick(USBWireDataInTick),
.USBWireDataOut(USBWireDataOut),
.USBWireDataOutTick(USBWireDataOutTick),
.USBWireCtrlOut(USBWireCtrlOut),
.USBFullSpeed(USBFullSpeed),
.USBDPlusPullup(USBDPlusPullup),
.USBDMinusPullup(USBDMinusPullup),
.vBusDetect(vBusDetect)
);
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:51:26 09/02/2013
// Design Name: siete_segmentos_principal
// Module Name: C:/Users/Fabian/Documents/Taller Diseno/Xilinx/Lab1/sietesegmentos/pruebaalonso.v
// Project Name: sietesegmentos
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: siete_segmentos_principal
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module pruebaalonso;
// Inputs
reg bitA;
reg bitB;
reg bitC;
reg bitD;
reg en1;
reg en2;
reg en3;
reg en4;
// Outputs
wire seg_a;
wire seg_b;
wire seg_c;
wire seg_d;
wire seg_e;
wire seg_f;
wire seg_g;
wire s_seg1;
wire s_seg2;
wire s_seg3;
wire s_seg4;
// Instantiate the Unit Under Test (UUT)
siete_segmentos_principal uut (
.bitA(bitA),
.bitB(bitB),
.bitC(bitC),
.bitD(bitD),
.en1(en1),
.en2(en2),
.en3(en3),
.en4(en4),
.seg_a(seg_a),
.seg_b(seg_b),
.seg_c(seg_c),
.seg_d(seg_d),
.seg_e(seg_e),
.seg_f(seg_f),
.seg_g(seg_g),
.s_seg1(s_seg1),
.s_seg2(s_seg2),
.s_seg3(s_seg3),
.s_seg4(s_seg4)
);
initial begin
// Initialize Inputs
bitA = 0;
bitB = 0;
bitC = 0;
bitD = 0;
en1 = 0;
en2 = 0;
en3 = 0;
en4 = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
bitD = 1;
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module cf_dds_top (
vdma_clk,
vdma_valid,
vdma_data,
vdma_ready,
vdma_ovf,
vdma_unf,
dac_div3_clk,
dds_data_00,
dds_data_01,
dds_data_02,
dds_data_03,
dds_data_04,
dds_data_05,
dds_data_06,
dds_data_07,
dds_data_08,
dds_data_09,
dds_data_10,
dds_data_11,
up_dds_sel,
up_dds_incr,
up_dds_enable,
up_dds_interpolate,
debug_clk,
debug_data,
debug_trigger);
input vdma_clk;
input vdma_valid;
input [63:0] vdma_data;
output vdma_ready;
output vdma_ovf;
output vdma_unf;
input dac_div3_clk;
output [13:0] dds_data_00;
output [13:0] dds_data_01;
output [13:0] dds_data_02;
output [13:0] dds_data_03;
output [13:0] dds_data_04;
output [13:0] dds_data_05;
output [13:0] dds_data_06;
output [13:0] dds_data_07;
output [13:0] dds_data_08;
output [13:0] dds_data_09;
output [13:0] dds_data_10;
output [13:0] dds_data_11;
input up_dds_sel;
input [15:0] up_dds_incr;
input up_dds_enable;
input up_dds_interpolate;
output debug_clk;
output [79:0] debug_data;
output [ 7:0] debug_trigger;
reg dds_sel_m1 = 'd0;
reg dds_sel = 'd0;
reg [13:0] dds_data_00 = 'd0;
reg [13:0] dds_data_01 = 'd0;
reg [13:0] dds_data_02 = 'd0;
reg [13:0] dds_data_03 = 'd0;
reg [13:0] dds_data_04 = 'd0;
reg [13:0] dds_data_05 = 'd0;
reg [13:0] dds_data_06 = 'd0;
reg [13:0] dds_data_07 = 'd0;
reg [13:0] dds_data_08 = 'd0;
reg [13:0] dds_data_09 = 'd0;
reg [13:0] dds_data_10 = 'd0;
reg [13:0] dds_data_11 = 'd0;
wire [13:0] ddsx_data_00_s;
wire [13:0] ddsx_data_01_s;
wire [13:0] ddsx_data_02_s;
wire [13:0] ddsx_data_03_s;
wire [13:0] ddsx_data_04_s;
wire [13:0] ddsx_data_05_s;
wire [13:0] ddsx_data_06_s;
wire [13:0] ddsx_data_07_s;
wire [13:0] ddsx_data_08_s;
wire [13:0] ddsx_data_09_s;
wire [13:0] ddsx_data_10_s;
wire [13:0] ddsx_data_11_s;
wire [13:0] ddsv_data_00_s;
wire [13:0] ddsv_data_01_s;
wire [13:0] ddsv_data_02_s;
wire [13:0] ddsv_data_03_s;
wire [13:0] ddsv_data_04_s;
wire [13:0] ddsv_data_05_s;
wire [13:0] ddsv_data_06_s;
wire [13:0] ddsv_data_07_s;
wire [13:0] ddsv_data_08_s;
wire [13:0] ddsv_data_09_s;
wire [13:0] ddsv_data_10_s;
wire [13:0] ddsv_data_11_s;
always @(posedge dac_div3_clk) begin
dds_sel_m1 <= up_dds_sel;
dds_sel <= dds_sel_m1;
end
always @(posedge dac_div3_clk) begin
dds_data_00 <= (dds_sel == 1'b1) ? ddsv_data_00_s : ddsx_data_00_s;
dds_data_01 <= (dds_sel == 1'b1) ? ddsv_data_01_s : ddsx_data_01_s;
dds_data_02 <= (dds_sel == 1'b1) ? ddsv_data_02_s : ddsx_data_02_s;
dds_data_03 <= (dds_sel == 1'b1) ? ddsv_data_03_s : ddsx_data_03_s;
dds_data_04 <= (dds_sel == 1'b1) ? ddsv_data_04_s : ddsx_data_04_s;
dds_data_05 <= (dds_sel == 1'b1) ? ddsv_data_05_s : ddsx_data_05_s;
dds_data_06 <= (dds_sel == 1'b1) ? ddsv_data_06_s : ddsx_data_06_s;
dds_data_07 <= (dds_sel == 1'b1) ? ddsv_data_07_s : ddsx_data_07_s;
dds_data_08 <= (dds_sel == 1'b1) ? ddsv_data_08_s : ddsx_data_08_s;
dds_data_09 <= (dds_sel == 1'b1) ? ddsv_data_09_s : ddsx_data_09_s;
dds_data_10 <= (dds_sel == 1'b1) ? ddsv_data_10_s : ddsx_data_10_s;
dds_data_11 <= (dds_sel == 1'b1) ? ddsv_data_11_s : ddsx_data_11_s;
end
cf_ddsx i_ddsx (
.dac_div3_clk (dac_div3_clk),
.dds_data_00 (ddsx_data_00_s),
.dds_data_01 (ddsx_data_01_s),
.dds_data_02 (ddsx_data_02_s),
.dds_data_03 (ddsx_data_03_s),
.dds_data_04 (ddsx_data_04_s),
.dds_data_05 (ddsx_data_05_s),
.dds_data_06 (ddsx_data_06_s),
.dds_data_07 (ddsx_data_07_s),
.dds_data_08 (ddsx_data_08_s),
.dds_data_09 (ddsx_data_09_s),
.dds_data_10 (ddsx_data_10_s),
.dds_data_11 (ddsx_data_11_s),
.up_dds_enable (up_dds_enable),
.up_dds_incr (up_dds_incr));
cf_ddsv i_ddsv (
.vdma_clk (vdma_clk),
.vdma_valid (vdma_valid),
.vdma_data (vdma_data),
.vdma_ready (vdma_ready),
.vdma_ovf (vdma_ovf),
.vdma_unf (vdma_unf),
.dac_div3_clk (dac_div3_clk),
.dds_data_00 (ddsv_data_00_s),
.dds_data_01 (ddsv_data_01_s),
.dds_data_02 (ddsv_data_02_s),
.dds_data_03 (ddsv_data_03_s),
.dds_data_04 (ddsv_data_04_s),
.dds_data_05 (ddsv_data_05_s),
.dds_data_06 (ddsv_data_06_s),
.dds_data_07 (ddsv_data_07_s),
.dds_data_08 (ddsv_data_08_s),
.dds_data_09 (ddsv_data_09_s),
.dds_data_10 (ddsv_data_10_s),
.dds_data_11 (ddsv_data_11_s),
.up_dds_enable (up_dds_enable),
.up_dds_interpolate (up_dds_interpolate),
.debug_clk (debug_clk),
.debug_data (debug_data),
.debug_trigger (debug_trigger));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// file: bclk_dll_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module bclk_dll_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 7.518*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
// Status and control signals
reg RESET = 0;
wire LOCKED;
reg COUNTER_RESET = 0;
wire [1:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
reg [13:0] timeout_counter = 14'b00000000000000;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
$display ("Timing checks are not valid");
COUNTER_RESET = 0;
test_phase = "reset";
RESET = 1;
#(PER1*6);
RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*19.5)
COUNTER_RESET = 0;
#(PER1*1)
$display ("Timing checks are valid");
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
always@(posedge CLK_IN1) begin
timeout_counter <= timeout_counter + 1'b1;
if (timeout_counter == 14'b10000000000000) begin
if (LOCKED != 1'b1) begin
$display("ERROR : NO LOCK signal");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
end
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
bclk_dll_exdes
dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED));
// Freq Check
endmodule
|
/*============================================================================
This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point
Arithmetic Package, Release 1, by John R. Hauser.
Copyright 2019 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
`include "HardFloat_consts.vi"
`include "HardFloat_specialize.vi"
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module
test_recFNToIN#(
parameter expWidth = 3, parameter sigWidth = 3, parameter intWidth = 1
);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
parameter maxNumErrors = 20;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
localparam formatWidth = expWidth + sigWidth;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
reg [(`floatControlWidth - 1):0] control;
reg [2:0] roundingMode;
reg signedOut;
reg [(formatWidth - 1):0] in;
reg [(intWidth - 1):0] expectOut;
reg [4:0] expectExceptionFlags;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire [formatWidth:0] recIn;
fNToRecFN#(expWidth, sigWidth) fNToRecFN_in(in, recIn);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire [(intWidth - 1):0] out;
wire [2:0] intExceptionFlags;
recFNToIN#(expWidth, sigWidth, intWidth)
recFNToIN(
control, recIn, roundingMode, signedOut, out, intExceptionFlags);
wire [4:0] exceptionFlags =
{|intExceptionFlags[2:1], 3'b0, intExceptionFlags[0]};
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
integer errorCount, count, partialCount;
initial begin
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
$fwrite('h80000002, "Testing 'recF%0dToI%0d'", formatWidth, intWidth);
if (
$fscanf('h80000000, "%h %h %h", control, signedOut, roundingMode)
< 3
) begin
$fdisplay('h80000002, ".\n--> Invalid test-cases input.");
`finish_fail;
end
$fdisplay(
'h80000002,
"control %H, signed %0d, rounding mode %0d:",
control,
signedOut,
roundingMode
);
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
errorCount = 0;
count = 0;
partialCount = 0;
begin :TestLoop
while (
$fscanf(
'h80000000, "%h %h %h", in, expectOut, expectExceptionFlags
) == 3
) begin
#1;
partialCount = partialCount + 1;
if (partialCount == 10000) begin
count = count + 10000;
$fdisplay('h80000002, "%0d...", count);
partialCount = 0;
end
if (
(out != expectOut)
|| (exceptionFlags !== expectExceptionFlags)
) begin
if (errorCount == 0) begin
$display(
"Errors found in 'recF%0dToI%0d', control %H, signed %0d, rounding mode %0d:",
formatWidth,
intWidth,
control,
signedOut,
roundingMode
);
end
$write("%H => %H %H", recIn, out, exceptionFlags);
if (formatWidth + intWidth > 160) begin
$write("\n\t");
end else begin
$write(" ");
end
$display(
"expected %H %H", expectOut, expectExceptionFlags);
errorCount = errorCount + 1;
if (errorCount == maxNumErrors) disable TestLoop;
end
#1;
end
end
count = count + partialCount;
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
if (errorCount) begin
$fdisplay(
'h80000002,
"--> In %0d tests, %0d errors found.",
count,
errorCount
);
`finish_fail;
end else if (count == 0) begin
$fdisplay('h80000002, "--> Invalid test-cases input.");
`finish_fail;
end else begin
$display(
"In %0d tests, no errors found in 'recF%0dToI%0d', control %H, signed %0d, rounding mode %0d.",
count,
formatWidth,
intWidth,
control,
signedOut,
roundingMode
);
end
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
$finish;
end
endmodule
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module test_recF16ToI32;
test_recFNToIN#(5, 11, 32) test_recF16ToI32();
endmodule
module test_recF32ToI32;
test_recFNToIN#(8, 24, 32) test_recF32ToI32();
endmodule
module test_recF64ToI32;
test_recFNToIN#(11, 53, 32) test_recF64ToI32();
endmodule
module test_recF128ToI32;
test_recFNToIN#(15, 113, 32) test_recF128ToI32();
endmodule
module test_recF16ToI64;
test_recFNToIN#(5, 11, 64) test_recF16ToI64();
endmodule
module test_recF32ToI64;
test_recFNToIN#(8, 24, 64) test_recF32ToI64();
endmodule
module test_recF64ToI64;
test_recFNToIN#(11, 53, 64) test_recF64ToI64();
endmodule
module test_recF128ToI64;
test_recFNToIN#(15, 113, 64) test_recF128ToI64();
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long a; cin >> a; cout << (a + a / 2) << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O211AI_TB_V
`define SKY130_FD_SC_MS__O211AI_TB_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o211ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 C1 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 C1 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 C1 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 C1 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_ms__o211ai dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O211AI_TB_V
|
#include <bits/stdc++.h> using namespace std; long long n, ans; string str; long long solve() { long long k; cin >> n >> k; long long t = 3 * n; while (t > k) { t--; ans++; } cout << ans; return 0; } signed main() { ios::sync_with_stdio(0); long long t = 1; while (t--) solve(); return 0; } |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2007 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file fifo_xlnx_16x19_2clk.v when simulating
// the core, fifo_xlnx_16x19_2clk. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module fifo_xlnx_16x19_2clk(
din,
rd_clk,
rd_en,
rst,
wr_clk,
wr_en,
dout,
empty,
full,
rd_data_count,
wr_data_count);
input [18 : 0] din;
input rd_clk;
input rd_en;
input rst;
input wr_clk;
input wr_en;
output [18 : 0] dout;
output empty;
output full;
output [4 : 0] rd_data_count;
output [4 : 0] wr_data_count;
// synthesis translate_off
FIFO_GENERATOR_V4_3 #(
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(5),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(19),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(19),
.C_ENABLE_RLOCS(0),
.C_FAMILY("spartan3"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(1),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(1),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(2),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(15),
.C_PROG_FULL_THRESH_NEGATE_VAL(14),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(5),
.C_RD_DEPTH(16),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(4),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(5),
.C_WR_DEPTH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(4),
.C_WR_RESPONSE_LATENCY(1))
inst (
.DIN(din),
.RD_CLK(rd_clk),
.RD_EN(rd_en),
.RST(rst),
.WR_CLK(wr_clk),
.WR_EN(wr_en),
.DOUT(dout),
.EMPTY(empty),
.FULL(full),
.RD_DATA_COUNT(rd_data_count),
.WR_DATA_COUNT(wr_data_count),
.CLK(),
.INT_CLK(),
.BACKUP(),
.BACKUP_MARKER(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.RD_RST(),
.SRST(),
.WR_RST(),
.ALMOST_EMPTY(),
.ALMOST_FULL(),
.DATA_COUNT(),
.OVERFLOW(),
.PROG_EMPTY(),
.PROG_FULL(),
.VALID(),
.UNDERFLOW(),
.WR_ACK(),
.SBITERR(),
.DBITERR());
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> a(n); map<int, vector<int>> indices; for (int i = 0; i < n; i++) cin >> a[i], indices[a[i]].push_back(i); map<int, int> dp; int mxn = 0, ans = -1; for (int i = n - 1; i >= 0; i--) { dp[a[i]] = 1 + dp[a[i] + 1]; if (dp[a[i]] > mxn) mxn = dp[a[i]], ans = a[i]; } cout << mxn << n ; int prevI = -1, currA = ans; while (mxn) { int currI = lower_bound(indices[currA].begin(), indices[currA].end(), prevI) - indices[currA].begin(); cout << indices[currA][currI] + 1 << ; prevI = indices[currA][currI], currA++, mxn--; } return 0; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// i2cSlave.v ////
//// ////
//// This file is part of the i2cSlave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// You will need to modify this file to implement your
//// interface.
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "i2cSlave_define.v"
module i2cSlave (
input clk,
input rst,
inout sda,
input scl,
output[7:0] ram_dataIn,
output[9:0] ram_wraddress,
output ram_wren,
output enable_osd,
output[7:0] highlight_line,
output[7:0] reconf_data,
output[7:0] video_gen_data,
output Scanline scanline,
output [23:0] conf240p,
output reset_dc,
output reset_opt,
output[7:0] reset_conf,
output activateHDMIoutput,
output hq2x,
output [1:0] colorspace,
input [23:0] pinok,
input [23:0] timingInfo,
input [23:0] rgbData,
input add_line,
input line_doubler,
input is_pal,
input force_generate,
input ControllerData controller_data,
input KeyboardData keyboard_data,
input [31:0] pll_adv_lockloss_count,
input [31:0] hpd_low_count,
input [31:0] pll54_lockloss_count,
input [31:0] pll_hdmi_lockloss_count,
input [31:0] control_resync_out_count,
input [31:0] monitor_sense_low_count,
input [15:0] testdata,
output [7:0] clock_config_data,
output [7:0] color_config_data,
input [11:0] nonBlackPos1,
input [11:0] nonBlackPos2,
output nonBlackPixelReset,
input [23:0] color_space_explorer,
output resetpll
);
// local wires and regs
reg sdaDeb;
reg sclDeb;
reg [`DEB_I2C_LEN-1:0] sdaPipe;
reg [`DEB_I2C_LEN-1:0] sclPipe;
reg [`SCL_DEL_LEN-1:0] sclDelayed;
reg [`SDA_DEL_LEN-1:0] sdaDelayed;
reg [1:0] startStopDetState;
wire clearStartStopDet;
wire sdaOut;
wire sdaIn;
wire [7:0] regAddr;
wire [7:0] dataToRegIF;
wire writeEn;
wire [7:0] dataFromRegIF;
reg [1:0] rstPipe;
wire rstSyncToClk;
reg startEdgeDet;
assign sda = (sdaOut == 1'b0) ? 1'b0 : 1'bz;
assign sdaIn = sda;
// sync rst rsing edge to clk
always @(posedge clk) begin
if (rst == 1'b1)
rstPipe <= 2'b11;
else
rstPipe <= {rstPipe[0], 1'b0};
end
assign rstSyncToClk = rstPipe[1];
// debounce sda and scl
always @(posedge clk) begin
if (rstSyncToClk == 1'b1) begin
sdaPipe <= {`DEB_I2C_LEN{1'b1}};
sdaDeb <= 1'b1;
sclPipe <= {`DEB_I2C_LEN{1'b1}};
sclDeb <= 1'b1;
end
else begin
sdaPipe <= {sdaPipe[`DEB_I2C_LEN-2:0], sdaIn};
sclPipe <= {sclPipe[`DEB_I2C_LEN-2:0], scl};
if (&sclPipe[`DEB_I2C_LEN-1:1] == 1'b1)
sclDeb <= 1'b1;
else if (|sclPipe[`DEB_I2C_LEN-1:1] == 1'b0)
sclDeb <= 1'b0;
if (&sdaPipe[`DEB_I2C_LEN-1:1] == 1'b1)
sdaDeb <= 1'b1;
else if (|sdaPipe[`DEB_I2C_LEN-1:1] == 1'b0)
sdaDeb <= 1'b0;
end
end
// delay scl and sda
// sclDelayed is used as a delayed sampling clock
// sdaDelayed is only used for start stop detection
// Because sda hold time from scl falling is 0nS
// sda must be delayed with respect to scl to avoid incorrect
// detection of start/stop at scl falling edge.
always @(posedge clk) begin
if (rstSyncToClk == 1'b1) begin
sclDelayed <= {`SCL_DEL_LEN{1'b1}};
sdaDelayed <= {`SDA_DEL_LEN{1'b1}};
end
else begin
sclDelayed <= {sclDelayed[`SCL_DEL_LEN-2:0], sclDeb};
sdaDelayed <= {sdaDelayed[`SDA_DEL_LEN-2:0], sdaDeb};
end
end
// start stop detection
always @(posedge clk) begin
if (rstSyncToClk == 1'b1) begin
startStopDetState <= `NULL_DET;
startEdgeDet <= 1'b0;
end
else begin
if (sclDeb == 1'b1 && sdaDelayed[`SDA_DEL_LEN-2] == 1'b0 && sdaDelayed[`SDA_DEL_LEN-1] == 1'b1)
startEdgeDet <= 1'b1;
else
startEdgeDet <= 1'b0;
if (clearStartStopDet == 1'b1)
startStopDetState <= `NULL_DET;
else if (sclDeb == 1'b1) begin
if (sdaDelayed[`SDA_DEL_LEN-2] == 1'b1 && sdaDelayed[`SDA_DEL_LEN-1] == 1'b0)
startStopDetState <= `STOP_DET;
else if (sdaDelayed[`SDA_DEL_LEN-2] == 1'b0 && sdaDelayed[`SDA_DEL_LEN-1] == 1'b1)
startStopDetState <= `START_DET;
end
end
end
registerInterface u_registerInterface(
.clk(clk),
.addr(regAddr),
.dataIn(dataToRegIF),
.writeEn(writeEn),
.dataOut(dataFromRegIF),
.ram_dataIn(ram_dataIn),
.ram_wraddress(ram_wraddress),
.ram_wren(ram_wren),
.enable_osd(enable_osd),
//.debugData(debugData),
.controller_data(controller_data),
.keyboard_data(keyboard_data),
.highlight_line(highlight_line),
.reconf_data(reconf_data),
.video_gen_data(video_gen_data),
.scanline(scanline),
.conf240p(conf240p),
.reset_dc(reset_dc),
.reset_opt(reset_opt),
.reset_conf(reset_conf),
.pinok(pinok),
.timingInfo(timingInfo),
.rgbData(rgbData),
.add_line(add_line),
.line_doubler(line_doubler),
.is_pal(is_pal),
.force_generate(force_generate),
.activateHDMIoutput(activateHDMIoutput),
.hq2x(hq2x),
.colorspace(colorspace),
.pll_adv_lockloss_count(pll_adv_lockloss_count),
.hpd_low_count(hpd_low_count),
.pll54_lockloss_count(pll54_lockloss_count),
.pll_hdmi_lockloss_count(pll_hdmi_lockloss_count),
.control_resync_out_count(control_resync_out_count),
.monitor_sense_low_count(monitor_sense_low_count),
.testdata(testdata),
.clock_config_data(clock_config_data),
.color_config_data(color_config_data),
.nonBlackPos1(nonBlackPos1),
.nonBlackPos2(nonBlackPos2),
.nonBlackPixelReset(nonBlackPixelReset),
.color_space_explorer(color_space_explorer),
.resetpll(resetpll)
);
serialInterface u_serialInterface (
.clk(clk),
.rst(rstSyncToClk | startEdgeDet),
.dataIn(dataFromRegIF),
.dataOut(dataToRegIF),
.writeEn(writeEn),
.regAddr(regAddr),
.scl(sclDelayed[`SCL_DEL_LEN-1]),
.sdaIn(sdaDeb),
.sdaOut(sdaOut),
.startStopDetState(startStopDetState),
.clearStartStopDet(clearStartStopDet)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 0x3f3f3f3f; const long long MAXN = 3e5 + 5; long long n, MOD, k, ans; map<long long, long long> mp; signed main() { scanf( %lld%lld%lld , &n, &MOD, &k); for (long long i = 1; i <= n; i++) { long long x; scanf( %lld , &x); x = (x * x % MOD * x % MOD * x % MOD + MOD - x * k % MOD) % MOD; mp[x]++; } for (map<long long, long long>::iterator it = mp.begin(); it != mp.end(); it++) { long long x = it->second; ans += (x - 1) * x / 2; } printf( %lld n , ans); return 0; } |
// Copyright (C) 2020-2021 The SymbiFlow Authors.
//
// Use of this source code is governed by a ISC-style
// license that can be found in the LICENSE file or at
// https://opensource.org/licenses/ISC
//
// SPDX-License-Identifier:ISC
module fsm (
clock,
reset,
req_0,
req_1,
gnt_0,
gnt_1
);
input clock, reset, req_0, req_1;
output gnt_0, gnt_1;
wire clock, reset, req_0, req_1;
reg gnt_0, gnt_1;
parameter SIZE = 3;
parameter IDLE = 3'b001;
parameter GNT0 = 3'b010;
parameter GNT1 = 3'b100;
parameter GNT2 = 3'b101;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
always @(posedge clock) begin : FSM
if (reset == 1'b1) begin
state <= #1 IDLE;
gnt_0 <= 0;
gnt_1 <= 0;
end else
case (state)
IDLE:
if (req_0 == 1'b1) begin
state <= #1 GNT0;
gnt_0 <= 1;
end else if (req_1 == 1'b1) begin
gnt_1 <= 1;
state <= #1 GNT0;
end else begin
state <= #1 IDLE;
end
GNT0:
if (req_0 == 1'b1) begin
state <= #1 GNT0;
end else begin
gnt_0 <= 0;
state <= #1 IDLE;
end
GNT1:
if (req_1 == 1'b1) begin
state <= #1 GNT2;
gnt_1 <= req_0;
end
GNT2:
if (req_0 == 1'b1) begin
state <= #1 GNT1;
gnt_1 <= req_1;
end
default: state <= #1 IDLE;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 5; struct node { int vl, mnvl; node *l, *r; node() { mnvl = MAXN; vl = -1; l = r = NULL; } }; vector<node*> dv(MAXN); vector<bool> inarr(MAXN, false); vector<vector<int>> diverse(MAXN); deque<int> dbl(int a) { deque<int> d; while (a != 0) d.push_front(a % 2), a /= 2; while (d.size() != 18) d.push_front(0); return d; } void ins(node* d, deque<int> a, int n) { while (!a.empty()) { d->mnvl = min(d->mnvl, n); int b = a.front(); a.pop_front(); if (b == 0) { if (d->l == NULL) d->l = new node(); d = d->l; } else { if (d->r == NULL) d->r = new node(); d = d->r; } } d->vl = n; d->mnvl = min(d->mnvl, n); } int fnd(node* d, deque<int> xd, int s, int x) { while (!xd.empty()) { int xx = xd.front(); xd.pop_front(); if (xx == 0) if (d->r != NULL && d->r->mnvl + x <= s) d = d->r; else if (d->l != NULL && d->l->mnvl + x <= s) d = d->l; else return -1; else if (d->l != NULL && d->l->mnvl + x <= s) d = d->l; else if (d->r != NULL && d->r->mnvl + x <= s) d = d->r; else return -1; } return d->vl; } int main() { for (int i = 1; i < MAXN; i++) for (int j = i; j < MAXN; j += i) diverse[j].push_back(i); for (int i = 1; i < dv.size(); i++) dv[i] = new node(); int n, q, a, x, k, s; cin >> n; for (int i = 0; i < n; i++) { cin >> q; if (q == 1) { cin >> a; if (!inarr[a]) { inarr[a] = true; deque<int> d = dbl(a); for (int i = 0; i < diverse[a].size(); i++) ins(dv[diverse[a][i]], d, a); } } else { cin >> x >> k >> s; if (x % k != 0 || s - x <= 0) cout << -1 << endl; else cout << fnd(dv[k], dbl(x), s, x) << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int h, m, ti; scanf( %d:%d , &h, &m); scanf( %d , &ti); int realh = ti / 60, realmin = ti % 60; while (realh--) { if (h == 23) h = 0; else h++; } while (realmin--) { if (m == 59) { m = 0; if (h == 23) h = 0; else h++; } else m++; } if (h < 10) printf( 0 ); printf( %d: , h); if (m < 10) printf( 0 ); printf( %d , m); return 0; } |
// ==========================================================================
// CRC Generation Unit - Linear Feedback Shift Register implementation
// (c) Kay Gorontzi, GHSi.de, distributed under the terms of LGPL
// ==========================================================================
module sd_crc_16(BITVAL, ENABLE, BITSTRB, CLEAR, CRC);
input BITVAL; // Next input bit
input ENABLE; // Enable calculation
input BITSTRB; // Current bit valid (Clock)
input CLEAR; // Init CRC value
output [15:0] CRC; // Current output CRC value
reg [15:0] CRC; // We need output registers
wire inv;
assign inv = BITVAL ^ CRC[15]; // XOR required?
always @(posedge BITSTRB or posedge CLEAR) begin
if (CLEAR) begin
CRC <= 0; // Init before calculation
end
else begin
if (ENABLE == 1) begin
CRC[15] <= CRC[14];
CRC[14] <= CRC[13];
CRC[13] <= CRC[12];
CRC[12] <= CRC[11] ^ inv;
CRC[11] <= CRC[10];
CRC[10] <= CRC[9];
CRC[9] <= CRC[8];
CRC[8] <= CRC[7];
CRC[7] <= CRC[6];
CRC[6] <= CRC[5];
CRC[5] <= CRC[4] ^ inv;
CRC[4] <= CRC[3];
CRC[3] <= CRC[2];
CRC[2] <= CRC[1];
CRC[1] <= CRC[0];
CRC[0] <= inv;
end
end
end
endmodule |
// -----------------------------------------------------------------------
//
// Copyright 2004,2007-2008 Tommy Thorn - All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, Inc., 53 Temple Place Ste 330,
// Bostom MA 02111-1307, USA; either version 2 of the License, or
// (at your option) any later version; incorporated herein by reference.
//
// -----------------------------------------------------------------------
`timescale 1ns/10ps
module rs232in
(// Control
input wire clock,
// Serial line
input wire serial_in,
output reg attention = 0,
output reg [7:0] received_data = 0);
parameter bps = 57_600;
parameter frequency = 25_000_000;
parameter period = (frequency + bps/2) / bps;
reg [16:0] ttyclk = 0;
wire [31:0] ttyclk_bit = period - 2;
wire [31:0] ttyclk_start = (3 * period) / 2 - 2;
reg [ 7:0] shift_in = 0;
reg [ 4:0] count = 0;
reg rxd = 0;
reg rxd2 = 0;
/*
* The theory: look for a negedge, then wait 1.5 bit period to skip
* start bit and center in first bit. Keep shifting bits until a full
* byte is collected.
*
* Start Stop
* data ~\__ B0 B1 B2 B3 B4 B5 B6 B7 ~~
* count 8 7 6 5 4 3 2 1
*/
always @(posedge clock) begin
attention <= 0;
// Get rid of meta stability.
{rxd2,rxd} <= {rxd,serial_in};
if (~ttyclk[16]) begin
ttyclk <= ttyclk - 1'd1;
end else if (count) begin
if (count == 1) begin
received_data <= {rxd2, shift_in[7:1]};
attention <= 1;
end
count <= count - 1'd1;
shift_in <= {rxd2, shift_in[7:1]}; // Shift in from the left
ttyclk <= ttyclk_bit[16:0];
end else if (~rxd2) begin
// Just saw the negedge of the start bit
ttyclk <= ttyclk_start[16:0];
count <= 8;
end
end
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps / 1ps
`include "utils/clock_multiplier.v"
`include "utils/DCM_sim.v"
`include "utils/IDDR_sim.v"
`include "utils/ddr_des.v"
`include "seq_gen/seq_gen.v"
`include "seq_gen/seq_gen_core.v"
`include "tdc_s3/tdc_s3_core.v"
`include "tdc_s3/tdc_s3.v"
`include "bram_fifo/bram_fifo_core.v"
`include "bram_fifo/bram_fifo.v"
`include "utils/bus_to_ip.v"
`include "utils/cdc_syncfifo.v"
`include "utils/cdc_pulse_sync.v"
`include "utils/flag_domain_crossing.v"
`include "utils/generic_fifo.v"
`include "utils/3_stage_synchronizer.v"
module tb (
input wire BUS_CLK,
input wire BUS_RST,
input wire [31:0] BUS_ADD,
inout wire [31:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
output wire BUS_BYTE_ACCESS
);
localparam SEQ_GEN_BASEADDR = 32'h0000;
localparam SEQ_GEN_HIGHADDR = 32'h8000 - 1;
localparam TDC_BASEADDR = 32'h8000;
localparam TDC_HIGHADDR = 32'h8100 - 1;
localparam FIFO_BASEADDR = 32'h8100;
localparam FIFO_HIGHADDR = 32'h8200 - 1;
localparam FIFO_BASEADDR_DATA = 32'h8000_0000;
localparam FIFO_HIGHADDR_DATA = 32'h9000_0000;
localparam ABUSWIDTH = 32;
assign BUS_BYTE_ACCESS = BUS_ADD < 32'h8000_0000 ? 1'b1 : 1'b0;
wire TDC_TRIGGER_IN, TDC_IN, TDC_ARM, TDC_EXT_EN;
wire [3:0] NOT_CONNECTED;
wire [7:0] SEQ_OUT;
assign NOT_CONNECTED = SEQ_OUT[7:4];
assign TDC_TRIGGER_IN = SEQ_OUT[0];
assign TDC_IN = SEQ_OUT[1];
assign TDC_ARM = SEQ_OUT[2];
assign TDC_EXT_EN = SEQ_OUT[3];
wire CLK_40, CLK_160, CLK_320, CLK_320_TO_DCM, CLK_640;
DCM #(
.CLKFX_MULTIPLY(40),
.CLKFX_DIVIDE(3)
) i_dcm_1 (
.CLK0(), .CLK180(), .CLK270(), .CLK2X(), .CLK2X180(), .CLK90(),
.CLKDV(), .CLKFX(CLK_320_TO_DCM), .CLKFX180(), .LOCKED(), .PSDONE(), .STATUS(),
.CLKFB(1'b0), .CLKIN(BUS_CLK), .DSSEN(1'b0), .PSCLK(1'b0), .PSEN(1'b0), .PSINCDEC(1'b0), .RST(1'b0)
);
DCM #(
.CLKFX_MULTIPLY(1),
.CLKFX_DIVIDE(2),
.CLKDV_DIVIDE(8)
) i_dcm_2 (
.CLK0(CLK_320), .CLK180(), .CLK270(), .CLK2X(CLK_640), .CLK2X180(), .CLK90(),
.CLKDV(CLK_40), .CLKFX(CLK_160), .CLKFX180(), .LOCKED(), .PSDONE(), .STATUS(),
.CLKFB(1'b0), .CLKIN(CLK_320_TO_DCM), .DSSEN(1'b0), .PSCLK(1'b0), .PSEN(1'b0), .PSINCDEC(1'b0), .RST(1'b0)
);
seq_gen #(
.BASEADDR(SEQ_GEN_BASEADDR),
.HIGHADDR(SEQ_GEN_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.MEM_BYTES(8 * 8 * 1024 - 1),
.OUT_BITS(8)
) i_seq_gen (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.SEQ_EXT_START(),
.SEQ_CLK(CLK_640),
.SEQ_OUT(SEQ_OUT)
);
wire TDC_FIFO_READ;
wire TDC_FIFO_EMPTY;
wire [31:0] TDC_FIFO_DATA;
wire FIFO_FULL;
wire ACKNOWLEDGE;
tdc_s3 #(
.BASEADDR(TDC_BASEADDR),
.HIGHADDR(TDC_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.CLKDV(4),
.DATA_IDENTIFIER(4'b0000),
.FAST_TDC(1),
.FAST_TRIGGER(1)
) i_tdc (
.CLK320(CLK_320),
.CLK160(CLK_160),
.DV_CLK(CLK_40),
.TDC_IN(TDC_IN),
.TDC_OUT(),
.TRIG_IN(TDC_TRIGGER_IN),
.TRIG_OUT(),
.FIFO_READ(TDC_FIFO_READ),
.FIFO_EMPTY(TDC_FIFO_EMPTY),
.FIFO_DATA(TDC_FIFO_DATA),
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.ARM_TDC(TDC_ARM),
.EXT_EN(TDC_EXT_EN),
.TIMESTAMP(16'b0)
);
wire FIFO_READ, FIFO_EMPTY;
wire [31:0] FIFO_DATA;
assign FIFO_DATA = TDC_FIFO_DATA;
assign FIFO_EMPTY = TDC_FIFO_EMPTY;
assign TDC_FIFO_READ = FIFO_READ;
bram_fifo #(
.BASEADDR(FIFO_BASEADDR),
.HIGHADDR(FIFO_HIGHADDR),
.BASEADDR_DATA(FIFO_BASEADDR_DATA),
.HIGHADDR_DATA(FIFO_HIGHADDR_DATA),
.ABUSWIDTH(ABUSWIDTH)
) i_out_fifo (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.FIFO_READ_NEXT_OUT(FIFO_READ),
.FIFO_EMPTY_IN(FIFO_EMPTY),
.FIFO_DATA(FIFO_DATA),
.FIFO_NOT_EMPTY(),
.FIFO_FULL(FIFO_FULL),
.FIFO_NEAR_FULL(),
.FIFO_READ_ERROR()
);
initial begin
$dumpfile("tdc.vcd");
$dumpvars(0);
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Outputs
ign,
// Inputs
clk
);
input clk;
output [31:0] ign;
reg [31:0] right;
reg [31:0] left;
reg [63:0] qright;
reg [63:0] qleft;
reg [31:0] amt;
assign ign = {31'h0, clk} >>> 4'bx; // bug760
always @* begin
right = 32'h819b018a >> amt;
left = 32'h819b018a << amt;
qright = 64'hf784bf8f_12734089 >> amt;
qleft = 64'hf784bf8f_12734089 >> amt;
end
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("%d %x %x %x %x\n", cyc, left, right, qleft, qright);
`endif
if (cyc==1) begin
amt <= 32'd0;
if (5'b10110>>2 != 5'b00101) $stop;
if (5'b10110>>>2 != 5'b00101) $stop; // Note it cares about sign-ness
if (5'b10110<<2 != 5'b11000) $stop;
if (5'b10110<<<2 != 5'b11000) $stop;
if (5'sb10110>>2 != 5'sb00101) $stop;
if (5'sb10110>>>2 != 5'sb11101) $stop;
if (5'sb10110<<2 != 5'sb11000) $stop;
if (5'sb10110<<<2 != 5'sb11000) $stop;
// Allow >64 bit shifts if the shift amount is a constant
if ((64'sh458c2de282e30f8b >> 68'sh4) !== 64'sh0458c2de282e30f8) $stop;
end
if (cyc==2) begin
amt <= 32'd28;
if (left != 32'h819b018a) $stop;
if (right != 32'h819b018a) $stop;
if (qleft != 64'hf784bf8f_12734089) $stop;
if (qright != 64'hf784bf8f_12734089) $stop;
end
if (cyc==3) begin
amt <= 32'd31;
if (left != 32'ha0000000) $stop;
if (right != 32'h8) $stop;
if (qleft != 64'h0000000f784bf8f1) $stop;
if (qright != 64'h0000000f784bf8f1) $stop;
end
if (cyc==4) begin
amt <= 32'd32;
if (left != 32'h0) $stop;
if (right != 32'h1) $stop;
if (qleft != 64'h00000001ef097f1e) $stop;
if (qright != 64'h00000001ef097f1e) $stop;
end
if (cyc==5) begin
amt <= 32'd33;
if (left != 32'h0) $stop;
if (right != 32'h0) $stop;
if (qleft != 64'h00000000f784bf8f) $stop;
if (qright != 64'h00000000f784bf8f) $stop;
end
if (cyc==6) begin
amt <= 32'd64;
if (left != 32'h0) $stop;
if (right != 32'h0) $stop;
if (qleft != 64'h000000007bc25fc7) $stop;
if (qright != 64'h000000007bc25fc7) $stop;
end
if (cyc==7) begin
amt <= 32'd128;
if (left != 32'h0) $stop;
if (right != 32'h0) $stop;
if (qleft != 64'h0) $stop;
if (qright != 64'h0) $stop;
end
if (cyc==8) begin
if (left != 32'h0) $stop;
if (right != 32'h0) $stop;
if (qleft != 64'h0) $stop;
if (qright != 64'h0) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O32AI_0_V
`define SKY130_FD_SC_LP__O32AI_0_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32ai with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o32ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o32ai_0 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o32ai_0 (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O32AI_0_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A31O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__A31O_FUNCTIONAL_PP_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__a31o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A31O_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int mod = 1e8 - 3; struct Data { int a, i; bool operator<(const Data& d) const { if (a == d.a) { return i < d.i; } return a < d.a; } }; const int N = 1e5 + 10; int C[N]; int lowbit(int first) { return first & -first; } void update(int first, int k) { while (first < N) { C[first] += k; first += lowbit(first); } } int query(int first) { int sum = 0; while (first > 0) { sum += C[first]; first -= lowbit(first); } return sum; } int main() { int n; cin >> n; vector<Data> a(n), b(n); for (int i = 0; i < n; i++) { cin >> a[i].a; a[i].i = i; } for (int i = 0; i < n; i++) { b[i].a = b[i].i = i; } sort(a.begin(), a.end()); sort(b.begin(), b.end()); vector<int> c(n); for (int i = 0; i < n; i++) { c[b[i].i] = a[i].i; } vector<pair<int, int> > res; for (int it = 0; it < n; it++) { for (int i = 0; i < n - 1; i++) { if (c[i] > c[i + 1]) { res.push_back({c[i + 1], c[i]}); swap(c[i], c[i + 1]); } } } cout << res.size() << endl; for (auto& p : res) { cout << p.first + 1 << << p.second + 1 << endl; } } |
#include <bits/stdc++.h> using namespace std; vector<int> e[100005]; int used[100005]; void bfs(int x) { queue<int> q; while (!q.empty()) q.pop(); q.push(x); used[x] = 1; while (!q.empty()) { int p = q.front(); q.pop(); for (int i = 0; i < e[p].size(); i++) { if (e[p][i]) { if (!used[e[p][i]]) { if (used[p] == 1) used[e[p][i]] = 2; else used[e[p][i]] = 1; q.push(e[p][i]); } } } } } int main() { int n, x, y; while (~scanf( %d , &n)) { for (int i = 0; i < n - 1; i++) { scanf( %d%d , &x, &y); e[x].push_back(y); e[y].push_back(x); } memset(used, 0, sizeof(used)); bfs(1); long long ans1 = 0, ans2 = 0; for (int i = 1; i <= n; i++) { if (used[i] == 1) ans1++; else ans2++; } printf( %I64d n , ans2 * ans1 - (n - 1)); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main(void) { unsigned long num_bottles = 0; cin >> num_bottles; map<unsigned long, pair<unsigned long, unsigned long> > links; map<unsigned long, unsigned long> counts; for (unsigned long n = 0; n < num_bottles; n++) { unsigned long a = 0, b = 0; cin >> a >> b; counts[a]++; links[a]; if (a == b) { links[b].second++; } else { links[b].first++; } } unsigned long unopened = 0; for (map<unsigned long, pair<unsigned long, unsigned long> >::iterator links_it = links.begin(); links_it != links.end(); ++links_it) { unsigned long bottle = links_it->first; unsigned long from_outside = links_it->second.first; unsigned long from_within = links_it->second.second; if (from_outside > 0) continue; if (from_within > 1) continue; if (from_within == 1) { unopened++; continue; } unopened += counts[bottle]; } cout << unopened; return 0; } |
`include "../../../../../vpr/muxes/logic/mux8/mux8.sim.v"
`include "../nreg/reg.sim.v"
`include "carryin_mux/carryin_mux.sim.v"
module CARRYINSEL_LOGIC (CARRYIN, CARRYCASCIN, CARRYCASCOUT, A, B, P, PCIN, CARRYINSEL, CIN,
RSTALLCARRYIN, CECARRYIN, CEM, CLK);
parameter MREG = 1;
parameter CARRYINREG = 1;
input wire CARRYIN;
input wire CARRYCASCIN;
input wire CARRYCASCOUT;
input wire [24:0] A;
input wire [17:0] B;
input wire [47:0] P;
input wire [47:0] PCIN;
input wire [2:0] CARRYINSEL;
output wire CIN;
input wire RSTALLCARRYIN;
input wire CECARRYIN;
input wire CEM;
input wire CLK;
`ifndef PB_TYPE
wire ROUND;
wire ROUND_REG;
wire ROUND_MUX_OUT;
assign ROUND = A[24] ~^ B[17];
REG round_reg (.D(ROUND), .Q(ROUND_REG), .CE(CEM), .CLK(CLK), .RESET(RSTALLCARRYIN));
// TODO(elms): not sure if the select is correct: "signal can be optionally registered to match the MREG pipeline delay"
CARRYIN_MUX #(.S(MREG)) round_mux (.BYPASS(ROUND), .REG(ROUND_REG), .O(ROUND_MUX_OUT));
wire CARRYIN_REG;
wire CARRYIN_MUX_OUT;
REG carryin_reg (.D(CARRYIN), .Q(CARRYIN_REG), .CE(CECARRYIN), .CLK(CLK), .RESET(RSTALLCARRYIN));
CARRYIN_MUX #(.S(CARRYINREG)) carryin_mux (.BYPASS(CARRYIN), .REG(CARRYIN_REG), .O(CARRYIN_MUX_OUT));
MUX8 carryinsel_mux (.I0(CARRYIN_MUX_OUT), .I1(~PCIN[47]), .I2(CARRYCASCIN), .I3(PCIN[47]), .I4(CARRYCASCOUT), .I5(~P[47]), .I6(ROUND_MUX_OUT), .I7(P[47]),
.S0(CARRYINSEL[0]), .S1(CARRYINSEL[1]), .S2(CARRYINSEL[2]), .O(CIN));
`endif // `ifndef PB_TYPE
endmodule // CARRYINSEL_LOGIC
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR2B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__NOR2B_BEHAVIORAL_PP_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__nor2b (
Y ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A );
and and0 (and0_out_Y , not0_out, B_N );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR2B_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; class wwj { public: wwj(int x); int klz(); int pdly(int k); private: int x; }; wwj::wwj(int x) { this->x = x; } int wwj::klz() { int i, sum = 0; double SM = 0; if (x == 0) return 0; SM = (-1 + sqrt(1.0 + 8 * abs(x))) / 2; if (int(SM) == SM) i = int(SM); else i = int(SM + 1); while (1) { if (pdly(i)) return i; else ++i; } } int wwj::pdly(int k) { int s; s = k * (1 + k) / 2; x = abs(x); if (x % 2 == s % 2) return 1; return 0; } int main() { int x; cin >> x; wwj LR(x); cout << LR.klz() << endl; ; } |
#include <bits/stdc++.h> using namespace std; bool r[1010], c[1010]; int main() { int n, m; cin >> n >> m; for (int i = 0; i < m; i++) { int a, b; cin >> a >> b; a--; b--; r[a] = 1; c[b] = 1; } int ans = 0; for (int i = 1; i < n - 1; i++) { if (!c[i]) ans++; if (!r[i]) ans++; if (!c[i] && !r[i] && !c[n - i] && !r[n - i] && (n - 1 - i) == i) ans--; } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; long long lgput(long long a, long long b, long long mod) { long long ret = 1; while (b) { if (b & 1) ret = (ret * a) % mod; a = (a * a) % mod; b >>= 1; } return (ret % mod); } inline long long inv(long long x, long long MOD) { return lgput(x, MOD - 2, MOD); } const long double PI = acos(-1); const long double eps = 1e-6; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cout.precision(12); cout.fixed; int n; cin >> n; vector<int> a(n); vector<int> b(n); for (int i = 0; i < n; ++i) cin >> a[i] >> b[i]; vector<int> order(n); for (int i = 0; i < n; ++i) order[i] = i; sort(order.begin(), order.end(), [&](int i, int j) -> bool { return a[i] + b[j] > a[j] + b[i]; }); long long ret = 0; for (int i = 0; i < n; ++i) { ret += 1ll * i * a[order[i]] + 1ll * (n - 1 - i) * b[order[i]]; } cout << ret << n ; return 0; } |
`ifdef __ICARUS__
`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
`endif
// Test array variables inside a constant function
module constfunc14();
function [7:0] concat1(input [7:0] value);
reg [3:0] tmp[1:2];
begin
{tmp[1], tmp[2]} = {value[3:0], value[7:4]};
{concat1[3:0], concat1[7:4]} = {tmp[2], tmp[1]};
end
endfunction
function [7:0] concat2(input [7:0] value);
reg [3:0] tmp[1:2];
begin
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
{tmp[1], tmp[3]} = {value[3:0], value[7:4]};
{concat2[3:0], concat2[7:4]} = {tmp[3], tmp[1]};
`else
{tmp[1]} = {value[3:0]};
{concat2[3:0], concat2[7:4]} = {4'bxxxx, tmp[1]};
`endif
end
endfunction
function [7:0] concat3(input [7:0] value);
reg [3:0] tmp[1:2];
begin
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
{tmp['bx], tmp[1]} = {value[3:0], value[7:4]};
{concat3[3:0], concat3[7:4]} = {tmp['bx], tmp[1]};
`else
{tmp[1]} = {value[7:4]};
{concat3[3:0], concat3[7:4]} = {4'bxxxx, tmp[1]};
`endif
end
endfunction
localparam res1 = concat1(8'ha5);
localparam res2 = concat2(8'ha5);
localparam res3 = concat2(8'ha5);
reg failed = 0;
initial begin
$display("%h", res1); if (res1 !== 8'h5a) failed = 1;
$display("%h", res2); if (res2 !== 8'h5x) failed = 1;
$display("%h", res3); if (res3 !== 8'h5x) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR2B_BLACKBOX_V
`define SKY130_FD_SC_HS__OR2B_BLACKBOX_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__or2b (
X ,
A ,
B_N
);
output X ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR2B_BLACKBOX_V
|
#include<bits/stdc++.h> using namespace std; #define forg(i,x) for(register int i=fir[x];i;i=nxt[i]) #define uu unsigned #define scanf a14=scanf #define rint register int #define fre(x) freopen(#x .in , r ,stdin),freopen(#x .out , w ,stdout) typedef long long ll; typedef uu long long ull; typedef pair<int,int>pii; int a14; inline int rd(int l,int r){return rand()%(r-l+1)+l;} const int mxn=1e5+3,sq=400,qs=320; int n,b[mxn],lp[mxn],rp[mxn],kn,be[mxn],po[mxn],qn; int ju[mxn/sq+2][mxn],ad[mxn/sq+2][mxn/qs+1]; int TG; struct shu{ int a[mxn],tg[mxn]; void add(int x){for(;x<=n;x+=x&-x){if(tg[x]!=TG)tg[x]=TG,a[x]=0;++a[x];}} int ask(int x){ int su=0,p=0; for(int i=1<<16;i;i>>=1){ if(p+i>=n)continue; p+=i;if(tg[p]!=TG)tg[p]=TG,a[p]=0; if(p+a[p]+su>=x)p-=i;else su+=a[p]; } return p+1; } void gb(int t){for(int i=1;i<=n;++i){if(tg[i]!=TG)a[i]=0;ju[t][i]=ju[t][i-(i&-i)]+a[i];}for(int i=1;i<=n;++i)ju[t][i]+=i;} }ar; void add2(int t,int x,int y){ int k=(x-1)/qs; for(int i=x;i<=(k+1)*qs;++i)ju[t][i]+=y; for(++k;k*qs+1<=n;++k)ad[t][k]+=y; } int main(){ //cout<<(sizeof(ju)>>20)<<endl; scanf( %d ,&n);for(int i=1;i<=n;++i)scanf( %d ,b+i),b[i]=i-b[i];scanf( %d ,&qn); for(int l=1,r;r!=n;l=r+1){r=min(l+sq-1,n);lp[++kn]=l,rp[kn]=r;for(int i=l;i<=r;++i)be[i]=kn;} for(int t=1;t<=kn;++t){ ++TG; for(int i=lp[t];i<=rp[t];++i)po[i]=ar.ask(b[i]),ar.add(po[i]); ar.gb(t); } while(qn--){ int o,x,y;scanf( %d%d ,&o,&x);if(o==1){ scanf( %d ,&y);b[x]=x-y;int k=be[x],ls; ++TG;for(int i=lp[k];i<=rp[k];++i){ if(i<x)ar.add(po[i]);else{ ls=po[i],po[i]=ar.ask(b[i]),ar.add(po[i]); if(ls==po[i])continue; if(ls==po[i]-1){--ju[k][ls];continue;} if(ls==po[i]+1){++ju[k][po[i]];continue;} assert(i==x); add2(k,ls,-1),add2(k,po[i],1); } } }else{ int t=be[x],re=b[x];for(int i=x+1;i<=rp[t];++i)re+=b[i]<=re; for(++t;t<=kn;++t)re=ju[t][re]+ad[t][(re-1)/qs]; printf( %d n ,re); } } return 0; } |
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