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#include<bits/stdc++.h> #define rep(i, a, n) for(int i = a; i <= n; i++) #define _rep(i, n, a) for(int i = n; i >= a; i--) typedef long long LL; using namespace std; const int maxn = 2e5 + 10; const int mod = 1004535809; inline LL read(){ LL x = 0, fl = 1; char c = getchar(); while (c < 0 || c > 9 ) { if(c == - ) fl = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = x * 10 + c - 0 ; c = getchar(); } return x * fl; } int n, m, t; LL cnt[maxn]; int main(){ cin >> t; while(t--){ cin >> n; memset(cnt, 0, (n + 5) * sizeof(LL)); int x; rep(i, 1, n) cin >> x, cnt[x]++; LL ans = 0; rep(i, 2, n - 1) ans += cnt[i - 1] * cnt[i] * cnt[i + 1]; rep(i, 1, n - 1) ans += cnt[i] * (cnt[i] - 1) / 2 * cnt[i + 1]; rep(i, 1, n - 1) ans += cnt[i] * cnt[i + 1] * (cnt[i + 1] - 1) / 2; rep(i, 1, n - 2) ans += cnt[i] * (cnt[i] - 1) / 2 * cnt[i + 2]; rep(i, 1, n - 2) ans += cnt[i] * cnt[i + 2] * (cnt[i + 2] - 1) / 2; rep(i, 1, n) ans += cnt[i] * (cnt[i] - 1) * (cnt[i] - 2) / 6; cout << ans << endl; } } |
#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 5; const double pi = acos(-1.0); const long long int inf = 0x3f3f3f3f3f3f3f3f; const long long int mod = 998244353; bool isPowerOfTwo(int x) { return x && (!(x & (x - 1))); } void fast() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); } string s[2]; int n, k, h; bool a[2][100005]; void dfs(int x, int y) { if (s[x][y] != - || a[x][y] == true || y < h) return; if (y + k >= n) { cout << YES ; exit(0); } h++; a[x][y] = true; dfs(1 - x, y + k); dfs(x, y + 1); dfs(x, y - 1); h--; } int main() { cin >> n >> k >> s[0] >> s[1]; dfs(0, 0); cout << NO ; return 0; } |
#include <bits/stdc++.h> using namespace std; int read() { register int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = 10 * x + ch - 0 ; ch = getchar(); } return x * f; } const int Size = 100005; int n, top; struct vec { double x, y; } w[Size], a[Size], O, stk[Size]; inline vec operator-(vec a, vec b) { return (vec){a.x - b.x, a.y - b.y}; } inline vec operator+(vec a, vec b) { return (vec){a.x + b.x, a.y + b.y}; } inline bool operator<(vec a, vec b) { if (a.x != b.x) return a.x < b.x; return a.y < b.y; } inline double Xji(vec p, vec q) { return p.x * q.y - p.y * q.x; } inline double dist(vec mhy) { return mhy.x * mhy.x + mhy.y * mhy.y; } inline bool comp(vec jzm, vec xjp) { double tmp = Xji(jzm, xjp); if (fabs(tmp) > 1e-6) return tmp > 1e-6; return dist(jzm) < dist(xjp); } inline double dist(vec mhy, vec zwt) { return sqrt((mhy.x - zwt.x) * (mhy.x - zwt.x) + (mhy.y - zwt.y) * (mhy.y - zwt.y)); } inline vec rotate(vec a, double rad) { return (vec){a.x * cos(rad) - a.y * sin(rad), a.x * sin(rad) + a.y * cos(rad)}; } int main() { n = read(); for (register int i = 1; i <= n; i++) { double x, y; scanf( %lf %lf , &x, &y); w[i].x = x; w[i].y = y - x * x; } vec O = w[1]; int id = 1; for (register int i = 2; i <= n; i++) { if (w[i] < O) { id = i; O = w[i]; } } swap(w[id], w[1]); for (register int i = 1; i <= n; i++) { a[i] = w[i] - O; } sort(a + 2, a + 1 + n, comp); for (register int i = 1; i <= n; i++) { while (top > 1 && Xji(stk[top] - stk[top - 1], a[i] - stk[top - 1]) <= 0) { top--; } stk[++top] = a[i]; } for (register int i = 1; i <= top; i++) { stk[i] = stk[i] + O; } int ans = 0; for (register int i = 1; i <= top; i++) { int pos = i % top + 1; if (stk[i].x > stk[pos].x) { ans++; } } printf( %d , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int oo = (int)1e9; const double eps = 1e-9; long long gcd(long long a, long long b); int main() { int n; long long maxi = 0, num, g; cin >> n; for (int i = 0; i < n; i++) { cin >> num; maxi = max(maxi, num); g = gcd(g, num); } if ((maxi / g - n) % 2) cout << Alice << endl; else cout << Bob << endl; } long long gcd(long long a, long long b) { if (b == 0) return a; else return gcd(b, a % b); } |
/*
* Wrapper for Xilinx MIG'd DDR2 controller, allowing 3 masters
* to contol the single interface.
*/
module xilinx_ddr2
(
// Inputs
input [31:0] wbm0_adr_i,
input [1:0] wbm0_bte_i,
input [2:0] wbm0_cti_i,
input wbm0_cyc_i,
input [31:0] wbm0_dat_i,
input [3:0] wbm0_sel_i,
input wbm0_stb_i,
input wbm0_we_i,
// Outputs
output wbm0_ack_o,
output wbm0_err_o,
output wbm0_rty_o,
output [31:0] wbm0_dat_o,
// Inputs
input [31:0] wbm1_adr_i,
input [1:0] wbm1_bte_i,
input [2:0] wbm1_cti_i,
input wbm1_cyc_i,
input [31:0] wbm1_dat_i,
input [3:0] wbm1_sel_i,
input wbm1_stb_i,
input wbm1_we_i,
// Outputs
output wbm1_ack_o,
output wbm1_err_o,
output wbm1_rty_o,
output [31:0] wbm1_dat_o,
// Inputs
input [31:0] wbm2_adr_i,
input [1:0] wbm2_bte_i,
input [2:0] wbm2_cti_i,
input wbm2_cyc_i,
input [31:0] wbm2_dat_i,
input [3:0] wbm2_sel_i,
input wbm2_stb_i,
input wbm2_we_i,
// Outputs
output wbm2_ack_o,
output wbm2_err_o,
output wbm2_rty_o,
output [31:0] wbm2_dat_o,
input wb_clk,
input wb_rst,
output [12:0] ddr2_a,
output [1:0] ddr2_ba,
output ddr2_ras_n,
output ddr2_cas_n,
output ddr2_we_n,
output [1:0] ddr2_cs_n,
output [1:0] ddr2_odt,
output [1:0] ddr2_cke,
output [7:0] ddr2_dm,
inout [63:0] ddr2_dq,
inout [7:0] ddr2_dqs,
inout [7:0] ddr2_dqs_n,
output [1:0] ddr2_ck,
output [1:0] ddr2_ck_n,
input ddr2_if_clk,
input clk200,
input ddr2_if_rst
, input sp_refresh_disable
);
// Internal wires to actual RAM
wire [31:0] wbs_ram_adr_i;
wire [1:0] wbs_ram_bte_i;
wire [2:0] wbs_ram_cti_i;
wire wbs_ram_cyc_i;
wire [31:0] wbs_ram_dat_i;
wire [3:0] wbs_ram_sel_i;
wire wbs_ram_stb_i;
wire wbs_ram_we_i;
wire wbs_ram_ack_o;
wire [31:0] wbs_ram_dat_o;
reg [2:0] input_select, last_selected;
wire arb_for_wbm0, arb_for_wbm1, arb_for_wbm2;
// Wires allowing selection of new input
assign arb_for_wbm0 = (last_selected[1] | last_selected[2] |
!wbm1_cyc_i | !wbm2_cyc_i) & !(|input_select);
assign arb_for_wbm1 = (last_selected[0] | last_selected[2] |
!wbm0_cyc_i | !wbm2_cyc_i) & !(|input_select);
assign arb_for_wbm2 = (last_selected[0] | last_selected[1] |
!wbm0_cyc_i | !wbm1_cyc_i) & !(|input_select);
// Master select logic
always @(posedge wb_clk)
if (wb_rst)
input_select <= 0;
else if ((input_select[0] & !wbm0_cyc_i) | (input_select[1] & !wbm1_cyc_i)
| (input_select[2] & !wbm2_cyc_i))
input_select <= 0;
else if (!(&input_select) & wbm0_cyc_i & arb_for_wbm0)
input_select <= 3'b001;
else if (!(&input_select) & wbm1_cyc_i & arb_for_wbm1)
input_select <= 3'b010;
else if (!(&input_select) & wbm2_cyc_i & arb_for_wbm2)
input_select <= 3'b100;
always @(posedge wb_clk)
if (wb_rst)
last_selected <= 0;
else if (!(&input_select) & wbm0_cyc_i & arb_for_wbm0)
last_selected <= 3'b001;
else if (!(&input_select) & wbm1_cyc_i & arb_for_wbm1)
last_selected <= 3'b010;
else if (!(&input_select) & wbm2_cyc_i & arb_for_wbm2)
last_selected <= 3'b100;
// Mux input signals to RAM (default to wbm0)
assign wbs_ram_adr_i = (input_select[2]) ? wbm2_adr_i :
(input_select[1]) ? wbm1_adr_i :
(input_select[0]) ? wbm0_adr_i : 0;
assign wbs_ram_bte_i = (input_select[2]) ? wbm2_bte_i :
(input_select[1]) ? wbm1_bte_i :
(input_select[0]) ? wbm0_bte_i : 0;
assign wbs_ram_cti_i = (input_select[2]) ? wbm2_cti_i :
(input_select[1]) ? wbm1_cti_i :
(input_select[0]) ? wbm0_cti_i : 0;
assign wbs_ram_cyc_i = (input_select[2]) ? wbm2_cyc_i :
(input_select[1]) ? wbm1_cyc_i :
(input_select[0]) ? wbm0_cyc_i : 0;
assign wbs_ram_dat_i = (input_select[2]) ? wbm2_dat_i :
(input_select[1]) ? wbm1_dat_i :
(input_select[0]) ? wbm0_dat_i : 0;
assign wbs_ram_sel_i = (input_select[2]) ? wbm2_sel_i :
(input_select[1]) ? wbm1_sel_i :
(input_select[0]) ? wbm0_sel_i : 0;
assign wbs_ram_stb_i = (input_select[2]) ? wbm2_stb_i :
(input_select[1]) ? wbm1_stb_i :
(input_select[0]) ? wbm0_stb_i : 0;
assign wbs_ram_we_i = (input_select[2]) ? wbm2_we_i :
(input_select[1]) ? wbm1_we_i :
(input_select[0]) ? wbm0_we_i : 0;
// Output from RAM, gate the ACK, ERR, RTY signals appropriately
assign wbm0_dat_o = wbs_ram_dat_o;
assign wbm0_ack_o = wbs_ram_ack_o & input_select[0];
assign wbm0_err_o = 0;
assign wbm0_rty_o = 0;
assign wbm1_dat_o = wbs_ram_dat_o;
assign wbm1_ack_o = wbs_ram_ack_o & input_select[1];
assign wbm1_err_o = 0;
assign wbm1_rty_o = 0;
assign wbm2_dat_o = wbs_ram_dat_o;
assign wbm2_ack_o = wbs_ram_ack_o & input_select[2];
assign wbm2_err_o = 0;
assign wbm2_rty_o = 0;
xilinx_ddr2_if xilinx_ddr2_if0
(
.wb_dat_o (wbs_ram_dat_o),
.wb_ack_o (wbs_ram_ack_o),
.wb_adr_i (wbs_ram_adr_i[31:0]),
.wb_stb_i (wbs_ram_stb_i),
.wb_cti_i (wbs_ram_cti_i),
.wb_bte_i (wbs_ram_bte_i),
.wb_cyc_i (wbs_ram_cyc_i),
.wb_we_i (wbs_ram_we_i),
.wb_sel_i (wbs_ram_sel_i[3:0]),
.wb_dat_i (wbs_ram_dat_i[31:0]),
.ddr2_a (ddr2_a[12:0]),
.ddr2_ba (ddr2_ba[1:0]),
.ddr2_ras_n (ddr2_ras_n),
.ddr2_cas_n (ddr2_cas_n),
.ddr2_we_n (ddr2_we_n),
.ddr2_cs_n (ddr2_cs_n),
.ddr2_odt (ddr2_odt),
.ddr2_cke (ddr2_cke),
.ddr2_dm (ddr2_dm[7:0]),
.ddr2_ck (ddr2_ck[1:0]),
.ddr2_ck_n (ddr2_ck_n[1:0]),
.ddr2_dq (ddr2_dq[63:0]),
.ddr2_dqs (ddr2_dqs[7:0]),
.ddr2_dqs_n (ddr2_dqs_n[7:0]),
.ddr2_if_clk (ddr2_if_clk),
.idly_clk_200 (clk200),
.ddr2_if_rst (ddr2_if_rst),
.wb_clk (wb_clk),
.wb_rst (wb_rst), .sp_refresh_disable(sp_refresh_disable));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxN = 5e5 + 10, mod = 1e9 + 7; int n, q, cnt; int nxt[maxN + 1], res[maxN + 1], ans[maxN + 1]; int pw[maxN + 1], id[maxN + 1], tp[maxN + 1]; int L[maxN + 1], R[maxN + 1], S[maxN + 1]; int stk[maxN + 1], top; int sum[maxN + 1], mn[maxN + 1][21], lg[maxN + 1]; char s[maxN + 1]; vector<int> pm[maxN + 1], pa[maxN + 1]; vector<int> son[maxN + 1], pre[maxN + 1], p0[maxN + 1]; inline int read() { int num = 0, f = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) f = -1; ch = getchar(); } while (isdigit(ch)) num = (num << 3) + (num << 1) + (ch ^ 48), ch = getchar(); return num * f; } inline void update(int &x, int y) { x = x + y >= mod ? x + y - mod : x + y; } inline int mpow(int a, int x) { int ans = 1; while (x) { if (x & 1) ans = 1ll * ans * a % mod; a = 1ll * a * a % mod; x >>= 1; } return ans; } inline int get_mn(int l, int r) { int k = lg[r - l + 1]; return min(mn[l][k], mn[r - (1 << k) + 1][k]); } inline bool check(int l, int r) { if (sum[r] != sum[l - 1]) return false; if (s[l] == * || s[l] == + ) return false; if (s[r] == * || s[r] == + ) return false; return get_mn(l, r) >= sum[r]; } inline int get_Mul(int l, int r) { int id = sum[r]; int x = lower_bound(pm[id].begin(), pm[id].end(), l) - pm[id].begin(); if (x == pm[id].size() || pm[id][x] > r) return -1; return pm[id][x]; } inline int get_Add(int l, int r) { int id = sum[r]; int x = lower_bound(pa[id].begin(), pa[id].end(), l) - pa[id].begin(); if (x == pa[id].size() || pa[id][x] > r) return -1; return pa[id][x]; } inline int build(int l, int r) { int node = ++cnt; L[node] = l, R[node] = r; while (s[l] == ( && nxt[l] == r) id[l++] = node, r--; int mid = get_Add(l, r); if (mid != -1) { tp[node] = 0; int x = l; while (mid != -1) { id[mid] = node; son[node].push_back(build(x, mid - 1)); x = mid + 1; mid = get_Add(x, r); } son[node].push_back(build(x, r)); int sum = 0; for (int i = 0; i < son[node].size(); i++) { update(sum, res[son[node][i]]); pre[node].push_back(sum); } return res[node] = sum, node; } mid = get_Mul(l, r); if (mid != -1) { tp[node] = 1; int x = l; while (mid != -1) { id[mid] = node; son[node].push_back(build(x, mid - 1)); x = mid + 1; mid = get_Mul(x, r); } son[node].push_back(build(x, r)); int sum = 1, tot = 0; for (int i = 0; i < son[node].size(); i++) { if (!res[son[node][i]]) tot++; else sum = 1ll * sum * res[son[node][i]] % mod; pre[node].push_back(sum); p0[node].push_back(tot); } return res[node] = tot ? 0 : sum, node; } tp[node] = 2; for (int i = l; i <= r; i++) res[node] = (10ll * res[node] % mod + s[i] - 0 ) % mod; return node; } inline int get(int l, int r) { int ans = S[r]; update(ans, mod - 1ll * S[l - 1] * pw[r - l + 1] % mod); return ans; } inline int findl(int node, int x) { int l = 0, r = son[node].size() - 1, ans = -1; while (l <= r) { int mid = (l + r) >> 1; if (L[son[node][mid]] < x) ans = mid, l = mid + 1; else r = mid - 1; } return ans; } inline int findr(int node, int x) { int l = 0, r = son[node].size() - 1, ans = son[node].size(); while (l <= r) { int mid = (l + r) >> 1; if (R[son[node][mid]] > x) ans = mid, r = mid - 1; else l = mid + 1; } return ans; } inline int query3(int node, int l, int r) { l = max(l, L[node]), r = min(r, R[node]); if (l > r) return 0; return get(l, r); } inline int query2(int node, int l, int r) { if (tp[node] == 2) return query3(node, l, r); l = max(l, L[node]), r = min(r, R[node]); if (l > r) return 0; int x = findl(node, l), y = findr(node, r); int ans = (y ? pre[node][y - 1] : 1), tot = (y ? p0[node][y - 1] : 0); if (x != -1) ans = 1ll * ans * mpow(pre[node][x], mod - 2) % mod, tot -= p0[node][x]; if (x != -1 && R[son[node][x]] >= l) ans = 1ll * ans * query3(son[node][x], l, r) % mod; if (y != son[node].size() && L[son[node][y]] <= r) ans = 1ll * ans * query3(son[node][y], l, r) % mod; return tot ? 0 : ans; } inline int query1(int node, int l, int r) { int x = findl(node, l), y = findr(node, r); int ans = (y ? pre[node][y - 1] : 0); if (x != -1) update(ans, mod - pre[node][x]); if (x != -1 && R[son[node][x]] >= l) update(ans, query2(son[node][x], l, r)); if (y != son[node].size() && L[son[node][y]] <= r) update(ans, query2(son[node][y], l, r)); return ans; } inline int solve(int l, int r) { if (s[l] == ( && nxt[l] == r) return res[id[l]]; int mid = get_Add(l, r); if (mid != -1) return query1(id[mid], l, r); mid = get_Mul(l, r); if (mid != -1) return query2(id[mid], l, r); return get(l, r); } int main() { scanf( %s , s + 1); n = strlen(s + 1); for (int i = 1; i <= n; i++) { sum[i] = sum[i - 1]; if (s[i] == ( ) sum[i]++, stk[++top] = i; if (s[i] == ) ) sum[i]--, nxt[stk[top--]] = i; } for (int i = 2; i <= n; i++) lg[i] = lg[i >> 1] + 1; for (int i = 1; i <= n; i++) mn[i][0] = sum[i]; for (int j = 1; (1 << j) <= n; j++) for (int i = 1; i + (1 << j) - 1 <= n; i++) mn[i][j] = min(mn[i][j - 1], mn[i + (1 << j - 1)][j - 1]); for (int i = 1; i <= n; i++) { if (s[i] == + ) pa[sum[i]].push_back(i); if (s[i] == * ) pm[sum[i]].push_back(i); } pw[0] = 1; for (int i = 1; i <= n; i++) pw[i] = 10ll * pw[i - 1] % mod; for (int i = 1; i <= n; i++) { S[i] = 10ll * S[i - 1] % mod; if (isdigit(s[i])) update(S[i], s[i] - 0 ); } build(1, n); q = read(); while (q--) { int l = read(), r = read(); if (!check(l, r)) { puts( -1 ); continue; } printf( %d n , solve(l, r)); } return 0; } |
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate release statement
//
// D: This code verifies the release statement.
// D: It depends on the force statement being
// D: functional! (Kinda have to - no way to
// D: release if you haven't forced the issue.
// D: It is intended to be self checking.
//
// By: Steve Wilson
//
module main ();
reg working;
reg timer;
initial
working = 1;
initial
begin
#5 ;
force working = 0;
end
initial
begin
#10;
release working; // This releases the force
#2 ;
working = 1; // This allows a new value onto the reg.
end
initial
begin
#20;
if(!working)
$display("FAILED\n");
else
$display("PASSED\n");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, lcnt; long long m, p, q; int a[100005], lsum[100005]; long long sum[100005], rmax[100005], lmin[100005], ls[100005]; long long ans1, ans2, ans; set<int> unu; inline long long Min(long long x, long long y) { return x < y ? x : y; } inline long long Max(long long x, long long y) { return x > y ? x : y; } inline int lowbit(int k) { return k & -k; } struct ta { long long t[100005]; void add(int k, long long x) { for (; k <= lcnt; k += lowbit(k)) t[k] += x; } inline long long query(int k) { long long ans = 0; for (; k; k -= lowbit(k)) ans += t[k]; return ans; } } tsum, tnum; struct ta2 { int t[100005]; void build() { for (int i = 1; i <= lcnt; i++) t[i] = n + 1; } void add(int k, int x) { for (; k <= lcnt; k += lowbit(k)) t[k] = Min(t[k], x); } inline int query(int k) { int ans = n + 1; for (; k; k -= lowbit(k)) ans = Min(ans, t[k]); return ans; } } tmin; struct subs { int l, r; long long w; bool operator>(const subs k) const { if (w != k.w) return w > k.w; else if (r != k.r) return r > k.r; else return l > k.l; } bool operator<(const subs k) const { if (w != k.w) return w < k.w; else if (r != k.r) return r < k.r; else return l < k.l; } bool operator==(const subs k) const { return (k.l == l) && (k.r == r) && (k.w == w); } bool operator!=(const subs k) const { return (k.l != l) || (k.r != r) || (k.w != w); } }; struct heap { subs h[100005]; int top; void pushdown(int k) { while ((k << 1) <= top) { int v = k << 1; if (v + 1 <= top) if (h[v | 1] > h[v]) v++; if (h[v] > h[k]) swap(h[v], h[k]); else break; k = v; } } void pushup(int k) { while (k > 1) { int v = k >> 1; if (h[v] < h[k]) swap(h[v], h[k]); else break; k = v; } } void push(subs k) { h[++top] = k; pushup(top); } void pop() { h[1] = h[top--]; pushdown(1); } } subsq; void del(int k); struct sg1 { bool b[400005]; void cover(int L, int R, int l, int r, int index) { if (L > R) return; if (b[index]) return; if (l == r) { del(l); b[index] = true; return; } if (L <= ((l + r) >> 1)) cover(L, R, l, ((l + r) >> 1), index << 1); if (R > ((l + r) >> 1)) cover(L, R, ((l + r) >> 1) + 1, r, index << 1 | 1); b[index] = b[index << 1] && b[index << 1 | 1]; } } s1; struct t { long long max[100005][17], min[100005][17]; int lo[100005]; void build(int l, int r, int index) { lo[1] = 0; for (int i = 2; i <= n; i++) if ((1 << (lo[i - 1] + 1)) == i) lo[i] = lo[i - 1] + 1; else lo[i] = lo[i - 1]; for (int i = 0; i <= n; i++) max[i][0] = min[i][0] = sum[i]; for (int i = 1; i <= lo[n]; i++) for (int j = 0; j + (1 << i) - 1 <= n; j++) max[j][i] = Max(max[j][i - 1], max[j + (1 << (i - 1))][i - 1]), min[j][i] = Min(min[j][i - 1], min[j + (1 << (i - 1))][i - 1]); } long long query(int l, int r) { int tmp = lo[r - l + 1]; return Max(max[l][tmp], max[r - (1 << tmp) + 1][tmp]) - Min(min[l][tmp], min[r - (1 << tmp) + 1][tmp]); } } s2; struct node3 { int l, r, s; }; struct sg3 { node3 t[4000005]; int root[100005], cnt; void ins(int &rt, int l, int r, int k) { if (rt == 0) rt = ++cnt; t[rt].s++; if (l == r) return; if (k <= ((l + r) >> 1)) ins(t[rt].l, l, ((l + r) >> 1), k); else ins(t[rt].r, ((l + r) >> 1) + 1, r, k); } void build() { for (int i = 0; i <= n; i++) ins(root[lsum[i]], 0, n, i); } inline int qsum(int rt, int l, int r, int k) { if (rt == 0) return 0; if (r == k) return t[rt].s; if (k <= ((l + r) >> 1)) return qsum(t[rt].l, l, ((l + r) >> 1), k); else return t[t[rt].l].s + qsum(t[rt].r, ((l + r) >> 1) + 1, r, k); } inline int query(int rt, int l, int r, int k) { if (l == r) return r; if (k <= t[t[rt].l].s) return query(t[rt].l, l, ((l + r) >> 1), k); else return query(t[rt].r, ((l + r) >> 1) + 1, r, k - t[t[rt].l].s); } } s3; struct sg4 { node3 t[4000005]; int cnt, root[100005]; void ins(int &rt, int Rt, int l, int r, int k) { rt = ++cnt; if (l == r) return; if (k <= ((l + r) >> 1)) { t[rt].r = t[Rt].r; ins(t[rt].l, t[Rt].l, l, ((l + r) >> 1), k); } else { t[rt].l = t[Rt].l; ins(t[rt].r, t[Rt].r, ((l + r) >> 1) + 1, r, k); } } void build() { ins(root[0], 0, 1, lcnt, lsum[0]); for (int i = 1; i <= n; i++) ins(root[i], root[i - 1], 1, lcnt, lsum[i]); } inline int query(int rt, int l, int r, int k) { if ((k > r) || (rt == 0)) return 0; if (l == r) return l; if (k > ((l + r) >> 1)) return query(t[rt].r, ((l + r) >> 1) + 1, r, k); else { int tmp = query(t[rt].l, l, ((l + r) >> 1), k); if (tmp) return tmp; else return query(t[rt].r, ((l + r) >> 1) + 1, r, k); } } } s4; struct splaynode { int l, r, size, fa; subs s; long long sum; }; struct Splay { splaynode t[100005]; int root, top, cnt, stack[100005]; inline int newnode() { return stack[top--]; } void pushup(int rt) { t[rt].size = t[t[rt].l].size + t[t[rt].r].size + 1; t[rt].sum = t[t[rt].l].sum + t[t[rt].r].sum + t[rt].s.w; } void rorate(int k, int i) { int tmp = t[k].fa; t[k].fa = t[tmp].fa; if (t[t[tmp].fa].l == tmp) t[t[tmp].fa].l = k; else t[t[tmp].fa].r = k; t[tmp].fa = k; if (i == 0) { if (t[k].l > 0) t[t[k].l].fa = tmp; t[tmp].r = t[k].l; t[k].l = tmp; } else { if (t[k].r > 0) t[t[k].r].fa = tmp; t[tmp].l = t[k].r; t[k].r = tmp; } pushup(tmp); pushup(k); } void splay(int k, int g) { while (t[k].fa != g) { int tmp = t[k].fa; if (t[tmp].fa == g) if (t[tmp].r == k) rorate(k, 0); else rorate(k, 1); else { int Tmp = t[tmp].fa; if (t[Tmp].l == tmp) { if (t[tmp].l == k) rorate(tmp, 1); else rorate(k, 0); rorate(k, 1); } else { if (t[tmp].r == k) rorate(tmp, 0); else rorate(k, 1); rorate(k, 0); } } } if (g == 0) root = k; } void build(int l, int r, int &rt) { rt = ++cnt; t[rt].s = (subs){((l + r) >> 1) + 1, ((l + r) >> 1), 0}; if (((l + r) >> 1) > l) { build(l, ((l + r) >> 1) - 1, t[rt].l); t[t[rt].l].fa = rt; } if (r > ((l + r) >> 1)) { build(((l + r) >> 1) + 1, r, t[rt].r); t[t[rt].r].fa = rt; } pushup(rt); } inline long long query(int k) { if (k > t[root].size) return -8333583335000000000ll; if (k == t[root].size) return t[root].sum; int p = root; while (t[t[p].r].size != k) { if (k < t[t[p].r].size) p = t[p].r; else k -= t[t[p].r].size + 1, p = t[p].l; } splay(p, 0); return t[t[p].r].sum; } void ins(subs k) { if (root == 0) { root = newnode(); t[root].l = t[root].r = t[root].fa = 0; t[root].s = k; pushup(root); return; } int p = root, v; while (true) { if (k < t[p].s) if (t[p].l) p = t[p].l; else { t[p].l = v = newnode(); break; } else if (t[p].r) p = t[p].r; else { t[p].r = v = newnode(); break; } } t[v].fa = p; t[v].l = t[v].r = 0; t[v].s = k; pushup(v); splay(v, 0); } void del(subs k) { if (t[root].size == 1) { root = 0; return; } int p = root; while (t[p].s != k) { if (k < t[p].s) p = t[p].l; else p = t[p].r; } splay(p, 0); int tmp = t[p].l; if (tmp == 0) { t[t[p].r].fa = 0; root = t[p].r; stack[++top] = p; return; } while (t[tmp].r) tmp = t[tmp].r; splay(tmp, root); t[tmp].fa = 0; root = tmp; if (t[p].r) t[t[p].r].fa = tmp, t[tmp].r = t[p].r; pushup(tmp); stack[++top] = p; } } s; inline long long read() { long long ret = 0, p = 1; char c = getchar(); while ((c < 0 ) || (c > 9 )) { if (c == - ) p = -1; c = getchar(); } while ((c >= 0 ) && (c <= 9 )) ret = (ret << 1) + (ret << 3) + c - 0 , c = getchar(); return ret * p; } inline int find(long long k) { int l = 0, r = lcnt + 1; while (r - l > 1) { if (ls[((l + r) >> 1)] > k) r = ((l + r) >> 1); else l = ((l + r) >> 1); } return l; } inline long long checknum(long long std) { long long ans = 0; for (int i = 0; i <= n; i++) { ans += tnum.query(find(sum[i] - std)); tnum.add(lsum[i], 1); } for (int i = 0; i <= n; i++) tnum.add(lsum[i], -1); return ans; } void del(int k) { set<int>::iterator p = unu.find(k), st = unu.begin(), ed = unu.end(); ed--; if (p != st) { set<int>::iterator pre = p; pre--; s.del((subs){(*pre) + 1, k - 1, s2.query((*pre), k - 1)}); } if (p != ed) { set<int>::iterator nex = p; nex++; s.del((subs){k + 1, (*nex) - 1, s2.query(k, (*nex) - 1)}); } if ((p != st) && (p != ed)) { set<int>::iterator pre = p, nex = p; pre--; nex++; s.ins((subs){(*pre) + 1, (*nex) - 1, s2.query((*pre), (*nex) - 1)}); } unu.erase(k); } inline subs Next(subs now) { int l = now.l, r = now.r, L, R = r; int tmp = s3.qsum(s3.root[lsum[l]], 0, n, l); if (tmp == 1) { int S = s4.query(s4.root[r - 1], 1, lcnt, lsum[l] + 1); if (S == 0) return (subs){0, R, -8333583335000000000ll}; int Sum = s3.qsum(s3.root[S], 0, n, r - 1); L = s3.query(s3.root[S], 0, n, Sum); } else L = s3.query(s3.root[lsum[l]], 0, n, tmp - 1); return (subs){L, R, sum[R] - sum[L]}; } inline long long checksum(long long std, long long rest) { long long ans = 0; tmin.build(); for (int i = 0; i <= n; i++) { int t = find(sum[i] - std); rest -= tnum.query(t); ans += tnum.query(t) * sum[i]; ans += tsum.query(t); s1.cover(tmin.query(t) + 1, i, 1, n, 1); tnum.add(lsum[i], 1); tsum.add(lsum[i], -sum[i]); tmin.add(lsum[i], i); } for (int i = 0; i <= n; i++) tnum.add(lsum[i], -1); std--; ans += rest * std; tnum.add(lsum[0], 1); for (int i = 1; i <= n; i++) { int Tmp = find(sum[i] - std); if (ls[Tmp] != sum[i] - std) { Tmp++; tnum.add(lsum[i], 1); int p = s4.query(s4.root[i - 1], 1, lcnt, Tmp); if (p == 0) continue; int L = s3.query(s3.root[p], 0, n, s3.qsum(s3.root[p], 0, n, i - 1)); subsq.push((subs){L, i, sum[i] - sum[L]}); } else { int tmp = tnum.query(Tmp) - tnum.query(Tmp - 1); tnum.add(lsum[i], 1); if (tmp == 0) { Tmp++; int p = s4.query(s4.root[i - 1], 1, lcnt, Tmp); if (p == 0) continue; int L = s3.query(s3.root[p], 0, n, s3.qsum(s3.root[p], 0, n, i - 1)); subsq.push((subs){L, i, sum[i] - sum[L]}); } else if (tmp <= rest) { int L = s3.query(s3.root[Tmp], 0, n, 1); s1.cover(L + 1, i, 1, n, 1); rest -= tmp; Tmp++; int p = s4.query(s4.root[i - 1], 1, lcnt, Tmp); if (p == 0) continue; L = s3.query(s3.root[p], 0, n, s3.qsum(s3.root[p], 0, n, i - 1)); subsq.push((subs){L, i, sum[i] - sum[L]}); } else { int L; if (rest) { L = s3.query(s3.root[Tmp], 0, n, tmp - rest + 1); s1.cover(L + 1, i, 1, n, 1); } L = s3.query(s3.root[Tmp], 0, n, tmp - rest); subsq.push((subs){L, i, sum[i] - sum[L]}); rest = 0; } } } return ans; } void upans2() { if (unu.empty()) { ans2 = -8333583335000000000ll; return; } ans2 = s.query(q - 1); if (ans2 == -8333583335000000000ll) return; set<int>::iterator p = unu.begin(); ans2 -= lmin[(*p) - 1]; p = unu.end(); p--; ans2 += rmax[(*p)]; } void work() { for (int i = 1; i <= n; i++) unu.insert(i); long long l = ls[1] - ls[lcnt] - 5, r = ls[lcnt] - ls[1] + 5; while (r - l > 1) { if (checknum(((l + r) >> 1)) >= p) l = ((l + r) >> 1); else r = ((l + r) >> 1); } ans1 = checksum(r, p); upans2(); if (ans2 > -8333583335000000000ll) ans = ans1 + ans2; else ans = -8333583335000000000ll; } void pre() { n = read(); m = read(); for (int i = 1; i <= n; i++) { a[i] = read(); ls[i] = sum[i] = sum[i - 1] + a[i]; } ls[n + 1] = 0; sort(ls + 1, ls + 2 + n); ls[0] = -8333583335000000000ll; for (int i = 1; i <= n + 1; i++) if (ls[i] != ls[i - 1]) ls[++lcnt] = ls[i]; for (int i = 0; i <= n; i++) lsum[i] = find(sum[i]); lmin[0] = sum[0]; for (int i = 1; i <= n; i++) lmin[i] = Min(lmin[i - 1], sum[i]); rmax[n] = sum[n]; for (int i = n - 1; i >= 0; i--) rmax[i] = Max(rmax[i + 1], sum[i]); s2.build(1, n - 1, 1); s3.build(); s4.build(); s.build(1, n - 1, s.root); if (m > n) p = m - n, q = n; else p = 0, q = m; work(); } void doit() { q--; p++; for (; q; q--, p++) { subs tmp = subsq.h[1], Tmp = Next(tmp); if (Tmp.w > -8333583335000000000ll) subsq.h[1] = Next(tmp), subsq.pushdown(1); else subsq.pop(); s1.cover(tmp.l + 1, tmp.r, 1, n, 1); ans1 += tmp.w; upans2(); if (ans2 > -8333583335000000000ll) ans = Max(ans, ans1 + ans2); } ans1 += subsq.h[1].w; s1.cover(subsq.h[1].l + 1, subsq.h[1].r, 1, n, 1); if (s1.b[1]) ans = ans1; printf( %I64d , ans); } int main() { pre(); doit(); } |
#include <bits/stdc++.h> const int INF_INT = 0x3f3f3f3f; const long long INF_LL = 0x7f7f7f7f; const int MOD = 1e9 + 7; const double eps = 1e-10; const double pi = acos(-1); using namespace std; const int N = 200010; long long n, k; long long fac[N], inv[N]; long long ksm(long long a, long long x, long long mod) { if (x == 0) return 1; long long ret = ksm(a, x / 2, mod); ret = ret * ret % mod; if (x & 1) ret = ret * a % mod; return ret; } void init() { fac[0] = 1; inv[0] = 1; for (long long i = 1; i < N; i++) { fac[i] = fac[i - 1] * i % MOD; inv[i] = ksm(fac[i], MOD - 2, MOD); } } map<int, int> mp; long long C(long long n, long long k) { long long ret = fac[n] * inv[k] % MOD; ret = ret * inv[n - k] % MOD; return ret; } int main(int argc, char const *argv[]) { init(); while (cin >> n >> k) { mp.clear(); for (int i = 1; i <= n; i++) { int l, r; scanf( %d%d , &l, &r); mp[l]++; mp[r + 1]--; } int last = mp.begin()->first; int tmp = 0; long long ans = 0; for (auto it = mp.begin(); it != mp.end(); it++) { long long num = it->first - last; if (tmp >= k) ans += C(tmp, k) * num % MOD; ans %= MOD; tmp += it->second; last = it->first; } cout << ans << endl; } return 0; } |
module mojo_top(
// 50MHz clock input
input wire clk,
// Input from reset button (active low)
input wire rst_n,
// cclk input from AVR, high when AVR is ready
input wire cclk,
// Outputs to the 8 onboard LEDs
output wire [7:0]led,
// AVR SPI connections
output wire spi_miso,
input wire spi_ss,
input wire spi_mosi,
input wire spi_sck,
// AVR ADC channel select
output wire [3:0] spi_channel,
// Serial connections
input wire avr_tx, // AVR Tx => FPGA Rx
output wire avr_rx, // AVR Rx => FPGA Tx
input wire avr_rx_busy, // AVR Rx buffer full
output wire i2c_scl,
inout wire i2c_sda,
output wire i2c_clk_in
);
wire reset = ~rst_n; // make reset active high
// these signals should be high-z when not used
assign spi_miso = 1'bz;
assign avr_rx = 1'bz;
assign spi_channel = 4'bzzzz;
assign led[5:0] = led_buffer;
assign led[7] = tick_1s;
assign led[6] = i2c_clk_in;
wire tick_1s;
//Generate a 1s timer
//timer #(.CTR_LEN(26)) second_timer (
timer #(.CTR_LEN(16)) second_timer (
.clk(clk),
.reset(reset),
.tick(tick_1s)
);
clk_divider #(.DIVIDER(500)) i2c_clk_divider (
.reset(reset),
.clk_in(clk),
.clk_out(i2c_clk_in)
);
wire i2c_start;
reg i2c_reset = 1'b1;
wire [7:0] i2c_nbytes;
wire [6:0] i2c_slave_addr;
wire i2c_rw;
wire [7:0] i2c_write_data;
wire [7:0] i2c_read_data;
wire i2c_tx_data_req;
wire i2c_rx_data_ready;
wire ready;
wire busy;
i2c_master i2c (
.clk(i2c_clk_in),
.reset(i2c_reset),
.start(i2c_start),
.nbytes_in(i2c_nbytes),
.addr_in(i2c_slave_addr),
.rw_in(i2c_rw),
.write_data(i2c_write_data),
.read_data(i2c_read_data),
.tx_data_req(i2c_tx_data_req),
.rx_data_ready(i2c_rx_data_ready),
.sda_w(i2c_sda),
.scl(i2c_scl)
);
wire [6:0] slave_addr = 7'b1010000;
reg [15:0] mem_addr;
wire [7:0] read_n_bytes = 8'd1;
wire [7:0] read_nbytes = 1;
reg start = 0;
wire [7:0] data_out;
wire byte_ready;
wire eeprom_busy;
read_eeprom instance_name (
.clk(clk),
.reset(reset),
.slave_addr_w(slave_addr),
.mem_addr_w(mem_addr),
.read_nbytes_w(read_nbytes),
.start(start),
.data_out(data_out),
.byte_ready(byte_ready),
.i2c_slave_addr(i2c_slave_addr),
.i2c_rw(i2c_rw),
.i2c_write_data(i2c_write_data),
.i2c_nbytes(i2c_nbytes),
.i2c_read_data(i2c_read_data),
.i2c_tx_data_req(i2c_tx_data_req),
.i2c_rx_data_ready(i2c_rx_data_ready),
.i2c_start(i2c_start),
.busy(eeprom_busy)
);
reg [5:0] led_buffer;
//every time a new byte is ready, write it to the LEDs
always @(posedge byte_ready) begin
led_buffer <= data_out[5:0];
end
reg measured_this_pulse;
always @(posedge clk) begin
if (reset == 1) begin
mem_addr <= 16'h0000;
measured_this_pulse <= 0;
end else begin
if ((tick_1s == 1) && (measured_this_pulse == 0)) begin
measured_this_pulse <= 1;
mem_addr <= mem_addr + 1'b1;
if (mem_addr > 8) begin
mem_addr <= 0;
end
start <= 1;
end //tick_1s==1
if ((start == 1) && (eeprom_busy == 1)) begin
start <= 0;
end //eeprom_busy and start
if (tick_1s == 0) begin
measured_this_pulse <= 0;
end //tick_1s==0
end //reset
end
//we need to make sure the i2c module is reset *after*
//it's clock has begun
always @(negedge i2c_clk_in) begin
if (reset == 1) begin
i2c_reset <= 1;
end else begin
i2c_reset <= 0;
end
end //posedge clk_i2c_in
endmodule |
#include <bits/stdc++.h> template <class T> inline bool rd(T &ret) { char c; int sgn; if (c = getchar(), c == EOF) return 0; while (c != - && (c < 0 || c > 9 )) c = getchar(); sgn = (c == - ) ? -1 : 1; ret = (c == - ) ? 0 : (c - 0 ); while (c = getchar(), c >= 0 && c <= 9 ) ret = ret * 10 + (c - 0 ); ret *= sgn; return 1; } template <class T> inline void pt(T x) { if (x < 0) { putchar( - ); x = -x; } if (x > 9) pt(x / 10); putchar(x % 10 + 0 ); } using namespace std; const long long N = 200050; long long n, m; struct node { long long op, l, r, num, id; } a[N * 2]; bool cmp(node x, node y) { if (x.r != y.r) return x.r < y.r; if (x.op != y.op) return x.op < y.op; } long long top, b[N]; void input() { top = 0; for (long long i = 1; i <= n; i++) { rd(a[top].l); rd(a[top].r); a[top].op = 0; a[top].id = i; top++; } rd(m); for (long long i = 1; i <= m; i++) { rd(a[top].l); rd(a[top].r); rd(a[top].num); a[top].op = 1; a[top].id = i; top++; } sort(a, a + top, cmp); } struct Edge { long long id, l; bool operator<(const Edge &e) const { if (e.l != l) return e.l > l; return e.id > id; } Edge(long long a = 0, long long b = 0) : id(a), l(b) {} } tmp; set<Edge> s; set<Edge>::iterator p; int main() { while (cin >> n) { input(); long long ans = 0; s.clear(); for (long long i = 0; i < top; i++) { if (a[i].op) { while (s.size() && a[i].num--) { p = s.lower_bound(Edge(0, a[i].l)); if (p == s.end()) break; tmp = *p; b[tmp.id] = a[i].id; s.erase(p); ans++; } } else { s.insert(Edge(a[i].id, a[i].l)); } } if (ans == n) { puts( YES ); for (long long i = 1; i <= n; i++) { pt(b[i]); putchar( ); } } else puts( NO ); } return 0; } |
#include <iostream> #include <algorithm> #include <vector> using namespace std; typedef vector<int> vi; int n,a[300010],res[300010],gtm[300010]; vi L,R,rm; void solve() { cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; L.assign(n,0); R.assign(n,0); rm.assign(n + 1, 0); L[0] = 0; for (int i = 1; i < n; i++) { if (a[i] > a[i - 1]) L[i] = i; else { int j = L[i - 1]; while (j > 0 && a[j - 1] >= a[i]) j = L[j - 1]; L[i] = j; } } R[n - 1] = n - 1; for (int i = n - 2; i >= 0; i--) { if (a[i] > a[i + 1]) R[i] = i; else { int j = R[i + 1]; while (j < n - 1 && a[j + 1] >= a[i]) j = R[j + 1]; R[i] = j; } } for (int i = 0; i < n; i++) { int x = R[i] - L[i] + 1; rm[a[i]] = max(rm[a[i]], x); } gtm[1] = rm[1]; for (int i = 2; i <= n; i++) { gtm[i] = min(gtm[i - 1], rm[i]); } for (int i = n; i >= 1; i--) { int k = n - i + 1; res[k] = (gtm[i] >= k); } for (int i = 1; i <= n; i++) cout << res[i]; cout << endl; } int main() { int t; cin >> t; while(t--) solve(); // system( pause ); return 0; } |
#include <bits/stdc++.h> using namespace std; const bool debug = 1; int xl = 1 << 30, xr = -(1 << 30), yl = 1 << 30, yr = -(1 << 30), zl = 1 << 30, zr = -(1 << 30); bool getpod(pair<int, int> p, int s) { int pzl = p.first - p.second - s; int pzr = p.first - p.second + s; int pxl = p.first - s; int pxr = p.first + s; int pyl = p.second - s; int pyr = p.second + s; if (pzl <= zl && pzr >= zr && pyl <= yl && pyr >= yr && pxl <= xl && pxr >= xr) return 1; return 0; } int main() { if (!debug) { cin.tie(0); cout.tie(0); ios::sync_with_stdio(0); } int n; cin >> n; vector<pair<int, int>> pt(n, {0, 0}); for (int i = 0; i < n; i++) { string s; cin >> s; for (int j = 0; j < s.size(); j++) if (s[j] == B ) pt[i].first++; else pt[i].second++; } for (int i = 0; i < n; i++) { xl = min(pt[i].first, xl); xr = max(pt[i].first, xr); yl = min(pt[i].second, yl); yr = max(pt[i].second, yr); zl = min(pt[i].first - pt[i].second, zl); zr = max(pt[i].first - pt[i].second, zr); } vector<pair<int, int>> p(12); vector<int> s(12); { int l = -1, r = 1 << 23; while (l + 1 < r) { int c = (l + r) / 2; pair<int, int> p = {zr + yl, yl + c}; if (getpod(p, c)) r = c; else l = c; } s[0] = r; p[0] = {zr + yl, yl + s[0]}; } { int l = -1, r = 1 << 23; while (l + 1 < r) { int c = (l + r) / 2; pair<int, int> p = {xl + c, xl - zl}; if (getpod(p, c)) r = c; else l = c; } s[1] = r; p[1] = {xl + s[1], xl - zl}; } { int l = -1, r = 1 << 23; while (l + 1 < r) { int c = (l + r) / 2; pair<int, int> p = {zl + yr, yr - c}; if (getpod(p, c)) r = c; else l = c; } s[2] = r; p[2] = {zl + yr, yr - s[2]}; } { int l = -1, r = 1 << 23; while (l + 1 < r) { int c = (l + r) / 2; pair<int, int> p = {xr - c, xr - zr}; if (getpod(p, c)) r = c; else l = c; } s[3] = r; p[3] = {xr - s[3], xr - zr}; } { int l = -1, r = 1 << 23; while (l + 1 < r) { int c = (l + r) / 2; pair<int, int> p = {xr - c, yr - c}; if (getpod(p, c)) r = c; else l = c; } s[4] = r; p[4] = {xr - s[4], yr - s[4]}; } { int l = -1, r = 1 << 23; while (l + 1 < r) { int c = (l + r) / 2; pair<int, int> p = {xl + c, yl + c}; if (getpod(p, c)) r = c; else l = c; } s[5] = r; p[5] = {xl + s[5], yl + s[5]}; } { int l = -1, r = zl - xl + yr; while (l + 1 < r) { int c = (l + r) / 2; pair<int, int> p = {xl + c, yr - c}; if (getpod(p, c)) r = c; else l = c; } s[6] = r; p[6] = {xl + s[6], yr - s[6]}; } { int l = -1, r = xr - yl - zr; while (l + 1 < r) { int c = (l + r) / 2; pair<int, int> p = {xr - c, yl + c}; if (getpod(p, c)) r = c; else l = c; } s[7] = r; p[7] = {xr - s[7], yl + s[7]}; } { int l = -1, r = xr - zl - yr; while (l + 1 < r) { int c = (l + r) / 2; pair<int, int> p = {xr - c, xr - zl - 2 * c}; if (getpod(p, c)) r = c; else l = c; } s[8] = r; p[8] = {xr - s[8], xr - zl - 2 * s[8]}; } { int l = -1, r = zr + yr - xr; while (l + 1 < r) { int c = (l + r) / 2; pair<int, int> p = {zr + yr - 2 * c, yr - c}; if (getpod(p, c)) r = c; else l = c; } s[9] = r; p[9] = {zr + yr - 2 * s[9], yr - s[9]}; } { int l = -1, r = yl + zr - xl; while (l + 1 < r) { int c = (l + r) / 2; pair<int, int> p = {xl + c, xl - zr + 2 * c}; if (getpod(p, c)) r = c; else l = c; } s[10] = r; p[10] = {xl + s[10], xl - zr + 2 * s[10]}; } { int l = -1, r = xl - zl - yl; while (l + 1 < r) { int c = (l + r) / 2; pair<int, int> p = {zl + yl + 2 * c, yl + c}; if (getpod(p, c)) r = c; else l = c; } s[11] = r; p[11] = {zl + yl + 2 * s[11], yl + s[11]}; } int iout = 0; for (int i = 0; i < 12; i++) if (s[i] < s[iout] && getpod(p[i], s[i])) iout = i; cout << s[iout] << n ; for (int i = 0; i < p[iout].first; i++) cout << B ; for (int i = 0; i < p[iout].second; i++) cout << N ; return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename Arg1, typename Arg2> ostream& operator<<(ostream& out, const pair<Arg1, Arg2>& x) { return out << ( << x.first << , << x.second << ) ; } template <typename Arg1> ostream& operator<<(ostream& out, const vector<Arg1>& a) { out << [ ; for (const auto& x : a) out << x << , ; return out << ] ; } template <typename Arg1> ostream& operator<<(ostream& out, const set<Arg1>& a) { out << [ ; for (const auto& x : a) out << x << , ; return out << ] ; } template <typename Arg1, typename Arg2> ostream& operator<<(ostream& out, const map<Arg1, Arg2>& a) { out << [ ; for (const auto& x : a) out << x << , ; return out << ] ; } template <typename Arg1> void __trace__(const string name, Arg1&& arg1) { cerr << name << : << arg1 << ] << endl; } template <typename Arg1, typename... Args> void __trace__(const string names, Arg1&& arg1, Args&&... args) { const string name = names.substr(0, names.find( , )); cerr << name << : << arg1 << | ; __trace__(names.substr(1 + (int)name.size()), args...); } clock_t time_p = clock(); void time_taken() { time_p = clock() - time_p; cerr << Time Taken : << (float)(time_p) / CLOCKS_PER_SEC << n ; } const long long mod = 1e9 + 7; const long long INF = 1e18; const int maxn = 2e5 + 5; vector<int> adj[maxn]; int Q[maxn]; int n; void bfs(int s, int* d) { for (int i = 1; i <= n; i++) { d[i] = -1; } d[s] = 0; int N = 0; Q[N++] = s; for (int i = 0; i < N; i++) { int u = Q[i]; for (int v : adj[u]) { if (d[v] == -1) { d[v] = d[u] + 1; Q[N++] = v; } } } } void solve() { int m, a, b, c; cin >> n >> m >> a >> b >> c; for (int i = 1; i <= n; i++) { adj[i].clear(); } vector<long long> p(m); for (int i = 0; i < m; i++) cin >> p[i]; sort(p.begin(), p.end()); for (int i = 1; i <= m - 1; i++) p[i] += p[i - 1]; for (int _ = 0; _ < m; _++) { int u, v; cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); } int da[n + 1], db[n + 1], dc[n + 1]; bfs(a, da); bfs(b, db); bfs(c, dc); if (a == b) { int foo = dc[a]; if (foo) { cout << p[foo - 1] << n ; } else { cout << 0 << n ; } return; } if (b == c) { int foo = da[b]; if (foo) { cout << p[foo - 1] << n ; } else { cout << 0 << n ; } return; } if (c == a) { int foo = da[b]; if (foo) { cout << 2 * p[foo - 1] << n ; } else { cout << 0 << n ; } return; } long long ans = INF; for (int i = 1; i <= n; i++) { long long cur = 0; int cnt = 0; long long foo = 0; if (db[i]) { foo = p[db[i] - 1]; cur += 2 * p[db[i] - 1]; } int tot = da[i] + db[i] + dc[i] - 1; if (tot < m) cur += p[tot] - foo; else continue; ans = min(ans, cur); } cout << ans << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cout.precision(12); cout << fixed; int t; cin >> t; while (t--) { solve(); } time_taken(); return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> inline void read(T &x) { x = 0; bool w = 1; char c = getchar(); while (!isdigit(c)) { if (c == - ) w = 0; c = getchar(); } while (isdigit(c)) { x = x * 10 + c - 0 ; c = getchar(); } x = w ? x : -x; } const long long N = 1e5 + 10, Mod = 1e9 + 7; long long n, m, a[N], lg[N], b[N], f[N], c[N], sum[N], d[N], ans[N]; struct en { long long l, r, id; bool operator<(const en &x) const { return r < x.r; } } q[N]; inline long long Get(long long x) { return f[x] ? f[x] = Get(f[x]) : x; } inline long long ji(long long x, long long y) { return (b[x] - b[y + 1] * lg[y - x + 1] % Mod + Mod) % Mod; } inline void add(long long x, long long y) { f[x] = y; c[y] = c[x]; if ((x - c[x] > 30 && sum[y] > 9) || (sum[x] + (sum[y] << x - c[x])) > Mod) sum[y] = Mod; else sum[y] = sum[x] + (sum[y] << x - c[x]); } signed main() { read(n), read(m); lg[0] = 1; for (long long i = 1; i <= n; i++) read(a[i]), sum[i] = a[i], lg[i] = (lg[i - 1] << 1) % Mod, c[i] = i - 1; for (long long i = 1; i <= m; i++) read(q[i].l), read(q[i].r), q[i].id = i; for (long long i = n; i >= 1; i--) b[i] = ((b[i + 1] << 1) + a[i] + Mod) % Mod; sort(q + 1, q + m + 1); long long k = 1; for (long long i = 1; i <= n; i++) { while (sum[i] >= 0 && c[i]) add(c[i], i); d[i] = (d[c[i]] + (ji(c[i] + 1, i) << 1) % Mod + Mod) % Mod; while (q[k].r == i) { long long x = Get(q[k].l); ans[q[k].id] = (d[i] - d[x] + ji(q[k].l, x) + Mod) % Mod; k++; } } for (long long i = 1; i <= m; i++) printf( %lld n , ans[i]); return 0; } |
#include <bits/stdc++.h> int n, d, m, t[200005][2], l, p, r, b; long long ans; std::pair<int, int> s[200005]; bool a = true; int main() { scanf( %d %d %d , &d, &n, &m); for (int i = 0; i < m; i++) scanf( %d %d , &s[i].first, &s[i].second); std::sort(s, s + m); t[l][0] = 0; t[l++][1] = n; s[m].first = d; s[m].second = 0; for (int i = 0; i <= m && a; i++) { if (s[i].first - p > n) a = false; else { r = s[i].first - p; while (s[i].first > p) { if (p + t[b][1] <= s[i].first) { ans += (long long)t[b][0] * t[b][1]; p += t[b][1]; b++; } else { ans += (long long)t[b][0] * (s[i].first - p); t[b][1] -= s[i].first - p; p = s[i].first; } } while (l > b && s[i].second <= t[l - 1][0]) r += t[--l][1]; t[l][0] = s[i].second; t[l++][1] = r; } } printf( %I64d n , a ? ans : -1); scanf( n ); return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> void in(T &x) { x = 0; bool f = 0; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = 1; c = getchar(); } while ( 0 <= c && c <= 9 ) { x = (x << 3) + (x << 1) + (c ^ 48); c = getchar(); } if (f) x = -x; } char tc[1000005]; int a[1000005], b[1000005]; int n, m; int sum[1000005][3][3]; signed main() { scanf( %s , tc + 1); n = strlen(tc + 1); for (register int i = 1; i <= n; ++i) a[i] = (tc[i] == R ? 0 : (tc[i] == G ? 1 : 2)); scanf( %s , tc + 1); m = strlen(tc + 1); for (register int i = 1; i <= m; ++i) b[i] = (tc[i] == R ? 0 : (tc[i] == G ? 1 : 2)); for (register int i = 2; i <= m; ++i) { for (register int j = 0; j < 3; ++j) for (register int k = 0; k < 3; ++k) sum[i][j][k] = sum[i - 1][j][k]; ++sum[i][b[i - 1]][b[i]]; } int l = 1, r = 0; long long ans = 0; for (register int i = 1; i <= n; ++i) { ++r; while (r < m && b[r] != a[i]) ++r; if (r > m) r = m; if (i > 1 && b[l] == a[i - 1]) ++l; if (l > m) break; ans += r - l + 1; if (i > 1 && a[i] != a[i - 1]) ans -= sum[r][a[i]][a[i - 1]] - sum[l - 1][a[i]][a[i - 1]]; } printf( %lld , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> void readi(T &x) { T input = 0; bool negative = false; char c = ; while (c < - ) { c = getchar(); } if (c == - ) { negative = true; c = getchar(); } while (c >= 0 ) { input = input * 10 + (c - 0 ); c = getchar(); } if (negative) { input = -input; } x = input; } template <class T> void printi(T output) { if (output == 0) { putchar( 0 ); return; } if (output < 0) { putchar( - ); output = -output; } int aout[20]; int ilen = 0; while (output) { aout[ilen] = ((output % 10)); output /= 10; ilen++; } for (int i = ilen - 1; i >= 0; i--) { putchar(aout[i] + 0 ); } return; } template <class T> void ckmin(T &a, T b) { a = min(a, b); } template <class T> void ckmax(T &a, T b) { a = max(a, b); } long long randomize(long long mod) { return ((1ll << 30) * rand() + (1ll << 15) * rand() + rand()) % mod; } const long double PI = 4.0 * atan(1.0); const long double EPS = 1e-10; long long normalize(long long x, long long mod = 1000000007) { return (((x % mod) + mod) % mod); } int Q; int X[3]; vector<int> factors[100013]; int A, B, C; vector<int> guy[8]; int need[8][8][8]; int sz[8], pref[8]; int p[6][3] = {{0, 1, 2}, {0, 2, 1}, {1, 0, 2}, {1, 2, 0}, {2, 0, 1}, {2, 1, 0}}; bool works(int a, int b, int c) { if ((a & 1) && (b & 2) && (c & 4)) { return true; } if ((a & 1) && (b & 4) && (c & 2)) { return true; } if ((a & 2) && (b & 1) && (c & 4)) { return true; } if ((a & 2) && (b & 4) && (c & 1)) { return true; } if ((a & 4) && (b & 1) && (c & 2)) { return true; } if ((a & 4) && (b & 2) && (c & 1)) { return true; } return false; } int gcd(int a, int b) { return b == 0 ? a : gcd(b, a % b); } long long cntleq(int idx, long long x) { return upper_bound(guy[idx].begin(), guy[idx].end(), x) - guy[idx].begin(); } long long choose2(long long a) { return a * (a - 1) / 2; } long long choose3(long long a) { return a * (a - 1) * (a - 2) / 6; } int32_t main() { ios_base::sync_with_stdio(0); srand(time(0)); if (fopen( cf1007b.in , r )) { freopen( cf1007b.in , r , stdin); } for (int i = 1; i < 100013; i++) { for (int j = i; j < 100013; j += i) { factors[j].push_back(i); } } cin >> Q; for (int q = 0; q < Q; q++) { cin >> X[0] >> X[1] >> X[2]; sort(X, X + 3); long long ans = 0; guy[1] = factors[X[0]]; guy[2] = factors[X[1]]; guy[3] = factors[gcd(X[0], X[1])]; guy[4] = factors[X[2]]; guy[5] = factors[gcd(X[0], X[2])]; guy[6] = factors[gcd(X[1], X[2])]; guy[7] = factors[gcd(X[0], gcd(X[1], X[2]))]; sz[7] = guy[7].size(); sz[6] = guy[6].size() - guy[7].size(); sz[5] = guy[5].size() - guy[7].size(); sz[3] = guy[3].size() - guy[7].size(); sz[4] = guy[4].size() - guy[6].size() - guy[5].size() + guy[7].size(); sz[2] = guy[2].size() - guy[6].size() - guy[3].size() + guy[7].size(); sz[1] = guy[1].size() - guy[3].size() - guy[5].size() + guy[7].size(); for (int i = 1; i < 8; i++) { pref[i] = guy[i].size(); } long long one = 0, two = 0, three = 0; one = sz[7]; for (int i = 1; i < 8; i++) { for (int j = 1; j < 8; j++) { if (!works(i, i, j)) { continue; } if (i == j) continue; two += sz[i] * sz[j]; } } two += choose2(sz[7]) * 2; for (int i = 1; i < 8; i++) { for (int j = i + 1; j < 8; j++) { for (int k = j + 1; k < 8; k++) { if (!works(i, j, k)) continue; three += sz[i] * sz[j] * sz[k]; } } } for (int i = 1; i < 8; i++) { for (int j = 1; j < 8; j++) { if (!works(i, i, j)) continue; if (i == j) continue; three += choose2(sz[i]) * sz[j]; } } three += choose3(sz[7]); ans = one + two + three; cout << ans << n ; } cerr << time elapsed = << (clock() / (CLOCKS_PER_SEC / 1000)) << ms << endl; return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:40:38 05/31/2011
// Design Name: main
// Module Name: /home/ikari/prj/sd2snes/verilog/sd2snes/main_tf.v
// Project Name: sd2snes
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: main
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module main_tf;
// Inputs
reg CLKIN;
reg [23:0] SNES_ADDR;
reg SNES_READ;
reg SNES_WRITE;
reg SNES_CS;
reg SNES_CPU_CLK;
reg SNES_REFRESH;
reg SNES_SYSCLK;
reg SPI_MOSI;
reg SPI_SS;
reg MCU_OVR;
reg [3:0] SD_DAT;
// Outputs
wire SNES_DATABUS_OE;
wire SNES_DATABUS_DIR;
wire IRQ_DIR;
wire [22:0] ROM_ADDR;
wire ROM_CE;
wire ROM_OE;
wire ROM_WE;
wire ROM_BHE;
wire ROM_BLE;
wire [18:0] RAM_ADDR;
wire RAM_CE;
wire RAM_OE;
wire RAM_WE;
wire DAC_MCLK;
wire DAC_LRCK;
wire DAC_SDOUT;
// Bidirs
wire [7:0] SNES_DATA;
wire SNES_IRQ;
wire [15:0] ROM_DATA;
wire [7:0] RAM_DATA;
wire SPI_MISO;
wire SPI_SCK;
wire SD_CMD;
wire SD_CLK;
// Instantiate the Unit Under Test (UUT)
main uut (
.CLKIN(CLKIN),
.SNES_ADDR(SNES_ADDR),
.SNES_READ(SNES_READ),
.SNES_WRITE(SNES_WRITE),
.SNES_CS(SNES_CS),
.SNES_DATA(SNES_DATA),
.SNES_CPU_CLK(SNES_CPU_CLK),
.SNES_REFRESH(SNES_REFRESH),
.SNES_IRQ(SNES_IRQ),
.SNES_DATABUS_OE(SNES_DATABUS_OE),
.SNES_DATABUS_DIR(SNES_DATABUS_DIR),
.IRQ_DIR(IRQ_DIR),
.SNES_SYSCLK(SNES_SYSCLK),
.ROM_DATA(ROM_DATA),
.ROM_ADDR(ROM_ADDR),
.ROM_CE(ROM_CE),
.ROM_OE(ROM_OE),
.ROM_WE(ROM_WE),
.ROM_BHE(ROM_BHE),
.ROM_BLE(ROM_BLE),
.RAM_DATA(RAM_DATA),
.RAM_ADDR(RAM_ADDR),
.RAM_CE(RAM_CE),
.RAM_OE(RAM_OE),
.RAM_WE(RAM_WE),
.SPI_MOSI(SPI_MOSI),
.SPI_MISO(SPI_MISO),
.SPI_SS(SPI_SS),
.SPI_SCK(SPI_SCK),
.MCU_OVR(MCU_OVR),
.DAC_MCLK(DAC_MCLK),
.DAC_LRCK(DAC_LRCK),
.DAC_SDOUT(DAC_SDOUT),
.SD_DAT(SD_DAT),
.SD_CMD(SD_CMD),
.SD_CLK(SD_CLK)
);
integer i;
reg [7:0] SNES_DATA_OUT;
reg [7:0] SNES_DATA_IN;
assign SNES_DATA = (!SNES_READ) ? 8'bZ : SNES_DATA_IN;
initial begin
// Initialize Inputs
CLKIN = 0;
SNES_ADDR = 0;
SNES_READ = 1;
SNES_WRITE = 1;
SNES_CS = 0;
SNES_CPU_CLK = 0;
SNES_REFRESH = 0;
SNES_SYSCLK = 0;
SPI_MOSI = 0;
SPI_SS = 0;
MCU_OVR = 1;
SD_DAT = 0;
// Wait 100 ns for global reset to finish
#500;
// Add stimulus here
SNES_ADDR = 24'h208000;
SNES_DATA_IN = 8'h1f;
SNES_WRITE = 0;
#100 SNES_WRITE = 1;
#100;
for (i = 0; i < 4096; i = i + 1) begin
#140 SNES_READ = 0;
SNES_CPU_CLK = 1;
#140 SNES_READ = 1;
SNES_CPU_CLK = 0;
end
end
always #24 CLKIN = ~CLKIN;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; for (int k = 0; k < t; k++) { int n, m; cin >> n >> m; vector<vector<int>> a(max(n, m), vector<int>(max(n, m))); vector<vector<int>> id(n * m, vector<int>(2)); vector<vector<int>> c(n, vector<int>(m)); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> a[i][j]; id[a[i][j] - 1][1] = j; } } for (int i = 0; i < m; i++) { for (int j = 0; j < n; j++) { cin >> a[i][j]; id[a[i][j] - 1][0] = j; } } for (int k = 0; k < n * m; k++) { int i = id[k][0], j = id[k][1]; c[i][j] = k + 1; } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cout << c[i][j] << ; } cout << n ; } } } |
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:09:17 06/06/2009
// Design Name:
// Module Name: RCB_FRL_COUNT_TO_64
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module RCB_FRL_COUNT_TO_64(
input clk,
input rst,
input count,
input ud,
output reg [5:0] counter_value /*synthesis syn_noprune = 1*/
);
//This module counts up/down between 0 to 63
wire [5:0] counter_value_preserver;
// reg [5:0] counter_value/*synthesis syn_noprune = 1*/;
always@(posedge clk or posedge rst) begin
if(rst == 1'b1)
counter_value = 6'h00;
else begin
case({count,ud})
2'b00: counter_value = counter_value_preserver;
2'b01: counter_value = counter_value_preserver;
2'b10: counter_value = counter_value_preserver - 1;
2'b11: counter_value = counter_value_preserver + 1;
default: counter_value = 6'h00;
endcase
end
end
assign counter_value_preserver = counter_value;
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:45:56 04/26/2014
// Design Name: sccpu_cpu
// Module Name: D:/XilinxProject/CPU/sccpu.v
// Project Name: CPU
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: sccpu_cpu
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module sccpu;
// Inputs
reg clk;
reg clrn;
// Outputs
wire [31:0] pc;
wire [31:0] inst;
wire [31:0] dataout;
wire [31:0] result;
wire [31:0] d;
wire zero;
wire wreg;
wire m2reg;
wire [1:0] pcsource;
// Instantiate the Unit Under Test (UUT)
sccpu_cpu uut (
.clk(clk),
.clrn(clrn),
.pc(pc),
.inst(inst),
.dataout(dataout),
.result(result),
.d(d),
.zero(zero),
.wreg(wreg),
.m2reg(m2reg),
.pcsource(pcsource)
);
always #100 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
clrn = 0;
#100;
clrn = 1;
// Wait 100 ns for global reset to finish
// Add stimulus here
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; char arr[n][n]; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { cin >> arr[i][j]; } } vector<pair<int, int>> vec; if (arr[0][1] == arr[1][0]) { if (arr[0][1] == 1 ) { if (arr[n - 2][n - 1] != 0 ) { vec.push_back({n - 1, n}); } if (arr[n - 1][n - 2] != 0 ) { vec.push_back({n, n - 1}); } } else { if (arr[0][1] == 0 ) { if (arr[n - 2][n - 1] != 1 ) { vec.push_back({n - 1, n}); } if (arr[n - 1][n - 2] != 1 ) { vec.push_back({n, n - 1}); } } } } else if (arr[n - 1][n - 2] == arr[n - 2][n - 1]) { if (arr[n - 1][n - 2] == 1 ) { if (arr[0][1] != 0 ) { vec.push_back({1, 2}); } if (arr[1][0] != 0 ) { vec.push_back({2, 1}); } } else { if (arr[n - 1][n - 2] == 0 ) { if (arr[1][0] != 1 ) { vec.push_back({2, 1}); } if (arr[0][1] != 1 ) { vec.push_back({1, 2}); } } } } else { if (arr[n - 1][n - 2] != 1 ) { vec.push_back({n, n - 1}); } if (arr[n - 2][n - 1] != 1 ) { vec.push_back({n - 1, n}); } if (arr[0][1] != 0 ) { vec.push_back({1, 2}); } if (arr[1][0] != 0 ) { vec.push_back({2, 1}); } } cout << vec.size() << endl; for (auto x : vec) { cout << x.first << << x.second << endl; } } } |
#include <bits/stdc++.h> using namespace std; unsigned long long mod = 1000000007; template <class T1> void deb(T1 e1) { cout << e1 << n ; } template <class T1, class T2> void deb(T1 e1, T2 e2) { cout << e1 << << e2 << n ; } template <class T1, class T2, class T3> void deb(T1 e1, T2 e2, T3 e3) { cout << e1 << << e2 << << e3 << n ; } template <class T1, class T2, class T3, class T4> void deb(T1 e1, T2 e2, T3 e3, T4 e4) { cout << e1 << << e2 << << e3 << << e4 << n ; } template <class T1, class T2, class T3, class T4, class T5> void deb(T1 e1, T2 e2, T3 e3, T4 e4, T5 e5) { cout << e1 << << e2 << << e3 << << e4 << << e5 << n ; } template <class T1, class T2, class T3, class T4, class T5, class T6> void deb(T1 e1, T2 e2, T3 e3, T4 e4, T5 e5, T6 e6) { cout << e1 << << e2 << << e3 << << e4 << << e5 << << e6 << n ; } int main() { int nob, nog, dancing_jodis = 0; cin >> nob >> nog; vector<pair<int, int> > store; int max_gender = max(nob, nog); int min_gender = min(nob, nog); for (int gender = 1; gender <= min_gender; gender++, dancing_jodis++) (nob >= nog) ? store.push_back(make_pair(1, gender)) : store.push_back(make_pair(gender, 1)); for (int gender = 2; gender <= max_gender; gender++, dancing_jodis++) (nob >= nog) ? store.push_back(make_pair(gender, 1)) : store.push_back(make_pair(1, gender)); cout << dancing_jodis << n ; for (int jodi = 0; jodi < int((store).size()); jodi++) cout << store[jodi].first << << store[jodi].second << n ; return 0; } |
// my simple if else example, indented by verilog-mode
if (x == 1)
begin
test1 <= 1;
test2 <= 2;
end
else
begin
test1 <= 2;
test2 <= 1;
end
// code from IEEE spec, pg. 164
class MyBus extends Bus;
rand AddrType atype;
constraint addr_range
{
(atype == low ) -> addr inside { [0 : 15] };
(atype == mid ) -> addr inside { [16 : 127]};
(atype == high) -> addr inside {[128 : 255]};
}
//
endclass // MyBus
// same example, with verilog mode indenting, Cexp indent = 3
class MyBus extends Bus;
rand AddrType atype;
constraint addr_range
{
(atype == low ) -> addr inside { [0 : 15] };
(atype == mid ) -> addr inside { [16 : 127]};
(atype == high) -> addr inside {[128 : 255]};
}
//
endclass // MyBus
// same example, with verilog mode indenting, Cexp indent = 0
class MyBus extends Bus;
rand AddrType atype;
constraint addr_range
{
(atype == low ) -> addr inside { [0 : 15] };
(atype == mid ) -> addr inside { [16 : 127]};
(atype == high) -> addr inside {[128 : 255]};
}
endclass // MyBus
// covergroup example from IEEE pg. 317
covergroup cg @(posedge clk );
a : coverpoint v_a {
bins a1 = { [0:63] };
bins a2 = { [64:127] };
bins a3 = { [128:191] };
bins a4 = { [192:255] };
}
b : coverpoint v_b {
bins b1 = {0};
bins b2 = { [1:84] };
bins b3 = { [85:169] };
bins b4 = { [170:255] };
}
//
c : cross a, b
{
bins c1 = ! binsof(a) intersect {[100:200]}; // 4 cross products
bins c2 = binsof(a.a2) || binsof(b.b2); // 7 cross products
bins c3 = binsof(a.a1) && binsof(b.b4); // 1 cross product
}
endgroup
// here is the same code with verilog-mode indenting
// covergroup example from IEEE pg. 317
covergroup cg @(posedge clk );
a : coverpoint v_a
{
bins a1 = { [0:63] };
bins a2 = { [64:127] };
bins a3 = { [128:191] };
bins a4 = { [192:255] };
}
// foo
b : coverpoint v_b
{
bins b1 = {0};
bins b2 = { [1:84] };
bins b3 = { [85:169] };
bins b4 = { [170:255] };
}
c : cross a, b
{
bins c1 = ! binsof(a) intersect {[100:200]}; // 4 cross products
bins c2 = binsof(a.a2) || binsof(b.b2); // 7 cross products
bins c3 = binsof(a.a1) && binsof(b.b4); // 1 cross product
}
endgroup
module fool;
always @(posedge clk) begin
if(!M_select)
xferCount < = 8'd0;
else
case (condition[1 :0])
2'b00 : xferCount <= xferCount;
2'b01 : xferCount <= xferCount - 8'd1;
2'b10 : xferCount <= xferCount + 8'd1;
2'b11 : xferCount <= xferCount;
endcase // case (condition[1:0])
end
// But not this :
always @(posedge clk) begin
if(!M_select)
xferCount < = 8'd0;
else
case ({M_seqAddr,OPB_xferAck})
2'b00 : xferCount <= xferCount;
2'b01 : xferCount <= xferCount - 8'd1;
2'b10 : xferCount <= xferCount + 8'd1;
2'b11 : xferCount <= xferCount;
endcase // case ({M_seqAddr,OPB_xferAck})
end // always @ (posedge clk)
endmodule // fool
module foo;
initial begin
k = 10;
std::randomize(delay) with { (delay>=1000 && delay<=3000); };
j = 9;
end
endmodule // foo
// Issue 324 - constraint indentation is not correct
// This checks for indentation around { and } inside constraint contents
class myclass;
constraint c {
foreach(items[i]) {
if(write) {
items[i].op_code == WRITE;
} else if(read) {
items[i].op_code == READ;
}
}
}
endclass // myclass
|
#include <bits/stdc++.h> struct node { int a, b, w; } p[200005]; int fa[200005]; bool d[200005]; bool cmp(node x, node y) { return x.w > y.w; } int find(int x) { return x == fa[x] ? x : fa[x] = find(fa[x]); } int main() { int n, m, ans = 0; scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { scanf( %d%d%d , &p[i].a, &p[i].b, &p[i].w); } std::sort(p + 1, p + m + 1, cmp); for (int i = 1; i <= n; i++) { fa[i] = i; d[i] = true; } for (int i = 1; i <= m; i++) { int x = find(p[i].a); int y = find(p[i].b); if (x != y && (d[x] || d[y])) { fa[y] = x; ans += p[i].w; d[x] = d[x] & d[y]; } else if (x == y && d[x]) { d[x] = false; ans += p[i].w; } } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; int main() { string s; cin >> s; int n = s.size(); if (n % 2 == 1) { for (int i = 0; i < n + 1; ++i) { cout << (i < (n + 1) / 2 ? 4 : 7); } cout << endl; return 0; } int seven = 0, four = 0; for (int i = 0; i < n; ++i) { if (s[i] == 4 ) { four++; } if (s[i] == 7 ) { seven++; } } if (seven == four && seven + four == n) { cout << s << endl; return 0; } for (int i = n - 1; i >= 0; --i) { if (s[i] == 4 ) { four--; } if (s[i] == 7 ) { seven--; } if (seven + four != i) { continue; } if (seven > n / 2 || four > n / 2) { continue; } if (s[i] < 4 && n / 2 - four > 0) { s[i] = 4 ; four++; int x = i + 1; while (four < n / 2) { s[x++] = 4 ; four++; } while (seven < n / 2) { s[x++] = 7 ; seven++; } cout << s << endl; return 0; } if (s[i] < 7 && n / 2 - seven > 0) { s[i] = 7 ; seven++; int x = i + 1; while (four < n / 2) { s[x++] = 4 ; four++; } while (seven < n / 2) { s[x++] = 7 ; seven++; } cout << s << endl; return 0; } } for (int i = 0; i < n + 2; ++i) { cout << (i < (n + 2) / 2 ? 4 : 7); } cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; long long ax, ay, bx, by, cx, cy; void check(long long axx, long long ayy) { if (cx == 0 && cy == 0) { if (axx == bx && ayy == by) { cout << YES ; exit(0); } else return; } if ((cx * (by - ayy) - cy * (bx - axx)) % (cx * cx + cy * cy) != 0 || (cx * (bx - axx) + cy * (by - ayy)) % (cx * cx + cy * cy) != 0) return; cout << YES ; exit(0); } int main() { cin >> ax >> ay >> bx >> by >> cx >> cy; check(ax, ay); check(ay, -ax); check(-ax, -ay); check(-ay, ax); cout << NO ; } |
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC optimize( unroll-loops ) using namespace std; using ll = long long; using db = long double; using ii = pair<int, int>; const int N = 1e5 + 5, LG = 17, MOD = 998244353; const int SQ = 225; const long double EPS = 1e-7; int n, m, a[N], b[N]; set<int> pos[N]; bool vis[N]; int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; for (int i = 1; i < n + 1; i++) cin >> a[i]; cin >> m; for (int i = 1; i < m + 1; i++) cin >> b[i]; sort(b + 1, b + m + 1); vector<int> lis; for (int i = 1; i < n + 1; i++) { if (a[i] == -1) { int p = lower_bound(lis.begin(), lis.end(), b[m]) - lis.begin(); if (p == lis.size()) lis.push_back(INT_MAX); for (int j = m; j; --j) { while (p > 0 && b[j] <= lis[p - 1]) --p; lis[p] = min(lis[p], b[j]); } } else { int p = lower_bound(lis.begin(), lis.end(), a[i]) - lis.begin(); if (p == lis.size()) lis.push_back(0); lis[p] = a[i]; pos[p].insert(i); } } int idx = n, prv = INT_MAX, ptr = m; for (int i = lis.size() - 1; i >= 0; --i) { auto it = pos[i].upper_bound(idx); if (it != pos[i].begin()) { --it; if (a[*it] < prv) { idx = *it; prv = a[idx]; continue; } } while (~a[idx]) --idx; while (b[ptr] >= prv) --ptr; prv = a[idx] = b[ptr]; vis[ptr] = true; } int tmp = 1; for (int i = 1; i < n + 1; i++) { while (tmp <= m && vis[tmp]) tmp++; if (a[i] == -1) a[i] = b[tmp++]; cout << a[i] << n [i == n]; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A222O_BEHAVIORAL_V
`define SKY130_FD_SC_LS__A222O_BEHAVIORAL_V
/**
* a222o: 2-input AND into all inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a222o (
X ,
A1,
A2,
B1,
B2,
C1,
C2
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire and2_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
and and2 (and2_out , C1, C2 );
or or0 (or0_out_X, and1_out, and0_out, and2_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A222O_BEHAVIORAL_V |
/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream demultiplexer
*/
module axis_demux #
(
// Number of AXI stream outputs
parameter M_COUNT = 4,
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = (DATA_WIDTH/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
parameter ID_WIDTH = 8,
// Propagate tdest signal
parameter DEST_ENABLE = 0,
// tdest signal width
parameter DEST_WIDTH = 8,
// Propagate tuser signal
parameter USER_ENABLE = 1,
// tuser signal width
parameter USER_WIDTH = 1
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [ID_WIDTH-1:0] s_axis_tid,
input wire [DEST_WIDTH-1:0] s_axis_tdest,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI outputs
*/
output wire [M_COUNT*DATA_WIDTH-1:0] m_axis_tdata,
output wire [M_COUNT*KEEP_WIDTH-1:0] m_axis_tkeep,
output wire [M_COUNT-1:0] m_axis_tvalid,
input wire [M_COUNT-1:0] m_axis_tready,
output wire [M_COUNT-1:0] m_axis_tlast,
output wire [M_COUNT*ID_WIDTH-1:0] m_axis_tid,
output wire [M_COUNT*DEST_WIDTH-1:0] m_axis_tdest,
output wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser,
/*
* Control
*/
input wire enable,
input wire drop,
input wire [$clog2(M_COUNT)-1:0] select
);
parameter CL_M_COUNT = $clog2(M_COUNT);
reg [CL_M_COUNT-1:0] select_reg = {CL_M_COUNT{1'b0}}, select_ctl, select_next;
reg drop_reg = 1'b0, drop_ctl, drop_next;
reg frame_reg = 1'b0, frame_ctl, frame_next;
reg s_axis_tready_reg = 1'b0, s_axis_tready_next;
// internal datapath
reg [DATA_WIDTH-1:0] m_axis_tdata_int;
reg [KEEP_WIDTH-1:0] m_axis_tkeep_int;
reg [M_COUNT-1:0] m_axis_tvalid_int;
reg m_axis_tready_int_reg = 1'b0;
reg m_axis_tlast_int;
reg [ID_WIDTH-1:0] m_axis_tid_int;
reg [DEST_WIDTH-1:0] m_axis_tdest_int;
reg [USER_WIDTH-1:0] m_axis_tuser_int;
wire m_axis_tready_int_early;
assign s_axis_tready = s_axis_tready_reg && enable;
always @* begin
select_next = select_reg;
select_ctl = select_reg;
drop_next = drop_reg;
drop_ctl = drop_reg;
frame_next = frame_reg;
frame_ctl = frame_reg;
s_axis_tready_next = 1'b0;
if (s_axis_tvalid && s_axis_tready) begin
// end of frame detection
if (s_axis_tlast) begin
frame_next = 1'b0;
drop_next = 1'b0;
end
end
if (!frame_reg && s_axis_tvalid && s_axis_tready) begin
// start of frame, grab select value
select_ctl = select;
drop_ctl = drop;
frame_ctl = 1'b1;
if (!(s_axis_tready && s_axis_tvalid && s_axis_tlast)) begin
select_next = select_ctl;
drop_next = drop_ctl;
frame_next = 1'b1;
end
end
s_axis_tready_next = (m_axis_tready_int_early || drop_ctl);
m_axis_tdata_int = s_axis_tdata;
m_axis_tkeep_int = s_axis_tkeep;
m_axis_tvalid_int = (s_axis_tvalid && s_axis_tready && !drop_ctl) << select_ctl;
m_axis_tlast_int = s_axis_tlast;
m_axis_tid_int = s_axis_tid;
m_axis_tdest_int = s_axis_tdest;
m_axis_tuser_int = s_axis_tuser;
end
always @(posedge clk) begin
if (rst) begin
select_reg <= 2'd0;
drop_reg <= 1'b0;
frame_reg <= 1'b0;
s_axis_tready_reg <= 1'b0;
end else begin
select_reg <= select_next;
drop_reg <= drop_next;
frame_reg <= frame_next;
s_axis_tready_reg <= s_axis_tready_next;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg [M_COUNT-1:0] m_axis_tvalid_reg = {M_COUNT{1'b0}}, m_axis_tvalid_next;
reg m_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg [M_COUNT-1:0] temp_m_axis_tvalid_reg = {M_COUNT{1'b0}}, temp_m_axis_tvalid_next;
reg temp_m_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] temp_m_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_m_axis_tuser_reg = {USER_WIDTH{1'b0}};
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign m_axis_tdata = {M_COUNT{m_axis_tdata_reg}};
assign m_axis_tkeep = KEEP_ENABLE ? {M_COUNT{m_axis_tkeep_reg}} : {M_COUNT*KEEP_WIDTH{1'b1}};
assign m_axis_tvalid = m_axis_tvalid_reg;
assign m_axis_tlast = {M_COUNT{m_axis_tlast_reg}};
assign m_axis_tid = ID_ENABLE ? {M_COUNT{m_axis_tid_reg}} : {M_COUNT*ID_WIDTH{1'b0}};
assign m_axis_tdest = DEST_ENABLE ? {M_COUNT{m_axis_tdest_reg}} : {M_COUNT*DEST_WIDTH{1'b0}};
assign m_axis_tuser = USER_ENABLE ? {M_COUNT{m_axis_tuser_reg}} : {M_COUNT*USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_axis_tready_int_early = (m_axis_tready & m_axis_tvalid) || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid || !m_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_axis_tvalid_next = m_axis_tvalid_reg;
temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (m_axis_tready_int_reg) begin
// input is ready
if ((m_axis_tready & m_axis_tvalid) || !m_axis_tvalid) begin
// output is ready or currently not valid, transfer data to output
m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_axis_tready & m_axis_tvalid) begin
// input is not ready, but output is ready
m_axis_tvalid_next = temp_m_axis_tvalid_reg;
temp_m_axis_tvalid_next = {M_COUNT{1'b0}};
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_axis_tvalid_reg <= {M_COUNT{1'b0}};
m_axis_tready_int_reg <= 1'b0;
temp_m_axis_tvalid_reg <= {M_COUNT{1'b0}};
end else begin
m_axis_tvalid_reg <= m_axis_tvalid_next;
m_axis_tready_int_reg <= m_axis_tready_int_early;
temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
m_axis_tdata_reg <= m_axis_tdata_int;
m_axis_tkeep_reg <= m_axis_tkeep_int;
m_axis_tlast_reg <= m_axis_tlast_int;
m_axis_tid_reg <= m_axis_tid_int;
m_axis_tdest_reg <= m_axis_tdest_int;
m_axis_tuser_reg <= m_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
m_axis_tdata_reg <= temp_m_axis_tdata_reg;
m_axis_tkeep_reg <= temp_m_axis_tkeep_reg;
m_axis_tlast_reg <= temp_m_axis_tlast_reg;
m_axis_tid_reg <= temp_m_axis_tid_reg;
m_axis_tdest_reg <= temp_m_axis_tdest_reg;
m_axis_tuser_reg <= temp_m_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_axis_tdata_reg <= m_axis_tdata_int;
temp_m_axis_tkeep_reg <= m_axis_tkeep_int;
temp_m_axis_tlast_reg <= m_axis_tlast_int;
temp_m_axis_tid_reg <= m_axis_tid_int;
temp_m_axis_tdest_reg <= m_axis_tdest_int;
temp_m_axis_tuser_reg <= m_axis_tuser_int;
end
end
endmodule
|
// file: clk_gen.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// _____clk____12.727______0.000______50.0______285.078____281.140
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_____________125____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "clk_gen,clk_wiz_v5_3_0,{component_name=clk_gen,use_phase_alignment=false,use_min_o_jitter=true,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=8.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module clk_gen
(
// Clock in ports
input clk125,
// Clock out ports
output clk,
// Status and control signals
output clk_locked
);
clk_gen_clk_wiz inst
(
// Clock in ports
.clk125(clk125),
// Clock out ports
.clk(clk),
// Status and control signals
.clk_locked(clk_locked)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const long long mx = 1e3 + 4; vector<vector<long long>> dist; vector<vector<bool>> col; queue<pair<long long, long long>> vis; long long n, m, t; long long expo_pow(long long x, long long y) { if (y == 0) return 1; y = y % (mod - 1); x %= mod; if (y == 0) y = mod - 1; long long res = 1; while (y) { if (y & 1) res = (res * x) % mod; x = (x * x) % mod; y >>= 1; } return res; } void solve() { cin >> n >> m >> t; col.resize(n + 1, vector<bool>(m + 1)); dist.resize(n + 1, vector<long long>(m + 1)); for (long long i = 1; i <= n; i++) { for (long long j = 1; j <= m; j++) { dist[i][j] = -1; char tmp; cin >> tmp; col[i][j] = (tmp == 1 ); } } for (long long i = 1; i <= n; i++) { for (long long j = 1; j <= m; j++) { if (i != 1 and col[i - 1][j] == col[i][j]) { dist[i][j] = 0; vis.push({i, j}); } else if (i != n and col[i + 1][j] == col[i][j]) { dist[i][j] = 0; vis.push({i, j}); } else if (j != 1 and col[i][j - 1] == col[i][j]) { dist[i][j] = 0; vis.push({i, j}); } else if (j != m and col[i][j + 1] == col[i][j]) { dist[i][j] = 0; vis.push({i, j}); } } } while (!vis.empty()) { auto cur = vis.front(); vis.pop(); if (cur.first != 1 and dist[cur.first - 1][cur.second] == -1) { dist[cur.first - 1][cur.second] = dist[cur.first][cur.second] + 1; vis.push({cur.first - 1, cur.second}); } if (cur.first != n and dist[cur.first + 1][cur.second] == -1) { dist[cur.first + 1][cur.second] = dist[cur.first][cur.second] + 1; vis.push({cur.first + 1, cur.second}); } if (cur.second != 1 and dist[cur.first][cur.second - 1] == -1) { dist[cur.first][cur.second - 1] = dist[cur.first][cur.second] + 1; vis.push({cur.first, cur.second - 1}); } if (cur.second != m and dist[cur.first][cur.second + 1] == -1) { dist[cur.first][cur.second + 1] = dist[cur.first][cur.second] + 1; vis.push({cur.first, cur.second + 1}); } } while (t--) { long long x, y, p; cin >> x >> y >> p; if (dist[x][y] == -1) { cout << col[x][y] << n ; continue; } if (p <= dist[x][y]) { cout << col[x][y] << n ; continue; } long long tmp = p - dist[x][y]; if (tmp % 2) { cout << !col[x][y] << n ; } else { cout << col[x][y] << n ; } } } signed main() { long long test = 1; long long i = 1; while (test--) { solve(); } } |
module deserializer
#( parameter INLOGBITS = 3,
parameter OUTLOGBITS = 6,
localparam INWIDTH = 1<<INLOGBITS,
localparam OUTWIDTH = 1<<OUTLOGBITS)
(
input clk,
input rst_n,
input in_valid,
output reg in_ready,
input [INWIDTH-1:0] in_data,
output reg out_valid,
input out_ready,
output reg [OUTWIDTH-1:0] out_data
);
localparam LOGBITDIFF = OUTLOGBITS-INLOGBITS ;
localparam MAXCNT = (1<<LOGBITDIFF)-1;
reg out_valid_next;
reg [LOGBITDIFF-1:0] cnt;
reg [LOGBITDIFF-1:0] cnt_next;
wire [OUTWIDTH-1:0] out_data_shifted;
wire [OUTWIDTH-1:0] out_data_new;
reg [OUTWIDTH-1:0] out_data_next;
assign out_data_shifted = (out_data >> INWIDTH);
assign out_data_new = {in_data,out_data_shifted[OUTWIDTH-INWIDTH-1:0]};
always @(*) begin
in_ready = 1;
out_valid_next = 0;
out_data_next = out_data;
cnt_next = cnt;
if (cnt == 0 && in_valid && out_ready) begin
out_data_next = out_data_new;
cnt_next = cnt - 1'b1; // Should wrap
out_valid_next = 1;
end
else if (cnt == 0 && !out_ready) begin
in_ready = 0;
end
else if (in_valid) begin
out_data_next = out_data_new;
cnt_next = cnt - 1'b1; // Should wrap
end
end
`REG(clk, cnt, MAXCNT, cnt_next)
`REG(clk, out_valid, 0, out_valid_next)
`REG(clk, out_data, 0, out_data_next)
endmodule
/*
deserializer #(.INLOGBITS(3), .OUTLOGBITS(6)) inst_XXX(
.clk(clk),
.rst_n(rst_n),
.in_valid(XXX_in_valid),
.in_ready(XXX_in_ready),
.in_data(XXX_in_data),
.out_valid(XXX_out_valid),
.out_ready(XXX_out_ready),
.out_data(XXX_out_data)
);
*/
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 7; long long a[N], n, seg[20][N]; void build(int xl = 0, int xr = n, int ind = 0) { if (xr - xl == 1) { seg[ind][xl] = a[xr] - a[xl]; return; } int xm = (xl + xr) / 2; build(xl, xm, ind + 1); build(xm, xr, ind + 1); for (int i = xl; i < xm; i++) seg[ind][i] = a[xm] - a[i]; for (int i = xm; i < xr; i++) seg[ind][i] = a[i + 1] - a[xm]; sort(&seg[ind][xl], &seg[ind][xm]); sort(&seg[ind][xm], &seg[ind][xr]); } inline long long GreaterThan(long long x, int xl = 0, int xr = n, int k = 1, int ind = 0) { if (xr - xl == 1) return (seg[ind][xl] > x); int xm = (xl + xr) / 2; long long GreaterChild = GreaterThan(x, xl, xm, 2 * k, ind + 1) + GreaterThan(x, xm, xr, 2 * k + 1, ind + 1); long long GreaterMid = 0; int j = xr; for (int i = xl; i < xm; i++) { while (j > xm && seg[ind][j - 1] + seg[ind][i] > x) j--; GreaterMid += xr - j; } return GreaterChild + GreaterMid; } int main() { ios::sync_with_stdio(0); long long k; scanf( %lld %lld , &n, &k); for (int i = 0; i < n; i++) scanf( %lld , &a[i + 1]); for (int i = 1; i < n; i++) a[i + 1] += a[i]; build(); long long l = -1e14 - 7, r = 1e14 + 7; while (r - l > 1) { long long m = (l + r) / 2; long long ans = GreaterThan(m); if (ans >= k) l = m; else r = m; } printf( %lld n , r); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, k, m, t; cin >> n >> k >> m >> t; for (int i = 0; i < t; i++) { int a, b; cin >> a >> b; if (a == 0 && b < k) { k -= b; n -= b; } else if (a == 1 && b <= k) { k++; n++; } else if (a == 0 && b >= k) { n = b; } else if (a == 1 && b > k) { n++; } cout << n << << k << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int n; int cnt[3], seen[3]; string s; int main() { ios::sync_with_stdio(0); cin >> n >> s; int m = n / 3; for (int i = 0; i < n; i++) { cnt[s[i] - 0 ]++; } for (int i = 0; i < n; i++) { if (cnt[s[i] - 0 ] > m) { for (long long j = 0; j < 3; j++) { if (cnt[j] < m) { if (j > s[i] - 0 && seen[s[i] - 0 ] < m) break; cnt[j]++; cnt[s[i] - 0 ]--; s[i] = j + 0 ; } } } seen[s[i] - 0 ]++; } cout << s << endl; return 0; } |
// jaxa_mm_interconnect_0_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 17.1 593
`timescale 1 ps / 1 ps
module jaxa_mm_interconnect_0_avalon_st_adapter #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
jaxa_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// Input must be RGB or CrYCb in that order, output is CrY/CbY
`timescale 1ns/100ps
module ad_ss_422to444 #(
parameter CR_CB_N = 0,
parameter DELAY_DATA_WIDTH = 16) (
// 422 inputs
input clk,
input s422_de,
input [DW:0] s422_sync,
input [15:0] s422_data,
// 444 outputs
output reg [DW:0] s444_sync,
output reg [23:0] s444_data);
localparam DW = DELAY_DATA_WIDTH - 1;
// internal registers
reg cr_cb_sel = 'd0;
reg s422_de_d = 'd0;
reg [DW:0] s422_sync_d = 'd0;
reg s422_de_2d = 'd0;
reg [7:0] s422_Y_d;
reg [7:0] s422_CbCr_d;
reg [7:0] s422_CbCr_2d;
reg [ 8:0] s422_CbCr_avg;
// internal wires
wire [ 7:0] s422_Y;
wire [ 7:0] s422_CbCr;
// Input format is
// [15:8] Cb/Cr
// [ 7:0] Y
//
// Output format is
// [23:15] Cr
// [16: 8] Y
// [ 7: 0] Cb
assign s422_Y = s422_data[7:0];
assign s422_CbCr = s422_data[15:8];
// first data on de assertion is cb (0x0), then cr (0x1).
// previous data is held when not current
always @(posedge clk) begin
if (s422_de_d == 1'b1) begin
cr_cb_sel <= ~cr_cb_sel;
end else begin
cr_cb_sel <= CR_CB_N;
end
end
// pipe line stages
always @(posedge clk) begin
s422_de_d <= s422_de;
s422_sync_d <= s422_sync;
s422_de_2d <= s422_de_d;
s422_Y_d <= s422_Y;
s422_CbCr_d <= s422_CbCr;
s422_CbCr_2d <= s422_CbCr_d;
end
// If both the left and the right sample are valid do the average, otherwise
// use the only valid.
always @(s422_de_2d, s422_de, s422_CbCr, s422_CbCr_2d)
begin
if (s422_de == 1'b1 && s422_de_2d)
s422_CbCr_avg <= s422_CbCr + s422_CbCr_2d;
else if (s422_de == 1'b1)
s422_CbCr_avg <= {s422_CbCr, 1'b0};
else
s422_CbCr_avg <= {s422_CbCr_2d, 1'b0};
end
// 444 outputs
always @(posedge clk) begin
s444_sync <= s422_sync_d;
s444_data[15:8] <= s422_Y_d;
if (cr_cb_sel) begin
s444_data[23:16] <= s422_CbCr_d;
s444_data[ 7: 0] <= s422_CbCr_avg[8:1];
end else begin
s444_data[23:16] <= s422_CbCr_avg[8:1];
s444_data[ 7: 0] <= s422_CbCr_d;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; using UL = unsigned long int; using UI = unsigned int; using ULL = unsigned long long int; using LI = long int; using LL = long long; using LF = double; using LLF = long double; const int mod1 = 1000000007; const int mod2 = 998244353; const double PI = acos(-1); int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); int ntc = 1, tc, i, j; int n, k; for (tc = 1; tc <= ntc; tc++) { cin >> n >> k; string s; cin >> s; int cnt1[26] = {0}, cnt2[26] = {0}; string ans = ; for (auto ch : s) { cnt1[ch - a ]++; } for (i = 0; i < 26 && k > 0; i++) { cnt2[i] += min(k, cnt1[i]); k -= min(k, cnt1[i]); } for (auto ch : s) { if (cnt2[ch - a ] > 0) { cnt2[ch - a ]--; continue; } cout << ch; } } return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jun 04 17:33:00 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_buffer_register_0_0 -prefix
// system_buffer_register_0_0_ system_buffer_register_0_0_sim_netlist.v
// Design : system_buffer_register_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module system_buffer_register_0_0_buffer_register
(val_out,
val_in,
clk);
output [31:0]val_out;
input [31:0]val_in;
input clk;
wire clk;
wire [31:0]val_in;
wire [31:0]val_out;
FDRE \val_out_reg[0]
(.C(clk),
.CE(1'b1),
.D(val_in[0]),
.Q(val_out[0]),
.R(1'b0));
FDRE \val_out_reg[10]
(.C(clk),
.CE(1'b1),
.D(val_in[10]),
.Q(val_out[10]),
.R(1'b0));
FDRE \val_out_reg[11]
(.C(clk),
.CE(1'b1),
.D(val_in[11]),
.Q(val_out[11]),
.R(1'b0));
FDRE \val_out_reg[12]
(.C(clk),
.CE(1'b1),
.D(val_in[12]),
.Q(val_out[12]),
.R(1'b0));
FDRE \val_out_reg[13]
(.C(clk),
.CE(1'b1),
.D(val_in[13]),
.Q(val_out[13]),
.R(1'b0));
FDRE \val_out_reg[14]
(.C(clk),
.CE(1'b1),
.D(val_in[14]),
.Q(val_out[14]),
.R(1'b0));
FDRE \val_out_reg[15]
(.C(clk),
.CE(1'b1),
.D(val_in[15]),
.Q(val_out[15]),
.R(1'b0));
FDRE \val_out_reg[16]
(.C(clk),
.CE(1'b1),
.D(val_in[16]),
.Q(val_out[16]),
.R(1'b0));
FDRE \val_out_reg[17]
(.C(clk),
.CE(1'b1),
.D(val_in[17]),
.Q(val_out[17]),
.R(1'b0));
FDRE \val_out_reg[18]
(.C(clk),
.CE(1'b1),
.D(val_in[18]),
.Q(val_out[18]),
.R(1'b0));
FDRE \val_out_reg[19]
(.C(clk),
.CE(1'b1),
.D(val_in[19]),
.Q(val_out[19]),
.R(1'b0));
FDRE \val_out_reg[1]
(.C(clk),
.CE(1'b1),
.D(val_in[1]),
.Q(val_out[1]),
.R(1'b0));
FDRE \val_out_reg[20]
(.C(clk),
.CE(1'b1),
.D(val_in[20]),
.Q(val_out[20]),
.R(1'b0));
FDRE \val_out_reg[21]
(.C(clk),
.CE(1'b1),
.D(val_in[21]),
.Q(val_out[21]),
.R(1'b0));
FDRE \val_out_reg[22]
(.C(clk),
.CE(1'b1),
.D(val_in[22]),
.Q(val_out[22]),
.R(1'b0));
FDRE \val_out_reg[23]
(.C(clk),
.CE(1'b1),
.D(val_in[23]),
.Q(val_out[23]),
.R(1'b0));
FDRE \val_out_reg[24]
(.C(clk),
.CE(1'b1),
.D(val_in[24]),
.Q(val_out[24]),
.R(1'b0));
FDRE \val_out_reg[25]
(.C(clk),
.CE(1'b1),
.D(val_in[25]),
.Q(val_out[25]),
.R(1'b0));
FDRE \val_out_reg[26]
(.C(clk),
.CE(1'b1),
.D(val_in[26]),
.Q(val_out[26]),
.R(1'b0));
FDRE \val_out_reg[27]
(.C(clk),
.CE(1'b1),
.D(val_in[27]),
.Q(val_out[27]),
.R(1'b0));
FDRE \val_out_reg[28]
(.C(clk),
.CE(1'b1),
.D(val_in[28]),
.Q(val_out[28]),
.R(1'b0));
FDRE \val_out_reg[29]
(.C(clk),
.CE(1'b1),
.D(val_in[29]),
.Q(val_out[29]),
.R(1'b0));
FDRE \val_out_reg[2]
(.C(clk),
.CE(1'b1),
.D(val_in[2]),
.Q(val_out[2]),
.R(1'b0));
FDRE \val_out_reg[30]
(.C(clk),
.CE(1'b1),
.D(val_in[30]),
.Q(val_out[30]),
.R(1'b0));
FDRE \val_out_reg[31]
(.C(clk),
.CE(1'b1),
.D(val_in[31]),
.Q(val_out[31]),
.R(1'b0));
FDRE \val_out_reg[3]
(.C(clk),
.CE(1'b1),
.D(val_in[3]),
.Q(val_out[3]),
.R(1'b0));
FDRE \val_out_reg[4]
(.C(clk),
.CE(1'b1),
.D(val_in[4]),
.Q(val_out[4]),
.R(1'b0));
FDRE \val_out_reg[5]
(.C(clk),
.CE(1'b1),
.D(val_in[5]),
.Q(val_out[5]),
.R(1'b0));
FDRE \val_out_reg[6]
(.C(clk),
.CE(1'b1),
.D(val_in[6]),
.Q(val_out[6]),
.R(1'b0));
FDRE \val_out_reg[7]
(.C(clk),
.CE(1'b1),
.D(val_in[7]),
.Q(val_out[7]),
.R(1'b0));
FDRE \val_out_reg[8]
(.C(clk),
.CE(1'b1),
.D(val_in[8]),
.Q(val_out[8]),
.R(1'b0));
FDRE \val_out_reg[9]
(.C(clk),
.CE(1'b1),
.D(val_in[9]),
.Q(val_out[9]),
.R(1'b0));
endmodule
(* CHECK_LICENSE_TYPE = "system_buffer_register_0_0,buffer_register,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "buffer_register,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_buffer_register_0_0
(clk,
val_in,
val_out);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
input [31:0]val_in;
output [31:0]val_out;
wire clk;
wire [31:0]val_in;
wire [31:0]val_out;
system_buffer_register_0_0_buffer_register U0
(.clk(clk),
.val_in(val_in),
.val_out(val_out));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; int main() { int c0, c1, c2, c3; cin >> c0 >> c1 >> c2 >> c3; if (c1 - c0 == c2 - c1 && c2 - c1 == c3 - c2) { cout << c3 + c1 - c0 << endl; } else if (c1 * c1 == c0 * c2 && c2 * c2 == c1 * c3 && !((c3 * c3) % c2)) { cout << c3 * c1 / c0 << endl; } else { cout << 42 << endl; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O21BA_2_V
`define SKY130_FD_SC_MS__O21BA_2_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog wrapper for o21ba with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o21ba.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o21ba_2 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o21ba_2 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O21BA_2_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int x = 0, y = 0; char s[n]; for (int i = 0; i < n; i++) { cin >> s[i]; if (s[i] == 0 ) y++; else x++; } if (x == y) { cout << 2 << endl << s[0] << ; for (int i = 1; i < n; i++) cout << s[i]; } else { cout << 1 << endl; for (int i = 0; i < n; i++) cout << s[i]; } return 0; } |
#include <bits/stdc++.h> using namespace std; char A[300]; int cnt[5]; char data[5] = ACGT ; int main() { int n; scanf( %d , &n); scanf( %s , A); for (int i = 0; A[i]; i++) { if (A[i] == A ) cnt[0]++; else if (A[i] == C ) cnt[1]++; else if (A[i] == G ) cnt[2]++; else if (A[i] == T ) cnt[3]++; else cnt[4]++; } int big = 0, dif = 0; ; for (int i = 0; i < 4; i++) big = max(big, cnt[i]); for (int i = 0; i < 4; i++) { cnt[i] = big - cnt[i]; dif += cnt[i]; } if (dif > cnt[4]) { printf( === ); return 0; } if ((cnt[4] - dif) % 4 != 0) { printf( === ); return 0; } int flag = 0; for (int i = 0; A[i]; i++) { if (A[i] == ? ) { flag = 0; for (int j = 0; j < 4; j++) { if (cnt[j] > 0) { A[i] = data[j]; cnt[j]--; flag = 1; break; } } if (flag == 0) { for (int j = 0; j < 4; j++) cnt[j]++; i--; } } } printf( %s , A); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O41AI_2_V
`define SKY130_FD_SC_HD__O41AI_2_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog wrapper for o41ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o41ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o41ai_2 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o41ai_2 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O41AI_2_V
|
#include <bits/stdc++.h> using namespace std; template <typename A, typename B, typename C> struct triple { A X; B Y; C Z; triple(A a = 0, B b = 0, C c = 0) : X(a), Y(b), Z(c) {} }; template <typename A, typename B, typename C> triple<A, B, C> make_triple(A a = 0, B b = 0, C c = 0) { return triple<A, B, C>(a, b, c); } template <typename A, typename B, typename C> bool operator<(const triple<A, B, C>& a, const triple<A, B, C>& b) { if (a.X != b.X) return a.X < b.X; if (a.Y != b.Y) return a.Y < b.Y; return a.Z < b.Z; } template <typename T, typename SS> ostream& operator<<(ostream& ofs, const pair<T, SS>& p) { ofs << ( << p.first << , << p.second << ) ; return ofs; } template <typename T> void print(T a) { for (auto i : a) cout << i << ; cout << n ; } template <typename T> T max(T a, T b, T c) { return max(a, max(b, c)); } template <typename T> T min(T a, T b, T c) { return min(a, min(b, c)); } struct custom_hash { static uint64_t splitmix64(uint64_t x) { x += 0x9e3779b97f4a7c15; x = (x ^ (x >> 30)) * 0xbf58476d1ce4e5b9; x = (x ^ (x >> 27)) * 0x94d049bb133111eb; return x ^ (x >> 31); } size_t operator()(uint64_t x) const { static const uint64_t FIXED_RANDOM = chrono::steady_clock::now().time_since_epoch().count(); return splitmix64(x + FIXED_RANDOM); } }; signed main() { srand(time(NULL)); cin.tie(0); cout.tie(0); ios_base::sync_with_stdio(false); long long n; cin >> n; vector<long long> a(n); for (long long i = 0; i < (n); i++) cin >> a[i]; long long ans = 0; auto solve = [&](long long v) { vector<long long> b(a); long long pw = 1 << v; for (long long i = 0; i < (n); i++) b[i] %= (pw * 2); sort(b.begin(), b.end()); long long c = 0; auto count = [&](long long l, long long r) -> long long { return lower_bound(b.begin(), b.end(), r) - lower_bound(b.begin(), b.end(), l); }; for (long long i = 0; i < (n); i++) c += (count(pw - b[i], pw * 2 - b[i]) + count(pw * 3 - b[i], pw * 4 - b[i])); for (long long i = 0; i < (n); i++) if ((2 * b[i]) & pw) c--; c >>= 1; return c & 1; }; for (long long i = 0; i < (25); i++) if (solve(i)) ans += 1LL << i; cout << ans << n ; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 4e5 + 5; const string s[] = { NW , NE , SE , SW }; inline int read() { int x = 0; char ch = getchar(); while (!isdigit(ch)) ch = getchar(); while (isdigit(ch)) { x = x * 10 + ch - 0 ; ch = getchar(); } return x; } struct Node { int x, y, k; inline bool operator==(const Node B) const { return this->x == B.x && this->y == B.y && this->k == B.k; } inline bool operator!=(const Node B) const { return !(*this == B); } }; int n, m, k; long long ans; set<int> s1[MAXN], s2[MAXN]; map<pair<int, int>, int> mp; inline void add(int x, int y) { s1[(1 == 1 ? x - y + m + 1 : x + y)].insert(x); s2[(2 == 1 ? x - y + m + 1 : x + y)].insert(x); mp[make_pair(x, y)] = 1; } inline void prepare() { for (int i = 0; i <= n + 1; i++) add(i, 0), add(i, m + 1); for (int i = 0; i <= m + 1; i++) add(0, i), add(n + 1, i); } inline Node change(Node x, int opt = 1) { Node now = x; int cur = 0; if (x.k == 1) { cur = *(--s1[(1 == 1 ? x.x - x.y + m + 1 : x.x + x.y)].lower_bound(x.x)); now.x -= (abs(cur - x.x) - 1), now.y -= (abs(cur - x.x) - 1); if ((mp.find(make_pair(now.x - 1, now.y)) != mp.end()) && (mp.find(make_pair(now.x, now.y - 1)) != mp.end())) now.k = 3; else if ((mp.find(make_pair(now.x - 1, now.y)) != mp.end())) now.y--, now.k = 4; else if ((mp.find(make_pair(now.x, now.y - 1)) != mp.end())) now.x--, now.k = 2; else now.k = 3; } if (x.k == 2) { cur = *(--s2[(2 == 1 ? x.x - x.y + m + 1 : x.x + x.y)].lower_bound(x.x)); now.x -= (abs(cur - x.x) - 1), now.y += (abs(cur - x.x) - 1); if ((mp.find(make_pair(now.x - 1, now.y)) != mp.end()) && (mp.find(make_pair(now.x, now.y + 1)) != mp.end())) now.k = 4; else if ((mp.find(make_pair(now.x - 1, now.y)) != mp.end())) now.y++, now.k = 3; else if ((mp.find(make_pair(now.x, now.y + 1)) != mp.end())) now.x--, now.k = 1; else now.k = 4; } if (x.k == 3) { cur = *(s1[(1 == 1 ? x.x - x.y + m + 1 : x.x + x.y)].lower_bound(x.x)); now.x += (abs(cur - x.x) - 1), now.y += (abs(cur - x.x) - 1); if ((mp.find(make_pair(now.x + 1, now.y)) != mp.end()) && (mp.find(make_pair(now.x, now.y + 1)) != mp.end())) now.k = 1; else if ((mp.find(make_pair(now.x + 1, now.y)) != mp.end())) now.y++, now.k = 2; else if ((mp.find(make_pair(now.x, now.y + 1)) != mp.end())) now.x++, now.k = 4; else now.k = 1; } if (x.k == 4) { cur = *(s2[(2 == 1 ? x.x - x.y + m + 1 : x.x + x.y)].lower_bound(x.x)); now.x += (abs(cur - x.x) - 1), now.y -= (abs(cur - x.x) - 1); if ((mp.find(make_pair(now.x + 1, now.y)) != mp.end()) && (mp.find(make_pair(now.x, now.y - 1)) != mp.end())) now.k = 2; else if ((mp.find(make_pair(now.x + 1, now.y)) != mp.end())) now.y--, now.k = 1; else if ((mp.find(make_pair(now.x, now.y - 1)) != mp.end())) now.x++, now.k = 3; else now.k = 2; } opt && (ans += abs(cur - x.x)); return now; } inline bool check_it(Node x) { Node tmp = x; Node y = change(x); x = y; if (((tmp.k + 1) % 4 == y.k - 1)) return false; while (tmp != x) { y = change(y); if (((x.k + 1) % 4 == y.k - 1)) return false; x = y; } return 1; } int main() { n = read(), m = read(); k = read(), prepare(); for (int i = 1; i <= k; i++) { int x = read(); int y = read(); add(x, y); } int sx = read(), sy = read(), sd = -1; string str; cin >> str; for (int i = 0; i < 4; i++) if (str == s[i]) sd = i + 1; assert(~sd); Node st = Node{sx, sy, sd}; st = change(st, 0); if (!check_it(st)) { ans--; st.k = (st.k + 1) % 4 + 1; check_it(st); } printf( %lld n , ans); return 0; } |
//move some stuff to minitests/ncy0
`define SEED 32'h12345678
module top(input clk, stb, di, output do);
localparam integer DIN_N = 42;
localparam integer DOUT_N = 79;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi #(.DIN_N(DIN_N), .DOUT_N(DOUT_N))
roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
//# ERROR: Assert `range_left >= range_right || (range_left == -1 && range_right == 0)' failed in frontends/ast/genrtlil.cc:861.
//module roi(input clk, input [DIN_N-1:0] din, output [DOUT_N-1:0] dout);
module roi(input clk, input [42-1:0] din, output [79-1:0] dout);
parameter integer DIN_N = -1;
parameter integer DOUT_N = -1;
picorv32 picorv32 (
.clk(clk),
.resetn(din[0]),
.mem_valid(dout[0]),
.mem_instr(dout[1]),
.mem_ready(din[1]),
.mem_addr(dout[33:2]),
.mem_wdata(dout[66:34]),
.mem_wstrb(dout[70:67]),
.mem_rdata(din[33:2])
);
randluts randluts (
.din(din[41:34]),
.dout(dout[78:71]));
endmodule
module randluts(input [7:0] din, output [7:0] dout);
//localparam integer N = 250;
localparam integer N = 100;
function [31:0] xorshift32(input [31:0] xorin);
begin
xorshift32 = xorin;
xorshift32 = xorshift32 ^ (xorshift32 << 13);
xorshift32 = xorshift32 ^ (xorshift32 >> 17);
xorshift32 = xorshift32 ^ (xorshift32 << 5);
end
endfunction
function [63:0] lutinit(input [7:0] a, b);
begin
lutinit[63:32] = xorshift32(xorshift32(xorshift32(xorshift32({a, b} ^ `SEED))));
lutinit[31: 0] = xorshift32(xorshift32(xorshift32(xorshift32({b, a} ^ `SEED))));
end
endfunction
wire [(N+1)*8-1:0] nets;
assign nets[7:0] = din;
assign dout = nets[(N+1)*8-1:N*8];
genvar i, j;
generate
for (i = 0; i < N; i = i+1) begin:is
for (j = 0; j < 8; j = j+1) begin:js
localparam integer k = xorshift32(xorshift32(xorshift32(xorshift32((i << 20) ^ (j << 10) ^ `SEED)))) & 255;
LUT6 #(
.INIT(lutinit(i, j))
) lut (
.I0(nets[8*i+(k+0)%8]),
.I1(nets[8*i+(k+1)%8]),
.I2(nets[8*i+(k+2)%8]),
.I3(nets[8*i+(k+3)%8]),
.I4(nets[8*i+(k+4)%8]),
.I5(nets[8*i+(k+5)%8]),
.O(nets[8*i+8+j])
);
end
end
endgenerate
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module altera_mem_if_ddr3_phy_0001_addr_cmd_datapath(
clk,
reset_n,
afi_address,
afi_bank,
afi_cs_n,
afi_cke,
afi_odt,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_rst_n,
phy_ddio_address,
phy_ddio_bank,
phy_ddio_cs_n,
phy_ddio_cke,
phy_ddio_we_n,
phy_ddio_ras_n,
phy_ddio_cas_n,
phy_ddio_reset_n,
phy_ddio_odt
);
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_CHIP_SELECT_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_BANK_WIDTH = "";
parameter AFI_CHIP_SELECT_WIDTH = "";
parameter AFI_CLK_EN_WIDTH = "";
parameter AFI_ODT_WIDTH = "";
parameter AFI_DATA_MASK_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter AFI_DATA_WIDTH = "";
parameter NUM_AC_FR_CYCLE_SHIFTS = "";
localparam RATE_MULT = 2;
input reset_n;
input clk;
input [AFI_ADDRESS_WIDTH-1:0] afi_address;
input [AFI_BANK_WIDTH-1:0] afi_bank;
input [AFI_CHIP_SELECT_WIDTH-1:0] afi_cs_n;
input [AFI_CLK_EN_WIDTH-1:0] afi_cke;
input [AFI_ODT_WIDTH-1:0] afi_odt;
input [AFI_CONTROL_WIDTH-1:0] afi_ras_n;
input [AFI_CONTROL_WIDTH-1:0] afi_cas_n;
input [AFI_CONTROL_WIDTH-1:0] afi_we_n;
input [AFI_CONTROL_WIDTH-1:0] afi_rst_n;
output [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address;
output [AFI_BANK_WIDTH-1:0] phy_ddio_bank;
output [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
output [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
output [AFI_ODT_WIDTH-1:0] phy_ddio_odt;
output [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
output [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
output [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
output [AFI_CONTROL_WIDTH-1:0] phy_ddio_reset_n;
wire [AFI_ADDRESS_WIDTH-1:0] afi_address_r = afi_address;
wire [AFI_BANK_WIDTH-1:0] afi_bank_r = afi_bank;
wire [AFI_CHIP_SELECT_WIDTH-1:0] afi_cs_n_r = afi_cs_n;
wire [AFI_CLK_EN_WIDTH-1:0] afi_cke_r = afi_cke;
wire [AFI_ODT_WIDTH-1:0] afi_odt_r = afi_odt;
wire [AFI_CONTROL_WIDTH-1:0] afi_ras_n_r = afi_ras_n;
wire [AFI_CONTROL_WIDTH-1:0] afi_cas_n_r = afi_cas_n;
wire [AFI_CONTROL_WIDTH-1:0] afi_we_n_r = afi_we_n;
wire [AFI_CONTROL_WIDTH-1:0] afi_rst_n_r = afi_rst_n;
wire [1:0] shift_fr_cycle =
(NUM_AC_FR_CYCLE_SHIFTS == 0) ? 2'b00 : (
(NUM_AC_FR_CYCLE_SHIFTS == 1) ? 2'b01 : (
(NUM_AC_FR_CYCLE_SHIFTS == 2) ? 2'b10 : (
2'b11 )));
altera_mem_if_ddr3_phy_0001_fr_cycle_shifter uaddr_cmd_shift_address(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_address_r),
.dataout (phy_ddio_address)
);
defparam uaddr_cmd_shift_address.DATA_WIDTH = MEM_ADDRESS_WIDTH;
defparam uaddr_cmd_shift_address.REG_POST_RESET_HIGH = "false";
altera_mem_if_ddr3_phy_0001_fr_cycle_shifter uaddr_cmd_shift_bank(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_bank_r),
.dataout (phy_ddio_bank)
);
defparam uaddr_cmd_shift_bank.DATA_WIDTH = MEM_BANK_WIDTH;
defparam uaddr_cmd_shift_bank.REG_POST_RESET_HIGH = "false";
altera_mem_if_ddr3_phy_0001_fr_cycle_shifter uaddr_cmd_shift_cke(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_cke_r),
.dataout (phy_ddio_cke)
);
defparam uaddr_cmd_shift_cke.DATA_WIDTH = MEM_CLK_EN_WIDTH;
defparam uaddr_cmd_shift_cke.REG_POST_RESET_HIGH = "false";
altera_mem_if_ddr3_phy_0001_fr_cycle_shifter uaddr_cmd_shift_cs_n(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_cs_n_r),
.dataout (phy_ddio_cs_n)
);
defparam uaddr_cmd_shift_cs_n.DATA_WIDTH = MEM_CHIP_SELECT_WIDTH;
defparam uaddr_cmd_shift_cs_n.REG_POST_RESET_HIGH = "true";
altera_mem_if_ddr3_phy_0001_fr_cycle_shifter uaddr_cmd_shift_odt(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_odt_r),
.dataout (phy_ddio_odt)
);
defparam uaddr_cmd_shift_odt.DATA_WIDTH = MEM_ODT_WIDTH;
defparam uaddr_cmd_shift_odt.REG_POST_RESET_HIGH = "false";
altera_mem_if_ddr3_phy_0001_fr_cycle_shifter uaddr_cmd_shift_ras_n(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_ras_n_r),
.dataout (phy_ddio_ras_n)
);
defparam uaddr_cmd_shift_ras_n.DATA_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_shift_ras_n.REG_POST_RESET_HIGH = "true";
altera_mem_if_ddr3_phy_0001_fr_cycle_shifter uaddr_cmd_shift_cas_n(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_cas_n_r),
.dataout (phy_ddio_cas_n)
);
defparam uaddr_cmd_shift_cas_n.DATA_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_shift_cas_n.REG_POST_RESET_HIGH = "true";
altera_mem_if_ddr3_phy_0001_fr_cycle_shifter uaddr_cmd_shift_we_n(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_we_n_r),
.dataout (phy_ddio_we_n)
);
defparam uaddr_cmd_shift_we_n.DATA_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_shift_we_n.REG_POST_RESET_HIGH = "true";
altera_mem_if_ddr3_phy_0001_fr_cycle_shifter uaddr_cmd_shift_rst_n(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_rst_n_r),
.dataout (phy_ddio_reset_n)
);
defparam uaddr_cmd_shift_rst_n.DATA_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_shift_rst_n.REG_POST_RESET_HIGH = "true";
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using uint = unsigned int; using pii = pair<int, int>; using vi = vector<int>; int main() { int t; cin >> t; while (t--) { int a, b; cin >> a >> b; if (a % b == 0) cout << YES n ; else cout << NO n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main(int argc, char* argv[]) { ios_base::sync_with_stdio(false); cin.tie(NULL); int k; string str; cin >> str; cin >> k; int temp[50]; memset(temp, 0, sizeof(temp)); int count = 0; for (int i = 0; i < str.size(); ++i) { if (temp[(int)(str[i] - a )] == 0) { count++; temp[str[i] - a ] = 1; } } if (count >= k) { cout << 0 << endl; } else if (k > (int)str.size()) { cout << impossible << endl; } else { cout << k - count << endl; } return 0; } |
module x (/*AUTOARG*/
// Inputs
MIERHW, MBOOTH_P, CEIopMADH_E_D2_R, CEIopMAZH_E_D2_R, DDATAH, DIV2HI, HI_R, MCLA, MCLASH,
MULTSHCYC, MULTUSCYC, HI_P
);
input [18:0] MIERHW;
integer i;
integer MTEMP1;
integer MTEMP2;
input MBOOTH_P;
input CEIopMADH_E_D2_R;
input CEIopMAZH_E_D2_R;
input DDATAH;
input DIV2HI;
input HI_R;
input MCLA;
input MCLASH;
input MULTSHCYC;
input MULTUSCYC;
input HI_P;
/*AUTOREG*/
/*AUTOINPUT*/
/*AUTOOUTPUT*/
always @(/*AUTOSENSE*/MIERHW) begin
for (i=0; i<=5; i=i+1) begin
MTEMP1[3:0] = {MIERHW[i*3+3],
MIERHW[i*3+2],
MIERHW[i*3+1],
MIERHW[i*3+0]};
casex (MTEMP1)
4'b0000: MTEMP2 = 4'b0101; // +0
4'b0001: MTEMP2 = 4'b0001; // +1
4'b0010: MTEMP2 = 4'b0001; // +1
4'b0011: MTEMP2 = 4'b0010; // +2
4'b0100: MTEMP2 = 4'b0010; // +2
4'b0101: MTEMP2 = 4'b0100; // +3
4'b0110: MTEMP2 = 4'b0100; // +3
4'b0111: MTEMP2 = 4'b1000; // +4
4'b1000: MTEMP2 = 4'b0111; // -4
4'b1001: MTEMP2 = 4'b1011; // -3
4'b1010: MTEMP2 = 4'b1011; // -3
4'b1011: MTEMP2 = 4'b1101; // -2
4'b1100: MTEMP2 = 4'b1101; // -2
4'b1101: MTEMP2 = 4'b1110; // -1
4'b1110: MTEMP2 = 4'b1110; // -1
4'b1111: MTEMP2 = 4'b1010; // -0
endcase
end
{MBOOTH_P[i*4+3],
MBOOTH_P[i*4+2],
MBOOTH_P[i*4+1],
MBOOTH_P[i*4+0]} = MTEMP2[3:0];
end
// always @(/*AUTOnotSENSE*/
// __CEIopMADH_E_D2_R or __CEIopMAZH_E_D2_R or __DIV2HI or
// __MULTUSCYC or __MULTSHCYC or
// __DDATAH or __HI_R or __MCLA or __MCLASH) begin
// always @(/*AUTOSENSE*/DDATAH or HI_R or MCLA or MCLASH) begin
`define DMCLASH MCLASH
`define DCONST 1'b1
always @(/*AUTOSENSE*/CEIopMADH_E_D2_R or CEIopMAZH_E_D2_R or DDATAH or DIV2HI or MCLA or MCLASH
or MULTSHCYC or MULTUSCYC) begin
case (1'b1)
CEIopMADH_E_D2_R: HI_P = MCLA;
CEIopMAZH_E_D2_R: HI_P = MCLA;
DIV2HI: HI_P = DDATAH;
MULTUSCYC: HI_P = MCLA;
MULTSHCYC: HI_P = `DMCLASH;
default: HI_P = `DCONST;
endcase
end
endmodule
// Local Variables:
// verilog-auto-read-includes:t
// End:
|
#include <bits/stdc++.h> using namespace std; int N[5]; int K; int getChoice(int choice) { if (N[choice]) return choice; for (int i = 1; true; i++) { if (choice + i < 5 && N[choice + i]) return choice + i; if (choice - i >= 0 && N[choice - i]) return choice - i; } } int main() { for (int i = 0; i < 5; i++) cin >> N[i]; cin >> K; map<string, int> strToInt; strToInt[ S ] = 0; strToInt[ M ] = 1; strToInt[ L ] = 2; strToInt[ XL ] = 3; strToInt[ XXL ] = 4; map<int, string> intToStr; intToStr[0] = S ; intToStr[1] = M ; intToStr[2] = L ; intToStr[3] = XL ; intToStr[4] = XXL ; string temp; for (int i = 0; i < K; i++) { cin.ignore(5, n ); cin >> temp; int choice = strToInt[temp]; int willGet = getChoice(choice); N[willGet]--; cout << intToStr[willGet] << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const long double PI = 4 * atan(1); const int32_t MOD = 1e9 + 7; int power(int x, unsigned int y) { int temp; if (y == 0) return 1; temp = power(x, y / 2); if (y % 2 == 0) return temp * temp % MOD; else return x * temp % MOD * temp % MOD; } void solve() { string s; cin >> s; int n = s.length(); string s1, s2; cin >> s1 >> s2; int m1 = s1.length(), m2 = s2.length(); int j = -1, k = -1; bool f1 = 0, f2 = 0; j = s.find(s1); k = s.find(s2, s1.length() + j); if (j != -1 && k != -1) f1 = 1; reverse(s.begin(), s.end()); j = -1, k = -1; j = s.find(s1); k = s.find(s2, s1.length() + j); if (j != -1 && k != -1) f2 = 1; if (f1 && f2) cout << both n ; else if (f1) cout << forward n ; else if (f2) cout << backward n ; else cout << fantasy n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(0); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; long long a, b, c, m, n; int main() { cin >> a; cout << a / 2520; } |
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; int l = s.length(); vector<char> s1; for (int i = 0; i < l; i++) { s1.push_back(s[i]); int f = 0; while (s[i] == / && i < l) { i++; f = 1; } if (f == 1) i--; } if (s1[s1.size() - 1] == / && s1.size() != 1) s1.pop_back(); for (int i = 0; i < s1.size(); i++) cout << s1[i]; return 0; } |
#include <bits/stdc++.h> int n; long long x, y, z = 2; int main() { scanf( %d , &n); for (long long k = 1; k <= n; k++) { y += 2; x += y; double a = x; double b = z; a = (double)(a / k); b = (double)(b / k); a = (double)a * x; printf( %.0lf n , (double)a - b); z = x; } } |
// This should blink at a rate of ~ second
// 12mhz/(56000hz) = 214/2 = 107
// 12mhz/2400 = 5000 /2 = 2500
// 12mhz/9600 = 1250 /2 = 625
// 12mhz/38400 = 312 /2 = 156
// 12mhz/57600 = 208.3 /2 = 104
// 12mhz/19200 = 625 /2 = 312
// 12mhz/115200 = 104 /2 = 52
// 2400hz
//parameter UART_PERIOD = 5000;
//parameter UART_PERIOD_TH = 7500; // three halves
//9600
//parameter UART_PERIOD = 1250;
//parameter UART_PERIOD_TH = 1875; // three halves
//19200
//parameter UART_PERIOD = 625;
//parameter UART_PERIOD_TH = 937; // three halves
//57600
//parameter UART_PERIOD = 206;
//parameter UART_PERIOD_TH = 309; // three halves
// 115200
// * the trick here is to have the FPGA run slightly faster than the computer
// then the FPGA won't get behind and drop data.
parameter UART_PERIOD = 100;
parameter UART_PERIOD_TH = 150; // three halves
module TXMOD(
output TX,
input CLK,
input [7:0] data,
input valid,
output ready);
reg TXReg = 1;
assign TX = TXReg;
reg [10:0] dataStore = 1536; // MSB=1, LSB=0
reg writing = 0;
assign ready = (writing==0);
reg [13:0] writeClock = 0; // which cycle are we in?
reg [3:0] writeBit = 0; // which bit are we writing? (10 bits total)
always @(posedge CLK) begin
if(writing==0 && valid==1) begin
writing <= 1;
dataStore[8:1] <= data;
writeClock <= UART_PERIOD;
writeBit <= 0;
TXReg <= dataStore[0];
end else if(writing==1 && writeClock==0 && writeBit==9) begin
// we're done
TXReg <= 1;
writing <= 0;
end else if(writing==1 && writeClock==0) begin
// move on to next bit
TXReg <= dataStore[writeBit];
writeBit <= writeBit+1;
writeClock <= UART_PERIOD;
end else if(writing==1) begin
TXReg <= dataStore[writeBit];
writeClock <= writeClock - 1;
end else begin
TXReg <= 1;
end
end
endmodule
module RXMOD(
input RX,
input CLK,
output [7:0] data,
output valid);
reg RX_1;
reg RX_2;
always @(posedge CLK) begin
RX_1 <= RX;
RX_2 <= RX_1;
end
wire RXi;
assign RXi = RX_2;
reg [8:0] dataReg;
reg validReg = 0;
assign data = dataReg[7:0];
assign valid = validReg;
reg [12:0] readClock = 0; // which subclock?
reg [3:0] readBit = 0; // which bit? (0-8)
reg reading = 0;
always @ (posedge CLK)
begin
if(RXi==0 && reading==0) begin
reading <= 1;
readClock <= UART_PERIOD_TH; // sample to middle of second byte
readBit <= 0;
validReg <= 0;
end else if(reading==1 && readClock==0 && readBit==8) begin
// we're done
reading <= 0;
dataReg[8] <= RXi;
validReg <= 1;
end else if(reading==1 && readClock==0) begin
// read a byte
dataReg[readBit] <= RXi;
readClock <= UART_PERIOD;
readBit <= readBit + 1;
validReg <= 0;
end else if(reading==1 && readClock>0) begin
readClock <= readClock - 1;
validReg <= 0;
end else begin
validReg <= 0;
end
end
endmodule
module main (input CLK, input RX, output TX,
output LED0,
output LED1,
output LED2,
output LED3,
output LED4,
output PMOD_1,
output PMOD_2);
assign PMOD_1 = RX;
assign PMOD_2 = TX;
wire [7:0] readData;
wire readValid;
reg [7:0] readDataReg;
wire txReady;
reg txValid = 0;
always @(posedge CLK) begin
if(readValid) begin
readDataReg <= readData;
txValid <= 1;
end else if(txReady) begin
txValid <= 0;
end
end
assign LED4 = readValid;
assign {LED3, LED2, LED1, LED0} = readDataReg[3:0];
RXMOD rxmod(.RX(RX), .CLK(CLK), .data(readData), .valid(readValid) );
TXMOD txmod(.TX(TX), .CLK(CLK), .data(readDataReg+10), .valid(txValid), .ready(txReady) );
endmodule
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// part of NeoGS flash programmer project (c) 2014 lvd^NedoPC
//
// top-level module
module top(
input wire clk_fpga, // clocks
input wire clk_24mhz, //
output wire clksel0, // clock selection
output wire clksel1, //
input wire warmres_n, // warm reset
inout wire [ 7:0] d, // Z80 data bus
output wire [15:0] a, // Z80 address bus
input wire iorq_n, // Z80 control signals
input wire mreq_n, //
input wire rd_n, //
input wire wr_n, //
input wire m1_n, //
output wire int_n, //
output wire nmi_n, //
output wire busrq_n, //
input wire busak_n, //
output wire z80res_n, //
output wire mema14, // memory control
output wire mema15, //
output wire mema16, //
output wire mema17, //
output wire mema18, //
output wire ram0cs_n, //
output wire ram1cs_n, //
output wire ram2cs_n, //
output wire ram3cs_n, //
output wire mema21, //
output wire romcs_n, //
output wire memoe_n, //
output wire memwe_n, //
inout wire [7:0] zxid, // zxbus signals
input wire [7:0] zxa, //
input wire zxa14, //
input wire zxa15, //
input wire zxiorq_n, //
input wire zxmreq_n, //
input wire zxrd_n, //
input wire zxwr_n, //
input wire zxcsrom_n, //
output wire zxblkiorq_n, //
output wire zxblkrom_n, //
output wire zxgenwait_n, //
output wire zxbusin, //
output wire zxbusena_n, //
output wire dac_bitck, // audio-DAC signals
output wire dac_lrck, //
output wire dac_dat, //
output wire sd_clk, // SD card interface
output wire sd_cs, //
output wire sd_do, //
input wire sd_di, //
input wire sd_wp, //
input wire sd_det, //
output wire ma_clk, // control interface of MP3 chip
output wire ma_cs,
output wire ma_do,
input wire ma_di,
output wire mp3_xreset, // data interface of MP3 chip
input wire mp3_req, //
output wire mp3_clk, //
output wire mp3_dat, //
output wire mp3_sync, //
output wire led_diag // LED driver
);
wire init, init_in_progress;
wire zxbus_rst_n;
wire rom_rst_n;
wire wr_addr;
wire wr_data;
wire rd_data;
wire [7:0] wr_buffer;
wire [7:0] rd_buffer;
wire autoinc_ena;
// assign unused pins to safe values
assign clksel0 = 1'b1;
assign clksel1 = 1'b1;
assign int_n = 1'b1;
assign nmi_n = 1'b1;
assign ram0cs_n = 1'b1;
assign ram1cs_n = 1'b1;
assign ram2cs_n = 1'b1;
assign ram3cs_n = 1'b1;
assign mema21 = 1'b0;
assign zxblkrom_n = 1'b1;
assign zxgenwait_n = 1'b1;
assign dac_bitck = 1'b0;
assign dac_lrck = 1'b0;
assign dac_dat = 1'b0;
assign sd_clk = 1'b0;
assign sd_cs = 1'b1;
assign sd_do = 1'b0;
assign ma_clk = 1'b0;
assign ma_cs = 1'b1;
assign ma_do = 1'b0;
assign mp3_xreset = 1'b0;
assign mp3_clk = 1'b0;
assign mp3_sync = 1'b0;
// reset controller
reset reset
(
.clk_fpga (clk_fpga ),
.clk_24mhz(clk_24mhz),
.init (init ),
.init_in_progress(init_in_progress),
.zxbus_rst_n(zxbus_rst_n),
.rom_rst_n (rom_rst_n ),
.z80_rst_n (z80res_n ),
.z80_busrq_n(busrq_n),
.z80_busak_n(busak_n)
);
// zxbus controller
zxbus zxbus
(
.clk (clk_24mhz ),
.rst_n(zxbus_rst_n),
.zxid (zxid ),
.zxa (zxa ),
.zxiorq_n (zxiorq_n ),
.zxmreq_n (zxmreq_n ),
.zxrd_n (zxrd_n ),
.zxwr_n (zxwr_n ),
.zxblkiorq_n(zxblkiorq_n),
.zxbusin (zxbusin ),
.zxbusena_n (zxbusena_n ),
.init (init ),
.init_in_progress(init_in_progress),
.led(led_diag),
.autoinc_ena(autoinc_ena),
.wr_addr (wr_addr ),
.wr_data (wr_data ),
.rd_data (rd_data ),
.wr_buffer(wr_buffer),
.rd_buffer(rd_buffer)
);
// rom controller
rom rom
(
.clk (clk_24mhz),
.rst_n(rom_rst_n),
.wr_addr (wr_addr ),
.wr_data (wr_data ),
.rd_data (rd_data ),
.wr_buffer(wr_buffer),
.rd_buffer(rd_buffer),
.autoinc_ena(autoinc_ena),
.rom_a ({mema18,mema17,mema16,mema15,mema14,a[13:0]}),
.rom_d (d),
.rom_cs_n(romcs_n),
.rom_oe_n(memoe_n),
.rom_we_n(memwe_n)
);
assign a[15:14] = 2'bZZ;
endmodule
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// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
(* altera_attribute = "-name GLOBAL_SIGNAL OFF" *)
module hps_sdram_p0_reset(
seq_reset_mem_stable,
pll_afi_clk,
pll_addr_cmd_clk,
pll_dqs_ena_clk,
seq_clk,
scc_clk,
pll_avl_clk,
reset_n_scc_clk,
reset_n_avl_clk,
read_capture_clk,
pll_locked,
global_reset_n,
soft_reset_n,
ctl_reset_n,
ctl_reset_export_n,
reset_n_afi_clk,
reset_n_addr_cmd_clk,
reset_n_resync_clk,
reset_n_seq_clk,
reset_n_read_capture_clk
);
parameter MEM_READ_DQS_WIDTH = "";
parameter NUM_AFI_RESET = 1;
input seq_reset_mem_stable;
input pll_afi_clk;
input pll_addr_cmd_clk;
input pll_dqs_ena_clk;
input seq_clk;
input scc_clk;
input pll_avl_clk;
output reset_n_scc_clk;
output reset_n_avl_clk;
input [MEM_READ_DQS_WIDTH-1:0] read_capture_clk;
input pll_locked;
input global_reset_n;
input soft_reset_n;
output ctl_reset_n;
output ctl_reset_export_n;
output [NUM_AFI_RESET-1:0] reset_n_afi_clk;
output reset_n_addr_cmd_clk;
output reset_n_resync_clk;
output reset_n_seq_clk;
output [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture_clk;
// Apply the synthesis keep attribute on the synchronized reset wires
// so that these names can be constrained using QSF settings to keep
// the resets on local routing.
wire phy_reset_n /* synthesis keep = 1 */;
wire phy_reset_mem_stable_n /* synthesis keep = 1*/;
wire [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture;
assign phy_reset_mem_stable_n = phy_reset_n & seq_reset_mem_stable;
assign reset_n_read_capture_clk = reset_n_read_capture;
assign phy_reset_n = pll_locked & global_reset_n & soft_reset_n;
hps_sdram_p0_reset_sync ureset_afi_clk(
.reset_n (phy_reset_n),
.clk (pll_afi_clk),
.reset_n_sync (reset_n_afi_clk)
);
defparam ureset_afi_clk.RESET_SYNC_STAGES = 15;
defparam ureset_afi_clk.NUM_RESET_OUTPUT = NUM_AFI_RESET;
hps_sdram_p0_reset_sync ureset_ctl_reset_clk(
.reset_n (phy_reset_n),
.clk (pll_afi_clk),
.reset_n_sync ({ctl_reset_n, ctl_reset_export_n})
);
defparam ureset_ctl_reset_clk.RESET_SYNC_STAGES = 15;
defparam ureset_ctl_reset_clk.NUM_RESET_OUTPUT = 2;
hps_sdram_p0_reset_sync ureset_addr_cmd_clk(
.reset_n (phy_reset_n),
.clk (pll_addr_cmd_clk),
.reset_n_sync (reset_n_addr_cmd_clk)
);
defparam ureset_addr_cmd_clk.RESET_SYNC_STAGES = 15;
defparam ureset_addr_cmd_clk.NUM_RESET_OUTPUT = 1;
hps_sdram_p0_reset_sync ureset_resync_clk(
.reset_n (phy_reset_n),
.clk (pll_dqs_ena_clk),
.reset_n_sync (reset_n_resync_clk)
);
defparam ureset_resync_clk.RESET_SYNC_STAGES = 15;
defparam ureset_resync_clk.NUM_RESET_OUTPUT = 1;
hps_sdram_p0_reset_sync ureset_seq_clk(
.reset_n (phy_reset_n),
.clk (seq_clk),
.reset_n_sync (reset_n_seq_clk)
);
defparam ureset_seq_clk.RESET_SYNC_STAGES = 15;
defparam ureset_seq_clk.NUM_RESET_OUTPUT = 1;
hps_sdram_p0_reset_sync ureset_scc_clk(
.reset_n (phy_reset_n),
.clk (scc_clk),
.reset_n_sync (reset_n_scc_clk)
);
defparam ureset_scc_clk.RESET_SYNC_STAGES = 15;
defparam ureset_scc_clk.NUM_RESET_OUTPUT = 1;
hps_sdram_p0_reset_sync ureset_avl_clk(
.reset_n (phy_reset_n),
.clk (pll_avl_clk),
.reset_n_sync (reset_n_avl_clk)
);
defparam ureset_avl_clk.RESET_SYNC_STAGES = 2;
defparam ureset_avl_clk.NUM_RESET_OUTPUT = 1;
generate
genvar i;
for (i=0; i<MEM_READ_DQS_WIDTH; i=i+1)
begin: read_capture_reset
hps_sdram_p0_reset_sync #(
.RESET_SYNC_STAGES(15),
.NUM_RESET_OUTPUT(1)
)
ureset_read_capture_clk(
.reset_n (phy_reset_mem_stable_n),
.clk (read_capture_clk[i]),
.reset_n_sync (reset_n_read_capture[i])
);
end
endgenerate
endmodule
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#include <bits/stdc++.h> using namespace std; const long long inf = ~0ULL >> 1; const int maxV = 3e5 + 10; const int maxE = 6e5 + 10; struct EDGE { int v, nxt; long long w; EDGE() {} EDGE(int vv, int xx, long long ww) { v = vv, nxt = xx, w = ww; } }; EDGE edg[maxE]; int EH[maxV], etot; void initG() { memset(EH, -1, sizeof(EH)); etot = 0; } void addEdge(int u, int v, long long w) { edg[etot] = EDGE(v, EH[u], w); EH[u] = etot++; } int n, m; short an[maxE]; long long dist[maxV]; short vs[maxV]; struct Node { int src, id; long long dst; Node() {} Node(int ss, long long dd, int ii) { src = ss, dst = dd, id = ii; } bool operator<(const Node &rhs) const { return (rhs.dst < dst) || (dst == rhs.dst && edg[rhs.id].w < edg[id].w); } }; void spfa(int s) { for (int i = 1; i <= n; i++) dist[i] = inf; memset(vs, 0, sizeof(vs)); memset(an, 0, sizeof(an)); priority_queue<Node> que; dist[s] = 0; que.push(Node(s, dist[s], -1)); long long rs = 0; while (!que.empty()) { Node now = que.top(); que.pop(); int u = now.src; int id = now.id; if (vs[u]) continue; vs[u] = 1; if (id != -1) { rs += edg[id].w; an[id] = 1; } for (int p = EH[u]; ~p; p = edg[p].nxt) { int v = edg[p].v; long long w = edg[p].w; if (dist[v] >= dist[u] + w) { dist[v] = dist[u] + w; que.push(Node(v, dist[v], p)); } } } cout << rs << endl; m <<= 1; for (int i = 0; i < m; i++) if (an[i]) cout << (i / 2 + 1) << ; cout << endl; } int main() { int u, v, p; long long w; while (~scanf( %d%d , &n, &m)) { initG(); for (int i = 1; i <= m; i++) { scanf( %d%d%I64d , &u, &v, &w); addEdge(u, v, w); addEdge(v, u, w); } scanf( %d , &p); spfa(p); } return 0; } |
#include <bits/stdc++.h> using namespace std; struct Segment { int l, r, x, ls, rs, fa; } seg[2000100]; int n, k, p[100100], cnt, pnt, b[2000100], w, ans[100100], res; int Dfs(int &id, int l, int r) { id = ++cnt; seg[id].l = l, seg[id].r = r; seg[id].x = 1; if (r - l == 1) return 1; int mid = (l + r) >> 1; seg[id].x += Dfs(seg[id].ls, l, mid); seg[id].x += Dfs(seg[id].rs, mid, r); return seg[id].x; } void Vis(int x) { if (!x) return; b[x] = 1; Vis(seg[x].ls); Vis(seg[x].rs); } bool cmp(int x, int y) { return seg[x].l < seg[y].l; } void Solve(int x) { if (!x) return; if (b[x]) { for (int i = seg[x].l; i < seg[x].r; i++) ans[i] = res++; return; } Solve(seg[x].rs); Solve(seg[x].ls); } int main() { scanf( %d%d , &n, &k); Dfs(w, 0, n); k = seg[1].x - k; for (int i = 1; i <= cnt; i++) if (!b[i]) { if (k >= seg[i].x - 1 && seg[i].x > 1) { k -= seg[i].x - 1; p[++pnt] = i; Vis(i); if (!k) break; } } if (k) printf( -1 ); else { res = 1; Solve(1); for (int i = n - 1; i >= 0; i--) ans[i] = ans[i] ? ans[i] : res++; for (int i = 0; i < n; i++) printf( %d , ans[i]); } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, A, B; double p[25]; double a[625][625], l[625][625], u[625][625]; vector<int> g[25]; double y[625], x[625], b[625]; int id[25][25]; void edge(int ea, int b, int c, int d, double e) { if (ea < b) swap(ea, b); if (c < d) swap(c, d); a[id[ea][b]][id[c][d]] += e; } int main() { scanf( %d %d %d %d , &n, &m, &A, &B); A--, B--; if (A < B) swap(A, B); for (int i = 0; i < (int)(m); i++) { int ue, v; scanf( %d %d , &ue, &v); ue--, v--; g[ue].push_back(v); g[v].push_back(ue); } for (int i = 0; i < (int)(n); i++) scanf( %lf , &p[i]); int N = 0; for (int i = 0; i < (int)(n); i++) for (int j = 0; j < (int)(i + 1); j++) id[i][j] = ++N; for (int i = 0; i < (int)(N + 1); i++) for (int j = 0; j < (int)(N + 1); j++) a[i][j] = 0; for (int i = 0; i < (int)(n); i++) for (int j = 0; j < (int)(i + 1); j++) { if (i == j) { edge(i, j, i, j, 1); continue; } edge(i, j, i, j, p[i] * p[j]); for (int q = 0; q < (int)(g[i].size()); q++) { int qi = g[i][q]; edge(i, j, qi, j, (1 - p[i]) / g[i].size() * p[j]); for (int qq = 0; qq < (int)(g[j].size()); qq++) { int qj = g[j][qq]; edge(i, j, qi, qj, (1 - p[i]) / g[i].size() * (1 - p[j]) / g[j].size()); } } for (int qq = 0; qq < (int)(g[j].size()); qq++) { int qj = g[j][qq]; edge(i, j, i, qj, (1 - p[j]) / g[j].size() * p[i]); } } for (int i = 0; i < (int)(n); i++) for (int j = 0; j < (int)(i); j++) a[id[i][j]][id[i][j]] -= 1; for (int j = 1; j <= N; j++) u[1][j] = a[1][j]; for (int j = 2; j <= N; j++) l[j][1] = a[j][1] / u[1][1]; for (int i = 2; i <= N; i++) { for (int j = i; j <= N; j++) { u[i][j] = a[i][j]; for (int k = 1; k <= i - 1; k++) u[i][j] -= l[i][k] * u[k][j]; } for (int j = i + 1; j <= N; j++) { l[j][i] = a[j][i]; for (int k = 1; k <= i - 1; k++) l[j][i] -= l[j][k] * u[k][i]; l[j][i] /= u[i][i]; } } for (int i = 1; i <= N; i++) l[i][i] = 1.0; for (int d = 0; d < (int)(n); d++) { for (int i = 0; i < (int)(n); i++) for (int j = 0; j < (int)(i + 1); j++) if (i != j) { b[id[i][j]] = 0; } else b[id[i][j]] = i == d; for (int i = 1; i <= N; i++) { y[i] = b[i]; for (int j = 1; j < i; j++) y[i] -= l[i][j] * y[j]; } for (int i = N; i >= 1; i--) { x[i] = y[i]; for (int j = i + 1; j <= N; j++) x[i] -= u[i][j] * x[j]; x[i] /= u[i][i]; } if (d) printf( ); printf( %.8f , x[id[A][B]]); } printf( n ); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 9; int n, p, q; string s, t, a, b; int c[2005], d[2005], h[2005], invH[2005], k[2005], invK[2005]; vector<pair<int, int>> memo; int mul(int aa, int bb) { return ((long long)aa * bb) % MOD; } int add(int aa, int bb) { return (aa + bb) % MOD; } int sub(int aa, int bb) { return (aa - bb + MOD) % MOD; } int modpow(int num, int pi) { int res = 1; while (pi > 0) { if (pi & 1) res = mul(res, num); num = mul(num, num); pi >>= 1; } return res; } pair<int, int> getHash(int lo, int hi) { return make_pair(mul(sub(c[hi], c[lo]), invH[lo]), mul(sub(d[hi], d[lo]), invK[lo])); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> s >> a >> b; n = s.size(); p = a.size(); q = b.size(); h[0] = invH[0] = 1; k[0] = invK[0] = 1; for (int i = 1; i <= n; i++) { h[i] = mul(h[i - 1], 31); invH[i] = modpow(h[i], MOD - 2); k[i] = mul(k[i - 1], 53); invK[i] = modpow(k[i], MOD - 2); } for (int i = 0; i < n; i++) { c[i + 1] = add(c[i], mul(h[i], s[i])); d[i + 1] = add(d[i], mul(k[i], s[i])); } pair<int, int> x = make_pair(0, 0); for (int i = 0; i < p; i++) { x.first = add(x.first, mul(h[i], a[i])); x.second = add(x.second, mul(k[i], a[i])); } pair<int, int> y = make_pair(0, 0); for (int i = 0; i < q; i++) { y.first = add(y.first, mul(h[i], b[i])); y.second = add(y.second, mul(k[i], b[i])); } for (int i = 0; i < n - p + 1; i++) { for (int j = i + max(0, p - q); j < n - q + 1; j++) { if (x == getHash(i, i + p) && y == getHash(j, j + q)) { memo.push_back(getHash(i, j + q)); } } } sort(memo.begin(), memo.end()); int ans = unique(memo.begin(), memo.end()) - memo.begin(); cout << ans << n ; return 0; } |
`timescale 1ns / 1ps
module quick_spi_hard_be_msb_testbench;
reg clk;
reg rst_n;
wire end_of_transaction;
wire[7:0] incoming_data;
reg[15:0] outgoing_data;
wire mosi;
reg miso;
wire sclk;
wire[1:0] ss_n;
reg enable;
reg start_transaction;
reg operation;
integer sclk_toggle_count;
reg[8:0] incoming_data_buffer;
reg spi_clock_phase;
initial begin
clk <= 1'b0;
rst_n <= 1'b0;
rst_n <= #50 1'b1;
outgoing_data <= {8'b11001100, 8'b10000010};
end
always @ (posedge clk)
begin
if(!rst_n)
begin
outgoing_data <= {8'b11001100, 8'b10000010};
enable <= 1'b1;
start_transaction <= 1'b1;
operation <= 1'b0;
miso <= 1'b0;
sclk_toggle_count <= 0;
incoming_data_buffer <= {8'b10010101, 1'b1};
spi_clock_phase <= 1'b1;
end
else
begin
if(end_of_transaction)
begin
operation <= ~operation;
sclk_toggle_count <= 0;
spi_clock_phase <= 1'b1;
incoming_data_buffer <= {8'b10010101, 1'b1};
miso <= 1'b0;
end
else
begin
if(sclk_toggle_count > 36)
begin
if(!spi_clock_phase)
begin
miso <= incoming_data_buffer[0];
incoming_data_buffer <= incoming_data_buffer >> 1;
end
end
sclk_toggle_count <= sclk_toggle_count + 1;
spi_clock_phase <= ~spi_clock_phase;
end
end
end
quick_spi_hard #
(
.BYTES_ORDER(1), // big endian,
.BITS_ORDER(1) // MSB First
)
spi
(
.clk(clk),
.reset_n(rst_n),
.enable(enable),
.start_transaction(start_transaction),
.slave(2'b01),
.operation(operation),
.end_of_transaction(end_of_transaction),
.incoming_data(incoming_data),
.outgoing_data(outgoing_data),
.mosi(mosi),
.miso(miso),
.sclk(sclk),
.ss_n(ss_n)
);
always #25 clk <= ~clk;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:05:35 06/18/2015
// Design Name:
// Module Name: gainMult
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module normMult(
input clk,
input useDiode,
input [1:0] oflowMode,
input signed [17:0] lutReg,
input signed [15:0] mixerIn,
//input signed [6:0] gain,
input signed [13:0] gain,
output reg signed [15:0] dout = 16'sd0,
output reg overflow = 1'b0
);
parameter GAIN_SCALE = 1; //sets the scale factor for the gain; e.g. 128 ADC cnts maps to 2048 at DAC for GAIN_SCALE = -4 //
parameter GAIN_OFFSET = 5; // maps ADC counts to DAC counts for the mid-range of the gain (i.e. 2^5 for 7-bit gain) // 7-bit gain //
parameter GAIN_MSB = 23;
parameter DIODE_SCALE = 4; // set to compensate the scale factor when using diode normalisation (eg. if diode =1000, sqrt(diode)~32, factor = 5 - 2 bits already included in LUT, -1 bit MSB)//
(* shreg_extract = "no" *) reg signed [15:0] mixerIn_reg = 16'sd0; // gainMult input register //
//(* shreg_extract = "no" *) reg signed [6:0] gain_reg = 7'sd0, gain_reg_b = 7'sd0; // 7-bit gain // gainMult input register //
(* shreg_extract = "no" *) reg signed [13:0] gain_reg = 14'sd0, gain_reg_b = 14'sd0; // 14-bit gain // gainMult input register //
//(* shreg_extract = "no" *) reg signed [13:0] gain_reg = 14'sd0; // 14-bit gain // gainMult input register //
//reg signed [GAIN_MSB:0] gainMult = 24'sd0; // GAIN_MSB+1'sd0, gainMult_a = GAIN_MSB+1'sd0, gainMult_b = GAIN_MSB+1'sd0, gainMult_c = GAIN_MSB+1'sd0; // 7-bit gain //
//reg signed [GAIN_MSB:0] gainMult = GAIN_MSB+1'sd0, gainMult_a = GAIN_MSB+1'sd0, gainMult_b = GAIN_MSB+1'sd0, gainMult_c = GAIN_MSB+1'sd0; // 7-bit gain //
reg signed [GAIN_MSB:0] gainMult = 31'sd0; // 14-bit gain //
wire gain_oflowDet = (~&gainMult[GAIN_MSB:GAIN_OFFSET+GAIN_SCALE+15] && ~&(~gainMult[GAIN_MSB:GAIN_OFFSET+GAIN_SCALE+15]));
(* equivalent_register_removal = "no", shreg_extract = "no" *) reg signed [17:0] lutReg_b = 18'sd0;
//(* shreg_extract = "no" *) reg signed [17:0] lutReg_c = 18'sd0; // normMult input register
(* shreg_extract = "no" *) reg signed [34:0] normMult = 35'sd0;//, normMult_reg = 35'sd0;
(* keep = "yes", shreg_extract = "no" *) reg signed [15:0] multReg = 16'sd0;//, multReg_b = 16'sd0;//, multReg_c = 16'sd0;
//(* shreg_extract = "no" *) reg signed [15:0] multReg = 16'sd0;//, multReg_b = 16'sd0;//, multReg_c = 16'sd0;
(* shreg_extract = "no" *) reg signed [15:0] multReg_b = 16'sd0;
(* shreg_extract = "no" *) reg signed [15:0] multReg_c = 16'sd0;
wire norm_oflowDet = (~&normMult[34:34-DIODE_SCALE] && ~&(~normMult[34:34-DIODE_SCALE]));
//wire [15:0] multReg;
always @(posedge clk) begin
mixerIn_reg <= mixerIn; //mult input reg
gain_reg <= gain; //mult input reg
gain_reg_b <= gain_reg; // to stop tools packing synchroniser into DSP48 (NB "keep" atribute should also do the trick ...)
//overflow <= gain_oflowDet || norm_oflowDet;
gainMult <= (mixerIn_reg * gain_reg_b);
//gainMult_a <= gainMult;
//gainMult_b <= gainMult_a;
//gainMult_c <= gainMult_b;
if (gain_oflowDet) begin
case (oflowMode)
2'b00: multReg <= gainMult[GAIN_OFFSET+GAIN_SCALE+15:GAIN_OFFSET+GAIN_SCALE]; // do nothing - ignore overflow //
2'b01: multReg <= 16'sd0; // kill output //
2'b10: multReg <= (gainMult[GAIN_MSB]) ? -16'sd32768 : 16'sd32767; // saturate output //
default: multReg <= 16'sd0;
endcase
end else multReg <= gainMult[GAIN_OFFSET+GAIN_SCALE+15:GAIN_OFFSET+GAIN_SCALE];
end
//wire oflowDet;
//gainMult #(GAIN_SCALE, GAIN_OFFSET, GAIN_MSB) gainMult(clk, oflowMode, mixerIn, gain, multReg, oflowDet);
always @(posedge clk) begin
overflow <= gain_oflowDet || norm_oflowDet;
//lutReg_b <= (useDiode) ? lutReg : {17'sd0, |lutReg}; //mult input reg
//lutReg_c <= lutReg_b;
multReg_b <= multReg;
multReg_c <= multReg_b;
lutReg_b <= lutReg;
//if (useDiode) normMult <= (multReg_b * lutReg_b);
//else normMult <= (multReg_b * |lutReg_b);
normMult <= (multReg_c * lutReg_b);
//if (useDiode) normMult <= (multReg * lutReg);
//else normMult <= (multReg * |lutReg);
//normMult_reg <= normMult;
if (norm_oflowDet) begin
case (oflowMode)
2'b00: dout <= (useDiode) ? normMult[34-DIODE_SCALE:34-DIODE_SCALE-15] : normMult[15:0]; // do nothing - ignore overflow //
2'b01: dout <= 16'sd0; // kill output //
2'b10: dout <= (normMult[34]) ? -16'sd32768 : 16'sd32767; // saturate output //
default: dout <= 16'sd0;
endcase
end else dout <= (useDiode) ? normMult[34-DIODE_SCALE:34-DIODE_SCALE-15] : normMult[15:0];
//dout <= (useDiode) ? normMult[34-DIODE_SCALE:34-DIODE_SCALE-15] : normMult[15:0];
end
endmodule
|
#include<bits/stdc++.h> using namespace std; #define sz(s) (int)s.size() #define f first #define s second #define pb push_back #define all(s) s.begin(), s.end() #define vi vector<int> #define vvi vector<vi> #define ll long long #define vll vector<ll> #define ii pair<int, int> #define vii vector<ii> #define vvii vector<vii> const int INF = 1e9 + 7; const int mod = 1e9 + 7; const int N = 1e6 + 7; const int T = 1 << 20; #define ld long double int n; int suma[T + T]; int maxi[T + T]; void set_val(int poz, int val){ poz += T; suma[poz] = val; maxi[poz] = max(val, 0); poz /= 2; while(poz > 0){ suma[poz] = suma[poz + poz] + suma[poz + poz + 1]; maxi[poz] = max(maxi[poz + poz + 1], suma[poz + poz + 1] + maxi[poz + poz]); poz /= 2; } } int max_suf(int poz){ poz += T; int ret = 1; int temp_suma = 1; while(poz > 0){ if(poz % 2 == 1){ ret = max(ret, maxi[poz - 1] + temp_suma); temp_suma += suma[poz - 1]; } poz /= 2; } return ret; } vector<int> policz(vector<int> tab){ for(auto & u : tab) assert(u >= 0 and u <= n); for(int i = 0; i < T + T; i++) suma[i] = maxi[i] = 0; for(int i = T; i < T + n; i++) suma[i] = maxi[i] = 1; for(int i = T - 1; i > 0; i--) suma[i] = maxi[i] = suma[i + i] + suma[i + i + 1]; vector<vector<int> > values(n + 1); for(int i = 0; i < n; i++) values[tab[i]].pb(i); vector<int> ret(n); for(int i = 0; i <= n; i++){ for(auto & poz : values[i]) ret[poz] = max_suf(poz); for(auto & poz : values[i]) set_val(poz, -1); } return ret; } void solve(){ cin >> n; vector<int> tab(n); for(int i = 0; i < n; i++) cin >> tab[i]; // for(auto & u : tab) // cout << u << ; // cout << endl; vector<int> ans(n); for(int faza = 0; faza < 2; faza++){ // cout << Tab: ; // for(auto & u : tab) // cout << u << ; // cout << endl; auto a = policz(tab); reverse(all(tab)); auto b = policz(tab); reverse(all(b)); reverse(all(tab)); // cout << a : ; // for(auto & u : a) // cout << u << ; // cout << endl; // cout << b : ; // for(auto & u : b) // cout << u << ; // cout << endl; for(int i = 0; i < n; i++) ans[i] = max(ans[i], (a[i] + b[i] - 1 - faza) / 2); for(auto & u : tab) u = -u + n; } for(int i = 0; i < n; i++) cout << ans[i] << ; cout << n ; } signed main(){ ios::sync_with_stdio(0); cin.tie(0); int test = 1; // cin >> test; for(int i = 0; i < test; i++) solve(); } |
`timescale 1 ns / 1 ps
module axis_ram_writer #
(
parameter integer ADDR_WIDTH = 20,
parameter integer AXI_ID_WIDTH = 6,
parameter integer AXI_ADDR_WIDTH = 32,
parameter integer AXI_DATA_WIDTH = 64,
parameter integer AXIS_TDATA_WIDTH = 64
)
(
// System signals
input wire aclk,
input wire aresetn,
input wire [AXI_ADDR_WIDTH-1:0] cfg_data,
output wire [ADDR_WIDTH-1:0] sts_data,
// Master side
output wire [AXI_ID_WIDTH-1:0] m_axi_awid, // AXI master: Write address ID
output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr, // AXI master: Write address
output wire [3:0] m_axi_awlen, // AXI master: Write burst length
output wire [2:0] m_axi_awsize, // AXI master: Write burst size
output wire [1:0] m_axi_awburst, // AXI master: Write burst type
output wire [3:0] m_axi_awcache, // AXI master: Write memory type
output wire m_axi_awvalid, // AXI master: Write address valid
input wire m_axi_awready, // AXI master: Write address ready
output wire [AXI_ID_WIDTH-1:0] m_axi_wid, // AXI master: Write data ID
output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata, // AXI master: Write data
output wire [AXI_DATA_WIDTH/8-1:0] m_axi_wstrb, // AXI master: Write strobes
output wire m_axi_wlast, // AXI master: Write last
output wire m_axi_wvalid, // AXI master: Write valid
input wire m_axi_wready, // AXI master: Write ready
input wire m_axi_bvalid, // AXI master: Write response valid
output wire m_axi_bready, // AXI master: Write response ready
// Slave side
output wire s_axis_tready,
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid
);
function integer clogb2 (input integer value);
for(clogb2 = 0; value > 0; clogb2 = clogb2 + 1) value = value >> 1;
endfunction
localparam integer ADDR_SIZE = clogb2((AXI_DATA_WIDTH/8)-1);
reg int_awvalid_reg, int_awvalid_next;
reg int_wvalid_reg, int_wvalid_next;
reg [ADDR_WIDTH-1:0] int_addr_reg, int_addr_next;
reg [AXI_ID_WIDTH-1:0] int_wid_reg, int_wid_next;
wire int_full_wire, int_empty_wire, int_rden_wire;
wire int_wlast_wire, int_tready_wire;
wire [71:0] int_wdata_wire;
assign int_tready_wire = ~int_full_wire;
assign int_wlast_wire = &int_addr_reg[3:0];
assign int_rden_wire = m_axi_wready & int_wvalid_reg;
FIFO36E1 #(
.FIRST_WORD_FALL_THROUGH("TRUE"),
.ALMOST_EMPTY_OFFSET(13'hf),
.DATA_WIDTH(72),
.FIFO_MODE("FIFO36_72")
) fifo_0 (
.FULL(int_full_wire),
.ALMOSTEMPTY(int_empty_wire),
.RST(~aresetn),
.WRCLK(aclk),
.WREN(int_tready_wire & s_axis_tvalid),
.DI({{(72-AXIS_TDATA_WIDTH){1'b0}}, s_axis_tdata}),
.RDCLK(aclk),
.RDEN(int_rden_wire),
.DO(int_wdata_wire)
);
always @(posedge aclk)
begin
if(~aresetn)
begin
int_awvalid_reg <= 1'b0;
int_wvalid_reg <= 1'b0;
int_addr_reg <= {(ADDR_WIDTH){1'b0}};
int_wid_reg <= {(AXI_ID_WIDTH){1'b0}};
end
else
begin
int_awvalid_reg <= int_awvalid_next;
int_wvalid_reg <= int_wvalid_next;
int_addr_reg <= int_addr_next;
int_wid_reg <= int_wid_next;
end
end
always @*
begin
int_awvalid_next = int_awvalid_reg;
int_wvalid_next = int_wvalid_reg;
int_addr_next = int_addr_reg;
int_wid_next = int_wid_reg;
if(~int_empty_wire & ~int_awvalid_reg & ~int_wvalid_reg)
begin
int_awvalid_next = 1'b1;
int_wvalid_next = 1'b1;
end
if(m_axi_awready & int_awvalid_reg)
begin
int_awvalid_next = 1'b0;
end
if(int_rden_wire)
begin
int_addr_next = int_addr_reg + 1'b1;
end
if(m_axi_wready & int_wlast_wire)
begin
int_wid_next = int_wid_reg + 1'b1;
if(int_empty_wire)
begin
int_wvalid_next = 1'b0;
end
else
begin
int_awvalid_next = 1'b1;
end
end
end
assign sts_data = int_addr_reg;
assign m_axi_awid = int_wid_reg;
assign m_axi_awaddr = cfg_data + {int_addr_reg, {(ADDR_SIZE){1'b0}}};
assign m_axi_awlen = 4'd15;
assign m_axi_awsize = ADDR_SIZE;
assign m_axi_awburst = 2'b01;
assign m_axi_awcache = 4'b1111;
assign m_axi_awvalid = int_awvalid_reg;
assign m_axi_wid = int_wid_reg;
assign m_axi_wdata = int_wdata_wire[AXI_DATA_WIDTH-1:0];
assign m_axi_wstrb = {(AXI_DATA_WIDTH/8){1'b1}};
assign m_axi_wlast = int_wlast_wire;
assign m_axi_wvalid = int_wvalid_reg;
assign m_axi_bready = 1'b1;
assign s_axis_tready = int_tready_wire;
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cpu_jtag_debug_module_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx0;
wire unxcomplemented_resetxx1;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 12] <= 1'b0;
sr[11 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx0 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx0)
);
defparam the_altera_std_synchronizer.depth = 2;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long infll = powl(2, 63) - 1; struct cup { long long a, b, c; }; bool comp(cup x, cup y) { return x.c < y.c; } bool cmp1(cup x, cup y) { if (x.a == y.a) return x.c < y.c; return x.a > y.a; } int32_t main() { long long n, tea; cin >> n >> tea; vector<cup> arr(n); for (long long i = 0; i < (long long)(n); ++i) cin >> arr[i].a; for (long long i = 0; i < (long long)(n); ++i) { arr[i].b = ceil(arr[i].a / 2.0); arr[i].c = i; tea -= arr[i].b; if (tea < 0) { cout << -1 << endl; return 0; } } sort((arr).begin(), (arr).end(), cmp1); for (long long i = 0; i < (long long)(n); ++i) { long long temp = min(tea, arr[i].a - arr[i].b); arr[i].b += temp; tea -= temp; if (tea == 0) break; } sort((arr).begin(), (arr).end(), comp); for (long long i = 0; i < (long long)(n); ++i) cout << arr[i].b << ; cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, k, m; int a[111]; int c[111][111]; long long dp[111][111][111]; long long f(int idx, int cnt, int last) { if (idx > n) return cnt == k ? 0 : 1e13; if (dp[idx][cnt][last] != -1) return dp[idx][cnt][last]; long long ans = 1e13; if (a[idx]) ans = min(ans, f(idx + 1, cnt + (a[idx] == last ? 0 : 1), a[idx])); else { for (int i = 1; i <= m; i++) ans = min(ans, f(idx + 1, cnt + (last == i ? 0 : 1), i) + c[idx][i]); } return dp[idx][cnt][last] = ans; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); memset(dp, -1, sizeof dp); cin >> n >> m >> k; for (int i = 1; i <= n; i++) cin >> a[i]; a[0] = 111; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) cin >> c[i][j]; long long ans = f(1, 0, 111); if (ans > 1e12) cout << -1; else cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5, M = 20; int n, m; string s; int pos[(1 << M) - 1], a[M + 5][M + 5], f[(1 << M) + 5], g[(1 << M) + 5][M + 5]; int main() { memset(a, 0, sizeof(a)); memset(f, 0x3f, sizeof(f)); memset(g, 0, sizeof(g)); cin >> n >> m >> s; for (int i = 0; i < n - 1; i++) { a[s[i] - a ][s[i + 1] - a ]++; a[s[i + 1] - a ][s[i] - a ]++; } for (int i = 0; i < m; i++) pos[1 << i] = i; for (int i = 1; i < (1 << m); i++) for (int j = 0; j < m; j++) { int k = i & (-i); g[i][j] = g[i ^ k][j] + a[j][pos[k]]; } f[0] = 0; for (int i = 0; i < (1 << m) - 1; i++) { long long sum = 0; for (int j = 0; j < m; j++) if ((i & (1 << j)) == 0) sum += g[i][j]; for (int j = 0; j < m; j++) if ((i & (1 << j)) == 0) f[i | (1 << j)] = min(f[i] + sum, (long long)f[i | (1 << j)]); } cout << f[(1 << m) - 1]; return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (lin64) Build Wed Dec 14 22:35:42 MST 2016
// Date : Sat Jan 21 14:43:33 2017
// Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mult_17x16_stub.v
// Design : mult_17x16
// Purpose : Stub declaration of top-level module interface
// Device : xcku035-fbva676-3-e
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "mult_gen_v12_0_12,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(CLK, A, B, P)
/* synthesis syn_black_box black_box_pad_pin="CLK,A[16:0],B[15:0],P[24:0]" */;
input CLK;
input [16:0]A;
input [15:0]B;
output [24:0]P;
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T, typename U> std::pair<T, U> operator+(const std::pair<T, U> &l, const std::pair<T, U> &r) { return {l.first + r.first, l.second + r.second}; } typedef void (*callback_function)(void); const long long INF64 = 1e18; const long long INF32 = 1e9; long long dist(pair<long long, long long> &a, pair<long long, long long> &b) { return abs(a.first - b.first) + abs(a.second - b.second); } long long dist(pair<long long, long long> &a) { return abs(a.first) + abs(a.second); } int main() { ios_base::sync_with_stdio(false); cin.tie(); { long long n; string s; cin >> n >> s; long long res = 1; bool first[2] = {true, true}; char hv[2]; string HV[2] = { LR , DU }; for (long long i = (0); i < (s.length()); i++) { for (long long j = (0); j < (2); j++) { if (HV[j].find(s[i]) != string::npos) { if (first[j]) { first[j] = false; hv[j] = s[i]; } else if (hv[j] != s[i]) { first[1 - j] = true; res++; hv[j] = s[i]; } break; } } } cout << res << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; struct node { int i; int num; } a[1005]; bool cmp(node x, node y) { return x.num < y.num; } int main() { int t; scanf( %d , &t); while (t--) { int n, m; scanf( %d %d , &n, &m); int i, j; int ans = 0; for (i = 1; i <= n; i++) { scanf( %d , &a[i].num); a[i].i = i; ans += a[i].num; } if (m < n || n <= 2) { printf( -1 n ); continue; } ans *= 2; sort(a + 1, a + 1 + n, cmp); int num = a[1].num + a[2].num; ans += (m - n) * num; printf( %d n , ans); for (i = 2; i <= n; i++) { printf( %d %d n , i - 1, i); } printf( 1 %d n , n); for (i = 0; i < (m - n); i++) { if (a[1].i > a[2].i) printf( %d %d n , a[2].i, a[1].i); else printf( %d %d n , a[1].i, a[2].i); } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A221O_TB_V
`define SKY130_FD_SC_MS__A221O_TB_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a221o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 B2 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 B2 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B2 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B2 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ms__a221o dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A221O_TB_V
|
#include <bits/stdc++.h> using namespace std; const int N = 20; int a[N], b[N], c[N], d[N], ln[N], rn[N], lm[N], rm[N]; int main() { int n, m; cin >> n >> m; for (int i = 1; i <= n; i++) { cin >> a[i] >> b[i]; if (a[i] > b[i]) swap(a[i], b[i]); } set<int> st; for (int i = 1; i <= m; i++) { cin >> c[i] >> d[i]; if (c[i] > d[i]) swap(c[i], d[i]); for (int j = 1; j <= n; j++) { if (a[j] == c[i] && b[j] == d[i]) continue; if (a[j] == c[i]) ln[j] = lm[i] = 1, st.insert(a[j]); if (a[j] == d[i]) ln[j] = rm[i] = 1, st.insert(a[j]); if (b[j] == c[i]) rn[j] = lm[i] = 1, st.insert(b[j]); if (b[j] == d[i]) rn[j] = rm[i] = 1, st.insert(b[j]); } } for (int i = 1; i <= n; i++) if (ln[i] && rn[i]) { puts( -1 ); return 0; } for (int i = 1; i <= m; i++) if (lm[i] && rm[i]) { puts( -1 ); return 0; } if (st.size() == 1) { cout << *st.begin(); return 0; } puts( 0 ); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR2B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__OR2B_BEHAVIORAL_PP_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__or2b (
X ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , B_N );
or or0 (or0_out_X , not0_out, A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR2B_BEHAVIORAL_PP_V |
// This is a component of pluto_servo, a PWM servo driver and quadrature
// counter for emc2
// Copyright 2006 Jeff Epler <>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
module main(clk, led, nConfig, epp_nReset, pport_data, nWrite, nWait, nDataStr,
nAddrStr, dout, din, step, dir);
parameter W=10;
parameter F=11;
parameter T=4;
input clk;
output led, nConfig;
inout [7:0] pport_data;
input nWrite;
output nWait;
input nDataStr, nAddrStr, epp_nReset;
input [15:0] din;
reg Spolarity;
reg[13:0] real_dout; output [13:0] dout = do_tristate ? 14'bZ : real_dout;
wire[3:0] real_step; output [3:0] step = do_tristate ? 4'bZ : real_step ^ {4{Spolarity}};
wire[3:0] real_dir; output [3:0] dir = do_tristate ? 4'bZ : real_dir;
wire [W+F-1:0] pos0, pos1, pos2, pos3;
reg [F:0] vel0, vel1, vel2, vel3;
reg [T-1:0] dirtime, steptime;
reg [1:0] tap;
reg [10:0] div2048;
wire stepcnt = ~|(div2048[5:0]);
always @(posedge clk) begin
div2048 <= div2048 + 1'd1;
end
wire do_enable_wdt, do_tristate;
wdt w(clk, do_enable_wdt, &div2048, do_tristate);
stepgen #(W,F,T) s0(clk, stepcnt, pos0, vel0, dirtime, steptime, real_step[0], real_dir[0], tap);
stepgen #(W,F,T) s1(clk, stepcnt, pos1, vel1, dirtime, steptime, real_step[1], real_dir[1], tap);
stepgen #(W,F,T) s2(clk, stepcnt, pos2, vel2, dirtime, steptime, real_step[2], real_dir[2], tap);
stepgen #(W,F,T) s3(clk, stepcnt, pos3, vel3, dirtime, steptime, real_step[3], real_dir[3], tap);
// EPP stuff
wire EPP_write = ~nWrite;
wire EPP_read = nWrite;
wire EPP_addr_strobe = ~nAddrStr;
wire EPP_data_strobe = ~nDataStr;
wire EPP_strobe = EPP_data_strobe | EPP_addr_strobe;
wire EPP_wait; assign nWait = ~EPP_wait;
wire [7:0] EPP_datain = pport_data;
wire [7:0] EPP_dataout; assign pport_data = EPP_dataout;
reg [4:0] EPP_strobe_reg;
always @(posedge clk) EPP_strobe_reg <= {EPP_strobe_reg[3:0], EPP_strobe};
wire EPP_strobe_edge1 = (EPP_strobe_reg[2:1]==2'b01);
// reg led;
assign EPP_wait = EPP_strobe_reg[4];
wire[15:0] EPP_dataword = {EPP_datain, lowbyte};
reg[4:0] addr_reg;
reg[7:0] lowbyte;
always @(posedge clk)
if(EPP_strobe_edge1 & EPP_write & EPP_addr_strobe) begin
addr_reg <= EPP_datain[4:0];
end
else if(EPP_strobe_edge1 & !EPP_addr_strobe) addr_reg <= addr_reg + 4'd1;
always @(posedge clk) begin
if(EPP_strobe_edge1 & EPP_write & EPP_data_strobe) begin
if(addr_reg[3:0] == 4'd1) vel0 <= EPP_dataword[F:0];
else if(addr_reg[3:0] == 4'd3) vel1 <= EPP_dataword[F:0];
else if(addr_reg[3:0] == 4'd5) vel2 <= EPP_dataword[F:0];
else if(addr_reg[3:0] == 4'd7) vel3 <= EPP_dataword[F:0];
else if(addr_reg[3:0] == 4'd9) begin
real_dout <= { EPP_datain[5:0], lowbyte };
end
else if(addr_reg[3:0] == 4'd11) begin
tap <= lowbyte[7:6];
steptime <= lowbyte[T-1:0];
Spolarity <= EPP_datain[7];
// EPP_datain[6] is do_enable_wdt
dirtime <= EPP_datain[T-1:0];
end
else lowbyte <= EPP_datain;
end
end
reg [31:0] data_buf;
always @(posedge clk) begin
if(EPP_strobe_edge1 & EPP_read && addr_reg[1:0] == 2'd0) begin
if(addr_reg[4:2] == 3'd0) data_buf <= pos0;
else if(addr_reg[4:2] == 3'd1) data_buf <= pos1;
else if(addr_reg[4:2] == 3'd2) data_buf <= pos2;
else if(addr_reg[4:2] == 3'd3) data_buf <= pos3;
else if(addr_reg[4:2] == 3'd4)
data_buf <= din;
end
end
// the addr_reg test looks funny because it is auto-incremented in an always
// block so "1" reads the low byte, "2 and "3" read middle bytes, and "0"
// reads the high byte I have a feeling that I'm doing this in the wrong way.
wire [7:0] data_reg = addr_reg[1:0] == 2'd1 ? data_buf[7:0] :
(addr_reg[1:0] == 2'd2 ? data_buf[15:8] :
(addr_reg[1:0] == 2'd3 ? data_buf[23:16] :
data_buf[31:24]));
wire [7:0] EPP_data_mux = data_reg;
assign EPP_dataout = (EPP_read & EPP_wait) ? EPP_data_mux : 8'hZZ;
// assign do_enable_wdt = EPP_strobe_edge1 & EPP_write & EPP_data_strobe & (addr_reg[3:0] == 4'd9) & EPP_datain[6];
// assign led = do_tristate ? 1'BZ : (real_step[0] ^ real_dir[0]);
assign led = do_tristate ? 1'bZ : (real_step[0] ^ real_dir[0]);
assign nConfig = epp_nReset; // 1'b1;
assign do_enable_wdt = EPP_strobe_edge1 & EPP_write & EPP_data_strobe & (addr_reg[3:0] == 4'd9) & EPP_datain[6];
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T1> void deb(T1 e) { cout << e << endl; } template <class T1, class T2> void deb(T1 e1, T2 e2) { cout << e1 << << e2 << endl; } template <class T1, class T2, class T3> void deb(T1 e1, T2 e2, T3 e3) { cout << e1 << << e2 << << e3 << endl; } template <class T1, class T2, class T3, class T4> void deb(T1 e1, T2 e2, T3 e3, T4 e4) { cout << e1 << << e2 << << e3 << << e4 << endl; } template <class T1, class T2, class T3, class T4, class T5> void deb(T1 e1, T2 e2, T3 e3, T4 e4, T5 e5) { cout << e1 << << e2 << << e3 << << e4 << << e5 << endl; } template <class T1, class T2, class T3, class T4, class T5, class T6> void deb(T1 e1, T2 e2, T3 e3, T4 e4, T5 e5, T6 e6) { cout << e1 << << e2 << << e3 << << e4 << << e5 << << e6 << endl; } template <class T> T Abs(T x) { return x > 0 ? x : -x; } template <class T> inline T sqr(T x) { return x * x; } long long Pow(long long B, long long P) { long long R = 1; while (P > 0) { if (P % 2 == 1) R = (R * B); P /= 2; B = (B * B); } return R; } long long BigMod(long long B, long long P, long long M) { long long R = 1; while (P > 0) { if (P % 2 == 1) { R = (R * B) % M; } P /= 2; B = (B * B) % M; } return R; } long long n, m; vector<pair<long long, long long> > v; long long mod = 1000000007LL; long long stree[4 * 200050]; map<long long, int> M; set<long long> S; void update(int node, int left, int right, int pos, long long val) { if (pos < left || right < pos) return; if (left == right) { stree[node] = val; return; } int mid = (left + right) / 2; update(node * 2, left, mid, pos, val); update(node * 2 + 1, mid + 1, right, pos, val); stree[node] = stree[node * 2] % mod + stree[node * 2 + 1] % mod; return; } long long query(int node, int left, int right, int srch_l, int srch_r) { if (srch_l <= left && right <= srch_r) return stree[node]; if (right < srch_l || left > srch_r) return 0; int mid = (left + right) / 2; long long ret1 = query(node * 2, left, mid, srch_l, srch_r); ret1 %= mod; long long ret2 = query(node * 2 + 1, mid + 1, right, srch_l, srch_r); ret2 %= mod; long long ret = (ret1 + ret2) % mod; return ret; } vector<int> adj[200050]; int main(void) { long long a, b; cin >> n >> m; for (int i = 0; i < m; i++) { cin >> a >> b, v.push_back(make_pair(a, b)); S.insert(a); S.insert(b); } S.insert(0); S.insert(n); int track = 0; for (__typeof((S).begin()) it = (S.begin()); it != (S).end(); ++it) M[*it] = track++; n = (int)M.size() - 1; update(1, 0, n, 0, 1); for (int i = 0; i < (int)v.size(); i++) { long long right = v[i].second; right = M[right]; adj[right].push_back(i); } for (int i = 1; i < (int)M.size(); i++) { long long val = 0; for (int j = 0; j < (int)adj[i].size(); j++) { int indx = adj[i][j]; int left = v[indx].first; int right = v[indx].second; left = M[left]; right = M[right]; val += query(1, 0, n, left, right); val %= mod; } update(1, 0, n, i, val); } deb(query(1, 0, n, n, n)); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DIODE_BLACKBOX_V
`define SKY130_FD_SC_LP__DIODE_BLACKBOX_V
/**
* diode: Antenna tie-down diode.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__diode (
DIODE
);
input DIODE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DIODE_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const long long int maxn = 2e5 + 5; long long int sz[maxn], dp[maxn], ans[maxn]; vector<long long int> g[maxn]; long long int n; long long int dp1(long long int node, long long int parent) { sz[node] = 1; for (auto& itr : g[node]) if (itr != parent) sz[node] += dp1(itr, node); return sz[node]; } long long int dp2(long long int node, long long int parent) { dp[node] = sz[node]; for (auto& itr : g[node]) if (itr != parent) dp[node] += dp2(itr, node); return dp[node]; } void dp3(long long int node, long long int parent, long long int fromParent = 0) { if (parent == -1) ans[node] = dp[node]; else ans[node] = n - 2 * sz[node] + ans[parent]; for (auto& itr : g[node]) if (itr != parent) dp3(itr, node); } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n; for (long long int i = 1; i < n; i++) { long long int u, v; cin >> u >> v; g[u].push_back(v); g[v].push_back(u); } dp1(1, -1); dp2(1, -1); dp3(1, -1); long long int answer = 0; for (long long int i = 1; i <= n; i++) answer = max(answer, ans[i]); cout << answer; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long int n, m, j = 0, ans = 0; cin >> n >> m; string s; cin >> s; set<char> st; vector<long long int> vec; for (long long int i = 0; i < m; i++) { char c; cin >> c; st.insert(c); } for (long long int i = 0; i < n; i++) { if (st.count(s[i])) { j++; } if (!st.count(s[i])) { ans += (j * (j + 1)) / 2; j = 0; } } if (j > 0) { ans += (j * (j + 1)) / 2; } cout << ans; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21BO_SYMBOL_V
`define SKY130_FD_SC_LS__A21BO_SYMBOL_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a21bo (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21BO_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long a, b, c, d, e, t1, t2, t3; long long la, lb, lc; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n, m, s; cin >> n >> m >> s; a = 0; b = 0; long long i = 0; c = 1; if (s <= n) { while (i < n) { if (i + s < n) { i += s; ++c; } else { a = n - (i + 1); ++a; break; } } } else { c = n; a = 1; } i = 0; d = 1; if (s <= m) { while (i < m) { if (i + s < m) { i += s; ++d; } else { b = m - (i + 1); ++b; break; } } } else { d = m; b = 1; } e = c * d; t1 = a * b; cout << t1 * e; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = int(1.5 * 1e7); const int inf = 1e9 + 7; const long long ll_inf = 1e18 + 420; const double eps = 1e-4; const int N = 1e6; const int MAX = 2e5 + 9; const int MOD = 1e9 + 7; const long double pi = 3.14159265359; string s; bool was[10][10]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> s; for (int i0 = 0; i0 < s.size(); ++i0) { int cnt = 0; for (int i = 1; i <= 4; ++i, cnt = 0) { for (int j = 1; j <= 4; ++j) { cnt += was[i][j]; } if (cnt == 4) { for (int j = 1; j <= 4; ++j) { was[i][j] = 0; } } } for (int i = 1; i <= 4; ++i, cnt = 0) { for (int j = 1; j <= 4; ++j) { cnt += was[j][i]; } if (cnt == 4) { for (int j = 1; j <= 4; ++j) { was[j][i] = 0; } } } if (s[i0] == 1 ) { bool q = 0; for (int i = 1; i <= 4; ++i) { for (int j = 1; j <= 3; ++j) { if (!was[i][j] && !was[i][j + 1]) { was[i][j] = 1; was[i][j + 1] = 1; cout << i << << j << n ; q = 1; break; } } if (q) break; } } else { bool q = 0; for (int i = 1; i <= 4; ++i) { for (int j = 1; j <= 3; ++j) { if (!was[j][i] && !was[j + 1][i]) { was[j][i] = 1; was[j + 1][i] = 1; cout << j << << i << n ; q = 1; break; } } if (q) break; } } } } |
#include <bits/stdc++.h> using namespace std; long long mod = 1000000007; long long qpow(long long x, long long tms) { long long tmp = 1; while (tms) { if (tms & 1) tmp = tmp * x % mod; tms >>= 1; x = x * x % mod; } return tmp; } int n, m, T; bool chk(int k) { if (n == 1) return 1; long long sum = 1, t = (long long)k * m; double C = 1; long long s = 1; for (int i = 1; i <= k; ++i) { long long x = t / i, y = mod; if (x == 0) return 0; C = C * (k - i + 1) / i; s = s * (k - i + 1) % mod * qpow(i, mod - 2) % mod; if (C < mod) y = s; x = min(x, y); sum += x; if (sum >= n) return 1; t -= x * i; } return 0; } int main() { scanf( %d , &T); while (T--) { scanf( %d%d , &n, &m); int l = 0, r = n; while (l < r) { int mid = (l + r) >> 1; if (chk(mid)) r = mid; else l = mid + 1; } printf( %d n , l); } } |
`timescale 1ns/10ps
module pll_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("normal"),
.number_of_clocks(1),
.output_clock_frequency0("5.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("0 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
/*
* Copyright (c) 2002 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This program tests the ability to take bit and part selects
* of parameters. This is actually not legal in Verilog, but
* Icarus Verilog supports it anyhow, as do many (most?) other
* Verilog compilers.
*/
module main;
parameter vec = 16'b0000_1001_0111_1010;
initial begin
if (vec[0] !== 0) begin
$display("FAILED -- %b[0] !== 0", vec);
$finish;
end
if (vec[1] !== 1) begin
$display("FAILED -- %b[1] !== 1", vec);
$finish;
end
if (vec[3:1] !== 3'b101) begin
$display("FAILED -- %b[3:1] !== b101", vec);
$finish;
end
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> const int N = 1e5 + 10; const int MOD = 1e9 + 7; const int INF = 2e9; const long long INFLL = 1e18; const double PI = acos((double)-1); inline int mult(int a, int b, int p = MOD) { return (1ll * a * b) % p; } inline int add(int a, int b, int p = MOD) { return (1ll * a + b) % p; } inline int fpow(long long n, long long k, int p = MOD) { long long r = 1; for (; k; k >>= 1) { if (k & 1) r = r * n % p; n = n * n % p; } return r; } inline int inv(int a, int p = MOD) { return fpow(a, p - 2, p); } using namespace std; int s, x1, x2, t1, t2, p, ok; int f[10000][2]; bool d; int main() { ios::sync_with_stdio(false); cin >> s >> x1 >> x2; cin >> t1 >> t2; cin >> p >> ok; if (ok == -1) d = 0; else d = 1; int ans = abs(x2 - x1) * t2; f[p][d] = 0; if (d == 0) { for (int i = p - 1; i >= 0; i--) f[i][d] = f[i + 1][d] + t1; f[0][!d] = f[0][d]; d = !d; for (int i = 1; i <= s; i++) f[i][d] = f[i - 1][d] + t1; f[s][!d] = f[s][d]; d = !d; for (int i = s - 1; i > p; i--) f[i][d] = f[i + 1][d] + t1; } else { for (int i = p + 1; i <= s; i++) f[i][d] = f[i - 1][d] + t1; f[s][!d] = f[s][d]; d = !d; for (int i = s - 1; i >= 0; i--) f[i][d] = f[i + 1][d] + t1; f[0][!d] = f[0][d]; d = !d; for (int i = 1; i < p; i++) f[i][d] = f[i - 1][d] + t1; } if (x1 > x2) { for (int i = x2 + 1; i <= x1; i++) { if (f[i][0] < (x1 - i) * t2) f[i][0] += s * 2 * t1; int x = (i - x2) * t1 + f[i][0]; ans = min(ans, x); } } else { for (int i = x2 - 1; i >= x1; i--) { if (f[i][1] < (i - x1) * t2) f[i][1] += s * 2 * t1; int x = (x2 - i) * t1 + f[i][1]; ans = min(ans, x); } } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int a[150005]; int main() { int n, k, q; scanf( %d %d %d , &n, &k, &q); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); } multiset<int> t; for (int i = 1; i <= q; i++) { int x, y; scanf( %d %d , &x, &y); if (x == 1) { t.insert(a[y]); if ((int)t.size() > k) { t.erase(t.begin()); } } else { auto it = t.find(a[y]); printf(it != t.end() ? YES n : NO n ); } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = 1e9; const long long inf64 = 1e18; void solve() { int n, m; cin >> n >> m; vector<vector<int>> a(n, vector<int>(m)), b; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) cin >> a[i][j]; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { int c = 0; if (i > 0) c++; if (j > 0) c++; if (i + 1 < n) c++; if (j + 1 < m) c++; if (a[i][j] > c) { cout << NO n ; return; } a[i][j] = c; } } cout << YES n ; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cout << a[i][j] << ; } cout << n ; } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int tt; cin >> tt; while (tt--) solve(); return 0; } |
`define bsg_mul_booth_gen_macro(name,blocks,S_above,dot_bar,b_vec,one_vec) \
if ( blocks == blocks_p && S_above == S_above_vec_p \
&& dot_bar == dot_bar_vec_p && b_vec == B_vec_p && one_vec == one_vec_p) \
begin : macro \
name``_b``blocks b4b (.*); \
end
module bsg_mul_booth_4_block_rep #(parameter [31:0] blocks_p=1
,parameter S_above_vec_p=0
,parameter dot_bar_vec_p=0
,parameter B_vec_p=0
,parameter one_vec_p=0
)
( input [4:0][2:0] SDN_i
, input cr_i
, input [blocks_p-1:0][3:0][1:0] y_vec_i
, output cl_o
, output [blocks_p-1:0] c_o
, output [blocks_p-1:0] s_o
);
genvar i;
wire [blocks_p:0] ci_local;
`bsg_mul_booth_gen_macro(bsg_rp_tsmc_40_booth_4_block,5,0,0,0,0)
else `bsg_mul_booth_gen_macro(bsg_rp_tsmc_40_booth_4_block,6,0,0,0,0)
else `bsg_mul_booth_gen_macro(bsg_rp_tsmc_40_booth_4_block,7,0,0,0,0)
else `bsg_mul_booth_gen_macro(bsg_rp_tsmc_40_booth_4_block,8,0,0,0,0)
else `bsg_mul_booth_gen_macro(bsg_rp_tsmc_40_booth_4_block_cornice,8,32'b0000_1000_0000_0100_0000_0010_0000_0001,32'b0000_0000_0000_0000_0000_0000_0000_0000,32'b1000_0000_1100_1000_1110_1100_1111_1110,32'b0000_0000_0000_0000_0000_0000_0000_0000)
else `bsg_mul_booth_gen_macro(bsg_rp_tsmc_40_booth_4_block_cornice,6,24'b0000_1000_0000_0100_0000_0010,24'b0000_0000_0000_0000_0000_0000,24'b1000_0000_1100_1000_1110_1100,24'b0000_0000_0000_0000_0000_0000)
else `bsg_mul_booth_gen_macro(bsg_rp_tsmc_40_booth_4_block_end_cornice,7,28'b0000_0000_0000_0000_0000_0000_0000,28'b1000_0000_0100_0000_0010_0000_0001,28'b0111_0011_0011_0001_0001_0000_0000,28'b0000_0100_0000_0010_0000_0001_0000)
else `bsg_mul_booth_gen_macro(bsg_rp_tsmc_40_booth_4_block_end_cornice,8,32'b0000_0000_0000_0000_0000_0000_0000_0000,32'b0000_1000_0000_0100_0000_0010_0000_0001,32'b0111_0111_0011_0011_0001_0001_0000_0000,32'b1000_0000_0100_0000_0010_0000_0001_0000)
else
// some cases are too complex to spend time on handling;
// so we fall back to some default code.
// warning: this code has some replication with
// the main line bsg_mul code.
begin: notmacro
for (i = 0; i < blocks_p; i=i+1)
begin: rof
localparam S_above_vec_tmp = (S_above_vec_p >> (i << 2)) & 4'hf;
localparam S_dot_bar_vec_tmp = (dot_bar_vec_p >> (i << 2)) & 4'hf;
localparam B_vec_tmp = (B_vec_p >> (i << 2)) & 4'hf;
localparam one_vec_tmp = (one_vec_p >> (i << 2)) & 4'hf;
bsg_mul_booth_4_block #(
.S_above_vec_p(S_above_vec_tmp)
,.dot_bar_vec_p(S_dot_bar_vec_tmp)
,.B_vec_p(B_vec_tmp)
,.one_vec_p(one_vec_tmp)
)
b4b (.SDN_i(SDN_i), .y_i (y_vec_i[i])
, .cr_i(ci_local[i]), .cl_o(ci_local[i+1]), .c_o (c_o[i]), .s_o (s_o[i]));
end // block: rof
assign ci_local[0] = cr_i;
assign cl_o = ci_local[blocks_p];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const long long MAXN = 2e5 + 7; long long a[MAXN]; bool good[MAXN]; long long want[MAXN], pref[MAXN], next_[MAXN]; signed main() { ios_base::sync_with_stdio(false); cout.precision(40); long long n; cin >> n; for (long long i = 0; i < n; ++i) { cin >> a[i]; } stack<long long> st; for (long long i = 0; i < n; ++i) { while (st.size() && a[st.top()] < a[i]) { next_[st.top()] = i; st.pop(); } st.push(i); } while (st.size()) { next_[st.top()] = n; st.pop(); } long long mx1 = -MOD; long long mx2 = -MOD; for (long long i = 0; i < n; ++i) { if (a[i] < mx1 && a[i] > mx2) { want[i] = true; } if (a[i] > mx1) { mx2 = mx1; mx1 = a[i]; } else if (a[i] > mx2) { mx2 = a[i]; } } pref[0] = want[0]; for (long long i = 1; i < n; ++i) { pref[i] = pref[i - 1] + want[i]; } long long mx = -MOD; long long ans = -MOD; long long best = -1; for (long long i = 0; i < n; ++i) { mx = max(mx, a[i]); if (a[i] != mx) continue; long long j = next_[i]; long long new_ans = pref[j - 1] - pref[i] - 1; if (new_ans > ans || (new_ans == ans && a[i] < a[best])) { ans = new_ans; best = i; } } mx = -MOD; for (long long i = 0; i < n; ++i) { mx = max(mx, a[i]); if (a[i] == mx) continue; long long new_ans = 0; if (new_ans > ans || (new_ans == ans && a[i] < a[best])) { ans = new_ans; best = i; } } cout << a[best] << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2BB2A_TB_V
`define SKY130_FD_SC_MS__O2BB2A_TB_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o2bb2a.v"
module top();
// Inputs are registered
reg A1_N;
reg A2_N;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1_N = 1'bX;
A2_N = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1_N = 1'b0;
#40 A2_N = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1_N = 1'b1;
#200 A2_N = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1_N = 1'b0;
#360 A2_N = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2_N = 1'b1;
#640 A1_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2_N = 1'bx;
#800 A1_N = 1'bx;
end
sky130_fd_sc_ms__o2bb2a dut (.A1_N(A1_N), .A2_N(A2_N), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2BB2A_TB_V
|
module decoder (cx,d);
output [7:0] d;
input [18:0] cx;
reg [7:0] d;
reg [7:0] s;
reg [18:0] cx1;
parameter s0 = 8'b10000000000;
parameter s1 = 8'b01000000000;
parameter s2 = 8'b00100000000;
parameter s3 = 8'b00010000000;
parameter s4 = 8'b00001000000;
parameter s5 = 8'b00000100000;
parameter s6 = 8'b00000010000;
parameter s7 = 8'b00000001000;
parameter s8 = 8'b00000000100;
parameter s9 = 8'b00000000010;
parameter s10 = 8'b00000000001;
parameter s11 = 8'b00101101101;
parameter s12 = 8'b10101100110;
parameter s13 = 8'b01000111001;
parameter s14 = 8'b11110011101;
parameter s15 = 8'b10001100011;
parameter s16 = 8'b11000010001;
parameter s17 = 8'b10001000010;
parameter s18 = 8'b10010100110;
always @(cx)
begin
cx1[0] = cx[0];
cx1[1] = cx[1];
cx1[2] = cx[2];
cx1[3] = cx[3];
cx1[4] = cx[4];
cx1[5] = cx[5];
cx1[6] = cx[6];
cx1[7] = cx[7];
cx1[8] = cx[8];
cx1[9] = cx[9];
cx1[10] = cx[10];
cx1[11] = cx[11];
cx1[12] = cx[12];
cx1[13] = cx[13];
cx1[14] = cx[14];
cx1[15] = cx[15];
cx1[16] = cx[16];
cx1[17] = cx[17];
cx1[18] = cx[18];
s[0]= cx[0]+ cx[12]+ cx[14]+ cx[15]+ cx[16]+ cx[17]+ cx[18];
s[1]= cx[1]+ cx[13]+ cx[14]+ cx[16];
s[2]= cx[2]+ cx[11]+ cx[12]+ cx[14];
s[3]= cx[3]+ cx[14]+ cx[18];
s[4]= cx[4]+ cx[11]+ cx[12]+ cx[15]+ cx[17];
s[5]= cx[5]+ cx[11]+ cx[12]+ cx[13]+ cx[15]+ cx[18];
s[6]= cx[6]+ cx[13]+ cx[14]+ cx[16];
s[7]= cx[7]+ cx[11]+ cx[13]+ cx[14];
s[8]= cx[8]+ cx[11]+ cx[12]+ cx[14]+ cx[18];
s[9]= cx[9]+ cx[12]+ cx[15]+ cx[17]+ cx[18];
s[10]= cx[10]+ cx[11]+ cx[13]+ cx[14]+ cx[15]+ cx[16];
case(s)
s0:
begin
if(cx[0]==1'b0)
begin
cx1[0]=1'b1;
end
else
begin
cx1[0]=1'b0;
end
end
s1:
begin
if(cx[1]==1'b0)
begin
cx1[1]=1'b1;
end
else
begin
cx1[1]=1'b0;
end
end
s2:
begin
if(cx[2]==1'b0)
begin
cx1[2]=1'b1;
end
else
begin
cx1[2]=1'b0;
end
end
s3:
begin
if(cx[3]==1'b0)
begin
cx1[3]=1'b1;
end
else
begin
cx1[3]=1'b0;
end
end
s4:
begin
if(cx[4]==1'b0)
begin
cx1[4]=1'b1;
end
else
begin
cx1[4]=1'b0;
end
end
s5:
begin
if(cx[5]==1'b0)
begin
cx1[5]=1'b1;
end
else
begin
cx1[5]=1'b0;
end
end
s6:
begin
if(cx[6]==1'b0)
begin
cx1[6]=1'b1;
end
else
begin
cx1[6]=1'b0;
end
end
s7:
begin
if(cx[7]==1'b0)
begin
cx1[7]=1'b1;
end
else
begin
cx1[7]=1'b0;
end
end
s8:
begin
if(cx[8]==1'b0)
begin
cx1[8]=1'b1;
end
else
begin
cx1[8]=1'b0;
end
end
s9:
begin
if(cx[9]==1'b0)
begin
cx1[9]=1'b1;
end
else
begin
cx1[9]=1'b0;
end
end
s10:
begin
if(cx[10]==1'b0)
begin
cx1[10]=1'b1;
end
else
begin
cx1[10]=1'b0;
end
end
s11:
begin
if(cx[11]==1'b0)
begin
cx1[11]=1'b1;
end
else
begin
cx1[11]=1'b0;
end
end
s12:
begin
if(cx[12]==1'b0)
begin
cx1[12]=1'b1;
end
else
begin
cx1[12]=1'b0;
end
end
s13:
begin
if(cx[13]==1'b0)
begin
cx1[13]=1'b1;
end
else
begin
cx1[13]=1'b0;
end
end
s14:
begin
if(cx[14]==1'b0)
begin
cx1[14]=1'b1;
end
else
begin
cx1[14]=1'b0;
end
end
s15:
begin
if(cx[15]==1'b0)
begin
cx1[15]=1'b1;
end
else
begin
cx1[15]=1'b0;
end
end
s16:
begin
if(cx[16]==1'b0)
begin
cx1[16]=1'b1;
end
else
begin
cx1[16]=1'b0;
end
end
s17:
begin
if(cx[17]==1'b0)
begin
cx1[17]=1'b1;
end
else
begin
cx1[17]=1'b0;
end
end
s18:
begin
if(cx[18]==1'b0)
begin
cx1[18]=1'b1;
end
else
begin
cx1[18]=1'b0;
end
end
default:
begin
cx1[0]=cx[0];
cx1[1]=cx[1];
cx1[2]=cx[2];
cx1[3]=cx[3];
cx1[4]=cx[4];
cx1[5]=cx[5];
cx1[6]=cx[6];
cx1[7]=cx[7];
cx1[8]=cx[8];
cx1[9]=cx[9];
cx1[10]=cx[10];
cx1[11]=cx[11];
cx1[12]=cx[12];
cx1[13]=cx[13];
cx1[14]=cx[14];
cx1[15]=cx[15];
cx1[16]=cx[16];
cx1[17]=cx[17];
cx1[18]=cx[18];
end
endcase
d[0] = cx1[11];
d[1] = cx1[12];
d[2] = cx1[13];
d[3] = cx1[14];
d[4] = cx1[15];
d[5] = cx1[16];
d[6] = cx1[17];
d[7] = cx1[18];
end
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) std::pair<int, int> DR[] = {{-1, 0}, {0, 1}, {1, 0}, {0, -1}, {-1, 1}, {-1, -1}, {1, 1}, {1, -1}}; using namespace std; int n, x, a[1 << 19]; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cerr.tie(0); cout.tie(0); cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; multiset<int> ms; for (int i = 1; i <= n; i++) { cin >> x; ms.insert(x); } for (int i = 1; i <= n; i++) { auto it = ms.begin(); auto itt = ms.end(); itt--; int x = 0; for (int j = 29; j + 1; j--) { if (a[i] & (1LL << j)) { if (*itt >= x + (1LL << j)) { x += (1LL << j); auto luh = ms.lower_bound(x); if (*luh > *it) it = luh; } } else { if (*it < x + (1LL << j)) { auto luh = ms.lower_bound(x + (1LL << j)); luh--; if (*luh < *itt) itt = luh; } else x += (1LL << j); } } cout << (a[i] ^ (*it)) << ; ms.erase(it); } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFSTP_TB_V
`define SKY130_FD_SC_HD__DFSTP_TB_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dfstp.v"
module top();
// Inputs are registered
reg D;
reg SET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SET_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 SET_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 SET_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 SET_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 SET_B = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hd__dfstp dut (.D(D), .SET_B(SET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFSTP_TB_V
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const long long LINF = 0x3f3f3f3f3f3f3f3f; const int MOD = (int)1e9 + 7; const int N = (int)1e6 + 7; const int M = (int)-1; int a[N], cnt[100]; int main() { int T; cin >> T; while (T--) { long long n; int m; cin >> n >> m; for (int i = (0); i < (m); ++i) cin >> a[i]; long long sum = 0; for (int i = (0); i < (m); ++i) sum += a[i]; if (sum < n) { cout << -1 << endl; continue; } sort(a, a + m); memset(cnt, 0, sizeof(cnt)); for (int i = 0, j = 0; i < m; i++) { while (a[i] > (1ll << j)) j++; cnt[j]++; } long long res = 0; int ans = 0; for (int i = (0); i < (63); ++i) { if (n >> i & 1) { if (!cnt[i] && res < (1ll << i)) { int j = i + 1; cnt[i] = 2; while (!cnt[j]) { cnt[j]++; j++; ans++; } cnt[j]--; ans++; } if (cnt[i]) cnt[i]--; else res -= 1ll << i; } res += (1ll << i) * cnt[i]; } cout << ans << endl; } return 0; } |
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