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#include <bits/stdc++.h> using namespace std; const int DX[8] = {1, -1, 0, 0, 1, 1, -1, -1}; const int DY[8] = {0, 0, 1, -1, 1, -1, 1, -1}; const int intmax = 0x7fffffff; const int mod = 1000000007; int n, m; int f[205]; int p[205]; vector<pair<int, int> > op; int main() { scanf( %d%d , &n, &m); int cnt = 0; for (int i = 0; i < m; i++) { int nk; scanf( %d , &nk); for (int j = 0; j < nk; j++) { int a; scanf( %d , &a); cnt++; f[a] = cnt; p[cnt] = a; } } int pemp; for (int i = 1; i <= n; i++) if (!f[i]) pemp = i; for (int j = 1; j <= cnt; j++) { if (f[j] != j) { if (!f[j] || j == pemp) { pemp = p[j]; op.push_back(make_pair(p[j], j)); p[j] = j; f[j] = j; continue; } f[pemp] = f[j]; p[f[j]] = pemp; op.push_back(make_pair(j, pemp)); int now = j; while (f[now] != now && now <= cnt && now >= 1) { op.push_back(make_pair(p[now], now)); int tmp = now; f[now] = now; now = p[now]; p[tmp] = tmp; } pemp = now; } } printf( %d n , op.size()); for (int i = 0; i < op.size(); i++) { printf( %d %d n , op[i].first, op[i].second); } } |
#include <bits/stdc++.h> using namespace std; using pii = pair<int, int>; const int rows[5] = {3, 4, 5, 4, 3}; bool dp[1 << 19], seen[1 << 19]; pii int_to_pair(int c) { pii res = {0, 0}; while (rows[res.first] <= c) { c -= rows[res.first]; res.first++; } res.second = c; return res; } int pair_to_int(pii p) { int res = 0; for (int i = 0; i < p.first; i++) res += rows[i]; res += p.second; return res; } pii next_coords(pii p, int dir) { if (dir == 0) { return {p.first, p.second - 1}; } else if (dir == 1) { if (p.first <= 2) { return {p.first - 1, p.second - 1}; } else { return {p.first - 1, p.second}; } } else if (dir == 2) { if (p.first <= 2) { return {p.first - 1, p.second}; } else { return {p.first - 1, p.second + 1}; } } else if (dir == 3) { return {p.first, p.second + 1}; } else if (dir == 4) { if (p.first >= 2) { return {p.first + 1, p.second}; } else { return {p.first + 1, p.second + 1}; } } else if (dir == 5) { if (p.first >= 2) { return {p.first + 1, p.second - 1}; } else { return {p.first + 1, p.second}; } } } void print_box(int box) { int b = 0; for (int i = 0; i < 5; i++) { for (int j = 0; j < 5 - rows[i]; j++) printf( ); for (int j = 0; j < rows[i]; j++) { printf( %c , .O [(box >> b) & 1]); b++; } printf( n ); } } bool getdp(int box) { if (box == 0) return false; if (seen[box]) { return dp[box]; } seen[box] = true; for (int i = 0; i < 19; i++) { if (!(box & (1 << i))) { continue; } for (int dir = 0; dir < 6; dir++) { int boxcpy = box; pii curr = int_to_pair(i); while (true) { if (curr.first < 0) break; if (curr.first > 4) break; if (curr.second < 0) break; if (curr.second >= rows[curr.first]) break; if (!(boxcpy & (1 << pair_to_int(curr)))) { break; } boxcpy ^= (1 << pair_to_int(curr)); if (!getdp(boxcpy)) { dp[box] = true; return true; } curr = next_coords(curr, dir); } } } return false; } int main() { int start_box = 0; for (int i = 0; i < 19; i++) { char c; cin >> c; if (c == O ) start_box |= 1 << i; } if (getdp(start_box)) { cout << Karlsson n ; } else { cout << Lillebror n ; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND3B_PP_SYMBOL_V
`define SKY130_FD_SC_HS__NAND3B_PP_SYMBOL_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nand3b (
//# {{data|Data Signals}}
input A_N ,
input B ,
input C ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND3B_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { long q, m, n, i, j, dummy, a, b, x, y, t, x1, y1; cin >> n >> m >> q; vector<vector<long> > R(100, vector<long>(100, 0)); vector<vector<long> > C(100, vector<long>(100, 0)); vector<vector<long> > E(100, vector<long>(100, 0)); for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { R[i][j] = i; C[i][j] = j; } } for (dummy = 0; dummy < q; dummy++) { cin.ignore(); cin >> t >> b; if (t == 1) { x1 = R[b - 1][0]; y1 = C[b - 1][0]; for (j = 0; j < m - 1; j++) { R[b - 1][j] = R[b - 1][j + 1]; C[b - 1][j] = C[b - 1][j + 1]; } R[b - 1][m - 1] = x1; C[b - 1][m - 1] = y1; } if (t == 2) { x1 = R[0][b - 1]; y1 = C[0][b - 1]; for (i = 0; i < n - 1; i++) { R[i][b - 1] = R[i + 1][b - 1]; C[i][b - 1] = C[i + 1][b - 1]; } R[n - 1][b - 1] = x1; C[n - 1][b - 1] = y1; } if (t == 3) { x = b; cin >> y >> a; x1 = R[x - 1][y - 1]; y1 = C[x - 1][y - 1]; E[x1][y1] = a; } } for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { cout << E[i][j]; cout << ; } cout << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long mod = 998244353; template <class T> inline void read(T &res) { char c; T flag = 1; while ((c = getchar()) < 0 || c > 9 ) if (c == - ) flag = -1; res = c - 0 ; while ((c = getchar()) >= 0 && c <= 9 ) res = res * 10 + c - 0 ; res *= flag; } long long quick(long long a, long long b) { long long ans = 1 % mod; while (b) { if (b & 1) ans = (ans % mod * a % mod) % mod; a = (a % mod * a % mod) % mod; b >>= 1; } return ans % mod; } int yy[1005000], m1[1005000]; vector<int> vv[1005000]; int main() { int n; read(n); map<int, int> mm; int cutt = 0; for (int i = 1; i <= n; i++) { int m; read(m); for (int j = 1; j <= m; j++) { int x; read(x); if (mm[x] == 0) yy[cutt++] = x; mm[x]++; vv[i].push_back(x); } } for (int i = 0; i < cutt; ++i) { m1[i] = quick(mm[yy[i]], mod - 2); } long long ans = 0; long long sss = quick(cutt, mod - 2); long long s1 = quick(n, mod - 2); for (int i = 1; i <= n; i++) { int y = vv[i].size(); long long s2 = quick(y, mod - 2); for (int j = 0; j < vv[i].size(); j++) { int x = vv[i][j]; int a = mm[x]; ans = ((ans % mod) % mod + ((s1 * s2 % mod) % mod * (a * s1 % mod) % mod) % mod) % mod; } } printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; long long GCD(long long a, long long b) { return b ? GCD(b, a % b) : a; } long long lcm(long long a, long long b) { return a * b / GCD(a, b); } int lb(int x) { return x & (-x); } const long long N = 3e5 + 7; const long long inf = 1e18 + 1; const long long mod2 = 998244353; const long long mod1 = 1e9 + 7; const int P1 = 13331; const int P2 = 131; const double eps = 1e-6; const double dbinf = 1e13 + 7; const long long mod3 = 10000 + 7; int n, m; string s; struct node { int v, nxt; }; node e[N]; int tot; int head[N]; int ing[N]; int ans; int dp[N][26]; void add(int u, int v) { e[++tot] = {v, head[u]}; head[u] = tot; } void topsort(void) { queue<int> q; for (int i = 1; i <= n; i++) { if (ing[i] == 0) { q.push(i); dp[i][s[i] - a ] = 1; } } int cnt = 0; while (!q.empty()) { int x = q.front(); cnt++; q.pop(); for (int i = head[x]; i; i = e[i].nxt) { int v = e[i].v; if (--ing[v] == 0) q.push(v); for (int j = 0; j <= 25; j++) { dp[v][j] = max(dp[v][j], dp[x][j] + (s[v] - a == j)); } } } if (cnt != n) { cout << -1 n ; } else { int maxn = 0; for (int i = 1; i <= n; i++) { for (int j = 0; j <= 25; j++) { maxn = max(maxn, dp[i][j]); } } cout << maxn << n ; } } int main() { memset(head, 0, sizeof head); memset(ing, 0, sizeof ing); cin >> n >> m; cin >> s; s = * + s; tot = 0; for (int i = 1, u = 1, v = 1; i <= m; i++) { cin >> u >> v; add(u, v); ing[v]++; } topsort(); return 0; } |
// file: Clock70HMz_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module Clock70HMz_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 10.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
// Status and control signals
reg RESET = 0;
wire LOCKED;
reg COUNTER_RESET = 0;
wire [1:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
reg [13:0] timeout_counter = 14'b00000000000000;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
$display ("Timing checks are not valid");
COUNTER_RESET = 0;
test_phase = "reset";
RESET = 1;
#(PER1*6);
RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*19.5)
COUNTER_RESET = 0;
#(PER1*1)
$display ("Timing checks are valid");
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
always@(posedge CLK_IN1) begin
timeout_counter <= timeout_counter + 1'b1;
if (timeout_counter == 14'b10000000000000) begin
if (LOCKED != 1'b1) begin
$display("ERROR : NO LOCK signal");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
end
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
Clock70HMz_exdes
dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED));
// Freq Check
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O21AI_SYMBOL_V
`define SKY130_FD_SC_MS__O21AI_SYMBOL_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o21ai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O21AI_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O32AI_BEHAVIORAL_V
`define SKY130_FD_SC_HS__O32AI_BEHAVIORAL_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o32ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
// Local signals
wire B1 nor0_out ;
wire B1 nor1_out ;
wire or0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A3, A1, A2 );
nor nor1 (nor1_out , B1, B2 );
or or0 (or0_out_Y , nor1_out, nor0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O32AI_BEHAVIORAL_V |
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 21:19:22 06/22/2009
// Design Name:
// Module Name: posted_pkt_gen_sora
// Project Name: Sora
// Target Devices: virtex-5 LX50T
// Tool versions: ISE 10.1.02
// Description: This module is created by Jiansong Zhang. Main purpose of this module is
// to generate posted packet header and data. We have two data sources: RX path
// and TX descriptor write back.
// On RX path, when every 28DW data is arrived, we
// generates three PCIe packets: (1) 28DW data packet (2) RX descriptor for next
// data block, valid bit is 0 (3) RX descriptor for this data block, valid bit is 1.
// This design facilitates driver for recognizing the latest data in RX buffer.
// For TX desc write back, we write back the TX descriptor and set own bit to 0.
// TX desc write back has higher priority.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
`include "Sora_config.v"
module posted_pkt_gen_sora(
input clk,
input rst,
//interface from/to dma_ctrl_wrapper
/// Jiansong: TX desc write back
input TX_desc_write_back_req,
output TX_desc_write_back_ack,
input [63:0] SourceAddr,
input [31:0] DestAddr,
input [23:0] FrameSize,
input [7:0] FrameControl,
input [63:0] DescAddr, /// Jiansong: pending
/// Jiansong: RX path
input RXEnable,
input [63:0] RXBufAddr,
input [31:0] RXBufSize,
/// the 2nd RX path
`ifdef SORA_FRL_2nd
input [63:0] RXBufAddr_2nd,
input [31:0] RXBufSize_2nd,
`endif
//interface to PCIe Endpoint Block Plus
input [2:0] max_pay_size,
input [15:0] req_id,
//interface to posted header fifo (a64_128_distram_fifo_p)
output posted_fifo_wren,
output [63:0] posted_fifo_data,
input posted_fifo_full, /// pending
//interface to dma write data fifo in TX engine
output [63:0] dma_write_data_fifo_data,
output dma_write_data_fifo_wren,
input dma_write_data_fifo_full,
//interface to RX data fifo
input [63:0] RX_FIFO_data,
output RX_FIFO_RDEN,
input RX_FIFO_pempty,
// interface to 2nd RX data fifo
`ifdef SORA_FRL_2nd
input [63:0] RX_FIFO_2nd_data,
output RX_FIFO_2nd_RDEN,
input RX_FIFO_2nd_pempty,
`endif
// debug interface
output [31:0] Debug20RX1,
output [4:0] Debug22RX3,
output [31:0] Debug24RX5,
output [31:0] Debug26RX7,
output [31:0] Debug27RX8,
output [31:0] Debug28RX9,
output [31:0] Debug29RX10
);
//internal wrapper connections
wire [63:0] dmawad_reg;
wire [9:0] length;
wire ack,go; //handshake signals
`ifdef SORA_FRL_2nd // two radios
posted_pkt_scheduler_2radios posted_pkt_scheduler_2radios_inst (
.clk(clk),
.rst(rst),
//interface to PCIe Endpoint Block Plus
.max_pay_size(max_pay_size),
//interface from/to RX data fifo
.RX_FIFO_data (RX_FIFO_data),
.RX_FIFO_RDEN (RX_FIFO_RDEN),
.RX_FIFO_pempty (RX_FIFO_pempty),
//interface from/to the 2nd RX data fifo
.RX_FIFO_2nd_data (RX_FIFO_2nd_data),
.RX_FIFO_2nd_RDEN (RX_FIFO_2nd_RDEN),
.RX_FIFO_2nd_pempty (RX_FIFO_2nd_pempty),
//interface from/to dma ctrl wrapper
/// TX descriptor write back
.TX_desc_write_back_req (TX_desc_write_back_req),
.TX_desc_write_back_ack (TX_desc_write_back_ack),
.SourceAddr (SourceAddr),
.DestAddr (DestAddr),
.FrameSize (FrameSize),
.FrameControl (FrameControl),
.DescAddr (DescAddr),
/// RX control signals
.RXEnable (RXEnable),
.RXBufAddr (RXBufAddr),
.RXBufSize (RXBufSize),
/// RX control signals for the 2nd RX buffer
.RXBufAddr_2nd (RXBufAddr_2nd),
.RXBufSize_2nd (RXBufSize_2nd),
//interface from/to dma write data fifo in TX engine
.dma_write_data_fifo_data (dma_write_data_fifo_data),
.dma_write_data_fifo_wren (dma_write_data_fifo_wren),
.dma_write_data_fifo_full (dma_write_data_fifo_full),
//interface to posted pkt builder
.go(go),
.ack(ack),
.dmawad(dmawad_reg[63:0]),
.length(length[9:0]),
//interface from a64_128_distram_p(posted header fifo)
.posted_fifo_full(posted_fifo_full),
// debug interface
.Debug20RX1(Debug20RX1),
.Debug22RX3(Debug22RX3),
.Debug24RX5(Debug24RX5),
.Debug26RX7(Debug26RX7),
.Debug27RX8(Debug27RX8),
.Debug28RX9(Debug28RX9),
.Debug29RX10(Debug29RX10)
);
`else // signal radio
posted_pkt_scheduler posted_pkt_scheduler_inst (
.clk(clk),
.rst(rst),
//interface to PCIe Endpoint Block Plus
.max_pay_size(max_pay_size),
//interface from/to RX data fifo
.RX_FIFO_data (RX_FIFO_data),
.RX_FIFO_RDEN (RX_FIFO_RDEN),
.RX_FIFO_pempty (RX_FIFO_pempty),
//interface from/to dma ctrl wrapper
/// TX descriptor write back
.TX_desc_write_back_req (TX_desc_write_back_req),
.TX_desc_write_back_ack (TX_desc_write_back_ack),
.SourceAddr (SourceAddr),
.DestAddr (DestAddr),
.FrameSize (FrameSize),
.FrameControl (FrameControl),
.DescAddr (DescAddr),
/// RX control signals
.RXEnable (RXEnable),
.RXBufAddr (RXBufAddr),
.RXBufSize (RXBufSize),
//interface from/to dma write data fifo in TX engine
.dma_write_data_fifo_data (dma_write_data_fifo_data),
.dma_write_data_fifo_wren (dma_write_data_fifo_wren),
.dma_write_data_fifo_full (dma_write_data_fifo_full),
//interface to posted pkt builder
.go(go),
.ack(ack),
.dmawad(dmawad_reg[63:0]),
.length(length[9:0]),
//interface from a64_128_distram_p(posted header fifo)
.posted_fifo_full(posted_fifo_full),
// debug interface
.Debug20RX1(Debug20RX1),
.Debug22RX3(Debug22RX3),
.Debug24RX5(Debug24RX5),
.Debug26RX7(Debug26RX7),
.Debug27RX8(Debug27RX8),
.Debug28RX9(Debug28RX9),
.Debug29RX10(Debug29RX10)
);
`endif
/// build posted packet header and put in fifo
posted_pkt_builder posted_pkt_builder_inst(
.clk(clk),
.rst(rst),
.req_id(req_id[15:0]),//from pcie block
//interface to posted_pkt_scheduler
.posted_fifo_full(posted_fifo_full),
.go(go),
.ack(ack),
.dmawad(dmawad_reg[63:0]),
.length(length[9:0]),
//interface to/from a64_128_distram_p(posted header fifo)
.header_data_out(posted_fifo_data[63:0]),
.header_data_wren(posted_fifo_wren)
);
endmodule
|
#include <bits/stdc++.h> const int MAXN = (int)1e5 + 5; const int MODN = (int)1e9 + 7; int inf = 0x3f3f3f3f; using namespace std; char str[MAXN]; int num[MAXN]; int a[MAXN]; int vis[MAXN]; int main() { int n, m; while (scanf( %d , &n) != EOF) { memset(vis, 0, sizeof(vis)); int sum = 0; for (int i = 0; i < n; i++) { scanf( %d , &a[i]); sum += a[i]; } int it = sum * 2 / n; for (int i = 0; i < n; i++) { if (vis[i] == 0) { vis[i] = 1; printf( %d , i + 1); for (int j = 0; j < n; j++) { if (vis[j] == 0 && a[j] + a[i] == it) { vis[j] = 1; printf( %d n , j + 1); break; } } } } } } |
// i2c.v
// This file was auto-generated as part of a generation operation.
// If you edit it your changes will probably be lost.
`timescale 1 ps / 1 ps
module i2c (
input wire wb_clk_i, // clock.clk
input wire wb_rst_i, // clock_reset.reset
inout wire scl_pad_io, // export_0.export
inout wire sda_pad_io, // .export
input wire [2:0] wb_adr_i, // avalon_slave_0.address
input wire [7:0] wb_dat_i, // .writedata
output wire [7:0] wb_dat_o, // .readdata
input wire wb_we_i, // .write
input wire wb_stb_i, // .chipselect
output wire wb_ack_o, // .waitrequest_n
output wire wb_inta_o // interrupt_sender.irq
);
opencores_i2c i2c (
.wb_clk_i (wb_clk_i), // clock.clk
.wb_rst_i (wb_rst_i), // clock_reset.reset
.scl_pad_io (scl_pad_io), // export_0.export
.sda_pad_io (sda_pad_io), // .export
.wb_adr_i (wb_adr_i), // avalon_slave_0.address
.wb_dat_i (wb_dat_i), // .writedata
.wb_dat_o (wb_dat_o), // .readdata
.wb_we_i (wb_we_i), // .write
.wb_stb_i (wb_stb_i), // .chipselect
.wb_ack_o (wb_ack_o), // .waitrequest_n
.wb_inta_o (wb_inta_o) // interrupt_sender.irq
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int ans[51][6] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 4, 3, 0, 0, 0, 0, 5, 3, 0, 0, 0, 0, 6, 5, 0, 0, 0, 0, 7, 6, 0, 0, 0, 0, 8, 6, 5, 4, 0, 0, 9, 5, 0, 0, 0, 0, 10, 7, 0, 0, 0, 0, 11, 9, 0, 0, 0, 0, 12, 6, 4, 1, 0, 0, 13, 4, 3, 1, 0, 0, 14, 5, 3, 1, 0, 0, 15, 14, 0, 0, 0, 0, 16, 15, 13, 4, 0, 0, 17, 14, 0, 0, 0, 0, 18, 11, 0, 0, 0, 0, 19, 6, 2, 1, 0, 0, 20, 17, 0, 0, 0, 0, 21, 19, 0, 0, 0, 0, 22, 21, 0, 0, 0, 0, 23, 18, 0, 0, 0, 0, 24, 23, 22, 17, 0, 0, 25, 22, 0, 0, 0, 0, 26, 6, 2, 1, 0, 0, 27, 5, 2, 1, 0, 0, 28, 25, 0, 0, 0, 0, 29, 27, 0, 0, 0, 0, 30, 6, 4, 1, 0, 0, 31, 28, 0, 0, 0, 0, 32, 22, 2, 1, 0, 0, 33, 20, 0, 0, 0, 0, 34, 27, 2, 1, 0, 0, 35, 33, 0, 0, 0, 0, 36, 25, 0, 0, 0, 0, 37, 5, 4, 3, 2, 1, 38, 6, 5, 1, 0, 0, 39, 35, 0, 0, 0, 0, 40, 38, 21, 19, 0, 0, 41, 38, 0, 0, 0, 0, 42, 41, 20, 19, 0, 0, 43, 42, 38, 37, 0, 0, 44, 43, 18, 17, 0, 0, 45, 44, 42, 41, 0, 0, 46, 45, 26, 25, 0, 0, 47, 42, 0, 0, 0, 0, 48, 47, 21, 20, 0, 0, 49, 40, 0, 0, 0, 0, 50, 49, 24, 23, 0, 0, }; int main() { int k; cin >> k; for (int i = 0; i < k; i++) { int found = 0; for (int j = 0; j < 6; j++) if (ans[k][j] == i + 1) found = 1; cout << found << ; } cout << endl; for (int i = 0; i < k; i++) cout << 1 ; cout << endl; return 0; } |
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module lab9_soc_to_sw_sig (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 1: 0] in_port;
input reset_n;
wire clk_en;
wire [ 1: 0] data_in;
wire [ 1: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {2 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
// =============================================================================
// COPYRIGHT NOTICE
// Copyright 2000-2001 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court (other locations)
// Hillsboro, OR 97124 web : http://www.latticesemi.com/
// U.S.A email:
// =============================================================================
// FILE DETAILS
// Project : sonet framer
// File : sync1s.v
// Title :
// Dependencies :
// Description : Synchronizer :Transfers signal from faster clock
// domain to slower clock domain.
// =============================================================================
// REVISION HISTORY
// Version : 1.0
// Author(s) :
// Mod. Date : Dec 14, 2004
// Changes Made : Initial Creation
// =============================================================================
`timescale 1 ns / 1 ps
module sync1s (
f_clk ,
s_clk ,
rst_n ,
in_fclk,
out_sclk
);
parameter WIDTH = 1 ;
input f_clk ; // Fast clock.
input s_clk ; // Slow clock.
input rst_n ; // reset signal.
input [WIDTH-1:0] in_fclk ; // Input pulse in fast clock domain.
output [WIDTH-1:0] out_sclk ; // Output pulse in slow clock domain.
reg [WIDTH-1:0] f_reg1 ;
reg [WIDTH-1:0] f_reg2 ;
reg [WIDTH-1:0] f_reg3 ;
reg [WIDTH-1:0] s_reg1 ;
reg [WIDTH-1:0] s_reg2 ;
wire [WIDTH-1:0] hold_fb ;
wire [WIDTH-1:0] out_sclk ;
integer i ;
// register fast clock signal edge and hold it untill
// it is transfered into slower clock domain.
always @(posedge f_clk or negedge rst_n) begin
if (!rst_n)
f_reg1 <= {WIDTH{1'b0}};
else
for (i = 0; i <= WIDTH-1; i = i+1) begin
f_reg1[i] <= (hold_fb[i]=== 1'b1) ? f_reg1[i] : in_fclk[i];
end
end
// first register in slower clock domain, this can be
// a metastable flop.
always @(posedge s_clk or negedge rst_n) begin
if (!rst_n)
s_reg1 <= {WIDTH{1'b0}};
else
s_reg1 <= f_reg1;
end
// Cleaner registering in slower clock domain.
always @(posedge s_clk or negedge rst_n) begin
if (!rst_n)
s_reg2 <= {WIDTH{1'b0}};
else
s_reg2 <= s_reg1;
end
// Output signal.
assign out_sclk = s_reg2 ;
// Register clean output in slower clock domain into
// fast clock domains, this can be metastable flop.
always @(posedge f_clk or negedge rst_n) begin
if (!rst_n)
f_reg2 <= {WIDTH{1'b0}};
else
f_reg2 <= s_reg2;
end
// Cleaner registering in faster clock domain.
always @(posedge f_clk or negedge rst_n) begin
if (!rst_n)
f_reg3 <= {WIDTH{1'b0}};
else
f_reg3 <= f_reg2;
end
// generate feed back hold signal for holding
// input signal in fast clock domain, until it reaches
// slower clock domain.
assign hold_fb = f_reg1 ^ f_reg3;
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`ifdef OVL_ASSERT_ON
wire xzcheck_enable;
`ifdef OVL_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
assign xzcheck_enable = 1'b1;
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
generate
case (property_type)
`OVL_ASSERT_2STATE,
`OVL_ASSERT: begin: assert_checks
assert_range_assert #(
.width(width),
.min(min),
.max(max))
assert_range_assert (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.xzcheck_enable(xzcheck_enable));
end
`OVL_ASSUME_2STATE,
`OVL_ASSUME: begin: assume_checks
assert_range_assume #(
.width(width),
.min(min),
.max(max))
assert_range_assert (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.xzcheck_enable(xzcheck_enable));
end
`OVL_IGNORE: begin: ovl_ignore
//do nothing
end
default: initial ovl_error_t(`OVL_FIRE_2STATE,"");
endcase
endgenerate
`endif
`ifdef OVL_COVER_ON
generate
if (coverage_level != `OVL_COVER_NONE)
begin: cover_checks
assert_range_cover #(
.width(width),
.min(min),
.max(max),
.OVL_COVER_SANITY_ON(OVL_COVER_SANITY_ON),
.OVL_COVER_CORNER_ON(OVL_COVER_CORNER_ON))
assert_range_cover (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr));
end
endgenerate
`endif
`endmodule //Required to pair up with already used "`module" in file assert_range.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_range_assert (clk, reset_n, test_expr, xzcheck_enable);
parameter width = 8;
parameter min = 1;
parameter max = 2;
input clk, reset_n;
input [width-1:0] test_expr;
input xzcheck_enable;
endmodule
//Module to be replicated for assume checks
//This module is bound to a PSL vunits with assume checks
module assert_range_assume (clk, reset_n, test_expr, xzcheck_enable);
parameter width = 8;
parameter min = 1;
parameter max = 2;
input clk, reset_n;
input [width-1:0] test_expr;
input xzcheck_enable;
endmodule
//Module to be replicated for cover properties
//This module is bound to a PSL vunit with cover properties
module assert_range_cover (clk, reset_n, test_expr);
parameter width = 8;
parameter min = 1;
parameter max = 2;
parameter OVL_COVER_SANITY_ON = 1;
parameter OVL_COVER_CORNER_ON = 1;
input clk, reset_n;
input [width-1:0] test_expr;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); int n; cin >> n; cout << 6 - n << n ; vector<bool> chk(6, false); for (int i = 0; i < n; i++) { string s; cin >> s; if (s[0] == p ) chk[0] = true; else if (s[0] == g ) chk[1] = true; else if (s[0] == b ) chk[2] = true; else if (s[0] == o ) chk[3] = true; else if (s[0] == r ) chk[4] = true; else if (s[0] == y ) chk[5] = true; } if (chk[0] == false) cout << Power << n ; if (chk[1] == false) cout << Time << n ; if (chk[2] == false) cout << Space << n ; if (chk[3] == false) cout << Soul << n ; if (chk[4] == false) cout << Reality << n ; if (chk[5] == false) cout << Mind << n ; } |
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: IPfifo.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.0.0 Build 614 04/24/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
module IPfifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrempty,
wrusedw);
input aclr;
input [9:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [9:0] q;
output rdempty;
output [13:0] rdusedw;
output wrempty;
output [13:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "8192"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "10"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "1"
// Retrieval info: PRIVATE: output_width NUMERIC "10"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_USEDW_MSB_BIT STRING "ON"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "8192"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "10"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "14"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 10 0 INPUT NODEFVAL "data[9..0]"
// Retrieval info: USED_PORT: q 0 0 10 0 OUTPUT NODEFVAL "q[9..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: rdusedw 0 0 14 0 OUTPUT NODEFVAL "rdusedw[13..0]"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL "wrempty"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 14 0 OUTPUT NODEFVAL "wrusedw[13..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 10 0 data 0 0 10 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 10 0 @q 0 0 10 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 14 0 @rdusedw 0 0 14 0
// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 14 0 @wrusedw 0 0 14 0
// Retrieval info: GEN_FILE: TYPE_NORMAL IPfifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL IPfifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL IPfifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL IPfifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL IPfifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL IPfifo_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9 + 7; const long long LL_INF = 1ll * INF * INF; const int MAX_N = 1000000 + 7; template <typename T> inline void addmod(T& a, const long long& b, const int& MOD = INF) { a = (a + b) % MOD; if (a < 0) a += MOD; } const int mod = INF; long long f[MAX_N]; int n; vector<int> adj[MAX_N]; vector<int> rev[MAX_N]; long long gcd(long long a, long long b) { return a == 0 ? b : gcd(b % a, a); } vector<int> divisors[MAX_N]; void init() { for (int i = 1; i < MAX_N; ++i) if (!rev[i].empty()) { for (int j = i; j < MAX_N; j += i) divisors[j].push_back(i); } } class FenWickTree { public: void update(int x, int val) { for (int t = x; t < MAX_N; t += t & -t) { tree[t] += val; } } int get(int x) { int res = 0; for (int t = x; t > 0; t -= t & -t) { res += tree[t]; } return res; } private: static const int MAX_N = ::MAX_N + 7; int tree[MAX_N]; } fenwickTree; int level[MAX_N]; int low[MAX_N], high[MAX_N]; void dfs(int u) { static int cnt = 0; low[u] = ++cnt; for (int v : adj[u]) { level[v] = level[u] + 1; dfs(v); f[u] += f[v]; } high[u] = cnt; } bool check(int d) { if (d == 1) return true; if (f[0] % d) return false; long long sum = f[0] / d; int cnt = 0; for (int c : divisors[d]) if (!rev[c].empty()) { cnt += rev[c].size(); } return d == cnt; } int ans[MAX_N]; void solve() { cin >> n; for (int i = (0), _b = (n); i < _b; ++i) cin >> f[i]; for (int i = (1), _b = (n); i < _b; ++i) { int p; cin >> p; adj[p - 1].push_back(i); } dfs(0); for (int i = 0; i < n; ++i) { long long d = gcd(f[i], f[0]); if (f[0] / d < MAX_N) { rev[f[0] / d].push_back(i); } } init(); for (int i = n; i > 0; --i) if (check(i)) { ans[i] += 1; if (ans[i] >= mod) ans[i] -= mod; for (int c : divisors[i]) if (c != i) { ans[c] += ans[i]; if (ans[c] >= mod) ans[c] -= mod; } } cout << ans[1] << n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); const bool multiple_test = false; int test = 1; if (multiple_test) cin >> test; for (int i = 0; i < test; ++i) { solve(); } } |
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cpu_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule
|
module top;
reg pass;
real rarr [1:0];
real rat;
integer i;
wire real rmon = rarr[0];
wire real rmonv = rarr[i];
always @(rarr[0]) begin
rat = rarr[0];
end
initial begin
pass = 1'b1;
i = 0;
rarr[0] = 1.125;
#1;
if (rmon != 1.125) begin
$display("Failed CA at 0, expected 1.125, got %6.3f", rmon);
pass = 1'b0;
end
if (rmonv != 1.125) begin
$display("Failed CA (var) at 0, expected 1.125, got %6.3f", rmonv);
pass = 1'b0;
end
if (rat != 1.125) begin
$display("Failed @ at 0, expected 1.125, got %6.3f", rat);
pass = 1'b0;
end
rarr[0] = 2.25;
#1;
if (rmon != 2.25) begin
$display("Failed CA at 1, expected 2.250, got %6.3f", rmon);
pass = 1'b0;
end
if (rmonv != 2.25) begin
$display("Failed CA (var) at 1, expected 2.250, got %6.3f", rmonv);
pass = 1'b0;
end
if (rat != 2.25) begin
$display("Failed @ at 1, expected 2.250, got %6.3f", rat);
pass = 1'b0;
end
i = 1;
#1
if (rmonv != 0.0) begin
$display("Failed CA (var) at 2, expected 0.000, got %6.3f", rmonv);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// pfpu32_i2f ////
//// 32-bit integer to floating point converter ////
//// ////
//// Author: Andrey Bacherov ////
//// ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2014 Andrey Bacherov ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
`include "mor1kx-defines.v"
module pfpu32_i2f
(
input clk,
input rst,
input flush_i, // flush pipe
input adv_i, // advance pipe
input start_i, // start conversion
input [31:0] opa_i,
output reg i2f_rdy_o, // i2f is ready
output reg i2f_sign_o, // i2f signum
output reg [3:0] i2f_shr_o,
output reg [7:0] i2f_exp8shr_o,
output reg [4:0] i2f_shl_o,
output reg [7:0] i2f_exp8shl_o,
output reg [7:0] i2f_exp8sh0_o,
output reg [31:0] i2f_fract32_o
);
/*
Any stage's output is registered.
Definitions:
s??o_name - "S"tage number "??", "O"utput
s??t_name - "S"tage number "??", "T"emporary (internally)
*/
// signum of input
wire s1t_signa = opa_i[31];
// magnitude (tow's complement for negative input)
wire [31:0] s1t_fract32 =
(opa_i ^ {32{s1t_signa}}) + {31'd0,s1t_signa};
// normalization shifts
reg [3:0] s1t_shrx;
reg [4:0] s1t_shlx;
// shift goal:
// 23 22 0
// | | |
// h fffffffffffffffffffffff
// right shift
always @(s1t_fract32[31:24]) begin
casez(s1t_fract32[31:24]) // synopsys full_case parallel_case
8'b1???????: s1t_shrx = 4'd8;
8'b01??????: s1t_shrx = 4'd7;
8'b001?????: s1t_shrx = 4'd6;
8'b0001????: s1t_shrx = 4'd5;
8'b00001???: s1t_shrx = 4'd4;
8'b000001??: s1t_shrx = 4'd3;
8'b0000001?: s1t_shrx = 4'd2;
8'b00000001: s1t_shrx = 4'd1;
8'b00000000: s1t_shrx = 4'd0;
endcase
end
// left shift
always @(s1t_fract32[23:0]) begin
casez(s1t_fract32[23:0]) // synopsys full_case parallel_case
24'b1???????????????????????: s1t_shlx = 5'd0; // hidden '1' is in its plase
24'b01??????????????????????: s1t_shlx = 5'd1;
24'b001?????????????????????: s1t_shlx = 5'd2;
24'b0001????????????????????: s1t_shlx = 5'd3;
24'b00001???????????????????: s1t_shlx = 5'd4;
24'b000001??????????????????: s1t_shlx = 5'd5;
24'b0000001?????????????????: s1t_shlx = 5'd6;
24'b00000001????????????????: s1t_shlx = 5'd7;
24'b000000001???????????????: s1t_shlx = 5'd8;
24'b0000000001??????????????: s1t_shlx = 5'd9;
24'b00000000001?????????????: s1t_shlx = 5'd10;
24'b000000000001????????????: s1t_shlx = 5'd11;
24'b0000000000001???????????: s1t_shlx = 5'd12;
24'b00000000000001??????????: s1t_shlx = 5'd13;
24'b000000000000001?????????: s1t_shlx = 5'd14;
24'b0000000000000001????????: s1t_shlx = 5'd15;
24'b00000000000000001???????: s1t_shlx = 5'd16;
24'b000000000000000001??????: s1t_shlx = 5'd17;
24'b0000000000000000001?????: s1t_shlx = 5'd18;
24'b00000000000000000001????: s1t_shlx = 5'd19;
24'b000000000000000000001???: s1t_shlx = 5'd20;
24'b0000000000000000000001??: s1t_shlx = 5'd21;
24'b00000000000000000000001?: s1t_shlx = 5'd22;
24'b000000000000000000000001: s1t_shlx = 5'd23;
24'b000000000000000000000000: s1t_shlx = 5'd0;
endcase
end
// registering output
always @(posedge clk) begin
if(adv_i) begin
// computation related
i2f_sign_o <= s1t_signa;
i2f_shr_o <= s1t_shrx;
i2f_exp8shr_o <= 8'd150 + {4'd0,s1t_shrx}; // 150=127+23
i2f_shl_o <= s1t_shlx;
i2f_exp8shl_o <= 8'd150 - {3'd0,s1t_shlx};
i2f_exp8sh0_o <= {8{s1t_fract32[23]}} & 8'd150; // "1" is in [23] / zero
i2f_fract32_o <= s1t_fract32;
end // advance
end // posedge clock
// ready is special case
always @(posedge clk `OR_ASYNC_RST) begin
if (rst)
i2f_rdy_o <= 1'b0;
else if(flush_i)
i2f_rdy_o <= 1'b0;
else if(adv_i)
i2f_rdy_o <= start_i;
end // posedge clock
endmodule // pfpu32_i2f
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using vi = vector<int>; using ii = pair<int, int>; template <typename A, typename B> ostream& operator<<(ostream& os, pair<A, B> p) { return os << { << p.first << , << p.second << } ; } const int oo = 0x3f3f3f3f; const ll OO = ll(oo) * oo; const ll M = 1e9 + 9; ll p2[100005]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n; cin >> n; int m; cin >> m; ll k = 1; for (int i = 0; i < m + 1; i++) { p2[i] = k; k <<= 1ll; k %= M; } ll ans = 1; for (int i = 0; i < n; i++) { if (p2[m] - i - 1 <= 0) { cout << 0 << endl; return 0; } ans *= (p2[m] - i - 1) % M; ans %= M; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 5; long long T[N]; long long sum[5]; multiset<long long, greater<long long>> ms[5]; int main() { ios::sync_with_stdio(0); cin.tie(0); int n, k, b, c; cin >> n >> k >> b >> c; for (int i = 1; i <= n; i++) { cin >> T[i]; } sort(T + 1, T + n + 1); if (T[1] < 0) { long long val = -T[1]; for (int i = 1; i <= n; i++) { T[i] += val; } } if (5 * c <= b) { long long ans = 9e18; long long sum = 0; for (int i = 1; i <= n; i++) { sum += T[i]; if (i >= k) { ans = min(ans, T[i] * k - sum); sum -= T[i - k + 1]; } } cout << ans << n ; exit(0); } long long ans = 9e18; for (int i = 1; i <= n; i++) { for (int j = 0; j < 5; j++) { long long cnt = -((T[i] + j) / 5) * b + j * c; int mm = (T[i] + j) % 5; sum[mm] += cnt; ms[mm].insert(cnt); } if (i > k) { for (int j = 0; j < 5; j++) { sum[j] -= *ms[j].begin(); ms[j].erase(ms[j].begin()); } } if (i >= k) { for (int j = 0; j < 5; j++) { int mm = (T[i] + j) % 5; ans = min(ans, ((T[i] + j) / 5) * b * k + sum[mm]); } } } cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 3010; const int INF = 0x3f3f3f3f; int d[MAXN], e[MAXN]; int main() { memset(d, INF, sizeof d); memset(e, INF, sizeof e); int n; cin >> n; string s; cin >> s; int at = INF; for (int i = 0; i < n; i++) { if (s[i] == R ) at = 0; else if (s[i] == L ) at = INF; d[i] = at; if (at < INF) at++; } at = INF; for (int i = n - 1; i >= 0; i--) { if (s[i] == R ) at = INF; else if (s[i] == L ) at = 0; e[i] = at; if (at < INF) at++; } int cont = 0; for (int i = 0; i < n; i++) { if (d[i] == e[i]) cont++; } cout << cont << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, k, sum = 0; cin >> n; for (int i = 0; i < n; i++) { cin >> k; sum += (int)abs(k); } cout << sum << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2111AI_SYMBOL_V
`define SKY130_FD_SC_HS__O2111AI_SYMBOL_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o2111ai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
input D1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2111AI_SYMBOL_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Tue May 30 22:27:54 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_clock_splitter_1_0/system_clock_splitter_1_0_sim_netlist.v
// Design : system_clock_splitter_1_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_clock_splitter_1_0,clock_splitter,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "clock_splitter,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_clock_splitter_1_0
(clk_in,
latch_edge,
clk_out);
input clk_in;
input latch_edge;
output clk_out;
wire clk_in;
wire clk_out;
wire latch_edge;
system_clock_splitter_1_0_clock_splitter U0
(.clk_in(clk_in),
.clk_out(clk_out),
.latch_edge(latch_edge));
endmodule
(* ORIG_REF_NAME = "clock_splitter" *)
module system_clock_splitter_1_0_clock_splitter
(clk_out,
latch_edge,
clk_in);
output clk_out;
input latch_edge;
input clk_in;
wire clk_i_1_n_0;
wire clk_in;
wire clk_out;
wire last_edge;
wire latch_edge;
LUT3 #(
.INIT(8'h6F))
clk_i_1
(.I0(latch_edge),
.I1(last_edge),
.I2(clk_out),
.O(clk_i_1_n_0));
FDRE #(
.INIT(1'b0))
clk_reg
(.C(clk_in),
.CE(1'b1),
.D(clk_i_1_n_0),
.Q(clk_out),
.R(1'b0));
FDRE #(
.INIT(1'b0))
last_edge_reg
(.C(clk_in),
.CE(1'b1),
.D(latch_edge),
.Q(last_edge),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; int pos = -1; void Go(vector<string> &t) { if (t[++pos] == int ) { cout << int ; } else { cout << pair< ; Go(t); cout << , ; Go(t); cout << > ; } } int main() { int n, i = 0; bool check = true; cin >> n; string t, t1 = ; int bal = 0; int k = 0; std::vector<std::string> s; char c; std::getline(std::cin, t); std::getline(std::cin, t); for (int j = 0; j < t.length(); j++) { if (t[j] != ) { t1 += t[j]; } else { s.push_back(t1); t1 = ; } } s.push_back(t1); k = s.size(); { for (int i = 0; i < k - 1; i++) { if (s[i] == pair ) bal++; else { bal--; } if (bal < 0) { check = false; } } if (s[k - 1] == pair ) bal++; else { bal--; } if (bal != -1) { check = false; } if (!check) { cout << Error occurred ; return 0; } } Go(s); } |
`include "constants.vh"
module pLayer(state_in, state_out, clk, rst, out_rdy, en);
input clk;
input rst;
input [263:0] state_in;
input en;
output reg [263:0] state_out;
output reg out_rdy;
wire [7:0] out_comb;
reg [7:0] permute [0:32];
reg [263:0] state_comb;
reg [7:0] x, y;
reg [31:0] j, PermutedBitNo;
wire [8:0] pi_out_field [8:0][32:0];
reg [31:0] idx;
integer k;
initial begin
for (k=0; k<`nSBox; k=k+1)
permute[k] = 0;
end
genvar itr_i, itr_j;
generate begin
for (itr_i = 0; itr_i<`nSBox; itr_i=itr_i+1) begin : Pi_i
for (itr_j = 0; itr_j<8; itr_j=itr_j+1) begin : Pi_j
Pi_mod pi(.in ((itr_i<<3)+itr_j), .out (pi_out_field[itr_j][itr_i]), .clk (clk), .rst (rst));
end
end
end endgenerate
always @ (posedge clk or posedge rst) begin
if (rst) begin
state_out = 0;
state_comb = 0;
idx = 0;
out_rdy = 0;
for (k=0; k<`nSBox; k=k+1)
permute[k] = 0;
end else if(en) begin
for (j=0; j<8; j=j+1) begin
x = (state_in[(idx*8)+:8]>>j) & 8'b00000001;
PermutedBitNo = pi_out_field[j][idx];
y = PermutedBitNo>>3;
permute[y] = permute[y] ^ (x << (PermutedBitNo - 8*y));
state_comb = state_comb | permute[y] << (y*8);
end
if (idx==32) begin
state_out = state_comb;
out_rdy = 1'b1;
end else begin
out_rdy = 1'b0;
end
idx = idx + 1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; scanf( %d , &t); while (t--) { int m, n; scanf( %d %d , &m, &n); if (m % n == 0) printf( YES n ); else printf( NO n ); } } |
#include <bits/stdc++.h> using namespace std; int main() { int t, s, q; cin >> t >> s >> q; int cnt = 0; while (s < t) { s = s * q; cnt++; } cout << cnt << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, i = 1, j = 1, c1, c2; cin >> n; if (n % 2) cout << 9 << << (n - 9) << endl; else cout << 8 << << (n - 8) << endl; return 0; } |
//---------------------------------------------------------------------------
//-- Copyright 2015 - 2017 Systems Group, ETH Zurich
//--
//-- This hardware module is free software: you can redistribute it and/or
//-- modify it under the terms of the GNU General Public License as published
//-- by the Free Software Foundation, either version 3 of the License, or
//-- (at your option) any later version.
//--
//-- This program is distributed in the hope that it will be useful,
//-- but WITHOUT ANY WARRANTY; without even the implied warranty of
//-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
//-- GNU General Public License for more details.
//--
//-- You should have received a copy of the GNU General Public License
//-- along with this program. If not, see <http://www.gnu.org/licenses/>.
//---------------------------------------------------------------------------
module rem_top_ff #(parameter CHAR_COUNT=32, DELIMITER=0, STATE_COUNT=4)
(
clk,
rst, //active high
softRst,
input_valid,
input_data,
input_ready,
output_valid,
output_match,
output_index
);
input clk;
input rst;
input softRst;
input input_valid;
input [511:0] input_data;
output reg input_ready;
output reg output_valid;
output reg output_match;
output reg [15:0] output_index;
reg scan_mode;
reg input_wasvalid;
reg input_wasready;
reg input_hasdata;
reg [511:0] input_datareg;
reg config_valid;
reg [CHAR_COUNT*8-1:0] config_chars;
reg [CHAR_COUNT/2-1:0] config_ranges;
reg [CHAR_COUNT-1:0] config_conds;
reg [STATE_COUNT*(CHAR_COUNT)-1:0] config_state_pred;
reg [STATE_COUNT*STATE_COUNT-1:0] config_state_act;
reg restart;
reg wait_new;
reg wait_conf;
wire pred_valid;
wire [CHAR_COUNT-1:0] pred_bits;
wire [15:0] pred_index;
wire pred_last;
reg need_purge;
reg pred_valid_D;
reg pred_last_D;
reg [15:0] pred_index_D;
reg [STATE_COUNT*(CHAR_COUNT)-1:0] state_pred_masks;
reg [STATE_COUNT*STATE_COUNT-1:0] state_act_masks;
wire [STATE_COUNT-1:0] state_match_bits;
wire [STATE_COUNT-1:0] state_inact_bits;
wire [STATE_COUNT-1:0] state_outact_bits;
reg [STATE_COUNT*4-1:0] state_inact_delays;
reg [STATE_COUNT-1:0] always_activated;
reg [STATE_COUNT-1:0] state_act_sticky;
reg [15:0] string_length;
reg [7:0] length_remaining ;
reg [5:0] byte_addr;
reg waiting_pred;
reg dec_valid;
reg dec_last;
reg [7:0] dec_char;
reg rstBuf;
localparam STATE_ACT_SIZE = (STATE_COUNT*STATE_COUNT % 8 ==0) ? STATE_COUNT*STATE_COUNT : STATE_COUNT*STATE_COUNT+8-(STATE_COUNT*STATE_COUNT%8);
rem_decoder #(
.CHAR_COUNT(CHAR_COUNT),
.DELIMITER(DELIMITER)
) decoder_inst (
.clk(clk),
.rst(rstBuf),
.config_valid(config_valid),
.config_chars(config_chars),
.config_ranges(config_ranges),
.config_conds(config_conds),
.input_valid(dec_valid),
.input_last(dec_last),
.input_char(dec_char),
.index_rewind(wait_new),
.output_valid(pred_valid),
.output_data(pred_bits),
.output_index(pred_index),
.output_last(pred_last)
);
genvar X;
generate
for (X=0; X<STATE_COUNT; X=X+1)
begin: gen_states
rem_onestate onestate_inst (
.clk(clk),
.rst(rstBuf | wait_new),
.is_sticky(state_act_sticky),
.delay_valid(config_valid),
.delay_cycles(state_inact_delays[X*4 +: 4]),
.pred_valid(pred_valid),
.pred_match(state_match_bits[X]),
.act_input(state_inact_bits[X]),
.act_output(state_outact_bits[X])
);
assign state_match_bits[X] = ((state_pred_masks[(X+1)*(CHAR_COUNT)-1:X*(CHAR_COUNT)] & pred_bits) == 0 && state_pred_masks[(X+1)*(CHAR_COUNT)-1:X*(CHAR_COUNT)]!=0) ? 0 : 1;
assign state_inact_bits[X] = ((state_act_masks[(X+1)*STATE_COUNT-1:X*STATE_COUNT] & state_outact_bits) != 0) ? 1 : always_activated[X];
end
endgenerate
integer ind;
always @(posedge clk) begin
pred_valid_D <= pred_valid;
pred_last_D <= pred_last;
pred_index_D <= pred_index;
rstBuf <= rst;
if (rst) begin
output_valid <= 0;
always_activated <= 0;
string_length <= 0;
wait_new <= 1;
wait_conf <= 1;
restart <= 0;
need_purge <= 0;
input_ready <= 1;
config_valid <= 0;
dec_valid <= 0;
dec_last <= 0;
input_wasready <= input_ready;
input_wasvalid <= input_valid;
input_hasdata <= 0;
state_inact_delays <= 0;
waiting_pred <= 0;
scan_mode <= 0;
end
else begin
if (restart) begin
wait_conf <= 1 & (~scan_mode);
wait_new <= 1;
restart <= 0;
end
if (softRst) begin
wait_conf <= 1;
wait_new <= 1;
restart <= 0;
end
input_wasvalid <= input_valid;
input_wasready <= input_ready;
output_valid <= 0;
config_valid <= 0;
dec_valid <= 0;
dec_last <= 0;
if (input_valid==1) begin
input_ready <= 0;
end
input_hasdata <= input_ready==1 ? 0 : input_hasdata;
if (input_ready && input_valid) begin
input_datareg <= input_data;
input_hasdata <= 1;
end
if (input_hasdata==1 && wait_conf==1) begin
config_valid <= 1;
config_chars <= input_datareg[CHAR_COUNT*8-1:0];
config_ranges <= input_datareg[CHAR_COUNT/2 + CHAR_COUNT*8-1 : CHAR_COUNT*8];
config_conds <= input_datareg[CHAR_COUNT-1+CHAR_COUNT/2 + CHAR_COUNT*8:CHAR_COUNT/2 + CHAR_COUNT*8];
config_state_pred <= input_datareg[STATE_COUNT*CHAR_COUNT+CHAR_COUNT+CHAR_COUNT/2 + CHAR_COUNT*8-1:CHAR_COUNT/2 + CHAR_COUNT*8+CHAR_COUNT];
config_state_act <= input_datareg[STATE_COUNT*STATE_COUNT+STATE_COUNT*CHAR_COUNT+CHAR_COUNT+CHAR_COUNT/2 + CHAR_COUNT*8-1:STATE_COUNT*CHAR_COUNT+CHAR_COUNT+CHAR_COUNT/2 + CHAR_COUNT*8];
state_pred_masks <= input_datareg[STATE_COUNT*CHAR_COUNT+CHAR_COUNT+CHAR_COUNT/2 + CHAR_COUNT*8-1:CHAR_COUNT/2 + CHAR_COUNT*8+CHAR_COUNT];
state_act_masks <= input_datareg[STATE_COUNT*STATE_COUNT+STATE_COUNT*CHAR_COUNT+CHAR_COUNT+CHAR_COUNT/2 + CHAR_COUNT*8-1:STATE_COUNT*CHAR_COUNT+CHAR_COUNT+CHAR_COUNT/2 + CHAR_COUNT*8];
state_inact_delays <= input_datareg[STATE_COUNT*4-1+STATE_ACT_SIZE+STATE_COUNT*CHAR_COUNT+CHAR_COUNT+CHAR_COUNT/2 + CHAR_COUNT*8 : STATE_ACT_SIZE+STATE_COUNT*CHAR_COUNT+CHAR_COUNT+CHAR_COUNT/2 + CHAR_COUNT*8];
state_act_sticky <= input_datareg[STATE_COUNT-1+STATE_COUNT*4+STATE_ACT_SIZE+STATE_COUNT*CHAR_COUNT+CHAR_COUNT+CHAR_COUNT/2 + CHAR_COUNT*8 : STATE_COUNT*4+STATE_ACT_SIZE+STATE_COUNT*CHAR_COUNT+CHAR_COUNT+CHAR_COUNT/2 + CHAR_COUNT*8];
for (ind=0; ind<STATE_COUNT; ind=ind+1) begin
always_activated[ind]=0;
if (input_datareg[(ind)*STATE_COUNT+STATE_COUNT*CHAR_COUNT+CHAR_COUNT+CHAR_COUNT/2 + CHAR_COUNT*8 +: STATE_COUNT]==0) always_activated[ind]=1;
end
wait_conf <= 0;
input_ready <= 1;
scan_mode <= input_datareg[511];
end
if (restart==0 && wait_conf==0) begin
if (!input_ready && input_hasdata==1 && wait_new==1) begin
byte_addr <= 2;
string_length <= input_datareg[15:0];
length_remaining <= (input_datareg[15:0]+63)/64;
wait_new <= 0;
if (input_datareg[15:0]==0) begin
wait_new <=1;
input_ready <= 1;
end
end
if (!input_ready && input_hasdata==1 && wait_new==0) begin
if (byte_addr<=63) begin
dec_valid <= 1;
dec_char <= input_datareg[byte_addr[5:0]*8 +: 8];
byte_addr <= byte_addr+1;
if (byte_addr==63 && length_remaining==1) begin
dec_last <= 1;
end else begin
dec_last <= 0;
end
end
if (byte_addr==63 && length_remaining>1) begin
byte_addr <= 0;
input_ready <= 1;
length_remaining <= length_remaining-1;
end
else if (byte_addr==63 && length_remaining==1 && !need_purge) begin
byte_addr <= 0;
input_hasdata <= 0;
waiting_pred <= 1;
length_remaining <= 0;
end
if (need_purge==1) begin
if (length_remaining>1) begin
byte_addr <= 64;
length_remaining <= length_remaining-1;
input_ready <= 1;
end
else begin
byte_addr <= 0;
restart <= 1;
input_ready <= 1;
need_purge <= 0;
end
end
end
if (!need_purge && !wait_new && pred_valid_D==1 && (state_outact_bits[STATE_COUNT-1]==1 || pred_last_D==1)) begin
output_valid <= 1;
output_match <= state_outact_bits[STATE_COUNT-1]==1;
output_index <= pred_index_D;
if (!waiting_pred) begin
need_purge<=1;
end
else begin
waiting_pred <= 0;
byte_addr <= 0;
restart <= 1;
input_ready <= 1;
need_purge <= 0;
end
end
if (!input_hasdata && output_valid==1 && waiting_pred==1) begin
waiting_pred <= 0;
byte_addr <= 0;
restart <= 1;
input_ready <= 1;
need_purge <= 0;
end
if (!need_purge && waiting_pred==1 && pred_valid_D==0 && length_remaining==0) begin
output_valid <= 1;
output_match <= 0;
output_index <= 0;
waiting_pred <= 0;
byte_addr <= 0;
restart <= 1;
input_ready <= 1;
need_purge <= 0;
end
end
end
end
endmodule |
module j1soc#(
//parameter bootram_file = "../../firmware/hello_world/j1.mem" // For synthesis
parameter bootram_file = "../firmware/Hello_World/j1.mem" // For simulation
)(
trigger, echo, done, [15:0]distance
sys_clk_i, sys_rst_i
);
input sys_clk_i, sys_rst_i, trigger;
output echo, done, [15:0]distance;
output done;
//------------------------------------ regs and wires-------------------------------
wire j1_io_rd;//********************** J1
wire j1_io_wr;//********************** J1
wire [15:0] j1_io_addr;//************* J1
reg [15:0] j1_io_din;//************** J1
wire [15:0] j1_io_dout;//************* J1
reg [1:4]cs; // CHIP-SELECT
wire [15:0]ult_out;
//------------------------------------ regs and wires-------------------------------
j1 #(bootram_file) cpu0(sys_clk_i, sys_rst_i, j1_io_din, j1_io_rd, j1_io_wr, j1_io_addr, j1_io_dout);
peripherial_ultrasnd ultra(.clk(sys_clk_i),.reset(sys_rst_i),.d_in(j1_io_dout),.cs(cs[1]),.addr(j1_io_addr[3:0]),.rd(j1_io_rd),.wr(j1_io_wr),.d_out(ult_out),.trigger(trigger),.echo(echo),.done(done),.d_out(distance));
dpRAM_interface dpRm(.clk(sys_clk_i), .d_in(j1_io_dout), .cs(cs[4]), .addr(j1_io_addr[7:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(dp_ram_dout));
// ============== Chip_Select (Addres decoder) ======================== // se hace con los 8 bits mas significativos de j1_io_addr
always @* begin
case (j1_io_addr[15:8]) // direcciones - chip_select
8'h67: cs= 4'b1000; //mult
8'h68: cs= 4'b0100; //div
8'h69: cs= 4'b0010; //uart
8'h70: cs= 4'b0001; //dp_ram
default: cs= 3'b000;
endcase
end
//============== Chip_Select (Addres decoder) ======================== //
// ============== MUX ======================== // se encarga de lecturas del J1
always @* begin
case (cs)
4'b1000: j1_io_din = ult_out;
4'b0001: j1_io_din = dp_ram_dout;
default: j1_io_din = 16'h0666;
endcase
end
// ============== MUX ======================== //
endmodule // top
|
#include <bits/stdc++.h> using namespace std; int main() { int n, a = 0, l[101], r[101], k; cin >> n; for (int i = 0; i < n; i++) { cin >> l[i] >> r[i]; } cin >> k; for (int i = 0; i < n; i++) { if (k <= r[i]) { a++; } } cout << a; } |
#include <bits/stdc++.h> using namespace std; const long long INF = 0x3ffffffffffff; int main() { long long T; scanf( %lld , &T); while (T--) { long long k, n, a, b; scanf( %lld%lld%lld%lld , &k, &n, &a, &b); k -= b * n; if (k <= 0) printf( -1 n ); else printf( %lld n , min(n, (k - 1) / (a - b))); } } |
#include <bits/stdc++.h> using namespace std; class solution { public: void solve() { int n; cin >> n; int i = 1; int prev = 0; vector<int> sol; while (n != 0) { if (n > prev) { prev++; sol.push_back(prev); n = n - prev; } else { sol[prev - 1] = sol[prev - 1] + n; n = 0; } } cout << sol.size() << n ; for (auto it : sol) { cout << it << ; } } }; int main() { ios::sync_with_stdio(0), cout.tie(0), cin.tie(0); long long i = 0; solution second; second.solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const int MAXN = 1e6 + 5; long long a[MAXN], b[MAXN]; int main() { int x; cin >> x; for (int i = 1; i <= x; i++) for (int j = 1; j <= x; j++) { if (i * j > x && (i / j) < x && (i % j == 0)) { cout << i << << j << endl; return 0; } } cout << -1 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; inline int read() { char ch = getchar(); int x = 0, f = 1; while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = (x << 1) + (x << 3) - 0 + ch; ch = getchar(); } return x * f; } int main() { priority_queue<int> q; int n = read(), T = read(); int ans = 0; for (int i = 1; i <= n; i++) { int x = read(); x = max(x, i); while (!q.empty() && q.top() >= T - i) { q.pop(); } if (x < T) q.push(x - i); ans = max(ans, (int)q.size()); } printf( %d n , ans); } |
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); const int N = 1e6 + 5; int f[N]; int a[] = {1, 2}; int na = 2; int main() { int cnt; cin >> cnt; if (cnt == 1) { cout << 1 1 n1 ; return 0; } int x = 1; for (int i = 2; i < N; i++) { if (i % 2 == 0) x++; if (x == cnt) { cout << i << 2 n1 2 ; return 0; } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e4 + 5; const int mod = 1e9 + 7; int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n; cin >> n; int a[n + 5], mx = 0; long long sum = 0; for (int i = 0; i < n; i++) cin >> a[i], sum += a[i], mx = max(mx, a[i]); sum -= mx; cout << (mx - sum + 1) << endl; return 0; } |
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module system1_output0 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 31: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 31: 0] data_out;
wire [ 31: 0] out_port;
wire [ 31: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {32 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[31 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<pair<int, int> > ans; int a[305], b[305], n; int cur[305]; map<int, vector<int> > m; int main() { ios_base::sync_with_stdio(0); cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) cin >> b[i]; for (int i = 0; i < n; i++) { m[a[i]].push_back(i); } for (auto &x : m) reverse(x.second.begin(), x.second.end()); for (int i = 0; i < n; i++) { cur[i] = m[b[i]].back(); m[b[i]].pop_back(); } for (int i = 0; i < n; i++) if (1) cerr << cur[i] << ; if (1) cerr << n ; for (int i = 0; i < n; i++) for (int j = 0; j < n - 1; j++) { if (cur[j] > cur[j + 1]) { ans.push_back({j + 1, j + 2}); swap(cur[j], cur[j + 1]); } } cout << ans.size() << n ; for (auto x : ans) cout << x.first << << x.second << n ; } |
#include <bits/stdc++.h> using namespace std; int min(int a, int b) { if (a > b) { return b; } else { return a; } } int max(int a, int b) { if (a > b) { return a; } else { return b; } } int main() { int n, x0; int a, b; int d, f; cin >> n >> x0 >> a >> b; if (a > b) { d = b; f = a; } else { d = a; f = b; } int temp1; int temp2; for (int i = 1; i != n; i++) { cin >> a >> b; if (a > b) { temp1 = a; a = b; b = temp1; } if (a > d) { if (a > f) { cout << -1; return 0; } d = a; } if (b < f) { if (b < d) { cout << -1; return 0; } f = b; } } if (x0 >= d && x0 <= f) { cout << 0; } else { if (x0 < d) { cout << d - x0; } else { cout << x0 - f; } } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND4B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__AND4B_FUNCTIONAL_PP_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__and4b (
VPWR,
VGND,
X ,
A_N ,
B ,
C ,
D
);
// Module ports
input VPWR;
input VGND;
output X ;
input A_N ;
input B ;
input C ;
input D ;
// Local signals
wire D not0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , not0_out, B, C, D );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND4B_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int a[2006]; int Gcd(int m, int n) { if (n == 0) return m; return Gcd(n, m % n); } int main() { int n; scanf( %d , &n); int yi = 0; int flag = 0; for (int i = 0; i < n; i++) { scanf( %d , &a[i]); if (a[i] == 1) yi++; } if (yi != 0) { printf( %d n , n - yi); return 0; } int min = 5000; for (int i = 0; i < n; i++) { int sum = 0, mod = a[i]; for (int j = i + 1; j < n; j++) { mod = Gcd(mod, a[j]); sum++; if (mod == 1) { flag = 1; if (sum < min) min = sum; break; } } } if (flag == 1) printf( %d n , min + n - 1); else printf( -1 n ); } |
// Author: wlzhouzhuan #pragma GCC optimize( Ofast ) #pragma GCC target( avx ) #include <bits/stdc++.h> using namespace std; #define ull unsigned long long namespace IO { const int SIZE = 1 << 23; char ibuf[SIZE], *iS, *iT; char obuf[SIZE], *oS = obuf, *oT = oS + SIZE - 1; bool flush() { fwrite(obuf, 1, oS - obuf, stdout); oS = obuf; return true; } #define gc() (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++) #define pc(x) (*oS++ = x) int read() { int x = 0, f = 0; char c = gc(); while (!isdigit(c)) f |= c == - , c = gc(); while (isdigit(c)) x = 10 * x + c - 0 , c = gc(); return f ? -x : x; } char qu[55]; int qlen; template <class T> void print(T x) { if (!x) pc( 0 ); if (x < 0) pc( - ), x = -x; while (x) qu[++qlen] = x % 10 + 0 , x /= 10; while (qlen) pc(qu[qlen--]); } template <class T> void print(T x, char charset) { print(x), pc(charset); } struct Flusher { ~Flusher() { flush(); } } flusher; } using namespace IO; const int N = 1005; const int mod = 998244353; int qpow(int a, int b = mod - 2) { int res = 1; while (b > 0) { if (b & 1) res = 1ll * res * a % mod; a = 1ll * a * a % mod; b >>= 1; } return res; } ull mul(ull a, ull b) { return (static_cast<unsigned long long>(a) * b) % mod; } int a[N], m, n; ull fz = 1, sumfz = 0, fm = 1, ans = 0; int j = 0; void run(int t) { for (; j < t; j++) { fz = mul(fz, 2 * n - j); sumfz = mul(sumfz, (n - j)) + fz; fm = mul(fm, n - j); } } int main() { m = read(); for (int i = 1; i <= m; i++) { a[i] = read(), n += a[i]; } sort(a + 1, a + m + 1); for (int i = 1; i <= m; i++) { run(a[i]); ans = (ans + mul(sumfz, qpow(fm))) % mod; } run(n); ans = (ans + mod - mul(sumfz, qpow(fm))) % mod; print((mod - ans) % mod, n ); return 0; } |
#include <bits/stdc++.h> using namespace std; struct coordinate { float x; float y; }; float check1(coordinate c1, coordinate c2, coordinate c3, coordinate c4, coordinate x1) { float ans1 = (x1.y - c1.y) + (x1.x - c1.x); float ans2 = (x1.y - c3.y) + (x1.x - c3.x); if (ans1 == 0 || ans2 == 0) return 0; else { float ans = ans1 / ans2; return ans; } } float check2(coordinate c1, coordinate c2, coordinate c3, coordinate c4, coordinate x1) { float m = (c3.y - c1.y) / (c3.x - c1.x); float ans1 = (x1.y - c1.y) - m * (x1.x - c1.x); float ans2 = (x1.y - c2.y) - m * (x1.x - c2.x); if (ans1 == 0 || ans2 == 0) return 0; else { float ans = ans1 / ans2; return ans; } } int main() { float n, d; cin >> n >> d; coordinate c1, c2, c3, c4; c1.x = d; c1.y = 0; c2.x = 0; c2.y = d; c3.x = n; c3.y = n - d; c4.x = n - d; c4.y = n; int t; cin >> t; while (t--) { coordinate x1; cin >> x1.x >> x1.y; float ans1 = check1(c1, c2, c3, c4, x1); float ans2 = check2(c1, c2, c3, c4, x1); if (ans1 < 0 && ans2 < 0) cout << YES << endl; else if (ans1 == 0 || ans2 == 0) cout << YES << endl; else cout << NO << endl; } return 0; } |
//#############################################################################
//# Function: Isolation buffer (HIGH) for multi supply domains #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_pwr_isohi #(parameter DW = 1 // width of data inputs
)
(
input iso,// active low isolation signal
input [DW-1:0] in, // input signal
output [DW-1:0] out // out = iso | in
);
localparam ASIC = `CFG_ASIC; // use ASIC lib
generate
if(ASIC)
begin : asic
asic_iso_hi iiso [DW-1:0] (.iso(iso),
.in(in[DW-1:0]),
.out(out[DW-1:0]));
end
else
begin : gen
assign out[DW-1:0] = {(DW){iso}} | in[DW-1:0];
end
endgenerate
endmodule // oh_buf
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV3SD3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__CLKDLYINV3SD3_BEHAVIORAL_PP_V
/**
* clkdlyinv3sd3: Clock Delay Inverter 3-stage 0.50um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__clkdlyinv3sd3 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV3SD3_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; int main() { int n, m, x1, y1, x2, y2, x, y; scanf( %d%d%d%d%d%d , &n, &m, &x1, &y1, &x2, &y2); x = abs(x1 - x2); y = abs(y1 - y2); if (x + y >= 7 || y >= 5 || x >= 5) printf( Second n ); else printf( First n ); return 0; } |
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_custom_add(clock, enable, resetn, dataa, datab, result);
input clock, enable, resetn;
input [31:0] dataa;
input [31:0] datab;
output [31:0] result;
// Total Latency = 12.
acl_fp_custom_add_core core(
.clock(clock),
.resetn(resetn),
.dataa(dataa),
.datab(datab),
.result(result),
.valid_in(),
.valid_out(),
.stall_in(),
.stall_out(),
.enable(enable));
defparam core.HIGH_LATENCY = 1;
defparam core.HIGH_CAPACITY = 0;
defparam core.FLUSH_DENORMS = 0;
defparam core.ROUNDING_MODE = 0;
defparam core.FINITE_MATH_ONLY = 0;
defparam core.REMOVE_STICKY = 0;
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_pmod (
pmod_clk,
pmod_rst,
pmod_signal_freq,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
localparam PCORE_VERSION = 32'h00010001;
parameter PCORE_ID = 0;
input pmod_clk;
output pmod_rst;
input [31:0] pmod_signal_freq;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg up_wack = 'd0;
reg [31:0] up_scratch = 'd0;
reg up_resetn = 'd0;
reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0;
// internal signals
wire [31:0] up_pmod_signal_freq_s;
wire up_wreq_s;
wire up_rreq_s;
// decode block select
assign up_wreq_s = (up_waddr[13:8] == 6'h00) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:8] == 6'h00) ? up_rreq : 1'b0;
assign up_preset_s = ~up_resetn;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 'd0;
up_scratch <= 'd0;
up_resetn <= 'd0;
end else begin
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
up_scratch <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
up_resetn <= up_wdata[0];
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[7:0])
8'h00: up_rdata <= PCORE_VERSION;
8'h01: up_rdata <= PCORE_ID;
8'h02: up_rdata <= up_scratch;
8'h03: up_rdata <= up_pmod_signal_freq_s;
8'h10: up_rdata <= up_resetn;
default: up_rdata <= 0;
endcase
end else begin
up_rdata <= 32'd0;
end
end
end
// resets
ad_rst i_adc_rst_reg (.preset(up_preset_s), .clk(pmod_clk), .rst(pmod_rst));
// adc control & status
up_xfer_status #(.DATA_WIDTH(32)) i_pmod_xfer_status (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_status (up_pmod_signal_freq_s),
.d_rst (pmod_rst),
.d_clk (pmod_clk),
.d_data_status (pmod_signal_freq));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; scanf( %d %d , &n, &k); char c[200005]; scanf( %s , c); int ok[26]; memset(ok, 0, sizeof(ok)); for (int i = 0; i < k; i++) { char cc; scanf( %c , &cc); ok[cc - a ] = 1; } long long cnt = 0; long long ans = 0; for (int i = 0; c[i] != 0; i++) { if (ok[c[i] - a ]) cnt++; else { ans += cnt * (cnt + 1) / 2; cnt = 0; } } ans += cnt * (cnt + 1) / 2; printf( %lld n , ans); } |
#include <bits/stdc++.h> using namespace std; const int N = 100500; const int INF = 2 * (1e9); int n, m; vector<pair<int, int> > edge[N]; vector<pair<int, int> > delay[N]; int dist[N]; int main() { cin.sync_with_stdio(false); cin >> n >> m; for (int i = 0; i < m; i++) { int from, to, len; cin >> from >> to >> len; from--; to--; edge[from].push_back(make_pair(to, len)); edge[to].push_back(make_pair(from, len)); } for (int i = 0; i < n; i++) { int num; cin >> num; int cur; for (int j = 0; j < num; j++) { cin >> cur; if (j == 0 or delay[i].back().second != cur) delay[i].push_back(make_pair(cur, cur + 1)); else delay[i].back().second++; } } for (int i = 0; i < n; i++) dist[i] = INF; dist[0] = 0; if (delay[0].size() >= 1 and delay[0][0].first == 0) dist[0] = delay[0][0].second; set<pair<int, int> > dijkstra; dijkstra.insert(make_pair(dist[0], 0)); for (int i = 0; i < n; i++) { if (dijkstra.empty()) break; pair<int, int> now = *dijkstra.begin(); dijkstra.erase(now); for (const pair<int, int> &next : edge[now.second]) { int arrival = next.first; int tm = next.second + now.first; int idx = lower_bound(delay[arrival].begin(), delay[arrival].end(), make_pair(tm, INF)) - delay[arrival].begin(); if (idx > 0 and arrival != n - 1) { idx--; if (delay[arrival][idx].first <= tm and tm < delay[arrival][idx].second) tm = delay[arrival][idx].second; } if (dist[arrival] > tm) { dijkstra.erase(make_pair(dist[arrival], arrival)); dist[arrival] = tm; dijkstra.insert(make_pair(dist[arrival], arrival)); } } } if (dist[n - 1] == INF) dist[n - 1] = -1; cout << dist[n - 1] << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int a1, b1, a2, b2; scanf( %d%d%d%d , &a1, &b1, &a2, &b2); int i; int two1 = 0, three1 = 0, two2 = 0, three2 = 0; long long s1 = (long long)a1 * b1, s2 = (long long)a2 * b2; while (!(s1 % 2)) { two1++; s1 /= 2; } while (!(s1 % 3)) { three1++; s1 /= 3; } while (!(s2 % 2)) { two2++; s2 /= 2; } while (!(s2 % 3)) { three2++; s2 /= 3; } int t1 = 0, th1 = 0, t2 = 0, th2 = 0; if (s1 != s2) { printf( -1 n ); return 0; } int ans = 0; while (three1 > three2) { three1--; th1++; two1++; t1--; ans++; if (a1 % 3 == 0) { a1 /= 3; a1 *= 2; } else if (b1 % 3 == 0) { b1 /= 3; b1 *= 2; } } while (three1 < three2) { three2--; th2++; two2++; t2--; ans++; if (a2 % 3 == 0) { a2 /= 3; a2 *= 2; } else if (b2 % 3 == 0) { b2 /= 3; b2 *= 2; } else { puts( -1 ); return 0; } } while (two1 > two2) { two1--; t1++; ans++; if (a1 % 2 == 0) { a1 /= 2; } else if (b1 % 2 == 0) { b1 /= 2; } else { puts( -1 ); return 0; } } while (two1 < two2) { two2--; t2++; ans++; if (a2 % 2 == 0) { a2 /= 2; } else if (b2 % 2 == 0) { b2 /= 2; } else { puts( -1 ); return 0; } } cout << ans << endl; printf( %d %d n , a1, b1); printf( %d %d n , a2, b2); return 0; } |
/*
* Copyright 2013, Homer Hsing <>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* in byte_num out
* 0x11223344 0 0x01000000
* 0x11223344 1 0x11010000
* 0x11223344 2 0x11220100
* 0x11223344 3 0x11223301
*/
module padder1(in, byte_num, out);
input [31:0] in;
input [1:0] byte_num;
output reg [31:0] out;
always @ (*)
case (byte_num)
0: out = 32'h1000000;
1: out = {in[31:24], 24'h010000};
2: out = {in[31:16], 16'h0100};
3: out = {in[31:8], 8'h01};
endcase
endmodule
|
module test_bench(clk, rst);
input clk;
input rst;
wire [31:0] wire_39069600;
wire wire_39069600_stb;
wire wire_39069600_ack;
wire [31:0] wire_39795024;
wire wire_39795024_stb;
wire wire_39795024_ack;
wire [31:0] wire_39795168;
wire wire_39795168_stb;
wire wire_39795168_ack;
file_reader_a file_reader_a_39796104(
.clk(clk),
.rst(rst),
.output_z(wire_39069600),
.output_z_stb(wire_39069600_stb),
.output_z_ack(wire_39069600_ack));
file_reader_b file_reader_b_39759816(
.clk(clk),
.rst(rst),
.output_z(wire_39795024),
.output_z_stb(wire_39795024_stb),
.output_z_ack(wire_39795024_ack));
file_writer file_writer_39028208(
.clk(clk),
.rst(rst),
.input_a(wire_39795168),
.input_a_stb(wire_39795168_stb),
.input_a_ack(wire_39795168_ack));
divider divider_39759952(
.clk(clk),
.rst(rst),
.input_a(wire_39069600),
.input_a_stb(wire_39069600_stb),
.input_a_ack(wire_39069600_ack),
.input_b(wire_39795024),
.input_b_stb(wire_39795024_stb),
.input_b_ack(wire_39795024_ack),
.output_z(wire_39795168),
.output_z_stb(wire_39795168_stb),
.output_z_ack(wire_39795168_ack));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9, MAXN = 4010; int n; inline int pack(int l, int r, int k) { return (l << 19) + (r << 7) + k; } unordered_map<int, int> dp(MAXN* MAXN * 2); vector<int> a, pref; int calc(int l, int r, int k, int p) { if (p) { if (dp.count(pack(l, r, k))) return dp[pack(l, r, k)]; if (r - l + 1 < k) return dp[pack(l, r, k)] = 0; if (r - l + 1 == k) return dp[pack(l, r, k)] = (calc(l + k, r, k, p ^ 1) + (pref[l + k - 1] - pref[l - 1])); return dp[pack(l, r, k)] = max( calc(l + k, r, k, p ^ 1) + (pref[l + k - 1] - pref[l - 1]), calc(l + k + 1, r, k + 1, p ^ 1) + (pref[l + k] - pref[l - 1])); } if (r - l + 1 < k) return 0; if (r - l + 1 == k) return calc(l, r - k, k, p ^ 1) - (pref[r] - pref[r - k]); return min(calc(l, r - k, k, p ^ 1) - (pref[r] - pref[r - k]), calc(l, r - k - 1, k + 1, p ^ 1) - (pref[r] - pref[r - k - 1])); } int main() { ios::sync_with_stdio(0); cin.tie(nullptr); cout.tie(nullptr); cin >> n; a.resize(n); pref.resize(n + 1); for (int i = 0; i < n; i++) { cin >> a[i]; pref[i + 1] = pref[i] + a[i]; } cout << calc(1, n, 1, 1) << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int INFint = 2147483647; const long long INF = 9223372036854775807ll; const long long MOD = 1000000007ll; long long cnt[100000]; int main() { ios_base::sync_with_stdio(0); long long a; cin >> a; string s; cin >> s; for (int i = 0; i < s.size(); i++) { long long sum = 0; for (int j = i; j < s.size(); j++) { sum += s[j] - 0 ; cnt[sum]++; } } long long ans = 0; if (a == 0) { ans = cnt[0] * cnt[0]; for (int i = 1; i < 100000; i++) { ans += cnt[0] * cnt[i] * 2; } } else { for (int i = 1; i < 100000; i++) { if (i <= a) { if (a % i == 0 && a / i < 100000) ans += cnt[i] * cnt[a / i]; } else break; } } cout << ans << endl; fprintf(stderr, nTIME = %lf n , 1.0 * clock() / CLOCKS_PER_SEC); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxN = 1e5 + 5; long double N, t; long double Pow(long double b, long long e) { if (e == 0) return 1; long double ret = Pow(b, e / 2); ret *= ret; if (e % 2) return ret * b; return ret; } int main() { cin >> N >> t; N *= Pow(1.000000011, t); printf( %.12lf , (double)N); } |
#include <bits/stdc++.h> using namespace std; int main() { long long n; scanf( %lld , &n); long long a[n + 100]; for (long long i = 0; i < n; i++) scanf( %lld , &a[i]); sort(a, a + n); long long q, x; scanf( %lld , &q); while (q--) { long long c = 0; scanf( %lld , &x); cout << upper_bound(a, a + n, x) - a << endl; } } |
#include <bits/stdc++.h> using namespace std; long long int e, d, c, x, aux, aux2; priority_queue<pair<long long int, long long int> > q; void res(long long int n) { long long int k = n; e = 0; d = 1; while (k > 0) { d = d * 10 + 1; e++; k = k / 10; } c = (d - 1) / 10; if (c > n) { d = c; c = (d - 1) / 10; e--; } } void dis(long long v) { q.push(make_pair(0, v)); aux = q.top().second; while (aux != 0) { res(aux); aux2 = q.top().first; q.pop(); if (d - aux < aux) q.push(make_pair(aux2 - (e + 1), d - aux)); q.push(make_pair(aux2 - e, aux - c)); aux = q.top().second; } x = q.top().first; } int main() { long long int a; cin >> a; dis(a); cout << x * -1 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { char ch; string s1, s2; int S = 1, H = 2, D = 3, C = 4; int T = 10, J = 11, Q = 12, K = 13, A = 14; cin >> ch >> s1 >> s2; if (s1[1] == ch && s2[1] != ch) cout << YES n ; else if (s1[1] == s2[1]) { if (s1[0] == A && s2[0] != !A ) cout << YES n ; else if (s1[0] == K && ((s2[0] == Q ) || (s2[0] == J ) || (s2[0] == T ) || (s2[0] == 9 ) || (s2[0] == 8 ) || (s2[0] == 7 ) || (s2[0] == 6 ))) cout << YES n ; else if (s1[0] == Q && ((s2[0] == J ) || (s2[0] == T ) || (s2[0] == 9 ) || (s2[0] == 8 ) || (s2[0] == 7 ) || (s2[0] == 6 ))) cout << YES n ; else if (s1[0] == J && ((s2[0] == T ) || (s2[0] == 9 ) || (s2[0] == 8 ) || (s2[0] == 7 ) || (s2[0] == 6 ))) cout << YES n ; else if (s1[0] == T && ((s2[0] == 9 ) || (s2[0] == 8 ) || (s2[0] == 7 ) || (s2[0] == 6 ))) cout << YES n ; else if (s1[0] == 9 && ((s2[0] == 8 ) || (s2[0] == 7 ) || (s2[0] == 6 ))) cout << YES n ; else if (s1[0] == 8 && ((s2[0] == 7 ) || (s2[0] == 6 ))) cout << YES n ; else if (s1[0] == 7 && (s2[0] == 6 )) cout << YES n ; else cout << NO n ; } else cout << NO n ; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 5; const int inf = 1e9 + 7; long long n, m, k, w; long long dp1[maxn]; long long dp2[maxn]; int d1[maxn]; int d2[maxn]; long long a, b; inline int low_bit(int x) { return x & (-x); } inline void upd1(int p, int x) { while (p <= n) { dp1[p] += x; p += low_bit(p); } return; } inline void upd2(int p, int x) { while (p <= n) { dp2[p] += x; p += low_bit(p); } return; } inline int query1(int p) { int sum = 0; while (p > 0) { sum += dp1[p]; p -= low_bit(p); } return sum; } inline int query2(int p) { int sum = 0; while (p > 0) { sum += dp2[p]; p -= low_bit(p); } return sum; } inline int query(int p) { return query1(p - 1) + query2(n) - query2(p + k - 1); } int main() { long long ans = 0; cin >> n >> k >> a >> b >> m; for (int i = 1; i <= m; i++) { int op; scanf( %d , &op); if (op == 1) { int x, y; scanf( %d%d , &x, &y); int p1 = d1[x]; int p2 = d2[x]; int to1 = 0, to2 = 0; to1 = b - p1; to2 = a - p2; upd1(x, y > to1 ? to1 : y); upd2(x, y > to2 ? to2 : y); d1[x] += y > to1 ? to1 : y; d2[x] += y > to2 ? to2 : y; } else { int x; scanf( %d , &x); cout << query(x) << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int NR = 5005; void Min(int& x, int y) { x = min(x, y); } void Max(int& x, int y) { x = max(x, y); } int read() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = (x << 3) + (x << 1) + (ch ^ 48); ch = getchar(); } return x * f; } int n, m; char s[NR << 1]; int sa[NR << 1], id[NR << 1]; int rk[NR << 1], lark[NR << 1]; int cnt[NR]; int h[NR << 1]; int dp[NR << 1]; int mn[NR][NR]; void work() { memset(s, 0, sizeof(s)); memset(sa, 0, sizeof(sa)); memset(rk, 0, sizeof(rk)); n = read(), scanf( %s , s + 1); m = max(n, 300); memset(cnt, 0, sizeof(cnt)); for (int i = 1; i <= n; i++) cnt[rk[i] = s[i]]++; for (int i = 1; i <= m; i++) cnt[i] += cnt[i - 1]; for (int i = n; i >= 1; i--) sa[cnt[rk[i]]--] = i; for (int w = 1; w < n; w <<= 1) { memset(cnt, 0, sizeof(cnt)); int p = 0; for (int i = n - w + 1; i <= n; i++) id[++p] = i; for (int i = 1; i <= n; i++) if (sa[i] > w) id[++p] = sa[i] - w; for (int i = 1; i <= n; i++) cnt[rk[id[i]]]++; for (int i = 1; i <= m; i++) cnt[i] += cnt[i - 1]; for (int i = n; i >= 1; i--) sa[cnt[rk[id[i]]]--] = id[i]; memcpy(lark, rk, sizeof(lark)); rk[sa[1]] = m = 1; for (int i = 2; i <= n; i++) { if (lark[sa[i]] == lark[sa[i - 1]] && lark[sa[i] + w] == lark[sa[i - 1] + w]) rk[sa[i]] = m; else rk[sa[i]] = ++m; } } memset(h, 0, sizeof(h)); int lcp = 0; for (int i = 1; i <= n; i++) { if (lcp) lcp--; while (s[i + lcp] == s[sa[rk[i] - 1] + lcp]) lcp++; h[rk[i]] = lcp; } for (int i = 1; i <= n; i++) { mn[i][i] = h[i]; for (int j = i + 1; j <= n; j++) mn[i][j] = min(mn[i][j - 1], h[j]); } int ans = 0; memset(dp, 0, sizeof(dp)); for (int i = 1; i <= n; i++) { int len = dp[i] = n - i + 1; for (int j = 1; j < i; j++) { if (rk[i] < rk[j]) continue; dp[i] = max(dp[i], dp[j] + len - mn[rk[j] + 1][rk[i]]); } ans = max(ans, dp[i]); } printf( %d n , ans); for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) mn[i][j] = 0; } int main() { int T = read(); while (T--) work(); return 0; } |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2014 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2014.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Differential Bidirectional I/O Buffer with Offset Calibration
// /___/ /\ Filename : IOBUFDSE3.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module IOBUFDSE3 #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter DIFF_TERM = "FALSE",
parameter DQS_BIAS = "FALSE",
parameter IBUF_LOW_PWR = "TRUE",
parameter IOSTANDARD = "DEFAULT",
parameter integer SIM_INPUT_BUFFER_OFFSET = 0,
parameter USE_IBUFDISABLE = "FALSE"
)(
output O,
inout IO,
inout IOB,
input DCITERMDISABLE,
input I,
input IBUFDISABLE,
input [3:0] OSC,
input [1:0] OSC_EN,
input T
);
// define constants
localparam MODULE_NAME = "IOBUFDSE3";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam DIFF_TERM_FALSE = 0;
localparam DIFF_TERM_TRUE = 1;
localparam DQS_BIAS_FALSE = 0;
localparam DQS_BIAS_TRUE = 1;
localparam IBUF_LOW_PWR_FALSE = 1;
localparam IBUF_LOW_PWR_TRUE = 0;
localparam USE_IBUFDISABLE_FALSE = 0;
localparam USE_IBUFDISABLE_TRUE = 1;
// include dynamic registers - XILINX test only
reg trig_attr = 1'b0;
localparam [40:1] DIFF_TERM_REG = DIFF_TERM;
localparam [40:1] DQS_BIAS_REG = DQS_BIAS;
localparam [40:1] IBUF_LOW_PWR_REG = IBUF_LOW_PWR;
localparam integer SIM_INPUT_BUFFER_OFFSET_REG = SIM_INPUT_BUFFER_OFFSET;
localparam [40:1] USE_IBUFDISABLE_REG = USE_IBUFDISABLE;
wire DIFF_TERM_BIN;
wire DQS_BIAS_BIN;
wire IBUF_LOW_PWR_BIN;
wire USE_IBUFDISABLE_BIN;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
reg O_out;
wire IO_out;
wire IOB_out;
reg O_OSC_in;
wire O_delay;
wire DCITERMDISABLE_in;
wire IBUFDISABLE_in;
wire I_in;
wire IO_in;
wire IOB_in;
wire T_in;
wire [1:0] OSC_EN_in;
wire [3:0] OSC_in;
wire DCITERMDISABLE_delay;
wire IBUFDISABLE_delay;
wire I_delay;
wire IOB_delay_I;
wire IO_delay_I;
wire IO_delay_O;
wire IOB_delay_O;
wire T_delay;
wire [1:0] OSC_EN_delay;
wire [3:0] OSC_delay;
wire ts;
integer OSC_int = 0;
wire not_t_or_ibufdisable;
assign not_t_or_ibufdisable = ~T_in || IBUFDISABLE_in;
tri0 GTS = glbl.GTS;
or O1 (ts, GTS, T_in);
bufif0 B1 (IO_out, I_in, ts);
notif0 N1 (IOB_out, I_in, ts);
assign #(out_delay) O = O_delay;
assign #(out_delay) IO = IO_delay_O;
assign #(out_delay) IOB = IOB_delay_O;
// inputs with no timing checks
assign #(in_delay) IOB_delay_I = IOB;
assign #(in_delay) DCITERMDISABLE_delay = DCITERMDISABLE;
assign #(in_delay) IBUFDISABLE_delay = IBUFDISABLE;
assign #(in_delay) I_delay = I;
assign #(in_delay) IO_delay_I = IO;
assign #(in_delay) OSC_EN_delay = OSC_EN;
assign #(in_delay) OSC_delay = OSC;
assign #(in_delay) T_delay = T;
// assign O_delay = O_out;
assign IO_delay_O = IO_out;
assign IOB_delay_O = IOB_out;
assign DCITERMDISABLE_in = DCITERMDISABLE_delay;
assign IBUFDISABLE_in = IBUFDISABLE_delay;
assign I_in = I_delay;
assign IO_in = IO_delay_I;
assign IOB_in = IOB_delay_I;
assign OSC_EN_in = OSC_EN_delay;
assign OSC_in = OSC_delay;
assign T_in = T_delay;
assign O_delay = (OSC_EN_in === 2'b11) ? O_OSC_in : (OSC_EN_in === 2'b10 || OSC_EN_in === 2'b01) ? 1'bx : O_out;
always @ (OSC_in or OSC_EN_in) begin
OSC_int = OSC_in[2:0] * 5;
if (OSC_in[3] == 1'b0 )
OSC_int = -1*OSC_int;
if(OSC_EN_in == 1'b1) begin
if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) < 0)
O_OSC_in <= 1'b0;
else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) > 0)
O_OSC_in <= 1'b1;
else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) == 0)
O_OSC_in <= ~O_OSC_in;
end
end
initial begin
if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int)< 0)
O_OSC_in <= 1'b0;
else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) > 0)
O_OSC_in <= 1'b1;
else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) == 0)
O_OSC_in <= 1'bx;
end
assign DIFF_TERM_BIN =
(DIFF_TERM_REG == "FALSE") ? DIFF_TERM_FALSE :
(DIFF_TERM_REG == "TRUE") ? DIFF_TERM_TRUE :
DIFF_TERM_FALSE;
assign DQS_BIAS_BIN =
(DQS_BIAS_REG == "FALSE") ? DQS_BIAS_FALSE :
(DQS_BIAS_REG == "TRUE") ? DQS_BIAS_TRUE :
DQS_BIAS_FALSE;
assign IBUF_LOW_PWR_BIN =
(IBUF_LOW_PWR_REG == "TRUE") ? IBUF_LOW_PWR_TRUE :
(IBUF_LOW_PWR_REG == "FALSE") ? IBUF_LOW_PWR_FALSE :
IBUF_LOW_PWR_TRUE;
assign USE_IBUFDISABLE_BIN =
(USE_IBUFDISABLE_REG == "FALSE") ? USE_IBUFDISABLE_FALSE :
(USE_IBUFDISABLE_REG == "TRUE") ? USE_IBUFDISABLE_TRUE :
USE_IBUFDISABLE_FALSE;
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((SIM_INPUT_BUFFER_OFFSET_REG < -50) || (SIM_INPUT_BUFFER_OFFSET_REG > 50))) begin
$display("Error: [Unisim %s-105] SIM_INPUT_BUFFER_OFFSET attribute is set to %d. Legal values for this attribute are -50 to 50. Instance: %m", MODULE_NAME, SIM_INPUT_BUFFER_OFFSET_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(DIFF_TERM_REG != "TRUE" && DIFF_TERM_REG != "FALSE")) begin
$display("Error: [Unisim %s-101] DIFF_TERM attribute is set to %s. Legal values for this attribute are TRUE or FALSE. . Instance: %m", MODULE_NAME, DIFF_TERM_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DQS_BIAS_REG != "FALSE") &&
(DQS_BIAS_REG != "TRUE"))) begin
$display("Error: [Unisim %s-102] DQS_BIAS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, DQS_BIAS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IBUF_LOW_PWR_REG != "TRUE") &&
(IBUF_LOW_PWR_REG != "FALSE"))) begin
$display("Error: [Unisim %s-103] IBUF_LOW_PWR attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, IBUF_LOW_PWR_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((USE_IBUFDISABLE_REG != "FALSE") &&
(USE_IBUFDISABLE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-107] USE_IBUFDISABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, USE_IBUFDISABLE_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
always @(IO_in or IOB_in or DQS_BIAS_BIN or not_t_or_ibufdisable or USE_IBUFDISABLE_BIN) begin
if (USE_IBUFDISABLE_BIN == 1'b1 && not_t_or_ibufdisable == 1'b1)
O_out <= 1'b0;
else if ((USE_IBUFDISABLE_BIN == 1'b1 && not_t_or_ibufdisable == 1'b0) || (USE_IBUFDISABLE_BIN == 1'b0)) begin
if (IO_in == 1'b1 && IOB_in == 1'b0)
O_out <= 1'b1;
else if (IO_in == 1'b0 && IOB_in == 1'b1)
O_out <= 1'b0;
else if ((IO_in === 1'bz || IO_in == 1'b0) && (IOB_in === 1'bz || IOB_in == 1'b1))
if (DQS_BIAS_BIN == 1'b1)
O_out <= 1'b0;
else
O_out <= 1'bx;
else if ((IO_in === 1'bx) || (IOB_in === 1'bx))
O_out <= 1'bx;
end
else begin
O_out <= 1'bx;
end
end
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; string s; pair<int, int> a[100003]; int l = 0; bool lios(string s) { if (s.size() < 4) return false; if (s.substr(s.size() - 4, 4) == lios ) return true; return false; } bool liala(string s) { if (s.size() < 5) return false; if (s.substr(s.size() - 5, 5) == liala ) return true; return false; } bool etr(string s) { if (s.size() < 3) return false; if (s.substr(s.size() - 3, 3) == etr ) return true; return false; } bool etra(string s) { if (s.size() < 4) return false; if (s.substr(s.size() - 4, 4) == etra ) return true; return false; } bool initis(string s) { if (s.size() < 6) return false; if (s.substr(s.size() - 6, 6) == initis ) return true; return false; } bool inites(string s) { if (s.size() < 6) return false; if (s.substr(s.size() - 6, 6) == inites ) return true; return false; } bool adj, n, v; int main() { while (cin >> s) { a[l].first = -1, a[l].second = -1; if (lios(s)) { a[l++] = pair<int, int>{0, 0}; continue; } if (liala(s)) { a[l++] = pair<int, int>{0, 1}; continue; } if (etr(s)) { a[l++] = pair<int, int>{1, 0}; continue; } if (etra(s)) { a[l++] = pair<int, int>{1, 1}; continue; } if (initis(s)) { a[l++] = pair<int, int>{2, 0}; continue; } if (inites(s)) { a[l++] = pair<int, int>{2, 1}; continue; } l++; } if (l == 1 && a[0].first != -1) { cout << YES ; return 0; } for (int i = 0; i < l; i++) { if (a[i].first == -1) { cout << NO ; return 0; } if (i == 0) ; else { if (a[i].second != a[i - 1].second) { cout << NO ; return 0; } } if (a[i].first == 0) { if (n || v) { cout << NO ; return 0; } adj = 1; continue; } if (a[i].first == 1) { if (n || v) { cout << NO ; return 0; } n = 1; continue; } if (a[i].first == 2) { if (!n) { cout << NO ; return 0; } v = 1; continue; } } if (!n) cout << NO ; else cout << YES ; return 0; } |
`timescale 1ns / 1ps
module alu(a,b,aluc,result
);
input wire [31:0] a,b;
input wire [4:0] aluc;
output reg [31:0] result;
always @*
begin
case(aluc)
5'd0://0:add
result=a+b;
5'd1://1:addu
result=a+b;
5'd2://2:sub
result=a-b;
5'd3://3:subu
result=a-b;
5'd4://4:and
result=a&b;
5'd5://5:or
result=a|b;
5'd6://6:xor
result=a^b;
5'd7://7:nor
result=~(a|b);
5'd8://8:slt
result=(a[31]^b[31])?(a[31]?1:0):(a<b);
5'd9://9:sltu
result=a<b;
5'd10://10:sll
result=b<<a;
5'd11://11:srl
result=b>>a;
5'd12://12:sra
begin
case(a[4:0])
5'd0:result=b;
5'd1:result={b[31],b[31:1]};
5'd2:result={{2{b[31]}},b[31:2]};
5'd3:result={{3{b[31]}},b[31:3]};
5'd4:result={{4{b[31]}},b[31:4]};
5'd5:result={{5{b[31]}},b[31:5]};
5'd6:result={{6{b[31]}},b[31:6]};
5'd7:result={{7{b[31]}},b[31:7]};
5'd8:result={{8{b[31]}},b[31:8]};
5'd9:result={{9{b[31]}},b[31:9]};
5'd10:result={{10{b[31]}},b[31:10]};
5'd11:result={{11{b[31]}},b[31:11]};
5'd12:result={{12{b[31]}},b[31:12]};
5'd13:result={{13{b[31]}},b[31:13]};
5'd14:result={{14{b[31]}},b[31:14]};
5'd15:result={{15{b[31]}},b[31:15]};
5'd16:result={{16{b[31]}},b[31:16]};
5'd17:result={{17{b[31]}},b[31:17]};
5'd18:result={{18{b[31]}},b[31:18]};
5'd19:result={{19{b[31]}},b[31:19]};
5'd20:result={{20{b[31]}},b[31:20]};
5'd21:result={{21{b[31]}},b[31:21]};
5'd22:result={{22{b[31]}},b[31:22]};
5'd23:result={{23{b[31]}},b[31:23]};
5'd24:result={{24{b[31]}},b[31:24]};
5'd25:result={{25{b[31]}},b[31:25]};
5'd26:result={{26{b[31]}},b[31:26]};
5'd27:result={{27{b[31]}},b[31:27]};
5'd28:result={{28{b[31]}},b[31:28]};
5'd29:result={{29{b[31]}},b[31:29]};
5'd30:result={{30{b[31]}},b[31:30]};
5'd31:result={32{b[31]}};
endcase
end
5'd14://14 lui
result={b[15:0],16'b0};
default:
begin
result=0;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> bool visited[200010] = {0}; int first[200010], second[200010], thrid[200010], count = 0; std::set<long long int> happened; long long int f(int one, int two) { return (1LL * 1e6 * std::min(one, two) + std::max(one, two)); } int dfs(int current, std::vector<std::vector<int> > &g, int parent = -1) { if (visited[current]) return current; visited[current] = 1; std::vector<int> s; for (int i = 0; i < g[current].size(); ++i) { if (g[current][i] != parent) { int value = dfs(g[current][i], g, current); if (value != -1 && happened.find(f(g[current][i], current)) == happened.end()) { s.push_back(value); } } } int ffirst = 0, ssecond = 1; while (ssecond < s.size()) { happened.insert(f(s[ffirst], current)); happened.insert(f(s[ssecond], current)); first[count] = s[ffirst]; second[count] = current; thrid[count] = s[ssecond]; ++count; ffirst += 2; ssecond += 2; } if (ffirst == s.size()) return current; if (parent != -1) { first[count] = s[ffirst]; second[count] = current; thrid[count] = parent; ++count; happened.insert(f(s[ffirst], current)); happened.insert(f(current, parent)); } return -1; } int main() { int n, m; std::cin >> n >> m; std::vector<std::vector<int> > g(n); for (int i = 0; i < m; ++i) { int x, y; std::cin >> x >> y; --x; --y; g[x].push_back(y); g[y].push_back(x); } for (int i = 0; i < n; ++i) { if (!visited[i]) { dfs(i, g); } } std::cout << count << n ; for (int i = 0; i < count; ++i) { std::cout << first[i] + 1 << << second[i] + 1 << << thrid[i] + 1 << n ; } } |
/*
L2 Data Cache
This version will use the Cache as RAM,
0C00_0000 .. 0C00_7FFF
May be accessed either as 128 bit tiles, or as 32 or 64 bit words.
MMIO may only be accessed as 32-bits.
*/
`include "CoreDefs.v"
module Dc2Tile(
/* verilator lint_off UNUSED */
clock, reset,
regInAddr, regInData,
regOutData, regOutOK,
regInOE, regInWR,
regInOp,
memInData, memOutData, memAddr,
memOE, memWR, memOK,
mmioInData, mmioOutData, mmioAddr,
mmioOE, mmioWR, mmioOK
);
input clock; //clock
input reset; //reset
input[31:0] regInAddr; //input PC address
input[127:0] regInData; //input data (store)
input regInOE; //Load
input regInWR; //Store
input[4:0] regInOp; //Operation Size/Type
output[127:0] regOutData; //output data (load)
output[1:0] regOutOK; //set if operation suceeds
input[127:0] memInData; //memory PC data
output[127:0] memOutData; //memory PC data
output[31:0] memAddr; //memory PC address
output memOE; //memory PC output-enable
output memWR; //memory PC output-enable
input[1:0] memOK; //memory PC OK
reg[127:0] tMemOutData; //memory PC data
reg[31:0] tMemAddr; //memory PC address
reg tMemOE; //memory PC output-enable
reg tMemWR; //memory PC output-enable
assign memOutData = tMemOutData;
assign memAddr = tMemAddr;
assign memOE = tMemOE;
assign memWR = tMemWR;
input[31:0] mmioInData; //mmio data in
output[31:0] mmioOutData; //mmio data out
output[31:0] mmioAddr; //mmio address
output mmioOE; //mmio read
output mmioWR; //mmio write
input[1:0] mmioOK; //mmio OK
reg[31:0] tMmioOutData; //mmio data out
reg[31:0] tMmioAddr; //mmio address
reg tMmioOE; //mmio read
reg tMmioWR; //mmio write
assign mmioOutData = tMmioOutData;
assign mmioAddr = tMmioAddr;
assign mmioOE = tMmioOE;
assign mmioWR = tMmioWR;
// (* ram_style="block" *) reg[127:0] memTile[2047:0]; //memory
(* ram_style="block" *) reg[31:0] memTileA[0:2047]; //memory
(* ram_style="block" *) reg[31:0] memTileB[0:2047]; //memory
(* ram_style="block" *) reg[31:0] memTileC[0:2047]; //memory
(* ram_style="block" *) reg[31:0] memTileD[0:2047]; //memory
(* ram_style="block" *) reg[127:0] romTile[255:0]; //ROM
// reg[127:0] tRomTile;
reg[127:0] tRamTile;
reg[10:0] tAccTileIx;
reg[127:0] tMemTile;
reg[127:0] tOutData;
reg[127:0] tNextTile;
reg[10:0] tRegTileIx;
reg[10:0] tNextTileIx;
reg tNextTileSt;
reg[1:0] tRegOutOK;
wire addrIsRam;
assign addrIsRam =
(regInAddr[28:0] >= 29'h0C00_0000) &&
(regInAddr[28:0] <= 29'h1E00_0000) ;
wire addrIsRom;
assign addrIsRom =
(regInAddr[28:0] <= 29'h0010_0000) ;
assign regOutData = tOutData;
assign regOutOK = tRegOutOK;
initial begin
$readmemh("bootrom.txt", romTile);
end
always @*
begin
tMemTile = 0;
tOutData = 0;
tNextTile = 0;
tRegTileIx = regInAddr[14:4];
tNextTileIx = tRegTileIx;
tNextTileSt = 0;
tRegOutOK = 0;
tMemOutData = 0; //memory PC data
tMemAddr = 0; //memory PC address
tMemOE = 0; //memory PC output-enable
tMemWR = 0; //memory PC output-enable
tMmioOutData = 0; //mmio data out
tMmioAddr = 0; //mmio address
tMmioOE = 0; //mmio read
tMmioWR = 0; //mmio write
if(regInOE || regInWR)
begin
$display("DcTile2 %X %d %d", regInAddr, addrIsRom, addrIsRam);
if(addrIsRom)
begin
tMemTile = romTile[tRegTileIx[7:0]];
// tMemTile = tRomTile;
tNextTile = tMemTile;
tRegOutOK = 1;
// tRegOutOK = (tAccTileIx == tRegTileIx) ?
// UMEM_OK_OK : UMEM_OK_HOLD;
$display("Rom: %X", tMemTile);
case(regInOp[1:0])
2'b00:
tOutData=tMemTile;
2'b01:
tOutData=tMemTile;
2'b10: case(regInAddr[3:2])
2'b00: tOutData={96'h0, tMemTile[ 31: 0]};
2'b01: tOutData={96'h0, tMemTile[ 63:32]};
2'b10: tOutData={96'h0, tMemTile[ 95:64]};
2'b11: tOutData={96'h0, tMemTile[127:96]};
endcase
2'b11: begin
if(regInAddr[3])
tOutData={64'h0, tMemTile[127:64]};
else
tOutData={64'h0, tMemTile[ 63: 0]};
end
endcase
$display("Rom: Out=%X", tOutData);
end
else
if(addrIsRam)
begin
// tMemTile = memTile[tRegTileIx];
// tMemTile[ 31: 0] = memTileA[tRegTileIx];
// tMemTile[ 63:32] = memTileB[tRegTileIx];
// tMemTile[ 95:64] = memTileC[tRegTileIx];
// tMemTile[127:96] = memTileD[tRegTileIx];
tMemTile = tRamTile;
tNextTile = tMemTile;
// tRegOutOK = 1;
tRegOutOK = (tAccTileIx == tRegTileIx) ?
UMEM_OK_OK : UMEM_OK_HOLD;
case(regInOp[1:0])
2'b00:
tOutData=tMemTile;
2'b01:
tOutData=tMemTile;
2'b10: case(regInAddr[3:2])
2'b00: tOutData={96'h0, tMemTile[ 31: 0]};
2'b01: tOutData={96'h0, tMemTile[ 63:32]};
2'b10: tOutData={96'h0, tMemTile[ 95:64]};
2'b11: tOutData={96'h0, tMemTile[127:96]};
endcase
2'b11: begin
if(regInAddr[3])
tOutData={64'h0, tMemTile[127:64]};
else
tOutData={64'h0, tMemTile[ 63: 0]};
end
endcase
if(regInWR)
begin
tNextTileIx = tRegTileIx;
tNextTileSt = 1;
case(regInOp[1:0])
2'b00:
tNextTile=regInData;
2'b01:
tNextTile=regInData;
2'b10: case(regInAddr[3:2])
2'b00: tNextTile[ 31: 0] = regInData[31:0];
2'b01: tNextTile[ 63:32] = regInData[31:0];
2'b10: tNextTile[ 95:64] = regInData[31:0];
2'b11: tNextTile[127:96] = regInData[31:0];
endcase
2'b11: begin
if(regInAddr[3])
tNextTile[127:64] = regInData[63:0];
else
tNextTile[ 63: 0] = regInData[63:0];
end
endcase
end
end
else
begin
tMmioOutData = regInData[31:0];
tMmioAddr = regInAddr;
tMmioOE = regInOE;
tMmioWR = regInWR;
tRegOutOK = mmioOK;
tOutData = { 96'h0, mmioInData[31:0] };
end
end
end
always @ (posedge clock)
begin
// tRomTile <= romTile[tRegTileIx[7:0]];
// tRamTile <= memTile[tRegTileIx];
tRamTile[ 31: 0] <= memTileA[tRegTileIx];
tRamTile[ 63:32] <= memTileB[tRegTileIx];
tRamTile[ 95:64] <= memTileC[tRegTileIx];
tRamTile[127:96] <= memTileD[tRegTileIx];
tAccTileIx <= tRegTileIx;
if(tNextTileSt)
begin
// memTile[tNextTileIx] <= tNextTile;
memTileA[tNextTileIx] <= tNextTile[ 31: 0];
memTileB[tNextTileIx] <= tNextTile[ 63:32];
memTileC[tNextTileIx] <= tNextTile[ 95:64];
memTileD[tNextTileIx] <= tNextTile[127:96];
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int test = 1; cin >> test; while (test--) { long long int n, m; cin >> n >> m; long long int sum1 = 0, sum2 = 0; long long int a[n], b[n], mina[n], mi = 0; for (int i = 0; i < n; i++) { cin >> a[i] >> b[i]; sum1 += a[i]; sum2 += b[i]; mina[i] = max(0LL, m - b[i]); mi += mina[i]; a[i] = min(a[i], m); } long long int ans = sum1 - sum2 + (n * m); long long int x = ans - 2LL * mi; for (int i = 0; i < n; i++) { if (x <= 0) break; long long int temp = min(2LL * (a[i] - mina[i]), x); temp /= 2; mina[i] += temp; x -= 2LL * temp; } cout << abs(x) << n ; for (int i = 0; i < n; i++) cout << mina[i] << << m - mina[i] << n ; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A221OI_FUNCTIONAL_V
`define SKY130_FD_SC_LP__A221OI_FUNCTIONAL_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a221oi (
Y ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Local signals
wire and0_out ;
wire and1_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
nor nor0 (nor0_out_Y, and0_out, C1, and1_out);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A221OI_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; const int MAX = 1000; long long d[MAX + 10][3][3]; string s; int n; long long dyn() { if (s[1] == 0) d[1][0][0] = 1; d[1][0][2] = 1; if (s[0] == 0 && s[1] == 1) d[1][1][1] = 1; if (s[0] == 1) d[1][2][2] = 1; for (int i = 1; i <= n - 2; i++) for (int k = 0; k < 3; k++) for (int l = 0; l < 3; l++) for (int j = 0; j < 2; j++) { if (l == 0 || l == 1) { if (j == 0) { if (s[i + 1] == 0) d[i + 1][k][0] += d[i][k][l]; } else { d[i + 1][k][2] += d[i][k][l]; } } else if (l == 2) { if (j == 0) { if (s[i] == 0 && s[i + 1] == 1) d[i + 1][k][1] += d[i][k][l]; } else { if (s[i] == 1) d[i + 1][k][2] += d[i][k][l]; } } } long long sum = 0; for (int k = 0; k < 3; k++) for (int l = 0; l < 3; l++) { if (k == 0) { if (l == 2) { if (s[0] == 1 && s[n - 1] == 0) sum += d[n - 1][k][l]; } else { if (s[0] == 0) sum += d[n - 1][k][l]; } } else { if (l == 2) { if (s[n - 1] == 1) sum += d[n - 1][k][l]; } else { sum += d[n - 1][k][l]; } } } return sum; } int main() { cin >> s; n = (int)s.size(); for (int i = 0; i < n; i++) { s[i] -= A ; s[i] = !s[i]; } cout << dyn() << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long MAX = (long long)1e6 + 100; long long inf = (long long)1e18; long long mod = (long long)1e9 + 7; long long n, a, b, c, d; long long get_maxi() { long long uk1 = 0, uk2 = c + 1; while (uk2 - uk1 > 1) { long long mid = (uk2 + uk1) / 2; if (mid * b < a) uk1 = mid; else uk2 = mid; } return uk1; } void solve() { cin >> a >> b >> c >> d; if (c * b < a) { cout << -1 << n ; return; } long long act = get_maxi(); act -= act % d; c = act; long long am = (c / d + 1) * a - (c * (c / d + 1) / 2) * b; cout << am << n ; } int main() { mt19937_64 rng(chrono::steady_clock::now().time_since_epoch().count()); long long q; ios::sync_with_stdio(0); cin >> q; while (q--) solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; void print(int a) { cout << a << ; } void print(long long a) { cout << a << ; } void print(double a) { cout << a << ; } void print(string a) { cout << a << ; } template <typename T1, typename T2> void print(pair<T1, T2> a) { print(a.first); cout << ::: ; print(a.second); } template <typename Container> void print(const Container& c) { for (auto it = c.begin(); it != c.end(); it++) { print(*it); } cout << endl; } vector<long long> tot_comb(51, 0); vector<long long> fac(51, 1); int CALC_MAX = 0; long long INF = 2e18; long long get_fac(int x) { if (x <= 0) return 1; return fac[x]; } long long mul(long long x, long long y) { if (x >= INF || y >= INF || x * y >= INF || x * y < 0) return INF; return x * y; } long long add(long long x, long long y) { if (x >= INF || y >= INF || x + y >= INF) return INF; return x + y; } void fill_fac() { fac[0] = 1; fac[1] = 1; for (int i = 2; i <= 50; i++) { fac[i] = mul(fac[i - 1], i); } } void fill_tot_comb() { tot_comb[0] = 1; tot_comb[1] = 1; tot_comb[2] = 2; tot_comb[3] = 4; for (int i = 4; i <= 50; i++) { tot_comb[i] = 0; for (int j = 1; j <= i; j++) { tot_comb[i] = add(tot_comb[i], mul(get_fac(j - 2), tot_comb[i - j])); } } } void KthPermhelp(int k, long long n, int st) { vector<int> perm(k + 1, 0); vector<int> pos(k + 1, 0); perm[1] = k; pos[k] = 1; long long cnt = n; vector<bool> taken(k + 1, false); taken[k] = true; for (int i = 2; i <= k; i++) { for (int j = 1; j < k; j++) { if (!taken[j]) { int jk = i; while (taken[jk]) jk = pos[jk]; if (j == jk && i != k) continue; long long tot_with_j_i = get_fac(k - 1 - i); if (cnt > tot_with_j_i) { cnt -= tot_with_j_i; } else { perm[i] = j; taken[j] = true; pos[j] = i; break; } } } } if (k == 2) { perm[1] = 2; perm[2] = 1; } for (int i = 1; i <= k; i++) cout << perm[i] + st << ; } void KthPerm(int n, long long k, int st) { if (n == 0) return; if (tot_comb[n] < k) { cout << -1; return; } for (int i = 1; i <= n; i++) { if (mul(get_fac(i - 2), tot_comb[n - i]) >= k) { KthPermhelp(i, (k / tot_comb[n - i]) + (k % tot_comb[n - i] > 0), st); KthPerm(n - i, (k % tot_comb[n - i]) + ((k % tot_comb[n - i] == 0) ? tot_comb[n - i] : 0), st + i); break; } k -= mul(get_fac(i - 2), tot_comb[n - i]); } } int main() { fill_fac(); fill_tot_comb(); int t; cin >> t; while (t--) { int n; long long int k; cin >> n >> k; KthPerm(n, k, 0); cout << endl; } } |
#include <bits/stdc++.h> using namespace std; int main() { int w, h, u1, d1, u2, d2; cin >> w >> h >> u1 >> d1 >> u2 >> d2; int ans = w; if (d1 > d2) { ans += ((d1 + h) * (h - d1 + 1)) / 2; ans -= u1; ans = max(0, ans); ans += ((d1 + d2 - 1) * (d1 - d2) / 2); ans -= u2; ans = max(0, ans); ans += ((d2) * (d2 - 1)) / 2; } else { ans += ((d2 + h) * (h - d2 + 1)) / 2; ans -= u2; ans = max(0, ans); ans += ((d2 + d1 - 1) * (d2 - d1) / 2); ans -= u1; ans = max(0, ans); ans += ((d1 - 1) * (d1)) / 2; } cout << ans << endl; return 0; } |
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 08/25/2009
Version 1.0
This block takes the length and forms the appropriate burst count.
Whenever one of the short access enables are asserted this block
will post a burst of one. Posting a burst of one isn't necessary
but it will make it possible to add byte enable support to the
read master at a later date.
Revision History:
1.0 First version
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module read_burst_control (
address,
length,
maximum_burst_count,
short_first_access_enable,
short_last_access_enable,
short_first_and_last_access_enable,
burst_count
);
parameter BURST_ENABLE = 1; // set to 0 to hardwire the address and write signals straight out
parameter BURST_COUNT_WIDTH = 3;
parameter WORD_SIZE_LOG2 = 2; // log2(DATA WIDTH/8)
parameter ADDRESS_WIDTH = 32;
parameter LENGTH_WIDTH = 32;
parameter BURST_WRAPPING_SUPPORT = 1; // set 1 for on, set 0 for off. This parameter can't be enabled when hte master supports programmable burst.
localparam BURST_OFFSET_WIDTH = (BURST_COUNT_WIDTH == 1)? 1: (BURST_COUNT_WIDTH-1);
input [ADDRESS_WIDTH-1:0] address;
input [LENGTH_WIDTH-1:0] length;
input [BURST_COUNT_WIDTH-1:0] maximum_burst_count; // will be either a hardcoded input or programmable
input short_first_access_enable;
input short_last_access_enable;
input short_first_and_last_access_enable;
output wire [BURST_COUNT_WIDTH-1:0] burst_count;
wire [BURST_COUNT_WIDTH-1:0] posted_burst; // when the burst statemachine is used this will be the burst count posted to the fabric
reg [BURST_COUNT_WIDTH-1:0] internal_burst_count; // muxes posted_burst, posted_burst_d1, and '1' since we need to be able to post bursts of '1' for short accesses
wire burst_of_one_enable; // asserted when partial word accesses are occuring
wire short_burst_enable;
wire [BURST_OFFSET_WIDTH-1:0] burst_offset;
assign burst_offset = address[BURST_OFFSET_WIDTH+WORD_SIZE_LOG2-1:WORD_SIZE_LOG2];
// for unaligned or partial transfers we must use a burst length of 1 so that
assign burst_of_one_enable = (short_first_access_enable == 1) | (short_last_access_enable == 1) | (short_first_and_last_access_enable == 1) | // when performing partial accesses use a burst length of 1
((BURST_WRAPPING_SUPPORT == 1) & (burst_offset != 0)); // when the burst boundary offset is non-zero then the master isn't in burst alignment yet as so a burst of 1 needs to be posted
assign short_burst_enable = ((length >> WORD_SIZE_LOG2) < maximum_burst_count);
always @ (maximum_burst_count or length or short_burst_enable or burst_of_one_enable)
begin
case ({short_burst_enable, burst_of_one_enable})
2'b00 : internal_burst_count = maximum_burst_count;
2'b01 : internal_burst_count = 1; // this is when the master starts unaligned
2'b10 : internal_burst_count = ((length >> WORD_SIZE_LOG2) & {(BURST_COUNT_WIDTH-1){1'b1}}); // this could be followed by a burst of 1 if there are a few bytes leftover
2'b11 : internal_burst_count = 1; // burst of 1 needs to win, this is when the master starts with very little data to transfer
endcase
end
generate
if (BURST_ENABLE == 1)
begin
assign burst_count = internal_burst_count;
end
else
begin
assign burst_count = 1; // this will be stubbed at the top level but will be used for the address and pending reads incrementing
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mx = (int)2e5 + 5; int n, c[mx], ans[mx]; char a[mx], b[mx]; void solve() { int cnt = 0, temp = 0; for (int i = n - 1; i >= 0; i--) { c[cnt++] = (a[i] + b[i] - 2 * a + temp) % 26; temp = (a[i] + b[i] - 2 * a + temp) / 26; } c[cnt++] = temp; temp = 0; for (int i = cnt - 1; i >= 0; i--) { temp *= 26; ans[i] = (c[i] + temp) / 2; temp = (c[i] + temp) % 2; } for (int i = n - 1; i >= 0; i--) { printf( %c , ans[i] + a ); } cout << endl; } int main() { cin >> n; scanf( %s%s , a, b); solve(); } |
#include <bits/stdc++.h> using namespace std; signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); string s; getline(cin, s); for (auto i = s.end() - 1; i >= s.begin(); i--) { if ((int(*i) >= 65 && (int(*i) <= 90)) || (int(*i) >= 97 && (int(*i) <= 122))) { if (*i == A || *i == E || *i == I || *i == O || *i == U || *i == a || *i == e || *i == i || *i == o || *i == u || *i == y || *i == Y ) cout << YES ; else cout << NO ; return 0; } } } |
#include <bits/stdc++.h> using namespace std; void solve() { int n; string s, t, ss; cin >> n >> s; ss = s; t = abacaba ; int cnt = 0; for (int i = 0; i < n - 6; i++) { int j, k = 0; for (j = i; j < i + 7; j++) { if (s[j] != t[k]) break; k++; } if (j == i + 7) cnt++; } if (cnt == 1) { cout << Yes << n ; for (int i = 0; i < n; i++) { if (s[i] == ? ) s[i] = z ; } cout << s << n ; } else if (cnt > 1) { cout << No << n ; return; } else { cnt = 0; for (int i = 0; i < n - 6; i++) { cnt = 0; int j, k = 0; for (j = i; j < i + 7; j++) { if (s[j] != t[k] && s[j] != ? ) break; s[j] = t[k]; k++; } if (j == i + 7) { for (int x = 0; x < n - 6; x++) { int y, z = 0; for (y = x; y < x + 7; y++) { if (s[y] != t[z]) break; z++; } if (y == x + 7) cnt++; } if (cnt == 1) { cout << Yes << n ; for (int i = 0; i < n; i++) { if (s[i] == ? ) s[i] = z ; } cout << s << n ; return; } else { for (int i = 0; i < n; i++) s[i] = ss[i]; } } else { for (int i = 0; i < n; i++) s[i] = ss[i]; } } cout << No << n ; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long tt; cin >> tt; while (tt--) solve(); return 0; } |
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module VCC (output V);
assign V = 1'b1;
endmodule // VCC
module GND (output G);
assign G = 1'b0;
endmodule // GND
/* Altera Cyclone V devices Input Buffer Primitive */
module cyclonev_io_ibuf
(output o, input i, input ibar);
assign ibar = ibar;
assign o = i;
endmodule // cyclonev_io_ibuf
/* Altera Cyclone V devices Output Buffer Primitive */
module cyclonev_io_obuf
(output o, input i, input oe);
assign o = i;
assign oe = oe;
endmodule // cyclonev_io_obuf
/* Altera Cyclone V LUT Primitive */
module cyclonev_lcell_comb
(output combout, cout, sumout, shareout,
input dataa, datab, datac, datad,
input datae, dataf, datag, cin,
input sharein);
parameter lut_mask = 64'hFFFFFFFFFFFFFFFF;
parameter dont_touch = "off";
parameter lpm_type = "cyclonev_lcell_comb";
parameter shared_arith = "off";
parameter extended_lut = "off";
// Internal variables
// Sub mask for fragmented LUTs
wire [15:0] mask_a, mask_b, mask_c, mask_d;
// Independent output for fragmented LUTs
wire output_0, output_1, output_2, output_3;
// Extended mode uses mux to define the output
wire mux_0, mux_1;
// Input for hold the shared LUT mode value
wire shared_lut_alm;
// Simulation model of 4-input LUT
function lut4;
input [15:0] mask;
input dataa, datab, datac, datad;
reg [7:0] s3;
reg [3:0] s2;
reg [1:0] s1;
begin
s3 = datad ? mask[15:8] : mask[7:0];
s2 = datac ? s3[7:4] : s3[3:0];
s1 = datab ? s2[3:2] : s2[1:0];
lut4 = dataa ? s1[1] : s1[0];
end
endfunction // lut4
// Simulation model of 5-input LUT
function lut5;
input [31:0] mask; // wp-01003.pdf, page 3: "a 5-LUT can be built with two 4-LUTs and a multiplexer.
input dataa, datab, datac, datad, datae;
reg upper_lut_value;
reg lower_lut_value;
begin
upper_lut_value = lut4(mask[31:16], dataa, datab, datac, datad);
lower_lut_value = lut4(mask[15:0], dataa, datab, datac, datad);
lut5 = (datae) ? upper_lut_value : lower_lut_value;
end
endfunction // lut5
// Simulation model of 6-input LUT
function lut6;
input [63:0] mask;
input dataa, datab, datac, datad, datae, dataf;
reg upper_lut_value;
reg lower_lut_value;
reg out_0, out_1, out_2, out_3;
begin
upper_lut_value = lut5(mask[63:32], dataa, datab, datac, datad, datae);
lower_lut_value = lut5(mask[31:0], dataa, datab, datac, datad, datae);
lut6 = (dataf) ? upper_lut_value : lower_lut_value;
end
endfunction // lut6
assign {mask_a, mask_b, mask_c, mask_d} = {lut_mask[15:0], lut_mask[31:16], lut_mask[47:32], lut_mask[63:48]};
`ifdef ADVANCED_ALM
always @(*) begin
if(extended_lut == "on")
shared_lut_alm = datag;
else
shared_lut_alm = datac;
// Build the ALM behaviour
out_0 = lut4(mask_a, dataa, datab, datac, datad);
out_1 = lut4(mask_b, dataa, datab, shared_lut_alm, datad);
out_2 = lut4(mask_c, dataa, datab, datac, datad);
out_3 = lut4(mask_d, dataa, datab, shared_lut_alm, datad);
end
`else
`ifdef DEBUG
initial $display("Advanced ALM lut combine is not implemented yet");
`endif
`endif
endmodule // cyclonev_lcell_comb
/* Altera D Flip-Flop Primitive */
module dffeas
(output q,
input d, clk, clrn, prn, ena,
input asdata, aload, sclr, sload);
// Timing simulation is not covered
parameter power_up="dontcare";
parameter is_wysiwyg="false";
reg q_tmp;
wire reset;
reg [7:0] debug_net;
assign reset = (prn && sclr && ~clrn && ena);
assign q = q_tmp & 1'b1;
always @(posedge clk, posedge aload) begin
if(reset) q_tmp <= 0;
else q_tmp <= d;
end
assign q = q_tmp;
endmodule // dffeas
|
#include <bits/stdc++.h> using namespace std; const int N = 5000 + 10; char s[N], t[N]; int n, m, dp[N][N]; int main() { scanf( %d%d%s%s , &n, &m, s + 1, t + 1); int ans = 0; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { dp[i][j] = 0; if (i >= 1) dp[i][j] = max(dp[i][j], dp[i - 1][j] - 1); if (j >= 1) dp[i][j] = max(dp[i][j], dp[i][j - 1] - 1); if (i >= 1 && j >= 1 && s[i] == t[j]) dp[i][j] = max(dp[i][j], dp[i - 1][j - 1] + 2); ans = max(ans, dp[i][j]); } } printf( %d n , ans); } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 20; const int MAXX = 65536; int n, m; long long year; vector<int> graph[MAXN], rev_graph[MAXN]; vector<int> sol; long long dp[MAXX]; long long countPermutations(int mask, int pos) { dp[0] = 1; for (int i = 1; i < 1 << (n - pos); ++i) { dp[i] = 0; } for (int i = 0; i < 1 << (n - pos); ++i) { int value = n - 1; while (value >= 0 && (mask & (1 << value))) --value; for (int j = 0; j < n - pos; ++j) if (i & (1 << j)) { do { --value; } while (value >= 0 && (mask & (1 << value))); } for (int j = 0; j < n - pos; ++j) if ((i & (1 << j)) == 0) { int ok = 1; for (size_t k = 0; k < graph[j + pos].size() && ok; ++k) if ((graph[j + pos][k] >= pos && (i & (1 << (graph[j + pos][k] - pos))) == 0) || (graph[j + pos][k] < pos && sol[graph[j + pos][k]] < value)) { ok = 0; } for (size_t k = 0; k < rev_graph[j + pos].size() && ok; ++k) if (rev_graph[j + pos][k] < pos && sol[rev_graph[j + pos][k]] > value) ok = 0; if (ok) dp[i ^ (1 << j)] += dp[i]; } } return dp[(1 << (n - pos)) - 1]; } void findPermutation(int mask, int pos) { if (pos < n) { for (int i = 0; i < n; ++i) if ((mask & (1 << i)) == 0) { int ok = 1; for (size_t j = 0; j < graph[pos].size() && ok; ++j) if (graph[pos][j] < pos && sol[graph[pos][j]] < i) ok = 0; for (size_t j = 0; j < rev_graph[pos].size() && ok; ++j) if (rev_graph[pos][j] < pos && sol[rev_graph[pos][j]] > i) ok = 0; if (!ok) { continue; } mask ^= 1 << i; sol.push_back(i); long long cnt = countPermutations(mask, pos + 1); if (cnt >= year) { findPermutation(mask, pos + 1); break; } year -= cnt; mask ^= 1 << i; sol.pop_back(); } } } int main() { cin >> n >> year >> m; year -= 2000; for (int i = 1; i <= m; ++i) { int x, y; cin >> x >> y; --x, --y; graph[x].push_back(y); rev_graph[y].push_back(x); } findPermutation(0, 0); if ((int)sol.size() != n) { cout << The times have changed n ; return 0; } for (int i = 0; i < n - 1; ++i) cout << sol[i] + 1 << ; cout << sol[n - 1] + 1 << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const long N = 1000L + 10; const long long modulo = 1000000007L; vector<pair<long, long> > interv; bool memo[N][N]; bool visited[N]; void divideByZero(const char *error) { printf(error); fclose(stdout); int a = 234; a = a / (a - a); } bool canDirectly(long a, long b, long c, long d) { return (c < a && a < d) || (c < b && b < d); } void addInterval(long x, long y) { long n = interv.size(); interv.push_back(make_pair(x, y)); for (long i = 0; i < n; i++) { if (canDirectly(interv[i].first, interv[i].second, x, y)) { memo[i][n] = true; } if (canDirectly(x, y, interv[i].first, interv[i].second)) { memo[n][i] = true; } } } bool pathExists(long from, long to) { for (long i = 0; i < N; i++) visited[i] = false; long n = interv.size(); queue<long> q; visited[from] = true; q.push(from); while (!q.empty()) { long v = q.front(); if (v == to) return true; q.pop(); for (long nb = 0; nb < n; nb++) if (memo[v][nb]) { if (visited[nb]) continue; visited[nb] = true; q.push(nb); } } return false; } int main() { long n; scanf( %ld , &n); for (long i = 0; i < n; i++) for (long j = 0; j < n; j++) memo[i][j] = false; for (long i = 0; i < n; i++) { long mode, x, y; scanf( %ld %ld %ld , &mode, &x, &y); if (mode == 1) addInterval(x, y); else { if (pathExists(x - 1, y - 1)) printf( YES n ); else printf( NO n ); } } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A32O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__A32O_FUNCTIONAL_PP_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a32o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
and and1 (and1_out , B1, B2 );
or or0 (or0_out_X , and1_out, and0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A32O_FUNCTIONAL_PP_V |
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlslice:1.0
// IP Revision: 0
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlslice_1_1 (
Din,
Dout
);
input wire [31 : 0] Din;
output wire [0 : 0] Dout;
xlslice #(
.DIN_WIDTH(32),
.DIN_FROM(0),
.DIN_TO(0)
) inst (
.Din(Din),
.Dout(Dout)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; bitset<4001> g[4001]; int main() { int n, m; cin >> n >> m; vector<pair<int, int> > v; for (int i = 0; i < m; i++) { int a, b; cin >> a >> b; a--; b--; g[a][b] = 1; g[b][a] = 1; v.push_back(pair<int, int>(a, b)); } int minx = 100000000; bool was = 0; for (int i = 0; i < v.size(); i++) { int a = v[i].first; int b = v[i].second; for (int j = 0; j < n; j++) { if (g[a][j] && g[b][j]) { minx = min(minx, (int)(g[a].count() + g[b].count() + g[j].count()) - 6); was = true; } } } if (was) cout << minx; else cout << -1; return 0; } |
#include <bits/stdc++.h> using namespace std; long long fact_a[1000005]; long long factorial() { fact_a[0] = fact_a[1] = 1; for (long long i = 2; i < 1000005; i++) fact_a[i] = (fact_a[i - 1] * i); } long long power(long long x, long long n) { long long result = 1; while (n > 0) { if (n % 2 == 1) result = result * x; x = x * x; n = n / 2; } return result; } long long nCr(long long n, long long r) { if (n < r) return 0LL; if (n == r) return 1LL; long long ans = fact_a[n]; ans = (ans * power(fact_a[r], 1000000007 - 2)) % 1000000007; ans = (ans * power(fact_a[n - r], 1000000007 - 2)) % 1000000007; return ans; } long long prime[1000005]; void sieve() { prime[1000005] = {0}; for (long long i = 2; i < 1000005; i++) { if (prime[i] == 0) { for (long long j = i * i; j < 1000005; j += i) { prime[j] = 1; } } } } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long tc; cin >> tc; while (tc--) { long long n, k; cin >> n; long long a[n]; set<long long> s; for (long long i = 0; i < n; i++) { cin >> a[i]; s.insert(a[i]); } if (s.size() == 1) cout << n << n ; else cout << 1 << n ; } } |
#include <bits/stdc++.h> using namespace std; void rd(int &x) { x = 0; int f = 1; char ch = (getchar()); while (!isdigit(ch)) { if (ch == - ) f = -1; ch = (getchar()); } while (isdigit(ch)) x = x * 10 + ch - 0 , ch = (getchar()); x *= f; } const int N = 5e5 + 5; int n, m; int a[N], c[N], tmp[N]; priority_queue<int, vector<int>, greater<int> > Q; int main() { rd(n); long long ans = 0; for (int i = 1; i <= n; ++i) rd(a[i]), ans += a[i]; sort(a + 1, a + n + 1, greater<int>()); for (int i = 1; i <= n; ++i) { int j = i; a[++m] = a[i]; while (j <= n && a[j + 1] == a[i]) ++j; c[m] = j - i + 1, i = j; } n = m; int cnt = 0, tmp0 = 0; for (int i = 1; i <= n; ++i) { int res = min(cnt - 2 * (int)Q.size(), c[i]), ok = min(c[i] - res, cnt - res); tmp0 = 0; for (int j = 1; j <= res; ++j) tmp[++tmp0] = a[i]; for (int j = 1; j <= ok; j += 2) { int val = Q.top(); Q.pop(); if (val < a[i]) { tmp[++tmp0] = a[i]; if (ok - j) tmp[++tmp0] = a[i]; } else { tmp[++tmp0] = val; if (ok - j && 2 * a[i] - val > 0) tmp[++tmp0] = 2 * a[i] - val; } } for (int j = 1; j <= tmp0; ++j) Q.push(tmp[j]); cnt += c[i]; } while (!Q.empty()) ans -= Q.top(), Q.pop(); cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); long long int num, ans = INT_MAX, temp, multi1 = INT_MAX, multi2 = INT_MAX; cin >> num; for (long long int i = 1; i <= sqrt(num); i++) { if (num % i == 0) { temp = num / i; if (abs(i - temp) < ans) ans = abs(i - temp), multi1 = i, multi2 = temp; } } cout << multi1 << << multi2; return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:36:10 11/21/2015
// Design Name: Datapath1
// Module Name: C:/Users/Ariel/Documents/finalArquitectura/TestDatapathPart1/DatapathPart1/DatapathTest.v
// Project Name: DatapathPart1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Datapath1
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module DatapathTestFinal;
// Inputs
reg clock;
reg resetGral;
// Outputs
wire ALUzero;
wire ALUOverflow;
// Instantiate the Unit Under Test (UUT)
Datapath1 uut (
.clock(clock),
.resetGral(resetGral),
.ALUzero(ALUzero),
.ALUOverflow(ALUOverflow)
);
initial begin
// Initialize Inputs
clock = 0;
resetGral = 1;
// Wait 100 ns for global reset to finish
#100;
resetGral=0;
// Add stimulus here
end
always begin
clock = ~clock;
#1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool sorting(const pair<long long int, long long int>& a, const pair<long long int, long long int>& b) { if (a.first != b.first) { return (a.first > b.first); } else return (!(a.second >= b.second)); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int n, k; cin >> n >> k; pair<long long int, long long int> v[n]; for (int i = 0; i < n; ++i) { cin >> v[i].first >> v[i].second; } sort(v, v + n, sorting); long long int ans = 0; for (int i = 0; i < n; ++i) { if (v[k - 1].first == v[i].first && v[k - 1].second == v[i].second) { ans++; } } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n; int ans = 0; int l1min = 1e9, l1max = 0, r1min = 1e9, r1max = 0; for (int i = 1; i <= n; i++) { int l, r; cin >> l >> r; l1min = min(l1min, l); l1max = max(l1max, l); r1max = max(r1max, r); r1min = min(r1min, r); } cin >> m; int l2min = 1e9, l2max = 0, r2min = 1e9, r2max = 0; for (int i = 1; i <= m; i++) { int l, r; cin >> l >> r; l2min = min(l2min, l); l2max = max(l2max, l); r2max = max(r2max, r); r2min = min(r2min, r); } ans = max(ans, l1max - r2min); ans = max(ans, l2max - r1min); cout << ans; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O22AI_BLACKBOX_V
`define SKY130_FD_SC_HVL__O22AI_BLACKBOX_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__o22ai (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O22AI_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O221A_2_V
`define SKY130_FD_SC_MS__O221A_2_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog wrapper for o221a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o221a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o221a_2 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o221a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o221a_2 (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o221a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O221A_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_GROUND_HVC_WPAD_PP_BLACKBOX_V
`define SKY130_FD_IO__TOP_GROUND_HVC_WPAD_PP_BLACKBOX_V
/**
* top_ground_hvc_wpad: Ground pad.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_ground_hvc_wpad (
G_PAD ,
AMUXBUS_A ,
AMUXBUS_B ,
OGC_HVC ,
DRN_HVC ,
SRC_BDY_HVC,
G_CORE ,
VDDIO ,
VDDIO_Q ,
VDDA ,
VCCD ,
VSWITCH ,
VCCHIB ,
VSSA ,
VSSD ,
VSSIO_Q ,
VSSIO
);
inout G_PAD ;
inout AMUXBUS_A ;
inout AMUXBUS_B ;
inout OGC_HVC ;
inout DRN_HVC ;
inout SRC_BDY_HVC;
inout G_CORE ;
inout VDDIO ;
inout VDDIO_Q ;
inout VDDA ;
inout VCCD ;
inout VSWITCH ;
inout VCCHIB ;
inout VSSA ;
inout VSSD ;
inout VSSIO_Q ;
inout VSSIO ;
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_GROUND_HVC_WPAD_PP_BLACKBOX_V
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : mig_7series_v1_x_ddr_if_post_fifo.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Feb 08 2011
// \___\/\___\
//
//Device : 7 Series
//Design Name : DDR3 SDRAM
//Purpose : Extends the depth of a PHASER IN_FIFO up to 4 entries
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v2_0_ddr_if_post_fifo #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter DEPTH = 4, // # of entries
parameter WIDTH = 32 // data bus width
)
(
input clk, // clock
input rst, // synchronous reset
input [3:0] empty_in,
input rd_en_in,
input [WIDTH-1:0] d_in, // write data from controller
output empty_out,
output byte_rd_en,
output [WIDTH-1:0] d_out // write data to OUT_FIFO
);
// # of bits used to represent read/write pointers
localparam PTR_BITS
= (DEPTH == 2) ? 1 :
(((DEPTH == 3) || (DEPTH == 4)) ? 2 : 'bx);
integer i;
reg [WIDTH-1:0] mem[0:DEPTH-1];
(* max_fanout = 40 *) reg [4:0] my_empty /* synthesis syn_maxfan = 3 */;
(* max_fanout = 40 *) reg [1:0] my_full /* synthesis syn_maxfan = 3 */;
reg [PTR_BITS-1:0] rd_ptr /* synthesis syn_maxfan = 10 */;
// Register duplication to reduce the fan out
(* KEEP = "TRUE" *) reg [PTR_BITS-1:0] rd_ptr_timing /* synthesis syn_maxfan = 10 */;
reg [PTR_BITS-1:0] wr_ptr /* synthesis syn_maxfan = 10 */;
wire [WIDTH-1:0] mem_out;
(* max_fanout = 40 *) wire wr_en /* synthesis syn_maxfan = 10 */;
task updt_ptrs;
input rd;
input wr;
reg [1:0] next_rd_ptr;
reg [1:0] next_wr_ptr;
begin
next_rd_ptr = (rd_ptr + 1'b1)%DEPTH;
next_wr_ptr = (wr_ptr + 1'b1)%DEPTH;
casez ({rd, wr, my_empty[1], my_full[1]})
4'b00zz: ; // No access, do nothing
4'b0100: begin
// Write when neither empty, nor full; check for full
wr_ptr <= #TCQ next_wr_ptr;
my_full[0] <= #TCQ (next_wr_ptr == rd_ptr);
my_full[1] <= #TCQ (next_wr_ptr == rd_ptr);
//mem[wr_ptr] <= #TCQ d_in;
end
4'b0110: begin
// Write when empty; no need to check for full
wr_ptr <= #TCQ next_wr_ptr;
my_empty <= #TCQ 5'b00000;
//mem[wr_ptr] <= #TCQ d_in;
end
4'b1000: begin
// Read when neither empty, nor full; check for empty
rd_ptr <= #TCQ next_rd_ptr;
rd_ptr_timing <= #TCQ next_rd_ptr;
my_empty[0] <= #TCQ (next_rd_ptr == wr_ptr);
my_empty[1] <= #TCQ (next_rd_ptr == wr_ptr);
my_empty[2] <= #TCQ (next_rd_ptr == wr_ptr);
my_empty[3] <= #TCQ (next_rd_ptr == wr_ptr);
my_empty[4] <= #TCQ (next_rd_ptr == wr_ptr);
end
4'b1001: begin
// Read when full; no need to check for empty
rd_ptr <= #TCQ next_rd_ptr;
rd_ptr_timing <= #TCQ next_rd_ptr;
my_full[0] <= #TCQ 1'b0;
my_full[1] <= #TCQ 1'b0;
end
4'b1100, 4'b1101, 4'b1110: begin
// Read and write when empty, full, or neither empty/full; no need
// to check for empty or full conditions
rd_ptr <= #TCQ next_rd_ptr;
rd_ptr_timing <= #TCQ next_rd_ptr;
wr_ptr <= #TCQ next_wr_ptr;
//mem[wr_ptr] <= #TCQ d_in;
end
4'b0101, 4'b1010: ;
// Read when empty, Write when full; Keep all pointers the same
// and don't change any of the flags (i.e. ignore the read/write).
// This might happen because a faulty DQS_FOUND calibration could
// result in excessive skew between when the various IN_FIFO's
// first become not empty. In this case, the data going to each
// post-FIFO/IN_FIFO should be read out and discarded
// synthesis translate_off
default: begin
// Covers any other cases, in particular for simulation if
// any signals are X's
$display("ERR %m @%t: Bad access: rd:%b,wr:%b,empty:%b,full:%b",
$time, rd, wr, my_empty[1], my_full[1]);
rd_ptr <= #TCQ 2'bxx;
rd_ptr_timing <= #TCQ 2'bxx;
wr_ptr <= #TCQ 2'bxx;
end
// synthesis translate_on
endcase
end
endtask
assign d_out = my_empty[4] ? d_in : mem_out;//mem[rd_ptr];
// The combined IN_FIFO + post FIFO is only "empty" when both are empty
assign empty_out = empty_in[0] & my_empty[0];
assign byte_rd_en = !empty_in[3] || !my_empty[3];
always @(posedge clk)
if (rst) begin
my_empty <= #TCQ 5'b11111;
my_full <= #TCQ 2'b00;
rd_ptr <= #TCQ 'b0;
rd_ptr_timing <= #TCQ 'b0;
wr_ptr <= #TCQ 'b0;
end else begin
// Special mode: If IN_FIFO has data, and controller is reading at
// the same time, then operate post-FIFO in "passthrough" mode (i.e.
// don't update any of the read/write pointers, and route IN_FIFO
// data to post-FIFO data)
if (my_empty[1] && !my_full[1] && rd_en_in && !empty_in[1]) ;
else
// Otherwise, we're writing to FIFO when IN_FIFO is not empty,
// and reading from the FIFO based on the rd_en_in signal (read
// enable from controller). The functino updt_ptrs should catch
// an illegal conditions.
updt_ptrs(rd_en_in, !empty_in[1]);
end
assign wr_en = (!empty_in[2] & ((!rd_en_in & !my_full[0]) |
(rd_en_in & !my_empty[2])));
always @ (posedge clk)
begin
if (wr_en)
mem[wr_ptr] <= #TCQ d_in;
end
assign mem_out = mem[rd_ptr_timing];
endmodule
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ps / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
// megafunction wizard: %DDR3 SDRAM High Performance Controller v10.0%
//GENERATION: XML
//Generated by DDR3 SDRAM High Performance Controller 10.0
//IPFS_FILES:
//RELATED_FILES:
//<< MEGAWIZARD PARSE FILE DDR310.0
//.
//<< START MEGAWIZARD INSERT MODULE
module ddr3_int_example_top (
// inputs:
clock_source,
global_reset_n,
// outputs:
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_clk,
mem_clk_n,
mem_cs_n,
mem_dm,
mem_dq,
mem_dqs,
mem_dqsn,
mem_odt,
mem_ras_n,
mem_reset_n,
mem_we_n,
pnf,
pnf_per_byte,
test_complete,
test_status
)
;
output [ 14: 0] mem_addr;
output [ 2: 0] mem_ba;
output mem_cas_n;
output [ 0: 0] mem_cke;
inout [ 0: 0] mem_clk;
inout [ 0: 0] mem_clk_n;
output [ 0: 0] mem_cs_n;
output [ 3: 0] mem_dm;
inout [ 31: 0] mem_dq;
inout [ 3: 0] mem_dqs;
inout [ 3: 0] mem_dqsn;
output [ 0: 0] mem_odt;
output mem_ras_n;
output mem_reset_n;
output mem_we_n;
output pnf;
output [ 15: 0] pnf_per_byte;
output test_complete;
output [ 7: 0] test_status;
input clock_source;
input global_reset_n;
wire [ 0: 0] cs_n;
wire dll_reference_clk_sig;
wire [ 5: 0] dqs_delay_ctrl_export_sig;
wire local_burstbegin_sig;
wire [ 14: 0] mem_addr;
wire mem_aux_full_rate_clk;
wire mem_aux_half_rate_clk;
wire [ 2: 0] mem_ba;
wire mem_cas_n;
wire [ 0: 0] mem_cke;
wire [ 0: 0] mem_clk;
wire [ 0: 0] mem_clk_n;
wire [ 0: 0] mem_cs_n;
wire [ 3: 0] mem_dm;
wire [ 31: 0] mem_dq;
wire [ 3: 0] mem_dqs;
wire [ 3: 0] mem_dqsn;
wire [ 25: 0] mem_local_addr;
wire [ 15: 0] mem_local_be;
wire [ 9: 0] mem_local_col_addr;
wire mem_local_cs_addr;
wire [127: 0] mem_local_rdata;
wire mem_local_rdata_valid;
wire mem_local_read_req;
wire mem_local_ready;
wire [ 6: 0] mem_local_size;
wire [127: 0] mem_local_wdata;
wire mem_local_write_req;
wire [ 0: 0] mem_odt;
wire mem_ras_n;
wire mem_reset_n;
wire mem_we_n;
wire phy_clk;
wire pnf;
wire [ 15: 0] pnf_per_byte;
wire reset_phy_clk_n;
wire test_complete;
wire [ 7: 0] test_status;
wire tie_high;
wire tie_low;
//
//
assign mem_cs_n = cs_n;
//<< END MEGAWIZARD INSERT MODULE
assign tie_high = 1'b1;
assign tie_low = 1'b0;
//<< START MEGAWIZARD INSERT WRAPPER_NAME
ddr3_int ddr3_int_inst
(
.aux_full_rate_clk (mem_aux_full_rate_clk),
.aux_half_rate_clk (mem_aux_half_rate_clk),
.dll_reference_clk (dll_reference_clk_sig),
.dqs_delay_ctrl_export (dqs_delay_ctrl_export_sig),
.global_reset_n (global_reset_n),
.local_address (mem_local_addr),
.local_be (mem_local_be),
.local_burstbegin (local_burstbegin_sig),
.local_init_done (),
.local_rdata (mem_local_rdata),
.local_rdata_valid (mem_local_rdata_valid),
.local_read_req (mem_local_read_req),
.local_ready (mem_local_ready),
.local_refresh_ack (),
.local_size (mem_local_size),
.local_wdata (mem_local_wdata),
.local_wdata_req (),
.local_write_req (mem_local_write_req),
.mem_addr (mem_addr[14 : 0]),
.mem_ba (mem_ba),
.mem_cas_n (mem_cas_n),
.mem_cke (mem_cke),
.mem_clk (mem_clk),
.mem_clk_n (mem_clk_n),
.mem_cs_n (cs_n),
.mem_dm (mem_dm[3 : 0]),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs[3 : 0]),
.mem_dqsn (mem_dqsn[3 : 0]),
.mem_odt (mem_odt),
.mem_ras_n (mem_ras_n),
.mem_reset_n (mem_reset_n),
.mem_we_n (mem_we_n),
.phy_clk (phy_clk),
.pll_ref_clk (clock_source),
.reset_phy_clk_n (reset_phy_clk_n),
.reset_request_n (),
.soft_reset_n (tie_high)
);
//<< END MEGAWIZARD INSERT WRAPPER_NAME
//<< START MEGAWIZARD INSERT CS_ADDR_MAP
//connect up the column address bits, dropping 2 bits from example driver output because of 4:1 data rate
assign mem_local_addr[7 : 0] = mem_local_col_addr[9 : 2];
//<< END MEGAWIZARD INSERT CS_ADDR_MAP
//<< START MEGAWIZARD INSERT EXAMPLE_DRIVER
//Self-test, synthesisable code to exercise the DDR SDRAM Controller
ddr3_int_example_driver driver
(
.clk (phy_clk),
.local_bank_addr (mem_local_addr[25 : 23]),
.local_be (mem_local_be),
.local_burstbegin (local_burstbegin_sig),
.local_col_addr (mem_local_col_addr),
.local_cs_addr (mem_local_cs_addr),
.local_rdata (mem_local_rdata),
.local_rdata_valid (mem_local_rdata_valid),
.local_read_req (mem_local_read_req),
.local_ready (mem_local_ready),
.local_row_addr (mem_local_addr[22 : 8]),
.local_size (mem_local_size),
.local_wdata (mem_local_wdata),
.local_write_req (mem_local_write_req),
.pnf_per_byte (pnf_per_byte[15 : 0]),
.pnf_persist (pnf),
.reset_n (reset_phy_clk_n),
.test_complete (test_complete),
.test_status (test_status)
);
//<< END MEGAWIZARD INSERT EXAMPLE_DRIVER
//<< START MEGAWIZARD INSERT DLL
//<< END MEGAWIZARD INSERT DLL
//<< START MEGAWIZARD INSERT BANK_INFORMATION_EXAMPLE
//<< END MEGAWIZARD INSERT BANK_INFORMATION_EXAMPLE
//<< start europa
endmodule
|
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