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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10/12/2015 12:55:13 PM
// Design Name:
// Module Name: SerialHandler_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SerialServo_tb;
parameter CHANNEL_WIDTH = 5;
parameter POSITION_WIDTH = 11;
reg clk;
reg rst;
reg ext_clk;
reg ext_flush;
reg serial;
wire [1:0] pwm;
reg [7:0] data_in [3:0];
SerialServo U0 (
.clk100MHz(clk),
.clk1MHz(clk),
.rst(rst),
.ext_clk(ext_clk),
.ext_flush(ext_flush),
.serial(serial),
.channel(5'h02),
.pwm(pwm[0])
);
SerialServo U1 (
.clk100MHz(clk),
.clk1MHz(clk),
.rst(rst),
.ext_clk(ext_clk),
.ext_flush(ext_flush),
.serial(serial),
.channel(5'h04),
.pwm(pwm[1])
);
integer i = 0;
integer state = 0;
initial
begin
ext_clk = 0;
rst = 1;
ext_flush = 0;
serial = 0;
data_in[0] = 8'b00010_111;
data_in[1] = 8'b1111_1111;
data_in[2] = 8'b00100_100;
data_in[3] = 8'b0000_0000;
#5
ext_flush = 1;
rst = 0;
#5
ext_flush = 0;
state = 1;
for(i = 0; i < 8; i=i+1) begin
#1
clk = 0;
ext_clk = 0;
#1
clk = 1;
#1
clk = 0;
serial = data_in[2][7-i];
#5
ext_clk = 1;
#1
clk = 1;
end
state = 2;
for(i = 0; i < 8; i=i+1) begin
#1
clk = 0;
ext_clk = 0;
#1
clk = 1;
#1
clk = 0;
serial = data_in[3][7-i];
#5
ext_clk = 1;
#1
clk = 1;
end
state = 3;
for(i = 0; i < 8; i=i+1) begin
#1
clk = 0;
ext_clk = 0;
#1
clk = 1;
#1
clk = 0;
serial = data_in[0][7-i];
#5
ext_clk = 1;
#1
clk = 1;
end
state = 4;
for(i = 0; i < 8; i=i+1) begin
#1
clk = 0;
ext_clk = 0;
#1
clk = 1;
#1
clk = 0;
serial = data_in[1][7-i];
#5
ext_clk = 1;
#1
clk = 1;
end
state = 5;
for(i = 0; i < 8; i=i+1) begin
#1
clk = 0;
ext_clk = 0;
#1
clk = 1;
#1
clk = 0;
serial = 1;
#5
ext_clk = 1;
#1
clk = 1;
end
#5
ext_flush = 1;
#5
ext_flush = 0;
#50
#10 $stop;
#5 $finish;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:40:46 12/20/2010
// Design Name:
// Module Name: clk_test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module clk_test(
input clk,
input sysclk,
output [31:0] snes_sysclk_freq
);
reg [31:0] snes_sysclk_freq_r;
assign snes_sysclk_freq = snes_sysclk_freq_r;
reg [31:0] sysclk_counter;
reg [31:0] sysclk_value;
initial snes_sysclk_freq_r = 32'hFFFFFFFF;
initial sysclk_counter = 0;
initial sysclk_value = 0;
reg [1:0] sysclk_sreg;
always @(posedge clk) sysclk_sreg <= {sysclk_sreg[0], sysclk};
wire sysclk_rising = (sysclk_sreg == 2'b01);
always @(posedge clk) begin
if(sysclk_counter < 86000000) begin
sysclk_counter <= sysclk_counter + 1;
if(sysclk_rising) sysclk_value <= sysclk_value + 1;
end else begin
snes_sysclk_freq_r <= sysclk_value;
sysclk_counter <= 0;
sysclk_value <= 0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[100005], b[100005], m[100005]; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i <= n; i++) scanf( %d , &b[i]); m[1] = a[1] - b[1]; for (int i = 2; i <= n; i++) m[i] = m[i - 1] + a[i] - b[i]; int min = 1000000001; for (int i = 1; i <= n; i++) if (min > m[i]) min = m[i]; vector<int> d; for (int i = 1; i <= n; i++) { if (min >= 0) d.push_back(i); min -= a[i] - b[i]; } m[n + 1] = a[1] - b[n]; m[1] = a[1] - b[n]; for (int i = n; i >= 2; i--) m[i] = m[i + 1] + a[i] - b[i - 1]; min = 1000000001; for (int i = 1; i <= n; i++) if (min > m[i]) min = m[i]; if (min >= 0) d.push_back(1); min -= a[1] - b[n]; for (int i = n; i >= 2; i--) { if (min >= 0) d.push_back(i); min -= a[i] - b[i - 1]; } sort(d.begin(), d.end()); int i = 1; for (size_t j = 1; j < d.size(); j++) if (d[j] != d[j - 1]) d[i++] = d[j]; cout << i << endl; for (int j = 0; j < i; j++) if (j != i - 1) cout << d[j] << ; else cout << d[j] << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int suma = 0; int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; suma += a[i]; } int half = 0; for (int i = 0; i < n; i++) { half += a[i]; if (half >= suma / 2 + suma % 2) { cout << i + 1; return 0; } } return 0; } |
////////////////////////////////////////////////////////////////////////////////////////////////////
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
// 02111-1307, USA.
//
// ©2013 - Roman Ovseitsev <>
////////////////////////////////////////////////////////////////////////////////////////////////////
//##################################################################################################
//
// OmniVision Camera setup module. Configured to initialize OV7670 model.
//
// Initializes camera module using register set defined in OV7670Init and once done raises
// done_o signal.
//
// Other camera models require modification of register set and timing parameters.
// After a hardware reset delay for 1ms prior to raising rst_i.
// External pull-up register (4.7k should be enough) is required on SIOD line. FPGA`s internal
// pull-ups may not be sufficient.
//
//##################################################################################################
`timescale 1ns / 1ps
module CameraSetup (clk_i, rst_i, done, sioc_o, siod_io);
`include "Math.v"
parameter IN_FREQ = 24_000_000; // clk_i frequency in Hz.
parameter CAM_ID = 8'h42; // OV7670 ID. Bit 0 is Don't Care since we specify r/w op in register lookup table.
input clk_i; // Main clock.
input rst_i; // 0 - reset.
output reg done; // 0 - setup in progress. 1 - setup has completed.
output sioc_o; // Camera's SIOC.
inout siod_io; // Camera's SIOD. Should have a pullup resistor.
localparam SCCB_FREQ = 100_000; // SCCB frequency in Hz.
localparam T_SREG = 300; // Register setup time in ms. 300ms for OV7670.
localparam integer SREG_CYCLES = (IN_FREQ/1000)*T_SREG;
localparam SCCB_PERIOD = IN_FREQ/SCCB_FREQ/2;
reg [clog2(SCCB_PERIOD):0] sccb_clk_cnt = 0;
reg sccb_clk = 0;
reg [1:0] stm = 0;
reg [5:0] reg_data_index = 0;
wire [7:0] reg_data_rcvd;
wire [16:0] reg_data_snd;
reg rw;
reg start;
wire transact_done;
wire ack_error;
reg [clog2(SREG_CYCLES):0] reg_setup_tmr = 0;
wire data_pulse = (sccb_clk_cnt == SCCB_PERIOD/2 && sccb_clk == 0);
reg do_tsreg_delay = 0;
OV7670Init caminit
(
.index_i(reg_data_index),
.data_o(reg_data_snd)
);
SCCBCtrl sccbcntl
(
.clk_i(clk_i),
.rst_i(rst_i),
.sccb_clk_i(sccb_clk),
.data_pulse_i(data_pulse),
.addr_i(CAM_ID),
.data_i(reg_data_snd[16:1]),
.rw_i(rw),
.start_i(start),
.ack_error_o(ack_error),
.done_o(transact_done),
.data_o(reg_data_rcvd),
.sioc_o(sioc_o),
.siod_io(siod_io)
);
// Generate clock for the SCCB.
always @(posedge clk_i or negedge rst_i) begin
if (rst_i == 0) begin
sccb_clk_cnt <= 0;
sccb_clk <= 0;
end else begin
if (sccb_clk_cnt < SCCB_PERIOD) begin
sccb_clk_cnt <= sccb_clk_cnt + 1;
end else begin
sccb_clk <= ~sccb_clk;
sccb_clk_cnt <= 0;
end
end
end
// Read/Write the registers.
always @(posedge clk_i or negedge rst_i) begin
if (rst_i == 0) begin
done <= 0;
reg_data_index <= 0;
stm <= 0;
start <= 0;
rw <= 0;
reg_setup_tmr <= 0;
do_tsreg_delay <= 0;
// once registers have been written we need to wait for T_SREG ms.
end else if (do_tsreg_delay == 1) begin
if (reg_setup_tmr == SREG_CYCLES)
done <= 1;
else
reg_setup_tmr <= reg_setup_tmr + 1;
// delay for T_SREG ms if needed
end else if (reg_data_snd == {16'hf0f0, 1'b1}) begin
if (reg_setup_tmr == SREG_CYCLES)
reg_data_index <= reg_data_index + 1;
else
reg_setup_tmr <= reg_setup_tmr + 1;
end else if (data_pulse) begin
if(reg_data_snd != {16'hffff, 1'b1}) begin
done <= 0;
(* parallel_case *) case(stm)
2'd0: begin
if (transact_done == 1)
stm <= 2'd0;
else
stm <= 2'd1;
start <= 1;
rw <= reg_data_snd[0];
end
2'd1: begin
if (transact_done == 1) begin
if (ack_error == 1)
stm <= 2'd0;
else
stm <= 2'd2;
rw <= reg_data_snd[0];
start <= 0;
end
end
2'd2: begin
reg_data_index <= reg_data_index + 1;
stm <= 0;
start <= 0;
rw <= reg_data_snd[0];
end
endcase
end else begin
stm <= 3;
start <= 0;
rw <= 0;
do_tsreg_delay <= 1;
reg_setup_tmr <= 0;
end
end
end
endmodule
|
// Copyright (c) 2014 CERN
// Maciej Suminski <>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test for dynamic arrays used as the function parameters and return type.
module sv_darray_function();
typedef logic[7:0] byte_array [];
typedef logic[3*8-1:0] byte_vector;
function byte_array inc_array(byte_array inp);
byte_array tmp;
tmp = new[$size(inp)];
for(int i = 0; i < $size(inp); ++i)
begin
tmp[i] = inp[i] + 1;
end
return tmp;
endfunction
initial begin
byte_array a, b;
byte_vector c;
a = new[3];
a[0] = 10;
a[1] = 11;
a[2] = 12;
b = inc_array(a);
if($size(a) != 3 || a[0] !== 10 || a[1] !== 11 || a[2] !== 12) begin
$display("FAILED 1");
$finish();
end
if($size(b) != 3 || b[0] !== 11 || b[1] !== 12 || b[2] !== 13) begin
$display("FAILED 2");
$finish();
end
// Cast dynamic array returned by function to logic vector
c = byte_vector'(inc_array(b));
if(c !== 24'h0c0d0e) begin
$display("FAILED 3");
$finish();
end
$display("PASSED");
end
endmodule
|
/* This file is part of JT51.
JT51 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-10-2016
*/
`timescale 1ns / 1ps
module jt51_exp2lin(
output reg signed [15:0] lin,
input signed [9:0] man,
input [2:0] exp
);
always @(*) begin
case( exp )
3'd7: lin = { man, 6'b0 };
3'd6: lin = { {1{man[9]}}, man, 5'b0 };
3'd5: lin = { {2{man[9]}}, man, 4'b0 };
3'd4: lin = { {3{man[9]}}, man, 3'b0 };
3'd3: lin = { {4{man[9]}}, man, 2'b0 };
3'd2: lin = { {5{man[9]}}, man, 1'b0 };
3'd1: lin = { {6{man[9]}}, man };
3'd0: lin = 16'd0;
endcase
end
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_nios2_qsys_0_jtag_debug_module_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
jdo[36];
assign take_no_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
~jdo[36];
assign take_action_tracemem_b = enable_action_strobe && (ir == 2'b01) &&
jdo[37];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /stack:640000000 ) using namespace std; const double EPS = 1e-9; const int INF = 0x7f7f7f7f; const double PI = acos(-1.0); template <class T> inline T gcd(T a, T b) { return (b) == 0 ? (a) : gcd((b), ((a) % (b))); } template <class T> inline T lcm(T a, T b) { return ((a) / gcd((a), (b)) * (b)); } template <typename T> string NumberToString(T Number) { ostringstream second; second << Number; return second.str(); } struct debugger { template <typename T> debugger& operator,(const T& v) { cerr << v << ; return *this; } } dbg; int t, n, m; string s; int main() { while (~scanf( %d%d , &n, &m)) { long long k; scanf( %lld , &k); if (k < n) { printf( %lld 1 n , k + 1); continue; } k -= (n - 1); int row = k / (m - 1); if (k % (m - 1) == 0) row--; int col = k % (m - 1); if (k % (m - 1) == 0) col = m - 1; int odd = row % 2; row = n - row; if (odd) col = m - col + 1; else col = col + 1; printf( %d %d n , row, col); } return 0; } |
//MODULE REFERENCE
`define tenv_clock tenv_clock
`define tenv_descstd_device tenv_descstd_device
module tenv_usbdev #(parameter DATA_MAXSIZE=64);
//IFACE
reg rst0_async=1;
reg rst0_sync=1;
wire[1:0] trsac_type;
localparam TYPE_SETUP=0,
TYPE_OUT=1,
TYPE_IN=2;
wire[3:0] trsac_ep;
wire[1:0] trsac_req;
localparam REQ_OK=0,
REQ_ACTIVE=1,
REQ_FAIL=2;
reg[1:0] trsac_reply=0;
localparam ACK=0,
NAK=1,
STALL=2;
reg rfifo_rd=0;
wire rfifo_empty;
wire[7:0] rfifo_rdata;
reg tfifo_wr=0;
wire tfifo_full;
reg[7:0] tfifo_wdata=0;
reg[15:1] ep_enable=15'h7FFF;
reg[15:1] ep_isoch=15'b100_0000_0000_0000;
reg[15:1] ep_intnoretry=15'b000_0010_0000_0000;
reg speed=0;
reg device_wakeup=0;
reg device_addr_wr=0;
reg[6:0] device_addr=0;
reg device_config_wr=0;
reg[7:0] device_config=0;
wire[2:0] device_state;
parameter POWERED=3'd0,
DEFAULT=3'd1,
ADDRESSED=3'd2,
CONFIGURED=3'd3,
SPND_PWR=3'd4,
SPND_DFT=3'd5,
SPND_ADDR=3'd6,
SPND_CONF=3'd7;
wire sof_tick;
wire[10:0] sof_value;
reg[7:0] buffer[DATA_MAXSIZE-1:0];
integer reply_delay=0;
//LOCAL
localparam block_name="tenv_usbdev";
reg[7:0] bm_request_type=0;
reg[7:0] b_request=0;
reg[15:0] w_value=0;
reg[15:0] w_index=0;
reg[15:0] w_length=0;
localparam GET_STATUS=0,
CLEAR_FEATURE=1,
SET_FEATURE=3,
SET_ADDRESS=5,
GET_DESCRIPTOR=6,
SET_DESCRIPTOR=7,
GET_CONFIGURATION=8,
SET_CONFIGURATION=9,
GET_INTERFACE=10,
SET_INTERFACE=11,
SYNCH_FRAME=12;
//TASKS
`include "tenv_usbdev/tenv_usbdev.mntr_trsac_off.v"
`include "tenv_usbdev/tenv_usbdev.mntr_devstate.v"
`include "tenv_usbdev/tenv_usbdev.reset.v"
`include "tenv_usbdev/tenv_usbdev.gen_data.v"
`include "tenv_usbdev/tenv_usbdev.trsac_in.v"
`include "tenv_usbdev/tenv_usbdev.trsac_out.v"
`include "tenv_usbdev/tenv_usbdev.trsac_setup.v"
`include "tenv_usbdev/tenv_usbdev.trfer_in.v"
`include "tenv_usbdev/tenv_usbdev.trfer_out.v"
`include "tenv_usbdev/tenv_usbdev.reqstd_getdesc.v"
`include "tenv_usbdev/tenv_usbdev.reqstd_setconf.v"
`include "tenv_usbdev/tenv_usbdev.reqstd_setaddr.v"
`include "tenv_usbdev/tenv_usbdev.reqstd_clrfeat.v"
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIEBus_axi_basic_rx.v
// Version : 1.11
// //
// Description: //
// TRN to AXI RX module. Instantiates pipeline and null generator RX //
// submodules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_rx //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module PCIEBus_axi_basic_rx #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI RX
//-----------
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
output m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables
output m_axis_rx_tlast, // RX data is last
output [21:0] m_axis_rx_tuser, // RX user signals
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN RX
//-----------
input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block
input trn_rsof, // RX start of packet
input trn_reof, // RX end of packet
input trn_rsrc_rdy, // RX source ready
output trn_rdst_rdy, // RX destination ready
input trn_rsrc_dsc, // RX source discontinue
input [REM_WIDTH-1:0] trn_rrem, // RX remainder
input trn_rerrfwd, // RX error forward
input [6:0] trn_rbar_hit, // RX BAR hit
input trn_recrc_err, // RX ECRC error
// System
//-----------
output [2:0] np_counter, // Non-posted counter
input user_clk, // user clock from block
input user_rst // user reset from block
);
// Wires
wire null_rx_tvalid;
wire null_rx_tlast;
wire [KEEP_WIDTH-1:0] null_rx_tkeep;
wire null_rdst_rdy;
wire [4:0] null_is_eof;
//---------------------------------------------//
// RX Data Pipeline //
//---------------------------------------------//
PCIEBus_axi_basic_rx_pipeline #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) rx_pipeline_inst (
// Outgoing AXI TX
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tkeep( m_axis_rx_tkeep ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Incoming TRN RX
//-----------
.trn_rd( trn_rd ),
.trn_rsof( trn_rsof ),
.trn_reof( trn_reof ),
.trn_rsrc_rdy( trn_rsrc_rdy ),
.trn_rdst_rdy( trn_rdst_rdy ),
.trn_rsrc_dsc( trn_rsrc_dsc ),
.trn_rrem( trn_rrem ),
.trn_rerrfwd( trn_rerrfwd ),
.trn_rbar_hit( trn_rbar_hit ),
.trn_recrc_err( trn_recrc_err ),
// Null Inputs
//-----------
.null_rx_tvalid( null_rx_tvalid ),
.null_rx_tlast( null_rx_tlast ),
.null_rx_tkeep( null_rx_tkeep ),
.null_rdst_rdy( null_rdst_rdy ),
.null_is_eof( null_is_eof ),
// System
//-----------
.np_counter( np_counter ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// RX Null Packet Generator //
//---------------------------------------------//
PCIEBus_axi_basic_rx_null_gen #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.TCQ( TCQ ),
.KEEP_WIDTH( KEEP_WIDTH )
) rx_null_gen_inst (
// Inputs
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Null Outputs
//-----------
.null_rx_tvalid( null_rx_tvalid ),
.null_rx_tlast( null_rx_tlast ),
.null_rx_tkeep( null_rx_tkeep ),
.null_rdst_rdy( null_rdst_rdy ),
.null_is_eof( null_is_eof ),
// System
//-----------
.user_clk( user_clk ),
.user_rst( user_rst )
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV3SD1_PP_SYMBOL_V
`define SKY130_FD_SC_MS__CLKDLYINV3SD1_PP_SYMBOL_V
/**
* clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
* stage gate.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__clkdlyinv3sd1 (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV3SD1_PP_SYMBOL_V
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2011 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Bi-Directional Buffer
// /___/ /\ Filename : IOBUF_INTERMDISABLE.v
// \ \ / \ Timestamp : Wed Apr 20 17:49:56 PDT 2011
// \___\/\___\
//
// Revision:
// 04/20/11 - Initial version.
// 06/15/11 - CR 613347 -- made ouput logic_1 when IBUFDISABLE is active
// 08/31/11 - CR 623170 -- Tristate powergating support
// 09/20/11 - CR 624774, 625725 -- Removed attributes IBUF_DELAY_VALUE, IFD_DELAY_VALUE and CAPACITANCE
// 09/20/11 - CR 625564 -- Fixed Tristate powergating polarity
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IOBUF_INTERMDISABLE (O, IO, I, IBUFDISABLE, INTERMDISABLE, T);
parameter integer DRIVE = 12;
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter SIM_DEVICE = "7SERIES";
parameter SLEW = "SLOW";
parameter USE_IBUFDISABLE = "TRUE";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
output O;
inout IO;
input I;
input IBUFDISABLE;
input INTERMDISABLE;
input T;
// define constants
localparam MODULE_NAME = "IOBUF_INTERMDISABLE";
wire ts,out_val;
wire T_OR_IBUFDISABLE;
tri0 GTS = glbl.GTS;
or O1 (ts, GTS, T);
bufif0 T1 (IO, I, ts);
// buf B1 (O, IO);
initial begin
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IOBUF_INTERMDISABLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
#1 $finish;
end
endcase
if ((SIM_DEVICE != "7SERIES") &&
(SIM_DEVICE != "ULTRASCALE") &&
(SIM_DEVICE != "VERSAL_AI_CORE") &&
(SIM_DEVICE != "VERSAL_AI_CORE_ES1") &&
(SIM_DEVICE != "VERSAL_AI_CORE_ES2") &&
(SIM_DEVICE != "VERSAL_AI_EDGE") &&
(SIM_DEVICE != "VERSAL_AI_EDGE_ES1") &&
(SIM_DEVICE != "VERSAL_AI_EDGE_ES2") &&
(SIM_DEVICE != "VERSAL_AI_RF") &&
(SIM_DEVICE != "VERSAL_AI_RF_ES1") &&
(SIM_DEVICE != "VERSAL_AI_RF_ES2") &&
(SIM_DEVICE != "VERSAL_HBM") &&
(SIM_DEVICE != "VERSAL_HBM_ES1") &&
(SIM_DEVICE != "VERSAL_HBM_ES2") &&
(SIM_DEVICE != "VERSAL_PREMIUM") &&
(SIM_DEVICE != "VERSAL_PREMIUM_ES1") &&
(SIM_DEVICE != "VERSAL_PREMIUM_ES2") &&
(SIM_DEVICE != "VERSAL_PRIME") &&
(SIM_DEVICE != "VERSAL_PRIME_ES1") &&
(SIM_DEVICE != "VERSAL_PRIME_ES2")) begin
$display("Error: [Unisim %s-104] SIM_DEVICE attribute is set to %s. Legal values for this attribute are 7SERIES, ULTRASCALE, VERSAL_AI_CORE, VERSAL_AI_CORE_ES1, VERSAL_AI_CORE_ES2, VERSAL_AI_EDGE, VERSAL_AI_EDGE_ES1, VERSAL_AI_EDGE_ES2, VERSAL_AI_RF, VERSAL_AI_RF_ES1, VERSAL_AI_RF_ES2, VERSAL_HBM, VERSAL_HBM_ES1, VERSAL_HBM_ES2, VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2, VERSAL_PRIME, VERSAL_PRIME_ES1 or VERSAL_PRIME_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE);
#1 $finish;
end
end // initial begin
generate
case (SIM_DEVICE)
"7SERIES" : begin
assign out_val = 1'b1;
end
default : begin
assign out_val = 1'b0;
end
endcase
endgenerate
generate
case (USE_IBUFDISABLE)
"TRUE" : begin
assign T_OR_IBUFDISABLE = ~T || IBUFDISABLE;
assign O = (T_OR_IBUFDISABLE == 1'b1) ? out_val : (T_OR_IBUFDISABLE == 1'b0) ? IO : 1'bx;
end
"FALSE" : begin
assign O = IO;
end
endcase
endgenerate
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(I => IO) = (0:0:0, 0:0:0);
(IO => O) = (0:0:0, 0:0:0);
(IBUFDISABLE => O) = (0:0:0, 0:0:0);
(IBUFDISABLE => IO) = (0:0:0, 0:0:0);
(INTERMDISABLE => O) = (0:0:0, 0:0:0);
(INTERMDISABLE => IO) = (0:0:0, 0:0:0);
(T => O) = (0:0:0, 0:0:0);
(T => IO) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule
`endcelldefine
|
/*
* File Name : tb.v
* Version : 0.1
* Date : Feb 27, 2008
* Description : jhash input modules testbench
* Dependencies :
*
* Company : Beijing soul
* Author : Hu Gang
*
*****************************************************************************/
`timescale 1ns/1ps
module tb(/*AUTOARG*/
// Outputs
stream_valid, stream_left, stream_done, stream_data2,
stream_data1, stream_data0, fi_cnt,
// Inputs
m_endn
);
parameter LZF_WIDTH = 20;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input m_endn; // To data of data.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [LZF_WIDTH-1:0]fi_cnt; // From data of data.v
output [31:0] stream_data0; // From jhash_in of jhash_in.v
output [31:0] stream_data1; // From jhash_in of jhash_in.v
output [31:0] stream_data2; // From jhash_in of jhash_in.v
output stream_done; // From jhash_in of jhash_in.v
output [1:0] stream_left; // From jhash_in of jhash_in.v
output stream_valid; // From jhash_in of jhash_in.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire ce; // From data of data.v
wire clk; // From data of data.v
wire [63:0] fi; // From data of data.v
wire fo_full; // From data of data.v
wire m_last; // From data of data.v
wire m_src_getn; // From jhash_in of jhash_in.v
wire rst; // From data of data.v
wire src_empty; // From data of data.v
// End of automatics
data data(/*AUTOINST*/
// Outputs
.clk (clk),
.rst (rst),
.src_empty (src_empty),
.ce (ce),
.fo_full (fo_full),
.m_last (m_last),
.fi (fi[63:0]),
.fi_cnt (fi_cnt[LZF_WIDTH-1:0]),
// Inputs
.m_src_getn (m_src_getn),
.m_endn (m_endn));
defparam data.LZF_FILE = "/tmp/decode.chk";
defparam data.LZF_DEBUG = 0;
defparam data.LZF_DELAY = 4;
defparam data.LZF_FIFO_AW = 5;
reg stream_ack;
jhash_in jhash_in(/*AUTOINST*/
// Outputs
.m_src_getn (m_src_getn),
.stream_data0 (stream_data0[31:0]),
.stream_data1 (stream_data1[31:0]),
.stream_data2 (stream_data2[31:0]),
.stream_valid (stream_valid),
.stream_done (stream_done),
.stream_left (stream_left[1:0]),
// Inputs
.ce (ce),
.clk (clk),
.fi (fi[63:0]),
.fo_full (fo_full),
.m_last (m_last),
.rst (rst),
.src_empty (src_empty),
.stream_ack (stream_ack));
initial
begin
$dumpfile("tb_in.vcd");
$dumpvars(0, tb);
stream_ack = 1'b1;
@(posedge stream_done);
$finish;
end
endmodule // tb
// Local Variables:
// verilog-library-directories:("." "../../rtl/verilog/" "../../../encode/bench/verilog/")
// verilog-library-files:("")
// verilog-library-extensions:(".v" ".h")
// End:
|
`define WIDTH_P 2
/**************************** TEST RATIONALE *******************************
1. STATE SPACE
This module generates gray codes of every possible binary number of WIDTH_P
and feeds these vales as test inputs to the DUT. An up-counter is used to
generate the binary numbers whose gray codes are test inputs to DUT. The
output of the DUT is compared with count to check correctness. Thus the DUT
is tested exhaustively for any given WIDTH_P.
2. PARAMETERIZATION
The DUT uses a module already defined in bsg_misc to calculate the
value of the input gray code. Hence tests with WIDTH_P = 1,2,..8 would give
sufficient confidence. Since the number of test cases grows exponentially
with WIDTH_P, simulations with WIDTH_P > 16 would take very long time to
complete apart from generating a large "output.log".
***************************************************************************/
module test_bsg
#(
parameter cycle_time_p = 20,
parameter width_p = `WIDTH_P,
parameter reset_cycles_lo_p=1,
parameter reset_cycles_hi_p=5
);
wire clk;
wire reset;
bsg_nonsynth_clock_gen #( .cycle_time_p(cycle_time_p)
) clock_gen
( .o(clk)
);
bsg_nonsynth_reset_gen #( .num_clocks_p (1)
, .reset_cycles_lo_p(reset_cycles_lo_p)
, .reset_cycles_hi_p(reset_cycles_lo_p)
) reset_gen
( .clk_i (clk)
, .async_reset_o(reset)
);
initial
begin
$display("\n\n\n");
$display("===========================================================");
$display("testing with ...");
$display("WIDTH_P: %d\n", width_p);
end
logic [width_p-1:0] count, count_r;
bsg_cycle_counter #( .width_p(width_p)
) bcc
( .clk_i (clk)
, .reset_i(reset)
, .ctr_r_o(count)
);
logic [width_p-1:0] test_input;
wire [width_p-1:0] test_output;
assign test_input = (count>>1) ^ count; // test_input is gray code of count
always_ff @(posedge clk)
begin
count_r <= count;
/*$display("\ntest_input: %b, count: %b, test_output: %b"
, test_input, count, test_output);*/
if(!reset)
assert(test_output == count)
else $error("mismatch on input %x", test_input);
if(!(|count) & (&count_r))
begin
$display("===============================================================\n");
$finish;
end
end
bsg_gray_to_binary #( .width_p(width_p)
) DUT
( .gray_i (test_input)
, .binary_o(test_output)
);
/*bsg_nonsynth_ascii_writer #( .width_p (width_p)
, .values_p (3)
, .filename_p ("output.log")
, .fopen_param_p("a+")
, .format_p ("%x")
) ascii_writer
( .clk (clk)
, .reset_i(reset)
, .valid_i(1'b1)
, .data_i ({test_output,
count,
test_input}
)
);*/
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<long long> bitr; void update(long long ind, long long val, long long n) { long long i = ind + 1; while (i <= n) { bitr[i] += val; i += i & (-i); } } long long sum(long long ind) { long long i = ind + 1; long long ans = 0; while (i > 0) { ans += bitr[i]; i -= i & (-i); } return ans; } int main() { long long n, q, i; cin >> n >> q; long long arr[n]; bitr.push_back(0); for (i = 0; i < n; i++) { cin >> arr[i]; bitr.push_back(0); } sort(arr, arr + n); for (i = 0; i < q; i++) { long long l, r; cin >> l >> r; l--; r--; update(l, 1, n); update(r + 1, -1, n); } long long fact[n]; for (i = 0; i < n; i++) fact[i] = sum(i); sort(fact, fact + n); long long res = 0; for (i = 0; i < n; i++) { res += (fact[i] * arr[i]); } cout << res << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR4BB_PP_SYMBOL_V
`define SKY130_FD_SC_MS__OR4BB_PP_SYMBOL_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__or4bb (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N ,
input D_N ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR4BB_PP_SYMBOL_V
|
// File generic.vhd translated with vhd2vl v2.4 VHDL to Verilog RTL translator
// vhd2vl settings:
// * Verilog Module Declaration Style: 1995
// vhd2vl is Free (libre) Software:
// Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
// http://www.ocean-logic.com
// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
// Modifications (C) 2010 Shankar Giri
// Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL
// http://doolittle.icarus.com/~larry/vhd2vl/
//
// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting
// Verilog for correctness, ideally with a formal verification tool.
//
// You are welcome to redistribute vhd2vl under certain conditions.
// See the license (GPLv2) file included with the source for details.
// The result of translation follows. Its copyright status should be
// considered unchanged from the original VHDL.
// no timescale needed
module test(
reset,
sysclk,
a,
b,
enf,
load,
qtd,
base
);
parameter [7:0] dog_width=8'b 10101100;
parameter [31:0] bus_width=32;
input reset, sysclk;
input [bus_width:0] a, b, enf, load, qtd, base;
wire reset;
wire sysclk;
wire [bus_width:0] a;
wire [bus_width:0] b;
wire [bus_width:0] enf;
wire [bus_width:0] load;
wire [bus_width:0] qtd;
wire [bus_width:0] base;
wire [1 + 1:0] foo;
reg [9:0] code; wire [9:0] code1;
wire [324:401] egg;
wire [bus_width * 3 - 1:bus_width * 4] baz;
wire [31:0] complex;
// Example of with statement
always @(*) begin
case(foo[2:0])
3'b 000,3'b 110 : code[9:2] <= {3'b 110,egg[325:329]};
3'b 101 : code[9:2] <= 8'b 11100010;
3'b 010 : code[9:2] <= {8{1'b1}};
3'b 011 : code[9:2] <= {8{1'b0}};
default : code[9:2] <= a + b + 1'b 1;
endcase
end
assign code1[1:0] = a[6:5] ^ ({a[4],b[6]});
assign foo = {(((1 + 1))-((0))+1){1'b0}};
assign egg = {78{1'b0}};
assign baz = {(((bus_width * 4))-((bus_width * 3 - 1))+1){1'b1}};
assign complex = {enf,(3'b 110 * load),qtd[3:0],base,5'b 11001};
endmodule
|
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V2.1
// Ultra-Embedded.com
// Copyright 2011 - 2014
//
// Email:
//
// License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2014 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
`include "altor32_defs.v"
//-----------------------------------------------------------------
// Module: Data Forwarding Unit
//-----------------------------------------------------------------
module altor32_dfu
(
// Input registers
input [4:0] ra_i /*verilator public*/,
input [4:0] rb_i /*verilator public*/,
// Input register contents
input [31:0] ra_regval_i /*verilator public*/,
input [31:0] rb_regval_i /*verilator public*/,
// Dest register (EXEC stage)
input [4:0] rd_ex_i/*verilator public*/,
// Dest register (WB stage)
input [4:0] rd_wb_i/*verilator public*/,
// Load pending / target
input load_pending_i /*verilator public*/,
input [4:0] rd_load_i /*verilator public*/,
// Multiplier status
input mult_ex_i /*verilator public*/,
// Result (EXEC)
input [31:0] result_ex_i /*verilator public*/,
// Result (WB)
input [31:0] result_wb_i /*verilator public*/,
// Resolved register values
output reg [31:0] result_ra_o /*verilator public*/,
output reg [31:0] result_rb_o /*verilator public*/,
// Result required resolving
output reg resolved_o /*verilator public*/,
// Stall due to failed resolve
output reg stall_o /*verilator public*/
);
//-------------------------------------------------------------------
// Data forwarding unit
//-------------------------------------------------------------------
always @ *
begin
// Default to no forwarding
result_ra_o = ra_regval_i;
result_rb_o = rb_regval_i;
stall_o = 1'b0;
resolved_o = 1'b0;
//---------------------------------------------------------------
// RA - Hazard detection & forwarding
//---------------------------------------------------------------
// Register[ra] hazard detection & forwarding logic
// (higher priority = latest results!)
if (ra_i != 5'b00000)
begin
//---------------------------------------------------------------
// RA from load (result not ready)
//---------------------------------------------------------------
if (ra_i == rd_load_i & load_pending_i)
begin
stall_o = 1'b1;
`ifdef CONF_CORE_DEBUG
$display(" rA[%d] not ready as load still pending", ra_i);
`endif
end
//---------------------------------------------------------------
// RA from PC-4 (exec)
//---------------------------------------------------------------
else if (ra_i == rd_ex_i)
begin
// Multiplier has one cycle latency, stall if needed now
if (mult_ex_i)
stall_o = 1'b1;
else
begin
result_ra_o = result_ex_i;
resolved_o = 1'b1;
`ifdef CONF_CORE_DEBUG
$display(" rA[%d] forwarded 0x%08x (PC-4)", ra_i, result_ra_o);
`endif
end
end
//---------------------------------------------------------------
// RA from PC-8 (writeback)
//---------------------------------------------------------------
else if (ra_i == rd_wb_i)
begin
result_ra_o = result_wb_i;
resolved_o = 1'b1;
`ifdef CONF_CORE_DEBUG
$display(" rA[%d] forwarded 0x%08x (PC-8)", ra_i, result_ra_o);
`endif
end
end
//---------------------------------------------------------------
// RB - Hazard detection & forwarding
//---------------------------------------------------------------
// Register[rb] hazard detection & forwarding logic
// (higher priority = latest results!)
if (rb_i != 5'b00000)
begin
//---------------------------------------------------------------
// RB from load (result not ready)
//---------------------------------------------------------------
if (rb_i == rd_load_i & load_pending_i)
begin
stall_o = 1'b1;
`ifdef CONF_CORE_DEBUG
$display(" rB[%d] not ready as load still pending", rb_i);
`endif
end
//---------------------------------------------------------------
// RB from PC-4 (exec)
//---------------------------------------------------------------
else if (rb_i == rd_ex_i)
begin
// Multiplier has one cycle latency, stall if needed now
if (mult_ex_i)
stall_o = 1'b1;
else
begin
result_rb_o = result_ex_i;
resolved_o = 1'b1;
`ifdef CONF_CORE_DEBUG
$display(" rB[%d] forwarded 0x%08x (PC-4)", rb_i, result_rb_o);
`endif
end
end
//---------------------------------------------------------------
// RB from PC-8 (writeback)
//---------------------------------------------------------------
else if (rb_i == rd_wb_i)
begin
result_rb_o = result_wb_i;
resolved_o = 1'b1;
`ifdef CONF_CORE_DEBUG
$display(" rB[%d] forwarded 0x%08x (PC-8)", rb_i, result_rb_o);
`endif
end
end
end
endmodule
|
/**
* Hydra - An open source strand lighting controller
* (c) 2013-2014 Jon Evans <>
* Released under the MIT License -- see LICENSE.txt for details.
*
* strand_driver.v - WS2801/WS2811 driver state machine
*
* Input clock is assumed to be 100 MHz, giving the following timings:
* WS2811 T0H = 50, T0L = 200, T1H = 120, T1L = 130
*
*
*
*/
module strand_driver (
clk,
rst_n,
ws2811_mode,
strand_length,
current_idx,
mem_data,
start_frame,
busy,
done,
strand_clk,
strand_data
);
parameter MEM_DATA_WIDTH = 24;
parameter STRAND_PARAM_WIDTH = 16;
input clk;
input rst_n;
// Parameter inputs (from registers)
input ws2811_mode;
input [STRAND_PARAM_WIDTH-1:0] strand_length;
// Current pixel index (used to control the pixel RAM)
output reg [STRAND_PARAM_WIDTH-1:0] current_idx;
// Data in from the pixel RAM
input [MEM_DATA_WIDTH-1:0] mem_data;
// Toggle high to begin the state machine
input start_frame;
// Control outputs
output reg busy;
output reg done;
// Outputs to IOB
output reg strand_clk;
output reg strand_data;
// Locals
reg [7:0] counter;
reg [7:0] counter_preset;
reg [7:0] bit_position;
reg [2:0] current_state;
reg [2:0] next_state;
reg [MEM_DATA_WIDTH-1:0] current_data;
reg strand_clk_i;
reg strand_data_i;
reg busy_i;
reg [7:0] bit_position_i;
reg [STRAND_PARAM_WIDTH-1:0] current_idx_i;
reg counter_set_i;
reg counter_running;
wire words_to_decode;
wire current_bit;
// FSM
localparam STATE_IDLE = 3'b000,
STATE_START = 3'b001,
STATE_UNPACK = 3'b010,
STATE_DECODE_1 = 3'b011,
STATE_DECODE_2 = 3'b100;
// Output timing
localparam T1H = 8'd120, // WS2811 1-bit high period
T1L = 8'd130,
T0H = 8'd50,
T0L = 8'd200,
TRESET = 8'd255,
TCLKDIV2 = 8'd10;
// State machine
always @(posedge clk) begin
if (rst_n == 1'b0) begin
current_idx <= { STRAND_PARAM_WIDTH {1'b0} };
current_data <= { MEM_DATA_WIDTH {1'b0} };
busy <= 1'b0;
done <= 1'b0;
strand_clk <= 1'b0;
strand_data <= 1'b0;
counter <= {8 {1'b0} };
bit_position <= {8 {1'b0} };
current_state <= STATE_IDLE;
counter_running <= 1'b0;
end
else begin
busy <= busy_i;
current_idx <= current_idx_i;
strand_clk <= strand_clk_i;
strand_data <= strand_data_i;
// Latch the new data word
if (current_state == STATE_UNPACK) begin
current_data <= mem_data;
bit_position <= {8 {1'b0} };
end else begin
bit_position <= bit_position_i;
end
// Manage the timing counter
if (counter_set_i == 1'b1) begin
counter <= counter_preset;
counter_running <= 1'b1;
end else begin
if (counter > 0) begin
counter <= counter - 1;
end else begin
counter_running <= 1'b0;
end
end
current_state <= next_state;
end
end
assign words_to_decode = (current_idx < strand_length);
assign current_bit = mem_data[bit_position];
// Next state process
always @(*) begin
next_state = current_state;
strand_data_i = strand_data;
strand_clk_i = strand_clk;
counter_preset = counter;
busy_i = busy;
bit_position_i = bit_position;
current_idx_i = current_idx;
case (current_state)
STATE_IDLE: begin
// Start transmission
if (start_frame == 1'b1) begin
next_state = STATE_START;
busy_i = 1'b1;
current_idx_i = { STRAND_PARAM_WIDTH {1'b0} };
bit_position_i = {8 {1'b0} };
end
end
STATE_START: begin
// Perform any one-time initialization
// TODO: does this need to exist?
current_idx_i = { STRAND_PARAM_WIDTH {1'b0} };
bit_position_i = {8 {1'b0} };
next_state = STATE_UNPACK;
end
STATE_UNPACK: begin
// Grab the next pixel word
if (words_to_decode == 1'b1) begin
next_state = STATE_DECODE_1;
end else begin
next_state = STATE_IDLE;
busy_i = 0;
end
// Reset the bit position counter at the beginning of each word
bit_position = {8 {1'b0} };
end
STATE_DECODE_1: begin
// First output phase.
if (ws2811_mode == 1'b1) begin
// WS2811? D <= 1, T <= (bit==1) ? T1H : T0H
if (current_bit == 1'b1) begin
counter_preset = T1H;
end else begin
counter_preset = T0H;
end
strand_data_i = 1'b1;
end else begin
// WS2812? D <= bit, C <= 0, T <= TCLKDIV2
strand_data_i = mem_data[bit_position];
strand_clk_i = 1'b0;
counter_preset = TCLKDIV2;
end
counter_set_i = !counter_running;
if (counter == 0 && counter_running) begin
next_state = STATE_DECODE_2;
end
end
STATE_DECODE_2: begin
// Second output phase.
// WS2811? D <= 0, T <= (bit==1) ? T1L: T0L
// WS2812? C <= 0, T <= TCLKDIV2
if (ws2811_mode == 1'b1) begin
if (mem_data[bit_position] == 1'b1) begin
counter_preset = T1L;
end else begin
counter_preset = T0L;
end
strand_data_i = 1'b0;
end else begin
// Toggle the clock high; data remains the same
strand_data_i = strand_data;
strand_clk_i = 1'b1;
counter_preset = TCLKDIV2;
end
// Advance the bit index
if (counter == 0 && counter_running) begin
if (bit_position < 8'd23) begin
next_state = STATE_DECODE_1;
bit_position_i = bit_position + 1;
end else begin
next_state = STATE_UNPACK;
current_idx_i = current_idx + 1;
end
end
counter_set_i = !counter_running;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); ll n, a, b; cin >> n >> a >> b; ll tot = 6 * n; ll ans = 1e18; if (a * b >= tot) { cout << a * b << n << a << << b << n ; } else { bool swp = false; if (a > b) { swp = true; swap(a, b); } ll na = a, nb = b; for (ll i = 1; i * i <= tot; i++) { ll j = tot / i; if (i * j < tot) j++; if (i >= a && j >= b) { if (i * j >= tot && i * j <= ans) { ans = i * j; na = i; nb = j; } } } if (swp) swap(na, nb); cout << na * nb << n << na << << nb << n ; } return 0; } |
#include <bits/stdc++.h> const int N = 1e6 + 10; const int mod = 1e9 + 7; const int inf = 0x3f3f3f3f; const double eps = 1e-8; const double pi = acos(-1); using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { int n, k; cin >> n >> k; int ans; if (n < k) ans = k - n; else { if (n % 2 == k % 2) ans = 0; else ans = 1; } cout << ans << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SEDFXBP_TB_V
`define SKY130_FD_SC_LS__SEDFXBP_TB_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__sedfxbp.v"
module top();
// Inputs are registered
reg D;
reg DE;
reg SCD;
reg SCE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
DE = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 DE = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 DE = 1'b1;
#220 SCD = 1'b1;
#240 SCE = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 DE = 1'b0;
#380 SCD = 1'b0;
#400 SCE = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SCE = 1'b1;
#600 SCD = 1'b1;
#620 DE = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SCE = 1'bx;
#760 SCD = 1'bx;
#780 DE = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ls__sedfxbp dut (.D(D), .DE(DE), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SEDFXBP_TB_V
|
module sine_lut(addr, s);
input [7:0] addr;
output [7:0] s;
reg [7:0] s;
always @(addr) begin
case (addr)
0: s = 8'h80;
1: s = 8'h83;
2: s = 8'h86;
3: s = 8'h89;
4: s = 8'h8C;
5: s = 8'h8F;
6: s = 8'h92;
7: s = 8'h95;
8: s = 8'h98;
9: s = 8'h9B;
10: s = 8'h9E;
11: s = 8'hA2;
12: s = 8'hA5;
13: s = 8'hA7;
14: s = 8'hAA;
15: s = 8'hAD;
16: s = 8'hB0;
17: s = 8'hB3;
18: s = 8'hB6;
19: s = 8'hB9;
20: s = 8'hBC;
21: s = 8'hBE;
22: s = 8'hC1;
23: s = 8'hC4;
24: s = 8'hC6;
25: s = 8'hC9;
26: s = 8'hCB;
27: s = 8'hCE;
28: s = 8'hD0;
29: s = 8'hD3;
30: s = 8'hD5;
31: s = 8'hD7;
32: s = 8'hDA;
33: s = 8'hDC;
34: s = 8'hDE;
35: s = 8'hE0;
36: s = 8'hE2;
37: s = 8'hE4;
38: s = 8'hE6;
39: s = 8'hE8;
40: s = 8'hEA;
41: s = 8'hEB;
42: s = 8'hED;
43: s = 8'hEE;
44: s = 8'hF0;
45: s = 8'hF1;
46: s = 8'hF3;
47: s = 8'hF4;
48: s = 8'hF5;
49: s = 8'hF6;
50: s = 8'hF8;
51: s = 8'hF9;
52: s = 8'hFA;
53: s = 8'hFA;
54: s = 8'hFB;
55: s = 8'hFC;
56: s = 8'hFD;
57: s = 8'hFD;
58: s = 8'hFE;
59: s = 8'hFE;
60: s = 8'hFE;
61: s = 8'hFF;
62: s = 8'hFF;
63: s = 8'hFF;
64: s = 8'hFF;
65: s = 8'hFF;
66: s = 8'hFF;
67: s = 8'hFF;
68: s = 8'hFE;
69: s = 8'hFE;
70: s = 8'hFE;
71: s = 8'hFD;
72: s = 8'hFD;
73: s = 8'hFC;
74: s = 8'hFB;
75: s = 8'hFA;
76: s = 8'hFA;
77: s = 8'hF9;
78: s = 8'hF8;
79: s = 8'hF6;
80: s = 8'hF5;
81: s = 8'hF4;
82: s = 8'hF3;
83: s = 8'hF1;
84: s = 8'hF0;
85: s = 8'hEE;
86: s = 8'hED;
87: s = 8'hEB;
88: s = 8'hEA;
89: s = 8'hE8;
90: s = 8'hE6;
91: s = 8'hE4;
92: s = 8'hE2;
93: s = 8'hE0;
94: s = 8'hDE;
95: s = 8'hDC;
96: s = 8'hDA;
97: s = 8'hD7;
98: s = 8'hD5;
99: s = 8'hD3;
100: s = 8'hD0;
101: s = 8'hCE;
102: s = 8'hCB;
103: s = 8'hC9;
104: s = 8'hC6;
105: s = 8'hC4;
106: s = 8'hC1;
107: s = 8'hBE;
108: s = 8'hBC;
109: s = 8'hB9;
110: s = 8'hB6;
111: s = 8'hB3;
112: s = 8'hB0;
113: s = 8'hAD;
114: s = 8'hAA;
115: s = 8'hA7;
116: s = 8'hA5;
117: s = 8'hA2;
118: s = 8'h9E;
119: s = 8'h9B;
120: s = 8'h98;
121: s = 8'h95;
122: s = 8'h92;
123: s = 8'h8F;
124: s = 8'h8C;
125: s = 8'h89;
126: s = 8'h86;
127: s = 8'h83;
128: s = 8'h80;
129: s = 8'h7C;
130: s = 8'h79;
131: s = 8'h76;
132: s = 8'h73;
133: s = 8'h70;
134: s = 8'h6D;
135: s = 8'h6A;
136: s = 8'h67;
137: s = 8'h64;
138: s = 8'h61;
139: s = 8'h5D;
140: s = 8'h5A;
141: s = 8'h58;
142: s = 8'h55;
143: s = 8'h52;
144: s = 8'h4F;
145: s = 8'h4C;
146: s = 8'h49;
147: s = 8'h46;
148: s = 8'h43;
149: s = 8'h41;
150: s = 8'h3E;
151: s = 8'h3B;
152: s = 8'h39;
153: s = 8'h36;
154: s = 8'h34;
155: s = 8'h31;
156: s = 8'h2F;
157: s = 8'h2C;
158: s = 8'h2A;
159: s = 8'h28;
160: s = 8'h25;
161: s = 8'h23;
162: s = 8'h21;
163: s = 8'h1F;
164: s = 8'h1D;
165: s = 8'h1B;
166: s = 8'h19;
167: s = 8'h17;
168: s = 8'h15;
169: s = 8'h14;
170: s = 8'h12;
171: s = 8'h11;
172: s = 8'h0F;
173: s = 8'h0E;
174: s = 8'h0C;
175: s = 8'h0B;
176: s = 8'h0A;
177: s = 8'h09;
178: s = 8'h07;
179: s = 8'h06;
180: s = 8'h05;
181: s = 8'h05;
182: s = 8'h04;
183: s = 8'h03;
184: s = 8'h02;
185: s = 8'h02;
186: s = 8'h01;
187: s = 8'h01;
188: s = 8'h01;
189: s = 8'h00;
190: s = 8'h00;
191: s = 8'h00;
192: s = 8'h00;
193: s = 8'h00;
194: s = 8'h00;
195: s = 8'h00;
196: s = 8'h01;
197: s = 8'h01;
198: s = 8'h01;
199: s = 8'h02;
200: s = 8'h02;
201: s = 8'h03;
202: s = 8'h04;
203: s = 8'h05;
204: s = 8'h05;
205: s = 8'h06;
206: s = 8'h07;
207: s = 8'h09;
208: s = 8'h0A;
209: s = 8'h0B;
210: s = 8'h0C;
211: s = 8'h0E;
212: s = 8'h0F;
213: s = 8'h11;
214: s = 8'h12;
215: s = 8'h14;
216: s = 8'h15;
217: s = 8'h17;
218: s = 8'h19;
219: s = 8'h1B;
220: s = 8'h1D;
221: s = 8'h1F;
222: s = 8'h21;
223: s = 8'h23;
224: s = 8'h25;
225: s = 8'h28;
226: s = 8'h2A;
227: s = 8'h2C;
228: s = 8'h2F;
229: s = 8'h31;
230: s = 8'h34;
231: s = 8'h36;
232: s = 8'h39;
233: s = 8'h3B;
234: s = 8'h3E;
235: s = 8'h41;
236: s = 8'h43;
237: s = 8'h46;
238: s = 8'h49;
239: s = 8'h4C;
240: s = 8'h4F;
241: s = 8'h52;
242: s = 8'h55;
243: s = 8'h58;
244: s = 8'h5A;
245: s = 8'h5D;
246: s = 8'h61;
247: s = 8'h64;
248: s = 8'h67;
249: s = 8'h6A;
250: s = 8'h6D;
251: s = 8'h70;
252: s = 8'h73;
253: s = 8'h76;
254: s = 8'h79;
255: s = 8'h7C;
endcase
end
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module minimac2_sync(
input sys_clk,
input phy_rx_clk,
input phy_tx_clk,
input [1:0] sys_rx_ready,
output [1:0] sys_rx_done,
output reg [10:0] sys_rx_count_0,
output reg [10:0] sys_rx_count_1,
input sys_tx_start,
output sys_tx_done,
input [10:0] sys_tx_count,
output [1:0] phy_rx_ready,
input [1:0] phy_rx_done,
input [10:0] phy_rx_count_0,
input [10:0] phy_rx_count_1,
output phy_tx_start,
input phy_tx_done,
output reg [10:0] phy_tx_count
);
minimac2_psync rx_ready_0(
.clk1(sys_clk),
.i(sys_rx_ready[0]),
.clk2(phy_rx_clk),
.o(phy_rx_ready[0])
);
minimac2_psync rx_ready_1(
.clk1(sys_clk),
.i(sys_rx_ready[1]),
.clk2(phy_rx_clk),
.o(phy_rx_ready[1])
);
minimac2_psync rx_done_0(
.clk1(phy_rx_clk),
.i(phy_rx_done[0]),
.clk2(sys_clk),
.o(sys_rx_done[0])
);
minimac2_psync rx_done_1(
.clk1(phy_rx_clk),
.i(phy_rx_done[1]),
.clk2(sys_clk),
.o(sys_rx_done[1])
);
reg [10:0] sys_rx_count_0_r;
reg [10:0] sys_rx_count_1_r;
always @(posedge sys_clk) begin
sys_rx_count_0_r <= phy_rx_count_0;
sys_rx_count_0 <= sys_rx_count_0_r;
sys_rx_count_1_r <= phy_rx_count_1;
sys_rx_count_1 <= sys_rx_count_1_r;
end
minimac2_psync tx_start(
.clk1(sys_clk),
.i(sys_tx_start),
.clk2(phy_tx_clk),
.o(phy_tx_start)
);
minimac2_psync tx_done(
.clk1(phy_tx_clk),
.i(phy_tx_done),
.clk2(sys_clk),
.o(sys_tx_done)
);
reg [10:0] phy_tx_count_r;
always @(posedge phy_tx_clk) begin
phy_tx_count_r <= sys_tx_count;
phy_tx_count <= phy_tx_count_r;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[6]; int sum = 0; int x, y, z; int x1, adjf, z1; int main() { ios_base::sync_with_stdio(false); cin.tie(0); scanf( %d%d%d , &x, &y, &z); scanf( %d%d%d , &x1, &adjf, &z1); for (auto i = 0; i != 6; i++) scanf( %d , &a[i]); if (y < 0) { sum += a[0]; } if (y > adjf) { sum += a[1]; } if (z < 0) { sum += a[2]; } if (z > z1) { sum += a[3]; } if (x < 0) { sum += a[4]; } if (x > x1) { sum += a[5]; } printf( %d , sum); return 0; } |
#include <bits/stdc++.h> using namespace std; struct Grass { int sizee; char dir; } a[100005]; int n; bool flag[100005]; int main() { cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i].dir; } for (int i = 1; i <= n; i++) { cin >> a[i].sizee; } int nowx = 1; flag[nowx] = 1; while (true) { if (a[nowx].dir == > ) { nowx += a[nowx].sizee; } else { nowx -= a[nowx].sizee; } if (nowx > n || nowx < 1) { cout << FINITE ; break; } if (flag[nowx] == 1) { cout << INFINITE ; break; } flag[nowx] = 1; } return 0; } |
#include <bits/stdc++.h> int* array; int f(int index) { if (array[index] == -1) { array[index] = index; return index; } if (array[index] == index) return index; int r = f(array[index]); array[index] = r; return r; } int main() { int n, m; scanf( %d %d , &n, &m); int coils = 0; int connect[n]; array = connect + 0; int notcoils[n]; for (int i = 0; i < n; i++) { connect[i] = -1; notcoils[i] = 0; } for (int i = 0; i < m; i++) { int b, e; scanf( %d %d , &b, &e); --b; --e; if (b == e) { if (connect[b] == -1) connect[b] = b; ++coils; } else { int rootb = f(b); int roote = f(e); connect[roote] = rootb; ++notcoils[b]; ++notcoils[e]; } } int notcoilsTotal = m - coils; int r = -1; for (int i = 0; i < n; i++) { if (connect[i] != -1) if (f(i) != r) { if (r == -1) r = connect[i]; else { printf( %d , 0); return 0; } } } long long ans = coils; ans = ans * (ans - 1) / 2 + notcoilsTotal * ans; for (int i = 0; i < n; i++) { long long nc = notcoils[i]; ans += nc * (nc - 1) / 2; } std::cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; signed main() { long long n; cin >> n; long long a[n]; long long sum = 0; for (long long i = 0; i < n; i++) { cin >> a[i]; sum += a[i]; } long long req = ceil(4.5 * n) - sum; vector<long long> b(n); for (long long i = 0; i < n; i++) { b[i] = 5 - a[i]; } bool check = 0; sort(b.begin(), b.end(), greater<long long>()); long long ans = 0; for (long long i = 0; i < n; i++) { if (req <= 0) { cout << ans; check = 1; break; } req -= b[i]; ans++; } if (!check) cout << n; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A21BOI_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__A21BOI_PP_BLACKBOX_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a21boi (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A21BOI_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S50_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__CLKDLYBUF4S50_PP_BLACKBOX_V
/**
* clkdlybuf4s50: Clock Delay Buffer 4-stage 0.59um length inner stage
* gates.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__clkdlybuf4s50 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S50_PP_BLACKBOX_V
|
//#############################################################################
//# Function: Clock domain crossing FIFO #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_fifo_cdc # (parameter DW = 104, //FIFO width
parameter DEPTH = 32, //FIFO depth (entries)
parameter TARGET = "GENERIC" //XILINX,ALTERA,GENERIC
)
(
input nreset, // shared domain async active low reset
input clk_in, // write clock
input access_in, // write access
input [DW-1:0] packet_in, // write packet
output wait_out, // write pushback
input clk_out, //read clock
output reg access_out, //read access
output [DW-1:0] packet_out, //read packet
input wait_in, // read pushback
output prog_full, // fifo is half full
output full, // fifo is full
output empty // fifo is empty
);
// local wires
wire wr_en;
wire rd_en;
wire io_nreset;
// parametric async fifo
oh_fifo_async #(.TARGET(TARGET),
.DW(DW),
.DEPTH(DEPTH))
fifo (.prog_full (prog_full),
.full (full),
.rd_count (),
.nreset (nreset),
.dout (packet_out[DW-1:0]),
.empty (empty),
.wr_clk (clk_in),
.rd_clk (clk_out),
.wr_en (wr_en),
.din (packet_in[DW-1:0]),
.rd_en (rd_en));
// FIFO control logic
assign wr_en = access_in;
assign rd_en = ~empty & ~wait_in;
assign wait_out = prog_full; //wait_out should stall access_in signal
// pipeline access_out signal
always @ (posedge clk_out or negedge io_nreset)
if(!io_nreset)
access_out <= 1'b0;
else if(~wait_in)
access_out <= rd_en;
// be safe, synchronize reset with clk_out
oh_rsync sync_reset(.nrst_out (io_nreset),
.clk (clk_out),
.nrst_in (nreset));
endmodule // oh_fifo_cdc
|
// Beck Pang
// University of Washington, Seattle
// Apr. 6th, 2015
// EE 471, Lab 1
`include "DFlipFlop.v"
`include "JohnsonCounter.v"
// test bench running on gtkwave
module JohnsonCounter_testBench ();
// connext the two modules
wire clk, rst_n;
wire [3:0] out;
// declare an instance of the AND module
JohnsonCounter myCounter (clk, rst_n, out);
// Running the GUI part of simulation
JohnsonCounter_Tester aTester (clk, rst_n, out);
// file for gtkwave
initial
begin
$dumpfile("JohnsonCounter.vcd");
$dumpvars(1, myCounter);
end
endmodule
module JohnsonCounter_Tester (
output reg clk, rst_n,
input [3:0] out
);
parameter stimDelay = 20;
// generate a clock
always #(stimDelay/2) clk = ~clk;
initial // Response
begin
$display("\t\t clk rst_n \t out \t Time ");
$monitor("\t %b ", out, $time);
clk = 'b0;
end
always @(posedge clk) // Stimulus
begin
rst_n = 'b0;
#stimDelay rst_n = 'b1;
#(32*stimDelay) rst_n = 'b0;
#stimDelay clk = 'b1;
#(32*stimDelay) clk = 'b0;
#stimDelay clk = 'b1;
#(2*stimDelay);
$stop;
$finish;
end
endmodule |
#include <bits/stdc++.h> using namespace std; const long long N = 5e5 + 1, mod = 1e9 + 7, base = 17; int n, m, d, c, up; int f[N]; int sum[N]; int it[N * 4]; int common[N]; int small[N * 2]; int tmp[N]; int flag[N * 2][30]; unsigned long long hashes[N]; long long pw[N]; string srr; vector<int> idx[N * 2]; int convert(char c) { if (c == ( ) { return 7; } return 13; } long long ask(int l, int r) { long long sub = 0; if (l > 0) { sub = hashes[l - 1]; } return (hashes[r] - sub * pw[r - l + 1]); } int lcp(int x, int y) { int low = 0, high = srr.size() - min(x, y) - 1, ans = -1; while (low <= high) { int val = (low + high) >> 1; if (ask(x, x + val) == ask(y, y + val)) { ans = val; low = val + 1; } else { high = val - 1; } } return ans; } bool cmp(int u, int v) { if (small[u] != small[v]) { return small[u] < small[v]; } return small[u + up] < small[v + up]; } void build(int i, int l, int r) { if (l == r) { it[i] = sum[l]; return; } int mid = (l + r) >> 1; build(i * 2, l, mid); build(i * 2 + 1, mid + 1, r); it[i] = min(it[i * 2], it[i * 2 + 1]); } int query(int i, int l, int r) { if (d > r || l > c) { return N; } if (l >= d && r <= c) { return it[i]; } int mid = (l + r) >> 1; return min(query(i * 2, l, mid), query(i * 2 + 1, mid + 1, r)); } int range(int l, int r) { int lgr = log2(r - l + 1); return min(flag[l][lgr], flag[r - (1 << lgr) + 1][lgr]); } bool correct(int l, int r) { int sub = 0; if (l > 0) { sub = sum[l - 1]; } return (sum[r] == sub && range(l, r) >= sub); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n >> srr; for (int i = 0; i < srr.size(); ++i) { f[i] = i; small[i] = srr[i]; } hashes[0] = convert(srr[0]); for (int i = 1; i < srr.size(); ++i) { hashes[i] = (1LL * hashes[i - 1] * base + convert(srr[i])); } pw[0] = 1; for (int i = 1; i <= srr.size(); ++i) { pw[i] = (pw[i - 1] * base); } for (up = 1; up <= srr.size(); up *= 2) { sort(f, f + n, cmp); tmp[f[0]] = 0; for (int i = 1; i < srr.size(); ++i) { tmp[f[i]] = tmp[f[i - 1]] + cmp(f[i - 1], f[i]); } for (int i = 0; i < srr.size(); ++i) { small[i] = tmp[i]; } if (small[f[n - 1]] == n - 1) { break; } } for (int i = 1; i < srr.size(); ++i) { common[i] = lcp(f[i - 1], f[i]) + 1; } sum[0] = (srr[0] == ( ? 1 : -1); for (int i = 1; i < srr.size(); ++i) { sum[i] = sum[i - 1] + (srr[i] == ( ? 1 : -1); } for (int i = 0; i < srr.size(); ++i) { for (int j = 0; j < 30; ++j) { flag[i][j] = N * 2; } } for (int i = 0; i < srr.size(); ++i) { flag[i][0] = sum[i]; } for (int j = 1; j <= 20; ++j) { for (int i = 0; i < srr.size(); ++i) { flag[i][j] = min(flag[i][j - 1], flag[i + (1 << (j - 1))][j - 1]); } } for (int i = 0; i < srr.size(); ++i) { idx[sum[i] + N].push_back(i); } long long answer = 0; for (int i = 0; i < srr.size(); ++i) { int least = common[i] + 1, u = f[i]; int values = 0; if (u > 0) { values = sum[u - 1]; } int curr = values + N; int low = lower_bound(idx[curr].begin(), idx[curr].end(), u + least - 1) - idx[curr].begin(); if (low == idx[curr].size()) { continue; } int high = idx[curr].size() - 1, ans = low - 1, old = low; while (low <= high) { int mid = (low + high) >> 1; int tt = idx[curr][mid]; if (range(u, tt) >= values) { low = mid + 1; ans = mid; } else { high = mid - 1; } } answer += (ans - old + 1); } cout << answer; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long n, k; cin >> n >> k; vector<long long> v, v1; map<long long, long long> m; for (long long i = 0; i < n; i++) { long long a; cin >> a; v.push_back(a); } long long a, c = 0; cin >> a; for (long long i = 0; i < n; i++) if (v[i] > ((i + 1) * a + k)) c = -1; long long val = k; for (int i = 0; i < n; i++) { int a; cin >> a; v1.push_back(a); } long long sum = 0; if (c == 0) { for (long long i = 0; i < n; i++) { m[v1[i]]++; auto itr = m.begin(); while (v[i] > val && itr != m.end()) { if (itr->second == 0 && itr != m.end()) { auto itr1 = itr; itr1++; m.erase(itr->first); itr = m.find(itr1->first); } else { val += a; sum += itr->first; (itr->second)--; } } } cout << sum << n ; } else cout << -1 << n ; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLCLKP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__DLCLKP_FUNCTIONAL_PP_V
/**
* dlclkp: Clock gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hvl__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hvl__dlclkp (
GCLK,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output GCLK;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire m0 ;
wire clkn ;
wire GCLK_b;
// Name Output Other arguments
not not0 (clkn , CLK );
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE, clkn, , VPWR, VGND);
and and0 (GCLK_b, m0, CLK );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (GCLK , GCLK_b, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLCLKP_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; const long double pi = 3.14159265358979323846; long long MOD = 1e9 + 7; const char nl = n ; const long long inf = 1e15; long long nxt() { long long x; cin >> x; return x; } long long mul(long long x, long long y) { return (1ll * (x % MOD) * (y % MOD)); } long long modpow(long long x, long long y) { long long z = 1; while (y > 0) { if (y % 2) z = mul(z, x); x = mul(x, x); y /= 2; } return z; } long long power(long long x, long long y) { long long z = 1; while (y > 0) { if (y % 2) z = z * x; x = x * x; y /= 2; } return z; } long long gcd(long long a, long long b) { if (a < b) return gcd(b, a); if (b == 0) return a; return gcd(b, a % b); } long long min(long long a, long long b) { if (a < b) return a; return b; } long long max(long long a, long long b) { if (a > b) return a; return b; } long long sq(long long a) { long long ans = (1ll * a * a); return ans; } void solve() { long long n, k; cin >> n >> k; long long t[n]; vector<long long> neg; for (long long i = 0; i < n; i++) { cin >> t[i]; if (t[i] < 0) neg.push_back(i); } if ((long long)(neg.size()) > k) { cout << -1 << nl; return; } if ((long long)(neg.size()) == 0) { cout << 0 << nl; return; } if (n == 1) { if (t[0] < 0) { cout << 1 << nl; } else cout << 0 << nl; return; } vector<long long> dis; for (long long i = 0; i < (long long)(neg.size()) - 1; i++) { if (neg[i + 1] - neg[i] > 1) { dis.push_back(neg[i + 1] - neg[i] - 1); } } sort(((dis).begin()), ((dis).end())); long long ans = (long long)(dis.size()) * 2; ans++; if (t[n - 1] >= 0) ans++; long long ewd = k - (long long)(neg.size()); for (long long x : dis) { if (ewd >= x) ewd -= x, ans -= 2; } long long ex = n - 1 - neg.back(); if (ewd >= ex && ex) ans--; cout << ans << n ; } int main() { ios::sync_with_stdio(false); cin.tie(0), cout.tie(0); long long TC = 1; while (TC--) { solve(); } cerr << Time : << 1000 * ((double)clock()) / (double)CLOCKS_PER_SEC << ms n ; } |
#include <bits/stdc++.h> using namespace std; void solve() { long long n; cin >> n; vector<long long> ar(n + 1, 1e10); vector<long long> cur(n + 1, 1); for (long long i = 1; i <= n; i++) { cin >> ar[i]; if (ar[i] == ar[i - 1]) cur[i] = cur[i - 1] + 1; } long long ans = 0; for (long long i = 1; i <= n; i++) ans += cur[i]; cout << ans; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long t = 1; while (t--) solve(); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10.03.2017 09:19:09
// Design Name:
// Module Name: sine
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sinemod(
input clkdds,
input[31:0] freq,
input signed[15:0] amp,
input signed[15:0] amp_off,
output[11:0] sin
);
wire data_valid;
reg phase_valid = 1;
wire signed[16:0] data;
wire[23:0] phase = (freq*83886)/10000;
dds_compiler_0 sine_dds(clkdds, phase_valid, phase, data_valid, data);
reg signed[16:0] amped = 16'b0;
reg signed[16:0] offseted = 16'b0;
reg signed[16:0] clipped = 16'b0;
wire signed[16:0] amp_clipped = amp > 2048 ? 2048 : amp;
always @(posedge clkdds) begin
amped <= (data * amp_clipped) / 1024; // max 2048 to -2048
offseted <= amp_off + amped;
clipped <= offseted < 0 ? 0 : offseted > 4095 ? 4095 : offseted;
end
assign sin = data_valid?clipped:0;
endmodule |
module tb_gmii2fifo9();
/* 125MHz system clock */
reg sys_clk;
initial sys_clk = 1'b0;
always #8 sys_clk = ~sys_clk;
/* 33MHz PCI clock */
reg pci_clk;
initial pci_clk = 1'b0;
always #30 pci_clk = ~pci_clk;
/* 62.5MHz CPCI clock */
reg cpci_clk;
initial cpci_clk = 1'b0;
always #16 cpci_clk = ~cpci_clk;
/* 125MHz RX clock */
reg phy_rx_clk;
initial phy_rx_clk = 1'b0;
always #8 phy_rx_clk = ~phy_rx_clk;
/* 125MHz TX clock */
reg phy_tx_clk;
initial phy_tx_clk = 1'b0;
always #8 phy_tx_clk = ~phy_tx_clk;
reg sys_rst;
reg phy_rx_dv;
reg [7:0] phy_rxd;
wire [8:0] din;
reg full;
wire wr_en;
wire wr_clk;
gmii2fifo9 # (
.Gap(4'h2)
) gmii2fifo9_tb (
.sys_rst(sys_rst),
.gmii_rx_clk(phy_rx_clk),
.gmii_rx_dv(phy_rx_dv),
.gmii_rxd(phy_rxd),
.din(din),
.full(full),
.wr_en(wr_en),
.wr_clk(wr_clk)
);
task waitclock;
begin
@(posedge sys_clk);
#1;
end
endtask
always @(posedge wr_clk) begin
if (wr_en == 1'b1)
$display("din: %x", din);
end
reg [8:0] rom [0:199];
reg [11:0] counter;
always @(posedge phy_rx_clk) begin
{phy_rx_dv,phy_rxd} <= rom[ counter ];
counter <= counter + 1;
end
initial begin
$dumpfile("./test.vcd");
$dumpvars(0, tb_gmii2fifo9);
$readmemh("./phy_rx.hex", rom);
/* Reset / Initialize our logic */
sys_rst = 1'b1;
full = 1'b0;
counter = 0;
waitclock;
waitclock;
sys_rst = 1'b0;
waitclock;
#30000;
$finish;
end
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.3 (lin64) Build Fri Oct 3 16:31:15 MDT 2014
// Date : Sun Oct 25 15:41:08 2015
// Host : arthas-ubuntu running 64-bit Ubuntu 14.04.3 LTS
// Command : write_verilog -force -mode synth_stub /home/arthas/git/SHD/SHD.srcs/sources_1/ip/clk_gen/clk_gen_stub.v
// Design : clk_gen
// Purpose : Stub declaration of top-level module interface
// Device : xc7vx690tffg1761-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module clk_gen(clk_in1, clk_out1, reset)
/* synthesis syn_black_box black_box_pad_pin="clk_in1,clk_out1,reset" */;
input clk_in1;
output clk_out1;
input reset;
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/SRL16E.v,v 1.7 2005/03/14 22:32:58 yanx Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 8.1i (I.13)
// \ \ Description : Xilinx Functional Simulation Library Component
// / / 16-Bit Shift Register Look-Up-Table with Clock Enable
// /___/ /\ Filename : SRL16E.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:40 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// End Revision
`timescale 1 ps / 1 ps
module SRL16E (Q, A0, A1, A2, A3, CE, CLK, D);
parameter INIT = 16'h0000;
output Q;
input A0, A1, A2, A3, CE, CLK, D;
reg [15:0] data;
assign Q = data[{A3, A2, A1, A0}];
initial
begin
assign data = INIT;
while (CLK === 1'b1 || CLK===1'bX)
#10;
deassign data;
end
always @(posedge CLK)
begin
if (CE == 1'b1) begin
{data[15:0]} <= #100 {data[14:0], D};
end
end
endmodule
|
/*************************************************************************
* *
* Copyright (C) 2016,2017 Alves, Fredy. *
* All rights reserved. Email: *
* *
* This design is free software; you can redistribute it and/or *
* modify it under the terms of EITHER: *
* (1) The GNU Lesser General Public License as published by the Free *
* Software Foundation; either version 2.1 of the License, or (at *
* your option) any later version. The text of the GNU Lesser *
* General Public License is included with this design in the *
* file LICENSE. *
* *
* This design is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the files *
* LICENSE.TXT and LICENSE-BSD.TXT for more details. *
* *
*************************************************************************/
module add3
(
input CLK,
input [31:0] a1,
input [31:0] a2,
input [31:0] a3,
input reset,
output reg [31:0] result,
output reg out_rdy
);
wire done_add1;
wire done_add2;
wire [31:0] out_add1;
wire [31:0] out_add2;
reg resetadd2 = 1'b0;
add_comb add1 (
.clk_en ( 1'b1 ),
.clock ( CLK ),
.dataa ( a1 ),
.datab ( a2 ),
.result ( out_add1 ),
.reset(reset),
.done(done_add1)
);
add_comb add2 (
.clk_en ( 1'b1 ),
.clock ( CLK ),
.dataa ( out_add1 ),
.datab ( a3 ),
.result ( out_add2 ),
.reset(resetadd2),
.done(done_add2)
);
always @(posedge done_add1 or posedge done_add2 or negedge reset)
begin
if(reset == 1'b0)
begin
resetadd2 <= 1'b0;
out_rdy <= 1'b0;
end
else
begin
if(done_add1)
begin
resetadd2 <= 1'b1;
end
if(done_add2)
begin
result <= out_add2;
out_rdy <= 1'b1;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int sum[1000000 + 10][27]; char c1[1000000 + 10], c2[1000000 + 10]; long long n, m; long long len1, len2; long long gcd(long long a, long long b) { long long t = a; while (b) { a = b; b = t % b; t = a; } return a; } int main() { cin >> n >> m; scanf( %s%s , c1, c2); len1 = strlen(c1), len2 = strlen(c2); long long t = gcd(len1, len2); long long k = n / (len2 / t); long long res = 0; for (int i = 0; i < len2; ++i) sum[i % t][c2[i] - a ]++; for (int i = 0; i < len1; ++i) for (int j = 0; j < 26; ++j) if (j != c1[i] - a ) res += sum[i % t][j]; res *= k; cout << res << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A22OI_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__A22OI_FUNCTIONAL_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__a22oi (
Y ,
A1,
A2,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y, nand0_out, nand1_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A22OI_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; pair<int, int> V[2001010]; int cnt[2002]; long long cum[2002], N; string s; void make(int l, int r) { while (l >= 0 && r < (int)s.size()) { if (s[l] == s[r]) { V[N++] = (make_pair(l, r)); cnt[l]++; } else break; l--, r++; } } int main() { N = 0; cin >> s; memset(cnt, 0, sizeof(cnt)); for (int i = 0; i < (int)s.size(); ++i) { make(i, i); make(i - 1, i); } cum[0] = 0; for (int i = 0; i < (int)s.size(); ++i) cum[i + 1] = cum[i] + cnt[i]; long long Sm = cum[s.size()]; long long c = 0; for (int i = 0; i < N; ++i) { c += (Sm - cum[V[i].second + 1]); } cout << c << endl; } |
#include <bits/stdc++.h> using namespace std; long long int n; int main() { scanf( %lld , &n); if (n == 1 || n == 3 || n == 4 || n == 6 || n == 9 || n == 12) { cout << 0 << endl; return 0; } int mod = n % 3, mx; if (mod == 2) { for (long long i = 1e7; i >= 1; i -= 3) { if (i * i * 3 + i <= n * 2) { mx = i; break; } } } else if (mod == 1) { for (long long i = 1e7 + 1; i >= 1; i -= 3) { if (i * i * 3 + i <= n * 2) { mx = i; break; } } } else if (mod == 0) { for (long long i = 1e7 + 5; i >= 1; i -= 3) { if (i * i * 3 + i <= n * 2) { mx = i; break; } } } cout << (int)ceil((double)mx / 3) << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long N = 1005; long long n, m, q, ans; bool vizitat[N][N]; long long dp[N][N][2]; bool verifica(long long i, long long j) { if (i < 1 || j < 1 || i > n || j > m) return false; return true; } long long cnt(long long i, long long j) { long long answer = 0; for (long long it = 0; it <= 1; it++) { long long up = 0; long long lin = i; long long col = j; while (verifica(lin, col) && vizitat[lin][col] == false) { if (up % 2 == it) { lin--; } else { col--; } up++; } long long down = 0; lin = i; col = j; while (verifica(lin, col) && vizitat[lin][col] == false) { if (down % 2 == it) { col++; } else { lin++; } down++; } answer += up * down; } answer--; return answer; } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> m >> q; for (long long i = 1; i <= n; i++) { for (long long j = 1; j <= m; j++) { dp[i][j][1] = dp[i][j - 1][0] + 1; dp[i][j][0] = dp[i - 1][j][1] + 1; ans += dp[i][j][1]; ans += dp[i][j][0]; } } ans -= n * m; while (q--) { long long lin, col; cin >> lin >> col; if (vizitat[lin][col] == true) { vizitat[lin][col] = false; ans += cnt(lin, col); } else { ans -= cnt(lin, col); vizitat[lin][col] = true; } cout << ans << n ; } return 0; } |
////////////////////////////////////////////////////////////////////////////////
//
// PS2-to-SAM Mouse
// (C) 2016 Sorgelig
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//
////////////////////////////////////////////////////////////////////////////////
module mouse
(
input clk_sys,
input ce_6mp,
input reset,
input [24:0] ps2_mouse,
input rd,
output [4:0] dout
);
assign dout = {1'b1, data};
reg [3:0] button;
reg [11:0] dx,ldx;
reg [11:0] dy,ldy;
wire [11:0] mdx = {{4{ps2_mouse[4]}},ps2_mouse[15:8]};
wire [11:0] mdy = {{4{ps2_mouse[5]}},ps2_mouse[23:16]};
wire [11:0] newdx = dx + mdx;
wire [11:0] newdy = dy + mdy;
reg [3:0] queue;
reg [3:0] data;
always @* begin
case({~rd, queue})
2: data = ~button;
3: data = ldy[11:8];
4: data = ldy[7:4];
5: data = ldy[3:0];
6: data = ldx[11:8];
7: data = ldx[7:4];
8: data = ldx[3:0];
default: data = 'hF;
endcase
end
always @(posedge clk_sys) begin
reg old_rd;
reg [7:0] timout;
reg old_stb;
if(reset) begin
dx <= 0;
dy <= 0;
button <= 0;
queue <= 0;
timout <= 0;
old_rd <= 0;
end else begin
old_rd <= rd;
if(old_rd & ~rd) queue <= (queue == 8) ? 4'd1 : queue + 1'd1;
if(~old_rd & rd) begin
timout <= 0;
if(queue == 2) begin
ldx <= dx;
ldy <= dy;
end
if(queue == 8) begin
dx <= dx - ldx;
dy <= dy - ldy;
end
end else begin
old_stb <= ps2_mouse[24];
if(old_stb != ps2_mouse[24]) begin
button <= ps2_mouse[2:0];
dx <= mdx[11] ? ((dx[11] & ~newdx[11]) ? 12'h800 : newdx) : ((~dx[11] & newdx[11]) ? 12'h7FF : newdx);
dy <= mdy[11] ? ((dy[11] & ~newdy[11]) ? 12'h800 : newdy) : ((~dy[11] & newdy[11]) ? 12'h7FF : newdy);
end
if(ce_6mp) begin
if(timout < 181) timout <= timout + 1'd1;
if(timout == 180) queue <= 0;
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int a[60], i, x, n, k; cin >> n >> k; for (i = 1; i <= n; i++) cin >> a[i]; sort(a + 1, a + 1 + n); if ((n + 1 - k) >= 1) cout << a[n + 1 - k] << << a[n + 1 - k]; else cout << -1 ; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 50; const int INF = 0x3f3f3f3f; struct node { int to, next; } edge[maxn * 3]; struct Node { int id; long long val; bool operator<(const Node& a) const { return val < a.val; } }; int head[maxn], cnt, d[maxn], depth[maxn], ans[maxn]; int s[maxn]; void add(int u, int v) { edge[cnt].to = v; edge[cnt].next = head[u]; head[u] = cnt++; } void dfs(int k, int fa) { for (int i = head[k]; i != -1; i = edge[i].next) { int to = edge[i].to; if (to == fa) continue; depth[to] = depth[k] + 1; dfs(to, k); s[k] += s[to] + 1; } } int main() { int n, k; cnt = 0; memset(head, -1, sizeof(head)); memset(depth, -1, sizeof(depth)); memset(s, 0, sizeof(s)); scanf( %d%d , &n, &k); for (int i = 1; i < n; i++) { int u, v; scanf( %d%d , &u, &v); add(u, v); add(v, u); d[u]++; d[v]++; } depth[1] = 0; dfs(1, 1); priority_queue<Node> q; for (int i = 1; i <= n; i++) if (d[i] == 1 && i != 1) q.push({i, depth[i]}); long long sum = 0; while (k && !q.empty()) { Node top = q.top(); sum += top.val; q.pop(); k--; for (int i = head[top.id]; i != -1; i = edge[i].next) { int to = edge[i].to; if (depth[to] < depth[top.id]) { d[to]--; if (d[to] == 1) q.push({to, depth[to] - s[to]}); break; } } } printf( %lld n , sum); } |
//////////////////////////////////////////////////////////////////////
//// ////
//// spi_slave_model.v ////
//// ////
//// This file is part of the SPI IP core project ////
//// http://www.opencores.org/projects/spi/ ////
//// ////
//// Author(s): ////
//// - Simon Srot () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "timescale.v"
module spi_slave_model (rst, ss, sclk, mosi, miso);
input rst; // reset
input ss; // slave select
input sclk; // serial clock
input mosi; // master out slave in
output miso; // master in slave out
reg miso;
reg rx_negedge; // slave receiving on negedge
reg tx_negedge; // slave transmiting on negedge
reg [31:0] data; // data register
parameter Tp = 1;
always @(posedge(sclk && !rx_negedge) or negedge(sclk && rx_negedge) or rst)
begin
if (rst)
data <= #Tp 32'b0;
else if (!ss)
data <= #Tp {data[30:0], mosi};
end
always @(posedge(sclk && !tx_negedge) or negedge(sclk && tx_negedge))
begin
miso <= #Tp data[31];
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2BB2A_BEHAVIORAL_V
`define SKY130_FD_SC_LS__O2BB2A_BEHAVIORAL_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
and and0 (and0_out_X, nand0_out, or0_out);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2BB2A_BEHAVIORAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:10:52 08/30/2014
// Design Name:
// Module Name: lab4dpath
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module lab4dpath(x1,x2,x3,y,clk);
input [9:0] x1,x2,x3;
input clk;
output [9:0] y;
//mult12x12 input (a,b[11:0] output (p[23:0])
wire [11:0] s2, v1, v2, v3;
wire [23:0] t1, t2, t3;
//dff io ports
reg [9:0] d1, d2, d3, q1, q2, q3;
//input dff
always @(posedge clk) begin
d1 <= x1;
d2 <= x2;
d3 <= x3;
end
//output dff
always @(posedge clk) begin
q1 <= d1;
q2 <= d2;
q3 <= d3;
end
assign v1 = {q1, 2'b00};
assign v2 = {q2, 2'b00};
assign v3 = {q3, 2'b00};
mult12x12 i1 (.a(12'b110000000000), .b(v1), .p(t1));
mult12x12 i2 (.a(12'b010100000000), .b(v2), .p(t2));
mult12x12 i3 (.a(12'b110000000000), .b(v3), .p(t3));
assign s2 = t1[22:11] + t2[22:11] + t3[22:11];
//assign y to upper bits of s2
assign y = s2[11:2];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21A_PP_SYMBOL_V
`define SKY130_FD_SC_LP__O21A_PP_SYMBOL_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o21a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21A_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FAH_FUNCTIONAL_V
`define SKY130_FD_SC_LP__FAH_FUNCTIONAL_V
/**
* fah: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__fah (
COUT,
SUM ,
A ,
B ,
CI
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
// Local signals
wire xor0_out_SUM;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT;
// Name Output Other arguments
xor xor0 (xor0_out_SUM, A, B, CI );
buf buf0 (SUM , xor0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, CI );
and and2 (b_ci , B, CI );
or or0 (or0_out_COUT, a_b, a_ci, b_ci);
buf buf1 (COUT , or0_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__FAH_FUNCTIONAL_V |
// DESCRIPTION: Verilator: SystemVerilog interface test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
logic rst = 1'b1; // reset
integer rst_cnt = 0;
// reset is removed after a delay
always @ (posedge clk)
begin
rst_cnt <= rst_cnt + 1;
rst <= rst_cnt <= 3;
end
// counters
int cnt;
int cnt_src;
int cnt_drn;
// add all counters
assign cnt = cnt_src + cnt_drn + inf.cnt;
// finish report
always @ (posedge clk)
if (cnt == 3*16) begin
$write("*-* All Finished *-*\n");
$finish;
end
// interface instance
handshake inf (
.clk (clk),
.rst (rst)
);
// source instance
source #(
.RW (8),
.RP (8'b11100001)
) source (
.clk (clk),
.rst (rst),
.inf (inf),
.cnt (cnt_src)
);
// drain instance
drain #(
.RW (8),
.RP (8'b11010100)
) drain (
.clk (clk),
.rst (rst),
.inf (inf),
.cnt (cnt_drn)
);
endmodule : t
// interface definition
interface handshake #(
parameter int unsigned WC = 32
)(
input logic clk,
input logic rst
);
// modport signals
logic req; // request
logic grt; // grant
logic inc; // increment
// local signals
integer cnt; // counter
// source
modport src (
output req,
input grt
);
// drain
modport drn (
input req,
output grt
);
// incremet condition
assign inc = req & grt;
// local logic (counter)
always @ (posedge clk, posedge rst)
if (rst) cnt <= '0;
else cnt <= cnt + {31'h0, inc};
endinterface : handshake
// source module
module source #(
// random generator parameters
parameter int unsigned RW=1, // LFSR width
parameter bit [RW-1:0] RP='0, // LFSR polinom
parameter bit [RW-1:0] RR='1 // LFSR reset state
)(
input logic clk,
input logic rst,
handshake.src inf,
output integer cnt
);
// LFSR
logic [RW-1:0] rnd;
// LFSR in Galois form
always @ (posedge clk, posedge rst)
if (rst) rnd <= RR;
else rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP);
// counter
always @ (posedge clk, posedge rst)
if (rst) cnt <= 32'd0;
else cnt <= cnt + {31'd0, (inf.req & inf.grt)};
// request signal
assign inf.req = rnd[0];
endmodule : source
// drain module
module drain #(
// random generator parameters
parameter int unsigned RW=1, // LFSR width
parameter bit [RW-1:0] RP='0, // LFSR polinom
parameter bit [RW-1:0] RR='1 // LFSR reset state
)(
input logic clk,
input logic rst,
handshake.drn inf,
output integer cnt
);
// LFSR
logic [RW-1:0] rnd;
// LFSR in Galois form
always @ (posedge clk, posedge rst)
if (rst) rnd <= RR;
else rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP);
// counter
always @ (posedge clk, posedge rst)
if (rst) cnt <= 32'd0;
else cnt <= cnt + {31'd0, (inf.req & inf.grt)};
// grant signal
assign inf.grt = rnd[0];
endmodule : drain
|
#include <bits/stdc++.h> using namespace std; int a[212345]; int cnts[212345]; int lft[212345]; int rght[212345]; int cumsum[212345]; int get_right_ans(int i) { return cumsum[rght[i]] - cumsum[i]; } int get_left_ans(int i) { if (lft[i]) return cumsum[i - 1] - cumsum[lft[i] - 1]; return cumsum[i - 1]; } void print_ans(int fin_ans, int slope) { if (cnts[fin_ans] < 1) { return; } if (cnts[fin_ans] < 2) { cnts[fin_ans] -= 1; printf( %d , fin_ans); return; } printf( %d , fin_ans); cnts[fin_ans] -= 1; print_ans(fin_ans + slope, slope); while (cnts[fin_ans]) { printf( %d , fin_ans); cnts[fin_ans]--; } } int main() { int n, tmp, fnd; scanf( %d , &n); ; for (int i = 0; i < n; i++) { scanf( %d , &a[i]); ; cnts[a[i]] += 1; } int lst_val = -1; for (int i = 0; i < 212345; i++) { lft[i] = lst_val; if (cnts[i] < 2) lst_val = i; } lst_val = 212345; for (int i = 212345 - 1; i >= 0; i--) { rght[i] = lst_val; if (cnts[i] < 2) lst_val = i; } for (int i = 1; i < 212345; i++) cumsum[i] = cumsum[i - 1] + cnts[i]; int maxi = 0; int fin_ans = -1; for (int i = 1; i < 212345; i++) { if (cnts[i] == 1) { if (1 + max(get_right_ans(i), get_left_ans(i)) > maxi) { maxi = max(maxi, 1 + max(get_right_ans(i), get_left_ans(i))); fin_ans = i; } } else if (cnts[i] > 1) { if (cnts[i] + get_right_ans(i) + get_left_ans(i) > maxi) { maxi = max(maxi, cnts[i] + get_right_ans(i) + get_left_ans(i)); fin_ans = i; } } } printf( %d n , maxi); if (cnts[fin_ans] == 1) { printf( %d , fin_ans); if (get_left_ans(fin_ans) > get_right_ans(fin_ans)) print_ans(fin_ans - 1, -1); else print_ans(fin_ans + 1, +1); } else { if (get_left_ans(fin_ans)) { printf( %d , fin_ans); print_ans(fin_ans - 1, -1); cnts[fin_ans] -= 1; } if (get_right_ans(fin_ans)) { printf( %d , fin_ans); print_ans(fin_ans + 1, 1); cnts[fin_ans] -= 1; } while (cnts[fin_ans]) { printf( %d , fin_ans); cnts[fin_ans]--; } } } |
module mem_arbiter(
output wire[31:0] out_address,
output wire[31:0] out_din,
output wire out_re,
output wire out_we,
input wire[31:0] os_address,
input wire[31:0] os_din,
input wire os_re,
input wire os_we,
input wire[31:0] mfind_address,
input wire[31:0] mfind_din,
input wire mfind_re,
input wire mfind_we,
input wire[31:0] intpr_address,
input wire[31:0] intpr_din,
input wire intpr_re,
input wire intpr_we
);
// Can't OR together the buses, must select
reg[1:0] selection = 0;
always @ (os_re, os_we, mfind_re, mfind_we, intpr_re, intpr_we) begin
if(os_re || os_we) begin
selection <= 2'd0;
end else if(mfind_re || mfind_we) begin
selection <= 2'd1;
end else if(intpr_re || intpr_we) begin
selection <= 2'd2;
end
end
assign out_address =
(selection == 0) ? os_address :
(selection == 1) ? mfind_address :
intpr_address;
assign out_din =
(selection == 0) ? os_din :
(selection == 1) ? mfind_address :
intpr_din;
assign out_we = os_we || mfind_we || intpr_we;
assign out_re = os_re || mfind_re || intpr_re;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; int main() { int t; int n, m; long long s = 0; cin >> n >> m; vector<long long> a(m); for (int i = 0; i < m; i++) { cin >> a[i]; } s += (a[0] - 1); for (int i = 1; i < m; i++) { if (a[i] >= a[i - 1]) { s += (a[i] - a[i - 1]); } else { s += (n - a[i - 1]); s += (a[i]); } } cout << s << endl; } |
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Grab settings off the wishbone bus, send them out to our simpler bus on the fast clock
module settings_bus
#(parameter AWIDTH=16, parameter DWIDTH=32)
(input wb_clk,
input wb_rst,
input [AWIDTH-1:0] wb_adr_i,
input [DWIDTH-1:0] wb_dat_i,
input wb_stb_i,
input wb_we_i,
output reg wb_ack_o,
output reg strobe,
output reg [7:0] addr,
output reg [31:0] data);
reg stb_int, stb_int_d1;
always @(posedge wb_clk)
if(wb_rst)
begin
strobe <= 1'b0;
addr <= 8'd0;
data <= 32'd0;
end
else if(wb_we_i & wb_stb_i & ~wb_ack_o)
begin
strobe <= 1'b1;
addr <= wb_adr_i[9:2];
data <= wb_dat_i;
end
else
strobe <= 1'b0;
always @(posedge wb_clk)
if(wb_rst)
wb_ack_o <= 0;
else
wb_ack_o <= wb_stb_i & ~wb_ack_o;
endmodule // settings_bus
|
#include <bits/stdc++.h> using namespace std; int n; vector<pair<int, int>> vp; int chk() { bool ok = true; int d = vp[2].first - vp[1].first; for (int i = 2; i < n; i++) if (vp[i].first - vp[i - 1].first != d) ok = false; if (ok) { printf( %d n , vp[0].second + 1); exit(0); } d = vp[2].first - vp[0].first; ok = true; for (int i = 3; i < n; ++i) if (vp[i].first - vp[i - 1].first != d) ok = false; if (ok) { printf( %d n , vp[1].second + 1); exit(0); } d = vp[1].first - vp[0].first; int cnt = 0, index = 0; ok = true; for (int i = 1; i < n; i++) { if (vp[i].first - vp[i - 1].first == d) continue; cnt++; if (i == n - 1 or vp[i + 1].first - vp[i - 1].first != d) ok = false; index = vp[i].second; i++; } if (ok and cnt == 1) { cout << index + 1 << endl; exit(0); } } int main() { scanf( %d , &n); vp.resize(n); for (int i = 0; i < n; ++i) { scanf( %d , &vp[i].first); vp[i].second = i; } sort(begin(vp), end(vp)); chk(); if (n < 4) return !printf( 1 n ); reverse(begin(vp), end(vp)); chk(); cout << -1 << endl; } |
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: one_hot_mux.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: A mux module, where the output select is a one-hot bus
// Author: Dustin Richmond
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module one_hot_mux
#(parameter C_DATA_WIDTH = 1,
parameter C_SELECT_WIDTH = 2,
parameter C_AGGREGATE_WIDTH = C_SELECT_WIDTH*C_DATA_WIDTH
)
(
input [C_SELECT_WIDTH-1:0] ONE_HOT_SELECT,
input [C_AGGREGATE_WIDTH-1:0] ONE_HOT_INPUTS,
output [C_DATA_WIDTH-1:0] ONE_HOT_OUTPUT);
`include "functions.vh"
genvar i;
wire [C_DATA_WIDTH-1:0] wOneHotInputs[(1<<C_SELECT_WIDTH):1];
reg [C_DATA_WIDTH-1:0] _rOneHotOutput;
assign ONE_HOT_OUTPUT = _rOneHotOutput;
generate
for( i = 0 ; i < C_SELECT_WIDTH; i = i + 1 ) begin : gen_input_array
assign wOneHotInputs[(1<<i)] = ONE_HOT_INPUTS[C_DATA_WIDTH*i +: C_DATA_WIDTH];
end
if(C_SELECT_WIDTH == 1) begin
always @(*) begin
_rOneHotOutput = wOneHotInputs[1];
end
end else if(C_SELECT_WIDTH == 2) begin
always @(*) begin
case(ONE_HOT_SELECT)
2'b01: _rOneHotOutput = wOneHotInputs[1];
2'b10: _rOneHotOutput = wOneHotInputs[2];
default:_rOneHotOutput = wOneHotInputs[1];
endcase // case (ONE_HOT_SELECT)
end
end else if( C_SELECT_WIDTH == 4) begin
always @(*) begin
case(ONE_HOT_SELECT)
4'b0001: _rOneHotOutput = wOneHotInputs[1];
4'b0010: _rOneHotOutput = wOneHotInputs[2];
4'b0100: _rOneHotOutput = wOneHotInputs[4];
4'b1000: _rOneHotOutput = wOneHotInputs[8];
default:_rOneHotOutput = wOneHotInputs[1];
endcase // case (ONE_HOT_SELECT)
end
end else if( C_SELECT_WIDTH == 8) begin
always @(*) begin
case(ONE_HOT_SELECT)
8'b00000001: _rOneHotOutput = wOneHotInputs[1];
8'b00000010: _rOneHotOutput = wOneHotInputs[2];
8'b00000100: _rOneHotOutput = wOneHotInputs[4];
8'b00001000: _rOneHotOutput = wOneHotInputs[8];
8'b00010000: _rOneHotOutput = wOneHotInputs[16];
8'b00100000: _rOneHotOutput = wOneHotInputs[32];
8'b01000000: _rOneHotOutput = wOneHotInputs[64];
8'b10000000: _rOneHotOutput = wOneHotInputs[128];
default:_rOneHotOutput = wOneHotInputs[1];
endcase // case (ONE_HOT_SELECT)
end
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; int main() { int n, k; scanf( %d %d , &n, &k); vector<int> A(n), acc(n); for (int i = (0); i < (n); ++i) cin >> A[i]; acc[0] = A[0]; for (int i = (1); i < (n); ++i) acc[i] = A[i] + acc[i - 1]; int rsp = -inf; for (int i = (0); i < (n); ++i) { for (int j = (i); j < (n); ++j) { int sum = acc[j] - (i ? acc[i - 1] : 0); rsp = max(rsp, sum); vector<int> v1, v2; for (int kk = (0); kk < (n); ++kk) { if (kk < i or kk > j) { v1.push_back(A[kk]); } else { v2.push_back(A[kk]); } } sort(v1.rbegin(), v1.rend()); sort(v2.begin(), v2.end()); int lim = min(v1.size(), v2.size()); for (int kk = (0); kk < (min(k, lim)); ++kk) { sum -= v2[kk]; sum += v1[kk]; rsp = max(rsp, sum); } } } printf( %d n , rsp); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, odd, up, down; odd = up = down = 0; cin >> n; int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; if (a[i] % 2 != 0) odd++; } for (int i = 0; i < n; i++) { if (a[i] % 2 == 0) cout << a[i] / 2 << endl; else { int x; if (up < odd / 2) { if (a[i] > 0) cout << (a[i] / 2 + 1) << endl; else cout << (a[i] / 2) << endl; up++; } else { if (a[i] > 0) cout << (a[i] / 2) << endl; else cout << (a[i] / 2 - 1) << endl; } } } return 0; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_zzctu_sync.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
//
// Cluster Name: CTU
// Unit Name: ctu_clsp
//
//-----------------------------------------------------------------------------
module bw_zzctu_sync (/*AUTOARG*/
// Outputs
so, out, sob,
// Inputs
d, si, sib, pll_out, pll_out_l, se
);
input d;
input si;
input sib;
input pll_out;
input pll_out_l;
input se;
output so;
output sob;
output out;
wire ql1, ql2;
wire so1, so2;
wire pll_out_inv;
assign pll_out_inv = ~pll_out;
/* bw_u1_soffi_4x AUTO_TEMPLATE (
.q_l(ql1),
.d(d),
.ck(pll_out),
.sd(si),
.so(so1),
);
*/
bw_u1_soffi_4x u_I0(/*AUTOINST*/
// Outputs
.q_l (ql1), // Templated
.so (so), // Templated
// Inputs
.ck (pll_out), // Templated
.d (d), // Templated
.se (se),
.sd (si)); // Templated
/* bw_u1_soffi_4x AUTO_TEMPLATE (
.q_l(ql2),
.d(ql1),
.ck(pll_out_inv),
.sd(so1),
.so(so2),
);
*/
bw_u1_soffi_4x u_I1(/*AUTOINST*/
// Outputs
.q_l (ql2), // Templated
.so (sob1), // Templated
// Inputs
.ck (pll_out_inv), // Templated
.d (ql1), // Templated
.se (se),
.sd (sib)); // Templated
/* bw_u1_soff_8x AUTO_TEMPLATE (
.q(out),
.d(ql2),
.ck(pll_out_l),
.sd(so2),
.so(so),
);
*/
bw_u1_soff_8x u_I2(/*AUTOINST*/
// Outputs
.q (out), // Templated
.so (sob ), // Templated
// Inputs
.ck (pll_out_l), // Templated
.d (ql2), // Templated
.se (se),
.sd (sob1)); // Templated
endmodule
// Local Variables:
// verilog-library-directories:(".")
// verilog-library-files:("../../../common/rtl/u1.behV")
// verilog-auto-sense-defines-constant:t
// End:
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns/1ps
module tb_ac97();
reg sys_clk;
reg sys_rst;
reg ac97_clk;
reg ac97_rst_n;
initial begin
sys_clk = 1'b0;
ac97_clk = 1'b0;
end
always #5 sys_clk <= ~sys_clk;
always #40 ac97_clk <= ~ac97_clk;
reg [13:0] csr_a;
reg csr_we;
reg [31:0] csr_di;
wire [31:0] wbm_adr_o;
wire wbm_we_o;
wire wbm_stb_o;
reg wbm_ack_i;
reg [31:0] wbm_dat_i;
wire [31:0] wbm_dat_o;
wire dat;
ac97 dut(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.ac97_clk(ac97_clk),
.ac97_rst_n(ac97_rst_n),
.ac97_sin(dat),
.ac97_sout(dat),
.ac97_sync(),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_di),
.csr_do(csr_do),
.cr_irq(),
.dmar_irq(),
.dmaw_irq(),
.wbm_adr_o(wbm_adr_o),
.wbm_cti_o(),
.wbm_we_o(wbm_we_o),
.wbm_cyc_o(),
.wbm_stb_o(wbm_stb_o),
.wbm_ack_i(wbm_ack_i),
.wbm_dat_i(wbm_dat_i),
.wbm_sel_o(),
.wbm_dat_o(wbm_dat_o)
);
always @(posedge sys_clk) begin
if(wbm_stb_o & ~wbm_ack_i) begin
wbm_ack_i <= 1'b1;
if(wbm_we_o) begin
$display("WB WRITE at addr %x, dat %x", wbm_adr_o, wbm_dat_o);
end else begin
wbm_dat_i = wbm_adr_o;
$display("WB READ at addr %x, dat %x", wbm_adr_o, wbm_dat_i);
end
end else
wbm_ack_i <= 1'b0;
end
task waitclock;
begin
@(posedge sys_clk);
#1;
end
endtask
task csrwrite;
input [31:0] address;
input [31:0] data;
begin
csr_a = address[16:2];
csr_di = data;
csr_we = 1'b1;
waitclock;
$display("Configuration Write: %x=%x", address, data);
csr_we = 1'b0;
end
endtask
task csrread;
input [31:0] address;
begin
csr_a = address[16:2];
waitclock;
$display("Configuration Read : %x=%x", address, csr_do);
end
endtask
initial begin
$dumpfile("ac97.vcd");
$dumpvars(0, dut);
ac97_rst_n = 1'b1;
sys_rst = 1'b0;
wbm_ack_i = 1'b0;
#161;
ac97_rst_n = 1'b0;
sys_rst = 1'b1;
#160;
ac97_rst_n = 1'b1;
sys_rst = 1'b0;
#100000;
//csrwrite(32'h8, 32'hcafe);
//csrwrite(32'h0, 32'h3);
//csrread(32'h0);
//#100000;
//csrread(32'h0);
//csrread(32'hc);
csrwrite(32'h14, 32'h0);
csrwrite(32'h18, 32'd40);
csrwrite(32'h10, 32'd1);
#500000;
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct node { int l; int r; } a[200005], b[2000005]; int cmpl(struct node n, struct node m) { return n.l < m.l; } int cmpr(struct node n, struct node m) { return n.r < m.r; } int main() { int n, m; while (~scanf( %d , &n)) { int sum = 0; for (int i = 0; i < n; i++) { scanf( %d%d , &a[i].l, &a[i].r); } scanf( %d , &m); for (int i = 0; i < m; i++) { scanf( %d%d , &b[i].l, &b[i].r); } sort(a, a + n, cmpl); sort(b, b + m, cmpr); if (a[n - 1].l > b[0].r) { sum = max(sum, a[n - 1].l - b[0].r); } sort(a, a + n, cmpr); sort(b, b + m, cmpl); if (b[m - 1].l > a[0].r) { sum = max(sum, b[m - 1].l - a[0].r); } if (!sum) printf( 0 n ); else printf( %d n , sum); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { long long int a, b, ans = 0; cin >> a >> b; ans = min(a, b); ans = min(ans, (a + b) / 3); cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; #define l1 long long int #define fast ios_base::sync_with_stdio(false);cin.tie(NULL);cout.tie(NULL); #define test l1 t;cin>>t;while(t--) // Function to check // if parentheses are balanced bool isBalanced(string exp) { // Initialising Variables bool flag = true; l1 count = 0; // Traversing the Expression for (l1 i = 0; i < exp.length(); i++) { if (exp[i] == ( ) { count++; } else { // It is a closing parenthesis count--; } if (count < 0) { // This means there are // more Closing parenthesis // than opening ones flag = false; break; } } // If count is not zero, // It means there are // more opening parenthesis if (count != 0) { flag = false; } return flag; } int main() { fast test { l1 i,l; string str,str1= ,str2= ; cin>>str; l=str.size(); l1 a=0,b=0,c=0; for(i=0;i<l;i++) { if(str[i]== A ) { a++; } if(str[i]== B ) { b++; } if(str[i]== C ) { c++; } } l1 arr[3]; arr[0]=a;arr[1]=b;arr[2]=c; sort(arr,arr+3); char temp=NULL; if(arr[2]==a) { temp= A ; } else { if(arr[2]==b) { temp= B ; } else { temp= C ; } } for(i=0;i<l;i++) { if(str[i]==temp) { str1+= ( ; str2+= ) ; } else { str1+= ) ; str2+= ( ; } } if(isBalanced(str1) || isBalanced(str2)) { cout<< YES n ; } else { cout<< NO n ; } } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_MUX_2TO1_BLACKBOX_V
`define SKY130_FD_SC_MS__UDP_MUX_2TO1_BLACKBOX_V
/**
* udp_mux_2to1: Two to one multiplexer
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__udp_mux_2to1 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_MUX_2TO1_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n, m; long long k, wyn; long long tab[27][27]; map<long long, long long> odp[27][27]; void back1(int, int, long long); void back2(int, int, long long); int main() { ios_base::sync_with_stdio(0); cin >> n >> m >> k; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) cin >> tab[i][j]; } back1(1, 1, tab[1][1]); back2(n, m, k); if (n == 1 && m == 1 && tab[1][1] == k) cout << 1; else cout << wyn; return 0; } void back1(int x, int y, long long akt) { if (x + y == n + 1) { odp[x][y][akt]++; return; } if (x + 1 <= n) back1(x + 1, y, (akt ^ tab[x + 1][y])); if (y + 1 <= m) back1(x, y + 1, (akt ^ tab[x][y + 1])); } void back2(int x, int y, long long akt) { if (x + y == n + 1) { wyn += odp[x][y][akt]; return; } if (x - 1 >= 1) back2(x - 1, y, (akt ^ tab[x][y])); if (y - 1 >= 1) back2(x, y - 1, (akt ^ tab[x][y])); } |
#include <bits/stdc++.h> using namespace std; int n, ini_pos; vector<int> v[2020]; int a[2020], MAX; map<int, int> mp; int dist(int a, int b) { if (a < b) swap(a, b); return min(a - b, n - a + b); } void input() { scanf( %d %d , &n, &ini_pos); for (int i = 1; i <= n; i++) scanf( %d , a + i), mp[a[i]] = 0; for (map<int, int>::iterator it = mp.begin(); it != mp.end(); it++) { mp[it->first] = ++MAX; } for (int i = 1; i <= n; i++) a[i] = mp[a[i]], v[a[i]].push_back(i); } int f[2020], en[2020]; int same[2020], Same[2020], nxt[2020]; void prepare() { v[0].push_back(ini_pos); for (int m = MAX; m >= 0; m--) { if (m < MAX) { for (int i, j = 0; j < v[m].size(); j++) { i = v[m][j]; int t = m ? i : 0; en[t] = -1; for (int ii, jj = 0; jj < v[m + 1].size(); jj++) { ii = v[m + 1][jj]; int d = dist(i, ii); if (en[t] == -1 || en[t] > d + f[ii]) { nxt[t] = ii; en[t] = d + f[ii]; } } } } if (!m) break; int s = v[m].size(); for (int ii, i, j = 0; j < s; j++) { i = v[m][j]; ii = v[m][(j + 1) % s]; same[i] = +1; Same[i] = ii; f[i] = en[ii] + (n - (ii >= i ? ii - i : ii - i + n)); if (ii == i) { f[i] = en[ii]; continue; } ii = v[m][(j - 1 + s) % s]; int ff = en[ii] + (n - (i >= ii ? i - ii : i - ii + n)); if (f[i] > ff) f[i] = ff, same[i] = -1, Same[i] = ii; } } } void move(int a, int b) { int d = dist(a, b); if (d == b - a || d == b + n - a) printf( %+d n , d); else printf( %+d n , -d); } void a_a(int s, int cur, int type) { if (type == -1) reverse(v[s].begin(), v[s].end()); for (int I = -1, i = 0; i < v[s].size(); i = (i + 1) % (int(v[s].size()))) { int t = v[s][i]; if (I == -1) { if (t == cur) I = i; continue; } if (I == i) return; move(cur, t); cur = t; } } void solve() { int cur = ini_pos; printf( %d n , en[0]); for (int s = 0; s < MAX;) { int t = nxt[s ? cur : 0]; move(cur, t); cur = t; ++s; a_a(s, cur, -same[cur]); cur = Same[cur]; } } int main() { input(); prepare(); solve(); return 0; } |
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the convolutional encoder
// Import the modules that will be tested for in this testbench
`include "cencoder.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_cencoder();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the arbiter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
wire [1:0] cout;
// Declare "reg" signals: inputs to the DUT
reg bin; // Input signal - b
reg ck; // Input clk signal
reg rset; // Input signal - reset
/**
* Instantiate an instance of arbiter_LRU4 so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "arb"
*/
conv_encoder enc (
// instance_name(signal name),
// Signal name can be the same as the instance name
cout,bin,ck,rset);
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
/*
cin = 15'b110101100000011;
$display(cin[1]," << b1 b2 >>",cin[2]);
$display(cin[3]," << b1 b2 >>",cin[4]);
// @ t=0,
#1;
cin = 15'b111000111000011;
#1;
cin = 15'b110011101010011;
#1;
cin = 15'b111101110010011;
#1;
cin = 15'b111110000100011;
#20;
*/
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
`timescale 1ns/1ns
module lspc_timer(
input LSPC_6M,
input RESETP,
input [15:0] M68K_DATA,
input WR_TIMER_HIGH,
input WR_TIMER_LOW,
input VMODE,
input [2:0] TIMER_MODE,
input TIMER_STOP,
input [8:0] RASTERC,
input TIMER_IRQ_EN,
input R74_nQ,
input BNKB,
output D46A_OUT
);
wire [15:0] REG_TIMERHIGH;
wire [15:0] REG_TIMERLOW;
// K31 G50 K48 K58
FDS16bit K31(WR_TIMER_HIGH, M68K_DATA, REG_TIMERHIGH);
assign L106A_OUT = L127_CO;
C43 N50(~LSPC_6M, ~REG_TIMERHIGH[3:0], RELOAD, L106A_OUT, L76_OUT, ~RESETP, , N50_CO);
C43 M18(~LSPC_6M, ~REG_TIMERHIGH[7:4], RELOAD, L106A_OUT, N50_CO, ~RESETP, , M18_CO);
assign K29_OUT = M18_CO ^ 1'b0; // Used for test mode
C43 L51(~LSPC_6M, ~REG_TIMERHIGH[11:8], RELOAD, L106A_OUT, K29_OUT, ~RESETP, , L51_CO);
C43 L16(~LSPC_6M, ~REG_TIMERHIGH[15:12], RELOAD, L106A_OUT, L51_CO, ~RESETP, , TIMER_CO);
// K104 K68 K87 K121
FDS16bit K104(WR_TIMER_LOW, M68K_DATA, REG_TIMERLOW);
C43 L127(~LSPC_6M, ~REG_TIMERLOW[3:0], RELOAD, nTIMER_EN, nTIMER_EN, ~RESETP, , L127_CO);
C43 M125(~LSPC_6M, ~REG_TIMERLOW[7:4], RELOAD, L127_CO, nTIMER_EN, ~RESETP, , M125_CO);
assign M52_OUT = M125_CO ^ 1'b0; // Used for test mode
assign L107A_OUT = L127_CO;
C43 M54(~LSPC_6M, ~REG_TIMERLOW[11:8], RELOAD, L107A_OUT, M52_OUT, ~RESETP, , M54_CO);
C43 L81(~LSPC_6M, ~REG_TIMERLOW[15:12], RELOAD, L107A_OUT, M54_CO, ~RESETP, , L81_CO);
assign L76_OUT = L81_CO ^ 1'b0; // Used for test mode
// Mode 0 reload pulse gen
FDPCell E10(WR_TIMER_LOW, 1'b0, E14A_OUT, 1'b1, E10_Q, );
FDPCell E20(~LSPC_6M, E10_Q, 1'b1, RESETP, E20_Q, E20_nQ);
FDPCell E32(~LSPC_6M, E20_Q, 1'b1, RESETP, , E32_nQ);
assign E14A_OUT = ~&{E20_nQ, E32_nQ};
assign RELOAD_MODE0 = ~|{E32_nQ, ~TIMER_MODE[0], E20_nQ};
// Mode 1 reload pulse gen
FDPCell K18(R74_nQ, BNKB, RESETP, 1'b1, K18_Q, );
FDPCell E16(LSPC_6M, K18_Q, RESETP, 1'b1, E16_Q, );
FDPCell E36(~LSPC_6M, E16_Q, RESETP, 1'b1, E36_Q, );
FDM E46_Q(~LSPC_6M, E36_Q, , E46_nQ);
assign RELOAD_MODE1 = ~|{~TIMER_MODE[1], E46_nQ, E36_Q};
// Mode 2 reload pulse gen and IRQ
assign K22A_OUT = L127_CO & TIMER_CO;
FDM E43(~LSPC_6M, K22A_OUT, , E43_nQ);
assign RELOAD_MODE2 = TIMER_MODE[2] & K22A_OUT;
assign D46A_OUT = ~|{~TIMER_IRQ_EN, E43_nQ};
assign RELOAD = ~|{RELOAD_MODE0, RELOAD_MODE1, RELOAD_MODE2};
// Stop option
assign J257A_OUT = ~|{RASTERC[5:4]};
assign I234_OUT = |{RASTERC[8], ~VMODE, TIMER_STOP};
assign J238B_OUT = ~|{J257A_OUT, I234_OUT};
FDM J69(LSPC_6M, J238B_OUT, , nTIMER_EN);
endmodule
|
#include <bits/stdc++.h> using namespace std; map<string, int> id; inline int getID(string s) { if (id.find(s) == id.end()) { int sz = id.size(); id[s] = sz; } return id[s]; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n, a, b, k, f; cin >> n >> a >> b >> k >> f; map<pair<int, int>, int> rcost; int last = -1, sum = 0; for (int i = 0; i < n; ++i) { string u, v; cin >> u >> v; int su = getID(u); int sv = getID(v); if (last == su) { rcost[pair<int, int>(min(su, sv), max(su, sv))] += b; sum += b; } else { rcost[pair<int, int>(min(su, sv), max(su, sv))] += a; sum += a; } last = sv; } vector<int> diff; for (auto it = rcost.begin(); it != rcost.end(); it++) { int cost = it->second; if (cost > f) { diff.push_back(cost - f); } } sort(diff.rbegin(), diff.rend()); for (int i = 0; i < min((int)diff.size(), k); ++i) { sum -= diff[i]; } cout << sum; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 5e6 + 50; vector<int> v; int vis[N] = {0}, n; int flag[N] = {0}, ans = 0; void dfs(int k) { if (vis[k]) return; vis[k] = 1; if (flag[k]) dfs(k ^ ((1 << n) - 1)); for (int i = 0; i < n; i++) if ((1 << i) & k) dfs(k ^ (1 << i)); } int main() { int m; scanf( %d %d , &n, &m); int temp; for (int i = 1; i <= m; i++) { scanf( %d , &temp); v.push_back(temp); flag[temp] = 1; } for (auto vv : v) { if (!vis[vv]) { ans++; vis[vv] = 1; dfs(vv ^ ((1 << n) - 1)); } } printf( %d n , ans); } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 3e5 + 5, LOG = 19, off = 1 << 19; pair<int, int> t[LOG][2 * off]; void upd(int x, pair<int, int> p, int lg) { for (x += off; x; x /= 2) { t[lg][x].first = min(t[lg][x].first, p.first); t[lg][x].second = max(t[lg][x].second, p.second); } } pair<int, int> get(int x, int lo, int hi, int a, int b, int lg) { if (lo >= a && hi <= b) { return t[lg][x]; } if (lo >= b || hi <= a) { return {off, 0}; } int mid = (lo + hi) >> 1; pair<int, int> lson = get(x * 2, lo, mid, a, b, lg); pair<int, int> rson = get(x * 2 + 1, mid, hi, a, b, lg); return pair<int, int>(min(lson.first, rson.first), max(lson.second, rson.second)); } int r[MAXN]; pair<int, int> par[MAXN][LOG]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n; cin >> n; for (int i = 0; i < n; ++i) { cin >> r[i]; } if (n == 1) { cout << 0; return 0; } for (int i = 0; i < 2 * off; ++i) for (int lg = 0; lg < LOG; ++lg) { t[lg][i].first = off; } for (int i = 0; i < n; ++i) for (int j = 0; j < 3; ++j) { par[i + j * n][0].first = max(0, i + j * n - r[i]); par[i + j * n][0].second = min(3 * n - 1, i + j * n + r[i]); upd(i + j * n, par[i + j * n][0], 0); } for (int lg = 1; lg < LOG; ++lg) { for (int i = n; i < 2 * n; ++i) { par[i][lg] = get(1, 0, off, par[i][lg - 1].first, par[i][lg - 1].second + 1, lg - 1); } for (int i = 0; i < n; ++i) { par[i][lg].first = max(0, par[i + n][lg].first - n); par[i][lg].second = min(3 * n - 1, par[i + n][lg].second - n); } for (int i = 2 * n; i < 3 * n; ++i) { par[i][lg].first = max(0, par[i - n][lg].first + n); par[i][lg].second = min(3 * n - 1, par[i - n][lg].second + n); } for (int i = 0; i < 3 * n; ++i) { upd(i, par[i][lg], lg); } } for (int j = 0; j < n; ++j) { int i = n + j; int lo = i, hi = i, sol = 0; for (int lg = LOG - 1; lg >= 0; --lg) { pair<int, int> res = get(1, 0, off, lo, hi + 1, lg); if (res.second - res.first + 1 < n) { lo = res.first; hi = res.second; sol += (1 << lg); } } cout << sol + 1 << endl; } } |
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; pair<long long, long long> a[n]; for (long long i = 0; i < n; i++) { cin >> a[i].first; a[i].second = i + 1; } sort(a, a + n); long long mx = 0, mx_start = 0, mx_end = 0; long long j; long long mn = n; for (long long i = 0; i < n; i++) { long long c = a[i].second; long long d, ck = 0; for (j = i; j < n; j++) { if (a[i].first != a[j].first) { d = a[j - 1].second; break; } else ck++; } if (j == n) { d = a[j - 1].second; i = n - 1; } else i = j - 1; if (ck > mx) { mx = ck; mx_start = c; mx_end = d; mn = d - c + 1; } else if (ck == mx && (d - c + 1) < mn) { mx = ck; mx_start = c; mx_end = d; mn = d - c + 1; } } cout << mx_start << << mx_end << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; double dp[2][605]; int main() { int n, k; scanf( %d%d , &n, &k); int pre = 0, cur = 1; for (int i = 0; i < n; ++i) { memset(dp[cur], 0, sizeof dp[cur]); for (int j = 1; j < 600; ++j) dp[cur][j] += (1. * j / k / (j + 1) + (k - 1.) / k) * dp[pre][j] + 1. * (dp[pre][j + 1] + j) / ((j + 1.) * k) + 1. * j / 2 / k; swap(pre, cur); } printf( %.15f n , k * dp[pre][1]); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 2e5 + 51, MOD = 998244353, INVP = 828542813; struct Matrix { int num[2][2]; Matrix() { memset(num, 0, sizeof(num)); } inline int *operator[](const int &x) { return num[x]; } inline const int *operator[](const int &x) const { return num[x]; } }; struct SegmentTree { int l, r; Matrix val; }; struct Query { int d, v, id, dl, dr; inline bool operator<(const Query &rhs) const { return (long long int)d * rhs.v < (long long int)v * rhs.d; } }; SegmentTree tree[MAXN << 2]; Matrix mat[MAXN]; Query qry[MAXN << 2]; Matrix id, m1, m2, r; int n, pr, qcnt, res, r2; int x[MAXN], v[MAXN]; inline int read() { register int num = 0, neg = 1; register char ch = getchar(); while (!isdigit(ch) && ch != - ) { ch = getchar(); } if (ch == - ) { neg = -1; ch = getchar(); } while (isdigit(ch)) { num = (num << 3) + (num << 1) + (ch - 0 ); ch = getchar(); } return num * neg; } inline int qpow(int base, int exponent) { int res = 1; while (exponent) { if (exponent & 1) { res = (long long int)res * base % MOD; } base = (long long int)base * base % MOD, exponent >>= 1; } return res; } inline Matrix operator*(Matrix x, Matrix y) { Matrix res; res[0][0] = ((long long int)x[0][0] * y[0][0] + (long long int)x[0][1] * y[1][0]) % MOD; res[0][1] = ((long long int)x[0][0] * y[0][1] + (long long int)x[0][1] * y[1][1]) % MOD; res[1][0] = ((long long int)x[1][0] * y[0][0] + (long long int)x[1][1] * y[1][0]) % MOD; res[1][1] = ((long long int)x[1][0] * y[0][1] + (long long int)x[1][1] * y[1][1]) % MOD; return res; } inline void update(int node) { tree[node].val = tree[node << 1].val * tree[(node << 1) | 1].val; } inline void create(int l, int r, int node) { tree[node] = (SegmentTree){l, r}; if (l == r) { return (void)(tree[node].val = mat[l]); } int mid = (l + r) >> 1; create(l, mid, node << 1), create(mid + 1, r, (node << 1) | 1), update(node); } inline void change(int pos, int x, int node) { if (tree[node].l == tree[node].r) { return (void)(tree[node].val = mat[x]); } int mid = (tree[node].l + tree[node].r) >> 1; change(pos, x, pos <= mid ? node << 1 : (node << 1) | 1), update(node); } int main() { n = read(), id[0][0] = id[1][1] = 1; for (register int i = 1; i <= n; i++) { x[i] = read(), v[i] = read(), pr = (long long int)read() * INVP % MOD; mat[i][0][1] = mat[i][1][1] = pr, mat[i][0][0] = mat[i][1][0] = (MOD + 1 - pr) % MOD; } for (register int i = 2; i <= n; i++) { qry[++qcnt] = (Query){x[i] - x[i - 1], v[i] + v[i - 1], i, 1, 0}; v[i] > v[i - 1] ? qry[++qcnt] = (Query){x[i] - x[i - 1], v[i] - v[i - 1], i, 0, 0}, 1 : 1; v[i] < v[i - 1] ? qry[++qcnt] = (Query){x[i] - x[i - 1], v[i - 1] - v[i], i, 1, 1}, 1 : 1; } sort(qry + 1, qry + qcnt + 1), create(1, n, 1); for (register int i = 1; i <= qcnt; i++) { m1 = mat[qry[i].id], m2 = Matrix(), r2 = (long long int)qry[i].d * qpow(qry[i].v, MOD - 2) % MOD; m2[qry[i].dl][qry[i].dr] = m1[qry[i].dl][qry[i].dr]; mat[qry[i].id] = m2, change(qry[i].id, qry[i].id, 1); r = tree[1].val, res = (res + (long long int)r2 * (r[0][0] + r[0][1]) % MOD) % MOD; m1[qry[i].dl][qry[i].dr] = 0, mat[qry[i].id] = m1; change(qry[i].id, qry[i].id, 1); } printf( %d n , res); } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string a; cin >> a; if (a.size() > 26) { cout << -1 n ; } else { int count = 0; int hash[26] = {0}; for (int i = 0; i < a.size(); i++) { if (hash[a[i] - 97]) count++; else hash[a[i] - 97]++; } cout << count << n ; } } |
#include <bits/stdc++.h> using namespace std; template <class X, class Y> void minimize(X &x, const Y &y) { if (x > y) x = y; } template <class X, class Y> void maximize(X &x, const Y &y) { if (x < y) x = y; } template <class T> T Abs(const T &x) { return (x < 0 ? -x : x); } const int mod = (int)1e9 + 7; int cntWay[500500 * 2], sumWay[500500 * 2]; int frac[500500], finv[500500]; int inverse(int x) { int res = 1; int mul = x; int k = mod - 2; while (k > 0) { if (k & 1) res = 1LL * res * mul % mod; mul = 1LL * mul * mul % mod; k >>= 1; } return (res); } void precalc(void) { frac[0] = finv[0] = 1; for (int i = (1), _b = (500500 - 1); i <= _b; i = i + 1) frac[i] = 1LL * frac[i - 1] * i % mod; for (int i = (1), _b = (500500 - 1); i <= _b; i = i + 1) finv[i] = inverse(frac[i]); } int comb(int k, int n) { if (k > n) return (0); return (1LL * frac[n] * finv[k] % mod * finv[n - k] % mod); } int countWay(int number, int sum, int absLim, int numBig) { sum -= numBig * absLim; sum += (number - numBig) * (absLim + 1); return (comb(number - 1, sum - 1)); } int countWay(int number, int sum, int absLim) { int res = 0; for (int numBig = 0, _n = (number + 1); numBig < _n; numBig = numBig + 1) { int numSet = comb(numBig, number); int numWay = countWay(number, sum, absLim, numBig); if (numBig % 2 == 0) res = (res + 1LL * numSet * numWay) % mod; else res = (res - 1LL * numSet * numWay % mod + mod) % mod; } return (res); } void process(void) { int a, b, range, n; cin >> a >> b >> range >> n; for (int i = (-range * n), _b = (range * n); i <= _b; i = i + 1) cntWay[i + 500500] = countWay(n, i, range); for (int i = (range * n), _a = (-range * n); i >= _a; i = i - 1) sumWay[i + 500500] = (sumWay[i + 1 + 500500] + cntWay[i + 500500]) % mod; int res = 0; for (int i = (-range * n), _b = (range * n); i <= _b; i = i + 1) { int reqScore = b + i + 1 - a; if (reqScore > range * n) continue; maximize(reqScore, -range * n); int numWayB = cntWay[i + 500500]; int numWayA = sumWay[reqScore + 500500]; res = (res + 1LL * numWayA * numWayB) % mod; } printf( %d n , res); } int main(void) { precalc(); process(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int tt; cin >> tt; while (tt--) { int a, b, c, saveb = 0; string st, md, en; st = md = en = ; cin >> a >> b >> c; bool ub = false; while (b) { if (!ub) { md += 01 ; b--; ub = true; } else { if (b == 1 && md[md.size() - 1] == 1 ) { saveb = 1; b--; } else { md += md[md.size() - 1] ^ 1; b--; } } } if (a) { if (!md.size()) st += 00 ; else st += 0 ; a--; } for (int i = 1; i <= a; i++) { st += 0 ; } if (c) { if (!md.size()) en += 11 ; else en += 1 ; c--; } for (int i = 1; i <= c; i++) { en += 1 ; } if (saveb > 0) cout << 1; cout << st << md << en << n ; } } |
#include <bits/stdc++.h> using namespace std; const long long INF = 2000000000000000000; long double eps = 1e-12; long long t, n, m, a; vector<long long> vec; void Stefan() { cin >> n >> m; long long cur = 1; for (int i = 0; i < n; i++) { cin >> a; vec.push_back(a); } if (n > m) { cout << 0; return; } for (int i = 0; i < n; i++) { for (int j = i + 1; j < n; j++) { cur *= abs(vec[i] - vec[j]); cur %= m; if (!cur) { cout << 0; return; } } } cout << cur; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); t = 1; while (t) { Stefan(); t--; } } |
module VGA_Ctrl ( // Host Side
iRed,
iGreen,
iBlue,
oCurrent_X,
oCurrent_Y,
oAddress,
oRequest,
// VGA Side
oVGA_R,
oVGA_G,
oVGA_B,
oVGA_HS,
oVGA_VS,
oVGA_SYNC,
oVGA_BLANK,
oVGA_CLOCK,
// Control Signal
iCLK,
iRST_N );
// Host Side
input [9:0] iRed;
input [9:0] iGreen;
input [9:0] iBlue;
output [21:0] oAddress;
output [10:0] oCurrent_X;
output [10:0] oCurrent_Y;
output oRequest;
// VGA Side
output [9:0] oVGA_R;
output [9:0] oVGA_G;
output [9:0] oVGA_B;
output reg oVGA_HS;
output reg oVGA_VS;
output oVGA_SYNC;
output oVGA_BLANK;
output oVGA_CLOCK;
// Control Signal
input iCLK;
input iRST_N;
// Internal Registers
reg [10:0] H_Cont;
reg [10:0] V_Cont;
////////////////////////////////////////////////////////////
// Horizontal Parameter
parameter H_FRONT = 16;
parameter H_SYNC = 96;
parameter H_BACK = 48;
parameter H_ACT = 640;
parameter H_BLANK = H_FRONT+H_SYNC+H_BACK;
parameter H_TOTAL = H_FRONT+H_SYNC+H_BACK+H_ACT;
////////////////////////////////////////////////////////////
// Vertical Parameter
parameter V_FRONT = 11;
parameter V_SYNC = 2;
parameter V_BACK = 31;
parameter V_ACT = 480;
parameter V_BLANK = V_FRONT+V_SYNC+V_BACK;
parameter V_TOTAL = V_FRONT+V_SYNC+V_BACK+V_ACT;
////////////////////////////////////////////////////////////
assign oVGA_SYNC = 1'b1; // This pin is unused.
assign oVGA_BLANK = ~((H_Cont<H_BLANK)||(V_Cont<V_BLANK));
assign oVGA_CLOCK = ~iCLK;
assign oVGA_R = iRed;
assign oVGA_G = iGreen;
assign oVGA_B = iBlue;
assign oAddress = oCurrent_Y*H_ACT+oCurrent_X;
assign oRequest = ((H_Cont>=H_BLANK && H_Cont<H_TOTAL) &&
(V_Cont>=V_BLANK && V_Cont<V_TOTAL));
assign oCurrent_X = (H_Cont>=H_BLANK) ? H_Cont-H_BLANK : 11'h0 ;
assign oCurrent_Y = (V_Cont>=V_BLANK) ? V_Cont-V_BLANK : 11'h0 ;
// Horizontal Generator: Refer to the pixel clock
always@(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
H_Cont <= 0;
oVGA_HS <= 1;
end
else
begin
if(H_Cont<H_TOTAL)
H_Cont <= H_Cont+1'b1;
else
H_Cont <= 0;
// Horizontal Sync
if(H_Cont==H_FRONT-1) // Front porch end
oVGA_HS <= 1'b0;
if(H_Cont==H_FRONT+H_SYNC-1) // Sync pulse end
oVGA_HS <= 1'b1;
end
end
// Vertical Generator: Refer to the horizontal sync
always@(posedge oVGA_HS or negedge iRST_N)
begin
if(!iRST_N)
begin
V_Cont <= 0;
oVGA_VS <= 1;
end
else
begin
if(V_Cont<V_TOTAL)
V_Cont <= V_Cont+1'b1;
else
V_Cont <= 0;
// Vertical Sync
if(V_Cont==V_FRONT-1) // Front porch end
oVGA_VS <= 1'b0;
if(V_Cont==V_FRONT+V_SYNC-1) // Sync pulse end
oVGA_VS <= 1'b1;
end
end
endmodule |
`timescale 1ns / 1ps
/***********************************************************************************************************************
* *
* ANTIKERNEL v0.1 *
* *
* Copyright (c) 2012-2017 Andrew D. Zonenberg *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or without modification, are permitted provided that the *
* following conditions are met: *
* *
* * Redistributions of source code must retain the above copyright notice, this list of conditions, and the *
* following disclaimer. *
* *
* * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the *
* following disclaimer in the documentation and/or other materials provided with the distribution. *
* *
* * Neither the name of the author nor the names of any contributors may be used to endorse or promote products *
* derived from this software without specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL *
* THE AUTHORS BE HELD LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES *
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR *
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
* POSSIBILITY OF SUCH DAMAGE. *
* *
***********************************************************************************************************************/
/**
@file
@author Andrew D. Zonenberg
@brief De-bounces a switch using a parameterizable delay
*/
module SwitchDebouncer #(
parameter INIT_VAL = 0
) (
input wire clk,
input wire din,
output reg dout = INIT_VAL,
output reg rising = 0,
output reg falling = 0
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Parameter declarations
parameter DELAY_MAX = 'h1023;
//number of bits in the counter
`include "../../synth_helpers/clog2.vh"
localparam COUNT_BITS = clog2(DELAY_MAX);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Synchronize the input to our clock domain
wire din_sync;
ThreeStageSynchronizer #(
.IN_REG(0)
) sync_in (
.clk_in(clk),
.din(din),
.clk_out(clk),
.dout(din_sync)
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Main state logic
reg[COUNT_BITS-1:0] count = 0;
reg din_last = 0;
reg busy = 0;
wire din_change = (din_last != din_sync);
always @(posedge clk) begin
//Save old state so we can detect changes
din_last <= din_sync;
//Clear single-cycle flags
rising <= 0;
falling <= 0;
//We already saw an edge, wait for more
if(busy) begin
//If we just bounced again, reset the counter - we're not stable yet
if(din_change)
count <= 0;
//Done toggling
else if(count == DELAY_MAX) begin
busy <= 0;
dout <= din_sync;
//Produce edge signals only if we changed state
if(din_sync != dout) begin
rising <= din_sync;
falling <= !din_sync;
end
end
//Nothing special, just bump the counter
else
count <= count + 1'd1;
end
//First edge in a while, start counting
else if(din_change) begin
count <= 1;
busy <= 1;
end
end
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo_mixed_widths
// ============================================================
// File Name: capture_fifo.v
// Megafunction Name(s):
// dcfifo_mixed_widths
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.0.0 Build 595 04/25/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module capture_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdfull,
rdusedw,
wrempty,
wrfull);
input aclr;
input [63:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output rdfull;
output [4:0] rdusedw;
output wrempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [4:0] sub_wire3;
wire sub_wire4;
wire sub_wire5;
wire [31:0] q = sub_wire0[31:0];
wire rdempty = sub_wire1;
wire rdfull = sub_wire2;
wire [4:0] rdusedw = sub_wire3[4:0];
wire wrempty = sub_wire4;
wire wrfull = sub_wire5;
dcfifo_mixed_widths dcfifo_mixed_widths_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.rdfull (sub_wire2),
.rdusedw (sub_wire3),
.wrempty (sub_wire4),
.wrfull (sub_wire5),
.eccstatus (),
.wrusedw ());
defparam
dcfifo_mixed_widths_component.intended_device_family = "Cyclone V",
dcfifo_mixed_widths_component.lpm_numwords = 16,
dcfifo_mixed_widths_component.lpm_showahead = "ON",
dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths",
dcfifo_mixed_widths_component.lpm_width = 64,
dcfifo_mixed_widths_component.lpm_widthu = 4,
dcfifo_mixed_widths_component.lpm_widthu_r = 5,
dcfifo_mixed_widths_component.lpm_width_r = 32,
dcfifo_mixed_widths_component.overflow_checking = "OFF",
dcfifo_mixed_widths_component.rdsync_delaypipe = 4,
dcfifo_mixed_widths_component.read_aclr_synch = "ON",
dcfifo_mixed_widths_component.underflow_checking = "OFF",
dcfifo_mixed_widths_component.use_eab = "ON",
dcfifo_mixed_widths_component.write_aclr_synch = "OFF",
dcfifo_mixed_widths_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "16"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "64"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "1"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "32"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "64"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
// Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "5"
// Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "32"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL "data[63..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdfull 0 0 0 0 OUTPUT NODEFVAL "rdfull"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: rdusedw 0 0 5 0 OUTPUT NODEFVAL "rdusedw[4..0]"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL "wrempty"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 64 0 data 0 0 64 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdfull 0 0 0 0 @rdfull 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 5 0 @rdusedw 0 0 5 0
// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL capture_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL capture_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL capture_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL capture_fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL capture_fifo_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL capture_fifo_bb.v TRUE
|
#include <bits/stdc++.h> using namespace std; const int N = 600010; const int Mod = 998244353; inline int sub(int x, int y) { return (x - y < 0 ? x - y + Mod : x - y); } inline int add(int x, int y) { return (x + y >= Mod ? x + y - Mod : x + y); } int po(int x, int y) { int r = 1; for (; y; y >>= 1, x = (1ll * x * x % Mod)) if (y & 1) r = (1ll * r * x % Mod); return r; } namespace poly { int r[N], a[N], b[N], w[N], iw[N], m, l; void init(int x) { for (m = 1, l = 0; m <= x; m <<= 1, ++l) ; for (int i = 0; i < m; ++i) r[i] = (r[i >> 1] >> 1) | ((i & 1) << (l - 1)); int b = po(3, (Mod - 1) / m), ib = po(b, Mod - 2); w[m / 2] = iw[m / 2] = 1; for (int i = 1; i < m / 2; ++i) w[m / 2 + i] = (1ll * w[m / 2 + i - 1] * b % Mod), iw[m / 2 + i] = (1ll * iw[m / 2 + i - 1] * ib % Mod); for (int i = m / 2 - 1; i; --i) w[i] = w[i << 1], iw[i] = iw[i << 1]; } void ntt(int* a, int f) { for (int i = 0; i < m; ++i) if (i < r[i]) swap(a[i], a[r[i]]); for (int i = 1, id = 1; i < m; i <<= 1, ++id) { for (int j = 0; j < m; j += i << 1) for (int k = 0; k < i; ++k) { int x = a[j + k], y = (1ll * (f == 1 ? w[i + k] : iw[i + k]) * a[i + j + k] % Mod); a[j + k] = add(x, y), a[i + j + k] = sub(x, y); } } if (f == -1) { int in = po(m, Mod - 2); for (int i = 0; i < m; ++i) a[i] = (1ll * a[i] * in % Mod); } } void prod(int* a, int* b, int len) { init(len); ntt(a, 1); ntt(b, 1); for (int i = 0; i < m; ++i) a[i] = (1ll * a[i] * b[i] % Mod); ntt(a, -1); } } // namespace poly using poly::a; using poly::b; using poly::prod; int fac[N], inv[N]; void init() { const int m = 3e5; fac[0] = 1; for (int i = 1; i <= m; ++i) fac[i] = (1ll * fac[i - 1] * i % Mod); inv[m] = po(fac[m], Mod - 2); for (int i = m - 1; i >= 0; i--) inv[i] = (1ll * i + 1 * inv[i + 1] % Mod); } vector<int> ve[N]; priority_queue<pair<int, int> > Q; int cq; struct Edge { int to, next; } edge[N << 1]; int head[N], num; void add_edge(int a, int b) { edge[++num] = (Edge){b, head[a]}; head[a] = num; } void dfs(int x, int f) { int cnt = 0; for (int i = head[x]; i; i = edge[i].next) if (edge[i].to != f) { dfs(edge[i].to, x); ++cnt; } if (cnt) { ++cq; ve[cq].push_back(1); ve[cq].push_back(cnt); Q.push(make_pair(-1, cq)); } } int main() { init(); int n; scanf( %d , &n); for (int i = 1; i < n; ++i) { int x, y; scanf( %d%d , &x, &y); add_edge(x, y); add_edge(y, x); } dfs(1, 0); for (int i = 1; i < cq; ++i) { int t1 = Q.top().second; Q.pop(); int t2 = Q.top().second; Q.pop(); int la = ve[t1].size() - 1, lb = ve[t2].size() - 1; for (int j = 0; j <= la; j++) a[j] = ve[t1][j]; for (int j = 0; j <= lb; j++) b[j] = ve[t2][j]; prod(a, b, la + lb + 2); ve[t1].clear(); for (int j = 0; j <= la + lb; j++) ve[t1].push_back(a[j]); for (int i = 0; i <= poly ::m; i++) a[i] = b[i] = 0; Q.push(make_pair(-la - lb, t1)); } int rt = Q.top().second, len = -Q.top().first; int ans = 0; for (int i = 0; i <= len; ++i) { int tmp = (1ll * ve[rt][i] * fac[n - i] % Mod); ans = (i & 1) ? sub(ans, tmp) : add(ans, tmp); } printf( %d n , ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLYGATE4SD1_BLACKBOX_V
`define SKY130_FD_SC_HDLL__DLYGATE4SD1_BLACKBOX_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__dlygate4sd1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLYGATE4SD1_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; while (cin >> n) { if (n == 1) cout << 8 << endl; else if (!n) cout << 1 << endl; else if (n % 4 == 0) cout << 6 << endl; else if (n % 4 == 1) cout << 8 << endl; else if (n % 4 == 2) cout << 4 << endl; else if (n % 4 == 3) cout << 2 << endl; } } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(), cout.tie(); int n; cin >> n; int temp = 1; int a[] = {4, 7, 44, 47, 74, 77, 444, 447, 474, 477, 744, 747, 774, 777}; for (int i = 0; i < 14; i++) { if (n % a[i] == 0) { cout << YES << endl; temp = 0; break; } } if (temp) { cout << NO << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; pair<int, int> arr[1000005]; int par[1000005], sz[1000005]; int find(int x) { if (par[x] != x) par[x] = find(par[x]); return par[x]; } void Union(int a, int b) { a = find(a); b = find(b); if (a != b) { par[a] = b; sz[b] += sz[a]; sz[a] = 0; } } int ans[1005][1005], n, m; bool vis[1005][1005], add[1000005]; long long k; void dfs(int x, int y) { vis[x][y] = 1; if (!k) return; ans[x][y] = 1; k--; for (int dx = -1; dx <= 1; dx++) { for (int dy = -1; dy <= 1; dy++) { if (abs(dx) + abs(dy) == 1 && x + dx >= 0 && x + dx < n && y + dy >= 0 && y + dy < m && !vis[x + dx][y + dy] && add[(x + dx) * m + y + dy]) dfs(x + dx, y + dy); } } } int main() { scanf( %d%d%I64d , &n, &m, &k); for (int i = 0; i < n * m; i++) { scanf( %d , &arr[i].first); arr[i].second = i; par[i] = i; sz[i] = 1; } sort(arr, arr + n * m); for (int i = n * m - 1; i >= 0; i--) { int idx = arr[i].second; if (idx >= m && add[idx - m]) Union(idx, idx - m); if (idx < (n - 1) * m && add[idx + m]) Union(idx, idx + m); if (idx % m && add[idx - 1]) Union(idx, idx - 1); if (idx % m != m - 1 && add[idx + 1]) Union(idx, idx + 1); if (k % arr[i].first == 0 && sz[find(idx)] >= k / arr[i].first) { k /= arr[i].first; dfs(idx / m, idx % m); printf( YES n ); for (int x = 0; x < n; x++) { for (int j = 0; j < m; j++) printf( %d , ans[x][j] * arr[i].first); printf( n ); } return 0; } add[idx] = 1; } printf( NO ); } |
#include <bits/stdc++.h> using namespace std; int n; int l[305]; int c[305]; map<pair<int, int>, long long int> m; int gcd(int a, int b) { return b == 0 ? a : gcd(b, a % b); } long long int solve(int i, int g) { if (g == 1) return 0; if (i == n) { if (g != 1) return (long long int)1000000000000; return 0; } if (m.count({i, g}) > 0) { return m[make_pair(i, g)]; } long long int x = solve(i + 1, gcd(l[i], g)); if (x != (long long int)1000000000000) x += c[i]; long long int y = solve(i + 1, g); m[make_pair(i, g)] = min(x, y); return m[make_pair(i, g)]; } int main() { scanf( %d , &n); for (int i = 0; i < n; ++i) { scanf( %d , &l[i]); } for (int i = 0; i < n; ++i) { scanf( %d , &c[i]); } m.clear(); long long int x = solve(0, 0); if (x == (long long int)1000000000000) printf( -1 ); else cout << x; } |
#include <bits/stdc++.h> int n, a, b, p; char s[51]; int main(void) { scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d %s , &a, s); b = 0; p = a / 2; for (int j = 0; j < a; j++) { if (s[j] == ( ) { b++; } else { if (b > 0) { b--; p--; } } } printf( %d n , p); } } |
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; int n; int main() { cin >> n; for (int i = 2; i * i <= n; i++) { if (n % i != 0) continue; int m1 = i; for (int z1 = 1; z1 < m1; z1++) { int val = n - 1 - z1 * (n / i); if (val > 0 && val % m1 == 0) { cout << YES << endl << 2 << endl << z1 << << m1 << endl << val / m1 << << n / m1 << endl; return 0; } } } puts( NO ); return 0; } |
/******************************************************************************/
/* Top module of sorting logic Ryohei Kobayashi */
/* 2015-08-01 */
/******************************************************************************/
`default_nettype none
`include "define.vh"
/***** generating a 512-bits data from 128-bits input data from a host PC *****/
/******************************************************************************/
module DATAGEN(input wire CLK,
input wire RST,
input wire dinen,
input wire [`MERGW-1:0] din,
output wire doten,
output wire [`DRAMW-1:0] dot);
reg [1:0] buf_t_cnt; // counter for temporary register
reg data_valid;
reg [`DRAMW-1:0] buf_t;
assign doten = data_valid;
assign dot = buf_t;
always @(posedge CLK) begin
if (dinen) buf_t <= {din, buf_t[`DRAMW-1:`MERGW]};
end
always @(posedge CLK) begin
if (RST) begin
buf_t_cnt <= 0;
end else begin
if (dinen) buf_t_cnt <= buf_t_cnt + 1;
end
end
always @(posedge CLK) data_valid <= (dinen && buf_t_cnt == 3);
endmodule
/******************************************************************************/
module USER_LOGIC #(parameter C_PCI_DATA_WIDTH = 128)
( input wire CLK,
input wire RST,
output wire CHNL_RX_CLK,
(* mark_debug = "true" *) input wire CHNL_RX,
(* mark_debug = "true" *) output wire CHNL_RX_ACK,
(* mark_debug = "true" *) input wire CHNL_RX_LAST,
(* mark_debug = "true" *) input wire [31:0] CHNL_RX_LEN,
(* mark_debug = "true" *) input wire [30:0] CHNL_RX_OFF,
(* mark_debug = "true" *) input wire [C_PCI_DATA_WIDTH-1:0] CHNL_RX_DATA,
(* mark_debug = "true" *) input wire CHNL_RX_DATA_VALID,
(* mark_debug = "true" *) output wire CHNL_RX_DATA_REN,
output wire CHNL_TX_CLK,
(* mark_debug = "true" *) output wire CHNL_TX,
(* mark_debug = "true" *) input wire CHNL_TX_ACK,
(* mark_debug = "true" *) output wire CHNL_TX_LAST,
(* mark_debug = "true" *) output wire [31:0] CHNL_TX_LEN,
(* mark_debug = "true" *) output wire [30:0] CHNL_TX_OFF,
(* mark_debug = "true" *) output wire [C_PCI_DATA_WIDTH-1:0] CHNL_TX_DATA,
(* mark_debug = "true" *) output wire CHNL_TX_DATA_VALID,
(* mark_debug = "true" *) input wire CHNL_TX_DATA_REN,
input wire d_busy, // DRAM busy
output wire [512-1:0] d_din, // DRAM data in
input wire d_w, // DRAM write flag
input wire [512-1:0] d_dout, // DRAM data out
input wire d_douten, // DRAM data out enable
output wire [1:0] d_req, // DRAM REQ access request (read/write)
output wire [31:0] d_initadr, // DRAM REQ initial address for the access
output wire [31:0] d_blocks // DRAM REQ the number of blocks per one access
);
function [`DRAMW-1:0] mux;
input [`DRAMW-1:0] a;
input [`DRAMW-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
function [1:0] mux2;
input [1:0] a;
input [1:0] b;
input sel;
begin
case (sel)
1'b0: mux2 = a;
1'b1: mux2 = b;
endcase
end
endfunction
function [32-1:0] mux32;
input [32-1:0] a;
input [32-1:0] b;
input sel;
begin
case (sel)
1'b0: mux32 = a;
1'b1: mux32 = b;
endcase
end
endfunction
reg [31:0] rLen;
(* mark_debug = "true" *) reg [31:0] rCount;
(* mark_debug = "true" *) reg [1:0] rState;
reg [31:0] tLen;
(* mark_debug = "true" *) reg [31:0] tCount;
(* mark_debug = "true" *) reg [1:0] tState;
wire [`DRAMW-1:0] idata; // initdata
wire idata_valid; // initdata is valid
wire rx_wait; // wait flag for PCIe
wire [C_PCI_DATA_WIDTH-1:0] core_dot; // sorting result
wire core_rdy; // sorting result is ready
DATAGEN datagen(CLK, RST, (CHNL_RX_DATA_REN && CHNL_RX_DATA_VALID), CHNL_RX_DATA, idata_valid, idata);
CORE core(CLK, RST,
d_busy, d_din, d_w, d_dout, d_douten, d_req, d_initadr, d_blocks, // DRAM interface
idata, idata_valid, rx_wait, // Interface for Host -> FPGA
CHNL_TX_DATA_REN, CHNL_TX_DATA_VALID, core_dot, core_rdy // Interface for FPGA -> Host
);
assign CHNL_RX_CLK = CLK;
assign CHNL_RX_ACK = (rState == 2'd1);
assign CHNL_RX_DATA_REN = (rState == 2'd1 && !rx_wait);
assign CHNL_TX_CLK = CLK;
assign CHNL_TX = (tState == 2'd1);
assign CHNL_TX_LAST = 1'd1;
assign CHNL_TX_LEN = tLen; // in words
assign CHNL_TX_OFF = 0;
assign CHNL_TX_DATA = core_dot;
assign CHNL_TX_DATA_VALID = (tState == 2'd1 && core_rdy);
// State machine for Host -> FPGA
always @(posedge CLK) begin
if (RST) begin
rLen <= 0;
rCount <= 0;
rState <= 0;
end else begin
case (rState)
2'd0: begin // Wait for start of RX, save length
if (CHNL_RX) begin
rLen <= CHNL_RX_LEN;
rCount <= 0;
rState <= 2'd1;
end
end
2'd1: begin // Wait for last data in RX, save value
if (CHNL_RX_DATA_REN && CHNL_RX_DATA_VALID) rCount <= rCount + (C_PCI_DATA_WIDTH >> 5);
if (rCount >= rLen) rState <= 2'd0;
end
endcase
end
end
// State machine for FPGA -> Host
always @(posedge CLK) begin
if (RST) begin
tLen <= 0;
tCount <= 0;
tState <= 0;
end else begin
case (tState)
2'd0: begin // Prepare for TX
if (core_rdy) begin
tLen <= rLen;
tCount <= 0;
tState <= 2'd1;
end
end
2'd1: begin // Start TX with save length and data value
if (CHNL_TX_DATA_REN && CHNL_TX_DATA_VALID) tCount <= tCount + (C_PCI_DATA_WIDTH >> 5);
if (tCount >= tLen) tState <= 2'd0;
end
endcase
end
end
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; const int mxn = 2e5 + 5; int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); ; int tc; cin >> tc; while (tc--) { string s; cin >> s; int a = 0, b = 0, c = 0; for (int i = 0; i < s.size(); i++) { if (s[i] == A ) a++; else if (s[i] == B ) b++; else c++; } if (a + c == b) cout << YES n ; else cout << NO n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); if (n % 3 == 0 || n % 3 == 1) { cout << 1 << << 1 << << n - 2; } else { cout << 1 << << 2 << << n - 3; } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Samuel A. Falvo II
//
// Create Date: 19:59:06 10/30/2011
// Design Name: UXA 1A
// Module Name: M_uxa_ps2
// Project Name: Kestrel-2
// Target Devices: Nexys2
// Tool versions:
// Description:
// This top-level module encapsulates one entire PS/2
// interface adapter. Instantiate one of these in your
// design, plus all dependent sub-modules, and you will
// have a PS/2 interface adapter with a 16-byte FIFO.
//
// Dependencies:
// M_uxa_ps2_busctl
// M_uxa_ps2_fifo
// M_uxa_ps2_wrtlgc
// M_uxa_ps2_shfreg
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module M_uxa_ps2(
// PS/2 port I/O ports
output ps2_c_oe_o,
output ps2_d_oe_o,
input ps2_d_i,
input ps2_c_i,
// Wishbone bus interface
input sys_clk_i,
input sys_reset_i,
output io_ack_o,
input io_stb_i,
input io_we_i,
input [9:8] io_dat_i,
output [15:0] io_dat_o
);
wire bc_rp_inc_o;
wire wl_we_o;
wire wl_ptr_inc_o;
wire wl_reset_o;
wire [7:0] sr_d_o;
wire sr_frame_o;
wire sr_reset_i = (sys_reset_i | wl_reset_o);
M_uxa_ps2_busctl busctl (
.sys_clk_i(sys_clk_i),
.sys_reset_i(sys_reset_i),
.wb_we_i(io_we_i),
.wb_stb_i(io_stb_i),
.wb_dat_8_i(io_dat_i[8]),
.wb_dat_9_i(io_dat_i[9]),
.wb_ack_o(io_ack_o),
.rp_inc_o(bc_rp_inc_o),
.c_oe_o(ps2_c_oe_o),
.d_oe_o(ps2_d_oe_o)
);
M_uxa_ps2_shfreg shfreg (
.ps2_d_i(ps2_d_i),
.ps2_c_i(ps2_c_i),
.d_o(sr_d_o),
.frame_o(sr_frame_o),
.reset_i(sr_reset_i),
.sys_clk_i(sys_clk_i)
);
M_uxa_ps2_wrtlgc wrtlgc (
.frame_i(sr_frame_o),
.reset_o(wl_reset_o),
.we_o(wl_we_o),
.ptr_inc_o(wl_ptr_inc_o),
.sys_clk_i(sys_clk_i),
.sys_reset_i(sys_reset_i)
);
M_uxa_ps2_fifo fifo (
.d_i(sr_d_o),
.we_i(wl_we_o),
.wp_inc_i(wl_ptr_inc_o),
.q_o(io_dat_o[7:0]),
.rp_inc_i(bc_rp_inc_o),
.full_o(io_dat_o[14]),
.data_available_o(io_dat_o[15]),
.sys_clk_i(sys_clk_i),
.sys_reset_i(sys_reset_i)
);
reg [3:0] zeros;
assign io_dat_o[13:10] = zeros;
assign io_dat_o[9] = ps2_c_i;
assign io_dat_o[8] = ps2_d_i;
initial begin
zeros <= 4'b0000;
end
endmodule
|
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