name string | code string | asm string | file string |
|---|---|---|---|
llvm::BPFPreserveStaticOffsetPass::reconstructLoad(llvm::CallInst*) | std::pair<GetElementPtrInst *, LoadInst *>
BPFPreserveStaticOffsetPass::reconstructLoad(CallInst *Call) {
GetElementPtrInst *GEP = reconstructGEP(Call, 0);
Type *ReturnType = Call->getFunctionType()->getReturnType();
auto *Load = new LoadInst(ReturnType, GEP, "",
/* These would be set ... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x58, %rsp
movq %rdi, %r14
xorl %esi, %esi
callq 0xe4f871
movq %rax, %rbx
movq 0x50(%r14), %rax
movq 0x10(%rax), %rax
movq (%rax), %r12
movl $0x50, %edi
movl $0x1, %esi
callq 0x1a8f59c
movq %rax, %r15
leaq 0x30(%rsp), %rcx
movw $0x101, 0x20(%rcx) # imm = 0x101
xorp... | /Target/BPF/BPFPreserveStaticOffset.cpp |
void llvm::cl::apply<llvm::cl::opt<bool, false, llvm::cl::parser<bool>>, char [14], llvm::cl::OptionHidden, llvm::cl::initializer<bool>, llvm::cl::desc>(llvm::cl::opt<bool, false, llvm::cl::parser<bool>>*, char const (&) [14], llvm::cl::OptionHidden const&, llvm::cl::initializer<bool> const&, llvm::cl::desc const&) | void apply(Opt *O, const Mod &M, const Mods &... Ms) {
applicator<Mod>::opt(M, *O);
apply(O, Ms...);
} | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %r8, %rbx
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %r14
movq %rsi, %rdi
callq 0x7512e0
movq %r14, %rdi
movq %r13, %rsi
movq %rax, %rdx
callq 0x1c90c20
movl (%r12), %eax
movzwl 0xa(%r14), %ecx
shll $0x5, %eax
andl $0x60, %eax
andl $-0x61, %ecx... | /llvm/Support/CommandLine.h |
llvm::BPFTargetLowering::isZExtFree(llvm::Type*, llvm::Type*) const | bool BPFTargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
if (!getHasAlu32() || !Ty1->isIntegerTy() || !Ty2->isIntegerTy())
return false;
unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
return NumBits1 == 32 && NumBits2 == 64;
} | cmpb $0x1, 0x4e0f3(%rdi)
jne 0xe57424
cmpb $0xd, 0x8(%rsi)
jne 0xe57424
pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rdx, %rbx
cmpb $0xd, 0x8(%rdx)
jne 0xe57427
movq %rsi, %rdi
callq 0x1a89c4e
movq %rsp, %r14
movq %rax, (%r14)
movb %dl, 0x8(%r14)
movq %r14, %rdi
callq 0x1cceb6c
movq %rax, %r15
movq %rbx, %rd... | /Target/BPF/BPFISelLowering.cpp |
llvm::BPFTargetLowering::LowerOperation(llvm::SDValue, llvm::SelectionDAG&) const | unsigned getOpcode() const { return (unsigned)NodeType; } | movl 0x18(%rsi), %eax
cmpl $0x3c, %eax
jle 0xe5787b
cmpl $0x122, %eax # imm = 0x122
jg 0xe578d6
cmpl $0x3d, %eax
je 0xe57d02
cmpl $0xce, %eax
je 0xe57b46
jmp 0xe57892
cmpl $0xd, %eax
je 0xe57ae8
cmpl $0x11, %eax
je 0xe578ed
cmpl $0x3b, %eax
je 0xe57d02
pushq %rbx
subq $0x80, %rsp
leaq 0x29ade9e(%rip), %rcx ... | /llvm/CodeGen/SelectionDAGNodes.h |
llvm::BPFTargetLowering::LowerSDIVSREM(llvm::SDValue, llvm::SelectionDAG&) const | SDValue BPFTargetLowering::LowerSDIVSREM(SDValue Op, SelectionDAG &DAG) const {
SDLoc DL(Op);
fail(DL, DAG,
"unsupported signed division, please convert to unsigned div/mod.");
return DAG.getUNDEF(Op->getValueType(0));
} | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
subq $0x38, %rsp
movq %rcx, %rbx
movq %rsi, %r14
movq 0x48(%rsi), %rsi
movq %rsi, (%rsp)
testq %rsi, %rsi
je 0xe57d2c
movq %rsp, %rdi
movl $0x1, %edx
callq 0x1a648a8
movl 0x44(%r14), %eax
movq %rsp, %r15
movl %eax, 0x8(%r15)
leaq 0x29adba8(%rip), %rax # 0x38058e6
leaq 0x10(... | /Target/BPF/BPFISelLowering.cpp |
llvm::BPFTargetLowering::EmitSubregExt(llvm::MachineInstr&, llvm::MachineBasicBlock*, unsigned int, bool) const | unsigned
BPFTargetLowering::EmitSubregExt(MachineInstr &MI, MachineBasicBlock *BB,
unsigned Reg, bool isSigned) const {
const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
const TargetRegisterClass *RC = getRegClassFor(MVT::i64);
int RShiftOp = isSigned ?... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x88, %rsp
movl %r8d, 0x54(%rsp)
movl %ecx, 0x4(%rsp)
movq %rdx, %rbx
movq %rsi, %r15
movq %rdi, %r13
movq 0x20(%rdx), %rax
movq 0x10(%rax), %rdi
movq (%rdi), %rax
callq *0x80(%rax)
movq %rax, %rbp
movq (%r13), %rax
movq %r13, %rdi
movl $0x8, %esi
... | /Target/BPF/BPFISelLowering.cpp |
llvm::BPFTargetLowering::EmitInstrWithCustomInserterMemcpy(llvm::MachineInstr&, llvm::MachineBasicBlock*) const | MachineBasicBlock *
BPFTargetLowering::EmitInstrWithCustomInserterMemcpy(MachineInstr &MI,
MachineBasicBlock *BB)
const {
MachineFunction *MF = MI.getParent()->getParent();
MachineRegisterInfo &MRI = MF->getReg... | pushq %r15
pushq %r14
pushq %rbx
subq $0x20, %rsp
movq %rdx, %rbx
movq %rsi, %r14
movq 0x18(%rsi), %rax
movq 0x20(%rax), %r15
movq 0x28(%r15), %rdi
leaq 0x48d455a(%rip), %rsi # 0x572e288
leaq 0x30b9703(%rip), %rdx # 0x3f13438
xorl %ecx, %ecx
callq 0x17da89a
movq %rsp, %rdx
movq $0x0, 0x8(%rdx)
movl $0x45000000, (%r... | /Target/BPF/BPFISelLowering.cpp |
llvm::BPFTargetLowering::isLegalAddressingMode(llvm::DataLayout const&, llvm::TargetLoweringBase::AddrMode const&, llvm::Type*, unsigned int, llvm::Instruction*) const | bool BPFTargetLowering::isLegalAddressingMode(const DataLayout &DL,
const AddrMode &AM, Type *Ty,
unsigned AS,
Instruction *I) const {
// No global is ever allowed as a base.
if ... | cmpq $0x0, (%rdx)
je 0xe5a753
xorl %eax, %eax
retq
movq 0x18(%rdx), %rax
testq %rax, %rax
je 0xe5a768
cmpq $0x1, %rax
jne 0xe5a750
cmpb $0x0, 0x10(%rdx)
jne 0xe5a750
movb $0x1, %al
retq
nop
| /Target/BPF/BPFISelLowering.cpp |
llvm::HexagonAsmPrinter::printOperand(llvm::MachineInstr const*, unsigned int, llvm::raw_ostream&) | void HexagonAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
raw_ostream &O) {
const MachineOperand &MO = MI->getOperand(OpNo);
switch (MO.getType()) {
default:
llvm_unreachable ("<unknown operand type>");
case MachineOperand::MO_Register:
O << Hexago... | pushq %r14
pushq %rbx
pushq %rax
movq %rcx, %rbx
movq %rdi, %r14
movq 0x20(%rsi), %rax
movl %edx, %ecx
shlq $0x5, %rcx
leaq (%rax,%rcx), %rsi
movzbl (%rax,%rcx), %eax
leaq 0x29ab089(%rip), %rcx # 0x3805a54
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
movl 0x4(%rsi), %edi
callq 0x15e96c4
movq %rbx, %rdi
movq ... | /Target/Hexagon/HexagonAsmPrinter.cpp |
llvm::HexagonAsmPrinter::PrintAsmMemoryOperand(llvm::MachineInstr const*, unsigned int, char const*, llvm::raw_ostream&) | bool HexagonAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
unsigned OpNo,
const char *ExtraCode,
raw_ostream &O) {
if (ExtraCode && ExtraCode[0])
return true; // Unk... | pushq %r15
pushq %r14
pushq %rbx
movq %r8, %rbx
testq %rcx, %rcx
je 0xe5aba0
movb $0x1, %al
cmpb $0x0, (%rcx)
jne 0xe5abe1
movq 0x20(%rsi), %r14
leal 0x1(%rdx), %r15d
shlq $0x5, %r15
movq %rbx, %rcx
callq 0xe5a9a8
cmpq $0x0, 0x10(%r14,%r15)
je 0xe5abdf
addq %r15, %r14
leaq 0x38664b8(%rip), %rsi # 0x46c107e
movl $0x2,... | /Target/Hexagon/HexagonAsmPrinter.cpp |
llvm::Automaton<unsigned long>::Automaton<(anonymous namespace)::HexagonTransition>(llvm::ArrayRef<(anonymous namespace)::HexagonTransition>, llvm::ArrayRef<llvm::NfaStatePair>) | Automaton(ArrayRef<InfoT> Transitions,
ArrayRef<NfaStatePair> TranscriptionTable = {}) {
if (!TranscriptionTable.empty())
Transcriber =
std::make_shared<internal::NfaTranscriber>(TranscriptionTable);
Transcribe = Transcriber != nullptr;
M = std::make_shared<MapTy>();
for (con... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %rsi, %r14
movq %rdi, %rbx
xorps %xmm0, %xmm0
movups %xmm0, 0x4a4c61c(%rip) # 0x58a8a70
movups %xmm0, 0x4a4c605(%rip) # 0x58a8a60
movq $0x1, 0x4a4c61a(%rip) # 0x58a8a80
movabsq $0x100000001, %rbp # imm = 0x100000001
testq %rc... | /llvm/Support/Automaton.h |
llvm::HexagonInstrInfo::hasStoreToStackSlot(llvm::MachineInstr const&, llvm::SmallVectorImpl<llvm::MachineMemOperand const*>&) const | bool HexagonInstrInfo::hasStoreToStackSlot(
const MachineInstr &MI,
SmallVectorImpl<const MachineMemOperand *> &Accesses) const {
if (MI.isBundle()) {
const MachineBasicBlock *MBB = MI.getParent();
MachineBasicBlock::const_instr_iterator MII = MI.getIterator();
for (++MII; MII != MBB->instr_end() ... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
cmpw $0x14, 0x44(%rsi)
jne 0xe5cfb2
movq 0x18(%r14), %r12
addq $0x30, %r12
movq 0x8(%r14), %r14
cmpq %r12, %r14
je 0xe5cfcb
testb $0x4, 0x2c(%r14)
je 0xe5cfcb
movq %r15, %rdi
movq %r14, %rsi
movq %rbx, %rdx
callq 0x18... | /Target/Hexagon/HexagonInstrInfo.cpp |
llvm::HexagonInstrInfo::removeBranch(llvm::MachineBasicBlock&, int*) const | unsigned HexagonInstrInfo::removeBranch(MachineBasicBlock &MBB,
int *BytesRemoved) const {
assert(!BytesRemoved && "code size not handled");
LLVM_DEBUG(dbgs() << "\nRemoving branches out of " << printMBBReference(MBB));
MachineBasicBlock::iterator I = MBB.end();
unsigned... | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x10, %rsp
movq %rsi, %rbx
leaq 0x30(%rsi), %r12
movq %rsp, %r14
movq %r12, (%r14)
xorl %ebp, %ebp
leaq 0x8(%rsp), %r15
movq (%rsp), %rax
cmpq 0x38(%rbx), %rax
je 0xe5d60d
movq %r14, %rdi
callq 0x911492
movq (%rsp), %rdi
movl 0x44(%rdi), %eax
addl $-0xd, %eax... | /Target/Hexagon/HexagonInstrInfo.cpp |
llvm::HexagonInstrInfo::isProfitableToIfCvt(llvm::MachineBasicBlock&, unsigned int, unsigned int, llvm::MachineBasicBlock&, unsigned int, unsigned int, llvm::BranchProbability) const | NodeBase *getNext() const { return Next; } | movq 0x38(%rsi), %rax
addq $0x30, %rsi
cmpq %rsi, %rax
je 0xe5e198
xorl %ecx, %ecx
movl 0x44(%rax), %edx
addl $-0x12, %edx
cmpw $-0x5, %dx
adcl $0x0, %ecx
movq 0x8(%rax), %rax
cmpq %rsi, %rax
jne 0xe5e17d
cmpl $0x3, %ecx
ja 0xe5e1c4
movq 0x38(%r8), %rax
addq $0x30, %r8
cmpq %r8, %rax
je 0xe5e1c7
xorl %ecx, %ecx
movl 0x... | /llvm/ADT/ilist_node_base.h |
llvm::HexagonInstrInfo::loadRegFromStackSlot(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::Register, int, llvm::TargetRegisterClass const*, llvm::TargetRegisterInfo const*, llvm::Register) const | void HexagonInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
Register DestReg, int FI,
const TargetRegisterClass *RC,
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xe8, %rsp
movq %r9, %rbx
movl %r8d, %r12d
movl %ecx, 0x30(%rsp)
movq %rsi, %r14
movq %rdi, 0x58(%rsp)
leaq 0x38(%rsp), %rdi
movq %rdx, 0x68(%rsp)
callq 0x1753b92
movq %r14, 0x60(%rsp)
movq 0x20(%r14), %r14
movq 0x38(%r14), %rbp
xorl %r15d, %r15d
l... | /Target/Hexagon/HexagonInstrInfo.cpp |
llvm::HexagonInstrInfo::insertNoop(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>) const | void HexagonInstrInfo::insertNoop(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const {
DebugLoc DL;
BuildMI(MBB, MI, DL, get(Hexagon::A2_nop));
} | pushq %rbx
subq $0x30, %rsp
xorl %eax, %eax
movq %rax, 0x8(%rsp)
movq %rax, (%rsp)
xorps %xmm0, %xmm0
leaq 0x10(%rsp), %rbx
movaps %xmm0, (%rbx)
movq %rax, 0x10(%rbx)
movq $-0x7620, %rcx # imm = 0x89E0
addq 0x8(%rdi), %rcx
movq %rsi, %rdi
movq %rdx, %rsi
movq %rbx, %rdx
callq 0x911582
movq (%rbx), %rsi
testq %... | /Target/Hexagon/HexagonInstrInfo.cpp |
llvm::HexagonInstrInfo::getPredReg(llvm::ArrayRef<llvm::MachineOperand>, llvm::Register&, unsigned int&, unsigned int&) const | bool empty() const { return Length == 0; } | testq %rdx, %rdx
je 0xe648d6
movl 0x10(%rsi), %eax
movq 0x8(%rdi), %rdx
movq %rax, %rdi
shlq $0x5, %rdi
negq %rdi
movq 0x18(%rdx,%rdi), %rdi
btl $0xe, %edi
jae 0xe648d0
negq %rax
shlq $0x5, %rax
andl 0x10(%rdx,%rax), %edi
btl $0xa, %edi
jb 0xe648d6
cmpb $0x4, 0x20(%rsi)
jne 0xe648d9
xorl %eax, %eax
retq
movl 0x24(%rsi)... | /llvm/ADT/ArrayRef.h |
llvm::HexagonInstrInfo::isNewValueInst(llvm::MachineInstr const&) const | bool HexagonInstrInfo::isNewValueInst(const MachineInstr &MI) const {
return isNewValueJump(MI) || isNewValueStore(MI);
} | pushq %rbx
movq %rsi, %rbx
movq 0x10(%rsi), %rax
testb $0x40, 0x19(%rax)
je 0xe65498
movq %rbx, %rdi
movl $0xa, %esi
movl $0x1, %edx
callq 0x8dd368
movl %eax, %ecx
movb $0x1, %al
testb %cl, %cl
jne 0xe654a4
movq 0x10(%rbx), %rax
movb 0x1a(%rax), %al
andb $0x10, %al
shrb $0x4, %al
popq %rbx
retq
| /Target/Hexagon/HexagonInstrInfo.cpp |
llvm::HexagonInstrInfo::isTailCall(llvm::MachineInstr const&) const | bool HexagonInstrInfo::isTailCall(const MachineInstr &MI) const {
if (!MI.isBranch())
return false;
for (auto &Op : MI.operands())
if (Op.isGlobal() || Op.isSymbol())
return true;
return false;
} | pushq %rbx
movq %rsi, %rbx
movq %rsi, %rdi
movl $0xa, %esi
movl $0x1, %edx
callq 0x8dd368
testb %al, %al
je 0xe66589
movzwl 0x28(%rbx), %eax
movzbl 0x2a(%rbx), %ecx
shll $0x10, %ecx
orq %rax, %rcx
testq %rcx, %rcx
setne %al
je 0xe6658b
movq 0x20(%rbx), %rdx
movzbl (%rdx), %esi
addl $-0x9, %esi
cmpl $0x2, %esi
jb 0xe665... | /Target/Hexagon/HexagonInstrInfo.cpp |
llvm::HexagonInstrInfo::getBaseAndOffset(llvm::MachineInstr const&, long&, llvm::LocationSize&) const | MachineOperand *
HexagonInstrInfo::getBaseAndOffset(const MachineInstr &MI, int64_t &Offset,
LocationSize &AccessSize) const {
// Return if it is not a base+offset type instruction or a MemOp.
if (getAddrMode(MI) != HexagonII::BaseImmOffset &&
getAddrMode(MI) != HexagonII::B... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rcx, %r12
movq %rdx, %r14
movq %rsi, %rbx
movq %rdi, %r15
movq 0x10(%rsi), %rax
movq 0x18(%rax), %rax
shrq $0x28, %rax
andl $0x7, %eax
addl $-0x3, %eax
cmpl $0x2, %eax
jb 0xe66c9c
movq %rbx, %rsi
callq 0xe65124
testb %al, %al
jne 0xe66c9c
movq (%r15), %rax
mo... | /Target/Hexagon/HexagonInstrInfo.cpp |
void llvm::cl::apply<llvm::cl::opt<bool, false, llvm::cl::parser<bool>>, char [15], llvm::cl::initializer<bool>, llvm::cl::OptionHidden, llvm::cl::desc>(llvm::cl::opt<bool, false, llvm::cl::parser<bool>>*, char const (&) [15], llvm::cl::initializer<bool> const&, llvm::cl::OptionHidden const&, llvm::cl::desc const&) | void apply(Opt *O, const Mod &M, const Mods &... Ms) {
applicator<Mod>::opt(M, *O);
apply(O, Ms...);
} | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %r8, %rbx
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %r14
movq %rsi, %rdi
callq 0x7512e0
movq %r14, %rdi
movq %r13, %rsi
movq %rax, %rdx
callq 0x1c90c20
movq (%r12), %rax
movb (%rax), %cl
movb %cl, 0x80(%r14)
movb $0x1, 0x91(%r14)
movb (%rax), ... | /llvm/Support/CommandLine.h |
llvm::HexagonRegisterInfo::eliminateFrameIndex(llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, int, unsigned int, llvm::RegScavenger*) const | bool HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, unsigned FIOp,
RegScavenger *RS) const {
static unsigned ReuseCount = 0;
//
// Hexagon_TODO: Do we need to enforce this for Hexagon?
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x188, %rsp # imm = 0x188
movl %ecx, %r15d
movq %rsi, %rbx
movq %rdi, 0x38(%rsp)
movq 0x18(%rsi), %rax
movq %rax, 0x48(%rsp)
movq 0x20(%rax), %r13
movq 0x10(%r13), %r14
movq (%r14), %rax
movq %r14, %rdi
callq *0x80(%rax)
movq %rax, 0x30(... | /Target/Hexagon/HexagonRegisterInfo.cpp |
bool llvm::any_of<llvm::LiveInterval&, llvm::HexagonRegisterInfo::shouldCoalesce(llvm::MachineInstr*, llvm::TargetRegisterClass const*, unsigned int, llvm::TargetRegisterClass const*, unsigned int, llvm::TargetRegisterClass const*, llvm::LiveIntervals&) const::$_0>(llvm::LiveInterval&, llvm::HexagonRegisterInfo::should... | Callable() = default; | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq (%rdi), %rbx
movl 0x8(%rdi), %r12d
leaq (%r12,%r12,2), %rax
leaq (%rbx,%rax,8), %r15
cmpq $0x4, %r12
jae 0xe6979e
movq %r15, %rcx
subq %rbx, %rcx
sarq $0x3, %rcx
movabsq $-0x5555555555555555, %rax # imm = 0xAAAAAAAAAAAAAAAB
imulq %rcx, %rax
cmpq $0x1, %rax
je ... | /llvm/ADT/STLExtras.h |
llvm::cl::opt<bool, false, llvm::cl::parser<bool>>::opt<char [19], llvm::cl::OptionHidden, llvm::cl::initializer<bool>>(char const (&) [19], llvm::cl::OptionHidden const&, llvm::cl::initializer<bool> const&) | explicit opt(const Mods &... Ms)
: Option(llvm::cl::Optional, NotHidden), Parser(*this) {
apply(this, Ms...);
done();
} | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
movq %rcx, %r14
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %rbx
xorl %ebp, %ebp
xorl %esi, %esi
xorl %edx, %edx
callq 0x7c77e2
movb %bpl, 0x80(%rbx)
xorps %xmm0, %xmm0
movups %xmm0, 0x88(%rbx)
movb %bpl, 0x91(%rbx)
leaq 0x487930c(%rip), %rax # 0x56e32b0
movq %rax... | /llvm/Support/CommandLine.h |
llvm::Hexagon::getCpu(llvm::StringRef) | inline std::optional<Hexagon::ArchEnum> getCpu(StringRef CPU) {
return StringSwitch<std::optional<Hexagon::ArchEnum>>(CPU)
.Case("generic", Hexagon::ArchEnum::V5)
.Case("hexagonv5", Hexagon::ArchEnum::V5)
.Case("hexagonv55", Hexagon::ArchEnum::V55)
.Case("hexagonv60", Hexagon::ArchEnum::V60)
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
movq %rsi, %rbx
movq %rdi, %r14
cmpq $0x7, %rsi
jne 0xe6a779
leaq 0x3561255(%rip), %rsi # 0x43cb9bb
movq %r14, %rdi
movq %rbx, %rdx
callq 0x751d10
testl %eax, %eax
sete %bpl
jmp 0xe6a77b
xorl %ebp, %ebp
cmpq $0x9, %rbx
setne %al
orb %bpl, %al
jne 0xe6a7a7
leaq 0x... | /Target/Hexagon/HexagonDepArch.h |
void llvm::cl::apply<llvm::cl::opt<bool, false, llvm::cl::parser<bool>>, char [19], llvm::cl::OptionHidden, llvm::cl::initializer<bool>>(llvm::cl::opt<bool, false, llvm::cl::parser<bool>>*, char const (&) [19], llvm::cl::OptionHidden const&, llvm::cl::initializer<bool> const&) | void apply(Opt *O, const Mod &M, const Mods &... Ms) {
applicator<Mod>::opt(M, *O);
apply(O, Ms...);
} | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rcx, %rbx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
movq %rsi, %rdi
callq 0x7512e0
movq %r12, %rdi
movq %r15, %rsi
movq %rax, %rdx
callq 0x1c90c20
movl (%r14), %eax
movzwl 0xa(%r12), %ecx
shll $0x5, %eax
andl $0x60, %eax
andl $-0x61, %ecx
orl %eax, %ecx... | /llvm/Support/CommandLine.h |
llvm::cl::opt<bool, false, llvm::cl::parser<bool>>::opt<char [19], llvm::cl::initializer<bool>, llvm::cl::OptionHidden, llvm::cl::NumOccurrencesFlag, llvm::cl::desc>(char const (&) [19], llvm::cl::initializer<bool> const&, llvm::cl::OptionHidden const&, llvm::cl::NumOccurrencesFlag const&, llvm::cl::desc const&) | explicit opt(const Mods &... Ms)
: Option(llvm::cl::Optional, NotHidden), Parser(*this) {
apply(this, Ms...);
done();
} | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %r9, (%rsp)
movq %r8, %r15
movq %rcx, %r12
movq %rdx, %r13
movq %rsi, %rbp
movq %rdi, %r14
xorl %ebx, %ebx
xorl %esi, %esi
xorl %edx, %edx
callq 0x7c77e2
movb %bl, 0x80(%r14)
xorps %xmm0, %xmm0
movups %xmm0, 0x88(%r14)
movb %bl, 0x91(%r14... | /llvm/Support/CommandLine.h |
(anonymous namespace)::HexagonPassConfig::addIRPasses() | void HexagonPassConfig::addIRPasses() {
TargetPassConfig::addIRPasses();
bool NoOpt = (getOptLevel() == CodeGenOptLevel::None);
if (!NoOpt) {
if (EnableInstSimplify)
addPass(createInstSimplifyLegacyPass());
addPass(createDeadCodeEliminationPass());
}
addPass(createAtomicExpandLegacyPass());
... | pushq %r14
pushq %rbx
subq $0x58, %rsp
movq %rdi, %rbx
callq 0x18cda3a
movq %rbx, %rdi
callq 0x18cd11e
testl %eax, %eax
je 0xe6f00c
cmpb $0x1, 0x4a3bf96(%rip) # 0x58aae88
jne 0xe6ef04
callq 0x24ae0fe
movq %rbx, %rdi
movq %rax, %rsi
callq 0x18cd594
callq 0x24693e1
movq %rbx, %rdi
movq %rax, %rsi
callq 0x18cd594
callq ... | /Target/Hexagon/HexagonTargetMachine.cpp |
(anonymous namespace)::HexagonPassConfig::addInstSelector() | bool HexagonPassConfig::addInstSelector() {
HexagonTargetMachine &TM = getHexagonTargetMachine();
bool NoOpt = (getOptLevel() == CodeGenOptLevel::None);
if (!NoOpt)
addPass(createHexagonOptimizeSZextends());
addPass(createHexagonISelDag(TM, getOptLevel()));
if (!NoOpt) {
if (EnableVExtractOpt)
... | pushq %r14
pushq %rbx
pushq %rax
movq %rdi, %rbx
movq 0x70(%rdi), %r14
callq 0x18cd11e
testl %eax, %eax
je 0xe6f14a
callq 0xf26462
movq %rbx, %rdi
movq %rax, %rsi
callq 0x18cd594
movq %rbx, %rdi
callq 0x18cd11e
movq %r14, %rdi
movl %eax, %esi
callq 0xedffd4
movq %rbx, %rdi
movq %rax, %rsi
callq 0x18cd594
cmpb $0x1, 0x4... | /Target/Hexagon/HexagonTargetMachine.cpp |
void llvm::cl::apply<llvm::cl::opt<unsigned int, false, llvm::cl::parser<unsigned int>>, char [13], llvm::cl::OptionHidden, llvm::cl::initializer<int>, llvm::cl::desc>(llvm::cl::opt<unsigned int, false, llvm::cl::parser<unsigned int>>*, char const (&) [13], llvm::cl::OptionHidden const&, llvm::cl::initializer<int> cons... | void apply(Opt *O, const Mod &M, const Mods &... Ms) {
applicator<Mod>::opt(M, *O);
apply(O, Ms...);
} | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %r8, %rbx
movq %rcx, %r14
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %r13
movq %rsi, %rdi
callq 0x7512e0
movq %r13, %rdi
movq %r12, %rsi
movq %rax, %rdx
callq 0x1c90c20
movl (%r15), %eax
movzwl 0xa(%r13), %ecx
shll $0x5, %eax
andl $0x60, %eax
andl $-0x61, %ecx... | /llvm/Support/CommandLine.h |
void llvm::cl::apply<llvm::cl::opt<bool, false, llvm::cl::parser<bool>>, char [12], llvm::cl::OptionHidden, llvm::cl::desc>(llvm::cl::opt<bool, false, llvm::cl::parser<bool>>*, char const (&) [12], llvm::cl::OptionHidden const&, llvm::cl::desc const&) | void apply(Opt *O, const Mod &M, const Mods &... Ms) {
applicator<Mod>::opt(M, *O);
apply(O, Ms...);
} | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rcx, %rbx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
movq %rsi, %rdi
callq 0x7512e0
movq %r12, %rdi
movq %r15, %rsi
movq %rax, %rdx
callq 0x1c90c20
movl (%r14), %eax
movzwl 0xa(%r12), %ecx
shll $0x5, %eax
andl $0x60, %eax
andl $-0x61, %ecx
orl %eax, %ecx... | /llvm/Support/CommandLine.h |
void llvm::cl::apply<llvm::cl::opt<bool, false, llvm::cl::parser<bool>>, char [13], llvm::cl::initializer<bool>, llvm::cl::OptionHidden, llvm::cl::desc>(llvm::cl::opt<bool, false, llvm::cl::parser<bool>>*, char const (&) [13], llvm::cl::initializer<bool> const&, llvm::cl::OptionHidden const&, llvm::cl::desc const&) | void apply(Opt *O, const Mod &M, const Mods &... Ms) {
applicator<Mod>::opt(M, *O);
apply(O, Ms...);
} | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %r8, %rbx
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %r14
movq %rsi, %rdi
callq 0x7512e0
movq %r14, %rdi
movq %r13, %rsi
movq %rax, %rdx
callq 0x1c90c20
movq (%r12), %rax
movb (%rax), %cl
movb %cl, 0x80(%r14)
movb $0x1, 0x91(%r14)
movb (%rax), ... | /llvm/Support/CommandLine.h |
void llvm::cl::apply<llvm::cl::opt<bool, false, llvm::cl::parser<bool>>, char [21], llvm::cl::initializer<bool>, llvm::cl::OptionHidden, llvm::cl::desc>(llvm::cl::opt<bool, false, llvm::cl::parser<bool>>*, char const (&) [21], llvm::cl::initializer<bool> const&, llvm::cl::OptionHidden const&, llvm::cl::desc const&) | void apply(Opt *O, const Mod &M, const Mods &... Ms) {
applicator<Mod>::opt(M, *O);
apply(O, Ms...);
} | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %r8, %rbx
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %r14
movq %rsi, %rdi
callq 0x7512e0
movq %r14, %rdi
movq %r13, %rsi
movq %rax, %rdx
callq 0x1c90c20
movq (%r12), %rax
movb (%rax), %cl
movb %cl, 0x80(%r14)
movb $0x1, 0x91(%r14)
movb (%rax), ... | /llvm/Support/CommandLine.h |
void llvm::StringMapEntry<std::unique_ptr<llvm::HexagonSubtarget, std::default_delete<llvm::HexagonSubtarget>>>::Destroy<llvm::MallocAllocator>(llvm::MallocAllocator&) | void Destroy(AllocatorTy &allocator) {
// Free memory referenced by the item.
size_t AllocSize = sizeof(StringMapEntry) + this->getKeyLength() + 1;
this->~StringMapEntry();
allocator.Deallocate(static_cast<void *>(this), AllocSize,
alignof(StringMapEntry));
} | pushq %r14
pushq %rbx
pushq %rax
movq %rdi, %rbx
movq (%rdi), %r14
movq 0x8(%rdi), %rdi
testq %rdi, %rdi
je 0xe6fa75
movq (%rdi), %rax
callq *0x8(%rax)
addq $0x11, %r14
movq $0x0, 0x8(%rbx)
movl $0x8, %edx
movq %rbx, %rdi
movq %r14, %rsi
addq $0x8, %rsp
popq %rbx
popq %r14
jmp 0x1cac6c2
| /llvm/ADT/StringMapEntry.h |
llvm::BasicTTIImplBase<llvm::HexagonTTIImpl>::preferToKeepConstantsAttached(llvm::Instruction const&, llvm::Function const&) const | unsigned getValueID() const {
return SubclassID;
} | movzbl (%rsi), %ecx
xorl %eax, %eax
cmpq $0x34, %rcx
ja 0xe7198a
pushq %r14
pushq %rbx
pushq %rax
movq %rdx, %rbx
movabsq $0x1b000000000000, %rdx # imm = 0x1B000000000000
btq %rcx, %rdx
jae 0xe71983
movq %rdi, %r14
movl 0x4(%rsi), %eax
btl $0x1e, %eax
jb 0xe71945
shll $0x5, %eax
movq %rsi, %rcx
subq %rax, %rcx
jmp 0xe7... | /llvm/IR/Value.h |
llvm::HexagonTTIImpl::getIntrinsicInstrCost(llvm::IntrinsicCostAttributes const&, llvm::TargetTransformInfo::TargetCostKind) | InstructionCost
HexagonTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
TTI::TargetCostKind CostKind) {
if (ICA.getID() == Intrinsic::bswap) {
std::pair<InstructionCost, MVT> LT =
getTypeLegalizationCost(ICA.getReturnType());
return LT.first + 2;... | movq %rdi, %rax
cmpl $0xe, 0x10(%rsi)
jne 0xe77266
pushq %rbx
subq $0x20, %rsp
movq 0x8(%rsi), %rdx
leaq 0x8(%rsp), %rbx
movq %rbx, %rdi
movq %rax, %rsi
callq 0xe72102
movq (%rbx), %rcx
movl 0x8(%rbx), %edx
addq $0x2, %rcx
movabsq $0x7fffffffffffffff, %rax # imm = 0x7FFFFFFFFFFFFFFF
cmovnoq %rcx, %rax
addq $0x20, %rsp
... | /Target/Hexagon/HexagonTargetTransformInfo.cpp |
llvm::BasicTTIImplBase<llvm::HexagonTTIImpl>::getArithmeticInstrCost(unsigned int, llvm::Type*, llvm::TargetTransformInfo::TargetCostKind, llvm::TargetTransformInfo::OperandValueInfo, llvm::TargetTransformInfo::OperandValueInfo, llvm::ArrayRef<llvm::Value const*>, llvm::Instruction const*) | InstructionCost getArithmeticInstrCost(
unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
TTI::OperandValueInfo Opd1Info = {TTI::OK_AnyValue, TTI::OP_None},
TTI::OperandValueInfo Opd2Info = {TTI::OK_AnyValue, TTI::OP_None},
ArrayRef<const Value *> Args = std::nullopt,
const Instruct... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xc8, %rsp
movq %r9, 0x18(%rsp)
movq %r8, %r15
movl %ecx, %r12d
movq %rdx, %rbx
movl %esi, %r13d
movq %rdi, %r14
movq 0x18(%rdi), %rbp
movq %rbp, %rdi
callq 0x18c2518
testl %r12d, %r12d
je 0xe78160
addq $0x8, %r14
leaq 0x100(%rsp), %rax
movups (%ra... | /llvm/CodeGen/BasicTTIImpl.h |
llvm::HexagonTTIImpl::getCastInstrCost(unsigned int, llvm::Type*, llvm::Type*, llvm::TargetTransformInfo::CastContextHint, llvm::TargetTransformInfo::TargetCostKind, llvm::Instruction const*) | InstructionCost HexagonTTIImpl::getCastInstrCost(unsigned Opcode, Type *DstTy,
Type *SrcTy,
TTI::CastContextHint CCH,
TTI::TargetCostKind CostKind,
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x38, %rsp
movl %r9d, %r13d
movq %rcx, %r12
movq %rdx, %r14
movq %rdi, %r15
movl $0xfe, %ebp
movl 0x8(%rcx), %eax
andl %ebp, %eax
movabsq $0x7fffffffffffffff, %rbx # imm = 0x7FFFFFFFFFFFFFFF
cmpl $0x12, %eax
jne 0xe78584
movq %r15, %rdi
movq %r12, ... | /Target/Hexagon/HexagonTargetTransformInfo.cpp |
llvm::DenseMapBase<llvm::DenseMap<unsigned int, unsigned long, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, unsigned long>>, unsigned int, unsigned long, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, unsigned long>>::find(unsigned int const&) | iterator find(const_arg_type_t<KeyT> Val) {
BucketT *TheBucket;
if (LookupBucketFor(Val, TheBucket))
return makeIterator(TheBucket,
shouldReverseIterate<KeyT>() ? getBuckets()
: getBucketsEnd(),
*thi... | pushq %r14
pushq %rbx
pushq %rax
movq %rdi, %rbx
movq %rsp, %r14
movq %r14, %rdx
callq 0xe7aa9e
movl 0x10(%rbx), %edx
shlq $0x4, %rdx
addq (%rbx), %rdx
testb %al, %al
movq (%r14), %rax
cmoveq %rdx, %rax
addq $0x8, %rsp
popq %rbx
popq %r14
retq
nop
| /llvm/ADT/DenseMap.h |
bool llvm::DenseMapBase<llvm::DenseMap<unsigned int, unsigned long, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, unsigned long>>, unsigned int, unsigned long, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, unsigned long>>::LookupBucketFor<unsigned in... | unsigned getNumBuckets() const {
return NumBuckets;
} | movl 0x10(%rdi), %ecx
testl %ecx, %ecx
je 0xe7ab16
pushq %rbx
movq (%rdi), %rdi
movl (%rsi), %esi
leal (%rsi,%rsi,8), %eax
leal (%rsi,%rax,4), %r8d
decl %ecx
andl %ecx, %r8d
movl $0x1, %r10d
xorl %r9d, %r9d
movl %r8d, %ebx
shlq $0x4, %rbx
leaq (%rdi,%rbx), %r11
movl (%rdi,%rbx), %ebx
cmpl %ebx, %esi
jne 0xe7aae1
movq %... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::HexagonVectorCombine::run() | auto HexagonVectorCombine::run() -> bool {
if (DumpModule)
dbgs() << "Module before HexagonVectorCombine\n" << *F.getParent();
bool Changed = false;
if (HST.useHVXOps()) {
if (VAEnabled)
Changed |= AlignVectors(*this).run();
if (VIEnabled)
Changed |= HvxIdioms(*this).run();
}
if (Dum... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x688, %rsp # imm = 0x688
cmpb $0x1, 0x4a2ffbc(%rip) # 0x58ab700
movq %rdi, 0x38(%rsp)
jne 0xe7b784
callq 0x1c9e5e1
leaq 0x2be0248(%rip), %rsi # 0x3a5b99f
movl $0x23, %edx
movq %rax, %rdi
callq 0x7c4562
movq 0x38(%rsp), %rcx
movq (%r... | /Target/Hexagon/HexagonVectorCombine.cpp |
llvm::DenseMap<llvm::Instruction*, llvm::Instruction*, llvm::DenseMapInfo<llvm::Instruction*, void>, llvm::detail::DenseMapPair<llvm::Instruction*, llvm::Instruction*>>::operator=(llvm::DenseMap<llvm::Instruction*, llvm::Instruction*, llvm::DenseMapInfo<llvm::Instruction*, void>, llvm::detail::DenseMapPair<llvm::Instru... | DenseMap& operator=(DenseMap &&other) {
this->destroyAll();
deallocate_buffer(Buckets, sizeof(BucketT) * NumBuckets, alignof(BucketT));
init(0);
swap(other);
return *this;
} | pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %r14
movq %rdi, %rbx
movq (%rdi), %rdi
movl 0x10(%rbx), %esi
shlq $0x4, %rsi
movl $0x8, %edx
callq 0x1cac6c2
xorl %eax, %eax
movl %eax, 0x10(%rbx)
xorps %xmm0, %xmm0
movups %xmm0, (%rbx)
movq (%r14), %rcx
movq %rcx, (%rbx)
movq $0x0, (%r14)
movl 0x8(%r14), %ecx
movl %ecx, 0x8... | /llvm/ADT/DenseMap.h |
std::pair<llvm::DenseMapIterator<llvm::Instruction*, llvm::Instruction*, llvm::DenseMapInfo<llvm::Instruction*, void>, llvm::detail::DenseMapPair<llvm::Instruction*, llvm::Instruction*>, false>, bool> llvm::DenseMapBase<llvm::DenseMap<llvm::Instruction*, llvm::Instruction*, llvm::DenseMapInfo<llvm::Instruction*, void>,... | std::pair<iterator, bool> try_emplace(KeyT &&Key, Ts &&... Args) {
BucketT *TheBucket;
if (LookupBucketFor(Key, TheBucket))
return std::make_pair(makeIterator(TheBucket,
shouldReverseIterate<KeyT>()
? getBuckets()
... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x10, %rsp
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r14
movq %rdi, %rbx
leaq 0x8(%rsp), %r13
movq %rsi, %rdi
movq %rdx, %rsi
movq %r13, %rdx
callq 0xe83efa
movl %eax, %ecx
movq (%r13), %rax
testb %cl, %cl
je 0xe83eb2
xorl %ecx, %ecx
jmp 0xe83ed3
movq %r14,... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::AlignVectors::createAdjustedPointer(llvm::IRBuilderBase&, llvm::Value*, llvm::Type*, int, llvm::DenseMap<llvm::Instruction*, llvm::Instruction*, llvm::DenseMapInfo<llvm::Instruction*, void>, llvm::detail::DenseMapPair<llvm::Instruction*, llvm::Instruction*>> const&) const | auto AlignVectors::createAdjustedPointer(IRBuilderBase &Builder, Value *Ptr,
Type *ValTy, int Adjust,
const InstMap &CloneMap) const
-> Value * {
if (auto *I = dyn_cast<Instruction>(Ptr))
if (Instruction *New = CloneMap.lookup(I... | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x40, %rsp
movl %ecx, %ebp
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
cmpb $0x1d, (%rdx)
jb 0xe8452b
leaq 0x18(%rsp), %rsi
movq %rbx, (%rsi)
leaq 0x10(%rsp), %rdx
movq %r8, %rdi
callq 0xe846f4
testb %al, %al
je 0xe84522
movq 0x10(%rsp), %rax
movq 0x8(%ra... | /Target/Hexagon/HexagonVectorCombine.cpp |
(anonymous namespace)::AlignVectors::getPayload(llvm::Value*) const | auto AlignVectors::getPayload(Value *Val) const -> Value * {
if (auto *In = dyn_cast<Instruction>(Val)) {
Intrinsic::ID ID = 0;
if (auto *II = dyn_cast<IntrinsicInst>(In))
ID = II->getIntrinsicID();
if (isa<StoreInst>(In) || ID == Intrinsic::masked_store)
return In->getOperand(0);
}
return... | pushq %rbx
movq %rdi, %rbx
cmpb $0x1d, (%rdi)
jb 0xe84fa0
cmpb $0x55, (%rbx)
jne 0xe84f5c
movq %rbx, %rdi
callq 0x8f16ea
xorl %ecx, %ecx
testb %al, %al
cmovneq %rbx, %rcx
jmp 0xe84f5e
xorl %ecx, %ecx
testq %rcx, %rcx
je 0xe84f73
movq -0x20(%rcx), %rax
cmpl $0xe0, 0x24(%rax)
sete %cl
jmp 0xe84f75
xorl %ecx, %ecx
cmpb $0... | /Target/Hexagon/HexagonVectorCombine.cpp |
llvm::SmallVectorImpl<llvm::SmallVector<llvm::Value*, 6u>>::truncate(unsigned long) | void truncate(size_type N) {
assert(this->size() >= N && "Cannot increase size with truncate");
this->destroy_range(this->begin() + N, this->end());
this->set_size(N);
} | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %rsi, %rbx
movq %rdi, %r14
movl 0x8(%rdi), %r15d
cmpq %rsi, %r15
je 0xe87e5f
movq (%r14), %r12
leaq -0x30(%r12), %r13
shlq $0x6, %r15
movq %rbx, %rbp
shlq $0x6, %rbp
movq -0x40(%r12,%r15), %rdi
leaq (%r15,%r13), %rax
cmpq %rdi, %rax
je 0x... | /llvm/ADT/SmallVector.h |
void llvm::cl::apply<llvm::cl::opt<bool, false, llvm::cl::parser<bool>>, char [7], llvm::cl::OptionHidden, llvm::cl::initializer<bool>>(llvm::cl::opt<bool, false, llvm::cl::parser<bool>>*, char const (&) [7], llvm::cl::OptionHidden const&, llvm::cl::initializer<bool> const&) | void apply(Opt *O, const Mod &M, const Mods &... Ms) {
applicator<Mod>::opt(M, *O);
apply(O, Ms...);
} | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rcx, %rbx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
movq %rsi, %rdi
callq 0x7512e0
movq %r12, %rdi
movq %r15, %rsi
movq %rax, %rdx
callq 0x1c90c20
movl (%r14), %eax
movzwl 0xa(%r12), %ecx
shll $0x5, %eax
andl $0x60, %eax
andl $-0x61, %ecx
orl %eax, %ecx... | /llvm/Support/CommandLine.h |
(anonymous namespace)::HexagonVectorLoopCarriedReuse::run() | bool HexagonVectorLoopCarriedReuse::run() {
if (!CurLoop->getLoopPreheader())
return false;
// Work only on innermost loops.
if (!CurLoop->getSubLoops().empty())
return false;
// Work only on single basic blocks loops.
if (CurLoop->getNumBlocks() != 1)
return false;
return doVLCR();
} | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x1a8, %rsp # imm = 0x1A8
movq %rdi, %rbx
movq 0x58(%rdi), %rdi
callq 0x2922d58
testq %rax, %rax
je 0xe88516
movq 0x58(%rbx), %rax
movq 0x8(%rax), %rcx
cmpq 0x10(%rax), %rcx
je 0xe88532
xorl %r15d, %r15d
andb $0x1, %r15b
movl %r15d, %eax... | /Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp |
void llvm::cl::apply<llvm::cl::opt<int, false, llvm::cl::parser<int>>, char [27], llvm::cl::OptionHidden, llvm::cl::desc, llvm::cl::initializer<int>>(llvm::cl::opt<int, false, llvm::cl::parser<int>>*, char const (&) [27], llvm::cl::OptionHidden const&, llvm::cl::desc const&, llvm::cl::initializer<int> const&) | void apply(Opt *O, const Mod &M, const Mods &... Ms) {
applicator<Mod>::opt(M, *O);
apply(O, Ms...);
} | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %r8, %r14
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %rbx
movq %rsi, %rdi
callq 0x7512e0
movq %rbx, %rdi
movq %r13, %rsi
movq %rax, %rdx
callq 0x1c90c20
movl (%r12), %eax
movzwl 0xa(%rbx), %ecx
shll $0x5, %eax
andl $0x60, %eax
andl $-0x61, %ecx... | /llvm/Support/CommandLine.h |
(anonymous namespace)::HexagonVectorPrint::HexagonVectorPrint() | HexagonVectorPrint() : MachineFunctionPass(ID) {
initializeHexagonVectorPrintPass(*PassRegistry::getPassRegistry());
} | pushq %rax
xorl %eax, %eax
movq %rax, 0x8(%rdi)
leaq 0x4a21a00(%rip), %rcx # 0x58abc94
movq %rcx, 0x10(%rdi)
movl $0x2, 0x18(%rdi)
xorps %xmm0, %xmm0
movups %xmm0, 0x20(%rdi)
movq %rax, 0x30(%rdi)
leaq 0x48a7f8f(%rip), %rcx # 0x5732240
movq %rcx, (%rdi)
movups %xmm0, 0x38(%rdi)
movq %rax, 0x48(%rdi)
callq 0x1a82116... | /Target/Hexagon/HexagonVectorPrint.cpp |
llvm::HexagonPacketizerList::ignorePseudoInstruction(llvm::MachineInstr const&, llvm::MachineBasicBlock const*) | unsigned getOpcode() const { return Opcode; } | movl 0x44(%rsi), %ecx
leal -0xd(%rcx), %edx
movb $0x1, %al
cmpw $0x5, %dx
jb 0xe8d28e
decl %ecx
cmpw $0xa, %cx
jae 0xe8d28f
movl $0x207, %eax # imm = 0x207
btl %ecx, %eax
jae 0xe8d28f
xorl %eax, %eax
retq
movq 0x10(%rsi), %rax
movq 0x40(%rdi), %rcx
movq (%rcx), %rcx
movzwl 0x6(%rax), %eax
movq 0x48(%rcx), %r... | /llvm/CodeGen/MachineInstr.h |
llvm::HexagonPacketizerList::isLegalToPacketizeTogether(llvm::SUnit*, llvm::SUnit*) | bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
assert(SUI->getInstr() && SUJ->getInstr());
MachineInstr &I = *SUI->getInstr();
MachineInstr &J = *SUJ->getInstr();
// Clear IgnoreDepMIs when Packet starts.
if (CurrentPacketMIs.size() == 1)
IgnoreDepMIs.clear();
Machine... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x58, %rsp
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %rbx
movq (%rsi), %r12
movq (%rdx), %r13
movq 0x30(%rdi), %rax
subq 0x28(%rdi), %rax
cmpq $0x8, %rax
jne 0xe8ddfa
movq 0xa8(%rbx), %rax
cmpq %rax, 0xb0(%rbx)
je 0xe8ddfa
movq %rax, 0xb0(%rbx)
mo... | /Target/Hexagon/HexagonVLIWPacketizer.cpp |
llvm::Pass* llvm::callDefaultCtor<(anonymous namespace)::HexagonBitSimplify, true>() | Pass *callDefaultCtor() {
return new PassName();
} | pushq %rax
movl $0x40, %edi
callq 0x751940
movq $0x0, 0x8(%rax)
leaq 0x4a1c7dc(%rip), %rcx # 0x58ac5b0
movq %rcx, 0x10(%rax)
movl $0x2, 0x18(%rax)
xorps %xmm0, %xmm0
movups %xmm0, 0x20(%rax)
movups %xmm0, 0x30(%rax)
leaq 0x48a27af(%rip), %rcx # 0x57325a0
movq %rcx, (%rax)
popq %rcx
retq
| /llvm/PassSupport.h |
(anonymous namespace)::HexagonLoopRescheduling::runOnMachineFunction(llvm::MachineFunction&) | bool HexagonLoopRescheduling::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(MF.getFunction()))
return false;
auto &HST = MF.getSubtarget<HexagonSubtarget>();
HII = HST.getInstrInfo();
HRI = HST.getRegisterInfo();
MRI = &MF.getRegInfo();
const HexagonEvaluator HE(*HRI, *MRI, *HII, MF);
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x528, %rsp # imm = 0x528
movq %rsi, %r12
movq %rdi, %rbx
movq (%rsi), %rsi
callq 0x1a7c502
testb %al, %al
je 0xe8fe54
xorl %eax, %eax
jmp 0xe921f0
movq %rbx, 0x8(%rsp)
movq 0x10(%r12), %r14
movq (%r14), %rax
movq %r14, %rdi
callq *0x80(... | /Target/Hexagon/HexagonBitSimplify.cpp |
(anonymous namespace)::HexagonLoopRescheduling::getDefReg(llvm::MachineInstr const*) | unsigned HexagonLoopRescheduling::getDefReg(const MachineInstr *MI) {
RegisterSet Defs;
HBS::getInstrDefs(*MI, Defs);
if (Defs.count() != 1)
return 0;
return Defs.find_first();
} | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x98, %rsp
movq %rdi, %r15
leaq 0x10(%rsp), %r13
movq %r13, -0x10(%r13)
movabsq $0x600000000, %rax # imm = 0x600000000
movq %rax, -0x8(%r13)
movl $0x0, 0x30(%r13)
leaq 0x48(%rsp), %rbx
xorps %xmm0, %xmm0
movups %xmm0, (%rbx)
movups %xmm0, 0x10... | /Target/Hexagon/HexagonBitSimplify.cpp |
(anonymous namespace)::HexagonBitSimplify::runOnMachineFunction(llvm::MachineFunction&) | bool HexagonBitSimplify::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(MF.getFunction()))
return false;
auto &HST = MF.getSubtarget<HexagonSubtarget>();
auto &HRI = *HST.getRegisterInfo();
auto &HII = *HST.getInstrInfo();
MDT = &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x658, %rsp # imm = 0x658
movq %rsi, %rbx
movq %rdi, %r13
movq (%rsi), %rsi
callq 0x1a7c502
testb %al, %al
je 0xe93380
xorl %ebp, %ebp
jmp 0xe93a2f
movq 0x10(%rbx), %r15
movq (%r15), %rax
movq %r15, %rdi
callq *0xc8(%rax)
movq %rax, 0x8(... | /Target/Hexagon/HexagonBitSimplify.cpp |
(anonymous namespace)::HexagonBitSimplify::isTransparentCopy(llvm::BitTracker::RegisterRef const&, llvm::BitTracker::RegisterRef const&, llvm::MachineRegisterInfo&) | bool HexagonBitSimplify::isTransparentCopy(const BitTracker::RegisterRef &RD,
const BitTracker::RegisterRef &RS, MachineRegisterInfo &MRI) {
if (!RD.Reg.isVirtual() || !RS.Reg.isVirtual())
return false;
// Return false if one (or both) classes are nullptr.
auto *DRC = getFinalVRegClass(RD, MRI);
if (!... | xorl %eax, %eax
cmpl $0x0, (%rdi)
jns 0xe959f7
pushq %r15
pushq %r14
pushq %rbx
movq %rsi, %r14
cmpl $0x0, (%rsi)
jns 0xe959f2
movq %rdx, %rbx
movq %rdx, %rsi
callq 0xe95bc2
testq %rax, %rax
je 0xe959f0
movq %rax, %r15
movq %r14, %rdi
movq %rbx, %rsi
callq 0xe95bc2
cmpq %rax, %r15
sete %al
jmp 0xe959f2
xorl %eax, %eax
... | /Target/Hexagon/HexagonBitSimplify.cpp |
(anonymous namespace)::CopyGeneration::~CopyGeneration() | CopyGeneration(BitTracker &bt, const HexagonInstrInfo &hii,
const HexagonRegisterInfo &hri, MachineRegisterInfo &mri)
: Transformation(true), HII(hii), HRI(hri), MRI(mri), BT(bt) {} | pushq %rbx
movq %rdi, %rbx
leaq 0x489c977(%rip), %rax # 0x57326b0
movq %rax, (%rdi)
addq $0x78, %rdi
callq 0xe928ba
movq 0x30(%rbx), %rdi
leaq 0x40(%rbx), %rax
cmpq %rax, %rdi
je 0xe95d57
callq 0x751980
movl $0xc8, %esi
movq %rbx, %rdi
popq %rbx
jmp 0x7510e0
nop
| /Target/Hexagon/HexagonBitSimplify.cpp |
(anonymous namespace)::CopyPropagation::isCopyReg(unsigned int, bool) | bool CopyPropagation::isCopyReg(unsigned Opc, bool NoConv) {
switch (Opc) {
case TargetOpcode::COPY:
case TargetOpcode::REG_SEQUENCE:
case Hexagon::A4_combineir:
case Hexagon::A4_combineri:
return true;
case Hexagon::A2_tfr:
case Hexagon::A2_tfrp:
case Hexagon::A2_combinew:
case ... | movb $0x1, %al
cmpl $0x3f0, %edi # imm = 0x3F0
jg 0xe96523
leal -0x12(%rdi), %ecx
cmpl $0x2, %ecx
jb 0xe96522
cmpl $0x12d, %edi # imm = 0x12D
je 0xe96543
movl %esi, %eax
cmpl $0x3a6, %edi # imm = 0x3A6
jne 0xe96540
retq
leal -0x44b(%rdi), %ecx
cmpl $0x2, %ecx
jb 0xe96522
cmpl $0xb35, %e... | /Target/Hexagon/HexagonBitSimplify.cpp |
(anonymous namespace)::CopyGeneration::findMatch(llvm::BitTracker::RegisterRef const&, llvm::BitTracker::RegisterRef&, (anonymous namespace)::RegisterSet const&) | bool CopyGeneration::findMatch(const BitTracker::RegisterRef &Inp,
BitTracker::RegisterRef &Out, const RegisterSet &AVs) {
if (!BT.has(Inp.Reg))
return false;
const BitTracker::RegisterCell &InpRC = BT.lookup(Inp.Reg);
auto *FRC = HBS::getFinalVRegClass(Inp, MRI);
unsigned B, W;
if (!HBS::getSubregM... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x58, %rsp
movq %rcx, %rbx
movq %rdx, %r15
movq %rsi, %r14
movq %rdi, %r12
movq 0x28(%rdi), %rcx
movl (%rsi), %eax
movq 0x18(%rcx), %r13
movq 0x10(%r13), %rcx
addq $0x8, %r13
movq %r13, %rdx
testq %rcx, %rcx
je 0xe96597
movq %rcx, %rsi
movq %r13, %... | /Target/Hexagon/HexagonBitSimplify.cpp |
(anonymous namespace)::CopyPropagation::processBlock(llvm::MachineBasicBlock&, (anonymous namespace)::RegisterSet const&) | bool CopyPropagation::processBlock(MachineBasicBlock &B, const RegisterSet&) {
std::vector<MachineInstr*> Instrs;
for (MachineInstr &MI : llvm::reverse(B))
Instrs.push_back(&MI);
bool Changed = false;
for (auto *I : Instrs) {
unsigned Opc = I->getOpcode();
if (!CopyPropagation::isCopyReg(Opc, true)... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x58, %rsp
movq %rsi, %r14
movq %rdi, 0x10(%rsp)
xorps %xmm0, %xmm0
movaps %xmm0, 0x30(%rsp)
movq $0x0, 0x40(%rsp)
movq %rsi, %rdi
callq 0x96669c
addq $0x30, %r14
movq %rax, 0x18(%rsp)
cmpq %r14, %rax
je 0xe9690c
leaq 0x30(%rsp), %r15
leaq 0x20(%rs... | /Target/Hexagon/HexagonBitSimplify.cpp |
(anonymous namespace)::BitSimplification::validateReg(llvm::BitTracker::RegisterRef, unsigned int, unsigned int) | bool BitSimplification::validateReg(BitTracker::RegisterRef R, unsigned Opc,
unsigned OpNum) {
auto *OpRC = HII.getRegClass(HII.get(Opc), OpNum, &HRI, MF);
auto *RRC = HBS::getFinalVRegClass(R, MRI);
return OpRC->hasSubClassEq(RRC);
} | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rdi, %rbx
leaq 0x8(%rsp), %r14
movq %rsi, (%r14)
movq 0x30(%rdi), %rdi
movq 0x38(%rbx), %rax
movq (%rdi), %r9
movq 0x8(%rdi), %rsi
movl %edx, %edx
shlq $0x5, %rdx
subq %rdx, %rsi
movq 0x48(%rbx), %r8
movl %ecx, %edx
movq %rax, %rcx
callq *0x10(%r9)
movq %rax, %r15... | /Target/Hexagon/HexagonBitSimplify.cpp |
(anonymous namespace)::HexagonBranchRelaxation::HexagonBranchRelaxation() | HexagonBranchRelaxation() : MachineFunctionPass(ID) {
initializeHexagonBranchRelaxationPass(*PassRegistry::getPassRegistry());
} | pushq %rax
xorl %eax, %eax
movq %rax, 0x8(%rdi)
leaq 0x4a0a9c8(%rip), %rcx # 0x58ac684
movq %rcx, 0x10(%rdi)
movl $0x2, 0x18(%rdi)
xorps %xmm0, %xmm0
movups %xmm0, 0x20(%rdi)
movq %rax, 0x30(%rdi)
leaq 0x4890a9f(%rip), %rax # 0x5732778
movq %rax, (%rdi)
callq 0x1a82116
movq %rsp, %rdx
movq %rax, (%rdx)
leaq 0x4a0a9... | /Target/Hexagon/HexagonBranchRelaxation.cpp |
(anonymous namespace)::HexagonCFGOptimizer::HexagonCFGOptimizer() | HexagonCFGOptimizer() : MachineFunctionPass(ID) {
initializeHexagonCFGOptimizerPass(*PassRegistry::getPassRegistry());
} | pushq %rax
xorl %eax, %eax
movq %rax, 0x8(%rdi)
leaq 0x4a0a4c6(%rip), %rcx # 0x58ac68c
movq %rcx, 0x10(%rdi)
movl $0x2, 0x18(%rdi)
xorps %xmm0, %xmm0
movups %xmm0, 0x20(%rdi)
movq %rax, 0x30(%rdi)
leaq 0x4890655(%rip), %rax # 0x5732838
movq %rax, (%rdi)
callq 0x1a82116
movq %rsp, %rdx
movq %rax, (%rdx)
leaq 0x4a0a4... | /Target/Hexagon/HexagonCFGOptimizer.cpp |
(anonymous namespace)::HexagonCFGOptimizer::runOnMachineFunction(llvm::MachineFunction&) | bool HexagonCFGOptimizer::runOnMachineFunction(MachineFunction &Fn) {
if (skipFunction(Fn.getFunction()))
return false;
// Loop over all of the basic blocks.
for (MachineBasicBlock &MBB : Fn) {
// Traverse the basic block.
MachineBasicBlock::iterator MII = MBB.getFirstTerminator();
if (MII != MBB... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x58, %rsp
movq %rsi, %rbx
movq (%rsi), %rsi
callq 0x1a7c502
movb %al, 0x7(%rsp)
testb %al, %al
jne 0xea264c
movq 0x148(%rbx), %r14
addq $0x140, %rbx # imm = 0x140
movq %rbx, 0x50(%rsp)
cmpq %rbx, %r14
je 0xea264c
movq %r14, %rdi
callq 0... | /Target/Hexagon/HexagonCFGOptimizer.cpp |
(anonymous namespace)::HexagonCommonGEP::getBlockTraversalOrder(llvm::BasicBlock*, std::vector<llvm::Value*, std::allocator<llvm::Value*>>&) | void HexagonCommonGEP::getBlockTraversalOrder(BasicBlock *Root,
ValueVect &Order) {
// Compute block ordering for a typical DT-based traversal of the flow
// graph: "before visiting a block, all of its dominators must have been
// visited".
Order.push_back(Root);
for (auto *DTN : children<DomTreeNode*>... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x10, %rsp
movq %rdx, %rbx
movq %rsi, %r15
movq %rdi, %r14
leaq 0x8(%rsp), %rsi
movq %r15, (%rsi)
movq %rdx, %rdi
callq 0xca4a0e
movq 0xb8(%r14), %rdi
addq $0x18, %rdi
movq %r15, %rsi
callq 0xb0422c
movq 0x8(%rax), %rax
movl 0x20(%rax), %r15d
testq %r15, %r15... | /Target/Hexagon/HexagonCommonGEP.cpp |
llvm::DenseMap<llvm::Use*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::Use*, void>, llvm::detail::DenseSetPair<llvm::Use*>>::copyFrom(llvm::DenseMap<llvm::Use*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::Use*, void>, llvm::detail::DenseSetPair<llvm::Use*>> const&) | void copyFrom(const DenseMap& other) {
this->destroyAll();
deallocate_buffer(Buckets, sizeof(BucketT) * NumBuckets, alignof(BucketT));
if (allocateBuckets(other.NumBuckets)) {
this->BaseT::copyFrom(other);
} else {
NumEntries = 0;
NumTombstones = 0;
}
} | pushq %r15
pushq %r14
pushq %rbx
movq %rsi, %r14
movq %rdi, %rbx
movq (%rdi), %rdi
movl 0x10(%rbx), %esi
shlq $0x3, %rsi
movl $0x8, %edx
callq 0x1cac6c2
movl 0x10(%r14), %r15d
movl %r15d, 0x10(%rbx)
testq %r15, %r15
je 0xea70fa
leaq (,%r15,8), %rdi
movl $0x8, %esi
callq 0x1cac6bd
jmp 0xea70fc
xorl %eax, %eax
movq %rax,... | /llvm/ADT/DenseMap.h |
void llvm::cl::apply<llvm::cl::opt<bool, false, llvm::cl::parser<bool>>, char [12], llvm::cl::initializer<bool>, llvm::cl::OptionHidden>(llvm::cl::opt<bool, false, llvm::cl::parser<bool>>*, char const (&) [12], llvm::cl::initializer<bool> const&, llvm::cl::OptionHidden const&) | void apply(Opt *O, const Mod &M, const Mods &... Ms) {
applicator<Mod>::opt(M, *O);
apply(O, Ms...);
} | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rcx, %rbx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
movq %rsi, %rdi
callq 0x7512e0
movq %r12, %rdi
movq %r15, %rsi
movq %rax, %rdx
callq 0x1c90c20
movq (%r14), %rax
movb (%rax), %cl
movb %cl, 0x80(%r12)
movb $0x1, 0x91(%r12)
movb (%rax), %al
movb %al, 0... | /llvm/Support/CommandLine.h |
llvm::Pass* llvm::callDefaultCtor<(anonymous namespace)::HexagonConstExtenders, true>() | Pass *callDefaultCtor() {
return new PassName();
} | pushq %rax
movl $0x90, %edi
callq 0x751940
xorl %ecx, %ecx
movq %rcx, 0x8(%rax)
leaq 0x4a05594(%rip), %rdx # 0x58aca5c
movq %rdx, 0x10(%rax)
movl $0x2, 0x18(%rax)
xorps %xmm0, %xmm0
movups %xmm0, 0x20(%rax)
movq %rcx, 0x30(%rax)
leaq 0x488b4b3(%rip), %rdx # 0x5732998
movq %rdx, (%rax)
movups %xmm0, 0x38(%rax)
movup... | /llvm/PassSupport.h |
(anonymous namespace)::HexagonConstExtenders::runOnMachineFunction(llvm::MachineFunction&) | bool HCE::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(MF.getFunction()))
return false;
if (MF.getFunction().hasPersonalityFn()) {
LLVM_DEBUG(dbgs() << getPassName() << ": skipping " << MF.getName()
<< " due to exception handling\n");
return false;
}
LLVM_DEBUG(... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x258, %rsp # imm = 0x258
movq %rsi, %r15
movq %rdi, %r12
movq (%rsi), %rsi
callq 0x1a7c502
testb %al, %al
jne 0xea7fb2
movq (%r15), %rax
testb $0x8, 0x2(%rax)
jne 0xea7fb2
movq 0x10(%r15), %rdi
movq %rdi, 0x38(%r12)
movq (%rdi), %rax
ca... | /Target/Hexagon/HexagonConstExtenders.cpp |
(anonymous namespace)::HexagonConstExtenders::ExtValue::operator<((anonymous namespace)::HexagonConstExtenders::ExtValue const&) const | bool HCE::ExtValue::operator< (const HCE::ExtValue &EV) const {
const ExtRoot &ER = *this;
if (!(ER == ExtRoot(EV)))
return ER < EV;
return Offset < EV.Offset;
} | pushq %r15
pushq %r14
pushq %rbx
subq $0x20, %rsp
movq %rsi, %rbx
movq (%rsi), %rax
movl 0x8(%rsi), %esi
movl 0x8(%rdi), %edx
cmpl %esi, %edx
sete %r8b
movq (%rdi), %rcx
cmpq %rax, %rcx
sete %r9b
testb %r9b, %r8b
je 0xeac36c
movl 0x10(%rdi), %eax
cmpl 0x10(%rbx), %eax
jmp 0xeac38a
cmpl %esi, %edx
jne 0xeac38f
decl %edx... | /Target/Hexagon/HexagonConstExtenders.cpp |
(anonymous namespace)::RangeTree::add((anonymous namespace)::RangeTree::Node*, (anonymous namespace)::OffsetRange const&) | RangeTree::Node *RangeTree::add(Node *N, const OffsetRange &R) {
if (N == nullptr)
return new Node(R);
if (N->Range == R) {
N->Count++;
return N;
}
if (R < N->Range)
N->Left = add(N->Left, R);
else
N->Right = add(N->Right, R);
return rebalance(update(N));
} | pushq %r15
pushq %r14
pushq %rbx
movq %rsi, %r14
testq %rdi, %rdi
je 0xead19f
movq %rdi, %rbx
movq 0x10(%rdi), %rax
movl (%rax), %ecx
movl (%r14), %edx
cmpl %edx, %ecx
jne 0xead1ed
movl 0x4(%rax), %esi
cmpl 0x4(%r14), %esi
jne 0xead1d4
movb 0x8(%rax), %sil
cmpb 0x8(%r14), %sil
jne 0xead1d4
incl 0x4(%rbx)
jmp 0xead1cb
m... | /Target/Hexagon/HexagonConstExtenders.cpp |
(anonymous namespace)::HexagonConstEvaluator::evaluateHexExt(llvm::MachineInstr const&, (anonymous namespace)::MachineConstPropagator::CellMap const&, (anonymous namespace)::MachineConstPropagator::CellMap&) | bool HexagonConstEvaluator::evaluateHexExt(const MachineInstr &MI,
const CellMap &Inputs, CellMap &Outputs) {
// Dst0 = ext R1
RegisterSubReg R1(MI.getOperand(1));
assert(Inputs.has(R1.Reg));
unsigned Opc = MI.getOpcode();
unsigned Bits;
switch (Opc) {
case Hexagon::A2_sxtb:
case Hexagon::A2_... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xb8, %rsp
movq %rcx, %rbx
movq %rdx, %r13
movq %rdi, %r14
movq 0x20(%rsi), %rax
movl 0x24(%rax), %ecx
movl %ecx, 0x58(%rsp)
movl 0x20(%rax), %ecx
shrl $0x8, %ecx
andl $0xfff, %ecx # imm = 0xFFF
movl %ecx, 0x5c(%rsp)
movzwl 0x44(%rsi), %... | /Target/Hexagon/HexagonConstPropagation.cpp |
(anonymous namespace)::MachineConstEvaluator::evaluateCLBr((anonymous namespace)::RegisterSubReg const&, bool, bool, (anonymous namespace)::MachineConstPropagator::CellMap const&, (anonymous namespace)::LatticeCell&) | bool MachineConstEvaluator::evaluateCLBr(const RegisterSubReg &R1, bool Zeros,
bool Ones, const CellMap &Inputs, LatticeCell &Result) {
assert(Inputs.has(R1.Reg));
LatticeCell LS1;
if (!getCell(R1, Inputs, LS1))
return false;
if (LS1.isBottom() || LS1.isProperty())
return false;
APInt A, CA;
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x68, %rsp
movq %r9, %rbx
movl %ecx, %ebp
movl %edx, %r14d
movq %rdi, %r15
leaq 0x40(%rsp), %rcx
movb (%rcx), %al
andb $-0x40, %al
incb %al
movb %al, (%rcx)
xorps %xmm0, %xmm0
movups %xmm0, 0x8(%rcx)
movups %xmm0, 0x18(%rcx)
movq %r8, %rdx
callq 0x... | /Target/Hexagon/HexagonConstPropagation.cpp |
(anonymous namespace)::MachineConstEvaluator::getCell((anonymous namespace)::RegisterSubReg const&, (anonymous namespace)::MachineConstPropagator::CellMap const&, (anonymous namespace)::LatticeCell&) | bool MachineConstEvaluator::getCell(const RegisterSubReg &R, const CellMap &Inputs,
LatticeCell &RC) {
if (!R.Reg.isVirtual())
return false;
const LatticeCell &L = Inputs.get(R.Reg);
if (!R.SubReg) {
RC = L;
return !RC.isBottom();
}
bool Eval = evaluate(R, L, RC);
return Eval && !RC.isBott... | pushq %r15
pushq %r14
pushq %rbx
movq %rsi, %r14
movl (%rsi), %esi
testl %esi, %esi
js 0xeb3542
xorl %eax, %eax
jmp 0xeb3584
movq %rcx, %rbx
movq %rdi, %r15
movq %rdx, %rdi
callq 0xeb1aa4
cmpl $0x0, 0x4(%r14)
je 0xeb3570
movq (%r15), %r8
movq %r15, %rdi
movq %r14, %rsi
movq %rax, %rdx
movq %rbx, %rcx
callq *0x18(%r8)
t... | /Target/Hexagon/HexagonConstPropagation.cpp |
llvm::SmallVectorTemplateBase<llvm::APInt, false>::grow(unsigned long) | void SmallVectorTemplateBase<T, TriviallyCopyable>::grow(size_t MinSize) {
size_t NewCapacity;
T *NewElts = mallocForGrow(MinSize, NewCapacity);
moveElementsForGrow(NewElts);
takeAllocationForGrow(NewElts, NewCapacity);
} | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rsi, %rdx
movq %rdi, %rbx
leaq 0x10(%rdi), %r15
movq %rsp, %r12
movl $0x10, %ecx
movq %r15, %rsi
movq %r12, %r8
callq 0x1cba3de
movq %rax, %r14
movq %rbx, %rdi
movq %rax, %rsi
callq 0xeb37ca
movq (%r12), %r12
movq (%rbx), %rdi
cmpq %r15, %rdi
je 0xeb37b6
call... | /llvm/ADT/SmallVector.h |
(anonymous namespace)::MachineConstEvaluator::evaluateANDri((anonymous namespace)::RegisterSubReg const&, llvm::APInt const&, (anonymous namespace)::MachineConstPropagator::CellMap const&, (anonymous namespace)::LatticeCell&) | bool MachineConstEvaluator::evaluateANDri(const RegisterSubReg &R1,
const APInt &A2, const CellMap &Inputs, LatticeCell &Result) {
assert(Inputs.has(R1.Reg));
if (A2 == -1)
return getCell(R1, Inputs, Result);
if (A2 == 0) {
LatticeCell RC;
RC.add(intToConst(A2));
// Overwrite Result.
Res... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x58, %rsp
movq %r8, %rbx
movq %rcx, %r12
movq %rdx, %r14
movq %rsi, %r13
movq %rdi, %r15
movl 0x8(%rdx), %ebp
cmpl $0x41, %ebp
jb 0xeb4182
movq %r14, %rdi
callq 0x1c82ec2
movl %ebp, %ecx
subl %eax, %ecx
cmpl $0x40, %ecx
ja 0xeb4193
movq %r14, %rax... | /Target/Hexagon/HexagonConstPropagation.cpp |
llvm::DenseMap<llvm::MachineBasicBlock const*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::MachineBasicBlock const*, void>, llvm::detail::DenseSetPair<llvm::MachineBasicBlock const*>>::init(unsigned int) | void init(unsigned InitNumEntries) {
auto InitBuckets = BaseT::getMinBucketToReserveForEntries(InitNumEntries);
if (allocateBuckets(InitBuckets)) {
this->BaseT::initEmpty();
} else {
NumEntries = 0;
NumTombstones = 0;
}
} | pushq %rbp
pushq %rbx
pushq %rax
movq %rdi, %rbx
testl %esi, %esi
je 0xeb46bc
shll $0x2, %esi
movl $0xaaaaaaab, %eax # imm = 0xAAAAAAAB
imulq %rsi, %rax
shrq $0x21, %rax
incl %eax
movl %eax, %ecx
shrl %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x2, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x4, %ecx
orl %eax, %ecx... | /llvm/ADT/DenseMap.h |
void llvm::cl::initializer<char [1]>::apply<llvm::cl::opt<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char>>, false, llvm::cl::parser<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char>>>>>(llvm::cl::opt<std::__cxx11::basic_string<char, std::char_traits<char>, std::... | void apply(Opt &O) const { O.setInitialValue(Init); } | pushq %r14
pushq %rbx
subq $0x28, %rsp
movq %rsi, %rbx
movq (%rdi), %rsi
leaq 0x8(%rsp), %r14
leaq 0x7(%rsp), %rdx
movq %r14, %rdi
callq 0x7c52c8
leaq 0x80(%rbx), %rdi
movq %r14, %rsi
callq 0x751880
movb $0x1, 0xc8(%rbx)
addq $0xa8, %rbx
movq %rbx, %rdi
movq %r14, %rsi
callq 0x751880
movq (%r14), %rdi
leaq 0x18(%rsp), ... | /llvm/Support/CommandLine.h |
llvm::cl::opt<unsigned int, false, llvm::cl::parser<unsigned int>>::opt<char [10], llvm::cl::initializer<int>, llvm::cl::OptionHidden, llvm::cl::desc>(char const (&) [10], llvm::cl::initializer<int> const&, llvm::cl::OptionHidden const&, llvm::cl::desc const&) | explicit opt(const Mods &... Ms)
: Option(llvm::cl::Optional, NotHidden), Parser(*this) {
apply(this, Ms...);
done();
} | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %r8, %rbx
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %r14
xorl %esi, %esi
xorl %edx, %edx
callq 0x7c77e2
movl $0x0, 0x80(%r14)
xorps %xmm0, %xmm0
movups %xmm0, 0x88(%r14)
movb $0x0, 0x94(%r14)
leaq 0x48381c2(%rip), %rax # 0x56f1ec8
movq %rax,... | /llvm/Support/CommandLine.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::MachineBasicBlock*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::MachineBasicBlock*, void>, llvm::detail::DenseSetPair<llvm::MachineBasicBlock*>>, llvm::MachineBasicBlock*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::MachineBasicBlock*, void>, llvm::detail::Den... | unsigned getNumEntries() const {
return NumEntries;
} | movl 0x8(%rdi), %eax
testl %eax, %eax
jne 0xeba2d9
cmpl $0x0, 0xc(%rdi)
je 0xeba3ac
shll $0x2, %eax
movl 0x10(%rdi), %ecx
cmpl %ecx, %eax
setae %al
cmpl $0x41, %ecx
setb %dl
orb %al, %dl
je 0xeba3ae
testq %rcx, %rcx
je 0xeba3a4
movq (%rdi), %rax
movabsq $0x1fffffffffffffff, %rdx # imm = 0x1FFFFFFFFFFFFFFF
addq %rdx, %r... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::HexagonEarlyIfConversion::predicateBlockNB(llvm::MachineBasicBlock*, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::MachineBasicBlock*, unsigned int, bool) | void HexagonEarlyIfConversion::predicateBlockNB(MachineBasicBlock *ToB,
MachineBasicBlock::iterator At, MachineBasicBlock *FromB,
unsigned PredR, bool IfTrue) {
LLVM_DEBUG(dbgs() << "Predicating block " << PrintMB(FromB) << "\n");
MachineBasicBlock::iterator End = FromB->getFirstTerminator();
MachineB... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x98, %rsp
movl %r9d, %ebx
movl %r8d, 0x14(%rsp)
movq %rcx, %r14
movq %rdx, %r12
movq %rsi, 0x40(%rsp)
movq %rdi, %rbp
movq %rcx, %rdi
callq 0x174ff92
movq %r14, 0x88(%rsp)
movq 0x38(%r14), %r14
movq %rax, 0x90(%rsp)
cmpq %rax, %r14
je 0xebc242
mov... | /Target/Hexagon/HexagonEarlyIfConv.cpp |
void llvm::cl::apply<llvm::cl::opt<unsigned int, false, llvm::cl::parser<unsigned int>>, char [10], llvm::cl::initializer<int>, llvm::cl::OptionHidden, llvm::cl::desc>(llvm::cl::opt<unsigned int, false, llvm::cl::parser<unsigned int>>*, char const (&) [10], llvm::cl::initializer<int> const&, llvm::cl::OptionHidden cons... | void apply(Opt *O, const Mod &M, const Mods &... Ms) {
applicator<Mod>::opt(M, *O);
apply(O, Ms...);
} | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %r8, %rbx
movq %rcx, %r14
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %r13
movq %rsi, %rdi
callq 0x7512e0
movq %r13, %rdi
movq %r12, %rsi
movq %rax, %rdx
callq 0x1c90c20
movq (%r15), %rax
movl (%rax), %eax
movl %eax, 0x80(%r13)
movb $0x1, 0x94(%r13)
movl %eax, ... | /llvm/Support/CommandLine.h |
(anonymous namespace)::HexagonExpandCondsets::updateLiveness(std::set<llvm::Register, std::less<llvm::Register>, std::allocator<llvm::Register>> const&, bool, bool, bool) | void HexagonExpandCondsets::updateLiveness(const std::set<Register> &RegSet,
bool Recalc, bool UpdateKills,
bool UpdateDeads) {
UpdateKills |= UpdateDeads;
for (Register R : RegSet) {
if (!R.isVirtual()) {
assert(R.isPhy... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movl %edx, 0x4(%rsp)
movq %rsi, %r14
movq 0x18(%rsi), %r12
addq $0x8, %r14
cmpq %r14, %r12
je 0xebe2a4
movl %ecx, %ebp
movq %rdi, %r15
movl %ecx, (%rsp)
movl 0x20(%r12), %r13d
testl %r13d, %r13d
jns 0xebe290
cmpb $0x0, 0x4(%rsp)
je 0xebe1f0
mo... | /Target/Hexagon/HexagonExpandCondsets.cpp |
llvm::DenseMap<llvm::VNInfo*, llvm::VNInfo*, llvm::DenseMapInfo<llvm::VNInfo*, void>, llvm::detail::DenseMapPair<llvm::VNInfo*, llvm::VNInfo*>>::grow(unsigned int) | void grow(unsigned AtLeast) {
unsigned OldNumBuckets = NumBuckets;
BucketT *OldBuckets = Buckets;
allocateBuckets(std::max<unsigned>(64, static_cast<unsigned>(NextPowerOf2(AtLeast-1))));
assert(Buckets);
if (!OldBuckets) {
this->BaseT::initEmpty();
return;
}
this->moveFromOldBu... | pushq %r15
pushq %r14
pushq %rbx
movq %rdi, %r15
movl 0x10(%rdi), %ebx
movq (%rdi), %r14
leal -0x1(%rsi), %eax
movl %eax, %ecx
shrl %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x2, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x4, %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x8, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x10,... | /llvm/ADT/DenseMap.h |
void llvm::cl::apply<llvm::cl::opt<unsigned int, false, llvm::cl::parser<unsigned int>>, char [26], llvm::cl::initializer<unsigned int>, llvm::cl::OptionHidden, llvm::cl::desc>(llvm::cl::opt<unsigned int, false, llvm::cl::parser<unsigned int>>*, char const (&) [26], llvm::cl::initializer<unsigned int> const&, llvm::cl:... | void apply(Opt *O, const Mod &M, const Mods &... Ms) {
applicator<Mod>::opt(M, *O);
apply(O, Ms...);
} | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %r8, %rbx
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %r14
movq %rsi, %rdi
callq 0x7512e0
movq %r14, %rdi
movq %r13, %rsi
movq %rax, %rdx
callq 0x1c90c20
movq (%r12), %rax
movl (%rax), %ecx
movl %ecx, 0x80(%r14)
movb $0x1, 0x94(%r14)
movl (%rax)... | /llvm/Support/CommandLine.h |
llvm::cl::opt<unsigned int, false, llvm::cl::parser<unsigned int>>::opt<char [19], llvm::cl::OptionHidden, llvm::cl::initializer<int>, llvm::cl::desc>(char const (&) [19], llvm::cl::OptionHidden const&, llvm::cl::initializer<int> const&, llvm::cl::desc const&) | explicit opt(const Mods &... Ms)
: Option(llvm::cl::Optional, NotHidden), Parser(*this) {
apply(this, Ms...);
done();
} | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %r8, %rbx
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %r14
xorl %esi, %esi
xorl %edx, %edx
callq 0x7c77e2
movl $0x0, 0x80(%r14)
xorps %xmm0, %xmm0
movups %xmm0, 0x88(%r14)
movb $0x0, 0x94(%r14)
leaq 0x48319fe(%rip), %rax # 0x56f1ec8
movq %rax,... | /llvm/Support/CommandLine.h |
llvm::HexagonFrameLowering::emitPrologue(llvm::MachineFunction&, llvm::MachineBasicBlock&) const | void HexagonFrameLowering::emitPrologue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
MachineFrameInfo &MFI = MF.getFrameInfo();
const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x118, %rsp # imm = 0x118
movq %rsi, %r14
movq %rdi, %rbx
movq 0x10(%rsi), %rdi
movq (%rdi), %rax
callq *0xc8(%rax)
movq %rax, %r12
movq 0x38(%r14), %rax
movq %rax, 0x38(%rsp)
leaq 0x60(%rax), %r13
movq 0x148(%r14), %rax
movq %rax, 0x18(... | /Target/Hexagon/HexagonFrameLowering.cpp |
llvm::HexagonFrameLowering::insertAllocframe(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, unsigned int) const | void HexagonFrameLowering::insertAllocframe(MachineBasicBlock &MBB,
MachineBasicBlock::iterator InsertPt, unsigned NumBytes) const {
MachineFunction &MF = *MBB.getParent();
auto &HST = MF.getSubtarget<HexagonSubtarget>();
auto &HII = *HST.getInstrInfo();
auto &HRI = *HST.getRegisterInfo();
// Check for... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xd8, %rsp
movl %ecx, %ebp
movq %rdx, 0x88(%rsp)
movq %rsi, %r14
movq 0x20(%rsi), %r12
movq 0x10(%r12), %rbx
movq (%rbx), %rax
movq %rbx, %rdi
callq *0x80(%rax)
movq %rax, 0x78(%rsp)
movq (%rbx), %rax
movq %rbx, %rdi
callq *0xc8(%rax)
movq %rax, %r... | /Target/Hexagon/HexagonFrameLowering.cpp |
(anonymous namespace)::HexagonGenExtract::visitBlock(llvm::BasicBlock*) | bool HexagonGenExtract::visitBlock(BasicBlock *B) {
bool Changed = false;
// Depth-first, bottom-up traversal.
for (auto *DTN : children<DomTreeNode*>(DT->getNode(B)))
Changed |= visitBlock(DTN->getBlock());
// Allow limiting the number of generated extracts for debugging purposes.
bool HasCutoff = Extr... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x168, %rsp # imm = 0x168
movq %rsi, %r14
movq %rdi, %r13
movq 0x20(%rdi), %rdi
addq $0x18, %rdi
callq 0xb0422c
movq 0x8(%rax), %rax
movl 0x20(%rax), %ebx
testq %rbx, %rbx
je 0xecd34e
movq 0x18(%rax), %r15
shlq $0x3, %rbx
xorl %r12d, %r1... | /Target/Hexagon/HexagonGenExtract.cpp |
llvm::DenseMapBase<llvm::DenseMap<unsigned int, std::vector<std::pair<unsigned int, unsigned short>, std::allocator<std::pair<unsigned int, unsigned short>>>, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, std::vector<std::pair<unsigned int, unsigned short>, std::allocator<std::pair<un... | void moveFromOldBuckets(BucketT *OldBucketsBegin, BucketT *OldBucketsEnd) {
initEmpty();
// Insert all the old elements.
const KeyT EmptyKey = getEmptyKey();
const KeyT TombstoneKey = getTombstoneKey();
for (BucketT *B = OldBucketsBegin, *E = OldBucketsEnd; B != E; ++B) {
if (!KeyInfoT::isEqu... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movq $0x0, 0x8(%rdi)
movl 0x10(%rdi), %ecx
testq %rcx, %rcx
je 0xed31c7
movq (%r15), %rax
movabsq $0x7ffffffffffffff, %rdx # imm = 0x7FFFFFFFFFFFFFF
addq %rdx, %rcx
andq %rcx, %rdx
andl $0x3, %ecx
negq %rcx
addq %rdx,... | /llvm/ADT/DenseMap.h |
bool llvm::DenseMapBase<llvm::DenseMap<unsigned int, std::vector<std::pair<(anonymous namespace)::IFRecord, (anonymous namespace)::RegisterSet>, std::allocator<std::pair<(anonymous namespace)::IFRecord, (anonymous namespace)::RegisterSet>>>, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned in... | unsigned getNumBuckets() const {
return NumBuckets;
} | movl 0x10(%rdi), %ecx
testl %ecx, %ecx
je 0xed341d
pushq %rbp
pushq %r14
pushq %rbx
movq (%rdi), %rdi
movl (%rsi), %esi
leal (%rsi,%rsi,8), %eax
leal (%rsi,%rax,4), %r8d
decl %ecx
andl %ecx, %r8d
movl $0x1, %r10d
xorl %r9d, %r9d
movl %r8d, %r14d
shlq $0x5, %r14
leaq (%rdi,%r14), %r11
movl (%rdi,%r14), %ebp
cmpl %ebp, %... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::HexagonGenInsert::pruneEmptyLists() | void HexagonGenInsert::pruneEmptyLists() {
// Remove all entries from the map, where the register has no insert forms
// associated with it.
using IterListType = SmallVector<IFMapType::iterator, 16>;
IterListType Prune;
for (IFMapType::iterator I = IFMap.begin(), E = IFMap.end(); I != E; ++I) {
if (I->sec... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x118, %rsp # imm = 0x118
movq %rdi, %rbx
leaq 0x18(%rsp), %r13
movq %r13, -0x10(%r13)
movabsq $0x1000000000, %rax # imm = 0x1000000000
movq %rax, -0x8(%r13)
movq 0x98(%rdi), %rcx
movl 0xa8(%rdi), %edx
movq %rdx, %rax
shlq $0x5, %rax... | /Target/Hexagon/HexagonGenInsert.cpp |
bool llvm::DenseMapBase<llvm::DenseMap<std::pair<unsigned int, unsigned int>, unsigned int, llvm::DenseMapInfo<std::pair<unsigned int, unsigned int>, void>, llvm::detail::DenseMapPair<std::pair<unsigned int, unsigned int>, unsigned int>>, std::pair<unsigned int, unsigned int>, unsigned int, llvm::DenseMapInfo<std::pair... | unsigned getNumBuckets() const {
return NumBuckets;
} | movl 0x10(%rdi), %ecx
testl %ecx, %ecx
je 0xed40d7
pushq %rbp
pushq %r14
pushq %rbx
movq (%rdi), %rdi
movl (%rsi), %r8d
movl 0x4(%rsi), %eax
leal (%r8,%r8,8), %r9d
leal (%r8,%r9,4), %r9d
leal (%rax,%rax,8), %r10d
leal (%rax,%r10,4), %eax
shlq $0x20, %r9
orq %r9, %rax
movabsq $-0x40a7b892e31b1a47, %r10 # imm = 0xBF58476... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<std::pair<unsigned int, unsigned int>, unsigned int, llvm::DenseMapInfo<std::pair<unsigned int, unsigned int>, void>, llvm::detail::DenseMapPair<std::pair<unsigned int, unsigned int>, unsigned int>>, std::pair<unsigned int, unsigned int>, unsigned int, llvm::DenseMapInfo<std::pair<unsi... | void moveFromOldBuckets(BucketT *OldBucketsBegin, BucketT *OldBucketsEnd) {
initEmpty();
// Insert all the old elements.
const KeyT EmptyKey = getEmptyKey();
const KeyT TombstoneKey = getTombstoneKey();
for (BucketT *B = OldBucketsBegin, *E = OldBucketsEnd; B != E; ++B) {
if (!KeyInfoT::isEqu... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movq $0x0, 0x8(%rdi)
movl 0x10(%rdi), %eax
testq %rax, %rax
je 0xed441d
movq (%r15), %rcx
leaq (%rax,%rax,2), %rax
leaq -0xc(,%rax,4), %rax
movabsq $-0x5555555555555555, %rdx # imm = 0xAAAAAAAAAAAAAAAB
mulq %rdx
movq ... | /llvm/ADT/DenseMap.h |
llvm::HexagonDAGToDAGISel::SelectIndexedLoad(llvm::LoadSDNode*, llvm::SDLoc const&) | void HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl) {
SDValue Chain = LD->getChain();
SDValue Base = LD->getBasePtr();
SDValue Offset = LD->getOffset();
int32_t Inc = cast<ConstantSDNode>(Offset.getNode())->getSExtValue();
EVT LoadedVT = LD->getMemoryVT();
unsigned Opcode = 0;
//... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x188, %rsp # imm = 0x188
movq %rdx, 0x50(%rsp)
movq %rsi, %rbx
movq %rdi, %r14
movq 0x28(%rsi), %rax
movups (%rax), %xmm0
movaps %xmm0, 0xe0(%rsp)
movups 0x28(%rax), %xmm0
movaps %xmm0, 0x90(%rsp)
movq 0x50(%rax), %rax
movq 0x58(%rax), ... | /Target/Hexagon/HexagonISelDAGToDAG.cpp |
shuffles::vdeal(llvm::ArrayRef<int>, llvm::ArrayRef<int>, unsigned int, bool) | MaskT vdeal(ArrayRef<int> Vu, ArrayRef<int> Vv, unsigned Size, bool TakeOdd) {
int Len = Vu.size();
MaskT T = vdealvdd(Vu, Vv, Len - 2 * Size);
return vpack(hi(T), lo(T), Size, TakeOdd);
} | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
subq $0x218, %rsp # imm = 0x218
movl %r9d, %r14d
movq %rdi, %rbx
movb 0x240(%rsp), %bpl
movl %edx, %r9d
subl %r14d, %r9d
subl %r14d, %r9d
leaq 0x8(%rsp), %r15
movq %r15, %rdi
callq 0xee9d35
movq (%r15), %rcx
movl 0x8(%r15), %eax
movl %eax, %edx
shrl %edx
xorl %esi,... | /Target/Hexagon/HexagonISelDAGToDAGHVX.cpp |
llvm::HvxSelector::vmuxs(llvm::ArrayRef<unsigned char>, (anonymous namespace)::OpRef, (anonymous namespace)::OpRef, (anonymous namespace)::ResultStack&) | OpRef HvxSelector::vmuxs(ArrayRef<uint8_t> Bytes, OpRef Va, OpRef Vb,
ResultStack &Results) {
DEBUG_WITH_TYPE("isel", {dbgs() << __func__ << '\n';});
MVT ByteTy = getSingleVT(MVT::i8);
MVT BoolTy = MVT::getVectorVT(MVT::i1, HwLen);
const SDLoc &dl(Results.InpNode);
SDValue B = getVect... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x88, %rsp
movq %r8, %r14
movq %rcx, %r12
movq %rdx, %r13
movq %rsi, %rbx
movq %rdi, 0x20(%rsp)
movq %rsi, %rdi
movl $0x5, %esi
callq 0xeead0a
movl %eax, %ebp
movl 0x20(%rbx), %esi
movl $0x2, %edi
callq 0x8f256c
movb %al, 0xf(%rsp)
movq (%r14), %r1... | /Target/Hexagon/HexagonISelDAGToDAGHVX.cpp |
llvm::DenseMapBase<llvm::DenseMap<llvm::SDNode*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::SDNode*, void>, llvm::detail::DenseSetPair<llvm::SDNode*>>, llvm::SDNode*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::SDNode*, void>, llvm::detail::DenseSetPair<llvm::SDNode*>>::clear() | unsigned getNumEntries() const {
return NumEntries;
} | movl 0x8(%rdi), %eax
testl %eax, %eax
jne 0xef5c11
cmpl $0x0, 0xc(%rdi)
je 0xef5ce4
shll $0x2, %eax
movl 0x10(%rdi), %ecx
cmpl %ecx, %eax
setae %al
cmpl $0x41, %ecx
setb %dl
orb %al, %dl
je 0xef5ce6
testq %rcx, %rcx
je 0xef5cdc
movq (%rdi), %rax
movabsq $0x1fffffffffffffff, %rdx # imm = 0x1FFFFFFFFFFFFFFF
addq %rdx, %r... | /llvm/ADT/DenseMap.h |
llvm::HexagonTargetLowering::getTargetNodeName(unsigned int) const | const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
switch ((HexagonISD::NodeType)Opcode) {
case HexagonISD::ADDC: return "HexagonISD::ADDC";
case HexagonISD::SUBC: return "HexagonISD::SUBC";
case HexagonISD::ALLOCA: return "HexagonISD::ALLOCA";
case HexagonI... | addl $0xfffffe1b, %esi # imm = 0xFFFFFE1B
cmpl $0x32, %esi
ja 0xefe10c
movl %esi, %eax
leaq 0x2b87950(%rip), %rcx # 0x3a85a54
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
retq
xorl %eax, %eax
retq
nop
| /Target/Hexagon/HexagonISelLowering.cpp |
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