name string | code string | asm string | file string |
|---|---|---|---|
llvm::HexagonTargetLowering::expandPredicate(llvm::SDValue, llvm::SDLoc const&, llvm::SelectionDAG&) const | SDValue
HexagonTargetLowering::expandPredicate(SDValue Vec32, const SDLoc &dl,
SelectionDAG &DAG) const {
assert(ty(Vec32).getSizeInBits() == 32);
if (isUndef(Vec32))
return DAG.getUNDEF(MVT::i64);
SDValue P = DAG.getBitcast(MVT::v4i8, Vec32);
SDValue X = DAG.getNode(I... | pushq %r14
pushq %rbx
subq $0x28, %rsp
movq %r8, %rbx
movq %rcx, %r14
movl %edx, %r8d
movq %rsi, %rcx
movl 0x18(%rsi), %eax
testl %eax, %eax
movl $0xfffffff5, %edx # imm = 0xFFFFFFF5
movl $0x33, %esi
cmovsl %edx, %esi
cmpl %esi, %eax
jne 0xf015b1
movq %rbx, %rdi
movl $0x8, %esi
xorl %edx, %edx
addq $0x28, %rsp
po... | /Target/Hexagon/HexagonISelLowering.cpp |
llvm::HexagonTargetLowering::insertVector(llvm::SDValue, llvm::SDValue, llvm::SDValue, llvm::SDLoc const&, llvm::MVT, llvm::SelectionDAG&) const | SDValue
HexagonTargetLowering::insertVector(SDValue VecV, SDValue ValV, SDValue IdxV,
const SDLoc &dl, MVT ValTy,
SelectionDAG &DAG) const {
MVT VecTy = ty(VecV);
if (VecTy.getVectorElementType() == MVT::i1)
return insertVectorPred(VecV, Va... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xe8, %rsp
movl %edx, %ebp
movq %rsi, %r12
movq 0x30(%rsi), %rax
movl %edx, %edx
shlq $0x4, %rdx
movzbl (%rax,%rdx), %edx
leaq 0x228c50f(%rip), %rax # 0x318db40
cmpb $0x2, -0x1(%rdx,%rax)
jne 0xf01653
movq %r12, %rsi
movl %ebp, %edx
addq $0xe8, %... | /Target/Hexagon/HexagonISelLowering.cpp |
llvm::HexagonTargetLowering::extractHvxElementPred(llvm::SDValue, llvm::SDValue, llvm::SDLoc const&, llvm::MVT, llvm::SelectionDAG&) const | SDValue
HexagonTargetLowering::extractHvxElementPred(SDValue VecV, SDValue IdxV,
const SDLoc &dl, MVT ResTy, SelectionDAG &DAG) const {
// Implement other return types if necessary.
assert(ResTy == MVT::i1);
unsigned HwLen = Subtarget.getVectorLength();
MVT ByteTy = MVT::getVectorVT(MVT::i8, HwLen);
SD... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x98, %rsp
movq %r9, %rbx
movl %r8d, 0x24(%rsp)
movq %rcx, 0x30(%rsp)
movl %edx, %ebp
movq %rsi, %r13
movq %rdi, %r15
movq 0xd8(%rsp), %r14
movq 0x4e100(%rdi), %rax
cmpl $0x0, 0x13c(%rax)
setle %cl
movb 0x120(%rax), %al
notb %al
orb %cl, %al
movzbl... | /Target/Hexagon/HexagonISelLoweringHVX.cpp |
llvm::HexagonTargetLowering::compressHvxPred(llvm::SDValue, llvm::SDLoc const&, llvm::MVT, llvm::SelectionDAG&) const | SDValue
HexagonTargetLowering::compressHvxPred(SDValue VecQ, const SDLoc &dl,
MVT ResTy, SelectionDAG &DAG) const {
// Given a predicate register VecQ, transfer bits VecQ[0..HwLen-1]
// (i.e. the entire predicate register) to bits [0..HwLen-1] of a
// vector register. The remaining bits of the vector regist... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x748, %rsp # imm = 0x748
movl %r8d, 0x84(%rsp)
movq %rcx, 0x70(%rsp)
movl %edx, %ebx
movq %rsi, %r14
movq %r9, 0x68(%rsp)
movq 0x28(%r9), %rax
movq %rax, 0x78(%rsp)
movq %rdi, 0x60(%rsp)
movq 0x4e100(%rdi), %rax
cmpl $0x0, 0x13c(%rax)
s... | /Target/Hexagon/HexagonISelLoweringHVX.cpp |
llvm::HexagonTargetLowering::LowerHvxInsertSubvector(llvm::SDValue, llvm::SelectionDAG&) const | SDValue
HexagonTargetLowering::LowerHvxInsertSubvector(SDValue Op, SelectionDAG &DAG)
const {
// Idx does not need to be a constant.
SDValue VecV = Op.getOperand(0);
SDValue ValV = Op.getOperand(1);
SDValue IdxV = Op.getOperand(2);
const SDLoc &dl(Op);
MVT VecTy = ty(VecV);
MVT ElemTy = VecTy.getVe... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x48, %rsp
movq %rcx, %r14
movq %rsi, %rbx
movq 0x28(%rsi), %rax
movq (%rax), %rbp
movl 0x8(%rax), %r12d
movq 0x28(%rax), %r13
movl 0x30(%rax), %r15d
movups 0x50(%rax), %xmm0
movaps %xmm0, 0x30(%rsp)
movq 0x48(%rsi), %rsi
movq %rsi, 0x18(%rsp)
test... | /Target/Hexagon/HexagonISelLoweringHVX.cpp |
llvm::HexagonTargetLowering::typeWidenToWider(llvm::MVT, llvm::MVT) const | HexagonTargetLowering::TypePair
HexagonTargetLowering::typeWidenToWider(MVT Ty0, MVT Ty1) const {
// Compare the numbers of elements of two vector types, and widen the
// narrower one to match the number of elements in the wider one.
assert(Ty0.isVector() && Ty1.isVector());
unsigned Len0 = Ty0.getVectorNumEle... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movl %edx, %r14d
movl %esi, %ebx
leal 0x77(%rbx), %eax
cmpb $0x34, %al
ja 0xf124af
leaq 0x2472d50(%rip), %rdi # 0x33851fa
callq 0x1cceae7
movzbl %bl, %r15d
leaq 0x2474356(%rip), %r13 # 0x3386810
movzwl -0x2(%r13,%r15,2), %ebp
leal 0x77(%r1... | /Target/Hexagon/HexagonISelLoweringHVX.cpp |
llvm::HexagonTargetLowering::SplitHvxMemOp(llvm::SDValue, llvm::SelectionDAG&) const | SDValue
HexagonTargetLowering::SplitHvxMemOp(SDValue Op, SelectionDAG &DAG) const {
auto *MemN = cast<MemSDNode>(Op.getNode());
MVT MemTy = MemN->getMemoryVT().getSimpleVT();
if (!isHvxPairTy(MemTy))
return Op;
const SDLoc &dl(Op);
unsigned HwLen = Subtarget.getVectorLength();
MVT SingleTy = typeSplit... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x2f8, %rsp # imm = 0x2F8
movq %rcx, %r13
movl %edx, %r14d
movq %rsi, %rbp
movq %rdi, %r12
movzbl 0x58(%rsi), %r15d
movl %r15d, %esi
callq 0xf06d14
testb %al, %al
je 0xf13d78
movq 0x48(%rbp), %rsi
movq %rsi, 0x90(%rsp)
testq %rsi, %rsi
j... | /Target/Hexagon/HexagonISelLoweringHVX.cpp |
bool llvm::DenseMapBase<llvm::DenseMap<llvm::SDValue, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::SDValue, void>, llvm::detail::DenseSetPair<llvm::SDValue>>, llvm::SDValue, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::SDValue, void>, llvm::detail::DenseSetPair<llvm::SDValue>>::LookupBucketFor<llvm::S... | unsigned getNumBuckets() const {
return NumBuckets;
} | movl 0x10(%rdi), %ecx
testl %ecx, %ecx
je 0xf16ad6
pushq %rbp
pushq %r14
pushq %rbx
movq (%rdi), %rdi
movq (%rsi), %rax
movq %rax, %r8
shrq $0x4, %r8
shrq $0x9, %rax
xorl %eax, %r8d
addl 0x8(%rsi), %r8d
decl %ecx
andl %ecx, %r8d
movl $0x1, %r10d
xorl %r9d, %r9d
movl %r8d, %r14d
shlq $0x4, %r14
leaq (%rdi,%r14), %r11
mo... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::Simplifier::Context::Context(llvm::Instruction*) | Context(Instruction *Exp)
: Ctx(Exp->getParent()->getParent()->getContext()) {
initialize(Exp);
} | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xe8, %rsp
movq %rsi, %r12
movq %rdi, %rbx
leaq 0x10(%rdi), %rax
xorl %r14d, %r14d
movl %r14d, 0x10(%rdi)
movq %r14, 0x18(%rdi)
movq %rax, 0x20(%rdi)
movq %rax, 0x28(%rdi)
movq %r14, 0x30(%rdi)
leaq 0x40(%rdi), %rax
movl %r14d, 0x40(%rdi)
movq %r14... | /Target/Hexagon/HexagonLoopIdiomRecognition.cpp |
bool llvm::DenseMapBase<llvm::DenseMap<llvm::Value*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::Value*, void>, llvm::detail::DenseSetPair<llvm::Value*>>, llvm::Value*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::Value*, void>, llvm::detail::DenseSetPair<llvm::Value*>>::LookupBucketFor<llvm::Value c... | unsigned getNumBuckets() const {
return NumBuckets;
} | movl 0x10(%rdi), %ecx
testl %ecx, %ecx
je 0xf1fb14
pushq %rbx
movq (%rdi), %rdi
movl (%rsi), %r8d
movl %r8d, %eax
shrl $0x4, %eax
shrl $0x9, %r8d
xorl %eax, %r8d
decl %ecx
andl %ecx, %r8d
movl $0x1, %r10d
xorl %r9d, %r9d
movl %r8d, %r11d
leaq (%rdi,%r11,8), %r11
movq (%r11), %rbx
cmpq %rbx, (%rsi)
jne 0xf1fadb
movq %r1... | /llvm/ADT/DenseMap.h |
llvm::FunctionCallee llvm::Module::getOrInsertFunction<llvm::Type*, llvm::Type*, llvm::Type*>(llvm::StringRef, llvm::AttributeList, llvm::Type*, llvm::Type*, llvm::Type*, llvm::Type*) | FunctionCallee getOrInsertFunction(StringRef Name,
AttributeList AttributeList, Type *RetTy,
ArgsTy... Args) {
SmallVector<Type*, sizeof...(ArgsTy)> ArgTys{Args...};
return getOrInsertFunction(Name,
Function... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x48, %rsp
movq %r8, %r12
movq %rcx, %rbx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r13
movaps 0x80(%rsp), %xmm0
leaq 0x20(%rsp), %rdx
movq %r9, -0x18(%rdx)
movups %xmm0, -0x10(%rdx)
leaq 0x30(%rsp), %rcx
movq %rcx, -0x10(%rcx)
movabsq $0x3000000... | /llvm/IR/Module.h |
llvm::cl::opt<int, false, llvm::cl::parser<int>>::opt<char [10], llvm::cl::initializer<int>, llvm::cl::OptionHidden, llvm::cl::desc>(char const (&) [10], llvm::cl::initializer<int> const&, llvm::cl::OptionHidden const&, llvm::cl::desc const&) | explicit opt(const Mods &... Ms)
: Option(llvm::cl::Optional, NotHidden), Parser(*this) {
apply(this, Ms...);
done();
} | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %r8, %rbx
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %r14
xorl %esi, %esi
xorl %edx, %edx
callq 0x7c77e2
movl $0x0, 0x80(%r14)
xorps %xmm0, %xmm0
movups %xmm0, 0x88(%r14)
movb $0x0, 0x94(%r14)
leaq 0x47d13b6(%rip), %rax # 0x56f2650
movq %rax,... | /llvm/Support/CommandLine.h |
llvm::initializeHexagonOptAddrModePass(llvm::PassRegistry&) | bool HexagonOptAddrMode::hasRepForm(MachineInstr &MI, unsigned TfrDefR) {
const MCInstrDesc &MID = MI.getDesc();
if ((!MID.mayStore() && !MID.mayLoad()) || HII->isPredicated(MI))
return false;
if (MID.mayStore()) {
MachineOperand StOp = MI.getOperand(MI.getNumOperands() - 1);
if (StOp.isReg() && StO... | pushq %rax
movq %rsp, %rdx
movq %rdi, (%rdx)
leaq 0x498d810(%rip), %rdi # 0x58b00a0
leaq 0x7(%rip), %rsi # 0xf2289e
callq 0x90ae4f
popq %rax
retq
| /Target/Hexagon/HexagonOptAddrMode.cpp |
llvm::DenseMap<llvm::MachineInstr*, bool, llvm::DenseMapInfo<llvm::MachineInstr*, void>, llvm::detail::DenseMapPair<llvm::MachineInstr*, bool>>::shrink_and_clear() | void shrink_and_clear() {
unsigned OldNumBuckets = NumBuckets;
unsigned OldNumEntries = NumEntries;
this->destroyAll();
// Reduce the number of buckets.
unsigned NewNumBuckets = 0;
if (OldNumEntries)
NewNumBuckets = std::max(64, 1 << (Log2_32_Ceil(OldNumEntries) + 1));
if (NewNumBucke... | pushq %rbp
pushq %rbx
pushq %rax
movq %rdi, %rbx
movl 0x8(%rdi), %eax
movl 0x10(%rdi), %esi
testl %eax, %eax
je 0xf25a82
decl %eax
je 0xf25a86
bsrl %eax, %eax
xorl $0x1f, %eax
jmp 0xf25a8b
xorl %ebp, %ebp
jmp 0xf25aa1
movl $0x20, %eax
movb $0x21, %cl
subb %al, %cl
movl $0x1, %eax
shll %cl, %eax
cmpl $0x41, %eax
movl $0... | /llvm/ADT/DenseMap.h |
initializeHexagonPeepholePassOnce(llvm::PassRegistry&) | bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(MF.getFunction()))
return false;
QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());
QRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
MRI = &MF.getRegInfo();
DenseMap<unsigned, unsig... | pushq %r14
pushq %rbx
pushq %rax
movq %rdi, %rbx
movl $0x50, %edi
callq 0x751940
movq %rax, %r14
leaq 0x2b5fcba(%rip), %rax # 0x3a86577
movq %rax, (%r14)
movl $0x10, %eax
movq %rax, 0x8(%r14)
leaq 0x2b5fbb8(%rip), %rcx # 0x3a86488
movq %rcx, 0x10(%r14)
movq %rax, 0x18(%r14)
leaq 0x4989ad5(%rip), %rax # 0x58b03b4
... | /Target/Hexagon/HexagonPeephole.cpp |
(anonymous namespace)::HexagonPeephole::HexagonPeephole() | HexagonPeephole() : MachineFunctionPass(ID) {
initializeHexagonPeepholePass(*PassRegistry::getPassRegistry());
} | pushq %rax
xorl %eax, %eax
movq %rax, 0x8(%rdi)
leaq 0x4989a66(%rip), %rcx # 0x58b03b4
movq %rcx, 0x10(%rdi)
movl $0x2, 0x18(%rdi)
xorps %xmm0, %xmm0
movups %xmm0, 0x20(%rdi)
movq %rax, 0x30(%rdi)
leaq 0x480dee5(%rip), %rax # 0x5734850
movq %rax, (%rdi)
callq 0x1a82116
movq %rsp, %rdx
movq %rax, (%rdx)
leaq 0x4989a... | /Target/Hexagon/HexagonPeephole.cpp |
llvm::cl::opt<bool, false, llvm::cl::parser<bool>>::opt<char [12], llvm::cl::OptionHidden, llvm::cl::initializer<bool>, llvm::cl::desc>(char const (&) [12], llvm::cl::OptionHidden const&, llvm::cl::initializer<bool> const&, llvm::cl::desc const&) | explicit opt(const Mods &... Ms)
: Option(llvm::cl::Optional, NotHidden), Parser(*this) {
apply(this, Ms...);
done();
} | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %r8, %rbx
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %r14
xorl %ebp, %ebp
xorl %esi, %esi
xorl %edx, %edx
callq 0x7c77e2
movb %bpl, 0x80(%r14)
xorps %xmm0, %xmm0
movups %xmm0, 0x88(%r14)
movb %bpl, 0x91(%r14)
leaq 0x47b911... | /llvm/Support/CommandLine.h |
llvm::createHexagonSplitDoubleRegs() | FunctionPass *llvm::createHexagonSplitDoubleRegs() {
return new HexagonSplitDoubleRegs();
} | pushq %rax
movl $0x58, %edi
callq 0x751940
xorl %ecx, %ecx
movq %rcx, 0x8(%rax)
leaq 0x4986590(%rip), %rdx # 0x58b0854
movq %rdx, 0x10(%rax)
movl $0x2, 0x18(%rax)
xorps %xmm0, %xmm0
movups %xmm0, 0x20(%rax)
movq %rcx, 0x30(%rax)
leaq 0x480a84f(%rip), %rcx # 0x5734b30
movq %rcx, (%rax)
movups %xmm0, 0x38(%rax)
popq ... | /Target/Hexagon/HexagonSplitDouble.cpp |
llvm::rdf::CopyPropagation::recordCopy(llvm::rdf::NodeAddr<llvm::rdf::StmtNode*>, std::map<llvm::rdf::RegisterRef, llvm::rdf::RegisterRef, std::less<llvm::rdf::RegisterRef>, std::allocator<std::pair<llvm::rdf::RegisterRef const, llvm::rdf::RegisterRef>>>&) | void CopyPropagation::recordCopy(NodeAddr<StmtNode*> SA, EqualityMap &EM) {
CopyMap.insert(std::make_pair(SA.Id, EM));
Copies.push_back(SA.Id);
for (auto I : EM) {
auto FS = DefM.find(I.second.Reg);
if (FS == DefM.end() || FS->second.empty())
continue; // Undefined source
RDefMap[I.second][SA.I... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x58, %rsp
movq %rcx, %rbx
movq %rdi, %r14
leaq 0x50(%rsp), %r15
movq %rsi, -0x8(%r15)
movl %edx, (%r15)
leaq 0x88(%rdi), %r12
leaq 0x18(%rsp), %r13
movl %edx, -0x8(%r13)
movq %r13, %rdi
movq %rcx, %rsi
callq 0xf3398c
leaq 0x10(%rsp), %rbp
movq %r1... | /Target/Hexagon/RDFCopy.cpp |
llvm::BitTracker::RegisterCell::cl(bool) const | uint16_t BT::RegisterCell::cl(bool B) const {
uint16_t W = width();
uint16_t C = 0;
BitValue V = B;
while (C < W && Bits[W-(C+1)] == V)
C++;
return C;
} | movl 0x8(%rdi), %ecx
testw %cx, %cx
je 0xf369a9
movzwl %cx, %eax
incl %esi
movq (%rdi), %rdx
leaq (%rax,%rax,2), %rax
leaq (%rdx,%rax,4), %rdx
addq $-0x8, %rdx
xorl %eax, %eax
movl -0x4(%rdx), %edi
cmpl %esi, %edi
jne 0xf369a8
cmpl $0x3, %edi
jne 0xf3699b
cmpl $0x0, (%rdx)
jne 0xf369a8
incl %eax
addq $-0xc, %rdx
cmpw %... | /Target/Hexagon/BitTracker.cpp |
llvm::BitTracker::MachineEvaluator::eMLS(llvm::BitTracker::RegisterCell const&, llvm::BitTracker::RegisterCell const&) const | BT::RegisterCell BT::MachineEvaluator::eMLS(const RegisterCell &A1,
const RegisterCell &A2) const {
uint16_t W = A1.width() + A2.width();
uint16_t Z = A1.ct(false) + A2.ct(false);
RegisterCell Res(W);
Res.fill(0, Z, BitValue::Zero);
Res.fill(Z, W, BitValue::self());
return Res;
} | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
movq %rdi, %rbx
movl 0x8(%rdx), %r12d
movl $0xffff, %eax # imm = 0xFFFF
movl 0x8(%rcx), %r15d
leal (%r15,%r12), %ebp
testw %r12w, %r12w
je 0xf3722a
movq %r12, %rsi
andq %rax, %rsi
movq (%rdx), %rdi
xorl %edx, %edx
cmpl $0x1, (%rdi)
jne 0xf3722f
incq %rdx
... | /Target/Hexagon/BitTracker.cpp |
llvm::DenseMapBase<llvm::DenseMap<llvm::MachineInstr const*, unsigned int, llvm::DenseMapInfo<llvm::MachineInstr const*, void>, llvm::detail::DenseMapPair<llvm::MachineInstr const*, unsigned int>>, llvm::MachineInstr const*, unsigned int, llvm::DenseMapInfo<llvm::MachineInstr const*, void>, llvm::detail::DenseMapPair<l... | iterator find(const_arg_type_t<KeyT> Val) {
BucketT *TheBucket;
if (LookupBucketFor(Val, TheBucket))
return makeIterator(TheBucket,
shouldReverseIterate<KeyT>() ? getBuckets()
: getBucketsEnd(),
*thi... | pushq %r14
pushq %rbx
subq $0x18, %rsp
movq %rdi, %rbx
leaq 0x8(%rsp), %rax
movq %rsi, (%rax)
leaq 0x10(%rsp), %r14
movq %rax, %rsi
movq %r14, %rdx
callq 0xf3a2d6
movl 0x10(%rbx), %edx
shlq $0x4, %rdx
addq (%rbx), %rdx
testb %al, %al
movq (%r14), %rax
cmoveq %rdx, %rax
addq $0x18, %rsp
popq %rbx
popq %r14
retq
nop
| /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::MachineInstr const*, unsigned int, llvm::DenseMapInfo<llvm::MachineInstr const*, void>, llvm::detail::DenseMapPair<llvm::MachineInstr const*, unsigned int>>, llvm::MachineInstr const*, unsigned int, llvm::DenseMapInfo<llvm::MachineInstr const*, void>, llvm::detail::DenseMapPair<l... | void moveFromOldBuckets(BucketT *OldBucketsBegin, BucketT *OldBucketsEnd) {
initEmpty();
// Insert all the old elements.
const KeyT EmptyKey = getEmptyKey();
const KeyT TombstoneKey = getTombstoneKey();
for (BucketT *B = OldBucketsBegin, *E = OldBucketsEnd; B != E; ++B) {
if (!KeyInfoT::isEqu... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x10, %rsp
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movq $0x0, 0x8(%rdi)
movl 0x10(%rdi), %ecx
testq %rcx, %rcx
je 0xf3a67d
movq (%r15), %rax
movabsq $0xfffffffffffffff, %rdx # imm = 0xFFFFFFFFFFFFFFF
addq %rdx, %rcx
andq %rcx, %rdx
andl $0x1, %ecx
neg... | /llvm/ADT/DenseMap.h |
llvm::BasicTTIImplBase<llvm::LanaiTTIImpl>::getCmpSelInstrCost(unsigned int, llvm::Type*, llvm::Type*, llvm::CmpInst::Predicate, llvm::TargetTransformInfo::TargetCostKind, llvm::Instruction const*) | InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
CmpInst::Predicate VecPred,
TTI::TargetCostKind CostKind,
const Instruction *I = nullptr) {
const TargetLoweringBase *TLI = ge... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x38, %rsp
movl %r9d, %r13d
movl %r8d, %r12d
movq %rcx, 0x18(%rsp)
movq %rdx, %r14
movl %esi, %ebp
movq %rdi, %r15
movq 0x18(%rdi), %rbx
movq %rbx, %rdi
callq 0x18c2518
testl %r13d, %r13d
jne 0xf44423
movq %rbx, %r13
movl %ebp, 0x10(%rsp)
movl %r12... | /llvm/CodeGen/BasicTTIImpl.h |
llvm::BasicTTIImplBase<llvm::LanaiTTIImpl>::isTypeLegal(llvm::Type*) | bool isTypeLegal(Type *Ty) {
EVT VT = getTLI()->getValueType(DL, Ty, /*AllowUnknown=*/true);
return getTLI()->isTypeLegal(VT);
} | pushq %rbx
movq %rsi, %rdx
movq %rdi, %rbx
movq 0x8(%rdi), %rsi
movq 0x18(%rdi), %rdi
movl $0x1, %ecx
callq 0x8f1f84
testb %al, %al
je 0xf479a1
movq 0x18(%rbx), %rcx
movzbl %al, %eax
cmpq $0x0, 0x68(%rcx,%rax,8)
setne %al
jmp 0xf479a3
xorl %eax, %eax
popq %rbx
retq
nop
| /llvm/CodeGen/BasicTTIImpl.h |
llvm::LanaiInstrInfo::copyPhysReg(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::DebugLoc const&, llvm::MCRegister, llvm::MCRegister, bool) const | void LanaiInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator Position,
const DebugLoc &DL,
MCRegister DestinationRegister,
MCRegister SourceRegister,
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x58, %rsp
movl %r9d, %ebx
movl %r8d, %ebp
movq %rcx, %r13
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
leaq 0x47ecdb1(%rip), %rax # 0x57363c8
movq (%rax), %rdi
movl %r8d, %esi
movl %r9d, %edx
callq 0xd2fefe
movq (%r13), %rsi
movq %rsi, 0x8(%r... | /Target/Lanai/LanaiInstrInfo.cpp |
llvm::LanaiInstrInfo::analyzeSelect(llvm::MachineInstr const&, llvm::SmallVectorImpl<llvm::MachineOperand>&, unsigned int&, unsigned int&, bool&) const | bool LanaiInstrInfo::analyzeSelect(const MachineInstr &MI,
SmallVectorImpl<MachineOperand> &Cond,
unsigned &TrueOp, unsigned &FalseOp,
bool &Optimizable) const {
assert(MI.getOpcode() == Lanai::SELECT && "unknown ... | pushq %r14
pushq %rbx
pushq %rax
movq %r9, %rbx
movq %rdx, %r14
movl $0x1, (%rcx)
movl $0x2, (%r8)
movq 0x20(%rsi), %rsi
addq $0x60, %rsi
movl $0x1, %edx
movq %r14, %rdi
callq 0xa48af6
movq (%r14), %rcx
movl 0x8(%r14), %edx
shlq $0x5, %rdx
movups (%rax), %xmm0
movups 0x10(%rax), %xmm1
movups %xmm1, 0x10(%rcx,%rdx)
movu... | /Target/Lanai/LanaiInstrInfo.cpp |
llvm::LanaiInstrInfo::isLoadFromStackSlot(llvm::MachineInstr const&, int&) const | Register LanaiInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const {
if (MI.getOpcode() == Lanai::LDW_RI)
if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
MI.getOperand(2).getImm() == 0) {
FrameIndex = MI.getOperand(1).g... | xorl %eax, %eax
cmpw $0x14d, 0x44(%rsi) # imm = 0x14D
jne 0xf4abcb
movq 0x20(%rsi), %rcx
cmpb $0x5, 0x20(%rcx)
jne 0xf4abcb
cmpb $0x1, 0x40(%rcx)
jne 0xf4abcb
cmpq $0x0, 0x50(%rcx)
je 0xf4abcc
retq
movl 0x30(%rcx), %eax
movl %eax, (%rdx)
movl 0x4(%rcx), %eax
retq
nop
| /Target/Lanai/LanaiInstrInfo.cpp |
llvm::BasicTTIImplBase<llvm::LoongArchTTIImpl>::getCastInstrCost(unsigned int, llvm::Type*, llvm::Type*, llvm::TargetTransformInfo::CastContextHint, llvm::TargetTransformInfo::TargetCostKind, llvm::Instruction const*) | InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
TTI::CastContextHint CCH,
TTI::TargetCostKind CostKind,
const Instruction *I = nullptr) {
if (BaseT::getCastInstrCost(Opcode, Dst, Src, CCH... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xa8, %rsp
movl %r9d, %ebx
movl %r8d, %r15d
movq %rcx, %r13
movq %rdx, %r12
movl %esi, %ebp
movq %rdi, %r14
movq 0xe0(%rsp), %rax
addq $0x8, %rdi
movq %rax, (%rsp)
movq %rdi, 0x88(%rsp)
callq 0x90877e
xorl %ecx, %ecx
xorl %esi, %esi
testq %rax, %ra... | /llvm/CodeGen/BasicTTIImpl.h |
(anonymous namespace)::LoongArchPreRAExpandPseudo::expandPcalau12iInstPair(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>&, unsigned int, unsigned int, unsigned int) | bool LoongArchPreRAExpandPseudo::expandPcalau12iInstPair(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
MachineBasicBlock::iterator &NextMBBI, unsigned FlagsHi,
unsigned SecondOpcode, unsigned FlagsLo) {
MachineFunction *MF = MBB.getParent();
MachineInstr &MI = *MBBI;
DebugLoc DL = MI.getD... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x88, %rsp
movl %r9d, 0x2c(%rsp)
movl %r8d, 0x28(%rsp)
movl %ecx, %ebp
movq %rdx, %rbx
movq %rsi, %r15
movq %rdi, 0x30(%rsp)
movq 0x20(%rsi), %r14
movq 0x38(%rdx), %rsi
movq %rsi, 0x18(%rsp)
testq %rsi, %rsi
je 0xf63995
leaq 0x18(%rsp), %rdi
movl $... | /Target/LoongArch/LoongArchExpandPseudoInsts.cpp |
llvm::MachineInstrBuilder::addDisp(llvm::MachineOperand const&, long, unsigned char) const | const MachineInstrBuilder &addDisp(const MachineOperand &Disp, int64_t off,
unsigned char TargetFlags = 0) const {
// If caller specifies new TargetFlags then use it, otherwise the
// default behavior is to copy the target flags from the existing
// MachineOperand. This ... | pushq %rbx
subq $0x20, %rsp
movq %rdi, %rbx
testl %ecx, %ecx
jne 0xf63c14
movl (%rsi), %eax
movl %eax, %edi
shrl $0x8, %edi
xorl %ecx, %ecx
testb %al, %al
cmovnel %edi, %ecx
movzbl (%rsi), %eax
decl %eax
leaq 0x2b24b5c(%rip), %rdi # 0x3a8877c
movslq (%rdi,%rax,4), %rax
addq %rdi, %rax
jmpq *%rax
addq 0x10(%rsi), %rdx... | /llvm/CodeGen/MachineInstrBuilder.h |
(anonymous namespace)::LoongArchExpandPseudo::expandLargeAddressLoad(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>&, unsigned int, unsigned int, llvm::MachineOperand const&, llvm::Register, bool) | bool LoongArchExpandPseudo::expandLargeAddressLoad(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
MachineBasicBlock::iterator &NextMBBI, unsigned LastOpcode,
unsigned IdentifyingMO, const MachineOperand &Symbol, Register DestReg,
bool EraseFromParent) {
// Code Sequence:
//
// Part1: p... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xe8, %rsp
movq %r9, 0xe0(%rsp)
movq %rdx, 0x18(%rsp)
movq %rsi, %r14
movq %rdi, %r15
cmpl $0x12, %r8d
movl %ecx, 0x7c(%rsp)
jg 0xf651d2
cmpl $0x4, %r8d
je 0xf651f8
cmpl $0x7, %r8d
jne 0xf65218
movl $0x9, %eax
movq %rax, 0x68(%rsp)
movl $0xa, %eax
... | /Target/LoongArch/LoongArchExpandPseudoInsts.cpp |
initializeLoongArchDAGToDAGISelLegacyPassOnce(llvm::PassRegistry&) | void LoongArchDAGToDAGISel::Select(SDNode *Node) {
// If we have a custom node, we have already selected.
if (Node->isMachineOpcode()) {
LLVM_DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n");
Node->setNodeId(-1);
return;
}
// Instruction Selection not handled by the auto-generated tablege... | pushq %r14
pushq %rbx
pushq %rax
movq %rdi, %rbx
movl $0x50, %edi
callq 0x751940
movq %rax, %r14
leaq 0x2b2310d(%rip), %rax # 0x3a88a64
movq %rax, (%r14)
movq $0x30, 0x8(%r14)
leaq 0x2b2312c(%rip), %rax # 0x3a88a95
movq %rax, 0x10(%r14)
movq $0xe, 0x18(%r14)
leaq 0x494b3a6(%rip), %rax # 0x58b0d22
movq %rax, 0x20(... | /Target/LoongArch/LoongArchISelDAGToDAG.cpp |
llvm::LoongArchRegisterInfo::getReservedRegs(llvm::MachineFunction const&) const | BitVector
LoongArchRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
const LoongArchFrameLowering *TFI = getFrameLowering(MF);
BitVector Reserved(getNumRegs());
// Use markSuperRegs to ensure any register aliases are also reserved
markSuperRegs(Reserved, LoongArch::R0); // zero
markSuperRegs(... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %rdx, %r15
movq %rsi, %r14
movq %rdi, %rbx
movq 0x10(%rdx), %rdi
movq (%rdi), %rax
callq *0x88(%rax)
movq %rax, %r12
movl 0x10(%r14), %r13d
leal 0x3f(%r13), %esi
shrl $0x6, %esi
leaq 0x10(%rbx), %rax
movq %rax, (%rbx)
movabsq $0x600000000, %rax # imm = 0x... | /Target/LoongArch/LoongArchRegisterInfo.cpp |
llvm::LoongArchInstrInfo::storeRegToStackSlot(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::Register, bool, int, llvm::TargetRegisterClass const*, llvm::TargetRegisterInfo const*, llvm::Register) const | void LoongArchInstrInfo::storeRegToStackSlot(
MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register SrcReg,
bool IsKill, int FI, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI, Register VReg) const {
MachineFunction *MF = MBB.getParent();
MachineFrameInfo &MFI = MF->getFrameInfo(... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xc8, %rsp
movl %r9d, %ebx
movl %r8d, 0x30(%rsp)
movl %ecx, 0x34(%rsp)
movq %rdx, 0x58(%rsp)
movq %rdi, 0x48(%rsp)
movq 0x100(%rsp), %rax
movq %rsi, 0x50(%rsp)
movq 0x20(%rsi), %rbp
movq 0x38(%rbp), %r13
movq (%rax), %rax
movzwl 0x18(%rax), %ecx
le... | /Target/LoongArch/LoongArchInstrInfo.cpp |
llvm::LoongArchTargetLowering::analyzeInputArgs(llvm::MachineFunction&, llvm::CCState&, llvm::SmallVectorImpl<llvm::ISD::InputArg> const&, bool, bool (*)(llvm::DataLayout const&, llvm::LoongArchABI::ABI, unsigned int, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&, bool, bool, llvm::Type*)... | void LoongArchTargetLowering::analyzeInputArgs(
MachineFunction &MF, CCState &CCInfo,
const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet,
LoongArchCCAssignFn Fn) const {
FunctionType *FType = MF.getFunction().getFunctionType();
for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
MVT ArgVT = Ins[i... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x68, %rsp
movq %r9, 0x60(%rsp)
movl %r8d, 0x30(%rsp)
movq %rdx, 0x58(%rsp)
movq %rsi, 0x40(%rsp)
movl 0x8(%rcx), %eax
testq %rax, %rax
je 0xf802e9
movq %rcx, %r12
movq 0x40(%rsp), %rdx
movq (%rdx), %rdx
movq 0x18(%rdx), %rdx
movq %rdx, 0x38(%rsp)
... | /Target/LoongArch/LoongArchISelLowering.cpp |
llvm::LoongArchTargetLowering::LowerFormalArguments(llvm::SDValue, unsigned int, bool, llvm::SmallVectorImpl<llvm::ISD::InputArg> const&, llvm::SDLoc const&, llvm::SelectionDAG&, llvm::SmallVectorImpl<llvm::SDValue>&) const | SDValue LoongArchTargetLowering::LowerFormalArguments(
SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
MachineFunction &MF = DAG.getMachineFunction();
switch (CallConv) {
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x3d8, %rsp # imm = 0x3D8
movq %r9, 0x80(%rsp)
movl %r8d, 0xf0(%rsp)
movl %ecx, %ebp
movq %rdi, 0x108(%rsp)
movq 0x418(%rsp), %rax
movq %rsi, 0x70(%rsp)
movl %edx, 0x78(%rsp)
movq 0x28(%rax), %r14
cmpl $0xa, %ecx
jne 0xf80433
movq 0x10(%... | /Target/LoongArch/LoongArchISelLowering.cpp |
llvm::LoongArchTargetLowering::LowerCall(llvm::TargetLowering::CallLoweringInfo&, llvm::SmallVectorImpl<llvm::SDValue>&) const | SDValue
LoongArchTargetLowering::LowerCall(CallLoweringInfo &CLI,
SmallVectorImpl<SDValue> &InVals) const {
SelectionDAG &DAG = CLI.DAG;
SDLoc &DL = CLI.DL;
SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
SmallVectorImpl<ISD... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x768, %rsp # imm = 0x768
movq %rdx, 0x1e0(%rsp)
movq %rsi, %r13
movq %rdi, %rbx
movq 0x50(%rsi), %r12
leaq 0x70(%rsi), %rax
movq %rax, 0xf8(%rsp)
movq (%rsi), %rax
movq %rax, 0xb8(%rsp)
movl 0x8(%rsi), %eax
movl %eax, 0x98(%rsp)
movq 0x... | /Target/LoongArch/LoongArchISelLowering.cpp |
llvm::MipsAsmPrinter::EmitSwapFPIntRetval(llvm::MCSubtargetInfo const&, llvm::Mips16HardFloatInfo::FPReturnVariant, bool) | void MipsAsmPrinter::EmitSwapFPIntRetval(
const MCSubtargetInfo &STI, Mips16HardFloatInfo::FPReturnVariant RV,
bool LE) {
using namespace Mips16HardFloatInfo;
unsigned MovOpc = Mips::MFC1;
switch (RV) {
case FRet:
EmitInstrRegReg(STI, MovOpc, Mips::V0, Mips::F0);
break;
case DRet:
EmitMov... | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
cmpl $0x3, %edx
ja 0xf8d0fa
movq %rsi, %rbx
movq %rdi, %r14
movl %edx, %eax
leaq 0x2b12c09(%rip), %rdx # 0x3a9fc20
movslq (%rdx,%rax,4), %rax
addq %rdx, %rax
jmpq *%rax
movzbl %cl, %ebp
movl $0x15a, %ecx # imm = 0x15A
subl %ebp, %ecx
addl $0x159, %ebp ... | /Target/Mips/MipsAsmPrinter.cpp |
LLVMInitializeMipsTarget | LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsTarget() {
// Register the target.
RegisterTargetMachine<MipsebTargetMachine> X(getTheMipsTarget());
RegisterTargetMachine<MipselTargetMachine> Y(getTheMipselTarget());
RegisterTargetMachine<MipsebTargetMachine> A(getTheMips64Target());
RegisterTargetMachine<Mip... | pushq %r14
pushq %rbx
pushq %rax
callq 0x168067f
leaq 0xfb4(%rip), %rbx # 0xf9194c
movq %rbx, 0x60(%rax)
callq 0x168069d
leaq 0x104c(%rip), %r14 # 0xf919f4
movq %r14, 0x60(%rax)
callq 0x16806bb
movq %rbx, 0x60(%rax)
callq 0x16806d9
movq %r14, 0x60(%rax)
callq 0x1a82116
movq %rax, %rbx
movq %rax, %rdi
callq 0... | /Target/Mips/MipsTargetMachine.cpp |
(anonymous namespace)::MicroMipsSizeReduce::ReduceArithmeticInstructions((anonymous namespace)::ReduceEntryFunArgs*) | bool MicroMipsSizeReduce::ReduceArithmeticInstructions(
ReduceEntryFunArgs *Arguments) {
MachineInstr *MI = Arguments->MI;
const ReduceEntry &Entry = Arguments->Entry;
if (!isMMThreeBitGPRegister(MI->getOperand(0)) ||
!isMMThreeBitGPRegister(MI->getOperand(1)) ||
!isMMThreeBitGPRegister(MI->getO... | pushq %r15
pushq %r14
pushq %rbx
movq (%rdi), %rbx
movq 0x8(%rdi), %r14
movq 0x20(%rbx), %r15
movq %r15, %rdi
callq 0xf9bbe4
testb %al, %al
je 0xf9b3bf
leaq 0x20(%r15), %rdi
callq 0xf9bbe4
testb %al, %al
je 0xf9b3bf
addq $0x40, %r15
movq %r15, %rdi
callq 0xf9bbe4
testb %al, %al
je 0xf9b3bf
movq %rbx, %rdi
movq %r14, %r... | /Target/Mips/MicroMipsSizeReduction.cpp |
llvm::MipsCCState::PreAnalyzeCallResultForVectorFloat(llvm::SmallVectorImpl<llvm::ISD::InputArg> const&, llvm::Type const*) | void MipsCCState::PreAnalyzeCallResultForVectorFloat(
const SmallVectorImpl<ISD::InputArg> &Ins, const Type *RetTy) {
for (unsigned i = 0; i < Ins.size(); ++i) {
OriginalRetWasFloatVector.push_back(originalTypeIsVectorFloat(RetTy));
}
} | cmpl $0x0, 0x8(%rsi)
je 0xfa4208
pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
addq $0x1e8, %r15 # imm = 0x1E8
xorl %ebp, %ebp
movl $0xfe, %r12d
movl 0x8(%rbx), %eax
andl %r12d, %eax
cmpl $0x12, %eax
jne 0xfa41da
movq 0x10(%rbx), %rax
movq (%rax), %rax... | /Target/Mips/MipsCCState.cpp |
llvm::cl::opt<CompactBranchPolicy, false, llvm::cl::parser<CompactBranchPolicy>>::getValueExpectedFlagDefault() const | enum ValueExpected getValueExpectedFlagDefault() const {
// If there is an ArgStr specified, then we are of the form:
//
// -opt=O2 or -opt O2 or -optO2
//
// In which case, the value is required. Otherwise if an arg str has not
// been specified, we are of the form:
//
// -... | movq 0xa0(%rdi), %rcx
xorl %eax, %eax
cmpq $0x1, 0x18(%rcx)
adcl $0x2, %eax
retq
| /llvm/Support/CommandLine.h |
llvm::MipsTargetLowering::emitLDR_W(llvm::MachineInstr&, llvm::MachineBasicBlock*) const | MachineBasicBlock *MipsTargetLowering::emitLDR_W(MachineInstr &MI,
MachineBasicBlock *BB) const {
MachineFunction *MF = BB->getParent();
MachineRegisterInfo &MRI = MF->getRegInfo();
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
const bool IsLittle = Subt... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xb8, %rsp
movq %rsi, %r14
movq %rdi, %r15
movq %rdx, 0x20(%rsp)
movq 0x20(%rdx), %rax
movq 0x28(%rax), %r12
movq 0x4e0f8(%rdi), %rdi
movq (%rdi), %rax
callq *0x80(%rax)
movq %rax, 0x48(%rsp)
movq 0x4e0f8(%r15), %rax
movb 0x128(%rax), %al
movb %al,... | /Target/Mips/MipsISelLowering.cpp |
llvm::MipsTargetLowering::emitSTR_D(llvm::MachineInstr&, llvm::MachineBasicBlock*) const | MachineBasicBlock *MipsTargetLowering::emitSTR_D(MachineInstr &MI,
MachineBasicBlock *BB) const {
MachineFunction *MF = BB->getParent();
MachineRegisterInfo &MRI = MF->getRegInfo();
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
const bool IsLittle = Subt... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xf8, %rsp
movq %rdx, %r14
movq %rsi, %rbx
movq %rdi, %r15
movq 0x20(%rdx), %rax
movq 0x28(%rax), %rbp
movq 0x4e0f8(%rdi), %rdi
movq (%rdi), %rax
callq *0x80(%rax)
movq %rax, 0x28(%rsp)
movq 0x4e0f8(%r15), %rax
movb 0x128(%rax), %al
movb %al, 0x68(... | /Target/Mips/MipsISelLowering.cpp |
llvm::SDValue llvm::MipsTargetLowering::getAddrNonPIC<llvm::JumpTableSDNode>(llvm::JumpTableSDNode*, llvm::SDLoc const&, llvm::EVT, llvm::SelectionDAG&) const | SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty,
SelectionDAG &DAG) const {
SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
return DAG.getNode(ISD::ADD, DL, Ty,
DAG.getNode... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x78, %rsp
movq %r9, %r14
movq %r8, %rbx
movl %ecx, %ebp
movq %rdx, 0x30(%rsp)
movq %rsi, %r12
movl 0x58(%rsi), %esi
movq %r9, %rdi
movl %ecx, %edx
movq %r8, %rcx
movl $0x1, %r8d
movl $0x4, %r9d
callq 0x1f30f8c
movq %rax, %r13
movl %edx, %r15d
movl... | /Target/Mips/MipsISelLowering.h |
(anonymous namespace)::MipsPreLegalizerCombiner::MipsPreLegalizerCombiner() | MipsPreLegalizerCombiner::MipsPreLegalizerCombiner() : MachineFunctionPass(ID) {
initializeMipsPreLegalizerCombinerPass(*PassRegistry::getPassRegistry());
} | pushq %rax
xorl %eax, %eax
movq %rax, 0x8(%rdi)
leaq 0x48d4eee(%rip), %rcx # 0x58b2998
movq %rcx, 0x10(%rdi)
movl $0x2, 0x18(%rdi)
xorps %xmm0, %xmm0
movups %xmm0, 0x20(%rdi)
movq %rax, 0x30(%rdi)
leaq 0x47620e9(%rip), %rax # 0x573fbb0
movq %rax, (%rdi)
callq 0x1a82116
movq %rsp, %rdx
movq %rax, (%rdx)
leaq 0x48d4e... | /Target/Mips/MipsPreLegalizerCombiner.cpp |
(anonymous namespace)::MipsPreLegalizerCombiner::getAnalysisUsage(llvm::AnalysisUsage&) const | void MipsPreLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<TargetPassConfig>();
AU.addRequired<GISelKnownBitsAnalysis>();
AU.addPreserved<GISelKnownBitsAnalysis>();
AU.setPreservesCFG();
getSelectionDAGFallbackAnalysisUsage(AU);
MachineFunctionPass::getAnalysisUsage(AU);
} | pushq %r15
pushq %r14
pushq %rbx
movq %rsi, %rbx
movq %rdi, %r14
leaq 0x48f8996(%rip), %rsi # 0x58d64d4
movq %rbx, %rdi
callq 0x1a7c8da
leaq 0x4905943(%rip), %r15 # 0x58e3490
movq %rbx, %rdi
movq %r15, %rsi
callq 0x1a7c8da
leaq 0x70(%rbx), %rsi
movq %rbx, %rdi
movq %r15, %rdx
callq 0x945e5e
movq %rbx, %rdi
callq 0x... | /Target/Mips/MipsPreLegalizerCombiner.cpp |
(anonymous namespace)::MipsPreLegalizerCombinerImpl::tryCombineAll(llvm::MachineInstr&) const | bool tryCombineAll(MachineInstr &MI) const override {
switch (MI.getOpcode()) {
default:
return false;
case TargetOpcode::G_MEMCPY_INLINE:
return Helper.tryEmitMemcpyInline(MI);
case TargetOpcode::G_LOAD:
case TargetOpcode::G_SEXTLOAD:
case TargetOpcode::G_ZEXTLOAD: {
// Don't... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %rsi, %rbx
movq %rdi, %r14
movzwl 0x44(%rsi), %eax
leal -0x59(%rax), %ecx
cmpl $0x3, %ecx
jae 0xfddd37
movq 0x30(%rbx), %rax
testb $0x7, %al
je 0xfddd62
andq $-0x8, %rax
addq $0x10, %rax
movq %rax, %rcx
jmp 0xfddd69
cmpl $0x10d, %ea... | /Target/Mips/MipsPreLegalizerCombiner.cpp |
llvm::MipsSEFrameLowering::hasReservedCallFrame(llvm::MachineFunction const&) const | const MachineFrameInfo &getFrameInfo() const { return *FrameInfo; } | movq 0x38(%rsi), %rax
movq 0x50(%rax), %rdx
movb 0xc(%rdi), %cl
movl $0x1, %esi
shlq %cl, %rsi
movl $0x8000, %ecx # imm = 0x8000
leaq (%rdx,%rcx), %rdi
cmpq $-0x1, %rdx
movl %esi, %edx
cmoveq %rcx, %rdi
addq %rdx, %rdi
cmpq $0xffff, %rdi # imm = 0xFFFF
ja 0xfea448
movb 0x24(%rax), %al
xorb $0x1, %al... | /llvm/CodeGen/MachineFunction.h |
(anonymous namespace)::ExpandPseudo::expandExtractElementF64(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, bool) const | bool ExpandPseudo::expandExtractElementF64(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
bool FP64) const {
const MachineOperand &Op1 = I->getOperand(1);
const MachineOperand &Op2 = I->getOperand(2);
if ((Op1.isReg() &... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %rdx, %rbx
movq %rsi, %r15
movq %rdi, %r14
movq 0x20(%rdx), %r12
movl $0x100000ff, %eax # imm = 0x100000FF
movl 0x20(%r12), %edx
andl %eax, %edx
cmpl $0x10000000, %edx # imm = 0x10000000
je 0xfeba09
andl 0x40(%r12), %eax... | /Target/Mips/MipsSEFrameLowering.cpp |
lowerVECTOR_SHUFFLE_VSHF(llvm::SDValue, llvm::EVT, llvm::SmallVector<int, 16u> const&, llvm::SelectionDAG&) | static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy,
const SmallVector<int, 16> &Indices,
SelectionDAG &DAG) {
SmallVector<SDValue, 16> Ops;
SDValue Op0;
SDValue Op1;
EVT MaskVecTy = ResTy.changeVectorElementTypeToInteger(... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x1d8, %rsp # imm = 0x1D8
movq %r8, %r13
movq %rcx, %r12
movq %rdi, %rbx
leaq 0x78(%rsp), %rdi
movb %sil, (%rdi)
movq %rdx, 0x8(%rdi)
leaq 0xd8(%rsp), %rcx
movq %rcx, -0x10(%rcx)
movabsq $0x1000000000, %rax # imm = 0x1000000000
movq ... | /Target/Mips/MipsSEISelLowering.cpp |
llvm::Mips16TargetLowering::emitFEXT_CCRX16_ins(unsigned int, llvm::MachineInstr&, llvm::MachineBasicBlock*) const | MachineBasicBlock *
Mips16TargetLowering::emitFEXT_CCRX16_ins(unsigned SltOpc, MachineInstr &MI,
MachineBasicBlock *BB) const {
if (DontExpandCondPseudos16)
return BB;
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
Register CC = MI.getOperand(0).getReg();
Re... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x68, %rsp
movq %rcx, %rbx
cmpb $0x0, 0x48ab27c(%rip) # 0x58b2e28
jne 0x1007dc6
movq %rdx, %r14
movl %esi, %r12d
movq 0x4e0f8(%rdi), %rdi
movq (%rdi), %rax
callq *0x80(%rax)
movq %rax, %r15
movq 0x20(%r14), %rax
movl 0x4(%rax), %ecx
movl %ecx, 0x... | /Target/Mips/Mips16ISelLowering.cpp |
llvm::SmallVectorTemplateBase<llvm::SmallVector<llvm::MipsAnalyzeImmediate::Inst, 7u>, false>::grow(unsigned long) | void SmallVectorTemplateBase<T, TriviallyCopyable>::grow(size_t MinSize) {
size_t NewCapacity;
T *NewElts = mallocForGrow(MinSize, NewCapacity);
moveElementsForGrow(NewElts);
takeAllocationForGrow(NewElts, NewCapacity);
} | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rsi, %rdx
movq %rdi, %rbx
leaq 0x10(%rdi), %r15
movq %rsp, %r12
movl $0x48, %ecx
movq %r15, %rsi
movq %r12, %r8
callq 0x1cba3de
movq %rax, %r14
movq %rbx, %rdi
movq %rax, %rsi
callq 0x10092de
movq (%r12), %r12
movq (%rbx), %rdi
cmpq %r15, %rdi
je 0x10092ca
ca... | /llvm/ADT/SmallVector.h |
llvm::MSP430TargetMachine::MSP430TargetMachine(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, std::optional<llvm::Reloc::Model>, std::optional<llvm::CodeModel::Model>, llvm::CodeGenOptLevel, bool) | MSP430TargetMachine::MSP430TargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
std::optional<Reloc::Model> RM,
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xa8, %rsp
movq %r9, 0x50(%rsp)
movq %r8, %r15
movq %rcx, %r12
movq %rdx, 0x40(%rsp)
movq %rsi, 0x48(%rsp)
movq %rdi, %rbx
leaq 0x68(%rsp), %rax
movq %rax, -0x10(%rax)
leaq 0x88(%rsp), %r14
movq $0x37, (%r14)
xorl %ebp, %ebp
leaq 0x58(%rsp), %r13
m... | /Target/MSP430/MSP430TargetMachine.cpp |
(anonymous namespace)::MSP430DAGToDAGISel::SelectInlineAsmMemoryOperand(llvm::SDValue const&, llvm::InlineAsm::ConstraintCode, std::vector<llvm::SDValue, std::allocator<llvm::SDValue>>&) | bool MSP430DAGToDAGISel::SelectInlineAsmMemoryOperand(
const SDValue &Op, InlineAsm::ConstraintCode ConstraintID,
std::vector<SDValue> &OutOps) {
SDValue Op0, Op1;
switch (ConstraintID) {
default: return true;
case InlineAsm::ConstraintCode::m: // memory
if (!SelectAddr(Op, Op0, Op1))
return t... | pushq %rbp
pushq %rbx
subq $0x28, %rsp
xorl %eax, %eax
movq %rax, 0x18(%rsp)
movl %eax, 0x20(%rsp)
movq %rax, 0x8(%rsp)
movl %eax, 0x10(%rsp)
movb $0x1, %bpl
cmpl $0x4, %edx
jne 0x10186b3
movq %rcx, %rbx
movq (%rsi), %rax
movl 0x8(%rsi), %edx
leaq 0x18(%rsp), %rcx
leaq 0x8(%rsp), %r8
movq %rax, %rsi
callq 0x10189d4
tes... | /Target/MSP430/MSP430ISelDAGToDAG.cpp |
llvm::MSP430InstrInfo::storeRegToStackSlot(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::Register, bool, int, llvm::TargetRegisterClass const*, llvm::TargetRegisterInfo const*, llvm::Register) const | void MSP430InstrInfo::storeRegToStackSlot(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
bool isKill, int FrameIdx, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI, Register VReg) const {
DebugLoc DL;
if (MI != MBB.end()) DL = MI->getDebugLoc();
MachineFunction ... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xc8, %rsp
movl %r9d, 0x34(%rsp)
movl %r8d, 0x50(%rsp)
movl %ecx, 0x54(%rsp)
movq %rdx, %rbx
movq %rsi, %r13
movq %rdi, 0x58(%rsp)
movq $0x0, 0x48(%rsp)
leaq 0x30(%rsi), %rax
cmpq %rdx, %rax
je 0x1019014
leaq 0x38(%rbx), %rsi
leaq 0x48(%rsp), %rdi
... | /Target/MSP430/MSP430InstrInfo.cpp |
llvm::MSP430TargetLowering::CanLowerReturn(unsigned int, llvm::MachineFunction&, bool, llvm::SmallVectorImpl<llvm::ISD::OutputArg> const&, llvm::LLVMContext&) const | bool
MSP430TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
MachineFunction &MF,
bool IsVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
LLVMContext &Context) c... | pushq %r15
pushq %r14
pushq %rbx
subq $0x320, %rsp # imm = 0x320
movq %r8, %rbx
movq %rdx, %rax
leaq 0x1a0(%rsp), %r15
movq %r15, -0x10(%r15)
movabsq $0x1000000000, %rdx # imm = 0x1000000000
movq %rdx, -0x8(%r15)
movl $0x0, (%rsp)
leaq 0x8(%rsp), %r14
leaq 0x190(%rsp), %r8
movq %r14, %rdi
movl %ecx, %edx... | /Target/MSP430/MSP430ISelLowering.cpp |
ComputePTXValueVTs(llvm::TargetLowering const&, llvm::DataLayout const&, llvm::Type*, llvm::SmallVectorImpl<llvm::EVT>&, llvm::SmallVectorImpl<unsigned long>*, unsigned long) | static void ComputePTXValueVTs(const TargetLowering &TLI, const DataLayout &DL,
Type *Ty, SmallVectorImpl<EVT> &ValueVTs,
SmallVectorImpl<uint64_t> *Offsets = nullptr,
uint64_t StartingOffset = 0) {
SmallVector<EVT, 16> TempV... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x208, %rsp # imm = 0x208
movq %r9, %r15
movq %r8, %rbx
movq %rcx, %r14
movq %rdx, %rbp
movq %rsi, %r12
movq %rdi, %r13
leaq 0x108(%rsp), %rcx
movq %rcx, -0x10(%rcx)
movabsq $0x1000000000, %rax # imm = 0x1000000000
movq %rax, -0x8(%r... | /Target/NVPTX/NVPTXISelLowering.cpp |
llvm::BasicTTIImplBase<llvm::NVPTXTTIImpl>::getFPOpCost(llvm::Type*) | InstructionCost getFPOpCost(Type *Ty) {
// Check whether FADD is available, as a proxy for floating-point in
// general.
const TargetLoweringBase *TLI = getTLI();
EVT VT = TLI->getValueType(DL, Ty);
if (TLI->isOperationLegalOrCustomOrPromote(ISD::FADD, VT))
return TargetTransformInfo::TCC_Basi... | pushq %rbx
movq %rsi, %rdx
movq 0x8(%rdi), %rsi
movq 0x18(%rdi), %rbx
movq %rbx, %rdi
xorl %ecx, %ecx
callq 0x8f1f84
movq %rdx, %rcx
movzbl %al, %edx
movq %rbx, %rdi
movl $0x60, %esi
xorl %r8d, %r8d
callq 0x8f36b6
xorb $0x1, %al
movzbl %al, %eax
leaq (%rax,%rax,2), %rax
incq %rax
xorl %edx, %edx
popq %rbx
retq
| /llvm/CodeGen/BasicTTIImpl.h |
initializeNVPTXProxyRegErasurePassOnce(llvm::PassRegistry&) | bool NVPTXProxyRegErasure::runOnMachineFunction(MachineFunction &MF) {
SmallVector<MachineInstr *, 16> RemoveList;
for (auto &BB : MF) {
for (auto &MI : BB) {
switch (MI.getOpcode()) {
case NVPTX::ProxyRegI1:
case NVPTX::ProxyRegI16:
case NVPTX::ProxyRegI32:
case NVPTX::ProxyRegI6... | pushq %r14
pushq %rbx
pushq %rax
movq %rdi, %rbx
movl $0x50, %edi
callq 0x751940
movq %rax, %r14
leaq 0x2a831e6(%rip), %rax # 0x3acd201
movq %rax, (%r14)
movl $0x16, %eax
movq %rax, 0x8(%r14)
leaq 0x2a831ea(%rip), %rcx # 0x3acd218
movq %rcx, 0x10(%r14)
movq %rax, 0x18(%r14)
leaq 0x4869ad7(%rip), %rax # 0x58b3b14
... | /Target/NVPTX/NVPTXProxyRegErasure.cpp |
llvm::DenseMapBase<llvm::DenseMap<llvm::ValueMapCallbackVH<llvm::Constant*, llvm::Value*, llvm::ValueMapConfig<llvm::Constant*, llvm::sys::SmartMutex<false>>>, llvm::Value*, llvm::DenseMapInfo<llvm::ValueMapCallbackVH<llvm::Constant*, llvm::Value*, llvm::ValueMapConfig<llvm::Constant*, llvm::sys::SmartMutex<false>>>, v... | void initEmpty() {
setNumEntries(0);
setNumTombstones(0);
assert((getNumBuckets() & (getNumBuckets()-1)) == 0 &&
"# initial buckets must be a power of two!");
const KeyT EmptyKey = getEmptyKey();
for (BucketT *B = getBuckets(), *E = getBucketsEnd(); B != E; ++B)
::new (&B->getFirst... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
xorl %eax, %eax
movq %rax, 0x8(%rdi)
leaq 0x8(%rsp), %rbx
movq $0x2, (%rbx)
movq %rax, 0x8(%rbx)
movq $-0x1000, 0x10(%rbx) # imm = 0xF000
leaq 0x46fcacf(%rip), %r14 # 0x574a578
movq %r14, -0x8(%rbx)
movq %rax, 0x18(%rbx)
movl 0x10(%... | /llvm/ADT/DenseMap.h |
bool llvm::DenseMapBase<llvm::DenseMap<std::pair<llvm::MCSymbol const*, llvm::MCSymbolRefExpr::VariantKind>, unsigned int, llvm::DenseMapInfo<std::pair<llvm::MCSymbol const*, llvm::MCSymbolRefExpr::VariantKind>, void>, llvm::detail::DenseMapPair<std::pair<llvm::MCSymbol const*, llvm::MCSymbolRefExpr::VariantKind>, unsi... | unsigned getNumBuckets() const {
return NumBuckets;
} | movl 0x10(%rdi), %ecx
testl %ecx, %ecx
je 0x1062205
pushq %rbp
pushq %rbx
movq (%rdi), %rdi
movl (%rsi), %eax
movl %eax, %r8d
shrl $0x4, %r8d
shrl $0x9, %eax
xorl %r8d, %eax
movzwl 0x8(%rsi), %r8d
leaq (%r8,%r8,8), %r9
leaq (%r8,%r9,4), %r8
shlq $0x20, %rax
orq %r8, %rax
movabsq $-0x40a7b892e31b1a47, %r9 # imm = 0xBF58... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<unsigned int, std::pair<llvm::Register, llvm::Register>, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, std::pair<llvm::Register, llvm::Register>>>, unsigned int, std::pair<llvm::Register, llvm::Register>, llvm::DenseMapInfo<unsigned int, void>, llvm::... | unsigned getNumEntries() const {
return NumEntries;
} | movl 0x8(%rdi), %ecx
testl %ecx, %ecx
jne 0x1071503
cmpl $0x0, 0xc(%rdi)
je 0x1071644
shll $0x2, %ecx
movl 0x10(%rdi), %eax
cmpl %eax, %ecx
setae %cl
cmpl $0x41, %eax
setb %dl
orb %cl, %dl
je 0x1072a60
testq %rax, %rax
je 0x107163c
movq (%rdi), %rcx
leaq (%rax,%rax,2), %rax
leaq -0xc(,%rax,4), %rax
movabsq $-0x55555555... | /llvm/ADT/DenseMap.h |
llvm::PPCTTIImpl::instCombineIntrinsic(llvm::InstCombiner&, llvm::IntrinsicInst&) const | std::optional<Instruction *>
PPCTTIImpl::instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const {
Intrinsic::ID IID = II.getIntrinsicID();
switch (IID) {
default:
break;
case Intrinsic::ppc_altivec_lvx:
case Intrinsic::ppc_altivec_lvxl:
// Turn PPC lvx -> load if the pointer is known aligned.... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x1b8, %rsp # imm = 0x1B8
movq %rdx, %rbx
movq -0x20(%rdx), %rax
movl 0x24(%rax), %eax
xorl %r13d, %r13d
cmpl $0x2611, %eax # imm = 0x2611
jle 0x10889a5
cmpl $0x274e, %eax # imm = 0x274E
jle 0x1088a48
cmpl $0x274f, %e... | /Target/PowerPC/PPCTargetTransformInfo.cpp |
llvm::PPCTTIImpl::getRegisterClassForType(bool, llvm::Type*) const | unsigned PPCTTIImpl::getRegisterClassForType(bool Vector, Type *Ty) const {
if (Vector)
return ST->hasVSX() ? VSXRC : VRRC;
else if (Ty && (Ty->getScalarType()->isFloatTy() ||
Ty->getScalarType()->isDoubleTy()))
return ST->hasVSX() ? VSXRC : FPRRC;
else if (Ty && (Ty->getScalarType()->is... | testl %esi, %esi
je 0x108a7cd
movq 0x10(%rdi), %rax
movzbl 0x203(%rax), %eax
orl $0x2, %eax
retq
testq %rdx, %rdx
je 0x108a85c
movl $0xfe, %ecx
andl 0x8(%rdx), %ecx
movq %rdx, %rax
cmpl $0x12, %ecx
jne 0x108a7ed
movq 0x10(%rdx), %rax
movq (%rax), %rax
cmpb $0x2, 0x8(%rax)
je 0x108a808
movq %rdx, %rax
cmpl $0x12, %ecx
j... | /Target/PowerPC/PPCTargetTransformInfo.cpp |
(anonymous namespace)::PPCBSel::runOnMachineFunction(llvm::MachineFunction&) | bool PPCBSel::runOnMachineFunction(MachineFunction &Fn) {
const PPCInstrInfo *TII =
static_cast<const PPCInstrInfo *>(Fn.getSubtarget().getInstrInfo());
// Give the blocks of the function a dense, in-order, numbering.
Fn.RenumberBlocks();
BlockSizes.resize(Fn.getNumBlockIDs());
FirstImpreciseBlock = -1;... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xc8, %rsp
movq %rsi, %rbx
movq %rdi, %r12
movq 0x10(%rsi), %rdi
movq (%rdi), %rax
callq *0x80(%rax)
movq %rax, 0x58(%rsp)
xorl %r14d, %r14d
movq %rbx, %rdi
xorl %esi, %esi
callq 0x1789970
leaq 0x38(%r12), %rdi
movq 0x70(%rbx), %rax
subq 0x68(%rbx)... | /Target/PowerPC/PPCBranchSelector.cpp |
(anonymous namespace)::PPCBSel::GetAlignmentAdjustment(llvm::MachineBasicBlock&, unsigned int) | Align getAlignment() const { return Alignment; } | movzbl 0xb0(%rsi), %ecx
testq %rcx, %rcx
je 0x10a3f21
movq 0x20(%rsi), %rax
cmpb 0x154(%rax), %cl
jbe 0x10a3f24
cmpl $0x0, 0x50(%rdi)
jns 0x10a3f00
movl 0x18(%rsi), %eax
movl %eax, 0x50(%rdi)
movl $0x1, %eax
shlq %cl, %rax
movl %edx, %ecx
leaq (%rcx,%rax), %rdx
decq %rdx
movq %rax, %rsi
negq %rsi
andq %rdx, %rsi
subq %... | /llvm/CodeGen/MachineBasicBlock.h |
llvm::PPCInstrInfo::CreateTargetHazardRecognizer(llvm::TargetSubtargetInfo const*, llvm::ScheduleDAG const*) const | ScheduleHazardRecognizer *
PPCInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
const ScheduleDAG *DAG) const {
unsigned Directive =
static_cast<const PPCSubtarget *>(STI)->getCPUDirective();
if (Directive == PPC::DIR_440 || Directive == PPC::DI... | pushq %r15
pushq %r14
pushq %rbx
movq %rdx, %rbx
movl 0x21c(%rsi), %eax
cmpl $0xc, %eax
ja 0x10a9b77
movl $0x1a04, %ecx # imm = 0x1A04
btl %eax, %ecx
jae 0x10a9b77
movq (%rsi), %rax
movq %rsi, %rdi
callq *0xd8(%rax)
movq %rax, %r14
movl $0x60, %edi
callq 0x751940
movq %rax, %r15
leaq 0x2e698d8(%rip), %rcx #... | /Target/PowerPC/PPCInstrInfo.cpp |
llvm::PPCInstrInfo::CreateTargetPostRAHazardRecognizer(llvm::InstrItineraryData const*, llvm::ScheduleDAG const*) const | ScheduleHazardRecognizer *
PPCInstrInfo::CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
const ScheduleDAG *DAG) const {
unsigned Directive =
DAG->MF.getSubtarget<PPCSubtarget>().getCPUDirective();
// FIXME: Leaving this as-is until we have PO... | pushq %r15
pushq %r14
pushq %rbx
movq %rdx, %rbx
movq %rsi, %r15
movq 0x20(%rdx), %rax
movq 0x10(%rax), %rax
movl 0x21c(%rax), %eax
leal -0x13(%rax), %ecx
cmpl $0x1, %ecx
ja 0x10a9bfc
movl $0xb8, %edi
callq 0x751940
movq %rax, %r14
leaq 0x2e6987f(%rip), %rcx # 0x3f13438
movq %rax, %rdi
movq %r15, %rsi
movq %rbx, %rdx... | /Target/PowerPC/PPCInstrInfo.cpp |
llvm::PPCInstrInfo::ClobbersPredicate(llvm::MachineInstr&, std::vector<llvm::MachineOperand, std::allocator<llvm::MachineOperand>>&, bool) const | mop_iterator operands_end() { return Operands + NumOperands; } | movzwl 0x28(%rsi), %eax
movzbl 0x2a(%rsi), %ecx
shll $0x10, %ecx
orl %eax, %ecx
testl %ecx, %ecx
je 0x10b1473
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %rbx
movq 0x20(%rsi), %r14
shll $0x5, %ecx
addq %r14, %rcx
xorl %eax, %eax
movq %rcx, (%rsp)
testb $0x1, %al
je 0x10b134b
... | /llvm/CodeGen/MachineInstr.h |
llvm::PPC::isVMRGLShuffleMask(llvm::ShuffleVectorSDNode*, unsigned int, unsigned int, llvm::SelectionDAG&) | bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
unsigned ShuffleKind, SelectionDAG &DAG) {
if (DAG.getDataLayout().isLittleEndian()) {
if (ShuffleKind == 1) // unary
return isVMerge(N, UnitSize, 0, 0);
else if (ShuffleKind == 2) // swapped
retur... | pushq %rbp
pushq %r14
pushq %rbx
movl %edx, %ebp
movl %esi, %ebx
movq %rdi, %r14
movq 0x28(%rcx), %rdi
callq 0x1789320
cmpb $0x0, (%rax)
je 0x10d6903
testl %ebp, %ebp
je 0x10d691f
cmpl $0x1, %ebp
jne 0x10d6918
movq %r14, %rdi
movl %ebx, %esi
movl $0x8, %edx
movl $0x8, %ecx
jmp 0x10d693c
cmpl $0x2, %ebp
je 0x10d6930
cmp... | /Target/PowerPC/PPCISelLowering.cpp |
PrepareTailCall(llvm::SelectionDAG&, llvm::SDValue&, llvm::SDValue&, llvm::SDLoc const&, int, unsigned int, llvm::SDValue, llvm::SDValue, llvm::SmallVectorImpl<(anonymous namespace)::TailCallArgumentInfo>&) | static void
PrepareTailCall(SelectionDAG &DAG, SDValue &InGlue, SDValue &Chain,
const SDLoc &dl, int SPDiff, unsigned NumBytes, SDValue LROp,
SDValue FPOp,
SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
// Emit a sequence of copyto/copyfrom virtual register... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x1a8, %rsp # imm = 0x1A8
movl %r9d, 0x6c(%rsp)
movl %r8d, 0x40(%rsp)
movq %rcx, 0x60(%rsp)
movq %rdx, 0x48(%rsp)
movq %rdi, %r12
movq 0x1f0(%rsp), %rbp
leaq 0x128(%rsp), %rcx
movq %rcx, -0x10(%rcx)
movabsq $0x800000000, %rax # imm ... | /Target/PowerPC/PPCISelLowering.cpp |
getRegClassForSVT(llvm::MVT::SimpleValueType, bool, bool, bool) | static const TargetRegisterClass *getRegClassForSVT(MVT::SimpleValueType SVT,
bool IsPPC64,
bool HasP8Vector,
bool HasVSX) {
assert((IsPPC64 || SVT != MVT::i64) &... | cmpl $0x26, %edi
jle 0x10e9b02
leaq 0x46627a7(%rip), %rax # 0x574c290
leal -0x27(%rdi), %ecx
cmpl $0x30, %ecx
ja 0x10e9b27
movabsq $0x1008000200801, %rdx # imm = 0x1008000200801
btq %rcx, %rdx
jae 0x10e9b27
retq
addl $-0x2, %edi
cmpl $0xb, %edi
ja 0x10e9b34
leaq 0x2a654db(%rip), %rax # 0x3b4efec
movslq (%rax,%rdi,... | /Target/PowerPC/PPCISelLowering.cpp |
llvm::PPCTargetLowering::LowerBSWAP(llvm::SDValue, llvm::SelectionDAG&) const | SDValue PPCTargetLowering::LowerBSWAP(SDValue Op, SelectionDAG &DAG) const {
SDLoc dl(Op);
if (!Subtarget.isPPC64())
return Op;
// MTVSRDD
Op = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, Op.getOperand(0),
Op.getOperand(0));
// XXBRD
Op = DAG.getNode(ISD::BSWAP, dl, MVT::v2i64, Op)... | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
subq $0x68, %rsp
movq %rcx, %rbx
movl %edx, %ebp
movq %rsi, %r15
movq %rdi, %r14
movq 0x48(%rsi), %rsi
movq %rsi, 0x28(%rsp)
testq %rsi, %rsi
je 0x10f9334
leaq 0x28(%rsp), %rdi
movl $0x1, %edx
callq 0x1a648a8
movl 0x44(%r15), %eax
movl %eax, 0x30(%rsp)
movq 0x4e0f8(%r14), %rd... | /Target/PowerPC/PPCISelLowering.cpp |
(anonymous namespace)::PPCMergeStringPool::doInitialization(llvm::Module&) | bool doInitialization(Module &M) override { return mergeModuleStringPool(M); } | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x118, %rsp # imm = 0x118
movq %rsi, %rbp
movq %rdi, 0x8(%rsp)
leaq 0x40(%rsp), %rax
movq %rax, -0x10(%rax)
movabsq $0x400000000, %rbx # imm = 0x400000000
movq %rbx, -0x8(%rax)
leaq 0x30(%rsp), %r14
movq %rsi, %rdi
movq %r14, %rsi
x... | /Target/PowerPC/PPCMergeStringPool.cpp |
void llvm::cl::apply<llvm::cl::opt<unsigned int, false, llvm::cl::parser<unsigned int>>, char [23], llvm::cl::OptionHidden, llvm::cl::initializer<int>, llvm::cl::desc>(llvm::cl::opt<unsigned int, false, llvm::cl::parser<unsigned int>>*, char const (&) [23], llvm::cl::OptionHidden const&, llvm::cl::initializer<int> cons... | void apply(Opt *O, const Mod &M, const Mods &... Ms) {
applicator<Mod>::opt(M, *O);
apply(O, Ms...);
} | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %r8, %rbx
movq %rcx, %r14
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %r13
movq %rsi, %rdi
callq 0x7512e0
movq %r13, %rdi
movq %r12, %rsi
movq %rax, %rdx
callq 0x1c90c20
movl (%r15), %eax
movzwl 0xa(%r13), %ecx
shll $0x5, %eax
andl $0x60, %eax
andl $-0x61, %ecx... | /llvm/Support/CommandLine.h |
(anonymous namespace)::PPCMIPeephole::runOnMachineFunction(llvm::MachineFunction&) | bool runOnMachineFunction(MachineFunction &MF) override {
initialize(MF);
// At this point, TOC pointer should not be used in a function that uses
// PC-Relative addressing.
assert((MF.getRegInfo().use_empty(PPC::X2) ||
!MF.getSubtarget<PPCSubtarget>().isUsingPCRelativeCalls()) &&
... | pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %r14
movq %rdi, %rbx
movq %rsi, 0x40(%rdi)
movq 0x28(%rsi), %rax
movq %rax, 0x48(%rdi)
movq 0x8(%rdi), %rax
movq (%rax), %rdx
movq 0x8(%rax), %rax
xorl %edi, %edi
leaq 0x47a1218(%rip), %rcx # 0x58cc8c0
leaq 0x10(%rdx), %rsi
cmpq %rcx, (%rdx)
jne 0x112b6b5
movq 0x8(%rdx), %r... | /Target/PowerPC/PPCMIPeephole.cpp |
(anonymous namespace)::getPredicateToDecImm(llvm::MachineInstr*, llvm::MachineInstr*) | MachineOperand& getOperand(unsigned i) {
assert(i < getNumOperands() && "getOperand() out of range!");
return Operands[i];
} | movq 0x20(%rsi), %rax
movq 0x50(%rax), %rcx
movzwl 0x44(%rsi), %eax
addl $0xfffffd6c, %eax # imm = 0xFFFFFD6C
cmpl $0xa, %eax
ja 0x1130b27
movl $0x8000, %edx # imm = 0x8000
movl $0x603, %esi # imm = 0x603
btl %eax, %esi
jae 0x1130b27
xorl %eax, %eax
cmpq %rdx, %rcx
je 0x1130b30
movq 0x20(%rdi... | /llvm/CodeGen/MachineInstr.h |
(anonymous namespace)::RISCVAsmPrinter::PrintAsmOperand(llvm::MachineInstr const*, unsigned int, char const*, llvm::raw_ostream&) | bool RISCVAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
const char *ExtraCode, raw_ostream &OS) {
// First try the generic code, which knows about modifiers like 'c' and 'n'.
if (!AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS))
return false;
co... | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
movq %r8, %rbx
movq %rcx, %r15
movl %edx, %ebp
movq %rsi, %r12
movq %rdi, %r14
callq 0x1de9c08
testb %al, %al
je 0x113481e
movl %ebp, %esi
shlq $0x5, %rsi
addq 0x20(%r12), %rsi
testq %r15, %r15
je 0x11347b2
movzbl (%r15), %ecx
testl %ecx, %ecx
je 0x11347b2
movb $0x... | /Target/RISCV/RISCVAsmPrinter.cpp |
llvm::RISCVInstrInfo::analyzeSelect(llvm::MachineInstr const&, llvm::SmallVectorImpl<llvm::MachineOperand>&, unsigned int&, unsigned int&, bool&) const | bool RISCVInstrInfo::analyzeSelect(const MachineInstr &MI,
SmallVectorImpl<MachineOperand> &Cond,
unsigned &TrueOp, unsigned &FalseOp,
bool &Optimizable) const {
assert(MI.getOpcode() == RISCV::PseudoCCMOVGPR &&
... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %r9, %rbx
movq %rdx, %r14
movq %rsi, %r12
movq %rdi, %r15
movl $0x5, (%rcx)
movl $0x4, (%r8)
movq 0x20(%rsi), %rsi
addq $0x20, %rsi
movl $0x1, %edx
movq %r14, %rdi
callq 0xa48af6
movq (%r14), %rcx
movl 0x8(%r14), %edx
shlq $0x5, %rdx
movups (%rax), %xmm0
movup... | /Target/RISCV/RISCVInstrInfo.cpp |
llvm::RISCVInstrInfo::areRVVInstsReassociable(llvm::MachineInstr const&, llvm::MachineInstr const&) const | bool RISCVInstrInfo::areRVVInstsReassociable(const MachineInstr &Root,
const MachineInstr &Prev) const {
if (!areOpcodesEqualOrInverse(Root.getOpcode(), Prev.getOpcode()))
return false;
assert(Root.getMF() == Prev.getMF());
const MachineRegisterInfo *MRI = &Root.g... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r12
movzwl 0x44(%rsi), %esi
movzwl 0x44(%rdx), %edx
callq 0x18bd324
testb %al, %al
je 0x113c970
movq %r14, %rdi
callq 0x1793b7e
movq 0x28(%rax), %rax
movq (%rax), %rax
movq 0x10(%rax), %rdi
mov... | /Target/RISCV/RISCVInstrInfo.cpp |
llvm::RISCVInstrInfo::getReassociateOperandIndices(llvm::MachineInstr const&, unsigned int, std::array<unsigned int, 5ul>&) const | void RISCVInstrInfo::getReassociateOperandIndices(
const MachineInstr &Root, unsigned Pattern,
std::array<unsigned, 5> &OperandIndices) const {
TargetInstrInfo::getReassociateOperandIndices(Root, Pattern, OperandIndices);
if (RISCV::getRVVMCOpcode(Root.getOpcode())) {
// Skip the passthrough operand, so... | pushq %r14
pushq %rbx
pushq %rax
movq %rcx, %rbx
movq %rsi, %r14
callq 0x18bd672
movzwl 0x44(%r14), %edi
callq 0x1135280
testq %rax, %rax
je 0x113cb67
cmpw $0x0, 0x2(%rax)
je 0x113cb67
xorl %eax, %eax
incl (%rbx,%rax,4)
incq %rax
cmpq $0x5, %rax
jne 0x113cb5b
addq $0x8, %rsp
popq %rbx
popq %r14
retq
nop
| /Target/RISCV/RISCVInstrInfo.cpp |
llvm::RISCVInstrInfo::insertOutlinedCall(llvm::Module&, llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>&, llvm::MachineFunction&, llvm::outliner::Candidate&) const | MachineBasicBlock::iterator RISCVInstrInfo::insertOutlinedCall(
Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It,
MachineFunction &MF, outliner::Candidate &C) const {
// Add in a call instruction to the outlined function at the given location.
It = MBB.insert(It,
BuildMI... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x58, %rsp
movq %r8, %r13
movq %rcx, 0x18(%rsp)
movq %rdx, %r12
movq %rsi, 0x10(%rsp)
movq (%rcx), %rbx
xorl %ebp, %ebp
movq %rbp, 0x8(%rsp)
xorps %xmm0, %xmm0
leaq 0x20(%rsp), %rsi
movaps %xmm0, (%rsi)
movq %rbp, 0x10(%rsi)
movq $-0x2760, %rdx ... | /Target/RISCV/RISCVInstrInfo.cpp |
llvm::cl::opt<unsigned int, false, llvm::cl::parser<unsigned int>>::opt<char [26], llvm::cl::desc, llvm::cl::initializer<int>, llvm::cl::OptionHidden>(char const (&) [26], llvm::cl::desc const&, llvm::cl::initializer<int> const&, llvm::cl::OptionHidden const&) | explicit opt(const Mods &... Ms)
: Option(llvm::cl::Optional, NotHidden), Parser(*this) {
apply(this, Ms...);
done();
} | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %r8, %rbx
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %r14
xorl %esi, %esi
xorl %edx, %edx
callq 0x7c77e2
movl $0x0, 0x80(%r14)
xorps %xmm0, %xmm0
movups %xmm0, 0x88(%r14)
movb $0x0, 0x94(%r14)
leaq 0x45aa644(%rip), %rax # 0x56f1ec8
movq %rax,... | /llvm/Support/CommandLine.h |
llvm::TargetTransformInfo::Model<llvm::RISCVTTIImpl>::enableMemCmpExpansion(bool, bool) const | MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize,
bool IsZeroCmp) const override {
return Impl.enableMemCmpExpansion(OptSize, IsZeroCmp);
} | movq %rdi, %rax
movl $0x0, (%rdi)
leaq 0x18(%rdi), %rcx
movq %rcx, 0x8(%rdi)
movabsq $0x800000000, %rcx # imm = 0x800000000
movq %rcx, 0x10(%rdi)
movl $0x1, 0x38(%rdi)
movb $0x0, 0x3c(%rdi)
leaq 0x50(%rdi), %rcx
movq %rcx, 0x40(%rdi)
movabsq $0x400000000, %rcx # imm = 0x400000000
movq %rcx, 0x48(%rdi)
retq
no... | /llvm/Analysis/TargetTransformInfo.h |
llvm::RISCVTTIImpl::getRegUsageForType(llvm::Type*) | unsigned RISCVTTIImpl::getRegUsageForType(Type *Ty) {
TypeSize Size = DL.getTypeSizeInBits(Ty);
if (Ty->isVectorTy()) {
if (Size.isScalable() && ST->hasVInstructions())
return divideCeil(Size.getKnownMinValue(), RISCV::RVVBitsPerBlock);
if (ST->useRVVForFixedLengthVectors())
return divideCeil(S... | pushq %r14
pushq %rbx
subq $0x18, %rsp
movq %rsi, %r14
movq %rdi, %rbx
movq 0x8(%rdi), %rdi
callq 0x8ef294
movq %rax, 0x8(%rsp)
movb %dl, 0x10(%rsp)
movl $0xfe, %ecx
andl 0x8(%r14), %ecx
cmpl $0x12, %ecx
jne 0x1155cf3
testb $0x1, %dl
je 0x1155ca4
movq 0x10(%rbx), %rcx
cmpb $0x1, 0x1a1(%rcx)
jne 0x1155ca4
xorl %ecx, %ec... | /Target/RISCV/RISCVTargetTransformInfo.cpp |
(anonymous namespace)::VSETVLIInfo::hasSameAVLLatticeValue((anonymous namespace)::VSETVLIInfo const&) const | bool hasSameAVLLatticeValue(const VSETVLIInfo &Other) const {
if (hasAVLReg() && Other.hasAVLReg()) {
assert(!getAVLVNInfo() == !Other.getAVLVNInfo() &&
"we either have intervals or we don't");
if (!getAVLVNInfo())
return getAVLReg() == Other.getAVLReg();
return getAVLVNInfo()... | pushq %rbp
pushq %rbx
pushq %rax
movq %rsi, %rbx
movb 0x10(%rdi), %cl
cmpb $0x1, %cl
jne 0x118dd7b
cmpb $0x1, 0x10(%rbx)
jne 0x118dd7b
movq (%rdi), %rax
testq %rax, %rax
je 0x118ddbb
movl (%rax), %eax
movq (%rbx), %rcx
xorl (%rcx), %eax
movl 0x8(%rbx), %ecx
xorl 0x8(%rdi), %ecx
orl %eax, %ecx
jmp 0x118ddc1
cmpb $0x2, %... | /Target/RISCV/RISCVInsertVSETVLI.cpp |
(anonymous namespace)::RISCVInsertVSETVLI::insertVSETVLI(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::DebugLoc, (anonymous namespace)::VSETVLIInfo const&, (anonymous namespace)::VSETVLIInfo const&) | void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
MachineBasicBlock::iterator InsertPt, DebugLoc DL,
const VSETVLIInfo &Info, const VSETVLIInfo &PrevInfo) {
++NumInsertedVSETVL;
if (PrevInfo.isValid() && !PrevInfo.isUnknown()) {
// Use X0, X0 form if the A... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x98, %rsp
movq %r8, %r14
movq %rcx, %rbx
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %r15
movzbl 0x10(%r9), %eax
testb $-0x5, %al
movq %rdi, 0x8(%rsp)
jne 0x118e594
movzbl 0x10(%r14), %eax
cmpl $0x3, %eax
je 0x118e763
cmpl $0x2, %eax
jne 0x118e8ed
... | /Target/RISCV/RISCVInsertVSETVLI.cpp |
llvm::RISCVDAGToDAGISel::PostprocessISelDAG() | void RISCVDAGToDAGISel::PostprocessISelDAG() {
HandleSDNode Dummy(CurDAG->getRoot());
SelectionDAG::allnodes_iterator Position = CurDAG->allnodes_end();
bool MadeChange = false;
while (Position != CurDAG->allnodes_begin()) {
SDNode *N = &*--Position;
// Skip dead nodes and any non-machine opcodes.
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x80, %rsp
movq %rdi, %rbx
movq 0x38(%rdi), %rax
movq 0x140(%rax), %rsi
movl 0x148(%rax), %edx
movq %rsp, %rdi
callq 0xd78682
movq 0x38(%rbx), %rdi
leaq 0x150(%rdi), %r12
cmpq 0x158(%rdi), %r12
je 0x11915e9
xorl %r15d, %r15d
movq (%r12), %r12
leaq -0x8(%r12),... | /Target/RISCV/RISCVISelDAGToDAG.cpp |
llvm::RISCVDAGToDAGISel::selectSHXADDOp(llvm::SDValue, unsigned int, llvm::SDValue&) | bool RISCVDAGToDAGISel::selectSHXADDOp(SDValue N, unsigned ShAmt,
SDValue &Val) {
if (N.getOpcode() == ISD::AND && isa<ConstantSDNode>(N.getOperand(1))) {
SDValue N0 = N.getOperand(0);
bool LeftShift = N0.getOpcode() == ISD::SHL;
if ((LeftShift || N0.getOpcode() == ... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xc8, %rsp
movl %ecx, %r12d
movl %edx, %r9d
movq %rsi, %r15
movq %rdi, %r14
cmpl $0xb9, 0x18(%rsi)
jne 0x119b66b
movq 0x28(%r15), %rax
movq 0x28(%rax), %rcx
movl 0x18(%rcx), %edx
cmpl $0x23, %edx
je 0x119b591
cmpl $0xb, %edx
jne 0x119b66b
movq (%ra... | /Target/RISCV/RISCVISelDAGToDAG.cpp |
llvm::RISCVTargetLowering::lowerINSERT_SUBVECTOR(llvm::SDValue, llvm::SelectionDAG&) const | SDValue RISCVTargetLowering::lowerINSERT_SUBVECTOR(SDValue Op,
SelectionDAG &DAG) const {
SDValue Vec = Op.getOperand(0);
SDValue SubVec = Op.getOperand(1);
MVT VecVT = Vec.getSimpleValueType();
MVT SubVecVT = SubVec.getSimpleValueType();
SDLoc DL(Op);
MVT... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x378, %rsp # imm = 0x378
movq %rcx, %r15
movl %edx, %ebx
movq %rsi, %r14
movq %rdi, %rbp
movq 0x28(%rsi), %rax
movq (%rax), %rsi
movl 0x8(%rax), %edx
movl 0xc(%rax), %ecx
movl %ecx, 0x7c(%rsp)
movq 0x28(%rax), %r8
movl 0x30(%rax), %edi
... | /Target/RISCV/RISCVISelLowering.cpp |
lowerGetVectorLength(llvm::SDNode*, llvm::SelectionDAG&, llvm::RISCVSubtarget const&) | static SDValue lowerGetVectorLength(SDNode *N, SelectionDAG &DAG,
const RISCVSubtarget &Subtarget) {
MVT XLenVT = Subtarget.getXLenVT();
// The smallest LMUL is only valid for the smallest element width.
const unsigned ElementWidth = 8;
// Determine the VF that corresponds ... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xc8, %rsp
movq %rsi, %rbx
movq %rdi, %r15
movq 0x28(%rdi), %rax
movq 0x50(%rax), %rax
movq 0x58(%rax), %rax
cmpl $0x41, 0x20(%rax)
jb 0x11d07de
movq 0x18(%rax), %rax
jmp 0x11d07e2
addq $0x18, %rax
movb 0x1d7(%rdx), %bpl
movl (%rax), %ecx
cmpl $0x7... | /Target/RISCV/RISCVISelLowering.cpp |
processVCIXOperands(llvm::SDValue&, llvm::SmallVectorImpl<llvm::SDValue>&, llvm::SelectionDAG&) | static void processVCIXOperands(SDValue &OrigOp,
SmallVectorImpl<SDValue> &Operands,
SelectionDAG &DAG) {
promoteVCIXScalar(OrigOp, Operands, DAG);
const RISCVSubtarget &Subtarget =
DAG.getMachineFunction().getSubtarget<RISCVSubtarget>();
for (... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %rdx, 0x20(%rsp)
movq %rsi, %r14
movq 0x28(%rdx), %rax
movq (%rdi), %r15
movl 0x18(%r15), %ecx
addl $-0x2f, %ecx
xorl %edx, %edx
cmpl $0x2, %ecx
setb %dl
movq 0x28(%r15), %rcx
leaq (%rdx,%rdx,4), %rdx
movq (%rcx,%rdx,8), %rcx
movq 0... | /Target/RISCV/RISCVISelLowering.cpp |
performSETCCCombine(llvm::SDNode*, llvm::SelectionDAG&, llvm::RISCVSubtarget const&) | static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG,
const RISCVSubtarget &Subtarget) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
EVT VT = N->getValueType(0);
EVT OpVT = N0.getValueType();
if (OpVT != MVT::i64 || !Subtarget.is64Bit())
ret... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xf8, %rsp
movq %rdx, %rax
movq %rsi, %rbx
movq %rdi, %r13
movq 0x28(%rdi), %rdi
movq (%rdi), %r12
movl 0x8(%rdi), %edx
movq 0x30(%r12), %rcx
movq %rdx, %rsi
shlq $0x4, %rsi
movb (%rcx,%rsi), %r14b
cmpb $0x8, %r14b
jne 0x11e2f03
cmpb $0x1, 0x1d7(%r... | /Target/RISCV/RISCVISelLowering.cpp |
performTRUNCATECombine(llvm::SDNode*, llvm::SelectionDAG&, llvm::RISCVSubtarget const&) | static SDValue performTRUNCATECombine(SDNode *N, SelectionDAG &DAG,
const RISCVSubtarget &Subtarget) {
SDValue N0 = N->getOperand(0);
EVT VT = N->getValueType(0);
// Pre-promote (i1 (truncate (srl X, Y))) on RV64 with Zbs without zero
// extending X. This is safe since we ... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x108, %rsp # imm = 0x108
movq %rsi, %rbp
cmpb $0x0, 0x46d6012(%rip) # 0x58b9fb0
jne 0x11e41ac
cmpb $0x1, 0x1d7(%rdx)
jne 0x11e41ac
movq 0x30(%rdi), %rax
movb (%rax), %r15b
cmpb $0x2, %r15b
sete %cl
andb 0x16f(%rdx), %cl
cmpb $0x1, %cl... | /Target/RISCV/RISCVISelLowering.cpp |
(anonymous namespace)::canFoldToVWWithSameExtensionImpl(llvm::SDNode*, (anonymous namespace)::NodeExtensionHelper const&, (anonymous namespace)::NodeExtensionHelper const&, unsigned char, llvm::SelectionDAG&, llvm::RISCVSubtarget const&) | static std::optional<CombineResult>
canFoldToVWWithSameExtensionImpl(SDNode *Root, const NodeExtensionHelper &LHS,
const NodeExtensionHelper &RHS,
uint8_t AllowExtMask, SelectionDAG &DAG,
const RISCVSubtarget &Subtarget) ... | movq %rdi, %rax
testb $0x1, %r8b
je 0x11fa8a7
cmpb $0x1, (%rdx)
jne 0x11fa8a7
cmpb $0x1, (%rcx)
jne 0x11fa8a7
movl 0x18(%rsi), %r9d
movw $0x101, %di # imm = 0x101
movl $0x285, %r8d # imm = 0x285
cmpl $0x23e, %r9d # imm = 0x23E
jle 0x11fa94f
cmpl $0x287, %r9d # imm = 0x287
jl... | /Target/RISCV/RISCVISelLowering.cpp |
EmitHiLo(llvm::MCStreamer&, llvm::MCSymbol*, llvm::SparcMCExpr::VariantKind, llvm::SparcMCExpr::VariantKind, llvm::MCOperand&, llvm::MCContext&, llvm::MCSubtargetInfo const&) | static void EmitHiLo(MCStreamer &OutStreamer, MCSymbol *GOTSym,
SparcMCExpr::VariantKind HiKind,
SparcMCExpr::VariantKind LoKind,
MCOperand &RD,
MCContext &OutContext,
const MCSubtargetInfo &STI) {
MCOperand hi ... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %r9, %r12
movq %r8, %rbx
movl %ecx, %ebp
movl %edx, %r13d
movq %rsi, %r14
movq %rdi, %r15
movq %rsi, %rdi
xorl %esi, %esi
movq %r9, %rdx
xorl %ecx, %ecx
callq 0x1af074a
movl %r13d, %edi
movq %rax, %rsi
movq %r12, %rdx
callq 0x1647f0... | /Target/Sparc/SparcAsmPrinter.cpp |
llvm::SparcFrameLowering::remapRegsForLeafProc(llvm::MachineFunction&) const | void SparcFrameLowering::remapRegsForLeafProc(MachineFunction &MF) const {
MachineRegisterInfo &MRI = MF.getRegInfo();
// Remap %i[0-7] to %o[0-7].
for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
if (!MRI.isPhysRegUsed(reg))
continue;
unsigned mapped_reg = reg - SP::I0 + SP::O0;
// Replace... | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %rbx
movq 0x28(%rsi), %r14
xorl %r15d, %r15d
leal 0xa6(%r15), %ebp
movq %r14, %rdi
movl %ebp, %esi
xorl %edx, %edx
callq 0x17db56a
testb %al, %al
je 0x121a852
leal 0xb6(%r15), %edx
movq %r14, %rdi
movl %ebp, %esi
callq 0x17dade8
testb $0x1, %bpl
jne 0x12... | /Target/Sparc/SparcFrameLowering.cpp |
lowerSubvectorStore(llvm::MachineInstr const*, unsigned int) | static MCInst lowerSubvectorStore(const MachineInstr *MI, unsigned Opcode) {
return MCInstBuilder(Opcode)
.addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
.addReg(MI->getOperand(1).getReg())
.addImm(MI->getOperand(2).getImm())
.addReg(MI->getOperand(3).getReg())
.addImm(0);
} | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x80, %rsp
movq %rsi, %r15
movq %rdi, %rbx
leaq 0x10(%rsp), %r14
leaq 0x20(%rsp), %r12
xorps %xmm0, %xmm0
movaps %xmm0, -0x20(%r12)
movq %r12, -0x10(%r12)
movabsq $0x600000000, %r13 # imm = 0x600000000
movq %r13, -0x8(%r12)
movl %edx, -0x20(%r12)
movq 0x... | /Target/SystemZ/SystemZAsmPrinter.cpp |
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