name string | code string | asm string | file string |
|---|---|---|---|
llvm::DenseMapBase<llvm::DenseMap<std::pair<llvm::MCSymbol const*, unsigned int>, unsigned int, llvm::DenseMapInfo<std::pair<llvm::MCSymbol const*, unsigned int>, void>, llvm::detail::DenseMapPair<std::pair<llvm::MCSymbol const*, unsigned int>, unsigned int>>, std::pair<llvm::MCSymbol const*, unsigned int>, unsigned in... | iterator find(const_arg_type_t<KeyT> Val) {
BucketT *TheBucket;
if (LookupBucketFor(Val, TheBucket))
return makeIterator(TheBucket,
shouldReverseIterate<KeyT>() ? getBuckets()
: getBucketsEnd(),
*thi... | pushq %r14
pushq %rbx
pushq %rax
movq %rdi, %rbx
movq %rsp, %r14
movq %r14, %rdx
callq 0x1220d7a
movl 0x10(%rbx), %ecx
leaq (%rcx,%rcx,2), %rdx
shlq $0x3, %rdx
addq (%rbx), %rdx
testb %al, %al
movq (%r14), %rax
cmoveq %rdx, %rax
addq $0x8, %rsp
popq %rbx
popq %r14
retq
nop
| /llvm/ADT/DenseMap.h |
llvm::detail::DenseMapPair<std::pair<llvm::MCSymbol const*, unsigned int>, unsigned int>* llvm::DenseMapBase<llvm::DenseMap<std::pair<llvm::MCSymbol const*, unsigned int>, unsigned int, llvm::DenseMapInfo<std::pair<llvm::MCSymbol const*, unsigned int>, void>, llvm::detail::DenseMapPair<std::pair<llvm::MCSymbol const*, ... | BucketT *InsertIntoBucketImpl(const KeyT &Key, const LookupKeyT &Lookup,
BucketT *TheBucket) {
incrementEpoch();
// If the load of the hash table is more than 3/4, or if fewer than 1/8 of
// the buckets are empty (meaning that many are filled with tombstones),
// grow th... | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rcx, %rax
movq %rdx, %r14
movq %rdi, %rbx
movl 0x8(%rdi), %ecx
movl 0x10(%rdi), %esi
leal 0x4(,%rcx,4), %edx
leal (%rsi,%rsi,2), %edi
cmpl %edi, %edx
jae 0x1220f35
notl %ecx
addl %esi, %ecx
subl 0xc(%rbx), %ecx
movl %esi, %edx
shrl $0x3, %edx
cmpl %edx, %ecx
jbe 0... | /llvm/ADT/DenseMap.h |
llvm::format_provider<char const*, void>::format(char const* const&, llvm::raw_ostream&, llvm::StringRef) | static void format(const T &V, llvm::raw_ostream &Stream, StringRef Style) {
size_t N = StringRef::npos;
if (!Style.empty() && Style.getAsInteger(10, N)) {
assert(false && "Style is not a valid integer");
}
llvm::StringRef S = V;
Stream << S.substr(0, N);
} | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rsi, %rbx
movq %rdi, %r15
testq %rcx, %rcx
je 0x1221552
leaq 0x8(%rsp), %rax
movq %rdx, %rdi
movq %rcx, %rsi
movl $0xa, %edx
movq %rax, %rcx
callq 0x1cc39ba
movq $-0x1, %r14
testb %al, %al
jne 0x1221559
movq 0x8(%rsp), %r14
jmp 0x1221559
movq $-0x1, %r14
movq (%r1... | /llvm/Support/FormatProviders.h |
llvm::ADDR64BitGetRawAllocationOrder(llvm::MachineFunction const&) | iterator begin() const { return RegsBegin; } | leaq 0x45ae242(%rip), %rax # 0x57d7670
movq 0x200(%rax), %rcx
movzwl 0x214(%rax), %eax
movq %rcx, -0x28(%rsp)
movq %rax, -0x20(%rsp)
leaq 0x2bc5983(%rip), %rax # 0x3deedd0
movq %rax, -0x18(%rsp)
movq $0xf, -0x10(%rsp)
movq 0x10(%rdi), %rax
movl 0x17c(%rax), %ecx
movl 0x184(%rax), %eax
xorl $0x4, %eax
xorl $0xf, %ec... | /llvm/MC/MCRegisterInfo.h |
llvm::TargetTransformInfoImplCRTPBase<llvm::SystemZTTIImpl>::getPointersChainCost(llvm::ArrayRef<llvm::Value const*>, llvm::Value const*, llvm::TargetTransformInfo::PointersChainInfo const&, llvm::Type*, llvm::TargetTransformInfo::TargetCostKind) | InstructionCost getPointersChainCost(ArrayRef<const Value *> Ptrs,
const Value *Base,
const TTI::PointersChainInfo &Info,
Type *AccessTy,
TTI::TargetCostKind CostKi... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xa8, %rsp
movq %r9, 0x38(%rsp)
movq %r8, 0x40(%rsp)
movq %rcx, 0x48(%rsp)
testq %rdx, %rdx
je 0x122cbf8
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, 0x30(%rsp)
leaq -0x8(%rdi), %rax
movq %rax, 0x28(%rsp)
shlq $0x3, %r12
xorl %r15d, %r15d
movl $0x0, ... | /llvm/Analysis/TargetTransformInfoImpl.h |
llvm::BasicTTIImplBase<llvm::SystemZTTIImpl>::simplifyDemandedVectorEltsIntrinsic(llvm::InstCombiner&, llvm::IntrinsicInst&, llvm::APInt, llvm::APInt&, llvm::APInt&, llvm::APInt&, std::function<void (llvm::Instruction*, unsigned int, llvm::APInt, llvm::APInt&)>) | std::optional<Value *> simplifyDemandedVectorEltsIntrinsic(
InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
APInt &UndefElts2, APInt &UndefElts3,
std::function<void(Instruction *, unsigned, APInt, APInt &)>
SimplifyAndSetOp) {
return BaseT::simplifyDemandedVect... | pushq %r14
pushq %rbx
subq $0x38, %rsp
movq 0x58(%rsp), %rbx
movl 0x8(%rcx), %eax
movl %eax, 0x8(%rsp)
cmpl $0x40, %eax
ja 0x122e1d5
movq (%rcx), %rax
movq %rax, (%rsp)
jmp 0x122e1e0
movq %rsp, %rdi
movq %rcx, %rsi
callq 0x1c8174e
xorps %xmm0, %xmm0
movaps %xmm0, 0x20(%rsp)
movaps %xmm0, 0x10(%rsp)
movq 0x10(%rbx), %ra... | /llvm/CodeGen/BasicTTIImpl.h |
llvm::BasicTTIImplBase<llvm::SystemZTTIImpl>::isTypeLegal(llvm::Type*) | bool isTypeLegal(Type *Ty) {
EVT VT = getTLI()->getValueType(DL, Ty, /*AllowUnknown=*/true);
return getTLI()->isTypeLegal(VT);
} | pushq %rbx
movq %rsi, %rdx
movq %rdi, %rbx
movq 0x8(%rdi), %rsi
movq 0x18(%rdi), %rdi
movl $0x1, %ecx
callq 0x8f1f84
testb %al, %al
je 0x122e279
movq 0x18(%rbx), %rcx
movzbl %al, %eax
cmpq $0x0, 0x68(%rcx,%rax,8)
setne %al
jmp 0x122e27b
xorl %eax, %eax
popq %rbx
retq
nop
| /llvm/CodeGen/BasicTTIImpl.h |
llvm::SystemZTTIImpl::adjustInliningThreshold(llvm::CallBase const*) const | operator Value *() const { return Val; } | movq -0x20(%rsi), %rax
xorl %edi, %edi
testq %rax, %rax
je 0x1232b30
cmpb $0x0, (%rax)
cmoveq %rax, %rdi
testq %rdi, %rdi
je 0x1232b3f
movq 0x18(%rdi), %rax
cmpq 0x50(%rsi), %rax
je 0x1232b41
xorl %edi, %edi
pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x10, %rsp
xorl %ebp, %ebp
testq %rdi, %rdi
je 0x12... | /llvm/IR/Use.h |
llvm::BasicTTIImplBase<llvm::SystemZTTIImpl>::getScalarizationOverhead(llvm::VectorType*, llvm::ArrayRef<llvm::Value const*>, llvm::ArrayRef<llvm::Type*>, llvm::TargetTransformInfo::TargetCostKind) | InstructionCost getScalarizationOverhead(VectorType *RetTy,
ArrayRef<const Value *> Args,
ArrayRef<Type *> Tys,
TTI::TargetCostKind CostKind) {
InstructionCost Cost = getScalarizationOver... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %r9, 0x10(%rsp)
movq %r8, 0x8(%rsp)
movq %rcx, %r13
movq %rdx, %r14
movq %rsi, %r12
movq %rdi, %r15
movl 0x50(%rsp), %r8d
movl $0x1, %edx
xorl %ecx, %ecx
callq 0x122e4e2
movq %rax, %rbx
movl %edx, %ebp
movq %r15, %rdi
testq %r13, %r... | /llvm/CodeGen/BasicTTIImpl.h |
llvm::SystemZTargetLowering::LowerOperationWrapper(llvm::SDNode*, llvm::SmallVectorImpl<llvm::SDValue>&, llvm::SelectionDAG&) const | void
SystemZTargetLowering::LowerOperationWrapper(SDNode *N,
SmallVectorImpl<SDValue> &Results,
SelectionDAG &DAG) const {
switch (N->getOpcode()) {
case ISD::ATOMIC_LOAD: {
SDLoc DL(N);
SDVTList Tys = DAG.getVTList(MV... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x178, %rsp # imm = 0x178
movq %rcx, %r14
movq %rdx, %rbx
movq %rsi, %r15
movl 0x18(%rsi), %eax
cmpl $0x149, %eax # imm = 0x149
jg 0x1255a0b
cmpl $0xe6, %eax
jne 0x1255b77
movq 0x30(%r15), %rax
cmpb $0x9, (%rax)
jne 0x1255fcf
... | /Target/SystemZ/SystemZISelLowering.cpp |
getADAEntry(llvm::SelectionDAG&, llvm::SDValue, llvm::SDLoc, unsigned int, bool) | static SDValue getADAEntry(SelectionDAG &DAG, SDValue Val, SDLoc DL,
unsigned Offset, bool LoadAdr = false) {
MachineFunction &MF = DAG.getMachineFunction();
SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>();
unsigned ADAvReg = MFI->getADAVirtualRegister();
EV... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xe8, %rsp
movl %r9d, 0x54(%rsp)
movl %r8d, %r15d
movq %rcx, %r13
movl %edx, 0x50(%rsp)
movq %rsi, 0x58(%rsp)
movq %rdi, %r14
movq 0x10(%rdi), %rbp
movq 0x28(%rdi), %rdi
movq 0x30(%rdi), %rax
movl 0x3c(%rax), %r12d
callq 0x1789320
movq (%rbp), %rcx... | /Target/SystemZ/SystemZISelLowering.cpp |
(anonymous namespace)::SystemZPostRewrite::SystemZPostRewrite() | SystemZPostRewrite() : MachineFunctionPass(ID) {
initializeSystemZPostRewritePass(*PassRegistry::getPassRegistry());
} | pushq %rax
xorl %eax, %eax
movq %rax, 0x8(%rdi)
leaq 0x464f4ea(%rip), %rcx # 0x58ba724
movq %rcx, 0x10(%rdi)
movl $0x2, 0x18(%rdi)
xorps %xmm0, %xmm0
movups %xmm0, 0x20(%rdi)
movq %rax, 0x30(%rdi)
leaq 0x44f3591(%rip), %rax # 0x575e7e8
movq %rax, (%rdi)
callq 0x1a82116
movq %rsp, %rdx
movq %rax, (%rdx)
leaq 0x464f4... | /Target/SystemZ/SystemZPostRewrite.cpp |
llvm::SystemZELFFrameLowering::usePackedStack(llvm::MachineFunction&) const | bool SystemZELFFrameLowering::usePackedStack(MachineFunction &MF) const {
bool HasPackedStackAttr = MF.getFunction().hasFnAttribute("packed-stack");
const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>();
bool BackChain = Subtarget.hasBackChain();
bool SoftFloat = Subtarget.hasSoftFloat();
if... | pushq %rbx
movq %rsi, %rbx
movq (%rsi), %rdi
leaq 0x2b91cdf(%rip), %rsi # 0x3dff8e3
movl $0xc, %edx
callq 0x1a2e4f6
testb %al, %al
je 0x126dc28
movq 0x10(%rbx), %rcx
cmpb $0x0, 0x121(%rcx)
je 0x126dc28
cmpb $0x0, 0x142(%rcx)
je 0x126dc42
movq (%rbx), %rcx
movzwl 0x2(%rcx), %ecx
andl $0x3ff0, %ecx # imm = 0x... | /Target/SystemZ/SystemZFrameLowering.cpp |
llvm::SystemZXPLINKFrameLowering::assignCalleeSavedSpillSlots(llvm::MachineFunction&, llvm::TargetRegisterInfo const*, std::vector<llvm::CalleeSavedInfo, std::allocator<llvm::CalleeSavedInfo>>&) const | bool SystemZXPLINKFrameLowering::assignCalleeSavedSpillSlots(
MachineFunction &MF, const TargetRegisterInfo *TRI,
std::vector<CalleeSavedInfo> &CSI) const {
MachineFrameInfo &MFFrame = MF.getFrameInfo();
SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>();
const SystemZSubtarget &Su... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x48, %rsp
movq %rcx, %r12
movq %rdx, %rbx
movq %rsi, %r13
movq %rdi, 0x30(%rsp)
movq 0x38(%rsi), %rax
movq %rax, 0x20(%rsp)
movq 0x10(%rsi), %r15
movq 0x30(%rsi), %r14
movq (%rcx), %rax
cmpq 0x8(%rcx), %rax
jne 0x12706a5
movq 0x20(%rsp), %rax
cmpb... | /Target/SystemZ/SystemZFrameLowering.cpp |
createMemMemNode(llvm::SelectionDAG&, llvm::SDLoc const&, unsigned int, llvm::SDValue, llvm::SDValue, llvm::SDValue, llvm::SDValue, llvm::SDValue) | static SDValue createMemMemNode(SelectionDAG &DAG, const SDLoc &DL, unsigned Op,
SDValue Chain, SDValue Dst, SDValue Src,
SDValue LenAdj, SDValue Byte) {
SDVTList VTs = Op == SystemZISD::CLC ? DAG.getVTList(MVT::i32, MVT::Other)
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xe8, %rsp
movl %r8d, %r13d
movq %rcx, %rbx
movl %edx, %ebp
movq %rsi, 0x20(%rsp)
movq %rdi, %r14
cmpl $0x204, %edx # imm = 0x204
jne 0x1275c1a
movl $0x7, %esi
xorl %edx, %edx
movl $0x1, %ecx
xorl %r8d, %r8d
callq 0x1f2df6c
jmp 0x1275c26... | /Target/SystemZ/SystemZSelectionDAGInfo.cpp |
emitLEASLrri(llvm::MCStreamer&, llvm::MCOperand&, llvm::MCOperand&, llvm::MCOperand&, llvm::MCOperand&, llvm::MCSubtargetInfo const&) | static void emitLEASLrri(MCStreamer &OutStreamer, MCOperand &RS1,
MCOperand &RS2, MCOperand &Imm, MCOperand &RD,
const MCSubtargetInfo &STI) {
MCInst LEASLInst;
LEASLInst.setOpcode(VE::LEASLrri);
LEASLInst.addOperand(RD);
LEASLInst.addOperand(RS1);
LEASLInst.a... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x98, %rsp
movq %r9, 0x8(%rsp)
movq %rcx, %r15
movq %rdx, %r13
movq %rsi, %rbp
movq %rdi, %r14
leaq 0x20(%rsp), %r12
leaq 0x30(%rsp), %rbx
xorps %xmm0, %xmm0
movaps %xmm0, -0x20(%rbx)
movq %rbx, -0x10(%rbx)
movabsq $0x600000000, %rax # imm = 0... | /Target/VE/VEAsmPrinter.cpp |
llvm::TargetTransformInfo::Model<llvm::VETTIImpl>::simplifyDemandedVectorEltsIntrinsic(llvm::InstCombiner&, llvm::IntrinsicInst&, llvm::APInt, llvm::APInt&, llvm::APInt&, llvm::APInt&, std::function<void (llvm::Instruction*, unsigned int, llvm::APInt, llvm::APInt&)>) | std::optional<Value *> simplifyDemandedVectorEltsIntrinsic(
InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
APInt &UndefElts2, APInt &UndefElts3,
std::function<void(Instruction *, unsigned, APInt, APInt &)>
SimplifyAndSetOp) override {
return Impl.simplifyDeman... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x48, %rsp
movq %r9, %rbx
movq %r8, 0x18(%rsp)
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %r13
movq 0x88(%rsp), %rbp
movl 0x8(%rcx), %eax
movl %eax, 0x10(%rsp)
cmpl $0x40, %eax
ja 0x127763f
movq (%rcx), %rax
movq %rax, 0x8(%rsp)
jmp 0x127764c
leaq ... | /llvm/Analysis/TargetTransformInfo.h |
llvm::initializeVEDAGToDAGISelLegacyPass(llvm::PassRegistry&) | bool VEDAGToDAGISel::selectADDRrri(SDValue Addr, SDValue &Base, SDValue &Index,
SDValue &Offset) {
if (Addr.getOpcode() == ISD::FrameIndex)
return false;
if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
Addr.getOpcode() == ISD::TargetGlobalAddress ||
Addr.getOp... | pushq %rax
movq %rsp, %rdx
movq %rdi, (%rdx)
leaq 0x463a341(%rip), %rdi # 0x58ba8b4
leaq 0x7(%rip), %rsi # 0x1280581
callq 0x90ae4f
popq %rax
retq
| /Target/VE/VEISelDAGToDAG.cpp |
llvm::VEInstrInfo::expandGetStackTopPseudo(llvm::MachineInstr&) const | bool VEInstrInfo::expandGetStackTopPseudo(MachineInstr &MI) const {
MachineBasicBlock *MBB = MI.getParent();
MachineFunction &MF = *MBB->getParent();
const VESubtarget &STI = MF.getSubtarget<VESubtarget>();
const VEInstrInfo &TII = *STI.getInstrInfo();
DebugLoc DL = MBB->findDebugLoc(MI);
// Create followi... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x58, %rsp
movq %rsi, %rbx
movq 0x18(%rsi), %r15
movq 0x20(%r15), %r13
movq 0x10(%r13), %r14
movq (%r14), %rax
movq %r14, %rdi
callq *0x80(%rax)
movq %rax, 0x10(%rsp)
leaq 0x8(%rsp), %rdi
movq %r15, %rsi
movq %rbx, %rdx
callq 0x1753b92
movq 0x38(%r... | /Target/VE/VEInstrInfo.cpp |
llvm::VETargetLowering::initVPUActions() | void VETargetLowering::initVPUActions() {
for (MVT LegalMaskVT : AllMaskVTs)
setOperationAction(ISD::BUILD_VECTOR, LegalMaskVT, Custom);
for (unsigned Opc : {ISD::AND, ISD::OR, ISD::XOR})
setOperationAction(Opc, MVT::v512i1, Custom);
for (MVT LegalVecVT : AllVectorVTs) {
setOperationAction(ISD::BUIL... | leaq 0x10ea(%rdi), %rax
xorl %edx, %edx
leaq 0x2b8517b(%rip), %rcx # 0x3e113b5
movzbl (%rdx,%rcx), %esi
imulq $0x1e5, %rsi, %rsi # imm = 0x1E5
movb $0x4, 0x9b(%rax,%rsi)
incq %rdx
cmpq $0x2, %rdx
jne 0x128c23a
movabsq $0xba000000b9, %rdx # imm = 0xBA000000B9
movq %rdx, -0x18(%rsp)
movl $0xbb, -0x10(%rsp)
xor... | /Target/VE/VEISelLowering.cpp |
llvm::VETargetLowering::getRegisterByName(char const*, llvm::LLT, llvm::MachineFunction const&) const | Register VETargetLowering::getRegisterByName(const char *RegName, LLT VT,
const MachineFunction &MF) const {
Register Reg = StringSwitch<Register>(RegName)
.Case("sp", VE::SX11) // Stack pointer
.Case("fp", VE::SX9) // Frame... | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %rbx
testq %rsi, %rsi
je 0x128cf1a
movq %rbx, %rdi
callq 0x7512e0
movq %rax, %r14
jmp 0x128cf1d
xorl %r14d, %r14d
cmpq $0x2, %r14
jne 0x128cf3d
leaq 0x1f134ad(%rip), %rsi # 0x31a03d7
movq %rbx, %rdi
movq %r14, %rdx
callq 0x751d10
testl %eax, %eax
sete ... | /Target/VE/VEISelLowering.cpp |
llvm::VETargetLowering::lowerATOMIC_SWAP(llvm::SDValue, llvm::SelectionDAG&) const | SDValue VETargetLowering::lowerATOMIC_SWAP(SDValue Op,
SelectionDAG &DAG) const {
SDLoc DL(Op);
AtomicSDNode *N = cast<AtomicSDNode>(Op);
if (N->getMemoryVT() == MVT::i8) {
// For i8, use "ts1am"
// Input:
// ATOMIC_SWAP Ptr, Val, Order
//
// ... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x118, %rsp # imm = 0x118
movq %rcx, %rbx
movl %edx, %ebp
movq %rsi, %r14
movq 0x48(%rsi), %rsi
movq %rsi, 0x28(%rsp)
testq %rsi, %rsi
je 0x128eba2
leaq 0x28(%rsp), %rdi
movl $0x1, %edx
callq 0x1a648a8
movl 0x44(%r14), %eax
movl %eax, 0x... | /Target/VE/VEISelLowering.cpp |
llvm::VETargetLowering::legalizeInternalLoadStoreOp(llvm::SDValue, llvm::VECustomDAG&) const | SDValue VETargetLowering::legalizeInternalLoadStoreOp(SDValue Op,
VECustomDAG &CDAG) const {
LLVM_DEBUG(dbgs() << "::legalizeInternalLoadStoreOp\n";);
MVT DataVT = getIdiomaticVectorType(Op.getNode())->getSimpleVT();
// TODO: Recognize packable load,store.
... | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
subq $0x18, %rsp
movq %rcx, %rbx
movl %edx, %ebp
movq %rsi, %r14
movq %rsp, %r15
movq %r15, %rdi
callq 0x129b824
movl (%r15), %edi
xorl %esi, %esi
callq 0x129b2f9
movq %r14, %rsi
movl %ebp, %edx
movq %rbx, %rcx
testb %al, %al
je 0x129ac08
callq 0x129a73c
jmp 0x129ac0d
callq 0... | /Target/VE/VVPISelLowering.cpp |
llvm::SmallSet<llvm::StringRef, 4u, std::less<llvm::StringRef>>::insert(llvm::StringRef const&) | std::pair<const_iterator, bool> insert(const T &V) {
if (!isSmall()) {
auto [I, Inserted] = Set.insert(V);
return std::make_pair(const_iterator(I), Inserted);
}
VIterator I = vfind(V);
if (I != Vector.end()) // Don't reinsert if it already exists.
return std::make_pair(const_iterat... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %r15
movq %rsi, %r14
movq %rdi, %rbx
cmpq $0x0, 0x78(%rsi)
je 0x129e543
addq $0x50, %r14
movq %r14, %rdi
movq %r15, %rsi
callq 0x129f0be
xorl %ecx, %ecx
jmp 0x129e591
movq %r14, %rdi
movq %r15, %rsi
callq 0x129f068
movl 0x8(%r14), %ecx
movq %rcx, %rdx
sh... | /llvm/ADT/SmallSet.h |
std::pair<llvm::DenseMapIterator<llvm::MCSymbol*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::MCSymbol*, void>, llvm::detail::DenseSetPair<llvm::MCSymbol*>, false>, bool> llvm::DenseMapBase<llvm::DenseMap<llvm::MCSymbol*, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<llvm::MCSymbol*, void>, llvm::detail::De... | std::pair<iterator, bool> try_emplace(KeyT &&Key, Ts &&... Args) {
BucketT *TheBucket;
if (LookupBucketFor(Key, TheBucket))
return std::make_pair(makeIterator(TheBucket,
shouldReverseIterate<KeyT>()
? getBuckets()
... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %r15
movq %rsi, %r14
movq %rdi, %rbx
movq %rsp, %r12
movq %rsi, %rdi
movq %rdx, %rsi
movq %r12, %rdx
callq 0x1063df6
movl %eax, %ecx
movq (%r12), %rax
testb %cl, %cl
je 0x129efd2
xorl %ecx, %ecx
jmp 0x129efeb
movq %r14, %rdi
movq %r15, %rsi
movq %r15, %r... | /llvm/ADT/DenseMap.h |
std::pair<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char>>, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char>>>& llvm::SmallVectorTemplateBase<std::pair<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char>>, std::__cxx11::basic_string<ch... | T &growAndEmplaceBack(ArgTypes &&... Args) {
// Grow manually in case one of Args is an internal reference.
size_t NewCapacity;
T *NewElts = mallocForGrow(0, NewCapacity);
::new ((void *)(NewElts + this->size())) T(std::forward<ArgTypes>(Args)...);
moveElementsForGrow(NewElts);
takeAllocationFor... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %rbx
leaq 0x10(%rdi), %r15
movq %rsp, %rbp
movl $0x40, %ecx
movq %r15, %rsi
xorl %edx, %edx
movq %rbp, %r8
callq 0x1cba3de
movq %rax, %r14
movl 0x8(%rbx), %edi
shlq $0x6, %rdi
addq %rax, %rdi
movq %r1... | /llvm/ADT/SmallVector.h |
llvm::WebAssemblyMCInstLower::lowerTypeIndexOperand(llvm::SmallVectorImpl<llvm::wasm::ValType>&&, llvm::SmallVectorImpl<llvm::wasm::ValType>&&) const | MCOperand WebAssemblyMCInstLower::lowerTypeIndexOperand(
SmallVectorImpl<wasm::ValType> &&Returns,
SmallVectorImpl<wasm::ValType> &&Params) const {
auto Signature = Ctx.createWasmSignature();
Signature->Returns = std::move(Returns);
Signature->Params = std::move(Params);
MCSymbol *Sym = Printer.createTe... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %rbx
movq (%rdi), %rdi
callq 0x1ae1264
movq %rax, %r12
movq %rax, %rdi
movq %r15, %rsi
callq 0x8b82ee
leaq 0x18(%r12), %rdi
movq %r14, %rsi
callq 0x8b82ee
movq 0x8(%rbx), %rdi
leaq 0x1ff30a5(%rip), %rax # 0x3295485... | /Target/WebAssembly/WebAssemblyMCInstLower.cpp |
(anonymous namespace)::WebAssemblyCFGStackify::registerTryScope(llvm::MachineInstr*, llvm::MachineInstr*, llvm::MachineBasicBlock*) | void WebAssemblyCFGStackify::registerTryScope(MachineInstr *Begin,
MachineInstr *End,
MachineBasicBlock *EHPad) {
registerScope(Begin, End);
TryToEHPad[Begin] = EHPad;
EHPadToTry[EHPad] = Begin;
} | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %rdx, %r12
movq %rdi, %rbx
leaq 0x10(%rsp), %r15
movq %rsi, (%r15)
leaq 0x8(%rsp), %r14
movq %rcx, (%r14)
leaq 0x20(%rsp), %r13
movq %rsi, (%r13)
leaq 0x18(%rsp), %rbp
movq %rdx, (%rbp)
addq $0x88, %rdi
movq %r13, %rsi
callq 0x12b2c... | /Target/WebAssembly/WebAssemblyCFGStackify.cpp |
llvm::WebAssemblyExceptionInfo::runOnMachineFunction(llvm::MachineFunction&) | bool WebAssemblyExceptionInfo::runOnMachineFunction(MachineFunction &MF) {
LLVM_DEBUG(dbgs() << "********** Exception Info Calculation **********\n"
"********** Function: "
<< MF.getName() << '\n');
releaseMemory();
if (MF.getTarget().getMCAsmInfo()->getExceptionHandling... | pushq %r15
pushq %r14
pushq %rbx
movq %rsi, %rbx
movq %rdi, %r14
callq 0x12b7a64
movq 0x8(%rbx), %rax
movq 0x260(%rax), %rax
cmpl $0x5, 0x1a4(%rax)
jne 0x12b7a5b
movq (%rbx), %rax
testb $0x8, 0x2(%rax)
je 0x12b7a5b
movq 0x8(%r14), %rax
movq (%rax), %rdx
movq 0x8(%rax), %rax
xorl %edi, %edi
leaq 0x4614ed9(%rip), %rcx ... | /Target/WebAssembly/WebAssemblyExceptionInfo.cpp |
llvm::DenseMapBase<llvm::DenseMap<llvm::MachineBasicBlock const*, llvm::WebAssemblyException*, llvm::DenseMapInfo<llvm::MachineBasicBlock const*, void>, llvm::detail::DenseMapPair<llvm::MachineBasicBlock const*, llvm::WebAssemblyException*>>, llvm::MachineBasicBlock const*, llvm::WebAssemblyException*, llvm::DenseMapIn... | bool erase(const KeyT &Val) {
BucketT *TheBucket;
if (!LookupBucketFor(Val, TheBucket))
return false; // not in map.
TheBucket->getSecond().~ValueT();
TheBucket->getFirst() = getTombstoneKey();
decrementNumEntries();
incrementNumTombstones();
return true;
} | pushq %rbx
subq $0x10, %rsp
movq %rdi, %rbx
leaq 0x8(%rsp), %rdx
callq 0x12b31ce
testb %al, %al
je 0x12b969e
movq 0x8(%rsp), %rcx
movq $-0x2000, (%rcx) # imm = 0xE000
movq 0x8(%rbx), %xmm0
paddd 0x20d3a27(%rip), %xmm0 # 0x338d0c0
movq %xmm0, 0x8(%rbx)
addq $0x10, %rsp
popq %rbx
retq
| /llvm/ADT/DenseMap.h |
llvm::DenseMap<llvm::MachineBasicBlock const*, llvm::WebAssemblyException*, llvm::DenseMapInfo<llvm::MachineBasicBlock const*, void>, llvm::detail::DenseMapPair<llvm::MachineBasicBlock const*, llvm::WebAssemblyException*>>::grow(unsigned int) | void grow(unsigned AtLeast) {
unsigned OldNumBuckets = NumBuckets;
BucketT *OldBuckets = Buckets;
allocateBuckets(std::max<unsigned>(64, static_cast<unsigned>(NextPowerOf2(AtLeast-1))));
assert(Buckets);
if (!OldBuckets) {
this->BaseT::initEmpty();
return;
}
this->moveFromOldBu... | pushq %r15
pushq %r14
pushq %rbx
movq %rdi, %r15
movl 0x10(%rdi), %ebx
movq (%rdi), %r14
leal -0x1(%rsi), %eax
movl %eax, %ecx
shrl %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x2, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x4, %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x8, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x10,... | /llvm/ADT/DenseMap.h |
llvm::po_iterator<llvm::MachineDominatorTree*, llvm::SmallPtrSet<llvm::DomTreeNodeBase<llvm::MachineBasicBlock>*, 8u>, false, llvm::GraphTraits<llvm::MachineDominatorTree*>>::po_iterator(llvm::DomTreeNodeBase<llvm::MachineBasicBlock>*) | po_iterator(NodeRef BB) {
this->insertEdge(std::optional<NodeRef>(), BB);
VisitStack.emplace_back(BB, GT::child_begin(BB), GT::child_end(BB));
traverseChild();
} | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %rsi, %rdx
movq %rdi, %rbx
leaq 0x8(%rsp), %r14
movq %rsi, (%r14)
leaq 0x20(%rdi), %rax
movq %rax, (%rdi)
movq %rax, 0x8(%rdi)
movq $0x8, 0x10(%rdi)
movl $0x0, 0x18(%rdi)
leaq 0x60(%rdi), %r15
leaq 0x70(%rdi), %rax
movq %rax, 0x60(%rdi)
movabsq $0x800000... | /llvm/ADT/PostOrderIterator.h |
bool llvm::DenseMapBase<llvm::DenseMap<llvm::MachineBasicBlock*, llvm::SmallPtrSet<llvm::MachineBasicBlock*, 4u>, llvm::DenseMapInfo<llvm::MachineBasicBlock*, void>, llvm::detail::DenseMapPair<llvm::MachineBasicBlock*, llvm::SmallPtrSet<llvm::MachineBasicBlock*, 4u>>>, llvm::MachineBasicBlock*, llvm::SmallPtrSet<llvm::... | unsigned getNumBuckets() const {
return NumBuckets;
} | movl 0x10(%rdi), %ecx
testl %ecx, %ecx
je 0x12be566
pushq %rbx
movq (%rdi), %rdi
movl (%rsi), %r8d
movl %r8d, %eax
shrl $0x4, %eax
shrl $0x9, %r8d
xorl %eax, %r8d
decl %ecx
andl %ecx, %r8d
movl $0x1, %r10d
xorl %r9d, %r9d
movl %r8d, %r11d
leaq (%r11,%r11,8), %r11
leaq (%rdi,%r11,8), %r11
movq (%r11), %rbx
cmpq %rbx, (%... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<std::pair<llvm::Function*, llvm::FunctionType*>, llvm::Function*, llvm::DenseMapInfo<std::pair<llvm::Function*, llvm::FunctionType*>, void>, llvm::detail::DenseMapPair<std::pair<llvm::Function*, llvm::FunctionType*>, llvm::Function*>>, std::pair<llvm::Function*, llvm::FunctionType*>, l... | void moveFromOldBuckets(BucketT *OldBucketsBegin, BucketT *OldBucketsEnd) {
initEmpty();
// Insert all the old elements.
const KeyT EmptyKey = getEmptyKey();
const KeyT TombstoneKey = getTombstoneKey();
for (BucketT *B = OldBucketsBegin, *E = OldBucketsEnd; B != E; ++B) {
if (!KeyInfoT::isEqu... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movq $0x0, 0x8(%rdi)
movl 0x10(%rdi), %ecx
testq %rcx, %rcx
je 0x12bf930
movq (%r15), %rax
leaq (%rcx,%rcx,2), %rcx
leaq (%rax,%rcx,8), %rcx
movq $-0x1000, %rdx # imm = 0xF000
movq %rdx,... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::WebAssemblyDAGToDAGISel::PreprocessISelDAG() | void WebAssemblyDAGToDAGISel::PreprocessISelDAG() {
// Stack objects that should be allocated to locals are hoisted to WebAssembly
// locals when they are first used. However for those without uses, we hoist
// them here. It would be nice if there were some hook to do this when they
// are added to the Machin... | pushq %rbp
pushq %r14
pushq %rbx
movq 0x28(%rdi), %rax
movq 0x38(%rax), %r14
movq 0x10(%r14), %rax
subq 0x8(%r14), %rax
shrq $0x3, %rax
imull $0xcccccccd, %eax, %eax # imm = 0xCCCCCCCD
subl 0x20(%r14), %eax
testl %eax, %eax
jle 0x12c0f3e
movq %rdi, %rbx
xorl %ebp, %ebp
movq 0x28(%rbx), %rdi
movl %ebp, %esi
callq 0x12bf... | /Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp |
llvm::DenseMapBase<llvm::DenseMap<llvm::Register, std::vector<std::pair<llvm::SlotIndex, llvm::MachineInstr*>, std::allocator<std::pair<llvm::SlotIndex, llvm::MachineInstr*>>>, llvm::DenseMapInfo<llvm::Register, void>, llvm::detail::DenseMapPair<llvm::Register, std::vector<std::pair<llvm::SlotIndex, llvm::MachineInstr*... | void moveFromOldBuckets(BucketT *OldBucketsBegin, BucketT *OldBucketsEnd) {
initEmpty();
// Insert all the old elements.
const KeyT EmptyKey = getEmptyKey();
const KeyT TombstoneKey = getTombstoneKey();
for (BucketT *B = OldBucketsBegin, *E = OldBucketsEnd; B != E; ++B) {
if (!KeyInfoT::isEqu... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movq $0x0, 0x8(%rdi)
movl 0x10(%rdi), %ecx
testq %rcx, %rcx
je 0x12cd363
movq (%r15), %rax
movabsq $0x7ffffffffffffff, %rdx # imm = 0x7FFFFFFFFFFFFFF
addq %rdx, %rcx
andq %rcx, %rdx
andl $0x3, %ecx
negq %rcx
addq %rdx... | /llvm/ADT/DenseMap.h |
llvm::createWebAssemblyRegNumbering() | FunctionPass *llvm::createWebAssemblyRegNumbering() {
return new WebAssemblyRegNumbering();
} | pushq %rax
movl $0x38, %edi
callq 0x751940
xorl %ecx, %ecx
movq %rcx, 0x8(%rax)
leaq 0x45ec8f0(%rip), %rdx # 0x58bae74
movq %rdx, 0x10(%rax)
movl $0x2, 0x18(%rax)
xorps %xmm0, %xmm0
movups %xmm0, 0x20(%rax)
movq %rcx, 0x30(%rax)
leaq 0x449900f(%rip), %rcx # 0x57675b0
movq %rcx, (%rax)
popq %rcx
retq
| /Target/WebAssembly/WebAssemblyRegNumbering.cpp |
(anonymous namespace)::WebAssemblyRegNumbering::runOnMachineFunction(llvm::MachineFunction&) | bool WebAssemblyRegNumbering::runOnMachineFunction(MachineFunction &MF) {
LLVM_DEBUG(dbgs() << "********** Register Numbering **********\n"
"********** Function: "
<< MF.getName() << '\n');
WebAssemblyFunctionInfo &MFI = *MF.getInfo<WebAssemblyFunctionInfo>();
MachineRe... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %rsi, %r15
movq 0x28(%rsi), %rbx
movq 0x30(%rsi), %r14
movq %r14, %rdi
movq %rbx, %rsi
callq 0x129fc82
movq 0x148(%r15), %rax
movq 0x38(%rax), %rcx
addq $0x30, %rax
cmpq %rax, %rcx
je 0x12ce6a1
movzwl 0x44(%rcx), %edx
addl $0xfffffe87, %e... | /Target/WebAssembly/WebAssemblyRegNumbering.cpp |
llvm::WebAssemblyDebugValueManager::updateReg(llvm::Register) | void WebAssemblyDebugValueManager::updateReg(Register Reg) {
if (Reg != CurrentReg && Reg.isValid()) {
for (auto *DBI : DbgValues)
for (auto &MO : DBI->getDebugOperandsForReg(CurrentReg))
MO.setReg(Reg);
CurrentReg = Reg;
Def->getOperand(0).setReg(Reg);
}
} | testl %esi, %esi
je 0x12d346f
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xc8, %rsp
movl %esi, %ebx
movq %rdi, %r14
cmpl %esi, 0x20(%rdi)
je 0x12d345e
movl 0x10(%r14), %eax
testq %rax, %rax
je 0x12d344c
movq 0x8(%r14), %rbp
leaq (,%rax,8), %rax
addq %rbp, %rax
movq %rax, (%rsp)
leaq 0x18(%r... | /Target/WebAssembly/WebAssemblyDebugValueManager.cpp |
bool llvm::DenseMapBase<llvm::SmallDenseMap<llvm::DebugVariable, llvm::SmallVector<llvm::MachineInstr*, 2u>, 4u, llvm::DenseMapInfo<llvm::DebugVariable, void>, llvm::detail::DenseMapPair<llvm::DebugVariable, llvm::SmallVector<llvm::MachineInstr*, 2u>>>, llvm::DebugVariable, llvm::SmallVector<llvm::MachineInstr*, 2u>, l... | bool LookupBucketFor(const LookupKeyT &Val,
const BucketT *&FoundBucket) const {
const BucketT *BucketsPtr = getBuckets();
const unsigned NumBuckets = getNumBuckets();
if (NumBuckets == 0) {
FoundBucket = nullptr;
return false;
}
// FoundTombstone - Keep track of... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %rdx, %rbx
leaq 0x8(%rdi), %r13
testb $0x1, (%rdi)
cmoveq 0x8(%rdi), %r13
movl $0x4, %r15d
cmovel 0x10(%rdi), %r15d
testl %r15d, %r15d
je 0x12d3dfe
movq %rsi, %r14
movq %rsi, %rdi
callq 0xde9dea
movl %eax, %ebp
decl %r15d
movl %r15d... | /llvm/ADT/DenseMap.h |
llvm::WebAssemblyTargetLowering::isLegalAddressingMode(llvm::DataLayout const&, llvm::TargetLoweringBase::AddrMode const&, llvm::Type*, unsigned int, llvm::Instruction*) const | bool WebAssemblyTargetLowering::isLegalAddressingMode(const DataLayout &DL,
const AddrMode &AM,
Type *Ty, unsigned AS,
Instruction *I) const {
// WebAssembl... | cmpq $0x0, 0x8(%rdx)
setns %cl
cmpq $0x0, 0x18(%rdx)
sete %al
andb %cl, %al
retq
nop
| /Target/WebAssembly/WebAssemblyISelLowering.cpp |
llvm::WebAssemblyTargetLowering::getTgtMemIntrinsic(llvm::TargetLoweringBase::IntrinsicInfo&, llvm::CallInst const&, llvm::MachineFunction&, unsigned int) const | bool WebAssemblyTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
const CallInst &I,
MachineFunction &MF,
unsigned Intrinsic) const {
switch (Intrinsic) {
ca... | xorl %eax, %eax
leal -0x3085(%r8), %ecx
cmpl $0x4, %ecx
ja 0x12d73af
leaq 0x2b451db(%rip), %rdi # 0x3e1c55c
movslq (%rdi,%rcx,4), %rcx
addq %rdi, %rcx
jmpq *%rcx
movl $0x2f, (%rsi)
movb $0x7, 0x8(%rsi)
movq $0x0, 0x10(%rsi)
movl 0x4(%rdx), %eax
shll $0x5, %eax
subq %rax, %rdx
movss 0x2b450e3(%rip), %xmm0 # 0x3e1c490... | /Target/WebAssembly/WebAssemblyISelLowering.cpp |
llvm::WebAssemblyTargetLowering::LowerCopyToReg(llvm::SDValue, llvm::SelectionDAG&) const | SDValue WebAssemblyTargetLowering::LowerCopyToReg(SDValue Op,
SelectionDAG &DAG) const {
SDValue Src = Op.getOperand(2);
if (isa<FrameIndexSDNode>(Src.getNode())) {
// CopyToReg nodes don't support FrameIndex operands. Other targets select
// the FI to some ... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x88, %rsp
movq %rcx, %rbx
movq %rsi, %r15
movq 0x28(%rsi), %rax
movq 0x50(%rax), %r13
movq 0x58(%rax), %xmm0
movl 0x18(%r13), %ecx
cmpl $0x27, %ecx
je 0x12da0f6
cmpl $0xf, %ecx
jne 0x12da1d2
movq (%rax), %r14
movl 0x8(%rax), %ebp
movq 0x48(%r15), ... | /Target/WebAssembly/WebAssemblyISelLowering.cpp |
llvm::X86AsmPrinter::PrintMemReference(llvm::MachineInstr const*, unsigned int, llvm::raw_ostream&, char const*) | void X86AsmPrinter::PrintMemReference(const MachineInstr *MI, unsigned OpNo,
raw_ostream &O, const char *Modifier) {
assert(isMem(*MI, OpNo) && "Invalid memory reference!");
const MachineOperand &Segment = MI->getOperand(OpNo + X86::AddrSegmentReg);
if (Segment.getReg()) {
... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %r8, %rbx
movq %rcx, %r14
movl %edx, %r15d
movq %rsi, %r12
movq %rdi, %r13
leal 0x4(%r15), %edx
movq 0x20(%rsi), %rax
movq %rdx, %rcx
shlq $0x5, %rcx
cmpl $0x0, 0x4(%rax,%rcx)
je 0x12e5f59
movq %r13, %rdi
movq %r12, %rsi
movq %r14, %rcx
movq %rbx, %r8
callq 0x... | /Target/X86/X86AsmPrinter.cpp |
llvm::ShapeT::operator==(llvm::ShapeT const&) const | bool operator==(const ShapeT &Shape) const {
MachineOperand *R = Shape.Row;
MachineOperand *C = Shape.Col;
if (!R || !C)
return false;
if (!Row || !Col)
return false;
if (Row->getReg() == R->getReg() && Col->getReg() == C->getReg())
return true;
if ((RowImm != InvalidImmShape) ... | movq (%rsi), %rax
movq 0x8(%rsi), %rcx
testq %rax, %rax
sete %dl
testq %rcx, %rcx
sete %r8b
orb %dl, %r8b
movq (%rdi), %rdx
testq %rdx, %rdx
sete %r9b
orb %r8b, %r9b
jne 0x12f12e0
movq 0x8(%rdi), %r8
testq %r8, %r8
je 0x12f12e0
movl 0x4(%rdx), %edx
cmpl 0x4(%rax), %edx
jne 0x12f12bc
movl 0x4(%r8), %edx
movb $0x1, %al
c... | /llvm/CodeGen/TileShapeInfo.h |
llvm::X86TTIImpl::getMinMaxReductionCost(unsigned int, llvm::VectorType*, llvm::FastMathFlags, llvm::TargetTransformInfo::TargetCostKind) | InstructionCost
X86TTIImpl::getMinMaxReductionCost(Intrinsic::ID IID, VectorType *ValTy,
FastMathFlags FMF,
TTI::TargetCostKind CostKind) {
std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(ValTy);
MVT MTy = LT.second;
int ISD;
i... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xc8, %rsp
movl %r8d, %ebp
movl %ecx, 0x54(%rsp)
movq %rdx, %r12
movl %esi, %ebx
movq %rdi, %r14
leaq 0x68(%rsp), %rdi
movq %r14, %rsi
callq 0x12f65ec
movl $0xfe, %ecx
andl 0x8(%r12), %ecx
movq %r12, %rax
cmpl $0x12, %ecx
jne 0x1301b1f
movq 0x10(%r... | /Target/X86/X86TargetTransformInfo.cpp |
llvm::po_iterator<llvm::Function*, llvm::SmallPtrSet<llvm::BasicBlock*, 8u>, false, llvm::GraphTraits<llvm::Function*>>::traverseChild() | void traverseChild() {
while (true) {
auto &Entry = VisitStack.back();
if (std::get<1>(Entry) == std::get<2>(Entry))
break;
NodeRef BB = *std::get<1>(Entry)++;
if (this->insertEdge(std::optional<NodeRef>(std::get<0>(Entry)), BB)) {
// If the block is not visited...
Vi... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x38, %rsp
movq %rdi, %rbx
leaq 0x60(%rdi), %r14
leaq 0x20(%rsp), %r15
leaq 0x10(%rsp), %r13
movq 0x60(%rbx), %rax
movl 0x68(%rbx), %ecx
leaq (%rcx,%rcx,4), %rcx
movl -0x20(%rax,%rcx,8), %ebp
movl -0x10(%rax,%rcx,8), %r12d
cmpl %ebp, %r12d
je 0x130... | /llvm/ADT/PostOrderIterator.h |
(anonymous namespace)::X86CmovConverterPass::~X86CmovConverterPass() | X86CmovConverterPass() : MachineFunctionPass(ID) { } | pushq %rbx
movq %rdi, %rbx
leaq 0x445f02b(%rip), %rax # 0x576e998
movq %rax, (%rdi)
movq 0x118(%rdi), %rdi
leaq 0x128(%rbx), %rax
cmpq %rax, %rdi
je 0x130f988
callq 0x751980
movq %rbx, %rdi
callq 0x1a7c91e
movl $0x170, %esi # imm = 0x170
movq %rbx, %rdi
popq %rbx
jmp 0x7510e0
| /Target/X86/X86CmovConversion.cpp |
(anonymous namespace)::X86CmovConverterPass::collectCmovCandidates(llvm::ArrayRef<llvm::MachineBasicBlock*>, llvm::SmallVector<llvm::SmallVector<llvm::MachineInstr*, 2u>, 2u>&, bool) | bool X86CmovConverterPass::collectCmovCandidates(
ArrayRef<MachineBasicBlock *> Blocks, CmovGroups &CmovInstGroups,
bool IncludeLoads) {
//===--------------------------------------------------------------------===//
// Collect all CMOV-group-candidates and add them into CmovInstGroups.
//
// CMOV-group:... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x58, %rsp
movl %r8d, 0x24(%rsp)
movq %rcx, 0x18(%rsp)
movq %rsi, 0x10(%rsp)
movq %rdi, 0x48(%rsp)
leaq 0x38(%rsp), %rcx
movq %rcx, -0x10(%rcx)
movabsq $0x200000000, %rax # imm = 0x200000000
movq %rax, -0x8(%rcx)
testq %rdx, %rdx
je 0x1310a34
... | /Target/X86/X86CmovConversion.cpp |
void llvm::CodeGenPassBuilder<(anonymous namespace)::X86CodeGenPassBuilder, llvm::X86TargetMachine>::AddMachinePass::operator()<llvm::DeadMachineInstructionElimPass>(llvm::DeadMachineInstructionElimPass&&, bool, llvm::StringRef) | void operator()(PassT &&Pass, bool Force = false,
StringRef Name = PassT::name()) {
static_assert((is_detected<is_machine_function_pass_t, PassT>::value ||
is_detected<is_module_pass_t, PassT>::value) &&
"Only module pass and function pass are supported... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %rcx, %rbx
movq %rdx, %r14
movq %rsi, %r13
movq %rdi, %r12
movq 0x20(%rdi), %rdi
movq %rdx, %rsi
movq %rcx, %rdx
callq 0x1315ef0
testb %al, %al
je 0x1316106
leaq 0x8(%r12), %r15
movq %r15, %rdi
movq %r13, %rsi
callq 0xab8a32
movq 0x20(%r12), %rax
movl 0x130(%r... | /llvm/Passes/CodeGenPassBuilder.h |
llvm::cl::opt<bool, false, llvm::cl::parser<bool>>::opt<char [33], llvm::cl::initializer<bool>, llvm::cl::desc, llvm::cl::OptionHidden>(char const (&) [33], llvm::cl::initializer<bool> const&, llvm::cl::desc const&, llvm::cl::OptionHidden const&) | explicit opt(const Mods &... Ms)
: Option(llvm::cl::Optional, NotHidden), Parser(*this) {
apply(this, Ms...);
done();
} | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %r8, %rbx
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %r14
xorl %ebp, %ebp
xorl %esi, %esi
xorl %edx, %edx
callq 0x7c77e2
movb %bpl, 0x80(%r14)
xorps %xmm0, %xmm0
movups %xmm0, 0x88(%r14)
movb %bpl, 0x91(%r14)
leaq 0x43c97e... | /llvm/Support/CommandLine.h |
llvm::DenseMapBase<llvm::DenseMap<std::pair<llvm::StringRef, unsigned int>, llvm::DenseSet<unsigned int, llvm::DenseMapInfo<unsigned int, void>>, llvm::DenseMapInfo<std::pair<llvm::StringRef, unsigned int>, void>, llvm::detail::DenseMapPair<std::pair<llvm::StringRef, unsigned int>, llvm::DenseSet<unsigned int, llvm::De... | value_type& FindAndConstruct(const KeyT &Key) {
BucketT *TheBucket;
if (LookupBucketFor(Key, TheBucket))
return *TheBucket;
return *InsertIntoBucket(TheBucket, Key);
} | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rsi, %rbx
movq %rdi, %r14
leaq 0x8(%rsp), %r15
movq %r15, %rdx
callq 0x131a740
movl %eax, %ecx
movq (%r15), %rax
testb %cl, %cl
jne 0x131a735
movq %r14, %rdi
movq %rbx, %rsi
movq %rbx, %rdx
movq %rax, %rcx
callq 0x131a8b4
movups (%rbx), %xmm0
movups %xmm0, (%rax)
... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::X86ExpandPseudo::runOnMachineFunction(llvm::MachineFunction&) | bool X86ExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
STI = &MF.getSubtarget<X86Subtarget>();
TII = STI->getInstrInfo();
TRI = STI->getRegisterInfo();
X86FI = MF.getInfo<X86MachineFunctionInfo>();
X86FL = STI->getFrameLowering();
bool Modified = expandPseudosWhichAffectControlFlow(MF);
for (... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x1a8, %rsp # imm = 0x1A8
movq %rdi, %r14
movq 0x10(%rsi), %rdi
movq %rdi, 0x38(%r14)
leaq 0x260(%rdi), %rax
movq %rax, 0x40(%r14)
leaq 0x2b8(%rdi), %rdx
movq %rdx, 0x48(%r14)
movq 0x30(%rsi), %rcx
movq %rcx, 0x50(%r14)
movq %rdi, 0x48(%... | /Target/X86/X86ExpandPseudo.cpp |
llvm::DenseMap<llvm::MachineBasicBlock*, long, llvm::DenseMapInfo<llvm::MachineBasicBlock*, void>, llvm::detail::DenseMapPair<llvm::MachineBasicBlock*, long>>::grow(unsigned int) | void grow(unsigned AtLeast) {
unsigned OldNumBuckets = NumBuckets;
BucketT *OldBuckets = Buckets;
allocateBuckets(std::max<unsigned>(64, static_cast<unsigned>(NextPowerOf2(AtLeast-1))));
assert(Buckets);
if (!OldBuckets) {
this->BaseT::initEmpty();
return;
}
this->moveFromOldBu... | pushq %r15
pushq %r14
pushq %rbx
movq %rdi, %r15
movl 0x10(%rdi), %ebx
movq (%rdi), %r14
leal -0x1(%rsi), %eax
movl %eax, %ecx
shrl %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x2, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x4, %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x8, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x10,... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::MachineBasicBlock*, long, llvm::DenseMapInfo<llvm::MachineBasicBlock*, void>, llvm::detail::DenseMapPair<llvm::MachineBasicBlock*, long>>, llvm::MachineBasicBlock*, long, llvm::DenseMapInfo<llvm::MachineBasicBlock*, void>, llvm::detail::DenseMapPair<llvm::MachineBasicBlock*, long... | void moveFromOldBuckets(BucketT *OldBucketsBegin, BucketT *OldBucketsEnd) {
initEmpty();
// Insert all the old elements.
const KeyT EmptyKey = getEmptyKey();
const KeyT TombstoneKey = getTombstoneKey();
for (BucketT *B = OldBucketsBegin, *E = OldBucketsEnd; B != E; ++B) {
if (!KeyInfoT::isEqu... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x10, %rsp
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movq $0x0, 0x8(%rdi)
movl 0x10(%rdi), %ecx
testq %rcx, %rcx
je 0x13414a7
movq (%r15), %rax
movabsq $0xfffffffffffffff, %rdx # imm = 0xFFFFFFFFFFFFFFF
addq %rdx, %rcx
andq %rcx, %rdx
andl $0x1, %ecx
ne... | /llvm/ADT/DenseMap.h |
llvm::Pass* llvm::callDefaultCtor<(anonymous namespace)::X86FixupSetCCPass, true>() | Pass *callDefaultCtor() {
return new PassName();
} | pushq %rax
movl $0x50, %edi
callq 0x751940
xorl %ecx, %ecx
movq %rcx, 0x8(%rax)
leaq 0x457a68a(%rip), %rdx # 0x58bbccc
movq %rdx, 0x10(%rax)
movl $0x2, 0x18(%rax)
xorps %xmm0, %xmm0
movups %xmm0, 0x20(%rax)
movq %rcx, 0x30(%rax)
leaq 0x442e111(%rip), %rdx # 0x576f770
movq %rdx, (%rax)
movups %xmm0, 0x38(%rax)
movq ... | /llvm/PassSupport.h |
llvm::df_iterator<llvm::MachineBasicBlock*, llvm::df_iterator_default_set<llvm::MachineBasicBlock*, 8u>, true, llvm::GraphTraits<llvm::MachineBasicBlock*>>::begin(llvm::MachineBasicBlock* const&, llvm::df_iterator_default_set<llvm::MachineBasicBlock*, 8u>&) | static df_iterator begin(const GraphT &G, SetType &S) {
return df_iterator(GT::getEntryNode(G), S);
} | pushq %r15
pushq %r14
pushq %rbx
subq $0x20, %rsp
movq %rdi, %rbx
movq (%rsi), %r14
movq %rdx, (%rdi)
xorps %xmm0, %xmm0
movups %xmm0, 0x8(%rdi)
movq $0x0, 0x18(%rdi)
leaq 0x8(%rsp), %r15
movq %r15, %rdi
movq %rdx, %rsi
movq %r14, %rdx
callq 0x972ebc
cmpb $0x1, 0x10(%r15)
jne 0x13468ba
movq %r14, 0x8(%rsp)
movb $0x0, 0... | /llvm/ADT/DepthFirstIterator.h |
flagsNeedToBePreservedBeforeTheTerminators(llvm::MachineBasicBlock const&) | static bool
flagsNeedToBePreservedBeforeTheTerminators(const MachineBasicBlock &MBB) {
for (const MachineInstr &MI : MBB.terminators()) {
bool BreakNext = false;
for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg())
continue;
Register Reg = MO.getReg();
if (Reg != X86::EF... | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
movq %rdi, %r14
callq 0x174ff92
leaq 0x30(%r14), %rcx
cmpq %rcx, %rax
sete %sil
je 0x134878c
movl $0x1, %edx
movzwl 0x28(%rax), %edi
movzbl 0x2a(%rax), %r9d
shll $0x10, %r9d
orq %rdi, %r9
movl $0x4, %edi
testq %r9, %r9
je 0x1348734
movq 0x20(%rax), %r10
shll $0x5, ... | /Target/X86/X86FrameLowering.cpp |
llvm::X86FrameLowering::enableShrinkWrapping(llvm::MachineFunction const&) const | bool X86FrameLowering::enableShrinkWrapping(const MachineFunction &MF) const {
// If we may need to emit frameless compact unwind information, give
// up as this is currently broken: PR25614.
bool CompactUnwind =
MF.getContext().getObjectFileInfo()->getCompactUnwindSection() != nullptr;
return (MF.getFunc... | pushq %r15
pushq %r14
pushq %rbx
movq %rsi, %rbx
movq %rdi, %r14
movq (%rsi), %rdi
movq 0x18(%rsi), %rax
movq 0xa8(%rax), %rax
movq 0x40(%rax), %r15
movl $0x27, %esi
callq 0x1a2e4ec
testb %al, %al
je 0x135a3f8
movq (%rbx), %rax
movzwl 0x2(%rax), %eax
andl $0x3ff0, %eax # imm = 0x3FF0
cmpl $0xb0, %eax
je 0x135... | /Target/X86/X86FrameLowering.cpp |
llvm::X86MachineFunctionInfo::getPreallocatedIdForCallSite(llvm::Value const*) | size_t getPreallocatedIdForCallSite(const Value *CS) {
auto Insert = PreallocatedIds.insert({CS, PreallocatedIds.size()});
if (Insert.second) {
PreallocatedStackSizes.push_back(0);
PreallocatedArgOffsets.emplace_back();
}
return Insert.first->second;
} | pushq %r14
pushq %rbx
subq $0x28, %rsp
movq %rdi, %rbx
leaq 0xb8(%rdi), %rax
movl 0xc0(%rdi), %edx
leaq 0x8(%rsp), %rcx
movq %rsi, -0x8(%rcx)
movq %rdx, (%rcx)
leaq 0x10(%rsp), %r14
movq %rsp, %rdx
movq %r14, %rdi
movq %rax, %rsi
callq 0x1371248
cmpb $0x1, 0x10(%r14)
jne 0x136f16c
leaq 0xd0(%rbx), %rdi
xorl %esi, %esi
... | /Target/X86/X86MachineFunctionInfo.h |
(anonymous namespace)::X86DAGToDAGISel::matchVectorAddressRecursively(llvm::SDValue, (anonymous namespace)::X86ISelAddressMode&, unsigned int) | bool X86DAGToDAGISel::matchVectorAddressRecursively(SDValue N,
X86ISelAddressMode &AM,
unsigned Depth) {
SDLoc dl(N);
LLVM_DEBUG({
dbgs() << "MatchVectorAddress: ";
AM.dump(CurDAG);
});
// Limit recur... | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x110, %rsp # imm = 0x110
movl %r8d, %r12d
movq %rcx, %rbx
movl %edx, %ebp
movq %rsi, %r14
movq %rdi, %r15
movq 0x48(%rsi), %rsi
movq %rsi, 0x8(%rsp)
testq %rsi, %rsi
je 0x1370db6
leaq 0x8(%rsp), %rdi
movl $0x1, %edx
callq 0x1a648a8
movl 0x44(%r14)... | /Target/X86/X86ISelDAGToDAG.cpp |
llvm::SmallVector<unsigned long, 4u>& llvm::SmallVectorTemplateBase<llvm::SmallVector<unsigned long, 4u>, false>::growAndEmplaceBack<>() | T &growAndEmplaceBack(ArgTypes &&... Args) {
// Grow manually in case one of Args is an internal reference.
size_t NewCapacity;
T *NewElts = mallocForGrow(0, NewCapacity);
::new ((void *)(NewElts + this->size())) T(std::forward<ArgTypes>(Args)...);
moveElementsForGrow(NewElts);
takeAllocationFor... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rdi, %rbx
leaq 0x10(%rdi), %r15
movq %rsp, %r12
movl $0x30, %ecx
movq %r15, %rsi
xorl %edx, %edx
movq %r12, %r8
callq 0x1cba3de
movq %rax, %r14
movl 0x8(%rbx), %eax
leaq (%rax,%rax,2), %rax
shlq $0x4, %rax
addq %r14, %rax
addq $0x10, %rax
movq %rax, -0x10(%ra... | /llvm/ADT/SmallVector.h |
foldMaskedShiftToBEXTR(llvm::SelectionDAG&, llvm::SDValue, unsigned long, llvm::SDValue, llvm::SDValue, (anonymous namespace)::X86ISelAddressMode&, llvm::X86Subtarget const&) | static bool foldMaskedShiftToBEXTR(SelectionDAG &DAG, SDValue N,
uint64_t Mask,
SDValue Shift, SDValue X,
X86ISelAddressMode &AM,
const X86Subtarget &Subtarget) {
if (Shift.getOp... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xb8, %rsp
movb $0x1, %r13b
cmpl $0xbf, 0x18(%r8)
jne 0x13739c1
movq %r8, %r15
movq %rcx, %r12
movl %edx, %ebp
movq %rsi, %rbx
movq %rdi, %r14
movq 0x28(%r8), %rax
movq 0x28(%rax), %rax
movl 0x18(%rax), %eax
cmpl $0x23, %eax
je 0x1373657
cmpl $0xb,... | /Target/X86/X86ISelDAGToDAG.cpp |
llvm::X86TargetLowering::LowerJumpTable(llvm::SDValue, llvm::SelectionDAG&) const | SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
// In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
// global base reg.
unsigned char OpFlag = Subtarget.classifyLocalReference(nullptr);
auto PtrVT = getPoi... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x88, %rsp
movq %rcx, %rbx
movq %rsi, %r12
movq %rdi, %r15
movq 0x4e0f8(%rdi), %rdi
xorl %esi, %esi
callq 0x14c114e
movl %eax, %r14d
movq 0x28(%rbx), %rdi
callq 0x1789320
movq %rax, %rdi
xorl %esi, %esi
callq 0x19e9984
movl 0x4(%rax), %edi
callq 0x... | /Target/X86/X86ISelLowering.cpp |
llvm::X86TargetLowering::LowerDYNAMIC_STACKALLOC(llvm::SDValue, llvm::SelectionDAG&) const | SDValue
X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
SelectionDAG &DAG) const {
MachineFunction &MF = DAG.getMachineFunction();
bool SplitStack = MF.shouldSplitStack();
bool EmitStackProbeCall = hasStackProbeSymbol(MF);
bool Lower = (Subtarget.isOSWindows() &... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x198, %rsp # imm = 0x198
movq %rcx, %rbx
movq %rsi, %r15
movq %rdi, %r12
movq 0x28(%rcx), %r13
movq %r13, %rdi
callq 0x17898b8
movl %eax, %r14d
movq %r12, %rdi
movq %r13, %rsi
callq 0x141ae88
movq 0x4e0f8(%r12), %rax
cmpl $0xe, 0x21c(%r... | /Target/X86/X86ISelLowering.cpp |
llvm::X86TargetLowering::LowerGC_TRANSITION(llvm::SDValue, llvm::SelectionDAG&) const | SDValue X86TargetLowering::LowerGC_TRANSITION(SDValue Op,
SelectionDAG &DAG) const {
// TODO: Eventually, the lowering of these nodes should be informed by or
// deferred to the GC strategy for the function in which they appear. For
// now, however, they must be lower... | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x60, %rsp
movq %rcx, %rbx
movq %rsi, %r14
leaq 0x40(%rsp), %r12
movq %r12, -0x10(%r12)
movabsq $0x200000000, %rax # imm = 0x200000000
movq %rax, -0x8(%r12)
movq 0x28(%rsi), %rax
movq (%rax), %rsi
movl 0x8(%rax), %edx
leaq 0x30(%rsp), %rdi
callq 0x9b3dce... | /Target/X86/X86ISelLowering.cpp |
LowerMGATHER(llvm::SDValue, llvm::X86Subtarget const&, llvm::SelectionDAG&) | static SDValue LowerMGATHER(SDValue Op, const X86Subtarget &Subtarget,
SelectionDAG &DAG) {
assert(Subtarget.hasAVX2() &&
"MGATHER/MSCATTER are supported on AVX-512/AVX-2 arch only");
MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
SDLoc dl(Op);
MVT VT = Op.... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x138, %rsp # imm = 0x138
movq %rcx, %rbx
movq %rdx, %r8
movl %esi, %r14d
movq %rdi, %r15
movq 0x48(%rdi), %rsi
movq %rsi, 0x48(%rsp)
testq %rsi, %rsi
je 0x13c719b
leaq 0x48(%rsp), %rdi
movl $0x1, %edx
movq %r8, %r12
callq 0x1a648a8
movq... | /Target/X86/X86ISelLowering.cpp |
llvm::X86TargetLowering::isFMAFasterThanFMulAndFAdd(llvm::MachineFunction const&, llvm::EVT) const | bool X86TargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
EVT VT) const {
if (!Subtarget.hasAnyFMA())
return false;
VT = VT.getScalarType();
if (!VT.isSimple())
return false;
switch (VT.getSimpleVT().SimpleTy) {
case MVT::f16:
... | pushq %r14
pushq %rbx
subq $0x18, %rsp
movq %rdi, %rbx
movb %dl, 0x8(%rsp)
movq %rcx, 0x10(%rsp)
movq 0x4e0f8(%rdi), %rax
cmpb $0x0, 0x161(%rax)
jne 0x13cfc74
testb $0x1, 0x162(%rax)
jne 0x13cfc74
xorl %eax, %eax
jmp 0x13cfca9
leaq 0x8(%rsp), %r14
movq %r14, %rdi
callq 0x903280
movb %al, (%r14)
movq %rdx, 0x8(%r14)
mov... | /Target/X86/X86ISelLowering.cpp |
combineExtractVectorElt(llvm::SDNode*, llvm::SelectionDAG&, llvm::TargetLowering::DAGCombinerInfo&, llvm::X86Subtarget const&) | static SDValue combineExtractVectorElt(SDNode *N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI,
const X86Subtarget &Subtarget) {
if (SDValue NewOp = combineExtractWithShuffle(N, DAG, DCI, Subtarget))
return NewOp;
SDValue ... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x468, %rsp # imm = 0x468
movq %rcx, 0x50(%rsp)
movq %rdx, %rbx
cmpl $0x2, 0x8(%rdx)
movq %rsi, 0x60(%rsp)
movq %rdi, 0x88(%rsp)
jge 0x13ee8aa
movq %rsi, %r13
xorl %r12d, %r12d
xorl %r15d, %r15d
jmp 0x13ef371
movq %rdi, %r12
movq 0x48(%r... | /Target/X86/X86ISelLowering.cpp |
combineSBB(llvm::SDNode*, llvm::SelectionDAG&) | static SDValue combineSBB(SDNode *N, SelectionDAG &DAG) {
SDValue LHS = N->getOperand(0);
SDValue RHS = N->getOperand(1);
SDValue BorrowIn = N->getOperand(2);
if (SDValue Flags = combineCarryThroughADD(BorrowIn, DAG)) {
MVT VT = N->getSimpleValueType(0);
SDVTList VTs = DAG.getVTList(VT, MVT::i32);
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xd8, %rsp
movq %rsi, %rbx
movq %rdi, %r14
movq 0x28(%rdi), %rax
movq (%rax), %r13
movq 0x8(%rax), %rcx
movq %rcx, 0x68(%rsp)
movq 0x28(%rax), %rcx
movq %rcx, 0x48(%rsp)
movsd 0x30(%rax), %xmm0
movaps %xmm0, 0x70(%rsp)
movq 0x50(%rax), %r12
movq 0x... | /Target/X86/X86ISelLowering.cpp |
combineVectorPack(llvm::SDNode*, llvm::SelectionDAG&, llvm::TargetLowering::DAGCombinerInfo&, llvm::X86Subtarget const&) | static SDValue combineVectorPack(SDNode *N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI,
const X86Subtarget &Subtarget) {
unsigned Opcode = N->getOpcode();
assert((X86ISD::PACKSS == Opcode || X86ISD::PACKUS == Opcode) &&
"Unexpec... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x768, %rsp # imm = 0x768
movq %rdx, 0x80(%rsp)
movq %rsi, %r12
movq %rdi, %r13
movl 0x18(%rdi), %eax
movl %eax, 0x68(%rsp)
movq 0x30(%rdi), %rax
movb (%rax), %cl
movq 0x8(%rax), %rax
leaq 0x70(%rsp), %rbx
movb %cl, (%rbx)
movq %rax, 0x8... | /Target/X86/X86ISelLowering.cpp |
getScalarValueForVectorElement(llvm::SDValue, int, llvm::SelectionDAG&) | static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
SelectionDAG &DAG) {
MVT VT = V.getSimpleValueType();
MVT EltVT = VT.getVectorElementType();
V = peekThroughBitcasts(V);
// If the bitcasts shift the element size, we can't extract an equivalent
//... | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
movq %rcx, %rbx
movl %edx, %ebp
movq 0x30(%rdi), %rax
movl %esi, %ecx
shlq $0x4, %rcx
movzbl (%rax,%rcx), %r15d
leaq 0x1d5fa91(%rip), %r12 # 0x318db40
movzbl -0x1(%r15,%r12), %r14d
callq 0x1f47abf
movq 0x30(%rax), %rcx
movl %edx, %edx
shlq $0x4, %rdx
movzbl (%rcx... | /Target/X86/X86ISelLowering.cpp |
isRepeatedShuffleMask(unsigned int, llvm::MVT, llvm::ArrayRef<int>, llvm::SmallVectorImpl<int>&) | static bool isRepeatedShuffleMask(unsigned LaneSizeInBits, MVT VT,
ArrayRef<int> Mask,
SmallVectorImpl<int> &RepeatedMask) {
auto LaneSize = LaneSizeInBits / VT.getScalarSizeInBits();
RepeatedMask.assign(LaneSize, -1);
int Size = Mask.size();
f... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %r8, %r12
movq %rcx, %rbx
movq %rdx, %r14
movl %edi, %eax
leal -0x11(%rsi), %ecx
cmpb $-0x54, %cl
ja 0x142ef4f
movzbl %sil, %ecx
leaq 0x1d5ebf6(%rip), %rdx # 0x318db40
movb -0x1(%rcx,%rdx), %sil
movzbl %sil, %ecx
shll $0x4, %ecx
leaq 0x1d5dee3(%rip), %rsi ... | /Target/X86/X86ISelLowering.cpp |
isShuffleEquivalent(llvm::ArrayRef<int>, llvm::ArrayRef<int>, llvm::SDValue, llvm::SDValue) | static bool isShuffleEquivalent(ArrayRef<int> Mask, ArrayRef<int> ExpectedMask,
SDValue V1 = SDValue(),
SDValue V2 = SDValue()) {
int Size = Mask.size();
if (Size != (int)ExpectedMask.size())
return false;
for (int i = 0; i < Size; ++i) {
as... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x38, %rsp
movl %r9d, 0x14(%rsp)
movq %r8, 0x30(%rsp)
movq %rsi, %r12
cmpl %ecx, %r12d
jne 0x142f0fe
testl %r12d, %r12d
setle %bpl
jle 0x142f100
movq %rdi, %r13
leaq 0x70(%rsp), %rax
movq (%rax), %rcx
movq %rcx, 0x28(%rsp)
movl 0x8(%rax), %eax
movl... | /Target/X86/X86ISelLowering.cpp |
llvm::SmallVectorTemplateBase<llvm::SmallVector<int, 8u>, false>::growAndAssign(unsigned long, llvm::SmallVector<int, 8u> const&) | void growAndAssign(size_t NumElts, const T &Elt) {
// Grow manually in case Elt is an internal reference.
size_t NewCapacity;
T *NewElts = mallocForGrow(NumElts, NewCapacity);
std::uninitialized_fill_n(NewElts, NumElts, Elt);
this->destroy_range(this->begin(), this->end());
takeAllocationForGrow... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %rdx, %r13
movq %rsi, %rbx
movq %rdi, %r14
leaq 0x10(%rdi), %rsi
leaq 0x10(%rsp), %r8
movl $0x30, %ecx
movq %rsi, 0x8(%rsp)
movq %rbx, %rdx
callq 0x1cba3de
movq %rax, %r12
movq %rax, %rdi
movq %rbx, %rsi
movq %r13, %rdx
callq 0x143e... | /llvm/ADT/SmallVector.h |
llvm::SmallBitVector::count() const | bool isSmall() const { return X & uintptr_t(1); } | movq (%rdi), %rcx
testb $0x1, %cl
jne 0x143f639
movl 0x8(%rcx), %edx
xorl %eax, %eax
testq %rdx, %rdx
je 0x143f638
pushq %rbx
movq (%rcx), %rcx
shlq $0x3, %rdx
movabsq $0x5555555555555555, %rsi # imm = 0x5555555555555555
movabsq $0x3333333333333333, %rdi # imm = 0x3333333333333333
movabsq $0xf0f0f0f0f0f0f0f, %r8 # imm ... | /llvm/ADT/SmallBitVector.h |
LowerSIGN_EXTEND_Mask(llvm::SDValue, llvm::SDLoc const&, llvm::X86Subtarget const&, llvm::SelectionDAG&) | static SDValue LowerSIGN_EXTEND_Mask(SDValue Op, const SDLoc &dl,
const X86Subtarget &Subtarget,
SelectionDAG &DAG) {
MVT VT = Op->getSimpleValueType(0);
SDValue In = Op->getOperand(0);
MVT InVT = In.getSimpleValueType();
assert(InVT.getV... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x128, %rsp # imm = 0x128
movq %rcx, %rbx
movq %rdx, %r13
movq %rsi, %r12
movq 0x28(%rdi), %rax
movq %rdi, 0x50(%rsp)
movq 0x30(%rdi), %rcx
movb (%rcx), %bpl
movq (%rax), %rcx
movq %rcx, 0x40(%rsp)
movl 0x8(%rax), %ecx
movl %ecx, 0x3c(%r... | /Target/X86/X86ISelLowering.cpp |
combineToExtendBoolVectorInReg(unsigned int, llvm::SDLoc const&, llvm::EVT, llvm::SDValue, llvm::SelectionDAG&, llvm::TargetLowering::DAGCombinerInfo&, llvm::X86Subtarget const&) | static SDValue combineToExtendBoolVectorInReg(
unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N0, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget) {
if (Opcode != ISD::SIGN_EXTEND && Opcode != ISD::ZERO_EXTEND &&
Opcode != ISD::ANY_EXTEND)
return SDValue();
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x3e8, %rsp # imm = 0x3E8
movl %edi, %r14d
movb %dl, 0x40(%rsp)
movq %rcx, 0x48(%rsp)
leal -0xd4(%r14), %eax
xorl %r13d, %r13d
movl $0x0, %ebp
cmpl $0x2, %eax
ja 0x145c541
movq 0x428(%rsp), %rax
cmpl $0x1, 0x8(%rax)
jg 0x145c541
movq %rs... | /Target/X86/X86ISelLowering.cpp |
combineVSelectToBLENDV(llvm::SDNode*, llvm::SelectionDAG&, llvm::SDLoc const&, llvm::TargetLowering::DAGCombinerInfo&, llvm::X86Subtarget const&) | static SDValue combineVSelectToBLENDV(SDNode *N, SelectionDAG &DAG,
const SDLoc &DL,
TargetLowering::DAGCombinerInfo &DCI,
const X86Subtarget &Subtarget) {
SDValue Cond = N->getOperand(0);
if ((N->getOp... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xf8, %rsp
movq %r8, %r15
movq %rcx, %r12
movq %rdx, %r13
movq %rsi, %rbx
movq %rdi, %r14
movq 0x28(%rdi), %rax
movups (%rax), %xmm0
movaps %xmm0, 0x50(%rsp)
movl 0x18(%rdi), %eax
cmpl $0x214, %eax # imm = 0x214
je 0x145d03f
cmpl $0xcd, ... | /Target/X86/X86ISelLowering.cpp |
needCarryOrOverflowFlag(llvm::SDValue) | static bool needCarryOrOverflowFlag(SDValue Flags) {
assert(Flags.getValueType() == MVT::i32 && "Unexpected VT!");
for (const SDNode *User : Flags->uses()) {
X86::CondCode CC;
switch (User->getOpcode()) {
default:
// Be conservative.
return true;
case X86ISD::SETCC:
case X86ISD::SET... | movq 0x38(%rdi), %rcx
testq %rcx, %rcx
setne %al
je 0x1462571
movl $0xf0cf, %edx # imm = 0xF0CF
movq 0x10(%rcx), %rsi
movl 0x18(%rsi), %edi
leal -0x1fc(%rdi), %r8d
cmpl $0x2, %r8d
jb 0x146253a
cmpl $0x1f8, %edi # imm = 0x1F8
je 0x1462534
cmpl $0x1f6, %edi # imm = 0x1F6
jne 0x1462571
movq... | /Target/X86/X86ISelLowering.cpp |
llvm::SDValue SplitOpsAndApply<matchPMADDWD_2(llvm::SelectionDAG&, llvm::SDValue, llvm::SDValue, llvm::SDLoc const&, llvm::EVT, llvm::X86Subtarget const&)::$_0>(llvm::SelectionDAG&, llvm::X86Subtarget const&, llvm::SDLoc const&, llvm::EVT, llvm::ArrayRef<llvm::SDValue>, matchPMADDWD_2(llvm::SelectionDAG&, llvm::SDValue... | SDValue SplitOpsAndApply(SelectionDAG &DAG, const X86Subtarget &Subtarget,
const SDLoc &DL, EVT VT, ArrayRef<SDValue> Ops,
F Builder, bool CheckBWI = true) {
assert(Subtarget.hasSSE2() && "Target assumed to support at least SSE2");
unsigned NumSubs = 1;
if ((Check... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x108, %rsp # imm = 0x108
movq %rdx, 0x40(%rsp)
movq %rdi, 0x38(%rsp)
movb %cl, 0x28(%rsp)
movq %r8, 0x30(%rsp)
movl 0x130(%rsi), %eax
cmpl $0x9, %eax
setge %dl
andb 0x14c(%rsi), %dl
cmpb $0x1, %dl
jne 0x14637bb
cmpb $0x1, 0x15f(%rsi)
jn... | /Target/X86/X86ISelLowering.cpp |
llvm::SDValue SplitOpsAndApply<combineMulToPMADDWD(llvm::SDNode*, llvm::SDLoc const&, llvm::SelectionDAG&, llvm::X86Subtarget const&)::$_0>(llvm::SelectionDAG&, llvm::X86Subtarget const&, llvm::SDLoc const&, llvm::EVT, llvm::ArrayRef<llvm::SDValue>, combineMulToPMADDWD(llvm::SDNode*, llvm::SDLoc const&, llvm::Selection... | SDValue SplitOpsAndApply(SelectionDAG &DAG, const X86Subtarget &Subtarget,
const SDLoc &DL, EVT VT, ArrayRef<SDValue> Ops,
F Builder, bool CheckBWI = true) {
assert(Subtarget.hasSSE2() && "Target assumed to support at least SSE2");
unsigned NumSubs = 1;
if ((Check... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x108, %rsp # imm = 0x108
movq %rdx, 0x48(%rsp)
movq %rdi, 0x40(%rsp)
movb %cl, 0x20(%rsp)
movq %r8, 0x28(%rsp)
movl 0x130(%rsi), %eax
cmpl $0x9, %eax
setge %dl
andb 0x14c(%rsi), %dl
cmpb $0x1, %dl
jne 0x1466970
cmpb $0x1, 0x15f(%rsi)
jn... | /Target/X86/X86ISelLowering.cpp |
bool llvm::SDPatternMatch::BinaryOpc_match<llvm::SDPatternMatch::Value_bind, llvm::SDPatternMatch::SpecificInt_match, true, false>::match<llvm::SDPatternMatch::BasicMatchContext>(llvm::SDPatternMatch::BasicMatchContext const&, llvm::SDValue) | inline UnaryOpc_match<Opnd> m_UnaryOp(unsigned Opc, const Opnd &Op) {
return UnaryOpc_match<Opnd>(Opc, Op);
} | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movl 0x18(%rdx), %eax
cmpl (%rdi), %eax
jne 0x1467b66
movq %rdx, %r14
movq %rsi, %rbx
movq %rdi, %r15
movq 0x28(%rdx), %rax
movq (%rax), %rcx
movl 0x8(%rax), %eax
movq 0x8(%rdi), %rdx
movq %rcx, (%rdx)
movl %eax, 0x8(%rdx)
leaq 0x10(%rdi), %r12
movq 0x28(%r14), %ra... | /llvm/CodeGen/SDPatternMatch.h |
combineAndShuffleNot(llvm::SDNode*, llvm::SelectionDAG&, llvm::X86Subtarget const&) | static SDValue combineAndShuffleNot(SDNode *N, SelectionDAG &DAG,
const X86Subtarget &Subtarget) {
assert(N->getOpcode() == ISD::AND && "Unexpected opcode combine into ANDNP");
EVT VT = N->getValueType(0);
// Do not split 256 and 512 bit vectors with SSE2 as they overwrite ori... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xc8, %rsp
movq %rdx, %r14
movq %rsi, %rbx
movq %rdi, %r15
movq 0x30(%rdi), %rax
movb (%rax), %cl
movq 0x8(%rax), %rax
leaq 0x18(%rsp), %rdi
movb %cl, (%rdi)
movq %rax, 0x8(%rdi)
callq 0x9b1c42
testb %al, %al
je 0x1468e03
cmpl $0x1, 0x130(%r14)
jle... | /Target/X86/X86ISelLowering.cpp |
getIndexFromUnindexedLoad(llvm::LoadSDNode*) | ISD::MemIndexedMode getAddressingMode() const {
return static_cast<ISD::MemIndexedMode>(LSBaseSDNodeBits.AddressingMode);
} | movzwl 0x1e(%rdi), %eax
testl $0x380, %eax # imm = 0x380
jne 0x146a975
movq 0x28(%rdi), %rax
movq 0x28(%rax), %rax
cmpl $0x38, 0x18(%rax)
jne 0x146a975
movq 0x28(%rax), %rax
movq (%rax), %rax
cmpl $0xbd, 0x18(%rax)
jne 0x146a975
movq 0x28(%rax), %rcx
movq (%rcx), %rax
movl 0x8(%rcx), %edx
retq
xorl %edx, %ed... | /llvm/CodeGen/SelectionDAGNodes.h |
llvm::X86TargetLowering::getByValTypeAlignment(llvm::Type*, llvm::DataLayout const&) const | uint64_t X86TargetLowering::getByValTypeAlignment(Type *Ty,
const DataLayout &DL) const {
if (Subtarget.is64Bit()) {
// Max of 8 and alignment of type.
Align TyAlign = DL.getABITypeAlign(Ty);
if (TyAlign > 8)
return TyAlign.value();
return 8;
}... | pushq %rax
movq 0x4e0f8(%rdi), %rax
cmpb $0x1, 0x1c5(%rax)
jne 0x1479bc4
movq %rdx, %rdi
callq 0x19e803a
movl $0x1, %edx
movl %eax, %ecx
shlq %cl, %rdx
cmpb $0x4, %al
movl $0x8, %eax
cmovaeq %rdx, %rax
jmp 0x1479bee
movb $0x2, 0x7(%rsp)
cmpl $0x0, 0x130(%rax)
jle 0x1479be2
leaq 0x7(%rsp), %rax
movq %rsi, %rdi
movq %rax... | /Target/X86/X86ISelLoweringCall.cpp |
lowerMasksToReg(llvm::SDValue const&, llvm::EVT const&, llvm::SDLoc const&, llvm::SelectionDAG&) | static SDValue lowerMasksToReg(const SDValue &ValArg, const EVT &ValLoc,
const SDLoc &DL, SelectionDAG &DAG) {
EVT ValVT = ValArg.getValueType();
if (ValVT == MVT::v1i1)
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ValLoc, ValArg,
DAG.getIntPtrConstant(0... | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x50, %rsp
movq %rcx, %r14
movq %rdx, %rbx
movq %rsi, %r15
movq (%rdi), %rcx
movl 0x8(%rdi), %r8d
movq 0x30(%rcx), %rax
movq %r8, %rdx
shlq $0x4, %rdx
movzbl (%rax,%rdx), %eax
cmpl $0x11, %eax
jne 0x147b5d3
movq 0x8(%r15), %r12
movups (%rdi), %xmm0
movl (%r15... | /Target/X86/X86ISelLoweringCall.cpp |
getv64i1Argument(llvm::CCValAssign&, llvm::CCValAssign&, llvm::SDValue&, llvm::SelectionDAG&, llvm::SDLoc const&, llvm::X86Subtarget const&, llvm::SDValue*) | static SDValue getv64i1Argument(CCValAssign &VA, CCValAssign &NextVA,
SDValue &Root, SelectionDAG &DAG,
const SDLoc &DL, const X86Subtarget &Subtarget,
SDValue *InGlue = nullptr) {
assert((Subtarget.hasBWI()) && "Expected ... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x88, %rsp
movq %r8, %rbx
movq %rcx, %r14
movq %rdx, %r12
movq %rsi, %r13
movb 0x8(%rdi), %al
testq %r9, %r9
je 0x147c04e
testb %al, %al
jne 0x147c175
movq %r9, %rbp
movl 0x8(%r12), %edx
movq (%r12), %rsi
movl (%rdi), %r8d
movb $0x7, 0x58(%rsp)
mov... | /Target/X86/X86ISelLoweringCall.cpp |
mayTailCallThisCC(unsigned int) | static bool mayTailCallThisCC(CallingConv::ID CC) {
switch (CC) {
// C calling conventions:
case CallingConv::C:
case CallingConv::Win64:
case CallingConv::X86_64_SysV:
case CallingConv::PreserveNone:
// Callee pop conventions:
case CallingConv::X86_ThisCall:
case CallingConv::X86_StdCall:
case Call... | leal -0x40(%rdi), %eax
cmpl $0x10, %eax
ja 0x147c263
movl $0x1c043, %ecx # imm = 0x1C043
btl %eax, %ecx
jb 0x147c272
cmpl $0x15, %edi
ja 0x147c275
movl $0x210001, %eax # imm = 0x210001
btl %edi, %eax
jae 0x147c275
movb $0x1, %al
retq
jmp 0x147e647
| /Target/X86/X86ISelLoweringCall.cpp |
llvm::X86::isCalleePop(unsigned int, bool, bool, bool) | bool X86::isCalleePop(CallingConv::ID CallingConv,
bool is64Bit, bool IsVarArg, bool GuaranteeTCO) {
// If GuaranteeTCO is true, we force some calls to be callee pop so that we
// can guarantee TCO.
if (!IsVarArg && shouldGuaranteeTCO(CallingConv, GuaranteeTCO))
return true;
switch (C... | pushq %r14
pushq %rbx
pushq %rax
movl %esi, %ebx
movl %edi, %r14d
testl %edx, %edx
je 0x147e5d5
addl $-0x40, %r14d
cmpl $0x10, %r14d
ja 0x147e643
movl $0x10043, %eax # imm = 0x10043
btl %r14d, %eax
jb 0x147e629
jmp 0x147e643
testb %cl, %cl
je 0x147e60f
movl %r14d, %edi
callq 0x147e647
cmpl $0x12, %r14d
sete %c... | /Target/X86/X86ISelLoweringCall.cpp |
(anonymous namespace)::X86InterleavedAccessGroup::isSupported() const | bool X86InterleavedAccessGroup::isSupported() const {
VectorType *ShuffleVecTy = Shuffles[0]->getType();
Type *ShuffleEltTy = ShuffleVecTy->getElementType();
unsigned ShuffleElemSize = DL.getTypeSizeInBits(ShuffleEltTy);
unsigned WideInstSize;
// Currently, lowering is supported for the following vectors:
... | pushq %r14
pushq %rbx
subq $0x18, %rsp
movq %rdi, %rbx
movq 0x8(%rdi), %rax
movq (%rax), %rax
movq 0x8(%rax), %rax
movq 0x18(%rax), %rsi
movq 0x38(%rdi), %rdi
callq 0x8ef294
leaq 0x8(%rsp), %rdi
movq %rax, (%rdi)
movb %dl, 0x8(%rdi)
callq 0x1cceb6c
movq %rax, %r14
movq 0x30(%rbx), %rax
cmpl $0x7, 0x130(%rax)
jl 0x14838... | /Target/X86/X86InterleavedAccess.cpp |
isConvertibleLEA(llvm::MachineInstr*) | unsigned getOpcode() const { return Opcode; } | movzwl 0x44(%rdi), %eax
addl $0xfffff7d3, %eax # imm = 0xFFFFF7D3
cmpl $0x2, %eax
ja 0x1497ff6
movq 0x20(%rdi), %rax
cmpl $0x0, 0xa4(%rax)
jne 0x1497ff6
cmpb $0x1, 0x80(%rax)
jne 0x1497ff6
cmpq $0x0, 0x90(%rax)
je 0x1497ff9
xorl %eax, %eax
retq
cmpq $0x2, 0x50(%rax)
setl %al
retq
| /llvm/CodeGen/MachineInstr.h |
llvm::X86::getConstantFromPool(llvm::MachineInstr const&, unsigned int) | const Constant *X86::getConstantFromPool(const MachineInstr &MI,
unsigned OpNo) {
assert(MI.getNumOperands() >= (OpNo + X86::AddrNumOperands) &&
"Unexpected number of operands!");
const MachineOperand &Index = MI.getOperand(OpNo + X86::AddrIndexReg);
if (!Index.i... | leal 0x2(%rsi), %ecx
movq 0x20(%rdi), %rax
shlq $0x5, %rcx
cmpb $0x0, (%rax,%rcx)
jne 0x149852e
addq %rax, %rcx
cmpl $0x0, 0x4(%rcx)
jne 0x149852e
addl $0x3, %esi
shlq $0x5, %rsi
cmpb $0x6, (%rax,%rsi)
jne 0x149852e
addq %rsi, %rax
movl 0x4(%rax), %ecx
movl 0x18(%rax), %edx
orq %rdx, %rcx
jne 0x149852e
movq 0x18(%rdi),... | /Target/X86/X86InstrInfo.cpp |
llvm::X86InstrInfo::foldImmediateImpl(llvm::MachineInstr&, llvm::MachineInstr*, llvm::Register, long, llvm::MachineRegisterInfo*, bool) const | bool X86InstrInfo::foldImmediateImpl(MachineInstr &UseMI, MachineInstr *DefMI,
Register Reg, int64_t ImmVal,
MachineRegisterInfo *MRI,
bool MakeChange) const {
bool Modified = false;
// 64 bit operations ... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x48, %rsp
movq %r9, %r12
movq %r8, %r13
movl %ecx, %r15d
movq %rsi, %rbx
testl %ecx, %ecx
js 0x149cf64
xorl %eax, %eax
jmp 0x149cf7d
movl %r15d, %eax
andl $0x7fffffff, %eax # imm = 0x7FFFFFFF
movq 0x38(%r12), %rcx
shlq $0x4, %rax
movq (%rcx,... | /Target/X86/X86InstrInfo.cpp |
llvm::X86InstrInfo::expandPostRAPseudo(llvm::MachineInstr&) const | bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
bool HasAVX = Subtarget.hasAVX();
MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
switch (MI.getOpcode()) {
case X86::MOV32r0:
return Expand2AddrUndef(MIB, get(X86::XOR32rr));
case X86::MOV32r1:
return expandMOV32r1(MIB, *this,... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xc8, %rsp
movq %rdi, %rbx
movq 0x50(%rdi), %r12
movl 0x130(%r12), %ecx
movq 0x18(%rsi), %r15
movq 0x20(%r15), %rbp
movq %rbp, 0x8(%rsp)
movq %rsi, 0x10(%rsp)
movzwl 0x44(%rsi), %r13d
xorl %eax, %eax
leal -0x127(%r13), %edx
cmpl $0x5f, %edx
ja 0x14... | /Target/X86/X86InstrInfo.cpp |
expandNOVLXStore(llvm::MachineInstrBuilder&, llvm::TargetRegisterInfo const*, llvm::MCInstrDesc const&, llvm::MCInstrDesc const&, unsigned int) | static bool expandNOVLXStore(MachineInstrBuilder &MIB,
const TargetRegisterInfo *TRI,
const MCInstrDesc &StoreDesc,
const MCInstrDesc &ExtractDesc, unsigned SubIdx) {
Register SrcReg = MIB.getReg(X86::AddrNumOperands);
// Check i... | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
subq $0x28, %rsp
movq %rdi, %rbx
movq 0x8(%rdi), %rdi
movq 0x20(%rdi), %rax
movl 0xa4(%rax), %r15d
movq 0x68(%rsi), %rax
cmpw $0xf, (%rax,%r15,2)
ja 0x149f047
movq %rdx, %rsi
addq $0x28, %rsp
popq %rbx
popq %r14
popq %r15
popq %rbp
jmp 0x179246e
movl %r8d, %ebp
movq %rsi, %r1... | /Target/X86/X86InstrInfo.cpp |
extractLoadMMOs(llvm::ArrayRef<llvm::MachineMemOperand*>, llvm::MachineFunction&) | static SmallVector<MachineMemOperand *, 2>
extractLoadMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
SmallVector<MachineMemOperand *, 2> LoadMMOs;
for (MachineMemOperand *MMO : MMOs) {
if (!MMO->isLoad())
continue;
if (!MMO->isStore()) {
// Reuse the MMO.
LoadMMOs.push_b... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %rdi, %r15
leaq 0x10(%rdi), %rax
movq %rax, (%rdi)
movabsq $0x200000000, %rax # imm = 0x200000000
movq %rax, 0x8(%rdi)
testq %rdx, %rdx
je 0x14a3924
movq %rcx, %rbx
movq %rdx, %r14
movq %rsi, %r12
shlq $0x3, %r14
xorl %r13d, %r13d
movq (%r12,%r13), %rsi
m... | /Target/X86/X86InstrInfo.cpp |
extractStoreMMOs(llvm::ArrayRef<llvm::MachineMemOperand*>, llvm::MachineFunction&) | static SmallVector<MachineMemOperand *, 2>
extractStoreMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
SmallVector<MachineMemOperand *, 2> StoreMMOs;
for (MachineMemOperand *MMO : MMOs) {
if (!MMO->isStore())
continue;
if (!MMO->isLoad()) {
// Reuse the MMO.
StoreMMOs.pus... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %rdi, %r15
leaq 0x10(%rdi), %rax
movq %rax, (%rdi)
movabsq $0x200000000, %rax # imm = 0x200000000
movq %rax, 0x8(%rdi)
testq %rdx, %rdx
je 0x14a3a83
movq %rcx, %rbx
movq %rdx, %r14
movq %rsi, %r12
shlq $0x3, %r14
xorl %r13d, %r13d
movq (%r12,%r13), %rsi
m... | /Target/X86/X86InstrInfo.cpp |
llvm::X86InstrInfo::getMachineCombinerPatterns(llvm::MachineInstr&, llvm::SmallVectorImpl<unsigned int>&, bool) const | bool X86InstrInfo::getMachineCombinerPatterns(
MachineInstr &Root, SmallVectorImpl<unsigned> &Patterns,
bool DoRegPressureReduce) const {
unsigned Opc = Root.getOpcode();
switch (Opc) {
case X86::VPDPWSSDrr:
case X86::VPDPWSSDrm:
case X86::VPDPWSSDYrr:
case X86::VPDPWSSDYrm: {
if (!Subtarget.has... | pushq %rax
movzwl 0x44(%rsi), %eax
addl $0xffffca35, %eax # imm = 0xFFFFCA35
cmpl $0x1e, %eax
ja 0x14a75b7
movl $0x4120904, %r8d # imm = 0x4120904
btl %eax, %r8d
jae 0x14a759e
movq 0x50(%rdi), %rax
cmpb $0x1, 0x14c(%rax)
je 0x14a75ae
jmp 0x14a75b7
movl $0x60000003, %r8d # imm = 0x60000003
btl %eax, %... | /Target/X86/X86InstrInfo.cpp |
llvm::DenseMap<unsigned int, std::vector<unsigned int, std::allocator<unsigned int>>, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, std::vector<unsigned int, std::allocator<unsigned int>>>>::grow(unsigned int) | void grow(unsigned AtLeast) {
unsigned OldNumBuckets = NumBuckets;
BucketT *OldBuckets = Buckets;
allocateBuckets(std::max<unsigned>(64, static_cast<unsigned>(NextPowerOf2(AtLeast-1))));
assert(Buckets);
if (!OldBuckets) {
this->BaseT::initEmpty();
return;
}
this->moveFromOldBu... | pushq %r15
pushq %r14
pushq %rbx
movq %rdi, %r15
movl 0x10(%rdi), %ebx
movq (%rdi), %r14
leal -0x1(%rsi), %eax
movl %eax, %ecx
shrl %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x2, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x4, %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x8, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x10,... | /llvm/ADT/DenseMap.h |
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