sass stringlengths 231 30.8k | rdna stringlengths 69 28.4k | function_name stringlengths 1 85 | sass_tokens int64 90 14.4k ⌀ | rdna_tokens int64 11 14.5k ⌀ | source stringclasses 15
values |
|---|---|---|---|---|---|
// Demangled: generateHeat(int, int, float*, float*, float*, float)
Function : _Z12generateHeatiiPfS_S_f
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR5, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x380] &wr=0x2 ?trans7;
LDC R23, c[0x0][0x360] &wr=0x1 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, -0x1, URZ &req={2} ?trans1;
IMAD R23, R23, UR5, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R23, UR4, PT ?WAIT5_END_GROUP;
ISETP.LT.OR P0, PT, R23, 0x1, P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC R2, c[0x0][0x384] &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x1 ?trans1;
HFMA2 R22, -RZ, RZ, 0, 0 ?trans1;
ISETP.GE.AND P0, PT, R2, 0x3, PT &req={0} ?WAIT13_END_GROUP;
@!P0 BRA 0xbf0 &req={1} ?trans5;
IADD3 R0, PT, PT, R2, -0x3, RZ ?trans1;
UMOV UR4, 0x1 ?trans1;
IMAD R6, R23, R2, RZ ?trans1;
MOV R22, RZ ?trans2;
ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ?trans1;
IADD3 R0, PT, PT, R2, -0x2, RZ ?WAIT4_END_GROUP;
LOP3.LUT R28, R0, 0x3, RZ, 0xc0, !PT ?WAIT8_END_GROUP;
@!P0 BRA 0x6d0 ?trans5;
LDC.64 R10, c[0x0][0x390] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x388] &wr=0x1 ?trans1;
IADD3 R25, PT, PT, R6, 0x1, RZ ?trans1;
IMAD.WIDE R4, R2, 0x4, RZ ?trans1;
LOP3.LUT R0, R0, 0xfffffffc, RZ, 0xc0, !PT ?trans1;
LDCU.64 UR8, c[0x0][0x388] &wr=0x2 ?trans1;
IADD3 R27, PT, PT, R23, 0x1, RZ ?trans1;
HFMA2 R22, -RZ, RZ, 0, 0 ?trans2;
IMAD.WIDE.U32 R8, R2, 0x4, RZ ?trans1;
IADD3 R0, PT, PT, -R0, RZ, RZ ?trans1;
MOV R29, R25 ?WAIT2_END_GROUP;
IMAD R27, R27, R2, 0x1 ?trans1;
IADD.64 R4, -R4, UR4 &req={1} ?trans2;
UMOV UR4, URZ ?trans2;
IADD.64 R12, R4, -0x4 ?trans2;
IMAD.WIDE.U32 R10, R25, 0x4, R10 &req={0} ?trans1;
MOV.64 R4, UR8 &req={2} ?WAIT4_END_GROUP;
IADD.64 R10, R10, 0x8 ?WAIT8_END_GROUP;
IMAD.WIDE R32, R29, 0x4, R12 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R30, R27, 0x4, R4.reuse ?trans1;
IADD.64 R14, R8, R32 ?trans2;
LDG.E R32, desc[UR6][R32.64+0x4] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R16, R25, 0x4, R4 ?WAIT3_END_GROUP;
LDG.E R31, desc[UR6][R30.64] &wr=0x2 ?trans4;
LDG.E R18, desc[UR6][R14.64] &wr=0x3 ?trans4;
LDG.E R20, desc[UR6][R16.64+0x4] &wr=0x4 ?trans1;
FADD R19, R32, R31 &req={2} ?WAIT4_END_GROUP;
FADD R21, R18, R19 &req={3} ?trans1;
IMAD.WIDE.U32 R18, R25, 0x4, -R8 ?WAIT4_END_GROUP;
FADD R24, R20, R21 &req={4} ?trans1;
IMAD.WIDE.U32 R20, R25, 0x4, R8 ?trans1;
IADD.64 R18, R18, R4 ?WAIT3_END_GROUP;
FMUL R31, R24, 0.25 ?trans1;
IADD.64 R20, R20, R4 ?trans2;
LDG.E R24, desc[UR6][R16.64] &wr=0x2 ?trans4;
STG.E desc[UR6][R10.64+-0x8], R31 &rd=0x2 ?trans4;
LDG.E R26, desc[UR6][R18.64+0x4] &wr=0x3 ?trans4;
LDG.E R33, desc[UR6][R20.64+0x4] &wr=0x3 ?trans4;
LDG.E R14, desc[UR6][R14.64+0x4] &wr=0x4 ?trans4;
LDG.E R30, desc[UR6][R16.64+0x8] &wr=0x5 ?trans1;
FADD R33, R26, R33 &req={3} ?WAIT3_END_GROUP;
LDG.E R26, desc[UR6][R16.64+0x4] &wr=0x3 ?trans1;
FADD R33, R14, R33 &req={4} ?WAIT4_END_GROUP;
FADD R33, R30, R33 &req={5} ?WAIT4_END_GROUP;
FMUL R33, R33, 0.25 ?WAIT5_END_GROUP;
STG.E desc[UR6][R10.64+-0x4], R33 &rd=0x3 ?trans4;
LDG.E R30, desc[UR6][R18.64+0x8] &wr=0x4 ?trans4;
LDG.E R35, desc[UR6][R20.64+0x8] &wr=0x4 ?trans4;
LDG.E R32, desc[UR6][R16.64+0x4] &wr=0x5 ?trans4;
LDG.E R14, desc[UR6][R16.64+0xc] &wr=0x2 ?trans1;
FADD R35, R30, R35 &req={4} ?WAIT4_END_GROUP;
FADD R35, R32, R35 &req={5} ?WAIT4_END_GROUP;
FADD R14, R14, R35 &req={2} ?WAIT4_END_GROUP;
FMUL R15, R14, 0.25 ?trans2;
LDG.E R14, desc[UR6][R16.64+0x8] &wr=0x2 ?trans4;
STG.E desc[UR6][R10.64], R15 &rd=0x2 ?trans4;
LDG.E R34, desc[UR6][R18.64+0xc] &wr=0x4 ?trans4;
LDG.E R35, desc[UR6][R20.64+0xc] &wr=0x4 ?trans4;
LDG.E R36, desc[UR6][R16.64+0x8] &wr=0x5 ?trans4;
LDG.E R30, desc[UR6][R16.64+0x10] &wr=0x5 ?trans4;
LDG.E R32, desc[UR6][R16.64+0xc] &rd=0x0 &wr=0x5 ?trans1;
FADD R31, R24, -R31 ?WAIT5_END_GROUP;
FSETP.GT.AND P0, PT, |R31|, R22, PT ?trans1;
FADD R33, R26, -R33 &req={3} ?WAIT4_END_GROUP;
FSEL R22, |R31|, R22, P0 ?WAIT5_END_GROUP;
FSETP.GT.AND P0, PT, |R33|, R22, PT ?trans1;
IADD3 R0, PT, PT, R0, 0x4, RZ ?WAIT4_END_GROUP;
FSEL R22, |R33|, R22, P0 ?trans1;
ISETP.NE.AND P1, PT, R0, RZ, PT ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x4, URZ ?trans1;
IADD.64 R4, R4, 0x10 ?WAIT3_END_GROUP;
IADD3 R29, PT, PT, R29, 0x4, RZ ?trans1;
FADD R15, R14, -R15 &req={2} ?trans1;
FADD R35, R34, R35 &req={4} ?WAIT4_END_GROUP;
FADD R35, R36, R35 &req={5} ?trans1;
FSETP.GT.AND P0, PT, |R15|, R22, PT ?WAIT3_END_GROUP;
FADD R30, R30, R35 ?WAIT4_END_GROUP;
FMUL R17, R30, 0.25 &req={0} ?trans1;
FSEL R22, |R15|, R22, P0 ?WAIT3_END_GROUP;
FADD R15, R32, -R17 ?trans1;
STG.E desc[UR6][R10.64+0x4], R17 &rd=0x0 ?trans4;
FSETP.GT.AND P0, PT, |R15|, R22, PT ?WAIT5_END_GROUP;
FSEL R22, |R15|, R22, P0 ?trans1;
IADD.64 R10, R10, 0x10 &req={0} ?trans2;
@P1 BRA 0x290 ?trans6;
UIADD3 UR4, UPT, UPT, UR4, 0x1, URZ ?WAIT12_END_GROUP;
ISETP.NE.AND P0, PT, R28, RZ, PT ?WAIT13_END_GROUP;
@!P0 BRA 0xbf0 ?trans5;
ISETP.NE.AND P1, PT, R28, 0x1, PT ?trans1;
LOP3.LUT R0, R2, 0x1, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.U32.AND P0, PT, R0, 0x1, PT ?WAIT7_END_GROUP;
@!P1 BRA 0xa70 ?trans6;
LDC.64 R4, c[0x0][0x388] &wr=0x0 ?trans1;
IADD3 R21, PT, PT, R6, UR4, RZ ?trans1;
LDCU.64 UR8, c[0x0][0x388] &wr=0x1 ?trans3;
IADD3 R15, PT, PT, R21.reuse, -R2.reuse, RZ ?trans2;
IADD3 R17, PT, PT, R21, R2, RZ ?trans1;
LDC.64 R10, c[0x0][0x390] &wr=0x2 ?trans2;
IMAD.WIDE R14, R15, 0x4, R4 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R16, R17, 0x4, R4 ?trans1;
LDG.E R0, desc[UR6][R14.64] &rd=0x0 &wr=0x3 ?trans3;
IMAD.WIDE.U32 R8, R2, 0x4, R14 ?trans2;
LDG.E R17, desc[UR6][R16.64] &wr=0x3 ?trans4;
LDG.E R3, desc[UR6][R8.64+-0x4] &wr=0x4 ?trans1;
IMAD.WIDE.U32 R12, R21, 0x4, R4 ?WAIT5_END_GROUP;
LDG.E R18, desc[UR6][R12.64+0x4] &wr=0x5 ?trans1;
USHF.R.S32.HI UR5, URZ, 0x1f, UR4 ?trans1;
HFMA2 R7, -RZ, RZ, 0, 0 ?WAIT5_END_GROUP;
IADD.64 R14, R6, UR4 &req={0} ?trans2;
IMAD.WIDE.U32 R20, R21, 0x4, R10 &req={2} ?trans1;
LDG.E R13, desc[UR6][R12.64] &wr=0x2 ?trans3;
FADD R0, R0, R17 &req={3} ?WAIT4_END_GROUP;
FADD R19, R3, R0 &req={4} ?trans1;
MOV R3, RZ ?WAIT5_END_GROUP;
IADD.64 R26, R2.reuse, R14.reuse ?trans2;
IADD.64 R16, -R2, R14 ?trans2;
FADD R0, R18, R19 &req={5} ?trans1;
LEA R18, P2, R26, UR8, 0x2 &req={1} ?trans2;
LEA R24, P1, R16, UR8, 0x2 ?trans1;
FMUL R0, R0, 0.25 ?trans1;
LEA.HI.X R19, R26, UR9, R27, 0x2, P2 ?trans2;
LEA.HI.X R25, R16, UR9, R17, 0x2, P1 ?WAIT2_END_GROUP;
SHF.L.U64.HI R15, R14.reuse, 0x2, R15 ?trans1;
IMAD.SHL.U32 R14, R14, 0x4, RZ ?trans1;
STG.E desc[UR6][R20.64], R0 &rd=0x0 ?trans4;
LDG.E R24, desc[UR6][R24.64+0x4] &wr=0x3 ?trans1;
IADD.64 R4, R14, R4 ?WAIT3_END_GROUP;
LDG.E R19, desc[UR6][R18.64+0x4] &wr=0x3 ?trans4;
LDG.E R8, desc[UR6][R8.64] &wr=0x4 ?trans4;
LDG.E R16, desc[UR6][R4.64+0x8] &wr=0x5 ?trans4;
LDG.E R17, desc[UR6][R4.64+0x4] &wr=0x5 ?trans1;
IADD.64 R10, R14, R10 ?WAIT2_END_GROUP;
FADD R13, R13, -R0 &req={2} ?WAIT5_END_GROUP;
FSETP.GT.AND P1, PT, |R13|, R22, PT ?WAIT5_END_GROUP;
FSEL R22, |R13|, R22, P1 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x2, URZ ?trans1;
FADD R27, R24, R19 &req={3} ?WAIT4_END_GROUP;
FADD R27, R8, R27 &req={4} ?WAIT4_END_GROUP;
FADD R16, R16, R27 &req={5} ?WAIT4_END_GROUP;
FMUL R16, R16, 0.25 ?WAIT5_END_GROUP;
STG.E desc[UR6][R10.64+0x4], R16 &rd=0x0 ?trans1;
FADD R17, R17, -R16 ?WAIT5_END_GROUP;
FSETP.GT.AND P1, PT, |R17|, R22, PT ?WAIT5_END_GROUP;
FSEL R22, |R17|, R22, P1 ?WAIT8_END_GROUP;
@P0 BRA 0xbf0 ?trans5;
LDC.64 R8, c[0x0][0x388] &wr=0x1 ?trans1;
IADD3 R13, PT, PT, R6, UR4, RZ ?WAIT4_END_GROUP;
IADD3 R5, PT, PT, R13.reuse, -R2.reuse, RZ ?trans2;
IADD3 R7, PT, PT, R13, R2, RZ ?trans1;
LDC.64 R10, c[0x0][0x390] &req={0} &wr=0x0 ?trans2;
IMAD.WIDE R4, R5, 0x4, R8 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R6, R7, 0x4, R8 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R2, R2, 0x4, R4 ?trans2;
LDG.E R7, desc[UR6][R6.64] &wr=0x2 ?trans4;
LDG.E R4, desc[UR6][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R8, R13, 0x4, R8 ?WAIT3_END_GROUP;
LDG.E R2, desc[UR6][R2.64+-0x4] &wr=0x3 ?trans4;
LDG.E R0, desc[UR6][R8.64+0x4] &wr=0x4 ?trans4;
LDG.E R12, desc[UR6][R8.64] &wr=0x5 ?trans1;
FADD R15, R4, R7 &req={2} ?trans1;
IMAD.WIDE.U32 R6, R13, 0x4, R10 &req={0} ?WAIT4_END_GROUP;
FADD R15, R2, R15 &req={3} ?WAIT4_END_GROUP;
FADD R0, R0, R15 &req={4} ?WAIT4_END_GROUP;
FMUL R11, R0, 0.25 ?WAIT4_END_GROUP;
FADD R5, R12, -R11 &req={5} ?trans1;
STG.E desc[UR6][R6.64], R11 &rd=0x1 ?trans4;
FSETP.GT.AND P0, PT, |R5|, R22, PT ?WAIT5_END_GROUP;
FSEL R22, |R5|, R22, P0 ?WAIT8_END_GROUP;
LDC.64 R2, c[0x0][0x398] &wr=0x2 ?trans2;
IMAD.WIDE.U32 R2, R23, 0x4, R2 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R22 ?trans1;
EXIT ?trans5;
BRA 0xc30;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: generateHeat(int, int, float*, float*, float*, float)
_Z12generateHeatiiPfS_S_f:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_add_i32 s2, s2, -1
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, 0, v1
v_cmp_gt_i32_e64 s2, s2, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_5
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x18
v_mov_b32_e32 v0, 0
s_cmp_lt_i32 s3, 3
s_cbranch_scc1 .LBB0_4
v_mad_u64_u32 v[2:3], null, v1, s3, 1
s_ashr_i32 s9, s3, 31
s_mov_b32 s8, s3
v_mov_b32_e32 v0, 0
s_lshl_b64 s[8:9], s[8:9], 2
s_add_i32 s2, s3, -2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_add_nc_u32_e32 v4, s3, v2
s_sub_u32 s3, 0, s8
v_lshlrev_b64 v[6:7], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[8:9], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v7, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v7, vcc_lo
v_add_co_u32 v6, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v9, vcc_lo
s_subb_u32 s4, 0, s9
.LBB0_3:
v_add_co_u32 v8, vcc_lo, v4, s3
v_add_co_ci_u32_e32 v9, vcc_lo, s4, v5, vcc_lo
s_add_i32 s2, s2, -1
global_load_b32 v11, v[6:7], off
s_clause 0x1
global_load_b32 v12, v[8:9], off
global_load_b96 v[8:10], v[4:5], off offset:-4
v_add_co_u32 v6, vcc_lo, v6, 4
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_cmp_eq_u32 s2, 0
s_waitcnt vmcnt(1)
v_add_f32_e32 v11, v12, v11
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v8, v11, v8
v_add_f32_e32 v8, v8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v9, 0xbe800000, v8
v_mul_f32_e32 v8, 0x3e800000, v8
v_cmp_gt_f32_e64 s5, |v9|, v0
global_store_b32 v[2:3], v8, off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
v_cndmask_b32_e64 v0, v0, |v9|, s5
s_cbranch_scc0 .LBB0_3
.LBB0_4:
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| generateHeat | 5,075 | 1,577 | stackv2-00000-of-00015 |
// Demangled: findLowestVal(int*, int*, int)
Function : _Z13findLowestValPiS_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans1;
S2R R11, SR_TID.X &wr=0x2 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x2 ?trans1;
LDCU UR5, c[0x0][0x390] &wr=0x3 ?trans7;
LDC R6, c[0x0][0x360] &wr=0x2 ?trans1;
LDG.E R7, desc[UR6][R2.64] &req={1} &rd=0x1 &wr=0x5 ?trans1;
BSSY.RECONVERGENT B0, 0x190 ?trans1;
IMAD R0, R6, UR4, R11 &req={2} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, UR5, PT &req={3} ?WAIT13_END_GROUP;
@P0 BRA 0x180 &req={1,0} ?trans5;
LDC.64 R4, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU UR4, c[0x0][0x370] &wr=0x1 ?trans1;
HFMA2 R9, -RZ, RZ, 0, 0 ?trans2;
IMAD R10, R6, UR4, RZ &req={1} ?WAIT7_END_GROUP;
IADD3 R3, PT, PT, R0, R9, RZ ?WAIT5_END_GROUP;
IMAD.WIDE R2, R3, 0x4, R4 &req={0} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR6][R2.64] &wr=0x2 ?trans1;
IADD3 R9, PT, PT, R10, R9, RZ ?WAIT4_END_GROUP;
IADD3 R8, PT, PT, R0, R9, RZ ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R8, UR5, PT ?trans1;
VIMNMX.S32 R7, R2, R7, PT &req={5,2} ?WAIT12_END_GROUP;
@!P0 BRA 0x100 ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
S2UR UR5, SR_CgaCtaId &wr=0x0 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GE.U32.AND P1, PT, R6, 0x2, PT ?trans1;
ISETP.NE.AND P0, PT, R11, RZ, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={0} ?WAIT6_END_GROUP;
LEA R0, R11, UR4, 0x2 ?WAIT5_END_GROUP;
STS [R0], R7 &req={5} &rd=0x0 ?trans1;
@!P1 BRA 0x2c0 ?trans5;
SHF.R.U32.HI R4, RZ, 0x1, R6 ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P1, PT, R11, R4, PT ?WAIT13_END_GROUP;
@!P1 IMAD R3, R4, 0x4, R0 ?trans1;
@!P1 LDS R2, [R0] ?trans5;
@!P1 LDS R3, [R3] &wr=0x1 ?trans2;
@!P1 VIMNMX.S32 R5, R2, R3, PT &req={1} ?WAIT5_END_GROUP;
@!P1 STS [R0], R5 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P1, PT, R6, 0x3, PT ?trans1;
MOV R6, R4 ?WAIT12_END_GROUP;
@P1 BRA 0x210 &req={1} ?trans5;
@P0 EXIT ?trans5;
LDC.64 R2, c[0x0][0x388] &wr=0x1 ?trans2;
LDG.E R0, desc[UR6][R2.64] &req={1,0} &wr=0x2 ?trans6;
S2UR UR5, SR_CgaCtaId &wr=0x0 ?trans1;
UMOV UR4, 0x400 ?trans2;
ULEA UR4, UR5, UR4, 0x18 &req={0} ?WAIT9_END_GROUP;
LDS R5, [UR4] &wr=0x2 ?trans2;
VIMNMX.S32 R5, R0, R5, PT &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R5 ?trans1;
EXIT ?trans5;
BRA 0x360;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: findLowestVal(int*, int*, int)
_Z13findLowestValPiS_i:
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_add_u32 s0, s0, 24
s_addc_u32 s1, s1, 0
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_load_b32 s9, s[4:5], 0x0
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v3, s9
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_4
s_load_b32 s1, s[0:1], 0x0
v_mov_b32_e32 v3, s9
s_mov_b32 s0, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s1, s2
.LBB1_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s3, v1
global_load_b32 v2, v[4:5], off
s_or_b32 s0, vcc_lo, s0
s_waitcnt vmcnt(0)
v_min_i32_e32 v3, v3, v2
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB1_2
s_or_b32 exec_lo, exec_lo, s0
.LBB1_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s8
v_lshlrev_b32_e32 v1, 2, v0
s_cmp_lt_u32 s2, 2
ds_store_b32 v1, v3
s_cbranch_scc1 .LBB1_8
.LBB1_5:
s_lshr_b32 s0, s2, 1
s_mov_b32 s1, exec_lo
v_cmpx_gt_u32_e64 s0, v0
s_cbranch_execz .LBB1_7
v_lshl_add_u32 v2, s0, 2, v1
ds_load_b32 v3, v1
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v2, v3, v2
ds_store_b32 v1, v2
.LBB1_7:
s_or_b32 exec_lo, exec_lo, s1
s_cmp_gt_u32 s2, 3
s_mov_b32 s2, s0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_5
.LBB1_8:
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_10
v_mov_b32_e32 v0, 0
global_load_b32 v1, v0, s[6:7]
ds_load_b32 v2, v0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_min_i32_e32 v1, v1, v2
global_store_b32 v0, v1, s[6:7]
.LBB1_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| findLowestVal | 1,324 | 1,126 | stackv2-00000-of-00015 |
// Demangled: squareMatrix(int*, int*, int)
Function : _Z12squareMatrixPiS_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.Y &wr=0x1 ?trans7;
LDC R2, c[0x0][0x364] &wr=0x1 ?trans1;
LDCU UR18, c[0x0][0x390] &wr=0x2 ?trans1;
S2R R0, SR_TID.X &wr=0x3 ?trans6;
S2UR UR4, SR_CTAID.Y &wr=0x1 ?trans8;
S2UR UR5, SR_CTAID.X &wr=0x3 ?trans8;
LDC R9, c[0x0][0x360] &wr=0x3 ?trans1;
IMAD R2, R2, UR4, R3 &req={1} ?WAIT2_END_GROUP;
IMAD R9, R9, UR5, R0 &req={3} ?WAIT5_END_GROUP;
VIMNMX.S32 R0, R2, R9, !PT ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, UR18, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
UISETP.GE.U32.AND UP0, UPT, UR18, 0x8, UPT ?trans1;
ULOP3.LUT UR6, UR18, 0x7, URZ, 0xc0, !UPT ?trans1;
UMOV UR4, URZ ?trans1;
LDCU.64 UR16, c[0x0][0x358] &wr=0x0 ?trans1;
HFMA2 R0, -RZ, RZ, 0, 0 ?trans2;
IMAD R2, R2, UR18, RZ ?trans1;
PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x8 ?WAIT13_END_GROUP;
@!P0 BRA 0x500 ?trans5;
LDCU.64 UR20, c[0x0][0x380] &wr=0x1 ?trans1;
MOV R5, 0x4 ?trans1;
MOV R8, R9 ?trans1;
ULOP3.LUT UR4, UR18, 0x7ffffff8, URZ, 0xc0, !UPT ?WAIT4_END_GROUP;
UIADD3 UR5, UPT, UPT, -UR4, URZ, URZ ?WAIT3_END_GROUP;
UMOV UR4, URZ ?trans1;
IMAD.WIDE.U32 R4, R2, R5, UR20 &req={1} ?trans1;
UIMAD.WIDE UR8, UR18, 0x14, UR20 ?trans1;
UIMAD.WIDE UR10, UR18, 0x10, UR20 ?trans1;
UIMAD.WIDE UR12, UR18, 0xc, UR20 ?trans1;
UIMAD.WIDE UR14, UR18, 0x8, UR20 ?trans1;
IADD.64 R4, R4, 0x10 ?WAIT11_END_GROUP;
MOV R7, 0x4 ?trans1;
MOV R27, UR18 ?trans1;
HFMA2 R11, -RZ, RZ, 0, 2.384185791015625e-07 ?trans1;
LDG.E R13, desc[UR16][R4.64+-0x10] &req={0} &wr=0x2 ?trans2;
IMAD.WIDE R6, R8, R7, UR20 ?trans1;
MOV R25, 0x4 ?trans1;
LDG.E R14, desc[UR16][R4.64+-0xc] &wr=0x3 ?trans2;
IMAD.WIDE R26, R27, 0x4, R6 ?trans2;
LDG.E R12, desc[UR16][R6.64] &wr=0x2 ?trans2;
HFMA2 R23, -RZ, RZ, 0, 2.384185791015625e-07 ?WAIT2_END_GROUP;
IMAD.WIDE R10, R8.reuse, R11, UR14 ?trans1;
LDG.E R15, desc[UR16][R26.64] &wr=0x3 ?trans1;
MOV R19, 0x4 ?trans2;
IMAD.WIDE R24, R8.reuse, R25, UR12 ?trans1;
LDG.E R17, desc[UR16][R10.64] &rd=0x0 &wr=0x4 ?trans4;
LDG.E R16, desc[UR16][R4.64+-0x8] &wr=0x4 ?trans1;
IMAD.WIDE R22, R8, R23, UR10 ?trans1;
MOV R29, UR18 ?WAIT2_END_GROUP;
LDG.E R21, desc[UR16][R24.64] &wr=0x5 ?trans1;
IMAD.WIDE R18, R8, R19, UR8 ?WAIT3_END_GROUP;
LDG.E R20, desc[UR16][R4.64+-0x4] &wr=0x5 ?trans1;
MOV R31, UR18 ?trans1;
IMAD.WIDE R10, R29, 0x18, R6.reuse &req={0} ?trans2;
LDG.E R22, desc[UR16][R22.64] &wr=0x5 ?trans4;
LDG.E R27, desc[UR16][R4.64] &wr=0x5 ?trans1;
IMAD.WIDE R6, R31, 0x1c, R6 ?WAIT3_END_GROUP;
LDG.E R18, desc[UR16][R18.64] &wr=0x5 ?trans4;
LDG.E R29, desc[UR16][R4.64+0x4] &wr=0x5 ?trans4;
LDG.E R10, desc[UR16][R10.64] &rd=0x0 &wr=0x5 ?trans4;
LDG.E R25, desc[UR16][R4.64+0x8] &wr=0x5 ?trans4;
LDG.E R6, desc[UR16][R6.64] &wr=0x5 ?trans4;
LDG.E R31, desc[UR16][R4.64+0xc] &rd=0x1 &wr=0x5 ?trans1;
UIADD3 UR5, UPT, UPT, UR5, 0x8, URZ ?WAIT6_END_GROUP;
ISETP.NE.AND P0, PT, RZ, UR5, PT ?trans1;
MOV R11, UR18 &req={0} ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x8, URZ ?trans1;
IADD.64 R4, R4, 0x20 &req={1} ?WAIT3_END_GROUP;
IMAD R8, R11, 0x8, R8 ?trans2;
IMAD R12, R13, R12, R0 &req={2} ?WAIT4_END_GROUP;
IMAD R12, R14, R15, R12 &req={3} ?WAIT4_END_GROUP;
IMAD R12, R16, R17, R12 &req={4} ?WAIT4_END_GROUP;
IMAD R12, R20, R21, R12 &req={5} ?WAIT4_END_GROUP;
IMAD R12, R27, R22, R12 ?WAIT4_END_GROUP;
IMAD R12, R29, R18, R12 ?WAIT4_END_GROUP;
IMAD R10, R25, R10, R12 ?WAIT4_END_GROUP;
IMAD R0, R31, R6, R10 ?trans1;
@P0 BRA 0x210 ?trans6;
ISETP.NE.AND P0, PT, RZ, UR6, PT ?WAIT13_END_GROUP;
@!P0 BRA 0xa50 ?trans5;
UISETP.GE.U32.AND UP0, UPT, UR6, 0x4, UPT ?trans1;
ULOP3.LUT UR6, UR18, 0x3, URZ, 0xc0, !UPT ?WAIT5_END_GROUP;
PLOP3.LUT P1, PT, PT, PT, UP0, 0x80, 0x8 ?trans1;
ISETP.NE.AND P0, PT, RZ, UR6, PT ?WAIT12_END_GROUP;
@!P1 BRA 0x7b0 ?trans5;
LDC.64 R10, c[0x0][0x380] &wr=0x1 ?trans1;
LDCU.64 UR8, c[0x0][0x380] &wr=0x2 ?trans1;
HFMA2 R3, -RZ, RZ, 0, 0 ?trans1;
MOV R4, UR4 ?trans1;
MOV R12, UR18 ?trans1;
UMOV UR5, URZ ?trans1;
USHF.R.S32.HI UR7, URZ, 0x1f, UR18 ?trans1;
IADD.64 R18, R2, UR4 ?trans2;
IMAD R7, R4, UR18, R9 ?trans1;
IADD3 R17, PT, PT, R2, UR4, RZ ?WAIT2_END_GROUP;
MOV R13, UR7 ?WAIT5_END_GROUP;
IADD.64 R14, R12, R12 ?WAIT3_END_GROUP;
LEA R4, P1, R18, UR8, 0x2 &req={2} ?trans1;
IMAD.WIDE R6, R7, 0x4, R10 &req={1} ?WAIT3_END_GROUP;
LEA.HI.X R5, R18, UR9, R19, 0x2, P1 ?trans1;
MOV R19, UR18 ?trans1;
IMAD.WIDE.U32 R10, R17, 0x4, R10 ?trans1;
IADD.64 R16, R12, R14 ?trans2;
LDG.E R8, desc[UR16][R6.64] &req={0} &wr=0x2 ?trans1;
LEA R18, P1, R14.reuse, R6, 0x2 ?trans1;
IMAD.WIDE R12, R19, 0x4, R6 ?trans2;
LDG.E R11, desc[UR16][R10.64] &wr=0x2 ?trans1;
LEA.HI.X R19, R14, R7, R15, 0x2, P1 ?WAIT2_END_GROUP;
LEA R14, P1, R16.reuse, R6, 0x2 ?trans1;
LDG.E R12, desc[UR16][R12.64] &wr=0x3 ?trans4;
LDG.E R21, desc[UR16][R4.64+0x4] &wr=0x3 ?trans1;
LEA.HI.X R15, R16, R7, R17, 0x2, P1 ?WAIT3_END_GROUP;
LDG.E R18, desc[UR16][R18.64] &wr=0x4 ?trans4;
LDG.E R17, desc[UR16][R4.64+0x8] &wr=0x4 ?trans4;
LDG.E R23, desc[UR16][R4.64+0xc] &wr=0x5 ?trans4;
LDG.E R14, desc[UR16][R14.64] &wr=0x5 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x4, URZ ?trans1;
IMAD R8, R11, R8, R0 &req={2} ?WAIT4_END_GROUP;
IMAD R8, R21, R12, R8 &req={3} ?WAIT4_END_GROUP;
IMAD R8, R17, R18, R8 &req={4} ?WAIT4_END_GROUP;
IMAD R0, R23, R14, R8 &req={5} ?WAIT7_END_GROUP;
@!P0 BRA 0xa50 ?trans5;
UISETP.NE.AND UP0, UPT, UR6, 0x1, UPT ?trans1;
ULOP3.LUT UR5, UR18, 0x1, URZ, 0xc0, !UPT ?trans1;
MOV R8, UR4 ?WAIT3_END_GROUP;
UISETP.NE.U32.AND UP1, UPT, UR5, 0x1, UPT ?trans1;
PLOP3.LUT P1, PT, PT, PT, UP0, 0x80, 0x8 ?WAIT5_END_GROUP;
@UP0 LDCU.64 UR8, c[0x0][0x380] &wr=0x1 ?trans1;
PLOP3.LUT P2, PT, PT, PT, UP1, 0x80, 0x8 ?trans1;
@UP0 LDCU.64 UR10, c[0x0][0x380] &wr=0x2 ?trans3;
@!UP1 LDCU.64 UR12, c[0x0][0x380] &wr=0x3 ?trans3;
@P1 MOV R4, R2 ?trans1;
@P1 MOV R5, RZ ?trans1;
@P1 IADD3 R15, PT, PT, R2, UR4, RZ ?trans1;
@UP0 UMOV UR6, UR4 ?trans1;
@UP0 UMOV UR7, URZ ?trans1;
@UP0 UIADD3 UR4, UPT, UPT, UR4, 0x2, URZ ?trans1;
@P1 IADD.64 R6, R4, UR6 ?WAIT2_END_GROUP;
@P1 IMAD R5, R8, UR18, R9 ?trans1;
MOV.64 R10, UR8 &req={1} ?trans2;
MOV.64 R12, UR8 ?trans2;
MOV R8, UR4 ?trans1;
@P1 LEA R4, P0, R6, UR10, 0x2 &req={2} ?trans1;
@P1 IMAD.WIDE.U32 R10, R15, 0x4, R10 ?trans1;
MOV R15, UR18 ?WAIT3_END_GROUP;
@P1 IMAD.WIDE R12, R5, 0x4, R12 ?trans1;
@P1 LEA.HI.X R5, R6, UR11, R7, 0x2, P0 ?trans1;
@P1 LDG.E R23, desc[UR16][R10.64] &req={0} &rd=0x0 &wr=0x2 ?trans1;
MOV.64 R6, UR12 &req={3} ?WAIT3_END_GROUP;
@!P2 IADD3 R19, PT, PT, R2, UR4, RZ ?trans1;
MOV.64 R16, UR12 ?trans2;
@P1 IMAD.WIDE R14, R15, 0x4, R12 ?trans1;
@P1 LDG.E R4, desc[UR16][R4.64+0x4] &wr=0x3 ?trans3;
@!P2 IMAD R21, R8, UR18, R9 ?trans1;
@P1 LDG.E R12, desc[UR16][R12.64] &wr=0x2 ?trans1;
@!P2 IMAD.WIDE.U32 R6, R19, 0x4, R6 ?WAIT3_END_GROUP;
@P1 LDG.E R14, desc[UR16][R14.64] &wr=0x3 ?trans1;
@!P2 IMAD.WIDE R10, R21, 0x4, R16 &req={0} ?WAIT3_END_GROUP;
@!P2 LDG.E R7, desc[UR16][R6.64] &wr=0x4 ?trans4;
@!P2 LDG.E R10, desc[UR16][R10.64] &wr=0x4 ?trans1;
@P1 IMAD R23, R23, R12, R0 &req={2} ?WAIT4_END_GROUP;
@P1 IMAD R0, R4, R14, R23 &req={3} ?WAIT4_END_GROUP;
@!P2 IMAD R0, R7, R10, R0 &req={4} ?WAIT7_END_GROUP;
LDC.64 R4, c[0x0][0x388] &wr=0x1 ?trans1;
IADD3 R3, PT, PT, R9, R2, RZ ?WAIT5_END_GROUP;
IMAD.WIDE R2, R3, 0x4, R4 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR16][R2.64], R0 &req={0} ?trans1;
EXIT ?trans5;
BRA 0xaa0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: squareMatrix(int*, int*, int)
_Z12squareMatrixPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
v_mad_u64_u32 v[0:1], null, s14, s2, v[4:5]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v1, v2, v0
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_6
s_load_b128 s[0:3], s[0:1], 0x0
v_mul_lo_u32 v1, v2, s4
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s5, s4
v_mov_b32_e32 v5, v0
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s5, s5, -1
s_cmp_eq_u32 s5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s0, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
global_load_b32 v8, v[3:4], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s4, v5
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
.LBB0_5:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v1, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| squareMatrix | 4,366 | 1,215 | stackv2-00000-of-00015 |
// Demangled: inCircle(float*, float*, int*)
Function : _Z8inCirclePfS_Pi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R7, SR_TID.X &wr=0x1 ?trans7;
S2UR UR5, SR_CTAID.X ?trans1;
LDCU UR4, c[0x0][0x374] &wr=0x2 ?trans1;
S2R R9, SR_TID.Y &wr=0x3 ?trans1;
S2R R11, SR_TID.Z &wr=0x4 ?trans5;
S2UR UR6, SR_CTAID.Y &wr=0x2 ?trans8;
LDC R0, c[0x0][0x360] &wr=0x1 ?trans1;
LDCU UR8, c[0x0][0x364] &wr=0x3 ?trans1;
LDCU UR9, c[0x0][0x368] &wr=0x4 ?trans6;
LDC.64 R4, c[0x0][0x388] &wr=0x5 ?trans8;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
UIMAD UR4, UR4, UR5, UR6 &req={2} ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x2 ?trans5;
IMAD R0, R0, UR4, R7 &req={1} ?WAIT4_END_GROUP;
IMAD R0, R0, UR8, R9 &req={3} ?WAIT4_END_GROUP;
IMAD R7, R0, UR9, R11 &req={4} ?WAIT4_END_GROUP;
IMAD.WIDE R4, R7, 0x4, R4 &req={5} ?WAIT4_END_GROUP;
IMAD.WIDE R2, R7, 0x4, R2 &req={0} ?trans2;
LDG.E R4, desc[UR6][R4.64] &req={2} &wr=0x2 ?trans4;
LDG.E R2, desc[UR6][R2.64] &wr=0x3 ?trans1;
FMUL R9, R4, R4 &req={2} ?WAIT4_END_GROUP;
FFMA R9, R2, R2, R9 &req={3} ?WAIT5_END_GROUP;
FSETP.GTU.AND P0, PT, R9, 1, PT ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LDCU.64 UR4, c[0x0][0x390] &wr=0x0 ?trans1;
SHF.R.S32.HI R0, RZ, 0x1f, R7 ?trans1;
HFMA2 R5, -RZ, RZ, 0, 5.9604644775390625e-08 ?trans1;
LEA R2, P0, R7, UR4, 0x2 &req={0} ?WAIT4_END_GROUP;
LEA.HI.X R3, R7, UR5, R0, 0x2, P0 ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R5 ?trans1;
EXIT ?trans5;
BRA 0x200;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: inCircle(float*, float*, int*)
_Z8inCirclePfS_Pi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x24
v_and_b32_e32 v1, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s4, s14
s_and_b32 s5, s2, 0xffff
s_add_i32 s4, s4, s15
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s4, s5, v[1:2]
v_bfe_u32 v1, v0, 10, 10
v_bfe_u32 v0, v0, 20, 10
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, v2, s2, v[1:2]
s_and_b32 s2, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, v3, s2, v[0:1]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
s_waitcnt vmcnt(1)
v_mul_f32_e32 v2, v2, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, v3, v3
v_cmpx_ge_f32_e32 1.0, v2
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v2, 1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| inCircle | 873 | 865 | stackv2-00000-of-00015 |
// Demangled: add(vector3*, vector3*, vector3*, int, int)
Function : _Z3addP7vector3S0_S0_ii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R11, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x39c] &wr=0x1 ?trans2;
ISETP.GE.AND P0, PT, R11, UR4, PT &req={1} ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans1;
LDCU UR6, c[0x0][0x398] &wr=0x3 ?trans6;
LDC.64 R4, c[0x0][0x388] &wr=0x4 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x5 ?trans1;
IMAD.WIDE.U32 R2, R11, 0xc, R2 &req={1} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR4][R2.64] &req={2} &wr=0x2 ?trans1;
IMAD.WIDE.U32 R4, R11, 0xc, R4 &req={4} ?WAIT5_END_GROUP;
LDG.E R9, desc[UR4][R4.64] &wr=0x2 ?trans1;
IADD3 R11, PT, PT, R11, UR6, RZ &req={3} ?WAIT5_END_GROUP;
IMAD.WIDE R6, R11, 0xc, R6 &req={5} ?WAIT4_END_GROUP;
FADD R9, R0, R9 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans4;
LDG.E R0, desc[UR4][R2.64+0x4] &wr=0x2 ?trans4;
LDG.E R11, desc[UR4][R4.64+0x4] &wr=0x2 ?trans2;
FADD R11, R0, R11 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64+0x4], R11 ?trans4;
LDG.E R0, desc[UR4][R2.64+0x8] &wr=0x2 ?trans4;
LDG.E R13, desc[UR4][R4.64+0x8] &wr=0x2 ?trans2;
FADD R13, R0, R13 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64+0x8], R13 ?trans1;
EXIT ?trans5;
BRA 0x1b0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: add(vector3*, vector3*, vector3*, int, int)
_Z3addP7vector3S0_S0_ii:
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s3
s_cbranch_scc1 .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_mul_i32 s3, s15, 12
s_mul_hi_i32 s8, s15, 12
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s3
s_addc_u32 s5, s5, s8
s_add_u32 s6, s6, s3
s_addc_u32 s7, s7, s8
s_add_i32 s2, s15, s2
s_load_b64 s[8:9], s[6:7], 0x0
s_clause 0x1
s_load_b64 s[10:11], s[4:5], 0x0
s_load_b32 s3, s[4:5], 0x8
s_load_b32 s4, s[6:7], 0x8
s_mul_i32 s5, s2, 12
s_mul_hi_i32 s2, s2, 12
s_add_u32 s0, s0, s5
s_addc_u32 s1, s1, s2
s_waitcnt lgkmcnt(0)
v_add_f32_e64 v0, s10, s8
v_add_f32_e64 v1, s11, s9
v_add_f32_e64 v2, s3, s4
global_store_b96 v3, v[0:2], s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| add | 786 | 520 | stackv2-00000-of-00015 |
// Demangled: cross(vector3*, vector3*, vector3*, int, int)
Function : _Z5crossP7vector3S0_S0_ii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R13, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x39c] &wr=0x1 ?trans2;
ISETP.GE.AND P0, PT, R13, UR4, PT &req={1} ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans1;
LDCU UR6, c[0x0][0x398] &wr=0x3 ?trans6;
LDC.64 R4, c[0x0][0x388] &wr=0x4 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x5 ?trans1;
IMAD.WIDE.U32 R2, R13, 0xc, R2 &req={1} ?WAIT5_END_GROUP;
LDG.E R8, desc[UR4][R2.64+0x8] &req={2} &wr=0x2 ?trans1;
IMAD.WIDE.U32 R4, R13, 0xc, R4 &req={4} ?WAIT3_END_GROUP;
LDG.E R0, desc[UR4][R2.64+0x4] &wr=0x4 ?trans4;
LDG.E R11, desc[UR4][R4.64+0x4] &wr=0x2 ?trans4;
LDG.E R9, desc[UR4][R4.64+0x8] &wr=0x4 ?trans1;
IADD3 R13, PT, PT, R13, UR6, RZ &req={3} ?WAIT5_END_GROUP;
IMAD.WIDE R6, R13, 0xc, R6 &req={5} ?WAIT4_END_GROUP;
FMUL R11, R8, R11 &req={2} ?WAIT4_END_GROUP;
FFMA R11, R0, R9, -R11 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R11 ?trans4;
LDG.E R0, desc[UR4][R2.64] &wr=0x2 ?trans4;
LDG.E R13, desc[UR4][R4.64] &wr=0x3 ?trans1;
FMUL R9, R9, R0 &req={2} ?WAIT4_END_GROUP;
FFMA R9, R8, R13, -R9 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64+0x4], R9 ?trans4;
LDG.E R8, desc[UR4][R2.64+0x4] &wr=0x2 ?trans4;
LDG.E R15, desc[UR4][R4.64+0x4] &wr=0x3 ?trans1;
FMUL R13, R13, R8 &req={2} ?WAIT4_END_GROUP;
FFMA R13, R0, R15, -R13 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64+0x8], R13 ?trans1;
EXIT ?trans5;
BRA 0x200;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: cross(vector3*, vector3*, vector3*, int, int)
_Z5crossP7vector3S0_S0_ii:
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s3
s_cbranch_scc1 .LBB3_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_mul_i32 s3, s15, 12
s_mul_hi_i32 s8, s15, 12
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s3
s_addc_u32 s5, s5, s8
s_add_u32 s6, s6, s3
s_addc_u32 s7, s7, s8
s_load_b64 s[8:9], s[4:5], 0x4
s_load_b64 s[10:11], s[6:7], 0x4
s_add_i32 s2, s15, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s3, s2, 12
s_mul_hi_i32 s2, s2, 12
s_add_u32 s0, s0, s3
s_addc_u32 s1, s1, s2
s_waitcnt lgkmcnt(0)
v_mul_f32_e64 v0, s9, s10
s_delay_alu instid0(VALU_DEP_1)
v_fma_f32 v0, s8, s11, -v0
global_store_b32 v1, v0, s[0:1]
s_clause 0x1
global_load_b32 v0, v1, s[4:5]
global_load_b32 v2, v1, s[6:7]
s_waitcnt vmcnt(1)
v_mul_f32_e32 v3, s11, v0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fma_f32 v3, s9, v2, -v3
global_store_b32 v1, v3, s[0:1] offset:4
s_clause 0x1
global_load_b32 v3, v1, s[4:5] offset:4
global_load_b32 v4, v1, s[6:7] offset:4
s_waitcnt vmcnt(1)
v_mul_f32_e32 v2, v2, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fma_f32 v0, v0, v4, -v2
global_store_b32 v1, v0, s[0:1] offset:8
.LBB3_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| cross | 936 | 753 | stackv2-00000-of-00015 |
// Demangled: prod(vector3*, vector3*, float*, int, int)
Function : _Z4prodP7vector3S0_Pfii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R15, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x39c] &wr=0x1 ?trans2;
ISETP.GE.AND P0, PT, R15, UR4, PT &req={1} ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans1;
LDCU UR6, c[0x0][0x398] &wr=0x3 ?trans6;
LDC.64 R4, c[0x0][0x388] &wr=0x4 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x5 ?trans1;
IMAD.WIDE.U32 R2, R15, 0xc, R2 &req={1} ?WAIT5_END_GROUP;
LDG.E R8, desc[UR4][R2.64+0x4] &req={2} &wr=0x2 ?trans1;
IMAD.WIDE.U32 R4, R15, 0xc, R4 &req={4} ?WAIT3_END_GROUP;
LDG.E R0, desc[UR4][R2.64] &wr=0x4 ?trans4;
LDG.E R11, desc[UR4][R4.64+0x4] &wr=0x2 ?trans4;
LDG.E R9, desc[UR4][R4.64] &wr=0x4 ?trans4;
LDG.E R13, desc[UR4][R2.64+0x8] &wr=0x4 ?trans4;
LDG.E R10, desc[UR4][R4.64+0x8] &wr=0x4 ?trans1;
IADD3 R15, PT, PT, R15, UR6, RZ &req={3} ?WAIT5_END_GROUP;
IMAD.WIDE R6, R15, 0x4, R6 &req={5} ?WAIT4_END_GROUP;
FMUL R11, R8, R11 &req={2} ?WAIT4_END_GROUP;
FFMA R0, R0, R9, R11 &req={4} ?WAIT4_END_GROUP;
FFMA R13, R13, R10, R0 ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R13 ?trans1;
EXIT ?trans5;
BRA 0x190;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: prod(vector3*, vector3*, float*, int, int)
_Z4prodP7vector3S0_Pfii:
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s3
s_cbranch_scc1 .LBB2_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_mul_i32 s3, s15, 12
s_mul_hi_i32 s8, s15, 12
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s3
s_addc_u32 s5, s5, s8
s_add_u32 s6, s6, s3
s_addc_u32 s7, s7, s8
s_add_i32 s2, s15, s2
s_load_b64 s[8:9], s[6:7], 0x0
s_clause 0x1
s_load_b64 s[10:11], s[4:5], 0x0
s_load_b32 s4, s[4:5], 0x8
s_load_b32 s5, s[6:7], 0x8
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt lgkmcnt(0)
v_mul_f32_e64 v0, s11, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e64 v0, s10, s8
v_fmac_f32_e64 v0, s4, s5
global_store_b32 v1, v0, s[0:1]
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| prod | 745 | 590 | stackv2-00000-of-00015 |
// Demangled: sub(vector3*, vector3*, vector3*, int, int)
Function : _Z3subP7vector3S0_S0_ii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R11, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x39c] &wr=0x1 ?trans2;
ISETP.GE.AND P0, PT, R11, UR4, PT &req={1} ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans1;
LDCU UR6, c[0x0][0x398] &wr=0x3 ?trans6;
LDC.64 R4, c[0x0][0x388] &wr=0x4 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x5 ?trans1;
IMAD.WIDE.U32 R2, R11, 0xc, R2 &req={1} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR4][R2.64] &req={2} &wr=0x2 ?trans1;
IMAD.WIDE.U32 R4, R11, 0xc, R4 &req={4} ?WAIT5_END_GROUP;
LDG.E R9, desc[UR4][R4.64] &wr=0x2 ?trans1;
IADD3 R11, PT, PT, R11, UR6, RZ &req={3} ?WAIT5_END_GROUP;
IMAD.WIDE R6, R11, 0xc, R6 &req={5} ?WAIT4_END_GROUP;
FADD R9, R0, -R9 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans4;
LDG.E R0, desc[UR4][R2.64+0x4] &wr=0x2 ?trans4;
LDG.E R11, desc[UR4][R4.64+0x4] &wr=0x2 ?trans2;
FADD R11, R0, -R11 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64+0x4], R11 ?trans4;
LDG.E R0, desc[UR4][R2.64+0x8] &wr=0x2 ?trans4;
LDG.E R13, desc[UR4][R4.64+0x8] &wr=0x2 ?trans2;
FADD R13, R0, -R13 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64+0x8], R13 ?trans1;
EXIT ?trans5;
BRA 0x1b0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: sub(vector3*, vector3*, vector3*, int, int)
_Z3subP7vector3S0_S0_ii:
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s3
s_cbranch_scc1 .LBB1_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_mul_i32 s3, s15, 12
s_mul_hi_i32 s8, s15, 12
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s3
s_addc_u32 s5, s5, s8
s_add_u32 s6, s6, s3
s_addc_u32 s7, s7, s8
s_add_i32 s2, s15, s2
s_load_b64 s[8:9], s[6:7], 0x0
s_clause 0x1
s_load_b64 s[10:11], s[4:5], 0x0
s_load_b32 s3, s[4:5], 0x8
s_load_b32 s4, s[6:7], 0x8
s_mul_i32 s5, s2, 12
s_mul_hi_i32 s2, s2, 12
s_add_u32 s0, s0, s5
s_addc_u32 s1, s1, s2
s_waitcnt lgkmcnt(0)
v_sub_f32_e64 v0, s10, s8
v_sub_f32_e64 v1, s11, s9
v_sub_f32_e64 v2, s3, s4
global_store_b96 v3, v[0:2], s[0:1]
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| sub | 789 | 520 | stackv2-00000-of-00015 |
// Demangled: BackwardSubstitution(float*, float*, float*, int)
Function : _Z20BackwardSubstitutionPfS_S_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R2, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
BSSY.RECONVERGENT B0, 0x220 ?trans1;
S2R R5, SR_TID.X &wr=0x2 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x3 ?trans1;
IMAD R0, R2, UR4, RZ &req={1} ?trans1;
IADD3 R3, PT, PT, -R5, RZ, RZ &req={2} ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R0, R3, PT ?WAIT13_END_GROUP;
@P0 BRA 0x210 &req={3,0} ?trans5;
LDC R11, c[0x0][0x398] &wr=0x0 ?trans8;
LDC.64 R8, c[0x0][0x380] &wr=0x1 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x2 ?trans1;
IADD3 R0, PT, PT, R11, -0x1, RZ &req={0} ?WAIT5_END_GROUP;
IMAD R3, R0, R11, R0 ?WAIT4_END_GROUP;
IMAD.WIDE R8, R3, 0x4, R8 &req={1} ?WAIT5_END_GROUP;
LDG.E R3, desc[UR6][R8.64] &wr=0x3 ?trans1;
IMAD.WIDE R6, R11, 0x4, R6 &req={2} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR6][R6.64+-0x4] &wr=0x2 ?trans1;
MUFU.RCP R4, R3 &req={3} &wr=0x0 ?trans1;
FCHK P0, R0, R3 &req={2} &wr=0x1 ?trans1;
FFMA R11, -R3, R4, 1 &req={0} ?WAIT4_END_GROUP;
FFMA R11, R4, R11, R4 ?WAIT4_END_GROUP;
FFMA R4, R0, R11, RZ ?WAIT4_END_GROUP;
FFMA R10, -R3, R4, R0 ?WAIT4_END_GROUP;
FFMA R11, R11, R10, R4 ?trans1;
@!P0 BRA 0x1d0 &req={1} ?trans6;
MOV R4, 0x1d0 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x530 ?trans5;
LDC R3, c[0x0][0x398] &wr=0x0 ?trans8;
LDC.64 R6, c[0x0][0x388] &wr=0x0 ?trans2;
IMAD.WIDE R6, R3, 0x4, R6 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64+-0x4], R11 &rd=0x0 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
LDC R13, c[0x0][0x398] &wr=0x1 ?trans2;
IADD3 R2, PT, PT, -R2, -0x2, R13 &req={1} ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R2, R5, RZ ?WAIT4_END_GROUP;
LOP3.LUT R0, RZ, R0, RZ, 0x33, !PT ?WAIT4_END_GROUP;
IADD3 R3, PT, PT, R0, R13, RZ ?WAIT5_END_GROUP;
VIMNMX.S32 R0, R2, R3, !PT ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, R13, PT ?WAIT5_END_GROUP;
ISETP.LT.OR P0, PT, R3, RZ, P0 ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
ISETP.NE.AND P0, PT, R5, RZ, PT ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans8;
LDC.64 R10, c[0x0][0x380] &req={0} &wr=0x0 ?trans8;
@!P0 LDC.64 R4, c[0x0][0x390] &wr=0x2 ?trans8;
LDC.64 R8, c[0x0][0x388] &wr=0x3 ?trans1;
@!P0 IMAD.WIDE R4, R2, 0x4, R4 &req={2} ?WAIT5_END_GROUP;
@!P0 LDG.E R0, desc[UR6][R4.64] &wr=0x2 ?trans1;
UMOV UR4, 0x400 ?trans1;
IMAD R7, R3.reuse, R13, R2 ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?trans1;
IMAD.WIDE.U32 R8, R3, 0x4, R8 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE R6, R7, 0x4, R10 &req={0} ?WAIT4_END_GROUP;
@!P0 STS [UR4], R0 &req={2} ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDG.E R6, desc[UR6][R6.64] &wr=0x2 ?trans4;
LDG.E R8, desc[UR6][R8.64] &wr=0x2 ?trans1;
IMAD R5, R2, R13, R2 ?WAIT3_END_GROUP;
LDS R3, [UR4] &wr=0x2 ?trans1;
IMAD.WIDE R4, R5, 0x4, R10 ?WAIT4_END_GROUP;
FFMA R3, -R6, R8, R3 &req={2} ?WAIT5_END_GROUP;
STS [UR4], R3 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDG.E R5, desc[UR6][R4.64] &wr=0x2 ?trans4;
LDS R0, [UR4] &wr=0x0 ?trans1;
MUFU.RCP R10, R5 &req={2} &wr=0x1 ?trans1;
FCHK P0, R0, R5 &req={0} &wr=0x0 ?trans1;
FFMA R7, -R5, R10, 1 &req={1} ?WAIT4_END_GROUP;
FFMA R7, R10, R7, R10 ?WAIT4_END_GROUP;
FFMA R6, R0, R7, RZ ?WAIT4_END_GROUP;
FFMA R8, -R5, R6, R0 ?WAIT4_END_GROUP;
FFMA R7, R7, R8, R6 ?trans1;
@!P0 BRA 0x4f0 &req={0} ?trans6;
MOV R3, R5 ?trans1;
MOV R4, 0x4e0 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x530 ?trans5;
MOV R7, R11 ?WAIT7_END_GROUP;
LDC.64 R4, c[0x0][0x388] &wr=0x0 ?trans2;
IMAD.WIDE R2, R2, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R7 ?trans1;
EXIT ?trans5;
SHF.R.U32.HI R7, RZ, 0x17, R3 ?trans1;
BSSY.RECONVERGENT B1, 0xb70 ?trans1;
SHF.R.U32.HI R6, RZ, 0x17, R0 ?trans2;
LOP3.LUT R12, R7, 0xff, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R10, R6, 0xff, RZ, 0xc0, !PT ?trans2;
IADD3 R8, PT, PT, R12, -0x1, RZ ?trans2;
IADD3 R7, PT, PT, R10, -0x1, RZ ?WAIT3_END_GROUP;
ISETP.GT.U32.AND P0, PT, R8, 0xfd, PT ?WAIT5_END_GROUP;
ISETP.GT.U32.OR P0, PT, R7, 0xfd, P0 ?WAIT13_END_GROUP;
@!P0 MOV R6, RZ ?trans1;
@!P0 BRA 0x750 ?trans6;
FSETP.GTU.FTZ.AND P0, PT, |R0|, +INF , PT ?trans1;
FSETP.GTU.FTZ.AND P1, PT, |R3|, +INF , PT ?WAIT5_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, PT, 0xf8, 0x8f ?WAIT13_END_GROUP;
@P0 BRA 0xb50 ?trans5;
LOP3.LUT P0, RZ, R3, 0x7fffffff, R0, 0xc8, !PT ?WAIT13_END_GROUP;
@!P0 BRA 0xb30 ?trans5;
FSETP.NEU.FTZ.AND P2, PT, |R0|.reuse, +INF , PT ?trans1;
FSETP.NEU.FTZ.AND P1, PT, |R3|, +INF , PT ?trans1;
FSETP.NEU.FTZ.AND P0, PT, |R0|, +INF , PT ?WAIT12_END_GROUP;
@!P1 BRA !P2, 0xb30 ?trans5;
LOP3.LUT P2, RZ, R0, 0x7fffffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P1, PT, P1, P2, PT, 0x2f, 0xf2 ?WAIT13_END_GROUP;
@P1 BRA 0xb10 ?trans5;
LOP3.LUT P1, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, PT, 0x2f, 0xf2 ?WAIT13_END_GROUP;
@P0 BRA 0xae0 ?trans5;
ISETP.GE.AND P0, PT, R7, RZ, PT ?trans1;
ISETP.GE.AND P1, PT, R8, RZ, PT ?WAIT12_END_GROUP;
@P0 MOV R6, RZ ?trans1;
@!P0 MOV R6, 0xffffffc0 ?trans1;
@!P0 FFMA R0, R0, 1.84467440737095516160e+19, RZ ?trans1;
@!P1 FFMA R3, R3, 1.84467440737095516160e+19, RZ ?WAIT3_END_GROUP;
@!P1 IADD3 R6, PT, PT, R6, 0x40, RZ ?WAIT7_END_GROUP;
LEA R8, R12, 0xc0800000, 0x17 ?trans1;
BSSY.RECONVERGENT B2, 0xad0 ?trans3;
IADD3 R8, PT, PT, -R8, R3, RZ ?trans2;
IADD3 R3, PT, PT, R10, -0x7f, RZ ?trans2;
MUFU.RCP R7, R8 &wr=0x0 ?trans1;
FADD.FTZ R9, -R8, -RZ ?trans2;
IMAD R0, R3.reuse, -0x800000, R0 ?trans1;
IADD3 R3, PT, PT, R3, 0x7f, -R12 ?WAIT4_END_GROUP;
IADD3 R3, PT, PT, R3, R6, RZ ?trans1;
FFMA R10, R7, R9, 1 &req={0} ?WAIT4_END_GROUP;
FFMA R14, R7, R10, R7 ?WAIT4_END_GROUP;
FFMA R7, R0, R14, RZ ?WAIT4_END_GROUP;
FFMA R10, R9, R7, R0 ?WAIT4_END_GROUP;
FFMA R11, R14, R10, R7 ?WAIT4_END_GROUP;
FFMA R10, R9, R11, R0 ?WAIT4_END_GROUP;
FFMA R7, R14, R10, R11 ?WAIT5_END_GROUP;
SHF.R.U32.HI R0, RZ, 0x17, R7 ?WAIT4_END_GROUP;
LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R8, PT, PT, R0, R3, RZ ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R8, -0x1, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R0, 0xfe, PT ?WAIT13_END_GROUP;
@!P0 BRA 0xab0 ?trans5;
ISETP.GT.AND P0, PT, R8, 0xfe, PT ?WAIT13_END_GROUP;
@P0 BRA 0xa80 ?trans5;
ISETP.GE.AND P0, PT, R8, 0x1, PT ?WAIT13_END_GROUP;
@P0 BRA 0xac0 ?trans5;
ISETP.GE.AND P0, PT, R8, -0x18, PT ?trans1;
LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ?WAIT12_END_GROUP;
@!P0 BRA 0xac0 ?trans5;
FFMA.RZ R0, R14, R10.reuse, R11.reuse ?trans1;
IADD3 R9, PT, PT, R8, 0x20, RZ ?trans1;
FFMA.RM R3, R14, R10.reuse, R11.reuse ?trans1;
ISETP.NE.AND P1, PT, R8.reuse, RZ, PT ?trans1;
ISETP.NE.AND P2, PT, R8, RZ, PT ?trans1;
LOP3.LUT R0, R0, 0x7fffff, RZ, 0xc0, !PT ?trans2;
IADD3 R8, PT, PT, -R8, RZ, RZ ?trans2;
LOP3.LUT R6, R0, 0x800000, RZ, 0xfc, !PT ?trans1;
FFMA.RP R0, R14, R10, R11 ?WAIT3_END_GROUP;
SHF.L.U32 R9, R6, R9, RZ ?trans2;
FSETP.NEU.FTZ.AND P0, PT, R0, R3, PT ?trans1;
SEL R3, R8, RZ, P2 ?trans2;
ISETP.NE.AND P1, PT, R9, RZ, P1 ?WAIT3_END_GROUP;
SHF.R.U32.HI R3, RZ, R3, R6 ?trans2;
PLOP3.LUT P0, PT, P0, P1, PT, 0xf8, 0x8f ?trans2;
SHF.R.U32.HI R9, RZ, 0x1, R3 ?WAIT3_END_GROUP;
SEL R0, RZ, 0x1, !P0 ?WAIT5_END_GROUP;
LOP3.LUT R0, R0, 0x1, R9, 0xf8, !PT ?WAIT4_END_GROUP;
LOP3.LUT R0, R0, R3, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R9, R0, RZ ?WAIT4_END_GROUP;
LOP3.LUT R7, R0, R7, RZ, 0xfc, !PT ?trans1;
BRA 0xac0 ?trans6;
LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ?trans1;
BRA 0xac0 ?trans6;
IMAD R7, R3, 0x800000, R7 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
BRA 0xb60 ?trans5;
LOP3.LUT R0, R3, 0x80000000, R0, 0x48, !PT ?WAIT4_END_GROUP;
LOP3.LUT R7, R0, 0x7f800000, RZ, 0xfc, !PT ?trans1;
BRA 0xb60 ?trans6;
LOP3.LUT R7, R3, 0x80000000, R0, 0x48, !PT ?trans1;
BRA 0xb60 ?trans6;
MUFU.RSQ R7, -QNAN &wr=0x0 ?trans1;
BRA 0xb60 ?trans5;
FADD.FTZ R7, R0, R3 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B1 ?trans5;
MOV R11, R7 &req={0} ?trans1;
MOV R6, R4 ?trans1;
HFMA2 R7, -RZ, RZ, 0, 0 ?WAIT4_END_GROUP;
RET.REL.NODEC R6 0x0 ?trans5;
BRA 0xbb0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: BackwardSubstitution(float*, float*, float*, int)
_Z20BackwardSubstitutionPfS_S_i:
s_clause 0x3
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[10:11], s[0:1], 0x10
v_sub_nc_u32_e32 v1, 0, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s0, s15, s0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, s0, v1
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB2_2
s_ashr_i32 s3, s2, 31
s_add_i32 s1, s2, -1
s_lshl_b64 s[8:9], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_add_u32 s3, s10, s8
s_addc_u32 s13, s11, s9
s_add_u32 s12, s3, -4
s_addc_u32 s13, s13, -1
s_add_i32 s3, s2, 1
s_mul_i32 s16, s1, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s17, s16, 31
s_lshl_b64 s[16:17], s[16:17], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s4, s16
s_addc_u32 s17, s5, s17
s_load_b32 s1, s[12:13], 0x0
s_load_b32 s3, s[16:17], 0x0
s_add_u32 s8, s6, s8
s_addc_u32 s9, s7, s9
s_waitcnt lgkmcnt(0)
v_div_scale_f32 v1, null, s3, s3, s1
v_div_scale_f32 v4, vcc_lo, s1, s3, s1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v2, v1
s_waitcnt_depctr 0xfff
v_fma_f32 v3, -v1, v2, 1.0
v_fmac_f32_e32 v2, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, v4, v2
v_fma_f32 v5, -v1, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, v5, v2
v_fma_f32 v1, -v1, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v1, v1, v2, v3
v_mov_b32_e32 v2, 0
v_div_fixup_f32 v1, v1, s3, s1
global_store_b32 v2, v1, s[8:9] offset:-4
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s0
s_sub_i32 s0, s2, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s8, s0, -2
s_cmp_ge_i32 s8, s2
s_cbranch_scc1 .LBB2_7
v_add_nc_u32_e32 v1, s8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xad_u32 v1, v1, -1, s2
v_cmp_gt_i32_e32 vcc_lo, s2, v1
v_cmp_lt_i32_e64 s0, -1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB2_7
s_ashr_i32 s9, s8, 31
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB2_6
s_lshl_b64 s[12:13], s[8:9], 2
v_mov_b32_e32 v0, 0
s_add_u32 s10, s10, s12
s_addc_u32 s11, s11, s13
global_load_b32 v2, v0, s[10:11]
s_waitcnt vmcnt(0)
ds_store_b32 v0, v2
.LBB2_6:
s_or_b32 exec_lo, exec_lo, s0
v_mad_u64_u32 v[3:4], null, v1, s2, s[8:9]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_add_i32 s0, s2, 1
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_mul_i32 s0, s8, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_ashr_i32 s1, s0, 31
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_lshl_b64 s[0:1], s[0:1], 2
s_add_u32 s0, s4, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v0, v[0:1], off
global_load_b32 v1, v[3:4], off
ds_load_b32 v3, v2
s_addc_u32 s1, s5, s1
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f32 v0, -v1, v0, v3
ds_store_b32 v2, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
global_load_b32 v0, v2, s[0:1]
ds_load_b32 v1, v2
s_lshl_b64 s[0:1], s[8:9], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
s_add_u32 s0, s6, s0
s_addc_u32 s1, s7, s1
s_waitcnt vmcnt(0) lgkmcnt(0)
v_div_scale_f32 v3, null, v0, v0, v1
v_div_scale_f32 v6, vcc_lo, v1, v0, v1
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v4
v_mul_f32_e32 v5, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v3, v5, v6
v_fmac_f32_e32 v5, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v5, v6
v_div_fmas_f32 v3, v3, v4, v5
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v0, v3, v0, v1
global_store_b32 v2, v0, s[0:1]
.LBB2_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| BackwardSubstitution | 4,539 | 2,531 | stackv2-00000-of-00015 |
// Demangled: ForwardSubstitution(float*, float*, float*, int)
Function : _Z19ForwardSubstitutionPfS_S_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
BSSY.RECONVERGENT B0, 0x1c0 ?trans1;
S2R R2, SR_TID.X &wr=0x2 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x3 ?trans1;
IMAD R0, R4, UR4, RZ &req={1} ?trans1;
IADD3 R3, PT, PT, -R2, RZ, RZ &req={2} ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R0, R3, PT ?WAIT13_END_GROUP;
@P0 BRA 0x1b0 &req={3,0} ?trans5;
LDC.64 R8, c[0x0][0x380] &wr=0x0 ?trans2;
LDG.E R3, desc[UR6][R8.64] &req={0} &wr=0x2 ?trans6;
LDC.64 R6, c[0x0][0x390] &wr=0x0 ?trans2;
LDG.E R0, desc[UR6][R6.64] &req={0} &wr=0x3 ?trans1;
MUFU.RCP R10, R3 &req={2} &wr=0x0 ?trans1;
FCHK P0, R0, R3 &req={3} &wr=0x1 ?trans1;
FFMA R11, -R3, R10, 1 &req={0} ?WAIT4_END_GROUP;
FFMA R11, R10, R11, R10 ?WAIT4_END_GROUP;
FFMA R10, R0, R11, RZ ?WAIT4_END_GROUP;
FFMA R12, -R3, R10, R0 ?WAIT4_END_GROUP;
FFMA R11, R11, R12, R10 ?trans1;
@!P0 BRA 0x190 &req={1} ?trans6;
MOV R6, 0x180 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x4f0 ?trans5;
MOV R11, R9 ?WAIT7_END_GROUP;
LDC.64 R6, c[0x0][0x388] &wr=0x0 ?trans2;
STG.E desc[UR6][R6.64], R11 &req={0} &rd=0x0 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
LDC R14, c[0x0][0x398] &wr=0x1 ?trans1;
IADD3 R13, PT, PT, R4, 0x1, RZ ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R13, -R2, RZ ?WAIT5_END_GROUP;
VIMNMX.S32 R3, R13, R0, !PT ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R3, R14, PT &req={1} ?WAIT5_END_GROUP;
ISETP.LT.OR P0, PT, R0, RZ, P0 ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
ISETP.NE.AND P0, PT, R2, RZ, PT ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
LDCU.64 UR8, c[0x0][0x380] &wr=0x2 ?trans7;
LDC.64 R10, c[0x0][0x388] &req={0} &wr=0x0 ?trans8;
@!P0 LDC.64 R2, c[0x0][0x390] &wr=0x3 ?trans2;
@!P0 IMAD.WIDE.U32 R2, R4, 0x4, R2 &req={3} ?WAIT5_END_GROUP;
@!P0 LDG.E R12, desc[UR6][R2.64+0x4] &rd=0x0 &wr=0x3 ?trans1;
UMOV UR4, 0x400 ?trans1;
IMAD R6, R0, R14, RZ ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?trans1;
HFMA2 R5, -RZ, RZ, 0, 0 ?trans1;
MOV R7, RZ ?WAIT5_END_GROUP;
IADD.64 R6, R6, R4 ?trans2;
IMAD.WIDE.U32 R2, R0, 0x4, R10 &req={0} ?WAIT3_END_GROUP;
LEA R8, P1, R6, UR8, 0x2 &req={2} ?WAIT4_END_GROUP;
LEA.HI.X R9, R6, UR9, R7, 0x2, P1 ?trans2;
LDC.64 R6, c[0x0][0x380] &wr=0x0 ?trans1;
@!P0 STS [UR4], R12 &req={3} ?trans7;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDG.E R9, desc[UR6][R8.64+0x4] &wr=0x2 ?trans4;
LDG.E R2, desc[UR6][R2.64] &wr=0x2 ?trans1;
IMAD R13, R13, R14, R13 ?WAIT3_END_GROUP;
LDS R0, [UR4] &wr=0x2 ?trans1;
IMAD.WIDE R6, R13, 0x4, R6 &req={0} ?WAIT4_END_GROUP;
FFMA R10, -R9, R2, R0 &req={2} ?WAIT5_END_GROUP;
STS [UR4], R10 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDG.E R7, desc[UR6][R6.64] &wr=0x2 ?trans4;
LDS R0, [UR4] &wr=0x0 ?trans1;
MUFU.RCP R8, R7 &req={2} &wr=0x1 ?trans1;
FCHK P0, R0, R7 &req={0} &wr=0x0 ?trans1;
FFMA R3, -R7, R8, 1 &req={1} ?WAIT4_END_GROUP;
FFMA R3, R8, R3, R8 ?WAIT4_END_GROUP;
FFMA R2, R0, R3, RZ ?WAIT4_END_GROUP;
FFMA R8, -R7, R2, R0 ?WAIT4_END_GROUP;
FFMA R9, R3, R8, R2 ?trans1;
@!P0 BRA 0x4b0 &req={0} ?trans6;
MOV R3, R7 ?trans1;
MOV R6, 0x4b0 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x4f0 ?trans5;
LDC.64 R2, c[0x0][0x388] &wr=0x0 ?trans2;
IMAD.WIDE.U32 R4, R4, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R4.64+0x4], R9 ?trans1;
EXIT ?trans5;
SHF.R.U32.HI R8, RZ, 0x17, R3 ?trans1;
BSSY.RECONVERGENT B1, 0xb30 ?trans1;
SHF.R.U32.HI R7, RZ, 0x17, R0 ?trans2;
LOP3.LUT R12, R8, 0xff, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R10, R7, 0xff, RZ, 0xc0, !PT ?trans2;
IADD3 R9, PT, PT, R12, -0x1, RZ ?trans2;
IADD3 R8, PT, PT, R10, -0x1, RZ ?WAIT3_END_GROUP;
ISETP.GT.U32.AND P0, PT, R9, 0xfd, PT ?WAIT5_END_GROUP;
ISETP.GT.U32.OR P0, PT, R8, 0xfd, P0 ?WAIT13_END_GROUP;
@!P0 MOV R7, RZ ?trans1;
@!P0 BRA 0x710 ?trans6;
FSETP.GTU.FTZ.AND P0, PT, |R0|, +INF , PT ?trans1;
FSETP.GTU.FTZ.AND P1, PT, |R3|, +INF , PT ?WAIT5_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, PT, 0xf8, 0x8f ?WAIT13_END_GROUP;
@P0 BRA 0xb10 ?trans5;
LOP3.LUT P0, RZ, R3, 0x7fffffff, R0, 0xc8, !PT ?WAIT13_END_GROUP;
@!P0 BRA 0xaf0 ?trans5;
FSETP.NEU.FTZ.AND P2, PT, |R0|.reuse, +INF , PT ?trans1;
FSETP.NEU.FTZ.AND P1, PT, |R3|, +INF , PT ?trans1;
FSETP.NEU.FTZ.AND P0, PT, |R0|, +INF , PT ?WAIT12_END_GROUP;
@!P1 BRA !P2, 0xaf0 ?trans5;
LOP3.LUT P2, RZ, R0, 0x7fffffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P1, PT, P1, P2, PT, 0x2f, 0xf2 ?WAIT13_END_GROUP;
@P1 BRA 0xad0 ?trans5;
LOP3.LUT P1, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, PT, 0x2f, 0xf2 ?WAIT13_END_GROUP;
@P0 BRA 0xaa0 ?trans5;
ISETP.GE.AND P0, PT, R8, RZ, PT ?trans1;
ISETP.GE.AND P1, PT, R9, RZ, PT ?WAIT12_END_GROUP;
@P0 MOV R7, RZ ?trans1;
@!P0 MOV R7, 0xffffffc0 ?trans1;
@!P0 FFMA R0, R0, 1.84467440737095516160e+19, RZ ?trans1;
@!P1 FFMA R3, R3, 1.84467440737095516160e+19, RZ ?WAIT3_END_GROUP;
@!P1 IADD3 R7, PT, PT, R7, 0x40, RZ ?WAIT7_END_GROUP;
LEA R8, R12, 0xc0800000, 0x17 ?trans1;
BSSY.RECONVERGENT B2, 0xa90 ?trans3;
IADD3 R8, PT, PT, -R8, R3, RZ ?trans2;
IADD3 R3, PT, PT, R10, -0x7f, RZ ?trans2;
MUFU.RCP R9, R8 &rd=0x0 &wr=0x1 ?trans1;
FADD.FTZ R11, -R8, -RZ ?trans2;
IMAD R0, R3.reuse, -0x800000, R0 ?trans1;
IADD3 R8, PT, PT, R3, 0x7f, -R12 &req={0} ?WAIT4_END_GROUP;
IADD3 R8, PT, PT, R8, R7, RZ ?trans1;
FFMA R10, R9, R11, 1 &req={1} ?WAIT4_END_GROUP;
FFMA R14, R9, R10, R9 ?WAIT4_END_GROUP;
FFMA R9, R0, R14, RZ ?WAIT4_END_GROUP;
FFMA R10, R11, R9, R0 ?WAIT4_END_GROUP;
FFMA R13, R14, R10, R9 ?WAIT4_END_GROUP;
FFMA R10, R11, R13, R0 ?WAIT4_END_GROUP;
FFMA R9, R14, R10, R13 ?WAIT5_END_GROUP;
SHF.R.U32.HI R0, RZ, 0x17, R9 ?WAIT4_END_GROUP;
LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R11, PT, PT, R0, R8, RZ ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R11, -0x1, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R0, 0xfe, PT ?WAIT13_END_GROUP;
@!P0 BRA 0xa70 ?trans5;
ISETP.GT.AND P0, PT, R11, 0xfe, PT ?WAIT13_END_GROUP;
@P0 BRA 0xa40 ?trans5;
ISETP.GE.AND P0, PT, R11, 0x1, PT ?WAIT13_END_GROUP;
@P0 BRA 0xa80 ?trans5;
ISETP.GE.AND P0, PT, R11, -0x18, PT ?trans1;
LOP3.LUT R9, R9, 0x80000000, RZ, 0xc0, !PT ?WAIT12_END_GROUP;
@!P0 BRA 0xa80 ?trans5;
FFMA.RZ R0, R14.reuse, R10.reuse, R13.reuse ?trans1;
IADD3 R8, PT, PT, R11.reuse, 0x20, RZ ?trans1;
FFMA.RM R3, R14, R10, R13 ?trans1;
ISETP.NE.AND P1, PT, R11.reuse, RZ, PT ?trans1;
ISETP.NE.AND P2, PT, R11, RZ, PT ?trans1;
LOP3.LUT R0, R0, 0x7fffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
LOP3.LUT R7, R0, 0x800000, RZ, 0xfc, !PT ?trans1;
FFMA.RP R0, R14, R10, R13 ?trans1;
IADD3 R10, PT, PT, -R11, RZ, RZ ?trans2;
SHF.L.U32 R8, R7, R8, RZ ?trans2;
FSETP.NEU.FTZ.AND P0, PT, R0, R3, PT ?trans1;
SEL R0, R10, RZ, P2 ?trans2;
ISETP.NE.AND P1, PT, R8, RZ, P1 ?WAIT3_END_GROUP;
SHF.R.U32.HI R0, RZ, R0, R7 ?trans2;
PLOP3.LUT P0, PT, P0, P1, PT, 0xf8, 0x8f ?trans2;
SHF.R.U32.HI R8, RZ, 0x1, R0 ?WAIT3_END_GROUP;
SEL R3, RZ, 0x1, !P0 ?WAIT5_END_GROUP;
LOP3.LUT R3, R3, 0x1, R8, 0xf8, !PT ?WAIT4_END_GROUP;
LOP3.LUT R3, R3, R0, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R8, PT, PT, R8, R3, RZ ?WAIT4_END_GROUP;
LOP3.LUT R9, R8, R9, RZ, 0xfc, !PT ?trans1;
BRA 0xa80 ?trans6;
LOP3.LUT R9, R9, 0x80000000, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
LOP3.LUT R9, R9, 0x7f800000, RZ, 0xfc, !PT ?trans1;
BRA 0xa80 ?trans6;
IMAD R9, R8, 0x800000, R9 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
BRA 0xb20 ?trans5;
LOP3.LUT R0, R3, 0x80000000, R0, 0x48, !PT ?WAIT4_END_GROUP;
LOP3.LUT R9, R0, 0x7f800000, RZ, 0xfc, !PT ?trans1;
BRA 0xb20 ?trans6;
LOP3.LUT R9, R3, 0x80000000, R0, 0x48, !PT ?trans1;
BRA 0xb20 ?trans6;
MUFU.RSQ R9, -QNAN &wr=0x0 ?trans1;
BRA 0xb20 ?trans5;
FADD.FTZ R9, R0, R3 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B1 ?trans5;
HFMA2 R7, -RZ, RZ, 0, 0 ?WAIT4_END_GROUP;
RET.REL.NODEC R6 0x0 &req={0} ?trans5;
BRA 0xb50;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: ForwardSubstitution(float*, float*, float*, int)
_Z19ForwardSubstitutionPfS_S_i:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[10:11], s[0:1], 0x10
v_sub_nc_u32_e32 v1, 0, v0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s3, s15, s3
v_cmp_eq_u32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB1_2
s_load_b32 s8, s[10:11], 0x0
s_load_b32 s9, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_div_scale_f32 v1, null, s9, s9, s8
v_div_scale_f32 v4, vcc_lo, s8, s9, s8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v2, v1
s_waitcnt_depctr 0xfff
v_fma_f32 v3, -v1, v2, 1.0
v_fmac_f32_e32 v2, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, v4, v2
v_fma_f32 v5, -v1, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, v5, v2
v_fma_f32 v1, -v1, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v1, v1, v2, v3
v_mov_b32_e32 v2, 0
v_div_fixup_f32 v1, v1, s9, s8
global_store_b32 v2, v1, s[6:7]
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s3
s_load_b32 s1, s[0:1], 0x18
s_add_i32 s8, s2, 1
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s8, s1
s_cbranch_scc1 .LBB1_7
v_sub_nc_u32_e32 v1, s8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s1, v1
v_cmp_lt_i32_e64 s0, -1, v1
s_and_b32 s0, s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s0
s_cbranch_execz .LBB1_7
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_6
s_ashr_i32 s3, s2, 31
v_mov_b32_e32 v0, 0
s_lshl_b64 s[12:13], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s10, s10, s12
s_addc_u32 s11, s11, s13
global_load_b32 v2, v0, s[10:11] offset:4
s_waitcnt vmcnt(0)
ds_store_b32 v0, v2
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s0
v_mad_u64_u32 v[3:4], null, v1, s1, s[8:9]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_add_i32 s0, s1, 1
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_mul_i32 s0, s0, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_ashr_i32 s1, s0, 31
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_lshl_b64 s[0:1], s[0:1], 2
s_add_u32 s0, s4, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v0, v[0:1], off
global_load_b32 v1, v[3:4], off
ds_load_b32 v3, v2
s_addc_u32 s1, s5, s1
s_ashr_i32 s3, s2, 31
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f32 v0, -v1, v0, v3
ds_store_b32 v2, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
global_load_b32 v0, v2, s[0:1]
ds_load_b32 v1, v2
s_lshl_b64 s[0:1], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
s_add_u32 s0, s6, s0
s_addc_u32 s1, s7, s1
s_waitcnt vmcnt(0) lgkmcnt(0)
v_div_scale_f32 v3, null, v0, v0, v1
v_div_scale_f32 v6, vcc_lo, v1, v0, v1
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v4
v_mul_f32_e32 v5, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v3, v5, v6
v_fmac_f32_e32 v5, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v5, v6
v_div_fmas_f32 v3, v3, v4, v5
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v0, v3, v0, v1
global_store_b32 v2, v0, s[0:1] offset:4
.LBB1_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| ForwardSubstitution | 4,452 | 2,165 | stackv2-00000-of-00015 |
// Demangled: RowOperations(float*, float*, int, int)
Function : _Z13RowOperationsPfS_ii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R11, SR_TID.X &wr=0x1 ?trans7;
S2UR UR5, SR_CTAID.X &wr=0x2 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x2 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x3 ?trans6;
LDC.64 R12, c[0x0][0x390] &wr=0x4 ?trans1;
UIMAD UR4, UR5, UR4, URZ &req={2} ?trans1;
IADD3 R0, PT, PT, -R11, RZ, RZ &req={1} ?WAIT2_END_GROUP;
IADD3.X R5, PT, PT, R12, UR5, RZ, PT, !PT &req={4} ?trans2;
IADD3 R2, PT, PT, R11, R12, RZ ?trans1;
ISETP.NE.AND P0, PT, R0, UR4, PT ?WAIT4_END_GROUP;
VIMNMX.S32 R0, R5, R2, !PT ?WAIT5_END_GROUP;
ISETP.GE.AND P1, PT, R0, R13, PT ?WAIT4_END_GROUP;
@!P0 LDC.64 R6, c[0x0][0x380] &wr=0x1 ?trans1;
@!P0 IMAD R3, R12, R13, R12 ?WAIT4_END_GROUP;
@!P0 IMAD.WIDE R6, R3, 0x4, R6 &req={1} ?trans1;
@!P0 MOV R3, 0x3f800000 ?WAIT5_END_GROUP;
@!P0 STG.E desc[UR6][R6.64], R3 &req={3} &rd=0x1 ?trans1;
@P1 EXIT &req={0} ?trans5;
LDC.64 R8, c[0x0][0x388] &wr=0x0 ?trans1;
ISETP.NE.AND P0, PT, R11, RZ, PT ?trans1;
IMAD R13, R12, R13, R12 ?trans1;
BSSY.RECONVERGENT B0, 0x2d0 ?trans3;
IMAD.WIDE R8, R13, 0x4, R8 &req={0} ?WAIT8_END_GROUP;
@P0 BRA 0x2c0 ?trans5;
LDG.E R3, desc[UR6][R8.64] &req={1} &wr=0x2 ?trans1;
UMOV UR4, 0x3f800000 ?trans2;
MOV R6, UR4 ?trans1;
MUFU.RCP R0, R3 &req={2} &wr=0x0 ?trans3;
FCHK P0, -R6, R3 &wr=0x1 ?trans1;
FFMA R7, -R3, R0, 1 &req={0} ?WAIT4_END_GROUP;
FFMA R0, R0, R7, R0 ?WAIT4_END_GROUP;
FFMA R4, R0, -1, RZ ?WAIT4_END_GROUP;
FFMA R7, -R3, R4, -1 ?WAIT4_END_GROUP;
FFMA R0, R0, R7, R4 ?trans1;
@!P0 BRA 0x280 &req={1} ?trans6;
HFMA2 R0, -RZ, RZ, -1.875, 0 ?trans1;
MOV R10, 0x270 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x520 ?trans5;
MOV R0, R13 ?WAIT7_END_GROUP;
S2UR UR5, SR_CgaCtaId &wr=0x0 ?trans1;
UMOV UR4, 0x400 ?trans2;
ULEA UR4, UR5, UR4, 0x18 &req={0} ?WAIT9_END_GROUP;
STS [UR4], R0 &rd=0x0 ?trans3;
BSYNC.RECONVERGENT B0 ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans8;
LDC.64 R10, c[0x0][0x390] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x388] &req={1} &wr=0x1 ?trans1;
LDG.E R3, desc[UR6][R8.64] &wr=0x3 ?trans1;
IMAD R4, R10, R11, R5 &req={2} ?WAIT4_END_GROUP;
IMAD.WIDE R6, R4, 0x4, R6 &req={1} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR6][R6.64] &req={0} &wr=0x2 ?trans1;
MUFU.RCP R10, R3 &req={3} &wr=0x0 ?trans2;
FFMA R11, -R3, R10, 1 &req={0} ?trans1;
FCHK P0, R0, R3 &req={2} &wr=0x0 ?trans3;
FFMA R11, R10, R11, R10 ?WAIT4_END_GROUP;
FFMA R10, R0, R11, RZ ?WAIT4_END_GROUP;
FFMA R12, -R3, R10, R0 ?WAIT4_END_GROUP;
FFMA R13, R11, R12, R10 ?trans1;
@!P0 BRA 0x3e0 &req={0} ?trans6;
MOV R10, 0x3e0 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x520 ?trans5;
LDC.64 R8, c[0x0][0x380] &wr=0x0 ?trans8;
LDC.64 R16, c[0x0][0x390] &wr=0x1 ?trans8;
LDC.64 R10, c[0x0][0x388] &wr=0x2 ?trans1;
IMAD.WIDE R8, R4, 0x4, R8 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R8.64], R13 ?trans1;
IMAD R15, R2, R17, R16 &req={1} ?WAIT3_END_GROUP;
LDG.E R7, desc[UR6][R6.64] &wr=0x3 ?trans1;
IMAD R3, R2, R17, R5 ?trans2;
IMAD.WIDE R4, R15, 0x4, R10 &req={2} ?WAIT4_END_GROUP;
IMAD.WIDE R2, R3, 0x4, R10 ?trans2;
LDG.E R4, desc[UR6][R4.64] &wr=0x2 ?trans4;
LDG.E R0, desc[UR6][R2.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x0 ?trans1;
UMOV UR4, 0x400 ?trans2;
ULEA UR4, UR5, UR4, 0x18 &req={0} ?WAIT9_END_GROUP;
LDS R10, [UR4] &wr=0x3 ?trans2;
FMUL R11, R10, R7 &req={3} ?WAIT4_END_GROUP;
FFMA R11, R11, R4, R0 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R11 ?trans1;
EXIT ?trans5;
SHF.R.U32.HI R12, RZ, 0x17, R3 ?trans1;
BSSY.RECONVERGENT B1, 0xb60 ?trans1;
SHF.R.U32.HI R11, RZ, 0x17, R0 ?trans2;
LOP3.LUT R16, R12, 0xff, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R14, R11, 0xff, RZ, 0xc0, !PT ?trans2;
IADD3 R13, PT, PT, R16, -0x1, RZ ?trans2;
IADD3 R12, PT, PT, R14, -0x1, RZ ?WAIT3_END_GROUP;
ISETP.GT.U32.AND P0, PT, R13, 0xfd, PT ?WAIT5_END_GROUP;
ISETP.GT.U32.OR P0, PT, R12, 0xfd, P0 ?WAIT13_END_GROUP;
@!P0 MOV R11, RZ ?trans1;
@!P0 BRA 0x740 ?trans6;
FSETP.GTU.FTZ.AND P0, PT, |R0|, +INF , PT ?trans1;
FSETP.GTU.FTZ.AND P1, PT, |R3|, +INF , PT ?WAIT5_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, PT, 0xf8, 0x8f ?WAIT13_END_GROUP;
@P0 BRA 0xb40 ?trans5;
LOP3.LUT P0, RZ, R3, 0x7fffffff, R0, 0xc8, !PT ?WAIT13_END_GROUP;
@!P0 BRA 0xb20 ?trans5;
FSETP.NEU.FTZ.AND P2, PT, |R0|.reuse, +INF , PT ?trans1;
FSETP.NEU.FTZ.AND P1, PT, |R3|, +INF , PT ?trans1;
FSETP.NEU.FTZ.AND P0, PT, |R0|, +INF , PT ?WAIT12_END_GROUP;
@!P1 BRA !P2, 0xb20 ?trans5;
LOP3.LUT P2, RZ, R0, 0x7fffffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P1, PT, P1, P2, PT, 0x2f, 0xf2 ?WAIT13_END_GROUP;
@P1 BRA 0xb00 ?trans5;
LOP3.LUT P1, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, PT, 0x2f, 0xf2 ?WAIT13_END_GROUP;
@P0 BRA 0xad0 ?trans5;
ISETP.GE.AND P0, PT, R12, RZ, PT ?trans1;
ISETP.GE.AND P1, PT, R13, RZ, PT ?WAIT12_END_GROUP;
@P0 MOV R11, RZ ?trans1;
@!P0 MOV R11, 0xffffffc0 ?trans1;
@!P0 FFMA R0, R0, 1.84467440737095516160e+19, RZ ?trans1;
@!P1 FFMA R3, R3, 1.84467440737095516160e+19, RZ ?WAIT3_END_GROUP;
@!P1 IADD3 R11, PT, PT, R11, 0x40, RZ ?WAIT7_END_GROUP;
LEA R12, R16, 0xc0800000, 0x17 ?trans1;
BSSY.RECONVERGENT B2, 0xac0 ?trans3;
IADD3 R12, PT, PT, -R12, R3, RZ ?trans2;
IADD3 R3, PT, PT, R14, -0x7f, RZ ?trans2;
MUFU.RCP R13, R12 &rd=0x0 &wr=0x1 ?trans1;
FADD.FTZ R15, -R12, -RZ ?trans2;
IMAD R0, R3.reuse, -0x800000, R0 ?trans1;
IADD3 R12, PT, PT, R3, 0x7f, -R16 &req={0} ?WAIT4_END_GROUP;
IADD3 R12, PT, PT, R12, R11, RZ ?trans1;
FFMA R14, R13, R15, 1 &req={1} ?WAIT4_END_GROUP;
FFMA R18, R13, R14, R13 ?WAIT4_END_GROUP;
FFMA R13, R0, R18, RZ ?WAIT4_END_GROUP;
FFMA R14, R15, R13, R0 ?WAIT4_END_GROUP;
FFMA R17, R18, R14, R13 ?WAIT4_END_GROUP;
FFMA R14, R15, R17, R0 ?WAIT4_END_GROUP;
FFMA R13, R18, R14, R17 ?WAIT5_END_GROUP;
SHF.R.U32.HI R0, RZ, 0x17, R13 ?WAIT4_END_GROUP;
LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R15, PT, PT, R0, R12, RZ ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R15, -0x1, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R0, 0xfe, PT ?WAIT13_END_GROUP;
@!P0 BRA 0xaa0 ?trans5;
ISETP.GT.AND P0, PT, R15, 0xfe, PT ?WAIT13_END_GROUP;
@P0 BRA 0xa70 ?trans5;
ISETP.GE.AND P0, PT, R15, 0x1, PT ?WAIT13_END_GROUP;
@P0 BRA 0xab0 ?trans5;
ISETP.GE.AND P0, PT, R15, -0x18, PT ?trans1;
LOP3.LUT R13, R13, 0x80000000, RZ, 0xc0, !PT ?WAIT12_END_GROUP;
@!P0 BRA 0xab0 ?trans5;
FFMA.RZ R0, R18.reuse, R14.reuse, R17.reuse ?trans1;
IADD3 R12, PT, PT, R15.reuse, 0x20, RZ ?trans1;
FFMA.RM R3, R18, R14, R17 ?trans1;
ISETP.NE.AND P1, PT, R15.reuse, RZ, PT ?trans1;
ISETP.NE.AND P2, PT, R15, RZ, PT ?trans1;
LOP3.LUT R0, R0, 0x7fffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
LOP3.LUT R11, R0, 0x800000, RZ, 0xfc, !PT ?trans1;
FFMA.RP R0, R18, R14, R17 ?trans1;
IADD3 R14, PT, PT, -R15, RZ, RZ ?trans2;
SHF.L.U32 R12, R11, R12, RZ ?trans2;
FSETP.NEU.FTZ.AND P0, PT, R0, R3, PT ?trans1;
SEL R0, R14, RZ, P2 ?trans2;
ISETP.NE.AND P1, PT, R12, RZ, P1 ?WAIT3_END_GROUP;
SHF.R.U32.HI R0, RZ, R0, R11 ?trans2;
PLOP3.LUT P0, PT, P0, P1, PT, 0xf8, 0x8f ?trans2;
SHF.R.U32.HI R12, RZ, 0x1, R0 ?WAIT3_END_GROUP;
SEL R3, RZ, 0x1, !P0 ?WAIT5_END_GROUP;
LOP3.LUT R3, R3, 0x1, R12, 0xf8, !PT ?WAIT4_END_GROUP;
LOP3.LUT R3, R3, R0, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R12, PT, PT, R12, R3, RZ ?WAIT4_END_GROUP;
LOP3.LUT R13, R12, R13, RZ, 0xfc, !PT ?trans1;
BRA 0xab0 ?trans6;
LOP3.LUT R13, R13, 0x80000000, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
LOP3.LUT R13, R13, 0x7f800000, RZ, 0xfc, !PT ?trans1;
BRA 0xab0 ?trans6;
IMAD R13, R12, 0x800000, R13 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
BRA 0xb50 ?trans5;
LOP3.LUT R0, R3, 0x80000000, R0, 0x48, !PT ?WAIT4_END_GROUP;
LOP3.LUT R13, R0, 0x7f800000, RZ, 0xfc, !PT ?trans1;
BRA 0xb50 ?trans6;
LOP3.LUT R13, R3, 0x80000000, R0, 0x48, !PT ?trans1;
BRA 0xb50 ?trans6;
MUFU.RSQ R13, -QNAN &wr=0x0 ?trans1;
BRA 0xb50 ?trans5;
FADD.FTZ R13, R0, R3 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B1 ?trans5;
HFMA2 R11, -RZ, RZ, 0, 0 ?WAIT4_END_GROUP;
RET.REL.NODEC R10 0x0 &req={0} ?trans5;
BRA 0xb80;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: RowOperations(float*, float*, int, int)
_Z13RowOperationsPfS_ii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_sub_nc_u32_e32 v1, 0, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s2, s15, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_add_i32 s3, s1, 1
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 1.0
s_mul_i32 s8, s3, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s9, s8, 31
s_lshl_b64 s[8:9], s[8:9], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s8, s4, s8
s_addc_u32 s9, s5, s9
global_store_b32 v1, v2, s[8:9]
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v1, s0, v0
s_add_i32 s2, s15, s0
s_mov_b32 s3, exec_lo
s_add_i32 s2, s2, 1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_max_i32_e32 v2, s2, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s1, v2
s_cbranch_execz .LBB0_6
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_5
s_add_i32 s8, s1, 1
v_mov_b32_e32 v0, 0
s_mul_i32 s8, s8, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s9, s8, 31
s_lshl_b64 s[8:9], s[8:9], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
s_add_u32 s8, s6, s8
s_addc_u32 s9, s7, s9
global_load_b32 v2, v0, s[8:9]
s_waitcnt vmcnt(0)
v_div_scale_f32 v3, null, v2, v2, -1.0
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v4
v_div_scale_f32 v5, vcc_lo, -1.0, v2, -1.0
v_mul_f32_e32 v6, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v3, v6, v5
v_fmac_f32_e32 v6, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v6, v5
v_div_fmas_f32 v3, v3, v4, v6
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v2, v3, v2, -1.0
ds_store_b32 v0, v2
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s3
s_mul_i32 s3, s1, s0
v_mov_b32_e32 v4, 0
s_add_i32 s8, s3, s2
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_ashr_i32 s9, s8, 31
s_barrier
s_lshl_b64 s[8:9], s[8:9], 2
buffer_gl0_inv
s_add_u32 s10, s6, s8
s_addc_u32 s11, s7, s9
s_add_i32 s12, s3, s0
v_mul_lo_u32 v1, v1, s1
s_ashr_i32 s13, s12, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[12:13], s[12:13], 2
s_add_u32 s12, s6, s12
s_addc_u32 s13, s7, s13
s_clause 0x1
global_load_b32 v5, v4, s[12:13]
global_load_b32 v6, v4, s[10:11]
v_add_nc_u32_e32 v2, s2, v1
s_waitcnt vmcnt(0)
v_div_scale_f32 v8, null, v5, v5, v6
v_div_scale_f32 v10, vcc_lo, v6, v5, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v9, v8
s_waitcnt_depctr 0xfff
v_fma_f32 v0, -v8, v9, 1.0
v_fmac_f32_e32 v9, v0, v9
v_add_nc_u32_e32 v0, s0, v1
s_add_u32 s0, s4, s8
s_addc_u32 s1, s5, s9
ds_load_b32 v7, v4
v_mul_f32_e32 v11, v10, v9
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v3, -v8, v11, v10
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v11, v3, v9
v_ashrrev_i32_e32 v3, 31, v2
v_fma_f32 v8, -v8, v11, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_div_fmas_f32 v8, v8, v9, v11
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_div_fixup_f32 v5, v8, v5, v6
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_store_b32 v4, v5, s[0:1]
s_clause 0x2
global_load_b32 v0, v[0:1], off
global_load_b32 v1, v4, s[10:11]
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(1) lgkmcnt(0)
v_mul_f32_e32 v1, v7, v1
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v4, v1, v0
global_store_b32 v[2:3], v4, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| RowOperations | 4,587 | 2,346 | stackv2-00000-of-00015 |
// Demangled: mallocTest()
Function : _Z10mallocTestv
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R2, SR_TID.X &wr=0x1 ?trans2;
ISETP.NE.AND P0, PT, R2, RZ, PT &req={1} ?WAIT13_END_GROUP;
@P0 BRA 0x100 ?trans5;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
MOV R6, 0x0 ?trans1;
HFMA2 R5, -RZ, RZ, 0, 0 ?WAIT5_END_GROUP;
LDC.64 R6, c[0x4][R6] &wr=0x2 ?trans1;
USHF.L.U32 UR4, UR4, 0x8, URZ &req={1} ?WAIT6_END_GROUP;
MOV R4, UR4 ?WAIT7_END_GROUP;
LEPC R20, 0xc0 ?WAIT7_END_GROUP;
CALL.ABS.NOINC R6 &req={2,0} ?trans5;
S2UR UR5, SR_CgaCtaId &wr=0x0 ?trans1;
UMOV UR4, 0x400 ?trans2;
ULEA UR4, UR5, UR4, 0x18 &req={0} ?WAIT9_END_GROUP;
STS.64 [UR4], R4 &rd=0x1 ?trans3;
WARPSYNC.ALL ?trans5;
NOP ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x2 ?trans8;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
UMOV UR4, 0x400 ?WAIT2_END_GROUP;
ULEA UR4, UR5, UR4, 0x18 &req={2} ?WAIT9_END_GROUP;
LDS.64 R22, [UR4] &wr=0x2 ?trans2;
ISETP.NE.S64.AND P0, PT, R22, RZ, PT &req={2} ?WAIT14_END_GROUP;
@!P0 EXIT ?trans5;
LDC R7, c[0x0][0x360] &wr=0x2 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x3 ?trans1;
IMAD.WIDE.U32 R28, R2.reuse, 0x4, R22 ?trans1;
ISETP.NE.AND P0, PT, R2, RZ, PT ?WAIT4_END_GROUP;
ST.E desc[UR6][R28.64], R2 &req={3} ?trans1;
IADD3 R0, PT, PT, R7.reuse, R7, R2 &req={2} ?trans1;
IMAD.WIDE R24, R7, 0x4, R28 ?WAIT3_END_GROUP;
IADD3 R0, PT, PT, R7.reuse, R0, R7 ?trans2;
ST.E desc[UR6][R24.64], R2 &rd=0x2 ?trans1;
IMAD.WIDE R26, R7.reuse, 0x4, R24 ?trans1;
IADD3 R3, PT, PT, R7, R0, R7 ?WAIT4_END_GROUP;
ST.E desc[UR6][R26.64], R2 &rd=0x3 ?trans1;
IADD3 R21, PT, PT, R3, R7, RZ ?trans1;
IMAD.WIDE R30, R7, 0x4, R26 ?WAIT3_END_GROUP;
IADD3 R8, PT, PT, R21, R7.reuse, RZ ?trans2;
ST.E desc[UR6][R30.64], R2 ?trans1;
IMAD.WIDE R32, R7, 0x4, R30 ?trans1;
IADD3 R16, PT, PT, R8, R7, RZ ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R24, R3, 0x4, R22 &req={2} ?trans1;
ST.E desc[UR6][R32.64], R2 &rd=0x2 ?trans1;
IADD3 R19, PT, PT, R16, R7.reuse, RZ ?trans2;
IMAD.WIDE R34, R7, 0x4, R32 ?trans2;
IADD3 R17, PT, PT, R19, R7.reuse, RZ ?trans2;
IMAD.WIDE.U32 R26, R21, 0x4, R22 &req={3} ?trans1;
ST.E desc[UR6][R34.64], R2 &rd=0x3 ?trans1;
IADD3 R14, PT, PT, R17, R7, RZ ?WAIT3_END_GROUP;
ST.E desc[UR6][R24.64], R2 &rd=0x4 ?trans1;
IMAD.WIDE.U32 R32, R16, 0x4, R22.reuse &req={2} ?trans1;
IADD3 R5, PT, PT, R14, R7.reuse, RZ &req={1} ?trans2;
ST.E desc[UR6][R26.64], R2 &rd=0x1 ?trans1;
IMAD.WIDE.U32 R16, R17, 0x4, R22 ?trans1;
IADD3 R15, PT, PT, R5, R7, RZ ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R34, R19, 0x4, R22 &req={3} ?trans1;
IADD3 R13, PT, PT, R15, R7, RZ ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R24, R8, 0x4, R22 &req={4} ?trans1;
IADD3 R0, PT, PT, R13, R7, RZ ?WAIT4_END_GROUP;
ST.E desc[UR6][R24.64], R2 ?trans1;
IMAD.WIDE.U32 R26, R14, 0x4, R22.reuse &req={1} ?trans1;
IADD3 R9, PT, PT, R0, R7.reuse, RZ ?trans2;
ST.E desc[UR6][R32.64], R2 &rd=0x1 ?trans1;
IMAD.WIDE.U32 R14, R15, 0x4, R22 ?trans1;
IADD3 R12, PT, PT, R9, R7.reuse, RZ ?trans2;
ST.E desc[UR6][R34.64], R2 ?trans2;
IADD3 R11, PT, PT, R12, R7, RZ ?WAIT2_END_GROUP;
ST.E desc[UR6][R16.64], R2 &rd=0x2 ?trans1;
IMAD.WIDE.U32 R32, R13, 0x4, R22.reuse &req={1} ?trans1;
IADD3 R18, PT, PT, R11, R7.reuse, RZ ?trans2;
ST.E desc[UR6][R26.64], R2 &rd=0x1 ?trans1;
IMAD.WIDE.U32 R12, R12, 0x4, R22 ?trans1;
IADD3 R10, PT, PT, R18, R7, RZ ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R16, R5, 0x4, R22 &req={2} ?trans1;
IADD3 R37, PT, PT, R10, R7, RZ ?WAIT4_END_GROUP;
ST.E desc[UR6][R16.64], R2 &rd=0x2 ?trans1;
IMAD.WIDE.U32 R26, R9, 0x4, R22.reuse &req={1} ?trans1;
IADD3 R6, PT, PT, R37, R7.reuse, RZ ?trans2;
ST.E desc[UR6][R14.64], R2 &rd=0x1 ?trans2;
IADD3 R4, PT, PT, R6, R7.reuse, RZ ?trans2;
ST.E desc[UR6][R32.64], R2 &rd=0x3 ?trans2;
IADD3 R20, PT, PT, R4, R7, RZ ?trans1;
IMAD.WIDE.U32 R16, R11, 0x4, R22 &req={2} ?WAIT3_END_GROUP;
IADD3 R36, PT, PT, R20, R7, RZ ?trans1;
IMAD.WIDE.U32 R14, R0, 0x4, R22 &req={1} ?WAIT3_END_GROUP;
IADD3 R28, PT, PT, R36, R7.reuse, RZ ?trans2;
ST.E desc[UR6][R14.64], R2 &rd=0x1 ?trans1;
IMAD.WIDE.U32 R10, R10, 0x4, R22.reuse ?trans1;
IADD3 R29, PT, PT, R28, R7.reuse, RZ ?trans2;
ST.E desc[UR6][R26.64], R2 ?trans1;
IMAD.WIDE.U32 R32, R6, 0x4, R22.reuse &req={3} ?trans1;
IADD3 R30, PT, PT, R29, R7.reuse, RZ ?trans2;
ST.E desc[UR6][R12.64], R2 &rd=0x2 ?trans1;
IMAD.WIDE.U32 R14, R37, 0x4, R22 &req={1} ?trans1;
IADD3 R31, PT, PT, R30, R7, RZ ?WAIT2_END_GROUP;
ST.E desc[UR6][R16.64], R2 &rd=0x1 ?trans2;
IADD3 R3, PT, PT, R31, R7, RZ ?trans1;
IMAD.WIDE.U32 R12, R18, 0x4, R22 &req={2} ?WAIT3_END_GROUP;
IADD3 R21, PT, PT, R3, R7.reuse, RZ ?trans2;
ST.E desc[UR6][R12.64], R2 &rd=0x2 ?trans1;
IMAD.WIDE.U32 R16, R36, 0x4, R22.reuse &req={1} ?trans1;
IADD3 R8, PT, PT, R21, R7.reuse, RZ ?trans2;
ST.E desc[UR6][R10.64], R2 &rd=0x1 ?trans2;
IADD3 R24, PT, PT, R8, R7.reuse, RZ ?trans2;
ST.E desc[UR6][R14.64], R2 &rd=0x3 ?trans2;
IADD3 R19, PT, PT, R24, R7.reuse, RZ ?trans1;
IMAD.WIDE.U32 R12, R20, 0x4, R22.reuse &req={2} ?trans1;
ST.E desc[UR6][R32.64], R2 &rd=0x2 ?trans2;
IADD3 R25, PT, PT, R19, R7, RZ ?trans1;
IMAD.WIDE.U32 R10, R4, 0x4, R22 &req={1} ?WAIT3_END_GROUP;
IADD3 R34, PT, PT, R25, R7.reuse, RZ ?trans2;
ST.E desc[UR6][R10.64], R2 &rd=0x1 ?trans1;
IMAD.WIDE.U32 R14, R29, 0x4, R22.reuse &req={3} ?trans1;
IADD3 R5, PT, PT, R34, R7.reuse, RZ ?trans2;
ST.E desc[UR6][R12.64], R2 &rd=0x3 ?trans1;
IMAD.WIDE.U32 R32, R8, 0x4, R22.reuse &req={2} ?trans1;
IADD3 R35, PT, PT, R5, R7.reuse, RZ ?trans2;
ST.E desc[UR6][R16.64], R2 &rd=0x2 ?trans1;
IMAD.WIDE.U32 R10, R28, 0x4, R22 &req={1} ?trans1;
IADD3 R0, PT, PT, R35, R7, RZ ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R28, R30, 0x4, R22.reuse ?trans1;
ST.E desc[UR6][R10.64], R2 ?trans1;
IADD3 R9, PT, PT, R0, R7.reuse, RZ ?trans2;
IMAD.WIDE.U32 R12, R3, 0x4, R22.reuse &req={3} ?trans1;
ST.E desc[UR6][R14.64], R2 &rd=0x1 ?trans1;
IADD3 R26, PT, PT, R9, R7.reuse, RZ ?trans2;
IMAD.WIDE.U32 R30, R31, 0x4, R22 ?trans1;
ST.E desc[UR6][R28.64], R2 ?trans1;
IADD3 R18, PT, PT, R26, R7, RZ ?WAIT3_END_GROUP;
ST.E desc[UR6][R30.64], R2 ?trans1;
IMAD.WIDE.U32 R16, R21, 0x4, R22 &req={2} ?trans1;
IADD3 R37, PT, PT, R18, R7, RZ ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R14, R19, 0x4, R22.reuse &req={1} ?trans1;
ST.E desc[UR6][R12.64], R2 &rd=0x1 ?trans1;
IADD3 R6, PT, PT, R37, R7.reuse, RZ ?trans2;
IMAD.WIDE.U32 R10, R24, 0x4, R22 ?trans1;
ST.E desc[UR6][R16.64], R2 &rd=0x2 ?trans1;
IADD3 R4, PT, PT, R6, R7, RZ ?WAIT3_END_GROUP;
ST.E desc[UR6][R32.64], R2 ?trans1;
IMAD.WIDE.U32 R24, R25, 0x4, R22 ?trans1;
IADD3 R20, PT, PT, R4, R7, RZ ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R12, R5, 0x4, R22.reuse &req={1} ?trans1;
ST.E desc[UR6][R10.64], R2 &rd=0x1 ?trans1;
IADD3 R27, PT, PT, R20, R7.reuse, RZ ?trans2;
IMAD.WIDE.U32 R28, R34, 0x4, R22.reuse ?trans1;
ST.E desc[UR6][R14.64], R2 &rd=0x3 ?trans1;
IADD3 R3, PT, PT, R27, R7.reuse, RZ ?trans2;
IMAD.WIDE.U32 R16, R35, 0x4, R22 &req={2} ?trans1;
ST.E desc[UR6][R24.64], R2 ?trans1;
IADD3 R8, PT, PT, R3, R7, RZ ?WAIT2_END_GROUP;
IMAD.WIDE.U32 R10, R0, 0x4, R22.reuse &req={1} ?trans1;
ST.E desc[UR6][R28.64], R2 &rd=0x1 ?trans1;
IADD3 R19, PT, PT, R8, R7.reuse, RZ ?trans2;
IMAD.WIDE.U32 R30, R9, 0x4, R22 ?trans1;
ST.E desc[UR6][R12.64], R2 ?trans1;
IADD3 R5, PT, PT, R19, R7, RZ ?WAIT3_END_GROUP;
ST.E desc[UR6][R16.64], R2 &rd=0x2 ?trans1;
IMAD.WIDE.U32 R14, R26, 0x4, R22 &req={3} ?trans1;
IADD3 R21, PT, PT, R5, R7, RZ ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R28, R6, 0x4, R22 &req={1} ?trans1;
ST.E desc[UR6][R10.64], R2 &rd=0x1 ?trans1;
IADD3 R0, PT, PT, R21, R7, RZ ?WAIT3_END_GROUP;
ST.E desc[UR6][R30.64], R2 ?trans1;
IMAD.WIDE.U32 R24, R18, 0x4, R22 ?trans1;
IADD3 R9, PT, PT, R0, R7, RZ ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R16, R4, 0x4, R22.reuse &req={2} ?trans1;
ST.E desc[UR6][R14.64], R2 &rd=0x2 ?trans1;
IADD3 R4, PT, PT, R9, R7.reuse, RZ ?trans2;
IMAD.WIDE.U32 R12, R37, 0x4, R22.reuse ?trans1;
ST.E desc[UR6][R24.64], R2 &rd=0x3 ?trans1;
IADD3 R6, PT, PT, R4, R7.reuse, RZ ?trans2;
IMAD.WIDE.U32 R10, R20, 0x4, R22.reuse &req={1} ?trans1;
ST.E desc[UR6][R12.64], R2 &rd=0x1 ?trans3;
IMAD.WIDE.U32 R14, R27, 0x4, R22.reuse &req={2} ?trans1;
ST.E desc[UR6][R28.64], R2 ?trans3;
IMAD.WIDE.U32 R26, R3, 0x4, R22.reuse ?trans1;
IADD3 R3, PT, PT, R6, R7.reuse, RZ ?trans1;
ST.E desc[UR6][R16.64], R2 &rd=0x2 ?trans2;
IMAD.WIDE.U32 R24, R8, 0x4, R22.reuse &req={3} ?trans1;
IADD3 R20, PT, PT, R3, R7, RZ ?trans1;
ST.E desc[UR6][R10.64], R2 &rd=0x3 ?trans2;
IMAD.WIDE.U32 R12, R19, 0x4, R22 &req={1} ?WAIT2_END_GROUP;
ST.E desc[UR6][R14.64], R2 &rd=0x1 ?trans2;
IMAD.WIDE.U32 R18, R21, 0x4, R22.reuse ?trans2;
ST.E desc[UR6][R26.64], R2 ?trans2;
IMAD.WIDE.U32 R16, R5, 0x4, R22.reuse &req={2} ?trans2;
ST.E desc[UR6][R24.64], R2 ?trans2;
IMAD.WIDE.U32 R10, R0, 0x4, R22.reuse &req={3} ?trans1;
IADD3 R0, PT, PT, R20, R7.reuse, RZ ?trans1;
ST.E desc[UR6][R12.64], R2 &rd=0x2 ?trans2;
IMAD.WIDE.U32 R8, R9, 0x4, R22.reuse ?trans1;
IADD3 R21, PT, PT, R0, R7, RZ ?trans1;
ST.E desc[UR6][R16.64], R2 &rd=0x3 ?trans2;
IMAD.WIDE.U32 R4, R4, 0x4, R22 ?WAIT2_END_GROUP;
ST.E desc[UR6][R18.64], R2 &rd=0x4 ?trans2;
IMAD.WIDE.U32 R14, R6, 0x4, R22.reuse &req={1} ?trans2;
ST.E desc[UR6][R10.64], R2 &rd=0x1 ?trans2;
IMAD.WIDE.U32 R12, R3, 0x4, R22.reuse &req={2} ?trans1;
IADD3 R3, PT, PT, R21.reuse, R7.reuse, RZ ?trans1;
ST.E desc[UR6][R8.64], R2 &rd=0x2 ?trans2;
IMAD.WIDE.U32 R16, R21, 0x4, R22 &req={3} ?trans1;
IADD3 R19, PT, PT, R3, R7, RZ &req={4} ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R6, R20, 0x4, R22.reuse ?trans1;
ST.E desc[UR6][R4.64], R2 &rd=0x3 ?trans3;
IMAD.WIDE.U32 R10, R0, 0x4, R22.reuse &req={1} ?trans1;
ST.E desc[UR6][R14.64], R2 &rd=0x3 ?trans3;
IMAD.WIDE.U32 R8, R3, 0x4, R22.reuse &req={2} ?trans1;
ST.E desc[UR6][R12.64], R2 &rd=0x3 ?trans3;
IMAD.WIDE.U32 R22, R19, 0x4, R22 ?trans1;
ST.E desc[UR6][R6.64], R2 &rd=0x3 ?trans4;
ST.E desc[UR6][R10.64], R2 &rd=0x3 ?trans4;
ST.E desc[UR6][R16.64], R2 &rd=0x3 ?trans4;
ST.E desc[UR6][R8.64], R2 &rd=0x3 ?trans4;
ST.E desc[UR6][R22.64], R2 &rd=0x3 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT ?trans5;
LDS.64 R4, [UR4] &req={3} &wr=0x1 ?trans1;
MOV R2, 0x8 ?WAIT6_END_GROUP;
LDC.64 R2, c[0x4][R2] &wr=0x2 ?trans2;
LEPC R20, 0xdf0 ?WAIT7_END_GROUP;
CALL.ABS.NOINC R2 &req={2,1,0} ?trans5;
EXIT ?trans5;
BRA 0xe00;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: mallocTest()
_Z10mallocTestv:
v_mov_b32_e32 v41, v0
s_mov_b64 s[8:9], s[0:1]
s_mov_b32 s32, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s33, 0, v41
s_and_saveexec_b32 s45, s33
s_cbranch_execnz .LBB2_6
.LBB2_1:
s_or_b32 exec_lo, exec_lo, s45
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
ds_load_b64 v[0:1], v0
s_waitcnt lgkmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
s_cbranch_vccnz .LBB2_5
s_load_b32 s0, s[8:9], 0xc
v_lshlrev_b32_e32 v2, 2, v41
s_mov_b32 s1, 64
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_add_co_u32 v0, vcc_lo, v0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s0, 0xffff
s_lshl_b32 s0, s0, 2
.LBB2_3:
flat_store_b32 v[0:1], v41
v_add_co_u32 v0, vcc_lo, v0, s0
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_add_i32 s1, s1, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s1, 0
s_cbranch_scc1 .LBB2_3
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s0, s33
s_cbranch_execnz .LBB2_7
.LBB2_5:
s_endpgm
.LBB2_6:
s_load_b32 s0, s[8:9], 0xc
v_dual_mov_b32 v42, 0 :: v_dual_mov_b32 v1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s0, 0xffff
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, __ockl_dm_alloc@rel32@lo+4
s_addc_u32 s1, s1, __ockl_dm_alloc@rel32@hi+12
s_lshl_b32 s2, s2, 8
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v0, s2
s_swappc_b64 s[30:31], s[0:1]
ds_store_b64 v42, v[0:1]
s_branch .LBB2_1
.LBB2_7:
v_mov_b32_e32 v0, 0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, __ockl_dm_dealloc@rel32@lo+4
s_addc_u32 s1, s1, __ockl_dm_dealloc@rel32@hi+12
ds_load_b64 v[0:1], v0
s_swappc_b64 s[30:31], s[0:1]
s_endpgm
| mallocTest | 5,833 | 973 | stackv2-00000-of-00015 |
// Demangled: square_array(double*, int)
Function : _Z12square_arrayPdi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x388] &wr=0x2 ?trans7;
LDC R5, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R5, R5, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R5, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD.WIDE R2, R5, 0x8, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E.64 R4, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans2;
DMUL R4, R4, R4 &req={2} &wr=0x0 ?trans2;
STG.E.64 desc[UR4][R2.64], R4 &req={0} ?trans1;
EXIT ?trans5;
BRA 0xf0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: square_array(double*, int)
_Z12square_arrayPdi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f64 v[2:3], v[2:3], v[2:3]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| square_array | 429 | 453 | stackv2-00000-of-00015 |
// Demangled: vupdate(int, int const*, int*)
Function : _Z7vupdateiPKiPi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x380] &wr=0x2 ?trans7;
LDC R7, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R7, R7, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R7, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x388] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x390] &wr=0x2 ?trans1;
IMAD.WIDE R2, R7, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x3 ?trans1;
IMAD.WIDE R4, R7, 0x4, R4 &req={2} ?WAIT5_END_GROUP;
LDG.E R7, desc[UR4][R4.64] &wr=0x3 ?trans2;
IADD3 R7, PT, PT, R2, R7, RZ &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64], R7 ?trans1;
EXIT ?trans5;
BRA 0x120;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: vupdate(int, int const*, int*)
_Z7vupdateiPKiPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| vupdate | 520 | 506 | stackv2-00000-of-00015 |
// Demangled: genran(int*, double)
Function : _Z6genranPid
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x2 ?trans1;
BSSY.RECONVERGENT B1, 0x640 ?trans7;
LDC R3, c[0x0][0x360] &wr=0x2 ?trans1;
ISETP.NE.AND P0, PT, R0, RZ, PT &req={1} ?trans1;
IMAD R10, R3, UR4, R0 &req={2} ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans5;
I2F.F64.U32 R10, R10 &wr=0x2 ?trans6;
@!P0 BRA 0x630 &req={0} ?trans5;
LDC.64 R2, c[0x0][0x388] &wr=0x0 ?trans1;
MOV R9, RZ ?trans1;
LOP3.LUT R3, R3, 0x7fffffff, RZ, 0xc0, !PT &req={0} ?WAIT4_END_GROUP;
SHF.R.U32.HI R8, RZ, 0x14, R3 ?trans1;
ISETP.GE.U32.AND P0, PT, R3, 0x100000, PT ?trans1;
DMUL R4, R2, 1.80143985094819840000e+16 &wr=0x0 ?trans2;
LEA.HI R7, R5.reuse, R8, RZ, 0xc &req={0} ?trans2;
FSEL R6, R5, R3, !P0 ?trans1;
FSEL R4, R4, R2, !P0 ?WAIT4_END_GROUP;
LOP3.LUT R5, R6, 0xfffff, RZ, 0xc0, !PT ?WAIT3_END_GROUP;
@!P0 IADD3 R8, PT, PT, R7, -0x36, RZ ?trans2;
LOP3.LUT R5, R5, 0x100000, RZ, 0xfc, !PT ?WAIT7_END_GROUP;
MOV.64 R6, 0x41d071939b400000 ?WAIT3_END_GROUP;
IADD3 R9, PT, PT, R9, 0x1, RZ ?trans1;
BSSY.RECONVERGENT B0, 0x620 ?trans3;
DFMA R6, R10, R6, 12345 &req={2} &wr=0x0 ?trans1;
ISETP.NE.AND P1, PT, R9, R0, PT ?trans1;
LOP3.LUT R13, R7, 0x7fffffff, RZ, 0xc0, !PT &req={0} ?trans1;
MOV R12, R6 ?WAIT4_END_GROUP;
VIMNMX.U32 R10, R3, R13, !PT ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R10, 0x7ff00000, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x340 ?trans5;
DSETP.NAN.AND P0, PT, R2, R2, PT &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DSETP.NUM.AND P0, PT, R12, R12, !P0 &req={0} &wr=0x0 ?trans2;
@!P0 LDC.64 R10, c[0x0][0x388] &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
@!P0 DADD R10, R6, R10 &req={0} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
@P0 DSETP.NEU.AND P2, PT, R12, +INF , PT &wr=0x0 ?trans2;
@P0 FSEL R10, R6, RZ, P2 &req={0} ?trans1;
@P0 FSEL R11, R7, -QNAN , P2 ?trans1;
BRA 0x610 ?trans6;
DSETP.NEU.AND P0, PT, R2, RZ, PT &wr=0x0 ?trans1;
MOV.64 R10, 0xfff8000000000000 ?trans2;
@!P0 BRA 0x610 &req={0} ?trans6;
DSETP.GE.AND P0, PT, R12, R2, PT &wr=0x0 ?trans1;
MOV.64 R10, R6 ?trans2;
@!P0 BRA 0x610 &req={0} ?trans6;
ISETP.GT.U32.AND P0, PT, R13, 0xfffff, PT ?trans1;
SHF.R.U32.HI R11, RZ, 0x14, R13 ?trans1;
BSSY.RECONVERGENT B2, 0x4b0 ?trans11;
@!P0 DMUL R12, R12, 1.80143985094819840000e+16 &wr=0x0 ?trans2;
@!P0 LEA.HI R10, R13, R11, RZ, 0xc &req={0} ?WAIT2_END_GROUP;
LOP3.LUT R13, R13, 0xfffff, RZ, 0xc0, !PT ?trans2;
@!P0 IADD3 R11, PT, PT, R10, -0x36, RZ ?trans2;
LOP3.LUT R13, R13, 0x100000, RZ, 0xfc, !PT ?trans2;
IADD3 R16, PT, PT, -R8, R11, RZ ?WAIT7_END_GROUP;
IADD.64 R10, R12, -R4 ?trans2;
ISETP.GT.AND P2, PT, R16.reuse, RZ, PT ?trans1;
IADD3 R16, PT, PT, R16, -0x1, RZ ?WAIT3_END_GROUP;
ISETP.GE.AND P0, PT, R11, RZ, PT ?WAIT5_END_GROUP;
SEL.64 R14, R12, R10, !P0 ?WAIT4_END_GROUP;
IADD.64 R12, R14, R14 ?trans2;
@P2 BRA 0x430 ?trans6;
BSYNC.RECONVERGENT B2 &req={1} ?trans5;
LOP3.LUT R13, R15, 0x7fffffff, RZ, 0xc0, !PT ?trans1;
BSSY.RECONVERGENT B2, 0x600 ?trans1;
MOV R12, R14 ?trans1;
MOV.64 R10, RZ ?WAIT4_END_GROUP;
ISETP.NE.S64.AND P0, PT, R12, RZ, PT ?WAIT14_END_GROUP;
@!P0 BRA 0x5f0 ?trans5;
DMUL R10, R12, 1.80143985094819840000e+16 &wr=0x0 ?trans2;
SHF.R.U32.HI R10, RZ, 0x14, R11 &req={0} ?WAIT4_END_GROUP;
IADD3 R11, PT, PT, -R10, 0x37, RZ ?WAIT4_END_GROUP;
IADD3 R12, PT, PT, R8, -R11.reuse, RZ ?trans2;
SHF.L.U64.HI R15, R14.reuse, R11.reuse, R13 ?trans2;
SHF.L.U32 R14, R14, R11, RZ ?trans1;
ISETP.GT.AND P0, PT, R12, RZ, PT ?WAIT13_END_GROUP;
@!P0 IADD3 R13, PT, PT, -R12.reuse, 0x1, RZ ?trans2;
@P0 IADD3 R12, PT, PT, R12, -0x1, RZ ?trans2;
@!P0 SHF.R.U64 R10, R14, R13.reuse, R15.reuse ?trans2;
@!P0 SHF.R.U32.HI R11, RZ, R13, R15 ?trans1;
@P0 IMAD.SHL.U32 R13, R12, 0x100000, RZ ?trans1;
@P0 MOV R12, RZ ?WAIT5_END_GROUP;
@P0 IADD.64 R10, R12, R14 ?WAIT8_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
LOP3.LUT R11, R11, 0x80000000, R7, 0xf8, !PT ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 &req={1} ?trans5;
@P1 BRA 0x160 ?trans5;
BSYNC.RECONVERGENT B1 &req={1} ?trans5;
LDCU.64 UR6, c[0x0][0x380] &wr=0x0 ?trans1;
F2I.U64.F64.TRUNC R10, R10 &req={2} &wr=0x0 ?trans1;
HFMA2 R5, -RZ, RZ, 0, 5.9604644775390625e-08 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
LEA R2, P0, R10, UR6, 0x2 &req={0} ?WAIT4_END_GROUP;
LEA.HI.X R3, R10, UR7, R11, 0x2, P0 ?WAIT5_END_GROUP;
REDG.E.ADD.STRONG.GPU desc[UR4][R2.64], R5 ?trans1;
EXIT ?trans5;
BRA 0x6c0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: genran(int*, double)
_Z6genranPid:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s8, 0
s_mov_b32 s1, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cvt_f64_u32_e32 v[5:6], v1
v_cmpx_ne_u32_e32 0, v0
s_cbranch_execz .LBB0_12
v_frexp_mant_f64_e64 v[1:2], |s[6:7]|
v_cmp_eq_f64_e64 s9, s[6:7], 0
v_cmp_o_f64_e64 s10, s[6:7], s[6:7]
s_mov_b32 s2, 0x9b400000
s_mov_b32 s3, 0x41d07193
s_mov_b32 s11, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[1:2], v[1:2], 1
v_div_scale_f64 v[3:4], null, v[1:2], v[1:2], 1.0
v_div_scale_f64 v[11:12], vcc_lo, 1.0, v[1:2], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[7:8], v[3:4]
s_waitcnt_depctr 0xfff
v_fma_f64 v[9:10], -v[3:4], v[7:8], 1.0
v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], -v[3:4], v[7:8], 1.0
v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[9:10], v[11:12], v[7:8]
v_fma_f64 v[3:4], -v[3:4], v[9:10], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[3:4], v[3:4], v[7:8], v[9:10]
v_frexp_exp_i32_f64_e32 v9, s[6:7]
v_div_fixup_f64 v[3:4], v[3:4], v[1:2], 1.0
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v10, -1, v9
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[5:6], v[5:6], s[2:3], 0x40c81c80
v_cmp_ngt_f64_e64 s0, |v[5:6]|, |s[6:7]|
v_and_b32_e32 v11, 0x80000000, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s12, s0
s_xor_b32 s0, exec_lo, s12
v_cmp_eq_f64_e64 vcc_lo, |v[5:6]|, |s[6:7]|
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v8, v6, v11, vcc_lo
v_cndmask_b32_e64 v7, v5, 0, vcc_lo
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_10
v_frexp_mant_f64_e64 v[7:8], |v[5:6]|
v_frexp_exp_i32_f64_e32 v12, v[5:6]
s_mov_b32 s12, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ldexp_f64 v[7:8], v[7:8], 26
v_sub_nc_u32_e32 v12, v12, v9
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e32 26, v12
s_cbranch_execz .LBB0_9
s_mov_b32 s13, 0
.LBB0_7:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[13:14], v[3:4], v[7:8]
v_rndne_f64_e32 v[13:14], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], -v[13:14], v[1:2], v[7:8]
v_cmp_gt_f64_e32 vcc_lo, 0, v[7:8]
v_cndmask_b32_e32 v14, 0x80000000, v2, vcc_lo
v_cndmask_b32_e32 v13, 0, v1, vcc_lo
v_cmp_gt_u32_e32 vcc_lo, 53, v12
v_subrev_nc_u32_e32 v12, 26, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[7:8], v[7:8], v[13:14]
s_or_b32 s13, vcc_lo, s13
v_ldexp_f64 v[7:8], v[7:8], 26
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execnz .LBB0_7
s_or_b32 exec_lo, exec_lo, s13
.LBB0_9:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s12
v_subrev_nc_u32_e32 v12, 25, v12
v_ldexp_f64 v[7:8], v[7:8], v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[12:13], v[3:4], v[7:8]
v_rndne_f64_e32 v[12:13], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], -v[12:13], v[1:2], v[7:8]
v_cmp_gt_f64_e32 vcc_lo, 0, v[7:8]
v_cndmask_b32_e32 v13, 0x80000000, v2, vcc_lo
v_cndmask_b32_e32 v12, 0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[7:8], v[7:8], v[12:13]
v_ldexp_f64 v[7:8], v[7:8], v10
s_delay_alu instid0(VALU_DEP_1)
v_xor_b32_e32 v8, v11, v8
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s0
v_cmp_class_f64_e64 s0, v[5:6], 0x1f8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v5, v7, 0, s9
v_cndmask_b32_e64 v6, v8, 0x7ff80000, s9
s_add_i32 s11, s11, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_eq_u32_e32 vcc_lo, s11, v0
s_and_b32 s0, s10, s0
s_or_b32 s8, vcc_lo, s8
v_cndmask_b32_e64 v6, 0x7ff80000, v6, s0
v_cndmask_b32_e64 v5, 0, v5, s0
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s8
.LBB0_12:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s1
v_trunc_f64_e32 v[0:1], v[5:6]
s_barrier
buffer_gl0_inv
v_ldexp_f64 v[2:3], v[0:1], 0xffffffe0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_floor_f64_e32 v[2:3], v[2:3]
v_fma_f64 v[0:1], 0xc1f00000, v[2:3], v[0:1]
v_cvt_u32_f64_e32 v2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f64_e32 v1, v[0:1]
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_atomic_add_u32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| genran | 2,709 | 3,062 | stackv2-00000-of-00015 |
// Demangled: positions(double*, double*, double*, double*, double*)
Function : _Z9positionsPdS_S_S_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R7, SR_CTAID.X &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x390] &wr=0x2 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x3 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans6;
LDC.64 R2, c[0x0][0x380] &wr=0x4 ?trans1;
IMAD R7, R7, R7, R0 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE R4, R7, 0x8, R4 &req={2} ?WAIT4_END_GROUP;
IMAD.WIDE R2, R7, 0x8, R2 &req={4} ?trans2;
LDG.E.64 R4, desc[UR4][R4.64] &req={3} &wr=0x5 ?trans4;
LDG.E.64 R8, desc[UR4][R2.64] &rd=0x1 &wr=0x5 ?trans1;
BSSY B0, 0x140 ?trans1;
SHF.R.S32.HI R0, RZ, 0x1f, R7 &req={0} ?WAIT7_END_GROUP;
DADD R10, R4, R8 &req={5} &wr=0x0 ?trans1;
YIELD ?trans5;
ATOMG.E.CAS.64.STRONG.GPU PT, R10, [R2], R8, R10 &req={0} &wr=0x2 ?trans2;
ISETP.NE.S64.AND P0, PT, R8, R10.reuse, PT &req={2} ?trans2;
MOV.64 R8, R10 ?WAIT12_END_GROUP;
@P0 BRA 0xd0 ?trans5;
BSYNC B0 ?trans5;
LDCU.64 UR8, c[0x0][0x398] &wr=0x0 ?trans1;
SHF.L.U64.HI R3, R7.reuse, 0x3, R0 &req={1} ?trans1;
IMAD.SHL.U32 R2, R7, 0x8, RZ ?trans1;
LDCU.64 UR6, c[0x0][0x388] &wr=0x1 ?trans4;
IADD.64 R4, R2.reuse, UR8 &req={0} ?trans2;
IADD.64 R2, R2, UR6 &req={1} ?WAIT5_END_GROUP;
LDG.E.64 R4, desc[UR4][R4.64] &wr=0x5 ?trans4;
LDG.E.64 R8, desc[UR4][R2.64] &rd=0x0 &wr=0x5 ?trans2;
DADD R10, R4, R8 &req={5} &wr=0x1 ?trans1;
YIELD ?trans5;
ATOMG.E.CAS.64.STRONG.GPU PT, R10, [R2], R8, R10 &req={1} &wr=0x2 ?trans2;
ISETP.NE.S64.AND P0, PT, R8, R10.reuse, PT &req={2} ?trans2;
MOV.64 R8, R10 ?WAIT12_END_GROUP;
@P0 BRA 0x1c0 ?trans5;
EXIT ?trans5;
BRA 0x230;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: positions(double*, double*, double*, double*, double*)
_Z9positionsPdS_S_S_S_:
s_load_b256 s[0:7], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s15, s15, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[4:5], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v5, vcc_lo
s_mov_b32 s0, 0
global_load_b64 v[8:9], v[0:1], off
global_load_b64 v[2:3], v[6:7], off
.LBB1_1:
s_waitcnt vmcnt(0)
v_add_f64 v[0:1], v[8:9], v[2:3]
global_atomic_cmpswap_b64 v[0:1], v[6:7], v[0:3], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[0:1]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB1_1
s_or_b32 exec_lo, exec_lo, s0
v_add_co_u32 v0, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_mov_b32 s0, 0
global_load_b64 v[6:7], v[0:1], off
global_load_b64 v[2:3], v[4:5], off
.LBB1_3:
s_waitcnt vmcnt(0)
v_add_f64 v[0:1], v[6:7], v[2:3]
global_atomic_cmpswap_b64 v[0:1], v[4:5], v[0:3], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[0:1]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB1_3
s_endpgm
| positions | 949 | 848 | stackv2-00000-of-00015 |
// Demangled: gen_image_kernel(curandStatePhilox4_32_10*, unsigned int*, unsigned int)
Function : _Z16gen_image_kernelP24curandStatePhilox4_32_10Pjj
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.Z &wr=0x1 ?trans8;
LDC R0, c[0x0][0x360] &wr=0x1 ?trans8;
LDC R5, c[0x0][0x390] &wr=0x2 ?trans8;
S2UR UR5, SR_CTAID.Y &wr=0x3 ?trans1;
IMAD R0, R0, UR4, R3 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R0, R5, PT &req={2} ?trans1;
IMAD R0, R5, UR5, R0 &req={3} ?WAIT12_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD.WIDE.U32 R2, R0, 0x40, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E.128 R8, desc[UR4][R2.64+0x20] &req={1} &wr=0x2 ?trans4;
LDG.E.128 R12, desc[UR4][R2.64+0x10] &wr=0x3 ?trans4;
LDG.E.128 R4, desc[UR4][R2.64] &rd=0x0 &wr=0x5 ?trans1;
BSSY.RECONVERGENT B0, 0x6c0 ?trans1;
HFMA2 R17, -RZ, RZ, 0, 1.1920928955078125e-07 ?trans1;
ISETP.NE.AND P0, PT, R10, 0x1, PT &req={2} ?trans1;
MOV R11, R15 &req={3} ?trans1;
MOV R19, R13 ?WAIT4_END_GROUP;
MOV R15, R11 ?WAIT7_END_GROUP;
@!P0 BRA 0x6b0 &req={0} ?trans5;
ISETP.NE.AND P0, PT, R10, 0x3, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x200 ?trans5;
ISETP.NE.AND P0, PT, R10, 0x2, PT ?WAIT13_END_GROUP;
@!P0 MOV R17, 0x3 ?trans1;
@!P0 MOV R19, R14 ?trans1;
@P0 MOV R15, R11 ?trans1;
@P0 IADD3 R17, PT, PT, R10, 0x1, RZ ?trans1;
@P0 MOV R19, R12 ?trans1;
BRA 0x6b0 ?trans6;
IADD3 R4, PT, PT, R4, 0x1, RZ &req={5} ?trans1;
BSSY.RECONVERGENT B1, 0x2e0 ?trans4;
ISETP.NE.AND P0, PT, R4.reuse, RZ, PT ?trans1;
IMAD.WIDE.U32 R14, R4, -0x2daee0ad, RZ ?WAIT12_END_GROUP;
@P0 BRA 0x2d0 ?trans5;
IADD3 R5, PT, PT, R5, 0x1, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R5, RZ, PT ?WAIT13_END_GROUP;
@!P0 IADD3 R6, PT, PT, R6, 0x1, RZ ?trans2;
@!P0 IADD3 R10, PT, PT, R7, 0x1, RZ ?trans1;
@!P0 MOV R5, RZ ?trans2;
ISETP.NE.AND P1, PT, R6, RZ, !P0 ?WAIT13_END_GROUP;
@P1 IADD3 R10, PT, PT, R7, RZ, RZ ?WAIT5_END_GROUP;
@!P0 MOV R7, R10 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B1 ?trans5;
IMAD.WIDE.U32 R16, R6, -0x326172a9, RZ ?trans1;
LOP3.LUT R12, R7, R9, R15, 0x96, !PT ?trans2;
IADD3 R15, PT, PT, R8, -0x61c88647, RZ ?trans2;
LOP3.LUT R18, R5, R8, R17, 0x96, !PT ?trans1;
IMAD.WIDE.U32 R12, R12, -0x326172a9, RZ ?trans1;
IADD3 R17, PT, PT, R9, -0x4498517b, RZ ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R18, R18, -0x2daee0ad, RZ ?trans1;
LOP3.LUT R15, R13, R16, R15, 0x96, !PT ?trans2;
IADD3 R13, PT, PT, R8, 0x3c6ef372, RZ ?trans2;
LOP3.LUT R17, R19, R17, R14, 0x96, !PT ?trans1;
IMAD.WIDE.U32 R14, R15, -0x2daee0ad, RZ ?trans1;
IADD3 R19, PT, PT, R9, 0x76cf5d0a, RZ ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R16, R17, -0x326172a9, RZ ?trans1;
LOP3.LUT R19, R15, R18, R19, 0x96, !PT ?trans2;
IADD3 R15, PT, PT, R8, -0x255992d5, RZ ?trans2;
LOP3.LUT R18, R17, R12, R13, 0x96, !PT ?trans1;
IMAD.WIDE.U32 R12, R19, -0x326172a9, RZ ?trans1;
IADD3 R17, PT, PT, R9, 0x32370b8f, RZ ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R18, R18, -0x2daee0ad, RZ ?trans1;
LOP3.LUT R15, R13, R16, R15, 0x96, !PT ?trans2;
IADD3 R13, PT, PT, R8, 0x78dde6e4, RZ ?trans2;
LOP3.LUT R17, R19, R14, R17, 0x96, !PT ?trans1;
IMAD.WIDE.U32 R14, R15, -0x2daee0ad, RZ ?trans1;
IADD3 R19, PT, PT, R9, -0x126145ec, RZ ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R16, R17, -0x326172a9, RZ ?trans1;
LOP3.LUT R19, R15, R18, R19, 0x96, !PT ?trans2;
IADD3 R15, PT, PT, R8, 0x1715609d, RZ ?trans2;
LOP3.LUT R18, R17, R12, R13, 0x96, !PT ?trans1;
IMAD.WIDE.U32 R12, R19, -0x326172a9, RZ ?trans1;
IADD3 R17, PT, PT, R9, -0x56f99767, RZ ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R18, R18, -0x2daee0ad, RZ ?trans1;
LOP3.LUT R15, R13, R16, R15, 0x96, !PT ?trans2;
IADD3 R13, PT, PT, R8, -0x4ab325aa, RZ ?trans2;
LOP3.LUT R17, R19, R14, R17, 0x96, !PT ?trans1;
IMAD.WIDE.U32 R14, R15, -0x2daee0ad, RZ ?trans1;
IADD3 R19, PT, PT, R9, 0x646e171e, RZ ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R16, R17, -0x326172a9, RZ ?trans1;
LOP3.LUT R19, R15, R18, R19, 0x96, !PT ?trans2;
IADD3 R15, PT, PT, R8, 0x5384540f, RZ ?trans2;
LOP3.LUT R18, R17, R12, R13, 0x96, !PT ?trans1;
IMAD.WIDE.U32 R12, R19, -0x326172a9, RZ ?trans1;
IADD3 R17, PT, PT, R9, 0x1fd5c5a3, RZ ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R18, R18, -0x2daee0ad, RZ ?trans1;
LOP3.LUT R15, R13, R16, R15, 0x96, !PT ?trans2;
IADD3 R13, PT, PT, R8, -0xe443238, RZ ?trans2;
LOP3.LUT R17, R19, R14, R17, 0x96, !PT ?trans1;
IMAD.WIDE.U32 R14, R15, -0x2daee0ad, RZ ?trans1;
IADD3 R19, PT, PT, R9.reuse, -0x24c28bd8, RZ ?trans2;
IADD3 R9, PT, PT, R9, -0x695add53, RZ ?trans1;
IMAD.WIDE.U32 R16, R17, -0x326172a9, RZ ?trans1;
LOP3.LUT R19, R15, R18, R19, 0x96, !PT ?WAIT2_END_GROUP;
IADD3 R15, PT, PT, R8, -0x700cb87f, RZ ?trans2;
LOP3.LUT R13, R17, R12, R13, 0x96, !PT ?trans1;
HFMA2 R17, -RZ, RZ, 0, 0 ?trans2;
IMAD.WIDE.U32 R20, R19, -0x326172a9, RZ ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R18, R13, -0x2daee0ad, RZ ?trans1;
LOP3.LUT R12, R21, R16, R15, 0x96, !PT ?trans1;
MOV R13, R20 ?WAIT3_END_GROUP;
LOP3.LUT R14, R19, R14, R9, 0x96, !PT ?trans1;
MOV R15, R18 ?trans1;
MOV R19, R11 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
LDCU.64 UR6, c[0x0][0x388] &wr=0x0 ?trans1;
STG.E.128 desc[UR4][R2.64], R4 &req={5} ?trans4;
STG.E desc[UR4][R2.64+0x28], R17 ?trans4;
STG.E.128 desc[UR4][R2.64+0x10], R12 ?trans1;
LEA R8, P0, R0, UR6, 0x2 &req={0} ?WAIT4_END_GROUP;
LEA.HI.X R9, R0, UR7, RZ, 0x2, P0 ?WAIT5_END_GROUP;
STG.E desc[UR4][R8.64], R19 ?trans1;
EXIT ?trans5;
BRA 0x740;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: gen_image_kernel(hiprandStatePhilox4_32_10*, unsigned int*, unsigned int)
_Z16gen_image_kernelP25hiprandStatePhilox4_32_10Pjj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s4, v1
s_cbranch_execz .LBB1_4
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[14:15], null, s14, s4, v[1:2]
v_mov_b32_e32 v15, 0
v_lshlrev_b64 v[0:1], 6, v[14:15]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v12, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v13, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s0, exec_lo
s_clause 0x2
global_load_b32 v16, v[12:13], off offset:40
global_load_b128 v[4:7], v[12:13], off offset:16
global_load_b128 v[0:3], v[12:13], off
s_waitcnt vmcnt(1)
v_dual_mov_b32 v10, v6 :: v_dual_add_nc_u32 v17, 1, v16
v_dual_mov_b32 v8, v4 :: v_dual_mov_b32 v9, v5
v_mov_b32_e32 v11, v7
s_delay_alu instid0(VALU_DEP_3)
v_cmpx_eq_u32_e32 4, v17
s_cbranch_execz .LBB1_3
global_load_b64 v[17:18], v[12:13], off offset:32
s_waitcnt vmcnt(1)
v_add_co_u32 v0, vcc_lo, v0, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v8, 0, 1, vcc_lo
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v8, 0, v8, vcc_lo
v_add_nc_u32_e32 v2, v8, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cmp_eq_u32_e32 vcc_lo, 0, v2
v_cndmask_b32_e32 v19, 0, v8, vcc_lo
v_mad_u64_u32 v[8:9], null, 0xd2511f53, v0, 0
v_mad_u64_u32 v[10:11], null, 0xcd9e8d57, v2, 0
v_add_nc_u32_e32 v3, v19, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor3_b32 v9, v18, v9, v3
v_xor3_b32 v11, v17, v11, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[19:20], null, 0xcd9e8d57, v9, 0
v_mad_u64_u32 v[21:22], null, 0xd2511f53, v11, 0
v_add_nc_u32_e32 v9, 0x9e3779b9, v17
v_add_nc_u32_e32 v11, 0xbb67ae85, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor3_b32 v10, v20, v10, v9
v_xor3_b32 v20, v22, v8, v11
v_add_nc_u32_e32 v22, 0x3c6ef372, v17
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[8:9], null, 0xd2511f53, v10, 0
v_mad_u64_u32 v[10:11], null, 0xcd9e8d57, v20, 0
v_add_nc_u32_e32 v20, 0x76cf5d0a, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor3_b32 v9, v9, v21, v20
v_xor3_b32 v11, v11, v19, v22
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[19:20], null, 0xcd9e8d57, v9, 0
v_mad_u64_u32 v[21:22], null, 0xd2511f53, v11, 0
v_add_nc_u32_e32 v9, 0xdaa66d2b, v17
v_add_nc_u32_e32 v11, 0x32370b8f, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor3_b32 v10, v20, v10, v9
v_xor3_b32 v20, v22, v8, v11
v_add_nc_u32_e32 v22, 0x78dde6e4, v17
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[8:9], null, 0xd2511f53, v10, 0
v_mad_u64_u32 v[10:11], null, 0xcd9e8d57, v20, 0
v_add_nc_u32_e32 v20, 0xed9eba14, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor3_b32 v9, v9, v21, v20
v_xor3_b32 v11, v11, v19, v22
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[19:20], null, 0xcd9e8d57, v9, 0
v_mad_u64_u32 v[21:22], null, 0xd2511f53, v11, 0
v_add_nc_u32_e32 v9, 0x1715609d, v17
v_add_nc_u32_e32 v11, 0xa9066899, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor3_b32 v10, v20, v10, v9
v_xor3_b32 v20, v22, v8, v11
v_add_nc_u32_e32 v22, 0xb54cda56, v17
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[8:9], null, 0xd2511f53, v10, 0
v_mad_u64_u32 v[10:11], null, 0xcd9e8d57, v20, 0
v_add_nc_u32_e32 v20, 0x646e171e, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor3_b32 v9, v9, v21, v20
v_xor3_b32 v11, v11, v19, v22
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[19:20], null, 0xcd9e8d57, v9, 0
v_mad_u64_u32 v[21:22], null, 0xd2511f53, v11, 0
v_add_nc_u32_e32 v9, 0x5384540f, v17
v_add_nc_u32_e32 v11, 0x1fd5c5a3, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor3_b32 v9, v20, v10, v9
v_xor3_b32 v10, v22, v8, v11
v_add_nc_u32_e32 v11, 0xf1bbcdc8, v17
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[22:23], null, 0xd2511f53, v9, 0
v_mad_u64_u32 v[8:9], null, 0xcd9e8d57, v10, 0
v_add_nc_u32_e32 v10, 0xdb3d7428, v18
v_add_nc_u32_e32 v18, 0x96a522ad, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_xor3_b32 v20, v23, v21, v10
v_xor3_b32 v11, v9, v19, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[9:10], null, 0xcd9e8d57, v20, 0
v_mad_u64_u32 v[19:20], null, 0xd2511f53, v11, 0
v_add_nc_u32_e32 v11, 0x8ff34781, v17
v_mov_b32_e32 v17, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_xor3_b32 v8, v11, v8, v10
v_xor3_b32 v10, v18, v22, v20
v_mov_b32_e32 v11, v19
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s0
v_cmp_eq_u32_e32 vcc_lo, 1, v16
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 2, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v6, v4, v6, vcc_lo
v_lshlrev_b64 v[4:5], 2, v[14:15]
v_cmp_eq_u32_e32 vcc_lo, 3, v16
v_cndmask_b32_e32 v6, v6, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_waitcnt vmcnt(0)
s_clause 0x2
global_store_b128 v[12:13], v[0:3], off
global_store_b128 v[12:13], v[8:11], off offset:16
global_store_b32 v[12:13], v17, off offset:40
global_store_b32 v[4:5], v6, off
.LBB1_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| gen_image_kernel | 3,298 | 3,672 | stackv2-00000-of-00015 |
// Demangled: setup_curand(curandStatePhilox4_32_10*, unsigned long, unsigned int)
Function : _Z12setup_curandP24curandStatePhilox4_32_10mj
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.Z &wr=0x1 ?trans8;
LDC R6, c[0x0][0x360] &wr=0x1 ?trans8;
LDC R5, c[0x0][0x390] &wr=0x2 ?trans8;
S2UR UR5, SR_CTAID.Y &wr=0x3 ?trans1;
IMAD R6, R6, UR4, R3 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R6, R5, PT &req={2} ?trans1;
IMAD R6, R5, UR5, R6 &req={3} ?WAIT12_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x388] &wr=0x0 ?trans1;
IMAD.WIDE.U32 R4, R6, -0x326172a9, RZ ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
CS2R R14, SRZ ?trans1;
IADD3 R7, PT, PT, R2, -0x61c88647, RZ &req={0} ?trans1;
IMAD.WIDE.U32 R10, R3, -0x326172a9, RZ ?trans1;
LOP3.LUT R8, R5, R2, RZ, 0x3c, !PT ?WAIT4_END_GROUP;
LOP3.LUT R4, R11, R7, R4, 0x96, !PT ?trans1;
IMAD.WIDE.U32 R8, R8, -0x2daee0ad, RZ ?trans1;
IADD3 R7, PT, PT, R3.reuse, -0x4498517b, RZ ?trans2;
IADD3 R11, PT, PT, R3, 0x76cf5d0a, RZ ?trans1;
IMAD.WIDE.U32 R4, R4, -0x2daee0ad, RZ ?trans1;
LOP3.LUT R7, R7, R9, RZ, 0x3c, !PT ?WAIT4_END_GROUP;
LOP3.LUT R8, R5, R8, R11, 0x96, !PT ?trans2;
IADD3 R5, PT, PT, R2.reuse, 0x3c6ef372, RZ ?trans1;
IMAD.WIDE.U32 R12, R7, -0x326172a9, RZ ?trans1;
IADD3 R11, PT, PT, R2, -0x255992d5, RZ ?trans2;
IADD3 R7, PT, PT, R3, 0x32370b8f, RZ ?trans1;
IMAD.WIDE.U32 R8, R8, -0x326172a9, RZ ?trans1;
LOP3.LUT R5, R13, R10, R5, 0x96, !PT ?WAIT4_END_GROUP;
LOP3.LUT R11, R9, R12, R11, 0x96, !PT ?trans1;
IMAD.WIDE.U32 R12, R5, -0x2daee0ad, RZ ?trans1;
IADD3 R9, PT, PT, R3, -0x126145ec, RZ ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R10, R11, -0x2daee0ad, RZ ?trans1;
LOP3.LUT R7, R13, R4, R7, 0x96, !PT ?WAIT4_END_GROUP;
LOP3.LUT R4, R11, R12, R9, 0x96, !PT ?trans1;
IMAD.WIDE.U32 R12, R7, -0x326172a9, RZ ?trans1;
IADD3 R9, PT, PT, R2.reuse, 0x78dde6e4, RZ ?trans2;
IADD3 R11, PT, PT, R2, 0x1715609d, RZ ?trans2;
IADD3 R7, PT, PT, R3, 0x646e171e, RZ ?trans1;
IMAD.WIDE.U32 R4, R4, -0x326172a9, RZ ?trans1;
LOP3.LUT R9, R13, R8, R9, 0x96, !PT ?WAIT4_END_GROUP;
LOP3.LUT R8, R5, R12, R11, 0x96, !PT ?trans2;
IADD3 R5, PT, PT, R3, -0x56f99767, RZ ?trans1;
IMAD.WIDE.U32 R12, R9, -0x2daee0ad, RZ ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R8, R8, -0x2daee0ad, RZ ?trans1;
LOP3.LUT R10, R13, R10, R5, 0x96, !PT ?trans2;
IADD3 R5, PT, PT, R2, -0x4ab325aa, RZ ?trans2;
LOP3.LUT R12, R9, R12, R7, 0x96, !PT ?trans1;
IMAD.WIDE.U32 R10, R10, -0x326172a9, RZ ?trans1;
IADD3 R7, PT, PT, R2, 0x5384540f, RZ ?trans2;
IADD3 R9, PT, PT, R3, -0x24c28bd8, RZ ?trans1;
IMAD.WIDE.U32 R12, R12, -0x326172a9, RZ ?trans1;
LOP3.LUT R5, R11, R4, R5, 0x96, !PT ?WAIT4_END_GROUP;
LOP3.LUT R16, R13, R10, R7, 0x96, !PT ?trans1;
IMAD.WIDE.U32 R4, R5, -0x2daee0ad, RZ ?trans1;
LDC.64 R10, c[0x0][0x380] &wr=0x0 ?trans1;
IADD3 R7, PT, PT, R3, 0x1fd5c5a3, RZ ?trans1;
MOV R13, R3 ?trans1;
IMAD.WIDE.U32 R16, R16, -0x2daee0ad, RZ ?trans2;
LOP3.LUT R8, R5, R8, R7, 0x96, !PT ?WAIT3_END_GROUP;
LOP3.LUT R22, R17, R4, R9, 0x96, !PT ?trans2;
IADD3 R5, PT, PT, R2, -0xe443238, RZ ?trans1;
IMAD.WIDE.U32 R8, R8, -0x326172a9, RZ ?trans1;
IADD3 R7, PT, PT, R2, -0x700cb87f, RZ ?trans2;
IADD3 R17, PT, PT, R3, -0x695add53, RZ ?trans1;
IMAD.WIDE.U32 R22, R22, -0x326172a9, RZ ?trans1;
LOP3.LUT R20, R9, R12, R5, 0x96, !PT ?trans1;
CS2R R4, SRZ ?trans1;
MOV R12, R2 ?WAIT2_END_GROUP;
LOP3.LUT R8, R23, R8, R7, 0x96, !PT ?trans1;
IMAD.WIDE.U32 R20, R20, -0x2daee0ad, RZ ?WAIT4_END_GROUP;
HFMA2 R7, -RZ, RZ, 0, 0 ?trans1;
MOV R9, R22 ?trans1;
IMAD.WIDE.U32 R18, R6, 0x40, R10 &req={0} ?trans1;
LOP3.LUT R10, R21, R16, R17, 0x96, !PT ?trans1;
MOV R11, R20 ?WAIT3_END_GROUP;
STG.E.128 desc[UR4][R18.64], R4 &req={1} ?trans4;
STG.E.128 desc[UR4][R18.64+0x20], R12 ?trans4;
STG.E.64 desc[UR4][R18.64+0x30], RZ ?trans4;
STG.E.64 desc[UR4][R18.64+0x38], RZ ?trans4;
STG.E.128 desc[UR4][R18.64+0x10], R8 ?trans1;
EXIT ?trans5;
BRA 0x530;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: setup_curand(hiprandStatePhilox4_32_10*, unsigned long, unsigned int)
_Z12setup_curandP25hiprandStatePhilox4_32_10mj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s4, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s14, s4, v[1:2]
v_mad_u64_u32 v[0:1], null, 0xcd9e8d57, v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_xor_b32_e32 v1, s2, v1
s_add_i32 s4, s2, 0x9e3779b9
s_mul_hi_u32 s5, s3, 0xcd9e8d57
s_add_i32 s6, s3, 0xbb67ae85
v_xor3_b32 v5, s5, s4, v0
v_mad_u64_u32 v[3:4], null, 0xd2511f53, v1, 0
s_mul_i32 s4, s3, 0xcd9e8d57
s_add_i32 s5, s3, 0x76cf5d0a
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, 0xd2511f53, v5, 0
v_xor_b32_e32 v6, s6, v4
s_add_i32 s6, s2, 0x3c6ef372
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor3_b32 v1, s5, v1, v3
v_mad_u64_u32 v[4:5], null, 0xcd9e8d57, v6, 0
s_add_i32 s5, s3, 0x32370b8f
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor3_b32 v3, s4, s6, v5
v_mad_u64_u32 v[5:6], null, 0xcd9e8d57, v1, 0
s_add_i32 s4, s2, 0xdaa66d2b
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[7:8], null, 0xd2511f53, v3, 0
v_xor3_b32 v3, s4, v6, v4
s_add_i32 s4, s3, 0xed9eba14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor3_b32 v6, s5, v8, v0
v_mad_u64_u32 v[0:1], null, 0xd2511f53, v3, 0
s_add_i32 s5, s2, 0x78dde6e4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, 0xcd9e8d57, v6, 0
v_xor3_b32 v1, s4, v1, v7
s_add_i32 s4, s2, 0x1715609d
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor3_b32 v8, s5, v4, v5
v_mad_u64_u32 v[4:5], null, 0xcd9e8d57, v1, 0
s_add_i32 s5, s3, 0xa9066899
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[6:7], null, 0xd2511f53, v8, 0
v_xor3_b32 v3, s4, v5, v3
s_add_i32 s4, s3, 0x646e171e
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor3_b32 v5, s5, v7, v0
v_mad_u64_u32 v[0:1], null, 0xd2511f53, v3, 0
s_add_i32 s5, s2, 0xb54cda56
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[7:8], null, 0xcd9e8d57, v5, 0
v_xor3_b32 v1, s4, v1, v6
s_add_i32 s4, s2, 0x5384540f
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor3_b32 v3, s5, v8, v4
v_mad_u64_u32 v[4:5], null, 0xcd9e8d57, v1, 0
s_add_i32 s5, s3, 0x1fd5c5a3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[8:9], null, 0xd2511f53, v3, 0
v_mov_b32_e32 v3, 0
v_xor3_b32 v1, s4, v5, v7
s_add_i32 s4, s3, 0xdb3d7428
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor3_b32 v0, s5, v9, v0
v_mad_u64_u32 v[9:10], null, 0xd2511f53, v1, 0
s_add_i32 s5, s2, 0xf1bbcdc8
v_mov_b32_e32 v1, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[11:12], null, 0xcd9e8d57, v0, 0
v_xor3_b32 v10, s4, v10, v8
v_lshlrev_b64 v[7:8], 6, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor3_b32 v4, s5, v12, v4
v_mad_u64_u32 v[5:6], null, 0xcd9e8d57, v10, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v14, vcc_lo, s0, v7
v_mad_u64_u32 v[12:13], null, 0xd2511f53, v4, 0
v_mov_b32_e32 v0, v3
v_add_co_ci_u32_e32 v15, vcc_lo, s1, v8, vcc_lo
s_add_i32 s0, s2, 0x8ff34781
s_add_i32 s1, s3, 0x96a522ad
v_xor3_b32 v4, s0, v11, v6
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v12
v_xor3_b32 v6, s1, v9, v13
global_store_b128 v[14:15], v[0:3], off
v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
v_mov_b32_e32 v2, v3
s_clause 0x2
global_store_b128 v[14:15], v[4:7], off offset:16
global_store_b128 v[14:15], v[0:3], off offset:32
global_store_b32 v[14:15], v3, off offset:48
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| setup_curand | 2,431 | 2,559 | stackv2-00000-of-00015 |
// Demangled: add(int*, int*, int*, int, int)
Function : _Z3addPiS_S_ii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
EXIT ?trans5;
BRA 0x20;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: add(int*, int*, int*, int, int)
_Z3addPiS_S_ii:
s_endpgm
| add | 95 | 15 | stackv2-00000-of-00015 |
// Demangled: add3(float*, float*, int*)
Function : _Z4add3PfS_Pi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R7, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x388] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x380] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R2, R7, 0x4, R2 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x4, R4 &req={2} ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans4;
LDG.E R7, desc[UR4][R4.64] &wr=0x2 ?trans2;
FADD R7, R2, R7 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64], R7 ?trans1;
EXIT ?trans5;
BRA 0xc0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: add3(float*, float*, int*)
_Z4add3PfS_Pi:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[2:3]
global_load_b32 v2, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| add3 | 362 | 170 | stackv2-00000-of-00015 |
// Demangled: sub3(float*, float*, int*)
Function : _Z4sub3PfS_Pi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R7, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x388] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x380] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R2, R7, 0x4, R2 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x4, R4 &req={2} ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans4;
LDG.E R7, desc[UR4][R4.64] &wr=0x3 ?trans1;
FADD R0, R2, 1 &req={2} ?WAIT4_END_GROUP;
FADD R7, R0, R7 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64], R7 ?trans1;
EXIT ?trans5;
BRA 0xd0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: sub3(float*, float*, int*)
_Z4sub3PfS_Pi:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[2:3]
global_load_b32 v2, v0, s[0:1]
s_waitcnt vmcnt(1)
v_add_f32_e32 v1, 1.0, v1
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| sub3 | 381 | 212 | stackv2-00000-of-00015 |
// Demangled: fillArray(int*, int*)
Function : _Z9fillArrayPiS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R7, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans1;
LDCU UR6, c[0x0][0x360] &wr=0x0 ?trans1;
S2R R0, SR_CTAID.X &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans5;
LDC.64 R4, c[0x0][0x388] &wr=0x3 ?trans1;
IMAD R7, R0, UR6, R7 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE R2, R7, 0x4, R2 &req={1} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &req={2} &wr=0x2 ?trans1;
IMAD.WIDE R4, R7.reuse, 0x4, R4 &req={3} ?trans1;
IADD3 R7, PT, PT, R7, R2, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64], R7 ?trans1;
EXIT ?trans5;
BRA 0xe0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: fillArray(int*, int*)
_Z9fillArrayPiS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
global_load_b32 v0, v[4:5], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, v1, v0
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| fillArray | 405 | 410 | stackv2-00000-of-00015 |
// Demangled: fillArrayUnified(int*)
Function : _Z16fillArrayUnifiedPi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R5, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans1;
LDCU UR6, c[0x0][0x360] &wr=0x0 ?trans1;
S2R R0, SR_CTAID.X &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans1;
IMAD R5, R0, UR6, R5 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE R2, R5, 0x4, R2 &req={1} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR4][R2.64] &req={2} &wr=0x2 ?trans2;
IADD3 R5, PT, PT, R5, R0, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R5 ?trans1;
EXIT ?trans5;
BRA 0xc0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: fillArrayUnified(int*)
_Z16fillArrayUnifiedPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v1, v0
global_store_b32 v[2:3], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| fillArrayUnified | 352 | 364 | stackv2-00000-of-00015 |
// Demangled: array_reverse(int*, int*, int)
Function : _Z13array_reversePiS_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R7, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
LDCU UR6, c[0x0][0x390] &wr=0x2 ?trans6;
LDC.64 R4, c[0x0][0x388] &wr=0x3 ?trans1;
IMAD.WIDE.U32 R2, R7, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E R3, desc[UR4][R2.64] &req={1} &wr=0x4 ?trans1;
LOP3.LUT R0, RZ, R7, RZ, 0x33, !PT ?WAIT4_END_GROUP;
IADD3 R7, PT, PT, R0, UR6, RZ &req={2} ?WAIT5_END_GROUP;
IMAD.WIDE R4, R7, 0x4, R4 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64], R3 &req={4} ?trans1;
EXIT ?trans5;
BRA 0xd0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: array_reverse(int*, int*, int)
_Z13array_reversePiS_i:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
s_load_b32 s0, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v1, s[4:5]
v_xad_u32 v0, v0, -1, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| array_reverse | 403 | 321 | stackv2-00000-of-00015 |
// Demangled: array_reverse_dynamic_shared(int*, int*, int)
Function : _Z28array_reverse_dynamic_sharedPiS_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R11, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x1 ?trans7;
S2UR UR5, SR_CgaCtaId &wr=0x2 ?trans1;
UMOV UR4, 0x400 ?WAIT7_END_GROUP;
LDC.64 R4, c[0x0][0x388] &wr=0x3 ?trans1;
IMAD.WIDE.U32 R2, R11, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR6][R2.64] &req={1} &rd=0x0 &wr=0x4 ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={2} ?trans1;
LOP3.LUT R6, RZ, R11, RZ, 0x33, !PT ?WAIT5_END_GROUP;
LEA R7, R11, UR4, 0x2 ?WAIT5_END_GROUP;
LDCU UR4, c[0x0][0x390] &wr=0x0 ?trans2;
IADD3 R3, PT, PT, R6, UR4, RZ &req={0} ?WAIT5_END_GROUP;
IMAD.WIDE R2, R3, 0x4, R4 &req={3} ?trans1;
STS [R7], R0 &req={4} ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R9, [R7] &wr=0x0 ?trans4;
STG.E desc[UR6][R2.64], R9 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x140;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: array_reverse_dynamic_shared(int*, int*, int)
_Z28array_reverse_dynamic_sharedPiS_i:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
s_load_b32 s0, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v1, s[4:5]
v_add_nc_u32_e32 v1, 0, v1
v_xad_u32 v0, v0, -1, s0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v2, v1
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| array_reverse_dynamic_shared | 552 | 373 | stackv2-00000-of-00015 |
// Demangled: array_reverse_shared(int*, int*, int)
Function : _Z20array_reverse_sharedPiS_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R11, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x1 ?trans7;
S2UR UR5, SR_CgaCtaId &wr=0x2 ?trans1;
UMOV UR4, 0x400 ?WAIT7_END_GROUP;
LDC.64 R4, c[0x0][0x388] &wr=0x3 ?trans1;
IMAD.WIDE.U32 R2, R11, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR6][R2.64] &req={1} &rd=0x0 &wr=0x4 ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={2} ?trans1;
LOP3.LUT R6, RZ, R11, RZ, 0x33, !PT ?WAIT5_END_GROUP;
LEA R7, R11, UR4, 0x2 ?WAIT5_END_GROUP;
LDCU UR4, c[0x0][0x390] &wr=0x0 ?trans2;
IADD3 R3, PT, PT, R6, UR4, RZ &req={0} ?WAIT5_END_GROUP;
IMAD.WIDE R2, R3, 0x4, R4 &req={3} ?trans1;
STS [R7], R0 &req={4} ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R9, [R7] &wr=0x0 ?trans4;
STG.E desc[UR6][R2.64], R9 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x140;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: array_reverse_shared(int*, int*, int)
_Z20array_reverse_sharedPiS_i:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
s_load_b32 s0, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v1, s[4:5]
v_xad_u32 v0, v0, -1, s0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v2, v1
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| array_reverse_shared | 551 | 354 | stackv2-00000-of-00015 |
// Demangled: rotateArray(int*, int)
Function : _Z11rotateArrayPii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
LDCU UR6, c[0x0][0x388] &wr=0x0 ?trans1;
S2R R7, SR_TID.X &wr=0x1 ?trans1;
UI2F.U32.RP UR4, UR6 &req={0} ?trans2;
ISETP.NE.U32.AND P1, PT, RZ, UR6, PT ?WAIT7_END_GROUP;
MUFU.RCP R0, UR4 &wr=0x0 ?trans2;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans1;
IADD3 R2, PT, PT, R0, 0xffffffe, RZ &req={0} ?trans2;
IADD3 R0, PT, PT, R7, 0x1, RZ &req={1} ?trans2;
F2I.FTZ.U32.TRUNC.NTZ R3, R2 &rd=0x0 &wr=0x1 ?trans2;
HFMA2 R2, -RZ, RZ, 0, 0 &req={0} ?trans1;
IADD3 R5, PT, PT, RZ, -R3, RZ &req={1} ?WAIT5_END_GROUP;
IMAD R5, R5, UR6, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R3, R3, R5, R2 ?trans2;
LDC.64 R4, c[0x0][0x380] &wr=0x0 ?trans4;
IMAD.HI.U32 R3, R3, R0, RZ ?WAIT5_END_GROUP;
IADD3 R3, PT, PT, -R3, RZ, RZ ?WAIT5_END_GROUP;
IMAD R3, R3, UR6, R0 ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R3, UR6, PT ?WAIT13_END_GROUP;
@P0 IADD3 R3, PT, PT, R3, -UR6, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R3, UR6, PT ?WAIT13_END_GROUP;
@P0 IADD3 R3, PT, PT, R3, -UR6, RZ ?trans2;
@!P1 LOP3.LUT R3, RZ, UR6, RZ, 0x33, !PT ?WAIT5_END_GROUP;
IMAD.WIDE.U32 R2, R3, 0x4, R4 &req={0} ?WAIT6_END_GROUP;
LDG.E R3, desc[UR4][R2.64] &req={2} &wr=0x2 ?trans1;
IMAD.WIDE.U32 R4, R7, 0x4, R4 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
STG.E desc[UR4][R4.64], R3 &req={2} ?trans1;
EXIT ?trans5;
BRA 0x1d0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: rotateArray(int*, int)
_Z11rotateArrayPii:
s_load_b32 s2, s[0:1], 0x8
v_add_nc_u32_e32 v3, 1, v0
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v1, s2
s_sub_i32 s3, 0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s3, v1
v_mul_hi_u32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v2
v_mul_hi_u32 v1, v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v1, s2
v_sub_nc_u32_e32 v1, v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s2, v1
v_cmp_le_u32_e32 vcc_lo, s2, v1
v_dual_cndmask_b32 v1, v1, v2 :: v_dual_mov_b32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v3, s2, v1
v_cmp_le_u32_e32 vcc_lo, s2, v1
v_cndmask_b32_e32 v1, v1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
s_barrier
buffer_gl0_inv
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| rotateArray | 796 | 814 | stackv2-00000-of-00015 |
// Demangled: vectorAdd(int)
Function : _Z9vectorAddi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x380] &wr=0x2 ?trans7;
LDC R9, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R9, R9, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R9, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x4][RZ] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x4][0x8] &wr=0x2 ?trans8;
LDC.64 R6, c[0x4][0x10] &wr=0x3 ?trans1;
IMAD.WIDE R2, R9, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x4 ?trans1;
IMAD.WIDE R4, R9, 0x4, R4 &req={2} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR4][R4.64] &wr=0x4 ?trans1;
IMAD.WIDE R6, R9, 0x4, R6 &req={3} ?trans1;
IADD3 R9, PT, PT, R2, R5, RZ &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x140;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: vectorAdd(int)
_Z9vectorAddi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b32 s0, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s1, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s0, v1
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v2, 31, v1
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, d_a@rel32@lo+4
s_addc_u32 s1, s1, d_a@rel32@hi+12
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, d_b@rel32@lo+4
s_addc_u32 s3, s3, d_b@rel32@hi+12
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v0, s0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, v0, s2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, d_c@rel32@lo+4
s_addc_u32 s1, s1, d_c@rel32@hi+12
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_u32 v0, vcc_lo, v0, s0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| vectorAdd | 563 | 677 | stackv2-00000-of-00015 |
// Demangled: kernel_sum(int*, int*, int*, int)
Function : _Z10kernel_sumPiS_S_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x398] &wr=0x2 ?trans7;
LDC R9, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R9, R9, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R9, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
IADD3 R11, PT, PT, R9, R9, RZ ?WAIT6_END_GROUP;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD.WIDE R2, R9, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R9 &req={1} ?trans1;
IMAD.WIDE R4, R9, 0x4, R4 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64], R11 ?trans4;
LDG.E R0, desc[UR4][R2.64] &wr=0x2 ?trans1;
IMAD.WIDE R6, R9, 0x4, R6 &req={3} ?trans1;
IADD3 R13, PT, PT, R11, R0, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R13 ?trans1;
EXIT ?trans5;
BRA 0x160;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: kernel_sum(int*, int*, int*, int)
_Z10kernel_sumPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b32_e32 v0, 1, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
global_store_b32 v[4:5], v1, off
global_store_b32 v[6:7], v0, off
global_load_b32 v1, v[4:5], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, v1, v0
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| kernel_sum | 611 | 613 | stackv2-00000-of-00015 |
// Demangled: mandelKernel(float, float, float, float, int*, int, int, int, unsigned long, unsigned long)
Function : _Z12mandelKernelffffPiiiimm
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R5, SR_TID.Y &wr=0x1 ?trans7;
LDC R2, c[0x0][0x360] &wr=0x2 ?trans1;
LDCU UR7, c[0x0][0x3b0] &wr=0x3 ?trans1;
S2R R3, SR_TID.X &wr=0x2 ?trans1;
LDCU UR6, c[0x0][0x3a8] &wr=0x4 ?trans5;
S2UR UR5, SR_CTAID.Y &wr=0x1 ?trans1;
LDCU.64 UR8, c[0x0][0x398] &wr=0x5 ?trans7;
LDC R0, c[0x0][0x364] &wr=0x1 ?trans8;
S2UR UR4, SR_CTAID.X &wr=0x2 ?trans1;
IMAD R0, R0, UR5, R5 &req={1} ?WAIT4_END_GROUP;
IMAD R0, R0, UR7, RZ &req={3} ?trans2;
IMAD R2, R2, UR4, R3 &req={2} ?WAIT3_END_GROUP;
ISETP.GE.AND P0, PT, R0, UR9, PT &req={5} ?trans1;
IMAD R2, R2, UR6, RZ &req={4} ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R2, UR8, P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDCU.64 UR4, c[0x0][0x3b0] &wr=0x0 ?trans1;
SHF.R.S32.HI R7, RZ, 0x1f, R0 ?trans1;
MOV R6, R0 ?WAIT5_END_GROUP;
IADD.64 R4, R6, UR4 &req={0} ?WAIT6_END_GROUP;
ISETP.GT.U64.AND P0, PT, R4, R6, PT ?WAIT14_END_GROUP;
@!P0 EXIT ?trans5;
LDCU.64 UR8, c[0x0][0x3a8] &wr=0x0 ?trans1;
SHF.R.S32.HI R3, RZ, 0x1f, R2 ?trans1;
LDCU UR4, c[0x0][0x3a0] &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x2 ?trans3;
IADD.64 R6, R2, UR8 &req={0} ?trans2;
UIADD3 UR4, UPT, UPT, -UR4, URZ, URZ &req={1} ?WAIT12_END_GROUP;
ISETP.GT.U64.AND P0, PT, R6, R2, PT ?trans2;
BSSY.RECONVERGENT B0, 0x5e0 ?WAIT12_END_GROUP;
@!P0 BRA 0x5d0 &req={1} ?trans5;
LDCU UR8, c[0x0][0x3a0] &wr=0x0 ?trans1;
LDC R9, c[0x0][0x384] &wr=0x1 ?trans1;
I2FP.F32.S32 R8, R0 ?trans1;
LDCU UR5, c[0x0][0x38c] &wr=0x1 ?trans1;
ISETP.LT.AND P0, PT, RZ, UR8, PT &req={0} ?WAIT3_END_GROUP;
FFMA R17, R8, UR5, R9 &req={1} ?WAIT10_END_GROUP;
@P0 BRA 0x330 ?trans5;
LDC R13, c[0x0][0x398] &wr=0x0 ?trans1;
MOV R10, R2 ?WAIT7_END_GROUP;
ISETP.GE.AND P0, PT, R10, R13, PT &req={0} ?WAIT13_END_GROUP;
@!P0 LDC.64 R8, c[0x0][0x390] &wr=0x0 ?trans1;
@!P0 IMAD R11, R0, R13, R10 ?trans1;
IADD3 R10, PT, PT, R10, 0x1, RZ ?WAIT3_END_GROUP;
@!P0 IMAD.WIDE R8, R11, 0x4, R8 &req={0} ?trans1;
SHF.R.S32.HI R11, RZ, 0x1f, R10 ?WAIT4_END_GROUP;
@!P0 STG.E desc[UR6][R8.64], RZ &req={2} &rd=0x1 ?trans1;
ISETP.GT.U64.AND P0, PT, R6, R10, PT ?WAIT14_END_GROUP;
@P0 BRA 0x290 &req={1} ?trans5;
BRA 0x5d0 ?trans5;
MOV R11, R2 ?WAIT7_END_GROUP;
LDCU UR5, c[0x0][0x398] &wr=0x0 ?trans1;
BSSY.RECONVERGENT B1, 0x580 ?trans1;
ISETP.GE.AND P0, PT, R11, UR5, PT &req={0} ?WAIT13_END_GROUP;
@P0 BRA 0x570 &req={1} ?trans5;
LDC R9, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU UR5, c[0x0][0x388] &wr=0x0 ?trans1;
I2FP.F32.S32 R8, R11 ?trans1;
BSSY.RECONVERGENT B2, 0x520 ?trans1;
MOV R18, UR4 ?WAIT4_END_GROUP;
LDC R16, c[0x0][0x3a0] &wr=0x1 ?trans1;
FFMA R15, R8, UR5, R9 &req={0} ?trans1;
HFMA2 R8, -RZ, RZ, 0, 0 ?trans1;
MOV R9, R17 ?WAIT3_END_GROUP;
MOV R10, R15 ?WAIT7_END_GROUP;
FMUL R14, R10, R10 ?trans1;
FMUL R19, R9, R9 ?trans1;
MOV R13, R8 ?WAIT3_END_GROUP;
FADD R12, R14, R19 ?WAIT5_END_GROUP;
FSETP.GT.AND P0, PT, R12, 4, PT ?WAIT13_END_GROUP;
@P0 BRA 0x510 ?trans5;
IADD3 R18, PT, PT, R18, 0x1, RZ ?trans1;
FADD R12, R10, R10 ?trans1;
FADD R10, R14, -R19 ?trans1;
IADD3 R8, PT, PT, R8, 0x1, RZ ?trans2;
ISETP.NE.AND P0, PT, R18, RZ, PT ?trans1;
FFMA R9, R12, R9, R17 ?trans1;
FADD R10, R15, R10 ?WAIT11_END_GROUP;
@P0 BRA 0x420 ?trans5;
MOV R13, R16 &req={1} ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 &req={2} ?trans5;
LDC.64 R8, c[0x0][0x390] &wr=0x0 ?trans1;
LDCU UR5, c[0x0][0x398] &wr=0x2 ?trans2;
IMAD R15, R0, UR5, R11 &req={2} ?WAIT4_END_GROUP;
IMAD.WIDE R8, R15, 0x4, R8 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R8.64], R13 &rd=0x0 ?trans2;
BSYNC.RECONVERGENT B1 &req={2} ?trans5;
IADD3 R11, PT, PT, R11, 0x1, RZ ?WAIT4_END_GROUP;
SHF.R.S32.HI R9, RZ, 0x1f, R11 &req={0} ?trans1;
MOV R8, R11 ?WAIT5_END_GROUP;
ISETP.GT.U64.AND P0, PT, R6, R8, PT ?WAIT14_END_GROUP;
@P0 BRA 0x340 ?trans5;
BSYNC.RECONVERGENT B0 &req={2} ?trans5;
LDCU UR5, c[0x0][0x39c] &wr=0x0 ?trans1;
IADD3 R0, PT, PT, R0, 0x1, RZ ?WAIT4_END_GROUP;
SHF.R.S32.HI R9, RZ, 0x1f, R0 ?trans1;
MOV R8, R0 ?WAIT5_END_GROUP;
ISETP.GT.U64.AND P1, PT, R4, R8, PT ?trans2;
ISETP.GE.AND P0, PT, R0, UR5, PT &req={0} ?WAIT13_END_GROUP;
@!P0 BRA P1, 0x1d0 ?trans5;
EXIT ?trans5;
BRA 0x660;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: mandelKernel(float, float, float, float, int*, int, int, int, unsigned long, unsigned long)
_Z12mandelKernelffffPiiiimm:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b256 s[4:11], s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s14, s2, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s3, v[0:1]
v_mul_lo_u32 v0, v2, s8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v3, s10
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v2
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_16
v_ashrrev_i32_e32 v3, 31, v2
v_add_co_u32 v4, vcc_lo, v2, s10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v3, vcc_lo
v_cmp_gt_u64_e32 vcc_lo, v[4:5], v[2:3]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_16
s_clause 0x1
s_load_b128 s[12:15], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v1, 31, v0
v_add_co_u32 v6, vcc_lo, v0, s8
s_cmp_gt_i32 s6, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v1, vcc_lo
s_cselect_b32 s7, -1, 0
v_cmp_gt_u64_e64 s0, v[6:7], v[0:1]
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_15
v_cvt_f32_i32_e32 v3, v2
v_mul_lo_u32 v1, v2, s4
v_mov_b32_e32 v8, v0
s_mov_b32 s9, 0
s_waitcnt lgkmcnt(0)
v_fma_f32 v3, v3, s15, s13
.LBB0_5:
s_mov_b32 s10, exec_lo
v_cmpx_gt_i32_e64 s4, v8
s_cbranch_execz .LBB0_14
s_and_not1_b32 vcc_lo, exec_lo, s7
s_cbranch_vccnz .LBB0_12
v_cvt_f32_i32_e32 v9, v8
v_mov_b32_e32 v10, v3
s_mov_b32 s11, 0
s_mov_b32 s16, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v9, v9, s14, s12
v_mov_b32_e32 v12, v9
.LBB0_8:
v_mul_f32_e32 v13, v10, v10
s_or_b32 s17, s17, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v11, v12, v12, v13
v_cmp_nlt_f32_e32 vcc_lo, 4.0, v11
v_mov_b32_e32 v11, s16
s_and_saveexec_b32 s18, vcc_lo
s_cbranch_execz .LBB0_10
v_mul_f32_e32 v11, v12, v12
v_add_f32_e32 v12, v12, v12
s_add_i32 s16, s16, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s6, s16
v_sub_f32_e32 v13, v11, v13
s_cselect_b32 s19, -1, 0
v_mov_b32_e32 v11, s6
v_fma_f32 v10, v10, v12, v3
s_and_not1_b32 s17, s17, exec_lo
v_add_f32_e32 v12, v9, v13
s_and_b32 s19, s19, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s17, s17, s19
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s18
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s18, exec_lo, s17
s_or_b32 s11, s18, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_8
s_or_b32 exec_lo, exec_lo, s11
s_branch .LBB0_13
.LBB0_12:
v_mov_b32_e32 v11, 0
.LBB0_13:
v_add_nc_u32_e32 v9, v8, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s2, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
global_store_b32 v[9:10], v11, off
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s10
v_add_nc_u32_e32 v8, 1, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v9, 31, v8
v_cmp_le_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_5
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v2, 1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_cmp_le_i32_e64 s1, s5, v2
v_cmp_le_u64_e32 vcc_lo, v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s1, s1, vcc_lo
s_and_b32 s1, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s8, s1, s8
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_3
.LBB0_16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| mandelKernel | 2,414 | 2,430 | stackv2-00000-of-00015 |
// Demangled: multithreads_inverse_calculate(double*, double*, double, int, int, int, int, int)
Function : _Z30multithreads_inverse_calculatePdS_diiiii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x398] &wr=0x2 ?trans7;
LDC R0, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R0, R0, UR4, R3 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R8, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x1 ?trans1;
HFMA2 R2, -RZ, RZ, 0, 5.9604644775390625e-08 ?trans1;
LDCU UR4, c[0x0][0x3a8] &wr=0x2 ?trans5;
LDC R17, c[0x0][0x3a0] &wr=0x3 ?trans1;
LDCU UR5, c[0x0][0x3a4] &wr=0x2 ?trans7;
LDC R18, c[0x0][0x39c] &wr=0x4 ?trans1;
IMAD.WIDE R8, R0, 0x8, R8 &req={0} ?WAIT6_END_GROUP;
LDG.E.64 R8, desc[UR6][R8.64] &req={1} &wr=0x5 ?trans1;
UIMAD UR4, UR4, UR5, URZ &req={2} ?trans1;
IABS R16, R17 &req={3} ?trans1;
BSSY.RECONVERGENT B0, 0x5f0 ?trans3;
I2F.RP R12, R16 &wr=0x0 ?trans1;
IABS R15, R18 &req={4} ?trans1;
I2F.F64 R10, R18 &wr=0x1 ?trans1;
MUFU.RCP R12, R12 &req={0} ?trans1;
MUFU.RCP64H R3, R9 &req={5} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R4, -R8, R2, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R4, R4, R4, R4 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R4, R2, R4, R2 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R6, -R8, R4, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R6, R4, R6, R4 &req={0} &rd=0x0 &wr=0x1 ?trans2;
IADD3 R4, PT, PT, R12, 0xffffffe, RZ &req={0} ?WAIT4_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R5, R4 &rd=0x0 &wr=0x2 ?trans2;
MOV R4, RZ &req={0} ?trans1;
IADD3 R13, PT, PT, RZ, -R5, RZ &req={2} ?WAIT5_END_GROUP;
IMAD R13, R13, R16, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R5, R5, R13, R4 ?WAIT6_END_GROUP;
IMAD.HI.U32 R14, R5, R15, RZ ?WAIT15_END_GROUP;
NOP ?WAIT10_END_GROUP;
NOP ?WAIT15_END_GROUP;
I2F.F64 R4, UR4 &wr=0x0 ?trans1;
IADD3 R19, PT, PT, -R14, RZ, RZ ?WAIT5_END_GROUP;
IMAD R15, R16, R19, R15 ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P1, PT, R16, R15, PT ?WAIT13_END_GROUP;
@!P1 IADD3 R15, PT, PT, R15, -R16, RZ ?trans2;
@!P1 IADD3 R14, PT, PT, R14, 0x1, RZ ?WAIT15_END_GROUP;
NOP ?WAIT8_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R2, R10, R6 &req={1} &wr=0x1 ?trans1;
ISETP.GE.U32.AND P0, PT, R15, R16, PT ?trans1;
LOP3.LUT R15, R18, R17, RZ, 0x3c, !PT ?WAIT5_END_GROUP;
ISETP.GE.AND P1, PT, R15, RZ, PT ?WAIT7_END_GROUP;
@P0 IADD3 R14, PT, PT, R14, 0x1, RZ ?trans1;
ISETP.NE.AND P0, PT, R17, RZ, PT ?WAIT5_END_GROUP;
@!P1 IADD3 R14, PT, PT, -R14, RZ, RZ ?trans1;
FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ?WAIT7_END_GROUP;
@!P0 LOP3.LUT R14, RZ, R17, RZ, 0x33, !PT ?WAIT15_END_GROUP;
NOP ?WAIT6_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, -R8, R2, R10 &req={1} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R6, R12, R2 &req={1} &wr=0x1 ?trans2;
FFMA R12, RZ, R9, R3 &req={1} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
I2F.F64 R6, R14 &rd=0x1 &wr=0x2 ?trans1;
FSETP.GT.AND P0, PT, |R12|, 1.469367938527859385e-39, PT ?WAIT13_END_GROUP;
@P0 BRA P1, 0x5e0 &req={1,0} ?trans5;
MOV R14, 0x5e0 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0xa30 &req={2} ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
LDCU UR4, c[0x0][0x394] &wr=0x0 ?trans1;
DADD R6, R6, -R2 &req={2} &rd=0x1 &wr=0x2 ?trans1;
BSSY.RECONVERGENT B0, 0x9e0 ?trans1;
MOV R2, 0x1 &req={1} ?trans1;
MUFU.RCP64H R3, UR4 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?trans1;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R8, R6, R4 &req={2} &rd=0x1 &wr=0x2 ?trans2;
LDC.64 R6, c[0x0][0x390] &req={1} &wr=0x0 ?trans1;
FSETP.GEU.AND P1, PT, |R9|, 6.5827683646048100446e-37, PT &req={2} ?WAIT15_END_GROUP;
NOP ?trans1;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R4, R2, -R6, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R4, R4, R4, R4 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R4, R2, R4, R2 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R4, -R6, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R4, R2, R4 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R4, R8, R2 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R6, R4, -R6, R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R2, R6, R4 &req={0} &wr=0x0 ?trans2;
FFMA R4, RZ, UR4, R3 &req={0} ?WAIT5_END_GROUP;
FSETP.GT.AND P0, PT, |R4|, 1.469367938527859385e-39, PT ?WAIT13_END_GROUP;
@P0 BRA P1, 0x9d0 ?trans5;
LDCU.64 UR4, c[0x0][0x390] &wr=0x0 ?trans1;
MOV R10, R8 ?trans1;
MOV R11, R9 ?trans1;
MOV R14, 0x9d0 ?trans1;
MOV R8, UR4 &req={0} ?trans1;
MOV R9, UR5 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0xa30 ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
LDC.64 R4, c[0x0][0x388] &wr=0x0 ?trans1;
DMUL R2, R2, 100 &wr=0x1 ?trans1;
IMAD.WIDE R4, R0, 0x8, R4 &req={0} ?WAIT5_END_GROUP;
STG.E.64 desc[UR6][R4.64], R2 &req={1} ?trans1;
EXIT ?trans5;
FSETP.GEU.AND P2, PT, |R11|.reuse, 1.469367938527859385e-39, PT ?trans1;
LOP3.LUT R16, R11, 0x7ff00000, RZ, 0xc0, !PT ?trans1;
BSSY.RECONVERGENT B1, 0x1220 ?trans1;
LOP3.LUT R17, R9.reuse, 0x7ff00000, RZ, 0xc0, !PT ?trans1;
MOV R15, 0x1ca00000 ?trans1;
FSETP.GEU.AND P0, PT, |R9|.reuse, 1.469367938527859385e-39, PT ?trans1;
LOP3.LUT R2, R9, 0x800fffff, RZ, 0xc0, !PT ?trans2;
ISETP.GE.U32.AND P1, PT, R16, R17, PT ?trans1;
MOV R12, R10 ?trans1;
LOP3.LUT R3, R2, 0x3ff00000, RZ, 0xfc, !PT ?WAIT3_END_GROUP;
@!P2 LOP3.LUT R13, R9, 0x7ff00000, RZ, 0xc0, !PT ?trans1;
@!P2 MOV R22, RZ ?trans1;
MOV R2, R8 ?trans1;
MOV R25, R16 ?trans2;
@!P2 ISETP.GE.U32.AND P3, PT, R16, R13, PT ?trans1;
SEL R13, R15.reuse, 0x63400000, !P1 ?trans1;
MOV R24, R17 ?trans1;
MOV R18, 0x1 ?trans1;
@!P0 DMUL R2, R8, 8.98846567431157953865e+307 &wr=0x0 ?trans1;
@!P2 SEL R23, R15, 0x63400000, !P3 ?trans1;
LOP3.LUT R13, R13, 0x800fffff, R11, 0xf8, !PT ?trans1;
MUFU.RCP64H R19, R3 &req={0} &wr=0x0 ?trans1;
@!P0 LOP3.LUT R24, R3, 0x7ff00000, RZ, 0xc0, !PT ?WAIT2_END_GROUP;
@!P2 LOP3.LUT R23, R23, 0x80000000, R11, 0xf8, !PT ?trans2;
IADD3 R26, PT, PT, R24, -0x1, RZ ?trans2;
@!P2 LOP3.LUT R23, R23, 0x100000, RZ, 0xfc, !PT ?WAIT15_END_GROUP;
NOP ?WAIT9_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
@!P2 DFMA R12, R12, 2, -R22 &wr=0x1 ?trans2;
@!P2 LOP3.LUT R25, R13, 0x7ff00000, RZ, 0xc0, !PT &req={1} ?WAIT4_END_GROUP;
IADD3 R17, PT, PT, R25, -0x1, RZ ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R17, 0x7feffffe, PT ?WAIT5_END_GROUP;
ISETP.GT.U32.OR P0, PT, R26, 0x7feffffe, P0 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R20, R18, -R2, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R20, R20, R20, R20 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R20, R18, R20, R18 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R20, -R2, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R20, R18, R20 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R20, R18, R12 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R22, R20, -R2, R12 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R18, R22, R20 &req={0} &rd=0x0 &wr=0x1 ?trans2;
@P0 BRA 0x10d0 &req={1,0} ?trans5;
LOP3.LUT R11, R9, 0x7ff00000, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R10, PT, PT, R16.reuse, -R11.reuse, RZ ?trans1;
ISETP.GE.U32.AND P0, PT, R16, R11, PT ?WAIT4_END_GROUP;
VIMNMX.S32 R10, R10, -0x46a00000, !PT ?trans1;
SEL R15, R15, 0x63400000, !P0 ?WAIT4_END_GROUP;
VIMNMX.S32 R10, R10, 0x46a00000, PT ?WAIT5_END_GROUP;
IADD3 R15, PT, PT, -R15, R10, RZ ?trans1;
MOV R10, RZ ?WAIT3_END_GROUP;
IADD3 R11, PT, PT, R15, 0x7fe00000, RZ ?WAIT6_END_GROUP;
DMUL R16, R18, R10 &wr=0x0 ?trans2;
FSETP.GTU.AND P0, PT, |R17|, 1.469367938527859385e-39, PT &req={0} ?WAIT13_END_GROUP;
@P0 BRA 0x1210 ?trans5;
DFMA R2, R18, -R2, R12 &wr=0x0 ?trans1;
MOV R10, RZ ?trans1;
FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT &req={0} ?trans1;
LOP3.LUT R9, R3, 0x80000000, R9, 0x48, !PT ?WAIT4_END_GROUP;
LOP3.LUT R11, R9, R11, RZ, 0xfc, !PT ?WAIT8_END_GROUP;
@!P0 BRA 0x1210 ?trans5;
IADD3 R3, PT, PT, -R15, RZ, RZ ?trans1;
MOV R2, RZ ?trans1;
DMUL.RP R10, R18, R10 &wr=0x0 ?trans2;
LOP3.LUT R9, R11, R9, RZ, 0x3c, !PT &req={0} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R16, -R2, R18 &wr=0x0 ?trans2;
IADD3 R2, PT, PT, -R15, -0x43300000, RZ &req={0} ?WAIT5_END_GROUP;
FSETP.NEU.AND P0, PT, |R3|, R2, PT ?WAIT5_END_GROUP;
FSEL R16, R10, R16, !P0 ?trans1;
FSEL R17, R9, R17, !P0 ?trans1;
BRA 0x1210 ?trans6;
DSETP.NAN.AND P0, PT, R10, R10, PT &wr=0x0 ?trans2;
@P0 BRA 0x11f0 &req={0} ?trans5;
DSETP.NAN.AND P0, PT, R8, R8, PT &wr=0x0 ?trans2;
@P0 BRA 0x11c0 &req={0} ?trans5;
ISETP.NE.AND P0, PT, R25, R24, PT ?trans1;
MOV.64 R16, 0xfff8000000000000 ?WAIT12_END_GROUP;
@!P0 BRA 0x1210 ?trans5;
ISETP.NE.AND P0, PT, R25, 0x7ff00000, PT ?trans1;
LOP3.LUT R17, R11, 0x80000000, R9, 0x48, !PT ?WAIT4_END_GROUP;
ISETP.EQ.OR P0, PT, R24, RZ, !P0 ?WAIT13_END_GROUP;
@P0 LOP3.LUT R2, R17, 0x7ff00000, RZ, 0xfc, !PT ?trans1;
@!P0 MOV R16, RZ ?trans1;
@P0 MOV R16, RZ ?WAIT3_END_GROUP;
@P0 MOV R17, R2 ?trans1;
BRA 0x1210 ?trans6;
LOP3.LUT R17, R9, 0x80000, RZ, 0xfc, !PT ?trans1;
MOV R16, R8 ?trans1;
BRA 0x1210 ?trans6;
LOP3.LUT R17, R11, 0x80000, RZ, 0xfc, !PT ?trans1;
MOV R16, R10 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B1 ?trans5;
HFMA2 R15, -RZ, RZ, 0, 0 ?trans1;
MOV R2, R16 ?trans1;
MOV R3, R17 ?trans2;
RET.REL.NODEC R14 0x0 ?trans5;
BRA 0x1260;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: multithreads_inverse_calculate(double*, double*, double, int, int, int, int, int)
_Z30multithreads_inverse_calculatePdS_diiiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b128 s[8:11], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
v_cvt_f64_i32_e32 v[4:5], s9
s_ashr_i32 s12, s9, 31
s_load_b32 s0, s[0:1], 0x28
s_add_i32 s9, s9, s12
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_xor_b32 s9, s9, s12
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
s_ashr_i32 s4, s10, 31
s_mul_i32 s0, s0, s11
s_add_i32 s5, s10, s4
global_load_b64 v[2:3], v[2:3], off
s_xor_b32 s5, s5, s4
s_xor_b32 s4, s12, s4
s_sub_i32 s10, 0, s5
s_waitcnt vmcnt(0)
v_div_scale_f64 v[6:7], null, v[2:3], v[2:3], v[4:5]
v_div_scale_f64 v[12:13], vcc_lo, v[4:5], v[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[10:11], v[12:13], v[8:9]
v_fma_f64 v[6:7], -v[6:7], v[10:11], v[12:13]
v_cvt_f32_u32_e32 v12, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_rcp_iflag_f32_e32 v12, v12
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v12, 0x4f7ffffe, v12
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[10:11]
v_cvt_u32_f32_e32 v8, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s8, v8
s_mul_i32 s10, s10, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s10, s8, s10
s_add_i32 s8, s8, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s8, s9, s8
s_mul_i32 s10, s8, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s9, s9, s10
s_add_i32 s10, s8, 1
s_sub_i32 s12, s9, s5
s_cmp_ge_u32 s9, s5
s_cselect_b32 s8, s10, s8
s_cselect_b32 s9, s12, s9
s_add_i32 s10, s8, 1
s_cmp_ge_u32 s9, s5
s_cselect_b32 s5, s10, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s5, s5, s4
s_sub_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cvt_f64_i32_e32 v[8:9], s4
v_div_fixup_f64 v[2:3], v[6:7], v[2:3], v[4:5]
v_cvt_f64_i32_e32 v[4:5], s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[8:9], -v[2:3]
v_mul_f64 v[2:3], v[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[4:5], null, s[2:3], s[2:3], v[2:3]
v_rcp_f64_e32 v[6:7], v[4:5]
s_waitcnt_depctr 0xfff
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_div_scale_f64 v[8:9], vcc_lo, v[2:3], s[2:3], v[2:3]
v_mul_f64 v[10:11], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[2:3], v[4:5], s[2:3], v[2:3]
v_mul_f64 v[2:3], 0x40590000, v[2:3]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| multithreads_inverse_calculate | 5,982 | 2,343 | stackv2-00000-of-00015 |
// Demangled: multithreads_normal_calculate(double*, double*, int, int, int, int)
Function : _Z29multithreads_normal_calculatePdS_iiii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x390] &wr=0x2 ?trans7;
LDC R0, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R0, R0, UR4, R3 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x394] &wr=0x2 ?trans1;
IMAD.WIDE R2, R0, 0x8, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E.64 R2, desc[UR6][R2.64] &req={1} &wr=0x3 ?trans1;
I2F.F64 R4, UR4 &req={2} &wr=0x3 ?trans1;
LDCU.64 UR4, c[0x0][0x398] &wr=0x0 ?trans1;
BSSY.RECONVERGENT B0, 0x500 ?trans1;
UIMAD UR4, UR5, UR4, URZ &req={0} ?WAIT15_END_GROUP;
NOP ?trans1;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
I2F.F64 R8, UR4 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R6, R2, -R4 &req={3} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R8, R8, R6 &req={0} &rd=0x0 &wr=0x1 ?trans2;
MUFU.RCP64H R7, R5 &req={0} &wr=0x0 ?trans1;
MOV R6, 0x1 ?trans1;
FSETP.GEU.AND P1, PT, |R9|, 6.5827683646048100446e-37, PT &req={1} ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, -R4, R6, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R10, R10, R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R6, R10, R6 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, -R4, R10, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R10, R2, R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R6, R8, R2 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, -R4, R6, R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R2, R10, R6 &req={0} &wr=0x0 ?trans2;
FFMA R6, RZ, R5, R3 &req={0} ?WAIT5_END_GROUP;
FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ?WAIT13_END_GROUP;
@P0 BRA P1, 0x4f0 ?trans5;
MOV R6, 0x4f0 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x550 ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
LDC.64 R4, c[0x0][0x388] &wr=0x0 ?trans1;
DMUL R2, R2, 100 &wr=0x1 ?trans1;
IMAD.WIDE R4, R0, 0x8, R4 &req={0} ?WAIT5_END_GROUP;
STG.E.64 desc[UR6][R4.64], R2 &req={1} ?trans1;
EXIT ?trans5;
FSETP.GEU.AND P0, PT, |R5|.reuse, 1.469367938527859385e-39, PT ?trans1;
LOP3.LUT R2, R5, 0x800fffff, RZ, 0xc0, !PT ?trans1;
BSSY.RECONVERGENT B1, 0xd10 ?trans1;
FSETP.GEU.AND P2, PT, |R9|.reuse, 1.469367938527859385e-39, PT ?trans1;
MOV R12, 0x1 ?trans1;
LOP3.LUT R3, R2, 0x3ff00000, RZ, 0xfc, !PT ?trans1;
MOV R2, R4 ?trans1;
LOP3.LUT R7, R9, 0x7ff00000, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R20, R5, 0x7ff00000, RZ, 0xc0, !PT ?trans1;
MOV R14, 0x1ca00000 ?WAIT3_END_GROUP;
@!P0 DMUL R2, R4, 8.98846567431157953865e+307 &wr=0x0 ?trans1;
MOV R21, R7 ?trans1;
MUFU.RCP64H R13, R3 &req={0} &wr=0x0 ?trans1;
ISETP.GE.U32.AND P1, PT, R7, R20, PT ?trans1;
@!P2 MOV R16, RZ ?trans1;
@!P0 LOP3.LUT R20, R3, 0x7ff00000, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R22, PT, PT, R20, -0x1, RZ ?WAIT15_END_GROUP;
NOP ?WAIT10_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R12, -R2, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R10, R10, R10 &req={0} &rd=0x0 ?trans2;
@!P2 LOP3.LUT R10, R5, 0x7ff00000, RZ, 0xc0, !PT &req={0} ?trans1;
SEL R11, R14, 0x63400000, !P1 ?WAIT4_END_GROUP;
@!P2 ISETP.GE.U32.AND P3, PT, R7, R10, PT ?trans1;
MOV R10, R8 ?trans1;
LOP3.LUT R11, R11, 0x800fffff, R9, 0xf8, !PT ?WAIT3_END_GROUP;
@!P2 SEL R15, R14, 0x63400000, !P3 ?WAIT5_END_GROUP;
@!P2 LOP3.LUT R15, R15, 0x80000000, R9, 0xf8, !PT ?WAIT4_END_GROUP;
@!P2 LOP3.LUT R17, R15, 0x100000, RZ, 0xfc, !PT ?WAIT15_END_GROUP;
NOP ?WAIT13_END_GROUP;
NOP ?WAIT15_END_GROUP;
@!P2 DFMA R10, R10, 2, -R16 &wr=0x0 ?trans2;
@!P2 LOP3.LUT R21, R11, 0x7ff00000, RZ, 0xc0, !PT &req={0} ?WAIT4_END_GROUP;
IADD3 R15, PT, PT, R21, -0x1, RZ ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R15, 0x7feffffe, PT ?WAIT5_END_GROUP;
ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R12, R18, R12 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, R18, -R2, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, R18, R12, R18 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R16, R12, R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R16, -R2, R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, R12, R18, R16 &req={0} &rd=0x0 &wr=0x1 ?trans2;
@P0 BRA 0xbc0 &req={1,0} ?trans5;
LOP3.LUT R16, R5, 0x7ff00000, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R8, PT, PT, R7.reuse, -R16.reuse, RZ ?trans1;
ISETP.GE.U32.AND P0, PT, R7, R16, PT ?WAIT4_END_GROUP;
VIMNMX.S32 R8, R8, -0x46a00000, !PT ?trans1;
SEL R7, R14, 0x63400000, !P0 ?WAIT4_END_GROUP;
VIMNMX.S32 R8, R8, 0x46a00000, PT ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, -R7, R8, RZ ?trans1;
MOV R8, RZ ?WAIT3_END_GROUP;
IADD3 R9, PT, PT, R7, 0x7fe00000, RZ ?WAIT6_END_GROUP;
DMUL R14, R12, R8 &wr=0x0 ?trans2;
FSETP.GTU.AND P0, PT, |R15|, 1.469367938527859385e-39, PT &req={0} ?WAIT13_END_GROUP;
@P0 BRA 0xd00 ?trans5;
DFMA R2, R12, -R2, R10 &wr=0x0 ?trans1;
MOV R8, RZ ?trans1;
FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT &req={0} ?trans1;
LOP3.LUT R5, R3, 0x80000000, R5, 0x48, !PT ?WAIT4_END_GROUP;
LOP3.LUT R9, R5, R9, RZ, 0xfc, !PT ?WAIT8_END_GROUP;
@!P0 BRA 0xd00 ?trans5;
IADD3 R3, PT, PT, -R7.reuse, RZ, RZ ?trans1;
MOV R2, RZ ?trans1;
IADD3 R7, PT, PT, -R7, -0x43300000, RZ ?trans1;
DMUL.RP R8, R12, R8 &wr=0x0 ?trans2;
LOP3.LUT R5, R9, R5, RZ, 0x3c, !PT &req={0} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R14, -R2, R12 &wr=0x0 ?trans2;
FSETP.NEU.AND P0, PT, |R3|, R7, PT &req={0} ?WAIT5_END_GROUP;
FSEL R14, R8, R14, !P0 ?trans1;
FSEL R15, R5, R15, !P0 ?trans1;
BRA 0xd00 ?trans6;
DSETP.NAN.AND P0, PT, R8, R8, PT &wr=0x0 ?trans2;
@P0 BRA 0xce0 &req={0} ?trans5;
DSETP.NAN.AND P0, PT, R4, R4, PT &wr=0x0 ?trans2;
@P0 BRA 0xcb0 &req={0} ?trans5;
ISETP.NE.AND P0, PT, R21, R20, PT ?trans1;
MOV.64 R14, 0xfff8000000000000 ?WAIT12_END_GROUP;
@!P0 BRA 0xd00 ?trans5;
ISETP.NE.AND P0, PT, R21, 0x7ff00000, PT ?trans1;
LOP3.LUT R15, R9, 0x80000000, R5, 0x48, !PT ?WAIT4_END_GROUP;
ISETP.EQ.OR P0, PT, R20, RZ, !P0 ?WAIT13_END_GROUP;
@P0 LOP3.LUT R2, R15, 0x7ff00000, RZ, 0xfc, !PT ?trans1;
@!P0 MOV R14, RZ ?trans1;
@P0 MOV R14, RZ ?WAIT3_END_GROUP;
@P0 MOV R15, R2 ?trans1;
BRA 0xd00 ?trans6;
LOP3.LUT R15, R5, 0x80000, RZ, 0xfc, !PT ?trans1;
MOV R14, R4 ?trans1;
BRA 0xd00 ?trans6;
LOP3.LUT R15, R9, 0x80000, RZ, 0xfc, !PT ?trans1;
MOV R14, R8 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B1 ?trans5;
HFMA2 R7, -RZ, RZ, 0, 0 ?trans1;
MOV R2, R14 ?trans1;
MOV R3, R15 ?trans2;
RET.REL.NODEC R6 0x0 ?trans5;
BRA 0xd50;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: multithreads_normal_calculate(double*, double*, int, int, int, int)
_Z29multithreads_normal_calculatePdS_iiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_cvt_f64_i32_e32 v[4:5], s5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
s_mul_i32 s0, s7, s6
v_cvt_f64_i32_e32 v[6:7], s0
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], -v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[2:3], v[2:3], v[6:7]
v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_div_scale_f64 v[10:11], vcc_lo, v[2:3], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[12:13], v[10:11], v[8:9]
v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_div_fixup_f64 v[2:3], v[6:7], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_mul_f64 v[2:3], 0x40590000, v[2:3]
global_store_b64 v[0:1], v[2:3], off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| multithreads_normal_calculate | 4,322 | 1,177 | stackv2-00000-of-00015 |
// Demangled: bedSlopeSourceSolver(float*, float*, float*, int, int, float, float)
Function : _Z20bedSlopeSourceSolverPfS_S_iiff
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.Y &wr=0x1 ?trans7;
S2UR UR6, SR_CTAID.Y &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x398] &wr=0x2 ?trans1;
S2R R5, SR_TID.X &wr=0x3 ?trans6;
LDC R0, c[0x0][0x364] &wr=0x1 ?trans8;
S2UR UR7, SR_CTAID.X &wr=0x3 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, -0x1, URZ &req={2} ?WAIT7_END_GROUP;
LDC R2, c[0x0][0x360] &wr=0x3 ?trans1;
IMAD R0, R0, UR6, R3 &req={1} ?trans1;
UIADD3 UR6, UPT, UPT, UR5, -0x1, URZ ?WAIT4_END_GROUP;
ISETP.NE.AND P0, PT, R0, RZ, PT ?trans1;
IMAD R3, R2, UR7, R5 &req={3} ?WAIT5_END_GROUP;
ISETP.LT.OR P0, PT, R3, 0x1, !P0 ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R3, UR6, P0 ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R0, UR4, P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R4, c[0x0][0x390] &wr=0x0 ?trans1;
IMAD R3, R0.reuse, UR5, R3 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x1 ?trans4;
IADD3 R8, PT, PT, R0, R3, RZ ?trans2;
LDC.64 R6, c[0x0][0x388] &wr=0x2 ?trans2;
IADD3 R9, PT, PT, R8, R8, RZ ?WAIT6_END_GROUP;
LDC R13, c[0x0][0x3a0] &wr=0x3 ?trans1;
IMAD.WIDE R4, R9, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
LDG.E R10, desc[UR6][R4.64+0x4] &req={1} &wr=0x4 ?trans4;
LDG.E R11, desc[UR6][R4.64+0xc] &wr=0x4 ?trans1;
IMAD R9, R3, 0x3, RZ ?WAIT4_END_GROUP;
IMAD.WIDE R6, R9, 0x4, R6 &req={2} ?WAIT5_END_GROUP;
LDG.E R2, desc[UR6][R6.64] &rd=0x0 &wr=0x2 ?trans1;
MUFU.RCP R0, R13 &req={3} &wr=0x1 ?trans1;
BSSY.RECONVERGENT B0, 0x320 ?trans1;
IADD3 R8, PT, PT, R8, UR5, RZ ?trans2;
IADD3 R7, PT, PT, R3, R3, RZ &req={0} ?trans1;
FFMA R9, R0, -R13, 1 &req={1} ?WAIT4_END_GROUP;
FFMA R9, R0, R9, R0 ?trans1;
FADD R0, -R10.reuse, R11.reuse &req={4} ?trans1;
FADD R11, R10, R11 ?WAIT3_END_GROUP;
FCHK P0, R0, R13 &wr=0x0 ?trans1;
FFMA R12, R0, R9, RZ ?WAIT4_END_GROUP;
FFMA R10, R12, -R13, R0 ?trans1;
FFMA R2, R11, -0.5, R2 &req={2} ?WAIT3_END_GROUP;
FFMA R6, R9, R10, R12 ?trans1;
@!P0 BRA 0x310 &req={0} ?trans6;
LDCU UR4, c[0x0][0x3a0] &wr=0x0 ?trans1;
MOV R10, 0x300 ?trans1;
MOV R3, UR4 &req={0} ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x500 ?trans5;
MOV R6, R3 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
LDC.64 R10, c[0x0][0x390] &wr=0x0 ?trans1;
IADD3 R9, PT, PT, R8, 0x2, R8 ?trans1;
LDG.E R5, desc[UR6][R4.64] &wr=0x2 ?trans6;
LDC R13, c[0x0][0x3a4] &wr=0x1 ?trans1;
IMAD.WIDE R8, R9, 0x4, R10 &req={0} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR6][R8.64] &wr=0x2 ?trans1;
MUFU.RCP R3, R13 &req={1} &wr=0x0 ?trans1;
BSSY.RECONVERGENT B0, 0x470 ?trans1;
FFMA R10, R3, -R13, 1 &req={0} ?WAIT4_END_GROUP;
FFMA R3, R3, R10, R3 ?trans1;
FADD R0, R0, -R5 &req={2} ?WAIT4_END_GROUP;
FCHK P0, R0, R13 &wr=0x0 ?trans1;
FFMA R10, R0, R3, RZ ?WAIT4_END_GROUP;
FFMA R11, R10, -R13, R0 ?WAIT4_END_GROUP;
FFMA R3, R3, R11, R10 ?trans1;
@!P0 BRA 0x460 &req={0} ?trans6;
LDCU UR4, c[0x0][0x3a4] &wr=0x0 ?trans1;
MOV R10, 0x460 ?trans1;
MOV R3, UR4 &req={0} ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x500 ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
LDC.64 R4, c[0x0][0x380] &wr=0x0 ?trans1;
FMUL R9, R6, -9.8100004196166992188 ?trans1;
FMUL R3, R3, -9.8100004196166992188 ?WAIT3_END_GROUP;
FMUL R9, R2.reuse, R9 ?trans1;
FMUL R3, R2, R3 ?trans1;
IMAD.WIDE R4, R7, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R4.64], R9 ?trans4;
STG.E desc[UR6][R4.64+0x4], R3 ?trans1;
EXIT ?trans5;
SHF.R.U32.HI R11, RZ, 0x17, R3 ?trans1;
BSSY.RECONVERGENT B1, 0xb40 ?trans1;
SHF.R.U32.HI R9, RZ, 0x17, R0 ?trans2;
LOP3.LUT R16, R11, 0xff, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R14, R9, 0xff, RZ, 0xc0, !PT ?trans2;
IADD3 R12, PT, PT, R16, -0x1, RZ ?trans2;
IADD3 R11, PT, PT, R14, -0x1, RZ ?WAIT3_END_GROUP;
ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ?WAIT5_END_GROUP;
ISETP.GT.U32.OR P0, PT, R11, 0xfd, P0 ?WAIT13_END_GROUP;
@!P0 MOV R9, RZ ?trans1;
@!P0 BRA 0x720 ?trans6;
FSETP.GTU.FTZ.AND P0, PT, |R0|, +INF , PT ?trans1;
FSETP.GTU.FTZ.AND P1, PT, |R3|, +INF , PT ?WAIT5_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, PT, 0xf8, 0x8f ?WAIT13_END_GROUP;
@P0 BRA 0xb20 ?trans5;
LOP3.LUT P0, RZ, R3, 0x7fffffff, R0, 0xc8, !PT ?WAIT13_END_GROUP;
@!P0 BRA 0xb00 ?trans5;
FSETP.NEU.FTZ.AND P2, PT, |R0|.reuse, +INF , PT ?trans1;
FSETP.NEU.FTZ.AND P1, PT, |R3|, +INF , PT ?trans1;
FSETP.NEU.FTZ.AND P0, PT, |R0|, +INF , PT ?WAIT12_END_GROUP;
@!P1 BRA !P2, 0xb00 ?trans5;
LOP3.LUT P2, RZ, R0, 0x7fffffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P1, PT, P1, P2, PT, 0x2f, 0xf2 ?WAIT13_END_GROUP;
@P1 BRA 0xae0 ?trans5;
LOP3.LUT P1, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, PT, 0x2f, 0xf2 ?WAIT13_END_GROUP;
@P0 BRA 0xab0 ?trans5;
ISETP.GE.AND P0, PT, R11, RZ, PT ?trans1;
ISETP.GE.AND P1, PT, R12, RZ, PT ?WAIT12_END_GROUP;
@P0 MOV R9, RZ ?trans1;
@!P0 MOV R9, 0xffffffc0 ?trans1;
@!P0 FFMA R0, R0, 1.84467440737095516160e+19, RZ ?trans1;
@!P1 FFMA R3, R3, 1.84467440737095516160e+19, RZ ?WAIT3_END_GROUP;
@!P1 IADD3 R9, PT, PT, R9, 0x40, RZ ?WAIT7_END_GROUP;
LEA R12, R16, 0xc0800000, 0x17 ?trans1;
BSSY.RECONVERGENT B2, 0xaa0 ?trans3;
IADD3 R12, PT, PT, -R12, R3, RZ ?trans2;
IADD3 R3, PT, PT, R14, -0x7f, RZ ?trans2;
MUFU.RCP R11, R12 &rd=0x0 &wr=0x1 ?trans1;
FADD.FTZ R13, -R12, -RZ ?trans2;
IMAD R0, R3.reuse, -0x800000, R0 ?trans1;
IADD3 R12, PT, PT, R3, 0x7f, -R16 &req={0} ?WAIT4_END_GROUP;
IADD3 R12, PT, PT, R12, R9, RZ ?trans1;
FFMA R14, R11, R13, 1 &req={1} ?WAIT4_END_GROUP;
FFMA R18, R11, R14, R11 ?WAIT4_END_GROUP;
FFMA R11, R0, R18, RZ ?WAIT4_END_GROUP;
FFMA R14, R13, R11, R0 ?WAIT4_END_GROUP;
FFMA R15, R18, R14, R11 ?WAIT4_END_GROUP;
FFMA R14, R13, R15, R0 ?WAIT4_END_GROUP;
FFMA R11, R18, R14, R15 ?WAIT5_END_GROUP;
SHF.R.U32.HI R0, RZ, 0x17, R11 ?WAIT4_END_GROUP;
LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R13, PT, PT, R0, R12, RZ ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R13, -0x1, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R0, 0xfe, PT ?WAIT13_END_GROUP;
@!P0 BRA 0xa80 ?trans5;
ISETP.GT.AND P0, PT, R13, 0xfe, PT ?WAIT13_END_GROUP;
@P0 BRA 0xa50 ?trans5;
ISETP.GE.AND P0, PT, R13, 0x1, PT ?WAIT13_END_GROUP;
@P0 BRA 0xa90 ?trans5;
ISETP.GE.AND P0, PT, R13, -0x18, PT ?trans1;
LOP3.LUT R11, R11, 0x80000000, RZ, 0xc0, !PT ?WAIT12_END_GROUP;
@!P0 BRA 0xa90 ?trans5;
FFMA.RZ R0, R18.reuse, R14.reuse, R15.reuse ?trans1;
IADD3 R12, PT, PT, R13.reuse, 0x20, RZ ?trans1;
FFMA.RM R3, R18, R14.reuse, R15.reuse ?trans1;
ISETP.NE.AND P1, PT, R13.reuse, RZ, PT ?trans1;
ISETP.NE.AND P2, PT, R13.reuse, RZ, PT ?trans1;
LOP3.LUT R0, R0, 0x7fffff, RZ, 0xc0, !PT ?trans2;
IADD3 R13, PT, PT, -R13, RZ, RZ ?trans2;
LOP3.LUT R9, R0, 0x800000, RZ, 0xfc, !PT ?trans1;
FFMA.RP R0, R18, R14, R15 ?WAIT3_END_GROUP;
SHF.L.U32 R12, R9, R12, RZ ?trans2;
FSETP.NEU.FTZ.AND P0, PT, R0, R3, PT ?trans1;
SEL R0, R13, RZ, P2 ?trans2;
ISETP.NE.AND P1, PT, R12, RZ, P1 ?WAIT3_END_GROUP;
SHF.R.U32.HI R0, RZ, R0, R9 ?trans2;
PLOP3.LUT P0, PT, P0, P1, PT, 0xf8, 0x8f ?trans2;
SHF.R.U32.HI R12, RZ, 0x1, R0 ?WAIT3_END_GROUP;
SEL R3, RZ, 0x1, !P0 ?WAIT5_END_GROUP;
LOP3.LUT R3, R3, 0x1, R12, 0xf8, !PT ?WAIT4_END_GROUP;
LOP3.LUT R3, R3, R0, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R12, PT, PT, R12, R3, RZ ?WAIT4_END_GROUP;
LOP3.LUT R11, R12, R11, RZ, 0xfc, !PT ?trans1;
BRA 0xa90 ?trans6;
LOP3.LUT R11, R11, 0x80000000, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
LOP3.LUT R11, R11, 0x7f800000, RZ, 0xfc, !PT ?trans1;
BRA 0xa90 ?trans6;
IMAD R11, R12, 0x800000, R11 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
BRA 0xb30 ?trans5;
LOP3.LUT R0, R3, 0x80000000, R0, 0x48, !PT ?WAIT4_END_GROUP;
LOP3.LUT R11, R0, 0x7f800000, RZ, 0xfc, !PT ?trans1;
BRA 0xb30 ?trans6;
LOP3.LUT R11, R3, 0x80000000, R0, 0x48, !PT ?trans1;
BRA 0xb30 ?trans6;
MUFU.RSQ R11, -QNAN &wr=0x0 ?trans1;
BRA 0xb30 ?trans5;
FADD.FTZ R11, R0, R3 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B1 ?trans5;
MOV R3, R11 &req={0} ?trans1;
HFMA2 R11, -RZ, RZ, 0, 0 ?WAIT4_END_GROUP;
RET.REL.NODEC R10 0x0 ?trans5;
BRA 0xb70;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: bedSlopeSourceSolver(float*, float*, float*, int, int, float, float)
_Z20bedSlopeSourceSolverPfS_S_iiff:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
s_add_i32 s2, s5, -1
s_add_i32 s3, s4, -1
v_min_i32_e32 v2, v0, v1
v_cmp_gt_i32_e32 vcc_lo, s2, v1
v_cmp_gt_i32_e64 s2, s3, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_i32_e64 s3, 0, v2
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_mad_u64_u32 v[2:3], null, v0, s5, v[1:2]
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b128 s[8:11], s[0:1], 0x0
s_add_i32 s4, s5, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v2, v0
v_lshlrev_b32_e32 v0, 1, v1
v_add_lshl_u32 v3, v1, s4, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_clause 0x2
global_load_b64 v[5:6], v[0:1], off
global_load_b32 v7, v[0:1], off offset:12
global_load_b32 v3, v[3:4], off
v_lshl_add_u32 v0, v2, 1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
global_load_b32 v4, v[0:1], off
s_waitcnt vmcnt(2)
v_dual_sub_f32 v1, v7, v6 :: v_dual_add_f32 v6, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v0, null, s6, s6, v1
v_div_scale_f32 v12, vcc_lo, v1, s6, v1
v_rcp_f32_e32 v8, v0
s_waitcnt_depctr 0xfff
v_fma_f32 v10, -v0, v8, 1.0
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v3, v3, v5 :: v_dual_fmac_f32 v8, v10, v8
v_div_scale_f32 v5, null, s7, s7, v3
v_div_scale_f32 v10, s0, v3, s7, v3
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v4, -0.5, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v9, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v11, -v5, v9, 1.0
v_fmac_f32_e32 v9, v11, v9
v_mul_f32_e32 v11, v12, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v14, -v0, v11, v12
v_fmac_f32_e32 v11, v14, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v12, -v0, v11, v12
v_dual_mul_f32 v13, v10, v9 :: v_dual_lshlrev_b32 v0, 1, v2
v_fma_f32 v15, -v5, v13, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v13, v15, v9
v_fma_f32 v2, -v5, v13, v10
v_div_fmas_f32 v5, v12, v8, v11
s_mov_b32 vcc_lo, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fmas_f32 v2, v2, v9, v13
v_div_fixup_f32 v5, v5, s6, v1
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fixup_f32 v2, v2, s7, v3
v_mul_f32_e32 v3, 0xc11cf5c3, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_dual_mul_f32 v5, 0xc11cf5c3, v2 :: v_dual_mul_f32 v2, v3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_mul_f32_e32 v3, v4, v5
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| bedSlopeSourceSolver | 4,526 | 2,377 | stackv2-00000-of-00015 |
// Demangled: res2fred(int, int, float*, float*)
Function : _Z8res2frediiPfS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
LDC R0, c[0x0][0x380] &wr=0x1 ?trans1;
S2R R2, SR_TID.X &wr=0x2 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x3 ?trans6;
S2UR UR6, SR_CTAID.X &wr=0x4 ?trans8;
LDC R9, c[0x0][0x360] &wr=0x2 ?trans1;
IADD3 R0, PT, PT, R0, -0x1, RZ &req={1} ?WAIT5_END_GROUP;
ISETP.LE.AND P0, PT, R0, UR6, PT &req={4} ?trans1;
IMAD R9, R9, UR6, R2 &req={2} ?WAIT12_END_GROUP;
@P0 BRA 0x220 &req={3,0} ?trans5;
LDCU UR6, c[0x0][0x384] &wr=0x0 ?trans1;
HFMA2 R11, -RZ, RZ, 0, 0 ?trans2;
IMAD R0, R0, UR6, RZ &req={0} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, 0x4, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x260 ?trans5;
LDC.64 R2, c[0x0][0x390] &wr=0x0 ?trans8;
LDC.64 R6, c[0x0][0x388] &wr=0x1 ?trans1;
IMAD.WIDE R2, R9, 0x4, R2 &req={0} ?WAIT7_END_GROUP;
SHF.R.U32.HI R8, RZ, 0x1, R0 ?trans1;
BSSY.RECONVERGENT B0, 0x1d0 ?trans4;
ISETP.GE.AND P0, PT, R9, R8, PT ?WAIT13_END_GROUP;
@P0 BRA 0x1c0 &req={0} ?trans5;
IADD3 R5, PT, PT, R9, R8, RZ ?trans1;
LDG.E R13, desc[UR4][R2.64] &wr=0x2 ?trans4;
IMAD.WIDE R4, R5, 0x4, R6 &req={1} ?WAIT6_END_GROUP;
LDG.E R4, desc[UR4][R4.64] &wr=0x2 ?trans2;
FADD R13, R4, R13 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R13 &rd=0x0 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P0, PT, R0, 0x7, PT ?trans1;
MOV R0, R8 ?WAIT12_END_GROUP;
@P0 BRA 0x120 ?trans5;
BRA 0x260 ?trans5;
LDC.64 R2, c[0x0][0x388] &wr=0x0 ?trans2;
IMAD.WIDE R2, R9, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &wr=0x2 ?trans2;
FADD R11, RZ, R2 &req={2} ?WAIT7_END_GROUP;
LDC R5, c[0x0][0x380] &wr=0x2 ?trans8;
LDC.64 R2, c[0x0][0x390] &req={0} &wr=0x2 ?trans2;
IMAD.WIDE R2, R5, 0x4, R2 &req={2} ?WAIT6_END_GROUP;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
STG.E desc[UR4][R2.64+-0x4], R11 ?trans1;
EXIT ?trans5;
BRA 0x2c0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: res2fred(int, int, float*, float*)
_Z8res2frediiPfS_:
s_clause 0x2
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b128 s[0:3], s[0:1], 0x8
s_mov_b32 s7, -1
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
s_add_i32 s6, s4, -1
s_cmp_ge_i32 s15, s6
s_cbranch_scc0 .LBB1_2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s7, 0
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, 0, v0
s_branch .LBB1_3
.LBB1_2:
.LBB1_3:
s_and_not1_b32 vcc_lo, exec_lo, s7
s_cbranch_vccnz .LBB1_10
s_mul_i32 s5, s6, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s5, 4
s_cbranch_scc1 .LBB1_9
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
.LBB1_6:
s_lshr_b32 s6, s5, 1
s_mov_b32 s7, exec_lo
v_cmpx_gt_i32_e64 s6, v1
s_cbranch_execz .LBB1_8
v_add_nc_u32_e32 v4, s6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v4
global_store_b32 v[2:3], v0, off
.LBB1_8:
s_or_b32 exec_lo, exec_lo, s7
s_cmp_lt_u32 s5, 8
s_mov_b32 s5, s6
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_6
.LBB1_9:
v_mov_b32_e32 v0, 0
.LBB1_10:
s_ashr_i32 s5, s4, 31
v_mov_b32_e32 v1, 0
s_lshl_b64 s[0:1], s[4:5], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
s_barrier
buffer_gl0_inv
global_store_b32 v1, v0, s[0:1] offset:-4
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| res2fred | 1,109 | 1,239 | stackv2-00000-of-00015 |
// Demangled: solve(int, float*, float*, float*, float*)
Function : _Z5solveiPfS_S_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans8;
LDC R2, c[0x0][0x360] &wr=0x1 ?trans8;
LDC R4, c[0x0][0x380] &wr=0x2 ?trans1;
IMAD R2, R2, UR4, R3 &req={1} ?trans1;
IADD3 R9, PT, PT, R4, 0x2, RZ &req={2} ?WAIT5_END_GROUP;
ISETP.GT.AND P0, PT, R2, R9, PT ?WAIT13_END_GROUP;
@!P0 EXIT &req={0} ?trans5;
IMAD R7, R9, R4, R9 ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R2, R7, PT ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
IABS R8, R9.reuse ?trans2;
IABS R10, R9 ?trans2;
I2F.RP R0, R8 &wr=0x0 ?trans2;
IADD3 R10, PT, PT, RZ, -R10, RZ ?trans1;
MUFU.RCP R0, R0 &req={0} &wr=0x0 ?trans2;
IADD3 R6, PT, PT, R0, 0xffffffe, RZ &req={0} ?trans2;
IABS R0, R2 ?WAIT2_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R7, R6 &rd=0x0 &wr=0x1 ?trans2;
HFMA2 R6, -RZ, RZ, 0, 0 &req={0} ?trans1;
IADD3 R11, PT, PT, RZ, -R7, RZ &req={1} ?WAIT5_END_GROUP;
IMAD R11, R11, R8, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R7, R7, R11, R6 ?WAIT6_END_GROUP;
IMAD.HI.U32 R7, R7, R0, RZ ?WAIT4_END_GROUP;
IMAD R7, R7, R10, R0 ?trans1;
IADD3 R0, PT, PT, R4, 0x1, RZ ?WAIT4_END_GROUP;
ISETP.GT.U32.AND P0, PT, R8, R7, PT ?WAIT13_END_GROUP;
@!P0 IADD3 R7, PT, PT, R7, -R8, RZ ?trans1;
ISETP.GE.AND P0, PT, R2, RZ, PT ?WAIT4_END_GROUP;
ISETP.GT.U32.AND P1, PT, R8, R7, PT ?WAIT13_END_GROUP;
@!P1 IADD3 R7, PT, PT, R7, -R8, RZ ?trans1;
ISETP.NE.AND P1, PT, R9, RZ, PT ?WAIT3_END_GROUP;
@!P0 IADD3 R7, PT, PT, -R7, RZ, RZ ?WAIT10_END_GROUP;
@!P1 LOP3.LUT R7, RZ, R9, RZ, 0x33, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R7, RZ, PT ?WAIT5_END_GROUP;
ISETP.EQ.OR P0, PT, R7, R0, !P0 ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LDCU.64 UR6, c[0x0][0x388] &wr=0x0 ?trans1;
LDC.64 R6, c[0x0][0x388] &wr=0x1 ?trans1;
SHF.R.S32.HI R5, RZ, 0x1f, R4 ?trans2;
SHF.R.S32.HI R3, RZ, 0x1f, R2 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans4;
LDC.64 R12, c[0x0][0x398] &wr=0x3 ?trans1;
IADD.64 R14, R2, -R4 ?WAIT2_END_GROUP;
IADD.64 R4, R2, R4 ?WAIT5_END_GROUP;
LEA R10, P1, R4, UR6, 0x2 &req={0} ?trans2;
LEA R8, P0, R14, UR6, 0x2 ?trans2;
LEA.HI.X R11, R4, UR7, R5, 0x2, P1 ?trans2;
LEA.HI.X R9, R14, UR7, R15, 0x2, P0 ?trans1;
IMAD.WIDE R4, R2, 0x4, R6 &req={1} ?WAIT3_END_GROUP;
LDG.E R11, desc[UR4][R10.64+0x8] &req={2} &wr=0x2 ?trans4;
LDG.E R8, desc[UR4][R8.64+-0x8] &wr=0x2 ?trans1;
IMAD.WIDE R6, R2, 0x4, R12 &req={3} ?trans2;
LDC.64 R12, c[0x0][0x390] &wr=0x0 ?trans1;
LDG.E R3, desc[UR4][R4.64+-0x4] &wr=0x3 ?trans4;
LDG.E R15, desc[UR4][R4.64+0x4] &wr=0x4 ?trans4;
LDG.E R7, desc[UR4][R6.64] &wr=0x5 ?trans4;
LDG.E R17, desc[UR4][R4.64] &wr=0x5 ?trans1;
FADD R0, -R8, -R11 &req={2} ?WAIT4_END_GROUP;
FADD R0, R0, -R3 &req={3} ?WAIT4_END_GROUP;
FADD R0, R0, -R15 &req={4} ?WAIT4_END_GROUP;
FADD R0, -R0, R7 &req={5} ?trans1;
IMAD.WIDE R8, R2, 0x4, R12 &req={0} ?trans1;
LDC.64 R6, c[0x0][0x3a0] &wr=0x0 ?trans3;
FMUL.D2 R0, R0, 0.25 ?WAIT4_END_GROUP;
FFMA R17, R17, 0.5, R0 ?WAIT5_END_GROUP;
STG.E desc[UR4][R8.64], R17 ?trans4;
LDG.E R0, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE R2, R2, 0x4, R6 &req={0} ?WAIT4_END_GROUP;
FADD R0, R17, -R0 &req={2} ?WAIT4_END_GROUP;
FMUL R7, R0, R0 ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R7 ?trans1;
EXIT ?trans5;
BRA 0x4a0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: solve(int, float*, float*, float*, float*)
_Z5solveiPfS_S_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s8, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_add_i32 s3, s8, 2
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e64 s3, v1
s_cbranch_execz .LBB0_4
s_add_i32 s2, s8, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s4, s3, s2
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_4
s_ashr_i32 s4, s3, 31
v_ashrrev_i32_e32 v2, 31, v1
s_add_i32 s3, s3, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s3, s3, s4
v_add_nc_u32_e32 v4, v1, v2
v_cvt_f32_u32_e32 v0, s3
s_sub_i32 s4, 0, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v4, v2
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v3, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v0, v3
v_add_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v4, v0
v_mul_lo_u32 v0, v0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v4, v0
v_subrev_nc_u32_e32 v3, s3, v0
v_cmp_le_u32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
v_subrev_nc_u32_e32 v3, s3, v0
v_cmp_le_u32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
v_xor_b32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v2
v_cmp_ne_u32_e32 vcc_lo, s2, v0
v_cmp_ne_u32_e64 s2, 0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_4
s_load_b256 s[0:7], s[0:1], 0x8
s_ashr_i32 s9, s8, 31
v_sub_co_u32 v3, vcc_lo, v1, s8
v_subrev_co_ci_u32_e32 v4, vcc_lo, s9, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, v1, s8
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_lshlrev_b64 v[7:8], 2, v[1:2]
v_lshlrev_b64 v[0:1], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v8, vcc_lo
s_clause 0x2
global_load_b32 v3, v[2:3], off offset:-8
global_load_b32 v6, v[0:1], off offset:8
global_load_b96 v[0:2], v[4:5], off offset:-4
v_add_co_u32 v9, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v8, vcc_lo
global_load_b32 v9, v[9:10], off
s_waitcnt vmcnt(2)
v_sub_f32_e64 v3, -v3, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v0, v3, v0
v_sub_f32_e32 v0, v0, v2
v_add_co_u32 v2, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v8, vcc_lo
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v0, v9, v0
v_mul_f32_e32 v0, 0x3e800000, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v0, 0.5, v0
v_fmac_f32_e32 v0, 0.5, v1
global_store_b32 v[2:3], v0, off
global_load_b32 v1, v[4:5], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v0, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v2, v0, v0
v_add_co_u32 v0, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v8, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| solve | 1,888 | 2,209 | stackv2-00000-of-00015 |
// Demangled: lud_diagonal(float*, int, int)
Function : _Z12lud_diagonalPfii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R8, SR_TID.X &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x3 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x4 ?trans1;
IADD3 R0, PT, PT, R4, 0x1, RZ &req={2} ?WAIT5_END_GROUP;
IMAD R5, R0, R5, R8 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R30, R5.reuse, 0x4, R2 &req={4} ?trans1;
IADD3 R33, PT, PT, R5, R4, RZ ?WAIT4_END_GROUP;
LDG.E R0, desc[UR6][R30.64] &req={3} &rd=0x1 &wr=0x2 ?trans1;
IADD3 R35, PT, PT, R33.reuse, R4, RZ ?trans1;
IMAD.WIDE.U32 R32, R33, 0x4, R2 ?WAIT3_END_GROUP;
IADD3 R25, PT, PT, R35.reuse, R4.reuse, RZ ?trans2;
LDG.E R5, desc[UR6][R32.64] &rd=0x3 &wr=0x4 ?trans1;
IMAD.WIDE.U32 R34, R35, 0x4, R2 ?trans1;
IADD3 R27, PT, PT, R25, R4, RZ ?WAIT4_END_GROUP;
LDG.E R9, desc[UR6][R34.64] &wr=0x5 ?trans1;
IADD3 R29, PT, PT, R27, R4, RZ ?WAIT4_END_GROUP;
IADD3 R11, PT, PT, R29, R4, RZ ?WAIT4_END_GROUP;
IADD3 R7, PT, PT, R11, R4, RZ ?WAIT4_END_GROUP;
IADD3 R17, PT, PT, R7, R4, RZ ?WAIT4_END_GROUP;
IADD3 R19, PT, PT, R17, R4, RZ ?WAIT4_END_GROUP;
IADD3 R21, PT, PT, R19, R4, RZ ?WAIT4_END_GROUP;
IADD3 R23, PT, PT, R21, R4, RZ ?WAIT4_END_GROUP;
IADD3 R15, PT, PT, R23, R4, RZ ?trans1;
IMAD.WIDE.U32 R10, R11, 0x4, R2 ?WAIT3_END_GROUP;
IADD3 R31, PT, PT, R15, R4.reuse, RZ &req={1} ?trans1;
IMAD.WIDE.U32 R24, R25, 0x4, R2.reuse ?trans2;
LDG.E R10, desc[UR6][R10.64] &rd=0x1 &wr=0x5 ?trans1;
IADD3 R33, PT, PT, R31, R4.reuse, RZ &req={3} ?trans1;
IMAD.WIDE.U32 R26, R27, 0x4, R2.reuse ?trans2;
LDG.E R12, desc[UR6][R24.64] &wr=0x3 ?trans2;
IMAD.WIDE.U32 R28, R29, 0x4, R2.reuse ?trans2;
LDG.E R13, desc[UR6][R26.64] &wr=0x3 ?trans1;
IADD3 R11, PT, PT, R33, R4, RZ &req={1} ?trans1;
IMAD.WIDE.U32 R6, R7, 0x4, R2 ?WAIT2_END_GROUP;
LDG.E R14, desc[UR6][R28.64] &rd=0x1 &wr=0x3 ?trans2;
IMAD.WIDE.U32 R16, R17, 0x4, R2.reuse ?trans2;
LDG.E R6, desc[UR6][R6.64] &wr=0x3 ?trans2;
IMAD.WIDE.U32 R18, R19, 0x4, R2.reuse ?trans2;
LDG.E R16, desc[UR6][R16.64] &wr=0x3 ?trans2;
IMAD.WIDE.U32 R20, R21, 0x4, R2 ?WAIT2_END_GROUP;
LDG.E R18, desc[UR6][R18.64] &rd=0x0 &wr=0x3 ?trans2;
IMAD.WIDE.U32 R22, R23, 0x4, R2.reuse ?trans2;
LDG.E R20, desc[UR6][R20.64] &wr=0x3 ?trans2;
IMAD.WIDE.U32 R28, R15, 0x4, R2.reuse &req={1} ?trans2;
LDG.E R22, desc[UR6][R22.64] &wr=0x3 ?trans2;
IMAD.WIDE.U32 R26, R31, 0x4, R2 ?WAIT2_END_GROUP;
LDG.E R28, desc[UR6][R28.64] &wr=0x3 ?trans2;
IMAD.WIDE.U32 R24, R33, 0x4, R2.reuse ?trans2;
LDG.E R26, desc[UR6][R26.64] &wr=0x3 ?trans2;
IMAD.WIDE.U32 R2, R11, 0x4, R2 ?trans2;
LDG.E R24, desc[UR6][R24.64] &wr=0x3 ?trans4;
LDG.E R30, desc[UR6][R2.64] &rd=0x1 &wr=0x3 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x0 ?trans1;
UMOV UR4, 0x400 ?WAIT2_END_GROUP;
ULEA UR5, UR5, UR4, 0x18 &req={0} ?WAIT6_END_GROUP;
LEA R19, R8.reuse, UR5, 0x2 ?trans2;
LEA R7, R8, UR5, 0x6 ?trans1;
MOV R2, 0x1 &req={1} ?trans1;
PRMT R4, RZ, 0x7610, R4 ?trans2;
IADD3 R7, PT, PT, R7, 0x10, RZ ?trans1;
STS [R19], R0 &req={2} ?trans4;
STS [R19+0x40], R5 &req={4} &rd=0x0 ?trans4;
STS [R19+0x80], R9 &req={5} ?trans1;
HFMA2 R5, -RZ, RZ, 0, 0 &req={0} ?WAIT3_END_GROUP;
STS [R19+0x180], R10 ?trans4;
STS [R19+0xc0], R12 &req={3} ?trans4;
STS [R19+0x100], R13 ?trans4;
STS [R19+0x140], R14 ?trans4;
STS [R19+0x1c0], R6 &rd=0x0 ?trans4;
STS [R19+0x200], R16 &rd=0x1 ?trans4;
STS [R19+0x240], R18 &rd=0x1 ?trans4;
STS [R19+0x280], R20 &rd=0x1 ?trans4;
STS [R19+0x2c0], R22 &rd=0x1 ?trans4;
STS [R19+0x300], R28 &rd=0x1 ?trans4;
STS [R19+0x340], R26 &rd=0x1 ?trans4;
STS [R19+0x380], R24 &rd=0x1 ?trans4;
STS [R19+0x3c0], R30 &rd=0x1 ?trans1;
PRMT R6, RZ, 0x7610, R6 &req={0} ?trans1;
IMAD R10, R8, 0x3c, R19 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
ISETP.GT.U32.AND P0, PT, R8, R5, PT ?trans1;
IADD3 R3, PT, PT, R6.reuse, 0x1, RZ ?trans1;
BSSY.RECONVERGENT B0, 0xcf0 ?trans1;
PRMT R0, R6, 0x7610, R0 &req={4,3,2} ?trans2;
PRMT R6, R3, 0x7610, R6 ?WAIT8_END_GROUP;
@!P0 BRA 0xce0 &req={0} ?trans5;
ISETP.NE.AND P0, PT, R5.reuse, RZ, PT ?trans1;
LEA R12, R5.reuse, UR5, 0x2 ?trans1;
IMAD R9, R5, 0x4, R10 ?WAIT11_END_GROUP;
@!P0 LDS R16, [R10] &req={1} &rd=0x0 &wr=0x1 ?trans1;
@!P0 BRA 0xbd0 ?trans5;
LDS R16, [R9] &req={1} &rd=0x1 &wr=0x2 ?trans1;
ISETP.GE.U32.AND P0, PT, R5.reuse, 0x8, PT ?trans1;
HFMA2 R11, -RZ, RZ, 0, 0 ?trans1;
LOP3.LUT P1, RZ, R5, 0x7, RZ, 0xc0, !PT ?WAIT11_END_GROUP;
@!P0 BRA 0x8d0 &req={1} ?trans5;
LOP3.LUT R14, R5, 0xfffffff8, RZ, 0xc0, !PT ?trans2;
IADD3 R13, PT, PT, R12, 0x100, RZ ?trans1;
MOV R11, RZ ?trans1;
MOV R3, R7 ?trans1;
IADD3 R14, PT, PT, -R14, RZ, RZ ?WAIT7_END_GROUP;
LDS R15, [R3+-0x10] ?trans1;
IADD3 R14, PT, PT, R14, 0x8, RZ ?trans2;
IADD3 R11, PT, PT, R11, 0x8, RZ ?trans1;
LDS R17, [R13+-0x100] &req={1} &wr=0x1 ?trans2;
ISETP.NE.AND P0, PT, R14, RZ, PT ?trans1;
FFMA R16, -R15, R17, R16 &req={2,1} ?WAIT5_END_GROUP;
STS [R9], R16 ?trans4;
LDS R15, [R3+-0xc] ?trans4;
LDS R17, [R13+-0xc0] &wr=0x1 ?trans2;
FFMA R18, -R15, R17, R16 &req={1} ?WAIT5_END_GROUP;
STS [R9], R18 ?trans4;
LDS R15, [R3+-0x8] ?trans4;
LDS R17, [R13+-0x80] &wr=0x1 ?trans2;
FFMA R20, -R15, R17, R18 &req={1} ?WAIT5_END_GROUP;
STS [R9], R20 ?trans4;
LDS R15, [R3+-0x4] ?trans4;
LDS R17, [R13+-0x40] &wr=0x1 ?trans2;
FFMA R16, -R15, R17, R20 &req={1} ?WAIT5_END_GROUP;
STS [R9], R16 ?trans4;
LDS R15, [R3] ?trans4;
LDS R17, [R13] &wr=0x1 ?trans2;
FFMA R18, -R15, R17, R16 &req={1} ?WAIT5_END_GROUP;
STS [R9], R18 ?trans4;
LDS R15, [R3+0x4] ?trans4;
LDS R17, [R13+0x40] &wr=0x1 ?trans2;
FFMA R20, -R15, R17, R18 &req={1} ?WAIT5_END_GROUP;
STS [R9], R20 ?trans4;
LDS R15, [R3+0x8] ?trans4;
LDS R17, [R13+0x80] &wr=0x1 ?trans2;
FFMA R22, -R15, R17, R20 &req={1} ?WAIT5_END_GROUP;
STS [R9], R22 ?trans4;
LDS R15, [R3+0xc] &rd=0x1 ?trans4;
LDS R16, [R13+0xc0] &rd=0x2 &wr=0x3 ?trans1;
IADD3 R3, PT, PT, R3, 0x20, RZ &req={1} ?trans2;
IADD3 R13, PT, PT, R13, 0x200, RZ &req={2} ?trans1;
FFMA R16, -R15, R16, R22 &req={3} ?WAIT5_END_GROUP;
STS [R9], R16 &rd=0x1 ?trans1;
@P0 BRA 0x670 ?trans5;
@!P1 BRA 0xbd0 ?trans5;
LOP3.LUT R0, R0, 0x7, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
LOP3.LUT P1, RZ, R0.reuse, 0x3, RZ, 0xc0, !PT ?trans2;
IADD3 R3, PT, PT, R0, -0x1, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ?WAIT13_END_GROUP;
@!P0 BRA 0xa60 ?trans5;
IMAD R0, R11.reuse, 0x4, R10 ?trans2;
IMAD R13, R11.reuse, 0x40, R12 ?trans1;
IADD3 R11, PT, PT, R11, 0x4, RZ ?trans2;
LDS R3, [R0] ?trans4;
LDS R14, [R13] &wr=0x3 ?trans2;
FFMA R14, -R3, R14, R16 &req={3,2} ?WAIT5_END_GROUP;
STS [R9], R14 ?trans4;
LDS R3, [R0+0x4] ?trans4;
LDS R15, [R13+0x40] &wr=0x2 ?trans2;
FFMA R18, -R3, R15, R14 &req={2} ?WAIT5_END_GROUP;
STS [R9], R18 ?trans4;
LDS R3, [R0+0x8] ?trans4;
LDS R15, [R13+0x80] &wr=0x2 ?trans2;
FFMA R20, -R3, R15, R18 &req={2} ?WAIT5_END_GROUP;
STS [R9], R20 ?trans4;
LDS R3, [R0+0xc] ?trans4;
LDS R16, [R13+0xc0] &req={1} &wr=0x1 ?trans2;
FFMA R16, -R3, R16, R20 &req={1} ?WAIT5_END_GROUP;
STS [R9], R16 &rd=0x3 ?trans2;
@!P1 BRA 0xbd0 ?trans5;
LOP3.LUT R0, R4.reuse, 0x3, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R3, R4, 0x1, RZ, 0xc0, !PT ?WAIT3_END_GROUP;
ISETP.NE.AND P0, PT, R0, 0x1, PT ?trans2;
ISETP.NE.U32.AND P1, PT, R3, 0x1, PT ?WAIT11_END_GROUP;
@!P0 BRA 0xb70 ?trans5;
IMAD R13, R11.reuse, 0x4, R10 ?trans2;
IMAD R14, R11.reuse, 0x40, R12 ?trans1;
IADD3 R11, PT, PT, R11, 0x2, RZ ?trans2;
LDS R3, [R13] ?trans4;
LDS R0, [R14] &wr=0x4 ?trans2;
FFMA R0, -R3, R0, R16 &req={4,2} ?WAIT5_END_GROUP;
STS [R9], R0 ?trans4;
LDS R3, [R13+0x4] ?trans4;
LDS R16, [R14+0x40] &req={3,1} &wr=0x1 ?trans2;
FFMA R16, -R3, R16, R0 &req={1} ?WAIT5_END_GROUP;
STS [R9], R16 &rd=0x4 ?trans2;
@!P1 IMAD R0, R11.reuse, 0x4, R10 ?trans2;
@!P1 IMAD R11, R11, 0x40, R12 ?WAIT3_END_GROUP;
@!P1 LDS R3, [R0] ?trans4;
@!P1 LDS R11, [R11] &wr=0x5 ?trans2;
@!P1 FFMA R16, -R3, R11, R16 &req={5,4,3,2,1} ?WAIT5_END_GROUP;
@!P1 STS [R9], R16 &rd=0x4 ?trans2;
IMAD R12, R5.reuse, 0x3c, R12 ?trans1;
BSSY.RECONVERGENT B1, 0xcd0 ?trans3;
IMAD R12, R5, 0x4, R12 ?WAIT5_END_GROUP;
LDS R13, [R12] &wr=0x5 ?trans2;
MUFU.RCP R0, R13 &req={5} &wr=0x5 ?trans1;
FCHK P0, R16, R13 &req={2,1} &wr=0x1 ?trans1;
FFMA R3, -R13, R0, 1 &req={5} ?WAIT4_END_GROUP;
FFMA R0, R0, R3, R0 ?WAIT4_END_GROUP;
FFMA R3, R0, R16, RZ ?WAIT4_END_GROUP;
FFMA R14, -R13, R3, R16 ?WAIT4_END_GROUP;
FFMA R0, R0, R14, R3 ?trans1;
@!P0 BRA 0xcc0 &req={1} ?trans6;
MOV R3, R16 ?trans1;
MOV R12, 0xcc0 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x17a0 &req={4,3,0} ?trans5;
BSYNC.RECONVERGENT B1 ?trans5;
STS [R9], R0 &rd=0x2 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P0, PT, R8, R5, PT ?WAIT5_END_GROUP;
BSSY.RECONVERGENT B0, 0x1330 ?trans8;
@!P0 BRA 0x1320 ?trans5;
LEA R3, R5.reuse, UR5, 0x6 ?trans1;
HFMA2 R12, -RZ, RZ, 0, 0 ?trans1;
ISETP.GE.U32.AND P0, PT, R5, 0x7, PT ?trans1;
LOP3.LUT P1, RZ, R2, 0x7, RZ, 0xc0, !PT ?trans2;
IMAD R0, R8, 0x4, R3 &req={2} ?WAIT5_END_GROUP;
LDS R9, [R0+0x40] &req={4,3} &rd=0x2 &wr=0x3 ?trans5;
@!P0 BRA 0x1030 ?trans5;
LOP3.LUT R18, R2, 0x7ffffff8, RZ, 0xc0, !PT &req={1} ?trans1;
UMOV UR4, URZ ?trans1;
MOV R12, RZ ?WAIT7_END_GROUP;
IMAD R11, R12.reuse, 0x4, R3 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x8, URZ ?trans1;
IMAD R13, R12.reuse, 0x40, R19 ?trans1;
IADD3 R12, PT, PT, R12, 0x8, RZ ?trans2;
LDS R14, [R11+0x40] ?trans2;
ISETP.NE.AND P0, PT, R18, UR4, PT ?trans2;
LDS R15, [R13] &wr=0x1 ?trans2;
FFMA R15, -R14, R15, R9 &req={3,1} ?WAIT5_END_GROUP;
STS [R0+0x40], R15 ?trans4;
LDS R14, [R11+0x44] ?trans4;
LDS R9, [R13+0x40] &req={4} &wr=0x1 ?trans2;
FFMA R9, -R14, R9, R15 &req={1} ?WAIT5_END_GROUP;
STS [R0+0x40], R9 ?trans4;
LDS R14, [R11+0x48] ?trans4;
LDS R16, [R13+0x80] &wr=0x1 ?trans2;
FFMA R17, -R14, R16, R9 &req={1} ?WAIT5_END_GROUP;
STS [R0+0x40], R17 ?trans4;
LDS R14, [R11+0x4c] ?trans4;
LDS R16, [R13+0xc0] &wr=0x1 ?trans2;
FFMA R15, -R14, R16, R17 &req={1} ?WAIT5_END_GROUP;
STS [R0+0x40], R15 ?trans4;
LDS R14, [R11+0x50] ?trans4;
LDS R16, [R13+0x100] &wr=0x1 ?trans2;
FFMA R9, -R14, R16, R15 &req={1} ?WAIT5_END_GROUP;
STS [R0+0x40], R9 ?trans4;
LDS R14, [R11+0x54] ?trans4;
LDS R16, [R13+0x140] &wr=0x1 ?trans2;
FFMA R17, -R14, R16, R9 &req={1} ?WAIT5_END_GROUP;
STS [R0+0x40], R17 ?trans4;
LDS R14, [R11+0x58] ?trans4;
LDS R16, [R13+0x180] &wr=0x1 ?trans2;
FFMA R15, -R14, R16, R17 &req={1} ?WAIT5_END_GROUP;
STS [R0+0x40], R15 ?trans4;
LDS R14, [R11+0x5c] ?trans4;
LDS R16, [R13+0x1c0] &wr=0x1 ?trans2;
FFMA R9, -R14, R16, R15 &req={1} ?WAIT5_END_GROUP;
STS [R0+0x40], R9 &rd=0x4 ?trans1;
@P0 BRA 0xdd0 ?trans5;
@!P1 BRA 0x1320 ?trans5;
LOP3.LUT R13, R6, 0x7, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
LOP3.LUT P1, RZ, R13.reuse, 0x3, RZ, 0xc0, !PT ?trans2;
IADD3 R11, PT, PT, R13, -0x1, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R11, 0x3, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x11c0 ?trans5;
IMAD R11, R12.reuse, 0x4, R3 ?trans2;
IMAD R13, R12.reuse, 0x40, R19 ?trans1;
IADD3 R12, PT, PT, R12, 0x4, RZ ?trans2;
LDS R14, [R11+0x40] ?trans4;
LDS R15, [R13] &wr=0x5 ?trans2;
FFMA R15, -R14, R15, R9 &req={5,3} ?WAIT5_END_GROUP;
STS [R0+0x40], R15 ?trans4;
LDS R14, [R11+0x44] ?trans4;
LDS R9, [R13+0x40] &req={4} &wr=0x3 ?trans2;
FFMA R17, -R14, R9, R15 &req={3} ?WAIT5_END_GROUP;
STS [R0+0x40], R17 ?trans4;
LDS R14, [R11+0x48] ?trans4;
LDS R9, [R13+0x80] &wr=0x3 ?trans2;
FFMA R21, -R14, R9, R17 &req={3} ?WAIT5_END_GROUP;
STS [R0+0x40], R21 ?trans4;
LDS R14, [R11+0x4c] ?trans4;
LDS R9, [R13+0xc0] &wr=0x3 ?trans2;
FFMA R9, -R14, R9, R21 &req={3} ?WAIT5_END_GROUP;
STS [R0+0x40], R9 &rd=0x3 ?trans2;
@!P1 BRA 0x1320 ?trans5;
LOP3.LUT P0, RZ, R4.reuse, 0x3, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R11, R4, 0x1, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.U32.AND P1, PT, R11, 0x1, PT ?WAIT6_END_GROUP;
@!P0 BRA 0x12c0 ?trans7;
IMAD R13, R12.reuse, 0x4, R3 ?trans2;
IMAD R15, R12.reuse, 0x40, R19 ?trans1;
IADD3 R12, PT, PT, R12, 0x2, RZ ?trans2;
LDS R14, [R13+0x40] ?trans4;
LDS R11, [R15] &wr=0x5 ?trans2;
FFMA R11, -R14, R11, R9 &req={5,3} ?WAIT5_END_GROUP;
STS [R0+0x40], R11 ?trans4;
LDS R14, [R13+0x44] ?trans4;
LDS R9, [R15+0x40] &req={4} &wr=0x3 ?trans2;
FFMA R9, -R14, R9, R11 &req={3} ?WAIT5_END_GROUP;
STS [R0+0x40], R9 &rd=0x3 ?trans2;
@P1 IMAD R11, R12.reuse, 0x40, R19 ?trans2;
@P1 IMAD R3, R12, 0x4, R3 ?WAIT4_END_GROUP;
@P1 LDS R11, [R11] ?trans4;
@P1 LDS R12, [R3+0x40] &wr=0x5 ?trans2;
@P1 FFMA R9, -R12, R11, R9 &req={5,4,3} ?WAIT5_END_GROUP;
@P1 STS [R0+0x40], R9 &rd=0x3 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
IADD3 R5, PT, PT, R5, 0x1, RZ ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
IADD3 R4, PT, PT, R4, 0x1, RZ ?trans2;
IADD3 R2, PT, PT, R2, 0x1, RZ ?trans1;
ISETP.NE.AND P0, PT, R5, 0xf, PT ?WAIT13_END_GROUP;
@P0 BRA 0x520 ?trans5;
LDCU.64 UR8, c[0x0][0x388] &wr=0x5 ?trans1;
LDS R14, [R19+0x40] &wr=0x0 ?trans1;
LDC.64 R20, c[0x0][0x380] &req={1} &wr=0x1 ?trans3;
LDS R32, [R19+0x80] &wr=0x2 ?trans4;
LDS R26, [R19+0xc0] &wr=0x4 ?trans4;
LDS R28, [R19+0x100] &wr=0x3 ?trans4;
LDS R30, [R19+0x140] &wr=0x0 ?trans1;
UIADD3 UR4, UPT, UPT, UR9, 0x1, URZ &req={5} ?WAIT3_END_GROUP;
LDS R22, [R19+0x180] &wr=0x5 ?trans1;
UIMAD UR4, UR4, UR8, UR9 ?WAIT3_END_GROUP;
LDS R0, [R19+0x1c0] &req={4,3,2} &wr=0x2 ?trans3;
IADD3 R3, PT, PT, R8, UR4, RZ ?trans1;
LDS R37, [R19+0x200] &wr=0x3 ?trans3;
IADD3 R7, PT, PT, R3.reuse, UR8, RZ ?trans1;
LDS R35, [R19+0x240] &wr=0x4 ?trans1;
IMAD.WIDE.U32 R2, R3, 0x4, R20.reuse &req={1} ?trans2;
IADD3 R17, PT, PT, R7.reuse, UR8, RZ ?trans1;
LDS R33, [R19+0x280] &wr=0x1 ?trans1;
IMAD.WIDE.U32 R6, R7, 0x4, R20 ?WAIT2_END_GROUP;
IADD3 R4, PT, PT, R17.reuse, UR8, RZ ?trans1;
LDS R31, [R19+0x2c0] &wr=0x1 ?trans1;
IMAD.WIDE.U32 R16, R17, 0x4, R20.reuse ?trans2;
IADD3 R5, PT, PT, R4, UR8, RZ ?trans1;
LDS R29, [R19+0x300] &wr=0x1 ?trans3;
IADD3 R12, PT, PT, R5, UR8, RZ ?trans1;
LDS R27, [R19+0x340] &wr=0x1 ?trans3;
IADD3 R10, PT, PT, R12, UR8, RZ &req={0} ?trans1;
LDS R25, [R19+0x380] &wr=0x0 ?trans3;
IADD3 R8, PT, PT, R10, UR8, RZ ?trans1;
LDS R23, [R19+0x3c0] &wr=0x0 ?trans3;
IADD3 R9, PT, PT, R8, UR8, RZ ?trans1;
STG.E desc[UR6][R2.64], R14 &rd=0x2 ?trans3;
IADD3 R11, PT, PT, R9, UR8, RZ ?trans1;
STG.E desc[UR6][R6.64], R32 &rd=0x3 ?trans3;
IADD3 R13, PT, PT, R11, UR8, RZ ?trans1;
STG.E desc[UR6][R16.64], R26 ?trans1;
IMAD.WIDE.U32 R2, R4, 0x4, R20 &req={2} ?WAIT2_END_GROUP;
IADD3 R15, PT, PT, R13, UR8, RZ ?trans2;
IMAD.WIDE.U32 R4, R5, 0x4, R20.reuse ?trans1;
STG.E desc[UR6][R2.64], R28 &rd=0x2 ?trans1;
IADD3 R18, PT, PT, R15, UR8, RZ ?trans2;
IMAD.WIDE.U32 R6, R8, 0x4, R20.reuse &req={3} ?trans1;
STG.E desc[UR6][R4.64], R30 &rd=0x3 ?trans1;
IADD3 R19, PT, PT, R18, UR8, RZ ?trans2;
IMAD.WIDE.U32 R8, R9, 0x4, R20 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R2, R12, 0x4, R20 &req={2} ?trans1;
IADD3 R24, PT, PT, R19, UR8, RZ ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R4, R10, 0x4, R20.reuse &req={3} ?trans1;
STG.E desc[UR6][R2.64], R22 &req={5} ?trans3;
IMAD.WIDE.U32 R10, R11, 0x4, R20.reuse ?trans1;
STG.E desc[UR6][R4.64], R0 ?trans3;
IMAD.WIDE.U32 R12, R13, 0x4, R20.reuse ?trans1;
STG.E desc[UR6][R6.64], R37 ?trans3;
IMAD.WIDE.U32 R14, R15, 0x4, R20.reuse ?trans1;
STG.E desc[UR6][R8.64], R35 &req={4} ?trans3;
IMAD.WIDE.U32 R16, R18, 0x4, R20.reuse ?trans1;
STG.E desc[UR6][R10.64], R33 &req={1} ?trans3;
IMAD.WIDE.U32 R18, R19, 0x4, R20.reuse ?trans1;
STG.E desc[UR6][R12.64], R31 ?trans3;
IMAD.WIDE.U32 R20, R24, 0x4, R20 ?trans1;
STG.E desc[UR6][R14.64], R29 ?trans4;
STG.E desc[UR6][R16.64], R27 ?trans4;
STG.E desc[UR6][R18.64], R25 &req={0} ?trans4;
STG.E desc[UR6][R20.64], R23 ?trans1;
EXIT ?trans5;
SHF.R.U32.HI R11, RZ, 0x17, R13 ?trans1;
BSSY.RECONVERGENT B2, 0x1e00 ?trans1;
SHF.R.U32.HI R0, RZ, 0x17, R3 ?trans2;
LOP3.LUT R21, R11, 0xff, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R16, R0, 0xff, RZ, 0xc0, !PT ?trans1;
MOV R14, R13 ?trans1;
IADD3 R17, PT, PT, R21, -0x1, RZ ?trans2;
IADD3 R15, PT, PT, R16, -0x1, RZ ?WAIT3_END_GROUP;
ISETP.GT.U32.AND P0, PT, R17, 0xfd, PT ?WAIT5_END_GROUP;
ISETP.GT.U32.OR P0, PT, R15, 0xfd, P0 ?WAIT13_END_GROUP;
@!P0 MOV R11, RZ ?trans1;
@!P0 BRA 0x19e0 ?trans6;
FSETP.GTU.FTZ.AND P0, PT, |R3|, +INF , PT ?trans1;
FSETP.GTU.FTZ.AND P1, PT, |R13|, +INF , PT ?trans1;
MOV R0, R13 ?WAIT4_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, PT, 0xf8, 0x8f ?WAIT13_END_GROUP;
@P0 BRA 0x1de0 ?trans5;
LOP3.LUT P0, RZ, R14, 0x7fffffff, R3, 0xc8, !PT ?WAIT13_END_GROUP;
@!P0 BRA 0x1dc0 ?trans5;
FSETP.NEU.FTZ.AND P2, PT, |R3|.reuse, +INF , PT ?trans1;
FSETP.NEU.FTZ.AND P1, PT, |R0|, +INF , PT ?trans1;
FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ?WAIT12_END_GROUP;
@!P1 BRA !P2, 0x1dc0 ?trans5;
LOP3.LUT P2, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P1, PT, P1, P2, PT, 0x2f, 0xf2 ?WAIT13_END_GROUP;
@P1 BRA 0x1da0 ?trans5;
LOP3.LUT P1, RZ, R14, 0x7fffffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, PT, 0x2f, 0xf2 ?WAIT13_END_GROUP;
@P0 BRA 0x1d70 ?trans5;
ISETP.GE.AND P0, PT, R15, RZ, PT ?trans1;
ISETP.GE.AND P1, PT, R17, RZ, PT ?WAIT12_END_GROUP;
@P0 MOV R11, RZ ?trans1;
@!P0 MOV R11, 0xffffffc0 ?trans1;
@!P0 FFMA R3, R3, 1.84467440737095516160e+19, RZ ?trans1;
@!P1 FFMA R14, R0, 1.84467440737095516160e+19, RZ ?WAIT3_END_GROUP;
@!P1 IADD3 R11, PT, PT, R11, 0x40, RZ ?WAIT7_END_GROUP;
LEA R13, R21, 0xc0800000, 0x17 ?trans1;
BSSY.RECONVERGENT B3, 0x1d60 ?trans3;
IADD3 R13, PT, PT, -R13, R14, RZ ?trans2;
IADD3 R14, PT, PT, R16, -0x7f, RZ ?trans2;
MUFU.RCP R15, R13 &wr=0x0 ?trans1;
FADD.FTZ R17, -R13, -RZ ?trans2;
IMAD R0, R14.reuse, -0x800000, R3 ?trans1;
IADD3 R14, PT, PT, R14, 0x7f, -R21 ?WAIT4_END_GROUP;
IADD3 R14, PT, PT, R14, R11, RZ ?trans1;
FFMA R16, R15, R17, 1 &req={0} ?WAIT4_END_GROUP;
FFMA R18, R15, R16, R15 ?WAIT4_END_GROUP;
FFMA R3, R0, R18, RZ ?WAIT4_END_GROUP;
FFMA R16, R17, R3, R0 ?WAIT4_END_GROUP;
FFMA R15, R18, R16, R3 ?WAIT4_END_GROUP;
FFMA R20, R17, R15, R0 ?WAIT4_END_GROUP;
FFMA R0, R18, R20, R15 ?WAIT5_END_GROUP;
SHF.R.U32.HI R3, RZ, 0x17, R0 ?WAIT4_END_GROUP;
LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R13, PT, PT, R3, R14, RZ ?WAIT4_END_GROUP;
IADD3 R3, PT, PT, R13, -0x1, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R3, 0xfe, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x1d40 ?trans5;
ISETP.GT.AND P0, PT, R13, 0xfe, PT ?WAIT13_END_GROUP;
@P0 BRA 0x1d10 ?trans5;
ISETP.GE.AND P0, PT, R13, 0x1, PT ?WAIT13_END_GROUP;
@P0 BRA 0x1d50 ?trans5;
ISETP.GE.AND P0, PT, R13, -0x18, PT ?trans1;
LOP3.LUT R0, R0, 0x80000000, RZ, 0xc0, !PT ?WAIT12_END_GROUP;
@!P0 BRA 0x1d50 ?trans5;
FFMA.RZ R3, R18.reuse, R20.reuse, R15.reuse ?trans1;
IADD3 R16, PT, PT, R13.reuse, 0x20, RZ ?trans1;
FFMA.RM R14, R18.reuse, R20.reuse, R15.reuse ?trans1;
ISETP.NE.AND P1, PT, R13.reuse, RZ, PT ?trans1;
ISETP.NE.AND P2, PT, R13, RZ, PT ?trans1;
LOP3.LUT R3, R3, 0x7fffff, RZ, 0xc0, !PT ?trans2;
IADD3 R13, PT, PT, -R13, RZ, RZ ?trans2;
LOP3.LUT R11, R3, 0x800000, RZ, 0xfc, !PT ?trans1;
FFMA.RP R3, R18, R20, R15 ?WAIT3_END_GROUP;
SHF.L.U32 R16, R11, R16, RZ ?trans2;
FSETP.NEU.FTZ.AND P0, PT, R3, R14, PT ?trans1;
SEL R14, R13, RZ, P2 ?trans2;
ISETP.NE.AND P1, PT, R16, RZ, P1 ?WAIT3_END_GROUP;
SHF.R.U32.HI R14, RZ, R14, R11 ?trans2;
PLOP3.LUT P0, PT, P0, P1, PT, 0xf8, 0x8f ?trans2;
SHF.R.U32.HI R16, RZ, 0x1, R14 ?WAIT3_END_GROUP;
SEL R3, RZ, 0x1, !P0 ?WAIT5_END_GROUP;
LOP3.LUT R3, R3, 0x1, R16, 0xf8, !PT ?WAIT4_END_GROUP;
LOP3.LUT R3, R3, R14, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R3, PT, PT, R16, R3, RZ ?WAIT4_END_GROUP;
LOP3.LUT R0, R3, R0, RZ, 0xfc, !PT ?trans1;
BRA 0x1d50 ?trans6;
LOP3.LUT R0, R0, 0x80000000, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
LOP3.LUT R0, R0, 0x7f800000, RZ, 0xfc, !PT ?trans1;
BRA 0x1d50 ?trans6;
IMAD R0, R14, 0x800000, R0 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B3 ?trans5;
BRA 0x1df0 ?trans5;
LOP3.LUT R0, R14, 0x80000000, R3, 0x48, !PT ?WAIT4_END_GROUP;
LOP3.LUT R0, R0, 0x7f800000, RZ, 0xfc, !PT ?trans1;
BRA 0x1df0 ?trans6;
LOP3.LUT R0, R14, 0x80000000, R3, 0x48, !PT ?trans1;
BRA 0x1df0 ?trans6;
MUFU.RSQ R0, -QNAN &wr=0x0 ?trans1;
BRA 0x1df0 ?trans5;
FADD.FTZ R0, R3, R0 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
HFMA2 R13, -RZ, RZ, 0, 0 ?WAIT4_END_GROUP;
RET.REL.NODEC R12 0x0 &req={0} ?trans5;
BRA 0x1e20;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: lud_diagonal(float*, int, int)
_Z12lud_diagonalPfii:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 2, v0
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s6, 1
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s0, s7, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s0, 0
.LBB0_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, s6, v1
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v4, v[4:5], off
v_add_nc_u32_e32 v5, s0, v3
s_add_i32 s0, s0, 64
s_cmpk_lg_i32 s0, 0x400
s_waitcnt vmcnt(0)
ds_store_b32 v5, v4
s_cbranch_scc1 .LBB0_1
v_lshlrev_b32_e32 v1, 6, v0
v_lshlrev_b32_e32 v2, 2, v0
s_mov_b32 s1, 0
s_mov_b32 s2, 0
s_mov_b32 s3, 1
s_mov_b32 s8, 64
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_cmp_lt_u32_e64 s0, s2, v0
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s9, s0
s_cbranch_execz .LBB0_12
s_cmp_lg_u32 s2, 0
s_cbranch_scc0 .LBB0_8
v_lshl_add_u32 v5, s2, 2, v1
v_mov_b32_e32 v6, v1
s_mov_b32 s10, 0
s_mov_b32 s11, s1
ds_load_b32 v4, v5
.LBB0_6:
v_mov_b32_e32 v7, s11
s_add_i32 s10, s10, 1
s_add_i32 s11, s11, 64
s_cmp_lt_u32 s10, s2
ds_load_b32 v8, v6
ds_load_b32 v7, v7
v_add_nc_u32_e32 v6, 4, v6
s_waitcnt lgkmcnt(0)
v_fma_f32 v4, -v8, v7, v4
ds_store_b32 v5, v4
s_cbranch_scc1 .LBB0_6
s_mov_b32 s10, 0
s_branch .LBB0_9
.LBB0_8:
s_mov_b32 s10, -1
.LBB0_9:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s10
s_cbranch_vccz .LBB0_11
ds_load_b32 v4, v1
.LBB0_11:
s_lshl_b32 s10, s2, 2
s_lshl_b32 s11, s2, 6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s11, s11, s10
v_mov_b32_e32 v5, s11
ds_load_b32 v5, v5
s_waitcnt lgkmcnt(0)
v_div_scale_f32 v6, null, v5, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v7, v6
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v6, v7, 1.0
v_fmac_f32_e32 v7, v8, v7
v_div_scale_f32 v8, vcc_lo, v4, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v9, v8, v7
v_fma_f32 v10, -v6, v9, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v9, v10, v7
v_fma_f32 v6, -v6, v9, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v6, v6, v7, v9
v_lshl_add_u32 v7, v0, 6, s10
v_div_fixup_f32 v4, v6, v5, v4
ds_store_b32 v7, v4
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s9
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s9, s0
s_cbranch_execz .LBB0_15
v_lshl_add_u32 v5, s2, 6, v2
s_mov_b32 s0, s3
s_mov_b32 s10, s8
v_mov_b32_e32 v6, v3
ds_load_b32 v4, v5 offset:64
v_add_nc_u32_e32 v5, 64, v5
.LBB0_14:
v_mov_b32_e32 v7, s10
s_add_i32 s0, s0, -1
s_add_i32 s10, s10, 4
s_cmp_lg_u32 s0, 0
ds_load_b32 v8, v6
ds_load_b32 v7, v7
v_add_nc_u32_e32 v6, 64, v6
s_waitcnt lgkmcnt(0)
v_fma_f32 v4, -v7, v8, v4
ds_store_b32 v5, v4
s_cbranch_scc1 .LBB0_14
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s9
s_add_i32 s2, s2, 1
s_add_i32 s3, s3, 1
s_add_i32 s1, s1, 4
s_add_i32 s8, s8, 64
s_cmp_lg_u32 s2, 15
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_3
s_add_i32 s0, s7, 1
v_mov_b32_e32 v1, 0
s_mul_i32 s0, s0, s6
s_delay_alu instid0(SALU_CYCLE_1)
v_add3_u32 v0, s0, s7, v0
s_mov_b32 s0, 64
.LBB0_17:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, s0, v3
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_add_nc_u32_e32 v0, s6, v0
s_add_i32 s0, s0, 64
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_lg_i32 s0, 0x400
ds_load_b32 v2, v2
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[4:5], v2, off
s_cbranch_scc1 .LBB0_17
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| lud_diagonal | 11,887 | 2,242 | stackv2-00000-of-00015 |
// Demangled: lud_internal(float*, int, int)
Function : _Z12lud_internalPfii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R15, SR_TID.X &wr=0x0 ?trans1;
LDCU.64 UR10, c[0x0][0x388] &wr=0x0 ?trans6;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans1;
S2R R13, SR_TID.Y &wr=0x2 ?trans1;
LDCU.64 UR8, c[0x0][0x358] &wr=0x3 ?trans1;
S2R R6, SR_CTAID.X &wr=0x4 ?trans1;
S2R R7, SR_CTAID.Y &wr=0x5 ?trans1;
IADD3 R5, PT, PT, R15, UR11, RZ &req={0} ?WAIT2_END_GROUP;
IADD3 R0, PT, PT, R13, UR11, RZ &req={2} ?trans2;
LEA R6, R6, R5, 0x4 &req={4} ?trans2;
LEA R4, R7, R0, 0x4 &req={5} ?trans2;
IADD3 R9, PT, PT, R6, 0x10, RZ ?trans2;
IADD3 R8, PT, PT, R4, 0x10, RZ ?WAIT3_END_GROUP;
IMAD R7, R0, UR10, R9 ?trans2;
IMAD R11, R8, UR10, R5 ?trans2;
IMAD.WIDE.U32 R4, R7, 0x4, R2 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R6, R11, 0x4, R2 ?trans1;
LDG.E R12, desc[UR8][R4.64] &req={3} &wr=0x2 ?trans4;
LDG.E R14, desc[UR8][R6.64] &wr=0x3 ?trans1;
S2UR UR6, SR_CgaCtaId &wr=0x0 ?trans1;
UMOV UR4, 0x400 ?trans1;
IMAD R9, R8, UR10, R9 ?trans1;
UIADD3 UR5, UPT, UPT, UR4, 0x400, URZ ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R2, R9, 0x4, R2 ?trans1;
ULEA UR4, UR6, UR4, 0x18 &req={0} ?trans1;
ULEA UR5, UR6, UR5, 0x18 ?WAIT5_END_GROUP;
LEA R0, R15, UR4, 0x2 ?trans2;
LEA R20, R13.reuse, UR5, 0x6 ?trans2;
LEA R13, R13, R0, 0x6 ?trans2;
LEA R15, R15, R20, 0x2 ?WAIT3_END_GROUP;
STS [R13], R12 &req={2} ?trans4;
STS [R15], R14 &req={3} ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDG.E R21, desc[UR8][R2.64] &wr=0x2 ?trans4;
LDS R17, [R0] ?trans4;
LDS.128 R4, [R20] &wr=0x0 ?trans4;
LDS R19, [R0+0x40] &wr=0x1 ?trans4;
LDS R16, [R0+0x80] &wr=0x3 ?trans4;
LDS R31, [R0+0xc0] &wr=0x4 ?trans4;
LDS R23, [R0+0x100] ?trans4;
LDS.128 R8, [R20+0x10] &wr=0x5 ?trans4;
LDS R22, [R0+0x140] &wr=0x5 ?trans4;
LDS R25, [R0+0x180] &wr=0x5 ?trans4;
LDS R24, [R0+0x1c0] &wr=0x5 ?trans4;
LDS R27, [R0+0x200] ?trans4;
LDS.128 R12, [R20+0x20] &wr=0x5 ?trans1;
FFMA R4, R4, R17, RZ &req={0} ?WAIT3_END_GROUP;
LDS R26, [R0+0x240] &wr=0x0 ?trans1;
FFMA R5, R19, R5, R4 &req={1} ?WAIT3_END_GROUP;
LDS R29, [R0+0x280] &wr=0x1 ?trans1;
FFMA R6, R16, R6, R5 &req={3} ?WAIT3_END_GROUP;
LDS R4, [R0+0x2c0] &wr=0x3 ?trans1;
FFMA R7, R31, R7, R6 &req={4} ?WAIT3_END_GROUP;
LDS R5, [R0+0x300] ?trans4;
LDS.128 R16, [R20+0x30] &wr=0x4 ?trans1;
FFMA R7, R8, R23, R7 &req={5} ?WAIT3_END_GROUP;
LDS R6, [R0+0x340] &wr=0x5 ?trans1;
FFMA R22, R22, R9, R7 ?WAIT3_END_GROUP;
LDS R8, [R0+0x380] &wr=0x5 ?trans1;
FFMA R25, R25, R10, R22 ?WAIT3_END_GROUP;
LDS R7, [R0+0x3c0] &wr=0x5 ?trans1;
FFMA R11, R24, R11, R25 ?WAIT4_END_GROUP;
FFMA R11, R12, R27, R11 ?WAIT4_END_GROUP;
FFMA R26, R26, R13, R11 &req={0} ?WAIT4_END_GROUP;
FFMA R29, R29, R14, R26 &req={1} ?WAIT4_END_GROUP;
FFMA R15, R4, R15, R29 &req={3} ?WAIT4_END_GROUP;
FFMA R5, R16, R5, R15 &req={4} ?WAIT4_END_GROUP;
FFMA R5, R6, R17, R5 &req={5} ?WAIT4_END_GROUP;
FFMA R8, R8, R18, R5 ?WAIT4_END_GROUP;
FFMA R8, R7, R19, R8 ?WAIT4_END_GROUP;
FADD R21, -R8, R21 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR8][R2.64], R21 ?trans1;
EXIT ?trans5;
BRA 0x4a0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: lud_internal(float*, int, int)
_Z12lud_internalPfii:
s_load_b128 s[0:3], s[0:1], 0x0
v_bfe_u32 v8, v0, 10, 10
v_and_b32_e32 v9, 0x3ff, v0
s_lshl_b32 s4, s15, 4
s_lshl_b32 s5, s14, 4
s_waitcnt lgkmcnt(0)
s_add_i32 s6, s3, 16
v_add_nc_u32_e32 v3, s3, v8
v_add3_u32 v0, s6, s5, v9
v_add3_u32 v4, s4, s6, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[1:2], null, v3, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_mul_lo_u32 v3, v4, s2
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add3_u32 v1, v3, v9, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s0, v4
v_lshlrev_b64 v[6:7], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
v_lshlrev_b32_e32 v1, 6, v8
v_add_co_u32 v6, vcc_lo, s0, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
s_clause 0x1
global_load_b32 v5, v[4:5], off
global_load_b32 v6, v[6:7], off
v_lshlrev_b32_e32 v7, 2, v9
v_add_nc_u32_e32 v4, 0x400, v7
v_add_nc_u32_e32 v7, v1, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v8, v4, v1
s_waitcnt vmcnt(1)
ds_store_b32 v8, v5
s_waitcnt vmcnt(0)
ds_store_b32 v7, v6
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB2_1:
v_add_nc_u32_e32 v5, s2, v1
s_add_i32 s2, s2, 4
ds_load_b32 v6, v4
ds_load_b32 v5, v5
v_add_nc_u32_e32 v4, 64, v4
s_cmp_lg_u32 s2, 64
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v5, v6
s_cbranch_scc1 .LBB2_1
v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| lud_internal | 1,835 | 1,151 | stackv2-00000-of-00015 |
// Demangled: gpu_add_two_vectors()
Function : _Z19gpu_add_two_vectorsv
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
EXIT ?trans5;
BRA 0x20;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: gpu_add_two_vectors()
_Z19gpu_add_two_vectorsv:
s_endpgm
| gpu_add_two_vectors | 95 | 15 | stackv2-00000-of-00015 |
// Demangled: fun_c(int*, int)
Function : _Z5fun_cPii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
LDC R4, c[0x0][0x388] &wr=0x1 ?trans2;
ISETP.GE.AND P0, PT, R4, 0x1, PT &req={1} ?WAIT13_END_GROUP;
@!P0 EXIT &req={0} ?trans5;
ISETP.GE.U32.AND P1, PT, R4.reuse, 0x10, PT ?trans1;
LOP3.LUT R30, R4, 0xf, RZ, 0xc0, !PT ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x0 ?trans1;
HFMA2 R0, -RZ, RZ, 0, 0 ?WAIT3_END_GROUP;
ISETP.NE.AND P0, PT, R30, RZ, PT ?WAIT7_END_GROUP;
@!P1 BRA 0x450 ?trans6;
LDCU.64 UR4, c[0x0][0x380] &wr=0x1 ?trans1;
LOP3.LUT R5, R4, 0x7ffffff0, RZ, 0xc0, !PT ?trans1;
MOV R0, RZ ?WAIT3_END_GROUP;
IADD3 R5, PT, PT, -R5, RZ, RZ ?trans1;
UIADD3.64 UR4, UPT, UPT, UR4, 0x20, URZ &req={1} ?WAIT6_END_GROUP;
MOV.64 R2, UR4 ?WAIT8_END_GROUP;
LDG.E R6, desc[UR6][R2.64+-0x20] &req={0} &wr=0x2 ?trans4;
LDG.E R8, desc[UR6][R2.64+-0x1c] &wr=0x3 ?trans4;
LDG.E R10, desc[UR6][R2.64+-0x18] &wr=0x4 ?trans4;
LDG.E R12, desc[UR6][R2.64+-0x14] &wr=0x5 ?trans4;
LDG.E R14, desc[UR6][R2.64+-0x10] &wr=0x5 ?trans4;
LDG.E R16, desc[UR6][R2.64+-0xc] &wr=0x5 ?trans4;
LDG.E R18, desc[UR6][R2.64+-0x8] &wr=0x5 ?trans4;
LDG.E R19, desc[UR6][R2.64+-0x4] &wr=0x5 ?trans4;
LDG.E R20, desc[UR6][R2.64] &wr=0x5 ?trans4;
LDG.E R22, desc[UR6][R2.64+0x4] &wr=0x5 ?trans4;
LDG.E R24, desc[UR6][R2.64+0x8] &wr=0x5 ?trans4;
LDG.E R26, desc[UR6][R2.64+0xc] &wr=0x5 ?trans4;
LDG.E R27, desc[UR6][R2.64+0x10] &wr=0x5 ?trans4;
LDG.E R28, desc[UR6][R2.64+0x14] &wr=0x5 ?trans4;
LDG.E R29, desc[UR6][R2.64+0x18] &wr=0x5 ?trans4;
LDG.E R31, desc[UR6][R2.64+0x1c] &wr=0x5 ?trans1;
IADD3 R5, PT, PT, R5, 0x10, RZ ?WAIT2_END_GROUP;
IADD3 R0, PT, PT, R0, 0x10, RZ ?WAIT3_END_GROUP;
ISETP.NE.AND P1, PT, R5, RZ, PT ?trans1;
LOP3.LUT R7, R6, 0xf, RZ, 0xc0, !PT &req={2} ?trans2;
LOP3.LUT R9, R8, 0xf, RZ, 0xc0, !PT &req={3} ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+-0x20], R7 &rd=0x0 ?trans1;
LOP3.LUT R11, R10, 0xf, RZ, 0xc0, !PT &req={4} ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+-0x1c], R9 &rd=0x1 ?trans1;
LOP3.LUT R13, R12, 0xf, RZ, 0xc0, !PT &req={5} ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+-0x18], R11 &rd=0x2 ?trans1;
LOP3.LUT R15, R14, 0xf, RZ, 0xc0, !PT ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+-0x14], R13 ?trans1;
LOP3.LUT R17, R16, 0xf, RZ, 0xc0, !PT ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+-0x10], R15 ?trans1;
LOP3.LUT R7, R18, 0xf, RZ, 0xc0, !PT &req={0} ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+-0xc], R17 ?trans1;
LOP3.LUT R19, R19, 0xf, RZ, 0xc0, !PT ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+-0x8], R7 ?trans1;
LOP3.LUT R21, R20, 0xf, RZ, 0xc0, !PT ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+-0x4], R19 ?trans1;
LOP3.LUT R23, R22, 0xf, RZ, 0xc0, !PT ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64], R21 ?trans1;
LOP3.LUT R25, R24, 0xf, RZ, 0xc0, !PT ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+0x4], R23 ?trans1;
LOP3.LUT R9, R26, 0xf, RZ, 0xc0, !PT &req={1} ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+0x8], R25 ?trans1;
LOP3.LUT R27, R27, 0xf, RZ, 0xc0, !PT ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+0xc], R9 ?trans1;
LOP3.LUT R11, R28, 0xf, RZ, 0xc0, !PT &req={2} ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+0x10], R27 ?trans1;
LOP3.LUT R29, R29, 0xf, RZ, 0xc0, !PT ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+0x14], R11 ?trans1;
LOP3.LUT R31, R31, 0xf, RZ, 0xc0, !PT ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+0x18], R29 ?trans4;
STG.E desc[UR6][R2.64+0x1c], R31 &rd=0x0 ?trans2;
IADD.64 R2, R2, 0x40 &req={0} ?trans2;
@P1 BRA 0x100 ?trans6;
@!P0 EXIT &req={0} ?trans5;
ISETP.GE.U32.AND P0, PT, R30, 0x8, PT ?trans1;
LOP3.LUT R20, R4, 0x7, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R20, RZ, PT ?WAIT7_END_GROUP;
@!P0 BRA 0x650 ?trans6;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans2;
IMAD.WIDE.U32 R2, R0, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E R5, desc[UR6][R2.64] &wr=0x2 ?trans4;
LDG.E R6, desc[UR6][R2.64+0x4] &wr=0x3 ?trans4;
LDG.E R8, desc[UR6][R2.64+0x8] &wr=0x4 ?trans4;
LDG.E R10, desc[UR6][R2.64+0xc] &wr=0x5 ?trans4;
LDG.E R12, desc[UR6][R2.64+0x10] &wr=0x5 ?trans4;
LDG.E R14, desc[UR6][R2.64+0x14] &wr=0x5 ?trans4;
LDG.E R16, desc[UR6][R2.64+0x18] &wr=0x5 ?trans4;
LDG.E R18, desc[UR6][R2.64+0x1c] &wr=0x5 ?trans1;
IADD3 R0, PT, PT, R0, 0x8, RZ ?WAIT2_END_GROUP;
LOP3.LUT R5, R5, 0xf, RZ, 0xc0, !PT &req={2} ?trans2;
LOP3.LUT R7, R6, 0xf, RZ, 0xc0, !PT &req={3} ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64], R5 &rd=0x0 ?trans1;
LOP3.LUT R9, R8, 0xf, RZ, 0xc0, !PT &req={4} ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+0x4], R7 &rd=0x0 ?trans1;
LOP3.LUT R11, R10, 0xf, RZ, 0xc0, !PT &req={5} ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+0x8], R9 &rd=0x0 ?trans1;
LOP3.LUT R13, R12, 0xf, RZ, 0xc0, !PT ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+0xc], R11 &rd=0x0 ?trans1;
LOP3.LUT R15, R14, 0xf, RZ, 0xc0, !PT ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+0x10], R13 &rd=0x0 ?trans1;
LOP3.LUT R17, R16, 0xf, RZ, 0xc0, !PT ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+0x14], R15 &rd=0x0 ?trans1;
LOP3.LUT R19, R18, 0xf, RZ, 0xc0, !PT ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+0x18], R17 &rd=0x0 ?trans4;
STG.E desc[UR6][R2.64+0x1c], R19 &rd=0x0 ?trans2;
@!P1 EXIT ?trans5;
ISETP.GE.U32.AND P0, PT, R20, 0x4, PT ?trans1;
LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R4, RZ, PT ?WAIT7_END_GROUP;
@!P0 BRA 0x790 ?trans6;
LDC.64 R2, c[0x0][0x380] &req={0} &wr=0x0 ?trans2;
IMAD.WIDE.U32 R2, R0, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E R5, desc[UR6][R2.64] &wr=0x2 ?trans4;
LDG.E R6, desc[UR6][R2.64+0x4] &wr=0x3 ?trans4;
LDG.E R8, desc[UR6][R2.64+0x8] &wr=0x4 ?trans4;
LDG.E R10, desc[UR6][R2.64+0xc] &wr=0x5 ?trans1;
IADD3 R0, PT, PT, R0, 0x4, RZ ?WAIT2_END_GROUP;
LOP3.LUT R5, R5, 0xf, RZ, 0xc0, !PT &req={2} ?trans2;
LOP3.LUT R7, R6, 0xf, RZ, 0xc0, !PT &req={3} ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64], R5 &rd=0x1 ?trans1;
LOP3.LUT R9, R8, 0xf, RZ, 0xc0, !PT &req={4} ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+0x4], R7 &rd=0x1 ?trans1;
LOP3.LUT R11, R10, 0xf, RZ, 0xc0, !PT &req={5} ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+0x8], R9 &rd=0x1 ?trans4;
STG.E desc[UR6][R2.64+0xc], R11 &rd=0x1 ?trans2;
@!P1 EXIT ?trans5;
LDC.64 R2, c[0x0][0x380] &req={1,0} &wr=0x0 ?trans1;
IADD3 R4, PT, PT, -R4, RZ, RZ ?trans1;
IMAD.WIDE.U32 R2, R0, 0x4, R2 &req={0} ?WAIT7_END_GROUP;
LDG.E R0, desc[UR6][R2.64] &wr=0x2 ?trans1;
IADD3 R4, PT, PT, R4, 0x1, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R4, RZ, PT ?trans1;
LOP3.LUT R5, R0, 0xf, RZ, 0xc0, !PT &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R5 &rd=0x0 ?trans2;
IADD.64 R2, R2, 0x4 &req={0} ?WAIT5_END_GROUP;
@P0 BRA 0x7d0 ?trans5;
EXIT ?trans5;
BRA 0x850;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: fun_c(int*, int)
_Z5fun_cPii:
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v0, 0
.LBB0_2:
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[0:1]
s_add_i32 s2, s2, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v1, 15, v1
global_store_b32 v0, v1, s[0:1]
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s2, 0
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| fun_c | 3,914 | 273 | stackv2-00000-of-00015 |
// Demangled: fun_d(int*, int)
Function : _Z5fun_dPii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
LDC R4, c[0x0][0x388] &wr=0x1 ?trans2;
ISETP.GE.AND P0, PT, R4, 0x1, PT &req={1} ?WAIT13_END_GROUP;
@!P0 EXIT &req={0} ?trans5;
ISETP.GE.U32.AND P1, PT, R4.reuse, 0x10, PT ?trans1;
LOP3.LUT R30, R4, 0xf, RZ, 0xc0, !PT ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x0 ?trans1;
HFMA2 R0, -RZ, RZ, 0, 0 ?WAIT3_END_GROUP;
ISETP.NE.AND P0, PT, R30, RZ, PT ?WAIT7_END_GROUP;
@!P1 BRA 0x450 ?trans6;
LDCU.64 UR4, c[0x0][0x380] &wr=0x1 ?trans1;
LOP3.LUT R5, R4, 0x7ffffff0, RZ, 0xc0, !PT ?trans1;
MOV R0, RZ ?WAIT3_END_GROUP;
IADD3 R5, PT, PT, -R5, RZ, RZ ?trans1;
UIADD3.64 UR4, UPT, UPT, UR4, 0x20, URZ &req={1} ?WAIT6_END_GROUP;
MOV.64 R2, UR4 ?WAIT8_END_GROUP;
LDG.E R6, desc[UR6][R2.64+-0x20] &req={0} &wr=0x2 ?trans4;
LDG.E R8, desc[UR6][R2.64+-0x1c] &wr=0x3 ?trans4;
LDG.E R10, desc[UR6][R2.64+-0x18] &wr=0x4 ?trans4;
LDG.E R12, desc[UR6][R2.64+-0x14] &wr=0x5 ?trans4;
LDG.E R14, desc[UR6][R2.64+-0x10] &wr=0x5 ?trans4;
LDG.E R16, desc[UR6][R2.64+-0xc] &wr=0x5 ?trans4;
LDG.E R18, desc[UR6][R2.64+-0x8] &wr=0x5 ?trans4;
LDG.E R19, desc[UR6][R2.64+-0x4] &wr=0x5 ?trans4;
LDG.E R20, desc[UR6][R2.64] &wr=0x5 ?trans4;
LDG.E R22, desc[UR6][R2.64+0x4] &wr=0x5 ?trans4;
LDG.E R24, desc[UR6][R2.64+0x8] &wr=0x5 ?trans4;
LDG.E R26, desc[UR6][R2.64+0xc] &wr=0x5 ?trans4;
LDG.E R27, desc[UR6][R2.64+0x10] &wr=0x5 ?trans4;
LDG.E R28, desc[UR6][R2.64+0x14] &wr=0x5 ?trans4;
LDG.E R29, desc[UR6][R2.64+0x18] &wr=0x5 ?trans4;
LDG.E R31, desc[UR6][R2.64+0x1c] &wr=0x5 ?trans1;
IADD3 R5, PT, PT, R5, 0x10, RZ ?WAIT2_END_GROUP;
IADD3 R0, PT, PT, R0, 0x10, RZ ?WAIT3_END_GROUP;
ISETP.NE.AND P1, PT, R5, RZ, PT ?trans1;
SGXT.U32 R7, R6, 0x4 &req={2} ?trans2;
SGXT.U32 R9, R8, 0x4 &req={3} ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+-0x20], R7 &rd=0x0 ?trans1;
SGXT.U32 R11, R10, 0x4 &req={4} ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+-0x1c], R9 &rd=0x1 ?trans1;
SGXT.U32 R13, R12, 0x4 &req={5} ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+-0x18], R11 &rd=0x2 ?trans1;
SGXT.U32 R15, R14, 0x4 ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+-0x14], R13 ?trans1;
SGXT.U32 R17, R16, 0x4 ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+-0x10], R15 ?trans1;
SGXT.U32 R7, R18, 0x4 &req={0} ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+-0xc], R17 ?trans1;
SGXT.U32 R19, R19, 0x4 ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+-0x8], R7 ?trans1;
SGXT.U32 R21, R20, 0x4 ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+-0x4], R19 ?trans1;
SGXT.U32 R23, R22, 0x4 ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64], R21 ?trans1;
SGXT.U32 R25, R24, 0x4 ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+0x4], R23 ?trans1;
SGXT.U32 R9, R26, 0x4 &req={1} ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+0x8], R25 ?trans1;
SGXT.U32 R27, R27, 0x4 ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+0xc], R9 ?trans1;
SGXT.U32 R11, R28, 0x4 &req={2} ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+0x10], R27 ?trans1;
SGXT.U32 R29, R29, 0x4 ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+0x14], R11 ?trans1;
SGXT.U32 R31, R31, 0x4 ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+0x18], R29 ?trans4;
STG.E desc[UR6][R2.64+0x1c], R31 &rd=0x0 ?trans2;
IADD.64 R2, R2, 0x40 &req={0} ?trans2;
@P1 BRA 0x100 ?trans6;
@!P0 EXIT &req={0} ?trans5;
ISETP.GE.U32.AND P0, PT, R30, 0x8, PT ?trans1;
LOP3.LUT R20, R4, 0x7, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R20, RZ, PT ?WAIT7_END_GROUP;
@!P0 BRA 0x650 ?trans6;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans2;
IMAD.WIDE.U32 R2, R0, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E R5, desc[UR6][R2.64] &wr=0x2 ?trans4;
LDG.E R6, desc[UR6][R2.64+0x4] &wr=0x3 ?trans4;
LDG.E R8, desc[UR6][R2.64+0x8] &wr=0x4 ?trans4;
LDG.E R10, desc[UR6][R2.64+0xc] &wr=0x5 ?trans4;
LDG.E R12, desc[UR6][R2.64+0x10] &wr=0x5 ?trans4;
LDG.E R14, desc[UR6][R2.64+0x14] &wr=0x5 ?trans4;
LDG.E R16, desc[UR6][R2.64+0x18] &wr=0x5 ?trans4;
LDG.E R18, desc[UR6][R2.64+0x1c] &wr=0x5 ?trans1;
IADD3 R0, PT, PT, R0, 0x8, RZ ?WAIT2_END_GROUP;
SGXT.U32 R5, R5, 0x4 &req={2} ?trans2;
SGXT.U32 R7, R6, 0x4 &req={3} ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64], R5 &rd=0x0 ?trans1;
SGXT.U32 R9, R8, 0x4 &req={4} ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+0x4], R7 &rd=0x0 ?trans1;
SGXT.U32 R11, R10, 0x4 &req={5} ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+0x8], R9 &rd=0x0 ?trans1;
SGXT.U32 R13, R12, 0x4 ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+0xc], R11 &rd=0x0 ?trans1;
SGXT.U32 R15, R14, 0x4 ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+0x10], R13 &rd=0x0 ?trans1;
SGXT.U32 R17, R16, 0x4 ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+0x14], R15 &rd=0x0 ?trans1;
SGXT.U32 R19, R18, 0x4 ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+0x18], R17 &rd=0x0 ?trans4;
STG.E desc[UR6][R2.64+0x1c], R19 &rd=0x0 ?trans2;
@!P1 EXIT ?trans5;
ISETP.GE.U32.AND P0, PT, R20, 0x4, PT ?trans1;
LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R4, RZ, PT ?WAIT7_END_GROUP;
@!P0 BRA 0x790 ?trans6;
LDC.64 R2, c[0x0][0x380] &req={0} &wr=0x0 ?trans2;
IMAD.WIDE.U32 R2, R0, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E R5, desc[UR6][R2.64] &wr=0x2 ?trans4;
LDG.E R6, desc[UR6][R2.64+0x4] &wr=0x3 ?trans4;
LDG.E R8, desc[UR6][R2.64+0x8] &wr=0x4 ?trans4;
LDG.E R10, desc[UR6][R2.64+0xc] &wr=0x5 ?trans1;
IADD3 R0, PT, PT, R0, 0x4, RZ ?WAIT2_END_GROUP;
SGXT.U32 R5, R5, 0x4 &req={2} ?trans2;
SGXT.U32 R7, R6, 0x4 &req={3} ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64], R5 &rd=0x1 ?trans1;
SGXT.U32 R9, R8, 0x4 &req={4} ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+0x4], R7 &rd=0x1 ?trans1;
SGXT.U32 R11, R10, 0x4 &req={5} ?WAIT3_END_GROUP;
STG.E desc[UR6][R2.64+0x8], R9 &rd=0x1 ?trans4;
STG.E desc[UR6][R2.64+0xc], R11 &rd=0x1 ?trans2;
@!P1 EXIT ?trans5;
LDC.64 R2, c[0x0][0x380] &req={1,0} &wr=0x0 ?trans1;
IADD3 R4, PT, PT, -R4, RZ, RZ ?trans1;
IMAD.WIDE.U32 R2, R0, 0x4, R2 &req={0} ?WAIT7_END_GROUP;
LDG.E R0, desc[UR6][R2.64] &wr=0x2 ?trans1;
IADD3 R4, PT, PT, R4, 0x1, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R4, RZ, PT ?trans1;
SGXT.U32 R5, R0, 0x4 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R5 &rd=0x0 ?trans2;
IADD.64 R2, R2, 0x4 &req={0} ?WAIT5_END_GROUP;
@P0 BRA 0x7d0 ?trans5;
EXIT ?trans5;
BRA 0x850;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: fun_d(int*, int)
_Z5fun_dPii:
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB1_3
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_mov_b32 s3, 0
s_mov_b32 s4, 4
.LBB1_2:
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
bfe.u32 s5, v1, s3, s4
v_mov_b32_e32 v1, s5
s_add_i32 s2, s2, -1
global_store_b32 v0, v1, s[0:1]
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s2, 0
s_cbranch_scc0 .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| fun_d | 3,624 | 309 | stackv2-00000-of-00015 |
// Demangled: kernel(int*, int*, int*)
Function : _Z6kernelPiS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans8;
LDC R2, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R2, R2, UR4, R3 &req={1} ?WAIT5_END_GROUP;
ISETP.GT.AND P0, PT, R2, 0xfffff, PT ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R12, c[0x0][0x380] &wr=0x0 ?trans1;
IADD3 R6, PT, PT, R2.reuse, 0x1, RZ ?trans2;
IADD3 R5, PT, PT, R2, 0x2, RZ ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
SHF.R.S32.HI R3, RZ, 0x1f, R6 ?trans2;
SHF.R.S32.HI R0, RZ, 0x1f, R5 ?trans2;
LEA.HI R3, R3, R6, RZ, 0x8 ?trans2;
LEA.HI R0, R0, R5, RZ, 0x8 ?WAIT2_END_GROUP;
LOP3.LUT R3, R3, 0xffffff00, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R0, R0, 0xffffff00, RZ, 0xc0, !PT ?trans2;
IADD3 R6, PT, PT, R6, -R3, RZ ?trans2;
IADD3 R5, PT, PT, R5, -R0, RZ ?trans1;
IMAD.WIDE R8, R2, 0x4, R12 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE R10, R6, 0x4, R12.reuse ?trans2;
LDG.E R8, desc[UR4][R8.64] &req={1} &wr=0x2 ?trans2;
IMAD.WIDE R12, R5, 0x4, R12 ?trans2;
LDG.E R11, desc[UR4][R10.64] &wr=0x2 ?trans4;
LDG.E R12, desc[UR4][R12.64] &wr=0x2 ?trans1;
HFMA2 R7, -RZ, RZ, 1.666015625, -0.052093505859375 ?trans1;
MOV R4, 0x40400000 ?WAIT5_END_GROUP;
FFMA R3, R7, -R4, 1 ?WAIT4_END_GROUP;
FFMA R3, R3, R7, 0.3333333432674407959 ?trans1;
BSSY.RECONVERGENT B0, 0x2a0 ?trans1;
IADD3 R0, PT, PT, R12, R11, R8 &req={2} ?WAIT4_END_GROUP;
I2FP.F32.S32 R0, R0 ?WAIT4_END_GROUP;
FCHK P0, R0, 3 &wr=0x0 ?trans1;
FFMA R7, R0, R3, RZ ?WAIT4_END_GROUP;
FFMA R8, R7, -3, R0 ?WAIT4_END_GROUP;
FFMA R7, R3, R8, R7 ?trans1;
@!P0 BRA 0x290 &req={0} ?trans6;
MOV R3, R0 ?trans1;
MOV R8, 0x280 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x470 ?trans5;
MOV R7, R3 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
LDC.64 R12, c[0x0][0x388] &wr=0x0 ?trans2;
IMAD.WIDE R10, R6, 0x4, R12 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE R8, R2, 0x4, R12.reuse ?trans2;
LDG.E R11, desc[UR4][R10.64] &wr=0x2 ?trans2;
IMAD.WIDE R12, R5, 0x4, R12 ?trans2;
LDG.E R8, desc[UR4][R8.64] &wr=0x2 ?trans4;
LDG.E R12, desc[UR4][R12.64] &wr=0x2 ?trans1;
HFMA2 R5, -RZ, RZ, 1.666015625, -0.052093505859375 ?WAIT5_END_GROUP;
FFMA R6, R5, -R4, 1 ?trans1;
BSSY.RECONVERGENT B0, 0x400 ?trans1;
IADD3 R0, PT, PT, R12, R11, R8 &req={2} ?WAIT4_END_GROUP;
I2FP.F32.S32 R3, R0 ?WAIT4_END_GROUP;
FCHK P0, R3, 3 &wr=0x0 ?trans1;
FFMA R0, R6, R5, 0.3333333432674407959 ?WAIT4_END_GROUP;
FFMA R6, R0, R3, RZ ?WAIT4_END_GROUP;
FFMA R5, R6, -3, R3 ?WAIT4_END_GROUP;
FFMA R0, R0, R5, R6 ?trans1;
@!P0 BRA 0x3f0 &req={0} ?trans6;
MOV R8, 0x3e0 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x470 ?trans5;
MOV R0, R3 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
LDC.64 R4, c[0x0][0x390] &wr=0x0 ?trans1;
FADD R0, R0, R7 ?WAIT4_END_GROUP;
FMUL R0, R0, 0.5 ?WAIT4_END_GROUP;
F2I.TRUNC.NTZ R7, R0 &wr=0x1 ?trans1;
IMAD.WIDE R2, R2, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R7 &req={1} ?trans1;
EXIT ?trans5;
SHF.R.U32.HI R9, RZ, 0x17, R4 ?trans1;
BSSY.RECONVERGENT B1, 0xad0 ?trans1;
SHF.R.U32.HI R0, RZ, 0x17, R3 ?trans1;
HFMA2 R10, -RZ, RZ, 2.125, 0 ?trans1;
LOP3.LUT R9, R9, 0xff, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R14, R0, 0xff, RZ, 0xc0, !PT ?trans2;
IADD3 R12, PT, PT, R9, -0x1, RZ ?trans2;
IADD3 R13, PT, PT, R14, -0x1, RZ ?WAIT3_END_GROUP;
ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ?WAIT5_END_GROUP;
ISETP.GT.U32.OR P0, PT, R13, 0xfd, P0 ?WAIT13_END_GROUP;
@!P0 MOV R11, RZ ?trans1;
@!P0 BRA 0x6b0 ?trans6;
MOV R0, 0x40400000 ?trans1;
FSETP.GTU.FTZ.AND P0, PT, |R3|, +INF , PT ?WAIT4_END_GROUP;
FSETP.GTU.FTZ.AND P1, PT, |R0|, +INF , PT ?WAIT5_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, PT, 0xf8, 0x8f ?WAIT13_END_GROUP;
@P0 BRA 0xab0 ?trans5;
LOP3.LUT P0, RZ, R10, 0x7fffffff, R3, 0xc8, !PT ?WAIT13_END_GROUP;
@!P0 BRA 0xa90 ?trans5;
FSETP.NEU.FTZ.AND P2, PT, |R3|.reuse, +INF , PT ?trans1;
FSETP.NEU.FTZ.AND P1, PT, |R0|, +INF , PT ?trans1;
FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ?WAIT12_END_GROUP;
@!P1 BRA !P2, 0xa90 ?trans5;
LOP3.LUT P2, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P1, PT, P1, P2, PT, 0x2f, 0xf2 ?WAIT13_END_GROUP;
@P1 BRA 0xa70 ?trans5;
LOP3.LUT P1, RZ, R10, 0x7fffffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, PT, 0x2f, 0xf2 ?WAIT13_END_GROUP;
@P0 BRA 0xa40 ?trans5;
ISETP.GE.AND P0, PT, R13, RZ, PT ?trans1;
ISETP.GE.AND P1, PT, R12, RZ, PT ?WAIT12_END_GROUP;
@P0 MOV R11, RZ ?trans1;
@!P0 MOV R11, 0xffffffc0 ?trans1;
@!P0 FFMA R3, R3, 1.84467440737095516160e+19, RZ ?trans1;
@!P1 FFMA R10, R0, 1.84467440737095516160e+19, RZ ?WAIT3_END_GROUP;
@!P1 IADD3 R11, PT, PT, R11, 0x40, RZ ?WAIT7_END_GROUP;
LEA R13, R9, 0xc0800000, 0x17 ?trans1;
BSSY.RECONVERGENT B2, 0xa30 ?trans3;
IADD3 R13, PT, PT, -R13, R10, RZ ?trans2;
IADD3 R10, PT, PT, R14, -0x7f, RZ ?trans2;
MUFU.RCP R12, R13 &wr=0x0 ?trans1;
FADD.FTZ R15, -R13, -RZ ?trans2;
IMAD R0, R10.reuse, -0x800000, R3 ?trans1;
IADD3 R10, PT, PT, R10, 0x7f, -R9 ?WAIT4_END_GROUP;
IADD3 R10, PT, PT, R10, R11, RZ ?trans1;
FFMA R17, R12, R15, 1 &req={0} ?WAIT4_END_GROUP;
FFMA R14, R12, R17, R12 ?WAIT4_END_GROUP;
FFMA R3, R0, R14, RZ ?WAIT4_END_GROUP;
FFMA R12, R15, R3, R0 ?WAIT4_END_GROUP;
FFMA R17, R14, R12, R3 ?WAIT4_END_GROUP;
FFMA R12, R15, R17, R0 ?WAIT4_END_GROUP;
FFMA R3, R14, R12, R17 ?WAIT5_END_GROUP;
SHF.R.U32.HI R0, RZ, 0x17, R3 ?WAIT4_END_GROUP;
LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R13, PT, PT, R0, R10, RZ ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R13, -0x1, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R0, 0xfe, PT ?WAIT13_END_GROUP;
@!P0 BRA 0xa10 ?trans5;
ISETP.GT.AND P0, PT, R13, 0xfe, PT ?WAIT13_END_GROUP;
@P0 BRA 0x9e0 ?trans5;
ISETP.GE.AND P0, PT, R13, 0x1, PT ?WAIT13_END_GROUP;
@P0 BRA 0xa20 ?trans5;
ISETP.GE.AND P0, PT, R13, -0x18, PT ?trans1;
LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ?WAIT12_END_GROUP;
@!P0 BRA 0xa20 ?trans5;
FFMA.RZ R0, R14.reuse, R12.reuse, R17.reuse ?trans1;
IADD3 R11, PT, PT, R13.reuse, 0x20, RZ ?trans1;
FFMA.RM R9, R14, R12, R17 ?trans1;
ISETP.NE.AND P1, PT, R13.reuse, RZ, PT ?trans1;
ISETP.NE.AND P2, PT, R13, RZ, PT ?trans1;
LOP3.LUT R0, R0, 0x7fffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
LOP3.LUT R10, R0, 0x800000, RZ, 0xfc, !PT ?trans1;
FFMA.RP R0, R14, R12, R17 ?trans1;
IADD3 R12, PT, PT, -R13, RZ, RZ ?trans2;
SHF.L.U32 R11, R10, R11, RZ ?trans2;
FSETP.NEU.FTZ.AND P0, PT, R0, R9, PT ?trans1;
SEL R9, R12, RZ, P2 ?trans2;
ISETP.NE.AND P1, PT, R11, RZ, P1 ?WAIT3_END_GROUP;
SHF.R.U32.HI R9, RZ, R9, R10 ?trans2;
PLOP3.LUT P0, PT, P0, P1, PT, 0xf8, 0x8f ?trans2;
SHF.R.U32.HI R11, RZ, 0x1, R9 ?WAIT3_END_GROUP;
SEL R0, RZ, 0x1, !P0 ?WAIT5_END_GROUP;
LOP3.LUT R0, R0, 0x1, R11, 0xf8, !PT ?WAIT4_END_GROUP;
LOP3.LUT R0, R0, R9, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R11, R0, RZ ?WAIT4_END_GROUP;
LOP3.LUT R3, R0, R3, RZ, 0xfc, !PT ?trans1;
BRA 0xa20 ?trans6;
LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ?trans1;
BRA 0xa20 ?trans6;
IMAD R3, R10, 0x800000, R3 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
BRA 0xac0 ?trans5;
LOP3.LUT R3, R10, 0x80000000, R3, 0x48, !PT ?WAIT4_END_GROUP;
LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ?trans1;
BRA 0xac0 ?trans6;
LOP3.LUT R3, R10, 0x80000000, R3, 0x48, !PT ?trans1;
BRA 0xac0 ?trans6;
MUFU.RSQ R3, -QNAN &wr=0x0 ?trans1;
BRA 0xac0 ?trans5;
FADD.FTZ R3, R3, R0 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B1 ?trans5;
HFMA2 R9, -RZ, RZ, 0, 0 ?WAIT4_END_GROUP;
RET.REL.NODEC R8 0x0 &req={0} ?trans5;
BRA 0xaf0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: kernel(int*, int*, int*)
_Z6kernelPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x100000, v1
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v0, 1, v1
v_add_nc_u32_e32 v4, 2, v1
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v0
v_ashrrev_i32_e32 v3, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshrrev_b32_e32 v2, 24, v2
v_lshrrev_b32_e32 v3, 24, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v0, v2
v_add_nc_u32_e32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v5, 0xffffff00, v2
v_and_b32_e32 v6, 0xffffff00, v3
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v0, v0, v5
v_sub_nc_u32_e32 v4, v4, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v5, 31, v4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v2
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v10, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v12, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
s_clause 0x2
global_load_b32 v6, v[6:7], off
global_load_b32 v7, v[10:11], off
global_load_b32 v10, v[12:13], off
s_clause 0x2
global_load_b32 v8, v[8:9], off
global_load_b32 v0, v[0:1], off
global_load_b32 v1, v[4:5], off
s_waitcnt vmcnt(3)
v_add3_u32 v4, v7, v6, v10
s_waitcnt vmcnt(0)
v_add3_u32 v0, v0, v8, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v1, v4
v_cvt_f32_i32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_scale_f32 v4, null, 0x40400000, 0x40400000, v1
v_div_scale_f32 v10, vcc_lo, v1, 0x40400000, v1
v_div_scale_f32 v5, null, 0x40400000, 0x40400000, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v6, v4
v_rcp_f32_e32 v7, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v4, v6, 1.0
v_fma_f32 v9, -v5, v7, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v6, v8, v6
v_div_scale_f32 v8, s0, v0, 0x40400000, v0
v_fmac_f32_e32 v7, v9, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v9, v10, v6
v_mul_f32_e32 v11, v8, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v12, -v4, v9, v10
v_fma_f32 v13, -v5, v11, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v9, v12, v6
v_fmac_f32_e32 v11, v13, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v4, -v4, v9, v10
v_fma_f32 v5, -v5, v11, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v4, v4, v6, v9
s_mov_b32 vcc_lo, s0
v_div_fmas_f32 v5, v5, v7, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f32 v1, v4, 0x40400000, v1
v_div_fixup_f32 v0, v5, 0x40400000, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, v1, v0
v_mul_f32_e32 v0, 0.5, v0
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v4, v0
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| kernel | 4,334 | 2,350 | stackv2-00000-of-00015 |
// Demangled: square_kernel(float*)
Function : _Z13square_kernelPf
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans8;
LDC R5, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R5, R5, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GT.AND P0, PT, R5, 0x7ffff, PT ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD.WIDE R2, R5, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans2;
FMUL R5, R0, R0 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R5 ?trans1;
EXIT ?trans5;
BRA 0xe0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: square_kernel(float*)
_Z13square_kernelPf:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x80000, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| square_kernel | 386 | 421 | stackv2-00000-of-00015 |
// Demangled: render(uchar4*, int, int)
Function : _Z6renderP6uchar4ii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R4, SR_TID.Y &wr=0x1 ?trans7;
LDC R0, c[0x0][0x360] &wr=0x2 ?trans1;
LDCU.64 UR6, c[0x0][0x388] &wr=0x3 ?trans1;
S2R R3, SR_TID.X &wr=0x2 ?trans6;
S2UR UR5, SR_CTAID.Y &wr=0x1 ?trans8;
LDC R5, c[0x0][0x364] &wr=0x1 ?trans8;
S2UR UR4, SR_CTAID.X &wr=0x2 ?trans1;
IMAD R4, R5, UR5, R4 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R4, UR7, PT &req={3} ?trans1;
IMAD R3, R0, UR4, R3 &req={2} ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R3, UR6, P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
I2FP.F32.S32 R5, UR6 ?trans1;
BSSY.RECONVERGENT B0, 0x1e0 ?trans1;
I2FP.F32.S32 R0, R3 ?trans2;
MUFU.RCP R2, R5 &wr=0x0 ?trans2;
FCHK P0, R0, R5 &wr=0x1 ?trans1;
FFMA R7, -R5, R2, 1 &req={0} ?WAIT4_END_GROUP;
FFMA R7, R2, R7, R2 ?trans1;
IMAD R2, R4, UR6, R3 ?WAIT3_END_GROUP;
FFMA R6, R0, R7, RZ ?WAIT4_END_GROUP;
FFMA R8, -R5, R6, R0 ?WAIT4_END_GROUP;
FFMA R6, R7, R8, R6 ?trans1;
@!P0 BRA 0x1d0 &req={1} ?trans6;
MOV R3, R5 ?trans1;
MOV R6, 0x1c0 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x4c0 ?trans5;
MOV R6, R10 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
LDCU UR4, c[0x0][0x38c] &wr=0x0 ?trans1;
I2FP.F32.U32 R0, R4 ?trans1;
F2F.F64.F32 R6, R6 &wr=0x1 ?trans1;
BSSY.RECONVERGENT B0, 0x380 ?trans1;
UMOV.64 UR6, 0x406fffae147ae148 ?trans1;
I2FP.F32.U32 R3, UR4 &req={0} ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans3;
MUFU.RCP R4, R3 &wr=0x2 ?trans1;
FCHK P0, R0, R3 &wr=0x3 ?trans1;
FFMA R5, -R3, R4, 1 &req={2} ?WAIT4_END_GROUP;
FFMA R5, R4, R5, R4 ?WAIT4_END_GROUP;
FFMA R4, R0, R5, RZ ?WAIT4_END_GROUP;
FFMA R8, -R3, R4, R0 ?WAIT4_END_GROUP;
FFMA R10, R5, R8, R4 ?WAIT15_END_GROUP;
NOP ?WAIT9_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R4, R6, UR6 &req={1} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2I.F64.TRUNC R4, R4 &req={1} &rd=0x1 &wr=0x2 ?trans2;
@!P0 BRA 0x370 &req={3,2,1,0} ?trans5;
MOV R6, 0x370 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x4c0 ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
LDC.64 R8, c[0x0][0x380] &wr=0x0 ?trans1;
F2F.F64.F32 R6, R10 &wr=0x1 ?trans1;
UMOV.64 UR6, 0x406fffae147ae148 ?trans1;
MOV R3, 0x46 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R6, R6, UR6 &req={1} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2I.F64.TRUNC R7, R6 &req={1} &wr=0x1 ?trans2;
PRMT R4, R7, 0x7604, R4 &req={1} ?WAIT4_END_GROUP;
PRMT R4, R3, 0x7054, R4 ?trans1;
IMAD.WIDE R2, R2, 0x4, R8 &req={0} ?WAIT3_END_GROUP;
PRMT R5, RZ, 0x654, R4 ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R5 ?trans1;
EXIT ?trans5;
SHF.R.U32.HI R7, RZ, 0x17, R3 ?trans1;
BSSY.RECONVERGENT B1, 0xb00 ?trans1;
SHF.R.U32.HI R5, RZ, 0x17, R0 ?trans2;
LOP3.LUT R12, R7, 0xff, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R10, R5, 0xff, RZ, 0xc0, !PT ?trans2;
IADD3 R8, PT, PT, R12, -0x1, RZ ?trans2;
IADD3 R7, PT, PT, R10, -0x1, RZ ?WAIT3_END_GROUP;
ISETP.GT.U32.AND P0, PT, R8, 0xfd, PT ?WAIT5_END_GROUP;
ISETP.GT.U32.OR P0, PT, R7, 0xfd, P0 ?WAIT13_END_GROUP;
@!P0 MOV R5, RZ ?trans1;
@!P0 BRA 0x6e0 ?trans6;
FSETP.GTU.FTZ.AND P0, PT, |R0|, +INF , PT ?trans1;
FSETP.GTU.FTZ.AND P1, PT, |R3|, +INF , PT ?WAIT5_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, PT, 0xf8, 0x8f ?WAIT13_END_GROUP;
@P0 BRA 0xae0 ?trans5;
LOP3.LUT P0, RZ, R3, 0x7fffffff, R0, 0xc8, !PT ?WAIT13_END_GROUP;
@!P0 BRA 0xac0 ?trans5;
FSETP.NEU.FTZ.AND P2, PT, |R0|.reuse, +INF , PT ?trans1;
FSETP.NEU.FTZ.AND P1, PT, |R3|, +INF , PT ?trans1;
FSETP.NEU.FTZ.AND P0, PT, |R0|, +INF , PT ?WAIT12_END_GROUP;
@!P1 BRA !P2, 0xac0 ?trans5;
LOP3.LUT P2, RZ, R0, 0x7fffffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P1, PT, P1, P2, PT, 0x2f, 0xf2 ?WAIT13_END_GROUP;
@P1 BRA 0xaa0 ?trans5;
LOP3.LUT P1, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, PT, 0x2f, 0xf2 ?WAIT13_END_GROUP;
@P0 BRA 0xa70 ?trans5;
ISETP.GE.AND P0, PT, R7, RZ, PT ?trans1;
ISETP.GE.AND P1, PT, R8, RZ, PT ?WAIT12_END_GROUP;
@P0 MOV R5, RZ ?trans1;
@!P0 MOV R5, 0xffffffc0 ?trans1;
@!P0 FFMA R0, R0, 1.84467440737095516160e+19, RZ ?trans1;
@!P1 FFMA R3, R3, 1.84467440737095516160e+19, RZ ?WAIT3_END_GROUP;
@!P1 IADD3 R5, PT, PT, R5, 0x40, RZ ?WAIT7_END_GROUP;
LEA R8, R12, 0xc0800000, 0x17 ?trans1;
BSSY.RECONVERGENT B2, 0xa60 ?trans3;
IADD3 R8, PT, PT, -R8, R3, RZ ?trans2;
IADD3 R3, PT, PT, R10, -0x7f, RZ ?trans2;
MUFU.RCP R7, R8 &rd=0x0 &wr=0x1 ?trans1;
FADD.FTZ R9, -R8, -RZ ?trans2;
IMAD R0, R3.reuse, -0x800000, R0 ?trans1;
IADD3 R8, PT, PT, R3, 0x7f, -R12 &req={0} ?WAIT4_END_GROUP;
IADD3 R8, PT, PT, R8, R5, RZ ?trans1;
FFMA R10, R7, R9, 1 &req={1} ?WAIT4_END_GROUP;
FFMA R14, R7, R10, R7 ?WAIT4_END_GROUP;
FFMA R7, R0, R14, RZ ?WAIT4_END_GROUP;
FFMA R10, R9, R7, R0 ?WAIT4_END_GROUP;
FFMA R11, R14, R10, R7 ?WAIT4_END_GROUP;
FFMA R10, R9, R11, R0 ?WAIT4_END_GROUP;
FFMA R7, R14, R10, R11 ?WAIT5_END_GROUP;
SHF.R.U32.HI R0, RZ, 0x17, R7 ?WAIT4_END_GROUP;
LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R9, PT, PT, R0, R8, RZ ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R9, -0x1, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R0, 0xfe, PT ?WAIT13_END_GROUP;
@!P0 BRA 0xa40 ?trans5;
ISETP.GT.AND P0, PT, R9, 0xfe, PT ?WAIT13_END_GROUP;
@P0 BRA 0xa10 ?trans5;
ISETP.GE.AND P0, PT, R9, 0x1, PT ?WAIT13_END_GROUP;
@P0 BRA 0xa50 ?trans5;
ISETP.GE.AND P0, PT, R9, -0x18, PT ?trans1;
LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ?WAIT12_END_GROUP;
@!P0 BRA 0xa50 ?trans5;
FFMA.RZ R0, R14.reuse, R10.reuse, R11.reuse ?trans1;
IADD3 R8, PT, PT, R9.reuse, 0x20, RZ ?trans1;
FFMA.RM R3, R14, R10.reuse, R11.reuse ?trans1;
ISETP.NE.AND P1, PT, R9.reuse, RZ, PT ?trans1;
ISETP.NE.AND P2, PT, R9.reuse, RZ, PT ?trans1;
LOP3.LUT R0, R0, 0x7fffff, RZ, 0xc0, !PT ?trans2;
IADD3 R9, PT, PT, -R9, RZ, RZ ?trans2;
LOP3.LUT R5, R0, 0x800000, RZ, 0xfc, !PT ?trans1;
FFMA.RP R0, R14, R10, R11 ?WAIT3_END_GROUP;
SHF.L.U32 R8, R5, R8, RZ ?trans2;
FSETP.NEU.FTZ.AND P0, PT, R0, R3, PT ?trans1;
SEL R0, R9, RZ, P2 ?trans2;
ISETP.NE.AND P1, PT, R8, RZ, P1 ?WAIT3_END_GROUP;
SHF.R.U32.HI R0, RZ, R0, R5 ?trans2;
PLOP3.LUT P0, PT, P0, P1, PT, 0xf8, 0x8f ?trans2;
SHF.R.U32.HI R8, RZ, 0x1, R0 ?WAIT3_END_GROUP;
SEL R3, RZ, 0x1, !P0 ?WAIT5_END_GROUP;
LOP3.LUT R3, R3, 0x1, R8, 0xf8, !PT ?WAIT4_END_GROUP;
LOP3.LUT R3, R3, R0, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R8, PT, PT, R8, R3, RZ ?WAIT4_END_GROUP;
LOP3.LUT R7, R8, R7, RZ, 0xfc, !PT ?trans1;
BRA 0xa50 ?trans6;
LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ?trans1;
BRA 0xa50 ?trans6;
IMAD R7, R8, 0x800000, R7 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
BRA 0xaf0 ?trans5;
LOP3.LUT R0, R3, 0x80000000, R0, 0x48, !PT ?WAIT4_END_GROUP;
LOP3.LUT R7, R0, 0x7f800000, RZ, 0xfc, !PT ?trans1;
BRA 0xaf0 ?trans6;
LOP3.LUT R7, R3, 0x80000000, R0, 0x48, !PT ?trans1;
BRA 0xaf0 ?trans6;
MUFU.RSQ R7, -QNAN &wr=0x0 ?trans1;
BRA 0xaf0 ?trans5;
FADD.FTZ R7, R0, R3 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B1 ?trans5;
MOV R10, R7 &req={0} ?trans1;
HFMA2 R7, -RZ, RZ, 0, 0 ?WAIT4_END_GROUP;
RET.REL.NODEC R6 0x0 ?trans5;
BRA 0xb30;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: render(HIP_vector_type<unsigned char, 4u>*, int, int)
_Z6renderP15HIP_vector_typeIhLj4EEii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v0
v_cmp_gt_i32_e64 s2, s5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_cvt_f32_i32_e32 v2, v0
v_cvt_f32_i32_e32 v3, s4
v_cvt_f32_i32_e32 v4, v1
v_cvt_f32_i32_e32 v5, s5
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_scale_f32 v6, null, v3, v3, v2
v_div_scale_f32 v7, null, v5, v5, v4
v_div_scale_f32 v12, vcc_lo, v2, v3, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v8, v6
v_rcp_f32_e32 v9, v7
s_waitcnt_depctr 0xfff
v_fma_f32 v10, -v6, v8, 1.0
v_fma_f32 v11, -v7, v9, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_fmac_f32 v8, v10, v8 :: v_dual_fmac_f32 v9, v11, v9
v_div_scale_f32 v10, s2, v4, v5, v4
v_mul_f32_e32 v11, v12, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v13, v10, v9
v_fma_f32 v14, -v6, v11, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v15, -v7, v13, v10
v_fmac_f32_e32 v11, v14, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v13, v15, v9
v_fma_f32 v6, -v6, v11, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v7, -v7, v13, v10
v_div_fmas_f32 v6, v6, v8, v11
s_mov_b32 vcc_lo, s2
s_mov_b32 s2, 0x147ae148
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fmas_f32 v7, v7, v9, v13
s_mov_b32 s3, 0x406fffae
v_div_fixup_f32 v4, v7, v5, v4
v_div_fixup_f32 v5, v6, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f64_f32_e32 v[2:3], v4
v_cvt_f64_f32_e32 v[4:5], v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[2:3], v[2:3], s[2:3]
v_mul_f64 v[4:5], v[4:5], s[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_i32_f64_e32 v6, v[2:3]
v_cvt_i32_f64_e32 v4, v[4:5]
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b16 v0, 8, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, 0xff, v4
v_or_b32_e32 v4, v1, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_and_b32_e32 v2, 0xffff, v4
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_or_b32_e32 v2, 0x460000, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| render | 4,037 | 1,875 | stackv2-00000-of-00015 |
// Demangled: apply_gaussian(unsigned char const*, unsigned char*, unsigned int, unsigned int, float const*, unsigned int)
Function : _Z14apply_gaussianPKhPhjjPKfj
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
LDC R2, c[0x0][0x364] &wr=0x2 ?trans1;
LDCU.64 UR6, c[0x0][0x390] &wr=0x3 ?trans1;
S2R R3, SR_TID.Y &wr=0x2 ?trans6;
S2UR UR5, SR_CTAID.X &wr=0x1 ?trans8;
LDC R5, c[0x0][0x360] &wr=0x1 ?trans8;
S2UR UR4, SR_CTAID.Y &wr=0x2 ?trans1;
IMAD R0, R5, UR5, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R0, UR6, PT &req={3} ?trans1;
IMAD R3, R2, UR4, R3 &req={2} ?WAIT5_END_GROUP;
ISETP.GE.U32.OR P0, PT, R3, UR7, P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC R6, c[0x0][0x3a0] &wr=0x0 ?trans1;
HFMA2 R29, -RZ, RZ, 0, 0 ?trans1;
LDCU.64 UR8, c[0x0][0x358] &wr=0x1 ?trans1;
UIADD3 UR4, UPT, UPT, UR7, -0x1, URZ ?trans1;
UIADD3 UR5, UPT, UPT, UR6, -0x1, URZ ?trans1;
LOP3.LUT R2, R6.reuse, 0xfffffffe, RZ, 0xc0, !PT &req={0} ?trans2;
SHF.R.U32.HI R5, RZ, 0x1, R6 ?trans2;
LOP3.LUT R4, R6, 0x6, RZ, 0xc0, !PT ?trans1;
ISETP.GE.U32.AND P1, PT, R2, 0x7, PT ?trans1;
LOP3.LUT R6, R6, 0xfffffff8, RZ, 0xc0, !PT ?WAIT2_END_GROUP;
IADD3 R2, PT, PT, -R5, RZ, RZ ?trans1;
ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ?trans1;
IADD3 R6, PT, PT, -R6, RZ, RZ ?WAIT3_END_GROUP;
MOV R8, R2 &req={1} ?WAIT9_END_GROUP;
LDC R10, c[0x0][0x3a0] &wr=0x0 ?trans1;
IADD3 R7, PT, PT, R3, R8.reuse, RZ ?trans2;
IADD3 R11, PT, PT, R5, R8, RZ ?trans1;
MOV R4, R2 ?trans2;
VIMNMX.U32 R7, R7, UR4, PT ?trans2;
IMAD R9, R11, R10, R5 &req={0} ?trans1;
@!P1 BRA 0x860 ?trans6;
LDC.64 R16, c[0x0][0x398] &wr=0x0 ?trans1;
IMAD R4, R11, R10, 0x3 ?trans1;
IADD3 R12, PT, PT, -R5, 0x3, RZ ?trans2;
IADD3 R11, PT, PT, R0, -R5, RZ ?trans1;
MOV R13, R6 ?trans1;
LDCU UR10, c[0x0][0x390] &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x380] &wr=0x2 ?trans5;
IADD3 R18, PT, PT, R11.reuse, 0x1, RZ ?trans1;
VIMNMX.U32 R20, R11.reuse, UR5, PT ?trans1;
IADD3 R19, PT, PT, R11, 0x2, RZ ?trans2;
IADD3 R27, PT, PT, R4.reuse, -0x3, RZ ?trans1;
IMAD.WIDE.U32 R14, R4, 0x4, R16 &req={0} ?trans1;
VIMNMX.U32 R18, R18, UR5, PT ?WAIT3_END_GROUP;
HFMA2 R21, -RZ, RZ, 0, 0 ?trans1;
IADD3 R23, PT, PT, R4, -0x2, RZ ?trans1;
IMAD R20, R7, UR10, R20 &req={1} ?trans1;
VIMNMX.U32 R30, R19, UR5, PT ?trans1;
IMAD R18, R7, UR10, R18 ?trans1;
MOV R19, RZ ?trans1;
IADD3 R24, PT, PT, R11, 0x3, RZ ?trans1;
IMAD.WIDE.U32 R26, R27, 0x4, R16.reuse ?trans1;
IADD3 R25, PT, PT, R11, 0x4, RZ ?trans1;
IADD.64 R20, R20, UR6 &req={2} ?trans2;
IMAD.WIDE.U32 R22, R23, 0x4, R16 ?trans1;
IADD.64 R18, R18, UR6 ?WAIT3_END_GROUP;
HFMA2 R31, -RZ, RZ, 0, 0 ?trans2;
IMAD R30, R7, UR10, R30 ?trans1;
VIMNMX.U32 R24, R24, UR5, PT ?trans1;
LDG.E R26, desc[UR8][R26.64] &rd=0x0 &wr=0x2 ?trans1;
VIMNMX.U32 R32, R25, UR5, PT ?WAIT3_END_GROUP;
LDG.E R28, desc[UR8][R14.64] &wr=0x3 ?trans1;
IADD.64 R30, R30, UR6 ?WAIT3_END_GROUP;
LDG.E R33, desc[UR8][R22.64] &rd=0x1 &wr=0x4 ?trans1;
IADD3 R27, PT, PT, R11.reuse, 0x5, RZ &req={0} ?trans2;
IADD3 R34, PT, PT, R11, 0x6, RZ ?trans1;
LDG.E.U8 R31, desc[UR8][R30.64] &wr=0x5 ?trans4;
LDG.E.U8 R14, desc[UR8][R20.64] &rd=0x0 &wr=0x2 ?trans1;
IMAD R22, R7, UR10, R24 &req={1} ?trans1;
MOV R23, RZ ?WAIT2_END_GROUP;
LDG.E.U8 R15, desc[UR8][R18.64] &rd=0x1 &wr=0x3 ?trans1;
VIMNMX.U32 R36, R27, UR5, PT ?trans1;
VIMNMX.U32 R34, R34, UR5, PT ?trans1;
IADD.64 R22, R22, UR6 ?WAIT3_END_GROUP;
IADD3 R20, PT, PT, R11, 0x7, RZ &req={0} ?trans1;
IMAD R18, R7.reuse, UR10, R32 &req={1} ?trans2;
HFMA2 R19, -RZ, RZ, 0, 0 ?trans2;
IMAD R36, R7, UR10, R36 ?trans1;
MOV R37, RZ ?trans1;
IADD3 R21, PT, PT, R4, -0x1, RZ ?trans1;
VIMNMX.U32 R20, R20, UR5, PT ?trans1;
IADD.64 R18, R18, UR6 ?trans2;
LDG.E.U8 R32, desc[UR8][R22.64] &wr=0x4 ?trans1;
IMAD R24, R7, UR10, R34 ?WAIT2_END_GROUP;
HFMA2 R25, -RZ, RZ, 0, 0 ?trans1;
IADD.64 R36, R36, UR6 ?trans2;
LDG.E.U8 R30, desc[UR8][R18.64] &rd=0x0 &wr=0x4 ?trans1;
IMAD R20, R7, UR10, R20 ?trans1;
IADD3 R35, PT, PT, R4, 0x1, RZ ?trans1;
IADD.64 R24, R24, UR6 ?trans2;
LDG.E.U8 R27, desc[UR8][R36.64] &rd=0x1 &wr=0x4 ?trans1;
IMAD.WIDE.U32 R18, R21, 0x4, R16 &req={0} ?trans1;
MOV R21, RZ ?WAIT2_END_GROUP;
LDG.E.U8 R34, desc[UR8][R24.64] &wr=0x4 ?trans1;
IMAD.WIDE.U32 R22, R35, 0x4, R16 ?trans2;
IADD.64 R20, R20, UR6 ?trans2;
LDG.E R35, desc[UR8][R18.64] &rd=0x0 &wr=0x4 ?trans1;
IADD3 R37, PT, PT, R4, 0x3, RZ &req={1} ?WAIT3_END_GROUP;
LDG.E R22, desc[UR8][R22.64] &rd=0x4 &wr=0x4 ?trans4;
LDG.E.U8 R20, desc[UR8][R20.64] &rd=0x1 &wr=0x4 ?trans1;
IADD3 R19, PT, PT, R4.reuse, 0x2, RZ &req={0} ?trans2;
IADD3 R25, PT, PT, R4, 0x4, RZ ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R18, R19, 0x4, R16 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R36, R37, 0x4, R16.reuse ?trans2;
LDG.E R18, desc[UR8][R18.64] &wr=0x4 ?trans2;
IMAD.WIDE.U32 R24, R25, 0x4, R16 ?trans2;
LDG.E R36, desc[UR8][R36.64] &wr=0x4 ?trans4;
LDG.E R24, desc[UR8][R24.64] &wr=0x4 ?trans1;
IADD3 R13, PT, PT, R13, 0x8, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P2, PT, R13, RZ, PT ?trans1;
IADD3 R12, PT, PT, R12, 0x8, RZ ?trans2;
IADD3 R4, PT, PT, R4, 0x8, RZ ?trans2;
IADD3 R11, PT, PT, R11, 0x8, RZ ?trans1;
I2F.U16 R14, R14 &req={2} &wr=0x0 ?trans1;
I2F.U16 R15, R15 &req={3} &wr=0x2 ?trans1;
I2F.U16 R31, R31 &req={5} &wr=0x3 ?trans1;
FFMA R26, R26, R14, R29 &req={0} ?trans1;
I2F.U16 R23, R32 &req={4} &wr=0x0 ?trans3;
FFMA R26, R33, R15, R26 &req={2} ?trans1;
I2F.U16 R21, R30 &req={1} &wr=0x1 ?trans1;
I2F.U16 R27, R27 &wr=0x2 ?trans2;
FFMA R35, R35, R31, R26 &req={3} ?trans1;
I2F.U16 R34, R34 &wr=0x3 ?trans3;
FFMA R23, R28, R23, R35 &req={0} ?WAIT4_END_GROUP;
FFMA R21, R22, R21, R23 &req={1} ?trans1;
I2F.U16 R20, R20 &wr=0x0 ?trans3;
FFMA R21, R18, R27, R21 &req={2} ?WAIT4_END_GROUP;
FFMA R21, R36, R34, R21 &req={3} ?WAIT4_END_GROUP;
FFMA R29, R24, R20, R21 &req={0} ?trans1;
@P2 BRA 0x290 ?trans6;
IADD3 R4, PT, PT, R12, -0x3, RZ ?WAIT7_END_GROUP;
LOP3.LUT P2, RZ, R10, 0x2, RZ, 0xc0, !PT ?trans1;
@!P0 BRA 0xb90 ?WAIT12_END_GROUP;
LDCU UR6, c[0x0][0x390] &wr=0x0 ?trans1;
IADD3 R18, PT, PT, R4, 0x1, RZ ?trans2;
IADD3 R10, PT, PT, R0, R4, RZ ?trans2;
IADD3 R17, PT, PT, R4.reuse, 0x2, RZ ?trans1;
LDCU.64 UR10, c[0x0][0x380] &wr=0x1 ?trans1;
IADD3 R16, PT, PT, R4, 0x3, RZ ?trans2;
IADD3 R11, PT, PT, R0, R18, RZ ?trans1;
VIMNMX.U32 R10, R10, UR5, PT ?trans1;
IADD3 R13, PT, PT, R0.reuse, R17, RZ ?trans1;
HFMA2 R15, -RZ, RZ, 0, 0 ?trans1;
IADD3 R19, PT, PT, R0, R16, RZ ?trans1;
VIMNMX.U32 R12, R11, UR5, PT ?WAIT2_END_GROUP;
VIMNMX.U32 R20, R13, UR5, PT ?trans1;
MOV R13, RZ ?trans1;
IMAD R14, R7.reuse, UR6, R10 &req={0} ?trans2;
LDC.64 R10, c[0x0][0x398] &wr=0x0 ?trans1;
IMAD R12, R7, UR6, R12 ?trans2;
IADD.64 R22, R14, UR10 &req={1} ?trans2;
IMAD R14, R7, UR6, R20 ?trans1;
IADD.64 R24, R12, UR10 ?WAIT2_END_GROUP;
VIMNMX.U32 R12, R19, UR5, PT ?trans1;
LDG.E.U8 R20, desc[UR8][R22.64] &rd=0x1 &wr=0x2 ?trans1;
IADD.64 R14, R14, UR10 ?WAIT3_END_GROUP;
IMAD R12, R7, UR6, R12 ?trans1;
LDG.E.U8 R21, desc[UR8][R24.64] &rd=0x3 &wr=0x4 ?trans1;
IADD3 R19, PT, PT, R9, R4, RZ ?WAIT3_END_GROUP;
IADD.64 R12, R12, UR10 ?trans2;
LDG.E.U8 R14, desc[UR8][R14.64] &wr=0x5 ?trans1;
IADD3 R27, PT, PT, R9, R18, RZ ?trans1;
IMAD.WIDE.U32 R18, R19, 0x4, R10 &req={0} ?WAIT3_END_GROUP;
LDG.E.U8 R12, desc[UR8][R12.64] &wr=0x5 ?trans1;
IADD3 R17, PT, PT, R9, R17, RZ ?trans1;
IMAD.WIDE.U32 R22, R27, 0x4, R10.reuse &req={1} ?trans1;
IADD3 R25, PT, PT, R9, R16, RZ &req={3} ?trans1;
LDG.E R18, desc[UR8][R18.64] &wr=0x3 ?trans2;
IMAD.WIDE.U32 R16, R17, 0x4, R10.reuse ?trans2;
LDG.E R23, desc[UR8][R22.64] &wr=0x3 ?trans2;
IMAD.WIDE.U32 R10, R25, 0x4, R10 ?WAIT2_END_GROUP;
LDG.E R17, desc[UR8][R16.64] &wr=0x3 ?trans4;
LDG.E R11, desc[UR8][R10.64] &wr=0x3 ?trans1;
IADD3 R4, PT, PT, R4, 0x4, RZ ?trans1;
I2F.U16 R20, R20 &req={2} &wr=0x3 ?trans1;
I2F.U16 R21, R21 &req={4} &wr=0x0 ?trans1;
I2F.U16 R14, R14 &req={5} &wr=0x1 ?trans1;
FFMA R18, R18, R20, R29 &req={3} ?trans1;
I2F.U16 R12, R12 &wr=0x2 ?trans3;
FFMA R18, R23, R21, R18 &req={0} ?WAIT4_END_GROUP;
FFMA R18, R17, R14, R18 &req={1} ?WAIT4_END_GROUP;
FFMA R29, R11, R12, R18 &req={2} ?WAIT7_END_GROUP;
@!P2 BRA 0xd50 ?trans5;
LDCU UR6, c[0x0][0x390] &wr=0x0 ?trans1;
IADD3 R18, PT, PT, R4, 0x1, RZ ?trans2;
IADD3 R10, PT, PT, R0.reuse, R4, RZ ?trans1;
MOV R17, RZ ?trans1;
LDCU.64 UR10, c[0x0][0x380] &wr=0x1 ?trans1;
IADD3 R13, PT, PT, R0, R18, RZ ?trans2;
VIMNMX.U32 R12, R10, UR5, PT ?trans2;
LDC.64 R10, c[0x0][0x398] &wr=0x2 ?trans1;
VIMNMX.U32 R16, R13, UR5, PT ?trans1;
HFMA2 R13, -RZ, RZ, 0, 0 ?WAIT2_END_GROUP;
IMAD R12, R7.reuse, UR6, R12 &req={0} ?trans2;
IMAD R16, R7, UR6, R16 ?WAIT3_END_GROUP;
IADD.64 R14, R12, UR10 &req={1} ?trans2;
IADD.64 R16, R16, UR10 ?WAIT5_END_GROUP;
LDG.E.U8 R14, desc[UR8][R14.64] &wr=0x3 ?trans1;
IADD3 R13, PT, PT, R9, R4, RZ ?WAIT3_END_GROUP;
LDG.E.U8 R16, desc[UR8][R16.64] &wr=0x4 ?trans1;
IADD3 R19, PT, PT, R9, R18, RZ ?trans1;
IMAD.WIDE.U32 R12, R13, 0x4, R10 &req={2} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R10, R19, 0x4, R10 ?trans2;
LDG.E R12, desc[UR8][R12.64] &wr=0x2 ?trans4;
LDG.E R11, desc[UR8][R10.64] &wr=0x5 ?trans1;
IADD3 R4, PT, PT, R4, 0x2, RZ ?trans1;
I2F.U16 R18, R14 &req={3} &wr=0x2 ?trans1;
I2F.U16 R19, R16 &req={4} &wr=0x5 ?trans1;
FFMA R18, R12, R18, R29 &req={2} ?WAIT4_END_GROUP;
FFMA R29, R11, R19, R18 &req={5} ?WAIT7_END_GROUP;
LDCU UR6, c[0x0][0x390] &wr=0x0 ?trans1;
IADD3 R10, PT, PT, R0, R4, RZ ?trans1;
LDC.64 R14, c[0x0][0x398] &wr=0x1 ?trans1;
MOV R11, RZ ?trans1;
LDCU.64 UR10, c[0x0][0x380] &wr=0x2 ?trans2;
VIMNMX.U32 R10, R10, UR5, PT ?WAIT5_END_GROUP;
IMAD R10, R7, UR6, R10 &req={0} ?WAIT5_END_GROUP;
IADD.64 R12, R10, UR10 &req={2} ?WAIT3_END_GROUP;
IADD3 R11, PT, PT, R9, R4, RZ ?WAIT4_END_GROUP;
LDG.E.U8 R12, desc[UR8][R12.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R10, R11, 0x4, R14 &req={1} ?WAIT6_END_GROUP;
LDG.E R10, desc[UR8][R10.64] &wr=0x3 ?trans1;
ISETP.NE.AND P2, PT, R8.reuse, R5, PT ?trans1;
IADD3 R8, PT, PT, R8, 0x1, RZ ?trans1;
I2F.U16 R4, R12 &req={2} &wr=0x3 ?trans2;
FFMA R29, R10, R4, R29 &req={3} ?WAIT9_END_GROUP;
@P2 BRA 0x1b0 ?trans5;
LDCU.64 UR4, c[0x0][0x388] &wr=0x0 ?trans1;
F2I.U32.TRUNC.NTZ R29, R29 &wr=0x1 ?trans1;
IMAD R2, R3, UR6, R0 ?trans2;
HFMA2 R3, -RZ, RZ, 0, 0 ?WAIT5_END_GROUP;
IADD.64 R2, R2, UR4 &req={0} ?WAIT6_END_GROUP;
STG.E.U8 desc[UR8][R2.64], R29 &req={1} ?trans1;
EXIT ?trans5;
BRA 0xed0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: apply_gaussian(unsigned char const*, unsigned char*, unsigned int, unsigned int, float const*, unsigned int)
_Z14apply_gaussianPKhPhjjPKfj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[8:9], s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_cmp_gt_u32_e32 vcc_lo, s9, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s8, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_7
s_clause 0x2
s_load_b32 s10, s[0:1], 0x20
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x18
v_mov_b32_e32 v2, 0
s_mov_b32 s3, 0
s_add_i32 s9, s9, -1
s_add_i32 s12, s8, -1
s_mov_b32 s15, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s11, s10, 1
s_or_b32 s14, s10, 1
v_subrev_nc_u32_e32 v3, s11, v1
s_sub_i32 s13, 0, s11
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, s13, v0
s_mov_b32 s2, s15
s_mov_b32 s16, s14
v_min_u32_e32 v4, s9, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_u32_e32 v[4:5], v4
v_max_f64 v[4:5], v[4:5], 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cvt_u32_f64_e32 v4, v[4:5]
v_mov_b32_e32 v5, v3
v_mul_lo_u32 v4, v4, s8
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_min_u32_e32 v6, s12, v5
s_lshl_b64 s[18:19], s[2:3], 2
s_add_u32 s18, s0, s18
s_addc_u32 s19, s1, s19
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_cvt_f64_u32_e32 v[6:7], v6
s_load_b32 s17, s[18:19], 0x0
s_add_i32 s16, s16, -1
s_add_i32 s2, s2, 1
s_cmp_eq_u32 s16, 0
v_max_f64 v[6:7], v[6:7], 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f64_e32 v6, v[6:7]
v_add_nc_u32_e32 v6, v4, v6
global_load_u8 v6, v6, s[4:5]
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v6, v6
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_dual_fmac_f32 v2, s17, v6 :: v_dual_add_nc_u32 v5, 1, v5
s_cbranch_scc0 .LBB0_3
s_add_i32 s2, s13, 1
s_add_i32 s15, s15, s10
s_cmp_eq_u32 s13, s11
s_cbranch_scc1 .LBB0_6
s_mov_b32 s13, s2
s_branch .LBB0_2
.LBB0_6:
v_mad_u64_u32 v[3:4], null, v0, s8, v[1:2]
v_cvt_i32_f32_e32 v0, v2
global_store_b8 v3, v0, s[6:7]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| apply_gaussian | 6,144 | 1,466 | stackv2-00000-of-00015 |
// Demangled: add_kernel(double*, double const*, double const*, unsigned long)
Function : _Z10add_kernelPdPKdS1_m
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x398] &wr=0x1 ?trans2;
ISETP.NE.S64.AND P0, PT, RZ, UR6, PT &req={1} ?WAIT14_END_GROUP;
@!P0 EXIT ?trans5;
S2R R2, SR_TID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans1;
S2R R3, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x370] &wr=0x3 ?trans1;
LDCU.64 UR8, c[0x0][0x358] &wr=0x4 ?trans5;
LDC.64 R6, c[0x0][0x390] &wr=0x5 ?trans8;
LDC.64 R8, c[0x0][0x380] &wr=0x0 ?trans1;
IMAD R2, R3, UR4, R2 &req={1} ?WAIT2_END_GROUP;
HFMA2 R3, -RZ, RZ, 0, 0 ?trans1;
UIMAD UR4, UR4, UR5, URZ &req={3} ?trans1;
IMAD.WIDE.U32 R4, R2.reuse, 0x8, R4 &req={2} ?trans2;
UMOV UR5, URZ ?trans1;
ISETP.GE.U64.AND P0, PT, R2, UR6, PT ?trans2;
IMAD.WIDE.U32 R6, R2, 0x8, R6 &req={5} ?trans1;
UMOV.64 UR6, URZ ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R2, R2, 0x8, R8 &req={4,0} ?WAIT8_END_GROUP;
@!P0 LDG.E.64 R8, desc[UR8][R4.64] &req={0} &wr=0x2 ?trans1;
LDC.64 R12, c[0x0][0x398] &wr=0x0 ?trans3;
@!P0 LDG.E.64 R10, desc[UR8][R6.64] &wr=0x2 ?trans1;
UIADD3.64 UR6, UPT, UPT, UR4, UR6, URZ ?WAIT6_END_GROUP;
ISETP.LE.U64.AND P1, PT, R12, UR6, PT &req={0} ?trans2;
@!P0 DADD R8, R8, R10 &req={2} &wr=0x0 ?trans2;
@!P0 STG.E.64 desc[UR8][R2.64], R8 &req={0} &rd=0x0 ?trans10;
@!P1 BRA 0x150 ?trans5;
EXIT ?trans5;
BRA 0x1e0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: add_kernel(double*, double const*, double const*, unsigned long)
_Z10add_kernelPdPKdS1_m:
s_load_b256 s[4:11], s[0:1], 0x0
s_mov_b64 s[2:3], 0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u64 s[10:11], 0
s_cbranch_scc1 .LBB0_5
s_clause 0x1
s_load_b32 s12, s[0:1], 0x2c
s_load_b32 s1, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s12, s12, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
v_mov_b32_e32 v2, 0
s_mul_i32 s1, s1, s12
v_lshlrev_b64 v[4:5], 3, v[1:2]
v_cmp_gt_u64_e64 s0, s[10:11], v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v2, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
.LBB0_2:
s_and_saveexec_b32 s4, s0
s_cbranch_execz .LBB0_4
global_load_b64 v[6:7], v[4:5], off
global_load_b64 v[8:9], v[2:3], off
s_waitcnt vmcnt(0)
v_add_f64 v[6:7], v[6:7], v[8:9]
global_store_b64 v[0:1], v[6:7], off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s4
s_add_u32 s2, s2, s1
s_addc_u32 s3, s3, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_u64_e64 s4, s[2:3], s[10:11]
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccz .LBB0_2
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| add_kernel | 851 | 767 | stackv2-00000-of-00015 |
// Demangled: cudaDx(float*, float*, float)
Function : _Z6cudaDxPfS_f
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R2, SR_CTAID.X &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x3 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans6;
LDC R9, c[0x0][0x390] &wr=0x4 ?trans1;
IMAD R2, R2, 0x100, R3 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE R4, R2, 0x4, R4 &req={2} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR4][R4.64] &req={3} &wr=0x2 ?trans1;
MUFU.RCP R3, R9 &req={4} &wr=0x1 ?trans1;
BSSY.RECONVERGENT B0, 0x150 ?trans1;
FFMA R6, R3, -R9, 1 &req={1} ?WAIT4_END_GROUP;
FFMA R3, R3, R6, R3 ?trans1;
FCHK P0, R0, R9 &req={2} &wr=0x1 ?trans3;
FFMA R6, R0, R3, RZ ?WAIT4_END_GROUP;
FFMA R7, R6, -R9, R0 ?WAIT4_END_GROUP;
FFMA R7, R3, R7, R6 ?trans1;
@!P0 BRA 0x140 &req={1,0} ?trans6;
MOV R4, 0x140 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x190 ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
LDC.64 R4, c[0x0][0x380] &wr=0x0 ?trans2;
IMAD.WIDE R2, R2, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R7 ?trans1;
EXIT ?trans5;
LDC R3, c[0x0][0x390] &wr=0x0 ?trans1;
SHF.R.U32.HI R5, RZ, 0x17, R0 ?trans1;
LDCU UR6, c[0x0][0x390] &wr=0x1 ?trans1;
BSSY.RECONVERGENT B1, 0x810 ?trans1;
MOV R7, R0 ?trans1;
LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R10, PT, PT, R5, -0x1, RZ ?trans1;
MOV R8, UR6 &req={1} ?trans1;
SHF.R.U32.HI R6, RZ, 0x17, R3 &req={0} ?WAIT4_END_GROUP;
LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R11, PT, PT, R6, -0x1, RZ ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ?WAIT5_END_GROUP;
ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ?WAIT13_END_GROUP;
@!P0 MOV R9, RZ ?trans1;
@!P0 BRA 0x3f0 ?trans6;
FSETP.GTU.FTZ.AND P1, PT, |R3|, +INF , PT ?trans1;
FSETP.GTU.FTZ.AND P0, PT, |R0|, +INF , PT ?WAIT5_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, PT, 0xf8, 0x8f ?WAIT13_END_GROUP;
@P0 BRA 0x7f0 ?trans5;
LOP3.LUT P0, RZ, R8, 0x7fffffff, R7, 0xc8, !PT ?WAIT13_END_GROUP;
@!P0 BRA 0x7d0 ?trans5;
FSETP.NEU.FTZ.AND P2, PT, |R0|.reuse, +INF , PT ?trans1;
FSETP.NEU.FTZ.AND P1, PT, |R3|, +INF , PT ?trans1;
FSETP.NEU.FTZ.AND P0, PT, |R0|, +INF , PT ?WAIT12_END_GROUP;
@!P1 BRA !P2, 0x7d0 ?trans5;
LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P1, PT, P1, P2, PT, 0x2f, 0xf2 ?WAIT13_END_GROUP;
@P1 BRA 0x7b0 ?trans5;
LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, PT, 0x2f, 0xf2 ?WAIT13_END_GROUP;
@P0 BRA 0x780 ?trans5;
ISETP.GE.AND P0, PT, R10, RZ, PT ?trans1;
ISETP.GE.AND P1, PT, R11, RZ, PT ?WAIT12_END_GROUP;
@P0 MOV R9, RZ ?trans1;
@!P0 MOV R9, 0xffffffc0 ?trans1;
@!P0 FFMA R7, R0, 1.84467440737095516160e+19, RZ ?trans1;
@!P1 FFMA R8, R3, 1.84467440737095516160e+19, RZ ?WAIT3_END_GROUP;
@!P1 IADD3 R9, PT, PT, R9, 0x40, RZ ?WAIT7_END_GROUP;
LEA R3, R6, 0xc0800000, 0x17 ?trans1;
BSSY.RECONVERGENT B2, 0x770 ?trans1;
IADD3 R5, PT, PT, R5, -0x7f, RZ ?trans2;
IADD3 R3, PT, PT, -R3, R8, RZ ?WAIT3_END_GROUP;
IMAD R0, R5.reuse, -0x800000, R7 ?trans1;
IADD3 R6, PT, PT, R5, 0x7f, -R6 ?trans1;
MUFU.RCP R8, R3 &wr=0x0 ?trans1;
FADD.FTZ R11, -R3, -RZ ?trans2;
IADD3 R6, PT, PT, R6, R9, RZ ?trans2;
FFMA R13, R8, R11, 1 &req={0} ?WAIT4_END_GROUP;
FFMA R10, R8, R13, R8 ?WAIT4_END_GROUP;
FFMA R7, R0, R10, RZ ?WAIT4_END_GROUP;
FFMA R8, R11, R7, R0 ?WAIT4_END_GROUP;
FFMA R13, R10, R8, R7 ?WAIT4_END_GROUP;
FFMA R8, R11, R13, R0 ?WAIT4_END_GROUP;
FFMA R7, R10, R8, R13 ?WAIT5_END_GROUP;
SHF.R.U32.HI R0, RZ, 0x17, R7 ?WAIT4_END_GROUP;
LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R9, PT, PT, R0, R6, RZ ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R9, -0x1, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R0, 0xfe, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x750 ?trans5;
ISETP.GT.AND P0, PT, R9, 0xfe, PT ?WAIT13_END_GROUP;
@P0 BRA 0x720 ?trans5;
ISETP.GE.AND P0, PT, R9, 0x1, PT ?WAIT13_END_GROUP;
@P0 BRA 0x760 ?trans5;
ISETP.GE.AND P0, PT, R9, -0x18, PT ?trans1;
LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ?WAIT12_END_GROUP;
@!P0 BRA 0x760 ?trans5;
FFMA.RZ R0, R10.reuse, R8.reuse, R13.reuse ?trans1;
IADD3 R6, PT, PT, R9.reuse, 0x20, RZ ?trans1;
FFMA.RM R3, R10, R8, R13 ?trans1;
ISETP.NE.AND P1, PT, R9.reuse, RZ, PT ?trans1;
ISETP.NE.AND P2, PT, R9, RZ, PT ?trans1;
LOP3.LUT R0, R0, 0x7fffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
LOP3.LUT R5, R0, 0x800000, RZ, 0xfc, !PT ?trans1;
FFMA.RP R0, R10, R8, R13 ?trans1;
IADD3 R8, PT, PT, -R9, RZ, RZ ?trans2;
SHF.L.U32 R6, R5, R6, RZ ?trans2;
FSETP.NEU.FTZ.AND P0, PT, R0, R3, PT ?trans1;
SEL R0, R8, RZ, P2 ?trans2;
ISETP.NE.AND P1, PT, R6, RZ, P1 ?WAIT3_END_GROUP;
SHF.R.U32.HI R0, RZ, R0, R5 ?trans2;
PLOP3.LUT P0, PT, P0, P1, PT, 0xf8, 0x8f ?trans2;
SHF.R.U32.HI R6, RZ, 0x1, R0 ?WAIT3_END_GROUP;
SEL R3, RZ, 0x1, !P0 ?WAIT5_END_GROUP;
LOP3.LUT R3, R3, 0x1, R6, 0xf8, !PT ?WAIT4_END_GROUP;
LOP3.LUT R3, R3, R0, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R6, PT, PT, R6, R3, RZ ?WAIT4_END_GROUP;
LOP3.LUT R7, R6, R7, RZ, 0xfc, !PT ?trans1;
BRA 0x760 ?trans6;
LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ?trans1;
BRA 0x760 ?trans6;
IMAD R7, R6, 0x800000, R7 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
BRA 0x800 ?trans5;
LOP3.LUT R7, R8, 0x80000000, R7, 0x48, !PT ?WAIT4_END_GROUP;
LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ?trans1;
BRA 0x800 ?trans6;
LOP3.LUT R7, R8, 0x80000000, R7, 0x48, !PT ?trans1;
BRA 0x800 ?trans6;
MUFU.RSQ R7, -QNAN &wr=0x0 ?trans1;
BRA 0x800 ?trans5;
FADD.FTZ R7, R0, R3 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B1 ?trans5;
HFMA2 R5, -RZ, RZ, 0, 0 ?WAIT4_END_GROUP;
RET.REL.NODEC R4 0x0 &req={0} ?trans5;
BRA 0x830;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: cudaDx(float*, float*, float)
_Z6cudaDxPfS_f:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshl_add_u32 v0, s15, 8, v0
s_load_b32 s0, s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v3, null, s0, s0, v2
v_div_scale_f32 v6, vcc_lo, v2, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
v_fmac_f32_e32 v4, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v6, v4
v_fma_f32 v7, -v3, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v7, v4
v_fma_f32 v3, -v3, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f32 v3, v3, v4, v5
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
v_div_fixup_f32 v2, v3, s0, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| cudaDx | 3,240 | 702 | stackv2-00000-of-00015 |
// Demangled: cudaDy(float*, float*, int)
Function : _Z6cudaDyPfS_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
LDC R8, c[0x0][0x390] &wr=0x1 ?trans1;
S2R R4, SR_CTAID.X &wr=0x2 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x3 ?trans1;
HFMA2 R12, -RZ, RZ, 0, 0 ?trans1;
S2R R3, SR_TID.X &wr=0x2 ?trans1;
ISETP.GE.AND P0, PT, R8, 0x1, PT &req={1} ?trans1;
IMAD R4, R4, 0x100, R3 &req={2} ?WAIT12_END_GROUP;
@!P0 BRA 0x1570 &req={3,0} ?trans5;
ISETP.GE.U32.AND P0, PT, R8, 0x8, PT ?trans1;
IADD3 R2, PT, PT, R4, 0x1, RZ ?trans2;
LOP3.LUT R11, R8, 0x7, RZ, 0xc0, !PT ?trans1;
CS2R R12, SRZ ?trans1;
I2FP.F32.S32 R2, R2 ?WAIT8_END_GROUP;
@!P0 BRA 0xb60 ?trans5;
LDCU.64 UR4, c[0x0][0x380] &wr=0x0 ?trans1;
LOP3.LUT R8, R8, 0x7ffffff8, RZ, 0xc0, !PT ?trans1;
HFMA2 R10, -RZ, RZ, 0, 2.384185791015625e-07 ?trans1;
MOV R12, RZ ?trans1;
MOV R9, R4 ?trans1;
IADD3 R8, PT, PT, -R8, RZ, RZ ?trans1;
UIADD3.64 UR4, UPT, UPT, UR4, 0x10, URZ &req={0} ?WAIT6_END_GROUP;
MOV.64 R14, UR4 ?WAIT8_END_GROUP;
LDG.E R3, desc[UR6][R14.64+-0x10] &wr=0x2 ?trans1;
IADD3 R17, PT, PT, R9, 0x1, RZ ?trans2;
I2FP.F32.S32 R0, R9 ?trans1;
BSSY.RECONVERGENT B2, 0x2c0 ?trans1;
IADD3 R8, PT, PT, R8, 0x8, RZ ?trans2;
I2FP.F32.S32 R17, R17 ?WAIT3_END_GROUP;
ISETP.NE.AND P2, PT, R8, RZ, PT ?trans2;
FMUL R5, R17, 0.5 ?WAIT4_END_GROUP;
FFMA R16, R5, R0, R2 ?WAIT4_END_GROUP;
MUFU.RCP R0, R16 &wr=0x0 ?trans2;
FFMA R5, -R16, R0, 1 &req={0} ?WAIT4_END_GROUP;
FFMA R0, R0, R5, R0 ?trans1;
FCHK P0, R3, R16 &req={2} &wr=0x0 ?trans3;
FFMA R5, R3, R0, RZ ?WAIT4_END_GROUP;
FFMA R6, -R16, R5, R3 ?WAIT4_END_GROUP;
FFMA R0, R0, R6, R5 ?trans1;
@!P0 BRA 0x2b0 &req={0} ?trans6;
MOV R0, R16 ?trans1;
MOV R6, 0x2b0 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x15b0 ?trans5;
BSYNC.RECONVERGENT B2 ?trans5;
LDG.E R3, desc[UR6][R14.64+-0xc] &wr=0x2 ?trans1;
IADD3 R13, PT, PT, R9, 0x2, RZ ?trans1;
BSSY.RECONVERGENT B2, 0x3f0 ?trans1;
FADD R12, R0, R12 ?trans2;
I2FP.F32.S32 R13, R13 ?WAIT5_END_GROUP;
FMUL R5, R13, 0.5 ?WAIT4_END_GROUP;
FFMA R16, R17, R5, R2 ?WAIT4_END_GROUP;
MUFU.RCP R5, R16 &wr=0x0 ?trans2;
FFMA R6, -R16, R5, 1 &req={0} ?WAIT4_END_GROUP;
FFMA R6, R5, R6, R5 ?trans1;
FCHK P0, R3, R16 &req={2} &wr=0x0 ?trans3;
FFMA R5, R3, R6, RZ ?WAIT4_END_GROUP;
FFMA R7, -R16, R5, R3 ?WAIT4_END_GROUP;
FFMA R0, R6, R7, R5 ?trans1;
@!P0 BRA 0x3e0 &req={0} ?trans6;
MOV R0, R16 ?trans1;
MOV R6, 0x3e0 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x15b0 ?trans5;
BSYNC.RECONVERGENT B2 ?trans5;
LDG.E R3, desc[UR6][R14.64+-0x8] &wr=0x2 ?trans1;
IADD3 R17, PT, PT, R9, 0x3, RZ ?trans1;
BSSY.RECONVERGENT B2, 0x520 ?trans1;
FADD R12, R12, R0 ?trans2;
I2FP.F32.S32 R17, R17 ?WAIT5_END_GROUP;
FMUL R5, R17, 0.5 ?WAIT4_END_GROUP;
FFMA R16, R13, R5, R2 ?WAIT4_END_GROUP;
MUFU.RCP R5, R16 &wr=0x0 ?trans2;
FFMA R6, -R16, R5, 1 &req={0} ?WAIT4_END_GROUP;
FFMA R6, R5, R6, R5 ?trans1;
FCHK P0, R3, R16 &req={2} &wr=0x0 ?trans3;
FFMA R5, R3, R6, RZ ?WAIT4_END_GROUP;
FFMA R7, -R16, R5, R3 ?WAIT4_END_GROUP;
FFMA R0, R6, R7, R5 ?trans1;
@!P0 BRA 0x510 &req={0} ?trans6;
MOV R0, R16 ?trans1;
MOV R6, 0x510 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x15b0 ?trans5;
BSYNC.RECONVERGENT B2 ?trans5;
LDG.E R3, desc[UR6][R14.64+-0x4] &wr=0x2 ?trans1;
IADD3 R13, PT, PT, R9, 0x4, RZ ?trans1;
BSSY.RECONVERGENT B2, 0x650 ?trans1;
FADD R12, R12, R0 ?trans2;
I2FP.F32.S32 R13, R13 ?WAIT5_END_GROUP;
FMUL R5, R13, 0.5 ?WAIT4_END_GROUP;
FFMA R16, R17, R5, R2 ?WAIT4_END_GROUP;
MUFU.RCP R5, R16 &wr=0x0 ?trans2;
FFMA R6, -R16, R5, 1 &req={0} ?WAIT4_END_GROUP;
FFMA R6, R5, R6, R5 ?trans1;
FCHK P0, R3, R16 &req={2} &wr=0x0 ?trans3;
FFMA R5, R3, R6, RZ ?WAIT4_END_GROUP;
FFMA R7, -R16, R5, R3 ?WAIT4_END_GROUP;
FFMA R0, R6, R7, R5 ?trans1;
@!P0 BRA 0x640 &req={0} ?trans6;
MOV R0, R16 ?trans1;
MOV R6, 0x640 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x15b0 ?trans5;
BSYNC.RECONVERGENT B2 ?trans5;
LDG.E R3, desc[UR6][R14.64] &wr=0x2 ?trans1;
IADD3 R17, PT, PT, R9, 0x5, RZ ?trans1;
BSSY.RECONVERGENT B2, 0x780 ?trans1;
FADD R12, R12, R0 ?trans2;
I2FP.F32.S32 R17, R17 ?WAIT5_END_GROUP;
FMUL R5, R17, 0.5 ?WAIT4_END_GROUP;
FFMA R16, R13, R5, R2 ?WAIT4_END_GROUP;
MUFU.RCP R5, R16 &wr=0x0 ?trans2;
FFMA R6, -R16, R5, 1 &req={0} ?WAIT4_END_GROUP;
FFMA R6, R5, R6, R5 ?trans1;
FCHK P0, R3, R16 &req={2} &wr=0x0 ?trans3;
FFMA R5, R3, R6, RZ ?WAIT4_END_GROUP;
FFMA R7, -R16, R5, R3 ?WAIT4_END_GROUP;
FFMA R0, R6, R7, R5 ?trans1;
@!P0 BRA 0x770 &req={0} ?trans6;
MOV R0, R16 ?trans1;
MOV R6, 0x770 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x15b0 ?trans5;
BSYNC.RECONVERGENT B2 ?trans5;
LDG.E R3, desc[UR6][R14.64+0x4] &wr=0x2 ?trans1;
IADD3 R13, PT, PT, R9, 0x6, RZ ?trans1;
BSSY.RECONVERGENT B2, 0x8b0 ?trans1;
FADD R12, R12, R0 ?trans2;
I2FP.F32.S32 R13, R13 ?WAIT5_END_GROUP;
FMUL R5, R13, 0.5 ?WAIT4_END_GROUP;
FFMA R16, R17, R5, R2 ?WAIT4_END_GROUP;
MUFU.RCP R5, R16 &wr=0x0 ?trans2;
FFMA R6, -R16, R5, 1 &req={0} ?WAIT4_END_GROUP;
FFMA R6, R5, R6, R5 ?trans1;
FCHK P0, R3, R16 &req={2} &wr=0x0 ?trans3;
FFMA R5, R3, R6, RZ ?WAIT4_END_GROUP;
FFMA R7, -R16, R5, R3 ?WAIT4_END_GROUP;
FFMA R0, R6, R7, R5 ?trans1;
@!P0 BRA 0x8a0 &req={0} ?trans6;
MOV R0, R16 ?trans1;
MOV R6, 0x8a0 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x15b0 ?trans5;
BSYNC.RECONVERGENT B2 ?trans5;
LDG.E R3, desc[UR6][R14.64+0x8] &wr=0x2 ?trans1;
IADD3 R17, PT, PT, R9, 0x7, RZ ?trans1;
BSSY.RECONVERGENT B2, 0x9e0 ?trans1;
FADD R12, R12, R0 ?trans2;
I2FP.F32.S32 R17, R17 ?WAIT5_END_GROUP;
FMUL R5, R17, 0.5 ?WAIT4_END_GROUP;
FFMA R16, R13, R5, R2 ?WAIT4_END_GROUP;
MUFU.RCP R5, R16 &wr=0x0 ?trans2;
FFMA R6, -R16, R5, 1 &req={0} ?WAIT4_END_GROUP;
FFMA R6, R5, R6, R5 ?trans1;
FCHK P0, R3, R16 &req={2} &wr=0x0 ?trans3;
FFMA R5, R3, R6, RZ ?WAIT4_END_GROUP;
FFMA R7, -R16, R5, R3 ?WAIT4_END_GROUP;
FFMA R0, R6, R7, R5 ?trans1;
@!P0 BRA 0x9d0 &req={0} ?trans6;
MOV R0, R16 ?trans1;
MOV R6, 0x9d0 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x15b0 ?trans5;
BSYNC.RECONVERGENT B2 ?trans5;
LDG.E R3, desc[UR6][R14.64+0xc] &wr=0x2 ?trans1;
IADD3 R9, PT, PT, R9, 0x8, RZ ?trans1;
BSSY.RECONVERGENT B2, 0xb10 ?trans1;
FADD R12, R12, R0 ?trans2;
I2FP.F32.S32 R5, R9 ?WAIT5_END_GROUP;
FMUL R5, R5, 0.5 ?WAIT4_END_GROUP;
FFMA R16, R17, R5, R2 ?WAIT4_END_GROUP;
MUFU.RCP R5, R16 &wr=0x0 ?trans2;
FFMA R6, -R16, R5, 1 &req={0} ?WAIT4_END_GROUP;
FFMA R6, R5, R6, R5 ?trans1;
FCHK P0, R3, R16 &req={2} &wr=0x0 ?trans3;
FFMA R5, R3, R6, RZ ?WAIT4_END_GROUP;
FFMA R7, -R16, R5, R3 ?WAIT4_END_GROUP;
FFMA R0, R6, R7, R5 ?trans1;
@!P0 BRA 0xb00 &req={0} ?trans6;
MOV R0, R16 ?trans1;
MOV R6, 0xb00 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x15b0 ?trans5;
BSYNC.RECONVERGENT B2 ?trans5;
IADD.64 R14, R14, 0x20 ?trans2;
FADD R12, R12, R0 ?trans1;
IADD3 R10, PT, PT, R10, 0x8, RZ ?trans1;
@P2 BRA 0x170 ?trans6;
IADD3 R13, PT, PT, R10, -0x4, RZ ?WAIT7_END_GROUP;
ISETP.NE.AND P0, PT, R11, RZ, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x1570 ?trans5;
LDC R14, c[0x0][0x390] &wr=0x0 ?trans1;
ISETP.GE.U32.AND P0, PT, R11, 0x4, PT ?trans1;
LOP3.LUT R14, R14, 0x3, RZ, 0xc0, !PT &req={0} ?WAIT12_END_GROUP;
@!P0 BRA 0x10d0 ?trans5;
LDC.64 R8, c[0x0][0x380] &wr=0x0 ?trans2;
IMAD.WIDE.U32 R8, R13, 0x4, R8 &req={0} ?WAIT5_END_GROUP;
LDG.E R3, desc[UR6][R8.64] &wr=0x2 ?trans1;
IADD3 R10, PT, PT, R4, R13, RZ ?trans1;
BSSY.RECONVERGENT B2, 0xd20 ?trans3;
IADD3 R15, PT, PT, R10, 0x1, RZ ?trans2;
I2FP.F32.S32 R0, R10 ?trans2;
I2FP.F32.S32 R15, R15 ?WAIT5_END_GROUP;
FMUL R5, R15, 0.5 ?WAIT4_END_GROUP;
FFMA R16, R5, R0, R2 ?WAIT4_END_GROUP;
MUFU.RCP R0, R16 &wr=0x0 ?trans2;
FFMA R5, -R16, R0, 1 &req={0} ?WAIT4_END_GROUP;
FFMA R0, R0, R5, R0 ?trans1;
FCHK P0, R3, R16 &req={2} &wr=0x0 ?trans3;
FFMA R5, R3, R0, RZ ?WAIT4_END_GROUP;
FFMA R6, -R16, R5, R3 ?WAIT4_END_GROUP;
FFMA R0, R0, R6, R5 ?trans1;
@!P0 BRA 0xd10 &req={0} ?trans6;
MOV R0, R16 ?trans1;
MOV R6, 0xd10 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x15b0 ?trans5;
BSYNC.RECONVERGENT B2 ?trans5;
LDG.E R3, desc[UR6][R8.64+0x4] &wr=0x2 ?trans1;
IADD3 R11, PT, PT, R10, 0x2, RZ ?trans1;
BSSY.RECONVERGENT B2, 0xe50 ?trans1;
FADD R12, R12, R0 ?trans2;
I2FP.F32.S32 R11, R11 ?WAIT5_END_GROUP;
FMUL R5, R11, 0.5 ?WAIT4_END_GROUP;
FFMA R16, R15, R5, R2 ?WAIT4_END_GROUP;
MUFU.RCP R5, R16 &wr=0x0 ?trans2;
FFMA R6, -R16, R5, 1 &req={0} ?WAIT4_END_GROUP;
FFMA R6, R5, R6, R5 ?trans1;
FCHK P0, R3, R16 &req={2} &wr=0x0 ?trans3;
FFMA R5, R3, R6, RZ ?WAIT4_END_GROUP;
FFMA R7, -R16, R5, R3 ?WAIT4_END_GROUP;
FFMA R0, R6, R7, R5 ?trans1;
@!P0 BRA 0xe40 &req={0} ?trans6;
MOV R0, R16 ?trans1;
MOV R6, 0xe40 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x15b0 ?trans5;
BSYNC.RECONVERGENT B2 ?trans5;
LDG.E R3, desc[UR6][R8.64+0x8] &wr=0x2 ?trans1;
IADD3 R15, PT, PT, R10, 0x3, RZ ?trans1;
BSSY.RECONVERGENT B2, 0xf80 ?trans1;
FADD R12, R12, R0 ?trans2;
I2FP.F32.S32 R15, R15 ?WAIT5_END_GROUP;
FMUL R5, R15, 0.5 ?WAIT4_END_GROUP;
FFMA R16, R11, R5, R2 ?WAIT4_END_GROUP;
MUFU.RCP R5, R16 &wr=0x0 ?trans2;
FFMA R6, -R16, R5, 1 &req={0} ?WAIT4_END_GROUP;
FFMA R6, R5, R6, R5 ?trans1;
FCHK P0, R3, R16 &req={2} &wr=0x0 ?trans3;
FFMA R5, R3, R6, RZ ?WAIT4_END_GROUP;
FFMA R7, -R16, R5, R3 ?WAIT4_END_GROUP;
FFMA R0, R6, R7, R5 ?trans1;
@!P0 BRA 0xf70 &req={0} ?trans6;
MOV R0, R16 ?trans1;
MOV R6, 0xf70 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x15b0 ?trans5;
BSYNC.RECONVERGENT B2 ?trans5;
LDG.E R3, desc[UR6][R8.64+0xc] &wr=0x2 ?trans1;
IADD3 R10, PT, PT, R10, 0x4, RZ ?trans1;
BSSY.RECONVERGENT B2, 0x10b0 ?trans1;
FADD R12, R12, R0 ?trans2;
I2FP.F32.S32 R10, R10 ?WAIT5_END_GROUP;
FMUL R10, R10, 0.5 ?WAIT4_END_GROUP;
FFMA R10, R15, R10, R2 ?WAIT4_END_GROUP;
MUFU.RCP R5, R10 &wr=0x0 ?trans2;
FFMA R6, -R10, R5, 1 &req={0} ?WAIT4_END_GROUP;
FFMA R6, R5, R6, R5 ?trans1;
FCHK P0, R3, R10 &req={2} &wr=0x0 ?trans3;
FFMA R5, R3, R6, RZ ?WAIT4_END_GROUP;
FFMA R7, -R10, R5, R3 ?WAIT4_END_GROUP;
FFMA R0, R6, R7, R5 ?trans1;
@!P0 BRA 0x10a0 &req={0} ?trans6;
MOV R0, R10 ?trans1;
MOV R6, 0x10a0 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x15b0 ?trans5;
BSYNC.RECONVERGENT B2 ?trans5;
FADD R12, R12, R0 ?trans1;
IADD3 R13, PT, PT, R13, 0x4, RZ ?WAIT7_END_GROUP;
ISETP.NE.AND P0, PT, R14, RZ, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x1570 ?trans5;
ISETP.NE.AND P0, PT, R14, 0x1, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x13c0 ?trans5;
LDC.64 R10, c[0x0][0x380] &wr=0x0 ?trans2;
IMAD.WIDE.U32 R10, R13, 0x4, R10 &req={0} ?WAIT5_END_GROUP;
LDG.E R3, desc[UR6][R10.64] &wr=0x2 ?trans1;
IADD3 R8, PT, PT, R4, R13, RZ ?trans1;
BSSY.RECONVERGENT B2, 0x1270 ?trans3;
IADD3 R9, PT, PT, R8, 0x1, RZ ?trans2;
I2FP.F32.S32 R0, R8 ?trans2;
I2FP.F32.S32 R9, R9 ?WAIT5_END_GROUP;
FMUL R5, R9, 0.5 ?WAIT4_END_GROUP;
FFMA R14, R5, R0, R2 ?WAIT4_END_GROUP;
MUFU.RCP R0, R14 &wr=0x0 ?trans2;
FFMA R5, -R14, R0, 1 &req={0} ?WAIT4_END_GROUP;
FFMA R0, R0, R5, R0 ?trans1;
FCHK P0, R3, R14 &req={2} &wr=0x0 ?trans3;
FFMA R5, R3, R0, RZ ?WAIT4_END_GROUP;
FFMA R6, -R14, R5, R3 ?WAIT4_END_GROUP;
FFMA R0, R0, R6, R5 ?trans1;
@!P0 BRA 0x1260 &req={0} ?trans6;
MOV R0, R14 ?trans1;
MOV R6, 0x1260 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x15b0 ?trans5;
BSYNC.RECONVERGENT B2 ?trans5;
LDG.E R3, desc[UR6][R10.64+0x4] &wr=0x2 ?trans1;
IADD3 R8, PT, PT, R8, 0x2, RZ ?trans1;
BSSY.RECONVERGENT B2, 0x13a0 ?trans1;
FADD R12, R12, R0 ?trans2;
I2FP.F32.S32 R8, R8 ?WAIT5_END_GROUP;
FMUL R8, R8, 0.5 ?WAIT4_END_GROUP;
FFMA R8, R9, R8, R2 ?WAIT4_END_GROUP;
MUFU.RCP R5, R8 &wr=0x0 ?trans2;
FFMA R6, -R8, R5, 1 &req={0} ?WAIT4_END_GROUP;
FFMA R6, R5, R6, R5 ?trans1;
FCHK P0, R3, R8 &req={2} &wr=0x0 ?trans3;
FFMA R5, R3, R6, RZ ?WAIT4_END_GROUP;
FFMA R7, -R8, R5, R3 ?WAIT4_END_GROUP;
FFMA R0, R6, R7, R5 ?trans1;
@!P0 BRA 0x1390 &req={0} ?trans6;
MOV R0, R8 ?trans1;
MOV R6, 0x1390 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x15b0 ?trans5;
BSYNC.RECONVERGENT B2 ?trans5;
FADD R12, R12, R0 ?trans1;
IADD3 R13, PT, PT, R13, 0x2, RZ ?WAIT7_END_GROUP;
LDC R0, c[0x0][0x390] &wr=0x0 ?trans2;
LOP3.LUT R0, R0, 0x1, RZ, 0xc0, !PT &req={0} ?WAIT5_END_GROUP;
ISETP.NE.U32.AND P0, PT, R0, 0x1, PT ?WAIT13_END_GROUP;
@P0 BRA 0x1570 ?trans5;
LDC.64 R6, c[0x0][0x380] &wr=0x0 ?trans2;
IMAD.WIDE.U32 R6, R13, 0x4, R6 &req={0} ?WAIT5_END_GROUP;
LDG.E R3, desc[UR6][R6.64] &wr=0x2 ?trans1;
IADD3 R13, PT, PT, R4, R13, RZ ?trans1;
BSSY.RECONVERGENT B2, 0x1560 ?trans3;
IADD3 R0, PT, PT, R13, 0x1, RZ ?trans2;
I2FP.F32.S32 R13, R13 ?trans2;
I2FP.F32.S32 R0, R0 ?WAIT5_END_GROUP;
FMUL R5, R0, 0.5 ?WAIT4_END_GROUP;
FFMA R8, R5, R13, R2 ?WAIT4_END_GROUP;
MUFU.RCP R0, R8 &wr=0x0 ?trans2;
FFMA R5, -R8, R0, 1 &req={0} ?WAIT4_END_GROUP;
FFMA R0, R0, R5, R0 ?trans1;
FCHK P0, R3, R8 &req={2} &wr=0x0 ?trans3;
FFMA R5, R3, R0, RZ ?WAIT4_END_GROUP;
FFMA R2, -R8, R5, R3 ?WAIT4_END_GROUP;
FFMA R0, R0, R2, R5 ?trans1;
@!P0 BRA 0x1550 &req={0} ?trans6;
MOV R0, R8 ?trans1;
MOV R6, 0x1550 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x15b0 ?trans5;
BSYNC.RECONVERGENT B2 ?trans5;
FADD R12, R12, R0 ?WAIT7_END_GROUP;
LDC.64 R2, c[0x0][0x388] &wr=0x0 ?trans2;
IMAD.WIDE R4, R4, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R4.64], R12 ?trans1;
EXIT ?trans5;
SHF.R.U32.HI R5, RZ, 0x17, R0 ?trans1;
BSSY.RECONVERGENT B0, 0x1bf0 ?trans1;
SHF.R.U32.HI R16, RZ, 0x17, R3 ?trans2;
LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R16, R16, 0xff, RZ, 0xc0, !PT ?trans2;
IADD3 R18, PT, PT, R5, -0x1, RZ ?trans2;
IADD3 R19, PT, PT, R16, -0x1, RZ ?WAIT3_END_GROUP;
ISETP.GT.U32.AND P0, PT, R18, 0xfd, PT ?WAIT5_END_GROUP;
ISETP.GT.U32.OR P0, PT, R19, 0xfd, P0 ?WAIT13_END_GROUP;
@!P0 MOV R7, RZ ?trans1;
@!P0 BRA 0x17d0 ?trans6;
FSETP.GTU.FTZ.AND P0, PT, |R3|, +INF , PT ?trans1;
FSETP.GTU.FTZ.AND P1, PT, |R0|, +INF , PT ?WAIT5_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, PT, 0xf8, 0x8f ?WAIT13_END_GROUP;
@P0 BRA 0x1bd0 ?trans5;
LOP3.LUT P0, RZ, R0, 0x7fffffff, R3, 0xc8, !PT ?WAIT13_END_GROUP;
@!P0 BRA 0x1bb0 ?trans5;
FSETP.NEU.FTZ.AND P3, PT, |R3|.reuse, +INF , PT ?trans1;
FSETP.NEU.FTZ.AND P1, PT, |R0|, +INF , PT ?trans1;
FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ?WAIT12_END_GROUP;
@!P1 BRA !P3, 0x1bb0 ?trans5;
LOP3.LUT P3, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P1, PT, P1, P3, PT, 0x2f, 0xf2 ?WAIT13_END_GROUP;
@P1 BRA 0x1b90 ?trans5;
LOP3.LUT P1, RZ, R0, 0x7fffffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, PT, 0x2f, 0xf2 ?WAIT13_END_GROUP;
@P0 BRA 0x1b60 ?trans5;
ISETP.GE.AND P0, PT, R19, RZ, PT ?trans1;
ISETP.GE.AND P1, PT, R18, RZ, PT ?WAIT12_END_GROUP;
@P0 MOV R7, RZ ?trans1;
@!P0 MOV R7, 0xffffffc0 ?trans1;
@!P0 FFMA R3, R3, 1.84467440737095516160e+19, RZ ?trans1;
@!P1 FFMA R0, R0, 1.84467440737095516160e+19, RZ ?WAIT3_END_GROUP;
@!P1 IADD3 R7, PT, PT, R7, 0x40, RZ ?WAIT7_END_GROUP;
LEA R19, R5, 0xc0800000, 0x17 ?trans1;
BSSY.RECONVERGENT B1, 0x1b50 ?trans1;
IADD3 R16, PT, PT, R16, -0x7f, RZ ?trans2;
IADD3 R20, PT, PT, -R19, R0, RZ ?WAIT3_END_GROUP;
IMAD R0, R16.reuse, -0x800000, R3 ?trans1;
IADD3 R16, PT, PT, R16, 0x7f, -R5 ?trans1;
MUFU.RCP R18, R20 &wr=0x0 ?trans1;
FADD.FTZ R19, -R20, -RZ ?trans2;
IADD3 R7, PT, PT, R16, R7, RZ ?trans2;
FFMA R21, R18, R19, 1 &req={0} ?WAIT4_END_GROUP;
FFMA R21, R18, R21, R18 ?WAIT4_END_GROUP;
FFMA R18, R0, R21, RZ ?WAIT4_END_GROUP;
FFMA R3, R19, R18, R0 ?WAIT4_END_GROUP;
FFMA R18, R21, R3, R18 ?WAIT4_END_GROUP;
FFMA R19, R19, R18, R0 ?WAIT4_END_GROUP;
FFMA R0, R21, R19, R18 ?WAIT5_END_GROUP;
SHF.R.U32.HI R3, RZ, 0x17, R0 ?WAIT4_END_GROUP;
LOP3.LUT R16, R3, 0xff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R3, PT, PT, R16, R7, RZ ?WAIT4_END_GROUP;
IADD3 R5, PT, PT, R3, -0x1, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x1b30 ?trans5;
ISETP.GT.AND P0, PT, R3, 0xfe, PT ?WAIT13_END_GROUP;
@P0 BRA 0x1b00 ?trans5;
ISETP.GE.AND P0, PT, R3, 0x1, PT ?WAIT13_END_GROUP;
@P0 BRA 0x1b40 ?trans5;
ISETP.GE.AND P0, PT, R3, -0x18, PT ?trans1;
LOP3.LUT R0, R0, 0x80000000, RZ, 0xc0, !PT ?WAIT12_END_GROUP;
@!P0 BRA 0x1b40 ?trans5;
FFMA.RZ R16, R21, R19.reuse, R18.reuse ?trans1;
IADD3 R5, PT, PT, R3, 0x20, RZ ?trans1;
FFMA.RP R7, R21.reuse, R19.reuse, R18.reuse ?trans1;
FFMA.RM R18, R21, R19, R18 ?trans1;
ISETP.NE.AND P1, PT, R3.reuse, RZ, PT ?trans1;
LOP3.LUT R16, R16, 0x7fffff, RZ, 0xc0, !PT ?trans1;
ISETP.NE.AND P3, PT, R3.reuse, RZ, PT ?trans1;
IADD3 R3, PT, PT, -R3, RZ, RZ ?trans2;
LOP3.LUT R16, R16, 0x800000, RZ, 0xfc, !PT ?trans1;
FSETP.NEU.FTZ.AND P0, PT, R7, R18, PT ?WAIT3_END_GROUP;
SHF.L.U32 R5, R16, R5, RZ ?trans1;
SEL R3, R3, RZ, P3 ?WAIT4_END_GROUP;
ISETP.NE.AND P1, PT, R5, RZ, P1 ?trans1;
SHF.R.U32.HI R16, RZ, R3, R16 ?WAIT4_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, PT, 0xf8, 0x8f ?trans2;
SHF.R.U32.HI R5, RZ, 0x1, R16 ?WAIT3_END_GROUP;
SEL R18, RZ, 0x1, !P0 ?WAIT5_END_GROUP;
LOP3.LUT R3, R18, 0x1, R5, 0xf8, !PT ?WAIT4_END_GROUP;
LOP3.LUT R16, R3, R16, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R5, PT, PT, R5, R16, RZ ?WAIT4_END_GROUP;
LOP3.LUT R0, R5, R0, RZ, 0xfc, !PT ?trans1;
BRA 0x1b40 ?trans6;
LOP3.LUT R0, R0, 0x80000000, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
LOP3.LUT R0, R0, 0x7f800000, RZ, 0xfc, !PT ?trans1;
BRA 0x1b40 ?trans6;
IMAD R0, R7, 0x800000, R0 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B1 ?trans5;
BRA 0x1be0 ?trans5;
LOP3.LUT R0, R0, 0x80000000, R3, 0x48, !PT ?WAIT4_END_GROUP;
LOP3.LUT R0, R0, 0x7f800000, RZ, 0xfc, !PT ?trans1;
BRA 0x1be0 ?trans6;
LOP3.LUT R0, R0, 0x80000000, R3, 0x48, !PT ?trans1;
BRA 0x1be0 ?trans6;
MUFU.RSQ R0, -QNAN &wr=0x0 ?trans1;
BRA 0x1be0 ?trans5;
FADD.FTZ R0, R3, R0 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
HFMA2 R7, -RZ, RZ, 0, 0 ?WAIT4_END_GROUP;
RET.REL.NODEC R6 0x0 &req={0} ?trans5;
BRA 0x1c10;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: cudaDy(float*, float*, int)
_Z6cudaDyPfS_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
v_lshl_add_u32 v0, s15, 8, v0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v1, 1, v0
v_mov_b32_e32 v3, v0
v_cvt_f32_i32_e32 v1, v1
.LBB0_2:
s_load_b32 s5, s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v4, 1, v3
v_cvt_f32_i32_e32 v3, v3
s_add_i32 s4, s4, -1
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
v_cvt_f32_i32_e32 v5, v4
s_cmp_eq_u32 s4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, 0.5, v5
v_fma_f32 v3, v5, v3, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v5, null, v3, v3, s5
v_div_scale_f32 v8, vcc_lo, s5, v3, s5
v_rcp_f32_e32 v6, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v7, -v5, v6, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v7, v6
v_mul_f32_e32 v7, v8, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v9, -v5, v7, v8
v_fmac_f32_e32 v7, v9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, -v5, v7, v8
v_div_fmas_f32 v5, v5, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v5, v5, v3, s5
v_dual_mov_b32 v3, v4 :: v_dual_add_f32 v2, v2, v5
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v2, 0
.LBB0_4:
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| cudaDy | 9,814 | 1,078 | stackv2-00000-of-00015 |
// Demangled: max(float*)
Function : _Z3maxPf
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R11, SR_TID.X &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x380] &wr=0x2 ?trans1;
LDCU UR6, c[0x0][0x360] &wr=0x3 ?trans1;
HFMA2 R9, -RZ, RZ, 0, 5.9604644775390625e-08 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x4 ?trans1;
MOV R2, UR6 &req={3} ?trans1;
IADD3 R0, PT, PT, R11, R11, RZ &req={4,1} ?WAIT7_END_GROUP;
ISETP.GE.U32.AND P1, PT, R11, R2, PT ?trans1;
BSSY.RECONVERGENT B0, 0x150 ?trans1;
ISETP.GT.U32.AND P0, PT, R2, 0x1, PT ?trans1;
SHF.R.U32.HI R10, RZ, 0x1, R2 ?WAIT10_END_GROUP;
@P1 BRA 0x140 &req={1} ?trans5;
IMAD R7, R0, R9, RZ ?WAIT4_END_GROUP;
IMAD.WIDE R6, R7, 0x4, R4 &req={2} ?WAIT5_END_GROUP;
LDG.E R8, desc[UR4][R6.64] &wr=0x2 ?trans1;
IMAD.WIDE R2, R9, 0x4, R6 ?WAIT6_END_GROUP;
LDG.E R3, desc[UR4][R2.64] &wr=0x2 ?trans2;
FSETP.GEU.AND P1, PT, R8, R3, PT &req={2} ?WAIT13_END_GROUP;
@!P1 STG.E desc[UR4][R6.64], R3 &rd=0x1 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
MOV R2, R10 ?trans1;
IADD3 R9, PT, PT, R9, R9, RZ ?trans1;
@P0 BRA 0x80 ?trans6;
EXIT ?trans5;
BRA 0x190;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: max(float*)
_Z3maxPf:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s4, 0
s_cbranch_scc1 .LBB1_6
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 1, v0
s_mov_b32 s2, 1
.LBB1_2:
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB1_5
v_mul_lo_u32 v1, v3, s2
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_lshl_b64 s[6:7], s[2:3], 2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
v_add_co_u32 v4, vcc_lo, v1, s6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v2, vcc_lo
s_clause 0x1
global_load_b32 v6, v[1:2], off
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_cmp_lt_f32_e32 vcc_lo, v6, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_5
global_store_b32 v[1:2], v4, off
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s5
s_lshr_b32 s3, s4, 1
s_lshl_b32 s2, s2, 1
s_cmp_gt_u32 s4, 1
s_mov_b32 s4, s3
s_cbranch_scc1 .LBB1_2
.LBB1_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| max | 668 | 732 | stackv2-00000-of-00015 |
// Demangled: min(float*)
Function : _Z3minPf
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R11, SR_TID.X &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x380] &wr=0x2 ?trans1;
LDCU UR6, c[0x0][0x360] &wr=0x3 ?trans1;
HFMA2 R9, -RZ, RZ, 0, 5.9604644775390625e-08 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x4 ?trans1;
MOV R2, UR6 &req={3} ?trans1;
IADD3 R0, PT, PT, R11, R11, RZ &req={4,1} ?WAIT7_END_GROUP;
ISETP.GE.U32.AND P1, PT, R11, R2, PT ?trans1;
BSSY.RECONVERGENT B0, 0x150 ?trans1;
ISETP.GT.U32.AND P0, PT, R2, 0x1, PT ?trans1;
SHF.R.U32.HI R10, RZ, 0x1, R2 ?WAIT10_END_GROUP;
@P1 BRA 0x140 &req={1} ?trans5;
IMAD R7, R0, R9, RZ ?WAIT4_END_GROUP;
IMAD.WIDE R6, R7, 0x4, R4 &req={2} ?WAIT5_END_GROUP;
LDG.E R8, desc[UR4][R6.64] &wr=0x2 ?trans1;
IMAD.WIDE R2, R9, 0x4, R6 ?WAIT6_END_GROUP;
LDG.E R3, desc[UR4][R2.64] &wr=0x2 ?trans2;
FSETP.GT.AND P1, PT, R8, R3, PT &req={2} ?WAIT13_END_GROUP;
@P1 STG.E desc[UR4][R6.64], R3 &rd=0x1 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
MOV R2, R10 ?trans1;
IADD3 R9, PT, PT, R9, R9, RZ ?trans1;
@P0 BRA 0x80 ?trans6;
EXIT ?trans5;
BRA 0x190;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: min(float*)
_Z3minPf:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s4, 0
s_cbranch_scc1 .LBB2_6
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 1, v0
s_mov_b32 s2, 1
.LBB2_2:
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB2_5
v_mul_lo_u32 v1, v3, s2
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_lshl_b64 s[6:7], s[2:3], 2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
v_add_co_u32 v4, vcc_lo, v1, s6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v2, vcc_lo
s_clause 0x1
global_load_b32 v6, v[1:2], off
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, v6, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_5
global_store_b32 v[1:2], v4, off
.LBB2_5:
s_or_b32 exec_lo, exec_lo, s5
s_lshr_b32 s3, s4, 1
s_lshl_b32 s2, s2, 1
s_cmp_gt_u32 s4, 1
s_mov_b32 s4, s3
s_cbranch_scc1 .LBB2_2
.LBB2_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| min | 667 | 732 | stackv2-00000-of-00015 |
// Demangled: std_(float*, float)
Function : _Z4std_Pff
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R21, SR_TID.X &wr=0x1 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x2 ?trans1;
LDCU UR6, c[0x0][0x360] &wr=0x3 ?trans1;
HFMA2 R13, -RZ, RZ, 0, 5.9604644775390625e-08 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x4 ?trans1;
MOV R4, UR6 &req={3} ?trans1;
IADD3 R0, PT, PT, R21, R21, RZ &req={4,1} ?WAIT7_END_GROUP;
ISETP.GE.U32.AND P1, PT, R21, R4, PT ?trans1;
BSSY.RECONVERGENT B0, 0x250 ?trans1;
ISETP.GT.U32.AND P0, PT, R4, 0x1, PT ?trans1;
SHF.R.U32.HI R12, RZ, 0x1, R4 ?WAIT10_END_GROUP;
@P1 BRA 0x240 ?trans5;
ISETP.NE.AND P1, PT, R13, 0x1, PT ?trans1;
IMAD R11, R0, R13, RZ ?WAIT12_END_GROUP;
@!P1 IMAD.WIDE.U32 R4, R11.reuse, 0x4, R2 &req={2} ?trans1;
@!P1 LDC R9, c[0x0][0x388] &wr=0x1 ?trans4;
@!P1 LDG.E R6, desc[UR4][R4.64] &wr=0x1 ?trans1;
IADD3 R23, PT, PT, R11, R13, RZ ?trans1;
@!P1 FADD R6, R6, -R9 &req={1} ?WAIT4_END_GROUP;
@!P1 FMUL R15, R6, R6 ?trans1;
@!P1 IMAD.WIDE.U32 R6, R23, 0x4, R2 ?WAIT4_END_GROUP;
@!P1 STG.E desc[UR4][R4.64], R15 &rd=0x1 ?trans4;
@!P1 LDG.E R8, desc[UR4][R6.64] &wr=0x2 ?trans2;
@!P1 FADD R8, R8, -R9 &req={2} ?WAIT4_END_GROUP;
@!P1 FMUL R17, R8, R8 ?WAIT5_END_GROUP;
@!P1 STG.E desc[UR4][R6.64], R17 &rd=0x1 ?trans4;
@!P1 LDG.E R8, desc[UR4][R4.64] &wr=0x2 ?trans1;
@P1 IMAD.WIDE R10, R11, 0x4, R2 ?WAIT4_END_GROUP;
@!P1 FADD R19, R17, R8 &req={2} ?trans1;
@P1 IMAD.WIDE R8, R23, 0x4, R2 ?WAIT4_END_GROUP;
@!P1 STG.E desc[UR4][R4.64], R19 &rd=0x1 ?trans4;
@P1 LDG.E R8, desc[UR4][R8.64] &wr=0x2 ?trans4;
@P1 LDG.E R15, desc[UR4][R10.64] &wr=0x2 ?trans2;
@P1 FADD R15, R8, R15 &req={2} ?WAIT5_END_GROUP;
@P1 STG.E desc[UR4][R10.64], R15 &rd=0x1 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
MOV R4, R12 &req={1} ?trans1;
IADD3 R13, PT, PT, R13, R13, RZ ?trans1;
@P0 BRA 0x80 ?trans6;
EXIT ?trans5;
BRA 0x290;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: std_(float*, float)
_Z4std_Pff:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s4, 0
s_cbranch_scc1 .LBB3_10
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x8
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v9, 1, v0
s_mov_b32 s1, 1
.LBB3_2:
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB3_9
v_mul_lo_u32 v1, v9, s1
s_cmp_lg_u32 s1, 1
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v3, s1, v1
s_cbranch_scc0 .LBB3_5
v_ashrrev_i32_e32 v5, 31, v1
v_mov_b32_e32 v4, v1
s_mov_b32 s6, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v5, vcc_lo
v_ashrrev_i32_e32 v4, 31, v3
global_load_b32 v10, v[7:8], off
v_lshlrev_b64 v[5:6], 2, v[3:4]
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
s_branch .LBB3_6
.LBB3_5:
s_mov_b32 s6, -1
.LBB3_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s6
s_cbranch_vccnz .LBB3_8
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b32 v1, v[5:6], off
v_mov_b32_e32 v4, v2
v_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v7, v5
s_waitcnt vmcnt(0)
v_subrev_f32_e32 v1, s0, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_mul_f32_e32 v1, v1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_store_b32 v[5:6], v1, off
global_load_b32 v1, v[3:4], off
s_waitcnt vmcnt(0)
v_subrev_f32_e32 v1, s0, v1
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v10, v1, v1
global_store_b32 v[3:4], v10, off
.LBB3_8:
global_load_b32 v1, v[5:6], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v10
global_store_b32 v[7:8], v1, off
.LBB3_9:
s_or_b32 exec_lo, exec_lo, s5
s_lshr_b32 s5, s4, 1
s_lshl_b32 s1, s1, 1
s_cmp_gt_u32 s4, 1
s_mov_b32 s4, s5
s_cbranch_scc1 .LBB3_2
.LBB3_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| std_ | 1,134 | 1,332 | stackv2-00000-of-00015 |
// Demangled: sum(float*)
Function : _Z3sumPf
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R11, SR_TID.X &wr=0x1 ?trans7;
LDC.64 R6, c[0x0][0x380] &wr=0x2 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x3 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x4 ?trans1;
MOV R0, UR4 &req={3} ?trans1;
UMOV UR4, 0x1 ?trans1;
IADD3 R8, PT, PT, R11, R11, RZ &req={4,1} ?WAIT7_END_GROUP;
ISETP.GE.U32.AND P0, PT, R11, R0, PT ?trans1;
BSSY.RECONVERGENT B0, 0x160 ?trans1;
ISETP.GT.U32.AND P1, PT, R0, 0x1, PT ?trans1;
SHF.R.U32.HI R0, RZ, 0x1, R0 ?WAIT10_END_GROUP;
@P0 BRA 0x150 &req={1} ?trans5;
IMAD R5, R8, UR4, RZ ?WAIT5_END_GROUP;
IADD3 R3, PT, PT, R5.reuse, UR4, RZ ?trans1;
IMAD.WIDE R4, R5, 0x4, R6 &req={2} ?WAIT4_END_GROUP;
IMAD.WIDE R2, R3, 0x4, R6 ?trans1;
LDG.E R9, desc[UR6][R4.64] &wr=0x2 ?trans5;
LDG.E R2, desc[UR6][R2.64] &wr=0x2 ?trans2;
FADD R9, R2, R9 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R4.64], R9 &rd=0x1 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
UIADD3 UR4, UPT, UPT, UR4, UR4, URZ ?trans1;
@P1 BRA 0x80 ?trans11;
EXIT ?trans5;
BRA 0x190;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: sum(float*)
_Z3sumPf:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB0_5
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 1, v0
s_mov_b32 s3, 1
.LBB0_2:
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e64 s2, v0
s_cbranch_execz .LBB0_4
v_mul_lo_u32 v2, v1, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, s3, v2
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v4, v5
global_store_b32 v[2:3], v4, off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s2, 1
s_lshl_b32 s3, s3, 1
s_cmp_gt_u32 s2, 1
s_mov_b32 s2, s4
s_cbranch_scc1 .LBB0_2
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| sum | 637 | 727 | stackv2-00000-of-00015 |
// Demangled: setValue(char*, int, char)
Function : _Z8setValuePcic
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans2;
ISETP.NE.AND P0, PT, R0, RZ, PT &req={1} ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LDC.U8 R0, c[0x0][0x38c] &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x388] &wr=0x2 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x3 ?trans6;
LDC.64 R2, c[0x0][0x380] &wr=0x4 ?trans1;
USHF.R.S32.HI UR5, URZ, 0x1f, UR4 &req={2} ?trans1;
PRMT R0, R0, 0x8880, RZ &req={1} ?WAIT4_END_GROUP;
PRMT R5, R0, 0x7710, RZ ?trans1;
IADD.64 R2, R2, UR4 &req={4} ?WAIT6_END_GROUP;
STG.E.U8 desc[UR6][R2.64], R5 &req={3} ?trans1;
EXIT ?trans5;
BRA 0xe0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: setValue(char*, int, char)
_Z8setValuePcic:
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s3
s_ashr_i32 s3, s2, 31
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b8 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| setValue | 399 | 195 | stackv2-00000-of-00015 |
// Demangled: getLineFromAccum(unsigned int*, int, int, int*, int*)
Function : _Z16getLineFromAccumPjiiPiS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R6, SR_CTAID.Y &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x2 ?trans1;
S2R R3, SR_TID.Y &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x364] &wr=0x1 ?trans1;
S2R R17, SR_CTAID.X &wr=0x2 ?trans1;
LDCU.64 UR6, c[0x0][0x388] &wr=0x3 ?trans1;
S2R R0, SR_TID.X &wr=0x2 ?trans1;
IMAD R6, R6, UR5, R3 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R6, UR7, PT &req={3} ?trans1;
IMAD R17, R17, UR4, R0 &req={2} ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R17, UR6, P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R4, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD R7, R6, UR6, R17 ?WAIT6_END_GROUP;
LDC.64 R2, c[0x0][0x398] &wr=0x1 ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans1;
IMAD.WIDE R4, R7, 0x4, R4 &req={0} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans2;
ISETP.NE.AND P0, PT, R2, R5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LDC.64 R18, c[0x0][0x390] &wr=0x0 ?trans1;
IADD3 R0, PT, PT, R17.reuse, -0xf, RZ ?trans2;
IADD3 R3, PT, PT, R17, 0xe, RZ ?trans2;
IADD3 R5, PT, PT, R6.reuse, -0xf, RZ ?trans2;
IADD3 R7, PT, PT, R6.reuse, -0xa, RZ ?trans1;
STG.E desc[UR4][R18.64], R17 &req={0} &rd=0x0 ?trans1;
IADD3 R9, PT, PT, R6.reuse, -0xb, RZ ?trans2;
IADD3 R11, PT, PT, R6, -0xc, RZ ?WAIT2_END_GROUP;
IADD3 R13, PT, PT, R6.reuse, -0xd, RZ ?trans1;
STG.E desc[UR4][R18.64+0x4], R6 &rd=0x1 ?trans1;
IADD3 R15, PT, PT, R6.reuse, -0xe, RZ ?trans1;
LDCU UR7, c[0x0][0x38c] &wr=0x2 ?trans1;
IADD3 R17, PT, PT, R6.reuse, -0x8, RZ &req={0} ?trans2;
IADD3 R19, PT, PT, R6, -0x9, RZ &req={1} ?WAIT7_END_GROUP;
LDC R21, c[0x0][0x388] &req={0} &wr=0x0 ?trans1;
LDCU UR6, c[0x0][0x388] &wr=0x1 ?trans1;
MOV R20, 0xfffffff4 ?trans1;
MOV R18, R5 ?trans1;
ISETP.GE.AND P0, PT, R0, UR6, PT &req={1} ?trans1;
IMAD R8, R7, UR6, R0.reuse ?trans2;
IMAD R10, R9, UR6, R0.reuse ?trans2;
IMAD R12, R11, UR6, R0.reuse ?trans2;
IMAD R14, R13, UR6, R0 ?WAIT2_END_GROUP;
IMAD R16, R15, UR6, R0.reuse ?trans2;
IMAD R4, R5, UR6, R0.reuse ?trans2;
IMAD R2, R17, UR6, R0.reuse ?trans2;
IMAD R6, R19, UR6, R0 ?WAIT7_END_GROUP;
IADD3 R22, PT, PT, R18.reuse, 0x1, RZ ?trans1;
ISETP.GE.OR P6, PT, R18.reuse, UR7, P0 &req={2} ?trans1;
IADD3 R26, PT, PT, R18.reuse, 0x2, RZ ?trans2;
IADD3 R27, PT, PT, R18.reuse, 0x3, RZ ?trans2;
IADD3 R28, PT, PT, R18, 0x4, RZ ?trans1;
ISETP.GE.OR P1, PT, R22, UR7, P0 ?trans1;
IADD3 R20, PT, PT, R20, 0x8, RZ ?trans1;
ISETP.GE.OR P2, PT, R26, UR7, P0 ?trans1;
IADD3 R26, PT, PT, R18, 0x5, RZ ?trans1;
ISETP.GE.OR P3, PT, R27, UR7, P0 ?trans1;
ISETP.GE.OR P4, PT, R28, UR7, P0 ?WAIT3_END_GROUP;
ISETP.GE.OR P5, PT, R26, UR7, P0 ?trans1;
@!P6 LDC.64 R24, c[0x0][0x380] &wr=0x1 ?trans8;
@!P1 LDC.64 R22, c[0x0][0x380] &wr=0x2 ?trans8;
@!P2 LDC.64 R32, c[0x0][0x380] &wr=0x3 ?trans1;
@!P6 IMAD.WIDE R34, R4, 0x4, R24 &req={1} ?trans1;
IADD3 R24, PT, PT, R18, 0x6, RZ ?WAIT6_END_GROUP;
@!P3 LDC.64 R30, c[0x0][0x380] &wr=0x1 ?trans1;
IMAD R4, R21, 0x8, R4 &req={0} ?trans1;
@!P6 STG.E desc[UR4][R34.64], RZ ?trans1;
ISETP.GE.OR P6, PT, R24, UR7, P0 ?trans1;
@!P1 IMAD.WIDE R36, R16, 0x4, R22 &req={2} ?trans1;
IADD3 R22, PT, PT, R18, 0x7, RZ ?WAIT3_END_GROUP;
@!P5 LDC.64 R28, c[0x0][0x380] &wr=0x0 ?trans1;
IMAD R16, R21, 0x8, R16 ?trans1;
@!P1 STG.E desc[UR4][R36.64], RZ ?trans1;
ISETP.GE.OR P1, PT, R22, UR7, P0 ?trans1;
@!P2 IMAD.WIDE R32, R14, 0x4, R32 &req={3} ?WAIT4_END_GROUP;
@!P4 LDC.64 R22, c[0x0][0x380] &wr=0x2 ?trans1;
IMAD R14, R21, 0x8, R14 ?trans1;
@!P2 STG.E desc[UR4][R32.64], RZ &rd=0x3 ?trans6;
@!P6 LDC.64 R26, c[0x0][0x380] &wr=0x4 ?trans1;
@!P3 IMAD.WIDE R30, R12, 0x4, R30 &req={1} ?trans1;
IADD3 R33, PT, PT, R18, 0x8, RZ &req={3} ?WAIT4_END_GROUP;
@!P3 STG.E desc[UR4][R30.64], RZ &rd=0x1 ?trans1;
MOV R32, R18 ?trans1;
@!P1 LDC.64 R24, c[0x0][0x380] &wr=0x3 ?trans1;
@!P5 IMAD.WIDE R28, R8, 0x4, R28 &req={0} ?trans1;
MOV R18, R33 ?WAIT3_END_GROUP;
IMAD R12, R21.reuse, 0x8, R12 ?trans2;
IMAD R8, R21, 0x8, R8 ?trans2;
@!P4 IMAD.WIDE R22, R10, 0x4, R22 &req={2} ?WAIT4_END_GROUP;
IMAD R10, R21, 0x8, R10 ?trans1;
@!P4 STG.E desc[UR4][R22.64], RZ &rd=0x1 ?trans1;
@!P6 IMAD.WIDE R26, R6, 0x4, R26 &req={4} ?WAIT3_END_GROUP;
@!P5 STG.E desc[UR4][R28.64], RZ &rd=0x1 ?trans1;
IMAD R6, R21, 0x8, R6 ?WAIT3_END_GROUP;
@!P6 STG.E desc[UR4][R26.64], RZ &rd=0x1 ?trans1;
@!P1 IMAD.WIDE R24, R2, 0x4, R24 &req={3} ?WAIT4_END_GROUP;
IMAD R2, R21, 0x8, R2 ?trans1;
@!P1 STG.E desc[UR4][R24.64], RZ &rd=0x1 ?trans1;
ISETP.NE.AND P1, PT, R20, 0xc, PT ?WAIT13_END_GROUP;
@P1 BRA 0x310 &req={1} ?trans5;
IADD3 R6, PT, PT, R32.reuse, 0x9, RZ ?trans2;
IADD3 R18, PT, PT, R32.reuse, 0xa, RZ ?trans2;
IADD3 R20, PT, PT, R32.reuse, 0xb, RZ ?trans2;
IADD3 R22, PT, PT, R32.reuse, 0xc, RZ ?trans1;
ISETP.GE.AND P0, PT, R33, UR7, PT ?trans1;
IADD3 R2, PT, PT, R32, 0xd, RZ ?trans1;
ISETP.GE.AND P4, PT, R6, UR7, PT ?trans1;
ISETP.GE.AND P5, PT, R18, UR7, PT ?trans1;
ISETP.GE.AND P3, PT, R20, UR7, PT ?trans1;
ISETP.GE.AND P1, PT, R22, UR7, PT ?trans1;
ISETP.GE.OR P0, PT, R0, R21.reuse, P0 ?trans1;
ISETP.GE.AND P2, PT, R2, UR7, PT ?trans1;
ISETP.GE.OR P4, PT, R0.reuse, R21.reuse, P4 ?trans1;
ISETP.GE.OR P5, PT, R0.reuse, R21.reuse, P5 ?trans1;
ISETP.GE.OR P3, PT, R0.reuse, R21.reuse, P3 ?trans1;
ISETP.GE.OR P1, PT, R0.reuse, R21.reuse, P1 ?trans1;
ISETP.GE.OR P2, PT, R0, R21, P2 ?WAIT7_END_GROUP;
@!P0 LDC.64 R30, c[0x0][0x380] &wr=0x0 ?trans8;
@!P4 LDC.64 R28, c[0x0][0x380] &wr=0x1 ?trans8;
@!P5 LDC.64 R26, c[0x0][0x380] &wr=0x2 ?trans8;
@!P3 LDC.64 R24, c[0x0][0x380] &wr=0x3 ?trans1;
@!P0 IMAD.WIDE R30, R4, 0x4, R30 &req={0} ?WAIT5_END_GROUP;
@!P0 STG.E desc[UR4][R30.64], RZ &rd=0x0 ?trans1;
ISETP.GE.AND P0, PT, R0, R3, PT ?trans1;
@!P1 LDC.64 R20, c[0x0][0x380] &wr=0x4 ?trans1;
@!P4 IMAD.WIDE R28, R16, 0x4, R28 &req={1} ?trans1;
IADD3 R0, PT, PT, R0, 0x1, RZ ?WAIT4_END_GROUP;
@!P4 STG.E desc[UR4][R28.64], RZ &rd=0x0 ?trans2;
@!P2 LDC.64 R22, c[0x0][0x380] &wr=0x1 ?trans1;
@!P5 IMAD.WIDE R26, R14, 0x4, R26 &req={2} ?WAIT5_END_GROUP;
@!P5 STG.E desc[UR4][R26.64], RZ &rd=0x0 ?trans1;
@!P3 IMAD.WIDE R24, R12, 0x4, R24 &req={3} ?WAIT5_END_GROUP;
@!P3 STG.E desc[UR4][R24.64], RZ &rd=0x0 ?trans1;
@!P1 IMAD.WIDE R20, R10, 0x4, R20 &req={4} ?WAIT5_END_GROUP;
@!P1 STG.E desc[UR4][R20.64], RZ &rd=0x0 ?trans1;
@!P2 IMAD.WIDE R22, R8, 0x4, R22 &req={1} ?WAIT5_END_GROUP;
@!P2 STG.E desc[UR4][R22.64], RZ &rd=0x0 ?trans1;
@!P0 BRA 0x240 ?trans5;
EXIT ?trans5;
BRA 0x8d0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: getLineFromAccum(unsigned int*, int, int, int*, int*)
_Z16getLineFromAccumPjiiPiS0_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x8
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_mul_i32 s14, s14, s3
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
v_add_nc_u32_e32 v0, s14, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e32 vcc_lo, s4, v0
v_cmp_gt_i32_e64 s2, s5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_8
s_load_b64 s[6:7], s[0:1], 0x0
v_mad_u64_u32 v[3:4], null, v2, s4, v[0:1]
s_load_b128 s[0:3], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
s_load_b32 s2, s[2:3], 0x0
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, s2, v3
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v3, -15, v2
v_add_nc_u32_e32 v5, 14, v0
s_mov_b32 s2, 0
v_add_nc_u32_e32 v4, 14, v2
s_delay_alu instid0(VALU_DEP_3)
v_mad_u64_u32 v[6:7], null, s4, v3, v[1:2]
v_mov_b32_e32 v3, 0
v_dual_mov_b32 v1, v2 :: v_dual_add_nc_u32 v2, -16, v2
v_add_nc_u32_e32 v7, -15, v0
global_store_b64 v3, v[0:1], s[0:1]
v_add3_u32 v6, v6, s14, -15
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v7
v_mov_b32_e32 v0, v6
v_mov_b32_e32 v8, v2
s_mov_b32 s1, 0
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v8, 1, v8
v_cmp_gt_i32_e64 s0, s5, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s3, s0
s_cbranch_execz .LBB0_6
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 2, v[0:1]
v_add_co_u32 v9, s0, s6, v9
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v10, s0, s7, v10, s0
global_store_b32 v[9:10], v3, off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s3
v_cmp_ge_i32_e64 s0, v8, v4
v_add_nc_u32_e32 v0, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s1, s0, s1
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_4
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v0, 1, v7
v_cmp_ge_i32_e32 vcc_lo, v7, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v7, v0 :: v_dual_add_nc_u32 v6, 1, v6
s_or_b32 s2, vcc_lo, s2
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_3
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| getLineFromAccum | 3,856 | 1,622 | stackv2-00000-of-00015 |
// Demangled: copy(float*, float const*)
Function : _Z4copyPfPKf
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R0, SR_CTAID.X &wr=0x0 ?trans7;
LDC R16, c[0x0][0x370] &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans1;
S2R R5, SR_TID.X &wr=0x0 ?trans1;
S2R R4, SR_CTAID.Y &wr=0x3 ?trans5;
LDC.64 R2, c[0x0][0x388] &wr=0x4 ?trans1;
S2R R7, SR_TID.Y &wr=0x3 ?trans7;
LDC.64 R14, c[0x0][0x380] &wr=0x5 ?trans1;
LEA R0, R0, R5, 0x5 &req={0} ?WAIT2_END_GROUP;
LEA R5, R4, R7, 0x5 &req={3} ?trans2;
SHF.L.U32 R4, R16, 0x5, RZ &req={1} ?WAIT5_END_GROUP;
IMAD R7, R5, R4, R0 ?WAIT4_END_GROUP;
IMAD.WIDE R4, R7, 0x4, R2 &req={4} ?WAIT5_END_GROUP;
LDG.E R17, desc[UR4][R4.64] &req={2} &wr=0x2 ?trans1;
LEA R11, R16, R7, 0x8 ?trans1;
IMAD.WIDE R6, R7, 0x4, R14 &req={5} ?WAIT4_END_GROUP;
IMAD.WIDE R8, R11.reuse, 0x4, R2 ?trans1;
LEA R19, R16, R11, 0x8 ?trans1;
STG.E desc[UR4][R6.64], R17 &req={2} &rd=0x0 ?trans4;
LDG.E R9, desc[UR4][R8.64] &wr=0x2 ?trans1;
IMAD.WIDE R10, R11, 0x4, R14 ?WAIT4_END_GROUP;
IMAD.WIDE R12, R19.reuse, 0x4, R2 ?trans1;
LEA R21, R16, R19, 0x8 ?trans1;
STG.E desc[UR4][R10.64], R9 &req={2} ?trans4;
LDG.E R13, desc[UR4][R12.64] &wr=0x2 ?trans1;
IMAD.WIDE R4, R19, 0x4, R14 ?WAIT4_END_GROUP;
IMAD.WIDE R2, R21.reuse, 0x4, R2 ?trans1;
STG.E desc[UR4][R4.64], R13 &req={2} ?trans5;
LDG.E R3, desc[UR4][R2.64] &wr=0x2 ?trans1;
IMAD.WIDE R6, R21, 0x4, R14 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R3 &req={2} ?trans1;
EXIT ?trans5;
BRA 0x210;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: copy(float*, float const*)
_Z4copyPfPKf:
s_load_b32 s4, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
s_load_b128 s[0:3], s[0:1], 0x0
v_and_b32_e32 v0, 0x3ff, v0
s_lshl_b32 s5, s14, 5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshl_add_u32 v1, s15, 5, v1
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v1, s4, v1
s_lshl_b32 s4, s4, 8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v1, 5, v1
v_add3_u32 v0, v0, v1, s5
s_mov_b32 s5, -8
.LBB0_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s5, s5, 8
s_cmp_gt_u32 s5, 23
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_add_nc_u32_e32 v0, s4, v0
v_add_co_u32 v3, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
global_store_b32 v[1:2], v3, off
s_cbranch_scc0 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| copy | 900 | 636 | stackv2-00000-of-00015 |
// Demangled: transposeCoalesced(float*, float*)
Function : _Z18transposeCoalescedPfS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R16, SR_CTAID.X &wr=0x0 ?trans7;
LDC R0, c[0x0][0x370] &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x2 ?trans1;
S2R R18, SR_TID.X &wr=0x0 ?trans1;
S2R R21, SR_CTAID.Y &wr=0x3 ?trans5;
LDC.64 R10, c[0x0][0x388] &wr=0x4 ?trans1;
S2R R20, SR_TID.Y &wr=0x3 ?trans1;
SHF.L.U32 R4, R0, 0x5, RZ &req={1} ?WAIT2_END_GROUP;
LEA R3, R16, R18, 0x5 &req={0} ?trans2;
LEA R2, R21, R20, 0x5 &req={3} ?WAIT5_END_GROUP;
IMAD R3, R2, R4, R3 ?WAIT5_END_GROUP;
LEA R7, R0, R3, 0x8 ?trans1;
IMAD.WIDE R2, R3, 0x4, R10 &req={4} ?WAIT3_END_GROUP;
LEA R9, R0.reuse, R7, 0x8 ?trans1;
IMAD.WIDE R6, R7, 0x4, R10.reuse ?trans1;
LDG.E R12, desc[UR6][R2.64] &req={2} &rd=0x0 &wr=0x2 ?trans2;
LEA R5, R0, R9, 0x8 ?trans1;
IMAD.WIDE R8, R9, 0x4, R10.reuse ?trans2;
LDG.E R6, desc[UR6][R6.64] &rd=0x1 &wr=0x3 ?trans2;
IMAD.WIDE R10, R5, 0x4, R10 ?trans2;
LDG.E R8, desc[UR6][R8.64] &rd=0x4 &wr=0x5 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans3;
LDG.E R10, desc[UR6][R10.64] &wr=0x5 ?trans1;
UMOV UR4, 0x400 ?WAIT4_END_GROUP;
LDC.64 R2, c[0x0][0x380] &req={0} &wr=0x0 ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R5, R18, UR4, 0x2 ?WAIT5_END_GROUP;
IMAD R13, R20, 0x84, R5 ?trans1;
LEA R5, R18, R5, 0x7 ?WAIT4_END_GROUP;
LEA R14, R20, R5, 0x2 ?trans2;
LEA R5, R21, R18, 0x5 ?trans2;
LEA R7, R16, R20, 0x5 ?WAIT5_END_GROUP;
IMAD R5, R4, R7, R5 ?WAIT5_END_GROUP;
LEA R7, R0, R5, 0x8 ?WAIT4_END_GROUP;
LEA R9, R0.reuse, R7, 0x8 &req={4} ?trans1;
IMAD.WIDE R4, R5, 0x4, R2.reuse &req={0} ?trans1;
STS [R13], R12 &req={2} ?trans4;
STS [R13+0x420], R6 &req={3} ?trans4;
STS [R13+0x840], R8 &req={5} ?trans4;
STS [R13+0xc60], R10 &rd=0x0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R11, [R14] &wr=0x1 ?trans4;
LDS R15, [R14+0x20] &wr=0x2 ?trans4;
LDS R17, [R14+0x40] &wr=0x3 ?trans4;
LDS R19, [R14+0x60] &wr=0x4 ?trans1;
LEA R13, R0, R9, 0x8 &req={0} ?trans1;
IMAD.WIDE R6, R7, 0x4, R2 ?WAIT4_END_GROUP;
IMAD.WIDE R8, R9, 0x4, R2 ?WAIT4_END_GROUP;
IMAD.WIDE R2, R13, 0x4, R2 ?trans1;
STG.E desc[UR6][R4.64], R11 &req={1} ?trans4;
STG.E desc[UR6][R6.64], R15 &req={2} ?trans4;
STG.E desc[UR6][R8.64], R17 &req={3} ?trans4;
STG.E desc[UR6][R2.64], R19 &req={4} ?trans1;
EXIT ?trans5;
BRA 0x370;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: transposeCoalesced(float*, float*)
_Z18transposeCoalescedPfS_:
s_load_b32 s5, s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
s_lshl_b32 s6, s15, 5
s_load_b128 s[0:3], s[0:1], 0x0
v_and_b32_e32 v3, 0x3ff, v0
s_lshl_b32 s7, s14, 5
v_add_nc_u32_e32 v1, s6, v2
s_mov_b32 s8, -8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v0, 2, v3
v_mad_u32_u24 v4, 0x84, v2, v0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v1, s5, v1
s_lshl_b32 s4, s5, 8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v1, 5, v1
v_add3_u32 v0, v3, v1, s7
.LBB2_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s8, s8, 8
s_cmp_gt_u32 s8, 23
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[0:1]
v_add_nc_u32_e32 v0, s4, v0
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b32 v1, v[5:6], off
s_waitcnt vmcnt(0)
ds_store_b32 v4, v1
v_add_nc_u32_e32 v4, 0x420, v4
s_cbranch_scc0 .LBB2_1
v_add_nc_u32_e32 v0, s7, v2
v_lshlrev_b32_e32 v1, 2, v2
s_mov_b32 s2, -8
s_waitcnt lgkmcnt(0)
s_barrier
v_mul_lo_u32 v0, s5, v0
v_mad_u32_u24 v2, 0x84, v3, v1
buffer_gl0_inv
v_lshlrev_b32_e32 v0, 5, v0
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v0, v3, v0, s6
.LBB2_3:
ds_load_b32 v5, v2
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v2, 32, v2
s_add_i32 s2, s2, 8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_gt_u32 s2, 23
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_add_nc_u32_e32 v0, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[3:4], v5, off
s_cbranch_scc0 .LBB2_3
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| transposeCoalesced | 1,384 | 1,101 | stackv2-00000-of-00015 |
// Demangled: transposeNaive(float*, float const*)
Function : _Z14transposeNaivePfPKf
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R0, SR_CTAID.X &wr=0x0 ?trans7;
LDC R12, c[0x0][0x370] &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans1;
S2R R5, SR_TID.X &wr=0x0 ?trans1;
S2R R9, SR_CTAID.Y &wr=0x3 ?trans5;
LDC.64 R2, c[0x0][0x388] &wr=0x4 ?trans1;
S2R R4, SR_TID.Y &wr=0x3 ?trans7;
LDC.64 R6, c[0x0][0x380] &wr=0x5 ?trans1;
SHF.L.U32 R8, R12, 0x5, RZ &req={1} ?WAIT2_END_GROUP;
LEA R0, R0, R5, 0x5 &req={0} ?trans2;
LEA R9, R9, R4, 0x5 &req={3} ?WAIT5_END_GROUP;
IMAD R11, R9, R8, R0 ?WAIT4_END_GROUP;
IMAD.WIDE R4, R11, 0x4, R2 &req={4} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR4][R4.64] &req={2} &wr=0x2 ?trans1;
IMAD R9, R0, R8, R9 ?trans1;
LEA R11, R12, R11, 0x8 ?WAIT3_END_GROUP;
IMAD.WIDE R6, R9, 0x4, R6 &req={5} ?WAIT4_END_GROUP;
IMAD.WIDE R8, R11, 0x4, R2 ?trans1;
STG.E desc[UR4][R6.64], R5 &req={2} ?trans5;
LDG.E R9, desc[UR4][R8.64] &wr=0x2 ?trans1;
LEA R13, R12, R11, 0x8 ?WAIT5_END_GROUP;
IMAD.WIDE R10, R13, 0x4, R2.reuse ?trans1;
LEA R13, R12, R13, 0x8 ?trans1;
STG.E desc[UR4][R6.64+0x20], R9 &req={2} ?trans4;
LDG.E R11, desc[UR4][R10.64] &wr=0x2 ?trans1;
IMAD.WIDE R2, R13, 0x4, R2 ?WAIT3_END_GROUP;
STG.E desc[UR4][R6.64+0x40], R11 &req={2} ?trans4;
LDG.E R3, desc[UR4][R2.64] &wr=0x2 ?trans4;
STG.E desc[UR4][R6.64+0x60], R3 &req={2} ?trans1;
EXIT ?trans5;
BRA 0x1f0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: transposeNaive(float*, float const*)
_Z14transposeNaivePfPKf:
s_load_b32 s4, s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_lshl_b32 s5, s14, 5
s_lshl_b32 s6, s15, 5
s_load_b128 s[0:3], s[0:1], 0x0
v_add_nc_u32_e32 v2, s5, v1
v_add_nc_u32_e32 v3, s6, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, s4, v2
v_mul_lo_u32 v3, s4, v3
s_lshl_b32 s4, s4, 8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v2, 5, v2
v_lshlrev_b32_e32 v3, 5, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v2, v0, v2, s6
v_add3_u32 v0, v1, v3, s5
s_mov_b32 s5, -8
.LBB1_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s5, s5, 8
s_cmp_gt_u32 s5, 23
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_add_nc_u32_e32 v0, s4, v0
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v1, v[3:4], off
v_add_nc_u32_e32 v3, s5, v2
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[3:4], v1, off
s_cbranch_scc0 .LBB1_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| transposeNaive | 836 | 885 | stackv2-00000-of-00015 |
// Demangled: bit_reverse_reorder(float2*, float2*, int)
Function : _Z19bit_reverse_reorderP6float2S0_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans8;
LDC R7, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R7, R7, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GT.AND P0, PT, R7, 0x3ff, PT ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R4, c[0x0][0x388] &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x390] &wr=0x2 ?trans6;
LDC.64 R2, c[0x0][0x380] &wr=0x3 ?trans1;
IMAD.WIDE R4, R7, 0x8, R4 &req={0} ?WAIT6_END_GROUP;
LDG.E.64 R4, desc[UR6][R4.64] &req={1} &wr=0x4 ?trans1;
BREV R7, R7 &wr=0x0 ?trans1;
UIADD3 UR4, UPT, UPT, -UR4, 0x20, URZ &req={2} ?WAIT6_END_GROUP;
SHF.R.U32.HI R9, RZ, UR4, R7 &req={0} ?WAIT5_END_GROUP;
IMAD.WIDE R2, R9, 0x8, R2 &req={3} ?WAIT5_END_GROUP;
STG.E.64 desc[UR6][R2.64], R4 &req={4} ?trans1;
EXIT ?trans5;
BRA 0x130;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: bit_reverse_reorder(HIP_vector_type<float, 2u>*, HIP_vector_type<float, 2u>*, int)
_Z19bit_reverse_reorderP15HIP_vector_typeIfLj2EES1_i:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x400, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x10
v_bfrev_b32_e32 v0, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_sub_i32 s0, 32, s0
v_lshrrev_b32_e32 v0, s0, v0
global_load_b64 v[2:3], v[2:3], off
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| bit_reverse_reorder | 559 | 650 | stackv2-00000-of-00015 |
// Demangled: fft(float2*, int, int)
Function : _Z3fftP6float2ii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R2, SR_TID.X &wr=0x1 ?trans7;
LDC R6, c[0x0][0x38c] &wr=0x2 ?trans8;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans8;
LDC R13, c[0x0][0x360] &wr=0x1 ?trans1;
LEA.HI R0, R6, R6, RZ, 0x1 &req={2} ?WAIT4_END_GROUP;
SHF.R.S32.HI R0, RZ, 0x1, R0 ?trans1;
IMAD R13, R13, UR4, R2 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R13, R0, PT ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDCU UR4, c[0x0][0x388] &wr=0x0 ?trans2;
IADD3 R5, PT, PT, R13, UR4, RZ &req={0} ?WAIT4_END_GROUP;
IADD3 R2, PT, PT, R0, R5, RZ ?WAIT5_END_GROUP;
ISETP.GT.AND P0, PT, R2, 0x3ff, PT ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
I2F.F64 R6, R6 &wr=0x0 ?trans1;
MOV R2, 0x1 ?trans1;
UMOV.64 UR4, 0x401921fb54442d18 ?trans1;
BSSY.RECONVERGENT B0, 0x4f0 ?trans1;
MUFU.RCP64H R3, R7 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
I2F.F64 R8, R13 &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, -R6, R2, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R10, R10, R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R2, R10, R2 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, -R6, R10, 1 &req={0} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R8, R8, UR4 &req={1} &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
FSETP.GEU.AND P1, PT, |R9|, 6.5827683646048100446e-37, PT &req={0} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R10, R2, R10 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R10, R8, R2 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, -R6, R10, R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R2, R12, R10 &req={0} &wr=0x0 ?trans2;
FFMA R4, RZ, R7, R3 &req={0} ?WAIT5_END_GROUP;
FSETP.GT.AND P0, PT, |R4|, 1.469367938527859385e-39, PT ?WAIT13_END_GROUP;
@P0 BRA P1, 0x4e0 &req={1} ?trans5;
MOV R4, 0x4c0 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x630 ?trans5;
MOV R2, R12 ?trans1;
MOV R3, R13 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
LDC.64 R6, c[0x0][0x380] &wr=0x0 ?trans2;
IMAD.WIDE R4, R5, 0x8, R6 &req={0} ?WAIT5_END_GROUP;
LDG.E.64 R10, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE R6, R0, 0x8, R4 ?WAIT5_END_GROUP;
LDG.E.64 R12, desc[UR4][R6.64] &wr=0x3 ?trans1;
F2F.F32.F64 R2, R2 &wr=0x0 ?trans2;
FMUL.RZ R14, R2, 0.15915493667125701904 &req={0} ?WAIT4_END_GROUP;
MUFU.SIN R8, R14 &wr=0x3 ?trans1;
MUFU.COS R0, R14 &wr=0x0 ?trans1;
FMUL R9, R8.reuse, R13 &req={3} ?trans1;
FMUL R8, R8, R12 ?WAIT3_END_GROUP;
FFMA R9, R0.reuse, R12, R9 &req={0} ?trans1;
FFMA R8, R0, R13, -R8 ?WAIT3_END_GROUP;
FADD R12, R10.reuse, R9.reuse &req={2} ?trans1;
FADD R13, R11.reuse, R8.reuse ?trans1;
FADD R10, R10, -R9 ?trans1;
FADD R11, R11, -R8 ?WAIT3_END_GROUP;
STG.E.64 desc[UR4][R4.64], R12 ?trans4;
STG.E.64 desc[UR4][R6.64], R10 ?trans1;
EXIT ?trans5;
FSETP.GEU.AND P2, PT, |R9|.reuse, 1.469367938527859385e-39, PT ?trans1;
LOP3.LUT R12, R9, 0x7ff00000, RZ, 0xc0, !PT ?trans1;
BSSY.RECONVERGENT B1, 0xe10 ?trans1;
LOP3.LUT R21, R7.reuse, 0x7ff00000, RZ, 0xc0, !PT ?trans1;
MOV R13, 0x1ca00000 ?trans1;
FSETP.GEU.AND P0, PT, |R7|.reuse, 1.469367938527859385e-39, PT ?trans1;
LOP3.LUT R2, R7, 0x800fffff, RZ, 0xc0, !PT ?trans2;
ISETP.GE.U32.AND P1, PT, R12, R21, PT ?trans1;
MOV R10, R8 ?trans1;
LOP3.LUT R3, R2, 0x3ff00000, RZ, 0xfc, !PT ?WAIT3_END_GROUP;
@!P2 LOP3.LUT R11, R7, 0x7ff00000, RZ, 0xc0, !PT ?trans1;
@!P2 MOV R18, RZ ?trans1;
MOV R2, R6 ?trans1;
MOV R20, R12 ?trans2;
@!P2 ISETP.GE.U32.AND P3, PT, R12, R11, PT ?trans1;
SEL R11, R13.reuse, 0x63400000, !P1 ?trans1;
MOV R14, 0x1 ?trans1;
@!P0 DMUL R2, R6, 8.98846567431157953865e+307 &wr=0x0 ?trans2;
@!P2 SEL R19, R13, 0x63400000, !P3 ?trans1;
LOP3.LUT R11, R11, 0x800fffff, R9, 0xf8, !PT ?trans1;
MUFU.RCP64H R15, R3 &req={0} &wr=0x0 ?trans1;
@!P0 LOP3.LUT R21, R3, 0x7ff00000, RZ, 0xc0, !PT ?WAIT2_END_GROUP;
@!P2 LOP3.LUT R19, R19, 0x80000000, R9, 0xf8, !PT ?trans2;
IADD3 R23, PT, PT, R21, -0x1, RZ ?trans2;
@!P2 LOP3.LUT R19, R19, 0x100000, RZ, 0xfc, !PT ?WAIT15_END_GROUP;
NOP ?WAIT8_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
@!P2 DFMA R10, R10, 2, -R18 &wr=0x1 ?trans2;
@!P2 LOP3.LUT R20, R11, 0x7ff00000, RZ, 0xc0, !PT &req={1} ?WAIT4_END_GROUP;
IADD3 R22, PT, PT, R20, -0x1, RZ ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R22, 0x7feffffe, PT ?WAIT5_END_GROUP;
ISETP.GT.U32.OR P0, PT, R23, 0x7feffffe, P0 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, R14, -R2, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, R16, R16, R16 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, R14, R16, R14 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R14, R16, -R2, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R14, R16, R14, R16 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R16, R14, R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R16, -R2, R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R14, R14, R18, R16 &req={0} &rd=0x0 &wr=0x1 ?trans2;
@P0 BRA 0xcc0 &req={1,0} ?trans5;
LOP3.LUT R9, R7, 0x7ff00000, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R8, PT, PT, R12.reuse, -R9.reuse, RZ ?trans1;
ISETP.GE.U32.AND P0, PT, R12, R9, PT ?WAIT4_END_GROUP;
VIMNMX.S32 R8, R8, -0x46a00000, !PT ?trans1;
SEL R13, R13, 0x63400000, !P0 ?WAIT4_END_GROUP;
VIMNMX.S32 R8, R8, 0x46a00000, PT ?WAIT5_END_GROUP;
IADD3 R16, PT, PT, -R13, R8, RZ ?trans1;
MOV R8, RZ ?WAIT3_END_GROUP;
IADD3 R9, PT, PT, R16, 0x7fe00000, RZ ?WAIT6_END_GROUP;
DMUL R12, R14, R8 &wr=0x0 ?trans2;
FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT &req={0} ?WAIT13_END_GROUP;
@P0 BRA 0xe00 ?trans5;
DFMA R2, R14, -R2, R10 &wr=0x0 ?trans1;
MOV R8, RZ ?trans1;
FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT &req={0} ?trans1;
LOP3.LUT R7, R3, 0x80000000, R7, 0x48, !PT ?WAIT4_END_GROUP;
LOP3.LUT R9, R7, R9, RZ, 0xfc, !PT ?WAIT8_END_GROUP;
@!P0 BRA 0xe00 ?trans5;
IADD3 R3, PT, PT, -R16, RZ, RZ ?trans1;
MOV R2, RZ ?trans1;
DMUL.RP R8, R14, R8 &wr=0x0 ?trans2;
LOP3.LUT R7, R9, R7, RZ, 0x3c, !PT &req={0} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R12, -R2, R14 &wr=0x0 ?trans2;
IADD3 R2, PT, PT, -R16, -0x43300000, RZ &req={0} ?WAIT5_END_GROUP;
FSETP.NEU.AND P0, PT, |R3|, R2, PT ?WAIT5_END_GROUP;
FSEL R12, R8, R12, !P0 ?trans1;
FSEL R13, R7, R13, !P0 ?trans1;
BRA 0xe00 ?trans6;
DSETP.NAN.AND P0, PT, R8, R8, PT &wr=0x0 ?trans2;
@P0 BRA 0xde0 &req={0} ?trans5;
DSETP.NAN.AND P0, PT, R6, R6, PT &wr=0x0 ?trans2;
@P0 BRA 0xdb0 &req={0} ?trans5;
ISETP.NE.AND P0, PT, R20, R21, PT ?trans1;
MOV.64 R12, 0xfff8000000000000 ?WAIT12_END_GROUP;
@!P0 BRA 0xe00 ?trans5;
ISETP.NE.AND P0, PT, R20, 0x7ff00000, PT ?trans1;
LOP3.LUT R13, R9, 0x80000000, R7, 0x48, !PT ?WAIT4_END_GROUP;
ISETP.EQ.OR P0, PT, R21, RZ, !P0 ?WAIT13_END_GROUP;
@P0 LOP3.LUT R2, R13, 0x7ff00000, RZ, 0xfc, !PT ?trans1;
@!P0 MOV R12, RZ ?trans1;
@P0 MOV R12, RZ ?WAIT3_END_GROUP;
@P0 MOV R13, R2 ?trans1;
BRA 0xe00 ?trans6;
LOP3.LUT R13, R7, 0x80000, RZ, 0xfc, !PT ?trans1;
MOV R12, R6 ?trans1;
BRA 0xe00 ?trans6;
LOP3.LUT R13, R9, 0x80000, RZ, 0xfc, !PT ?trans1;
MOV R12, R8 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B1 ?trans5;
MOV R2, R4 ?trans1;
HFMA2 R3, -RZ, RZ, 0, 0 ?WAIT4_END_GROUP;
RET.REL.NODEC R2 0x0 ?trans5;
BRA 0xe40;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: fft(HIP_vector_type<float, 2u>*, int, int)
_Z3fftP15HIP_vector_typeIfLj2EEii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_lshr_b32 s4, s3, 31
v_add_nc_u32_e32 v0, s2, v1
s_add_i32 s2, s3, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s4, s2, 1
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, s4, v0
v_cmp_gt_i32_e64 s2, 0x400, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s5, s2
s_cbranch_execz .LBB1_2
v_cvt_f64_i32_e32 v[1:2], v1
s_mov_b32 s6, 0x54442d18
s_mov_b32 s7, 0x401921fb
v_cvt_f64_i32_e32 v[3:4], s3
s_load_b64 s[0:1], s[0:1], 0x0
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f64 v[5:6], v[1:2], s[6:7]
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_lshl_b64 s[0:1], s[4:5], 3
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_add_co_u32 v13, vcc_lo, v0, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v14, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[15:16], v[13:14], off
v_div_scale_f64 v[7:8], null, v[3:4], v[3:4], v[5:6]
v_div_scale_f64 v[19:20], vcc_lo, v[5:6], v[3:4], v[5:6]
v_rcp_f64_e32 v[9:10], v[7:8]
s_waitcnt_depctr 0xfff
v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
global_load_b64 v[11:12], v[0:1], off
v_fma_f64 v[17:18], -v[7:8], v[9:10], 1.0
v_fma_f64 v[9:10], v[9:10], v[17:18], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[17:18], v[19:20], v[9:10]
v_fma_f64 v[7:8], -v[7:8], v[17:18], v[19:20]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[7:8], v[7:8], v[9:10], v[17:18]
v_div_fixup_f64 v[2:3], v[7:8], v[3:4], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v2, v[2:3]
v_mul_f32_e32 v2, 0.15915494, v2
s_delay_alu instid0(VALU_DEP_1)
v_sin_f32_e32 v3, v2
s_waitcnt vmcnt(1)
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, v3, v16
v_mul_f32_e32 v3, v3, v15
v_cos_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_fma_f32 v5, v2, v16, -v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v3, v12, v5 :: v_dual_fmac_f32 v4, v2, v15
v_dual_sub_f32 v5, v12, v5 :: v_dual_add_f32 v2, v11, v4
v_sub_f32_e32 v4, v11, v4
s_clause 0x1
global_store_b64 v[0:1], v[2:3], off
global_store_b64 v[13:14], v[4:5], off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| fft | 4,664 | 1,769 | stackv2-00000-of-00015 |
// Demangled: void cuda_asum_doub<128u>(double*, double*)
Function : _Z14cuda_asum_doubILj128EEvPdS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x2 ?trans6;
LDC.64 R6, c[0x0][0x380] &wr=0x3 ?trans1;
S2R R0, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x4 ?trans1;
UIADD3 UR4, UPT, UPT, UR5, UR5, URZ &req={2} ?WAIT6_END_GROUP;
IMAD R5, R0, UR4, R3 &req={1} ?WAIT5_END_GROUP;
IADD3 R9, PT, PT, R5.reuse, UR5, RZ ?trans1;
IMAD.WIDE.U32 R4, R5, 0x8, R6 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R6, R9, 0x8, R6 ?trans2;
LDG.E.64 R4, desc[UR6][R4.64] &req={4} &wr=0x2 ?trans4;
LDG.E.64 R6, desc[UR6][R6.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GT.U32.AND P0, PT, R3.reuse, 0x3f, PT ?trans1;
ISETP.GT.U32.AND P1, PT, R3, 0x1f, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R13, R3, UR4, 0x3 ?trans1;
DADD R8, R4, R6 &req={2} &wr=0x1 ?trans4;
STS.64 [R13], R8 &req={1} ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 LDS.64 R10, [R13+0x200] ?trans4;
@!P0 LDS.64 R4, [R13] &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
@!P0 DADD R4, R10, R4 &req={1} &wr=0x1 ?trans2;
@!P0 STS.64 [R13], R4 &req={1} &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P1 EXIT &req={0} ?trans5;
LDS.64 R4, [R13+0x100] &req={1} ?trans1;
ISETP.NE.AND P0, PT, R3, RZ, PT ?WAIT3_END_GROUP;
LDS.64 R6, [R13] &wr=0x0 ?trans2;
DADD R4, R4, R6 &req={0} &rd=0x0 &wr=0x1 ?trans2;
LDS.64 R6, [R13+0x80] &req={0} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R4, R4, R6 &req={1} &rd=0x0 &wr=0x1 ?trans2;
LDS.64 R6, [R13+0x40] &req={0} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R4, R4, R6 &req={1} &rd=0x0 &wr=0x1 ?trans2;
LDS.64 R6, [R13+0x20] &req={0} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R4, R4, R6 &req={1} &rd=0x0 &wr=0x1 ?trans2;
LDS.64 R6, [R13+0x10] &req={0} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R4, R4, R6 &req={1} &rd=0x0 &wr=0x1 ?trans2;
LDS.64 R6, [R13+0x8] &req={0} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R4, R4, R6 &req={1} &wr=0x0 ?trans2;
STS.64 [R13], R4 &req={0} &rd=0x0 ?trans1;
@P0 EXIT ?trans5;
LDS.64 R2, [UR4] &wr=0x1 ?trans1;
LDC.64 R4, c[0x0][0x388] &req={0} &wr=0x0 ?trans2;
IMAD.WIDE.U32 R4, R0, 0x8, R4 &req={0} ?WAIT5_END_GROUP;
STG.E.64 desc[UR6][R4.64], R2 &req={1} ?trans1;
EXIT ?trans5;
BRA 0x480;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void cuda_asum_doub<128u>(double*, double*)
_Z14cuda_asum_doubILj128EEvPdS0_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s5
v_lshl_add_u32 v1, s6, 1, v0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_add_nc_u32_e32 v1, s5, v1
v_lshlrev_b64 v[1:2], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b64 v[3:4], v[3:4], off
global_load_b64 v[1:2], v[1:2], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[3:4], v[1:2]
v_lshl_add_u32 v1, v0, 3, 0
ds_store_b64 v1, v[2:3]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 64, v0
s_cbranch_execz .LBB23_2
ds_load_2addr_stride64_b64 v[2:5], v1 offset1:1
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[4:5], v[2:3]
ds_store_b64 v1, v[2:3]
.LBB23_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB23_4
ds_load_b64 v[6:7], v1 offset:256
ds_load_2addr_b64 v[2:5], v1 offset1:1
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[6:7], v[2:3]
ds_load_2addr_b64 v[6:9], v1 offset0:8 offset1:16
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[2:3], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[6:7]
ds_load_2addr_b64 v[6:9], v1 offset0:2 offset1:4
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[2:3], v[8:9]
v_add_f64 v[2:3], v[2:3], v[6:7]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[4:5]
ds_store_b64 v1, v[2:3]
.LBB23_4:
s_or_b32 exec_lo, exec_lo, s0
s_mov_b32 s5, 0
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB23_6
v_mov_b32_e32 v2, 0
s_lshl_b64 s[0:1], s[4:5], 3
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
ds_load_b64 v[0:1], v2
s_waitcnt lgkmcnt(0)
global_store_b64 v2, v[0:1], s[0:1]
.LBB23_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| void_cuda_asum_doub_128u_ | 1,545 | 1,327 | stackv2-00000-of-00015 |
// Demangled: void cuda_asum_doub<16u>(double*, double*)
Function : _Z14cuda_asum_doubILj16EEvPdS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R11, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x2 ?trans6;
LDC.64 R4, c[0x0][0x380] &wr=0x3 ?trans1;
S2R R0, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x4 ?trans1;
UIADD3 UR4, UPT, UPT, UR5, UR5, URZ &req={2} ?WAIT6_END_GROUP;
IMAD R3, R0, UR4, R11 &req={1} ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R3.reuse, UR5, RZ ?trans1;
IMAD.WIDE.U32 R2, R3, 0x8, R4 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x8, R4 ?trans2;
LDG.E.64 R2, desc[UR6][R2.64] &req={4} &wr=0x2 ?trans4;
LDG.E.64 R4, desc[UR6][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GT.U32.AND P0, PT, R11, 0x1f, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R9, R11, UR4, 0x3 ?trans1;
DADD R6, R2, R4 &req={2} &wr=0x1 ?trans4;
STS.64 [R9], R6 &req={1} &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT &req={0} ?trans5;
LDS.64 R2, [R9+0x40] ?trans1;
ISETP.NE.AND P0, PT, R11, RZ, PT ?WAIT3_END_GROUP;
LDS.64 R4, [R9] &wr=0x0 ?trans2;
DADD R2, R2, R4 &req={0} &rd=0x0 &wr=0x2 ?trans2;
LDS.64 R4, [R9+0x20] &req={0} &wr=0x2 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R2, R2, R4 &req={2} &rd=0x0 &wr=0x2 ?trans2;
LDS.64 R4, [R9+0x10] &req={0} &wr=0x2 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R2, R2, R4 &req={2} &rd=0x0 &wr=0x2 ?trans2;
LDS.64 R4, [R9+0x8] &req={0} &wr=0x2 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R2, R2, R4 &req={2} &wr=0x0 ?trans2;
STS.64 [R9], R2 &req={0} &rd=0x0 ?trans1;
@P0 EXIT ?trans5;
LDS.64 R2, [UR4] &req={0} &wr=0x0 ?trans1;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans2;
IMAD.WIDE.U32 R4, R0, 0x8, R4 &req={2} ?WAIT5_END_GROUP;
STG.E.64 desc[UR6][R4.64], R2 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x330;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void cuda_asum_doub<16u>(double*, double*)
_Z14cuda_asum_doubILj16EEvPdS0_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s5
v_lshl_add_u32 v1, s6, 1, v0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_add_nc_u32_e32 v1, s5, v1
v_lshlrev_b64 v[1:2], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b64 v[3:4], v[3:4], off
global_load_b64 v[1:2], v[1:2], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[3:4], v[1:2]
v_lshl_add_u32 v1, v0, 3, 0
ds_store_b64 v1, v[2:3]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB26_2
ds_load_b64 v[6:7], v1 offset:64
ds_load_2addr_b64 v[2:5], v1 offset1:1
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[6:7], v[2:3]
ds_load_2addr_b64 v[6:9], v1 offset0:2 offset1:4
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[2:3], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[6:7]
v_add_f64 v[2:3], v[2:3], v[4:5]
ds_store_b64 v1, v[2:3]
.LBB26_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB26_4
v_mov_b32_e32 v2, 0
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[4:5], 3
s_add_u32 s0, s2, s0
ds_load_b64 v[0:1], v2
s_addc_u32 s1, s3, s1
s_waitcnt lgkmcnt(0)
global_store_b64 v2, v[0:1], s[0:1]
.LBB26_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| void_cuda_asum_doub_16u_ | 1,158 | 1,092 | stackv2-00000-of-00015 |
// Demangled: void cuda_asum_doub<1u>(double*, double*)
Function : _Z14cuda_asum_doubILj1EEvPdS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R9, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x2 ?trans6;
LDC.64 R4, c[0x0][0x380] &wr=0x3 ?trans1;
S2R R0, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x4 ?trans1;
UIADD3 UR4, UPT, UPT, UR5, UR5, URZ &req={2} ?WAIT6_END_GROUP;
IMAD R3, R0, UR4, R9 &req={1} ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R3.reuse, UR5, RZ ?trans1;
IMAD.WIDE.U32 R2, R3, 0x8, R4 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x8, R4 ?trans2;
LDG.E.64 R2, desc[UR6][R2.64] &req={4} &wr=0x2 ?trans4;
LDG.E.64 R4, desc[UR6][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.NE.AND P0, PT, R9, RZ, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R9, R9, UR4, 0x3 ?trans1;
DADD R6, R2, R4 &req={2} &wr=0x1 ?trans4;
STS.64 [R9], R6 &req={1} &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT &req={0} ?trans5;
LDS.64 R2, [UR4] &wr=0x0 ?trans1;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans2;
IMAD.WIDE.U32 R4, R0, 0x8, R4 &req={2} ?WAIT5_END_GROUP;
STG.E.64 desc[UR6][R4.64], R2 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x1b0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void cuda_asum_doub<1u>(double*, double*)
_Z14cuda_asum_doubILj1EEvPdS0_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s5
v_lshl_add_u32 v1, s6, 1, v0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_add_nc_u32_e32 v1, s5, v1
s_mov_b32 s5, 0
v_lshlrev_b64 v[5:6], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_lshl_add_u32 v1, v0, 3, 0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_clause 0x1
global_load_b64 v[3:4], v[3:4], off
global_load_b64 v[5:6], v[5:6], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_add_f64 v[3:4], v[3:4], v[5:6]
ds_store_b64 v1, v[3:4]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB30_2
ds_load_b64 v[0:1], v2
s_mov_b32 s4, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[4:5], 3
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
s_waitcnt lgkmcnt(0)
global_store_b64 v2, v[0:1], s[0:1]
.LBB30_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| void_cuda_asum_doub_1u_ | 732 | 760 | stackv2-00000-of-00015 |
// Demangled: void cuda_asum_doub<256u>(double*, double*)
Function : _Z14cuda_asum_doubILj256EEvPdS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x2 ?trans6;
LDC.64 R6, c[0x0][0x380] &wr=0x3 ?trans1;
S2R R0, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x4 ?trans1;
UIADD3 UR4, UPT, UPT, UR5, UR5, URZ &req={2} ?WAIT6_END_GROUP;
IMAD R5, R0, UR4, R3 &req={1} ?WAIT5_END_GROUP;
IADD3 R9, PT, PT, R5.reuse, UR5, RZ ?trans1;
IMAD.WIDE.U32 R4, R5, 0x8, R6 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R6, R9, 0x8, R6 ?trans2;
LDG.E.64 R4, desc[UR6][R4.64] &req={4} &wr=0x2 ?trans4;
LDG.E.64 R6, desc[UR6][R6.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GT.U32.AND P1, PT, R3.reuse, 0x7f, PT ?trans1;
ISETP.GT.U32.AND P0, PT, R3, 0x3f, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R2, R3, UR4, 0x3 ?trans1;
DADD R8, R4, R6 &req={2} &wr=0x1 ?trans4;
STS.64 [R2], R8 &req={1} ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P1 LDS.64 R10, [R2+0x400] ?trans4;
@!P1 LDS.64 R4, [R2] &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
@!P1 DADD R4, R10, R4 &req={1} &wr=0x1 ?trans2;
@!P1 STS.64 [R2], R4 &req={1} ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P1, PT, R3, 0x1f, PT ?WAIT5_END_GROUP;
@!P0 LDS.64 R6, [R2+0x200] ?trans4;
@!P0 LDS.64 R10, [R2] &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT6_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
@!P0 DADD R6, R6, R10 &req={1} &wr=0x1 ?trans2;
@!P0 STS.64 [R2], R6 &req={1} &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P1 EXIT &req={0} ?trans5;
LDS.64 R4, [R2+0x100] ?trans1;
ISETP.NE.AND P0, PT, R3, RZ, PT ?WAIT3_END_GROUP;
LDS.64 R6, [R2] &req={1} &wr=0x0 ?trans2;
DADD R4, R4, R6 &req={0} &rd=0x0 &wr=0x1 ?trans2;
LDS.64 R6, [R2+0x80] &req={0} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R4, R4, R6 &req={1} &rd=0x0 &wr=0x1 ?trans2;
LDS.64 R6, [R2+0x40] &req={0} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R4, R4, R6 &req={1} &rd=0x0 &wr=0x1 ?trans2;
LDS.64 R6, [R2+0x20] &req={0} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R4, R4, R6 &req={1} &rd=0x0 &wr=0x1 ?trans2;
LDS.64 R6, [R2+0x10] &req={0} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R4, R4, R6 &req={1} &rd=0x0 &wr=0x1 ?trans2;
LDS.64 R6, [R2+0x8] &req={0} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R4, R4, R6 &req={1} &wr=0x0 ?trans2;
STS.64 [R2], R4 &req={0} &rd=0x0 ?trans1;
@P0 EXIT ?trans5;
LDS.64 R2, [UR4] &req={0} &wr=0x0 ?trans1;
LDC.64 R4, c[0x0][0x388] &wr=0x1 ?trans2;
IMAD.WIDE.U32 R4, R0, 0x8, R4 &req={1} ?WAIT5_END_GROUP;
STG.E.64 desc[UR6][R4.64], R2 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x510;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void cuda_asum_doub<256u>(double*, double*)
_Z14cuda_asum_doubILj256EEvPdS0_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s5
v_lshl_add_u32 v1, s6, 1, v0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_add_nc_u32_e32 v1, s5, v1
v_lshlrev_b64 v[1:2], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b64 v[3:4], v[3:4], off
global_load_b64 v[1:2], v[1:2], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[3:4], v[1:2]
v_lshl_add_u32 v1, v0, 3, 0
ds_store_b64 v1, v[2:3]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 0x80, v0
s_cbranch_execz .LBB22_2
ds_load_2addr_stride64_b64 v[2:5], v1 offset1:2
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[4:5], v[2:3]
ds_store_b64 v1, v[2:3]
.LBB22_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 64, v0
s_cbranch_execz .LBB22_4
ds_load_b64 v[2:3], v1 offset:512
ds_load_b64 v[4:5], v1
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
ds_store_b64 v1, v[2:3]
.LBB22_4:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB22_6
ds_load_b64 v[6:7], v1 offset:256
ds_load_2addr_b64 v[2:5], v1 offset1:1
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[6:7], v[2:3]
ds_load_2addr_b64 v[6:9], v1 offset0:8 offset1:16
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[2:3], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[6:7]
ds_load_2addr_b64 v[6:9], v1 offset0:2 offset1:4
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[2:3], v[8:9]
v_add_f64 v[2:3], v[2:3], v[6:7]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[4:5]
ds_store_b64 v1, v[2:3]
.LBB22_6:
s_or_b32 exec_lo, exec_lo, s0
s_mov_b32 s5, 0
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB22_8
v_mov_b32_e32 v2, 0
s_lshl_b64 s[0:1], s[4:5], 3
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
ds_load_b64 v[0:1], v2
s_waitcnt lgkmcnt(0)
global_store_b64 v2, v[0:1], s[0:1]
.LBB22_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| void_cuda_asum_doub_256u_ | 1,706 | 1,503 | stackv2-00000-of-00015 |
// Demangled: void cuda_asum_doub<2u>(double*, double*)
Function : _Z14cuda_asum_doubILj2EEvPdS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x2 ?trans6;
LDC.64 R4, c[0x0][0x380] &wr=0x3 ?trans1;
S2R R11, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x4 ?trans1;
UIADD3 UR4, UPT, UPT, UR5, UR5, URZ &req={2} ?WAIT6_END_GROUP;
IMAD R3, R11, UR4, R0 &req={1} ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R3.reuse, UR5, RZ ?trans1;
IMAD.WIDE.U32 R2, R3, 0x8, R4 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x8, R4 ?trans2;
LDG.E.64 R2, desc[UR6][R2.64] &req={4} &wr=0x2 ?trans4;
LDG.E.64 R4, desc[UR6][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GT.U32.AND P0, PT, R0, 0x1f, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R9, R0, UR4, 0x3 ?trans1;
DADD R6, R2, R4 &req={2} &wr=0x1 ?trans4;
STS.64 [R9], R6 &req={1} &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT &req={0} ?trans5;
LDS.64 R2, [R9+0x8] ?trans1;
ISETP.NE.AND P0, PT, R0, RZ, PT ?WAIT3_END_GROUP;
LDS.64 R4, [R9] &wr=0x0 ?trans2;
DADD R2, R2, R4 &req={0} &wr=0x0 ?trans2;
STS.64 [R9], R2 &req={0} &rd=0x0 ?trans6;
@P0 EXIT ?trans5;
LDS.64 R2, [UR4] &req={0} &wr=0x0 ?trans1;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans2;
IMAD.WIDE.U32 R4, R11, 0x8, R4 &req={2} ?WAIT5_END_GROUP;
STG.E.64 desc[UR6][R4.64], R2 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x210;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void cuda_asum_doub<2u>(double*, double*)
_Z14cuda_asum_doubILj2EEvPdS0_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s5
v_lshl_add_u32 v1, s6, 1, v0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_add_nc_u32_e32 v1, s5, v1
v_lshlrev_b64 v[1:2], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b64 v[3:4], v[3:4], off
global_load_b64 v[1:2], v[1:2], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[3:4], v[1:2]
v_lshl_add_u32 v1, v0, 3, 0
ds_store_b64 v1, v[2:3]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB29_2
ds_load_2addr_b64 v[2:5], v1 offset1:1
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[4:5], v[2:3]
ds_store_b64 v1, v[2:3]
.LBB29_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB29_4
v_mov_b32_e32 v2, 0
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[4:5], 3
s_add_u32 s0, s2, s0
ds_load_b64 v[0:1], v2
s_addc_u32 s1, s3, s1
s_waitcnt lgkmcnt(0)
global_store_b64 v2, v[0:1], s[0:1]
.LBB29_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| void_cuda_asum_doub_2u_ | 874 | 936 | stackv2-00000-of-00015 |
// Demangled: void cuda_asum_doub<32u>(double*, double*)
Function : _Z14cuda_asum_doubILj32EEvPdS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R11, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x2 ?trans6;
LDC.64 R4, c[0x0][0x380] &wr=0x3 ?trans1;
S2R R0, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x4 ?trans1;
UIADD3 UR4, UPT, UPT, UR5, UR5, URZ &req={2} ?WAIT6_END_GROUP;
IMAD R3, R0, UR4, R11 &req={1} ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R3.reuse, UR5, RZ ?trans1;
IMAD.WIDE.U32 R2, R3, 0x8, R4 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x8, R4 ?trans2;
LDG.E.64 R2, desc[UR6][R2.64] &req={4} &wr=0x2 ?trans4;
LDG.E.64 R4, desc[UR6][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GT.U32.AND P0, PT, R11, 0x1f, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R9, R11, UR4, 0x3 ?trans1;
DADD R6, R2, R4 &req={2} &wr=0x1 ?trans4;
STS.64 [R9], R6 &req={1} &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT &req={0} ?trans5;
LDS.64 R2, [R9+0x80] ?trans1;
ISETP.NE.AND P0, PT, R11, RZ, PT ?WAIT3_END_GROUP;
LDS.64 R4, [R9] &wr=0x0 ?trans2;
DADD R2, R2, R4 &req={0} &rd=0x0 &wr=0x2 ?trans2;
LDS.64 R4, [R9+0x40] &req={0} &wr=0x2 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R2, R2, R4 &req={2} &rd=0x0 &wr=0x2 ?trans2;
LDS.64 R4, [R9+0x20] &req={0} &wr=0x2 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R2, R2, R4 &req={2} &rd=0x0 &wr=0x2 ?trans2;
LDS.64 R4, [R9+0x10] &req={0} &wr=0x2 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R2, R2, R4 &req={2} &rd=0x0 &wr=0x2 ?trans2;
LDS.64 R4, [R9+0x8] &req={0} &wr=0x2 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R2, R2, R4 &req={2} &wr=0x0 ?trans2;
STS.64 [R9], R2 &req={0} &rd=0x0 ?trans1;
@P0 EXIT ?trans5;
LDS.64 R2, [UR4] &req={0} &wr=0x0 ?trans1;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans2;
IMAD.WIDE.U32 R4, R0, 0x8, R4 &req={2} ?WAIT5_END_GROUP;
STG.E.64 desc[UR6][R4.64], R2 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x390;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void cuda_asum_doub<32u>(double*, double*)
_Z14cuda_asum_doubILj32EEvPdS0_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s5
v_lshl_add_u32 v1, s6, 1, v0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_add_nc_u32_e32 v1, s5, v1
v_lshlrev_b64 v[1:2], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b64 v[3:4], v[3:4], off
global_load_b64 v[1:2], v[1:2], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[3:4], v[1:2]
v_lshl_add_u32 v1, v0, 3, 0
ds_store_b64 v1, v[2:3]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB25_2
ds_load_2addr_b64 v[2:5], v1 offset0:8 offset1:16
ds_load_2addr_b64 v[6:9], v1 offset1:1
s_waitcnt lgkmcnt(0)
v_add_f64 v[4:5], v[4:5], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_f64 v[6:7], v[4:5], v[2:3]
ds_load_2addr_b64 v[2:5], v1 offset0:2 offset1:4
s_waitcnt lgkmcnt(0)
v_add_f64 v[4:5], v[6:7], v[4:5]
v_add_f64 v[2:3], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[8:9]
ds_store_b64 v1, v[2:3]
.LBB25_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB25_4
v_mov_b32_e32 v2, 0
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[4:5], 3
s_add_u32 s0, s2, s0
ds_load_b64 v[0:1], v2
s_addc_u32 s1, s3, s1
s_waitcnt lgkmcnt(0)
global_store_b64 v2, v[0:1], s[0:1]
.LBB25_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| void_cuda_asum_doub_32u_ | 1,257 | 1,140 | stackv2-00000-of-00015 |
// Demangled: void cuda_asum_doub<4u>(double*, double*)
Function : _Z14cuda_asum_doubILj4EEvPdS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x2 ?trans6;
LDC.64 R4, c[0x0][0x380] &wr=0x3 ?trans1;
S2R R11, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x4 ?trans1;
UIADD3 UR4, UPT, UPT, UR5, UR5, URZ &req={2} ?WAIT6_END_GROUP;
IMAD R3, R11, UR4, R0 &req={1} ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R3.reuse, UR5, RZ ?trans1;
IMAD.WIDE.U32 R2, R3, 0x8, R4 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x8, R4 ?trans2;
LDG.E.64 R2, desc[UR6][R2.64] &req={4} &wr=0x2 ?trans4;
LDG.E.64 R4, desc[UR6][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GT.U32.AND P0, PT, R0, 0x1f, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R9, R0, UR4, 0x3 ?trans1;
DADD R6, R2, R4 &req={2} &wr=0x1 ?trans4;
STS.64 [R9], R6 &req={1} &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT &req={0} ?trans5;
LDS.64 R2, [R9+0x10] ?trans1;
ISETP.NE.AND P0, PT, R0, RZ, PT ?WAIT3_END_GROUP;
LDS.64 R4, [R9] &wr=0x0 ?trans2;
DADD R2, R2, R4 &req={0} &rd=0x0 &wr=0x2 ?trans2;
LDS.64 R4, [R9+0x8] &req={0} &wr=0x2 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R2, R2, R4 &req={2} &wr=0x0 ?trans2;
STS.64 [R9], R2 &req={0} &rd=0x0 ?trans1;
@P0 EXIT ?trans5;
LDS.64 R2, [UR4] &req={0} &wr=0x0 ?trans1;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans2;
IMAD.WIDE.U32 R4, R11, 0x8, R4 &req={2} ?WAIT5_END_GROUP;
STG.E.64 desc[UR6][R4.64], R2 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x270;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void cuda_asum_doub<4u>(double*, double*)
_Z14cuda_asum_doubILj4EEvPdS0_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s5
v_lshl_add_u32 v1, s6, 1, v0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_add_nc_u32_e32 v1, s5, v1
v_lshlrev_b64 v[1:2], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b64 v[3:4], v[3:4], off
global_load_b64 v[1:2], v[1:2], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[3:4], v[1:2]
v_lshl_add_u32 v1, v0, 3, 0
ds_store_b64 v1, v[2:3]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB28_2
ds_load_b64 v[6:7], v1 offset:16
ds_load_2addr_b64 v[2:5], v1 offset1:1
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[6:7], v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[4:5]
ds_store_b64 v1, v[2:3]
.LBB28_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB28_4
v_mov_b32_e32 v2, 0
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[4:5], 3
s_add_u32 s0, s2, s0
ds_load_b64 v[0:1], v2
s_addc_u32 s1, s3, s1
s_waitcnt lgkmcnt(0)
global_store_b64 v2, v[0:1], s[0:1]
.LBB28_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| void_cuda_asum_doub_4u_ | 957 | 992 | stackv2-00000-of-00015 |
// Demangled: void cuda_asum_doub<512u>(double*, double*)
Function : _Z14cuda_asum_doubILj512EEvPdS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x2 ?trans6;
LDC.64 R6, c[0x0][0x380] &wr=0x3 ?trans1;
S2R R0, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x4 ?trans1;
UIADD3 UR4, UPT, UPT, UR5, UR5, URZ &req={2} ?WAIT6_END_GROUP;
IMAD R5, R0, UR4, R3 &req={1} ?WAIT5_END_GROUP;
IADD3 R9, PT, PT, R5.reuse, UR5, RZ ?trans1;
IMAD.WIDE.U32 R4, R5, 0x8, R6 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R6, R9, 0x8, R6 ?trans2;
LDG.E.64 R4, desc[UR6][R4.64] &req={4} &wr=0x2 ?trans4;
LDG.E.64 R6, desc[UR6][R6.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GT.U32.AND P1, PT, R3.reuse, 0xff, PT ?trans1;
ISETP.GT.U32.AND P0, PT, R3, 0x7f, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R2, R3, UR4, 0x3 ?trans1;
DADD R8, R4, R6 &req={2} &wr=0x1 ?trans4;
STS.64 [R2], R8 &req={1} ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P1 LDS.64 R10, [R2+0x800] ?trans4;
@!P1 LDS.64 R4, [R2] &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
@!P1 DADD R4, R10, R4 &req={1} &wr=0x1 ?trans2;
@!P1 STS.64 [R2], R4 &req={1} ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P1, PT, R3, 0x3f, PT ?WAIT5_END_GROUP;
@!P0 LDS.64 R6, [R2+0x400] ?trans4;
@!P0 LDS.64 R10, [R2] &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT6_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
@!P0 DADD R6, R6, R10 &req={1} &wr=0x1 ?trans2;
@!P0 STS.64 [R2], R6 &req={1} ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P0, PT, R3, 0x1f, PT ?WAIT5_END_GROUP;
@!P1 LDS.64 R8, [R2+0x200] ?trans4;
@!P1 LDS.64 R10, [R2] &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT6_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
@!P1 DADD R8, R8, R10 &req={1} &wr=0x1 ?trans2;
@!P1 STS.64 [R2], R8 &req={1} &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT &req={0} ?trans5;
LDS.64 R4, [R2+0x100] ?trans1;
ISETP.NE.AND P0, PT, R3, RZ, PT ?WAIT3_END_GROUP;
LDS.64 R6, [R2] &wr=0x0 ?trans2;
DADD R4, R4, R6 &req={0} &rd=0x0 &wr=0x2 ?trans2;
LDS.64 R6, [R2+0x80] &req={0} &wr=0x2 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R4, R4, R6 &req={2} &rd=0x0 &wr=0x2 ?trans2;
LDS.64 R6, [R2+0x40] &req={0} &wr=0x2 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R4, R4, R6 &req={2} &rd=0x0 &wr=0x2 ?trans2;
LDS.64 R6, [R2+0x20] &req={0} &wr=0x2 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R4, R4, R6 &req={2} &rd=0x0 &wr=0x2 ?trans2;
LDS.64 R6, [R2+0x10] &req={0} &wr=0x2 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R4, R4, R6 &req={2} &rd=0x0 &wr=0x2 ?trans2;
LDS.64 R6, [R2+0x8] &req={0} &wr=0x2 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R4, R4, R6 &req={2} &wr=0x0 ?trans2;
STS.64 [R2], R4 &req={0} &rd=0x0 ?trans1;
@P0 EXIT ?trans5;
LDS.64 R2, [UR4] &req={1,0} &wr=0x0 ?trans1;
LDC.64 R4, c[0x0][0x388] &wr=0x1 ?trans2;
IMAD.WIDE.U32 R4, R0, 0x8, R4 &req={1} ?WAIT5_END_GROUP;
STG.E.64 desc[UR6][R4.64], R2 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x5a0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void cuda_asum_doub<512u>(double*, double*)
_Z14cuda_asum_doubILj512EEvPdS0_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s5
v_lshl_add_u32 v1, s6, 1, v0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_add_nc_u32_e32 v1, s5, v1
v_lshlrev_b64 v[1:2], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b64 v[3:4], v[3:4], off
global_load_b64 v[1:2], v[1:2], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[3:4], v[1:2]
v_lshl_add_u32 v1, v0, 3, 0
ds_store_b64 v1, v[2:3]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 0x100, v0
s_cbranch_execz .LBB21_2
ds_load_2addr_stride64_b64 v[2:5], v1 offset1:4
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[4:5], v[2:3]
ds_store_b64 v1, v[2:3]
.LBB21_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 0x80, v0
s_cbranch_execz .LBB21_4
ds_load_b64 v[2:3], v1 offset:1024
ds_load_b64 v[4:5], v1
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
ds_store_b64 v1, v[2:3]
.LBB21_4:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 64, v0
s_cbranch_execz .LBB21_6
ds_load_b64 v[2:3], v1 offset:512
ds_load_b64 v[4:5], v1
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
ds_store_b64 v1, v[2:3]
.LBB21_6:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB21_8
ds_load_b64 v[6:7], v1 offset:256
ds_load_2addr_b64 v[2:5], v1 offset1:1
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[6:7], v[2:3]
ds_load_2addr_b64 v[6:9], v1 offset0:8 offset1:16
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[2:3], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[6:7]
ds_load_2addr_b64 v[6:9], v1 offset0:2 offset1:4
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[2:3], v[8:9]
v_add_f64 v[2:3], v[2:3], v[6:7]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[4:5]
ds_store_b64 v1, v[2:3]
.LBB21_8:
s_or_b32 exec_lo, exec_lo, s0
s_mov_b32 s5, 0
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB21_10
v_mov_b32_e32 v2, 0
s_lshl_b64 s[0:1], s[4:5], 3
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
ds_load_b64 v[0:1], v2
s_waitcnt lgkmcnt(0)
global_store_b64 v2, v[0:1], s[0:1]
.LBB21_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| void_cuda_asum_doub_512u_ | 1,875 | 1,683 | stackv2-00000-of-00015 |
// Demangled: void cuda_asum_doub<64u>(double*, double*)
Function : _Z14cuda_asum_doubILj64EEvPdS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x2 ?trans6;
LDC.64 R6, c[0x0][0x380] &wr=0x3 ?trans1;
S2R R0, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x4 ?trans1;
UIADD3 UR4, UPT, UPT, UR5, UR5, URZ &req={2} ?WAIT6_END_GROUP;
IMAD R5, R0, UR4, R3 &req={1} ?WAIT5_END_GROUP;
IADD3 R9, PT, PT, R5.reuse, UR5, RZ ?trans1;
IMAD.WIDE.U32 R4, R5, 0x8, R6 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R6, R9, 0x8, R6 ?trans2;
LDG.E.64 R4, desc[UR6][R4.64] &req={4} &wr=0x2 ?trans4;
LDG.E.64 R6, desc[UR6][R6.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GT.U32.AND P0, PT, R3, 0x1f, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R11, R3, UR4, 0x3 ?trans1;
DADD R8, R4, R6 &req={2} &wr=0x1 ?trans4;
STS.64 [R11], R8 &req={1} &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT &req={0} ?trans5;
LDS.64 R4, [R11+0x100] ?trans1;
ISETP.NE.AND P0, PT, R3, RZ, PT ?WAIT3_END_GROUP;
LDS.64 R6, [R11] &wr=0x0 ?trans2;
DADD R4, R4, R6 &req={0} &rd=0x0 &wr=0x2 ?trans2;
LDS.64 R6, [R11+0x80] &req={0} &wr=0x2 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R4, R4, R6 &req={2} &rd=0x0 &wr=0x2 ?trans2;
LDS.64 R6, [R11+0x40] &req={0} &wr=0x2 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R4, R4, R6 &req={2} &rd=0x0 &wr=0x2 ?trans2;
LDS.64 R6, [R11+0x20] &req={0} &wr=0x2 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R4, R4, R6 &req={2} &rd=0x0 &wr=0x2 ?trans2;
LDS.64 R6, [R11+0x10] &req={0} &wr=0x2 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R4, R4, R6 &req={2} &rd=0x0 &wr=0x2 ?trans2;
LDS.64 R6, [R11+0x8] &req={0} &wr=0x2 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R4, R4, R6 &req={2} &wr=0x0 ?trans2;
STS.64 [R11], R4 &req={0} &rd=0x0 ?trans1;
@P0 EXIT ?trans5;
LDS.64 R2, [UR4] &wr=0x2 ?trans1;
LDC.64 R4, c[0x0][0x388] &req={0} &wr=0x0 ?trans2;
IMAD.WIDE.U32 R4, R0, 0x8, R4 &req={0} ?WAIT5_END_GROUP;
STG.E.64 desc[UR6][R4.64], R2 &req={2} ?trans1;
EXIT ?trans5;
BRA 0x3f0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void cuda_asum_doub<64u>(double*, double*)
_Z14cuda_asum_doubILj64EEvPdS0_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s5
v_lshl_add_u32 v1, s6, 1, v0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_add_nc_u32_e32 v1, s5, v1
v_lshlrev_b64 v[1:2], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b64 v[3:4], v[3:4], off
global_load_b64 v[1:2], v[1:2], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[3:4], v[1:2]
v_lshl_add_u32 v1, v0, 3, 0
ds_store_b64 v1, v[2:3]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB24_2
ds_load_b64 v[6:7], v1 offset:256
ds_load_2addr_b64 v[2:5], v1 offset1:1
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[6:7], v[2:3]
ds_load_2addr_b64 v[6:9], v1 offset0:8 offset1:16
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[2:3], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[6:7]
ds_load_2addr_b64 v[6:9], v1 offset0:2 offset1:4
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[2:3], v[8:9]
v_add_f64 v[2:3], v[2:3], v[6:7]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[4:5]
ds_store_b64 v1, v[2:3]
.LBB24_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB24_4
v_mov_b32_e32 v2, 0
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[4:5], 3
s_add_u32 s0, s2, s0
ds_load_b64 v[0:1], v2
s_addc_u32 s1, s3, s1
s_waitcnt lgkmcnt(0)
global_store_b64 v2, v[0:1], s[0:1]
.LBB24_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| void_cuda_asum_doub_64u_ | 1,346 | 1,192 | stackv2-00000-of-00015 |
// Demangled: void cuda_asum_doub<8u>(double*, double*)
Function : _Z14cuda_asum_doubILj8EEvPdS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x2 ?trans6;
LDC.64 R4, c[0x0][0x380] &wr=0x3 ?trans1;
S2R R11, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x4 ?trans1;
UIADD3 UR4, UPT, UPT, UR5, UR5, URZ &req={2} ?WAIT6_END_GROUP;
IMAD R3, R11, UR4, R0 &req={1} ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R3.reuse, UR5, RZ ?trans1;
IMAD.WIDE.U32 R2, R3, 0x8, R4 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x8, R4 ?trans2;
LDG.E.64 R2, desc[UR6][R2.64] &req={4} &wr=0x2 ?trans4;
LDG.E.64 R4, desc[UR6][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GT.U32.AND P0, PT, R0, 0x1f, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R9, R0, UR4, 0x3 ?trans1;
DADD R6, R2, R4 &req={2} &wr=0x1 ?trans4;
STS.64 [R9], R6 &req={1} &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT &req={0} ?trans5;
LDS.64 R2, [R9+0x20] ?trans1;
ISETP.NE.AND P0, PT, R0, RZ, PT ?WAIT3_END_GROUP;
LDS.64 R4, [R9] &wr=0x0 ?trans2;
DADD R2, R2, R4 &req={0} &rd=0x0 &wr=0x2 ?trans2;
LDS.64 R4, [R9+0x10] &req={0} &wr=0x2 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R2, R2, R4 &req={2} &rd=0x0 &wr=0x2 ?trans2;
LDS.64 R4, [R9+0x8] &req={0} &wr=0x2 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R2, R2, R4 &req={2} &wr=0x0 ?trans2;
STS.64 [R9], R2 &req={0} &rd=0x0 ?trans1;
@P0 EXIT ?trans5;
LDS.64 R2, [UR4] &req={0} &wr=0x0 ?trans1;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans2;
IMAD.WIDE.U32 R4, R11, 0x8, R4 &req={2} ?WAIT5_END_GROUP;
STG.E.64 desc[UR6][R4.64], R2 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x2d0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void cuda_asum_doub<8u>(double*, double*)
_Z14cuda_asum_doubILj8EEvPdS0_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s5
v_lshl_add_u32 v1, s6, 1, v0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_add_nc_u32_e32 v1, s5, v1
v_lshlrev_b64 v[1:2], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b64 v[3:4], v[3:4], off
global_load_b64 v[1:2], v[1:2], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[3:4], v[1:2]
v_lshl_add_u32 v1, v0, 3, 0
ds_store_b64 v1, v[2:3]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB27_2
ds_load_2addr_b64 v[2:5], v1 offset0:2 offset1:4
ds_load_2addr_b64 v[6:9], v1 offset1:1
s_waitcnt lgkmcnt(0)
v_add_f64 v[4:5], v[4:5], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[4:5], v[2:3]
v_add_f64 v[2:3], v[2:3], v[8:9]
ds_store_b64 v1, v[2:3]
.LBB27_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB27_4
v_mov_b32_e32 v2, 0
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[4:5], 3
s_add_u32 s0, s2, s0
ds_load_b64 v[0:1], v2
s_addc_u32 s1, s3, s1
s_waitcnt lgkmcnt(0)
global_store_b64 v2, v[0:1], s[0:1]
.LBB27_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| void_cuda_asum_doub_8u_ | 1,056 | 1,040 | stackv2-00000-of-00015 |
// Demangled: void cuda_asum_flt<1024u>(float*, float*)
Function : _Z13cuda_asum_fltILj1024EEvPfS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x2 ?trans6;
LDC.64 R6, c[0x0][0x380] &wr=0x3 ?trans1;
S2R R0, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x4 ?trans1;
UIADD3 UR4, UPT, UPT, UR5, UR5, URZ &req={2} ?WAIT6_END_GROUP;
IMAD R5, R0, UR4, R3 &req={1} ?WAIT5_END_GROUP;
IADD3 R9, PT, PT, R5.reuse, UR5, RZ ?trans1;
IMAD.WIDE.U32 R4, R5, 0x4, R6 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R6, R9, 0x4, R6 ?trans2;
LDG.E R4, desc[UR6][R4.64] &req={4} &wr=0x2 ?trans4;
LDG.E R7, desc[UR6][R6.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GT.U32.AND P1, PT, R3.reuse, 0x1ff, PT ?trans1;
ISETP.GT.U32.AND P0, PT, R3, 0xff, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R9, R3, UR4, 0x2 ?trans1;
FADD R2, R4, R7 &req={2} ?WAIT5_END_GROUP;
STS [R9], R2 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P1 LDS R8, [R9+0x800] ?trans4;
@!P1 LDS R5, [R9] &wr=0x1 ?trans2;
@!P1 FADD R8, R8, R5 &req={1} ?WAIT5_END_GROUP;
@!P1 STS [R9], R8 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P1, PT, R3, 0x7f, PT ?WAIT5_END_GROUP;
@!P0 LDS R4, [R9+0x400] ?trans4;
@!P0 LDS R5, [R9] &wr=0x1 ?trans2;
@!P0 FADD R4, R4, R5 &req={1} ?WAIT5_END_GROUP;
@!P0 STS [R9], R4 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P0, PT, R3, 0x3f, PT ?WAIT5_END_GROUP;
@!P1 LDS R2, [R9+0x200] ?trans4;
@!P1 LDS R5, [R9] &wr=0x1 ?trans2;
@!P1 FADD R2, R2, R5 &req={1} ?WAIT5_END_GROUP;
@!P1 STS [R9], R2 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT &req={0} ?trans5;
LDS R2, [R9+0x100] &req={1} ?trans1;
ISETP.NE.AND P0, PT, R3, RZ, PT ?WAIT3_END_GROUP;
LDS R5, [R9] &wr=0x0 ?trans2;
FADD R2, R2, R5 &req={0} ?WAIT5_END_GROUP;
STS [R9], R2 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R4, [R9+0x80] ?trans4;
LDS R5, [R9] &wr=0x0 ?trans2;
FADD R4, R4, R5 &req={0} ?WAIT5_END_GROUP;
STS [R9], R4 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R5, [R9+0x40] ?trans4;
LDS R6, [R9] &wr=0x0 ?trans2;
FADD R6, R5, R6 &req={0} ?WAIT5_END_GROUP;
STS [R9], R6 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R2, [R9+0x20] ?trans4;
LDS R5, [R9] &wr=0x0 ?trans2;
FADD R2, R2, R5 &req={0} ?WAIT5_END_GROUP;
STS [R9], R2 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R4, [R9+0x10] ?trans4;
LDS R5, [R9] &wr=0x0 ?trans2;
FADD R4, R4, R5 &req={0} ?WAIT5_END_GROUP;
STS [R9], R4 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R5, [R9+0x8] ?trans4;
LDS R6, [R9] &wr=0x0 ?trans2;
FADD R6, R5, R6 &req={0} ?WAIT5_END_GROUP;
STS [R9], R6 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R2, [R9+0x4] ?trans4;
LDS R5, [R9] &wr=0x0 ?trans2;
FADD R2, R2, R5 &req={0} ?WAIT5_END_GROUP;
STS [R9], R2 &rd=0x0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT ?trans5;
LDS R5, [UR4] &wr=0x1 ?trans1;
LDC.64 R2, c[0x0][0x388] &req={0} &wr=0x0 ?trans2;
IMAD.WIDE.U32 R2, R0, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R5 &req={1} ?trans1;
EXIT ?trans5;
BRA 0x520;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void cuda_asum_flt<1024u>(float*, float*)
_Z13cuda_asum_fltILj1024EEvPfS0_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s5
v_lshl_add_u32 v1, s6, 1, v0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s5, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 0x200, v0
s_cbranch_execz .LBB10_2
ds_load_2addr_stride64_b32 v[2:3], v1 offset1:8
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
.LBB10_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 0x100, v0
s_cbranch_execz .LBB10_4
ds_load_b32 v2, v1 offset:1024
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB10_4:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 0x80, v0
s_cbranch_execz .LBB10_6
ds_load_b32 v2, v1 offset:512
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB10_6:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 64, v0
s_cbranch_execz .LBB10_8
ds_load_b32 v2, v1 offset:256
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:32
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:16
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:8
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB10_8:
s_or_b32 exec_lo, exec_lo, s0
s_mov_b32 s5, 0
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB10_10
v_mov_b32_e32 v0, 0
s_lshl_b64 s[0:1], s[4:5], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB10_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| void_cuda_asum_flt_1024u_ | 1,742 | 1,851 | stackv2-00000-of-00015 |
// Demangled: void cuda_asum_flt<128u>(float*, float*)
Function : _Z13cuda_asum_fltILj128EEvPfS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R9, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x2 ?trans6;
LDC.64 R4, c[0x0][0x380] &wr=0x3 ?trans1;
S2R R0, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x4 ?trans1;
UIADD3 UR4, UPT, UPT, UR5, UR5, URZ &req={2} ?WAIT6_END_GROUP;
IMAD R3, R0, UR4, R9 &req={1} ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R3.reuse, UR5, RZ ?trans1;
IMAD.WIDE.U32 R2, R3, 0x4, R4 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x4, R4 ?trans2;
LDG.E R2, desc[UR6][R2.64] &req={4} &wr=0x2 ?trans4;
LDG.E R5, desc[UR6][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GT.U32.AND P0, PT, R9, 0x3f, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R7, R9, UR4, 0x2 ?trans1;
FADD R6, R2, R5 &req={2} ?WAIT5_END_GROUP;
STS [R7], R6 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT &req={0} ?trans5;
LDS R2, [R7+0x100] ?trans1;
ISETP.NE.AND P0, PT, R9, RZ, PT ?WAIT3_END_GROUP;
LDS R3, [R7] &wr=0x0 ?trans2;
FADD R2, R2, R3 &req={0} ?WAIT5_END_GROUP;
STS [R7], R2 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R3, [R7+0x80] ?trans4;
LDS R4, [R7] &wr=0x0 ?trans2;
FADD R4, R3, R4 &req={0} ?WAIT5_END_GROUP;
STS [R7], R4 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R3, [R7+0x40] ?trans4;
LDS R6, [R7] &req={1} &wr=0x0 ?trans2;
FADD R6, R3, R6 &req={0} ?WAIT5_END_GROUP;
STS [R7], R6 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R2, [R7+0x20] ?trans4;
LDS R3, [R7] &wr=0x0 ?trans2;
FADD R2, R2, R3 &req={0} ?WAIT5_END_GROUP;
STS [R7], R2 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R3, [R7+0x10] ?trans4;
LDS R4, [R7] &wr=0x0 ?trans2;
FADD R4, R3, R4 &req={0} ?WAIT5_END_GROUP;
STS [R7], R4 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R3, [R7+0x8] ?trans4;
LDS R6, [R7] &wr=0x0 ?trans2;
FADD R6, R3, R6 &req={0} ?WAIT5_END_GROUP;
STS [R7], R6 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R2, [R7+0x4] ?trans4;
LDS R3, [R7] &wr=0x0 ?trans2;
FADD R2, R2, R3 &req={0} ?WAIT5_END_GROUP;
STS [R7], R2 &rd=0x0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT ?trans5;
LDS R5, [UR4] &wr=0x1 ?trans1;
LDC.64 R2, c[0x0][0x388] &req={0} &wr=0x0 ?trans2;
IMAD.WIDE.U32 R2, R0, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R5 &req={1} ?trans1;
EXIT ?trans5;
BRA 0x400;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void cuda_asum_flt<128u>(float*, float*)
_Z13cuda_asum_fltILj128EEvPfS0_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s5
v_lshl_add_u32 v1, s6, 1, v0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s5, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 64, v0
s_cbranch_execz .LBB13_2
ds_load_2addr_stride64_b32 v[2:3], v1 offset1:1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:32
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:16
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:8
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB13_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB13_4
v_mov_b32_e32 v0, 0
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[4:5], 2
s_add_u32 s0, s2, s0
ds_load_b32 v1, v0
s_addc_u32 s1, s3, s1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB13_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| void_cuda_asum_flt_128u_ | 1,357 | 1,393 | stackv2-00000-of-00015 |
// Demangled: void cuda_asum_flt<16u>(float*, float*)
Function : _Z13cuda_asum_fltILj16EEvPfS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R6, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x2 ?trans6;
LDC.64 R4, c[0x0][0x380] &wr=0x3 ?trans1;
S2R R9, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x4 ?trans1;
UIADD3 UR4, UPT, UPT, UR5, UR5, URZ &req={2} ?WAIT6_END_GROUP;
IMAD R3, R9, UR4, R6 &req={1} ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R3.reuse, UR5, RZ ?trans1;
IMAD.WIDE.U32 R2, R3, 0x4, R4 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x4, R4 ?trans2;
LDG.E R2, desc[UR6][R2.64] &req={4} &wr=0x2 ?trans4;
LDG.E R5, desc[UR6][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GT.U32.AND P0, PT, R6, 0x3f, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R7, R6, UR4, 0x2 ?trans1;
FADD R0, R2, R5 &req={2} ?WAIT5_END_GROUP;
STS [R7], R0 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT &req={0} ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans8;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans8;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.NE.AND P0, PT, R6, RZ, PT ?WAIT5_END_GROUP;
LDS R0, [R7+0x20] &req={1} ?trans4;
LDS R3, [R7] &wr=0x0 ?trans2;
FADD R0, R0, R3 &req={0} ?WAIT5_END_GROUP;
STS [R7], R0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R2, [R7+0x10] ?trans4;
LDS R3, [R7] &wr=0x0 ?trans2;
FADD R2, R2, R3 &req={0} ?WAIT5_END_GROUP;
STS [R7], R2 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R3, [R7+0x8] ?trans4;
LDS R4, [R7] &wr=0x0 ?trans2;
FADD R4, R3, R4 &req={0} ?WAIT5_END_GROUP;
STS [R7], R4 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R0, [R7+0x4] ?trans4;
LDS R3, [R7] &wr=0x0 ?trans2;
FADD R0, R0, R3 &req={0} ?WAIT5_END_GROUP;
STS [R7], R0 &rd=0x0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT ?trans5;
LDS R5, [UR4] &wr=0x1 ?trans1;
LDC.64 R2, c[0x0][0x388] &wr=0x2 ?trans2;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R5 &req={1} ?trans1;
EXIT ?trans5;
BRA 0x340;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void cuda_asum_flt<16u>(float*, float*)
_Z13cuda_asum_fltILj16EEvPfS0_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s5
v_lshl_add_u32 v1, s6, 1, v0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s5, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 64, v0
s_cbranch_execz .LBB16_2
s_barrier
buffer_gl0_inv
s_barrier
buffer_gl0_inv
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:8
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB16_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB16_4
v_mov_b32_e32 v0, 0
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[4:5], 2
s_add_u32 s0, s2, s0
ds_load_b32 v1, v0
s_addc_u32 s1, s3, s1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB16_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| void_cuda_asum_flt_16u_ | 1,135 | 1,180 | stackv2-00000-of-00015 |
// Demangled: void cuda_asum_flt<1u>(float*, float*)
Function : _Z13cuda_asum_fltILj1EEvPfS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R6, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x2 ?trans6;
LDC.64 R4, c[0x0][0x380] &wr=0x3 ?trans1;
S2R R9, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x4 ?trans1;
UIADD3 UR4, UPT, UPT, UR5, UR5, URZ &req={2} ?WAIT6_END_GROUP;
IMAD R3, R9, UR4, R6 &req={1} ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R3.reuse, UR5, RZ ?trans1;
IMAD.WIDE.U32 R2, R3, 0x4, R4 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x4, R4 ?trans2;
LDG.E R2, desc[UR6][R2.64] &req={4} &wr=0x2 ?trans4;
LDG.E R5, desc[UR6][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GT.U32.AND P0, PT, R6, 0x3f, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R7, R6, UR4, 0x2 ?trans1;
FADD R0, R2, R5 &req={2} ?WAIT5_END_GROUP;
STS [R7], R0 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT &req={0} ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans8;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans8;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans8;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans8;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans8;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans8;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.NE.AND P0, PT, R6, RZ, PT ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LDS R5, [UR4] &wr=0x0 ?trans1;
LDC.64 R2, c[0x0][0x388] &wr=0x2 ?trans2;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R5 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x240;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void cuda_asum_flt<1u>(float*, float*)
_Z13cuda_asum_fltILj1EEvPfS0_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s5
v_lshl_add_u32 v1, s6, 1, v0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s5, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v1, v[1:2], off
v_lshl_add_u32 v2, v0, 2, 0
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v3, v1
ds_store_b32 v2, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 64, v0
s_cbranch_execz .LBB20_2
s_barrier
buffer_gl0_inv
s_barrier
buffer_gl0_inv
s_barrier
buffer_gl0_inv
s_barrier
buffer_gl0_inv
s_barrier
buffer_gl0_inv
s_barrier
buffer_gl0_inv
s_barrier
buffer_gl0_inv
.LBB20_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB20_4
v_mov_b32_e32 v0, 0
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[4:5], 2
s_add_u32 s0, s2, s0
ds_load_b32 v1, v0
s_addc_u32 s1, s3, s1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB20_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| void_cuda_asum_flt_1u_ | 850 | 903 | stackv2-00000-of-00015 |
// Demangled: void cuda_asum_flt<256u>(float*, float*)
Function : _Z13cuda_asum_fltILj256EEvPfS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R9, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x2 ?trans6;
LDC.64 R4, c[0x0][0x380] &wr=0x3 ?trans1;
S2R R0, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x4 ?trans1;
UIADD3 UR4, UPT, UPT, UR5, UR5, URZ &req={2} ?WAIT6_END_GROUP;
IMAD R3, R0, UR4, R9 &req={1} ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R3.reuse, UR5, RZ ?trans1;
IMAD.WIDE.U32 R2, R3, 0x4, R4 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x4, R4 ?trans2;
LDG.E R2, desc[UR6][R2.64] &req={4} &wr=0x2 ?trans4;
LDG.E R5, desc[UR6][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GT.U32.AND P0, PT, R9.reuse, 0x7f, PT ?trans1;
ISETP.GT.U32.AND P1, PT, R9, 0x3f, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R7, R9, UR4, 0x2 ?trans1;
FADD R6, R2, R5 &req={2} ?WAIT5_END_GROUP;
STS [R7], R6 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 LDS R8, [R7+0x200] ?trans4;
@!P0 LDS R3, [R7] &wr=0x1 ?trans2;
@!P0 FADD R8, R8, R3 &req={1} ?WAIT5_END_GROUP;
@!P0 STS [R7], R8 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P1 EXIT &req={0} ?trans5;
LDS R2, [R7+0x100] ?trans1;
ISETP.NE.AND P0, PT, R9, RZ, PT ?WAIT3_END_GROUP;
LDS R3, [R7] &wr=0x0 ?trans2;
FADD R2, R2, R3 &req={0} ?WAIT5_END_GROUP;
STS [R7], R2 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R3, [R7+0x80] ?trans4;
LDS R4, [R7] &wr=0x0 ?trans2;
FADD R4, R3, R4 &req={0} ?WAIT5_END_GROUP;
STS [R7], R4 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R3, [R7+0x40] ?trans4;
LDS R6, [R7] &wr=0x0 ?trans2;
FADD R6, R3, R6 &req={0} ?WAIT5_END_GROUP;
STS [R7], R6 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R2, [R7+0x20] ?trans4;
LDS R3, [R7] &wr=0x0 ?trans2;
FADD R2, R2, R3 &req={0} ?WAIT5_END_GROUP;
STS [R7], R2 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R3, [R7+0x10] ?trans4;
LDS R4, [R7] &wr=0x0 ?trans2;
FADD R4, R3, R4 &req={0} ?WAIT5_END_GROUP;
STS [R7], R4 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R3, [R7+0x8] ?trans4;
LDS R6, [R7] &wr=0x0 ?trans2;
FADD R6, R3, R6 &req={0} ?WAIT5_END_GROUP;
STS [R7], R6 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R2, [R7+0x4] ?trans4;
LDS R3, [R7] &wr=0x0 ?trans2;
FADD R2, R2, R3 &req={0} ?WAIT5_END_GROUP;
STS [R7], R2 &rd=0x0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT ?trans5;
LDS R5, [UR4] &wr=0x2 ?trans1;
LDC.64 R2, c[0x0][0x388] &req={0} &wr=0x0 ?trans2;
IMAD.WIDE.U32 R2, R0, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R5 &req={2} ?trans1;
EXIT ?trans5;
BRA 0x460;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void cuda_asum_flt<256u>(float*, float*)
_Z13cuda_asum_fltILj256EEvPfS0_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s5
v_lshl_add_u32 v1, s6, 1, v0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s5, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 0x80, v0
s_cbranch_execz .LBB12_2
ds_load_2addr_stride64_b32 v[2:3], v1 offset1:2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
.LBB12_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 64, v0
s_cbranch_execz .LBB12_4
ds_load_b32 v2, v1 offset:256
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:32
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:16
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:8
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB12_4:
s_or_b32 exec_lo, exec_lo, s0
s_mov_b32 s5, 0
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB12_6
v_mov_b32_e32 v0, 0
s_lshl_b64 s[0:1], s[4:5], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB12_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| void_cuda_asum_flt_256u_ | 1,470 | 1,523 | stackv2-00000-of-00015 |
// Demangled: void cuda_asum_flt<2u>(float*, float*)
Function : _Z13cuda_asum_fltILj2EEvPfS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R6, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x2 ?trans6;
LDC.64 R4, c[0x0][0x380] &wr=0x3 ?trans1;
S2R R9, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x4 ?trans1;
UIADD3 UR4, UPT, UPT, UR5, UR5, URZ &req={2} ?WAIT6_END_GROUP;
IMAD R3, R9, UR4, R6 &req={1} ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R3.reuse, UR5, RZ ?trans1;
IMAD.WIDE.U32 R2, R3, 0x4, R4 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x4, R4 ?trans2;
LDG.E R2, desc[UR6][R2.64] &req={4} &wr=0x2 ?trans4;
LDG.E R5, desc[UR6][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GT.U32.AND P0, PT, R6, 0x3f, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R7, R6, UR4, 0x2 ?trans1;
FADD R0, R2, R5 &req={2} ?WAIT5_END_GROUP;
STS [R7], R0 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT &req={0} ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans8;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans8;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans8;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans8;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans8;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.NE.AND P0, PT, R6, RZ, PT ?WAIT5_END_GROUP;
LDS R0, [R7+0x4] &req={1} ?trans4;
LDS R3, [R7] &wr=0x0 ?trans2;
FADD R0, R0, R3 &req={0} ?WAIT5_END_GROUP;
STS [R7], R0 &rd=0x0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT ?trans5;
LDS R5, [UR4] &wr=0x1 ?trans1;
LDC.64 R2, c[0x0][0x388] &wr=0x2 ?trans2;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R5 &req={1} ?trans1;
EXIT ?trans5;
BRA 0x280;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void cuda_asum_flt<2u>(float*, float*)
_Z13cuda_asum_fltILj2EEvPfS0_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s5
v_lshl_add_u32 v1, s6, 1, v0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s5, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 64, v0
s_cbranch_execz .LBB19_2
s_barrier
buffer_gl0_inv
s_barrier
buffer_gl0_inv
s_barrier
buffer_gl0_inv
s_barrier
buffer_gl0_inv
s_barrier
buffer_gl0_inv
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB19_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB19_4
v_mov_b32_e32 v0, 0
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[4:5], 2
s_add_u32 s0, s2, s0
ds_load_b32 v1, v0
s_addc_u32 s1, s3, s1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB19_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| void_cuda_asum_flt_2u_ | 936 | 972 | stackv2-00000-of-00015 |
// Demangled: void cuda_asum_flt<32u>(float*, float*)
Function : _Z13cuda_asum_fltILj32EEvPfS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R6, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x2 ?trans6;
LDC.64 R4, c[0x0][0x380] &wr=0x3 ?trans1;
S2R R9, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x4 ?trans1;
UIADD3 UR4, UPT, UPT, UR5, UR5, URZ &req={2} ?WAIT6_END_GROUP;
IMAD R3, R9, UR4, R6 &req={1} ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R3.reuse, UR5, RZ ?trans1;
IMAD.WIDE.U32 R2, R3, 0x4, R4 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x4, R4 ?trans2;
LDG.E R2, desc[UR6][R2.64] &req={4} &wr=0x2 ?trans4;
LDG.E R5, desc[UR6][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GT.U32.AND P0, PT, R6, 0x3f, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R7, R6, UR4, 0x2 ?trans1;
FADD R0, R2, R5 &req={2} ?WAIT5_END_GROUP;
STS [R7], R0 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT &req={0} ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans8;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.NE.AND P0, PT, R6, RZ, PT ?WAIT5_END_GROUP;
LDS R0, [R7+0x40] &req={1} ?trans4;
LDS R3, [R7] &wr=0x0 ?trans2;
FADD R0, R0, R3 &req={0} ?WAIT5_END_GROUP;
STS [R7], R0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R2, [R7+0x20] ?trans4;
LDS R3, [R7] &wr=0x0 ?trans2;
FADD R2, R2, R3 &req={0} ?WAIT5_END_GROUP;
STS [R7], R2 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R3, [R7+0x10] ?trans4;
LDS R4, [R7] &wr=0x0 ?trans2;
FADD R4, R3, R4 &req={0} ?WAIT5_END_GROUP;
STS [R7], R4 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R0, [R7+0x8] ?trans4;
LDS R3, [R7] &wr=0x0 ?trans2;
FADD R0, R0, R3 &req={0} ?WAIT5_END_GROUP;
STS [R7], R0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R2, [R7+0x4] ?trans4;
LDS R3, [R7] &wr=0x0 ?trans2;
FADD R2, R2, R3 &req={0} ?WAIT5_END_GROUP;
STS [R7], R2 &rd=0x0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT ?trans5;
LDS R5, [UR4] &wr=0x1 ?trans1;
LDC.64 R2, c[0x0][0x388] &req={0} &wr=0x0 ?trans2;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R5 &req={1} ?trans1;
EXIT ?trans5;
BRA 0x380;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void cuda_asum_flt<32u>(float*, float*)
_Z13cuda_asum_fltILj32EEvPfS0_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s5
v_lshl_add_u32 v1, s6, 1, v0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s5, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 64, v0
s_cbranch_execz .LBB15_2
s_barrier
buffer_gl0_inv
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:16
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:8
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB15_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB15_4
v_mov_b32_e32 v0, 0
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[4:5], 2
s_add_u32 s0, s2, s0
ds_load_b32 v1, v0
s_addc_u32 s1, s3, s1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB15_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| void_cuda_asum_flt_32u_ | 1,217 | 1,250 | stackv2-00000-of-00015 |
// Demangled: void cuda_asum_flt<4u>(float*, float*)
Function : _Z13cuda_asum_fltILj4EEvPfS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R6, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x2 ?trans6;
LDC.64 R4, c[0x0][0x380] &wr=0x3 ?trans1;
S2R R9, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x4 ?trans1;
UIADD3 UR4, UPT, UPT, UR5, UR5, URZ &req={2} ?WAIT6_END_GROUP;
IMAD R3, R9, UR4, R6 &req={1} ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R3.reuse, UR5, RZ ?trans1;
IMAD.WIDE.U32 R2, R3, 0x4, R4 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x4, R4 ?trans2;
LDG.E R2, desc[UR6][R2.64] &req={4} &wr=0x2 ?trans4;
LDG.E R5, desc[UR6][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GT.U32.AND P0, PT, R6, 0x3f, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R7, R6, UR4, 0x2 ?trans1;
FADD R0, R2, R5 &req={2} ?WAIT5_END_GROUP;
STS [R7], R0 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT &req={0} ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans8;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans8;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans8;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans8;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.NE.AND P0, PT, R6, RZ, PT ?WAIT5_END_GROUP;
LDS R0, [R7+0x8] &req={1} ?trans4;
LDS R3, [R7] &wr=0x0 ?trans2;
FADD R0, R0, R3 &req={0} ?WAIT5_END_GROUP;
STS [R7], R0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R2, [R7+0x4] ?trans4;
LDS R3, [R7] &wr=0x0 ?trans2;
FADD R2, R2, R3 &req={0} ?WAIT5_END_GROUP;
STS [R7], R2 &rd=0x0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT ?trans5;
LDS R5, [UR4] &wr=0x1 ?trans1;
LDC.64 R2, c[0x0][0x388] &req={0} &wr=0x0 ?trans2;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R5 &req={1} ?trans1;
EXIT ?trans5;
BRA 0x2c0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void cuda_asum_flt<4u>(float*, float*)
_Z13cuda_asum_fltILj4EEvPfS0_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s5
v_lshl_add_u32 v1, s6, 1, v0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s5, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 64, v0
s_cbranch_execz .LBB18_2
s_barrier
buffer_gl0_inv
s_barrier
buffer_gl0_inv
s_barrier
buffer_gl0_inv
s_barrier
buffer_gl0_inv
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB18_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB18_4
v_mov_b32_e32 v0, 0
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[4:5], 2
s_add_u32 s0, s2, s0
ds_load_b32 v1, v0
s_addc_u32 s1, s3, s1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB18_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| void_cuda_asum_flt_4u_ | 1,001 | 1,041 | stackv2-00000-of-00015 |
// Demangled: void cuda_asum_flt<512u>(float*, float*)
Function : _Z13cuda_asum_fltILj512EEvPfS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x2 ?trans6;
LDC.64 R6, c[0x0][0x380] &wr=0x3 ?trans1;
S2R R0, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x4 ?trans1;
UIADD3 UR4, UPT, UPT, UR5, UR5, URZ &req={2} ?WAIT6_END_GROUP;
IMAD R5, R0, UR4, R3 &req={1} ?WAIT5_END_GROUP;
IADD3 R9, PT, PT, R5.reuse, UR5, RZ ?trans1;
IMAD.WIDE.U32 R4, R5, 0x4, R6 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R6, R9, 0x4, R6 ?trans2;
LDG.E R4, desc[UR6][R4.64] &req={4} &wr=0x2 ?trans4;
LDG.E R7, desc[UR6][R6.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GT.U32.AND P1, PT, R3.reuse, 0xff, PT ?trans1;
ISETP.GT.U32.AND P0, PT, R3, 0x7f, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R9, R3, UR4, 0x2 ?trans1;
FADD R2, R4, R7 &req={2} ?WAIT5_END_GROUP;
STS [R9], R2 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P1 LDS R8, [R9+0x400] ?trans4;
@!P1 LDS R5, [R9] &wr=0x1 ?trans2;
@!P1 FADD R8, R8, R5 &req={1} ?WAIT5_END_GROUP;
@!P1 STS [R9], R8 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P1, PT, R3, 0x3f, PT ?WAIT5_END_GROUP;
@!P0 LDS R4, [R9+0x200] ?trans4;
@!P0 LDS R5, [R9] &wr=0x1 ?trans2;
@!P0 FADD R4, R4, R5 &req={1} ?WAIT5_END_GROUP;
@!P0 STS [R9], R4 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P1 EXIT &req={0} ?trans5;
LDS R2, [R9+0x100] ?trans1;
ISETP.NE.AND P0, PT, R3, RZ, PT ?WAIT3_END_GROUP;
LDS R5, [R9] &wr=0x0 ?trans2;
FADD R2, R2, R5 &req={0} ?WAIT5_END_GROUP;
STS [R9], R2 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R4, [R9+0x80] &req={1} ?trans4;
LDS R5, [R9] &wr=0x0 ?trans2;
FADD R4, R4, R5 &req={0} ?WAIT5_END_GROUP;
STS [R9], R4 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R5, [R9+0x40] ?trans4;
LDS R6, [R9] &wr=0x0 ?trans2;
FADD R6, R5, R6 &req={0} ?WAIT5_END_GROUP;
STS [R9], R6 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R2, [R9+0x20] ?trans4;
LDS R5, [R9] &wr=0x0 ?trans2;
FADD R2, R2, R5 &req={0} ?WAIT5_END_GROUP;
STS [R9], R2 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R4, [R9+0x10] ?trans4;
LDS R5, [R9] &wr=0x0 ?trans2;
FADD R4, R4, R5 &req={0} ?WAIT5_END_GROUP;
STS [R9], R4 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R5, [R9+0x8] ?trans4;
LDS R6, [R9] &wr=0x0 ?trans2;
FADD R6, R5, R6 &req={0} ?WAIT5_END_GROUP;
STS [R9], R6 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R2, [R9+0x4] ?trans4;
LDS R5, [R9] &wr=0x0 ?trans2;
FADD R2, R2, R5 &req={0} ?WAIT5_END_GROUP;
STS [R9], R2 &rd=0x0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT ?trans5;
LDS R5, [UR4] &wr=0x1 ?trans1;
LDC.64 R2, c[0x0][0x388] &req={0} &wr=0x0 ?trans2;
IMAD.WIDE.U32 R2, R0, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R5 &req={1} ?trans1;
EXIT ?trans5;
BRA 0x4c0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void cuda_asum_flt<512u>(float*, float*)
_Z13cuda_asum_fltILj512EEvPfS0_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s5
v_lshl_add_u32 v1, s6, 1, v0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s5, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 0x100, v0
s_cbranch_execz .LBB11_2
ds_load_2addr_stride64_b32 v[2:3], v1 offset1:4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
.LBB11_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 0x80, v0
s_cbranch_execz .LBB11_4
ds_load_b32 v2, v1 offset:512
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB11_4:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 64, v0
s_cbranch_execz .LBB11_6
ds_load_b32 v2, v1 offset:256
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:32
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:16
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:8
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB11_6:
s_or_b32 exec_lo, exec_lo, s0
s_mov_b32 s5, 0
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB11_8
v_mov_b32_e32 v0, 0
s_lshl_b64 s[0:1], s[4:5], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB11_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| void_cuda_asum_flt_512u_ | 1,607 | 1,685 | stackv2-00000-of-00015 |
// Demangled: void cuda_asum_flt<64u>(float*, float*)
Function : _Z13cuda_asum_fltILj64EEvPfS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R6, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x2 ?trans6;
LDC.64 R4, c[0x0][0x380] &wr=0x3 ?trans1;
S2R R9, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x4 ?trans1;
UIADD3 UR4, UPT, UPT, UR5, UR5, URZ &req={2} ?WAIT6_END_GROUP;
IMAD R3, R9, UR4, R6 &req={1} ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R3.reuse, UR5, RZ ?trans1;
IMAD.WIDE.U32 R2, R3, 0x4, R4 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x4, R4 ?trans2;
LDG.E R2, desc[UR6][R2.64] &req={4} &wr=0x2 ?trans4;
LDG.E R5, desc[UR6][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GT.U32.AND P0, PT, R6, 0x3f, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R7, R6, UR4, 0x2 ?trans1;
FADD R0, R2, R5 &req={2} ?WAIT5_END_GROUP;
STS [R7], R0 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT &req={0} ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.NE.AND P0, PT, R6, RZ, PT ?WAIT5_END_GROUP;
LDS R0, [R7+0x80] &req={1} ?trans4;
LDS R3, [R7] &wr=0x0 ?trans2;
FADD R0, R0, R3 &req={0} ?WAIT5_END_GROUP;
STS [R7], R0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R2, [R7+0x40] ?trans4;
LDS R3, [R7] &wr=0x0 ?trans2;
FADD R2, R2, R3 &req={0} ?WAIT5_END_GROUP;
STS [R7], R2 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R3, [R7+0x20] ?trans4;
LDS R4, [R7] &wr=0x0 ?trans2;
FADD R4, R3, R4 &req={0} ?WAIT5_END_GROUP;
STS [R7], R4 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R0, [R7+0x10] ?trans4;
LDS R3, [R7] &wr=0x0 ?trans2;
FADD R0, R0, R3 &req={0} ?WAIT5_END_GROUP;
STS [R7], R0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R2, [R7+0x8] ?trans4;
LDS R3, [R7] &wr=0x0 ?trans2;
FADD R2, R2, R3 &req={0} ?WAIT5_END_GROUP;
STS [R7], R2 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R3, [R7+0x4] ?trans4;
LDS R4, [R7] &wr=0x0 ?trans2;
FADD R4, R3, R4 &req={0} ?WAIT5_END_GROUP;
STS [R7], R4 &rd=0x0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT ?trans5;
LDS R5, [UR4] &wr=0x1 ?trans1;
LDC.64 R2, c[0x0][0x388] &wr=0x2 ?trans2;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R5 &req={1} ?trans1;
EXIT ?trans5;
BRA 0x3c0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void cuda_asum_flt<64u>(float*, float*)
_Z13cuda_asum_fltILj64EEvPfS0_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s5
v_lshl_add_u32 v1, s6, 1, v0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s5, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 64, v0
s_cbranch_execz .LBB14_2
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:32
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:16
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:8
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB14_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB14_4
v_mov_b32_e32 v0, 0
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[4:5], 2
s_add_u32 s0, s2, s0
ds_load_b32 v1, v0
s_addc_u32 s1, s3, s1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB14_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| void_cuda_asum_flt_64u_ | 1,273 | 1,320 | stackv2-00000-of-00015 |
// Demangled: void cuda_asum_flt<8u>(float*, float*)
Function : _Z13cuda_asum_fltILj8EEvPfS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R6, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x2 ?trans6;
LDC.64 R4, c[0x0][0x380] &wr=0x3 ?trans1;
S2R R9, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x4 ?trans1;
UIADD3 UR4, UPT, UPT, UR5, UR5, URZ &req={2} ?WAIT6_END_GROUP;
IMAD R3, R9, UR4, R6 &req={1} ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R3.reuse, UR5, RZ ?trans1;
IMAD.WIDE.U32 R2, R3, 0x4, R4 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x4, R4 ?trans2;
LDG.E R2, desc[UR6][R2.64] &req={4} &wr=0x2 ?trans4;
LDG.E R5, desc[UR6][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GT.U32.AND P0, PT, R6, 0x3f, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R7, R6, UR4, 0x2 ?trans1;
FADD R0, R2, R5 &req={2} ?WAIT5_END_GROUP;
STS [R7], R0 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT &req={0} ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans8;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans8;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans8;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.NE.AND P0, PT, R6, RZ, PT ?WAIT5_END_GROUP;
LDS R0, [R7+0x10] &req={1} ?trans4;
LDS R3, [R7] &wr=0x0 ?trans2;
FADD R0, R0, R3 &req={0} ?WAIT5_END_GROUP;
STS [R7], R0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R2, [R7+0x8] ?trans4;
LDS R3, [R7] &wr=0x0 ?trans2;
FADD R2, R2, R3 &req={0} ?WAIT5_END_GROUP;
STS [R7], R2 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R3, [R7+0x4] ?trans4;
LDS R4, [R7] &wr=0x0 ?trans2;
FADD R4, R3, R4 &req={0} ?WAIT5_END_GROUP;
STS [R7], R4 &rd=0x0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT ?trans5;
LDS R5, [UR4] &wr=0x1 ?trans1;
LDC.64 R2, c[0x0][0x388] &wr=0x2 ?trans2;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R5 &req={1} ?trans1;
EXIT ?trans5;
BRA 0x300;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void cuda_asum_flt<8u>(float*, float*)
_Z13cuda_asum_fltILj8EEvPfS0_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s5
v_lshl_add_u32 v1, s6, 1, v0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s5, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 64, v0
s_cbranch_execz .LBB17_2
s_barrier
buffer_gl0_inv
s_barrier
buffer_gl0_inv
s_barrier
buffer_gl0_inv
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v1 offset1:1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB17_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB17_4
v_mov_b32_e32 v0, 0
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[4:5], 2
s_add_u32 s0, s2, s0
ds_load_b32 v1, v0
s_addc_u32 s1, s3, s1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB17_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| void_cuda_asum_flt_8u_ | 1,073 | 1,110 | stackv2-00000-of-00015 |
// Demangled: void cuda_asum_int<128u>(int*, int*)
Function : _Z13cuda_asum_intILj128EEvPiS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R8, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x2 ?trans6;
LDC.64 R4, c[0x0][0x380] &wr=0x3 ?trans1;
S2R R11, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x4 ?trans1;
UIADD3 UR4, UPT, UPT, UR5, UR5, URZ &req={2} ?WAIT6_END_GROUP;
IMAD R3, R11, UR4, R8 &req={1} ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R3.reuse, UR5, RZ ?trans1;
IMAD.WIDE.U32 R2, R3, 0x4, R4 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x4, R4 ?trans2;
LDG.E R2, desc[UR6][R2.64] &req={4} &wr=0x2 ?trans4;
LDG.E R5, desc[UR6][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GT.U32.AND P0, PT, R8.reuse, 0x3f, PT ?trans1;
ISETP.GT.U32.AND P1, PT, R8, 0x1f, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R7, R8, UR4, 0x2 ?trans2;
IADD3 R0, PT, PT, R2, R5, RZ &req={2} ?WAIT5_END_GROUP;
STS [R7], R0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 LDS R6, [R7+0x100] ?trans4;
@!P0 LDS R3, [R7] &wr=0x1 ?trans2;
@!P0 IADD3 R6, PT, PT, R6, R3, RZ &req={1} ?WAIT5_END_GROUP;
@!P0 STS [R7], R6 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P1 EXIT &req={0} ?trans5;
LDS R0, [R7+0x80] ?trans1;
ISETP.NE.AND P0, PT, R8, RZ, PT ?WAIT3_END_GROUP;
LDS R3, [R7] ?trans4;
LDS R2, [R7+0x40] &wr=0x0 ?trans4;
LDS R5, [R7+0x20] ?trans4;
LDS R4, [R7+0x10] &wr=0x2 ?trans4;
LDS R9, [R7+0x8] ?trans4;
LDS R6, [R7+0x4] &req={1} &wr=0x1 ?trans1;
IADD3 R0, PT, PT, R2, R3, R0 &req={0} ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R4, R5, R0 &req={2} ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R6, R9, R0 &req={1} ?WAIT5_END_GROUP;
STS [R7], R0 &rd=0x0 ?trans1;
@P0 EXIT ?trans5;
LDS R5, [UR4] &wr=0x1 ?trans1;
LDC.64 R2, c[0x0][0x388] &wr=0x2 ?trans2;
IMAD.WIDE.U32 R2, R11, 0x4, R2 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R5 &req={1} ?trans1;
EXIT ?trans5;
BRA 0x2e0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void cuda_asum_int<128u>(int*, int*)
_Z13cuda_asum_intILj128EEvPiS0_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s5
v_lshl_add_u32 v1, s6, 1, v0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s5, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 64, v0
s_cbranch_execz .LBB2_2
ds_load_2addr_stride64_b32 v[2:3], v1 offset1:1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB2_4
ds_load_b32 v8, v1 offset:128
ds_load_2addr_b32 v[2:3], v1 offset1:1
ds_load_2addr_b32 v[4:5], v1 offset0:8 offset1:16
ds_load_2addr_b32 v[6:7], v1 offset0:2 offset1:4
s_waitcnt lgkmcnt(1)
v_add3_u32 v2, v2, v8, v5
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v2, v4, v2, v7
v_add3_u32 v2, v6, v2, v3
ds_store_b32 v1, v2
.LBB2_4:
s_or_b32 exec_lo, exec_lo, s0
s_mov_b32 s5, 0
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB2_6
v_mov_b32_e32 v0, 0
s_lshl_b64 s[0:1], s[4:5], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB2_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| void_cuda_asum_int_128u_ | 1,135 | 1,174 | stackv2-00000-of-00015 |
// Demangled: void cuda_asum_int<16u>(int*, int*)
Function : _Z13cuda_asum_intILj16EEvPiS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R6, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x2 ?trans6;
LDC.64 R4, c[0x0][0x380] &wr=0x3 ?trans1;
S2R R9, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x4 ?trans1;
UIADD3 UR4, UPT, UPT, UR5, UR5, URZ &req={2} ?WAIT6_END_GROUP;
IMAD R3, R9, UR4, R6 &req={1} ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R3.reuse, UR5, RZ ?trans1;
IMAD.WIDE.U32 R2, R3, 0x4, R4 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x4, R4 ?trans2;
LDG.E R2, desc[UR6][R2.64] &req={4} &wr=0x2 ?trans4;
LDG.E R5, desc[UR6][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GT.U32.AND P0, PT, R6, 0x1f, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R7, R6, UR4, 0x2 ?trans2;
IADD3 R0, PT, PT, R2, R5, RZ &req={2} ?WAIT5_END_GROUP;
STS [R7], R0 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT &req={0} ?trans5;
LDS R0, [R7+0x20] &req={1} ?trans1;
ISETP.NE.AND P0, PT, R6, RZ, PT ?WAIT3_END_GROUP;
LDS R3, [R7] ?trans4;
LDS R2, [R7+0x10] &wr=0x0 ?trans4;
LDS R5, [R7+0x8] ?trans4;
LDS R4, [R7+0x4] &wr=0x1 ?trans1;
IADD3 R0, PT, PT, R2, R3, R0 &req={0} ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R4, R5, R0 &req={1} ?WAIT5_END_GROUP;
STS [R7], R0 &rd=0x0 ?trans1;
@P0 EXIT ?trans5;
LDS R5, [UR4] &wr=0x1 ?trans1;
LDC.64 R2, c[0x0][0x388] &wr=0x2 ?trans2;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R5 &req={1} ?trans1;
EXIT ?trans5;
BRA 0x250;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void cuda_asum_int<16u>(int*, int*)
_Z13cuda_asum_intILj16EEvPiS0_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s5
v_lshl_add_u32 v1, s6, 1, v0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s5, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB5_2
ds_load_2addr_b32 v[2:3], v1 offset0:2 offset1:4
ds_load_b32 v6, v1 offset:32
ds_load_2addr_b32 v[4:5], v1 offset1:1
s_waitcnt lgkmcnt(0)
v_add3_u32 v3, v4, v6, v3
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v2, v2, v3, v5
ds_store_b32 v1, v2
.LBB5_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB5_4
v_mov_b32_e32 v0, 0
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[4:5], 2
s_add_u32 s0, s2, s0
ds_load_b32 v1, v0
s_addc_u32 s1, s3, s1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB5_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| void_cuda_asum_int_16u_ | 924 | 976 | stackv2-00000-of-00015 |
// Demangled: void cuda_asum_int<1u>(int*, int*)
Function : _Z13cuda_asum_intILj1EEvPiS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x2 ?trans6;
LDC.64 R4, c[0x0][0x380] &wr=0x3 ?trans1;
S2R R9, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x4 ?trans1;
UIADD3 UR4, UPT, UPT, UR5, UR5, URZ &req={2} ?WAIT6_END_GROUP;
IMAD R3, R9, UR4, R0 &req={1} ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R3.reuse, UR5, RZ ?trans1;
IMAD.WIDE.U32 R2, R3, 0x4, R4 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x4, R4 ?trans2;
LDG.E R2, desc[UR6][R2.64] &req={4} &wr=0x2 ?trans4;
LDG.E R5, desc[UR6][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.NE.AND P0, PT, R0, RZ, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R7, R0, UR4, 0x2 ?trans2;
IADD3 R0, PT, PT, R2, R5, RZ &req={2} ?WAIT5_END_GROUP;
STS [R7], R0 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT &req={0} ?trans5;
LDS R5, [UR4] &wr=0x0 ?trans1;
LDC.64 R2, c[0x0][0x388] &wr=0x2 ?trans2;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R5 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x1b0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void cuda_asum_int<1u>(int*, int*)
_Z13cuda_asum_intILj1EEvPiS0_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s5
v_lshl_add_u32 v1, s6, 1, v0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s5, v1
s_mov_b32 s5, 0
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_clause 0x1
global_load_b32 v1, v[3:4], off
global_load_b32 v3, v[5:6], off
v_lshl_add_u32 v4, v0, 2, 0
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v3, v1
ds_store_b32 v4, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB9_2
ds_load_b32 v0, v2
s_mov_b32 s4, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[4:5], 2
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
s_waitcnt lgkmcnt(0)
global_store_b32 v2, v0, s[0:1]
.LBB9_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| void_cuda_asum_int_1u_ | 714 | 754 | stackv2-00000-of-00015 |
// Demangled: void cuda_asum_int<256u>(int*, int*)
Function : _Z13cuda_asum_intILj256EEvPiS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R8, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x2 ?trans6;
LDC.64 R4, c[0x0][0x380] &wr=0x3 ?trans1;
S2R R11, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x4 ?trans1;
UIADD3 UR4, UPT, UPT, UR5, UR5, URZ &req={2} ?WAIT6_END_GROUP;
IMAD R3, R11, UR4, R8 &req={1} ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R3.reuse, UR5, RZ ?trans1;
IMAD.WIDE.U32 R2, R3, 0x4, R4 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x4, R4 ?trans2;
LDG.E R2, desc[UR6][R2.64] &req={4} &wr=0x2 ?trans4;
LDG.E R5, desc[UR6][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GT.U32.AND P1, PT, R8.reuse, 0x7f, PT ?trans1;
ISETP.GT.U32.AND P0, PT, R8, 0x3f, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R7, R8, UR4, 0x2 ?trans2;
IADD3 R0, PT, PT, R2, R5, RZ &req={2} ?WAIT5_END_GROUP;
STS [R7], R0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P1 LDS R6, [R7+0x200] ?trans4;
@!P1 LDS R3, [R7] &wr=0x1 ?trans2;
@!P1 IADD3 R6, PT, PT, R6, R3, RZ &req={1} ?WAIT5_END_GROUP;
@!P1 STS [R7], R6 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P1, PT, R8, 0x1f, PT ?WAIT5_END_GROUP;
@!P0 LDS R2, [R7+0x100] ?trans4;
@!P0 LDS R3, [R7] &wr=0x1 ?trans2;
@!P0 IADD3 R2, PT, PT, R2, R3, RZ &req={1} ?WAIT5_END_GROUP;
@!P0 STS [R7], R2 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P1 EXIT &req={0} ?trans5;
LDS R0, [R7+0x80] ?trans1;
ISETP.NE.AND P0, PT, R8, RZ, PT ?WAIT3_END_GROUP;
LDS R3, [R7] ?trans4;
LDS R2, [R7+0x40] &req={1} &wr=0x0 ?trans4;
LDS R5, [R7+0x20] ?trans4;
LDS R4, [R7+0x10] &wr=0x1 ?trans4;
LDS R9, [R7+0x8] ?trans4;
LDS R6, [R7+0x4] &wr=0x2 ?trans1;
IADD3 R0, PT, PT, R2, R3, R0 &req={0} ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R4, R5, R0 &req={1} ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R6, R9, R0 &req={2} ?WAIT5_END_GROUP;
STS [R7], R0 &rd=0x0 ?trans1;
@P0 EXIT ?trans5;
LDS R5, [UR4] &wr=0x1 ?trans1;
LDC.64 R2, c[0x0][0x388] &wr=0x2 ?trans2;
IMAD.WIDE.U32 R2, R11, 0x4, R2 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R5 &req={1} ?trans1;
EXIT ?trans5;
BRA 0x340;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void cuda_asum_int<256u>(int*, int*)
_Z13cuda_asum_intILj256EEvPiS0_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s5
v_lshl_add_u32 v1, s6, 1, v0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s5, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 0x80, v0
s_cbranch_execz .LBB1_2
ds_load_2addr_stride64_b32 v[2:3], v1 offset1:2
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 64, v0
s_cbranch_execz .LBB1_4
ds_load_b32 v2, v1 offset:256
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB1_6
ds_load_b32 v8, v1 offset:128
ds_load_2addr_b32 v[2:3], v1 offset1:1
ds_load_2addr_b32 v[4:5], v1 offset0:8 offset1:16
ds_load_2addr_b32 v[6:7], v1 offset0:2 offset1:4
s_waitcnt lgkmcnt(1)
v_add3_u32 v2, v2, v8, v5
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v2, v4, v2, v7
v_add3_u32 v2, v6, v2, v3
ds_store_b32 v1, v2
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s0
s_mov_b32 s5, 0
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_8
v_mov_b32_e32 v0, 0
s_lshl_b64 s[0:1], s[4:5], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB1_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| void_cuda_asum_int_256u_ | 1,277 | 1,334 | stackv2-00000-of-00015 |
// Demangled: void cuda_asum_int<2u>(int*, int*)
Function : _Z13cuda_asum_intILj2EEvPiS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R6, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x2 ?trans6;
LDC.64 R4, c[0x0][0x380] &wr=0x3 ?trans1;
S2R R9, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x4 ?trans1;
UIADD3 UR4, UPT, UPT, UR5, UR5, URZ &req={2} ?WAIT6_END_GROUP;
IMAD R3, R9, UR4, R6 &req={1} ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R3.reuse, UR5, RZ ?trans1;
IMAD.WIDE.U32 R2, R3, 0x4, R4 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x4, R4 ?trans2;
LDG.E R2, desc[UR6][R2.64] &req={4} &wr=0x2 ?trans4;
LDG.E R5, desc[UR6][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GT.U32.AND P0, PT, R6, 0x1f, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R7, R6, UR4, 0x2 ?trans2;
IADD3 R0, PT, PT, R2, R5, RZ &req={2} ?WAIT5_END_GROUP;
STS [R7], R0 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT &req={0} ?trans5;
LDS R0, [R7+0x4] &req={1} ?trans1;
ISETP.NE.AND P0, PT, R6, RZ, PT ?WAIT3_END_GROUP;
LDS R3, [R7] &wr=0x0 ?trans2;
IADD3 R0, PT, PT, R0, R3, RZ &req={0} ?WAIT5_END_GROUP;
STS [R7], R0 &rd=0x0 ?trans3;
@P0 EXIT ?trans5;
LDS R5, [UR4] &wr=0x1 ?trans1;
LDC.64 R2, c[0x0][0x388] &wr=0x2 ?trans2;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R5 &req={1} ?trans1;
EXIT ?trans5;
BRA 0x210;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void cuda_asum_int<2u>(int*, int*)
_Z13cuda_asum_intILj2EEvPiS0_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s5
v_lshl_add_u32 v1, s6, 1, v0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s5, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB8_2
ds_load_2addr_b32 v[2:3], v1 offset1:1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB8_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB8_4
v_mov_b32_e32 v0, 0
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[4:5], 2
s_add_u32 s0, s2, s0
ds_load_b32 v1, v0
s_addc_u32 s1, s3, s1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB8_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| void_cuda_asum_int_2u_ | 843 | 902 | stackv2-00000-of-00015 |
// Demangled: void cuda_asum_int<32u>(int*, int*)
Function : _Z13cuda_asum_intILj32EEvPiS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R6, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x2 ?trans6;
LDC.64 R4, c[0x0][0x380] &wr=0x3 ?trans1;
S2R R11, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x4 ?trans1;
UIADD3 UR4, UPT, UPT, UR5, UR5, URZ &req={2} ?WAIT6_END_GROUP;
IMAD R3, R11, UR4, R6 &req={1} ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R3.reuse, UR5, RZ ?trans1;
IMAD.WIDE.U32 R2, R3, 0x4, R4 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x4, R4 ?trans2;
LDG.E R2, desc[UR6][R2.64] &req={4} &wr=0x2 ?trans4;
LDG.E R5, desc[UR6][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GT.U32.AND P0, PT, R6, 0x1f, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R7, R6, UR4, 0x2 ?trans2;
IADD3 R0, PT, PT, R2, R5, RZ &req={2} ?WAIT5_END_GROUP;
STS [R7], R0 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT &req={0} ?trans5;
LDS R0, [R7+0x40] &req={1} ?trans1;
ISETP.NE.AND P0, PT, R6, RZ, PT ?WAIT3_END_GROUP;
LDS R3, [R7] ?trans4;
LDS R2, [R7+0x20] &wr=0x0 ?trans4;
LDS R5, [R7+0x10] ?trans4;
LDS R4, [R7+0x8] &wr=0x1 ?trans4;
LDS R9, [R7+0x4] &wr=0x2 ?trans1;
IADD3 R0, PT, PT, R2, R3, R0 &req={0} ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R4, R5, R0 &req={1} ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R0, R9, RZ &req={2} ?WAIT5_END_GROUP;
STS [R7], R0 &rd=0x0 ?trans1;
@P0 EXIT ?trans5;
LDS R5, [UR4] &wr=0x1 ?trans1;
LDC.64 R2, c[0x0][0x388] &wr=0x2 ?trans2;
IMAD.WIDE.U32 R2, R11, 0x4, R2 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R5 &req={1} ?trans1;
EXIT ?trans5;
BRA 0x270;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void cuda_asum_int<32u>(int*, int*)
_Z13cuda_asum_intILj32EEvPiS0_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s5
v_lshl_add_u32 v1, s6, 1, v0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s5, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB4_2
ds_load_2addr_b32 v[2:3], v1 offset0:8 offset1:16
ds_load_2addr_b32 v[4:5], v1 offset1:1
ds_load_2addr_b32 v[6:7], v1 offset0:2 offset1:4
s_waitcnt lgkmcnt(1)
v_add_nc_u32_e32 v3, v4, v3
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v2, v2, v3, v7
v_add3_u32 v2, v6, v2, v5
ds_store_b32 v1, v2
.LBB4_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB4_4
v_mov_b32_e32 v0, 0
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[4:5], 2
s_add_u32 s0, s2, s0
ds_load_b32 v1, v0
s_addc_u32 s1, s3, s1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB4_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| void_cuda_asum_int_32u_ | 976 | 1,033 | stackv2-00000-of-00015 |
// Demangled: void cuda_asum_int<4u>(int*, int*)
Function : _Z13cuda_asum_intILj4EEvPiS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R6, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x2 ?trans6;
LDC.64 R4, c[0x0][0x380] &wr=0x3 ?trans1;
S2R R9, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x4 ?trans1;
UIADD3 UR4, UPT, UPT, UR5, UR5, URZ &req={2} ?WAIT6_END_GROUP;
IMAD R3, R9, UR4, R6 &req={1} ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R3.reuse, UR5, RZ ?trans1;
IMAD.WIDE.U32 R2, R3, 0x4, R4 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x4, R4 ?trans2;
LDG.E R2, desc[UR6][R2.64] &req={4} &wr=0x2 ?trans4;
LDG.E R5, desc[UR6][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GT.U32.AND P0, PT, R6, 0x1f, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R7, R6, UR4, 0x2 ?trans2;
IADD3 R0, PT, PT, R2, R5, RZ &req={2} ?WAIT5_END_GROUP;
STS [R7], R0 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT &req={0} ?trans5;
LDS R0, [R7+0x8] &req={1} ?trans1;
ISETP.NE.AND P0, PT, R6, RZ, PT ?WAIT3_END_GROUP;
LDS R3, [R7] ?trans4;
LDS R2, [R7+0x4] &wr=0x0 ?trans2;
IADD3 R0, PT, PT, R2, R3, R0 &req={0} ?WAIT5_END_GROUP;
STS [R7], R0 &rd=0x0 ?trans1;
@P0 EXIT ?trans5;
LDS R5, [UR4] &wr=0x1 ?trans1;
LDC.64 R2, c[0x0][0x388] &wr=0x2 ?trans2;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R5 &req={1} ?trans1;
EXIT ?trans5;
BRA 0x220;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void cuda_asum_int<4u>(int*, int*)
_Z13cuda_asum_intILj4EEvPiS0_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s5
v_lshl_add_u32 v1, s6, 1, v0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s5, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB7_2
ds_load_b32 v4, v1 offset:8
ds_load_2addr_b32 v[2:3], v1 offset1:1
s_waitcnt lgkmcnt(0)
v_add3_u32 v2, v2, v4, v3
ds_store_b32 v1, v2
.LBB7_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB7_4
v_mov_b32_e32 v0, 0
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[4:5], 2
s_add_u32 s0, s2, s0
ds_load_b32 v1, v0
s_addc_u32 s1, s3, s1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB7_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| void_cuda_asum_int_4u_ | 858 | 916 | stackv2-00000-of-00015 |
// Demangled: void cuda_asum_int<512u>(int*, int*)
Function : _Z13cuda_asum_intILj512EEvPiS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R8, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x2 ?trans6;
LDC.64 R4, c[0x0][0x380] &wr=0x3 ?trans1;
S2R R11, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x4 ?trans1;
UIADD3 UR4, UPT, UPT, UR5, UR5, URZ &req={2} ?WAIT6_END_GROUP;
IMAD R3, R11, UR4, R8 &req={1} ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R3.reuse, UR5, RZ ?trans1;
IMAD.WIDE.U32 R2, R3, 0x4, R4 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x4, R4 ?trans2;
LDG.E R2, desc[UR6][R2.64] &req={4} &wr=0x2 ?trans4;
LDG.E R5, desc[UR6][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GT.U32.AND P1, PT, R8.reuse, 0xff, PT ?trans1;
ISETP.GT.U32.AND P0, PT, R8, 0x7f, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R7, R8, UR4, 0x2 ?trans2;
IADD3 R0, PT, PT, R2, R5, RZ &req={2} ?WAIT5_END_GROUP;
STS [R7], R0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P1 LDS R6, [R7+0x400] ?trans4;
@!P1 LDS R3, [R7] &wr=0x1 ?trans2;
@!P1 IADD3 R6, PT, PT, R6, R3, RZ &req={1} ?WAIT5_END_GROUP;
@!P1 STS [R7], R6 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P1, PT, R8, 0x3f, PT ?WAIT5_END_GROUP;
@!P0 LDS R2, [R7+0x200] ?trans4;
@!P0 LDS R3, [R7] &wr=0x1 ?trans2;
@!P0 IADD3 R2, PT, PT, R2, R3, RZ &req={1} ?WAIT5_END_GROUP;
@!P0 STS [R7], R2 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P0, PT, R8, 0x1f, PT ?WAIT5_END_GROUP;
@!P1 LDS R0, [R7+0x100] ?trans4;
@!P1 LDS R3, [R7] &wr=0x1 ?trans2;
@!P1 IADD3 R0, PT, PT, R0, R3, RZ &req={1} ?WAIT5_END_GROUP;
@!P1 STS [R7], R0 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT &req={0} ?trans5;
LDS R0, [R7+0x80] &req={1} ?trans1;
ISETP.NE.AND P0, PT, R8, RZ, PT ?WAIT3_END_GROUP;
LDS R3, [R7] ?trans4;
LDS R2, [R7+0x40] &wr=0x0 ?trans4;
LDS R5, [R7+0x20] ?trans4;
LDS R4, [R7+0x10] &wr=0x1 ?trans4;
LDS R9, [R7+0x8] ?trans4;
LDS R6, [R7+0x4] &wr=0x2 ?trans1;
IADD3 R0, PT, PT, R2, R3, R0 &req={0} ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R4, R5, R0 &req={1} ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R6, R9, R0 &req={2} ?WAIT5_END_GROUP;
STS [R7], R0 &rd=0x0 ?trans1;
@P0 EXIT ?trans5;
LDS R5, [UR4] &wr=0x1 ?trans1;
LDC.64 R2, c[0x0][0x388] &wr=0x2 ?trans2;
IMAD.WIDE.U32 R2, R11, 0x4, R2 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R5 &req={1} ?trans1;
EXIT ?trans5;
BRA 0x3a0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void cuda_asum_int<512u>(int*, int*)
_Z13cuda_asum_intILj512EEvPiS0_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s5
v_lshl_add_u32 v1, s6, 1, v0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s5, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 0x100, v0
s_cbranch_execz .LBB0_2
ds_load_2addr_stride64_b32 v[2:3], v1 offset1:4
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 0x80, v0
s_cbranch_execz .LBB0_4
ds_load_b32 v2, v1 offset:512
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 64, v0
s_cbranch_execz .LBB0_6
ds_load_b32 v2, v1 offset:256
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB0_8
ds_load_b32 v8, v1 offset:128
ds_load_2addr_b32 v[2:3], v1 offset1:1
ds_load_2addr_b32 v[4:5], v1 offset0:8 offset1:16
ds_load_2addr_b32 v[6:7], v1 offset0:2 offset1:4
s_waitcnt lgkmcnt(1)
v_add3_u32 v2, v2, v8, v5
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v2, v4, v2, v7
v_add3_u32 v2, v6, v2, v3
ds_store_b32 v1, v2
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s0
s_mov_b32 s5, 0
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_10
v_mov_b32_e32 v0, 0
s_lshl_b64 s[0:1], s[4:5], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| void_cuda_asum_int_512u_ | 1,417 | 1,497 | stackv2-00000-of-00015 |
// Demangled: void cuda_asum_int<64u>(int*, int*)
Function : _Z13cuda_asum_intILj64EEvPiS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R8, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x2 ?trans6;
LDC.64 R4, c[0x0][0x380] &wr=0x3 ?trans1;
S2R R11, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x4 ?trans1;
UIADD3 UR4, UPT, UPT, UR5, UR5, URZ &req={2} ?WAIT6_END_GROUP;
IMAD R3, R11, UR4, R8 &req={1} ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R3.reuse, UR5, RZ ?trans1;
IMAD.WIDE.U32 R2, R3, 0x4, R4 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x4, R4 ?trans2;
LDG.E R2, desc[UR6][R2.64] &req={4} &wr=0x2 ?trans4;
LDG.E R5, desc[UR6][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GT.U32.AND P0, PT, R8, 0x1f, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R7, R8, UR4, 0x2 ?trans2;
IADD3 R0, PT, PT, R2, R5, RZ &req={2} ?WAIT5_END_GROUP;
STS [R7], R0 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT &req={0} ?trans5;
LDS R0, [R7+0x80] &req={1} ?trans1;
ISETP.NE.AND P0, PT, R8, RZ, PT ?WAIT3_END_GROUP;
LDS R3, [R7] ?trans4;
LDS R2, [R7+0x40] &wr=0x0 ?trans4;
LDS R5, [R7+0x20] ?trans4;
LDS R4, [R7+0x10] &wr=0x1 ?trans4;
LDS R9, [R7+0x8] ?trans4;
LDS R6, [R7+0x4] &wr=0x2 ?trans1;
IADD3 R0, PT, PT, R2, R3, R0 &req={0} ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R4, R5, R0 &req={1} ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R6, R9, R0 &req={2} ?WAIT5_END_GROUP;
STS [R7], R0 &rd=0x0 ?trans1;
@P0 EXIT ?trans5;
LDS R5, [UR4] &wr=0x1 ?trans1;
LDC.64 R2, c[0x0][0x388] &wr=0x2 ?trans2;
IMAD.WIDE.U32 R2, R11, 0x4, R2 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R5 &req={1} ?trans1;
EXIT ?trans5;
BRA 0x280;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void cuda_asum_int<64u>(int*, int*)
_Z13cuda_asum_intILj64EEvPiS0_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s5
v_lshl_add_u32 v1, s6, 1, v0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s5, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB3_2
ds_load_b32 v8, v1 offset:128
ds_load_2addr_b32 v[2:3], v1 offset1:1
ds_load_2addr_b32 v[4:5], v1 offset0:8 offset1:16
ds_load_2addr_b32 v[6:7], v1 offset0:2 offset1:4
s_waitcnt lgkmcnt(1)
v_add3_u32 v2, v2, v8, v5
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v2, v4, v2, v7
v_add3_u32 v2, v6, v2, v3
ds_store_b32 v1, v2
.LBB3_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB3_4
v_mov_b32_e32 v0, 0
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[4:5], 2
s_add_u32 s0, s2, s0
ds_load_b32 v1, v0
s_addc_u32 s1, s3, s1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB3_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| void_cuda_asum_int_64u_ | 1,008 | 1,049 | stackv2-00000-of-00015 |
// Demangled: void cuda_asum_int<8u>(int*, int*)
Function : _Z13cuda_asum_intILj8EEvPiS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R6, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x2 ?trans6;
LDC.64 R4, c[0x0][0x380] &wr=0x3 ?trans1;
S2R R9, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x4 ?trans1;
UIADD3 UR4, UPT, UPT, UR5, UR5, URZ &req={2} ?WAIT6_END_GROUP;
IMAD R3, R9, UR4, R6 &req={1} ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R3.reuse, UR5, RZ ?trans1;
IMAD.WIDE.U32 R2, R3, 0x4, R4 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x4, R4 ?trans2;
LDG.E R2, desc[UR6][R2.64] &req={4} &wr=0x2 ?trans4;
LDG.E R5, desc[UR6][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GT.U32.AND P0, PT, R6, 0x1f, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R7, R6, UR4, 0x2 ?trans2;
IADD3 R0, PT, PT, R2, R5, RZ &req={2} ?WAIT5_END_GROUP;
STS [R7], R0 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT &req={0} ?trans5;
LDS R0, [R7+0x10] &req={1} ?trans1;
ISETP.NE.AND P0, PT, R6, RZ, PT ?WAIT3_END_GROUP;
LDS R3, [R7] ?trans4;
LDS R2, [R7+0x8] &wr=0x0 ?trans4;
LDS R5, [R7+0x4] &wr=0x1 ?trans1;
IADD3 R0, PT, PT, R2, R3, R0 &req={0} ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R0, R5, RZ &req={1} ?WAIT5_END_GROUP;
STS [R7], R0 &rd=0x0 ?trans1;
@P0 EXIT ?trans5;
LDS R5, [UR4] &wr=0x1 ?trans1;
LDC.64 R2, c[0x0][0x388] &wr=0x2 ?trans2;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R5 &req={1} ?trans1;
EXIT ?trans5;
BRA 0x240;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void cuda_asum_int<8u>(int*, int*)
_Z13cuda_asum_intILj8EEvPiS0_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s5
v_lshl_add_u32 v1, s6, 1, v0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s5, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB6_2
ds_load_2addr_b32 v[2:3], v1 offset0:2 offset1:4
ds_load_2addr_b32 v[4:5], v1 offset1:1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v2, v2, v3, v5
ds_store_b32 v1, v2
.LBB6_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB6_4
v_mov_b32_e32 v0, 0
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[4:5], 2
s_add_u32 s0, s2, s0
ds_load_b32 v1, v0
s_addc_u32 s1, s3, s1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB6_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| void_cuda_asum_int_8u_ | 907 | 960 | stackv2-00000-of-00015 |
// Demangled: multiply(int, int, char*, char*, int*)
Function : _Z8multiplyiiPcS_Pi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R7, SR_TID.Y &wr=0x1 ?trans7;
LDC R2, c[0x0][0x360] &wr=0x2 ?trans1;
S2R R3, SR_TID.X &wr=0x2 ?trans7;
S2UR UR5, SR_CTAID.Y &wr=0x1 ?trans8;
LDC R6, c[0x0][0x364] &wr=0x1 ?trans8;
S2UR UR4, SR_CTAID.X &wr=0x2 ?trans8;
LDC.64 R12, c[0x0][0x380] &wr=0x3 ?trans1;
IMAD R6, R6, UR5, R7 &req={1} ?WAIT2_END_GROUP;
IMAD R2, R2, UR4, R3 &req={2} ?WAIT3_END_GROUP;
ISETP.GE.AND P0, PT, R6, R13, PT &req={3} ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R2, R12, P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R8, c[0x0][0x390] &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x388] &wr=0x1 ?trans1;
SHF.R.S32.HI R3, RZ, 0x1f, R2 ?trans1;
HFMA2 R7, -RZ, RZ, 0, 0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans4;
LDC.64 R10, c[0x0][0x398] &wr=0x3 ?trans1;
IADD.64 R4, R2, UR6 &req={1} ?trans2;
IADD.64 R8, R6, R8 &req={0} ?WAIT5_END_GROUP;
LDG.E.S8 R4, desc[UR4][R4.64] &req={2} &wr=0x2 ?trans4;
LDG.E.S8 R8, desc[UR4][R8.64] &wr=0x4 ?trans1;
IADD3 R2, PT, PT, -R2, R12, -R6 ?WAIT4_END_GROUP;
IADD3 R3, PT, PT, R2, -0x2, R13 ?WAIT5_END_GROUP;
IMAD.WIDE R2, R3, 0x4, R10 &req={3} ?trans1;
IADD3 R0, PT, PT, R4, -0x30, RZ &req={2} ?trans2;
IADD3 R7, PT, PT, R8, -0x30, RZ &req={4} ?WAIT5_END_GROUP;
IMAD R7, R0, R7, RZ ?WAIT5_END_GROUP;
REDG.E.ADD.STRONG.GPU desc[UR4][R2.64], R7 ?trans1;
EXIT ?trans5;
BRA 0x1f0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: multiply(int, int, char*, char*, int*)
_Z8multiplyiiPcS_Pi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v0
v_cmp_gt_i32_e64 s2, s5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x18
v_ashrrev_i32_e32 v3, 31, v0
v_ashrrev_i32_e32 v5, 31, v1
s_add_i32 s2, s4, s5
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s10, v1
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
v_add_nc_u32_e32 v0, v0, v1
global_load_i8 v2, v[2:3], off
global_load_i8 v3, v[4:5], off
v_sub_nc_u32_e32 v0, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, -2, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(1)
v_subrev_nc_u32_e32 v2, 48, v2
s_waitcnt vmcnt(0)
v_subrev_nc_u32_e32 v3, 48, v3
v_mul_i32_i24_e32 v2, v3, v2
global_atomic_add_u32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| multiply | 845 | 980 | stackv2-00001-of-00015 |
// Demangled: vecAdd(float*, float*, float*, int)
Function : _Z6vecAddPfS_S_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x398] &wr=0x2 ?trans7;
LDC R9, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R9, R9, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R9, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x4 ?trans1;
IMAD.WIDE.U32 R4, R9, 0x4, R4 &req={2} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR4][R4.64] &wr=0x4 ?trans1;
IMAD.WIDE.U32 R6, R9, 0x4, R6 &req={3} ?WAIT4_END_GROUP;
FADD R9, R2, R5 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x140;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: vecAdd(float*, float*, float*, int)
_Z6vecAddPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| vecAdd | 579 | 569 | stackv2-00001-of-00015 |
// Demangled: collatz(long, long, long, int*)
Function : _Z7collatzlllPi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R4, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x394] &wr=0x2 ?trans1;
HFMA2 R5, -RZ, RZ, 0, 0 ?trans1;
BSSY.RECONVERGENT B0, 0x260 ?trans1;
LDCU.64 UR6, c[0x0][0x380] &wr=0x3 ?trans4;
LDC R3, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD.WIDE.U32 R4, R3, UR4, R4 &req={1} ?WAIT5_END_GROUP;
LOP3.LUT R0, R5.reuse, UR5, RZ, 0xfc, !PT &req={2} ?trans1;
IADD.64 R2, R4, UR6 &req={3} ?WAIT4_END_GROUP;
ISETP.NE.U32.AND P0, PT, R0, RZ, PT ?WAIT13_END_GROUP;
@P0 BRA 0x220 &req={0} ?trans5;
LDCU UR5, c[0x0][0x390] &wr=0x0 ?trans1;
MOV R6, RZ ?trans1;
UI2F.U32.RP UR4, UR5 &req={0} ?trans2;
ISETP.NE.U32.AND P1, PT, RZ, UR5, PT ?WAIT7_END_GROUP;
MUFU.RCP R0, UR4 &wr=0x0 ?trans2;
IADD3 R0, PT, PT, R0, 0xffffffe, RZ &req={0} ?WAIT4_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R7, R0 &wr=0x0 ?trans2;
IADD3 R5, PT, PT, RZ, -R7, RZ &req={0} ?WAIT5_END_GROUP;
IMAD R5, R5, UR5, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R7, R7, R5, R6 ?trans1;
MOV R5, RZ ?WAIT5_END_GROUP;
IMAD.HI.U32 R7, R7, R4, RZ ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, -R7, RZ, RZ ?WAIT5_END_GROUP;
IMAD R4, R7, UR5, R4 ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R4, UR5, PT ?WAIT13_END_GROUP;
@P0 IADD3 R4, PT, PT, R4, -UR5, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R4, UR5, PT ?WAIT13_END_GROUP;
@P0 IADD3 R4, PT, PT, R4, -UR5, RZ ?trans2;
@!P1 LOP3.LUT R4, RZ, UR5, RZ, 0x33, !PT ?WAIT5_END_GROUP;
ISETP.NE.S64.AND P0, PT, R4, RZ, PT ?trans2;
BRA 0x250 ?WAIT12_END_GROUP;
MOV R0, 0x240 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x4a0 ?trans5;
ISETP.NE.S64.AND P0, PT, R4, RZ, PT ?WAIT14_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
LDCU.64 UR4, c[0x0][0x388] &wr=0x0 ?trans2;
ISETP.GE.S64.OR P0, PT, R2, UR4, P0 &req={0} ?WAIT14_END_GROUP;
@P0 EXIT ?trans5;
S2R R8, SR_LANEID &wr=0x0 ?trans1;
ISETP.NE.S64.AND P0, PT, R2, 0x1, PT ?trans2;
BSSY.RECONVERGENT B0, 0x410 ?trans1;
MOV R0, 0x1 ?WAIT11_END_GROUP;
@!P0 BRA 0x400 ?trans5;
HFMA2 R0, -RZ, RZ, 0, 5.9604644775390625e-08 ?WAIT7_END_GROUP;
LOP3.LUT R4, R2, 0x1, RZ, 0xc0, !PT ?trans1;
MOV R5, RZ ?trans1;
MOV R6, R3 ?trans1;
MOV R7, R2 ?trans1;
IADD3 R0, PT, PT, R0, 0x1, RZ ?trans2;
ISETP.NE.U64.AND P0, PT, R4, 0x1, PT ?WAIT14_END_GROUP;
@!P0 MOV.64 R4, 0x1 ?trans2;
@!P0 IMAD R9, R6, 0x3, RZ ?trans1;
@P0 SHF.R.S64 R2, R2, 0x1, R3 ?WAIT3_END_GROUP;
@!P0 IMAD.WIDE.U32 R4, R7, 0x3, R4 ?trans1;
@P0 SHF.R.S32.HI R7, RZ, 0x1, R3 ?WAIT4_END_GROUP;
@!P0 IADD3 R5, PT, PT, R5, R9, RZ ?trans1;
@P0 MOV R3, R7 ?trans1;
@!P0 MOV R2, R4 ?WAIT3_END_GROUP;
@!P0 MOV R3, R5 ?WAIT5_END_GROUP;
ISETP.NE.S64.AND P0, PT, R2, 0x1, PT ?WAIT14_END_GROUP;
@P0 BRA 0x2f0 ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
REDUX.MAX.S32 UR5, R0 &wr=0x1 ?trans1;
VOTEU.ANY UR4, UPT, PT ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x2 ?trans6;
LDC.64 R2, c[0x0][0x398] &wr=0x2 ?trans1;
UFLO.U32 UR4, UR4 ?WAIT6_END_GROUP;
ISETP.EQ.U32.AND P0, PT, R8, UR4, PT &req={0} ?trans1;
MOV R5, UR5 &req={1} ?WAIT12_END_GROUP;
@P0 REDG.E.MAX.S32.STRONG.GPU desc[UR6][R2.64], R5 &req={2} ?trans1;
EXIT ?trans5;
LDCU.64 UR6, c[0x0][0x390] &wr=0x0 ?trans1;
LDCU.64 UR8, c[0x0][0x390] &wr=0x1 ?trans1;
UIADD3 UR4, UP0, UPT, URZ, -UR6, URZ &req={0} ?WAIT4_END_GROUP;
UIADD3.X UR5, UPT, UPT, URZ, ~UR7, URZ, UP0, !UPT ?trans1;
UISETP.GE.AND UP0, UPT, UR7, URZ, UPT ?WAIT4_END_GROUP;
USEL.64 UR4, UR4, UR8, !UP0 &req={1} ?WAIT9_END_GROUP;
I2F.U64.RP R10, UR4 &wr=0x0 ?trans2;
MUFU.RCP R10, R10 &req={0} &wr=0x0 ?trans2;
IADD3 R6, PT, PT, R10, 0x1ffffffe, RZ &req={0} ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2I.U64.TRUNC R6, R6 &wr=0x0 ?trans2;
IMAD.WIDE.U32 R8, R6, UR4, RZ &req={0} ?WAIT4_END_GROUP;
IMAD R9, R6, UR5, R9 ?trans1;
IADD3 R11, P0, PT, RZ, -R8, RZ ?WAIT3_END_GROUP;
IMAD R9, R7, UR4, R9 ?trans2;
IMAD.HI.U32 R8, R6, R11, RZ ?WAIT3_END_GROUP;
IADD3.X R13, PT, PT, RZ, ~R9, RZ, P0, !PT ?trans1;
MOV R9, R6 ?WAIT4_END_GROUP;
IMAD R15, R7, R13.reuse, RZ ?trans2;
IMAD.WIDE.U32 R8, P0, R6, R13, R8 ?WAIT4_END_GROUP;
IMAD.HI.U32 R13, R7, R13, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R8, P1, R7, R11, R8 ?WAIT5_END_GROUP;
IADD3 R9, P2, PT, R15, R8, RZ ?trans2;
IADD3.X R8, PT, PT, R13, R7, RZ, P0, !PT ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R6, R9, UR4, RZ ?trans1;
IADD3.X R11, PT, PT, RZ, RZ, R8, P2, P1 ?WAIT3_END_GROUP;
IMAD R8, R9, UR5, R7 ?trans1;
IADD3 R7, P0, PT, RZ, -R6, RZ ?WAIT3_END_GROUP;
IMAD R6, R11, UR4, R8 ?trans2;
IMAD.HI.U32 R8, R9, R7, RZ ?WAIT3_END_GROUP;
IADD3.X R10, PT, PT, RZ, ~R6, RZ, P0, !PT ?trans1;
ISETP.GE.AND P0, PT, R5, RZ, PT ?trans1;
IADD3 R6, P3, PT, RZ, -R4, RZ ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R8, P1, R9, R10, R8 ?WAIT4_END_GROUP;
IMAD.HI.U32 R9, P2, R11, R7, R8 ?trans1;
IADD3.X R7, PT, PT, RZ, ~R5, RZ, P3, !PT ?WAIT3_END_GROUP;
IMAD R8, R11.reuse, R10, RZ ?trans1;
@!P0 MOV R4, R6 ?trans1;
IMAD.HI.U32 R10, R11, R10, RZ ?trans1;
@!P0 MOV R5, R7 ?WAIT3_END_GROUP;
HFMA2 R7, -RZ, RZ, 0, 0 ?trans1;
IADD3 R9, P3, PT, R8, R9, RZ ?trans2;
IADD3.X R11, PT, PT, R10, R11, RZ, P1, !PT ?WAIT3_END_GROUP;
IMAD.HI.U32 R6, R9, R4, RZ ?trans1;
IADD3.X R11, PT, PT, RZ, RZ, R11, P3, P2 ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R6, R5, R9, R6 ?WAIT4_END_GROUP;
IMAD R9, R5, R11.reuse, RZ ?trans2;
IMAD.HI.U32 R6, P1, R4, R11, R6 ?WAIT4_END_GROUP;
IMAD.HI.U32 R8, R5, R11, RZ ?trans1;
IADD3 R9, P2, PT, R9, R6, RZ ?WAIT4_END_GROUP;
IADD3.X R8, PT, PT, R8, RZ, RZ, P1, !PT ?trans1;
IMAD.WIDE.U32 R6, R9, UR4, RZ ?WAIT3_END_GROUP;
IADD3.X R8, PT, PT, RZ, R8, RZ, P2, !PT ?trans1;
IMAD R7, R9, UR5, R7 ?WAIT4_END_GROUP;
IMAD R7, R8, UR4, R7 ?WAIT5_END_GROUP;
IADD.64 R4, R4, -R6 ?WAIT6_END_GROUP;
ISETP.GE.U64.AND P1, PT, R4, UR4, PT ?WAIT14_END_GROUP;
@P1 IADD.64 R4, R4, -UR4 ?WAIT6_END_GROUP;
ISETP.GE.U64.AND P1, PT, R4, UR4, PT ?WAIT14_END_GROUP;
@P1 IADD.64 R4, R4, -UR4 ?WAIT5_END_GROUP;
IADD3 R6, P1, PT, RZ, -R4, RZ ?WAIT4_END_GROUP;
IADD3.X R7, PT, PT, RZ, ~R5, RZ, P1, !PT ?trans1;
ISETP.NE.S64.AND P1, PT, RZ, UR8, PT ?trans2;
@!P0 MOV R4, R6 ?trans1;
MOV R6, R0 ?trans1;
@!P0 MOV R5, R7 ?trans1;
HFMA2 R7, -RZ, RZ, 0, 0 ?WAIT4_END_GROUP;
SEL.64 R4, R4, -0x1, P1 ?trans2;
RET.REL.NODEC R6 0x0 ?trans6;
BRA 0x910;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: collatz(long, long, long, int*)
_ZL7collatzlllPi:
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b32 s1, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_ashr_i32 s0, s9, 31
s_and_b32 s12, s1, 0xffff
s_add_u32 s2, s8, s0
s_mov_b32 s1, s0
s_addc_u32 s3, s9, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b64 s[2:3], s[2:3], s[0:1]
v_cvt_f32_u32_e32 v1, s2
v_cvt_f32_u32_e32 v2, s3
s_sub_u32 s0, 0, s2
s_subb_u32 s1, 0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v1, v2, 0x4f800000, v1
v_rcp_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x5f7ffffc, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v2, 0x2f800000, v1
v_trunc_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmamk_f32 v1, v2, 0xcf800000, v1
v_cvt_u32_f32_e32 v2, v2
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, s0, v2
v_mul_hi_u32 v4, s0, v1
v_mul_lo_u32 v5, s1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, v4, v3
v_mul_lo_u32 v4, s0, v1
v_add_nc_u32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, v4
v_mul_lo_u32 v6, v1, v3
v_mul_hi_u32 v7, v1, v3
v_mul_hi_u32 v8, v2, v4
v_mul_lo_u32 v4, v2, v4
v_mul_hi_u32 v9, v2, v3
v_mul_lo_u32 v3, v2, v3
v_add_co_u32 v5, vcc_lo, v5, v6
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, v5, v4
v_add_co_ci_u32_e32 v4, vcc_lo, v6, v8, vcc_lo
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, v4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, v1, v3
v_add_co_ci_u32_e32 v4, vcc_lo, v2, v4, vcc_lo
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mul_hi_u32 v2, s0, v5
v_mul_lo_u32 v6, s1, v5
v_mul_lo_u32 v3, s0, v4
v_mul_lo_u32 v8, s0, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v7, v2, v3
v_mad_u64_u32 v[2:3], null, s12, s15, v[0:1]
v_mul_hi_u32 v1, v5, v8
v_mul_hi_u32 v10, v4, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v0, v7, v6
v_mul_lo_u32 v8, v4, v8
v_ashrrev_i32_e32 v9, 31, v3
v_mul_lo_u32 v6, v5, v0
v_mul_hi_u32 v7, v5, v0
v_mul_hi_u32 v11, v4, v0
v_mul_lo_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, v1, v6
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, v1, v8
v_add_co_ci_u32_e32 v1, vcc_lo, v6, v10, vcc_lo
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v11, vcc_lo
v_add_co_u32 v7, vcc_lo, v2, v9
v_add_co_ci_u32_e32 v8, vcc_lo, v3, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, v1, v0
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v10, v7, v9
v_add_co_u32 v6, vcc_lo, v5, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v11, vcc_lo, v4, v1, vcc_lo
v_xor_b32_e32 v8, v8, v9
v_mul_hi_u32 v12, v10, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[0:1], null, v10, v11, 0
v_mad_u64_u32 v[4:5], null, v8, v6, 0
v_mad_u64_u32 v[6:7], null, v8, v11, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, v12, v0
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v4
v_add_co_ci_u32_e32 v0, vcc_lo, v1, v5, vcc_lo
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, v0, v6
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v6, s3, v4
v_mad_u64_u32 v[0:1], null, s2, v4, 0
v_mul_lo_u32 v4, s2, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v0, vcc_lo, v10, v0
v_add3_u32 v1, v1, v4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v8, v1
v_subrev_co_ci_u32_e64 v4, s0, s3, v4, vcc_lo
v_sub_co_ci_u32_e32 v1, vcc_lo, v8, v1, vcc_lo
v_sub_co_u32 v5, vcc_lo, v0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_subrev_co_ci_u32_e64 v6, s0, 0, v4, vcc_lo
v_cmp_le_u32_e64 s0, s2, v0
v_subrev_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s3, v1
v_cndmask_b32_e64 v7, 0, -1, s0
v_cmp_le_u32_e64 s0, s2, v5
v_cndmask_b32_e64 v11, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, s3, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v8, 0, -1, s0
v_cmp_le_u32_e64 s0, s3, v6
v_cndmask_b32_e64 v10, 0, -1, s0
v_cmp_eq_u32_e64 s0, s3, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v8, v10, v8, vcc_lo
v_sub_co_u32 v10, vcc_lo, v5, s2
v_subrev_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v8
v_cndmask_b32_e64 v7, v11, v7, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v4, v6, v4 :: v_dual_cndmask_b32 v5, v5, v10
v_cmp_ne_u32_e32 vcc_lo, 0, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v0, v0, v5 :: v_dual_cndmask_b32 v1, v1, v4
v_xor_b32_e32 v0, v0, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v1, v1, v9
v_sub_co_u32 v4, vcc_lo, v0, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_sub_co_ci_u32_e32 v5, vcc_lo, v1, v9, vcc_lo
v_add_co_u32 v0, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s0, s[6:7], v[0:1]
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_13
v_mov_b32_e32 v2, 1
s_mov_b32 s0, exec_lo
v_cmpx_ne_u64_e32 1, v[0:1]
s_cbranch_execz .LBB0_9
s_mov_b32 s2, 1
s_mov_b32 s1, 0
.LBB0_3:
v_and_b32_e32 v2, 1, v0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 1, v2
s_xor_b32 s3, exec_lo, s3
v_mad_u64_u32 v[2:3], null, v0, 3, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v0, v3
v_mad_u64_u32 v[3:4], null, v1, 3, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
s_and_not1_saveexec_b32 s3, s3
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i64 v[0:1], 1, v[0:1]
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_eq_u64_e32 vcc_lo, 1, v[0:1]
s_add_i32 s2, s2, 1
v_mov_b32_e32 v2, s2
s_or_b32 s1, vcc_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s1
.LBB0_9:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s0
s_mov_b32 s1, exec_lo
s_brev_b32 s0, 1
.LBB0_10:
s_ctz_i32_b32 s2, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s3, v2, s2
s_lshl_b32 s2, 1, s2
s_and_not1_b32 s1, s1, s2
s_delay_alu instid0(VALU_DEP_1)
s_max_i32 s0, s0, s3
s_cmp_lg_u32 s1, 0
s_cbranch_scc1 .LBB0_10
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB0_13
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_atomic_max_i32 v0, v1, s[10:11]
.LBB0_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| collatz | 3,450 | 4,547 | stackv2-00001-of-00015 |
// Demangled: resolveWeight(signed char*, signed char*, signed char*, int, int)
Function : _Z13resolveWeightPaS_S_ii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R5, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans8;
LDC R4, c[0x0][0x360] &wr=0x1 ?trans8;
LDC.64 R2, c[0x0][0x398] &wr=0x2 ?trans1;
IMAD R4, R4, UR4, R5 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R4, R3, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
ISETP.GE.AND P0, PT, R2, 0x1, PT ?trans1;
LDCU.64 UR8, c[0x0][0x358] &wr=0x0 ?trans1;
PRMT R23, RZ, 0x7610, R23 ?WAIT11_END_GROUP;
@!P0 BRA 0xaa0 ?trans5;
ISETP.GE.U32.AND P1, PT, R2.reuse, 0x10, PT ?trans1;
LOP3.LUT R32, R2, 0xf, RZ, 0xc0, !PT ?trans1;
UMOV UR4, URZ ?trans1;
IMAD R3, R4, R2, RZ ?trans1;
PRMT R23, RZ, 0x7610, R23 ?trans2;
ISETP.NE.AND P0, PT, R32, RZ, PT ?WAIT7_END_GROUP;
@!P1 BRA 0x560 ?trans6;
LDCU.128 UR4, c[0x0][0x380] &wr=0x1 ?trans1;
LOP3.LUT R10, R2, 0x7ffffff0, RZ, 0xc0, !PT ?trans2;
PRMT R23, RZ, 0x7610, R23 ?trans1;
MOV R0, R3 ?trans1;
IADD3 R10, PT, PT, -R10, RZ, RZ ?trans1;
UIADD3.64 UR4, UPT, UPT, UR4, 0x7, URZ &req={1} ?trans1;
UIADD3.64 UR6, UPT, UPT, UR6, 0x7, URZ ?WAIT5_END_GROUP;
MOV.64 R6, UR4 ?trans2;
UMOV UR4, URZ ?WAIT6_END_GROUP;
SHF.R.S32.HI R9, RZ, 0x1f, R0 ?trans1;
LDG.E.U8 R24, desc[UR8][R6.64+-0x7] &req={0} &wr=0x2 ?trans1;
MOV R8, R0 ?WAIT3_END_GROUP;
LDG.E.U8 R31, desc[UR8][R6.64+-0x6] &wr=0x3 ?trans2;
IADD.64 R8, R8, UR6 ?trans2;
LDG.E.U8 R30, desc[UR8][R6.64+-0x5] &wr=0x4 ?trans4;
LDG.E.U8 R25, desc[UR8][R8.64+-0x7] &wr=0x2 ?trans4;
LDG.E.U8 R33, desc[UR8][R8.64+-0x6] &wr=0x3 ?trans4;
LDG.E.U8 R29, desc[UR8][R8.64+-0x5] &wr=0x4 ?trans4;
LDG.E.U8 R27, desc[UR8][R6.64+-0x4] &wr=0x5 ?trans4;
LDG.E.U8 R28, desc[UR8][R8.64+-0x4] &wr=0x5 ?trans4;
LDG.E.U8 R12, desc[UR8][R6.64+-0x3] &wr=0x5 ?trans4;
LDG.E.U8 R11, desc[UR8][R8.64+-0x3] &wr=0x5 ?trans4;
LDG.E.U8 R21, desc[UR8][R6.64+-0x2] &wr=0x5 ?trans4;
LDG.E.U8 R22, desc[UR8][R8.64+-0x2] &wr=0x5 ?trans4;
LDG.E.U8 R19, desc[UR8][R6.64+-0x1] &wr=0x5 ?trans4;
LDG.E.U8 R20, desc[UR8][R8.64+-0x1] &wr=0x5 ?trans4;
LDG.E.U8 R17, desc[UR8][R6.64] &wr=0x5 ?trans4;
LDG.E.U8 R18, desc[UR8][R8.64] &wr=0x5 ?trans4;
LDG.E.U8 R15, desc[UR8][R6.64+0x1] &wr=0x5 ?trans4;
LDG.E.U8 R16, desc[UR8][R8.64+0x1] &wr=0x5 ?trans4;
LDG.E.U8 R13, desc[UR8][R6.64+0x2] &wr=0x5 ?trans4;
LDG.E.U8 R14, desc[UR8][R8.64+0x2] &wr=0x5 ?trans4;
LDG.E.U8 R26, desc[UR8][R8.64+0x3] &wr=0x5 ?trans4;
LDG.E.U8 R34, desc[UR8][R8.64+0x6] &wr=0x5 ?trans4;
LDG.E.U8 R36, desc[UR8][R8.64+0x8] &wr=0x5 ?trans1;
IMAD R24, R24, R25, R23 &req={2} ?WAIT3_END_GROUP;
LDG.E.U8 R25, desc[UR8][R6.64+0x3] &wr=0x2 ?trans1;
IMAD R31, R31, R33, R24 &req={3} ?WAIT3_END_GROUP;
LDG.E.U8 R23, desc[UR8][R6.64+0x4] &wr=0x3 ?trans1;
IMAD R31, R30, R29, R31 &req={4} ?WAIT3_END_GROUP;
LDG.E.U8 R24, desc[UR8][R8.64+0x4] &wr=0x3 ?trans4;
LDG.E.U8 R29, desc[UR8][R6.64+0x5] &wr=0x4 ?trans4;
LDG.E.U8 R30, desc[UR8][R8.64+0x5] &wr=0x4 ?trans1;
IMAD R35, R27, R28, R31 &req={5} ?WAIT3_END_GROUP;
LDG.E.U8 R31, desc[UR8][R6.64+0x6] &wr=0x5 ?trans4;
LDG.E.U8 R27, desc[UR8][R6.64+0x7] &wr=0x5 ?trans4;
LDG.E.U8 R28, desc[UR8][R8.64+0x7] &wr=0x5 ?trans4;
LDG.E.U8 R33, desc[UR8][R6.64+0x8] &rd=0x0 &wr=0x5 ?trans1;
IMAD R11, R12, R11, R35 ?WAIT4_END_GROUP;
IMAD R11, R21, R22, R11 ?WAIT4_END_GROUP;
IMAD R11, R19, R20, R11 ?WAIT4_END_GROUP;
IMAD R11, R17, R18, R11 ?WAIT4_END_GROUP;
IMAD R11, R15, R16, R11 ?WAIT4_END_GROUP;
IMAD R11, R13, R14, R11 ?trans1;
IADD3 R10, PT, PT, R10, 0x10, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R10, RZ, PT ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x10, URZ ?trans1;
IADD.64 R6, R6, 0x10 &req={0} ?WAIT3_END_GROUP;
IADD3 R0, PT, PT, R0, 0x10, RZ ?trans1;
IMAD R11, R25, R26, R11 &req={2} ?WAIT4_END_GROUP;
IMAD R11, R23, R24, R11 &req={3} ?WAIT4_END_GROUP;
IMAD R11, R29, R30, R11 &req={4} ?WAIT4_END_GROUP;
IMAD R11, R31, R34, R11 &req={5} ?WAIT4_END_GROUP;
IMAD R11, R27, R28, R11 ?WAIT4_END_GROUP;
IMAD R11, R33, R36, R11 ?WAIT5_END_GROUP;
PRMT R23, R11, 0x7610, R23 ?trans1;
@P1 BRA 0x1c0 ?trans6;
@!P0 BRA 0xaa0 ?trans5;
ISETP.GE.U32.AND P0, PT, R32, 0x8, PT ?trans1;
LOP3.LUT R24, R2, 0x7, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R24, RZ, PT ?WAIT7_END_GROUP;
@!P0 BRA 0x7c0 ?trans6;
LDC.64 R6, c[0x0][0x380] &wr=0x1 ?trans1;
IADD3 R8, PT, PT, R3, UR4, RZ ?trans1;
UMOV UR5, URZ ?WAIT3_END_GROUP;
SHF.R.S32.HI R9, RZ, 0x1f, R8 ?WAIT3_END_GROUP;
LDC.64 R10, c[0x0][0x388] &wr=0x2 ?trans1;
IADD.64 R6, R6, UR4 &req={1} ?WAIT6_END_GROUP;
LDG.E.U8 R0, desc[UR8][R6.64] &req={0} &wr=0x3 ?trans1;
IADD.64 R8, R8, R10 &req={2} ?WAIT3_END_GROUP;
LDG.E.U8 R11, desc[UR8][R6.64+0x1] &wr=0x2 ?trans4;
LDG.E.U8 R10, desc[UR8][R8.64] &wr=0x3 ?trans4;
LDG.E.U8 R12, desc[UR8][R8.64+0x1] &wr=0x2 ?trans4;
LDG.E.U8 R13, desc[UR8][R6.64+0x2] &wr=0x4 ?trans4;
LDG.E.U8 R14, desc[UR8][R8.64+0x2] &wr=0x4 ?trans4;
LDG.E.U8 R15, desc[UR8][R6.64+0x3] &wr=0x5 ?trans4;
LDG.E.U8 R16, desc[UR8][R8.64+0x3] &wr=0x5 ?trans4;
LDG.E.U8 R17, desc[UR8][R6.64+0x4] &wr=0x5 ?trans4;
LDG.E.U8 R18, desc[UR8][R8.64+0x4] &wr=0x5 ?trans4;
LDG.E.U8 R19, desc[UR8][R6.64+0x5] &wr=0x5 ?trans4;
LDG.E.U8 R20, desc[UR8][R8.64+0x5] &wr=0x5 ?trans4;
LDG.E.U8 R21, desc[UR8][R6.64+0x6] &wr=0x5 ?trans4;
LDG.E.U8 R22, desc[UR8][R8.64+0x6] &wr=0x5 ?trans4;
LDG.E.U8 R26, desc[UR8][R8.64+0x7] &wr=0x5 ?trans4;
LDG.E.U8 R25, desc[UR8][R6.64+0x7] &wr=0x5 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x8, URZ ?trans1;
IMAD R0, R0, R10, R23 &req={3} ?WAIT4_END_GROUP;
IMAD R0, R11, R12, R0 &req={2} ?WAIT4_END_GROUP;
IMAD R0, R13, R14, R0 &req={4} ?WAIT4_END_GROUP;
IMAD R0, R15, R16, R0 &req={5} ?WAIT4_END_GROUP;
IMAD R0, R17, R18, R0 ?WAIT4_END_GROUP;
IMAD R0, R19, R20, R0 ?WAIT4_END_GROUP;
IMAD R0, R21, R22, R0 ?WAIT4_END_GROUP;
IMAD R0, R25, R26, R0 ?WAIT5_END_GROUP;
PRMT R23, R0, 0x7610, R23 ?WAIT7_END_GROUP;
@!P1 BRA 0xaa0 ?trans5;
ISETP.GE.U32.AND P0, PT, R24, 0x4, PT ?trans1;
LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R2, RZ, PT ?WAIT7_END_GROUP;
@!P0 BRA 0x960 ?trans6;
LDC.64 R6, c[0x0][0x380] &wr=0x1 ?trans1;
IADD3 R8, PT, PT, R3, UR4, RZ ?trans1;
UMOV UR5, URZ ?WAIT3_END_GROUP;
SHF.R.S32.HI R9, RZ, 0x1f, R8 ?WAIT3_END_GROUP;
LDC.64 R10, c[0x0][0x388] &wr=0x2 ?trans1;
IADD.64 R6, R6, UR4 &req={1} ?WAIT6_END_GROUP;
LDG.E.U8 R0, desc[UR8][R6.64] &req={0} &wr=0x3 ?trans1;
IADD.64 R10, R8, R10 &req={2} ?WAIT3_END_GROUP;
LDG.E.U8 R9, desc[UR8][R6.64+0x1] &wr=0x2 ?trans4;
LDG.E.U8 R8, desc[UR8][R10.64] &wr=0x3 ?trans4;
LDG.E.U8 R12, desc[UR8][R10.64+0x1] &wr=0x2 ?trans4;
LDG.E.U8 R13, desc[UR8][R6.64+0x2] &wr=0x4 ?trans4;
LDG.E.U8 R14, desc[UR8][R10.64+0x2] &wr=0x4 ?trans4;
LDG.E.U8 R16, desc[UR8][R10.64+0x3] &wr=0x5 ?trans4;
LDG.E.U8 R15, desc[UR8][R6.64+0x3] &wr=0x5 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x4, URZ ?trans1;
IMAD R0, R0, R8, R23 &req={3} ?WAIT4_END_GROUP;
IMAD R0, R9, R12, R0 &req={2} ?WAIT4_END_GROUP;
IMAD R0, R13, R14, R0 &req={4} ?WAIT4_END_GROUP;
IMAD R0, R15, R16, R0 &req={5} ?WAIT5_END_GROUP;
PRMT R23, R0, 0x7610, R23 ?WAIT7_END_GROUP;
@!P1 BRA 0xaa0 ?trans5;
LDCU.64 UR6, c[0x0][0x380] &wr=0x1 ?trans1;
IADD3 R9, PT, PT, R3, UR4, RZ ?trans2;
IADD3 R0, PT, PT, -R2, RZ, RZ ?trans1;
UMOV UR5, URZ ?trans1;
LDCU.64 UR10, c[0x0][0x388] &wr=0x2 ?trans1;
UIADD3.64 UR6, UPT, UPT, UR4, UR6, URZ &req={1} ?WAIT6_END_GROUP;
MOV.64 R2, UR6 &req={2} ?WAIT8_END_GROUP;
SHF.R.S32.HI R7, RZ, 0x1f, R9 ?trans1;
LDG.E.U8 R8, desc[UR8][R2.64] &req={0} &rd=0x0 &wr=0x2 ?trans1;
MOV R6, R9 ?WAIT5_END_GROUP;
IADD.64 R6, R6, UR10 ?WAIT7_END_GROUP;
LDG.E.U8 R6, desc[UR8][R6.64] &wr=0x2 ?trans1;
IADD3 R0, PT, PT, R0, 0x1, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R0, RZ, PT ?trans1;
IADD.64 R2, R2, 0x1 &req={0} ?WAIT3_END_GROUP;
IADD3 R9, PT, PT, R9, 0x1, RZ ?trans1;
IMAD R8, R8, R6, R23 &req={2} ?WAIT5_END_GROUP;
PRMT R23, R8, 0x7610, R23 ?WAIT3_END_GROUP;
@P0 BRA 0x9e0 ?trans5;
LDCU.64 UR4, c[0x0][0x390] &wr=0x1 ?trans1;
SHF.R.S32.HI R5, RZ, 0x1f, R4 ?WAIT5_END_GROUP;
IADD.64 R4, R4, UR4 &req={1} ?WAIT6_END_GROUP;
STG.E.U8 desc[UR8][R4.64], R23 &req={0} ?trans1;
EXIT ?trans5;
BRA 0xaf0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: resolveWeight(signed char*, signed char*, signed char*, int, int)
_Z13resolveWeightPaS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
v_mul_lo_u32 v0, v1, s2
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v3, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
v_mov_b32_e32 v0, 0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
.LBB0_3:
global_load_u8 v5, v4, s[4:5]
global_load_u8 v6, v[2:3], off
v_add_co_u32 v2, vcc_lo, v2, 1
s_add_i32 s2, s2, -1
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_add_u32 s4, s4, 1
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s2, 0
s_waitcnt vmcnt(0)
v_mad_u16 v0, v6, v5, v0
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v0, 0
.LBB0_5:
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b8 v[1:2], v0, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| resolveWeight | 4,805 | 777 | stackv2-00001-of-00015 |
// Demangled: KernelRect(unsigned char*, long*, long*, int, int)
Function : _Z10KernelRectPhPlS0_ii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R4, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR28, c[0x0][0x358] &wr=0x2 ?trans1;
BSSY.RECONVERGENT B0, 0x760 ?trans6;
LDC R5, c[0x0][0x360] &wr=0x1 ?trans8;
LDC R2, c[0x0][0x39c] &wr=0x3 ?trans1;
IMAD R4, R5, UR4, R4 &req={1} ?WAIT2_END_GROUP;
HFMA2 R5, -RZ, RZ, 0, 0 ?trans1;
SHF.R.S32.HI R3, RZ, 0x1f, R2 &req={3} ?WAIT5_END_GROUP;
ISETP.GE.U64.AND P0, PT, R4, R2, PT ?WAIT14_END_GROUP;
@P0 BRA 0x750 &req={2,0} ?trans5;
LDC R11, c[0x0][0x398] &wr=0x0 ?trans1;
MOV.64 R6, RZ ?trans2;
ISETP.GE.AND P0, PT, R11, 0x1, PT &req={0} ?WAIT13_END_GROUP;
@!P0 BRA 0x710 ?trans5;
IADD3 R0, PT, PT, R11.reuse, -0x1, RZ ?trans1;
IMAD.WIDE.U32 R6, R4, R11, RZ ?trans1;
UMOV UR4, URZ ?trans1;
LOP3.LUT R26, R11, 0xf, RZ, 0xc0, !PT ?trans2;
ISETP.GE.U32.AND P1, PT, R0, 0xf, PT ?trans1;
IADD3 R7, PT, PT, R7, UR4, RZ ?trans1;
UMOV UR4, URZ ?trans1;
HFMA2 R0, -RZ, RZ, 0, 0 ?trans1;
ISETP.NE.AND P0, PT, R26, RZ, PT ?WAIT9_END_GROUP;
@!P1 BRA 0x3d0 ?trans5;
LDCU.64 UR4, c[0x0][0x380] &wr=0x0 ?trans1;
LOP3.LUT R10, R11, 0x7ffffff0, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R10, PT, PT, -R10, RZ, RZ ?trans1;
IADD.64 R8, R6, UR4 &req={0} ?trans2;
UMOV UR4, URZ ?trans2;
IADD.64 R8, R8, 0x7 ?WAIT8_END_GROUP;
LDG.E.U8 R13, desc[UR28][R8.64+-0x7] &wr=0x2 ?trans4;
LDG.E.U8 R12, desc[UR28][R8.64+-0x6] &wr=0x2 ?trans4;
LDG.E.U8 R15, desc[UR28][R8.64+-0x5] &wr=0x3 ?trans4;
LDG.E.U8 R14, desc[UR28][R8.64+-0x4] &wr=0x3 ?trans4;
LDG.E.U8 R17, desc[UR28][R8.64+-0x3] &wr=0x4 ?trans4;
LDG.E.U8 R16, desc[UR28][R8.64+-0x2] &wr=0x4 ?trans4;
LDG.E.U8 R19, desc[UR28][R8.64+-0x1] &wr=0x5 ?trans4;
LDG.E.U8 R18, desc[UR28][R8.64] &wr=0x5 ?trans4;
LDG.E.U8 R21, desc[UR28][R8.64+0x1] &wr=0x5 ?trans4;
LDG.E.U8 R20, desc[UR28][R8.64+0x2] &wr=0x5 ?trans4;
LDG.E.U8 R23, desc[UR28][R8.64+0x3] &wr=0x5 ?trans4;
LDG.E.U8 R22, desc[UR28][R8.64+0x4] &wr=0x5 ?trans4;
LDG.E.U8 R25, desc[UR28][R8.64+0x5] &wr=0x5 ?trans4;
LDG.E.U8 R24, desc[UR28][R8.64+0x6] &wr=0x5 ?trans4;
LDG.E.U8 R27, desc[UR28][R8.64+0x7] &wr=0x5 ?trans4;
LDG.E.U8 R28, desc[UR28][R8.64+0x8] &rd=0x0 &wr=0x5 ?trans1;
IADD3 R10, PT, PT, R10, 0x10, RZ ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x10, URZ ?WAIT4_END_GROUP;
ISETP.NE.AND P1, PT, R10, RZ, PT ?trans1;
IADD.64 R8, R8, 0x10 &req={0} ?WAIT3_END_GROUP;
IADD3 R12, PT, PT, R12, R0, R13 &req={2} ?WAIT4_END_GROUP;
IADD3 R12, PT, PT, R14, R12, R15 &req={3} ?WAIT4_END_GROUP;
IADD3 R12, PT, PT, R16, R12, R17 &req={4} ?WAIT4_END_GROUP;
IADD3 R12, PT, PT, R18, R12, R19 &req={5} ?WAIT4_END_GROUP;
IADD3 R12, PT, PT, R20, R12, R21 ?WAIT4_END_GROUP;
IADD3 R12, PT, PT, R22, R12, R23 ?WAIT4_END_GROUP;
IADD3 R12, PT, PT, R24, R12, R25 ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R28, R12, R27 ?trans1;
@P1 BRA 0x200 ?trans6;
@!P0 BRA 0x6f0 ?trans5;
ISETP.GE.U32.AND P0, PT, R26, 0x8, PT ?trans1;
LOP3.LUT R18, R11, 0x7, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R18, RZ, PT ?WAIT7_END_GROUP;
@!P0 BRA 0x530 ?trans6;
LDCU.64 UR6, c[0x0][0x380] &wr=0x0 ?trans1;
UMOV UR5, URZ ?trans2;
IADD.64 R8, R6, UR4 ?WAIT4_END_GROUP;
IADD.64 R8, R8, UR6 &req={0} ?WAIT6_END_GROUP;
LDG.E.U8 R13, desc[UR28][R8.64] &wr=0x2 ?trans4;
LDG.E.U8 R10, desc[UR28][R8.64+0x1] &wr=0x2 ?trans4;
LDG.E.U8 R15, desc[UR28][R8.64+0x2] &wr=0x3 ?trans4;
LDG.E.U8 R12, desc[UR28][R8.64+0x3] &wr=0x3 ?trans4;
LDG.E.U8 R17, desc[UR28][R8.64+0x4] &wr=0x4 ?trans4;
LDG.E.U8 R14, desc[UR28][R8.64+0x5] &wr=0x4 ?trans4;
LDG.E.U8 R19, desc[UR28][R8.64+0x6] &wr=0x5 ?trans4;
LDG.E.U8 R16, desc[UR28][R8.64+0x7] &wr=0x5 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x8, URZ ?trans1;
IADD3 R10, PT, PT, R10, R0, R13 &req={2} ?WAIT4_END_GROUP;
IADD3 R10, PT, PT, R12, R10, R15 &req={3} ?WAIT4_END_GROUP;
IADD3 R10, PT, PT, R14, R10, R17 &req={4} ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R16, R10, R19 &req={5} ?WAIT7_END_GROUP;
@!P1 BRA 0x6f0 ?trans5;
ISETP.GE.U32.AND P0, PT, R18, 0x4, PT ?trans1;
LOP3.LUT R11, R11, 0x3, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R11, RZ, PT ?WAIT7_END_GROUP;
@!P0 BRA 0x630 ?trans6;
LDCU.64 UR6, c[0x0][0x380] &wr=0x0 ?trans1;
UMOV UR5, URZ ?trans2;
IADD.64 R8, R6, UR4 ?WAIT4_END_GROUP;
IADD.64 R8, R8, UR6 &req={0} ?WAIT6_END_GROUP;
LDG.E.U8 R13, desc[UR28][R8.64] &wr=0x2 ?trans4;
LDG.E.U8 R10, desc[UR28][R8.64+0x1] &wr=0x2 ?trans4;
LDG.E.U8 R15, desc[UR28][R8.64+0x2] &wr=0x3 ?trans4;
LDG.E.U8 R12, desc[UR28][R8.64+0x3] &wr=0x3 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x4, URZ ?trans1;
IADD3 R0, PT, PT, R10, R0, R13 &req={2} ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R12, R0, R15 &req={3} ?WAIT7_END_GROUP;
@!P1 BRA 0x6f0 ?trans5;
LDCU.64 UR6, c[0x0][0x380] &wr=0x0 ?trans1;
IADD3 R11, PT, PT, -R11, RZ, RZ ?trans1;
UMOV UR5, URZ ?trans2;
IADD.64 R6, R6, UR4 ?WAIT4_END_GROUP;
IADD.64 R6, R6, UR6 &req={0} ?WAIT8_END_GROUP;
LDG.E.U8 R9, desc[UR28][R6.64] &rd=0x0 &wr=0x2 ?trans1;
IADD3 R11, PT, PT, R11, 0x1, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R11, RZ, PT ?trans1;
IADD.64 R6, R6, 0x1 &req={0} ?WAIT3_END_GROUP;
IADD3 R0, PT, PT, R9, R0, RZ &req={2} ?WAIT9_END_GROUP;
@P0 BRA 0x690 ?trans5;
HFMA2 R7, -RZ, RZ, 0, 0 ?trans1;
MOV R6, R0 ?WAIT7_END_GROUP;
LDCU.64 UR4, c[0x0][0x390] &wr=0x0 ?trans2;
LEA R8, P0, R4, UR4, 0x3 &req={0} ?WAIT4_END_GROUP;
LEA.HI.X R9, R4, UR5, RZ, 0x3, P0 ?WAIT5_END_GROUP;
STG.E.64 desc[UR28][R8.64], R6 &rd=0x0 ?trans4;
BSYNC.RECONVERGENT B0 ?trans5;
LDCU UR32, c[0x0][0x398] &wr=0x1 ?trans2;
USHF.R.S32.HI UR33, URZ, 0x1f, UR32 &req={1} ?WAIT6_END_GROUP;
ISETP.GE.U64.AND P0, PT, R4, UR32, PT ?WAIT14_END_GROUP;
@P0 EXIT ?trans5;
ISETP.GE.AND P0, PT, R2, 0x1, PT ?trans1;
MOV.64 R6, RZ &req={0} ?WAIT12_END_GROUP;
@!P0 BRA 0x1620 ?trans5;
ISETP.GE.U32.AND P1, PT, R2.reuse, 0x10, PT ?trans1;
LOP3.LUT R27, R2, 0xf, RZ, 0xc0, !PT ?trans1;
UMOV UR4, URZ ?trans1;
HFMA2 R0, -RZ, RZ, 0, 0 ?WAIT3_END_GROUP;
ISETP.NE.AND P0, PT, R27, RZ, PT ?WAIT7_END_GROUP;
@!P1 BRA 0x1030 ?trans6;
LOP3.LUT R14, R2, 0x7ffffff0, RZ, 0xc0, !PT ?trans1;
UIADD3 UR5, UPT, UPT, UR32, UR32, URZ ?trans1;
MOV R0, RZ ?trans1;
UIMAD UR16, UR32, 0x3, URZ ?trans1;
USHF.L.U32 UR17, UR32, 0x2, URZ ?trans1;
IADD3 R14, PT, PT, -R14, RZ, RZ ?trans1;
UIMAD UR18, UR32, 0x5, URZ ?trans1;
UIMAD UR19, UR32, 0x6, URZ ?trans1;
UIMAD UR20, UR32, 0x7, URZ ?trans1;
USHF.L.U32 UR21, UR32, 0x3, URZ ?trans1;
UIMAD UR22, UR32, 0x9, URZ ?trans1;
UIMAD UR23, UR32, 0xa, URZ ?trans1;
LDCU UR31, c[0x0][0x398] &wr=0x0 ?trans1;
LDCU.64 UR34, c[0x0][0x380] &wr=0x1 ?trans1;
UIMAD UR24, UR32, 0xb, URZ ?trans1;
UIMAD UR25, UR32, 0xc, URZ ?trans1;
UIMAD UR26, UR32, 0xd, URZ ?trans1;
UIMAD UR27, UR32, 0xe, URZ ?trans1;
UIMAD UR30, UR32, 0xf, URZ ?trans1;
UMOV UR6, URZ ?trans1;
UMOV UR4, URZ ?WAIT10_END_GROUP;
USHF.R.S32.HI UR9, URZ, 0x1f, UR31 &req={0} ?trans1;
USHF.R.S32.HI UR11, URZ, 0x1f, UR5 ?trans1;
USHF.R.S32.HI UR7, URZ, 0x1f, UR6 ?trans1;
UMOV UR8, UR31 ?trans1;
UMOV UR10, UR5 ?trans1;
USHF.R.S32.HI UR13, URZ, 0x1f, UR16 ?trans1;
IADD.64 R8, R4.reuse, UR8 ?trans2;
IADD.64 R10, R4.reuse, UR10 ?trans2;
USHF.R.S32.HI UR9, URZ, 0x1f, UR17 ?trans1;
USHF.R.S32.HI UR11, URZ, 0x1f, UR18 ?trans1;
IADD.64 R6, R4, UR6 ?WAIT2_END_GROUP;
UMOV UR12, UR16 ?trans1;
UMOV UR8, UR17 ?trans1;
UMOV UR10, UR18 ?trans1;
IADD.64 R12, R4, UR12 ?trans2;
IADD.64 R6, R6, UR34 &req={1} ?trans2;
IADD.64 R8, R8, UR34 ?trans2;
IADD.64 R20, R4.reuse, UR8 ?trans2;
IADD.64 R24, R4, UR10 ?WAIT2_END_GROUP;
USHF.R.S32.HI UR9, URZ, 0x1f, UR19 ?trans1;
USHF.R.S32.HI UR11, URZ, 0x1f, UR20 ?trans1;
IADD.64 R12, R12, UR34 ?trans2;
USHF.R.S32.HI UR15, URZ, 0x1f, UR22 ?trans1;
UMOV UR8, UR19 ?trans1;
UMOV UR10, UR20 ?trans1;
IADD.64 R10, R10, UR34 ?trans2;
LDG.E.U8 R15, desc[UR28][R6.64] &rd=0x0 &wr=0x2 ?trans1;
IADD.64 R22, R20, UR34 ?WAIT3_END_GROUP;
LDG.E.U8 R16, desc[UR28][R8.64] &rd=0x1 &wr=0x2 ?trans1;
USHF.R.S32.HI UR13, URZ, 0x1f, UR21 ?trans1;
UMOV UR14, UR22 ?trans1;
IADD.64 R20, R24, UR34 ?trans2;
LDG.E.U8 R18, desc[UR28][R12.64] &rd=0x3 &wr=0x4 ?trans1;
IADD.64 R6, R4.reuse, UR8 &req={0} ?trans2;
USHF.R.S32.HI UR9, URZ, 0x1f, UR23 ?trans1;
LDG.E.U8 R17, desc[UR28][R10.64] &rd=0x0 &wr=0x4 ?trans1;
IADD.64 R8, R4, UR10 &req={1} ?WAIT2_END_GROUP;
USHF.R.S32.HI UR11, URZ, 0x1f, UR24 ?trans1;
UMOV UR12, UR21 ?trans1;
LDG.E.U8 R19, desc[UR28][R22.64] &wr=0x5 ?trans1;
IADD.64 R12, R4.reuse, UR14 &req={3} ?trans2;
UMOV UR8, UR23 ?trans1;
UMOV UR10, UR24 ?trans1;
IADD.64 R10, R4, UR12 &req={0} ?trans2;
IADD.64 R6, R6, UR34 ?trans2;
IADD.64 R8, R8, UR34 ?WAIT2_END_GROUP;
IADD.64 R12, R12, UR34 ?trans2;
IADD.64 R28, R4.reuse, UR8 ?trans2;
IADD.64 R30, R4, UR10 ?trans2;
USHF.R.S32.HI UR9, URZ, 0x1f, UR25 ?trans1;
USHF.R.S32.HI UR11, URZ, 0x1f, UR26 ?trans1;
LDG.E.U8 R20, desc[UR28][R20.64] &wr=0x5 ?trans1;
IADD.64 R10, R10, UR34 ?trans2;
USHF.R.S32.HI UR13, URZ, 0x1f, UR27 ?trans1;
USHF.R.S32.HI UR15, URZ, 0x1f, UR30 ?trans1;
UMOV UR8, UR25 ?trans1;
UMOV UR10, UR26 ?trans1;
LDG.E.U8 R22, desc[UR28][R8.64] &rd=0x0 &wr=0x3 ?trans1;
IADD.64 R28, R28, UR34 ?WAIT3_END_GROUP;
LDG.E.U8 R21, desc[UR28][R6.64] &wr=0x3 ?trans1;
IADD.64 R30, R30, UR34 ?WAIT3_END_GROUP;
LDG.E.U8 R24, desc[UR28][R12.64] &rd=0x1 &wr=0x3 ?trans1;
IADD.64 R8, R4.reuse, UR8 &req={0} ?trans2;
UMOV UR12, UR27 ?trans1;
UMOV UR14, UR30 ?trans1;
LDG.E.U8 R23, desc[UR28][R10.64] &rd=0x0 &wr=0x3 ?trans1;
IADD.64 R12, R4.reuse, UR10 &req={1} ?trans2;
IADD.64 R6, R4, UR14 ?trans2;
IADD.64 R8, R8, UR34 ?WAIT2_END_GROUP;
IADD.64 R10, R4, UR12 &req={0} ?trans2;
IADD.64 R12, R12, UR34 ?trans2;
LDG.E.U8 R25, desc[UR28][R28.64] &wr=0x3 ?trans1;
IADD.64 R10, R10, UR34 ?trans2;
IADD.64 R6, R6, UR34 ?trans2;
LDG.E.U8 R26, desc[UR28][R30.64] &wr=0x3 ?trans4;
LDG.E.U8 R8, desc[UR28][R8.64] &wr=0x3 ?trans4;
LDG.E.U8 R12, desc[UR28][R12.64] &wr=0x3 ?trans4;
LDG.E.U8 R11, desc[UR28][R10.64] &wr=0x3 ?trans4;
LDG.E.U8 R6, desc[UR28][R6.64] &wr=0x3 ?trans1;
IADD3 R14, PT, PT, R14, 0x10, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R14, RZ, PT ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x10, URZ ?trans1;
ULEA UR31, UR32, UR31, 0x4 ?trans1;
ULEA UR5, UR32, UR5, 0x4 ?trans1;
ULEA UR16, UR32, UR16, 0x4 ?trans1;
ULEA UR17, UR32, UR17, 0x4 ?trans1;
ULEA UR18, UR32, UR18, 0x4 ?trans1;
ULEA UR19, UR32, UR19, 0x4 ?trans1;
ULEA UR20, UR32, UR20, 0x4 ?trans1;
ULEA UR21, UR32, UR21, 0x4 ?trans1;
ULEA UR22, UR32, UR22, 0x4 ?trans1;
ULEA UR23, UR32, UR23, 0x4 ?trans1;
ULEA UR24, UR32, UR24, 0x4 ?trans1;
ULEA UR25, UR32, UR25, 0x4 ?trans1;
ULEA UR26, UR32, UR26, 0x4 ?trans1;
ULEA UR27, UR32, UR27, 0x4 ?trans1;
ULEA UR30, UR32, UR30, 0x4 ?trans1;
ULEA UR6, UR32, UR6, 0x4 ?trans1;
IADD3 R15, PT, PT, R16, R0, R15 &req={2} ?WAIT4_END_GROUP;
IADD3 R15, PT, PT, R18, R15, R17 &req={4} ?WAIT4_END_GROUP;
IADD3 R15, PT, PT, R20, R15, R19 &req={5} ?WAIT4_END_GROUP;
IADD3 R15, PT, PT, R22, R15, R21 &req={3} ?WAIT4_END_GROUP;
IADD3 R15, PT, PT, R24, R15, R23 ?WAIT4_END_GROUP;
IADD3 R15, PT, PT, R26, R15, R25 ?WAIT4_END_GROUP;
IADD3 R8, PT, PT, R12, R15, R8 ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R6, R8, R11 ?trans1;
@P1 BRA 0x980 ?trans6;
@!P0 BRA 0x1600 ?trans5;
ISETP.GE.U32.AND P0, PT, R27, 0x8, PT ?trans1;
LOP3.LUT R18, R2, 0x7, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R18, RZ, PT ?WAIT7_END_GROUP;
@!P0 BRA 0x1360 ?trans6;
UIMAD UR6, UR4, UR32, URZ ?trans1;
LDCU.64 UR14, c[0x0][0x380] &wr=0x0 ?trans3;
USHF.R.S32.HI UR7, URZ, 0x1f, UR6 ?trans1;
UIADD3 UR8, UPT, UPT, UR6, UR32, URZ ?WAIT4_END_GROUP;
USHF.R.S32.HI UR9, URZ, 0x1f, UR8 ?trans1;
IADD.64 R6, R4, UR6 ?trans2;
UIADD3 UR6, UPT, UPT, UR8, UR32, URZ ?WAIT4_END_GROUP;
UIADD3 UR10, UPT, UPT, UR6, UR32, URZ ?trans1;
IADD.64 R8, R4, UR8 ?trans2;
USHF.R.S32.HI UR7, URZ, 0x1f, UR6 ?trans1;
UIADD3 UR8, UPT, UPT, UR10, UR32, URZ ?trans1;
USHF.R.S32.HI UR11, URZ, 0x1f, UR10 ?trans1;
IADD.64 R6, R6, UR14 &req={0} ?trans2;
UIADD3 UR12, UPT, UPT, UR8, UR32, URZ ?trans1;
IADD.64 R10, R4, UR6 ?WAIT3_END_GROUP;
UIADD3 UR6, UPT, UPT, UR12, UR32, URZ ?trans1;
IADD.64 R12, R4, UR10 ?trans2;
USHF.R.S32.HI UR9, URZ, 0x1f, UR8 ?trans1;
USHF.R.S32.HI UR13, URZ, 0x1f, UR12 ?trans1;
UIADD3 UR10, UPT, UPT, UR6, UR32, URZ ?trans1;
IADD.64 R8, R8, UR14 ?trans2;
IADD.64 R10, R10, UR14 ?trans2;
USHF.R.S32.HI UR7, URZ, 0x1f, UR6 ?trans1;
USHF.R.S32.HI UR11, URZ, 0x1f, UR10 ?trans1;
IADD.64 R12, R12, UR14 ?WAIT2_END_GROUP;
IADD.64 R14, R4.reuse, UR8 ?trans2;
IADD.64 R16, R4, UR12 ?trans2;
LDG.E.U8 R7, desc[UR28][R6.64] &wr=0x2 ?trans1;
IADD.64 R14, R14, UR14 ?trans2;
IADD.64 R16, R16, UR14 ?trans2;
LDG.E.U8 R19, desc[UR28][R10.64] &rd=0x0 &wr=0x3 ?trans4;
LDG.E.U8 R12, desc[UR28][R12.64] &wr=0x3 ?trans4;
LDG.E.U8 R6, desc[UR28][R8.64] &rd=0x1 &wr=0x2 ?trans1;
IADD.64 R10, R4, UR10 &req={0} ?WAIT3_END_GROUP;
LDG.E.U8 R15, desc[UR28][R14.64] &wr=0x4 ?trans1;
IADD.64 R10, R10, UR14 ?WAIT3_END_GROUP;
LDG.E.U8 R16, desc[UR28][R16.64] &wr=0x4 ?trans1;
IADD.64 R8, R4, UR6 &req={1} ?WAIT3_END_GROUP;
LDG.E.U8 R10, desc[UR28][R10.64] &wr=0x5 ?trans1;
IADD.64 R8, R8, UR14 ?WAIT7_END_GROUP;
LDG.E.U8 R9, desc[UR28][R8.64] &wr=0x5 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x8, URZ ?trans1;
IADD3 R6, PT, PT, R6, R0, R7 &req={2} ?WAIT4_END_GROUP;
IADD3 R6, PT, PT, R12, R6, R19 &req={3} ?WAIT4_END_GROUP;
IADD3 R6, PT, PT, R16, R6, R15 &req={4} ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R10, R6, R9 &req={5} ?WAIT7_END_GROUP;
@!P1 BRA 0x1600 ?trans5;
ISETP.GE.U32.AND P0, PT, R18, 0x4, PT ?trans1;
LOP3.LUT R12, R2, 0x3, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R12, RZ, PT ?WAIT7_END_GROUP;
@!P0 BRA 0x1530 ?trans6;
UIMAD UR6, UR4, UR32, URZ ?trans1;
LDCU.64 UR8, c[0x0][0x380] &wr=0x0 ?trans3;
UIADD3 UR10, UPT, UPT, UR6, UR32, URZ ?trans1;
USHF.R.S32.HI UR7, URZ, 0x1f, UR6 ?WAIT3_END_GROUP;
UIADD3 UR12, UPT, UPT, UR10, UR32, URZ ?trans1;
USHF.R.S32.HI UR11, URZ, 0x1f, UR10 ?trans2;
IADD.64 R2, R4.reuse, UR6 ?trans2;
UIADD3 UR14, UPT, UPT, UR12, UR32, URZ ?trans1;
USHF.R.S32.HI UR13, URZ, 0x1f, UR12 ?trans1;
IADD.64 R6, R4, UR10 ?trans2;
USHF.R.S32.HI UR15, URZ, 0x1f, UR14 ?trans1;
IADD.64 R2, R2, UR8 &req={0} ?WAIT2_END_GROUP;
IADD.64 R6, R6, UR8 ?trans2;
IADD.64 R8, R4.reuse, UR12 ?trans2;
IADD.64 R10, R4, UR14 ?trans2;
IADD.64 R8, R8, UR8 ?trans2;
IADD.64 R10, R10, UR8 ?trans2;
LDG.E.U8 R3, desc[UR28][R2.64] &wr=0x2 ?trans4;
LDG.E.U8 R6, desc[UR28][R6.64] &wr=0x2 ?trans4;
LDG.E.U8 R9, desc[UR28][R8.64] &wr=0x3 ?trans4;
LDG.E.U8 R10, desc[UR28][R10.64] &wr=0x3 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x4, URZ ?trans1;
IADD3 R0, PT, PT, R6, R0, R3 &req={2} ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R10, R0, R9 &req={3} ?WAIT7_END_GROUP;
@!P1 BRA 0x1600 ?trans5;
IADD3 R12, PT, PT, -R12, RZ, RZ ?trans1;
LDCU.64 UR6, c[0x0][0x380] &wr=0x0 ?trans1;
UIMAD UR4, UR4, UR32, URZ ?WAIT12_END_GROUP;
USHF.R.S32.HI UR5, URZ, 0x1f, UR4 ?WAIT6_END_GROUP;
IADD.64 R2, R4, UR4 ?WAIT4_END_GROUP;
IADD.64 R2, R2, UR6 &req={0} ?WAIT7_END_GROUP;
LDG.E.U8 R3, desc[UR28][R2.64] &wr=0x2 ?trans1;
IADD3 R12, PT, PT, R12, 0x1, RZ ?trans1;
UIADD3 UR4, UPT, UPT, UR4, UR32, URZ ?WAIT4_END_GROUP;
ISETP.NE.AND P0, PT, R12, RZ, PT ?trans1;
IADD3 R0, PT, PT, R3, R0, RZ &req={2} ?WAIT12_END_GROUP;
@P0 BRA 0x1570 ?trans5;
HFMA2 R7, -RZ, RZ, 0, 0 ?trans1;
MOV R6, R0 ?WAIT7_END_GROUP;
LDCU.64 UR4, c[0x0][0x388] &wr=0x0 ?trans2;
LEA R2, P0, R4, UR4, 0x3 &req={0} ?WAIT4_END_GROUP;
LEA.HI.X R3, R4, UR5, RZ, 0x3, P0 ?WAIT5_END_GROUP;
STG.E.64 desc[UR28][R2.64], R6 ?trans1;
EXIT ?trans5;
BRA 0x1670;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: KernelRect(unsigned char*, long*, long*, int, int)
_ZL10KernelRectPhPlS0_ii:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x2c
s_load_b256 s[0:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s8, 0xffff
s_ashr_i32 s9, s7, 31
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s8, s7
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_u64_e32 vcc_lo, s[8:9], v[1:2]
s_and_saveexec_b32 s8, vcc_lo
s_cbranch_execz .LBB0_7
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB0_5
v_mad_u64_u32 v[4:5], null, v1, s6, s[0:1]
v_mov_b32_e32 v3, 0
s_mov_b32 s9, s6
.LBB0_3:
global_load_u8 v0, v[4:5], off
v_add_co_u32 v4, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_add_i32 s9, s9, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s9, 0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v3, v0
s_cbranch_scc0 .LBB0_3
v_mov_b32_e32 v4, 0
s_branch .LBB0_6
.LBB0_5:
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
.LBB0_6:
v_lshlrev_b64 v[5:6], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_store_b64 v[5:6], v[3:4], off
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s8
s_ashr_i32 s5, s6, 31
s_mov_b32 s4, s6
s_mov_b32 s6, exec_lo
v_cmpx_gt_u64_e64 s[4:5], v[1:2]
s_cbranch_execz .LBB0_14
s_cmp_lt_i32 s7, 1
s_cbranch_scc1 .LBB0_12
v_add_co_u32 v4, s0, s0, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, null, s1, 0, s0
v_mov_b32_e32 v3, 0
.LBB0_10:
global_load_u8 v0, v[4:5], off
v_add_co_u32 v4, vcc_lo, v4, s4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_add_i32 s7, s7, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s7, 0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v3, v0
s_cbranch_scc0 .LBB0_10
v_mov_b32_e32 v4, 0
s_branch .LBB0_13
.LBB0_12:
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
.LBB0_13:
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
.LBB0_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| KernelRect | 9,030 | 1,208 | stackv2-00001-of-00015 |
// Demangled: KernelSobel(unsigned char*, unsigned char*, unsigned char*, int, int, unsigned char)
Function : _Z11KernelSobelPhS_S_iih
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R2, SR_TID.X &wr=0x0 ?trans7;
S2UR UR6, SR_CTAID.X &wr=0x0 ?trans1;
LDCU.128 UR8, c[0x0][0x380] &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans6;
LDC R3, c[0x0][0x360] &wr=0x0 ?trans2;
IMAD R2, R3, UR6, R2 &req={0} ?WAIT2_END_GROUP;
HFMA2 R3, -RZ, RZ, 0, 0 ?trans1;
LDCU.U8 UR6, c[0x0][0x3a0] &wr=0x0 ?trans4;
IADD.64 R4, R2.reuse, UR8 &req={1} ?trans2;
IADD.64 R6, R2.reuse, UR10 ?trans2;
LDCU.64 UR8, c[0x0][0x390] &wr=0x1 ?trans3;
LDG.E.U8 R4, desc[UR4][R4.64] &req={2} &wr=0x2 ?trans4;
LDG.E.U8 R6, desc[UR4][R6.64] &wr=0x2 ?trans1;
IADD.64 R2, R2, UR8 &req={1} ?WAIT2_END_GROUP;
VIMNMX.U16x2 R0, R4.reuse, R6.reuse, PT &req={2} ?trans1;
VIMNMX.U16x2 R5, R4, R6, !PT ?WAIT4_END_GROUP;
IADD3 R9, PT, PT, RZ, -R0, RZ ?trans2;
PRMT R0, R5, 0x7610, R0 ?trans2;
PRMT R9, R9, 0x7710, RZ ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R0, R9, RZ ?WAIT4_END_GROUP;
LOP3.LUT R0, R0, 0xffff, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R0, UR6, PT &req={0} ?WAIT5_END_GROUP;
SEL R5, RZ, 0xffffffff, !P0 ?WAIT5_END_GROUP;
STG.E.U8 desc[UR4][R2.64], R5 ?trans1;
EXIT ?trans5;
BRA 0x1a0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: KernelSobel(unsigned char*, unsigned char*, unsigned char*, int, int, unsigned char)
_ZL11KernelSobelPhS_S_iih:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s0, s[0:1], 0x20
s_clause 0x1
global_load_u8 v0, v1, s[4:5]
global_load_u8 v2, v1, s[6:7]
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s0, 0xff
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, 0, v0
v_max_i32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmp_le_u32_e32 vcc_lo, s0, v0
v_cndmask_b32_e64 v0, 0, -1, vcc_lo
global_store_b8 v1, v0, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| KernelSobel | 725 | 438 | stackv2-00001-of-00015 |
// Demangled: update_jacobi_2gpu0(double*, double*, double*, double*, int, double, double)
Function : _Z19update_jacobi_2gpu0PdS_S_S_idd
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.Y &wr=0x1 ?trans7;
LDC R5, c[0x0][0x360] &wr=0x2 ?trans1;
BSSY.RECONVERGENT B0, 0x400 ?trans1;
S2R R2, SR_TID.X &wr=0x2 ?trans6;
S2UR UR5, SR_CTAID.Y &wr=0x1 ?trans8;
LDC R0, c[0x0][0x364] &wr=0x1 ?trans8;
LDC R7, c[0x0][0x3a0] &wr=0x3 ?trans8;
S2UR UR4, SR_CTAID.X &wr=0x2 ?trans1;
IMAD R3, R0, UR5, R3 &req={1} ?WAIT5_END_GROUP;
IADD3 R4, PT, PT, R3, 0x1, RZ ?trans2;
LEA.HI R0, R7, R7, RZ, 0x1 &req={3} ?trans1;
IMAD R2, R5, UR4, R2 &req={2} ?WAIT3_END_GROUP;
SHF.R.S32.HI R5, RZ, 0x1, R0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
IADD3 R0, PT, PT, R2, 0x1, RZ ?WAIT3_END_GROUP;
ISETP.NE.AND P1, PT, R4.reuse, R5.reuse, PT ?trans1;
ISETP.GE.AND P0, PT, R4, R5, PT ?trans1;
IADD3 R4, PT, PT, R7, 0x2, RZ ?WAIT3_END_GROUP;
ISETP.GT.OR P1, PT, R0.reuse, R7.reuse, P1 ?trans1;
ISETP.GT.OR P0, PT, R0, R7, P0 ?WAIT12_END_GROUP;
@P1 BRA 0x3f0 &req={1,0} ?trans5;
LDC.64 R6, c[0x0][0x388] &wr=0x0 ?trans1;
IMAD R9, R3.reuse, R4.reuse, R0 ?trans1;
LDCU.64 UR6, c[0x0][0x3a8] &wr=0x1 ?trans1;
IMAD R5, R3, R4, R4 ?WAIT5_END_GROUP;
LDC.64 R12, c[0x0][0x380] &wr=0x2 ?trans1;
IADD3 R11, PT, PT, R2, 0x2, R5 ?WAIT7_END_GROUP;
LDC.64 R18, c[0x0][0x398] &wr=0x3 ?trans1;
IADD3 R5, PT, PT, R0, R5, RZ ?trans1;
IMAD.WIDE R6, R2, 0x8, R6 &req={0} ?WAIT6_END_GROUP;
LDG.E.64 R6, desc[UR4][R6.64+0x8] &wr=0x4 ?trans1;
IMAD.WIDE R8, R9, 0x8, R12 &req={2} ?WAIT4_END_GROUP;
IMAD.WIDE R12, R11, 0x8, R12 ?trans2;
LDG.E.64 R8, desc[UR4][R8.64] &wr=0x4 ?trans2;
IMAD.WIDE R18, R5.reuse, 0x8, R18 &req={3} ?trans2;
LDG.E.64 R14, desc[UR4][R12.64] &wr=0x2 ?trans4;
LDG.E.64 R16, desc[UR4][R12.64+-0x10] &wr=0x3 ?trans4;
LDG.E.64 R18, desc[UR4][R18.64] &wr=0x1 ?trans1;
DADD R10, R6, R8 &req={4} &rd=0x0 &wr=0x2 ?trans2;
LDC.64 R6, c[0x0][0x390] &req={0} &wr=0x0 ?trans2;
IMAD.WIDE R6, R5, 0x8, R6 &req={0} ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R10, R10, R14 &req={2} &wr=0x3 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R10, R10, R16 &req={3} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R18, UR6, R10 &req={1} &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x3b0] &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R10, R10, UR6 &req={0} &wr=0x0 ?trans2;
STG.E.64 desc[UR4][R6.64], R10 &req={0} &rd=0x0 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
@P0 EXIT ?trans5;
LDC.64 R6, c[0x0][0x380] &req={0} &wr=0x0 ?trans1;
IADD3 R5, PT, PT, R3.reuse, 0x2, RZ ?trans1;
IMAD R15, R3, R4, R0 ?trans1;
LDCU.64 UR6, c[0x0][0x3a8] &wr=0x1 ?trans3;
IMAD R17, R4.reuse, R5.reuse, -R4 ?trans2;
LDC.64 R12, c[0x0][0x398] &wr=0x2 ?trans1;
IMAD R3, R4, R5, R0 ?trans2;
IADD3 R5, PT, PT, R2, 0x2, R17 ?WAIT2_END_GROUP;
IADD3 R17, PT, PT, R0, R17, RZ ?trans1;
IMAD.WIDE R2, R3, 0x8, R6 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE R14, R15, 0x8, R6.reuse ?trans2;
LDG.E.64 R2, desc[UR4][R2.64] &wr=0x3 ?trans2;
IMAD.WIDE R6, R5, 0x8, R6 ?trans2;
LDG.E.64 R4, desc[UR4][R14.64] &wr=0x3 ?trans2;
IMAD.WIDE R12, R17.reuse, 0x8, R12 &req={2} ?trans2;
LDG.E.64 R8, desc[UR4][R6.64] &wr=0x2 ?trans4;
LDG.E.64 R10, desc[UR4][R6.64+-0x10] &wr=0x4 ?trans4;
LDG.E.64 R12, desc[UR4][R12.64] &wr=0x1 ?trans1;
DADD R4, R2, R4 &req={3} &rd=0x0 &wr=0x2 ?trans2;
LDC.64 R2, c[0x0][0x390] &req={0} &wr=0x0 ?trans2;
IMAD.WIDE R2, R17, 0x8, R2 &req={0} ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R4, R4, R8 &req={2} &wr=0x4 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R4, R4, R10 &req={4} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R4, R12, UR6, R4 &req={1} &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x3b0] &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R4, R4, UR6 &req={0} &wr=0x0 ?trans2;
STG.E.64 desc[UR4][R2.64], R4 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x6c0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: update_jacobi_2gpu0(double*, double*, double*, double*, int, double, double)
_Z19update_jacobi_2gpu0PdS_S_S_idd:
s_clause 0x3
s_load_b32 s3, s[0:1], 0x44
s_load_b32 s2, s[0:1], 0x20
s_load_b128 s[16:19], s[0:1], 0x28
s_load_b256 s[4:11], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s0, s3, 16
s_and_b32 s1, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s1, v[2:3]
v_mad_u64_u32 v[2:3], null, s15, s0, v[4:5]
s_lshr_b32 s0, s2, 31
s_add_i32 s0, s2, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, 1, v0
s_ashr_i32 s1, s0, 1
v_add_nc_u32_e32 v4, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ge_i32_e32 vcc_lo, s2, v3
v_cmp_eq_u32_e64 s0, s1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s3, s0
s_cbranch_execz .LBB2_2
s_add_i32 s12, s2, 2
v_ashrrev_i32_e32 v1, 31, v0
v_mul_lo_u32 v9, v2, s12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 3, v[0:1]
v_add_nc_u32_e32 v5, v9, v3
v_add_nc_u32_e32 v1, s12, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v7, s0, s6, v7
v_add_co_ci_u32_e64 v8, s0, s7, v8, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v6, 31, v5
v_add_nc_u32_e32 v9, v1, v0
v_add_nc_u32_e32 v13, v1, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[5:6], 3, v[5:6]
v_add_nc_u32_e32 v10, 2, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v14, 31, v13
v_ashrrev_i32_e32 v11, 31, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v5, s0, s4, v5
v_add_co_ci_u32_e64 v6, s0, s5, v6, s0
global_load_b64 v[7:8], v[7:8], off offset:8
global_load_b64 v[5:6], v[5:6], off
v_lshlrev_b64 v[10:11], 3, v[10:11]
v_lshlrev_b64 v[13:14], 3, v[13:14]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v10, s0, s4, v10
v_add_co_ci_u32_e64 v11, s0, s5, v11, s0
global_load_b64 v[11:12], v[10:11], off
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 3, v[9:10]
v_add_co_u32 v9, s0, s4, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v10, s0, s5, v10, s0
v_add_co_u32 v15, s0, s10, v13
v_add_co_ci_u32_e64 v16, s0, s11, v14, s0
global_load_b64 v[9:10], v[9:10], off
global_load_b64 v[15:16], v[15:16], off
s_waitcnt vmcnt(3)
v_add_f64 v[5:6], v[7:8], v[5:6]
v_add_co_u32 v7, s0, s8, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v8, s0, s9, v14, s0
s_waitcnt vmcnt(2)
v_add_f64 v[5:6], v[5:6], v[11:12]
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[5:6], v[9:10]
s_waitcnt vmcnt(0)
v_fma_f64 v[5:6], v[15:16], s[16:17], v[5:6]
s_delay_alu instid0(VALU_DEP_1)
v_mul_f64 v[5:6], v[5:6], s[18:19]
global_store_b64 v[7:8], v[5:6], off
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s3
v_cmp_gt_i32_e64 s0, s1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB2_4
s_add_i32 s2, s2, 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, s2
v_lshl_add_u32 v6, s2, 1, v2
v_add_nc_u32_e32 v4, v2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v1, v6, v3
v_ashrrev_i32_e32 v5, 31, v4
v_subrev_nc_u32_e32 v10, s2, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[4:5], 3, v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v6, v10, v0
v_add_nc_u32_e32 v10, v10, v3
v_lshlrev_b64 v[1:2], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v7, 2, v6
v_ashrrev_i32_e32 v11, 31, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
v_ashrrev_i32_e32 v8, 31, v7
s_clause 0x1
global_load_b64 v[1:2], v[1:2], off
global_load_b64 v[4:5], v[4:5], off
v_lshlrev_b64 v[10:11], 3, v[10:11]
v_lshlrev_b64 v[7:8], 3, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
global_load_b64 v[8:9], v[7:8], off
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 3, v[6:7]
v_add_co_u32 v6, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
v_add_co_u32 v12, vcc_lo, s10, v10
v_add_co_ci_u32_e32 v13, vcc_lo, s11, v11, vcc_lo
global_load_b64 v[6:7], v[6:7], off
global_load_b64 v[12:13], v[12:13], off
s_waitcnt vmcnt(3)
v_add_f64 v[0:1], v[1:2], v[4:5]
v_add_co_u32 v2, vcc_lo, s8, v10
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v11, vcc_lo
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[0:1], v[8:9]
s_waitcnt vmcnt(1)
v_add_f64 v[0:1], v[0:1], v[6:7]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[0:1], v[12:13], s[16:17], v[0:1]
v_mul_f64 v[0:1], v[0:1], s[18:19]
global_store_b64 v[2:3], v[0:1], off
.LBB2_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| update_jacobi_2gpu0 | 2,414 | 3,299 | stackv2-00001-of-00015 |
// Demangled: update_jacobi_2gpu1(double*, double*, double*, double*, int, double, double)
Function : _Z19update_jacobi_2gpu1PdS_S_S_idd
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R4, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
BSSY.RECONVERGENT B0, 0x440 ?trans1;
S2R R0, SR_TID.Y &wr=0x2 ?trans6;
LDC R3, c[0x0][0x360] &wr=0x1 ?trans8;
LDC R6, c[0x0][0x3a0] &wr=0x3 ?trans1;
IMAD R4, R3, UR4, R4 &req={1} ?WAIT7_END_GROUP;
S2UR UR4, SR_CTAID.Y &wr=0x2 ?trans1;
IADD3 R2, PT, PT, R4, 0x1, RZ ?WAIT7_END_GROUP;
LDC R3, c[0x0][0x364] &wr=0x2 ?trans1;
ISETP.GT.AND P0, PT, R2, R6, PT &req={3} ?WAIT13_END_GROUP;
@!P0 LEA.HI R5, R6, R6, RZ, 0x1 ?WAIT4_END_GROUP;
@!P0 SHF.R.S32.HI R5, RZ, 0x1, R5 ?trans1;
IMAD R0, R3, UR4, R0 &req={2} ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans4;
ISETP.NE.AND P1, PT, R0.reuse, RZ, PT ?trans1;
ISETP.LT.AND P0, PT, R0, R5, !P0 ?trans1;
IADD3 R5, PT, PT, R6, 0x2, RZ ?WAIT3_END_GROUP;
ISETP.GT.OR P1, PT, R2, R6, P1 ?trans1;
ISETP.EQ.OR P0, PT, R0, RZ, !P0 ?WAIT12_END_GROUP;
@P1 BRA 0x430 &req={1,0} ?trans5;
LDC.64 R8, c[0x0][0x388] &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x380] &wr=0x1 ?trans1;
IMAD R12, R5, R6, RZ ?trans1;
SHF.R.S32.HI R7, RZ, 0x1f, R6 ?trans2;
SHF.R.S32.HI R3, RZ, 0x1f, R2 ?trans2;
LEA.HI R13, R12, R12, RZ, 0x1 ?trans1;
LDC.64 R10, c[0x0][0x380] &wr=0x2 ?trans2;
IADD.64 R6, R2, R6 ?WAIT3_END_GROUP;
LEA.HI.SX32 R13, R13, R2, 0x1f ?WAIT3_END_GROUP;
LDC.64 R16, c[0x0][0x398] &wr=0x3 ?trans1;
LEA R18, P1, R6, UR6, 0x3 &req={1} ?WAIT4_END_GROUP;
LEA.HI.X R19, R6, UR7, R7, 0x3, P1 ?trans1;
IMAD.WIDE R8, R13, 0x8, R8 &req={0} ?trans1;
LDCU.64 UR6, c[0x0][0x3a8] &wr=0x0 ?trans3;
LDG.E.64 R6, desc[UR4][R18.64+0x10] &wr=0x4 ?trans4;
LDG.E.64 R8, desc[UR4][R8.64] &wr=0x4 ?trans1;
IMAD.WIDE R10, R4, 0x8, R10 &req={2} ?WAIT5_END_GROUP;
LDG.E.64 R12, desc[UR4][R10.64+0x10] &wr=0x2 ?trans1;
IMAD.WIDE R16, R4, 0x8, R16 &req={3} ?WAIT3_END_GROUP;
LDG.E.64 R14, desc[UR4][R10.64] &wr=0x3 ?trans4;
LDG.E.64 R16, desc[UR4][R16.64+0x8] &wr=0x0 ?trans1;
DADD R6, R6, R8 &req={4} &rd=0x1 &wr=0x2 ?trans2;
LDC.64 R8, c[0x0][0x390] &req={1} &wr=0x1 ?trans2;
IMAD.WIDE R8, R4, 0x8, R8 &req={1} ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R6, R6, R12 &req={2} &wr=0x3 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R6, R6, R14 &req={3} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R6, R16, UR6, R6 &req={0} &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x3b0] &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R6, R6, UR6 &req={0} &wr=0x0 ?trans2;
STG.E.64 desc[UR4][R8.64+0x8], R6 &req={0} &rd=0x0 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
@P0 EXIT ?trans5;
LDC.64 R10, c[0x0][0x380] &wr=0x1 ?trans1;
IMAD R6, R0.reuse, R5, R4 &req={0} ?trans1;
IADD3 R4, PT, PT, R0.reuse, 0x1, RZ ?trans2;
IADD3 R3, PT, PT, R0, -0x1, RZ ?WAIT4_END_GROUP;
LDC.64 R16, c[0x0][0x398] &wr=0x0 ?trans1;
IMAD R7, R5.reuse, R4, R2.reuse ?trans1;
IADD3 R13, PT, PT, R6, 0x2, RZ ?trans1;
IMAD R3, R5, R3, R2.reuse ?trans1;
LDCU.64 UR6, c[0x0][0x3a8] &wr=0x2 ?trans1;
IMAD R19, R0, R5, R2 ?trans2;
IMAD.WIDE R6, R7, 0x8, R10 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE R8, R3, 0x8, R10.reuse ?trans2;
LDG.E.64 R6, desc[UR4][R6.64] &wr=0x3 ?trans2;
IMAD.WIDE R10, R13, 0x8, R10 ?trans2;
LDG.E.64 R8, desc[UR4][R8.64] &wr=0x3 ?trans2;
IMAD.WIDE R4, R19.reuse, 0x8, R16 &req={0} ?trans2;
LDG.E.64 R12, desc[UR4][R10.64] &wr=0x4 ?trans4;
LDG.E.64 R14, desc[UR4][R10.64+-0x10] &wr=0x5 ?trans4;
LDG.E.64 R4, desc[UR4][R4.64] &wr=0x2 ?trans1;
DADD R2, R6, R8 &req={3} &rd=0x0 &wr=0x4 ?trans2;
LDC.64 R6, c[0x0][0x390] &req={0} &wr=0x0 ?trans2;
IMAD.WIDE R6, R19, 0x8, R6 &req={0} ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R2, R2, R12 &req={4} &wr=0x5 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R2, R2, R14 &req={5} &wr=0x2 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R4, UR6, R2 &req={2} &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x3b0] &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R2, R2, UR6 &req={0} &wr=0x0 ?trans2;
STG.E.64 desc[UR4][R6.64], R2 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x710;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: update_jacobi_2gpu1(double*, double*, double*, double*, int, double, double)
_Z19update_jacobi_2gpu1PdS_S_S_idd:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x44
s_load_b32 s2, s[0:1], 0x20
v_and_b32_e32 v3, 0x3ff, v0
s_clause 0x1
s_load_b128 s[16:19], s[0:1], 0x28
s_load_b256 s[4:11], s[0:1], 0x0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s14, s0, v[3:4]
s_lshr_b32 s0, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, s15, s0, v[0:1]
v_add_nc_u32_e32 v0, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_ge_i32_e32 vcc_lo, s2, v0
v_cmp_eq_u32_e64 s0, 0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB3_2
s_add_i32 s0, s2, 2
v_ashrrev_i32_e32 v2, 31, v0
s_mul_i32 s0, s0, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshr_b32 s3, s0, 31
s_add_i32 s0, s0, s3
s_ashr_i32 s3, s2, 31
s_ashr_i32 s0, s0, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, s0, v0
v_add_co_u32 v6, s0, v0, s2
v_add_co_ci_u32_e64 v7, s0, s3, v2, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v5, 31, v4
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[6:7], 3, v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 3, v[4:5]
v_lshlrev_b64 v[8:9], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v6, s0, s4, v6
v_add_co_ci_u32_e64 v7, s0, s5, v7, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s0, s6, v4
v_add_co_ci_u32_e64 v5, s0, s7, v5, s0
global_load_b64 v[6:7], v[6:7], off offset:16
global_load_b64 v[4:5], v[4:5], off
v_add_co_u32 v10, s0, s4, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v11, s0, s5, v9, s0
s_clause 0x1
global_load_b64 v[12:13], v[10:11], off offset:16
global_load_b64 v[10:11], v[10:11], off
v_add_co_u32 v14, s0, s10, v8
v_add_co_ci_u32_e64 v15, s0, s11, v9, s0
global_load_b64 v[14:15], v[14:15], off offset:8
s_waitcnt vmcnt(3)
v_add_f64 v[4:5], v[6:7], v[4:5]
v_add_co_u32 v6, s0, s8, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v7, s0, s9, v9, s0
s_waitcnt vmcnt(2)
v_add_f64 v[4:5], v[4:5], v[12:13]
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[4:5], v[10:11]
s_waitcnt vmcnt(0)
v_fma_f64 v[4:5], v[14:15], s[16:17], v[4:5]
s_delay_alu instid0(VALU_DEP_1)
v_mul_f64 v[4:5], v[4:5], s[18:19]
global_store_b64 v[6:7], v[4:5], off offset:8
.LBB3_2:
s_or_b32 exec_lo, exec_lo, s1
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB3_5
s_lshr_b32 s0, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s2, s0
s_ashr_i32 s0, s0, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s0, v3
v_cmp_lt_i32_e64 s0, 0, v3
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB3_5
v_add_nc_u32_e32 v2, -1, v3
s_add_i32 s2, s2, 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v10, v3, s2
v_mad_u64_u32 v[4:5], null, v2, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v1, v10, v1
v_add_nc_u32_e32 v10, v10, v0
v_lshl_add_u32 v6, s2, 1, v4
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v2, 2, v1
v_ashrrev_i32_e32 v11, 31, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[4:5], 3, v[4:5]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[10:11], 3, v[10:11]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[6:7], 3, v[6:7]
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
s_clause 0x1
global_load_b64 v[6:7], v[6:7], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b64 v[8:9], v[2:3], off
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 3, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v12, vcc_lo, s10, v10
v_add_co_ci_u32_e32 v13, vcc_lo, s11, v11, vcc_lo
global_load_b64 v[1:2], v[1:2], off
global_load_b64 v[12:13], v[12:13], off
s_waitcnt vmcnt(3)
v_add_f64 v[3:4], v[6:7], v[4:5]
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[3:4], v[3:4], v[8:9]
s_waitcnt vmcnt(1)
v_add_f64 v[0:1], v[3:4], v[1:2]
v_add_co_u32 v2, vcc_lo, s8, v10
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v11, vcc_lo
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[0:1], v[12:13], s[16:17], v[0:1]
v_mul_f64 v[0:1], v[0:1], s[18:19]
global_store_b64 v[2:3], v[0:1], off
.LBB3_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| update_jacobi_2gpu1 | 2,571 | 3,175 | stackv2-00001-of-00015 |
// Demangled: update_jacobi_gpu(double*, double*, double*, int, double, double)
Function : _Z17update_jacobi_gpuPdS_S_idd
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
LDCU UR8, c[0x0][0x398] &wr=0x1 ?trans2;
UISETP.GE.AND UP0, UPT, UR8, 0x1, UPT &req={1} ?WAIT6_END_GROUP;
PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x8 ?WAIT13_END_GROUP;
@!P0 EXIT ?trans5;
ULOP3.LUT UR9, UR8, 0x7ffffffc, URZ, 0xc0, !UPT ?trans1;
UIADD3 UR20, UPT, UPT, UR8, 0x2, URZ ?trans1;
LDCU.64 UR18, c[0x0][0x358] &wr=0x1 ?trans1;
USHF.L.U32 UR8, UR8, 0x2, URZ ?trans1;
UIADD3 UR9, UPT, UPT, -UR9, URZ, URZ ?trans1;
UMOV UR22, 0x1 ?WAIT11_END_GROUP;
LDCU UR21, c[0x0][0x398] &req={2} &wr=0x2 ?trans1;
UMOV UR16, 0x1 ?trans1;
UISETP.GE.U32.AND UP0, UPT, UR21, 0x4, UPT &req={2} ?WAIT6_END_GROUP;
PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x8 ?WAIT13_END_GROUP;
@!P0 BRA 0xcb0 &req={3,0} ?trans5;
LDC.64 R8, c[0x0][0x390] &wr=0x2 ?trans1;
UIMAD UR23, UR21, 0x3, URZ ?trans1;
UIADD3 UR24, UPT, UPT, UR21, UR21, URZ ?trans1;
UIADD3 UR17, UPT, UPT, UR22, 0x6, URZ ?trans1;
UIMAD UR5, UR21, 0x5, UR22 ?trans1;
UIADD3 UR11, UPT, UPT, UR23, UR22, URZ ?trans1;
UIADD3 UR16, UPT, UPT, UR24, UR22, URZ ?trans1;
UIADD3 UR10, UPT, UPT, UR8, UR22, URZ ?trans1;
LDC.64 R6, c[0x0][0x380] &wr=0x3 ?trans1;
UIADD3 UR6, UPT, UPT, UR20, UR22, URZ ?trans1;
MOV R26, UR17 ?trans1;
MOV R17, UR11 ?trans1;
MOV R27, UR16 ?trans1;
MOV R16, UR5 ?trans1;
MOV R0, UR10 ?trans1;
LDCU.128 UR12, c[0x0][0x3a0] &wr=0x4 ?trans1;
LDC.64 R4, c[0x0][0x388] &wr=0x1 ?trans1;
UMOV UR4, URZ ?trans1;
UIMAD.WIDE.U32 UR6, UR6, 0x8, URZ ?trans1;
UMOV UR5, UR9 ?trans1;
UMOV UR10, UR8 ?WAIT4_END_GROUP;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans6;
IADD3 R25, PT, PT, R26, -0x6, RZ ?trans2;
IADD3 R31, PT, PT, R27, 0x4, RZ ?trans1;
IADD.64 R22, R6, UR6 &req={3,0} ?trans2;
IADD.64 R28, R8, UR6 &req={2} ?trans2;
IMAD.WIDE R24, R25, 0x8, R6.reuse ?trans2;
LDG.E.64 R18, desc[UR18][R22.64+0x8] &req={1} &wr=0x2 ?trans2;
IMAD.WIDE.U32 R14, R31, 0x8, R6 ?WAIT2_END_GROUP;
LDG.E.64 R24, desc[UR18][R24.64] &wr=0x3 ?trans4;
LDG.E.64 R20, desc[UR18][R14.64] &wr=0x3 ?trans4;
LDG.E.64 R12, desc[UR18][R22.64+-0x8] &wr=0x5 ?trans4;
LDG.E.64 R10, desc[UR18][R28.64] &req={4} &wr=0x4 ?trans1;
UIADD3 UR11, UPT, UPT, UR24, 0x4, URZ ?trans1;
IADD.64 R32, R4, UR6 ?WAIT2_END_GROUP;
DADD R20, R20, R24 &req={3} &wr=0x2 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R18, R20, R18 &req={2} &rd=0x1 &wr=0x5 ?trans2;
IADD3 R21, PT, PT, R17, 0x6, RZ &req={1} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R12, R18, R12 &req={5} &rd=0x1 &wr=0x4 ?trans2;
MOV R18, UR11 &req={1} ?trans1;
HFMA2 R19, -RZ, RZ, 0, 0 ?WAIT15_END_GROUP;
NOP ?trans1;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, R10, UR12, R12 &req={4} &rd=0x1 &wr=0x2 ?trans2;
MOV R10, UR22 &req={1} ?trans1;
MOV R11, RZ ?WAIT5_END_GROUP;
IADD.64 R18, R18, R10 ?WAIT5_END_GROUP;
LEA R28, P0, R18, R2, 0x3 &req={0} ?WAIT4_END_GROUP;
LEA.HI.X R29, R18, R3, R19, 0x3, P0 ?trans1;
IMAD.WIDE R18, R31, 0x8, R6 ?WAIT15_END_GROUP;
NOP ?trans1;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R34, R12, UR14 &req={2} &rd=0x0 &wr=0x1 ?trans2;
IMAD.WIDE.U32 R12, R21, 0x8, R6 &req={0} ?trans1;
STG.E.64 desc[UR18][R32.64], R34 &req={1} &rd=0x0 ?trans3;
IMAD.WIDE.U32 R20, R31, 0x8, R8 ?trans1;
LDG.E.64 R22, desc[UR18][R22.64] &wr=0x2 ?trans4;
LDG.E.64 R24, desc[UR18][R12.64] &wr=0x2 ?trans4;
LDG.E.64 R28, desc[UR18][R28.64+0x8] &wr=0x3 ?trans4;
LDG.E.64 R18, desc[UR18][R18.64+-0x8] &wr=0x4 ?trans4;
LDG.E.64 R20, desc[UR18][R20.64] &wr=0x5 ?trans1;
UIADD3 UR11, UPT, UPT, UR23, 0x6, URZ ?trans1;
MOV R33, RZ &req={0} ?WAIT5_END_GROUP;
MOV R32, UR11 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R24, R24, R22 &req={2} &rd=0x0 &wr=0x3 ?trans2;
IADD.64 R22, R10, R32 &req={0} ?trans2;
IMAD.WIDE.U32 R32, R31, 0x8, R4 ?trans1;
IADD3 R31, PT, PT, R17, 0x6, RZ ?WAIT15_END_GROUP;
NOP ?WAIT14_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R24, R24, R28 &req={3} &rd=0x0 &wr=0x4 ?trans2;
IADD3 R29, PT, PT, R0, 0x8, RZ &req={0} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R24, R24, R18 &req={4} &rd=0x0 &wr=0x5 ?trans2;
LEA R18, P0, R22, R2, 0x3 &req={0} ?WAIT4_END_GROUP;
LEA.HI.X R19, R22, R3, R23, 0x3, P0 ?trans1;
IMAD.WIDE.U32 R22, R31, 0x8, R8 ?WAIT15_END_GROUP;
NOP ?WAIT12_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R24, R20, UR12, R24 &req={5} &rd=0x0 &wr=0x1 ?trans2;
IMAD.WIDE R20, R31, 0x8, R6 &req={0} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R34, R24, UR14 &req={1} &rd=0x0 &wr=0x1 ?trans2;
IMAD.WIDE.U32 R24, R29, 0x8, R6 &req={0} ?trans1;
STG.E.64 desc[UR18][R32.64], R34 &req={1} &rd=0x0 ?trans4;
LDG.E.64 R14, desc[UR18][R14.64] &wr=0x2 ?trans4;
LDG.E.64 R24, desc[UR18][R24.64] &wr=0x2 ?trans4;
LDG.E.64 R18, desc[UR18][R18.64+0x8] &wr=0x3 ?trans4;
LDG.E.64 R20, desc[UR18][R20.64+-0x8] &wr=0x4 ?trans4;
LDG.E.64 R22, desc[UR18][R22.64] &wr=0x5 ?trans1;
UIADD3 UR11, UPT, UPT, UR10, 0x8, URZ ?trans1;
MOV R35, RZ &req={0} ?WAIT5_END_GROUP;
MOV R34, UR11 ?WAIT5_END_GROUP;
IADD.64 R34, R10, R34 ?WAIT5_END_GROUP;
LEA R10, P0, R34, R2, 0x3 ?WAIT4_END_GROUP;
LEA.HI.X R11, R34, R3, R35, 0x3, P0 ?WAIT15_END_GROUP;
NOP ?WAIT5_END_GROUP;
DADD R36, R24, R14 &req={2} &rd=0x0 &wr=0x3 ?trans2;
IMAD.WIDE R24, R29, 0x8, R6 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R14, R29, 0x8, R8 ?WAIT15_END_GROUP;
NOP ?WAIT13_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R36, R36, R18 &req={3} &rd=0x0 &wr=0x4 ?trans2;
IMAD.WIDE.U32 R18, R31, 0x8, R4 &req={0} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R32, R36, R20 &req={4} &rd=0x0 &wr=0x5 ?trans2;
IADD3 R21, PT, PT, R16, 0xa, RZ &req={0} ?WAIT5_END_GROUP;
IMAD.WIDE.U32 R20, R21, 0x8, R6 ?WAIT15_END_GROUP;
NOP ?WAIT12_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R32, R22, UR12, R32 &req={5} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R32, R32, UR14 &req={0} &wr=0x0 ?trans2;
STG.E.64 desc[UR18][R18.64], R32 &req={0} &rd=0x0 ?trans4;
LDG.E.64 R12, desc[UR18][R12.64] &wr=0x2 ?trans4;
LDG.E.64 R20, desc[UR18][R20.64] &wr=0x2 ?trans4;
LDG.E.64 R10, desc[UR18][R10.64+0x8] &wr=0x3 ?trans4;
LDG.E.64 R24, desc[UR18][R24.64+-0x8] &wr=0x4 ?trans4;
LDG.E.64 R14, desc[UR18][R14.64] &wr=0x5 ?trans1;
UIADD3 UR5, UPT, UPT, UR5, 0x4, URZ ?WAIT6_END_GROUP;
ISETP.NE.AND P0, PT, RZ, UR5, PT ?trans1;
UIADD3 UR11, UPT, UPT, UR8, 0x8, URZ ?trans1;
IMAD.WIDE.U32 R18, R29, 0x8, R4 &req={0} ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x4, URZ ?trans2;
UIADD3 UR10, UPT, UPT, UR11, UR10, URZ ?trans1;
UIADD3 UR23, UPT, UPT, UR11, UR23, URZ ?trans1;
UIADD3 UR24, UPT, UPT, UR11, UR24, URZ ?trans1;
UIMAD.WIDE.U32 UR6, UR11, 0x8, UR6 ?trans2;
IADD3 R16, PT, PT, R16, UR11, RZ ?WAIT2_END_GROUP;
IADD3 R0, PT, PT, R0, UR11, RZ ?trans2;
IADD3 R17, PT, PT, R17, UR11, RZ ?trans2;
IADD3 R27, PT, PT, R27, UR11, RZ ?trans2;
IADD3 R26, PT, PT, R26, UR11, RZ ?WAIT15_END_GROUP;
NOP ?trans2;
DADD R22, R20, R12 &req={2} &wr=0x3 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R22, R22, R10 &req={3} &wr=0x4 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R22, R22, R24 &req={4} &wr=0x5 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R22, R14, UR12, R22 &req={5} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R22, R22, UR14 &req={0} &wr=0x0 ?trans2;
STG.E.64 desc[UR18][R18.64], R22 &req={0} &rd=0x0 ?trans1;
@P0 BRA 0x260 ?trans5;
UIADD3 UR16, UPT, UPT, UR4, 0x1, URZ ?WAIT12_END_GROUP;
ULOP3.LUT UP0, UR4, UR21, 0x3, URZ, 0xc0, !UPT ?WAIT6_END_GROUP;
PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x8 ?WAIT13_END_GROUP;
@!P0 BRA 0x1680 ?trans5;
UISETP.NE.AND UP0, UPT, UR4, 0x1, UPT ?trans1;
ULOP3.LUT UP1, URZ, UR21, 0x1, URZ, 0xc0, !UPT ?WAIT5_END_GROUP;
PLOP3.LUT P1, PT, PT, PT, UP0, 0x80, 0x8 ?trans2;
PLOP3.LUT P0, PT, PT, PT, UP1, 0x80, 0x8 ?WAIT11_END_GROUP;
@!P1 BRA 0x1320 ?trans5;
LDCU.128 UR4, c[0x0][0x380] &wr=0x2 ?trans1;
LDC.64 R2, c[0x0][0x380] &wr=0x3 ?trans1;
MOV R6, UR22 ?trans1;
MOV R7, RZ ?trans1;
LDCU.64 UR14, c[0x0][0x390] &wr=0x4 ?trans1;
HFMA2 R5, -RZ, RZ, 0, 0 ?trans1;
UIADD3 UR10, UPT, UPT, UR16, -0x1, URZ ?trans1;
UIMAD UR11, UR20, UR16, URZ ?trans1;
UIMAD UR13, UR20, UR16, UR20 ?trans2;
UIMAD UR10, UR20, UR10, UR22 ?trans1;
UIADD3 UR12, UPT, UPT, UR11, UR22, URZ ?trans1;
UIADD3 UR17, UPT, UPT, UR13, UR22, URZ ?trans1;
MOV R4, UR11 ?trans1;
UIMAD.WIDE UR10, UR10, 0x8, UR4 &req={2} ?WAIT2_END_GROUP;
UIMAD.WIDE.U32 UR24, UR17, 0x8, UR4 ?trans2;
IADD.64 R4, R6, R4 ?trans2;
UIMAD.WIDE UR26, UR12, 0x8, UR4 ?trans1;
MOV.64 R10, UR10 ?trans2;
MOV.64 R18, UR24 &req={0} ?WAIT3_END_GROUP;
LEA R12, P1, R4.reuse, R2, 0x3 &req={3} ?trans1;
UIMAD.WIDE.U32 UR10, UR12, 0x8, UR14 &req={4} ?trans2;
LDG.E.64 R8, desc[UR18][R18.64] &req={1} &wr=0x2 ?trans1;
LEA.HI.X R13, R4, R3, R5, 0x3, P1 ?trans1;
MOV.64 R4, UR26 ?trans2;
LDG.E.64 R10, desc[UR18][R10.64] &wr=0x2 ?trans1;
MOV.64 R16, UR10 ?trans2;
LDCU.128 UR24, c[0x0][0x3a0] &wr=0x0 ?trans1;
LDG.E.64 R12, desc[UR18][R12.64+0x8] &wr=0x3 ?trans4;
LDG.E.64 R14, desc[UR18][R4.64+-0x8] &wr=0x4 ?trans4;
LDG.E.64 R16, desc[UR18][R16.64] &wr=0x0 ?trans1;
UIADD3 UR16, UPT, UPT, UR16, 0x2, URZ ?trans1;
UIMAD.WIDE.U32 UR10, UR12, 0x8, UR6 ?WAIT3_END_GROUP;
UIMAD UR12, UR20, UR16, UR22 ?trans1;
DADD R8, R8, R10 &req={2} &rd=0x1 &wr=0x3 ?trans2;
MOV R10, UR13 &req={1} ?trans1;
MOV R11, RZ ?trans1;
UIMAD.WIDE.U32 UR12, UR12, 0x8, UR4 ?WAIT4_END_GROUP;
IADD.64 R6, R6, R10 ?trans2;
UIMAD.WIDE UR4, UR17, 0x8, UR4 ?trans1;
MOV.64 R18, UR12 ?WAIT5_END_GROUP;
MOV.64 R10, UR4 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R8, R8, R12 &req={3} &wr=0x4 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R8, R8, R14 &req={4} &rd=0x1 &wr=0x0 ?trans2;
LEA R14, P1, R6, R2, 0x3 &req={1} ?WAIT4_END_GROUP;
LEA.HI.X R15, R6, R3, R7, 0x3, P1 ?WAIT15_END_GROUP;
NOP ?WAIT13_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R16, UR24, R8 &req={0} &rd=0x0 &wr=0x1 ?trans2;
MOV.64 R16, UR10 &req={0} ?trans2;
UIMAD.WIDE.U32 UR10, UR17, 0x8, UR14 ?WAIT6_END_GROUP;
MOV.64 R12, UR10 ?WAIT15_END_GROUP;
NOP ?WAIT9_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R8, R8, UR26 &req={1} &wr=0x0 ?trans2;
STG.E.64 desc[UR18][R16.64], R8 &req={0} &rd=0x2 ?trans4;
LDG.E.64 R4, desc[UR18][R4.64] &wr=0x3 ?trans4;
LDG.E.64 R2, desc[UR18][R18.64] &wr=0x3 ?trans4;
LDG.E.64 R6, desc[UR18][R14.64+0x8] &wr=0x4 ?trans4;
LDG.E.64 R10, desc[UR18][R10.64+-0x8] &wr=0x5 ?trans4;
LDG.E.64 R12, desc[UR18][R12.64] &wr=0x2 ?trans1;
UIMAD.WIDE.U32 UR6, UR17, 0x8, UR6 ?WAIT15_END_GROUP;
NOP ?WAIT11_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R2, R2, R4 &req={3} &wr=0x4 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R2, R2, R6 &req={4} &rd=0x0 &wr=0x5 ?trans2;
MOV.64 R6, UR6 &req={0} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R2, R2, R10 &req={5} &wr=0x2 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R12, UR24, R2 &req={2} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R2, R2, UR26 &req={0} &wr=0x0 ?trans2;
STG.E.64 desc[UR18][R6.64], R2 &req={0} &rd=0x2 ?trans2;
@!P0 BRA 0x1680 ?trans5;
LDCU.128 UR4, c[0x0][0x380] &wr=0x3 ?trans1;
LDC.64 R6, c[0x0][0x380] &req={2} &wr=0x2 ?trans1;
MOV R4, UR22 ?trans1;
MOV R5, RZ ?trans1;
LDCU.64 UR14, c[0x0][0x390] &wr=0x4 ?trans1;
HFMA2 R3, -RZ, RZ, 0, 0 ?trans1;
UIMAD UR11, UR20, UR16, URZ ?trans1;
UIADD3 UR10, UPT, UPT, UR16, -0x1, URZ ?trans1;
UIADD3 UR16, UPT, UPT, UR16, 0x1, URZ ?WAIT3_END_GROUP;
UIMAD UR12, UR20, UR10, UR22 ?trans1;
UIMAD UR10, UR20, UR16, UR22 ?trans1;
UIADD3 UR16, UPT, UPT, UR11, UR22, URZ ?trans2;
MOV R2, UR11 ?trans1;
UIMAD.WIDE.U32 UR10, UR10, 0x8, UR4 &req={3} ?trans1;
UIMAD.WIDE UR12, UR12, 0x8, UR4 ?trans1;
UIMAD.WIDE UR4, UR16, 0x8, UR4 ?trans2;
IADD.64 R2, R4, R2 ?trans2;
MOV.64 R12, UR10 ?WAIT2_END_GROUP;
MOV.64 R4, UR12 ?trans2;
MOV.64 R8, UR4 ?WAIT3_END_GROUP;
LEA R6, P0, R2.reuse, R6, 0x3 &req={2} ?trans1;
UIMAD.WIDE.U32 UR4, UR16, 0x8, UR14 &req={4} ?trans1;
LDCU.128 UR12, c[0x0][0x3a0] &wr=0x2 ?trans2;
LEA.HI.X R7, R2, R7, R3, 0x3, P0 ?trans1;
LDG.E.64 R4, desc[UR18][R4.64] &req={1} &wr=0x3 ?trans2;
MOV.64 R10, UR4 ?trans2;
LDG.E.64 R2, desc[UR18][R12.64] &wr=0x3 ?trans4;
LDG.E.64 R6, desc[UR18][R6.64+0x8] &wr=0x4 ?trans4;
LDG.E.64 R8, desc[UR18][R8.64+-0x8] &wr=0x5 ?trans4;
LDG.E.64 R10, desc[UR18][R10.64] &wr=0x2 ?trans1;
UIMAD.WIDE.U32 UR6, UR16, 0x8, UR6 ?trans1;
DADD R2, R2, R4 &req={3} &rd=0x1 &wr=0x4 ?trans5;
MOV.64 R4, UR6 &req={1} ?WAIT15_END_GROUP;
NOP ?WAIT14_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R2, R2, R6 &req={4} &wr=0x5 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R2, R2, R8 &req={5} &wr=0x2 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R10, UR12, R2 &req={2} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R2, R2, UR14 &req={1} &wr=0x1 ?trans2;
STG.E.64 desc[UR18][R4.64], R2 &req={1} &rd=0x3 ?trans2;
UISETP.NE.AND UP0, UPT, UR22, UR21, UPT ?trans1;
UIADD3 UR22, UPT, UPT, UR22, 0x1, URZ ?WAIT5_END_GROUP;
PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x8 ?WAIT13_END_GROUP;
@P0 BRA 0xb0 ?trans5;
EXIT &req={1} ?trans5;
BRA 0x16d0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: update_jacobi_gpu(double*, double*, double*, int, double, double)
_Z17update_jacobi_gpuPdS_S_idd:
s_load_b32 s12, s[0:1], 0x18
s_mov_b32 s13, 1
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s12, 1
s_cbranch_scc1 .LBB0_5
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x20
s_add_i32 s14, s12, 2
v_mov_b32_e32 v0, 0
s_lshl_b32 s15, s14, 1
s_mov_b32 s11, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s16, s4, 8
s_addc_u32 s17, s5, 0
s_add_u32 s18, s4, -8
s_addc_u32 s19, s5, -1
.LBB0_2:
s_mov_b32 s20, 1
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s10, s20, -1
s_mul_i32 s23, s20, s14
s_mul_i32 s10, s10, s14
s_add_i32 s21, s20, 1
s_add_i32 s24, s10, s13
s_add_i32 s22, s23, s13
s_add_i32 s10, s24, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[26:27], s[10:11], 3
s_add_u32 s26, s4, s26
s_addc_u32 s27, s5, s27
s_ashr_i32 s25, s24, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[24:25], s[24:25], 3
s_add_u32 s24, s4, s24
s_addc_u32 s25, s5, s25
s_clause 0x1
global_load_b64 v[1:2], v0, s[26:27]
global_load_b64 v[3:4], v0, s[24:25]
s_add_u32 s24, s13, s23
s_addc_u32 s25, 0, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[24:25], s[24:25], 3
s_add_u32 s24, s16, s24
s_addc_u32 s25, s17, s25
s_ashr_i32 s23, s22, 31
global_load_b64 v[5:6], v0, s[24:25]
s_lshl_b64 s[24:25], s[22:23], 3
s_mov_b32 s23, s11
s_add_u32 s24, s18, s24
s_addc_u32 s25, s19, s25
s_lshl_b64 s[22:23], s[22:23], 3
global_load_b64 v[7:8], v0, s[24:25]
s_add_u32 s24, s8, s22
s_addc_u32 s25, s9, s23
s_add_u32 s22, s6, s22
global_load_b64 v[9:10], v0, s[24:25]
s_addc_u32 s23, s7, s23
s_cmp_lg_u32 s20, s12
s_mov_b32 s20, s21
s_waitcnt vmcnt(3)
v_add_f64 v[1:2], v[1:2], v[3:4]
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[1:2], v[1:2], v[5:6]
s_waitcnt vmcnt(1)
v_add_f64 v[1:2], v[1:2], v[7:8]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[1:2], v[9:10], s[0:1], v[1:2]
v_mul_f64 v[1:2], v[1:2], s[2:3]
global_store_b64 v0, v[1:2], s[22:23]
s_cbranch_scc1 .LBB0_3
s_add_i32 s10, s13, 1
s_cmp_lg_u32 s13, s12
s_mov_b32 s13, s10
s_cbranch_scc1 .LBB0_2
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| update_jacobi_gpu | 7,876 | 1,451 | stackv2-00001-of-00015 |
// Demangled: update_jacobi_gpu2(double*, double*, double*, int, double, double)
Function : _Z18update_jacobi_gpu2PdS_S_idd
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
S2R R2, SR_TID.Y &wr=0x2 ?trans7;
LDC R3, c[0x0][0x360] &wr=0x1 ?trans8;
S2UR UR5, SR_CTAID.Y &wr=0x2 ?trans8;
LDC R5, c[0x0][0x364] &wr=0x2 ?trans8;
LDC R4, c[0x0][0x398] &wr=0x3 ?trans1;
IMAD R0, R3, UR4, R0 &req={1} ?WAIT5_END_GROUP;
IADD3 R6, PT, PT, R0, 0x1, RZ ?trans1;
IMAD R3, R5, UR5, R2 &req={2} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R3, R4, PT &req={3} ?WAIT5_END_GROUP;
ISETP.GT.OR P0, PT, R6, R4, P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R8, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
IADD3 R5, PT, PT, R4, 0x2, RZ ?trans2;
IADD3 R2, PT, PT, R3.reuse, 0x2, RZ ?trans1;
LDCU.128 UR8, c[0x0][0x3a0] &wr=0x2 ?trans2;
IMAD R7, R3, R5, R6.reuse ?trans1;
LDC.64 R14, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD R3, R5.reuse, R2.reuse, R6 ?trans2;
IMAD R17, R5, R2, -R5 ?WAIT5_END_GROUP;
IADD3 R11, PT, PT, R0, 0x2, R17 ?trans1;
IMAD.WIDE R2, R3, 0x8, R8 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE R4, R7, 0x8, R8.reuse ?trans2;
LDG.E.64 R2, desc[UR4][R2.64] &req={1} &wr=0x4 ?trans1;
IADD3 R17, PT, PT, R6, R17, RZ ?trans1;
IMAD.WIDE R8, R11, 0x8, R8 ?trans2;
LDG.E.64 R4, desc[UR4][R4.64] &wr=0x4 ?trans2;
IMAD.WIDE R14, R17.reuse, 0x8, R14 &req={3} ?trans2;
LDG.E.64 R10, desc[UR4][R8.64] &wr=0x3 ?trans4;
LDG.E.64 R12, desc[UR4][R8.64+-0x10] &wr=0x5 ?trans4;
LDG.E.64 R14, desc[UR4][R14.64] &wr=0x2 ?trans1;
DADD R6, R2, R4 &req={4} &rd=0x0 &wr=0x3 ?trans2;
LDC.64 R2, c[0x0][0x388] &req={0} &wr=0x0 ?trans2;
IMAD.WIDE R2, R17, 0x8, R2 &req={0} ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R6, R6, R10 &req={3} &wr=0x5 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R6, R6, R12 &req={5} &wr=0x2 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R6, R14, UR8, R6 &req={2} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R6, R6, UR10 &req={0} &wr=0x0 ?trans2;
STG.E.64 desc[UR4][R2.64], R6 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x3a0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: update_jacobi_gpu2(double*, double*, double*, int, double, double)
_Z18update_jacobi_gpu2PdS_S_idd:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x3c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, 1, v0
v_add_nc_u32_e32 v3, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v3, v2, v3
v_cmpx_ge_i32_e64 s2, v3
s_cbranch_execz .LBB1_2
s_add_i32 s8, s2, 2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_mul_lo_u32 v1, v1, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshl_add_u32 v7, s8, 1, v1
v_add_nc_u32_e32 v5, v1, v2
v_add_nc_u32_e32 v3, v7, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v6, 31, v5
v_subrev_nc_u32_e32 v9, s8, v7
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[5:6], 3, v[5:6]
v_add_nc_u32_e32 v0, v9, v0
v_add_nc_u32_e32 v9, v9, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[3:4], 3, v[3:4]
v_add_nc_u32_e32 v7, 2, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v10, 31, v9
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
s_clause 0x1
global_load_b64 v[3:4], v[3:4], off
global_load_b64 v[5:6], v[5:6], off
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[0:1], 3, v[0:1]
v_lshlrev_b64 v[9:10], 3, v[9:10]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 3, v[7:8]
v_add_co_u32 v7, vcc_lo, s4, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b64 v[7:8], v[7:8], off
v_add_co_u32 v11, vcc_lo, s2, v9
global_load_b64 v[0:1], v[0:1], off
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v10, vcc_lo
s_load_b128 s[0:3], s[0:1], 0x20
global_load_b64 v[11:12], v[11:12], off
s_waitcnt vmcnt(3)
v_add_f64 v[2:3], v[3:4], v[5:6]
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[7:8]
s_waitcnt vmcnt(1)
v_add_f64 v[0:1], v[2:3], v[0:1]
v_add_co_u32 v2, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v10, vcc_lo
s_waitcnt vmcnt(0) lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[0:1], v[11:12], s[0:1], v[0:1]
v_mul_f64 v[0:1], v[0:1], s[2:3]
global_store_b64 v[2:3], v[0:1], off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| update_jacobi_gpu2 | 1,321 | 1,741 | stackv2-00001-of-00015 |
// Demangled: concurrent_kernel(double*, double*, double*, double*, int*, int)
Function : _Z17concurrent_kernelPdS_S_S_Pii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
LDCU.64 UR8, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R10, c[0x0][0x380] &wr=0x1 ?trans1;
S2R R0, SR_TID.X &wr=0x2 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x2 ?trans1;
LDCU UR6, c[0x0][0x3a8] &wr=0x3 ?trans1;
LDG.E.64 R10, desc[UR8][R10.64] &req={1} &wr=0x4 ?trans6;
LDC R13, c[0x0][0x370] &wr=0x2 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x1 ?trans1;
BSSY.RECONVERGENT B0, 0x330 ?trans1;
MOV.64 R4, RZ ?WAIT2_END_GROUP;
MOV R2, UR5 &req={1} ?trans1;
IMAD R3, R13, UR4, R0 &req={2} ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R3, UR6, PT &req={3} ?trans1;
MOV.64 R6, R10 &req={4} ?WAIT12_END_GROUP;
@P0 BRA 0x320 &req={0} ?trans5;
LDC.64 R8, c[0x0][0x380] &wr=0x0 ?trans1;
MOV.64 R4, RZ ?trans2;
MOV.64 R6, R10 ?trans2;
HFMA2 R14, -RZ, RZ, 0, 0 ?trans2;
IMAD R17, R2, R13, RZ ?WAIT7_END_GROUP;
IADD3 R13, PT, PT, R3, R14, RZ ?WAIT5_END_GROUP;
IMAD.WIDE.U32 R12, R13, 0x8, R8 &req={0} ?WAIT6_END_GROUP;
LDG.E.64 R12, desc[UR8][R12.64] &wr=0x2 ?trans1;
IADD3 R14, PT, PT, R17, R14, RZ ?trans1;
MOV R18, R7 ?trans1;
MOV R16, R11 ?trans1;
MOV R19, R6 ?trans1;
IADD3 R15, PT, PT, R3, R14, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R15, UR6, PT ?trans1;
DSETP.MIN.AND P3, P4, R12, R6, PT &req={2} &rd=0x0 ?trans1;
MOV R15, R13.reuse ?trans1;
MOV R7, R13 &req={0} ?trans1;
MOV R6, R12 ?WAIT15_END_GROUP;
NOP ?trans1;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DSETP.MAX.AND P1, P2, R12, R10, PT &wr=0x0 ?trans2;
FSEL R11, R7, R16, P1 &req={0} ?trans1;
FSEL R7, R15, R18, P3 ?trans1;
SEL R10, R6.reuse, R10, P1 ?trans1;
SEL R6, R6, R19, P3 ?trans1;
@P2 LOP3.LUT R11, R16, 0x80000, RZ, 0xfc, !PT ?trans2;
@P4 LOP3.LUT R7, R18, 0x80000, RZ, 0xfc, !PT ?WAIT15_END_GROUP;
NOP ?WAIT11_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R4, R12, R4 &rd=0x1 &wr=0x2 ?trans2;
@!P0 BRA 0x150 &req={2,1} ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
S2UR UR7, SR_CgaCtaId &wr=0x0 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GE.U32.AND P0, PT, R2, 0x2, PT ?trans1;
UIADD3 UR5, UPT, UPT, UR4, 0x800, URZ ?trans1;
UIADD3 UR6, UPT, UPT, UR4, 0x1000, URZ ?trans1;
ULEA UR4, UR7, UR4, 0x18 &req={0} ?trans2;
ULEA UR5, UR7, UR5, 0x18 ?trans1;
ULEA UR6, UR7, UR6, 0x18 ?WAIT3_END_GROUP;
LEA R3, R0.reuse, UR4, 0x3 ?trans2;
LEA R9, R0.reuse, UR5, 0x3 ?trans2;
LEA R13, R0, UR6, 0x3 ?trans1;
STS.64 [R3], R10 &rd=0x0 ?trans4;
STS.64 [R9], R6 &rd=0x0 ?trans4;
STS.64 [R13], R4 &rd=0x0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 BRA 0x6d0 ?trans5;
SHF.R.U32.HI R12, RZ, 0x1, R2 ?trans1;
BSSY.RECONVERGENT B0, 0x690 ?trans4;
ISETP.GE.U32.AND P0, PT, R0, R12, PT ?WAIT13_END_GROUP;
@P0 BRA 0x680 &req={1} ?trans5;
IMAD R6, R12.reuse, 0x8, R3 &req={0} ?trans1;
LDS.64 R4, [R3] &wr=0x0 ?trans1;
IMAD R10, R12, 0x8, R9 ?WAIT4_END_GROUP;
LDS.64 R6, [R6] &wr=0x1 ?trans1;
MOV R8, R5 &req={0} ?trans1;
MOV R11, R7 &req={1} ?trans1;
DSETP.MAX.AND P0, P1, R4, R6, PT &rd=0x0 &wr=0x1 ?trans2;
MOV R5, R6 &req={0} ?trans2;
FSEL R15, R8, R11, P0 &req={1} ?trans1;
@P1 LOP3.LUT R15, R11, 0x80000, RZ, 0xfc, !PT ?trans2;
SEL R4, R4, R5, P0 ?WAIT3_END_GROUP;
MOV R5, R15 ?WAIT5_END_GROUP;
STS.64 [R3], R4 ?trans4;
LDS.64 R10, [R10] &wr=0x0 ?trans4;
LDS.64 R6, [R9] &wr=0x1 ?trans1;
MOV R15, R11 &req={0} ?trans1;
MOV R8, R7 &req={1} ?WAIT15_END_GROUP;
NOP ?WAIT9_END_GROUP;
NOP ?WAIT15_END_GROUP;
DSETP.MIN.AND P0, P1, R6, R10, PT &rd=0x0 &wr=0x1 ?trans2;
MOV R7, R10 &req={0} ?trans1;
FSEL R17, R8, R15, P0 &req={1} ?trans1;
@P1 LOP3.LUT R17, R15, 0x80000, RZ, 0xfc, !PT ?trans1;
IMAD R8, R12, 0x8, R13 ?trans2;
SEL R6, R6, R7, P0 ?trans2;
MOV R7, R17 ?WAIT5_END_GROUP;
STS.64 [R9], R6 ?trans4;
LDS.64 R4, [R8] ?trans4;
LDS.64 R10, [R13] &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT12_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R4, R4, R10 &req={0} &wr=0x0 ?trans2;
STS.64 [R13], R4 &req={0} &rd=0x1 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P0, PT, R2, 0x3, PT ?trans1;
MOV R2, R12 ?WAIT12_END_GROUP;
@P0 BRA 0x430 ?trans5;
ISETP.NE.AND P0, PT, R0, RZ, PT ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LDC.64 R2, c[0x0][0x3a0] &req={0} &wr=0x0 ?trans1;
HFMA2 R5, -RZ, RZ, 0, 5.9604644775390625e-08 &req={1} ?trans1;
BSSY B0, 0x780 ?trans6;
MOV R4, RZ ?trans1;
YIELD ?trans5;
ATOMG.E.CAS.STRONG.GPU PT, R0, [R2], R4, R5 &req={0} &wr=0x2 ?trans2;
ISETP.NE.AND P0, PT, R0, RZ, PT &req={2} ?WAIT13_END_GROUP;
@P0 BRA 0x720 ?trans5;
BSYNC B0 ?trans5;
LDC.64 R4, c[0x0][0x388] &wr=0x0 ?trans2;
LDG.E.64 R6, desc[UR8][R4.64] &req={0} &wr=0x2 ?trans6;
S2UR UR5, SR_CgaCtaId &wr=0x0 ?trans1;
UMOV UR4, 0x400 ?trans2;
ULEA UR4, UR5, UR4, 0x18 &req={0} ?WAIT9_END_GROUP;
LDS.64 R8, [UR4] &wr=0x0 ?trans2;
MOV R11, R9 &req={0} ?trans1;
MOV R0, R7 &req={2} ?trans1;
DSETP.MAX.AND P0, P1, R6, R8, PT &wr=0x0 ?trans2;
SEL R6, R6, R8, P0 &req={0} ?trans2;
LDC.64 R8, c[0x0][0x390] &wr=0x0 ?trans1;
FSEL R13, R0, R11, P0 ?trans1;
@P1 LOP3.LUT R13, R11, 0x80000, RZ, 0xfc, !PT ?WAIT5_END_GROUP;
MOV R7, R13 ?trans2;
LDS.64 R12, [UR4+0x800] &wr=0x1 ?trans4;
STG.E.64 desc[UR8][R4.64], R6 &rd=0x2 ?trans4;
LDG.E.64 R10, desc[UR8][R8.64] &req={0} &wr=0x3 ?trans4;
LDS.64 R4, [UR4+0x1000] &wr=0x0 ?trans1;
LDC.64 R6, c[0x0][0x398] &req={2} &wr=0x2 ?trans1;
MOV R15, R13 &req={1} ?trans1;
MOV R0, R11 &req={3} ?WAIT15_END_GROUP;
NOP ?WAIT6_END_GROUP;
NOP ?WAIT15_END_GROUP;
DSETP.MIN.AND P0, P1, R10, R12, PT &wr=0x1 ?trans2;
SEL R10, R10, R12, P0 &req={1} ?trans1;
FSEL R17, R0, R15, P0 ?trans1;
@P1 LOP3.LUT R17, R15, 0x80000, RZ, 0xfc, !PT ?WAIT5_END_GROUP;
MOV R11, R17 ?WAIT5_END_GROUP;
STG.E.64 desc[UR8][R8.64], R10 ?trans4;
LDG.E.64 R12, desc[UR8][R6.64] &req={2} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?trans1;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R4, R4, R12 &req={0} &wr=0x0 ?trans2;
STG.E.64 desc[UR8][R6.64], R4 &req={0} ?trans4;
ATOMG.E.EXCH.STRONG.GPU PT, RZ, desc[UR8][R2.64], RZ ?trans1;
EXIT ?trans5;
BRA 0x9d0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: concurrent_kernel(double*, double*, double*, double*, int*, int)
_Z17concurrent_kernelPdS_S_S_Pii:
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b32 s16, s[0:1], 0x30
s_mov_b32 s14, exec_lo
s_waitcnt lgkmcnt(0)
s_load_b64 s[2:3], s[4:5], 0x0
s_clause 0x2
s_load_b32 s13, s[0:1], 0x28
s_load_b32 s12, s[0:1], 0x3c
s_load_b64 s[0:1], s[0:1], 0x20
v_mad_u64_u32 v[5:6], null, s16, s15, v[0:1]
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v8, s3 :: v_dual_mov_b32 v7, s2
v_dual_mov_b32 v4, s3 :: v_dual_mov_b32 v3, s2
s_and_b32 s12, s12, 0xffff
v_cmpx_gt_u32_e64 s13, v5
s_cbranch_execz .LBB4_4
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v6, 0
v_mov_b32_e32 v8, s3
v_dual_mov_b32 v4, s3 :: v_dual_mov_b32 v3, s2
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v7, s2
s_mul_i32 s16, s16, s12
s_mov_b32 s2, 0
.LBB4_2:
v_lshlrev_b64 v[9:10], 3, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_max_f64 v[7:8], v[7:8], v[7:8]
v_max_f64 v[3:4], v[3:4], v[3:4]
v_add_nc_u32_e32 v5, s16, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v9, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s13, v5
global_load_b64 v[9:10], v[9:10], off
s_or_b32 s2, vcc_lo, s2
s_waitcnt vmcnt(0)
v_max_f64 v[11:12], v[9:10], v[9:10]
v_add_f64 v[1:2], v[1:2], v[9:10]
s_delay_alu instid0(VALU_DEP_2)
v_max_f64 v[7:8], v[7:8], v[11:12]
v_min_f64 v[3:4], v[3:4], v[11:12]
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB4_2
s_or_b32 exec_lo, exec_lo, s2
.LBB4_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s14
v_lshlrev_b32_e32 v5, 3, v0
s_cmp_lt_u32 s12, 2
ds_store_b64 v5, v[3:4] offset:4096
ds_store_2addr_stride64_b64 v5, v[1:2], v[7:8] offset1:4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB4_9
v_add_nc_u32_e32 v1, 0x800, v5
v_add_nc_u32_e32 v2, 0x1000, v5
.LBB4_6:
s_lshr_b32 s2, s12, 1
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e64 s2, v0
s_cbranch_execz .LBB4_8
s_lshl_b32 s4, s2, 3
s_delay_alu instid0(SALU_CYCLE_1)
v_add_nc_u32_e32 v8, s4, v1
v_add_nc_u32_e32 v10, s4, v2
v_add_nc_u32_e32 v12, s4, v5
ds_load_b64 v[3:4], v1
ds_load_b64 v[6:7], v2
ds_load_b64 v[8:9], v8
ds_load_b64 v[10:11], v10
ds_load_b64 v[12:13], v12
ds_load_b64 v[14:15], v5
s_waitcnt lgkmcnt(5)
v_max_f64 v[3:4], v[3:4], v[3:4]
s_waitcnt lgkmcnt(4)
v_max_f64 v[6:7], v[6:7], v[6:7]
s_waitcnt lgkmcnt(3)
v_max_f64 v[8:9], v[8:9], v[8:9]
s_waitcnt lgkmcnt(2)
v_max_f64 v[10:11], v[10:11], v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_max_f64 v[3:4], v[3:4], v[8:9]
v_min_f64 v[6:7], v[6:7], v[10:11]
s_waitcnt lgkmcnt(0)
v_add_f64 v[8:9], v[12:13], v[14:15]
ds_store_b64 v1, v[3:4]
ds_store_b64 v2, v[6:7]
ds_store_b64 v5, v[8:9]
.LBB4_8:
s_or_b32 exec_lo, exec_lo, s3
s_cmp_gt_u32 s12, 3
s_mov_b32 s12, s2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB4_6
.LBB4_9:
s_mov_b32 s2, 0
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB4_13
v_dual_mov_b32 v0, 1 :: v_dual_mov_b32 v1, 0
.LBB4_11:
global_atomic_cmpswap_b32 v2, v1, v[0:1], s[0:1] glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 0, v2
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB4_11
s_or_b32 exec_lo, exec_lo, s2
v_mov_b32_e32 v8, 0
global_load_b64 v[4:5], v8, s[6:7]
ds_load_2addr_stride64_b64 v[0:3], v8 offset1:4
ds_load_b64 v[6:7], v8 offset:4096
s_waitcnt lgkmcnt(1)
v_max_f64 v[2:3], v[2:3], v[2:3]
s_waitcnt vmcnt(0)
v_max_f64 v[4:5], v[4:5], v[4:5]
s_delay_alu instid0(VALU_DEP_1)
v_max_f64 v[2:3], v[4:5], v[2:3]
s_waitcnt lgkmcnt(0)
v_max_f64 v[4:5], v[6:7], v[6:7]
global_store_b64 v8, v[2:3], s[6:7]
global_load_b64 v[2:3], v8, s[8:9]
s_waitcnt vmcnt(0)
v_max_f64 v[2:3], v[2:3], v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_min_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v8, v[2:3], s[8:9]
global_load_b64 v[2:3], v8, s[10:11]
s_waitcnt vmcnt(0)
v_add_f64 v[0:1], v[0:1], v[2:3]
global_store_b64 v8, v[0:1], s[10:11]
global_atomic_swap_b32 v8, v8, s[0:1]
.LBB4_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| concurrent_kernel | 3,423 | 2,388 | stackv2-00001-of-00015 |
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