sass stringlengths 231 30.8k | rdna stringlengths 69 28.4k | function_name stringlengths 1 85 | sass_tokens int64 90 14.4k ⌀ | rdna_tokens int64 11 14.5k ⌀ | source stringclasses 15
values |
|---|---|---|---|---|---|
// Demangled: atomic_inc(int*)
Function : _Z10atomic_incPi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R5, SR_TID.X &wr=0x0 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x0 ?trans1;
HFMA2 R7, -RZ, RZ, 0, 5.9604644775390625e-08 ?WAIT7_END_GROUP;
LDC R0, c[0x0][0x360] &wr=0x0 ?trans8;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans1;
IMAD R0, R0, UR4, R5 &req={0} ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans3;
IMAD.HI R4, R0, 0x66666667, RZ ?WAIT5_END_GROUP;
SHF.R.U32.HI R5, RZ, 0x1f, R4 ?WAIT4_END_GROUP;
LEA.HI.SX32 R5, R4, R5, 0x1e ?WAIT5_END_GROUP;
IMAD R5, R5, -0xa, R0 ?WAIT4_END_GROUP;
IMAD.WIDE R2, R5, 0x4, R2 &req={1} ?WAIT5_END_GROUP;
REDG.E.ADD.STRONG.GPU desc[UR4][R2.64], R7 &req={0} ?trans1;
EXIT ?trans5;
BRA 0xf0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: atomic_inc(int*)
_Z10atomic_incPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mul_hi_i32 v0, 0x66666667, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v2, 31, v0
v_ashrrev_i32_e32 v0, 2, v0
v_add_nc_u32_e32 v0, v0, v2
v_mov_b32_e32 v2, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, 10
v_sub_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_atomic_add_u32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| atomic_inc | 443 | 538 | stackv2-00000-of-00015 |
// Demangled: naive_inc(int*)
Function : _Z9naive_incPi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R5, SR_TID.X &wr=0x0 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x0 ?trans8;
LDC R0, c[0x0][0x360] &wr=0x0 ?trans8;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans1;
IMAD R0, R0, UR4, R5 &req={0} ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans3;
IMAD.HI R4, R0, 0x66666667, RZ ?WAIT5_END_GROUP;
SHF.R.U32.HI R5, RZ, 0x1f, R4 ?WAIT4_END_GROUP;
LEA.HI.SX32 R5, R4, R5, 0x1e ?WAIT5_END_GROUP;
IMAD R5, R5, -0xa, R0 ?WAIT4_END_GROUP;
IMAD.WIDE R2, R5, 0x4, R2 &req={1} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR4][R2.64] &req={0} &wr=0x2 ?trans2;
IADD3 R5, PT, PT, R0, 0x1, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R5 ?trans1;
EXIT ?trans5;
BRA 0x100;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: naive_inc(int*)
_Z9naive_incPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mul_hi_i32 v0, 0x66666667, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v2, 31, v0
v_ashrrev_i32_e32 v0, 2, v0
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, 10
v_sub_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, 1, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| naive_inc | 466 | 565 | stackv2-00000-of-00015 |
// Demangled: gpuMM(float*, float*, float*, int)
Function : _Z5gpuMMPfS_S_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
LDCU UR18, c[0x0][0x398] &wr=0x1 ?trans1;
S2R R3, SR_TID.Y &wr=0x2 ?trans6;
LDC R0, c[0x0][0x364] &wr=0x2 ?trans1;
HFMA2 R26, -RZ, RZ, 0, 0 ?trans1;
LDCU.64 UR16, c[0x0][0x358] &wr=0x3 ?trans1;
S2R R2, SR_TID.X &wr=0x4 ?trans5;
S2UR UR4, SR_CTAID.Y &wr=0x2 ?trans8;
S2UR UR5, SR_CTAID.X &wr=0x4 ?trans1;
UISETP.GE.AND UP0, UPT, UR18, 0x1, UPT &req={1} ?WAIT6_END_GROUP;
PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x8 ?trans1;
LDC R25, c[0x0][0x360] &wr=0x4 ?trans1;
IMAD R0, R0, UR4, R3 &req={2} ?trans2;
IMAD R25, R25, UR5, R2 &req={4} ?WAIT9_END_GROUP;
@!P0 BRA 0xa40 &req={3,0} ?trans5;
UISETP.GE.U32.AND UP0, UPT, UR18, 0x8, UPT ?trans1;
ULOP3.LUT UR7, UR18, 0x7, URZ, 0xc0, !UPT ?trans2;
IMAD R4, R0, UR18, RZ ?trans1;
MOV R26, RZ ?trans1;
MOV R24, RZ ?trans1;
PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x8 ?trans1;
ISETP.NE.AND P1, PT, RZ, UR7, PT ?WAIT12_END_GROUP;
@!P0 BRA 0x520 ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
USHF.L.U32 UR4, UR18, 0x1, URZ ?trans1;
HFMA2 R24, -RZ, RZ, 0, 0 ?trans1;
ULOP3.LUT UR6, UR18, 0x7ffffff8, URZ, 0xc0, !UPT ?trans1;
MOV R26, RZ ?trans1;
UIMAD.WIDE.U32 UR4, UR4, 0x4, URZ ?trans1;
MOV R27, R25 ?trans1;
UIADD3 UR6, UPT, UPT, -UR6, URZ, URZ ?trans1;
LDC.64 R6, c[0x0][0x388] &wr=0x1 ?trans1;
UIMAD.WIDE.U32 UR8, UR18, 0x14, UR4 ?trans1;
UIMAD.WIDE.U32 UR10, UR18, 0x10, UR4 ?trans1;
UIMAD.WIDE.U32 UR12, UR18, 0xc, UR4 ?trans1;
UIMAD.WIDE.U32 UR14, UR18, 0x8, UR4 ?trans1;
IMAD.WIDE.U32 R2, R4, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
IADD.64 R2, R2, 0x10 ?trans2;
IADD.64 R8, R6.reuse, UR8 &req={1} ?trans2;
IADD.64 R10, R6.reuse, UR10 ?trans2;
IADD.64 R12, R6.reuse, UR12 ?trans2;
IADD.64 R14, R6, UR14 ?WAIT8_END_GROUP;
IMAD.WIDE R20, R27, 0x4, R6 ?trans1;
MOV R17, UR18 ?trans1;
LDG.E R29, desc[UR16][R2.64+-0x10] &wr=0x2 ?trans4;
IMAD.WIDE.U32 R16, R17, 0x4, R20 ?trans1;
LDG.E R30, desc[UR16][R20.64] &wr=0x2 ?trans1;
IADD.64 R22, R20, UR4 ?WAIT3_END_GROUP;
LDG.E R31, desc[UR16][R16.64] &rd=0x0 &wr=0x3 ?trans1;
IADD.64 R36, R16, UR4 ?WAIT3_END_GROUP;
LDG.E R28, desc[UR16][R2.64+-0xc] &wr=0x3 ?trans4;
LDG.E R32, desc[UR16][R22.64] &rd=0x1 &wr=0x4 ?trans1;
IMAD.WIDE R16, R27, 0x4, R14 &req={0} ?WAIT3_END_GROUP;
LDG.E R35, desc[UR16][R2.64+-0x8] &wr=0x4 ?trans1;
IMAD.WIDE R18, R27, 0x4, R12 ?WAIT3_END_GROUP;
LDG.E R34, desc[UR16][R36.64] &wr=0x5 ?trans4;
LDG.E R33, desc[UR16][R2.64+-0x4] &wr=0x5 ?trans1;
IMAD.WIDE R20, R27, 0x4, R10 ?WAIT3_END_GROUP;
LDG.E R16, desc[UR16][R16.64] &wr=0x5 ?trans1;
IMAD.WIDE R22, R27, 0x4, R8 &req={1} ?WAIT3_END_GROUP;
LDG.E R18, desc[UR16][R18.64] &wr=0x5 ?trans4;
LDG.E R37, desc[UR16][R2.64+0x4] &wr=0x5 ?trans4;
LDG.E R17, desc[UR16][R2.64] &wr=0x5 ?trans4;
LDG.E R20, desc[UR16][R20.64] &wr=0x5 ?trans4;
LDG.E R19, desc[UR16][R2.64+0x8] &wr=0x5 ?trans4;
LDG.E R23, desc[UR16][R22.64] &wr=0x5 ?trans4;
LDG.E R36, desc[UR16][R2.64+0xc] &rd=0x0 &wr=0x5 ?trans1;
UIADD3 UR6, UPT, UPT, UR6, 0x8, URZ ?WAIT6_END_GROUP;
ISETP.NE.AND P0, PT, RZ, UR6, PT ?trans1;
IADD3 R24, PT, PT, R24, 0x8, RZ ?trans1;
IADD.64 R2, R2, 0x20 &req={0} ?trans2;
FFMA R29, R29, R30, R26 &req={2} ?WAIT4_END_GROUP;
FFMA R28, R28, R31, R29 &req={3} ?WAIT4_END_GROUP;
FFMA R28, R35, R32, R28 &req={4} ?WAIT4_END_GROUP;
FFMA R28, R33, R34, R28 &req={5} ?WAIT4_END_GROUP;
FFMA R16, R17, R16, R28 ?WAIT4_END_GROUP;
FFMA R16, R37, R18, R16 ?trans1;
MOV R18, UR18 ?WAIT3_END_GROUP;
FFMA R19, R19, R20, R16 ?trans2;
IMAD R27, R18, 0x8, R27 ?trans2;
FFMA R26, R36, R23, R19 ?trans1;
@P0 BRA 0x2a0 ?trans6;
@!P1 BRA 0xa40 ?trans5;
UISETP.GE.U32.AND UP0, UPT, UR7, 0x4, UPT ?trans1;
ULOP3.LUT UR4, UR18, 0x3, URZ, 0xc0, !UPT ?WAIT5_END_GROUP;
PLOP3.LUT P1, PT, PT, PT, UP0, 0x80, 0x8 ?trans1;
ISETP.NE.AND P0, PT, RZ, UR4, PT ?WAIT12_END_GROUP;
@!P1 BRA 0x7e0 ?trans5;
LDC.64 R8, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x380] &wr=0x1 ?trans1;
HFMA2 R5, -RZ, RZ, 0, 0 ?trans1;
MOV R2, R24.reuse ?trans1;
HFMA2 R3, -RZ, RZ, 0, 0 ?trans1;
UIADD3 UR5, UPT, UPT, UR18, UR18, URZ ?trans1;
IADD3 R11, PT, PT, R4, R24, RZ ?trans1;
IMAD R13, R24, UR18, R25 ?trans1;
LDC.64 R6, c[0x0][0x388] &wr=0x2 ?trans1;
IADD.64 R16, R4, R2 ?trans2;
MOV R10, UR18 ?trans1;
MOV R14, UR5 ?trans1;
HFMA2 R15, -RZ, RZ, 0, 0 ?WAIT2_END_GROUP;
IMAD.WIDE.U32 R8, R11, 0x4, R8 &req={0} ?trans1;
MOV R11, RZ ?WAIT5_END_GROUP;
IADD.64 R14, R10, R14 ?trans2;
IMAD.WIDE R2, R13, 0x4, R6 &req={2} ?trans1;
MOV R13, UR18 ?trans1;
LEA R6, P1, R16.reuse, UR6, 0x2 &req={1} ?trans1;
LDG.E R9, desc[UR16][R8.64] &wr=0x2 ?trans1;
MOV R11, UR5 ?trans2;
IMAD.WIDE.U32 R12, R13, 0x4, R2 ?trans1;
LEA.HI.X R7, R16, UR7, R17, 0x2, P1 ?trans1;
LDG.E R18, desc[UR16][R2.64] &wr=0x2 ?trans1;
LEA R16, P1, R14, R2, 0x2 ?trans1;
IMAD.WIDE.U32 R10, R11, 0x4, R2 ?WAIT2_END_GROUP;
LDG.E R12, desc[UR16][R12.64] &wr=0x3 ?trans1;
LEA.HI.X R17, R14, R3, R15, 0x2, P1 ?WAIT3_END_GROUP;
LDG.E R20, desc[UR16][R6.64+0x4] &wr=0x3 ?trans4;
LDG.E R10, desc[UR16][R10.64] &wr=0x4 ?trans4;
LDG.E R14, desc[UR16][R6.64+0x8] &wr=0x4 ?trans4;
LDG.E R22, desc[UR16][R6.64+0xc] &wr=0x5 ?trans4;
LDG.E R16, desc[UR16][R16.64] &wr=0x5 ?trans1;
IADD3 R24, PT, PT, R24, 0x4, RZ ?trans1;
FFMA R9, R9, R18, R26 &req={2} ?WAIT4_END_GROUP;
FFMA R9, R20, R12, R9 &req={3} ?WAIT4_END_GROUP;
FFMA R9, R14, R10, R9 &req={4} ?WAIT4_END_GROUP;
FFMA R26, R22, R16, R9 &req={5} ?WAIT7_END_GROUP;
@!P0 BRA 0xa40 ?trans5;
MOV R2, UR4 ?trans1;
ULOP3.LUT UR4, UR18, 0x1, URZ, 0xc0, !UPT ?trans1;
LDC.64 R10, c[0x0][0x388] &wr=0x0 ?trans3;
ISETP.NE.AND P0, PT, R2, 0x1, PT ?trans1;
UISETP.NE.U32.AND UP0, UPT, UR4, 0x1, UPT ?WAIT4_END_GROUP;
LDC.64 R6, c[0x0][0x380] &wr=0x1 ?trans2;
PLOP3.LUT P2, PT, PT, PT, UP0, 0x80, 0x8 ?WAIT5_END_GROUP;
@!UP0 LDCU.128 UR4, c[0x0][0x380] &wr=0x2 ?trans1;
@P0 LDC.64 R2, c[0x0][0x380] &wr=0x3 ?trans1;
@P0 IADD3 R19, PT, PT, R4, R24.reuse, RZ ?trans1;
@P0 IMAD R21, R24.reuse, UR18, R25 ?trans1;
@P0 MOV R8, R24 ?trans1;
@P0 IADD3 R24, PT, PT, R24, 0x2, RZ ?trans1;
@P0 MOV R9, RZ ?trans1;
@P0 MOV R5, RZ ?trans1;
@P0 IMAD.WIDE R10, R21, 0x4, R10 &req={0} ?trans1;
@!P2 IADD3 R17, PT, PT, R4, R24, RZ ?WAIT3_END_GROUP;
@P0 IADD.64 R12, R4, R8 ?trans2;
@P0 IMAD.WIDE.U32 R8, R19, 0x4, R6 &req={1} ?trans1;
MOV.64 R14, UR4 &req={2} ?trans2;
MOV.64 R6, UR6 ?WAIT4_END_GROUP;
@!P2 IMAD.WIDE.U32 R4, R17, 0x4, R14 ?trans1;
MOV R17, UR18 ?trans1;
@P0 LEA R2, P1, R12, R2, 0x2 &req={3} ?trans1;
@P0 LDG.E R9, desc[UR16][R8.64] &wr=0x2 ?trans1;
@!P2 IMAD R15, R24, UR18, R25 ?trans2;
@P0 LEA.HI.X R3, R12, R3, R13, 0x2, P1 ?trans1;
@P0 IMAD.WIDE.U32 R12, R17, 0x4, R10 ?trans1;
@!P2 LDG.E R5, desc[UR16][R4.64] &wr=0x3 ?trans4;
@P0 LDG.E R10, desc[UR16][R10.64] &wr=0x2 ?trans1;
@!P2 IMAD.WIDE R6, R15, 0x4, R6 ?WAIT3_END_GROUP;
@P0 LDG.E R3, desc[UR16][R2.64+0x4] &wr=0x4 ?trans4;
@P0 LDG.E R12, desc[UR16][R12.64] &wr=0x4 ?trans4;
@!P2 LDG.E R6, desc[UR16][R6.64] &wr=0x3 ?trans1;
@P0 FFMA R14, R9, R10, R26 &req={2} ?WAIT4_END_GROUP;
@P0 FFMA R26, R3, R12, R14 &req={4} ?WAIT4_END_GROUP;
@!P2 FFMA R26, R5, R6, R26 &req={3} ?WAIT7_END_GROUP;
LDC.64 R2, c[0x0][0x390] &wr=0x0 ?trans1;
IMAD R25, R0, UR18, R25 ?WAIT4_END_GROUP;
IMAD.WIDE R2, R25, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR16][R2.64], R26 ?trans1;
EXIT ?trans5;
BRA 0xa90;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: gpuMM(float*, float*, float*, int)
_Z5gpuMMPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s8, s3, 16
s_and_b32 s3, s3, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s8, v[1:2]
v_and_b32_e32 v3, 0x3ff, v0
s_cmp_lt_i32 s2, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[0:1], null, s14, s3, v[3:4]
v_mul_lo_u32 v1, v2, s2
s_cbranch_scc1 .LBB0_3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.LBB0_2:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v1, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| gpuMM | 4,402 | 1,124 | stackv2-00000-of-00015 |
// Demangled: cudaProcessUnsignedChar0(unsigned char*, unsigned char*, int, int)
Function : _Z24cudaProcessUnsignedChar0PhS_ii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R2, SR_TID.Y &wr=0x0 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x1 ?trans6;
LDC R4, c[0x0][0x390] &wr=0x2 ?trans1;
S2R R5, SR_CTAID.Y &wr=0x3 ?trans1;
LDCU UR7, c[0x0][0x394] &wr=0x4 ?trans1;
S2R R0, SR_TID.X &wr=0x5 ?trans1;
LDCU UR6, c[0x0][0x364] &wr=0x3 ?trans1;
S2R R3, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.128 UR8, c[0x0][0x380] &wr=0x0 ?trans1;
UIADD3 UR4, UPT, UPT, UR7, -0x2, URZ &req={4} ?trans1;
IADD3 R2, PT, PT, R2, R2, RZ &req={0} ?WAIT5_END_GROUP;
IMAD R6, R5, UR6, R2 &req={3} ?trans1;
LDCU UR6, c[0x0][0x364] &wr=0x0 ?trans1;
IADD3 R0, PT, PT, R0, R0, RZ &req={5} ?WAIT3_END_GROUP;
ISETP.GE.AND P0, PT, R6.reuse, UR4, PT ?trans2;
IMAD R3, R3, UR5, R0 &req={1} ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans2;
ISETP.EQ.OR P0, PT, R6, RZ, P0 ?WAIT5_END_GROUP;
ISETP.LT.OR P0, PT, R3, 0x1, P0 ?trans1;
IMAD R2, R5, UR6, R2 &req={0} ?WAIT4_END_GROUP;
IMAD R12, R2, R4, R3 &req={2} ?WAIT8_END_GROUP;
@!P0 IADD3 R0, PT, PT, R4, -0x2, RZ ?trans2;
SHF.R.S32.HI R13, RZ, 0x1f, R12 ?trans2;
IADD3 R16, PT, PT, R12.reuse, 0x2, RZ ?trans2;
IADD3 R10, PT, PT, R12.reuse, R4, RZ ?trans1;
ISETP.LT.AND P0, PT, R3, R0, !P0 ?trans1;
IADD3 R24, PT, PT, R12, -R4, RZ ?WAIT4_END_GROUP;
SEL.64 R2, R12, RZ, P0 ?WAIT3_END_GROUP;
SHF.R.S32.HI R17, RZ, 0x1f, R16 ?trans1;
IADD.64 R8, R2, UR10 ?WAIT3_END_GROUP;
IADD3 R2, PT, PT, R12, -0x1, RZ ?trans2;
IADD3 R26, PT, PT, R10, 0x1, RZ ?trans1;
SEL.64 R14, R16, RZ, P0 ?WAIT3_END_GROUP;
IADD3 R6, PT, PT, R10, -0x1, RZ ?trans2;
SHF.R.S32.HI R25, RZ, 0x1f, R24 ?trans1;
LDG.E.U8 R0, desc[UR4][R8.64] &req={1} &rd=0x0 &wr=0x2 ?trans1;
SHF.R.S32.HI R3, RZ, 0x1f, R2 ?trans1;
IADD.64 R14, R14, UR10 ?trans2;
SEL.64 R18, R24, RZ, P0 ?WAIT3_END_GROUP;
SHF.R.S32.HI R27, RZ, 0x1f, R26 ?trans1;
IADD.64 R32, R18, UR10 ?WAIT3_END_GROUP;
IADD3 R20, PT, PT, R10, R4, RZ ?trans2;
SHF.R.S32.HI R7, RZ, 0x1f, R6 ?trans1;
SEL.64 R8, R2, RZ, P0 &req={0} ?trans2;
SEL.64 R2, R26, RZ, P0 ?trans2;
LDG.E.U8 R5, desc[UR4][R14.64] &rd=0x0 &wr=0x3 ?trans1;
IADD3 R30, PT, PT, R24, 0x1, RZ ?trans1;
SEL.64 R6, R6, RZ, P0 ?WAIT3_END_GROUP;
IADD3 R18, PT, PT, R12, 0x1, RZ ?trans1;
IADD.64 R28, R2, UR10 ?trans2;
IADD.64 R22, R8, UR10 ?WAIT3_END_GROUP;
IADD3 R14, PT, PT, R20, -0x1, RZ &req={0} ?trans2;
IADD3 R24, PT, PT, R24, 0x2, RZ ?trans2;
SHF.R.S32.HI R21, RZ, 0x1f, R20 ?trans1;
IADD.64 R8, R6, UR10 ?trans2;
LDG.E.U8 R6, desc[UR4][R32.64] &rd=0x0 &wr=0x4 ?trans1;
SHF.R.S32.HI R31, RZ, 0x1f, R30 ?trans2;
SHF.R.S32.HI R19, RZ, 0x1f, R18 ?trans1;
LDG.E.U8 R2, desc[UR4][R28.64] &rd=0x1 &wr=0x2 ?trans1;
SHF.R.S32.HI R15, RZ, 0x1f, R14 ?trans1;
SEL.64 R30, R30, RZ, P0 ?WAIT2_END_GROUP;
LDG.E.U8 R7, desc[UR4][R22.64] &rd=0x5 &wr=0x2 ?trans1;
SHF.R.S32.HI R25, RZ, 0x1f, R24 ?trans2;
IADD3 R32, PT, PT, R20.reuse, 0x1, RZ &req={0} ?trans2;
SHF.R.S32.HI R11, RZ, 0x1f, R10 ?trans1;
LDG.E.U8 R3, desc[UR4][R8.64] &rd=0x0 &wr=0x2 ?trans1;
SEL.64 R28, R20, RZ, P0 &req={1} ?WAIT3_END_GROUP;
IADD3 R20, PT, PT, R10, 0x2, RZ ?trans1;
SEL.64 R14, R14, RZ, P0 ?trans2;
SEL.64 R22, R18, RZ, P0 &req={5} ?trans2;
SEL.64 R24, R24, RZ, P0 ?trans2;
IADD.64 R30, R30, UR10 ?trans2;
SEL.64 R8, R10, RZ, P0 &req={0} ?trans2;
IADD.64 R22, R22, UR10 ?WAIT2_END_GROUP;
IADD.64 R28, R28, UR10 ?trans2;
IADD.64 R14, R14, UR10 ?WAIT3_END_GROUP;
SHF.R.S32.HI R21, RZ, 0x1f, R20 ?trans1;
IADD.64 R24, R24, UR10 ?trans2;
IADD.64 R8, R8, UR10 ?trans2;
SEL.64 R34, R20, RZ, P0 ?trans2;
LDG.E.U8 R30, desc[UR4][R30.64] &wr=0x3 ?trans1;
SHF.R.S32.HI R33, RZ, 0x1f, R32 ?trans1;
IADD.64 R34, R34, UR10 ?trans2;
LDG.E.U8 R28, desc[UR4][R28.64] &wr=0x5 ?trans4;
LDG.E.U8 R22, desc[UR4][R22.64] &wr=0x4 ?trans4;
LDG.E.U8 R14, desc[UR4][R14.64] &wr=0x4 ?trans1;
SEL.64 R32, R32, RZ, P0 ?WAIT3_END_GROUP;
LDG.E.U8 R25, desc[UR4][R24.64] &rd=0x0 &wr=0x4 ?trans4;
LDG.E.U8 R8, desc[UR4][R8.64] &rd=0x1 &wr=0x4 ?trans1;
IADD.64 R32, R32, UR10 ?WAIT3_END_GROUP;
LDG.E.U8 R35, desc[UR4][R34.64] &wr=0x4 ?trans4;
LDG.E.U8 R33, desc[UR4][R32.64] &rd=0x1 &wr=0x4 ?trans1;
IMAD R24, R4, 0x3, RZ &req={0} ?trans1;
IADD3 R11, PT, PT, R12.reuse, R12, RZ ?trans1;
IMAD R4, R12, 0x3, RZ ?trans2;
IMAD R9, R24, UR7, RZ &req={1} ?trans1;
IADD3 R18, PT, PT, R18, R11, RZ ?WAIT2_END_GROUP;
IADD3 R12, PT, PT, R16, R11, RZ ?trans2;
IADD3 R16, PT, PT, R4.reuse, 0x3, RZ ?trans2;
IADD3 R32, PT, PT, R4.reuse, 0x4, RZ ?trans1;
ISETP.GE.AND P0, PT, R4, R9.reuse, PT ?trans1;
ISETP.GE.AND P2, PT, R18, R9.reuse, PT ?trans1;
IADD3 R13, PT, PT, R10, R10, RZ ?trans1;
ISETP.GE.AND P3, PT, R12, R9.reuse, PT ?trans1;
ISETP.GE.AND P5, PT, R32, R9.reuse, PT ?trans1;
IADD3 R24, PT, PT, R16, R24, RZ ?trans1;
IMAD R36, R10, 0x3, RZ ?trans1;
IADD3 R15, PT, PT, R4.reuse, 0x5, RZ ?trans1;
SEL R4, R4, RZ, !P0 ?trans1;
SEL R10, R18, RZ, !P2 ?trans1;
ISETP.GE.AND P4, PT, R16, R9, PT ?trans1;
SEL R18, R32, RZ, !P5 ?trans1;
IADD3 R26, PT, PT, R26, R13, RZ ?WAIT2_END_GROUP;
IADD3 R20, PT, PT, R20, R13, RZ ?trans1;
SEL R12, R12, RZ, !P3 ?trans1;
IADD3 R34, PT, PT, R24.reuse, 0x1, RZ ?trans2;
IADD3 R32, PT, PT, R24, 0x2, RZ ?trans1;
SEL R16, R16, RZ, !P4 ?trans1;
ISETP.GE.AND P0, PT, R15, R9.reuse, PT ?trans1;
ISETP.GE.AND P1, PT, R36, R9.reuse, PT ?trans1;
ISETP.GE.AND P2, PT, R26, R9.reuse, PT ?trans1;
ISETP.GE.AND P3, PT, R20, R9.reuse, PT ?trans1;
ISETP.GE.AND P4, PT, R24, R9.reuse, PT ?trans1;
ISETP.GE.AND P5, PT, R34, R9.reuse, PT ?trans1;
ISETP.GE.AND P6, PT, R32, R9, PT ?trans1;
SHF.R.S32.HI R13, RZ, 0x1f, R12 ?WAIT2_END_GROUP;
SHF.R.S32.HI R17, RZ, 0x1f, R16 ?WAIT3_END_GROUP;
IADD.64 R12, R12, UR8 ?trans2;
SEL R36, R36, RZ, !P1 ?trans1;
SHF.R.S32.HI R19, RZ, 0x1f, R18 ?trans1;
SEL R26, R26, RZ, !P2 ?trans1;
SEL R20, R20, RZ, !P3 ?trans1;
SEL R24, R24, RZ, !P4 ?trans1;
IADD.64 R16, R16, UR8 ?trans2;
IADD.64 R18, R18, UR8 ?WAIT3_END_GROUP;
SHF.R.S32.HI R37, RZ, 0x1f, R36 ?trans2;
SHF.R.S32.HI R27, RZ, 0x1f, R26 ?trans2;
SHF.R.S32.HI R21, RZ, 0x1f, R20 ?trans1;
IADD.64 R36, R36, UR8 ?trans2;
IADD.64 R26, R26, UR8 ?trans2;
IADD.64 R20, R20, UR8 ?WAIT3_END_GROUP;
IADD3 R11, PT, PT, R2, R3, R0 &req={2} ?trans2;
IADD3 R3, PT, PT, R5, R0, R30 &req={3} ?trans2;
SHF.R.S32.HI R5, RZ, 0x1f, R4 ?trans2;
IADD3 R28, PT, PT, R28, R11, RZ &req={5} ?trans2;
SHF.R.S32.HI R11, RZ, 0x1f, R10 ?trans1;
IADD.64 R4, R4, UR8 ?WAIT3_END_GROUP;
IADD3 R30, PT, PT, R14, R22.reuse, R7 &req={4} ?trans2;
IADD3 R7, PT, PT, R7, R22, RZ ?trans2;
IADD3 R9, PT, PT, R6, R25, RZ ?trans1;
IADD.64 R10, R10, UR8 ?WAIT3_END_GROUP;
IADD3 R6, PT, PT, R8, R25, R6 ?trans2;
SHF.R.U32.HI R7, RZ, 0x1, R7 ?trans2;
SHF.R.U32.HI R9, RZ, 0x1, R9 ?trans1;
SEL R14, R15, RZ, !P0 ?trans1;
IADD3 R6, PT, PT, R35, R6, RZ ?trans1;
STG.E.U8 desc[UR4][R4.64], R7 &rd=0x0 ?trans1;
IADD3 R3, PT, PT, R2, R3, RZ ?WAIT3_END_GROUP;
STG.E.U8 desc[UR4][R10.64], R0 ?trans1;
SHF.R.S32.HI R15, RZ, 0x1f, R14 ?WAIT3_END_GROUP;
STG.E.U8 desc[UR4][R12.64], R9 &rd=0x1 ?trans1;
SHF.R.U32.HI R3, RZ, 0x2, R3 ?trans1;
SEL R4, R34, RZ, !P5 &req={0} ?trans1;
IADD3 R30, PT, PT, R33, R30, RZ ?trans2;
SHF.R.S32.HI R25, RZ, 0x1f, R24 ?trans1;
IADD.64 R14, R14, UR8 ?WAIT3_END_GROUP;
SHF.R.U32.HI R9, RZ, 0x2, R6 &req={1} ?trans1;
SEL R6, R32, RZ, !P6 ?trans1;
IADD3 R33, PT, PT, R22, R33, RZ ?trans2;
SHF.R.S32.HI R5, RZ, 0x1f, R4 ?trans1;
STG.E.U8 desc[UR4][R16.64], R22 ?trans1;
SHF.R.U32.HI R11, RZ, 0x2, R30 ?trans2;
SHF.R.S32.HI R7, RZ, 0x1f, R6 ?trans1;
STG.E.U8 desc[UR4][R18.64], R3 &rd=0x0 ?trans1;
IADD3 R35, PT, PT, R8, R35, RZ ?trans1;
IADD.64 R24, R24, UR8 ?WAIT2_END_GROUP;
IADD.64 R4, R4, UR8 ?trans2;
STG.E.U8 desc[UR4][R14.64], R9 ?trans1;
SHF.R.U32.HI R33, RZ, 0x1, R33 ?trans1;
IADD.64 R6, R6, UR8 ?WAIT3_END_GROUP;
SHF.R.U32.HI R3, RZ, 0x2, R28 &req={0} ?trans1;
STG.E.U8 desc[UR4][R36.64], R11 ?trans1;
SHF.R.U32.HI R35, RZ, 0x1, R35 ?WAIT3_END_GROUP;
STG.E.U8 desc[UR4][R26.64], R3 ?trans4;
STG.E.U8 desc[UR4][R20.64], R8 ?trans4;
STG.E.U8 desc[UR4][R24.64], R33 ?trans4;
STG.E.U8 desc[UR4][R4.64], R2 ?trans4;
STG.E.U8 desc[UR4][R6.64], R35 ?trans1;
EXIT ?trans5;
BRA 0xbe0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: cudaProcessUnsignedChar0(unsigned char*, unsigned char*, int, int)
_Z24cudaProcessUnsignedChar0PhS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_lshrrev_b32_e32 v1, 9, v0
v_and_b32_e32 v0, 0x3ff, v0
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, 0x7fe, v1
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
s_mul_i32 s14, s14, s2
s_mov_b32 s3, 0
v_lshl_add_u32 v3, v0, 1, s14
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_lt_i32_e32 0, v2
s_add_i32 s2, s5, -2
s_add_i32 s3, s4, -2
v_cmp_gt_i32_e32 vcc_lo, s2, v2
v_cmp_gt_i32_e64 s2, s3, v3
v_cmp_lt_i32_e64 s3, 0, v3
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s3, s2, exec_lo
s_or_b32 exec_lo, exec_lo, s6
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v2, s4, v[3:4]
v_dual_mov_b32 v9, v5 :: v_dual_add_nc_u32 v2, s4, v0
v_dual_mov_b32 v8, v4 :: v_dual_mov_b32 v7, v5
v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v19, v5
v_dual_mov_b32 v18, v4 :: v_dual_mov_b32 v27, v5
v_dual_mov_b32 v26, v4 :: v_dual_mov_b32 v21, v5
v_dual_mov_b32 v20, v4 :: v_dual_mov_b32 v25, v5
v_dual_mov_b32 v24, v4 :: v_dual_mov_b32 v15, v5
v_dual_mov_b32 v14, v4 :: v_dual_mov_b32 v31, v5
v_dual_mov_b32 v30, v4 :: v_dual_mov_b32 v23, v5
v_dual_mov_b32 v22, v4 :: v_dual_mov_b32 v13, v5
v_dual_mov_b32 v12, v4 :: v_dual_mov_b32 v29, v5
v_dual_mov_b32 v28, v4 :: v_dual_mov_b32 v11, v5
v_dual_mov_b32 v10, v4 :: v_dual_mov_b32 v17, v5
v_mov_b32_e32 v16, v4
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_4
v_subrev_nc_u32_e32 v10, s4, v0
v_ashrrev_i32_e32 v3, 31, v2
v_add_nc_u32_e32 v4, s4, v2
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v6, 2, v2
v_add_nc_u32_e32 v18, 1, v2
v_add_nc_u32_e32 v20, -1, v2
s_delay_alu instid0(VALU_DEP_4)
v_dual_mov_b32 v31, v1 :: v_dual_add_nc_u32 v24, 2, v0
v_add_nc_u32_e32 v14, 1, v0
v_add_nc_u32_e32 v28, 1, v10
v_add_nc_u32_e32 v22, -1, v0
v_dual_mov_b32 v27, v3 :: v_dual_add_nc_u32 v12, 2, v10
v_add_nc_u32_e32 v8, -1, v4
v_add_nc_u32_e32 v16, 1, v4
v_ashrrev_i32_e32 v5, 31, v4
v_ashrrev_i32_e32 v29, 31, v28
v_ashrrev_i32_e32 v25, 31, v24
v_ashrrev_i32_e32 v9, 31, v8
v_ashrrev_i32_e32 v21, 31, v20
v_ashrrev_i32_e32 v19, 31, v18
v_ashrrev_i32_e32 v23, 31, v22
v_ashrrev_i32_e32 v15, 31, v14
v_ashrrev_i32_e32 v17, 31, v16
v_ashrrev_i32_e32 v11, 31, v10
v_ashrrev_i32_e32 v13, 31, v12
v_ashrrev_i32_e32 v7, 31, v6
v_mov_b32_e32 v26, v2
v_mov_b32_e32 v30, v0
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
s_load_b128 s[0:3], s[0:1], 0x0
v_lshl_add_u32 v0, v0, 1, v0
v_lshl_add_u32 v1, v2, 1, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v28, vcc_lo, s2, v28
v_add_co_ci_u32_e32 v29, vcc_lo, s3, v29, vcc_lo
v_add_co_u32 v30, vcc_lo, s2, v30
v_add_co_ci_u32_e32 v31, vcc_lo, s3, v31, vcc_lo
v_add_co_u32 v24, vcc_lo, s2, v24
v_add_co_ci_u32_e32 v25, vcc_lo, s3, v25, vcc_lo
v_add_co_u32 v18, vcc_lo, s2, v18
v_add_co_ci_u32_e32 v19, vcc_lo, s3, v19, vcc_lo
v_add_co_u32 v20, vcc_lo, s2, v20
v_add_co_ci_u32_e32 v21, vcc_lo, s3, v21, vcc_lo
s_clause 0x1
global_load_u8 v30, v[30:31], off
global_load_u8 v31, v[18:19], off
v_add_co_u32 v18, vcc_lo, s2, v22
v_add_co_ci_u32_e32 v19, vcc_lo, s3, v23, vcc_lo
v_add_co_u32 v14, vcc_lo, s2, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s3, v15, vcc_lo
v_add_co_u32 v16, vcc_lo, s2, v16
v_add_co_ci_u32_e32 v17, vcc_lo, s3, v17, vcc_lo
v_add_co_u32 v10, vcc_lo, s2, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo
v_add_co_u32 v12, vcc_lo, s2, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s3, v13, vcc_lo
v_add_co_u32 v22, vcc_lo, s2, v26
v_add_co_ci_u32_e32 v23, vcc_lo, s3, v27, vcc_lo
v_add_co_u32 v6, vcc_lo, s2, v6
s_clause 0x5
global_load_u8 v26, v[18:19], off
global_load_u8 v27, v[14:15], off
global_load_u8 v32, v[16:17], off
global_load_u8 v33, v[10:11], off
global_load_u8 v34, v[12:13], off
global_load_u8 v35, v[22:23], off
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, s2, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
global_load_u8 v36, v[6:7], off
v_add_co_u32 v3, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v5, vcc_lo
s_clause 0x4
global_load_u8 v28, v[28:29], off
global_load_u8 v24, v[24:25], off
global_load_u8 v25, v[20:21], off
global_load_u8 v29, v[8:9], off
global_load_u8 v37, v[3:4], off
s_mul_i32 s2, s4, 3
v_add_nc_u32_e32 v7, 1, v1
s_mul_i32 s3, s2, s5
v_add_nc_u32_e32 v6, 4, v0
v_cmp_gt_i32_e32 vcc_lo, s3, v0
v_add_nc_u32_e32 v4, 1, v0
v_add_nc_u32_e32 v5, 2, v0
v_cndmask_b32_e32 v3, 0, v0, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, s3, v1
v_cndmask_b32_e32 v12, 0, v1, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, s3, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v9, 31, v3
v_ashrrev_i32_e32 v14, 31, v12
v_cndmask_b32_e32 v4, 0, v4, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, s3, v5
v_dual_cndmask_b32 v5, 0, v5 :: v_dual_add_nc_u32 v2, 3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v8, s2, v2
v_cmp_gt_i32_e32 vcc_lo, s3, v2
v_add_nc_u32_e32 v38, 2, v8
v_add_nc_u32_e32 v0, 5, v0
v_cndmask_b32_e32 v10, 0, v2, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, s3, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v17, 31, v10
v_cndmask_b32_e32 v11, 0, v6, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, s3, v0
v_ashrrev_i32_e32 v6, 31, v4
v_ashrrev_i32_e32 v18, 31, v11
v_cndmask_b32_e32 v13, 0, v0, vcc_lo
v_add_nc_u32_e32 v1, 2, v1
v_cmp_gt_i32_e32 vcc_lo, s3, v7
v_add_nc_u32_e32 v23, 1, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v19, 31, v13
v_cndmask_b32_e32 v15, 0, v7, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, s3, v1
v_ashrrev_i32_e32 v7, 31, v5
v_ashrrev_i32_e32 v20, 31, v15
v_cndmask_b32_e32 v16, 0, v1, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, s3, v8
s_delay_alu instid0(VALU_DEP_2)
v_ashrrev_i32_e32 v21, 31, v16
v_cndmask_b32_e32 v22, 0, v8, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v9, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v6, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v7, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v10
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v17, vcc_lo
v_add_co_u32 v8, vcc_lo, s0, v11
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v18, vcc_lo
v_add_co_u32 v10, vcc_lo, s0, v13
v_add_co_ci_u32_e32 v11, vcc_lo, s1, v19, vcc_lo
v_add_co_u32 v12, vcc_lo, s0, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s1, v14, vcc_lo
v_add_co_u32 v14, vcc_lo, s0, v15
v_add_co_ci_u32_e32 v15, vcc_lo, s1, v20, vcc_lo
v_add_co_u32 v16, vcc_lo, s0, v16
v_add_co_ci_u32_e32 v17, vcc_lo, s1, v21, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, s3, v23
v_ashrrev_i32_e32 v19, 31, v22
v_cndmask_b32_e32 v20, 0, v23, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, s3, v38
v_cndmask_b32_e32 v23, 0, v38, vcc_lo
v_add_co_u32 v18, vcc_lo, s0, v22
v_add_co_ci_u32_e32 v19, vcc_lo, s1, v19, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_ashrrev_i32_e32 v38, 31, v23
s_waitcnt vmcnt(13)
v_and_b32_e32 v39, 0xff, v30
s_waitcnt vmcnt(12)
v_and_b32_e32 v40, 0xff, v31
v_ashrrev_i32_e32 v21, 31, v20
v_add_co_u32 v20, vcc_lo, s0, v20
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v21, vcc_lo, s1, v21, vcc_lo
v_add_co_u32 v22, vcc_lo, s0, v23
v_add_co_ci_u32_e32 v23, vcc_lo, s1, v38, vcc_lo
s_waitcnt vmcnt(10)
v_and_b32_e32 v41, 0xff, v27
s_waitcnt vmcnt(7)
v_add_nc_u32_e32 v33, v34, v33
s_waitcnt vmcnt(6)
v_and_b32_e32 v42, 0xff, v35
v_add_nc_u32_e32 v34, v40, v39
v_add_nc_u32_e32 v26, v41, v26
v_add_nc_u32_e32 v39, v32, v41
v_lshrrev_b32_e32 v38, 1, v33
s_waitcnt vmcnt(5)
v_add_nc_u32_e32 v36, v36, v42
v_lshrrev_b32_e32 v40, 1, v26
s_waitcnt vmcnt(3)
v_add3_u32 v24, v34, v28, v24
s_waitcnt vmcnt(1)
v_add3_u32 v26, v26, v29, v32
v_add_nc_u32_e32 v28, v36, v33
s_waitcnt vmcnt(0)
v_add3_u32 v25, v34, v25, v37
v_lshrrev_b32_e32 v24, 2, v24
v_lshrrev_b32_e32 v29, 1, v39
v_lshrrev_b32_e32 v32, 1, v36
v_lshrrev_b32_e32 v28, 2, v28
v_lshrrev_b32_e32 v26, 2, v26
v_lshrrev_b32_e32 v25, 2, v25
s_clause 0xb
global_store_b8 v[0:1], v40, off
global_store_b8 v[2:3], v30, off
global_store_b8 v[4:5], v38, off
global_store_b8 v[6:7], v27, off
global_store_b8 v[8:9], v24, off
global_store_b8 v[10:11], v28, off
global_store_b8 v[12:13], v26, off
global_store_b8 v[14:15], v25, off
global_store_b8 v[16:17], v35, off
global_store_b8 v[18:19], v29, off
global_store_b8 v[20:21], v31, off
global_store_b8 v[22:23], v32, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| cudaProcessUnsignedChar0 | 4,828 | 5,142 | stackv2-00000-of-00015 |
// Demangled: interp2(double*, double*, double*, double*, int, int)
Function : _Z7interp2PdS_S_S_ii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R2, SR_TID.Y &wr=0x1 ?trans7;
LDC R0, c[0x0][0x360] &wr=0x2 ?trans1;
LDCU.64 UR6, c[0x0][0x3a0] &wr=0x3 ?trans1;
S2R R3, SR_TID.X &wr=0x2 ?trans6;
S2UR UR5, SR_CTAID.Y &wr=0x1 ?trans8;
LDC R7, c[0x0][0x364] &wr=0x1 ?trans8;
S2UR UR4, SR_CTAID.X &wr=0x2 ?trans1;
IMAD R7, R7, UR5, R2 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R7, UR7, PT &req={3} ?trans1;
IMAD R0, R0, UR4, R3 &req={2} ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R0, UR6, P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x388] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD R0, R0, UR7, R7 ?WAIT6_END_GROUP;
LDC.64 R4, c[0x0][0x390] &wr=0x2 ?trans1;
IMAD.WIDE R2, R0, 0x8, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E.64 R2, desc[UR4][R2.64] &req={1} &wr=0x3 ?trans1;
IMAD.WIDE R4, R0, 0x8, R4 &req={2} ?WAIT6_END_GROUP;
LDG.E.64 R4, desc[UR4][R4.64] &wr=0x2 ?trans1;
I2F.F64.U32 R8, UR7 &wr=0x0 ?trans2;
MOV R11, R9 &req={0} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
I2F.F64 R6, UR6 &wr=0x0 ?trans1;
MOV R10, R3 &req={3} ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DSETP.MIN.AND P2, P3, R2, R8, PT &wr=0x1 ?trans2;
SEL R2, R2, R8, P2 &req={1} ?trans1;
FSEL R13, R10, R11, P2 ?trans1;
@P3 LOP3.LUT R13, R11, 0x80000, RZ, 0xfc, !PT ?trans1;
MOV R10, 0x80000 ?trans1;
MOV R11, R7 &req={0} ?WAIT3_END_GROUP;
MOV R3, R13 ?WAIT5_END_GROUP;
MOV R8, R3 ?WAIT15_END_GROUP;
NOP ?WAIT5_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DSETP.MAX.AND P2, P3, R2, 1, PT &wr=0x0 ?trans2;
FSEL R9, R8, 1.875, P2 &req={0} ?trans1;
@P3 LOP3.LUT R9, R10, 0x3ff00000, RZ, 0xfc, !PT ?trans1;
MOV R10, R5 &req={2} ?trans1;
SEL R2, R2, RZ, P2 ?WAIT3_END_GROUP;
MOV R3, R9 ?WAIT15_END_GROUP;
NOP ?WAIT11_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DSETP.MIN.AND P1, P0, R4, R6, PT &wr=0x0 ?trans2;
FSEL R13, R10, R11, P1 &req={0} ?trans1;
@P0 LOP3.LUT R13, R11, 0x80000, RZ, 0xfc, !PT ?trans1;
SEL R4, R4, R6, P1 ?trans1;
MOV R10, 0x80000 ?WAIT3_END_GROUP;
MOV R5, R13 ?WAIT5_END_GROUP;
MOV R6, R5 ?WAIT15_END_GROUP;
NOP ?WAIT6_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DSETP.MAX.AND P0, P1, R4, 1, PT &wr=0x0 ?trans2;
FSEL R7, R6, 1.875, P0 &req={0} ?trans1;
@P1 LOP3.LUT R7, R10, 0x3ff00000, RZ, 0xfc, !PT ?trans2;
LDC.64 R10, c[0x0][0x398] &wr=0x0 ?trans1;
SEL R4, R4, RZ, P0 ?trans2;
MOV R5, R7 ?WAIT15_END_GROUP;
NOP ?WAIT11_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R8, R2, -1 &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2I.F64.FLOOR R12, R8 &req={1} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R6, R4, -1 &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2I.F64.FLOOR R13, R6 &req={1} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2I.F64.CEIL R14, R8 &rd=0x1 &wr=0x2 ?trans2;
IMAD R9, R12, UR7, R13.reuse &req={1} ?trans2;
IMAD R13, R14, UR7, R13 &req={2} ?trans2;
IMAD.WIDE R8, R9, 0x8, R10 &req={0} ?WAIT6_END_GROUP;
LDG.E.64 R8, desc[UR4][R8.64] &wr=0x2 ?WAIT15_END_GROUP;
NOP ?WAIT7_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2I.F64.CEIL R15, R6 &wr=0x0 ?trans2;
IMAD R21, R14, UR7, R15.reuse &req={0} ?trans2;
IMAD R15, R12, UR7, R15 ?trans2;
IMAD.WIDE R12, R13, 0x8, R10 ?WAIT4_END_GROUP;
IMAD.WIDE R20, R21, 0x8, R10.reuse ?trans2;
LDG.E.64 R12, desc[UR4][R12.64] &wr=0x3 ?trans2;
IMAD.WIDE R10, R15, 0x8, R10 ?trans2;
LDG.E.64 R6, desc[UR4][R20.64] &wr=0x4 ?trans4;
LDG.E.64 R10, desc[UR4][R10.64] &wr=0x5 ?WAIT15_END_GROUP;
NOP ?WAIT14_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R14, R2, 1 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
FRND.F64.FLOOR R16, R2 &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R18, R2, -R16 &req={1} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
FRND.F64.FLOOR R14, R14 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R16, -R2, R14 &req={0} &rd=0x0 ?trans2;
LDC.64 R2, c[0x0][0x380] &req={0} &wr=0x0 ?trans2;
IMAD.WIDE R2, R0, 0x8, R2 &req={0} ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
FRND.F64.FLOOR R24, R4 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R22, R4, 1 &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
FRND.F64.FLOOR R22, R22 &req={1} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R24, R4, -R24 &req={0} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R6, R18, R6 &req={4} &wr=0x5 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R8, R16, R8 &req={2} &wr=0x3 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R6, R16, R10, R6 &req={5} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R20, -R4, R22 &req={1} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R18, R12, R8 &req={3} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R6, R6, R24 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R6, R8, R20, R6 &req={0} &wr=0x0 ?trans2;
STG.E.64 desc[UR4][R2.64], R6 &req={0} ?trans1;
EXIT ?trans5;
BRA 0xbe0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: interp2(double*, double*, double*, double*, int, int)
_Z7interp2PdS_S_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[8:9], s[0:1], 0x20
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s8, v0
v_cmp_gt_i32_e64 s2, s9, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b256 s[0:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[2:3], null, v0, s9, v[1:2]
v_cvt_f64_i32_e32 v[6:7], s9
v_cvt_f64_i32_e32 v[8:9], s8
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
s_waitcnt vmcnt(1)
v_max_f64 v[2:3], v[2:3], v[2:3]
s_waitcnt vmcnt(0)
v_max_f64 v[4:5], v[4:5], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_min_f64 v[2:3], v[2:3], v[6:7]
v_min_f64 v[4:5], v[4:5], v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_max_f64 v[2:3], v[2:3], 1.0
v_max_f64 v[4:5], v[4:5], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[6:7], v[2:3], -1.0
v_floor_f64_e32 v[16:17], v[2:3]
v_add_f64 v[8:9], v[4:5], -1.0
v_add_f64 v[18:19], v[4:5], 1.0
s_delay_alu instid0(VALU_DEP_4)
v_ceil_f64_e32 v[10:11], v[6:7]
v_floor_f64_e32 v[6:7], v[6:7]
v_add_f64 v[16:17], v[2:3], -v[16:17]
v_ceil_f64_e32 v[12:13], v[8:9]
v_floor_f64_e32 v[8:9], v[8:9]
v_floor_f64_e32 v[18:19], v[18:19]
v_cvt_i32_f64_e32 v10, v[10:11]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cvt_i32_f64_e32 v11, v[12:13]
v_cvt_i32_f64_e32 v12, v[6:7]
v_cvt_i32_f64_e32 v14, v[8:9]
v_mul_lo_u32 v13, v10, s9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v9, v12, s9
v_add_nc_u32_e32 v6, v13, v11
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v12, v13, v14
v_add_nc_u32_e32 v8, v9, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v7, 31, v6
v_add_nc_u32_e32 v10, v9, v11
v_ashrrev_i32_e32 v13, 31, v12
v_add_f64 v[14:15], v[2:3], 1.0
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[6:7], 3, v[6:7]
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[12:13], 3, v[12:13]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[8:9], 3, v[8:9]
v_add_co_u32 v6, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
v_lshlrev_b64 v[10:11], 3, v[10:11]
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v8, vcc_lo, s6, v8
global_load_b64 v[6:7], v[6:7], off
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
v_add_co_u32 v10, vcc_lo, s6, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
s_clause 0x1
global_load_b64 v[8:9], v[8:9], off
global_load_b64 v[10:11], v[10:11], off
v_add_co_u32 v12, vcc_lo, s6, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[12:13], v[12:13], off
v_floor_f64_e32 v[14:15], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_add_f64 v[2:3], v[14:15], -v[2:3]
v_floor_f64_e32 v[14:15], v[4:5]
s_waitcnt vmcnt(3)
v_mul_f64 v[6:7], v[16:17], v[6:7]
s_waitcnt vmcnt(2)
v_mul_f64 v[8:9], v[8:9], v[2:3]
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[2:3], v[10:11], v[2:3], v[6:7]
v_add_f64 v[6:7], v[4:5], -v[14:15]
v_add_f64 v[4:5], v[18:19], -v[4:5]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[8:9], v[12:13], v[16:17], v[8:9]
v_mul_f64 v[2:3], v[6:7], v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[2:3], v[4:5], v[8:9], v[2:3]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| interp2 | 3,110 | 2,648 | stackv2-00000-of-00015 |
// Demangled: kernel(int*, int, int, float, float, float, float)
Function : _Z6kernelPiiiffff
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
LDCU UR4, c[0x0][0x370] &wr=0x1 ?trans7;
LDC R6, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R7, SR_TID.X &wr=0x2 ?trans1;
IMAD R0, R6, UR4, RZ &req={1} ?trans1;
LDCU.64 UR4, c[0x0][0x388] &wr=0x1 ?trans3;
I2F.U32.RP R4, R0 &wr=0x3 ?trans1;
IADD3 R5, PT, PT, RZ, -R0, RZ ?trans1;
ISETP.NE.U32.AND P2, PT, R0, RZ, PT ?trans1;
MUFU.RCP R4, R4 &req={3} &wr=0x3 ?trans1;
UIMAD UR4, UR5, UR4, URZ &req={1} ?trans1;
IADD3 R2, PT, PT, R4, 0xffffffe, RZ &req={3} ?WAIT4_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R3, R2 &rd=0x1 &wr=0x3 ?trans2;
HFMA2 R2, -RZ, RZ, 0, 0 &req={1} ?trans2;
IMAD R5, R5, R3, RZ &req={3} ?WAIT4_END_GROUP;
IMAD.HI.U32 R3, R3, R5, R2 ?WAIT6_END_GROUP;
IMAD.HI.U32 R3, R3, UR4, RZ ?WAIT5_END_GROUP;
IADD3 R5, PT, PT, -R3, RZ, RZ ?WAIT5_END_GROUP;
IMAD R5, R0, R5, UR4 ?trans1;
S2UR UR4, SR_CTAID.X &wr=0x2 ?trans4;
ISETP.GE.U32.AND P0, PT, R5, R0, PT ?WAIT13_END_GROUP;
@P0 IADD3 R5, PT, PT, -R0, R5, RZ ?trans2;
@P0 IADD3 R3, PT, PT, R3, 0x1, RZ ?WAIT3_END_GROUP;
ISETP.GE.U32.AND P1, PT, R5, R0, PT ?trans1;
IMAD R2, R6, UR4, R7 &req={2} ?WAIT5_END_GROUP;
I2FP.F32.U32 R5, R2 ?WAIT7_END_GROUP;
@P1 IADD3 R3, PT, PT, R3, 0x1, RZ ?trans2;
@!P2 LOP3.LUT R3, RZ, R0, RZ, 0x33, !PT ?WAIT4_END_GROUP;
I2FP.F32.U32 R0, R3 ?WAIT5_END_GROUP;
FMUL R5, R0, R5 ?WAIT4_END_GROUP;
F2I.TRUNC.NTZ R2, R5 &wr=0x1 ?trans1;
FADD R0, R0, R5 ?trans1;
I2FP.F32.S32 R3, R2 &req={1} ?WAIT5_END_GROUP;
FSETP.GT.AND P0, PT, R0, R3, PT ?WAIT13_END_GROUP;
@!P0 EXIT &req={0} ?trans5;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans2;
LDC R13, c[0x0][0x388] &req={1} &wr=0x1 ?trans1;
IABS R8, R2 ?trans1;
BSSY.RECONVERGENT B0, 0x840 ?trans6;
LDC.64 R10, c[0x0][0x390] &wr=0x2 ?trans1;
IABS R6, R13 &req={1} ?WAIT4_END_GROUP;
I2F.RP R3, R6 &wr=0x1 ?trans2;
MUFU.RCP R3, R3 &req={1} &wr=0x1 ?trans2;
IADD3 R4, PT, PT, R3, 0xffffffe, RZ &req={1} ?WAIT4_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R5, R4 &rd=0x1 &wr=0x3 ?trans2;
MOV R4, RZ &req={1} ?trans1;
IADD3 R7, PT, PT, RZ, -R5, RZ &req={3} ?WAIT5_END_GROUP;
IMAD R7, R7, R6, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R5, R5, R7, R4 ?trans1;
MOV R7, R8 ?trans1;
LOP3.LUT R4, R2, R13, RZ, 0x3c, !PT ?trans1;
LDC.64 R8, c[0x0][0x398] &wr=0x2 ?trans3;
IMAD.HI.U32 R3, R5, R7, RZ ?WAIT5_END_GROUP;
IADD3 R5, PT, PT, -R3, RZ, RZ ?WAIT5_END_GROUP;
IMAD R5, R6, R5, R7 ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P1, PT, R6, R5, PT ?WAIT13_END_GROUP;
@!P1 IADD3 R5, PT, PT, R5, -R6.reuse, RZ ?trans2;
@!P1 IADD3 R3, PT, PT, R3, 0x1, RZ ?trans1;
ISETP.GE.AND P1, PT, R4, RZ, PT ?trans2;
ISETP.GE.U32.AND P0, PT, R5, R6, PT ?WAIT13_END_GROUP;
@P0 IADD3 R3, PT, PT, R3, 0x1, RZ ?trans1;
ISETP.NE.AND P0, PT, R13, RZ, PT ?WAIT3_END_GROUP;
@!P1 IADD3 R3, PT, PT, -R3, RZ, RZ ?WAIT10_END_GROUP;
@!P0 LOP3.LUT R3, RZ, R13, RZ, 0x33, !PT ?WAIT4_END_GROUP;
I2FP.F32.S32 R6, R3 ?trans2;
IADD3 R5, PT, PT, -R3, RZ, RZ ?WAIT5_END_GROUP;
IMAD R4, R13, R5, R2 ?trans2;
FFMA R5, R6, R9, R11 &req={2} ?WAIT3_END_GROUP;
I2FP.F32.S32 R7, R4 ?WAIT5_END_GROUP;
FFMA R6, R7, R8, R10 ?trans1;
FADD R7, RZ, R5 ?WAIT3_END_GROUP;
FADD R8, RZ, R6 ?trans1;
FMUL R10, R7, R7 ?WAIT3_END_GROUP;
FMUL R9, R8, R8 ?WAIT4_END_GROUP;
FADD R11, R9, R10 ?WAIT5_END_GROUP;
FSETP.GT.AND P0, PT, R11, 4, PT ?trans1;
HFMA2 R11, -RZ, RZ, 0, 5.9604644775390625e-08 ?WAIT12_END_GROUP;
@P0 BRA 0x830 ?trans5;
MOV R11, R7 ?trans1;
MOV R7, 0x1 ?WAIT7_END_GROUP;
FMUL R13, R8, R11 ?trans1;
FADD R9, -R10, R9 ?WAIT3_END_GROUP;
FFMA R8, R8, R11, R13 ?trans1;
FADD R10, R6, R9 ?WAIT3_END_GROUP;
FADD R11, R5, R8 ?trans1;
FMUL R9, R10, R10 ?WAIT3_END_GROUP;
FMUL R12, R11, R11 ?WAIT4_END_GROUP;
FADD R8, R9, R12 ?WAIT5_END_GROUP;
FSETP.GT.AND P0, PT, R8, 4, PT ?WAIT13_END_GROUP;
@P0 BRA 0x820 ?trans5;
FMUL R8, R11, R10 ?trans1;
FADD R9, R9, -R12 ?WAIT3_END_GROUP;
FFMA R8, R11, R10, R8 ?trans1;
FADD R10, R6, R9 ?WAIT3_END_GROUP;
FADD R13, R5, R8 ?trans1;
FMUL R9, R10, R10 ?WAIT3_END_GROUP;
FMUL R12, R13, R13 ?WAIT4_END_GROUP;
FADD R8, R9, R12 ?WAIT5_END_GROUP;
FSETP.GT.AND P0, PT, R8, 4, PT ?WAIT13_END_GROUP;
@P0 BRA 0x800 ?trans5;
IADD3 R14, PT, PT, R7, 0x3, RZ ?trans1;
MOV R11, 0x100 ?WAIT4_END_GROUP;
ISETP.NE.AND P0, PT, R14, 0x100, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x830 ?trans5;
FMUL R8, R13, R10 ?trans1;
FADD R9, R9, -R12 ?WAIT3_END_GROUP;
FFMA R8, R13, R10, R8 ?trans1;
FADD R9, R6, R9 ?WAIT3_END_GROUP;
FADD R8, R5, R8 ?trans1;
FMUL R10, R9, R9 ?WAIT3_END_GROUP;
FMUL R13, R8, R8 ?WAIT4_END_GROUP;
FADD R11, R10, R13 ?WAIT5_END_GROUP;
FSETP.GT.AND P0, PT, R11, 4, PT ?trans1;
MOV R11, R14 ?WAIT12_END_GROUP;
@P0 BRA 0x830 ?trans5;
FMUL R8, R8, R9 ?trans1;
FADD R9, R10, -R13 ?trans1;
IADD3 R7, PT, PT, R7, 0x4, RZ ?trans2;
FADD R10, R8, R8 ?trans1;
FADD R8, R6, R9 ?WAIT3_END_GROUP;
FADD R11, R5, R10 ?trans1;
FMUL R9, R8, R8 ?WAIT3_END_GROUP;
FMUL R10, R11, R11 ?WAIT4_END_GROUP;
FADD R12, R9, R10 ?WAIT5_END_GROUP;
FSETP.GT.AND P0, PT, R12, 4, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x500 ?trans5;
MOV R11, R7 ?trans1;
BRA 0x830 ?trans6;
IADD3 R11, PT, PT, R7, 0x2, RZ ?trans1;
BRA 0x830 ?trans6;
IADD3 R11, PT, PT, R7, 0x1, RZ ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 &req={0} ?trans5;
LDC.64 R6, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU UR6, c[0x0][0x388] &wr=0x1 ?trans1;
IADD3 R2, PT, PT, R2, 0x1, RZ ?trans1;
IMAD R5, R3, UR6, R4 &req={1} ?WAIT3_END_GROUP;
I2FP.F32.S32 R3, R2 ?trans1;
IMAD.WIDE R4, R5, 0x4, R6 &req={0} ?WAIT4_END_GROUP;
FSETP.GT.AND P0, PT, R0, R3, PT ?trans1;
STG.E desc[UR4][R4.64], R11 &rd=0x1 ?WAIT12_END_GROUP;
@P0 BRA 0x240 ?trans5;
EXIT ?trans5;
BRA 0x8e0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: kernel(int*, int, int, float, float, float, float)
_Z6kernelPiiiffff:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x20
s_load_b128 s[4:7], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_mul_i32 s5, s5, s4
s_mul_i32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s3
s_sub_i32 s9, 0, s3
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s8, v1
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s9, s9, s8
s_mul_hi_u32 s9, s8, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_add_i32 s8, s8, s9
v_cvt_f32_u32_e32 v1, v1
s_mul_hi_u32 s8, s5, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s9, s8, s3
s_sub_i32 s5, s5, s9
s_add_i32 s9, s8, 1
s_sub_i32 s10, s5, s3
s_cmp_ge_u32 s5, s3
s_cselect_b32 s2, s9, s8
s_cselect_b32 s5, s10, s5
s_add_i32 s8, s2, 1
s_cmp_ge_u32 s5, s3
s_mov_b32 s5, 0
s_cselect_b32 s2, s8, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v2, s2
s_mov_b32 s2, exec_lo
v_mul_f32_e32 v0, v2, v1
v_fmac_f32_e32 v2, v2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f32_e32 v0, v0
v_cvt_f32_i32_e32 v1, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_f32_e32 v2, v1
s_cbranch_execz .LBB0_7
s_ashr_i32 s10, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s4, s10
s_xor_b32 s11, s2, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s11
s_sub_i32 s2, 0, s11
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_mul_lo_u32 v3, s2, v1
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b64 s[8:9], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v1, v3
v_add_nc_u32_e32 v3, v1, v3
.LBB0_2:
v_ashrrev_i32_e32 v1, 31, v0
v_mov_b32_e32 v10, 0
s_mov_b32 s1, 1
s_mov_b32 s0, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v0, v1
v_xor_b32_e32 v4, v4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v5, v4, v3
v_mul_lo_u32 v6, v5, s11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v4, v4, v6
v_add_nc_u32_e32 v6, 1, v5
v_subrev_nc_u32_e32 v7, s11, v4
v_cmp_le_u32_e32 vcc_lo, s11, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v5, v5, v6 :: v_dual_cndmask_b32 v4, v4, v7
v_xor_b32_e32 v7, s10, v1
v_add_nc_u32_e32 v6, 1, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s11, v4
v_cndmask_b32_e32 v4, v5, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v4, v4, v7
v_sub_nc_u32_e32 v4, v4, v7
v_mov_b32_e32 v7, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mul_lo_u32 v5, v4, s4
v_cvt_f32_i32_e32 v6, v4
v_mov_b32_e32 v4, 0
v_sub_nc_u32_e32 v5, v0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v8, v5
s_waitcnt lgkmcnt(0)
v_fma_f32 v5, v6, s3, s7
v_fma_f32 v6, v8, s2, s6
v_mov_b32_e32 v8, 0
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mul_f32_e32 v7, v7, v8
v_sub_f32_e32 v4, v10, v4
s_or_b32 s12, s12, exec_lo
v_fma_f32 v7, 2.0, v7, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v8, v6, v4
v_mul_f32_e32 v4, v7, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v9, v8, v8, v4
v_cmp_nlt_f32_e32 vcc_lo, 4.0, v9
v_mov_b32_e32 v9, s1
s_and_saveexec_b32 s13, vcc_lo
s_add_i32 s1, s1, 1
v_dual_mul_f32 v10, v8, v8 :: v_dual_mov_b32 v9, 0x100
s_cmpk_eq_i32 s1, 0x100
s_cselect_b32 s14, -1, 0
s_and_not1_b32 s12, s12, exec_lo
s_and_b32 s14, s14, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s12, s12, s14
s_or_b32 exec_lo, exec_lo, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s13, exec_lo, s12
s_or_b32 s0, s13, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s0
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_add_nc_u32_e32 v0, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f32_i32_e32 v1, v0
v_add_co_u32 v4, s0, s8, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v5, s0, s9, v5, s0
v_cmp_ngt_f32_e32 vcc_lo, v2, v1
global_store_b32 v[4:5], v9, off
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_2
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| kernel | 3,119 | 2,889 | stackv2-00000-of-00015 |
// Demangled: minvec(int*, int)
Function : _Z6minvecPii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R9, SR_TID.X &wr=0x1 ?trans7;
LDC R8, c[0x0][0x360] &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x2 ?trans1;
S2R R6, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x388] &wr=0x3 ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x4 ?trans1;
IMAD R5, R6, R8, R9 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE R2, R5, 0x4, R2 &req={4} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR6][R2.64] &req={2} &rd=0x1 &wr=0x2 ?trans1;
ISETP.GE.AND P0, PT, R5, UR4, PT &req={3} ?trans2;
LDC.64 R4, c[0x0][0x380] &wr=0x2 ?trans8;
S2UR UR5, SR_CgaCtaId &wr=0x3 ?trans1;
UMOV UR4, 0x400 ?WAIT2_END_GROUP;
@P0 LDG.E R0, desc[UR6][R4.64] &req={2} &wr=0x2 ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={3} ?trans1;
ISETP.GE.U32.AND P0, PT, R8, 0x2, PT ?WAIT5_END_GROUP;
LEA R7, R9, UR4, 0x2 ?WAIT5_END_GROUP;
STS [R7], R0 &req={2} &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 BRA 0x240 &req={0} ?trans5;
MOV R0, R8 &req={1} ?WAIT7_END_GROUP;
MOV R4, R0 ?trans1;
SHF.R.U32.HI R0, RZ, 0x1, R0 ?trans1;
BSSY.RECONVERGENT B0, 0x210 ?trans4;
ISETP.GE.U32.AND P0, PT, R9, R0, PT ?WAIT13_END_GROUP;
@P0 BRA 0x200 &req={0} ?trans5;
IMAD R3, R0, 0x4, R7 ?trans1;
LDS R2, [R7] ?trans5;
LDS R3, [R3] &wr=0x0 ?trans2;
ISETP.GT.AND P0, PT, R2, R3, PT &req={0} ?WAIT13_END_GROUP;
@P0 STS [R7], R3 &rd=0x0 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P0, PT, R4, 0x3, PT ?WAIT13_END_GROUP;
@P0 BRA 0x160 ?trans5;
ISETP.NE.AND P0, PT, R9, RZ, PT ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
S2UR UR5, SR_CgaCtaId &wr=0x2 ?trans1;
UMOV UR4, 0x400 ?WAIT7_END_GROUP;
LDC.64 R2, c[0x0][0x380] &req={1,0} &wr=0x0 ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={2} ?trans1;
IMAD.WIDE.U32 R2, R6, 0x4, R2 &req={0} ?WAIT8_END_GROUP;
LDS R5, [UR4] &wr=0x0 ?trans4;
STG.E desc[UR6][R2.64], R5 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x2e0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: minvec(int*, int)
_Z6minvecPii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
s_load_b32 s0, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_load_b32 s1, s[4:5], 0x0
v_mad_u64_u32 v[2:3], null, s2, s3, v[0:1]
s_cmp_lt_u32 s3, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, s0, v2
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_dual_cndmask_b32 v2, s1, v3 :: v_dual_lshlrev_b32 v1, 2, v0
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
.LBB0_1:
s_mov_b32 s0, s3
s_lshr_b32 s3, s3, 1
s_mov_b32 s1, exec_lo
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB0_4
v_lshl_add_u32 v2, s3, 2, v1
ds_load_b32 v3, v1
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v3, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_4
ds_store_b32 v1, v2
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s1
s_cmp_gt_u32 s0, 3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_1
.LBB0_5:
s_mov_b32 s3, 0
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v0, 0
s_lshl_b64 s[0:1], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| minvec | 1,105 | 904 | stackv2-00000-of-00015 |
// Demangled: mm_gpu(float*, float*, float*, int, int, int)
Function : _Z6mm_gpuPfS_S_iii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
LDCU UR6, c[0x0][0x3a0] &wr=0x1 ?trans7;
LDC R0, c[0x0][0x364] &wr=0x2 ?trans1;
S2R R3, SR_TID.Y &wr=0x3 ?trans1;
LDCU.64 UR14, c[0x0][0x398] &wr=0x1 ?trans1;
S2R R5, SR_TID.X &wr=0x4 ?trans1;
UMOV UR12, 0x1 ?WAIT4_END_GROUP;
LDC R2, c[0x0][0x360] &wr=0x0 ?trans1;
UIMAD UR6, UR6, UR15, URZ &req={1} ?WAIT4_END_GROUP;
UISETP.GE.AND UP0, UPT, UR6, UR14, UPT ?WAIT6_END_GROUP;
PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x8 ?WAIT13_END_GROUP;
@P0 BRA 0x2e0 &req={4,3} ?trans5;
MOV R4, UR6 ?WAIT5_END_GROUP;
IABS R6, R4.reuse ?trans2;
IABS R8, R4 ?trans2;
R2UR UR10, R6 ?trans2;
IADD3 R8, PT, PT, RZ, -R8, RZ ?WAIT11_END_GROUP;
UI2F.RP UR4, UR10 ?WAIT9_END_GROUP;
MUFU.RCP R6, UR4 &wr=0x1 ?trans2;
R2UR UR4, R6 &req={1} ?trans1;
MOV R6, UR14 ?WAIT5_END_GROUP;
IABS R6, R6 ?WAIT5_END_GROUP;
MOV R4, R6 ?trans2;
UIADD3 UR4, UPT, UPT, UR4, 0xffffffe, URZ ?WAIT4_END_GROUP;
UF2I.FTZ.U32.TRUNC.NTZ UR5, UR4 ?trans1;
R2UR UR8, R4 ?trans1;
MOV R4, R8 ?trans1;
UMOV UR4, URZ ?WAIT3_END_GROUP;
IADD3 R7, PT, PT, RZ, -UR5, RZ ?trans2;
R2UR UR9, R4 ?trans2;
R2UR UR7, R7 ?WAIT13_END_GROUP;
UIMAD UR7, UR7, UR10, URZ ?WAIT4_END_GROUP;
UIMAD.HI.U32 UR4, UR5, UR7, UR4 ?WAIT4_END_GROUP;
UIMAD.WIDE.U32 UR4, UR4, UR8, URZ ?WAIT4_END_GROUP;
UIMAD UR4, UR5, UR9, UR8 ?WAIT4_END_GROUP;
UISETP.GT.U32.AND UP1, UPT, UR10, UR4, UPT ?WAIT11_END_GROUP;
@!UP1 UIADD3 UR4, UPT, UPT, UR4, -UR10, URZ ?trans1;
@!UP1 UIADD3 UR5, UPT, UPT, UR5, 0x1, URZ ?WAIT3_END_GROUP;
UISETP.GE.U32.AND UP0, UPT, UR4, UR10, UPT ?trans1;
ULOP3.LUT UR4, UR6, UR14, URZ, 0x3c, !UPT ?WAIT4_END_GROUP;
UISETP.GE.AND UP1, UPT, UR4, URZ, UPT ?WAIT6_END_GROUP;
@UP0 UIADD3 UR5, UPT, UPT, UR5, 0x1, URZ ?trans1;
UISETP.NE.AND UP0, UPT, UR6, URZ, UPT ?WAIT4_END_GROUP;
@!UP1 UIADD3 UR5, UPT, UPT, -UR5, URZ, URZ ?WAIT7_END_GROUP;
@!UP0 ULOP3.LUT UR5, URZ, UR6, URZ, 0x33, !UPT ?WAIT7_END_GROUP;
UMOV UR12, UR5 ?WAIT5_END_GROUP;
S2UR UR4, SR_CTAID.Y &wr=0x1 ?trans1;
UISETP.GE.AND UP0, UPT, UR12, 0x1, UPT ?WAIT6_END_GROUP;
PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x8 ?trans1;
S2UR UR5, SR_CTAID.X &wr=0x3 ?trans1;
IMAD R0, R0, UR4, R3 &req={2,1} ?trans2;
IMAD R3, R2, UR5, R5 &req={3,0} ?WAIT5_END_GROUP;
VIMNMX.S32 R2, R0, R3, !PT ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R2, UR14, !P0 ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LDCU.128 UR4, c[0x0][0x380] &wr=0x0 ?trans1;
IMAD R12, R3, UR12, RZ ?trans1;
MOV R2, UR14 ?trans1;
IMAD R0, R0, UR12, RZ ?trans1;
LDCU.64 UR30, c[0x0][0x358] &wr=0x1 ?trans1;
ULOP3.LUT UR15, UR14, 0x7, URZ, 0xc0, !UPT ?trans1;
ULOP3.LUT UR16, UR14, 0x3, URZ, 0xc0, !UPT ?trans1;
UIMAD.WIDE UR18, UR14, 0x1c, UR6 &req={0} ?trans1;
UIMAD.WIDE UR20, UR14, 0x18, UR6 ?trans1;
UIMAD.WIDE UR22, UR14, 0x14, UR6 ?trans1;
UIMAD.WIDE UR24, UR14, 0x10, UR6 ?trans1;
UIMAD.WIDE UR26, UR14, 0xc, UR6 ?trans1;
UIMAD.WIDE UR28, UR14, 0x8, UR6 ?trans1;
UIMAD.WIDE UR8, UR14, 0x4, UR6 ?trans1;
USHF.R.S32.HI UR6, URZ, 0x1f, UR14 ?trans1;
UIADD3.64 UR10, UPT, UPT, UR4, 0x10, URZ ?trans1;
ULOP3.LUT UR4, UR14, 0x7ffffff8, URZ, 0xc0, !UPT ?trans1;
UIADD3 UR5, UPT, UPT, UR14, -0x1, URZ ?WAIT3_END_GROUP;
MOV R3, UR6 ?trans1;
UIADD3 UR13, UPT, UPT, -UR4, URZ, URZ ?trans1;
UISETP.GE.U32.AND UP0, UPT, UR5, 0x7, UPT ?trans2;
UMOV UR4, URZ &req={1} ?WAIT9_END_GROUP;
LDCU UR5, c[0x0][0x398] &req={0} &wr=0x0 ?trans1;
IADD3 R13, PT, PT, R0, UR4, RZ ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x1, URZ ?WAIT4_END_GROUP;
UISETP.NE.AND UP1, UPT, UR4, UR12, UPT ?trans1;
IMAD R13, R13, UR5, RZ &req={0} ?trans1;
UMOV UR5, URZ ?WAIT9_END_GROUP;
PLOP3.LUT P1, PT, PT, PT, UP0, 0x80, 0x8 ?trans1;
UMOV UR6, URZ ?trans1;
ISETP.NE.AND P0, PT, RZ, UR15, PT ?trans1;
HFMA2 R14, -RZ, RZ, 0, 0 ?WAIT10_END_GROUP;
@!P1 BRA 0x9c0 &req={0} ?trans5;
IADD3 R15, PT, PT, R12, UR5, RZ ?trans1;
MOV R14, RZ ?trans1;
MOV R16, R13 ?trans1;
UMOV UR7, UR13 ?WAIT6_END_GROUP;
LDC.64 R8, c[0x0][0x388] &wr=0x0 ?trans1;
MOV R5, 0x4 ?WAIT5_END_GROUP;
IMAD.WIDE R4, R16, R5, UR10 &req={1} ?WAIT5_END_GROUP;
LDG.E R18, desc[UR30][R4.64+-0x10] &req={2} &wr=0x2 ?trans1;
HFMA2 R10, -RZ, RZ, 0, 2.384185791015625e-07 ?WAIT3_END_GROUP;
LDG.E R20, desc[UR30][R4.64+-0xc] &wr=0x3 ?trans1;
IMAD.WIDE R8, R15.reuse, 0x4, R8 &req={0} ?trans1;
MOV R6, 0x4 ?trans2;
LDG.E R21, desc[UR30][R4.64+-0x8] &wr=0x4 ?trans4;
LDG.E R17, desc[UR30][R8.64] &rd=0x0 &wr=0x2 ?trans1;
IMAD.WIDE R10, R15, R10, UR8 ?WAIT4_END_GROUP;
HFMA2 R24, -RZ, RZ, 0, 2.384185791015625e-07 ?trans1;
LDG.E R23, desc[UR30][R4.64+-0x4] &wr=0x5 ?trans4;
LDG.E R19, desc[UR30][R10.64] &rd=0x1 &wr=0x3 ?trans1;
IMAD.WIDE R6, R15.reuse, R6, UR28 ?trans1;
MOV R26, 0x4 ?trans2;
LDG.E R25, desc[UR30][R4.64] &wr=0x3 ?trans4;
LDG.E R22, desc[UR30][R6.64] &rd=0x1 &wr=0x4 ?trans1;
IMAD.WIDE R8, R15, R24, UR26 &req={0} ?WAIT4_END_GROUP;
HFMA2 R28, -RZ, RZ, 0, 2.384185791015625e-07 ?trans1;
LDG.E R27, desc[UR30][R4.64+0x4] &wr=0x3 ?trans4;
LDG.E R24, desc[UR30][R8.64] &rd=0x0 &wr=0x5 ?trans1;
IMAD.WIDE R10, R15.reuse, R26, UR24 &req={1} ?trans1;
MOV R30, 0x4 ?trans2;
LDG.E R29, desc[UR30][R4.64+0xc] &wr=0x4 ?trans4;
LDG.E R26, desc[UR30][R10.64] &rd=0x1 &wr=0x4 ?trans1;
IMAD.WIDE R6, R15, R28, UR22 ?WAIT6_END_GROUP;
LDG.E R6, desc[UR30][R6.64] &rd=0x2 &wr=0x4 ?trans1;
IMAD.WIDE R8, R15, R28, UR20 &req={0} ?WAIT3_END_GROUP;
LDG.E R28, desc[UR30][R4.64+0x8] &wr=0x4 ?trans4;
LDG.E R9, desc[UR30][R8.64] &rd=0x0 &wr=0x4 ?trans1;
IMAD.WIDE R10, R15, R30, UR18 &req={1} ?WAIT6_END_GROUP;
LDG.E R10, desc[UR30][R10.64] &wr=0x5 ?trans1;
I2FP.F32.S32 R31, R14 ?trans1;
UIADD3 UR7, UPT, UPT, UR7, 0x8, URZ ?WAIT6_END_GROUP;
ISETP.NE.AND P1, PT, RZ, UR7, PT ?trans1;
UIADD3 UR6, UPT, UPT, UR6, 0x8, URZ ?trans1;
IADD3 R16, PT, PT, R16, 0x8, RZ ?trans1;
FFMA R17, R18, R17, R31 &req={2} ?WAIT6_END_GROUP;
F2I.TRUNC.NTZ R17, R17 &wr=0x1 ?trans2;
I2FP.F32.S32 R7, R17 &req={1} ?WAIT5_END_GROUP;
FFMA R7, R20, R19, R7 &req={3} ?WAIT6_END_GROUP;
F2I.TRUNC.NTZ R7, R7 &wr=0x0 ?trans2;
I2FP.F32.S32 R8, R7 &req={0} ?WAIT5_END_GROUP;
FFMA R8, R21, R22, R8 &req={4} ?WAIT6_END_GROUP;
F2I.TRUNC.NTZ R8, R8 &wr=0x0 ?trans2;
I2FP.F32.S32 R4, R8 &req={0} ?trans2;
LDC R8, c[0x0][0x398] &wr=0x0 ?trans3;
FFMA R4, R23, R24, R4 &req={5} ?WAIT6_END_GROUP;
F2I.TRUNC.NTZ R4, R4 &wr=0x1 ?trans2;
I2FP.F32.S32 R14, R4 &req={1} ?WAIT5_END_GROUP;
FFMA R14, R25, R26, R14 ?WAIT6_END_GROUP;
F2I.TRUNC.NTZ R14, R14 &wr=0x1 ?trans2;
I2FP.F32.S32 R18, R14 &req={1} ?WAIT5_END_GROUP;
FFMA R6, R27, R6, R18 ?WAIT6_END_GROUP;
F2I.TRUNC.NTZ R6, R6 &wr=0x1 ?trans2;
I2FP.F32.S32 R5, R6 &req={1} ?WAIT5_END_GROUP;
FFMA R5, R28, R9, R5 ?WAIT6_END_GROUP;
F2I.TRUNC.NTZ R5, R5 &wr=0x1 ?trans2;
I2FP.F32.S32 R4, R5 &req={1} ?WAIT5_END_GROUP;
FFMA R4, R29, R10, R4 ?WAIT4_END_GROUP;
F2I.TRUNC.NTZ R14, R4 &rd=0x1 &wr=0x2 ?trans1;
IMAD R15, R8, 0x8, R15 &req={0} ?trans1;
@P1 BRA 0x5c0 ?trans6;
IADD3 R4, PT, PT, R12, UR5, RZ &req={1} ?trans1;
@!P0 BRA 0xea0 ?trans6;
UIADD3 UR7, UPT, UPT, UR15, -0x1, URZ ?trans1;
ISETP.NE.AND P0, PT, RZ, UR16, PT ?WAIT3_END_GROUP;
UISETP.GE.U32.AND UP2, UPT, UR7, 0x3, UPT ?WAIT6_END_GROUP;
PLOP3.LUT P1, PT, PT, PT, UP2, 0x80, 0x8 ?WAIT13_END_GROUP;
@!P1 BRA 0xc60 ?trans5;
LDC R15, c[0x0][0x398] &wr=0x0 ?trans1;
IADD3 R5, PT, PT, R13, UR6, RZ ?WAIT7_END_GROUP;
LDC.64 R6, c[0x0][0x380] &wr=0x1 ?trans8;
LDC.64 R8, c[0x0][0x388] &wr=0x3 ?trans1;
IMAD R11, R15, UR6, R4 &req={0} ?trans2;
IMAD.WIDE R6, R5, 0x4, R6 &req={1} ?WAIT5_END_GROUP;
LDG.E R5, desc[UR30][R6.64] &wr=0x4 ?trans1;
IMAD.WIDE R8, R11, 0x4, R8 &req={3} ?trans1;
IADD.64 R16, R2, R2 ?trans2;
LDG.E R23, desc[UR30][R6.64+0x8] &wr=0x3 ?trans4;
LDG.E R22, desc[UR30][R8.64] &wr=0x4 ?trans1;
IMAD.WIDE R10, R15, 0x4, R8 ?WAIT3_END_GROUP;
LDG.E R15, desc[UR30][R6.64+0x4] &wr=0x5 ?trans4;
LDG.E R10, desc[UR30][R10.64] &wr=0x5 ?trans1;
LEA R18, P1, R16, R8, 0x2 ?WAIT4_END_GROUP;
LEA.HI.X R19, R16, R9, R17, 0x2, P1 ?WAIT5_END_GROUP;
LDG.E R18, desc[UR30][R18.64] &wr=0x3 ?trans1;
IADD.64 R16, R2, R16 ?WAIT5_END_GROUP;
LEA R20, P1, R16, R8, 0x2 ?WAIT4_END_GROUP;
LEA.HI.X R21, R16, R9, R17, 0x2, P1 ?trans2;
LDG.E R9, desc[UR30][R6.64+0xc] &req={2} &rd=0x0 &wr=0x2 ?trans4;
LDG.E R20, desc[UR30][R20.64] &wr=0x2 ?trans1;
I2FP.F32.S32 R14, R14 ?trans1;
UIADD3 UR6, UPT, UPT, UR6, 0x4, URZ ?WAIT4_END_GROUP;
FFMA R5, R5, R22, R14 &req={4} ?WAIT6_END_GROUP;
F2I.TRUNC.NTZ R5, R5 &wr=0x1 ?trans2;
I2FP.F32.S32 R8, R5 &req={1} ?WAIT5_END_GROUP;
FFMA R8, R15, R10, R8 &req={5} ?WAIT6_END_GROUP;
F2I.TRUNC.NTZ R8, R8 &wr=0x1 ?trans2;
I2FP.F32.S32 R10, R8 &req={1} ?WAIT5_END_GROUP;
FFMA R10, R23, R18, R10 &req={3} ?WAIT6_END_GROUP;
F2I.TRUNC.NTZ R10, R10 &wr=0x0 ?trans2;
I2FP.F32.S32 R6, R10 &req={0} ?WAIT5_END_GROUP;
FFMA R6, R9, R20, R6 &req={2} ?WAIT4_END_GROUP;
F2I.TRUNC.NTZ R14, R6 &rd=0x0 &wr=0x1 ?trans3;
@!P0 BRA 0xea0 ?trans5;
UISETP.NE.AND UP2, UPT, UR16, 0x1, UPT ?trans1;
LDC R15, c[0x0][0x398] &wr=0x3 ?trans1;
HFMA2 R11, -RZ, RZ, 0, 2.384185791015625e-07 ?trans1;
MOV R17, 0x4 ?WAIT3_END_GROUP;
PLOP3.LUT P1, PT, PT, PT, UP2, 0x80, 0x8 ?WAIT3_END_GROUP;
LDC.64 R8, c[0x0][0x380] &wr=0x4 ?trans2;
@UP2 LDCU.128 UR32, c[0x0][0x380] &wr=0x5 ?trans6;
LDC.64 R6, c[0x0][0x388] &req={0} &wr=0x0 ?trans2;
@P1 IADD3 R10, PT, PT, R13, UR6, RZ ?trans1;
@P1 IMAD R16, R15, UR6, R4 &req={3} ?WAIT4_END_GROUP;
@P1 IMAD.WIDE R10, R10, R11, UR32 &req={5} ?WAIT4_END_GROUP;
@P1 IMAD.WIDE R16, R16, R17, UR34 ?trans1;
@P1 LDG.E R20, desc[UR30][R10.64] &wr=0x3 ?trans4;
@P1 LDG.E R21, desc[UR30][R16.64] &wr=0x3 ?trans1;
@P1 IMAD.WIDE R18, R15.reuse, 0x4, R16 ?trans1;
LOP3.LUT R5, R15, 0x1, RZ, 0xc0, !PT ?trans2;
@P1 LDG.E R22, desc[UR30][R10.64+0x4] &wr=0x5 ?trans3;
ISETP.NE.U32.AND P0, PT, R5, 0x1, PT ?trans1;
@P1 LDG.E R19, desc[UR30][R18.64] &wr=0x5 ?trans1;
@UP2 UIADD3 UR6, UPT, UPT, UR6, 0x2, URZ ?WAIT11_END_GROUP;
@!P0 IADD3 R5, PT, PT, R13, UR6, RZ ?trans1;
@!P0 IMAD R15, R15, UR6, R4 ?WAIT4_END_GROUP;
@!P0 IMAD.WIDE R8, R5, 0x4, R8 &req={4} ?WAIT4_END_GROUP;
@!P0 IMAD.WIDE R6, R15, 0x4, R6 &req={0} ?trans2;
@!P0 LDG.E R8, desc[UR30][R8.64] &wr=0x4 ?trans4;
@!P0 LDG.E R7, desc[UR30][R6.64] &wr=0x4 ?trans1;
@P1 I2FP.F32.S32 R5, R14 &req={2,1} ?WAIT5_END_GROUP;
@P1 FFMA R20, R20, R21, R5 &req={3} ?WAIT6_END_GROUP;
@P1 F2I.TRUNC.NTZ R20, R20 &wr=0x0 ?trans2;
@P1 I2FP.F32.S32 R5, R20 &req={0} ?WAIT5_END_GROUP;
@P1 FFMA R19, R22, R19, R5 &req={5} ?WAIT4_END_GROUP;
@P1 F2I.TRUNC.NTZ R14, R19 &wr=0x0 ?trans2;
@!P0 I2FP.F32.S32 R5, R14 &req={0} ?WAIT5_END_GROUP;
@!P0 FFMA R5, R8, R7, R5 &req={4} ?WAIT4_END_GROUP;
@!P0 F2I.TRUNC.NTZ R14, R5 &rd=0x3 &wr=0x4 ?trans3;
LDC.64 R6, c[0x0][0x390] &req={0} &wr=0x0 ?trans1;
UIADD3 UR5, UPT, UPT, UR5, 0x1, URZ ?trans1;
IADD3 R5, PT, PT, R13, R4, RZ &req={3} ?trans2;
I2FP.F32.S32 R9, R14 &req={4,2,1} ?trans1;
UISETP.NE.AND UP2, UPT, UR5, UR12, UPT ?WAIT6_END_GROUP;
PLOP3.LUT P0, PT, PT, PT, UP2, 0x80, 0x8 ?trans1;
IMAD.WIDE R4, R5, 0x4, R6 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR30][R4.64], R9 &rd=0x0 ?trans7;
@P0 BRA 0x530 ?trans5;
PLOP3.LUT P0, PT, PT, PT, UP1, 0x80, 0x8 ?WAIT13_END_GROUP;
@P0 BRA 0x4d0 ?trans5;
EXIT ?trans5;
BRA 0xf60;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: mm_gpu(float*, float*, float*, int, int, int)
_Z6mm_gpuPfS_S_iii:
s_load_b128 s[4:7], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s6, s5
s_mov_b32 s6, 1
s_cmp_ge_i32 s2, s4
s_cbranch_scc1 .LBB0_2
s_ashr_i32 s3, s2, 31
s_ashr_i32 s7, s4, 31
s_add_i32 s2, s2, s3
s_add_i32 s8, s4, s7
s_xor_b32 s2, s2, s3
s_xor_b32 s8, s8, s7
v_cvt_f32_u32_e32 v1, s2
s_sub_i32 s6, 0, s2
s_xor_b32 s3, s7, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s5, v1
s_mul_i32 s6, s6, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s6, s5, s6
s_add_i32 s5, s5, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s5, s8, s5
s_mul_i32 s6, s5, s2
s_add_i32 s7, s5, 1
s_sub_i32 s6, s8, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s8, s6, s2
s_cmp_ge_u32 s6, s2
s_cselect_b32 s5, s7, s5
s_cselect_b32 s6, s8, s6
s_add_i32 s7, s5, 1
s_cmp_ge_u32 s6, s2
s_cselect_b32 s2, s7, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s2, s2, s3
s_sub_i32 s6, s2, s3
.LBB0_2:
s_load_b32 s2, s[0:1], 0x34
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_cmp_gt_i32 s6, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s14, s2, v[0:1]
s_cselect_b32 s2, -1, 0
v_max_i32_e32 v0, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_11
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_mul_i32 s2, s6, s4
v_mul_lo_u32 v10, v1, s6
v_mul_lo_u32 v0, v2, s6
v_mul_lo_u32 v1, s2, v1
s_cmp_gt_i32 s4, 0
s_cselect_b32 s12, -1, 0
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[4:5], 2
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v6, s7, v10
s_mov_b32 s5, 0
v_lshlrev_b64 v[4:5], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, v6, s4, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s8, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v5, vcc_lo
v_mov_b32_e32 v5, v0
.LBB0_5:
s_and_not1_b32 vcc_lo, exec_lo, s12
s_cbranch_vccnz .LBB0_8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v6, 31, v5
v_mov_b32_e32 v9, v4
v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v8, v3
s_mov_b32 s13, s4
v_lshlrev_b64 v[6:7], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s10, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
.LBB0_7:
global_load_b32 v12, v[8:9], off
global_load_b32 v13, v[6:7], off
v_cvt_f32_i32_e32 v11, v11
v_add_co_u32 v6, vcc_lo, v6, s2
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, v8, 4
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
s_add_i32 s13, s13, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s13, 0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v11, v12, v13
v_cvt_i32_f32_e32 v11, v11
s_cbranch_scc1 .LBB0_7
s_branch .LBB0_9
.LBB0_8:
v_mov_b32_e32 v11, 0
.LBB0_9:
v_add_nc_u32_e32 v6, s5, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cvt_f32_i32_e32 v8, v11
v_add_nc_u32_e32 v5, 1, v5
s_add_i32 s5, s5, 1
s_cmp_lg_u32 s5, s6
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_u32 v6, vcc_lo, s0, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
global_store_b32 v[6:7], v8, off
s_cbranch_scc1 .LBB0_5
v_add_nc_u32_e32 v1, s4, v1
s_add_i32 s7, s7, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s7, s6
s_cbranch_scc1 .LBB0_4
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| mm_gpu | 6,418 | 2,475 | stackv2-00000-of-00015 |
// Demangled: mm_multigpu(float*, float*, float*, int, int, int, int, int)
Function : _Z11mm_multigpuPfS_S_iiiii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
LDC R10, c[0x0][0x398] &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x3a8] &wr=0x2 ?trans1;
S2R R8, SR_TID.X &wr=0x3 ?trans6;
LDC R23, c[0x0][0x3a0] &wr=0x4 ?trans8;
S2UR UR7, SR_CTAID.Y &wr=0x5 ?trans1;
IABS R5, R10 &req={1} ?WAIT7_END_GROUP;
LDC R9, c[0x0][0x3a4] &wr=0x2 ?trans1;
I2F.RP R4, R5 &wr=0x1 ?trans1;
IABS R6, R23 &req={4} ?WAIT6_END_GROUP;
S2UR UR4, SR_CTAID.X &wr=0x3 ?trans1;
MUFU.RCP R4, R4 &req={1} &wr=0x1 ?trans2;
IADD3 R2, PT, PT, R4, 0xffffffe, RZ &req={1} ?WAIT4_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R3, R2 &rd=0x1 &wr=0x4 ?trans2;
HFMA2 R2, -RZ, RZ, 0, 0 &req={1} ?trans1;
IADD3 R0, PT, PT, RZ, -R3, RZ &req={4} ?WAIT5_END_GROUP;
IMAD R7, R0, R5, RZ ?trans1;
MOV R0, R6 ?trans2;
S2R R6, SR_TID.Y &wr=0x5 ?trans1;
IMAD.HI.U32 R3, R3, R7, R2 ?trans1;
LOP3.LUT R2, R23, R10, RZ, 0x3c, !PT ?WAIT5_END_GROUP;
IMAD.HI.U32 R3, R3, R0, RZ ?WAIT5_END_GROUP;
IADD3 R4, PT, PT, -R3, RZ, RZ ?WAIT5_END_GROUP;
IMAD R4, R5, R4, R0 ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P1, PT, R5, R4, PT ?WAIT13_END_GROUP;
@!P1 IADD3 R4, PT, PT, R4, -R5.reuse, RZ ?trans2;
@!P1 IADD3 R3, PT, PT, R3, 0x1, RZ ?trans1;
ISETP.GE.AND P1, PT, R2, RZ, PT ?trans2;
ISETP.GE.U32.AND P0, PT, R4, R5, PT ?trans2;
LDC R4, c[0x0][0x39c] &wr=0x1 ?trans8;
LDC R5, c[0x0][0x364] &wr=0x5 ?trans3;
@P0 IADD3 R3, PT, PT, R3, 0x1, RZ ?trans1;
ISETP.NE.AND P0, PT, R10, RZ, PT ?WAIT3_END_GROUP;
@!P1 IADD3 R3, PT, PT, -R3, RZ, RZ ?trans1;
LDC R7, c[0x0][0x360] &wr=0x3 ?trans1;
IADD3 R4, PT, PT, R4, 0x1, RZ &req={1} ?WAIT8_END_GROUP;
@!P0 LOP3.LUT R3, RZ, R10.reuse, RZ, 0x33, !PT ?trans1;
ISETP.NE.AND P1, PT, R4, R10, PT ?WAIT4_END_GROUP;
IMAD R2, R3, R10, RZ ?WAIT5_END_GROUP;
IADD3 R4, PT, PT, -R2.reuse, R23.reuse, RZ ?trans1;
ISETP.GE.AND P0, PT, R2, R23, PT ?trans1;
IMAD R2, R5, UR7, R6 &req={5} ?trans2;
HFMA2 R5, -RZ, RZ, 0, 5.9604644775390625e-08 ?trans2;
IMAD R6, R9, UR5, RZ &req={2} ?trans1;
SEL R4, R4, RZ, !P1 ?WAIT4_END_GROUP;
ISETP.GE.AND P1, PT, R6, R23, PT ?trans1;
SEL R4, R4, RZ, !P0 ?WAIT5_END_GROUP;
IADD3 R13, PT, PT, R3, R4, RZ ?trans1;
IMAD R3, R7, UR4, R8 &req={3} ?WAIT4_END_GROUP;
ISETP.GT.AND P2, PT, R13, R6, PT ?trans1;
ISETP.GE.AND P0, PT, R2, R13, PT ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R3, R23, P0 ?WAIT7_END_GROUP;
@!P2 BRA 0x4e0 &req={0} ?trans6;
IABS R9, R6.reuse ?trans2;
IABS R10, R13 ?trans2;
I2F.RP R7, R9 &wr=0x0 ?trans1;
IABS R12, R6 ?trans1;
MUFU.RCP R7, R7 &req={0} &wr=0x0 ?trans2;
IADD3 R4, PT, PT, R7, 0xffffffe, RZ &req={0} ?trans2;
IADD3 R7, PT, PT, RZ, -R12, RZ ?WAIT2_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R5, R4 &rd=0x0 &wr=0x1 ?trans2;
MOV R4, RZ &req={0} ?trans1;
IADD3 R8, PT, PT, RZ, -R5, RZ &req={1} ?WAIT5_END_GROUP;
IMAD R11, R8, R9, RZ ?trans1;
MOV R8, R10 ?WAIT3_END_GROUP;
IMAD.HI.U32 R5, R5, R11, R4 ?WAIT6_END_GROUP;
IMAD.HI.U32 R5, R5, R8, RZ ?WAIT4_END_GROUP;
IMAD R4, R5, R7, R8 ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P2, PT, R9, R4, PT ?WAIT13_END_GROUP;
@!P2 IADD3 R4, PT, PT, R4, -R9, RZ ?trans2;
@!P2 IADD3 R5, PT, PT, R5, 0x1, RZ ?WAIT3_END_GROUP;
ISETP.GE.U32.AND P3, PT, R4, R9, PT ?trans1;
LOP3.LUT R4, R13, R6, RZ, 0x3c, !PT ?WAIT5_END_GROUP;
ISETP.GE.AND P2, PT, R4, RZ, PT ?WAIT7_END_GROUP;
@P3 IADD3 R5, PT, PT, R5, 0x1, RZ ?trans1;
ISETP.NE.AND P3, PT, R6, RZ, PT ?WAIT5_END_GROUP;
@!P2 IADD3 R5, PT, PT, -R5, RZ, RZ ?WAIT8_END_GROUP;
@!P3 LOP3.LUT R5, RZ, R6, RZ, 0x33, !PT ?WAIT7_END_GROUP;
MOV R4, 0x1 ?trans1;
@P1 BRA 0x690 ?trans6;
IABS R11, R6.reuse ?trans2;
IABS R12, R6 ?trans2;
I2F.RP R4, R11 &wr=0x0 ?trans2;
IADD3 R12, PT, PT, RZ, -R12, RZ ?trans1;
MUFU.RCP R4, R4 &req={0} &wr=0x0 ?trans2;
IADD3 R8, PT, PT, R4, 0xffffffe, RZ &req={0} ?WAIT4_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R9, R8 &rd=0x0 &wr=0x1 ?trans2;
MOV R8, RZ &req={0} ?trans1;
IADD3 R10, PT, PT, RZ, -R9, RZ &req={1} ?WAIT5_END_GROUP;
IMAD R7, R10, R11, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R7, R9, R7, R8 ?trans1;
MOV R9, R12 ?WAIT5_END_GROUP;
IMAD.HI.U32 R7, R7, R0, RZ ?WAIT4_END_GROUP;
IMAD R0, R7, R9, R0 ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P2, PT, R11, R0, PT ?WAIT13_END_GROUP;
@!P2 IADD3 R0, PT, PT, R0, -R11, RZ ?trans2;
@!P2 IADD3 R7, PT, PT, R7, 0x1, RZ ?WAIT3_END_GROUP;
ISETP.GE.U32.AND P1, PT, R0, R11, PT ?trans1;
LOP3.LUT R0, R6, R23, RZ, 0x3c, !PT ?WAIT5_END_GROUP;
ISETP.GE.AND P2, PT, R0, RZ, PT ?WAIT7_END_GROUP;
@P1 IADD3 R7, PT, PT, R7, 0x1, RZ ?trans1;
ISETP.NE.AND P1, PT, R6, RZ, PT ?WAIT4_END_GROUP;
MOV R4, R7 ?WAIT5_END_GROUP;
@!P2 IADD3 R4, PT, PT, -R4, RZ, RZ ?WAIT4_END_GROUP;
@!P1 LOP3.LUT R4, RZ, R6, RZ, 0x33, !PT ?WAIT7_END_GROUP;
ISETP.LT.OR P0, PT, R5, 0x1, P0 ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
ISETP.GE.AND P0, PT, R4, 0x1, PT ?WAIT13_END_GROUP;
@!P0 EXIT ?trans5;
ISETP.GE.AND P0, PT, R23, 0x1, PT ?trans1;
LDCU.64 UR8, c[0x0][0x358] &wr=0x0 ?trans1;
IMAD R12, R2, R5, RZ ?trans2;
IMAD R3, R3, R4, RZ ?WAIT9_END_GROUP;
@!P0 BRA 0x1320 ?trans5;
LDC.64 R6, c[0x0][0x388] &wr=0x1 ?trans1;
IADD3 R10, PT, PT, R23, R23, RZ ?trans1;
HFMA2 R11, -RZ, RZ, 0, 0 ?trans1;
UMOV UR4, URZ ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R12, R10, 0x4, RZ ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R14, R23, 0x14, R12 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R16, R23, 0x10, R12 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R18, R23, 0xc, R12 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R20, R23, 0x8, R12 ?trans1;
IADD.64 R14, R14, R6.reuse &req={1} ?trans2;
IADD.64 R16, R16, R6.reuse ?trans2;
IADD.64 R18, R18, R6.reuse ?trans2;
IADD.64 R20, R20, R6 ?trans2;
IMAD.WIDE.U32 R22, R23, 0x4, R6 ?WAIT7_END_GROUP;
S2R R7, SR_TID.Y &req={1} &wr=0x1 ?trans1;
LDC R0, c[0x0][0x364] &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x3a0] &req={2} &wr=0x2 ?trans1;
IMAD R0, R0, UR7, R7 &req={1} ?WAIT4_END_GROUP;
IMAD R0, R0, R5, UR4 ?WAIT4_END_GROUP;
IMAD R2, R0, UR5, RZ &req={2} ?trans1;
UMOV UR5, URZ ?WAIT6_END_GROUP;
LDC R0, c[0x0][0x3a0] &req={1} &wr=0x1 ?trans1;
UMOV UR6, URZ ?trans1;
HFMA2 R36, -RZ, RZ, 0, 0 ?trans1;
IADD3 R6, PT, PT, R0, -0x1, RZ &req={1} ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R6, 0x7, PT ?WAIT13_END_GROUP;
@!P0 BRA 0xcb0 &req={2} ?trans5;
LOP3.LUT R8, R0, 0x7ffffff8, RZ, 0xc0, !PT ?trans2;
IADD3 R7, PT, PT, R3, UR5, RZ ?trans1;
MOV R36, RZ ?trans1;
MOV R6, R2 ?trans1;
IADD3 R8, PT, PT, -R8, RZ, RZ ?WAIT7_END_GROUP;
LDC.64 R28, c[0x0][0x388] &req={1} &wr=0x1 ?trans8;
LDC.64 R24, c[0x0][0x380] &wr=0x2 ?trans1;
IMAD.WIDE R28, R7, 0x4, R28 &req={1} ?WAIT5_END_GROUP;
LDG.E R35, desc[UR8][R28.64] &req={0} &rd=0x0 &wr=0x3 ?trans1;
IMAD.WIDE R24, R6, 0x4, R24 &req={2} ?WAIT5_END_GROUP;
LDG.E R37, desc[UR8][R24.64] &wr=0x3 ?trans1;
IMAD.WIDE R26, R7, 0x4, R22 ?WAIT3_END_GROUP;
LDG.E R34, desc[UR8][R24.64+0x4] &wr=0x2 ?trans4;
LDG.E R9, desc[UR8][R26.64] &rd=0x1 &wr=0x2 ?trans1;
IADD.64 R30, R12, R28 ?WAIT7_END_GROUP;
LDG.E R30, desc[UR8][R30.64] &wr=0x4 ?trans4;
LDG.E R31, desc[UR8][R24.64+0x8] &wr=0x4 ?trans1;
IADD.64 R32, R12, R26 ?WAIT7_END_GROUP;
LDG.E R32, desc[UR8][R32.64] &wr=0x5 ?trans4;
LDG.E R33, desc[UR8][R24.64+0xc] &wr=0x5 ?trans1;
I2FP.F32.S32 R36, R36 ?trans1;
IMAD.WIDE R28, R7, 0x4, R20 &req={0} ?WAIT6_END_GROUP;
LDG.E R28, desc[UR8][R28.64] &wr=0x5 ?trans4;
LDG.E R29, desc[UR8][R24.64+0x18] &wr=0x5 ?trans1;
FFMA R36, R37, R35, R36 &req={3} ?WAIT3_END_GROUP;
LDG.E R35, desc[UR8][R24.64+0x10] &wr=0x3 ?trans3;
F2I.TRUNC.NTZ R36, R36 &wr=0x1 ?trans2;
I2FP.F32.S32 R27, R36 &req={1} ?WAIT5_END_GROUP;
FFMA R9, R34, R9, R27 &req={2} ?trans1;
IMAD.WIDE R26, R7, 0x4, R18 ?WAIT3_END_GROUP;
F2I.TRUNC.NTZ R34, R9 &rd=0x0 &wr=0x1 ?trans3;
LDG.E R26, desc[UR8][R26.64] &wr=0x2 ?trans4;
LDG.E R9, desc[UR8][R24.64+0x14] &req={0} &wr=0x2 ?trans1;
IMAD.WIDE R36, R7, 0x4, R14 ?WAIT3_END_GROUP;
LDG.E R27, desc[UR8][R24.64+0x1c] &wr=0x2 ?trans1;
I2FP.F32.S32 R34, R34 &req={1} ?WAIT3_END_GROUP;
LDG.E R36, desc[UR8][R36.64] &wr=0x2 ?trans2;
FFMA R34, R31, R30, R34 &req={4} ?trans1;
IMAD.WIDE R30, R7, 0x4, R16 ?WAIT6_END_GROUP;
LDG.E R30, desc[UR8][R30.64] &rd=0x0 &wr=0x4 ?trans1;
F2I.TRUNC.NTZ R34, R34 &wr=0x1 ?trans2;
I2FP.F32.S32 R34, R34 &req={1} ?WAIT5_END_GROUP;
FFMA R32, R33, R32, R34 &req={5} ?WAIT6_END_GROUP;
F2I.TRUNC.NTZ R32, R32 &wr=0x1 ?trans2;
I2FP.F32.S32 R33, R32 &req={1} ?trans2;
IADD3 R8, PT, PT, R8, 0x8, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R8, RZ, PT ?trans1;
UIADD3 UR6, UPT, UPT, UR6, 0x8, URZ ?trans1;
IMAD R7, R0, 0x8, R7 ?trans1;
IADD3 R6, PT, PT, R6, 0x8, RZ ?trans1;
FFMA R28, R35, R28, R33 &req={3} ?WAIT6_END_GROUP;
F2I.TRUNC.NTZ R28, R28 &wr=0x0 ?trans2;
I2FP.F32.S32 R31, R28 &req={0} ?WAIT5_END_GROUP;
FFMA R9, R9, R26, R31 &req={2} ?WAIT6_END_GROUP;
F2I.TRUNC.NTZ R9, R9 &wr=0x0 ?trans2;
I2FP.F32.S32 R24, R9 &req={0} ?WAIT5_END_GROUP;
FFMA R24, R29, R30, R24 &req={4} ?WAIT6_END_GROUP;
F2I.TRUNC.NTZ R24, R24 &wr=0x0 ?trans2;
I2FP.F32.S32 R26, R24 &req={0} ?WAIT5_END_GROUP;
FFMA R36, R27, R36, R26 ?WAIT6_END_GROUP;
F2I.TRUNC.NTZ R36, R36 &wr=0x1 ?trans1;
@P0 BRA 0x920 ?trans5;
LDC R6, c[0x0][0x3a0] &wr=0x2 ?trans2;
LOP3.LUT R6, R6, 0x7, RZ, 0xc0, !PT &req={2} ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R6, RZ, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x1260 ?trans5;
IADD3 R6, PT, PT, R6, -0x1, RZ ?trans2;
LOP3.LUT P1, R32, R0, 0x3, RZ, 0xc0, !PT ?WAIT3_END_GROUP;
ISETP.GE.U32.AND P0, PT, R6, 0x3, PT ?WAIT13_END_GROUP;
@!P0 BRA 0xfb0 ?trans5;
LDC.64 R8, c[0x0][0x380] &wr=0x2 ?trans1;
IADD3 R27, PT, PT, R3, UR5, RZ ?trans2;
IADD3 R7, PT, PT, R2, UR6, RZ ?WAIT3_END_GROUP;
IMAD R27, R0, UR6, R27 ?trans2;
LDC.64 R24, c[0x0][0x388] &wr=0x3 ?trans1;
MOV R26, R0 ?trans1;
IMAD.WIDE R8, R7, 0x4, R8 &req={2} ?WAIT5_END_GROUP;
LDG.E R6, desc[UR8][R8.64] &req={0} &wr=0x2 ?trans1;
IMAD.WIDE R24, R27, 0x4, R24 &req={3} ?trans1;
MOV R29, R26 ?trans2;
LDG.E R33, desc[UR8][R8.64+0x4] &wr=0x3 ?trans4;
LDG.E R7, desc[UR8][R24.64] &rd=0x0 &wr=0x2 ?trans1;
MOV R28, R24 ?trans1;
HFMA2 R27, -RZ, RZ, 0, 0 ?trans1;
MOV R26, R25 ?trans1;
LDG.E R34, desc[UR8][R8.64+0x8] &wr=0x4 ?trans2;
LEA R28, P0, R29, R28, 0x2 ?WAIT4_END_GROUP;
LEA.HI.X R29, R29, R26, R27, 0x2, P0 ?WAIT5_END_GROUP;
LDG.E R28, desc[UR8][R28.64] &rd=0x5 &wr=0x3 ?trans1;
IADD.64 R30, R12, R24 ?WAIT7_END_GROUP;
LDG.E R31, desc[UR8][R30.64] &wr=0x4 ?trans1;
MOV R26, R0 ?WAIT5_END_GROUP;
IADD.64 R26, R10, R26 ?WAIT5_END_GROUP;
LEA R24, P0, R26, R24, 0x2 &req={0} ?WAIT4_END_GROUP;
LEA.HI.X R25, R26, R25, R27, 0x2, P0 ?trans2;
LDG.E R27, desc[UR8][R8.64+0xc] &wr=0x4 ?trans4;
LDG.E R24, desc[UR8][R24.64] &wr=0x4 ?trans1;
I2FP.F32.S32 R29, R36 &req={5,1} ?trans1;
UIADD3 UR6, UPT, UPT, UR6, 0x4, URZ ?WAIT4_END_GROUP;
FFMA R6, R6, R7, R29 &req={2} ?WAIT6_END_GROUP;
F2I.TRUNC.NTZ R6, R6 &wr=0x0 ?trans2;
I2FP.F32.S32 R26, R6 &req={0} ?WAIT5_END_GROUP;
FFMA R26, R33, R28, R26 &req={3} ?WAIT6_END_GROUP;
F2I.TRUNC.NTZ R26, R26 &wr=0x0 ?trans2;
I2FP.F32.S32 R7, R26 &req={0} ?WAIT5_END_GROUP;
FFMA R7, R34, R31, R7 &req={4} ?WAIT6_END_GROUP;
F2I.TRUNC.NTZ R7, R7 &wr=0x0 ?trans2;
I2FP.F32.S32 R28, R7 &req={0} ?WAIT5_END_GROUP;
FFMA R24, R27, R24, R28 ?WAIT4_END_GROUP;
F2I.TRUNC.NTZ R36, R24 &rd=0x2 &wr=0x3 ?trans3;
@!P1 BRA 0x1260 ?trans5;
ISETP.NE.AND P0, PT, R32, 0x1, PT ?trans1;
LOP3.LUT R6, R0, 0x1, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.U32.AND P1, PT, R6, 0x1, PT ?WAIT7_END_GROUP;
@!P0 BRA 0x1190 ?trans6;
LDC.64 R6, c[0x0][0x380] &wr=0x4 ?trans1;
IADD3 R27, PT, PT, R3, UR5, RZ ?trans2;
IADD3 R25, PT, PT, R2, UR6, RZ ?WAIT3_END_GROUP;
IMAD R27, R0, UR6, R27 ?trans2;
LDC.64 R8, c[0x0][0x388] &wr=0x5 ?trans1;
MOV R24, R0 &req={2} ?trans1;
IMAD.WIDE R6, R25, 0x4, R6 &req={4} ?WAIT5_END_GROUP;
LDG.E R28, desc[UR8][R6.64] &req={0} &wr=0x2 ?trans1;
IMAD.WIDE R8, R27, 0x4, R8 &req={5} ?WAIT4_END_GROUP;
HFMA2 R25, -RZ, RZ, 0, 0 ?trans1;
LDG.E R31, desc[UR8][R6.64+0x4] &wr=0x4 ?trans4;
LDG.E R29, desc[UR8][R8.64] &wr=0x2 ?trans1;
MOV R27, R24 ?trans1;
MOV R26, R8 ?trans1;
MOV R24, R9 ?WAIT4_END_GROUP;
LEA R26, P0, R27, R26, 0x2 ?WAIT4_END_GROUP;
LEA.HI.X R27, R27, R24, R25, 0x2, P0 ?WAIT5_END_GROUP;
LDG.E R26, desc[UR8][R26.64] &wr=0x4 ?trans1;
I2FP.F32.S32 R25, R36 &req={3,1} ?trans1;
UIADD3 UR6, UPT, UPT, UR6, 0x2, URZ ?WAIT4_END_GROUP;
FFMA R25, R28, R29, R25 &req={2} ?WAIT6_END_GROUP;
F2I.TRUNC.NTZ R25, R25 &wr=0x0 ?trans2;
I2FP.F32.S32 R36, R25 &req={0} ?WAIT5_END_GROUP;
FFMA R36, R31, R26, R36 &req={4} ?WAIT6_END_GROUP;
F2I.TRUNC.NTZ R36, R36 &wr=0x4 ?trans2;
@P1 BRA 0x1260 ?trans5;
LDC.64 R8, c[0x0][0x380] &wr=0x5 ?trans1;
IADD3 R27, PT, PT, R3, UR5, RZ ?trans2;
IADD3 R25, PT, PT, R2, UR6, RZ ?WAIT3_END_GROUP;
IMAD R27, R0, UR6, R27 ?trans2;
LDC.64 R6, c[0x0][0x388] &wr=0x2 ?trans1;
IMAD.WIDE R8, R25, 0x4, R8 &req={5} ?WAIT6_END_GROUP;
LDG.E R8, desc[UR8][R8.64] &req={0} &wr=0x5 ?trans1;
IMAD.WIDE R6, R27, 0x4, R6 &req={2} ?WAIT6_END_GROUP;
LDG.E R7, desc[UR8][R6.64] &wr=0x5 ?trans1;
I2FP.F32.S32 R25, R36 &req={4,3,1} ?WAIT5_END_GROUP;
FFMA R36, R8, R7, R25 &req={5} ?WAIT6_END_GROUP;
F2I.TRUNC.NTZ R36, R36 &wr=0x0 ?trans2;
LDC.64 R6, c[0x0][0x390] &wr=0x5 ?trans1;
IADD3 R9, PT, PT, R2, UR5, R3 ?trans1;
UIADD3 UR5, UPT, UPT, UR5, 0x1, URZ ?trans1;
I2FP.F32.S32 R25, R36 &req={4,3,1,0} ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R4, UR5, PT ?trans1;
IMAD.WIDE R6, R9, 0x4, R6 &req={5} ?WAIT5_END_GROUP;
STG.E desc[UR8][R6.64], R25 &rd=0x1 ?trans7;
@P0 BRA 0x870 ?trans5;
UIADD3 UR4, UPT, UPT, UR4, 0x1, URZ ?WAIT6_END_GROUP;
ISETP.NE.AND P0, PT, R5, UR4, PT ?WAIT13_END_GROUP;
@!P0 EXIT ?trans5;
BRA 0x800 ?trans5;
LOP3.LUT R14, R4.reuse, 0x7, RZ, 0xc0, !PT ?trans1;
UMOV UR4, URZ ?trans1;
LOP3.LUT R15, R4.reuse, 0x3, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R16, R4, 0x7ffffff8, RZ, 0xc0, !PT ?trans2;
IADD3 R0, PT, PT, R14, -0x1, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ?WAIT13_END_GROUP;
LDCU UR5, c[0x0][0x3a0] &req={1} &wr=0x1 ?trans1;
ISETP.GE.U32.AND P3, PT, R4, 0x8, PT ?trans1;
IADD3 R0, PT, PT, R12, UR4, RZ ?trans1;
HFMA2 R2, -RZ, RZ, 0, 0 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x1, URZ ?trans1;
ISETP.NE.AND P1, PT, R14, RZ, PT ?WAIT5_END_GROUP;
ISETP.NE.AND P2, PT, R5, UR4, PT ?trans1;
IMAD R13, R0, UR5, R3 &req={1} ?WAIT3_END_GROUP;
@!P3 BRA 0x1520 &req={3,2} ?trans9;
LDC.64 R8, c[0x0][0x390] &wr=0x1 ?trans1;
MOV R2, RZ ?trans1;
UMOV UR5, URZ ?WAIT6_END_GROUP;
UIADD3 UR5, UPT, UPT, UR5, 0x8, URZ ?trans1;
IADD3 R7, PT, PT, R13, R2, RZ &req={2} ?trans2;
IADD3 R2, PT, PT, R2, 0x8, RZ ?WAIT3_END_GROUP;
ISETP.NE.AND P3, PT, R16, UR5, PT ?trans1;
IMAD.WIDE R6, R7, 0x4, R8 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR8][R6.64], RZ &req={0} &rd=0x2 ?trans4;
STG.E desc[UR8][R6.64+0x4], RZ &rd=0x2 ?trans4;
STG.E desc[UR8][R6.64+0x8], RZ &rd=0x2 ?trans4;
STG.E desc[UR8][R6.64+0xc], RZ &rd=0x2 ?trans4;
STG.E desc[UR8][R6.64+0x10], RZ &rd=0x2 ?trans4;
STG.E desc[UR8][R6.64+0x14], RZ &rd=0x2 ?trans4;
STG.E desc[UR8][R6.64+0x18], RZ &rd=0x2 ?trans4;
STG.E desc[UR8][R6.64+0x1c], RZ &rd=0x2 ?trans1;
@P3 BRA 0x1440 ?trans5;
@!P1 BRA 0x16a0 ?trans5;
ISETP.NE.AND P1, PT, R15, RZ, PT ?trans1;
@!P0 BRA 0x15d0 ?WAIT12_END_GROUP;
LDC.64 R6, c[0x0][0x390] &req={2} &wr=0x1 ?trans1;
IADD3 R9, PT, PT, R13, R2, RZ ?trans2;
IADD3 R2, PT, PT, R2, 0x4, RZ ?WAIT3_END_GROUP;
IMAD.WIDE R6, R9, 0x4, R6 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR8][R6.64], RZ &req={0} &rd=0x1 ?trans4;
STG.E desc[UR8][R6.64+0x4], RZ &rd=0x1 ?trans4;
STG.E desc[UR8][R6.64+0x8], RZ &rd=0x1 ?trans4;
STG.E desc[UR8][R6.64+0xc], RZ &rd=0x1 ?trans2;
@!P1 BRA 0x16a0 ?trans5;
ISETP.NE.AND P1, PT, R15, 0x1, PT ?trans1;
LOP3.LUT P3, RZ, R4, 0x1, RZ, 0xc0, !PT ?WAIT12_END_GROUP;
@P1 LDC.64 R6, c[0x0][0x390] &req={2,1} &wr=0x1 ?trans1;
@P1 IADD3 R9, PT, PT, R13, R2, RZ ?trans2;
@P1 IADD3 R2, PT, PT, R2, 0x2, RZ ?WAIT4_END_GROUP;
@P3 IADD3 R13, PT, PT, R13, R2, RZ ?trans1;
@P3 LDC.64 R10, c[0x0][0x390] &wr=0x2 ?trans1;
@P1 IMAD.WIDE R8, R9, 0x4, R6 &req={1} ?WAIT5_END_GROUP;
@P1 STG.E desc[UR8][R8.64], RZ &req={0} &rd=0x3 ?trans1;
@P3 IMAD.WIDE R6, R13, 0x4, R10 &req={2} ?WAIT3_END_GROUP;
@P1 STG.E desc[UR8][R8.64+0x4], RZ &rd=0x3 ?trans4;
@P3 STG.E desc[UR8][R6.64], RZ &rd=0x3 ?trans2;
@P2 BRA 0x1380 ?trans5;
EXIT &req={0} ?trans5;
BRA 0x16c0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: mm_multigpu(float*, float*, float*, int, int, int, int, int)
_Z11mm_multigpuPfS_S_iiiii:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x18
s_load_b32 s9, s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_ashr_i32 s2, s4, 31
s_mul_i32 s7, s9, s7
s_add_i32 s3, s4, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s10, s3, s2
s_ashr_i32 s3, s6, 31
v_cvt_f32_u32_e32 v1, s10
s_sub_i32 s8, 0, s10
s_add_i32 s12, s6, s3
s_xor_b32 s2, s3, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s11, v1
s_mul_i32 s8, s8, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s13, s11, s8
s_xor_b32 s8, s12, s3
s_add_i32 s11, s11, s13
s_mul_hi_u32 s11, s8, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mul_i32 s12, s11, s10
s_add_i32 s13, s11, 1
s_sub_i32 s12, s8, s12
s_sub_i32 s16, s12, s10
s_cmp_ge_u32 s12, s10
s_cselect_b32 s11, s13, s11
s_cselect_b32 s12, s16, s12
s_add_i32 s13, s11, 1
s_cmp_ge_u32 s12, s10
s_cselect_b32 s10, s13, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s10, s10, s2
s_sub_i32 s2, s10, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s10, s2, s4
s_cmp_gt_i32 s6, s10
s_cselect_b32 s11, -1, 0
s_add_i32 s5, s5, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_cmp_eq_u32 s5, s4
s_cselect_b32 s4, -1, 0
s_sub_i32 s5, s6, s10
s_and_b32 s4, s11, s4
s_and_b32 s4, s4, exec_lo
s_cselect_b32 s4, s5, 0
s_mov_b32 s5, 1
s_add_i32 s2, s4, s2
s_mov_b32 s4, 1
s_cmp_le_i32 s2, s7
s_cbranch_scc1 .LBB1_2
s_ashr_i32 s5, s7, 31
s_ashr_i32 s12, s2, 31
s_add_i32 s9, s7, s5
s_add_i32 s13, s2, s12
s_xor_b32 s9, s9, s5
s_xor_b32 s13, s13, s12
v_cvt_f32_u32_e32 v1, s9
s_sub_i32 s11, 0, s9
s_xor_b32 s5, s12, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s10, v1
s_mul_i32 s11, s11, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s11, s10, s11
s_add_i32 s10, s10, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s10, s13, s10
s_mul_i32 s11, s10, s9
s_add_i32 s12, s10, 1
s_sub_i32 s11, s13, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s13, s11, s9
s_cmp_ge_u32 s11, s9
s_cselect_b32 s10, s12, s10
s_cselect_b32 s11, s13, s11
s_add_i32 s12, s10, 1
s_cmp_ge_u32 s11, s9
s_cselect_b32 s9, s12, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s9, s9, s5
s_sub_i32 s5, s9, s5
.LBB1_2:
s_load_b32 s9, s[0:1], 0x3c
s_cmp_ge_i32 s7, s6
s_cbranch_scc1 .LBB1_4
s_ashr_i32 s4, s7, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s4
s_xor_b32 s7, s7, s4
s_xor_b32 s4, s3, s4
v_cvt_f32_u32_e32 v1, s7
s_sub_i32 s11, 0, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s10, v1
s_mul_i32 s11, s11, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s11, s10, s11
s_add_i32 s10, s10, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s10, s8, s10
s_mul_i32 s11, s10, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s8, s8, s11
s_add_i32 s11, s10, 1
s_sub_i32 s12, s8, s7
s_cmp_ge_u32 s8, s7
s_cselect_b32 s10, s11, s10
s_cselect_b32 s8, s12, s8
s_add_i32 s11, s10, 1
s_cmp_ge_u32 s8, s7
s_cselect_b32 s7, s11, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s7, s7, s4
s_sub_i32 s4, s7, s4
.LBB1_4:
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s9, 0xffff
s_lshr_b32 s7, s9, 16
s_mov_b32 s12, 0
v_mad_u64_u32 v[0:1], null, s14, s8, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s7, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s6, v0
v_cmp_gt_i32_e64 s2, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_cmp_gt_i32 s5, 0
s_cselect_b32 s7, -1, 0
s_and_b32 s2, s2, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s7, s2
s_cbranch_execz .LBB1_14
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_mul_i32 s2, s5, s6
v_mul_lo_u32 v10, s5, v1
v_mul_lo_u32 v0, s4, v0
v_mul_lo_u32 v1, s2, v1
s_cmp_gt_i32 s4, 0
s_mov_b32 s7, s3
s_cselect_b32 s13, -1, 0
s_cmp_gt_i32 s6, 0
s_cselect_b32 s14, -1, 0
s_lshl_b64 s[2:3], s[6:7], 2
.LBB1_6:
s_and_not1_b32 vcc_lo, exec_lo, s13
s_cbranch_vccnz .LBB1_13
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v6, s12, v10
s_mov_b32 s7, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_mad_u64_u32 v[2:3], null, v6, s6, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v5, vcc_lo
v_mov_b32_e32 v5, v0
.LBB1_8:
s_and_not1_b32 vcc_lo, exec_lo, s14
s_cbranch_vccnz .LBB1_11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v6, 31, v5
v_mov_b32_e32 v9, v4
v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v8, v3
s_mov_b32 s15, s6
v_lshlrev_b64 v[6:7], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s10, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
.LBB1_10:
global_load_b32 v12, v[8:9], off
global_load_b32 v13, v[6:7], off
v_cvt_f32_i32_e32 v11, v11
v_add_co_u32 v6, vcc_lo, v6, s2
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, v8, 4
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
s_add_i32 s15, s15, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s15, 0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v11, v12, v13
v_cvt_i32_f32_e32 v11, v11
s_cbranch_scc1 .LBB1_10
s_branch .LBB1_12
.LBB1_11:
v_mov_b32_e32 v11, 0
.LBB1_12:
v_add_nc_u32_e32 v6, s7, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cvt_f32_i32_e32 v8, v11
v_add_nc_u32_e32 v5, 1, v5
s_add_i32 s7, s7, 1
s_cmp_lg_u32 s7, s4
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_u32 v6, vcc_lo, s0, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
global_store_b32 v[6:7], v8, off
s_cbranch_scc1 .LBB1_8
.LBB1_13:
v_add_nc_u32_e32 v1, s6, v1
s_add_i32 s12, s12, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s12, s5
s_cbranch_scc1 .LBB1_6
.LBB1_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| mm_multigpu | 9,254 | 4,170 | stackv2-00000-of-00015 |
// Demangled: mandelbrotCalc(RenderSettings)
Function : _Z14mandelbrotCalc14RenderSettings
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
LDCU UR6, c[0x0][0x394] &wr=0x1 ?trans7;
LDC.64 R6, c[0x0][0x390] &wr=0x2 ?trans1;
HFMA2 R2, -RZ, RZ, 0, 5.9604644775390625e-08 ?trans1;
S2R R9, SR_TID.X &wr=0x3 ?trans6;
S2UR UR4, SR_CTAID.X &wr=0x3 ?trans8;
LDC R0, c[0x0][0x360] &wr=0x3 ?trans1;
MUFU.RCP64H R3, UR6 &req={1} &wr=0x2 ?trans1;
LDCU UR5, c[0x0][0x370] &wr=0x1 ?trans1;
DFMA R4, R2, -R6, 1 &req={2} &wr=0x2 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R4, R4, R4, R4 &req={2} &wr=0x2 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R4, R2, R4, R2 &req={2} &wr=0x2 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R4, -R6, 1 &req={2} &wr=0x2 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R4, R2, R4 &req={2} &wr=0x2 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R4, R2, 2 &req={2} &wr=0x2 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R6, R4, -R6, 2 &req={2} &wr=0x2 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R4, R2, R6, R4 &req={2} &wr=0x2 ?trans2;
FFMA R2, RZ, UR6, R5 &req={2} ?trans1;
IMAD R6, R0.reuse, UR4, R9 &req={3} ?trans2;
IMAD R7, R0, UR5, RZ &req={1} ?trans2;
FSETP.GT.AND P0, PT, |R2|, 1.469367938527859385e-39, PT ?WAIT13_END_GROUP;
@P0 BRA 0x3b0 &req={0} ?trans5;
LDCU.64 UR4, c[0x0][0x390] &wr=0x0 ?trans1;
MOV R22, RZ ?trans1;
MOV R23, 0x40000000 ?trans1;
MOV R0, 0x390 ?trans1;
MOV R8, UR4 &req={0} ?trans1;
MOV R21, UR5 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x17f0 ?trans5;
MOV R4, R10 ?trans1;
MOV R5, R11 ?WAIT7_END_GROUP;
LDCU.64 UR4, c[0x0][0x388] &wr=0x0 ?trans1;
MOV R2, 0x1 ?trans1;
BSSY.RECONVERGENT B0, 0x7c0 ?trans1;
I2F.F64 R8, UR5 &req={0} &wr=0x0 ?trans2;
MUFU.RCP64H R3, R9 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
I2F.F64 R14, UR4 &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, -R8, R2, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R10, R10, R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R2, R10, R2 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, -R8, R10, 1 &req={0} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R22, R14, R4 &req={1} &wr=0x0 ?trans2;
FSETP.GEU.AND P1, PT, |R23|, 6.5827683646048100446e-37, PT &req={0} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R10, R2, R10 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R10, R22, R2 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, -R8, R10, R22 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R2, R12, R10 &req={0} &wr=0x0 ?trans2;
FFMA R0, RZ, R9, R3 &req={0} ?WAIT5_END_GROUP;
FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ?WAIT13_END_GROUP;
@P0 BRA P1, 0x7b0 ?trans5;
MOV R21, R9 ?trans1;
MOV R0, 0x790 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x17f0 ?trans5;
MOV R2, R10 ?trans1;
MOV R3, R11 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
LDCU.64 UR4, c[0x0][0x398] &wr=0x0 ?trans1;
BSSY.RECONVERGENT B0, 0xc20 ?trans1;
DADD R16, -R2, UR4 &req={0} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R2, R2, UR4 &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x3a0] &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R22, -R16, R2 &req={0} &rd=0x0 &wr=0x2 ?trans2;
MUFU.RCP64H R3, R15 &req={0} &wr=0x0 ?trans1;
MOV R2, 0x1 ?trans1;
FSETP.GEU.AND P1, PT, |R23|, 6.5827683646048100446e-37, PT &req={2} ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, -R14, R2, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R8, R8, R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R2, R8, R2 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, -R14, R8, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R8, R2, R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R8, R22, R2 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, -R14, R8, R22 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R2, R10, R8 &req={0} &wr=0x0 ?trans2;
FFMA R0, RZ, R15, R3 &req={0} ?WAIT5_END_GROUP;
FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ?WAIT15_END_GROUP;
NOP ?WAIT12_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R4, R4, UR4 &req={1} &wr=0x0 ?trans2;
@P0 BRA P1, 0xc10 &req={0} ?trans5;
MOV R8, R14 ?trans1;
MOV R21, R15 ?trans1;
MOV R0, 0xbf0 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x17f0 ?trans5;
MOV R2, R10 ?trans1;
MOV R3, R11 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
LDCU.64 UR4, c[0x0][0x388] &wr=0x0 ?trans2;
UIMAD UR4, UR4, UR5, URZ &req={0} ?WAIT6_END_GROUP;
ISETP.GE.AND P0, PT, R6, UR4, PT ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LDCU UR5, c[0x0][0x3a8] &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x1 ?trans1;
ISETP.NE.AND P0, PT, RZ, UR5, PT &req={0} ?WAIT13_END_GROUP;
@!P0 BRA 0x1770 &req={1} ?trans5;
I2F.F64.U32 R14, UR5 &wr=0x0 ?trans1;
LDCU UR8, c[0x0][0x3a8] &wr=0x1 ?trans2;
LDC R19, c[0x0][0x388] &wr=0x2 ?trans1;
IABS R12, R6.reuse ?trans1;
BSSY.RECONVERGENT B0, 0xf70 ?trans1;
MOV R18, R6 ?trans1;
IABS R11, R19 &req={2} ?WAIT4_END_GROUP;
I2F.RP R0, R11 &wr=0x2 ?trans2;
MUFU.RCP R0, R0 &req={2} &wr=0x2 ?trans2;
IADD3 R8, PT, PT, R0, 0xffffffe, RZ &req={2} ?WAIT4_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R9, R8 &rd=0x2 &wr=0x3 ?trans2;
HFMA2 R8, -RZ, RZ, 0, 0 &req={2} ?trans1;
IADD3 R10, PT, PT, RZ, -R9, RZ &req={3} ?WAIT5_END_GROUP;
IMAD R13, R10, R11, RZ ?trans1;
MOV R10, R12 ?WAIT3_END_GROUP;
IMAD.HI.U32 R9, R9, R13, R8 ?trans1;
LOP3.LUT R8, R6, R19, RZ, 0x3c, !PT ?WAIT5_END_GROUP;
IMAD.HI.U32 R9, R9, R10, RZ ?WAIT5_END_GROUP;
IADD3 R0, PT, PT, -R9, RZ, RZ ?WAIT5_END_GROUP;
IMAD R0, R11, R0, R10 ?trans1;
LOP3.LUT R10, RZ, R19, RZ, 0x33, !PT ?WAIT4_END_GROUP;
ISETP.GT.U32.AND P1, PT, R11, R0, PT ?WAIT13_END_GROUP;
@!P1 IADD3 R0, PT, PT, R0, -R11.reuse, RZ ?trans2;
@!P1 IADD3 R9, PT, PT, R9, 0x1, RZ ?trans1;
ISETP.GE.AND P1, PT, R8, RZ, PT ?trans2;
ISETP.GE.U32.AND P0, PT, R0, R11, PT ?WAIT13_END_GROUP;
@P0 IADD3 R9, PT, PT, R9, 0x1, RZ ?trans1;
ISETP.NE.AND P0, PT, R19, RZ, PT ?WAIT3_END_GROUP;
@!P1 IADD3 R9, PT, PT, -R9, RZ, RZ ?WAIT5_END_GROUP;
SEL R12, R10, R9, !P0 ?WAIT4_END_GROUP;
I2F.F64 R8, R12 &wr=0x2 ?trans1;
ISETP.GE.AND P1, PT, R12, 0x1, PT ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R8, -R2, R4 &req={2} &rd=0x2 &wr=0x3 ?trans2;
@!P1 BRA 0xf60 &req={3,2} ?trans5;
ISETP.GE.AND P2, PT, R6, RZ, PT ?trans1;
ISETP.GT.U32.AND P1, PT, R11, R0, PT ?trans1;
IADD3 R11, PT, PT, R0, -R11, RZ ?WAIT5_END_GROUP;
SEL R11, R11, R0, !P1 ?WAIT6_END_GROUP;
@!P2 IADD3 R11, PT, PT, -R11, RZ, RZ ?WAIT5_END_GROUP;
SEL R18, R10, R11, !P0 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 &req={1} ?trans5;
I2F.F64 R10, R18 &wr=0x1 ?trans1;
MOV.64 R12, R8 ?trans2;
HFMA2 R0, -RZ, RZ, 0, 0 ?trans1;
BSSY.RECONVERGENT B0, 0x1700 ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R24, R10, R2, R16 &req={1} &wr=0x1 ?trans2;
MOV.64 R10, R24 &req={1} ?WAIT8_END_GROUP;
DMUL R18, R12, R12 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R22, R10, R10, R24 &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R22, -R18, R22 &req={1} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R10, R10, R18 &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DSETP.GT.AND P0, PT, R18, 4, PT &req={1} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R20, R10, R12 &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R20, R10, R12, R20 &req={1} &rd=0x1 &wr=0x2 ?trans2;
@P0 BRA 0x1270 &req={2,1} ?trans5;
IADD3 R0, PT, PT, R0, 0x1, RZ ?trans1;
MOV.64 R10, R22 ?trans2;
DADD R12, R8, R20 &rd=0x1 &wr=0x2 ?trans2;
ISETP.NE.AND P0, PT, R0, UR8, PT ?WAIT13_END_GROUP;
@P0 BRA 0x1000 &req={2,1} ?trans5;
MOV R11, 0xff ?trans1;
BRA 0x16f0 ?trans6;
I2F.F64.U32 R8, R0 &wr=0x1 ?trans1;
BSSY.RECONVERGENT B1, 0x1620 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R22, R8, 510 &req={1} &rd=0x1 &wr=0x2 ?trans2;
MOV R8, 0x1 &req={1} ?trans1;
FSETP.GEU.AND P1, PT, |R23|, 6.5827683646048100446e-37, PT &req={2} ?trans1;
MUFU.RCP64H R9, R15 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, -R14, R8, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R10, R10, R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R8, R10, R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, -R14, R10, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R10, R8, R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R10, R22, R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, -R14, R10, R22 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R8, R12, R10 &req={0} &wr=0x0 ?trans2;
FFMA R0, RZ, R15, R9 &req={0} ?WAIT5_END_GROUP;
FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ?WAIT13_END_GROUP;
@P0 BRA P1, 0x1610 ?trans5;
MOV R8, R14 ?trans1;
MOV R21, R15 ?trans1;
MOV R0, 0x15f0 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x17f0 ?trans5;
MOV R8, R10 ?trans1;
MOV R9, R11 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B1 ?trans5;
DSETP.GT.AND P0, PT, R8, 255, PT &wr=0x0 ?trans2;
FSEL R8, R8, RZ, !P0 &req={0} ?trans1;
FSEL R9, R9, 3.748046875, !P0 ?WAIT15_END_GROUP;
NOP ?trans1;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2I.F64.TRUNC R8, R8 &wr=0x0 ?trans2;
IMAD.SHL.U32 R0, R8.reuse, 0x1000000, RZ &req={0} ?trans2;
IMAD.U32 R11, R8.reuse, 0x10000, RZ ?trans2;
IMAD.SHL.U32 R10, R8, 0x100, RZ ?WAIT5_END_GROUP;
LOP3.LUT R0, R10, R11, R0, 0xfe, !PT ?WAIT4_END_GROUP;
LOP3.LUT R11, R0, 0xff, RZ, 0xfc, !PT ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
LDC.64 R8, c[0x0][0x3b0] &wr=0x1 ?trans2;
IMAD.WIDE R8, R6, 0x4, R8 &req={1} ?trans1;
IADD3 R6, PT, PT, R7, R6, RZ ?WAIT4_END_GROUP;
STG.E desc[UR6][R8.64], R11 &rd=0x2 ?trans1;
ISETP.GE.AND P0, PT, R6, UR4, PT ?WAIT13_END_GROUP;
@!P0 BRA 0xcc0 &req={2} ?trans5;
EXIT ?trans5;
LDC.64 R4, c[0x0][0x3b0] &wr=0x0 ?trans1;
MOV R9, 0xff ?WAIT7_END_GROUP;
IMAD.WIDE R2, R6, 0x4, R4 &req={0} ?trans1;
IADD3 R6, PT, PT, R7, R6, RZ ?WAIT4_END_GROUP;
STG.E desc[UR6][R2.64], R9 &rd=0x1 ?trans1;
ISETP.GE.AND P0, PT, R6, UR4, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x1790 &req={1} ?trans5;
EXIT ?trans5;
FSETP.GEU.AND P2, PT, |R23|, 1.469367938527859385e-39, PT ?trans1;
LOP3.LUT R18, R21.reuse, 0x800fffff, RZ, 0xc0, !PT ?trans1;
BSSY.RECONVERGENT B2, 0x1fe0 ?trans1;
MOV R20, R8.reuse ?trans1;
LOP3.LUT R11, R21, 0x7ff00000, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R19, R18, 0x3ff00000, RZ, 0xfc, !PT ?trans1;
MOV R18, R8 ?trans1;
LOP3.LUT R8, R23, 0x7ff00000, RZ, 0xc0, !PT ?trans1;
FSETP.GEU.AND P0, PT, |R21|, 1.469367938527859385e-39, PT ?trans1;
MOV R24, R22 ?WAIT3_END_GROUP;
@!P2 LOP3.LUT R9, R21, 0x7ff00000, RZ, 0xc0, !PT ?trans1;
ISETP.GE.U32.AND P1, PT, R8.reuse, R11, PT ?trans1;
@!P2 MOV R28, RZ ?trans1;
MOV R10, R8 ?trans2;
@!P2 ISETP.GE.U32.AND P3, PT, R8, R9, PT ?trans1;
MOV R9, 0x1ca00000 ?trans1;
MOV R12, 0x1 ?WAIT4_END_GROUP;
@!P2 SEL R29, R9.reuse, 0x63400000, !P3 ?trans1;
SEL R25, R9, 0x63400000, !P1 ?trans1;
@!P0 DMUL R18, R20, 8.98846567431157953865e+307 &wr=0x0 ?trans2;
MUFU.RCP64H R13, R19 &req={0} &wr=0x0 ?trans1;
@!P2 LOP3.LUT R29, R29, 0x80000000, R23.reuse, 0xf8, !PT ?trans2;
LOP3.LUT R25, R25, 0x800fffff, R23, 0xf8, !PT ?trans2;
@!P2 LOP3.LUT R29, R29, 0x100000, RZ, 0xfc, !PT ?trans2;
@!P0 LOP3.LUT R11, R19, 0x7ff00000, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R31, PT, PT, R11, -0x1, RZ ?WAIT15_END_GROUP;
NOP ?WAIT6_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
@!P2 DFMA R24, R24, 2, -R28 &wr=0x1 ?trans2;
@!P2 LOP3.LUT R10, R25, 0x7ff00000, RZ, 0xc0, !PT &req={1} ?WAIT4_END_GROUP;
IADD3 R30, PT, PT, R10, -0x1, RZ ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R30, 0x7feffffe, PT ?WAIT5_END_GROUP;
ISETP.GT.U32.OR P0, PT, R31, 0x7feffffe, P0 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R26, R12, -R18, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R26, R26, R26, R26 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, R12, R26, R12 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R26, R12, -R18, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, R12, R26, R12 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R26, R12, R24 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R28, R26, -R18, R24 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R28, R12, R28, R26 &req={0} &rd=0x0 &wr=0x1 ?trans2;
@P0 BRA 0x1e90 &req={1,0} ?trans5;
LOP3.LUT R11, R21, 0x7ff00000, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R10, PT, PT, R8.reuse, -R11.reuse, RZ ?trans1;
ISETP.GE.U32.AND P0, PT, R8, R11, PT ?WAIT4_END_GROUP;
VIMNMX.S32 R10, R10, -0x46a00000, !PT ?trans1;
SEL R9, R9, 0x63400000, !P0 ?WAIT4_END_GROUP;
VIMNMX.S32 R10, R10, 0x46a00000, PT ?WAIT5_END_GROUP;
IADD3 R22, PT, PT, -R9, R10, RZ ?trans1;
MOV R10, RZ ?WAIT3_END_GROUP;
IADD3 R11, PT, PT, R22, 0x7fe00000, RZ ?WAIT6_END_GROUP;
DMUL R8, R28, R10 &wr=0x0 ?trans2;
FSETP.GTU.AND P0, PT, |R9|, 1.469367938527859385e-39, PT &req={0} ?WAIT13_END_GROUP;
@P0 BRA 0x1fd0 ?trans5;
DFMA R18, R28, -R18, R24 &wr=0x0 ?trans1;
MOV R10, RZ ?trans1;
FSETP.NEU.AND P0, PT, R19.reuse, RZ, PT &req={0} ?trans1;
LOP3.LUT R21, R19, 0x80000000, R21, 0x48, !PT ?WAIT4_END_GROUP;
LOP3.LUT R11, R21, R11, RZ, 0xfc, !PT ?WAIT8_END_GROUP;
@!P0 BRA 0x1fd0 ?trans5;
IADD3 R13, PT, PT, -R22, RZ, RZ ?trans1;
MOV R12, RZ ?trans1;
DMUL.RP R10, R28, R10 &wr=0x0 ?trans2;
LOP3.LUT R21, R11, R21, RZ, 0x3c, !PT &req={0} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, R8, -R12, R28 &wr=0x0 ?trans2;
IADD3 R12, PT, PT, -R22, -0x43300000, RZ &req={0} ?WAIT5_END_GROUP;
FSETP.NEU.AND P0, PT, |R13|, R12, PT ?WAIT5_END_GROUP;
FSEL R8, R10, R8, !P0 ?trans1;
FSEL R9, R21, R9, !P0 ?trans1;
BRA 0x1fd0 ?trans6;
DSETP.NAN.AND P0, PT, R22, R22, PT &wr=0x0 ?trans2;
@P0 BRA 0x1fb0 &req={0} ?trans5;
DSETP.NAN.AND P0, PT, R20, R20, PT &wr=0x0 ?trans2;
@P0 BRA 0x1f80 &req={0} ?trans5;
ISETP.NE.AND P0, PT, R10, R11, PT ?trans1;
MOV.64 R8, 0xfff8000000000000 ?WAIT12_END_GROUP;
@!P0 BRA 0x1fd0 ?trans5;
ISETP.NE.AND P0, PT, R10, 0x7ff00000, PT ?trans1;
LOP3.LUT R9, R23, 0x80000000, R21, 0x48, !PT ?WAIT4_END_GROUP;
ISETP.EQ.OR P0, PT, R11, RZ, !P0 ?WAIT13_END_GROUP;
@P0 LOP3.LUT R10, R9, 0x7ff00000, RZ, 0xfc, !PT ?trans1;
@!P0 MOV R8, RZ ?trans1;
@P0 MOV R8, RZ ?WAIT3_END_GROUP;
@P0 MOV R9, R10 ?trans1;
BRA 0x1fd0 ?trans6;
LOP3.LUT R9, R21, 0x80000, RZ, 0xfc, !PT ?trans1;
MOV R8, R20 ?trans1;
BRA 0x1fd0 ?trans6;
LOP3.LUT R9, R23, 0x80000, RZ, 0xfc, !PT ?trans1;
MOV R8, R22 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
MOV R10, R8 ?trans1;
MOV R11, R9 ?trans1;
MOV R8, R0 ?trans1;
HFMA2 R9, -RZ, RZ, 0, 0 ?WAIT4_END_GROUP;
RET.REL.NODEC R8 0x0 ?trans5;
BRA 0x2030;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: mandelbrotCalc(RenderSettings)
_Z14mandelbrotCalc14RenderSettings:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x44
s_load_b64 s[2:3], s[0:1], 0x8
s_add_u32 s6, s0, 56
s_addc_u32 s7, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s11, s4, 0xffff
s_mul_i32 s8, s3, s2
v_mad_u64_u32 v[1:2], null, s15, s11, v[0:1]
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_14
s_clause 0x1
s_load_b128 s[12:15], s[0:1], 0x10
s_load_b64 s[16:17], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
v_div_scale_f64 v[2:3], null, s[12:13], s[12:13], 2.0
v_div_scale_f64 v[8:9], vcc_lo, 2.0, s[12:13], 2.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[4:5], v[2:3]
s_waitcnt_depctr 0xfff
v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[6:7], v[8:9], v[4:5]
v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7]
v_cvt_f64_i32_e32 v[7:8], s2
v_div_fixup_f64 v[5:6], v[2:3], s[12:13], 2.0
v_cvt_f64_i32_e32 v[2:3], s3
s_clause 0x1
s_load_b32 s3, s[0:1], 0x28
s_load_b64 s[4:5], s[0:1], 0x30
s_load_b32 s6, s[6:7], 0x0
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s3, 0
s_cselect_b32 s1, -1, 0
s_ashr_i32 s9, s2, 31
s_mul_i32 s6, s6, s11
s_add_i32 s0, s2, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s10, s0, s9
v_cvt_f32_u32_e32 v0, s10
s_sub_i32 s0, 0, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_rcp_iflag_f32_e32 v0, v0
v_mul_f64 v[9:10], v[5:6], v[7:8]
v_add_f64 v[5:6], v[5:6], s[16:17]
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v0, v0
v_div_scale_f64 v[11:12], null, v[2:3], v[2:3], v[9:10]
v_div_scale_f64 v[17:18], vcc_lo, v[9:10], v[2:3], v[9:10]
v_rcp_f64_e32 v[13:14], v[11:12]
s_waitcnt_depctr 0xfff
v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
v_mul_f64 v[15:16], v[17:18], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], -v[11:12], v[15:16], v[17:18]
v_div_fmas_f64 v[11:12], v[11:12], v[13:14], v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[9:10], v[11:12], v[2:3], v[9:10]
v_mul_lo_u32 v2, s0, v0
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v0, v0, v2
v_add_f64 v[3:4], s[14:15], -v[9:10]
v_add_f64 v[9:10], s[14:15], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[9:10], v[9:10], -v[3:4]
v_div_scale_f64 v[11:12], null, v[7:8], v[7:8], v[9:10]
v_div_scale_f64 v[17:18], vcc_lo, v[9:10], v[7:8], v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[13:14], v[11:12]
s_waitcnt_depctr 0xfff
v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[15:16], v[17:18], v[13:14]
v_fma_f64 v[11:12], -v[11:12], v[15:16], v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[11:12], v[11:12], v[13:14], v[15:16]
v_div_fixup_f64 v[7:8], v[11:12], v[7:8], v[9:10]
v_cvt_f64_u32_e32 v[9:10], s3
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v11, v1, v2
v_xor_b32_e32 v11, v11, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v12, v11, v0
v_mul_lo_u32 v13, v12, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v11, v11, v13
v_add_nc_u32_e32 v13, 1, v12
v_subrev_nc_u32_e32 v14, s10, v11
v_cmp_le_u32_e32 vcc_lo, s10, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v12, v12, v13 :: v_dual_cndmask_b32 v11, v11, v14
v_xor_b32_e32 v14, s9, v2
v_add_nc_u32_e32 v13, 1, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s10, v11
v_dual_cndmask_b32 v11, v12, v13 :: v_dual_mov_b32 v12, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v11, v11, v14
v_sub_nc_u32_e32 v11, v11, v14
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e32 0, v11
v_mul_lo_u32 v12, v11, s2
s_delay_alu instid0(VALU_DEP_1)
v_sub_nc_u32_e32 v12, v1, v12
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_cvt_f64_i32_e32 v[12:13], v12
v_cvt_f64_i32_e32 v[14:15], v11
s_mov_b32 s0, 0
s_mov_b32 s14, 0
v_fma_f64 v[11:12], v[7:8], v[12:13], v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[13:14], -v[7:8], v[14:15], v[5:6]
v_dual_mov_b32 v16, v12 :: v_dual_mov_b32 v15, v11
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v18, v14 :: v_dual_mov_b32 v17, v13
.LBB0_6:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mul_f64 v[19:20], v[15:16], v[15:16]
s_or_b32 s12, s12, exec_lo
s_or_b32 s13, s13, exec_lo
s_mov_b32 s16, exec_lo
v_fma_f64 v[21:22], v[17:18], v[17:18], v[19:20]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_nlt_f64_e32 4.0, v[21:22]
s_cbranch_execz .LBB0_8
v_mul_f64 v[21:22], v[17:18], v[17:18]
v_mul_f64 v[15:16], v[17:18], v[15:16]
v_add_f64 v[19:20], v[11:12], v[19:20]
s_add_i32 s15, s14, 1
s_movk_i32 s17, 0xff
s_cmp_eq_u32 s3, s15
s_cselect_b32 s18, -1, 0
s_and_not1_b32 s13, s13, exec_lo
s_and_b32 s18, s18, exec_lo
s_and_not1_b32 s12, s12, exec_lo
s_or_b32 s13, s13, s18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[17:18], v[15:16], 2.0, v[13:14]
v_add_f64 v[15:16], v[19:20], -v[21:22]
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_and_b32 s16, exec_lo, s13
v_dual_mov_b32 v19, s17 :: v_dual_mov_b32 v20, s14
s_or_b32 s0, s16, s0
s_and_not1_b32 s11, s11, exec_lo
s_and_b32 s14, s12, exec_lo
s_or_b32 s11, s11, s14
s_mov_b32 s14, s15
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_6
s_or_b32 exec_lo, exec_lo, s0
s_and_saveexec_b32 s0, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_11
v_cvt_f64_i32_e32 v[11:12], v20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[11:12], 0x407fe000, v[11:12]
v_div_scale_f64 v[13:14], null, v[9:10], v[9:10], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[15:16], v[13:14]
s_waitcnt_depctr 0xfff
v_fma_f64 v[17:18], -v[13:14], v[15:16], 1.0
v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], -v[13:14], v[15:16], 1.0
v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
v_div_scale_f64 v[17:18], vcc_lo, v[11:12], v[9:10], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[19:20], v[17:18], v[15:16]
v_fma_f64 v[13:14], -v[13:14], v[19:20], v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[13:14], v[13:14], v[15:16], v[19:20]
v_div_fixup_f64 v[11:12], v[13:14], v[9:10], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_nlt_f64_e32 vcc_lo, 0x406fe000, v[11:12]
v_cndmask_b32_e32 v12, 0x406fe000, v12, vcc_lo
v_cndmask_b32_e32 v11, 0, v11, vcc_lo
v_cvt_i32_f64_e32 v11, v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v13, 8, v11
v_lshlrev_b32_e32 v12, 24, v11
v_lshl_or_b32 v11, v11, 16, v12
s_delay_alu instid0(VALU_DEP_1)
v_or3_b32 v19, v11, v13, 0xff
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s0
s_branch .LBB0_13
.LBB0_12:
v_mov_b32_e32 v19, 0xff
.LBB0_13:
v_lshlrev_b64 v[11:12], 2, v[1:2]
v_add_nc_u32_e32 v1, s6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_i32_e32 vcc_lo, s8, v1
v_add_co_u32 v11, s0, s4, v11
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v12, s0, s5, v12, s0
s_or_b32 s7, vcc_lo, s7
global_store_b32 v[11:12], v19, off
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_2
.LBB0_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| mandelbrotCalc | 9,471 | 5,525 | stackv2-00000-of-00015 |
// Demangled: kernel_laplacian(float*, long long, int)
Function : _Z16kernel_laplacianPfxi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
HFMA2 R0, -RZ, RZ, 0, 5.9604644775390625e-08 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
NOP ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0.reuse, UR4, PT &req={1} ?trans1;
MOV R7, R0.reuse ?trans1;
IADD3 R0, PT, PT, R0, R0, RZ ?WAIT11_END_GROUP;
@!P0 BRA 0x40 ?trans5;
S2R R0, SR_TID.X &wr=0x1 ?trans1;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
HFMA2 R9, -RZ, RZ, 1.875, 0 ?trans1;
BSSY.RECONVERGENT B0, 0x250 ?trans6;
S2UR UR5, SR_CgaCtaId &wr=0x2 ?trans8;
LDC.64 R2, c[0x0][0x388] &wr=0x3 ?trans8;
LDC.64 R4, c[0x0][0x380] &wr=0x4 ?trans1;
IMAD R6, R7, UR4, R0 &req={1} ?trans1;
UMOV UR4, 0x400 ?trans1;
MOV R7, RZ ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={2} ?WAIT6_END_GROUP;
LEA R0, R0, UR4, 0x2 ?trans1;
ISETP.GE.S64.AND P1, PT, R6, R2, PT &req={3} ?WAIT4_END_GROUP;
STS [R0], R9 &rd=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans1;
ISETP.EQ.OR P0, PT, R6.reuse, RZ, P1 ?trans1;
IMAD.WIDE.U32 R4, R6, 0x4, R4 &req={4} ?WAIT7_END_GROUP;
@P1 BRA 0x240 &req={1} ?trans5;
LDG.E R9, desc[UR4][R4.64+-0x4] &req={2} &wr=0x2 ?trans4;
LDG.E R8, desc[UR4][R4.64+0x4] &wr=0x3 ?trans1;
IADD.64 R2, R2, -0x1 ?WAIT6_END_GROUP;
ISETP.NE.S64.AND P1, PT, R2, R6, PT ?WAIT14_END_GROUP;
@!P1 FADD R2, R9.reuse, 23 &req={2} ?trans1;
FADD R8, R9, R8 &req={3} ?WAIT3_END_GROUP;
@!P1 FMUL R7, R2, 0.5 ?trans1;
FMUL R3, R8, 0.5 ?WAIT5_END_GROUP;
STS [R0], R3 &rd=0x1 ?trans4;
@!P1 STS [R0], R7 &rd=0x1 ?trans2;
BSYNC.RECONVERGENT B0 &req={2} ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT ?trans5;
LDS R3, [R0] &req={1} &wr=0x1 ?trans4;
STG.E desc[UR4][R4.64], R3 &req={1} ?trans1;
EXIT ?trans5;
BRA 0x2a0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: kernel_laplacian(float*, long long, int)
_Z16kernel_laplacianPfxi:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_mov_b32 s2, 0
s_cmp_eq_u32 s3, 0
s_cbranch_scc1 .LBB0_3
s_mov_b32 s4, 1
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, s4
s_lshl_b32 s4, s4, 1
s_cmp_lt_i32 s2, s3
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s2, s15, v[0:1]
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 1.0
v_lshl_add_u32 v0, v0, 2, 0
s_mov_b32 s1, exec_lo
ds_store_b32 v0, v3
s_waitcnt lgkmcnt(0)
v_cmp_le_i64_e32 vcc_lo, s[6:7], v[1:2]
v_cmpx_gt_i64_e64 s[6:7], v[1:2]
s_cbranch_execz .LBB0_6
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_add_u32 s2, s6, -1
s_addc_u32 s3, s7, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v5, s0, s4, v3
v_add_co_ci_u32_e64 v6, s0, s5, v4, s0
v_cmp_eq_u64_e64 s0, s[2:3], v[1:2]
s_clause 0x1
global_load_b32 v3, v[5:6], off offset:-4
global_load_b32 v4, v[5:6], off offset:4
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v3, v4
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v4, 0.5, v4
ds_store_b32 v0, v4
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_6
v_add_f32_e32 v3, 0x41b80000, v3
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v3, 0.5, v3
ds_store_b32 v0, v3
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_ne_u32_e64 s0, 0, v1
s_xor_b32 s1, vcc_lo, -1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s0, s0, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
ds_load_b32 v3, v0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v3, off
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| kernel_laplacian | 1,010 | 1,031 | stackv2-00000-of-00015 |
// Demangled: sumSingleBlock(int*)
Function : _Z14sumSingleBlockPi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R11, SR_TID.X &wr=0x1 ?trans7;
LDC.64 R6, c[0x0][0x380] &wr=0x2 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x3 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x4 ?trans1;
MOV R0, UR4 &req={3} ?trans1;
UMOV UR4, 0x1 ?trans1;
IADD3 R8, PT, PT, R11, R11, RZ &req={4,1} ?WAIT7_END_GROUP;
ISETP.GE.U32.AND P0, PT, R11, R0, PT ?trans1;
BSSY.RECONVERGENT B0, 0x160 ?trans1;
ISETP.GT.U32.AND P1, PT, R0, 0x1, PT ?trans1;
SHF.R.U32.HI R0, RZ, 0x1, R0 ?WAIT10_END_GROUP;
@P0 BRA 0x150 &req={1} ?trans5;
IMAD R5, R8, UR4, RZ ?WAIT5_END_GROUP;
IADD3 R3, PT, PT, R5.reuse, UR4, RZ ?trans1;
IMAD.WIDE R4, R5, 0x4, R6 &req={2} ?WAIT4_END_GROUP;
IMAD.WIDE R2, R3, 0x4, R6 ?trans1;
LDG.E R9, desc[UR6][R4.64] &wr=0x2 ?trans5;
LDG.E R2, desc[UR6][R2.64] &wr=0x2 ?trans2;
IADD3 R9, PT, PT, R2, R9, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R4.64], R9 &rd=0x1 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
UIADD3 UR4, UPT, UPT, UR4, UR4, URZ ?trans1;
@P1 BRA 0x80 ?trans11;
EXIT ?trans5;
BRA 0x190;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: sumSingleBlock(int*)
_Z14sumSingleBlockPi:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB0_5
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 1, v0
s_mov_b32 s3, 1
.LBB0_2:
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e64 s2, v0
s_cbranch_execz .LBB0_4
v_mul_lo_u32 v2, v1, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, s3, v2
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, v5, v4
global_store_b32 v[2:3], v4, off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s2, 1
s_lshl_b32 s3, s3, 1
s_cmp_lt_u32 s2, 2
s_mov_b32 s2, s4
s_cbranch_scc0 .LBB0_2
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| sumSingleBlock | 647 | 730 | stackv2-00000-of-00015 |
// Demangled: sumSingleBlock_shm(int*)
Function : _Z18sumSingleBlock_shmPi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R9, SR_TID.X &wr=0x1 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x2 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x3 ?trans1;
IADD3 R5, PT, PT, R9, R9, RZ &req={1} ?WAIT5_END_GROUP;
IMAD.WIDE.U32 R2, R5, 0x4, R2 &req={2} ?WAIT5_END_GROUP;
LDG.E R6, desc[UR6][R2.64] &req={3} &wr=0x2 ?trans4;
LDG.E R7, desc[UR6][R2.64+0x4] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans2;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x1 ?trans5;
LEA R0, R9, UR4, 0x3 ?trans1;
MOV R4, UR5 &req={1} ?trans1;
UMOV UR5, 0x1 ?WAIT3_END_GROUP;
STS.64 [R0], R6 &req={2,0} &rd=0x1 ?trans3;
ISETP.GE.U32.AND P0, PT, R9, R4, PT ?WAIT13_END_GROUP;
@!P0 IMAD R0, R5, UR5, RZ &req={1} ?WAIT5_END_GROUP;
@!P0 IADD3 R2, PT, PT, R0.reuse, UR5, RZ ?trans2;
@!P0 LEA R0, R0, UR4, 0x2 ?trans1;
UIADD3 UR5, UPT, UPT, UR5, UR5, URZ ?trans1;
@!P0 LEA R2, R2, UR4, 0x2 ?WAIT3_END_GROUP;
@!P0 LDS R3, [R0] ?trans4;
@!P0 LDS R2, [R2] &wr=0x0 ?trans2;
@!P0 IADD3 R3, PT, PT, R2, R3, RZ &req={0} ?WAIT5_END_GROUP;
@!P0 STS [R0], R3 &rd=0x0 ?trans1;
ISETP.GT.U32.AND P0, PT, R4, 0x1, PT ?trans1;
SHF.R.U32.HI R4, RZ, 0x1, R4 ?WAIT12_END_GROUP;
@P0 BRA 0x100 &req={0} ?trans5;
ISETP.NE.AND P0, PT, R9, RZ, PT ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
S2UR UR5, SR_CgaCtaId &wr=0x0 ?trans1;
UMOV UR4, 0x400 ?WAIT7_END_GROUP;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={0} ?WAIT9_END_GROUP;
LDS R5, [UR4] &wr=0x1 ?trans4;
STG.E desc[UR6][R2.64], R5 &req={1} ?trans1;
EXIT ?trans5;
BRA 0x260;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: sumSingleBlock_shm(int*)
_Z18sumSingleBlock_shmPi:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 3, v0
s_load_b32 s0, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
global_load_b64 v[1:2], v3, s[2:3]
v_add_nc_u32_e32 v3, 0, v3
s_and_b32 s0, s0, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s0, 0
s_waitcnt vmcnt(0)
ds_store_2addr_b32 v3, v1, v2 offset1:1
s_cbranch_scc1 .LBB1_5
v_lshlrev_b32_e32 v1, 1, v0
s_mov_b32 s1, 1
.LBB1_2:
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e64 s0, v0
s_cbranch_execz .LBB1_4
v_mul_lo_u32 v2, v1, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, s1, v2
v_lshl_add_u32 v2, v2, 2, 0
v_lshl_add_u32 v3, v3, 2, 0
ds_load_b32 v3, v3
ds_load_b32 v4, v2
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
ds_store_b32 v2, v3
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s0, 1
s_lshl_b32 s1, s1, 1
s_cmp_lt_u32 s0, 2
s_mov_b32 s0, s4
s_cbranch_scc0 .LBB1_2
.LBB1_5:
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_7
v_mov_b32_e32 v0, 0
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[2:3]
.LBB1_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| sumSingleBlock_shm | 961 | 665 | stackv2-00000-of-00015 |
// Demangled: gpu_phase2(unsigned int*, int, int, int)
Function : _Z10gpu_phase2Pjiii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
S2UR UR6, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x390] &wr=0x1 ?trans1;
S2R R0, SR_TID.Y &wr=0x2 ?trans1;
LDCU UR8, c[0x0][0x38c] &wr=0x3 ?trans1;
S2R R6, SR_TID.X &wr=0x4 ?trans4;
LDC.64 R10, c[0x0][0x388] &wr=0x5 ?trans8;
S2UR UR7, SR_CTAID.Y &wr=0x0 ?trans1;
MOV R17, UR8 &req={3} ?trans1;
UISETP.GE.U32.AND UP0, UPT, UR6, UR5, UPT &req={1} ?trans1;
UIADD3 UR4, UPT, UPT, UR6, 0x1, URZ ?WAIT5_END_GROUP;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans1;
IADD3 R8, PT, PT, R11, 0x1f, RZ &req={5} ?WAIT4_END_GROUP;
@!UP0 UIADD3 UR4, UPT, UPT, UR6, URZ, URZ ?trans1;
VIMNMX.S32 R8, R8, R11, !PT ?WAIT3_END_GROUP;
UIADD3 UR4, UPT, UPT, -UR5, UR4, URZ ?trans1;
UISETP.NE.AND UP0, UPT, UR7, URZ, UPT &req={0} ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x0 ?trans1;
IADD3 R5, PT, PT, R8, -R11, RZ ?trans1;
USHF.L.U32 UR4, UR4, 0x5, URZ ?WAIT3_END_GROUP;
IADD3 R4, PT, PT, R5.reuse, 0x1, RZ ?trans1;
ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ?trans1;
USEL UR5, UR4, URZ, UP0 ?trans1;
USEL UR4, UR4, URZ, !UP0 ?trans1;
LOP3.LUT P2, R4, R4, 0x3, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R15, PT, PT, R11.reuse, UR5, R0 &req={2} ?trans2;
IADD3 R0, PT, PT, R11, UR4, R6 &req={4} ?WAIT5_END_GROUP;
VIMNMX.S32 R7, R15.reuse, R0, !PT ?trans1;
IMAD R5, R15, R10, R0 ?WAIT4_END_GROUP;
ISETP.GE.AND P1, PT, R7, R10, PT ?trans1;
IMAD.WIDE R2, R5, 0x4, R2 &req={1} ?trans1;
@!P2 BRA 0x360 &req={0} ?trans11;
LDC R14, c[0x0][0x388] &wr=0x0 ?trans1;
IADD3 R0, PT, PT, R6, UR4, RZ ?trans2;
IADD3 R5, PT, PT, R10, 0x1, RZ ?trans1;
IMAD R9, R15, R10, R11 ?trans1;
IADD3 R17, PT, PT, R4, R11, RZ ?WAIT3_END_GROUP;
IMAD R7, R5, R11, R0 ?trans1;
IADD3 R0, PT, PT, -R4, RZ, RZ ?WAIT7_END_GROUP;
@!P1 LDC.64 R12, c[0x0][0x380] &req={1} &wr=0x1 ?trans1;
@!P1 LDG.E R10, desc[UR6][R2.64] &wr=0x2 ?trans1;
@!P1 IMAD.WIDE R4, R9, 0x4, R12 &req={1} ?WAIT4_END_GROUP;
@!P1 IMAD.WIDE R12, R7, 0x4, R12 ?trans2;
@!P1 LDG.E R4, desc[UR6][R4.64] &wr=0x3 ?trans4;
@!P1 LDG.E R13, desc[UR6][R12.64] &wr=0x3 ?trans1;
IADD3 R0, PT, PT, R0, 0x1, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P2, PT, R0, RZ, PT ?trans1;
IADD3 R9, PT, PT, R9, 0x1, RZ ?trans2;
@!P1 IADD3 R11, PT, PT, R4, R13, RZ &req={3} ?WAIT5_END_GROUP;
@!P1 VIMNMX.U32 R11, R10, R11, PT &req={2} ?WAIT5_END_GROUP;
@!P1 STG.E desc[UR6][R2.64], R11 &rd=0x1 ?trans1;
MOV R10, R14 &req={0} ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R7, R10, RZ ?trans1;
@P2 BRA 0x270 ?trans6;
@!P0 EXIT ?trans5;
LDC R7, c[0x0][0x38c] &wr=0x0 ?trans1;
IADD3 R11, PT, PT, -R8, R17, RZ &req={1} ?trans2;
SHF.R.S32.HI R13, RZ, 0x1f, R10 ?trans1;
IMAD R15, R15, R10.reuse, R17 ?trans1;
MOV R12, R10 ?trans1;
ISETP.GE.AND P0, PT, R11, 0x1, PT ?trans2;
LDC R0, c[0x0][0x388] &wr=0x1 ?trans2;
IADD.64 R18, R12, R12 ?WAIT4_END_GROUP;
IADD.64 R8, R12, R18 ?trans2;
LDC.64 R4, c[0x0][0x380] &wr=0x2 ?trans3;
SHF.L.U64.HI R9, R8.reuse, 0x2, R9 ?trans1;
IMAD.SHL.U32 R8, R8, 0x4, RZ ?trans1;
IADD3 R12, PT, PT, R7, UR4, R6 &req={0} ?trans1;
IMAD.SHL.U32 R6, R18.reuse, 0x4, RZ ?trans1;
SHF.L.U64.HI R7, R18, 0x2, R19 ?WAIT3_END_GROUP;
IMAD R17, R17, R10, R12 ?trans1;
@P0 BRA 0x1160 ?trans6;
IADD3 R12, PT, PT, -R11, 0x1, RZ ?trans2;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x8 ?WAIT3_END_GROUP;
ISETP.GT.AND P2, PT, R12, 0xc, PT ?WAIT13_END_GROUP;
@!P2 BRA 0xce0 ?trans5;
LDC R10, c[0x0][0x388] &wr=0x0 ?trans1;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x80 ?WAIT7_END_GROUP;
LDC.64 R12, c[0x0][0x380] &wr=0x3 ?trans6;
IMAD R23, R10.reuse, 0x4, R17 &req={4,3,0} ?trans1;
BSSY.RECONVERGENT B0, 0x6e0 ?trans3;
IMAD R19, R10, 0x4, R23 ?trans1;
@P1 BRA 0x6d0 ?trans6;
IMAD.WIDE R20, R15, 0x4, R12.reuse &req={3} ?trans1;
LDG.E R14, desc[UR6][R2.64] &wr=0x3 ?trans3;
IMAD.WIDE R16, R17, 0x4, R12 ?trans1;
LDG.E R18, desc[UR6][R20.64] &wr=0x4 ?trans4;
LDG.E R25, desc[UR6][R16.64] &wr=0x4 ?trans2;
IADD3 R25, PT, PT, R18, R25, RZ &req={4} ?WAIT5_END_GROUP;
VIMNMX.U32 R29, R14, R25, PT &req={3} ?trans1;
IMAD.WIDE R24, R10, 0x4, R16 ?WAIT4_END_GROUP;
STG.E desc[UR6][R2.64], R29 &rd=0x0 ?trans4;
LDG.E R25, desc[UR6][R24.64] &wr=0x3 ?trans4;
LDG.E R14, desc[UR6][R20.64+0x4] &wr=0x3 ?trans1;
IADD.64 R26, R6, R16 ?WAIT3_END_GROUP;
IADD3 R14, PT, PT, R14, R25, RZ &req={3} ?WAIT5_END_GROUP;
VIMNMX.U32 R31, R29, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R31 &rd=0x0 ?trans4;
LDG.E R27, desc[UR6][R26.64] &wr=0x3 ?trans4;
LDG.E R14, desc[UR6][R20.64+0x8] &wr=0x3 ?trans1;
IADD.64 R16, R8, R16 ?WAIT3_END_GROUP;
IADD3 R14, PT, PT, R14, R27, RZ &req={3} ?WAIT5_END_GROUP;
VIMNMX.U32 R33, R31, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R33 &rd=0x0 ?trans4;
LDG.E R14, desc[UR6][R20.64+0xc] &wr=0x3 ?trans4;
LDG.E R17, desc[UR6][R16.64] &wr=0x3 ?trans2;
IADD3 R14, PT, PT, R14, R17, RZ &req={3} ?WAIT5_END_GROUP;
VIMNMX.U32 R25, R33, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R25 &rd=0x0 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
BSSY.RECONVERGENT B0, 0x8c0 ?trans4;
@P1 BRA 0x8b0 ?trans5;
IADD3 R17, PT, PT, R15, 0x4, RZ ?trans1;
IMAD.WIDE R20, R23, 0x4, R12.reuse &req={3} ?trans1;
LDG.E R27, desc[UR6][R2.64] &wr=0x3 ?trans3;
IMAD.WIDE R16, R17, 0x4, R12 ?trans1;
LDG.E R23, desc[UR6][R20.64] &wr=0x4 ?trans4;
LDG.E R14, desc[UR6][R16.64] &wr=0x4 ?trans2;
IADD3 R14, PT, PT, R14, R23, RZ &req={4} ?trans1;
IMAD.WIDE R22, R10, 0x4, R20 ?WAIT4_END_GROUP;
VIMNMX.U32 R27, R14, R27, PT &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R27 &rd=0x4 ?trans4;
LDG.E R23, desc[UR6][R22.64] &wr=0x3 ?trans4;
LDG.E R14, desc[UR6][R16.64+0x4] &wr=0x3 ?trans1;
IADD.64 R24, R6, R20 &req={0} ?WAIT3_END_GROUP;
IADD3 R14, PT, PT, R14, R23, RZ &req={3} ?WAIT5_END_GROUP;
VIMNMX.U32 R29, R27, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R29 &rd=0x4 ?trans4;
LDG.E R25, desc[UR6][R24.64] &wr=0x3 ?trans4;
LDG.E R14, desc[UR6][R16.64+0x8] &wr=0x3 ?trans1;
IADD.64 R20, R8, R20 ?WAIT3_END_GROUP;
IADD3 R14, PT, PT, R14, R25, RZ &req={3} ?WAIT5_END_GROUP;
VIMNMX.U32 R31, R29, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R31 &rd=0x4 ?trans4;
LDG.E R14, desc[UR6][R16.64+0xc] &wr=0x3 ?trans4;
LDG.E R21, desc[UR6][R20.64] &wr=0x3 ?trans2;
IADD3 R14, PT, PT, R14, R21, RZ &req={3} ?WAIT5_END_GROUP;
VIMNMX.U32 R23, R31, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R23 &rd=0x4 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
BSSY.RECONVERGENT B0, 0xaa0 ?trans4;
@P1 BRA 0xa90 ?trans5;
IADD3 R17, PT, PT, R15, 0x8, RZ ?trans1;
IMAD.WIDE R20, R19, 0x4, R12.reuse &req={3} ?trans1;
LDG.E R27, desc[UR6][R2.64] &req={4} &wr=0x3 ?trans3;
IMAD.WIDE R16, R17, 0x4, R12 ?trans1;
LDG.E R23, desc[UR6][R20.64] &wr=0x4 ?trans4;
LDG.E R14, desc[UR6][R16.64] &wr=0x4 ?trans2;
IADD3 R14, PT, PT, R14, R23, RZ &req={4} ?trans1;
IMAD.WIDE R22, R10, 0x4, R20 ?WAIT4_END_GROUP;
VIMNMX.U32 R27, R14, R27, PT &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R27 &rd=0x3 ?trans4;
LDG.E R23, desc[UR6][R22.64] &wr=0x4 ?trans4;
LDG.E R14, desc[UR6][R16.64+0x4] &wr=0x4 ?trans1;
IADD.64 R24, R6, R20 &req={0} ?WAIT3_END_GROUP;
IADD3 R14, PT, PT, R14, R23, RZ &req={4} ?WAIT5_END_GROUP;
VIMNMX.U32 R29, R27, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R29 &rd=0x3 ?trans4;
LDG.E R25, desc[UR6][R24.64] &wr=0x4 ?trans4;
LDG.E R14, desc[UR6][R16.64+0x8] &wr=0x4 ?trans1;
IADD.64 R20, R8, R20 ?WAIT3_END_GROUP;
IADD3 R14, PT, PT, R14, R25, RZ &req={4} ?WAIT5_END_GROUP;
VIMNMX.U32 R31, R29, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R31 &rd=0x3 ?trans4;
LDG.E R14, desc[UR6][R16.64+0xc] &wr=0x4 ?trans4;
LDG.E R21, desc[UR6][R20.64] &wr=0x4 ?trans2;
IADD3 R14, PT, PT, R14, R21, RZ &req={4} ?WAIT5_END_GROUP;
VIMNMX.U32 R23, R31, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R23 &rd=0x3 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
BSSY.RECONVERGENT B0, 0xc90 ?trans1;
IMAD R21, R10, 0x4, R19 ?WAIT3_END_GROUP;
@P1 BRA 0xc80 ?trans5;
IADD3 R17, PT, PT, R15, 0xc, RZ ?trans1;
IMAD.WIDE R18, R21, 0x4, R12.reuse &req={3} ?trans1;
LDG.E R27, desc[UR6][R2.64] &req={4} &wr=0x3 ?trans3;
IMAD.WIDE R16, R17, 0x4, R12 ?trans1;
LDG.E R23, desc[UR6][R18.64] &wr=0x4 ?trans4;
LDG.E R14, desc[UR6][R16.64] &wr=0x4 ?trans2;
IADD3 R14, PT, PT, R14, R23, RZ &req={4} ?trans1;
IMAD.WIDE R22, R10, 0x4, R18 ?WAIT4_END_GROUP;
VIMNMX.U32 R27, R14, R27, PT &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R27 &rd=0x3 ?trans4;
LDG.E R23, desc[UR6][R22.64] &wr=0x4 ?trans4;
LDG.E R14, desc[UR6][R16.64+0x4] &wr=0x4 ?trans1;
IADD.64 R24, R6, R18 &req={0} ?WAIT3_END_GROUP;
IADD3 R14, PT, PT, R14, R23, RZ &req={4} ?WAIT5_END_GROUP;
VIMNMX.U32 R29, R27, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R29 &rd=0x3 ?trans4;
LDG.E R25, desc[UR6][R24.64] &wr=0x4 ?trans4;
LDG.E R14, desc[UR6][R16.64+0x8] &wr=0x4 ?trans1;
IADD.64 R18, R8, R18 ?WAIT3_END_GROUP;
IADD3 R14, PT, PT, R14, R25, RZ &req={4} ?WAIT5_END_GROUP;
VIMNMX.U32 R31, R29, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R31 &rd=0x3 ?trans4;
LDG.E R14, desc[UR6][R16.64+0xc] &wr=0x4 ?trans4;
LDG.E R19, desc[UR6][R18.64] &wr=0x4 ?trans2;
IADD3 R14, PT, PT, R14, R19, RZ &req={4} ?WAIT5_END_GROUP;
VIMNMX.U32 R23, R31, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R23 &rd=0x3 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
IADD3 R11, PT, PT, R11, 0x10, RZ ?trans1;
IMAD R17, R10, 0x4, R21 ?trans1;
IADD3 R15, PT, PT, R15, 0x10, RZ ?WAIT3_END_GROUP;
ISETP.GE.AND P2, PT, R11, -0xb, PT ?WAIT13_END_GROUP;
@!P2 BRA 0x4f0 ?trans5;
IADD3 R12, PT, PT, -R11, 0x1, RZ &req={3} ?WAIT5_END_GROUP;
ISETP.GT.AND P2, PT, R12, 0x4, PT ?WAIT13_END_GROUP;
@!P2 BRA 0x1140 ?trans5;
BSSY.RECONVERGENT B0, 0xf10 ?trans1;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x80 ?trans1;
IMAD R19, R10, 0x4, R17 ?trans2;
@P1 BRA 0xf00 ?trans10;
LDC.64 R20, c[0x0][0x380] &wr=0x3 ?trans1;
LDG.E R25, desc[UR6][R2.64] &req={0} &wr=0x5 ?trans1;
IMAD.WIDE R12, R15, 0x4, R20 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE R16, R17, 0x4, R20 ?trans1;
LDG.E R14, desc[UR6][R12.64] &wr=0x3 ?trans4;
LDG.E R21, desc[UR6][R16.64] &wr=0x3 ?trans2;
IADD3 R14, PT, PT, R14, R21, RZ &req={3} ?trans1;
IMAD.WIDE R20, R10, 0x4, R16 ?WAIT4_END_GROUP;
VIMNMX.U32 R25, R14, R25, PT &req={5} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R25 &rd=0x3 ?trans4;
LDG.E R21, desc[UR6][R20.64] &wr=0x5 ?trans4;
LDG.E R14, desc[UR6][R12.64+0x4] &wr=0x5 ?trans1;
IADD.64 R22, R6, R16 &req={4} ?WAIT3_END_GROUP;
IADD3 R14, PT, PT, R14, R21, RZ &req={5} ?WAIT5_END_GROUP;
VIMNMX.U32 R27, R25, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R27 &rd=0x3 ?trans4;
LDG.E R23, desc[UR6][R22.64] &wr=0x4 ?trans4;
LDG.E R14, desc[UR6][R12.64+0x8] &wr=0x4 ?trans1;
IADD.64 R16, R8, R16 ?WAIT3_END_GROUP;
IADD3 R14, PT, PT, R14, R23, RZ &req={4} ?WAIT5_END_GROUP;
VIMNMX.U32 R29, R27, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R29 &rd=0x3 ?trans4;
LDG.E R14, desc[UR6][R12.64+0xc] &wr=0x4 ?trans4;
LDG.E R17, desc[UR6][R16.64] &wr=0x4 ?trans2;
IADD3 R14, PT, PT, R14, R17, RZ &req={4} ?WAIT5_END_GROUP;
VIMNMX.U32 R21, R29, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R21 &rd=0x3 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
BSSY.RECONVERGENT B0, 0x1120 ?trans1;
IADD3 R11, PT, PT, R11, 0x4, RZ ?trans1;
IMAD R17, R10, 0x4, R19 ?trans1;
IADD3 R16, PT, PT, R15, 0x4, RZ ?trans1;
@P1 BRA 0x1110 ?trans6;
LDC.64 R14, c[0x0][0x380] &wr=0x5 ?trans1;
LDG.E R23, desc[UR6][R2.64] &req={4} &wr=0x4 ?trans1;
IMAD.WIDE R12, R16, 0x4, R14 &req={5} ?WAIT4_END_GROUP;
IMAD.WIDE R14, R19, 0x4, R14 ?trans1;
LDG.E R18, desc[UR6][R12.64] &wr=0x5 ?trans4;
LDG.E R19, desc[UR6][R14.64] &wr=0x5 ?trans2;
IADD3 R18, PT, PT, R18, R19, RZ &req={5} ?WAIT5_END_GROUP;
VIMNMX.U32 R23, R18, R23, PT &req={4} ?trans1;
IMAD.WIDE R18, R10, 0x4, R14 ?WAIT4_END_GROUP;
STG.E desc[UR6][R2.64], R23 &rd=0x4 ?trans4;
LDG.E R19, desc[UR6][R18.64] &wr=0x5 ?trans4;
LDG.E R10, desc[UR6][R12.64+0x4] &wr=0x5 ?trans1;
IADD.64 R20, R6, R14 &req={3} ?WAIT3_END_GROUP;
IADD3 R10, PT, PT, R10, R19, RZ &req={5} ?WAIT5_END_GROUP;
VIMNMX.U32 R25, R23, R10, PT &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R25 &rd=0x4 ?trans4;
LDG.E R21, desc[UR6][R20.64] &wr=0x3 ?trans4;
LDG.E R10, desc[UR6][R12.64+0x8] &wr=0x3 ?trans1;
IADD.64 R14, R8, R14 ?WAIT3_END_GROUP;
IADD3 R10, PT, PT, R10, R21, RZ &req={3} ?WAIT5_END_GROUP;
VIMNMX.U32 R27, R25, R10, PT ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R27 &rd=0x4 ?trans4;
LDG.E R10, desc[UR6][R12.64+0xc] &wr=0x3 ?trans4;
LDG.E R15, desc[UR6][R14.64] &wr=0x3 ?trans2;
IADD3 R10, PT, PT, R10, R15, RZ &req={3} ?WAIT5_END_GROUP;
VIMNMX.U32 R19, R27, R10, PT ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R19 &rd=0x4 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
IADD3 R11, PT, PT, R11, 0x4, RZ ?trans2;
IADD3 R15, PT, PT, R16, 0x4, RZ ?WAIT7_END_GROUP;
ISETP.NE.OR P0, PT, R11, 0x1, P0 ?WAIT13_END_GROUP;
@!P0 EXIT ?trans5;
IADD3 R11, PT, PT, R11, 0x4, RZ ?trans1;
BSSY.RECONVERGENT B0, 0x1350 ?trans4;
ISETP.NE.AND P0, PT, R11, 0x1, PT ?trans1;
@P1 BRA 0x1340 &req={0} ?WAIT12_END_GROUP;
IMAD.WIDE R12, R15, 0x4, R4.reuse &req={2} ?trans1;
LDG.E R10, desc[UR6][R2.64] &wr=0x2 ?trans3;
IMAD.WIDE R18, R17, 0x4, R4 &req={4} ?trans1;
LDG.E R14, desc[UR6][R12.64] &wr=0x4 ?trans4;
LDG.E R21, desc[UR6][R18.64] &req={3} &wr=0x4 ?trans2;
IADD3 R21, PT, PT, R14, R21, RZ &req={4} ?WAIT5_END_GROUP;
VIMNMX.U32 R25, R10, R21, PT &req={2,0} ?trans1;
IMAD.WIDE R20, R0, 0x4, R18 &req={1} ?WAIT4_END_GROUP;
STG.E desc[UR6][R2.64], R25 &rd=0x0 ?trans4;
LDG.E R21, desc[UR6][R20.64] &wr=0x2 ?trans4;
LDG.E R10, desc[UR6][R12.64+0x4] &wr=0x2 ?trans1;
IADD.64 R22, R6, R18 ?WAIT3_END_GROUP;
IADD3 R10, PT, PT, R10, R21, RZ &req={2} ?WAIT5_END_GROUP;
VIMNMX.U32 R27, R25, R10, PT ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R27 &rd=0x0 ?trans4;
LDG.E R23, desc[UR6][R22.64] &wr=0x2 ?trans4;
LDG.E R10, desc[UR6][R12.64+0x8] &wr=0x2 ?trans1;
IADD.64 R18, R8, R18 ?WAIT3_END_GROUP;
IADD3 R10, PT, PT, R10, R23, RZ &req={2} ?WAIT5_END_GROUP;
VIMNMX.U32 R29, R27, R10, PT ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R29 &rd=0x0 ?trans4;
LDG.E R10, desc[UR6][R12.64+0xc] &wr=0x2 ?trans4;
LDG.E R19, desc[UR6][R18.64] &wr=0x2 ?trans2;
IADD3 R10, PT, PT, R10, R19, RZ &req={2} ?WAIT5_END_GROUP;
VIMNMX.U32 R21, R29, R10, PT ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R21 &rd=0x0 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
IMAD R17, R0, 0x4, R17 &req={1} ?trans1;
IADD3 R15, PT, PT, R15, 0x4, RZ ?trans1;
@P0 BRA 0x1160 ?trans6;
EXIT ?trans5;
BRA 0x1390;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: gpu_phase2(unsigned int*, int, int, int)
_Z10gpu_phase2Pjiii:
s_load_b128 s[4:7], s[0:1], 0x8
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_cmp_ge_u32 s14, s6
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_cmp_lg_u32 s2, 0
s_addc_u32 s2, s14, 0
s_sub_i32 s2, s2, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b32 s2, s2, 5
s_add_i32 s2, s2, s5
s_cmp_eq_u32 s15, 0
s_cselect_b32 s3, s5, s2
s_cselect_b32 s2, s2, s5
v_add_nc_u32_e32 v3, s3, v1
v_add_nc_u32_e32 v2, s2, v0
s_load_b64 s[2:3], s[0:1], 0x0
s_add_i32 s1, s5, 31
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v4, v3, s4
v_max_i32_e32 v3, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e32 vcc_lo, s4, v3
v_add_nc_u32_e32 v0, v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[5:6], 2, v[0:1]
v_mad_u64_u32 v[0:1], null, s5, s4, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v2, s0, s2, v5
v_add_co_ci_u32_e64 v3, s0, s3, v6, s0
.LBB1_1:
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB1_3
v_add_nc_u32_e32 v5, s5, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[0:1]
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v5, s0, s2, v5
v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v7, s0, s2, v7
v_add_co_ci_u32_e64 v8, s0, s3, v8, s0
s_clause 0x2
global_load_b32 v1, v[5:6], off
global_load_b32 v5, v[7:8], off
global_load_b32 v6, v[2:3], off
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v1, v5, v1
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_min_u32_e32 v1, v6, v1
global_store_b32 v[2:3], v1, off
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(VALU_DEP_3)
v_add_nc_u32_e32 v0, s4, v0
s_add_i32 s0, s5, 1
s_cmp_ge_i32 s5, s1
s_mov_b32 s5, s0
s_cbranch_scc0 .LBB1_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| gpu_phase2 | 8,424 | 1,313 | stackv2-00000-of-00015 |
// Demangled: gpu_phase3(unsigned int*, int, int, int)
Function : _Z10gpu_phase3Pjiii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
S2R R4, SR_TID.Y &wr=0x2 ?trans1;
S2R R8, SR_TID.X &wr=0x3 ?trans6;
LDC R5, c[0x0][0x390] &wr=0x4 ?trans8;
S2UR UR5, SR_CTAID.Y &wr=0x5 ?trans8;
LDC.64 R10, c[0x0][0x388] &wr=0x0 ?trans1;
UIADD3 UR6, UPT, UPT, UR4, 0x1, URZ &req={1} ?WAIT6_END_GROUP;
MOV R17, UR6 ?trans1;
ISETP.LE.U32.AND P0, PT, R5.reuse, UR4, PT &req={4} ?trans1;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans3;
LDCU UR6, c[0x0][0x38c] &wr=0x4 ?trans1;
ISETP.LE.U32.AND P1, PT, R5, UR5, PT &req={5} ?trans1;
UIADD3 UR7, UPT, UPT, UR5, 0x1, URZ ?WAIT7_END_GROUP;
@!P0 IADD3 R17, PT, PT, RZ, UR4, RZ ?trans1;
MOV R0, UR7 ?trans1;
IADD3 R6, PT, PT, R11, 0x1f, RZ &req={0} ?trans2;
IADD3 R15, PT, PT, R4, R11, RZ &req={2} ?trans2;
IADD3 R17, PT, PT, -R5.reuse, R17, RZ ?trans2;
IADD3 R7, PT, PT, R8, R11.reuse, RZ &req={3} ?trans2;
@!P1 IADD3 R0, PT, PT, RZ, UR5, RZ ?trans1;
VIMNMX.S32 R6, R6, R11, !PT ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans1;
MOV R13, UR6 &req={4} ?trans1;
IADD3 R0, PT, PT, -R5, R0, RZ ?WAIT2_END_GROUP;
IADD3 R5, PT, PT, R6, -R11, RZ ?WAIT3_END_GROUP;
IMAD R15, R0, 0x20, R15 ?trans1;
IADD3 R4, PT, PT, R5, 0x1, RZ ?trans1;
IMAD R0, R17, 0x20, R7 ?trans1;
ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ?trans2;
LOP3.LUT P2, R4, R4, 0x3, RZ, 0xc0, !PT ?trans1;
IMAD R5, R15.reuse, R10, R0 ?trans1;
VIMNMX.S32 R9, R15, R0, !PT ?WAIT3_END_GROUP;
IMAD.WIDE R2, R5, 0x4, R2 &req={1} ?trans2;
ISETP.GE.AND P1, PT, R9, R10, PT ?WAIT6_END_GROUP;
@!P2 BRA 0x3a0 &req={0} ?trans7;
LDC R14, c[0x0][0x388] &wr=0x0 ?trans1;
IADD3 R0, PT, PT, R10, 0x1, RZ ?trans1;
IMAD R19, R15, R10, R11 ?trans1;
IADD3 R13, PT, PT, R4.reuse, R11.reuse, RZ ?trans2;
IADD3 R12, PT, PT, -R4, RZ, RZ ?trans1;
IMAD R0, R0, R11, R8 ?WAIT4_END_GROUP;
IMAD R11, R17, 0x20, R0 ?WAIT7_END_GROUP;
@!P1 LDC.64 R8, c[0x0][0x380] &req={1} &wr=0x1 ?trans1;
@!P1 LDG.E R0, desc[UR4][R2.64] &wr=0x2 ?trans1;
@!P1 IMAD.WIDE R4, R19, 0x4, R8 &req={1} ?WAIT4_END_GROUP;
@!P1 IMAD.WIDE R8, R11, 0x4, R8 ?trans2;
@!P1 LDG.E R4, desc[UR4][R4.64] &wr=0x3 ?trans4;
@!P1 LDG.E R9, desc[UR4][R8.64] &wr=0x3 ?trans1;
IADD3 R12, PT, PT, R12, 0x1, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P2, PT, R12, RZ, PT ?trans1;
MOV R10, R14 &req={0} ?trans1;
IADD3 R19, PT, PT, R19, 0x1, RZ ?WAIT4_END_GROUP;
IADD3 R11, PT, PT, R11, R10, RZ ?trans2;
@!P1 IADD3 R21, PT, PT, R4, R9, RZ &req={3} ?WAIT5_END_GROUP;
@!P1 VIMNMX.U32 R21, R0, R21, PT &req={2} ?WAIT5_END_GROUP;
@!P1 STG.E desc[UR4][R2.64], R21 &rd=0x1 ?trans1;
@P2 BRA 0x2b0 ?trans5;
@!P0 EXIT ?trans5;
LDC R0, c[0x0][0x388] &wr=0x0 ?trans1;
IADD3 R11, PT, PT, -R6, R13, RZ ?trans2;
SHF.R.S32.HI R9, RZ, 0x1f, R10 ?trans1;
IMAD R12, R13, R10.reuse, R7 ?trans1;
MOV R8, R10.reuse ?trans1;
IMAD R15, R15, R10, R13 ?trans1;
ISETP.GE.AND P0, PT, R11, 0x1, PT ?trans1;
IMAD R17, R17, 0x20, R12 ?trans1;
LDC.64 R4, c[0x0][0x380] &wr=0x2 ?trans1;
IADD.64 R18, R8, R8 ?WAIT4_END_GROUP;
IADD.64 R8, R8, R18 ?trans2;
IMAD.SHL.U32 R6, R18.reuse, 0x4, RZ ?trans1;
SHF.L.U64.HI R7, R18, 0x2, R19 ?trans2;
SHF.L.U64.HI R9, R8.reuse, 0x2, R9 ?trans1;
IMAD.SHL.U32 R8, R8, 0x4, RZ ?trans1;
@P0 BRA 0x1190 ?trans6;
IADD3 R12, PT, PT, -R11, 0x1, RZ ?trans2;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x8 ?WAIT3_END_GROUP;
ISETP.GT.AND P2, PT, R12, 0xc, PT ?WAIT13_END_GROUP;
@!P2 BRA 0xd10 ?trans5;
LDC R10, c[0x0][0x388] &wr=0x3 ?trans1;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x80 ?WAIT7_END_GROUP;
LDC.64 R12, c[0x0][0x380] &wr=0x4 ?trans6;
IMAD R23, R10.reuse, 0x4, R17 &req={3,1} ?trans1;
BSSY.RECONVERGENT B0, 0x710 ?trans3;
IMAD R19, R10, 0x4, R23 ?trans1;
@P1 BRA 0x700 ?trans6;
IMAD.WIDE R20, R15, 0x4, R12.reuse &req={4,1} ?trans1;
LDG.E R14, desc[UR4][R2.64] &wr=0x3 ?trans3;
IMAD.WIDE R16, R17, 0x4, R12 ?trans1;
LDG.E R18, desc[UR4][R20.64] &wr=0x4 ?trans4;
LDG.E R25, desc[UR4][R16.64] &wr=0x4 ?trans2;
IADD3 R25, PT, PT, R18, R25, RZ &req={4} ?WAIT5_END_GROUP;
VIMNMX.U32 R29, R14, R25, PT &req={3} ?trans1;
IMAD.WIDE R24, R10, 0x4, R16 ?WAIT4_END_GROUP;
STG.E desc[UR4][R2.64], R29 &rd=0x3 ?trans4;
LDG.E R25, desc[UR4][R24.64] &wr=0x4 ?trans4;
LDG.E R14, desc[UR4][R20.64+0x4] &wr=0x4 ?trans1;
IADD.64 R26, R6, R16 ?WAIT3_END_GROUP;
IADD3 R14, PT, PT, R14, R25, RZ &req={4} ?WAIT5_END_GROUP;
VIMNMX.U32 R31, R29, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R31 &rd=0x3 ?trans4;
LDG.E R27, desc[UR4][R26.64] &wr=0x4 ?trans4;
LDG.E R14, desc[UR4][R20.64+0x8] &wr=0x4 ?trans1;
IADD.64 R16, R8, R16 ?WAIT3_END_GROUP;
IADD3 R14, PT, PT, R14, R27, RZ &req={4} ?WAIT5_END_GROUP;
VIMNMX.U32 R33, R31, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R33 &rd=0x3 ?trans4;
LDG.E R14, desc[UR4][R20.64+0xc] &wr=0x4 ?trans4;
LDG.E R17, desc[UR4][R16.64] &wr=0x4 ?trans2;
IADD3 R14, PT, PT, R14, R17, RZ &req={4} ?WAIT5_END_GROUP;
VIMNMX.U32 R25, R33, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R25 &rd=0x3 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
BSSY.RECONVERGENT B0, 0x8f0 ?trans4;
@P1 BRA 0x8e0 ?trans5;
IADD3 R17, PT, PT, R15, 0x4, RZ ?trans1;
IMAD.WIDE R20, R23, 0x4, R12.reuse &req={4,1} ?trans1;
LDG.E R27, desc[UR4][R2.64] &wr=0x4 ?trans3;
IMAD.WIDE R16, R17, 0x4, R12 ?trans1;
LDG.E R23, desc[UR4][R20.64] &wr=0x5 ?trans4;
LDG.E R14, desc[UR4][R16.64] &wr=0x5 ?trans2;
IADD3 R14, PT, PT, R14, R23, RZ &req={5} ?trans1;
IMAD.WIDE R22, R10, 0x4, R20 ?WAIT4_END_GROUP;
VIMNMX.U32 R27, R14, R27, PT &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R27 &rd=0x1 ?trans4;
LDG.E R23, desc[UR4][R22.64] &wr=0x4 ?trans4;
LDG.E R14, desc[UR4][R16.64+0x4] &wr=0x4 ?trans1;
IADD.64 R24, R6, R20 &req={3} ?WAIT3_END_GROUP;
IADD3 R14, PT, PT, R14, R23, RZ &req={4} ?WAIT5_END_GROUP;
VIMNMX.U32 R29, R27, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R29 &rd=0x1 ?trans4;
LDG.E R25, desc[UR4][R24.64] &wr=0x3 ?trans4;
LDG.E R14, desc[UR4][R16.64+0x8] &wr=0x3 ?trans1;
IADD.64 R20, R8, R20 ?WAIT3_END_GROUP;
IADD3 R14, PT, PT, R14, R25, RZ &req={3} ?WAIT5_END_GROUP;
VIMNMX.U32 R31, R29, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R31 &rd=0x1 ?trans4;
LDG.E R14, desc[UR4][R16.64+0xc] &wr=0x3 ?trans4;
LDG.E R21, desc[UR4][R20.64] &wr=0x3 ?trans2;
IADD3 R14, PT, PT, R14, R21, RZ &req={3} ?WAIT5_END_GROUP;
VIMNMX.U32 R23, R31, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R23 &rd=0x1 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
BSSY.RECONVERGENT B0, 0xad0 ?trans4;
@P1 BRA 0xac0 ?trans5;
IADD3 R17, PT, PT, R15, 0x8, RZ ?trans1;
IMAD.WIDE R20, R19, 0x4, R12.reuse &req={4,1} ?trans1;
LDG.E R27, desc[UR4][R2.64] &wr=0x4 ?trans3;
IMAD.WIDE R16, R17, 0x4, R12 ?trans1;
LDG.E R23, desc[UR4][R20.64] &wr=0x5 ?trans4;
LDG.E R14, desc[UR4][R16.64] &wr=0x5 ?trans2;
IADD3 R14, PT, PT, R14, R23, RZ &req={5} ?trans1;
IMAD.WIDE R22, R10, 0x4, R20 ?WAIT4_END_GROUP;
VIMNMX.U32 R27, R14, R27, PT &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R27 &rd=0x1 ?trans4;
LDG.E R23, desc[UR4][R22.64] &wr=0x4 ?trans4;
LDG.E R14, desc[UR4][R16.64+0x4] &wr=0x4 ?trans1;
IADD.64 R24, R6, R20 &req={3} ?WAIT3_END_GROUP;
IADD3 R14, PT, PT, R14, R23, RZ &req={4} ?WAIT5_END_GROUP;
VIMNMX.U32 R29, R27, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R29 &rd=0x1 ?trans4;
LDG.E R25, desc[UR4][R24.64] &wr=0x3 ?trans4;
LDG.E R14, desc[UR4][R16.64+0x8] &wr=0x3 ?trans1;
IADD.64 R20, R8, R20 ?WAIT3_END_GROUP;
IADD3 R14, PT, PT, R14, R25, RZ &req={3} ?WAIT5_END_GROUP;
VIMNMX.U32 R31, R29, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R31 &rd=0x1 ?trans4;
LDG.E R14, desc[UR4][R16.64+0xc] &wr=0x3 ?trans4;
LDG.E R21, desc[UR4][R20.64] &wr=0x3 ?trans2;
IADD3 R14, PT, PT, R14, R21, RZ &req={3} ?WAIT5_END_GROUP;
VIMNMX.U32 R23, R31, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R23 &rd=0x1 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
BSSY.RECONVERGENT B0, 0xcc0 ?trans1;
IMAD R21, R10, 0x4, R19 &req={1} ?WAIT3_END_GROUP;
@P1 BRA 0xcb0 ?trans5;
IADD3 R17, PT, PT, R15, 0xc, RZ ?trans1;
IMAD.WIDE R18, R21, 0x4, R12.reuse &req={4} ?trans1;
LDG.E R27, desc[UR4][R2.64] &wr=0x4 ?trans3;
IMAD.WIDE R16, R17, 0x4, R12 ?trans1;
LDG.E R23, desc[UR4][R18.64] &wr=0x5 ?trans4;
LDG.E R14, desc[UR4][R16.64] &wr=0x5 ?trans2;
IADD3 R14, PT, PT, R14, R23, RZ &req={5} ?trans1;
IMAD.WIDE R22, R10, 0x4, R18 ?WAIT4_END_GROUP;
VIMNMX.U32 R27, R14, R27, PT &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R27 &rd=0x1 ?trans4;
LDG.E R23, desc[UR4][R22.64] &wr=0x4 ?trans4;
LDG.E R14, desc[UR4][R16.64+0x4] &wr=0x4 ?trans1;
IADD.64 R24, R6, R18 &req={3} ?WAIT3_END_GROUP;
IADD3 R14, PT, PT, R14, R23, RZ &req={4} ?WAIT5_END_GROUP;
VIMNMX.U32 R29, R27, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R29 &rd=0x1 ?trans4;
LDG.E R25, desc[UR4][R24.64] &wr=0x3 ?trans4;
LDG.E R14, desc[UR4][R16.64+0x8] &wr=0x3 ?trans1;
IADD.64 R18, R8, R18 ?WAIT3_END_GROUP;
IADD3 R14, PT, PT, R14, R25, RZ &req={3} ?WAIT5_END_GROUP;
VIMNMX.U32 R31, R29, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R31 &rd=0x1 ?trans4;
LDG.E R14, desc[UR4][R16.64+0xc] &wr=0x3 ?trans4;
LDG.E R19, desc[UR4][R18.64] &wr=0x3 ?trans2;
IADD3 R14, PT, PT, R14, R19, RZ &req={3} ?WAIT5_END_GROUP;
VIMNMX.U32 R23, R31, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R23 &rd=0x1 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
IADD3 R11, PT, PT, R11, 0x10, RZ ?trans1;
IMAD R17, R10, 0x4, R21 ?trans1;
IADD3 R15, PT, PT, R15, 0x10, RZ ?WAIT3_END_GROUP;
ISETP.GE.AND P2, PT, R11, -0xb, PT ?WAIT13_END_GROUP;
@!P2 BRA 0x520 ?trans5;
IADD3 R12, PT, PT, -R11, 0x1, RZ &req={4} ?WAIT5_END_GROUP;
ISETP.GT.AND P2, PT, R12, 0x4, PT ?WAIT13_END_GROUP;
@!P2 BRA 0x1170 ?trans5;
BSSY.RECONVERGENT B0, 0xf40 ?trans1;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x80 ?trans1;
IMAD R19, R10, 0x4, R17 ?trans2;
@P1 BRA 0xf30 ?trans10;
LDC.64 R20, c[0x0][0x380] &req={1} &wr=0x1 ?trans1;
LDG.E R25, desc[UR4][R2.64] &req={3} &wr=0x3 ?trans1;
IMAD.WIDE R12, R15, 0x4, R20 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE R16, R17, 0x4, R20 ?trans1;
LDG.E R14, desc[UR4][R12.64] &wr=0x4 ?trans4;
LDG.E R21, desc[UR4][R16.64] &wr=0x4 ?trans2;
IADD3 R14, PT, PT, R14, R21, RZ &req={4} ?trans1;
IMAD.WIDE R20, R10, 0x4, R16 ?WAIT4_END_GROUP;
VIMNMX.U32 R25, R14, R25, PT &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R25 &rd=0x4 ?trans4;
LDG.E R21, desc[UR4][R20.64] &wr=0x3 ?trans4;
LDG.E R14, desc[UR4][R12.64+0x4] &wr=0x3 ?trans1;
IADD.64 R22, R6, R16 ?WAIT3_END_GROUP;
IADD3 R14, PT, PT, R14, R21, RZ &req={3} ?WAIT5_END_GROUP;
VIMNMX.U32 R27, R25, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R27 &rd=0x4 ?trans4;
LDG.E R23, desc[UR4][R22.64] &wr=0x3 ?trans4;
LDG.E R14, desc[UR4][R12.64+0x8] &wr=0x3 ?trans1;
IADD.64 R16, R8, R16 ?WAIT3_END_GROUP;
IADD3 R14, PT, PT, R14, R23, RZ &req={3} ?WAIT5_END_GROUP;
VIMNMX.U32 R29, R27, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R29 &rd=0x4 ?trans4;
LDG.E R14, desc[UR4][R12.64+0xc] &wr=0x3 ?trans4;
LDG.E R17, desc[UR4][R16.64] &wr=0x3 ?trans2;
IADD3 R14, PT, PT, R14, R17, RZ &req={3} ?WAIT5_END_GROUP;
VIMNMX.U32 R21, R29, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R21 &rd=0x4 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
BSSY.RECONVERGENT B0, 0x1150 ?trans1;
IADD3 R11, PT, PT, R11, 0x4, RZ ?trans1;
IMAD R17, R10, 0x4, R19 ?trans1;
IADD3 R16, PT, PT, R15, 0x4, RZ ?trans1;
@P1 BRA 0x1140 ?trans6;
LDC.64 R14, c[0x0][0x380] &wr=0x5 ?trans1;
LDG.E R23, desc[UR4][R2.64] &req={3,1} &wr=0x3 ?trans1;
IMAD.WIDE R12, R16, 0x4, R14 &req={5} ?WAIT4_END_GROUP;
IMAD.WIDE R14, R19, 0x4, R14 ?trans1;
LDG.E R18, desc[UR4][R12.64] &wr=0x5 ?trans4;
LDG.E R19, desc[UR4][R14.64] &wr=0x5 ?trans2;
IADD3 R18, PT, PT, R18, R19, RZ &req={5} ?WAIT5_END_GROUP;
VIMNMX.U32 R23, R18, R23, PT &req={3} ?trans1;
IMAD.WIDE R18, R10, 0x4, R14 ?WAIT4_END_GROUP;
STG.E desc[UR4][R2.64], R23 &rd=0x1 ?trans4;
LDG.E R19, desc[UR4][R18.64] &wr=0x3 ?trans4;
LDG.E R10, desc[UR4][R12.64+0x4] &wr=0x3 ?trans1;
IADD.64 R20, R6, R14 &req={4} ?WAIT3_END_GROUP;
IADD3 R10, PT, PT, R10, R19, RZ &req={3} ?WAIT5_END_GROUP;
VIMNMX.U32 R25, R23, R10, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R25 &rd=0x1 ?trans4;
LDG.E R21, desc[UR4][R20.64] &wr=0x3 ?trans4;
LDG.E R10, desc[UR4][R12.64+0x8] &wr=0x3 ?trans1;
IADD.64 R14, R8, R14 ?WAIT3_END_GROUP;
IADD3 R10, PT, PT, R10, R21, RZ &req={3} ?WAIT5_END_GROUP;
VIMNMX.U32 R27, R25, R10, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R27 &rd=0x1 ?trans4;
LDG.E R10, desc[UR4][R12.64+0xc] &wr=0x3 ?trans4;
LDG.E R15, desc[UR4][R14.64] &wr=0x3 ?trans2;
IADD3 R10, PT, PT, R10, R15, RZ &req={3} ?WAIT5_END_GROUP;
VIMNMX.U32 R19, R27, R10, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R19 &rd=0x1 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
IADD3 R11, PT, PT, R11, 0x4, RZ ?trans2;
IADD3 R15, PT, PT, R16, 0x4, RZ ?WAIT7_END_GROUP;
ISETP.NE.OR P0, PT, R11, 0x1, P0 ?WAIT13_END_GROUP;
@!P0 EXIT ?trans5;
IADD3 R11, PT, PT, R11, 0x4, RZ ?trans1;
BSSY.RECONVERGENT B0, 0x1380 ?trans4;
ISETP.NE.AND P0, PT, R11, 0x1, PT ?trans1;
@P1 BRA 0x1370 ?WAIT12_END_GROUP;
IMAD.WIDE R12, R15, 0x4, R4.reuse &req={2} ?trans1;
LDG.E R10, desc[UR4][R2.64] &wr=0x2 ?trans3;
IMAD.WIDE R18, R17, 0x4, R4 &req={1} ?trans1;
LDG.E R14, desc[UR4][R12.64] &wr=0x5 ?trans4;
LDG.E R21, desc[UR4][R18.64] &req={4} &wr=0x5 ?trans2;
IADD3 R21, PT, PT, R14, R21, RZ &req={5} ?WAIT5_END_GROUP;
VIMNMX.U32 R25, R10, R21, PT &req={3,2} ?trans1;
IMAD.WIDE R20, R0, 0x4, R18 &req={0} ?WAIT4_END_GROUP;
STG.E desc[UR4][R2.64], R25 &rd=0x0 ?trans4;
LDG.E R21, desc[UR4][R20.64] &wr=0x2 ?trans4;
LDG.E R10, desc[UR4][R12.64+0x4] &wr=0x2 ?trans1;
IADD.64 R22, R6, R18 ?WAIT3_END_GROUP;
IADD3 R10, PT, PT, R10, R21, RZ &req={2} ?WAIT5_END_GROUP;
VIMNMX.U32 R27, R25, R10, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R27 &rd=0x0 ?trans4;
LDG.E R23, desc[UR4][R22.64] &wr=0x2 ?trans4;
LDG.E R10, desc[UR4][R12.64+0x8] &wr=0x2 ?trans1;
IADD.64 R18, R8, R18 ?WAIT3_END_GROUP;
IADD3 R10, PT, PT, R10, R23, RZ &req={2} ?WAIT5_END_GROUP;
VIMNMX.U32 R29, R27, R10, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R29 &rd=0x0 ?trans4;
LDG.E R10, desc[UR4][R12.64+0xc] &wr=0x2 ?trans4;
LDG.E R19, desc[UR4][R18.64] &wr=0x2 ?trans2;
IADD3 R10, PT, PT, R10, R19, RZ &req={2} ?WAIT5_END_GROUP;
VIMNMX.U32 R21, R29, R10, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R21 &rd=0x0 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
IMAD R17, R0, 0x4, R17 &req={0} ?trans1;
IADD3 R15, PT, PT, R15, 0x4, RZ ?trans1;
@P0 BRA 0x1190 ?trans6;
EXIT ?trans5;
BRA 0x13c0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: gpu_phase3(unsigned int*, int, int, int)
_Z10gpu_phase3Pjiii:
s_load_b128 s[4:7], s[0:1], 0x8
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_cmp_ge_u32 s14, s6
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_cmp_lg_u32 s2, 0
s_addc_u32 s2, s14, 0
s_sub_i32 s2, s2, s6
s_cmp_ge_u32 s15, s6
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_cmp_lg_u32 s3, 0
s_addc_u32 s3, s15, 0
s_sub_i32 s3, s3, s6
s_lshl_b32 s6, s2, 5
s_lshl_b32 s3, s3, 5
v_add3_u32 v5, s6, s5, v3
v_add3_u32 v2, s3, s5, v1
s_load_b64 s[2:3], s[0:1], 0x0
s_add_i32 s0, s4, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s1, s5, s0
v_mul_lo_u32 v4, v2, s4
v_max_i32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cmp_gt_i32_e32 vcc_lo, s4, v2
v_add3_u32 v2, s6, s1, v3
v_add_nc_u32_e32 v0, v4, v5
s_add_i32 s1, s5, 31
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s0, s2, v0
v_add_co_ci_u32_e64 v1, s0, s3, v1, s0
.LBB2_1:
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB2_3
v_add_nc_u32_e32 v5, s5, v4
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[7:8], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, s0, s2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
v_add_co_u32 v7, s0, s2, v7
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v8, s0, s3, v8, s0
s_clause 0x2
global_load_b32 v3, v[5:6], off
global_load_b32 v5, v[7:8], off
global_load_b32 v6, v[0:1], off
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v3, v5, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_min_u32_e32 v3, v6, v3
global_store_b32 v[0:1], v3, off
.LBB2_3:
s_or_b32 exec_lo, exec_lo, s6
v_add_nc_u32_e32 v2, s4, v2
s_add_i32 s0, s5, 1
s_cmp_ge_i32 s5, s1
s_mov_b32 s5, s0
s_cbranch_scc0 .LBB2_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| gpu_phase3 | 8,448 | 1,330 | stackv2-00000-of-00015 |
// Demangled: gpu_primary(unsigned int*, int, int)
Function : _Z11gpu_primaryPjii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
LDC.64 R10, c[0x0][0x388] &wr=0x1 ?trans1;
S2R R0, SR_TID.Y &wr=0x2 ?trans1;
LDCU UR6, c[0x0][0x38c] &wr=0x3 ?trans1;
S2R R8, SR_TID.X &wr=0x4 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans4;
LDC.64 R2, c[0x0][0x380] &wr=0x5 ?trans1;
MOV R13, UR6 &req={3} ?trans1;
IADD3 R6, PT, PT, R11, 0x1f, RZ &req={1} ?WAIT5_END_GROUP;
VIMNMX.S32 R6, R6, R11.reuse, !PT ?trans1;
IADD3 R15, PT, PT, R0, R11, RZ &req={2} ?WAIT4_END_GROUP;
IADD3 R4, PT, PT, R6, -R11.reuse, RZ ?trans2;
IADD3 R17, PT, PT, R8, R11, RZ &req={4} ?trans2;
IADD3 R0, PT, PT, R4.reuse, 0x1, RZ ?trans1;
ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ?trans2;
VIMNMX.S32 R7, R15.reuse, R17, !PT ?trans1;
IMAD R5, R15, R10, R17 ?trans1;
LOP3.LUT P2, R0, R0, 0x3, RZ, 0xc0, !PT ?WAIT3_END_GROUP;
ISETP.GE.AND P1, PT, R7, R10, PT ?trans1;
IMAD.WIDE R2, R5, 0x4, R2 &req={5} ?WAIT9_END_GROUP;
@!P2 BRA 0x2a0 &req={0} ?trans5;
LDC R12, c[0x0][0x388] &wr=0x0 ?trans1;
IADD3 R4, PT, PT, R10, 0x1, RZ ?trans2;
IADD3 R13, PT, PT, R0.reuse, R11.reuse, RZ ?trans1;
IMAD R19, R15, R10, R11 ?trans1;
IADD3 R0, PT, PT, -R0, RZ, RZ ?trans1;
IMAD R7, R4, R11, R8 ?WAIT7_END_GROUP;
@!P1 LDC.64 R8, c[0x0][0x380] &req={1} &wr=0x1 ?trans1;
@!P1 LDG.E R10, desc[UR4][R2.64] &wr=0x2 ?trans1;
@!P1 IMAD.WIDE R4, R19, 0x4, R8 &req={1} ?WAIT4_END_GROUP;
@!P1 IMAD.WIDE R8, R7, 0x4, R8 ?trans2;
@!P1 LDG.E R4, desc[UR4][R4.64] &wr=0x3 ?trans4;
@!P1 LDG.E R9, desc[UR4][R8.64] &wr=0x3 ?trans1;
IADD3 R0, PT, PT, R0, 0x1, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P2, PT, R0, RZ, PT ?trans1;
IADD3 R19, PT, PT, R19, 0x1, RZ ?trans2;
@!P1 IADD3 R11, PT, PT, R4, R9, RZ &req={3} ?WAIT5_END_GROUP;
@!P1 VIMNMX.U32 R11, R10, R11, PT &req={2} ?WAIT5_END_GROUP;
@!P1 STG.E desc[UR4][R2.64], R11 &rd=0x1 ?trans1;
MOV R10, R12 &req={0} ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R7, R10, RZ ?trans1;
@P2 BRA 0x1b0 ?trans6;
@!P0 EXIT ?trans5;
LDC R0, c[0x0][0x388] &wr=0x0 ?trans1;
IADD3 R11, PT, PT, -R6, R13, RZ &req={1} ?trans2;
SHF.R.S32.HI R9, RZ, 0x1f, R10 ?trans1;
IMAD R17, R13, R10.reuse, R17 ?trans1;
MOV R8, R10.reuse ?trans1;
IMAD R15, R15, R10, R13 ?trans1;
ISETP.GE.AND P0, PT, R11, 0x1, PT ?trans1;
LDC.64 R4, c[0x0][0x380] &wr=0x1 ?trans2;
IADD.64 R18, R8, R8 ?WAIT4_END_GROUP;
IADD.64 R6, R8, R18 ?trans2;
IMAD.SHL.U32 R8, R18.reuse, 0x4, RZ ?trans1;
SHF.L.U64.HI R9, R18, 0x2, R19 ?trans2;
SHF.L.U64.HI R7, R6.reuse, 0x2, R7 ?trans1;
IMAD.SHL.U32 R6, R6, 0x4, RZ ?trans1;
@P0 BRA 0x1080 ?trans6;
IADD3 R12, PT, PT, -R11, 0x1, RZ ?trans2;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x8 ?WAIT3_END_GROUP;
ISETP.GT.AND P2, PT, R12, 0xc, PT ?WAIT13_END_GROUP;
@!P2 BRA 0xc00 ?trans5;
LDC R10, c[0x0][0x388] &wr=0x2 ?trans1;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x80 ?WAIT7_END_GROUP;
LDC.64 R12, c[0x0][0x380] &wr=0x3 ?trans6;
IMAD R23, R10.reuse, 0x4, R17 &req={4,3,2} ?trans1;
BSSY.RECONVERGENT B0, 0x600 ?trans3;
IMAD R19, R10, 0x4, R23 ?trans1;
@P1 BRA 0x5f0 ?trans6;
IMAD.WIDE R20, R15, 0x4, R12.reuse &req={3} ?trans1;
LDG.E R14, desc[UR4][R2.64] &wr=0x2 ?trans3;
IMAD.WIDE R16, R17, 0x4, R12 ?trans1;
LDG.E R18, desc[UR4][R20.64] &wr=0x3 ?trans4;
LDG.E R25, desc[UR4][R16.64] &wr=0x3 ?trans2;
IADD3 R25, PT, PT, R18, R25, RZ &req={3} ?WAIT5_END_GROUP;
VIMNMX.U32 R29, R14, R25, PT &req={2} ?trans1;
IMAD.WIDE R24, R10, 0x4, R16 ?WAIT4_END_GROUP;
STG.E desc[UR4][R2.64], R29 &rd=0x2 ?trans4;
LDG.E R25, desc[UR4][R24.64] &wr=0x3 ?trans4;
LDG.E R14, desc[UR4][R20.64+0x4] &wr=0x3 ?trans1;
IADD.64 R26, R8, R16 ?WAIT3_END_GROUP;
IADD3 R14, PT, PT, R14, R25, RZ &req={3} ?WAIT5_END_GROUP;
VIMNMX.U32 R31, R29, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R31 &rd=0x2 ?trans4;
LDG.E R27, desc[UR4][R26.64] &wr=0x3 ?trans4;
LDG.E R14, desc[UR4][R20.64+0x8] &wr=0x3 ?trans1;
IADD.64 R16, R6, R16 ?WAIT3_END_GROUP;
IADD3 R14, PT, PT, R14, R27, RZ &req={3} ?WAIT5_END_GROUP;
VIMNMX.U32 R33, R31, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R33 &rd=0x2 ?trans4;
LDG.E R14, desc[UR4][R20.64+0xc] &wr=0x3 ?trans4;
LDG.E R17, desc[UR4][R16.64] &wr=0x3 ?trans2;
IADD3 R14, PT, PT, R14, R17, RZ &req={3} ?WAIT5_END_GROUP;
VIMNMX.U32 R25, R33, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R25 &rd=0x2 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
BSSY.RECONVERGENT B0, 0x7e0 ?trans4;
@P1 BRA 0x7d0 ?trans5;
IADD3 R17, PT, PT, R15, 0x4, RZ ?trans1;
IMAD.WIDE R20, R23, 0x4, R12.reuse &req={3} ?trans1;
LDG.E R27, desc[UR4][R2.64] &wr=0x3 ?trans3;
IMAD.WIDE R16, R17, 0x4, R12 ?trans1;
LDG.E R23, desc[UR4][R20.64] &wr=0x4 ?trans4;
LDG.E R14, desc[UR4][R16.64] &wr=0x4 ?trans2;
IADD3 R14, PT, PT, R14, R23, RZ &req={4} ?trans1;
IMAD.WIDE R22, R10, 0x4, R20 ?WAIT4_END_GROUP;
VIMNMX.U32 R27, R14, R27, PT &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R27 &rd=0x4 ?trans4;
LDG.E R23, desc[UR4][R22.64] &wr=0x3 ?trans4;
LDG.E R14, desc[UR4][R16.64+0x4] &wr=0x3 ?trans1;
IADD.64 R24, R8, R20 &req={2} ?WAIT3_END_GROUP;
IADD3 R14, PT, PT, R14, R23, RZ &req={3} ?WAIT5_END_GROUP;
VIMNMX.U32 R29, R27, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R29 &rd=0x4 ?trans4;
LDG.E R25, desc[UR4][R24.64] &wr=0x2 ?trans4;
LDG.E R14, desc[UR4][R16.64+0x8] &wr=0x2 ?trans1;
IADD.64 R20, R6, R20 ?WAIT3_END_GROUP;
IADD3 R14, PT, PT, R14, R25, RZ &req={2} ?WAIT5_END_GROUP;
VIMNMX.U32 R31, R29, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R31 &rd=0x4 ?trans4;
LDG.E R14, desc[UR4][R16.64+0xc] &wr=0x2 ?trans4;
LDG.E R21, desc[UR4][R20.64] &wr=0x2 ?trans2;
IADD3 R14, PT, PT, R14, R21, RZ &req={2} ?WAIT5_END_GROUP;
VIMNMX.U32 R23, R31, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R23 &rd=0x4 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
BSSY.RECONVERGENT B0, 0x9c0 ?trans4;
@P1 BRA 0x9b0 ?trans5;
IADD3 R17, PT, PT, R15, 0x8, RZ ?trans1;
IMAD.WIDE R20, R19, 0x4, R12.reuse &req={3} ?trans1;
LDG.E R27, desc[UR4][R2.64] &req={4} &wr=0x3 ?trans3;
IMAD.WIDE R16, R17, 0x4, R12 ?trans1;
LDG.E R23, desc[UR4][R20.64] &wr=0x4 ?trans4;
LDG.E R14, desc[UR4][R16.64] &wr=0x4 ?trans2;
IADD3 R14, PT, PT, R14, R23, RZ &req={4} ?trans1;
IMAD.WIDE R22, R10, 0x4, R20 ?WAIT4_END_GROUP;
VIMNMX.U32 R27, R14, R27, PT &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R27 &rd=0x3 ?trans4;
LDG.E R23, desc[UR4][R22.64] &wr=0x4 ?trans4;
LDG.E R14, desc[UR4][R16.64+0x4] &wr=0x4 ?trans1;
IADD.64 R24, R8, R20 &req={2} ?WAIT3_END_GROUP;
IADD3 R14, PT, PT, R14, R23, RZ &req={4} ?WAIT5_END_GROUP;
VIMNMX.U32 R29, R27, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R29 &rd=0x3 ?trans4;
LDG.E R25, desc[UR4][R24.64] &wr=0x2 ?trans4;
LDG.E R14, desc[UR4][R16.64+0x8] &wr=0x2 ?trans1;
IADD.64 R20, R6, R20 ?WAIT3_END_GROUP;
IADD3 R14, PT, PT, R14, R25, RZ &req={2} ?WAIT5_END_GROUP;
VIMNMX.U32 R31, R29, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R31 &rd=0x3 ?trans4;
LDG.E R14, desc[UR4][R16.64+0xc] &wr=0x2 ?trans4;
LDG.E R21, desc[UR4][R20.64] &wr=0x2 ?trans2;
IADD3 R14, PT, PT, R14, R21, RZ &req={2} ?WAIT5_END_GROUP;
VIMNMX.U32 R23, R31, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R23 &rd=0x3 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
BSSY.RECONVERGENT B0, 0xbb0 ?trans1;
IMAD R21, R10, 0x4, R19 ?WAIT3_END_GROUP;
@P1 BRA 0xba0 ?trans5;
IADD3 R17, PT, PT, R15, 0xc, RZ ?trans1;
IMAD.WIDE R18, R21, 0x4, R12.reuse &req={3} ?trans1;
LDG.E R27, desc[UR4][R2.64] &req={4} &wr=0x3 ?trans3;
IMAD.WIDE R16, R17, 0x4, R12 ?trans1;
LDG.E R23, desc[UR4][R18.64] &wr=0x4 ?trans4;
LDG.E R14, desc[UR4][R16.64] &wr=0x4 ?trans2;
IADD3 R14, PT, PT, R14, R23, RZ &req={4} ?trans1;
IMAD.WIDE R22, R10, 0x4, R18 ?WAIT4_END_GROUP;
VIMNMX.U32 R27, R14, R27, PT &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R27 &rd=0x3 ?trans4;
LDG.E R23, desc[UR4][R22.64] &wr=0x4 ?trans4;
LDG.E R14, desc[UR4][R16.64+0x4] &wr=0x4 ?trans1;
IADD.64 R24, R8, R18 &req={2} ?WAIT3_END_GROUP;
IADD3 R14, PT, PT, R14, R23, RZ &req={4} ?WAIT5_END_GROUP;
VIMNMX.U32 R29, R27, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R29 &rd=0x3 ?trans4;
LDG.E R25, desc[UR4][R24.64] &wr=0x2 ?trans4;
LDG.E R14, desc[UR4][R16.64+0x8] &wr=0x2 ?trans1;
IADD.64 R18, R6, R18 ?WAIT3_END_GROUP;
IADD3 R14, PT, PT, R14, R25, RZ &req={2} ?WAIT5_END_GROUP;
VIMNMX.U32 R31, R29, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R31 &rd=0x3 ?trans4;
LDG.E R14, desc[UR4][R16.64+0xc] &wr=0x2 ?trans4;
LDG.E R19, desc[UR4][R18.64] &wr=0x2 ?trans2;
IADD3 R14, PT, PT, R14, R19, RZ &req={2} ?WAIT5_END_GROUP;
VIMNMX.U32 R23, R31, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R23 &rd=0x3 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
IADD3 R11, PT, PT, R11, 0x10, RZ ?trans1;
IMAD R17, R10, 0x4, R21 ?trans1;
IADD3 R15, PT, PT, R15, 0x10, RZ ?WAIT3_END_GROUP;
ISETP.GE.AND P2, PT, R11, -0xb, PT ?WAIT13_END_GROUP;
@!P2 BRA 0x410 ?trans5;
IADD3 R12, PT, PT, -R11, 0x1, RZ &req={3} ?WAIT5_END_GROUP;
ISETP.GT.AND P2, PT, R12, 0x4, PT ?WAIT13_END_GROUP;
@!P2 BRA 0x1060 ?trans5;
BSSY.RECONVERGENT B0, 0xe30 ?trans1;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x80 ?trans1;
IMAD R19, R10, 0x4, R17 ?trans2;
@P1 BRA 0xe20 ?trans10;
LDC.64 R20, c[0x0][0x380] &wr=0x3 ?trans1;
LDG.E R25, desc[UR4][R2.64] &req={2} &wr=0x2 ?trans1;
IMAD.WIDE R12, R15, 0x4, R20 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE R16, R17, 0x4, R20 ?trans1;
LDG.E R14, desc[UR4][R12.64] &wr=0x3 ?trans4;
LDG.E R21, desc[UR4][R16.64] &wr=0x3 ?trans2;
IADD3 R14, PT, PT, R14, R21, RZ &req={3} ?trans1;
IMAD.WIDE R20, R10, 0x4, R16 ?WAIT4_END_GROUP;
VIMNMX.U32 R25, R14, R25, PT &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R25 &rd=0x3 ?trans4;
LDG.E R21, desc[UR4][R20.64] &wr=0x2 ?trans4;
LDG.E R14, desc[UR4][R12.64+0x4] &wr=0x2 ?trans1;
IADD.64 R22, R8, R16 &req={4} ?WAIT3_END_GROUP;
IADD3 R14, PT, PT, R14, R21, RZ &req={2} ?WAIT5_END_GROUP;
VIMNMX.U32 R27, R25, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R27 &rd=0x3 ?trans4;
LDG.E R23, desc[UR4][R22.64] &wr=0x2 ?trans4;
LDG.E R14, desc[UR4][R12.64+0x8] &wr=0x2 ?trans1;
IADD.64 R16, R6, R16 ?WAIT3_END_GROUP;
IADD3 R14, PT, PT, R14, R23, RZ &req={2} ?WAIT5_END_GROUP;
VIMNMX.U32 R29, R27, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R29 &rd=0x3 ?trans4;
LDG.E R14, desc[UR4][R12.64+0xc] &wr=0x2 ?trans4;
LDG.E R17, desc[UR4][R16.64] &wr=0x2 ?trans2;
IADD3 R14, PT, PT, R14, R17, RZ &req={2} ?WAIT5_END_GROUP;
VIMNMX.U32 R21, R29, R14, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R21 &rd=0x3 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
BSSY.RECONVERGENT B0, 0x1040 ?trans1;
IADD3 R11, PT, PT, R11, 0x4, RZ ?trans1;
IMAD R17, R10, 0x4, R19 ?trans1;
IADD3 R16, PT, PT, R15, 0x4, RZ ?trans1;
@P1 BRA 0x1030 ?trans6;
LDC.64 R14, c[0x0][0x380] &wr=0x5 ?trans1;
LDG.E R23, desc[UR4][R2.64] &req={4} &wr=0x4 ?trans1;
IMAD.WIDE R12, R16, 0x4, R14 &req={5} ?WAIT4_END_GROUP;
IMAD.WIDE R14, R19, 0x4, R14 ?trans1;
LDG.E R18, desc[UR4][R12.64] &wr=0x5 ?trans4;
LDG.E R19, desc[UR4][R14.64] &wr=0x5 ?trans2;
IADD3 R18, PT, PT, R18, R19, RZ &req={5} ?WAIT5_END_GROUP;
VIMNMX.U32 R23, R18, R23, PT &req={4} ?trans1;
IMAD.WIDE R18, R10, 0x4, R14 ?WAIT4_END_GROUP;
STG.E desc[UR4][R2.64], R23 &rd=0x4 ?trans4;
LDG.E R19, desc[UR4][R18.64] &wr=0x5 ?trans4;
LDG.E R10, desc[UR4][R12.64+0x4] &wr=0x5 ?trans1;
IADD.64 R20, R8, R14 &req={3} ?WAIT3_END_GROUP;
IADD3 R10, PT, PT, R10, R19, RZ &req={5} ?WAIT5_END_GROUP;
VIMNMX.U32 R25, R23, R10, PT &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R25 &rd=0x4 ?trans4;
LDG.E R21, desc[UR4][R20.64] &wr=0x2 ?trans4;
LDG.E R10, desc[UR4][R12.64+0x8] &wr=0x2 ?trans1;
IADD.64 R14, R6, R14 ?WAIT3_END_GROUP;
IADD3 R10, PT, PT, R10, R21, RZ &req={2} ?WAIT5_END_GROUP;
VIMNMX.U32 R27, R25, R10, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R27 &rd=0x4 ?trans4;
LDG.E R10, desc[UR4][R12.64+0xc] &wr=0x2 ?trans4;
LDG.E R15, desc[UR4][R14.64] &wr=0x2 ?trans2;
IADD3 R10, PT, PT, R10, R15, RZ &req={2} ?WAIT5_END_GROUP;
VIMNMX.U32 R19, R27, R10, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R19 &rd=0x4 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
IADD3 R11, PT, PT, R11, 0x4, RZ ?trans2;
IADD3 R15, PT, PT, R16, 0x4, RZ ?WAIT7_END_GROUP;
ISETP.NE.OR P0, PT, R11, 0x1, P0 ?WAIT13_END_GROUP;
@!P0 EXIT ?trans5;
IADD3 R11, PT, PT, R11, 0x4, RZ ?trans1;
BSSY.RECONVERGENT B0, 0x1270 ?trans4;
ISETP.NE.AND P0, PT, R11, 0x1, PT ?trans1;
@P1 BRA 0x1260 ?WAIT12_END_GROUP;
IMAD.WIDE R12, R15, 0x4, R4.reuse &req={1} ?trans1;
LDG.E R10, desc[UR4][R2.64] &wr=0x5 ?trans3;
IMAD.WIDE R18, R17, 0x4, R4 &req={4} ?trans1;
LDG.E R14, desc[UR4][R12.64] &wr=0x4 ?trans4;
LDG.E R21, desc[UR4][R18.64] &req={3} &wr=0x4 ?trans2;
IADD3 R21, PT, PT, R14, R21, RZ &req={4} ?WAIT5_END_GROUP;
VIMNMX.U32 R25, R10, R21, PT &req={5,2} ?trans1;
IMAD.WIDE R20, R0, 0x4, R18 &req={0} ?WAIT4_END_GROUP;
STG.E desc[UR4][R2.64], R25 &rd=0x0 ?trans4;
LDG.E R21, desc[UR4][R20.64] &wr=0x2 ?trans4;
LDG.E R10, desc[UR4][R12.64+0x4] &wr=0x2 ?trans1;
IADD.64 R22, R8, R18 ?WAIT3_END_GROUP;
IADD3 R10, PT, PT, R10, R21, RZ &req={2} ?WAIT5_END_GROUP;
VIMNMX.U32 R27, R25, R10, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R27 &rd=0x0 ?trans4;
LDG.E R23, desc[UR4][R22.64] &wr=0x2 ?trans4;
LDG.E R10, desc[UR4][R12.64+0x8] &wr=0x2 ?trans1;
IADD.64 R18, R6, R18 ?WAIT3_END_GROUP;
IADD3 R10, PT, PT, R10, R23, RZ &req={2} ?WAIT5_END_GROUP;
VIMNMX.U32 R29, R27, R10, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R29 &rd=0x0 ?trans4;
LDG.E R10, desc[UR4][R12.64+0xc] &wr=0x2 ?trans4;
LDG.E R19, desc[UR4][R18.64] &wr=0x2 ?trans2;
IADD3 R10, PT, PT, R10, R19, RZ &req={2} ?WAIT5_END_GROUP;
VIMNMX.U32 R21, R29, R10, PT ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R21 &rd=0x0 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
IMAD R17, R0, 0x4, R17 &req={0} ?trans1;
IADD3 R15, PT, PT, R15, 0x4, RZ ?trans1;
@P0 BRA 0x1080 ?trans6;
EXIT ?trans5;
BRA 0x12b0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: gpu_primary(unsigned int*, int, int)
_Z11gpu_primaryPjii:
s_load_b128 s[4:7], s[0:1], 0x0
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v2, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, s7, v1
v_add_nc_u32_e32 v5, s7, v2
s_add_i32 s0, s6, 1
s_add_i32 s1, s7, 31
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v4, v3, s6
v_max_i32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e32 vcc_lo, s6, v3
v_add_nc_u32_e32 v0, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[5:6], 2, v[0:1]
v_mad_u64_u32 v[0:1], null, s7, s0, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v2, s0, s4, v5
v_add_co_ci_u32_e64 v3, s0, s5, v6, s0
.LBB0_1:
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_3
v_add_nc_u32_e32 v5, s7, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[0:1]
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v5, s0, s4, v5
v_add_co_ci_u32_e64 v6, s0, s5, v6, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v7, s0, s4, v7
v_add_co_ci_u32_e64 v8, s0, s5, v8, s0
s_clause 0x2
global_load_b32 v1, v[5:6], off
global_load_b32 v5, v[7:8], off
global_load_b32 v6, v[2:3], off
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v1, v5, v1
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_min_u32_e32 v1, v6, v1
global_store_b32 v[2:3], v1, off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(VALU_DEP_3)
v_add_nc_u32_e32 v0, s6, v0
s_add_i32 s0, s7, 1
s_cmp_ge_i32 s7, s1
s_mov_b32 s7, s0
s_cbranch_scc0 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| gpu_primary | 8,061 | 1,119 | stackv2-00000-of-00015 |
// Demangled: matMultKernel_ijk(float*, float*, float*)
Function : _Z17matMultKernel_ijkPfS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R9, SR_CTAID.X &wr=0x1 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans2;
LOP3.LUT P0, RZ, R9, 0x7ffffff0, R0, 0xc8, !PT &req={1} ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LDC.64 R2, c[0x0][0x390] &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans1;
SHF.L.U32 R9, R9, 0x4, RZ ?WAIT4_END_GROUP;
IADD3 R11, PT, PT, R9, R0, RZ ?trans2;
LDC.64 R4, c[0x0][0x380] &wr=0x3 ?trans8;
LDC.64 R6, c[0x0][0x388] &wr=0x4 ?trans1;
IMAD.WIDE.U32 R2, R11, 0x4, R2 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], RZ &req={2} ?trans1;
IMAD.WIDE.U32 R4, R9, 0x4, R4 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R6, R0, 0x4, R6 &req={4} ?trans2;
LDG.E R0, desc[UR4][R4.64] &wr=0x2 ?trans4;
LDG.E R9, desc[UR4][R6.64] &wr=0x2 ?trans2;
FFMA R9, R0, R9, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R9 &rd=0x1 ?trans4;
LDG.E R0, desc[UR4][R4.64+0x4] &wr=0x2 ?trans4;
LDG.E R8, desc[UR4][R6.64+0x40] &wr=0x2 ?trans2;
FFMA R11, R0, R8, R9 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R11 &rd=0x2 ?trans4;
LDG.E R0, desc[UR4][R4.64+0x8] &wr=0x3 ?trans4;
LDG.E R8, desc[UR4][R6.64+0x80] &wr=0x3 ?trans2;
FFMA R13, R0, R8, R11 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R13 &rd=0x3 ?trans4;
LDG.E R0, desc[UR4][R4.64+0xc] &wr=0x1 ?trans4;
LDG.E R8, desc[UR4][R6.64+0xc0] &wr=0x1 ?trans2;
FFMA R9, R0, R8, R13 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R9 &rd=0x1 ?trans4;
LDG.E R0, desc[UR4][R4.64+0x10] &wr=0x2 ?trans4;
LDG.E R8, desc[UR4][R6.64+0x100] &wr=0x2 ?trans2;
FFMA R11, R0, R8, R9 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R11 &rd=0x2 ?trans4;
LDG.E R0, desc[UR4][R4.64+0x14] &wr=0x3 ?trans4;
LDG.E R8, desc[UR4][R6.64+0x140] &wr=0x3 ?trans2;
FFMA R13, R0, R8, R11 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R13 &rd=0x3 ?trans4;
LDG.E R0, desc[UR4][R4.64+0x18] &wr=0x1 ?trans4;
LDG.E R8, desc[UR4][R6.64+0x180] &wr=0x1 ?trans2;
FFMA R9, R0, R8, R13 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R9 &rd=0x1 ?trans4;
LDG.E R0, desc[UR4][R4.64+0x1c] &wr=0x2 ?trans4;
LDG.E R8, desc[UR4][R6.64+0x1c0] &wr=0x2 ?trans2;
FFMA R11, R0, R8, R9 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R11 &rd=0x2 ?trans4;
LDG.E R0, desc[UR4][R4.64+0x20] &wr=0x3 ?trans4;
LDG.E R8, desc[UR4][R6.64+0x200] &wr=0x3 ?trans2;
FFMA R13, R0, R8, R11 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R13 &rd=0x3 ?trans4;
LDG.E R0, desc[UR4][R4.64+0x24] &wr=0x1 ?trans4;
LDG.E R8, desc[UR4][R6.64+0x240] &wr=0x1 ?trans2;
FFMA R9, R0, R8, R13 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R9 &rd=0x1 ?trans4;
LDG.E R0, desc[UR4][R4.64+0x28] &wr=0x2 ?trans4;
LDG.E R8, desc[UR4][R6.64+0x280] &wr=0x2 ?trans2;
FFMA R11, R0, R8, R9 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R11 &rd=0x2 ?trans4;
LDG.E R0, desc[UR4][R4.64+0x2c] &wr=0x3 ?trans4;
LDG.E R8, desc[UR4][R6.64+0x2c0] &wr=0x3 ?trans2;
FFMA R13, R0, R8, R11 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R13 &rd=0x3 ?trans4;
LDG.E R0, desc[UR4][R4.64+0x30] &wr=0x1 ?trans4;
LDG.E R8, desc[UR4][R6.64+0x300] &wr=0x1 ?trans2;
FFMA R9, R0, R8, R13 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R9 &rd=0x1 ?trans4;
LDG.E R0, desc[UR4][R4.64+0x34] &wr=0x2 ?trans4;
LDG.E R8, desc[UR4][R6.64+0x340] &wr=0x2 ?trans2;
FFMA R11, R0, R8, R9 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R11 ?trans4;
LDG.E R0, desc[UR4][R4.64+0x38] &wr=0x3 ?trans4;
LDG.E R8, desc[UR4][R6.64+0x380] &wr=0x3 ?trans2;
FFMA R13, R0, R8, R11 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R13 ?trans4;
LDG.E R0, desc[UR4][R4.64+0x3c] &wr=0x1 ?trans4;
LDG.E R8, desc[UR4][R6.64+0x3c0] &wr=0x1 ?trans2;
FFMA R9, R0, R8, R13 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x500;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: matMultKernel_ijk(float*, float*, float*)
_Z17matMultKernel_ijkPfS_S_:
v_cmp_gt_u32_e32 vcc_lo, 16, v0
s_cmp_lt_i32 s15, 16
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_3
s_load_b64 s[4:5], s[0:1], 0x10
s_lshl_b32 s6, s15, 4
s_load_b128 s[0:3], s[0:1], 0x0
v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v1, s6, v0
v_lshlrev_b32_e32 v3, 2, v0
s_ashr_i32 s7, s6, 31
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v2, s2, s2, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, null, s3, 0, s2
s_lshl_b64 s[2:3], s[6:7], 2
global_store_b32 v[0:1], v4, off
s_add_u32 s2, s0, s2
s_addc_u32 s3, s1, s3
s_mov_b64 s[0:1], 0
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s4, s2, s0
s_addc_u32 s5, s3, s1
global_load_b32 v6, v[2:3], off
global_load_b32 v7, v4, s[4:5]
v_add_co_u32 v2, vcc_lo, v2, 64
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s0, 64
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v5, v7, v6
global_store_b32 v[0:1], v5, off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| matMultKernel_ijk | 2,321 | 838 | stackv2-00000-of-00015 |
// Demangled: matMultKernel_ikj(float*, float*, float*)
Function : _Z17matMultKernel_ikjPfS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R9, SR_CTAID.X &wr=0x1 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans2;
LOP3.LUT P0, RZ, R9, 0x7ffffff0, R0, 0xc8, !PT &req={1} ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LDC.64 R2, c[0x0][0x388] &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans1;
SHF.L.U32 R9, R9, 0x4, RZ ?trans2;
SHF.L.U32 R13, R0, 0x4, RZ ?trans2;
IADD3 R11, PT, PT, R9, R0, RZ ?trans2;
LDC.64 R4, c[0x0][0x390] &wr=0x3 ?trans8;
LDC.64 R6, c[0x0][0x380] &wr=0x4 ?trans1;
IMAD.WIDE.U32 R2, R13, 0x4, R2 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R9, 0x4, R4 &req={3} ?trans2;
LDG.E R9, desc[UR4][R2.64] &req={2} &wr=0x2 ?trans4;
LDG.E R13, desc[UR4][R4.64+0x4] &wr=0x3 ?trans1;
IMAD.WIDE.U32 R6, R11, 0x4, R6 &req={4} ?WAIT3_END_GROUP;
LDG.E R11, desc[UR4][R4.64] &wr=0x2 ?trans4;
LDG.E R0, desc[UR4][R6.64] &wr=0x2 ?trans4;
LDG.E R15, desc[UR4][R4.64+0x8] &wr=0x4 ?trans1;
FFMA R9, R0, R9, R11 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64], R9 &rd=0x1 ?trans4;
LDG.E R0, desc[UR4][R6.64] &wr=0x3 ?trans4;
LDG.E R11, desc[UR4][R2.64+0x4] &wr=0x3 ?trans2;
FFMA R11, R0, R11, R13 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64+0x4], R11 &rd=0x2 ?trans4;
LDG.E R0, desc[UR4][R6.64] &wr=0x4 ?trans4;
LDG.E R13, desc[UR4][R2.64+0x8] &wr=0x4 ?trans2;
FFMA R13, R0, R13, R15 &req={4} ?WAIT2_END_GROUP;
LDG.E R15, desc[UR4][R4.64+0xc] &wr=0x3 ?trans4;
STG.E desc[UR4][R4.64+0x8], R13 &rd=0x4 ?trans4;
LDG.E R0, desc[UR4][R6.64] &wr=0x3 ?trans4;
LDG.E R9, desc[UR4][R2.64+0xc] &req={1} &wr=0x3 ?trans2;
FFMA R9, R0, R9, R15 &req={3} ?WAIT2_END_GROUP;
LDG.E R15, desc[UR4][R4.64+0x10] &wr=0x3 ?trans4;
STG.E desc[UR4][R4.64+0xc], R9 &rd=0x1 ?trans4;
LDG.E R0, desc[UR4][R6.64] &wr=0x3 ?trans4;
LDG.E R11, desc[UR4][R2.64+0x10] &req={2} &wr=0x3 ?trans2;
FFMA R11, R0, R11, R15 &req={3} ?WAIT2_END_GROUP;
LDG.E R15, desc[UR4][R4.64+0x14] &wr=0x2 ?trans4;
STG.E desc[UR4][R4.64+0x10], R11 &rd=0x3 ?trans4;
LDG.E R0, desc[UR4][R6.64] &wr=0x2 ?trans4;
LDG.E R13, desc[UR4][R2.64+0x14] &req={4} &wr=0x2 ?trans2;
FFMA R13, R0, R13, R15 &req={2} ?WAIT2_END_GROUP;
LDG.E R15, desc[UR4][R4.64+0x18] &wr=0x2 ?trans4;
STG.E desc[UR4][R4.64+0x14], R13 &rd=0x4 ?trans4;
LDG.E R0, desc[UR4][R6.64] &wr=0x2 ?trans4;
LDG.E R9, desc[UR4][R2.64+0x18] &req={1} &wr=0x2 ?trans2;
FFMA R9, R0, R9, R15 &req={2} ?WAIT2_END_GROUP;
LDG.E R15, desc[UR4][R4.64+0x1c] &wr=0x2 ?trans4;
STG.E desc[UR4][R4.64+0x18], R9 &rd=0x1 ?trans4;
LDG.E R0, desc[UR4][R6.64] &wr=0x2 ?trans4;
LDG.E R11, desc[UR4][R2.64+0x1c] &req={3} &wr=0x2 ?trans2;
FFMA R11, R0, R11, R15 &req={2} ?WAIT2_END_GROUP;
LDG.E R15, desc[UR4][R4.64+0x20] &wr=0x2 ?trans4;
STG.E desc[UR4][R4.64+0x1c], R11 &rd=0x3 ?trans4;
LDG.E R0, desc[UR4][R6.64] &wr=0x2 ?trans4;
LDG.E R13, desc[UR4][R2.64+0x20] &req={4} &wr=0x2 ?trans2;
FFMA R13, R0, R13, R15 &req={2} ?WAIT2_END_GROUP;
LDG.E R15, desc[UR4][R4.64+0x24] &wr=0x2 ?trans4;
STG.E desc[UR4][R4.64+0x20], R13 &rd=0x4 ?trans4;
LDG.E R0, desc[UR4][R6.64] &wr=0x2 ?trans4;
LDG.E R9, desc[UR4][R2.64+0x24] &req={1} &wr=0x2 ?trans2;
FFMA R9, R0, R9, R15 &req={2} ?WAIT2_END_GROUP;
LDG.E R15, desc[UR4][R4.64+0x28] &wr=0x2 ?trans4;
STG.E desc[UR4][R4.64+0x24], R9 &rd=0x1 ?trans4;
LDG.E R0, desc[UR4][R6.64] &wr=0x2 ?trans4;
LDG.E R11, desc[UR4][R2.64+0x28] &req={3} &wr=0x2 ?trans2;
FFMA R11, R0, R11, R15 &req={2} ?WAIT2_END_GROUP;
LDG.E R15, desc[UR4][R4.64+0x2c] &wr=0x2 ?trans4;
STG.E desc[UR4][R4.64+0x28], R11 &rd=0x3 ?trans4;
LDG.E R0, desc[UR4][R6.64] &wr=0x2 ?trans4;
LDG.E R13, desc[UR4][R2.64+0x2c] &req={4} &wr=0x2 ?trans2;
FFMA R13, R0, R13, R15 &req={2} ?WAIT2_END_GROUP;
LDG.E R15, desc[UR4][R4.64+0x30] &wr=0x2 ?trans4;
STG.E desc[UR4][R4.64+0x2c], R13 &rd=0x4 ?trans4;
LDG.E R0, desc[UR4][R6.64] &wr=0x2 ?trans4;
LDG.E R9, desc[UR4][R2.64+0x30] &req={1} &wr=0x2 ?trans2;
FFMA R9, R0, R9, R15 &req={2} ?WAIT2_END_GROUP;
LDG.E R15, desc[UR4][R4.64+0x34] &wr=0x2 ?trans4;
STG.E desc[UR4][R4.64+0x30], R9 &rd=0x1 ?trans4;
LDG.E R0, desc[UR4][R6.64] &wr=0x2 ?trans4;
LDG.E R11, desc[UR4][R2.64+0x34] &req={3} &wr=0x2 ?trans2;
FFMA R11, R0, R11, R15 &req={2} ?WAIT2_END_GROUP;
LDG.E R15, desc[UR4][R4.64+0x38] &wr=0x2 ?trans4;
STG.E desc[UR4][R4.64+0x34], R11 ?trans4;
LDG.E R0, desc[UR4][R6.64] &wr=0x2 ?trans4;
LDG.E R13, desc[UR4][R2.64+0x38] &req={4} &wr=0x2 ?trans2;
FFMA R13, R0, R13, R15 &req={2} ?WAIT2_END_GROUP;
LDG.E R15, desc[UR4][R4.64+0x3c] &wr=0x2 ?trans4;
STG.E desc[UR4][R4.64+0x38], R13 ?trans4;
LDG.E R0, desc[UR4][R6.64] &wr=0x2 ?trans4;
LDG.E R9, desc[UR4][R2.64+0x3c] &req={1} &wr=0x2 ?trans2;
FFMA R9, R0, R9, R15 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64+0x3c], R9 ?trans1;
EXIT ?trans5;
BRA 0x600;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: matMultKernel_ikj(float*, float*, float*)
_Z17matMultKernel_ikjPfS_S_:
v_cmp_gt_u32_e32 vcc_lo, 16, v0
s_cmp_lt_i32 s15, 16
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_3
s_load_b128 s[4:7], s[0:1], 0x0
s_lshl_b32 s2, s15, 4
s_load_b64 s[0:1], s[0:1], 0x10
v_add_nc_u32_e32 v1, s2, v0
v_lshlrev_b32_e32 v5, 6, v0
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_lshl_b64 s[2:3], s[2:3], 2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v3
v_add_co_u32 v3, s4, s6, v5
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v4, vcc_lo
v_add_co_ci_u32_e64 v4, null, s7, 0, s4
s_add_u32 s2, s0, s2
s_addc_u32 s3, s1, s3
s_mov_b64 s[0:1], 0
.LBB1_2:
s_delay_alu instid0(SALU_CYCLE_1)
v_add_co_u32 v5, vcc_lo, v3, s0
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v4, vcc_lo
s_add_u32 s4, s2, s0
s_addc_u32 s5, s3, s1
global_load_b32 v7, v[0:1], off
global_load_b32 v8, v2, s[4:5]
global_load_b32 v5, v[5:6], off
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s0, 64
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v8, v7, v5
global_store_b32 v2, v8, s[4:5]
s_cbranch_scc1 .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| matMultKernel_ikj | 2,920 | 830 | stackv2-00000-of-00015 |
// Demangled: vectorAdd(int const*, int const*, int*, int)
Function : _Z9vectorAddPKiS0_Pii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x398] &wr=0x2 ?trans7;
LDC R9, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R9, R9, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R9, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD.WIDE R2, R9, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E.CONSTANT R2, desc[UR4][R2.64] &req={1} &wr=0x4 ?trans1;
IMAD.WIDE R4, R9, 0x4, R4 &req={2} ?WAIT6_END_GROUP;
LDG.E.CONSTANT R5, desc[UR4][R4.64] &wr=0x4 ?trans1;
IMAD.WIDE R6, R9, 0x4, R6 &req={3} ?trans1;
IADD3 R9, PT, PT, R2, R5, RZ &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x140;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: vectorAdd(int const*, int const*, int*, int)
_Z9vectorAddPKiS0_Pii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| vectorAdd | 580 | 578 | stackv2-00000-of-00015 |
// Demangled: add_kernel(double*, int)
Function : _Z10add_kernelPdi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x388] &wr=0x2 ?trans7;
LDC R5, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R5, R5, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R5, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD.WIDE R2, R5, 0x8, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E.64 R4, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans2;
DADD R4, R4, 1 &req={2} &wr=0x0 ?trans2;
STG.E.64 desc[UR4][R2.64], R4 &req={0} ?trans1;
EXIT ?trans5;
BRA 0xf0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: add_kernel(double*, int)
_Z10add_kernelPdi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], 1.0
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| add_kernel | 429 | 452 | stackv2-00000-of-00015 |
// Demangled: teste()
Function : _Z5testev
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x4][0x8] &wr=0x1 ?trans1;
MOV R16, 0x0 ?trans1;
CS2R R6, SRZ ?WAIT5_END_GROUP;
LDC.64 R2, c[0x4][R16] &rd=0x2 &wr=0x3 ?trans1;
MOV R4, UR4 &req={1} ?trans1;
MOV R5, UR5 &req={2} ?WAIT7_END_GROUP;
LEPC R20, 0x90 ?WAIT7_END_GROUP;
CALL.ABS.NOINC R2 &req={3,0} ?trans5;
LDCU.64 UR4, c[0x4][0x10] &wr=0x0 ?trans1;
LDC.64 R2, c[0x4][R16] &rd=0x1 &wr=0x2 ?trans1;
CS2R R6, SRZ ?trans1;
MOV R4, UR4 &req={0} ?trans1;
MOV R5, UR5 &req={1} ?WAIT7_END_GROUP;
LEPC R20, 0x100 ?WAIT7_END_GROUP;
CALL.ABS.NOINC R2 &req={2} ?trans5;
EXIT ?trans5;
BRA 0x110;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: teste()
_Z5testev:
s_load_b64 s[18:19], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v36, -1, 0
v_mov_b32_e32 v6, 0
s_mov_b64 s[16:17], s[0:1]
s_mov_b32 s32, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v36
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB1_6
v_mov_b32_e32 v0, 0
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[18:19] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[18:19] offset:40
global_load_b64 v[5:6], v0, s[18:19]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[18:19] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB1_5
s_mov_b32 s3, 0
.LBB1_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[18:19] offset:40
global_load_b64 v[10:11], v0, s[18:19]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[18:19] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s3, vcc_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB1_3
s_or_b32 exec_lo, exec_lo, s3
.LBB1_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
.LBB1_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s2, v6
v_readfirstlane_b32 s3, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[18:19] offset:40
global_load_b128 v[0:3], v5, s[18:19]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s4, v8
v_readfirstlane_b32 s5, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[4:5], s[2:3], s[4:5]
s_mul_i32 s1, s5, 24
s_mul_hi_u32 s6, s4, 24
s_mul_i32 s7, s4, 24
s_and_saveexec_b32 s9, s0
s_cbranch_execz .LBB1_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, v5
s_add_i32 s8, s6, s1
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s7
v_add_co_ci_u32_e32 v11, vcc_lo, s8, v1, vcc_lo
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB1_8:
s_or_b32 exec_lo, exec_lo, s9
s_lshl_b64 s[4:5], s[4:5], 12
v_lshlrev_b64 v[6:7], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, v2, v6
s_mov_b32 s11, s8
s_mov_b32 s9, s8
s_mov_b32 s10, s8
v_add_co_ci_u32_e32 v9, vcc_lo, v3, v7, vcc_lo
v_dual_mov_b32 v4, 33 :: v_dual_mov_b32 v7, v5
v_dual_mov_b32 v6, v5 :: v_dual_mov_b32 v13, s11
v_dual_mov_b32 v12, s10 :: v_dual_mov_b32 v11, s9
v_mov_b32_e32 v10, s8
s_clause 0x3
global_store_b128 v[8:9], v[4:7], off
global_store_b128 v[8:9], v[10:13], off offset:16
global_store_b128 v[8:9], v[10:13], off offset:32
global_store_b128 v[8:9], v[10:13], off offset:48
s_and_saveexec_b32 s4, s0
s_cbranch_execz .LBB1_15
v_mov_b32_e32 v10, 0
s_mov_b32 s5, exec_lo
s_clause 0x1
global_load_b64 v[13:14], v10, s[18:19] offset:32 glc
global_load_b64 v[2:3], v10, s[18:19] offset:40
v_dual_mov_b32 v11, s2 :: v_dual_mov_b32 v12, s3
s_waitcnt vmcnt(0)
v_and_b32_e32 v3, s3, v3
v_and_b32_e32 v2, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, v3, 24
v_mul_hi_u32 v4, v2, 24
v_mul_lo_u32 v2, v2, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, v4, v3
v_add_co_u32 v6, vcc_lo, v0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, v1, v3, vcc_lo
global_store_b64 v[6:7], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[18:19] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB1_11
.LBB1_10:
v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[18:19] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s8, vcc_lo, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB1_10
.LBB1_11:
s_or_b32 exec_lo, exec_lo, s5
v_mov_b32_e32 v5, 0
s_mov_b32 s8, exec_lo
s_mov_b32 s5, exec_lo
v_mbcnt_lo_u32_b32 v4, s8, 0
global_load_b64 v[2:3], v5, s[18:19] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB1_13
s_bcnt1_i32_b32 s8, s8
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v4, s8
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB1_13:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB1_15
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s5, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s5, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_15:
s_or_b32 exec_lo, exec_lo, s4
s_add_i32 s6, s6, s1
v_add_co_u32 v0, vcc_lo, v0, s7
v_add_co_ci_u32_e32 v1, vcc_lo, s6, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_16:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB1_18
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
.LBB1_18:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB1_20
s_mov_b32 s1, 0
s_sleep 1
s_branch .LBB1_21
.LBB1_20:
s_mov_b32 s1, -1
.LBB1_21:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB1_16
global_load_b64 v[0:1], v[8:9], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB1_26
v_mov_b32_e32 v8, 0
s_clause 0x2
global_load_b64 v[4:5], v8, s[18:19] offset:40
global_load_b64 v[9:10], v8, s[18:19] offset:24 glc
global_load_b64 v[6:7], v8, s[18:19]
s_waitcnt vmcnt(2)
v_add_co_u32 v11, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v11, s2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v4, v2, v4
v_mul_lo_u32 v5, v5, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v11, v4, 24
v_mul_lo_u32 v4, v4, 24
v_add_nc_u32_e32 v5, v11, v5
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v9
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v10
global_store_b64 v[6:7], v[9:10], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[18:19] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_26
s_mov_b32 s0, 0
.LBB1_25:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[18:19] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5]
v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB1_25
.LBB1_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, .str@rel32@lo+4
s_addc_u32 s1, s1, .str@rel32@hi+12
v_mov_b32_e32 v5, 0
s_cmp_lg_u64 s[0:1], 0
s_mov_b64 s[8:9], s[16:17]
s_cselect_b32 s2, -1, 0
v_mov_b32_e32 v3, s1
v_cndmask_b32_e64 v2, 0, 1, s2
v_mov_b32_e32 v37, 0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, __ockl_printf_append_string_n@rel32@lo+4
s_addc_u32 s3, s3, __ockl_printf_append_string_n@rel32@hi+12
v_lshlrev_b32_e32 v4, 4, v2
v_mov_b32_e32 v2, s0
s_swappc_b64 s[30:31], s[2:3]
v_readfirstlane_b32 s0, v36
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v36
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB1_32
global_load_b64 v[2:3], v37, s[18:19] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[0:1], v37, s[18:19] offset:40
global_load_b64 v[4:5], v37, s[18:19]
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v3
v_and_b32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v1, v1, 24
v_mul_hi_u32 v6, v0, 24
v_mul_lo_u32 v0, v0, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v1, v6, v1
s_waitcnt vmcnt(0)
v_add_co_u32 v0, vcc_lo, v4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
global_load_b64 v[0:1], v[0:1], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v37, v[0:3], s[18:19] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[2:3]
s_cbranch_execz .LBB1_31
v_mov_b32_e32 v0, 0
s_mov_b32 s3, 0
.LBB1_29:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[18:19] offset:40
global_load_b64 v[8:9], v0, s[18:19]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[18:19] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s3, vcc_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB1_29
s_or_b32 exec_lo, exec_lo, s3
.LBB1_31:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
.LBB1_32:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[6:7], v37, s[18:19] offset:40
global_load_b128 v[0:3], v37, s[18:19]
v_readfirstlane_b32 s2, v4
v_readfirstlane_b32 s3, v5
s_mov_b32 s8, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[4:5], s[2:3], s[4:5]
s_mul_i32 s1, s5, 24
s_mul_hi_u32 s6, s4, 24
s_mul_i32 s7, s4, 24
s_and_saveexec_b32 s9, s0
s_cbranch_execz .LBB1_34
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_add_i32 s8, s6, s1
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s7
v_add_co_ci_u32_e32 v9, vcc_lo, s8, v1, vcc_lo
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB1_34:
s_or_b32 exec_lo, exec_lo, s9
v_mov_b32_e32 v37, 0
s_lshl_b64 s[4:5], s[4:5], 12
s_mov_b32 s8, 0
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s4
v_lshlrev_b64 v[4:5], 6, v[36:37]
v_mov_b32_e32 v36, 33
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v3, v5, vcc_lo
v_mov_b32_e32 v38, v37
v_dual_mov_b32 v39, v37 :: v_dual_mov_b32 v2, s8
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
v_mov_b32_e32 v5, s11
s_clause 0x3
global_store_b128 v[6:7], v[36:39], off
global_store_b128 v[6:7], v[2:5], off offset:16
global_store_b128 v[6:7], v[2:5], off offset:32
global_store_b128 v[6:7], v[2:5], off offset:48
s_and_saveexec_b32 s4, s0
s_cbranch_execz .LBB1_42
s_clause 0x1
global_load_b64 v[12:13], v37, s[18:19] offset:32 glc
global_load_b64 v[2:3], v37, s[18:19] offset:40
v_dual_mov_b32 v10, s2 :: v_dual_mov_b32 v11, s3
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[2:3]
s_mul_i32 s5, s9, 24
s_mul_hi_u32 s9, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s9, s9, s5
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
s_mov_b32 s5, exec_lo
global_store_b64 v[8:9], v[12:13], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v37, v[10:13], s[18:19] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[12:13]
s_cbranch_execz .LBB1_38
v_mov_b32_e32 v10, 0
s_mov_b32 s8, 0
.LBB1_37:
v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[18:19] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s8, vcc_lo, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB1_37
.LBB1_38:
s_or_b32 exec_lo, exec_lo, s5
v_mov_b32_e32 v5, 0
s_mov_b32 s8, exec_lo
s_mov_b32 s5, exec_lo
v_mbcnt_lo_u32_b32 v4, s8, 0
global_load_b64 v[2:3], v5, s[18:19] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB1_40
s_bcnt1_i32_b32 s8, s8
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v4, s8
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB1_40:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB1_42
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s5, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s5, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_42:
s_or_b32 exec_lo, exec_lo, s4
s_add_i32 s6, s6, s1
v_add_co_u32 v0, vcc_lo, v0, s7
v_add_co_ci_u32_e32 v1, vcc_lo, s6, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_43:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB1_45
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
.LBB1_45:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB1_47
s_mov_b32 s1, 0
s_sleep 1
s_branch .LBB1_48
.LBB1_47:
s_mov_b32 s1, -1
.LBB1_48:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB1_43
global_load_b64 v[0:1], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB1_53
v_mov_b32_e32 v8, 0
s_clause 0x2
global_load_b64 v[4:5], v8, s[18:19] offset:40
global_load_b64 v[9:10], v8, s[18:19] offset:24 glc
global_load_b64 v[6:7], v8, s[18:19]
s_waitcnt vmcnt(2)
v_add_co_u32 v11, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v11, s2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v4, v2, v4
v_mul_lo_u32 v5, v5, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v11, v4, 24
v_mul_lo_u32 v4, v4, 24
v_add_nc_u32_e32 v5, v11, v5
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v9
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v10
global_store_b64 v[6:7], v[9:10], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[18:19] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_53
s_mov_b32 s0, 0
.LBB1_52:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[18:19] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5]
v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB1_52
.LBB1_53:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, .str.1@rel32@lo+4
s_addc_u32 s1, s1, .str.1@rel32@hi+12
s_mov_b64 s[8:9], s[16:17]
s_cmp_lg_u64 s[0:1], 0
v_mov_b32_e32 v3, s1
s_cselect_b32 s2, -1, 0
v_mov_b32_e32 v5, 0
v_cndmask_b32_e64 v2, 0, 1, s2
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, __ockl_printf_append_string_n@rel32@lo+4
s_addc_u32 s3, s3, __ockl_printf_append_string_n@rel32@hi+12
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v4, 1, v2
v_mov_b32_e32 v2, s0
s_swappc_b64 s[30:31], s[2:3]
s_endpgm
| teste | 399 | 9,998 | stackv2-00000-of-00015 |
// Demangled: addCincoVec(int*, int)
Function : _Z11addCincoVecPii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R5, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x388] &wr=0x2 ?trans7;
LDC R0, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R5, R0, UR4, R5 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R5, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD.WIDE R2, R5, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans2;
IADD3 R5, PT, PT, R0, 0x5, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R5 ?trans1;
EXIT ?trans5;
BRA 0xf0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: addCincoVec(int*, int)
_Z11addCincoVecPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, 5, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| addCincoVec | 427 | 445 | stackv2-00000-of-00015 |
// Demangled: vecAddKernel(int*, int*, int*, int)
Function : _Z12vecAddKernelPiS_S_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R9, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x398] &wr=0x2 ?trans1;
IMAD R9, R9, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R9, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD.WIDE R2, R9, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x4 ?trans1;
IMAD.WIDE R4, R9, 0x4, R4 &req={2} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR4][R4.64] &wr=0x4 ?trans1;
IMAD.WIDE R6, R9, 0x4, R6 &req={3} ?trans1;
IADD3 R9, PT, PT, R2, R5, RZ &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x140;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: vecAddKernel(int*, int*, int*, int)
_Z12vecAddKernelPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| vecAddKernel | 575 | 578 | stackv2-00000-of-00015 |
// Demangled: vecAdd(int*, int*, int*)
Function : _Z6vecAddPiS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R9, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R9.reuse, 0x4, R4 &req={2} ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans4;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R6, R9, 0x4, R6 &req={3} ?trans1;
IADD3 R9, PT, PT, R2, R5, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0xe0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: vecAdd(int*, int*, int*)
_Z6vecAddPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| vecAdd | 425 | 192 | stackv2-00000-of-00015 |
// Demangled: matrixAddKernel(double*, double*, int)
Function : _Z15matrixAddKernelPdS_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x390] &wr=0x2 ?trans7;
LDC R7, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R7, R7, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R7, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x388] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x380] &wr=0x2 ?trans1;
IMAD.WIDE R2, R7, 0x8, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E.64 R2, desc[UR4][R2.64] &req={1} &wr=0x3 ?trans1;
IMAD.WIDE R4, R7, 0x8, R4 &req={2} ?WAIT5_END_GROUP;
LDG.E.64 R6, desc[UR4][R4.64] &wr=0x3 ?trans2;
DADD R6, R2, R6 &req={3} &wr=0x0 ?trans2;
STG.E.64 desc[UR4][R4.64], R6 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x120;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: matrixAddKernel(double*, double*, int)
_Z15matrixAddKernelPdS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| matrixAddKernel | 532 | 523 | stackv2-00000-of-00015 |
// Demangled: GPUAdd(int*, int*, int*, int)
Function : _Z6GPUAddPiS_S_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R9, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R9.reuse, 0x4, R4 &req={2} ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans4;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R6, R9, 0x4, R6 &req={3} ?trans1;
IADD3 R9, PT, PT, R2, R5, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0xe0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: GPUAdd(int*, int*, int*, int)
_Z6GPUAddPiS_S_i:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| GPUAdd | 426 | 193 | stackv2-00000-of-00015 |
// Demangled: faster_game_of_life_iter(char*, char*, unsigned long, unsigned long, int)
Function : _Z24faster_game_of_life_iterPcS_mmi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans1;
LDCU UR8, c[0x0][0x3a0] &wr=0x2 ?trans1;
S2R R7, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x3 ?trans1;
S2R R5, SR_TID.Y &wr=0x4 ?trans1;
S2R R2, SR_CTAID.Y &wr=0x4 ?trans1;
IMAD R7, R7, 0x10, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R7, UR8, PT &req={2} ?trans1;
IMAD R2, R2, 0x10, R5 &req={4} ?WAIT4_END_GROUP;
ISETP.GT.AND P0, PT, R7, -0x1, !P0 ?WAIT5_END_GROUP;
ISETP.GE.OR P1, PT, R2, UR8, !P0 ?WAIT13_END_GROUP;
@!P1 LDC.64 R12, c[0x0][0x390] &wr=0x1 ?trans1;
@!P1 MOV R3, RZ ?WAIT7_END_GROUP;
@!P1 LDC.64 R10, c[0x0][0x380] &wr=0x2 ?trans1;
@!P1 IMAD.WIDE.U32 R8, R7, R12, R2 &req={1} ?WAIT4_END_GROUP;
@!P1 IMAD R9, R7, R13, R9 ?WAIT5_END_GROUP;
@!P1 IADD.64 R8, R8, R10 &req={2} ?WAIT3_END_GROUP;
PRMT R11, RZ, 0x7610, R11 ?WAIT6_END_GROUP;
@!P1 LDG.E.U8 R11, desc[UR6][R8.64] &req={3} &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.NE.AND P1, PT, R0, 0xf, PT ?trans1;
BSSY.RECONVERGENT B0, 0x440 ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
MOV R13, UR4 ?WAIT5_END_GROUP;
IMAD R6, R0, 0x12, R13 ?WAIT5_END_GROUP;
IADD3 R4, PT, PT, R6, R5, RZ ?WAIT5_END_GROUP;
STS.U8 [R4+0x13], R11 &req={2} &rd=0x1 ?trans1;
@!P1 BRA 0x320 &req={0} ?trans5;
ISETP.NE.AND P1, PT, R0, RZ, PT ?WAIT13_END_GROUP;
@P1 BRA 0x430 ?trans5;
ISETP.GT.AND P1, PT, R7, UR8, PT ?trans1;
BSSY.RECONVERGENT B1, 0x300 ?trans1;
PRMT R8, RZ, 0x7610, R8 ?WAIT3_END_GROUP;
ISETP.LT.OR P1, PT, R7, 0x1, P1 ?WAIT5_END_GROUP;
ISETP.GE.OR P1, PT, R2, UR8, P1 ?WAIT13_END_GROUP;
@P1 BRA 0x2f0 ?trans5;
LDCU.64 UR10, c[0x0][0x390] &wr=0x0 ?trans1;
IADD3 R11, PT, PT, R7, -0x1, RZ &req={1} ?trans1;
MOV R8, R2 ?trans1;
HFMA2 R9, -RZ, RZ, 0, 0 ?trans1;
LDCU.64 UR12, c[0x0][0x380] &wr=0x1 ?trans3;
IMAD.WIDE.U32 R8, R11, UR10, R8 &req={0} ?WAIT4_END_GROUP;
IMAD R9, R11, UR11, R9 ?WAIT5_END_GROUP;
IADD.64 R8, R8, UR12 &req={1} ?WAIT7_END_GROUP;
LDG.E.U8 R8, desc[UR6][R8.64] &rd=0x0 &wr=0x5 ?trans2;
BSYNC.RECONVERGENT B1 ?trans5;
STS.U8 [R5+UR4+0x1], R8 &req={5} &rd=0x2 ?trans1;
BRA 0x430 ?trans5;
IADD3 R11, PT, PT, R7.reuse, 0x1, RZ &req={1} ?trans1;
ISETP.GE.AND P1, PT, R7, -0x1, PT ?trans1;
BSSY.RECONVERGENT B1, 0x420 ?trans3;
VIMNMX.S32 R8, R2, R11, !PT ?WAIT5_END_GROUP;
ISETP.GE.OR P1, PT, R8, UR8, !P1 ?trans1;
PRMT R8, RZ, 0x7610, R8 ?WAIT12_END_GROUP;
@P1 BRA 0x410 ?trans5;
LDCU.64 UR10, c[0x0][0x390] &wr=0x0 ?trans1;
MOV R8, R2 ?trans1;
HFMA2 R9, -RZ, RZ, 0, 0 ?trans1;
LDCU.64 UR12, c[0x0][0x380] &wr=0x1 ?trans3;
IMAD.WIDE.U32 R8, R11, UR10, R8 &req={0} ?WAIT4_END_GROUP;
IMAD R9, R11, UR11, R9 ?WAIT5_END_GROUP;
IADD.64 R8, R8, UR12 &req={1} ?WAIT7_END_GROUP;
LDG.E.U8 R8, desc[UR6][R8.64] &rd=0x0 &wr=0x5 ?trans2;
BSYNC.RECONVERGENT B1 ?trans5;
STS.U8 [R5+UR4+0x133], R8 &req={5} &rd=0x3 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
ISETP.NE.AND P1, PT, R5, 0xf, PT ?trans1;
BSSY.RECONVERGENT B0, 0x690 ?WAIT12_END_GROUP;
@!P1 BRA 0x590 ?trans5;
ISETP.NE.AND P1, PT, R5, RZ, PT ?WAIT13_END_GROUP;
@P1 BRA 0x680 ?trans5;
ISETP.EQ.OR P0, PT, R2, RZ, !P0 ?trans1;
BSSY.RECONVERGENT B1, 0x570 ?trans1;
PRMT R9, RZ, 0x7610, R9 &req={0} ?WAIT3_END_GROUP;
ISETP.GT.OR P0, PT, R2, UR8, P0 ?WAIT13_END_GROUP;
@P0 BRA 0x560 ?trans5;
LDCU.64 UR10, c[0x0][0x390] &wr=0x0 ?trans1;
IADD3 R8, PT, PT, R2, -0x1, RZ &req={3,2} ?trans1;
MOV R9, RZ ?trans1;
LDCU.64 UR12, c[0x0][0x380] &wr=0x2 ?trans3;
IMAD.WIDE.U32 R8, R7, UR10, R8 &req={0} ?WAIT4_END_GROUP;
IMAD R9, R7, UR11, R9 ?WAIT5_END_GROUP;
IADD.64 R8, R8, UR12 &req={2} ?WAIT7_END_GROUP;
LDG.E.U8 R9, desc[UR6][R8.64] &rd=0x0 &wr=0x5 ?trans2;
BSYNC.RECONVERGENT B1 ?trans5;
STS.U8 [R6+0x12], R9 &req={5} &rd=0x4 ?trans1;
BRA 0x680 ?trans5;
IADD3 R8, PT, PT, R2, 0x1, RZ &req={3,2} ?trans1;
BSSY.RECONVERGENT B1, 0x670 ?trans1;
PRMT R9, RZ, 0x7610, R9 &req={0} ?WAIT3_END_GROUP;
ISETP.GE.OR P0, PT, R8, UR8, !P0 ?WAIT13_END_GROUP;
@P0 BRA 0x660 ?trans5;
LDCU.64 UR10, c[0x0][0x390] &wr=0x0 ?trans1;
MOV R8, R2 ?trans1;
HFMA2 R9, -RZ, RZ, 0, 0 ?trans1;
LDCU.64 UR12, c[0x0][0x380] &wr=0x2 ?trans3;
IMAD.WIDE.U32 R8, R7, UR10, R8 &req={0} ?WAIT4_END_GROUP;
IMAD R9, R7, UR11, R9 ?WAIT5_END_GROUP;
IADD.64 R8, R8, UR12 &req={2} ?WAIT7_END_GROUP;
LDG.E.U8 R9, desc[UR6][R8.64+0x1] &rd=0x0 &wr=0x5 ?trans2;
BSYNC.RECONVERGENT B1 ?trans5;
STS.U8 [R6+0x23], R9 &req={5} &rd=0x2 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
LOP3.LUT P0, RZ, R0, R5, RZ, 0xfc, !PT ?trans1;
BSSY.RECONVERGENT B0, 0x7f0 ?WAIT12_END_GROUP;
@P0 BRA 0x7e0 ?trans5;
ISETP.GT.AND P0, PT, R7, UR8, PT ?trans1;
BSSY.RECONVERGENT B1, 0x7d0 ?trans1;
PRMT R9, RZ, 0x7610, R9 &req={4,2,0} ?WAIT3_END_GROUP;
ISETP.LT.OR P0, PT, R7, 0x1, P0 ?WAIT5_END_GROUP;
ISETP.EQ.OR P0, PT, R2, RZ, P0 ?WAIT5_END_GROUP;
ISETP.GT.OR P0, PT, R2, UR8, P0 ?WAIT13_END_GROUP;
@P0 BRA 0x7c0 ?trans5;
LDCU.64 UR10, c[0x0][0x390] &wr=0x0 ?trans1;
IADD3 R8, PT, PT, R2, -0x1, RZ &req={3} ?trans2;
IADD3 R11, PT, PT, R7, -0x1, RZ &req={1} ?trans1;
MOV R9, RZ ?trans1;
LDCU.64 UR12, c[0x0][0x380] &wr=0x1 ?trans3;
IMAD.WIDE.U32 R8, R11, UR10, R8 &req={0} ?WAIT4_END_GROUP;
IMAD R9, R11, UR11, R9 ?WAIT5_END_GROUP;
IADD.64 R8, R8, UR12 &req={1} ?WAIT7_END_GROUP;
LDG.E.U8 R9, desc[UR6][R8.64] &rd=0x0 &wr=0x5 ?trans2;
BSYNC.RECONVERGENT B1 ?trans5;
STS.U8 [R4], R9 &req={5} &rd=0x2 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
ISETP.NE.AND P0, PT, R5, RZ, PT ?trans1;
BSSY.RECONVERGENT B0, 0x960 ?trans4;
ISETP.NE.OR P0, PT, R0, 0xf, P0 ?WAIT13_END_GROUP;
@P0 BRA 0x950 ?trans5;
IADD3 R11, PT, PT, R7, 0x1, RZ &req={1} ?trans1;
BSSY.RECONVERGENT B1, 0x940 ?trans1;
PRMT R8, RZ, 0x7610, R8 &req={3,2,0} ?WAIT3_END_GROUP;
ISETP.GE.AND P0, PT, R11, UR8, PT ?WAIT5_END_GROUP;
ISETP.LT.OR P0, PT, R7, -0x1, P0 ?WAIT5_END_GROUP;
ISETP.EQ.OR P0, PT, R2, RZ, P0 ?WAIT5_END_GROUP;
ISETP.GT.OR P0, PT, R2, UR8, P0 ?WAIT13_END_GROUP;
@P0 BRA 0x930 ?trans5;
LDCU.64 UR10, c[0x0][0x390] &wr=0x0 ?trans1;
IADD3 R8, PT, PT, R2, -0x1, RZ ?trans1;
HFMA2 R9, -RZ, RZ, 0, 0 &req={4} ?trans1;
LDCU.64 UR12, c[0x0][0x380] &wr=0x1 ?trans3;
IMAD.WIDE.U32 R8, R11, UR10, R8 &req={0} ?WAIT4_END_GROUP;
IMAD R9, R11, UR11, R9 ?WAIT5_END_GROUP;
IADD.64 R8, R8, UR12 &req={1} ?WAIT7_END_GROUP;
LDG.E.U8 R8, desc[UR6][R8.64] &rd=0x0 &wr=0x5 ?trans2;
BSYNC.RECONVERGENT B1 ?trans5;
STS.U8 [UR4+0x132], R8 &req={5} &rd=0x1 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
ISETP.NE.AND P0, PT, R5, 0xf, PT ?trans1;
BSSY.RECONVERGENT B0, 0xc20 ?trans4;
ISETP.NE.OR P1, PT, R0, RZ, P0 ?WAIT13_END_GROUP;
@P1 BRA 0xad0 ?trans5;
ISETP.GT.AND P0, PT, R7.reuse, UR8, PT ?trans1;
IADD3 R0, PT, PT, R2, 0x1, RZ ?trans1;
BSSY.RECONVERGENT B1, 0xab0 ?trans1;
PRMT R8, RZ, 0x7610, R8 &req={3,2,1,0} ?trans2;
ISETP.LT.OR P0, PT, R7, 0x1, P0 ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R0, UR8, P0 ?WAIT13_END_GROUP;
@P0 BRA 0xaa0 ?trans5;
LDCU.64 UR10, c[0x0][0x390] &wr=0x0 ?trans1;
IADD3 R5, PT, PT, R7, -0x1, RZ ?trans1;
MOV R8, R2 ?trans1;
HFMA2 R9, -RZ, RZ, 0, 0 &req={4} ?trans1;
LDCU.64 UR12, c[0x0][0x380] &wr=0x1 ?trans3;
IMAD.WIDE.U32 R8, R5, UR10, R8 &req={0} ?WAIT4_END_GROUP;
IMAD R9, R5, UR11, R9 ?WAIT5_END_GROUP;
IADD.64 R8, R8, UR12 &req={1} ?WAIT7_END_GROUP;
LDG.E.U8 R8, desc[UR6][R8.64+0x1] &rd=0x0 &wr=0x5 ?trans2;
BSYNC.RECONVERGENT B1 ?trans5;
STS.U8 [UR4+0x11], R8 &req={5} &rd=0x1 ?trans1;
BRA 0xc10 ?trans5;
ISETP.NE.OR P0, PT, R0, 0xf, P0 ?WAIT13_END_GROUP;
@P0 BRA 0xc10 ?trans5;
IADD3 R5, PT, PT, R7.reuse, 0x1, RZ &req={3,2} ?trans2;
IADD3 R0, PT, PT, R2, 0x1, RZ ?trans1;
ISETP.GE.AND P0, PT, R7, -0x1, PT ?trans1;
BSSY.RECONVERGENT B1, 0xc00 ?trans1;
PRMT R8, RZ, 0x7610, R8 &req={1,0} ?trans2;
VIMNMX.S32 R0, R5, R0, !PT ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R0, UR8, !P0 ?WAIT13_END_GROUP;
@P0 BRA 0xbf0 ?trans5;
LDCU.64 UR10, c[0x0][0x390] &wr=0x0 ?trans1;
MOV R8, R2 ?trans1;
HFMA2 R9, -RZ, RZ, 0, 0 &req={4} ?trans1;
LDCU.64 UR12, c[0x0][0x380] &wr=0x1 ?trans3;
IMAD.WIDE.U32 R8, R5, UR10, R8 &req={0} ?WAIT4_END_GROUP;
IMAD R9, R5, UR11, R9 ?WAIT5_END_GROUP;
IADD.64 R8, R8, UR12 &req={1} ?WAIT7_END_GROUP;
LDG.E.U8 R8, desc[UR6][R8.64+0x1] &rd=0x0 &wr=0x5 ?trans2;
BSYNC.RECONVERGENT B1 ?trans5;
STS.U8 [UR4+0x143], R8 &req={5} &rd=0x1 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDCU.64 UR10, c[0x0][0x398] &wr=0x5 ?trans1;
LDCU.64 UR12, c[0x0][0x388] &wr=0x0 ?trans1;
LDS.U8 R0, [R4] ?trans4;
LDS.U8 R3, [R4+0x1] ?trans4;
LDS.U8 R6, [R4+0x2] &req={4,2} &wr=0x2 ?trans4;
LDS.U8 R9, [R4+0x12] &req={0} ?trans4;
LDS.U8 R8, [R4+0x14] &req={3,1} &wr=0x0 ?trans4;
LDS.U8 R11, [R4+0x24] ?trans4;
LDS.U8 R10, [R4+0x25] &wr=0x1 ?trans4;
LDS.U8 R13, [R4+0x26] &wr=0x3 ?trans4;
LDS.U8 R5, [R4+0x13] &wr=0x4 ?trans1;
IADD3 R0, PT, PT, R6, R3, R0 &req={2} ?WAIT2_END_GROUP;
SHF.R.S32.HI R6, RZ, 0x1f, R7 ?trans1;
MOV R3, RZ ?WAIT4_END_GROUP;
IMAD R6, R6, UR10, RZ &req={5} ?trans1;
IADD3 R0, PT, PT, R8, R0, R9 &req={0} ?trans1;
IMAD.WIDE.U32 R2, R7, UR10, R2 ?WAIT4_END_GROUP;
IMAD R7, R7, UR11, R6 ?trans1;
IADD3 R0, PT, PT, R10, R0, R11 &req={1} ?WAIT4_END_GROUP;
IADD3 R3, PT, PT, R3, R7, RZ ?trans2;
IADD3 R0, PT, PT, R0, R13, RZ &req={3} ?WAIT3_END_GROUP;
IADD.64 R2, R2, UR12 ?trans2;
ISETP.NE.AND P2, PT, R5.reuse, RZ, PT &req={4} ?trans1;
IADD3 R4, PT, PT, R0.reuse, -0x4, RZ ?trans2;
LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ?trans1;
ISETP.NE.AND P0, PT, R5, RZ, PT ?trans1;
LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ?WAIT3_END_GROUP;
ISETP.NE.AND P3, PT, R0, 0x3, PT ?trans2;
ISETP.GE.U32.AND P1, PT, R4, 0xfe, PT ?WAIT3_END_GROUP;
@!P2 SEL R5, R5, 0x1, P3 ?WAIT5_END_GROUP;
@P0 SEL R5, R5, RZ, P1 ?WAIT5_END_GROUP;
STG.E.U8 desc[UR6][R2.64], R5 ?trans1;
EXIT ?trans5;
BRA 0xe40;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: faster_game_of_life_iter(char*, char*, unsigned long, unsigned long, int)
_Z24faster_game_of_life_iterPcS_mmi:
s_clause 0x1
s_load_b256 s[16:23], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x20
v_and_b32_e32 v4, 0x3ff, v0
v_bfe_u32 v5, v0, 10, 10
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshl_add_u32 v1, s14, 4, v4
v_lshl_add_u32 v0, s15, 4, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_i32_e64 s1, -1, v1
v_max_i32_e32 v3, v1, v0
s_delay_alu instid0(VALU_DEP_2)
s_and_saveexec_b32 s2, s1
s_cbranch_execz .LBB1_4
v_cmp_lt_i32_e32 vcc_lo, -1, v0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s0, s6, v3
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s0, vcc_lo
s_and_saveexec_b32 s0, s3
s_cbranch_execz .LBB1_3
v_mad_u64_u32 v[6:7], null, v1, s20, s[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v2, v7
v_add_co_u32 v6, vcc_lo, v6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[7:8], null, v1, s21, v[2:3]
v_mov_b32_e32 v2, v7
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v2, vcc_lo
global_load_u8 v6, v[6:7], off
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s0
.LBB1_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
v_mad_u32_u24 v2, v4, 18, v5
v_cmp_eq_u32_e32 vcc_lo, 0, v4
s_waitcnt vmcnt(0)
ds_store_b8 v2, v6 offset:19
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB1_10
v_mov_b32_e32 v6, 0
s_mov_b32 s5, exec_lo
v_cmpx_lt_i32_e32 0, v1
s_cbranch_execz .LBB1_9
s_waitcnt lgkmcnt(0)
v_cmp_ge_i32_e64 s0, s6, v1
v_cmp_lt_i32_e64 s2, -1, v0
v_cmp_gt_i32_e64 s3, s6, v0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_3)
s_and_b32 s0, s2, s0
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s3, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s0
s_cbranch_execz .LBB1_8
v_add_nc_u32_e32 v10, -1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[6:7], null, v10, s20, s[16:17]
v_mad_u64_u32 v[8:9], null, v10, s21, v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, s0, v6, v0
v_mov_b32_e32 v7, v8
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, s0, 0, v7, s0
global_load_u8 v6, v[6:7], off
.LBB1_8:
s_or_b32 exec_lo, exec_lo, s2
.LBB1_9:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt vmcnt(0)
ds_store_b8 v5, v6 offset:1
.LBB1_10:
s_or_b32 exec_lo, exec_lo, s4
v_cmp_eq_u32_e64 s0, 15, v4
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s4, s0
s_cbranch_execz .LBB1_16
v_mov_b32_e32 v6, 0
s_mov_b32 s5, exec_lo
v_cmpx_lt_i32_e32 -2, v1
s_cbranch_execz .LBB1_15
v_add_nc_u32_e32 v7, 1, v1
v_cmp_lt_i32_e64 s2, -1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_max_i32_e32 v6, v7, v0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s3, s6, v6
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s3, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_14
v_mad_u64_u32 v[8:9], null, v7, s20, s[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v6, v9
v_mad_u64_u32 v[9:10], null, v7, s21, v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, s2, v8, v0
v_mov_b32_e32 v7, v9
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, s2, 0, v7, s2
global_load_u8 v6, v[6:7], off
.LBB1_14:
s_or_b32 exec_lo, exec_lo, s3
.LBB1_15:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt vmcnt(0)
ds_store_b8 v5, v6 offset:307
.LBB1_16:
s_or_b32 exec_lo, exec_lo, s4
v_mul_u32_u24_e32 v6, 18, v4
v_cmp_eq_u32_e64 s3, 0, v5
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s7, s3
s_cbranch_execz .LBB1_20
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s2, s6, v1
v_cmp_lt_i32_e64 s4, 0, v0
v_cmp_ge_i32_e64 s5, s6, v0
v_mov_b32_e32 v7, 0
s_delay_alu instid0(VALU_DEP_3)
s_and_b32 s2, s4, s2
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s5, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s1, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB1_19
v_mad_u64_u32 v[7:8], null, v1, s20, s[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[9:10], null, v1, s21, v[8:9]
v_add_co_u32 v7, s2, v7, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v8, v9
v_add_co_ci_u32_e64 v8, s2, 0, v8, s2
global_load_u8 v7, v[7:8], off offset:-1
.LBB1_19:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt vmcnt(0)
ds_store_b8 v6, v7 offset:18
.LBB1_20:
s_or_b32 exec_lo, exec_lo, s7
v_cmp_eq_u32_e64 s2, 15, v5
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s5, s2
s_cbranch_execz .LBB1_26
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s4, s6, v1
v_mov_b32_e32 v7, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s1, s1, s4
s_and_saveexec_b32 s7, s1
s_cbranch_execz .LBB1_25
v_dual_mov_b32 v7, 0 :: v_dual_add_nc_u32 v8, 1, v0
v_cmp_lt_i32_e64 s1, -2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s4, s6, v8
s_and_b32 s1, s1, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s1
s_cbranch_execz .LBB1_24
v_mad_u64_u32 v[9:10], null, v1, s20, s[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v7, v10
v_mad_u64_u32 v[10:11], null, v1, s21, v[7:8]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v7, s1, v9, v8
v_add_co_ci_u32_e64 v8, s1, 0, v10, s1
global_load_u8 v7, v[7:8], off
.LBB1_24:
s_or_b32 exec_lo, exec_lo, s4
.LBB1_25:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s7
s_waitcnt vmcnt(0)
ds_store_b8 v6, v7 offset:35
.LBB1_26:
s_or_b32 exec_lo, exec_lo, s5
v_or_b32_e32 v4, v4, v5
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB1_30
v_min_i32_e32 v4, v1, v0
s_waitcnt lgkmcnt(0)
v_cmp_ge_i32_e64 s4, s6, v3
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_lt_i32_e64 s1, 0, v4
v_mov_b32_e32 v4, 0
s_and_b32 s1, s4, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s1
s_cbranch_execz .LBB1_29
v_add_nc_u32_e32 v8, -1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v8, s20, s[16:17]
v_mad_u64_u32 v[6:7], null, v8, s21, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, s1, v4, v0
v_mov_b32_e32 v5, v6
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s1, 0, v5, s1
global_load_u8 v4, v[4:5], off offset:-1
.LBB1_29:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt vmcnt(0)
ds_store_b8 v3, v4
.LBB1_30:
s_or_b32 exec_lo, exec_lo, s5
v_add_nc_u32_e32 v3, 1, v1
s_and_b32 s1, s0, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s7, s1
s_cbranch_execz .LBB1_34
v_cmp_lt_i32_e64 s1, -2, v1
v_cmp_lt_i32_e64 s3, 0, v0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s4, s6, v3
v_cmp_ge_i32_e64 s5, s6, v0
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0
s_and_b32 s1, s1, s3
s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
s_and_b32 s1, s1, s4
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s1, s5, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s1
s_cbranch_execz .LBB1_33
v_mad_u64_u32 v[5:6], null, v3, s20, s[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[7:8], null, v3, s21, v[6:7]
v_add_co_u32 v5, s1, v5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v6, v7
v_add_co_ci_u32_e64 v6, s1, 0, v6, s1
global_load_u8 v5, v[5:6], off offset:-1
.LBB1_33:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt vmcnt(0)
ds_store_b8 v4, v5 offset:306
.LBB1_34:
s_or_b32 exec_lo, exec_lo, s7
s_and_b32 s1, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s1
s_cbranch_execz .LBB1_40
v_cmp_lt_i32_e32 vcc_lo, 0, v1
s_waitcnt lgkmcnt(0)
v_cmp_ge_i32_e64 s1, s6, v1
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s1, vcc_lo, s1
s_and_saveexec_b32 s4, s1
s_cbranch_execz .LBB1_39
v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v6, 1, v0
v_cmp_lt_i32_e32 vcc_lo, -2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s1, s6, v6
s_and_b32 s5, vcc_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s5
s_cbranch_execz .LBB1_38
v_add_nc_u32_e32 v10, -1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[7:8], null, v10, s20, s[16:17]
v_mov_b32_e32 v5, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[8:9], null, v10, s21, v[5:6]
v_add_co_u32 v5, vcc_lo, v7, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v8, vcc_lo
global_load_u8 v5, v[5:6], off
.LBB1_38:
s_or_b32 exec_lo, exec_lo, s1
.LBB1_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt vmcnt(0)
ds_store_b8 v4, v5 offset:17
.LBB1_40:
s_or_b32 exec_lo, exec_lo, s3
s_and_b32 s0, s0, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB1_46
v_cmp_lt_i32_e32 vcc_lo, -2, v1
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s0, s6, v3
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s2, s0
s_cbranch_execz .LBB1_45
v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v6, 1, v0
v_cmp_lt_i32_e32 vcc_lo, -2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s0, s6, v6
s_and_b32 s3, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s3
s_cbranch_execz .LBB1_44
v_mad_u64_u32 v[7:8], null, v3, s20, s[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v5, v8
v_mad_u64_u32 v[8:9], null, v3, s21, v[5:6]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, v7, v6
v_mov_b32_e32 v3, v8
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v3, vcc_lo
global_load_u8 v5, v[5:6], off
.LBB1_44:
s_or_b32 exec_lo, exec_lo, s0
.LBB1_45:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt vmcnt(0)
ds_store_b8 v4, v5 offset:323
.LBB1_46:
s_or_b32 exec_lo, exec_lo, s1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_u8 v4, v2
ds_load_u8 v5, v2 offset:1
ds_load_u8 v6, v2 offset:2
ds_load_u8 v7, v2 offset:18
ds_load_u8 v8, v2 offset:20
ds_load_u8 v3, v2 offset:19
ds_load_u8 v9, v2 offset:36
ds_load_u8 v10, v2 offset:37
ds_load_u8 v2, v2 offset:38
s_waitcnt lgkmcnt(7)
v_add_nc_u16 v4, v5, v4
v_mul_lo_u32 v5, v1, s23
s_waitcnt lgkmcnt(3)
v_cmp_eq_u16_e32 vcc_lo, 0, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u16 v4, v4, v6
v_add_nc_u16 v4, v4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u16 v4, v4, v8
s_waitcnt lgkmcnt(2)
v_add_nc_u16 v4, v4, v9
s_waitcnt lgkmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u16 v4, v4, v10
s_waitcnt lgkmcnt(0)
v_add_nc_u16 v6, v4, v2
v_ashrrev_i32_e32 v4, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u16 v2, v6, -4
v_mul_lo_u32 v4, v4, s22
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v2, 0xff, v2
v_cmp_lt_u16_e64 s0, 0xfd, v2
v_ashrrev_i32_e32 v2, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s1
s_cbranch_execz .LBB1_52
v_mad_u64_u32 v[7:8], null, v1, s22, s[18:19]
v_and_b32_e32 v1, 0xff, v6
v_cmp_ne_u16_e32 vcc_lo, 0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_ne_u16_e64 s0, 3, v1
v_add3_u32 v4, v4, v8, v5
v_add_co_u32 v0, s1, v7, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
s_or_b32 s0, vcc_lo, s0
v_add_co_ci_u32_e64 v1, s1, v4, v2, s1
s_and_saveexec_b32 s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s1
s_cbranch_execz .LBB1_49
global_store_b8 v[0:1], v3, off
.LBB1_49:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB1_51
v_mov_b32_e32 v2, 1
global_store_b8 v[0:1], v2, off
.LBB1_51:
s_or_b32 exec_lo, exec_lo, s0
.LBB1_52:
s_and_not1_saveexec_b32 s0, s2
s_cbranch_execz .LBB1_54
v_mad_u64_u32 v[6:7], null, v1, s22, s[18:19]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v1, v4, v7, v5
v_add_co_u32 v0, vcc_lo, v6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v2, vcc_lo
v_mov_b32_e32 v2, 0
global_store_b8 v[0:1], v2, off
.LBB1_54:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| faster_game_of_life_iter | 5,549 | 7,075 | stackv2-00000-of-00015 |
// Demangled: game_of_life_iter(char*, char*, unsigned long, unsigned long, int)
Function : _Z17game_of_life_iterPcS_mmi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R27, SR_TID.X &wr=0x0 ?trans1;
LDCU UR6, c[0x0][0x3a0] &wr=0x1 ?trans1;
PRMT R31, RZ, 0x7610, R31 ?trans1;
S2R R0, SR_CTAID.X &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans1;
S2R R2, SR_TID.Y &wr=0x3 ?trans1;
S2R R3, SR_CTAID.Y &wr=0x3 ?trans1;
PRMT R28, RZ, 0x7610, R28 ?trans1;
LDCU.64 UR8, c[0x0][0x388] &wr=0x4 ?trans1;
IMAD R27, R0, 0x10, R27 &req={0} ?WAIT5_END_GROUP;
ISETP.GT.AND P1, PT, R27.reuse, UR6, PT &req={1} ?trans1;
ISETP.GE.AND P2, PT, R27.reuse, UR6, PT ?trans1;
IADD3 R29, PT, PT, R27, 0x1, RZ ?trans1;
IMAD R2, R3, 0x10, R2 &req={3} ?trans2;
ISETP.GT.AND P1, PT, R27.reuse, RZ, !P1 ?trans1;
ISETP.GT.AND P2, PT, R27, -0x1, !P2 ?trans1;
ISETP.GE.AND P0, PT, R29, UR6, PT ?trans1;
IADD3 R18, PT, PT, R2.reuse, 0x1, RZ ?trans2;
ISETP.EQ.OR P4, PT, R2.reuse, RZ, !P1 ?trans1;
ISETP.GE.OR P5, PT, R2.reuse, UR6, !P1 ?trans1;
ISETP.EQ.OR P3, PT, R2, RZ, !P2 ?trans1;
ISETP.GE.OR P1, PT, R18, UR6, !P1 ?trans1;
ISETP.GT.AND P0, PT, R27, -0x2, !P0 ?trans1;
ISETP.GT.OR P4, PT, R2, UR6, P4 ?WAIT2_END_GROUP;
ISETP.GT.OR P3, PT, R2, UR6, P3 ?WAIT7_END_GROUP;
@!P5 LDC.64 R12, c[0x0][0x390] &wr=0x0 ?trans4;
@!P4 IADD3 R4, PT, PT, R2, -0x1, RZ ?trans2;
@!P4 IADD3 R3, PT, PT, R27, -0x1, RZ ?trans1;
@!P4 MOV R5, RZ ?trans1;
@!P4 LDC.64 R8, c[0x0][0x390] &wr=0x1 ?trans8;
@!P4 LDC.64 R6, c[0x0][0x380] &wr=0x3 ?trans1;
ISETP.GE.OR P6, PT, R18, UR6, !P2 ?WAIT7_END_GROUP;
@!P5 LDC.64 R14, c[0x0][0x380] &wr=0x5 ?trans1;
@!P4 IMAD.WIDE.U32 R4, R3, R8, R4 &req={1} ?WAIT7_END_GROUP;
@!P6 LDC.64 R24, c[0x0][0x390] &wr=0x1 ?trans1;
@!P4 IMAD R5, R3, R9, R5 ?trans1;
@!P5 IADD3 R9, PT, PT, R27, -0x1, RZ ?trans1;
HFMA2 R3, -RZ, RZ, 0, 0 ?WAIT3_END_GROUP;
@!P4 IADD.64 R4, R4, R6 &req={3} ?trans2;
@!P5 IMAD.WIDE.U32 R10, R9.reuse, R12, R2 &req={0} ?trans1;
@!P1 LDC.64 R6, c[0x0][0x390] &wr=0x0 ?trans3;
@!P5 IMAD R11, R9, R13, R11 ?trans1;
@!P4 LDG.E.U8 R31, desc[UR4][R4.64] &req={2} &rd=0x2 &wr=0x3 ?trans4;
@!P3 LDC.64 R8, c[0x0][0x390] &wr=0x1 ?trans1;
ISETP.EQ.OR P4, PT, R2, RZ, !P0 ?WAIT5_END_GROUP;
ISETP.GT.OR P4, PT, R2, UR6, P4 ?trans1;
@!P5 IADD.64 R14, R10, R14 &req={5} ?trans2;
@!P1 LDC.64 R10, c[0x0][0x380] &wr=0x5 ?trans1;
PRMT R0, RZ, 0x7610, R0 ?trans2;
@!P1 IADD3 R19, PT, PT, R27, -0x1, RZ ?trans2;
@!P3 IADD3 R12, PT, PT, R2.reuse, -0x1, RZ ?trans1;
@!P3 MOV R13, RZ ?trans1;
@!P5 LDG.E.U8 R0, desc[UR4][R14.64] &rd=0x0 &wr=0x3 ?trans1;
@!P3 LDC.64 R16, c[0x0][0x380] &wr=0x4 ?trans1;
@!P1 IMAD.WIDE.U32 R20, R19, R6, R2 &req={0} ?trans1;
ISETP.GE.OR P5, PT, R2, UR6, !P0 ?WAIT6_END_GROUP;
@!P4 LDC.64 R4, c[0x0][0x390] &req={2} &wr=0x0 ?trans1;
@!P3 IMAD.WIDE.U32 R12, R27, R8, R12 &req={1} ?trans1;
ISETP.GE.OR P2, PT, R2, UR6, !P2 ?trans1;
ISETP.GE.OR P0, PT, R18, UR6, !P0 ?trans1;
PRMT R26, RZ, 0x7610, R26 ?trans1;
@!P1 IMAD R21, R19, R7, R21 ?trans2;
@!P6 IMAD.WIDE.U32 R22, R27.reuse, R24, R2 ?trans1;
@!P5 LDC.64 R6, c[0x0][0x390] &wr=0x1 ?trans1;
@!P3 MOV R18, R12 ?trans1;
LDCU.64 UR6, c[0x0][0x398] &wr=0x2 ?trans1;
@!P3 IMAD R19, R27, R9, R13 ?WAIT5_END_GROUP;
@!P6 LDC.64 R8, c[0x0][0x380] &wr=0x1 ?trans1;
@!P6 IMAD R23, R27, R25, R23 ?trans1;
@!P1 IADD.64 R10, R20, R10 &req={5} ?WAIT3_END_GROUP;
@!P4 IADD3 R24, PT, PT, R2, -0x1, RZ ?trans1;
@!P4 MOV R25, RZ ?trans2;
@!P2 LDC.64 R12, c[0x0][0x390] &wr=0x5 ?trans1;
@!P3 IADD.64 R16, R18, R16 &req={4} ?trans2;
@!P4 IMAD.WIDE.U32 R24, R29.reuse, R4, R24 &req={0} ?trans1;
@!P1 LDG.E.U8 R28, desc[UR4][R10.64+0x1] &wr=0x3 ?trans4;
@!P0 LDC.64 R20, c[0x0][0x390] &wr=0x0 ?trans1;
@!P4 IMAD R25, R29, R5, R25 ?trans1;
@!P3 LDG.E.U8 R26, desc[UR4][R16.64] &rd=0x4 &wr=0x3 ?trans6;
@!P4 LDC.64 R14, c[0x0][0x380] &wr=0x2 ?trans1;
@!P6 IADD.64 R8, R22, R8 &req={1} ?WAIT7_END_GROUP;
@!P5 LDC.64 R18, c[0x0][0x380] &wr=0x1 ?trans8;
@!P0 LDC.64 R4, c[0x0][0x380] &wr=0x1 ?trans1;
@!P5 IMAD.WIDE.U32 R32, R29, R6, R2 ?WAIT7_END_GROUP;
@!P2 LDC.64 R22, c[0x0][0x380] &wr=0x1 ?trans1;
@!P5 IMAD R33, R29, R7, R33 ?trans1;
PRMT R17, RZ, 0x7610, R17 &req={4} ?trans1;
@!P2 IMAD.WIDE.U32 R6, R27, R12, R2 &req={5} ?WAIT4_END_GROUP;
@!P0 IMAD.WIDE.U32 R10, R29, R20, R2 &req={0} ?trans1;
@!P4 IADD.64 R14, R24, R14 &req={2} ?trans2;
@!P5 IADD.64 R18, R32, R18 &req={1} ?trans2;
@!P2 IMAD R7, R27, R13, R7 ?trans1;
PRMT R13, RZ, 0x7610, R13 ?trans1;
@!P0 IMAD R11, R29, R21, R11 ?trans1;
PRMT R12, RZ, 0x7610, R12 ?trans1;
@!P6 LDG.E.U8 R17, desc[UR4][R8.64+0x1] &wr=0x2 ?trans3;
@!P0 IADD.64 R4, R10, R4 ?WAIT2_END_GROUP;
@!P4 LDG.E.U8 R13, desc[UR4][R14.64] &wr=0x4 ?trans1;
PRMT R10, RZ, 0x7610, R10 ?trans1;
@!P2 IADD.64 R22, R6, R22 ?trans2;
@!P5 LDG.E.U8 R12, desc[UR4][R18.64] &wr=0x4 ?trans1;
PRMT R7, RZ, 0x7610, R7 ?WAIT3_END_GROUP;
@!P0 LDG.E.U8 R10, desc[UR4][R4.64+0x1] &wr=0x5 ?trans4;
@!P2 LDG.E.U8 R7, desc[UR4][R22.64] &wr=0x5 ?trans1;
IMAD.WIDE.U32 R2, R27, UR6, R2 ?trans1;
IADD3 R0, PT, PT, R28, R0, R31 &req={3} ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R17, R0, R26 &req={2} ?WAIT4_END_GROUP;
IADD3 R13, PT, PT, R12, R0, R13 &req={4} ?trans2;
SHF.R.S32.HI R0, RZ, 0x1f, R27 ?trans2;
IADD3 R10, PT, PT, R13, R10, RZ &req={5} ?WAIT3_END_GROUP;
IMAD R6, R0, UR6, RZ ?trans1;
LOP3.LUT P0, RZ, R7, 0xff, RZ, 0xc0, !PT ?trans2;
IADD3 R0, PT, PT, R10.reuse, -0x4, RZ ?trans2;
LOP3.LUT R10, R10, 0xff, RZ, 0xc0, !PT ?trans1;
IMAD R27, R27, UR7, R6 ?trans1;
LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ?WAIT3_END_GROUP;
ISETP.NE.AND P2, PT, R10, 0x3, PT ?trans1;
IADD3 R3, PT, PT, R3, R27, RZ ?trans1;
ISETP.GE.U32.AND P1, PT, R0, 0xfe, PT ?WAIT3_END_GROUP;
@!P0 SEL R7, R7, 0x1, P2 ?trans1;
IADD.64 R2, R2, UR8 ?WAIT4_END_GROUP;
@P0 SEL R7, R7, RZ, P1 ?WAIT5_END_GROUP;
STG.E.U8 desc[UR4][R2.64], R7 ?trans1;
EXIT ?trans5;
BRA 0x7d0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: game_of_life_iter(char*, char*, unsigned long, unsigned long, int)
_Z17game_of_life_iterPcS_mmi:
s_clause 0x1
s_load_b256 s[16:23], s[0:1], 0x0
s_load_b32 s5, s[0:1], 0x20
v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshl_add_u32 v1, s14, 4, v1
v_lshl_add_u32 v0, s15, 4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e64 s1, -1, v1
s_and_saveexec_b32 s2, s1
s_cbranch_execz .LBB0_4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_max_i32_e32 v2, v1, v0
v_cmp_lt_i32_e32 vcc_lo, -1, v0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s0, s5, v2
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s0, vcc_lo
s_and_saveexec_b32 s0, s3
s_cbranch_execz .LBB0_3
v_mad_u64_u32 v[4:5], null, v1, s20, s[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v2, v5
v_add_co_u32 v4, vcc_lo, v4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, s21, v[2:3]
v_mov_b32_e32 v2, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v2, vcc_lo
global_load_u8 v2, v[4:5], off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
v_cmp_lt_i32_e64 s3, 0, v1
s_waitcnt lgkmcnt(0)
v_cmp_ge_i32_e64 s2, s5, v1
v_cmp_lt_i32_e64 s0, 0, v0
v_cmp_lt_i32_e32 vcc_lo, s5, v0
v_add_nc_u32_e32 v7, -1, v1
s_delay_alu instid0(VALU_DEP_4)
s_and_b32 s6, s3, s2
s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
s_and_b32 s4, s0, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s4, s4, -1
s_or_b32 s4, vcc_lo, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s4, s4, -1
s_and_saveexec_b32 s7, s4
s_cbranch_execz .LBB0_6
v_mad_u64_u32 v[3:4], null, v7, s20, s[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[5:6], null, v7, s21, v[4:5]
v_add_co_u32 v3, s4, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v4, v5
v_add_co_ci_u32_e64 v4, s4, 0, v4, s4
global_load_u8 v3, v[3:4], off offset:-1
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s7
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0
s_and_saveexec_b32 s7, s3
s_cbranch_execz .LBB0_10
v_cmp_lt_i32_e64 s3, -1, v0
v_cmp_gt_i32_e64 s4, s5, v0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s3, s4
s_and_b32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_9
v_mad_u64_u32 v[5:6], null, v7, s20, s[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[8:9], null, v7, s21, v[6:7]
v_add_co_u32 v5, s2, v5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v6, v8
v_add_co_ci_u32_e64 v6, s2, 0, v6, s2
global_load_u8 v5, v[5:6], off
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s3
.LBB0_10:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v6, 1, v0
s_and_saveexec_b32 s4, s6
s_cbranch_execz .LBB0_14
v_cmp_lt_i32_e64 s2, -2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e64 s3, s5, v6
v_mov_b32_e32 v4, 0
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_13
v_mad_u64_u32 v[8:9], null, v7, s20, s[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mov_b32_e32 v4, v9
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[9:10], null, v7, s21, v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, s2, v8, v6
v_mov_b32_e32 v4, v9
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v8, s2, 0, v4, s2
global_load_u8 v4, v[7:8], off
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s3
.LBB0_14:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s4
v_cmp_gt_i32_e64 s2, s5, v1
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v7, 0
s_and_b32 s2, s1, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s1, s0, s2
s_xor_b32 s1, s1, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s1, vcc_lo, s1
s_xor_b32 s1, s1, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s1
s_cbranch_execz .LBB0_16
v_mad_u64_u32 v[9:10], null, v1, s20, s[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v7, v10
v_add_co_u32 v9, s1, v9, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[10:11], null, v1, s21, v[7:8]
v_mov_b32_e32 v7, v10
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v10, s1, 0, v7, s1
global_load_u8 v7, v[9:10], off offset:-1
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_20
v_cmp_lt_i32_e64 s1, -2, v0
v_cmp_gt_i32_e64 s2, s5, v6
v_mov_b32_e32 v8, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s1, s1, s2
s_and_saveexec_b32 s2, s1
s_cbranch_execz .LBB0_19
v_mad_u64_u32 v[8:9], null, v1, s20, s[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[10:11], null, v1, s21, v[9:10]
v_add_co_u32 v8, s1, v8, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v9, v10
v_add_co_ci_u32_e64 v9, s1, 0, v9, s1
global_load_u8 v8, v[8:9], off
.LBB0_19:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_20:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
s_or_b32 exec_lo, exec_lo, s3
v_dual_mov_b32 v11, 0 :: v_dual_add_nc_u32 v10, 1, v1
v_cmp_lt_i32_e64 s2, -2, v1
v_mov_b32_e32 v9, 0
v_cmp_gt_i32_e64 s1, s5, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s2, s1
s_and_b32 s0, s0, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s0, s0, -1
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s4, s0, -1
s_and_saveexec_b32 s0, s4
s_cbranch_execz .LBB0_22
v_mad_u64_u32 v[12:13], null, v10, s20, s[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v9, v13
v_add_co_u32 v12, vcc_lo, v12, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[13:14], null, v10, s21, v[9:10]
v_mov_b32_e32 v9, v13
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v9, vcc_lo
global_load_u8 v9, v[12:13], off offset:-1
.LBB0_22:
s_or_b32 exec_lo, exec_lo, s0
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_26
v_cmp_lt_i32_e32 vcc_lo, -1, v0
v_cmp_gt_i32_e64 s0, s5, v0
v_mov_b32_e32 v11, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_b32 s1, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_25
v_mad_u64_u32 v[11:12], null, v10, s20, s[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[13:14], null, v10, s21, v[12:13]
v_add_co_u32 v11, vcc_lo, v11, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v12, v13
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
global_load_u8 v11, v[11:12], off
.LBB0_25:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_26:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
v_mov_b32_e32 v12, 0
s_and_saveexec_b32 s1, s3
s_cbranch_execz .LBB0_30
v_cmp_lt_i32_e32 vcc_lo, -2, v0
v_cmp_gt_i32_e64 s0, s5, v6
v_mov_b32_e32 v12, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s0
s_and_saveexec_b32 s0, s2
s_cbranch_execz .LBB0_29
v_mad_u64_u32 v[12:13], null, v10, s20, s[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[14:15], null, v10, s21, v[13:14]
v_add_co_u32 v12, vcc_lo, v12, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v10, v14
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v10, vcc_lo
global_load_u8 v12, v[12:13], off
.LBB0_29:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_30:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s1
s_waitcnt vmcnt(0)
v_add_nc_u16 v3, v5, v3
v_mul_lo_u32 v5, v1, s23
v_add_nc_u16 v3, v3, v4
v_ashrrev_i32_e32 v4, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u16 v3, v3, v7
v_and_b32_e32 v7, 0xff, v2
v_mul_lo_u32 v4, v4, s22
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u16 v3, v3, v8
v_cmp_eq_u16_e32 vcc_lo, 0, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u16 v3, v3, v9
v_add_nc_u16 v3, v3, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u16 v6, v3, v12
v_add_nc_u16 v3, v6, -4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v3, 0xff, v3
v_cmp_lt_u16_e64 s0, 0xfd, v3
v_ashrrev_i32_e32 v3, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s1
s_cbranch_execz .LBB0_36
v_mad_u64_u32 v[8:9], null, v1, s22, s[18:19]
v_and_b32_e32 v1, 0xff, v6
v_cmp_ne_u16_e32 vcc_lo, 0, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_ne_u16_e64 s0, 3, v1
v_add3_u32 v4, v4, v9, v5
v_add_co_u32 v0, s1, v8, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
s_or_b32 s0, vcc_lo, s0
v_add_co_ci_u32_e64 v1, s1, v4, v3, s1
s_and_saveexec_b32 s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s1
s_cbranch_execz .LBB0_33
global_store_b8 v[0:1], v2, off
.LBB0_33:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_35
v_mov_b32_e32 v2, 1
global_store_b8 v[0:1], v2, off
.LBB0_35:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_36:
s_and_not1_saveexec_b32 s0, s2
s_cbranch_execz .LBB0_38
v_mad_u64_u32 v[6:7], null, v1, s22, s[18:19]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add3_u32 v1, v4, v7, v5
v_add_co_u32 v0, vcc_lo, v6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
global_store_b8 v[0:1], v2, off
.LBB0_38:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| game_of_life_iter | 3,562 | 5,766 | stackv2-00000-of-00015 |
// Demangled: GaussFirst(double*, double*, unsigned int, unsigned int)
Function : _Z10GaussFirstPdS_jj
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
LDCU.64 UR10, c[0x0][0x390] &wr=0x1 ?trans1;
LDCU.64 UR12, c[0x3][URZ] &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x380] &wr=0x2 ?trans1;
LDCU.64 UR8, c[0x0][0x358] &wr=0x3 ?trans1;
UIMAD UR4, UR12, UR11, UR10 &req={1} ?trans1;
UISETP.GE.U32.AND UP1, UPT, UR11, UR13, UPT ?trans1;
UISETP.GE.U32.AND UP0, UPT, UR10, UR12, UPT ?trans2;
USHF.R.S32.HI UR5, URZ, 0x1f, UR4 ?WAIT4_END_GROUP;
USEL.64 UR4, UR4, -0x1, !UP1 ?WAIT4_END_GROUP;
USEL.64 UR4, UR4, -0x1, !UP0 ?WAIT4_END_GROUP;
ULEA UR6, UP0, UR4, UR6, 0x3 &req={2} ?WAIT4_END_GROUP;
ULEA.HI.X UR4, UR4, UR7, UR5, 0x3, UP0 ?trans2;
MOV R2, UR6 ?WAIT4_END_GROUP;
MOV R3, UR4 ?WAIT6_END_GROUP;
LDG.E.64 R2, desc[UR8][R2.64] &req={3} &wr=0x2 ?trans1;
UMOV.64 UR4, 0x3e7ad7f29abcaf48 ?trans2;
DSETP.GT.AND P0, PT, |R2|, UR4, PT &req={2} &wr=0x1 ?trans2;
@!P0 EXIT &req={1,0} ?trans5;
S2R R0, SR_CTAID.X &wr=0x0 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x0 ?trans1;
S2R R3, SR_TID.X &wr=0x0 ?trans2;
IMAD R0, R0, UR5, R3 &req={0} ?WAIT5_END_GROUP;
IADD3.X R5, PT, PT, R0, UR10, RZ, PT, !PT ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R5, UR12, PT ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
S2R R0, SR_CTAID.Y &wr=0x0 ?trans1;
LDCU UR4, c[0x0][0x364] &wr=0x0 ?trans1;
S2R R3, SR_TID.Y &wr=0x0 ?trans1;
LDCU UR6, c[0x0][0x374] &wr=0x1 ?trans1;
LDCU UR7, c[0x0][0x370] &wr=0x2 ?trans1;
LDCU.64 UR12, c[0x0][0x388] &wr=0x3 ?trans1;
UIMAD UR5, UR5, UR7, URZ &req={2} ?trans1;
IMAD R0, R0, UR4, R3 &req={0} ?trans1;
UIMAD UR4, UR4, UR6, URZ &req={1} ?WAIT4_END_GROUP;
IADD3.X R4, PT, PT, R0, UR11, RZ, PT, !PT &req={3} ?WAIT8_END_GROUP;
LDC.64 R2, c[0x3][RZ] &req={0} &wr=0x0 ?trans1;
LDCU UR6, c[0x0][0x394] &wr=0x0 ?trans7;
LDC.64 R10, c[0x0][0x380] &req={1} &wr=0x1 ?trans1;
IMAD R6, R2, UR6, R5 &req={0} ?trans1;
ISETP.LE.U32.AND P1, PT, R3, UR6, PT ?trans1;
ISETP.GE.U32.AND P0, PT, R5, R2, PT ?WAIT3_END_GROUP;
SHF.R.S32.HI R7, RZ, 0x1f, R6 ?WAIT5_END_GROUP;
SEL.64 R6, R6, -0x1, !P1 ?WAIT4_END_GROUP;
SEL.64 R8, R6, -0x1, !P0 ?WAIT5_END_GROUP;
LEA R6, P1, R8, R10, 0x3 &req={1} ?WAIT4_END_GROUP;
LEA.HI.X R7, R8, R11, R9, 0x3, P1 ?WAIT5_END_GROUP;
LDG.E.64 R8, desc[UR8][R6.64] &wr=0x2 ?trans1;
UMOV.64 UR6, 0x3e7ad7f29abcaf48 ?trans1;
BSSY.RECONVERGENT B0, 0x6d0 ?trans1;
DSETP.GT.AND P1, PT, |R8|, UR6, PT &req={2} &wr=0x0 ?trans3;
@!P1 BRA 0x6c0 &req={0} ?trans5;
LDC R9, c[0x3][0x8] &wr=0x0 ?trans1;
ISETP.GE.U32.AND P2, PT, R4, R3, PT ?trans1;
BSSY.RECONVERGENT B1, 0x520 ?trans1;
ISETP.GE.U32.AND P1, PT, R0, R9, PT &req={0} ?WAIT11_END_GROUP;
@P2 BRA 0x510 ?trans5;
LDC R23, c[0x0][0x390] &wr=0x0 ?trans1;
MOV R8, R4 ?trans1;
ISETP.GE.U32.AND P2, PT, R23, R2, PT &req={0} ?WAIT13_END_GROUP;
IMAD R12, R8.reuse, R2.reuse, R23 &req={0} ?trans1;
ISETP.GE.U32.AND P3, PT, R8.reuse, R3, PT ?trans1;
IMAD R14, R8, R2, R5 ?WAIT3_END_GROUP;
SHF.R.S32.HI R13, RZ, 0x1f, R12 ?trans2;
SHF.R.S32.HI R15, RZ, 0x1f, R14 ?WAIT3_END_GROUP;
SEL.64 R12, R12, -0x1, !P3 ?trans2;
SEL.64 R14, R14, -0x1, !P3 ?trans2;
SEL.64 R12, R12, -0x1, !P2 ?trans2;
SEL.64 R14, R14, -0x1, !P0 ?WAIT3_END_GROUP;
LEA R20, P3, R12, R10.reuse, 0x3 ?trans2;
LEA R16, P4, R14, R10, 0x3 ?trans2;
LEA.HI.X R21, R12, R11.reuse, R13, 0x3, P3 ?trans2;
LEA.HI.X R17, R14, R11, R15, 0x3, P4 ?trans2;
LDG.E.64 R14, desc[UR8][R6.64] &wr=0x2 ?trans4;
LDG.E.64 R12, desc[UR8][R20.64] &wr=0x2 ?trans4;
LDG.E.64 R18, desc[UR8][R16.64] &wr=0x2 ?trans1;
IADD3 R8, PT, PT, R8, UR4, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P3, PT, R8, R3, PT ?trans1;
DFMA R12, -R12, R14, R18 &req={2} &wr=0x0 ?trans2;
STG.E.64 desc[UR8][R16.64], R12 &req={0} &rd=0x0 ?trans10;
@!P3 BRA 0x3c0 ?trans5;
BSYNC.RECONVERGENT B1 ?trans5;
@P1 BRA 0x6c0 ?trans5;
LDC R3, c[0x0][0x390] &wr=0x1 ?trans1;
ISETP.GE.U32.AND P0, PT, R5, R2, PT ?trans1;
MOV R8, R0 ?trans1;
ISETP.GE.U32.AND P1, PT, R3, R2, PT &req={1} ?WAIT13_END_GROUP;
IMAD R10, R8.reuse, R2.reuse, R3 &req={1} ?trans1;
ISETP.GE.U32.AND P2, PT, R8.reuse, R9, PT ?trans1;
IMAD R12, R8, R2, R5 &req={0} ?WAIT3_END_GROUP;
SHF.R.S32.HI R11, RZ, 0x1f, R10 ?trans2;
SHF.R.S32.HI R13, RZ, 0x1f, R12 ?WAIT3_END_GROUP;
SEL.64 R10, R10, -0x1, !P2 ?trans2;
SEL.64 R12, R12, -0x1, !P2 ?trans2;
SEL.64 R10, R10, -0x1, !P1 ?trans2;
SEL.64 R12, R12, -0x1, !P0 ?WAIT3_END_GROUP;
LEA R18, P2, R10, UR12, 0x3 ?trans2;
LEA R14, P3, R12, UR12, 0x3 ?trans2;
LEA.HI.X R19, R10, UR13, R11, 0x3, P2 ?trans2;
LEA.HI.X R15, R12, UR13, R13, 0x3, P3 ?trans2;
LDG.E.64 R12, desc[UR8][R6.64] &wr=0x2 ?trans4;
LDG.E.64 R10, desc[UR8][R18.64] &wr=0x2 ?trans4;
LDG.E.64 R16, desc[UR8][R14.64] &wr=0x2 ?trans1;
IADD3 R8, PT, PT, R8, UR4, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P2, PT, R8, R9, PT ?trans1;
DFMA R10, -R10, R12, R16 &req={2} &wr=0x0 ?trans2;
STG.E.64 desc[UR8][R14.64], R10 &req={0} &rd=0x1 ?trans10;
@!P2 BRA 0x570 ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
IADD3 R5, PT, PT, R5, UR5, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R5, R2, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x240 ?trans5;
EXIT ?trans5;
BRA 0x710;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: GaussFirst(double*, double*, unsigned int, unsigned int)
_Z10GaussFirstPdS_jj:
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, SIZE_N@rel32@lo+4
s_addc_u32 s3, s3, SIZE_N@rel32@hi+12
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, SIZE_M@rel32@lo+4
s_addc_u32 s5, s5, SIZE_M@rel32@hi+12
s_mov_b32 s18, 0x9abcaf48
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b32 s12, s[2:3], 0x0
s_load_b32 s13, s[4:5], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s19, 0x3e7ad7f2
s_waitcnt lgkmcnt(0)
s_cmp_gt_u32 s12, s8
s_mul_i32 s16, s12, s9
s_cselect_b32 s2, -1, 0
s_cmp_gt_u32 s13, s9
s_cselect_b32 s3, -1, 0
s_add_i32 s10, s16, s8
s_and_b32 s11, s2, s3
s_ashr_i32 s17, s10, 31
s_and_b32 s11, s11, exec_lo
s_cselect_b32 s11, s17, -1
s_cselect_b32 s10, s10, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[10:11], 3
s_add_u32 s10, s4, s10
s_addc_u32 s11, s5, s11
s_load_b64 s[10:11], s[10:11], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_ngt_f64_e64 s10, |s[10:11]|, s[18:19]
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB2_11
s_load_b32 s10, s[0:1], 0x24
s_add_u32 s0, s0, 24
s_addc_u32 s1, s1, 0
v_and_b32_e32 v1, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s17, s10, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s18, s14, s17
s_add_i32 s10, s18, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add3_u32 v6, v1, s10, 1
s_mov_b32 s10, exec_lo
v_cmpx_gt_u32_e64 s12, v6
s_cbranch_execz .LBB2_11
s_getpc_b64 s[10:11]
s_add_u32 s10, s10, SIZE_K@rel32@lo+4
s_addc_u32 s11, s11, SIZE_K@rel32@hi+12
v_bfe_u32 v0, v0, 10, 10
s_load_b32 s19, s[0:1], 0x0
s_load_b32 s14, s[10:11], 0x0
v_add_nc_u32_e32 v7, s18, v1
s_mov_b32 s10, 0x9abcaf48
s_mov_b32 s11, 0x3e7ad7f2
s_add_i32 s9, s9, 1
s_mov_b32 s18, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s17, s19, s17
.LBB2_3:
v_add_nc_u32_e32 v1, s16, v6
s_mov_b32 s19, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v1, -1, v1, s3
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 3, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b64 v[3:4], v[1:2], off
s_waitcnt vmcnt(0)
v_cmpx_gt_f64_e64 |v[3:4]|, s[10:11]
s_cbranch_execz .LBB2_10
s_clause 0x1
s_load_b32 s20, s[0:1], 0xc
s_load_b32 s21, s[0:1], 0x4
s_mov_b32 s22, exec_lo
s_waitcnt lgkmcnt(0)
s_lshr_b32 s20, s20, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, s15, s20, v[0:1]
s_mul_i32 s20, s21, s20
s_mul_i32 s21, s20, s12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v8, s9, v3
v_cmpx_gt_u32_e64 s13, v8
s_cbranch_execz .LBB2_7
v_mad_u64_u32 v[4:5], null, s12, v8, s[8:9]
s_mov_b32 s23, 0
.LBB2_6:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_add3_u32 v9, v7, v4, 1
v_cndmask_b32_e64 v11, -1, v4, s2
v_add_nc_u32_e32 v8, s20, v8
v_add_nc_u32_e32 v4, s21, v4
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[9:10], 3, v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[11:12], 3, v[11:12]
v_add_co_u32 v9, vcc_lo, s4, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
v_add_co_u32 v11, vcc_lo, s4, v11
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s13, v8
s_clause 0x2
global_load_b64 v[13:14], v[9:10], off
global_load_b64 v[11:12], v[11:12], off
global_load_b64 v[15:16], v[1:2], off
s_or_b32 s23, vcc_lo, s23
s_waitcnt vmcnt(0)
v_fma_f64 v[11:12], -v[11:12], v[15:16], v[13:14]
global_store_b64 v[9:10], v[11:12], off
s_and_not1_b32 exec_lo, exec_lo, s23
s_cbranch_execnz .LBB2_6
.LBB2_7:
s_or_b32 exec_lo, exec_lo, s22
v_cmp_gt_u32_e32 vcc_lo, s14, v3
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_10
v_mad_u64_u32 v[4:5], null, s12, v3, s[8:9]
s_mov_b32 s22, 0
.LBB2_9:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v8, -1, v4, s2
v_add3_u32 v10, v7, v4, 1
v_add_nc_u32_e32 v3, s20, v3
v_add_nc_u32_e32 v4, s21, v4
v_ashrrev_i32_e32 v9, 31, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[8:9], 3, v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[10:11], 3, v[10:11]
v_add_co_u32 v8, vcc_lo, s6, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
v_add_co_u32 v10, vcc_lo, s6, v10
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
global_load_b64 v[12:13], v[1:2], off
s_clause 0x1
global_load_b64 v[8:9], v[8:9], off
global_load_b64 v[14:15], v[10:11], off
v_cmp_le_u32_e32 vcc_lo, s14, v3
s_or_b32 s22, vcc_lo, s22
s_waitcnt vmcnt(0)
v_fma_f64 v[8:9], -v[8:9], v[12:13], v[14:15]
global_store_b64 v[10:11], v[8:9], off
s_and_not1_b32 exec_lo, exec_lo, s22
s_cbranch_execnz .LBB2_9
.LBB2_10:
s_or_b32 exec_lo, exec_lo, s19
v_add_nc_u32_e32 v6, s17, v6
v_add_nc_u32_e32 v7, s17, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_u32_e32 vcc_lo, s12, v6
s_or_b32 s18, vcc_lo, s18
s_and_not1_b32 exec_lo, exec_lo, s18
s_cbranch_execnz .LBB2_3
.LBB2_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| GaussFirst | 3,001 | 3,301 | stackv2-00000-of-00015 |
// Demangled: GaussSecond(double*, double*, unsigned int, unsigned int)
Function : _Z11GaussSecondPdS_jj
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x390] &wr=0x2 ?trans1;
IMAD R0, R0, UR5, R3 &req={1} ?WAIT5_END_GROUP;
LOP3.LUT R0, RZ, R0, RZ, 0x33, !PT ?WAIT4_END_GROUP;
IADD3 R7, PT, PT, R0, UR4, RZ &req={2} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R7, RZ, PT ?WAIT13_END_GROUP;
@!P0 EXIT &req={0} ?trans5;
S2R R0, SR_CTAID.Y &wr=0x0 ?trans1;
LDCU UR7, c[0x0][0x364] &wr=0x1 ?trans1;
S2R R3, SR_TID.Y &wr=0x0 ?trans1;
LDCU UR4, c[0x0][0x374] &wr=0x1 ?trans1;
LDCU UR6, c[0x0][0x370] &wr=0x2 ?trans1;
LDCU.64 UR8, c[0x0][0x358] &wr=0x3 ?trans1;
LDCU.64 UR10, c[0x0][0x388] &wr=0x4 ?trans1;
UIMAD UR4, UR7, UR4, URZ &req={1} ?trans1;
UIMAD UR5, UR5, UR6, URZ &req={2} ?trans1;
IMAD R0, R0, UR7, R3 &req={4,3,0} ?WAIT11_END_GROUP;
LDC R9, c[0x3][0x8] &req={0} &wr=0x0 ?trans1;
BSSY.RECONVERGENT B0, 0x3b0 ?trans1;
ISETP.GE.U32.AND P0, PT, R0, R9, PT &req={0} ?WAIT13_END_GROUP;
@P0 BRA 0x3a0 ?trans5;
LDC.64 R2, c[0x3][RZ] &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x380] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x390] &wr=0x2 ?trans1;
ISETP.GE.U32.AND P0, PT, R7, R2.reuse, PT &req={0} ?trans1;
IMAD R10, R5.reuse, R2, R7 &req={2} ?trans1;
ISETP.GE.U32.AND P1, PT, R5, R3, PT ?trans1;
MOV R3, R0 ?WAIT3_END_GROUP;
SHF.R.S32.HI R11, RZ, 0x1f, R10 ?WAIT5_END_GROUP;
SEL.64 R10, R10, -0x1, !P1 ?trans2;
ISETP.GE.U32.AND P1, PT, R4, R2, PT ?trans2;
SEL.64 R12, R10, -0x1, !P0 ?WAIT5_END_GROUP;
LEA R10, P2, R12, UR6, 0x3 &req={1} ?WAIT4_END_GROUP;
LEA.HI.X R11, R12, UR7, R13, 0x3, P2 ?WAIT9_END_GROUP;
IMAD R12, R3.reuse, R2.reuse, R4 &req={0} ?trans1;
ISETP.GE.U32.AND P2, PT, R3.reuse, R9, PT ?trans1;
IMAD R14, R3, R2, R7 ?WAIT3_END_GROUP;
SHF.R.S32.HI R13, RZ, 0x1f, R12 ?trans2;
SHF.R.S32.HI R15, RZ, 0x1f, R14 ?WAIT3_END_GROUP;
SEL.64 R12, R12, -0x1, !P2 ?trans2;
SEL.64 R14, R14, -0x1, !P2 ?trans2;
SEL.64 R12, R12, -0x1, !P1 ?trans2;
SEL.64 R14, R14, -0x1, !P0 ?WAIT3_END_GROUP;
LEA R20, P2, R12, UR10, 0x3 ?trans2;
LEA R16, P3, R14, UR10, 0x3 ?trans2;
LEA.HI.X R21, R12, UR11, R13, 0x3, P2 ?trans2;
LEA.HI.X R17, R14, UR11, R15, 0x3, P3 ?trans2;
LDG.E.64 R14, desc[UR8][R10.64] &wr=0x2 ?trans4;
LDG.E.64 R12, desc[UR8][R20.64] &wr=0x2 ?trans4;
LDG.E.64 R18, desc[UR8][R16.64] &wr=0x2 ?trans1;
IADD3 R3, PT, PT, R3, UR4, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P2, PT, R3, R9, PT ?trans1;
DFMA R12, -R12, R14, R18 &req={2} &wr=0x0 ?trans2;
STG.E.64 desc[UR8][R16.64], R12 &req={0} &rd=0x0 ?trans10;
@!P2 BRA 0x250 ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
IADD3 R7, PT, PT, R7, -UR5, RZ ?WAIT5_END_GROUP;
ISETP.GT.AND P0, PT, R7, -0x1, PT ?WAIT13_END_GROUP;
@P0 BRA 0x140 ?trans5;
EXIT ?trans5;
BRA 0x3f0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: GaussSecond(double*, double*, unsigned int, unsigned int)
_Z11GaussSecondPdS_jj:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[2:3], null, s14, s10, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_not_b32_e32 v4, v2
v_add_nc_u32_e32 v5, s2, v4
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e32 -1, v5
s_cbranch_execz .LBB3_6
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, SIZE_N@rel32@lo+4
s_addc_u32 s7, s7, SIZE_N@rel32@hi+12
v_bfe_u32 v2, v0, 10, 10
s_load_b32 s9, s[4:5], 0xc
s_load_b32 s8, s[6:7], 0x0
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, SIZE_K@rel32@lo+4
s_addc_u32 s7, s7, SIZE_K@rel32@hi+12
s_load_b64 s[12:13], s[4:5], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s11, s9, 16
s_cmp_gt_u32 s8, s2
v_mad_u64_u32 v[0:1], null, s15, s11, v[2:3]
s_cselect_b32 vcc_lo, -1, 0
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, SIZE_M@rel32@lo+4
s_addc_u32 s5, s5, SIZE_M@rel32@hi+12
s_load_b32 s9, s[6:7], 0x0
s_load_b32 s14, s[4:5], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
s_mul_i32 s11, s13, s11
v_mad_u64_u32 v[1:2], null, s8, v0, s[2:3]
s_mul_i32 s10, s12, s10
s_mul_i32 s12, s8, s3
s_waitcnt lgkmcnt(0)
v_cmp_gt_u32_e64 s0, s9, v0
s_cmp_gt_u32 s14, s3
s_mul_i32 s3, s11, s8
s_cselect_b32 s13, -1, 0
s_mov_b32 s14, 0
.LBB3_2:
s_and_saveexec_b32 s15, s0
s_cbranch_execz .LBB3_5
v_dual_mov_b32 v7, v0 :: v_dual_add_nc_u32 v2, s12, v5
v_cmp_gt_u32_e64 s1, s8, v5
v_mov_b32_e32 v6, v1
s_mov_b32 s16, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v3, 31, v2
s_and_b32 s2, s1, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v2, -1, v2, s2
v_cndmask_b32_e64 v3, -1, v3, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 3, v[2:3]
v_add_co_u32 v2, s2, s4, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s2, s5, v3, s2
.LBB3_4:
v_add_nc_u32_e32 v9, v4, v6
v_dual_cndmask_b32 v8, -1, v6 :: v_dual_add_nc_u32 v7, s11, v7
v_add_nc_u32_e32 v6, s3, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v10, -1, v9, s1
v_ashrrev_i32_e32 v9, 31, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[8:9], 3, v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[10:11], 3, v[10:11]
v_add_co_u32 v8, s2, s6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v9, s2, s7, v9, s2
v_add_co_u32 v10, s2, s6, v10
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v11, s2, s7, v11, s2
v_cmp_le_u32_e64 s2, s9, v7
global_load_b64 v[12:13], v[2:3], off
s_clause 0x1
global_load_b64 v[8:9], v[8:9], off
global_load_b64 v[14:15], v[10:11], off
s_or_b32 s16, s2, s16
s_waitcnt vmcnt(0)
v_fma_f64 v[8:9], -v[8:9], v[12:13], v[14:15]
global_store_b64 v[10:11], v[8:9], off
s_and_not1_b32 exec_lo, exec_lo, s16
s_cbranch_execnz .LBB3_4
.LBB3_5:
s_or_b32 exec_lo, exec_lo, s15
v_subrev_nc_u32_e32 v5, s10, v5
v_subrev_nc_u32_e32 v4, s10, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s1, 0, v5
s_or_b32 s14, s1, s14
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s14
s_cbranch_execnz .LBB3_2
.LBB3_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| GaussSecond | 1,680 | 2,049 | stackv2-00000-of-00015 |
// Demangled: Normalize(double*, double*, unsigned int, unsigned int)
Function : _Z9NormalizePdS_jj
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
LDCU.64 UR10, c[0x0][0x390] &wr=0x1 ?trans1;
LDCU.64 UR12, c[0x3][URZ] &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x380] &wr=0x2 ?trans1;
LDCU.64 UR8, c[0x0][0x358] &wr=0x3 ?trans1;
UIMAD UR4, UR12, UR11, UR10 &req={1} ?trans1;
UISETP.GE.U32.AND UP1, UPT, UR11, UR13, UPT ?trans1;
UISETP.GE.U32.AND UP0, UPT, UR10, UR12, UPT ?trans2;
USHF.R.S32.HI UR5, URZ, 0x1f, UR4 ?WAIT4_END_GROUP;
USEL.64 UR4, UR4, -0x1, !UP1 ?WAIT4_END_GROUP;
USEL.64 UR4, UR4, -0x1, !UP0 ?WAIT4_END_GROUP;
ULEA UR6, UP0, UR4, UR6, 0x3 &req={2} ?WAIT4_END_GROUP;
ULEA.HI.X UR4, UR4, UR7, UR5, 0x3, UP0 ?trans2;
MOV R4, UR6 ?WAIT4_END_GROUP;
MOV R5, UR4 ?WAIT5_END_GROUP;
LDG.E.64 R2, desc[UR8][R4.64] &req={3} &wr=0x2 ?trans1;
UMOV.64 UR4, 0x3e7ad7f29abcaf48 ?trans2;
DSETP.GT.AND P0, PT, |R2|, UR4, PT &req={2} &wr=0x1 ?trans2;
@!P0 EXIT &req={1,0} ?trans5;
S2R R0, SR_CTAID.X &wr=0x0 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x0 ?trans1;
BSSY.RECONVERGENT B0, 0x5d0 ?trans1;
S2R R3, SR_TID.X &wr=0x0 ?trans1;
LDCU UR6, c[0x0][0x390] &wr=0x1 ?trans1;
LDCU.64 UR14, c[0x0][0x380] &wr=0x2 ?trans1;
IMAD R0, R0, UR4, R3 &req={0} ?WAIT5_END_GROUP;
IADD3.X R25, PT, PT, R0, UR11, RZ, PT, !PT ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R25, UR13, PT ?WAIT13_END_GROUP;
@P0 BRA 0x5c0 &req={2,1} ?trans5;
LDC R24, c[0x0][0x370] &wr=0x0 ?trans8;
LDC.64 R6, c[0x3][RZ] &wr=0x1 ?trans1;
IMAD R24, R24, UR4, RZ &req={0} ?WAIT7_END_GROUP;
IMAD R2, R25.reuse, R6, UR6 &req={1,0} ?trans1;
ISETP.GE.U32.AND P0, PT, R25, R7, PT ?trans1;
LDG.E.64 R10, desc[UR8][R4.64] &wr=0x2 ?trans1;
ISETP.LE.U32.AND P1, PT, R6, UR6, PT ?trans2;
SHF.R.S32.HI R3, RZ, 0x1f, R2 ?WAIT5_END_GROUP;
SEL.64 R2, R2, -0x1, !P0 ?WAIT4_END_GROUP;
SEL.64 R2, R2, -0x1, !P1 ?WAIT5_END_GROUP;
LEA R8, P0, R2, UR14, 0x3 ?WAIT4_END_GROUP;
LEA.HI.X R9, R2, UR15, R3, 0x3, P0 ?WAIT5_END_GROUP;
LDG.E.64 R12, desc[UR8][R8.64] &wr=0x3 ?trans1;
MOV R2, 0x1 ?trans1;
IADD3 R25, PT, PT, R24, R25, RZ ?trans1;
BSSY.RECONVERGENT B1, 0x5a0 ?trans4;
ISETP.GE.U32.AND P1, PT, R25, R7, PT ?trans1;
MUFU.RCP64H R3, R11 &req={2} &wr=0x0 ?trans2;
DFMA R14, -R10, R2, 1 &req={0} &wr=0x0 ?trans1;
FSETP.GEU.AND P2, PT, |R13|, 6.5827683646048100446e-37, PT &req={3} ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R14, R14, R14, R14 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R14, R2, R14, R2 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, -R10, R14, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R14, R2, R14 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R14, R12, R2 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, -R10, R14, R12 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R2, R16, R14 &req={0} &wr=0x0 ?trans2;
FFMA R14, RZ, R11, R3 &req={0} ?WAIT5_END_GROUP;
FSETP.GT.AND P0, PT, |R14|, 1.469367938527859385e-39, PT ?WAIT13_END_GROUP;
@P0 BRA P2, 0x590 ?trans5;
MOV R26, 0x590 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0xa50 ?trans5;
BSYNC.RECONVERGENT B1 ?trans5;
STG.E.64 desc[UR8][R8.64], R2 &rd=0x0 ?trans1;
@!P1 BRA 0x200 ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
LDCU UR5, c[0x3][0x8] &wr=0x1 ?trans2;
ISETP.GE.U32.AND P0, PT, R0, UR5, PT &req={1} ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LDC R9, c[0x3][RZ] &req={0} &wr=0x0 ?trans1;
LDCU UR5, c[0x0][0x370] &wr=0x1 ?trans1;
LDCU UR10, c[0x0][0x390] &wr=0x2 ?trans1;
LDCU UR11, c[0x3][0x8] &wr=0x3 ?trans1;
LDCU.64 UR6, c[0x0][0x388] &wr=0x4 ?trans1;
UIMAD UR4, UR4, UR5, URZ &req={1} ?WAIT12_END_GROUP;
IMAD R2, R0.reuse, R9, UR10 &req={2,1,0} ?trans1;
ISETP.GE.U32.AND P0, PT, R0, UR11, PT &req={3} ?trans1;
LDG.E.64 R10, desc[UR8][R4.64] &wr=0x2 ?trans1;
ISETP.LE.U32.AND P1, PT, R9, UR10, PT ?trans2;
SHF.R.S32.HI R3, RZ, 0x1f, R2 ?WAIT5_END_GROUP;
SEL.64 R2, R2, -0x1, !P0 ?WAIT4_END_GROUP;
SEL.64 R2, R2, -0x1, !P1 ?WAIT5_END_GROUP;
LEA R6, P0, R2, UR6, 0x3 &req={4} ?WAIT4_END_GROUP;
LEA.HI.X R7, R2, UR7, R3, 0x3, P0 ?WAIT5_END_GROUP;
LDG.E.64 R16, desc[UR8][R6.64] &wr=0x3 ?trans1;
MOV R2, 0x1 ?trans1;
IADD3 R0, PT, PT, R0, UR4, RZ ?trans1;
BSSY.RECONVERGENT B0, 0xa20 ?trans4;
ISETP.GE.U32.AND P1, PT, R0, UR11, PT ?trans1;
MUFU.RCP64H R3, R11 &req={2} &wr=0x0 ?trans2;
DFMA R12, -R10, R2, 1 &req={0} &wr=0x0 ?trans1;
FSETP.GEU.AND P2, PT, |R17|, 6.5827683646048100446e-37, PT &req={3} ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, R12, R12, R12 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, R2, R12, R2 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, -R10, R12, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R12, R2, R12 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R12, R16, R2 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R14, -R10, R12, R16 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R2, R14, R12 &req={0} &wr=0x0 ?trans2;
FFMA R8, RZ, R11, R3 &req={0} ?WAIT5_END_GROUP;
FSETP.GT.AND P0, PT, |R8|, 1.469367938527859385e-39, PT ?WAIT13_END_GROUP;
@P0 BRA P2, 0xa10 ?trans5;
MOV R12, R16 ?trans1;
MOV R13, R17 ?trans1;
MOV R26, 0xa10 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0xa50 ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
STG.E.64 desc[UR8][R6.64], R2 &rd=0x1 ?trans1;
@!P1 BRA 0x660 ?trans5;
EXIT ?trans5;
FSETP.GEU.AND P3, PT, |R13|.reuse, 1.469367938527859385e-39, PT ?trans1;
LOP3.LUT R23, R13, 0x7ff00000, RZ, 0xc0, !PT ?trans1;
BSSY.RECONVERGENT B2, 0x1230 ?trans1;
LOP3.LUT R28, R11.reuse, 0x7ff00000, RZ, 0xc0, !PT ?trans1;
MOV R22, 0x1ca00000 ?trans1;
FSETP.GEU.AND P0, PT, |R11|.reuse, 1.469367938527859385e-39, PT ?trans1;
LOP3.LUT R2, R11, 0x800fffff, RZ, 0xc0, !PT ?trans2;
ISETP.GE.U32.AND P2, PT, R23, R28, PT ?trans1;
MOV R27, R23 ?trans1;
LOP3.LUT R3, R2, 0x3ff00000, RZ, 0xfc, !PT ?WAIT3_END_GROUP;
@!P3 LOP3.LUT R14, R11, 0x7ff00000, RZ, 0xc0, !PT ?trans1;
SEL R15, R22.reuse, 0x63400000, !P2 ?trans1;
@!P3 MOV R20, RZ ?trans1;
MOV R2, R10 ?trans2;
@!P3 ISETP.GE.U32.AND P4, PT, R23, R14, PT ?trans1;
MOV R14, R12 ?trans1;
LOP3.LUT R15, R15, 0x800fffff, R13, 0xf8, !PT ?trans1;
MOV R16, 0x1 ?trans2;
@!P3 SEL R21, R22, 0x63400000, !P4 ?trans1;
@!P0 DMUL R2, R10, 8.98846567431157953865e+307 &wr=0x0 ?trans2;
MUFU.RCP64H R17, R3 &req={0} &wr=0x0 ?trans1;
@!P0 LOP3.LUT R28, R3, 0x7ff00000, RZ, 0xc0, !PT ?WAIT2_END_GROUP;
@!P3 LOP3.LUT R21, R21, 0x80000000, R13, 0xf8, !PT ?trans2;
IADD3 R30, PT, PT, R28, -0x1, RZ ?trans2;
@!P3 LOP3.LUT R21, R21, 0x100000, RZ, 0xfc, !PT ?WAIT15_END_GROUP;
NOP ?WAIT10_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
@!P3 DFMA R14, R14, 2, -R20 &wr=0x1 ?trans2;
@!P3 LOP3.LUT R27, R15, 0x7ff00000, RZ, 0xc0, !PT &req={1} ?WAIT4_END_GROUP;
IADD3 R29, PT, PT, R27, -0x1, RZ ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R29, 0x7feffffe, PT ?WAIT5_END_GROUP;
ISETP.GT.U32.OR P0, PT, R30, 0x7feffffe, P0 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R16, -R2, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R18, R18, R18 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, R16, R18, R16 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R16, -R2, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, R16, R18, R16 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R18, R16, R14 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R20, R18, -R2, R14 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R20, R16, R20, R18 &req={0} &rd=0x0 &wr=0x1 ?trans2;
@P0 BRA 0x10e0 &req={1,0} ?trans5;
LOP3.LUT R16, R11, 0x7ff00000, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R12, PT, PT, R23.reuse, -R16.reuse, RZ ?trans1;
ISETP.GE.U32.AND P0, PT, R23, R16, PT ?WAIT4_END_GROUP;
VIMNMX.S32 R12, R12, -0x46a00000, !PT ?trans1;
SEL R13, R22, 0x63400000, !P0 ?WAIT4_END_GROUP;
VIMNMX.S32 R12, R12, 0x46a00000, PT ?WAIT5_END_GROUP;
IADD3 R18, PT, PT, -R13, R12, RZ ?trans1;
MOV R12, RZ ?WAIT3_END_GROUP;
IADD3 R13, PT, PT, R18, 0x7fe00000, RZ ?WAIT6_END_GROUP;
DMUL R16, R20, R12 &wr=0x0 ?trans2;
FSETP.GTU.AND P0, PT, |R17|, 1.469367938527859385e-39, PT &req={0} ?WAIT13_END_GROUP;
@P0 BRA 0x1220 ?trans5;
DFMA R2, R20, -R2, R14 &wr=0x0 ?trans1;
MOV R12, RZ ?trans1;
FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT &req={0} ?trans1;
LOP3.LUT R11, R3, 0x80000000, R11, 0x48, !PT ?WAIT4_END_GROUP;
LOP3.LUT R13, R11, R13, RZ, 0xfc, !PT ?WAIT8_END_GROUP;
@!P0 BRA 0x1220 ?trans5;
IADD3 R3, PT, PT, -R18, RZ, RZ ?trans1;
MOV R2, RZ ?trans1;
DMUL.RP R12, R20, R12 &wr=0x0 ?trans2;
LOP3.LUT R11, R13, R11, RZ, 0x3c, !PT &req={0} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R16, -R2, R20 &wr=0x0 ?trans2;
IADD3 R2, PT, PT, -R18, -0x43300000, RZ &req={0} ?WAIT5_END_GROUP;
FSETP.NEU.AND P0, PT, |R3|, R2, PT ?WAIT5_END_GROUP;
FSEL R16, R12, R16, !P0 ?trans1;
FSEL R17, R11, R17, !P0 ?trans1;
BRA 0x1220 ?trans6;
DSETP.NAN.AND P0, PT, R12, R12, PT &wr=0x0 ?trans2;
@P0 BRA 0x1200 &req={0} ?trans5;
DSETP.NAN.AND P0, PT, R10, R10, PT &wr=0x0 ?trans2;
@P0 BRA 0x11d0 &req={0} ?trans5;
ISETP.NE.AND P0, PT, R27, R28, PT ?trans1;
MOV.64 R16, 0xfff8000000000000 ?WAIT12_END_GROUP;
@!P0 BRA 0x1220 ?trans5;
ISETP.NE.AND P0, PT, R27, 0x7ff00000, PT ?trans1;
LOP3.LUT R17, R13, 0x80000000, R11, 0x48, !PT ?WAIT4_END_GROUP;
ISETP.EQ.OR P0, PT, R28, RZ, !P0 ?WAIT13_END_GROUP;
@P0 LOP3.LUT R2, R17, 0x7ff00000, RZ, 0xfc, !PT ?trans1;
@!P0 MOV R16, RZ ?trans1;
@P0 MOV R16, RZ ?WAIT3_END_GROUP;
@P0 MOV R17, R2 ?trans1;
BRA 0x1220 ?trans6;
LOP3.LUT R17, R11, 0x80000, RZ, 0xfc, !PT ?trans1;
MOV R16, R10 ?trans1;
BRA 0x1220 ?trans6;
LOP3.LUT R17, R13, 0x80000, RZ, 0xfc, !PT ?trans1;
MOV R16, R12 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
HFMA2 R27, -RZ, RZ, 0, 0 ?trans1;
MOV R2, R16 ?trans1;
MOV R3, R17 ?trans2;
RET.REL.NODEC R26 0x0 ?trans5;
BRA 0x1270;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: Normalize(double*, double*, unsigned int, unsigned int)
_Z9NormalizePdS_jj:
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, SIZE_N@rel32@lo+4
s_addc_u32 s3, s3, SIZE_N@rel32@hi+12
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, SIZE_M@rel32@lo+4
s_addc_u32 s5, s5, SIZE_M@rel32@hi+12
s_mov_b32 s18, 0x9abcaf48
s_load_b64 s[10:11], s[0:1], 0x10
s_load_b32 s3, s[2:3], 0x0
s_load_b32 s12, s[4:5], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s19, 0x3e7ad7f2
s_waitcnt lgkmcnt(0)
s_cmp_gt_u32 s3, s10
s_mul_i32 s8, s3, s11
s_cselect_b32 s2, -1, 0
s_cmp_gt_u32 s12, s11
s_cselect_b32 s9, -1, 0
s_add_i32 s8, s8, s10
s_and_b32 s9, s2, s9
s_ashr_i32 s13, s8, 31
s_and_b32 s9, s9, exec_lo
s_cselect_b32 s9, s13, -1
s_cselect_b32 s8, s8, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[8:9], 3
s_add_u32 s8, s4, s8
s_addc_u32 s9, s5, s9
s_load_b64 s[16:17], s[8:9], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_ngt_f64_e64 s13, |s[16:17]|, s[18:19]
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s13
s_cbranch_vccnz .LBB1_7
s_clause 0x1
s_load_b32 s13, s[0:1], 0x24
s_load_b32 s0, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s13, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s1, v[0:1]
s_mul_i32 s0, s0, s1
s_mul_i32 s1, s0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add3_u32 v0, s11, 1, v1
s_mov_b32 s11, exec_lo
v_cmpx_gt_u32_e64 s12, v0
s_cbranch_execz .LBB1_4
v_mad_u64_u32 v[2:3], null, s3, v0, s[10:11]
v_mov_b32_e32 v3, 0
s_mov_b32 s13, 0
.LBB1_3:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v4, -1, v2, s2
v_add_nc_u32_e32 v0, s0, v0
v_add_nc_u32_e32 v2, s1, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 3, v[4:5]
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_clause 0x1
global_load_b64 v[6:7], v3, s[8:9]
global_load_b64 v[8:9], v[4:5], off
s_waitcnt vmcnt(0)
v_div_scale_f64 v[10:11], null, v[6:7], v[6:7], v[8:9]
v_div_scale_f64 v[16:17], vcc_lo, v[8:9], v[6:7], v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[12:13], v[10:11]
s_waitcnt_depctr 0xfff
v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[14:15], v[16:17], v[12:13]
v_fma_f64 v[10:11], -v[10:11], v[14:15], v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[10:11], v[10:11], v[12:13], v[14:15]
v_cmp_le_u32_e32 vcc_lo, s12, v0
s_or_b32 s13, vcc_lo, s13
v_div_fixup_f64 v[6:7], v[10:11], v[6:7], v[8:9]
global_store_b64 v[4:5], v[6:7], off
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execnz .LBB1_3
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s11
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, SIZE_K@rel32@lo+4
s_addc_u32 s5, s5, SIZE_K@rel32@hi+12
s_load_b32 s4, s[4:5], 0x0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u32_e64 s4, v1
s_cbranch_execz .LBB1_7
v_mad_u64_u32 v[2:3], null, s3, v1, s[10:11]
v_mov_b32_e32 v0, 0
s_mov_b32 s3, 0
.LBB1_6:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v3, -1, v2, s2
v_add_nc_u32_e32 v1, s0, v1
v_add_nc_u32_e32 v2, s1, v2
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[3:4]
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b64 v[5:6], v0, s[8:9]
global_load_b64 v[7:8], v[3:4], off
s_waitcnt vmcnt(0)
v_div_scale_f64 v[9:10], null, v[5:6], v[5:6], v[7:8]
v_div_scale_f64 v[15:16], vcc_lo, v[7:8], v[5:6], v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[11:12], v[9:10]
s_waitcnt_depctr 0xfff
v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0
v_fma_f64 v[11:12], v[11:12], v[13:14], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0
v_fma_f64 v[11:12], v[11:12], v[13:14], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[13:14], v[15:16], v[11:12]
v_fma_f64 v[9:10], -v[9:10], v[13:14], v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[9:10], v[9:10], v[11:12], v[13:14]
v_cmp_le_u32_e32 vcc_lo, s4, v1
s_or_b32 s3, vcc_lo, s3
v_div_fixup_f64 v[5:6], v[9:10], v[5:6], v[7:8]
global_store_b64 v[3:4], v[5:6], off
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB1_6
.LBB1_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| Normalize | 6,277 | 2,958 | stackv2-00000-of-00015 |
// Demangled: SwapRows(double*, double*, unsigned int, unsigned int, unsigned int)
Function : _Z8SwapRowsPdS_jjj
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
BSSY.RECONVERGENT B0, 0x2b0 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x398] &wr=0x2 ?trans1;
LDCU UR8, c[0x3][0x4] &wr=0x3 ?trans1;
LDCU UR9, c[0x3][0x8] &wr=0x4 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x0 ?trans1;
LDCU.64 UR10, c[0x0][0x380] &wr=0x0 ?trans1;
IMAD R0, R0, UR4, R3 &req={1} ?WAIT5_END_GROUP;
IADD3 R2, PT, PT, R0.reuse, UR5, RZ &req={2} ?trans1;
ISETP.GE.U32.AND P0, PT, R0, UR9, PT &req={4} ?WAIT4_END_GROUP;
ISETP.GE.U32.AND P1, PT, R2, UR8, PT &req={3} ?WAIT13_END_GROUP;
@P1 BRA 0x2a0 &req={0} ?trans5;
LDC R13, c[0x3][RZ] &wr=0x0 ?trans1;
MOV R10, R2 ?WAIT7_END_GROUP;
LDC.64 R14, c[0x0][0x390] &wr=0x0 ?trans8;
LDC R11, c[0x0][0x370] &wr=0x1 ?trans1;
ISETP.GE.U32.AND P1, PT, R15, R13.reuse, PT &req={0} ?trans1;
ISETP.GE.U32.AND P2, PT, R14, R13, PT ?trans1;
IMAD R11, R11, UR4, RZ &req={1} ?WAIT12_END_GROUP;
IMAD R4, R10.reuse, R13.reuse, R15 &req={0} ?trans1;
ISETP.GE.U32.AND P3, PT, R10.reuse, UR8, PT ?trans1;
IMAD R2, R10, R13, R14 ?WAIT3_END_GROUP;
SHF.R.S32.HI R5, RZ, 0x1f, R4 ?trans2;
SHF.R.S32.HI R3, RZ, 0x1f, R2 ?WAIT3_END_GROUP;
SEL.64 R4, R4, -0x1, !P3 ?trans2;
SEL.64 R2, R2, -0x1, !P3 ?trans2;
SEL.64 R6, R4, -0x1, !P1 ?trans2;
SEL.64 R2, R2, -0x1, !P2 ?WAIT3_END_GROUP;
LEA R8, P4, R6, UR10, 0x3 ?trans2;
LEA R4, P3, R2, UR10, 0x3 ?trans2;
LEA.HI.X R9, R6, UR11, R7, 0x3, P4 ?trans2;
LEA.HI.X R5, R2, UR11, R3, 0x3, P3 ?WAIT3_END_GROUP;
LDG.E.64 R6, desc[UR6][R8.64] &wr=0x2 ?trans4;
LDG.E.64 R2, desc[UR6][R4.64] &wr=0x3 ?trans1;
IADD3 R10, PT, PT, R11, R10, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P3, PT, R10, UR8, PT ?trans1;
STG.E.64 desc[UR6][R4.64], R6 &req={2} &rd=0x0 ?trans4;
STG.E.64 desc[UR6][R8.64], R2 &req={3} &rd=0x0 ?trans8;
@!P3 BRA 0x160 ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
@P0 EXIT ?trans5;
LDC R11, c[0x3][RZ] &wr=0x1 ?trans1;
LDCU.64 UR12, c[0x0][0x390] &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x370] &wr=0x2 ?trans1;
LDCU.64 UR10, c[0x0][0x388] &wr=0x3 ?trans1;
UIMAD UR4, UR4, UR5, URZ &req={2} ?trans1;
ISETP.LE.U32.AND P0, PT, R11.reuse, UR13, PT &req={1} ?trans1;
ISETP.LE.U32.AND P1, PT, R11, UR12, PT &req={3} ?WAIT13_END_GROUP;
IMAD R4, R0.reuse, R11.reuse, UR13 &req={1,0} ?trans1;
ISETP.GE.U32.AND P2, PT, R0.reuse, UR9, PT ?trans1;
IMAD R2, R0, R11, UR12 ?WAIT3_END_GROUP;
SHF.R.S32.HI R5, RZ, 0x1f, R4 ?trans2;
SHF.R.S32.HI R3, RZ, 0x1f, R2 ?WAIT3_END_GROUP;
SEL.64 R4, R4, -0x1, !P2 ?trans2;
SEL.64 R2, R2, -0x1, !P2 ?trans2;
SEL.64 R6, R4, -0x1, !P0 ?trans2;
SEL.64 R2, R2, -0x1, !P1 ?WAIT3_END_GROUP;
LEA R8, P3, R6, UR10, 0x3 ?trans2;
LEA R4, P2, R2, UR10, 0x3 ?trans2;
LEA.HI.X R9, R6, UR11, R7, 0x3, P3 ?trans2;
LEA.HI.X R5, R2, UR11, R3, 0x3, P2 ?WAIT3_END_GROUP;
LDG.E.64 R6, desc[UR6][R8.64] &wr=0x2 ?trans4;
LDG.E.64 R2, desc[UR6][R4.64] &wr=0x3 ?trans1;
IADD3 R0, PT, PT, R0, UR4, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P2, PT, R0, UR9, PT ?trans1;
STG.E.64 desc[UR6][R4.64], R6 &req={2} &rd=0x1 ?trans4;
STG.E.64 desc[UR6][R8.64], R2 &req={3} &rd=0x1 ?trans8;
@!P2 BRA 0x330 ?trans5;
EXIT ?trans5;
BRA 0x480;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: SwapRows(double*, double*, unsigned int, unsigned int, unsigned int)
_Z8SwapRowsPdS_jjj:
s_clause 0x1
s_load_b32 s12, s[0:1], 0x2c
s_load_b256 s[4:11], s[0:1], 0x0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, SIZE_M@rel32@lo+4
s_addc_u32 s3, s3, SIZE_M@rel32@hi+12
s_load_b32 s3, s[2:3], 0x0
s_load_b32 s2, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s12, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
s_mul_i32 s2, s2, s0
v_add_nc_u32_e32 v0, s10, v1
s_mov_b32 s10, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB0_3
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, SIZE_N@rel32@lo+4
s_addc_u32 s1, s1, SIZE_N@rel32@hi+12
s_mov_b32 s12, 0
s_load_b32 s1, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v2, s1, v0
s_cmp_gt_u32 s1, s8
s_mul_i32 s11, s2, s1
s_cselect_b32 vcc_lo, -1, 0
s_cmp_gt_u32 s1, s9
s_cselect_b32 s0, -1, 0
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v3, s9, v2
v_add_nc_u32_e32 v4, s8, v2
v_add_nc_u32_e32 v0, s2, v0
v_add_nc_u32_e32 v2, s11, v2
v_cndmask_b32_e64 v3, -1, v3, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v5, -1, v4, vcc_lo
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[3:4], 3, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 3, v[5:6]
v_add_co_u32 v3, s1, s4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v4, s1, s5, v4, s1
v_add_co_u32 v5, s1, s4, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s1, s5, v6, s1
v_cmp_le_u32_e64 s1, s3, v0
s_clause 0x1
global_load_b64 v[7:8], v[3:4], off
global_load_b64 v[9:10], v[5:6], off
s_waitcnt vmcnt(1)
global_store_b64 v[5:6], v[7:8], off
s_waitcnt vmcnt(0)
global_store_b64 v[3:4], v[9:10], off
s_or_b32 s12, s1, s12
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s10
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, SIZE_K@rel32@lo+4
s_addc_u32 s1, s1, SIZE_K@rel32@hi+12
s_load_b32 s3, s[0:1], 0x0
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_6
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, SIZE_N@rel32@lo+4
s_addc_u32 s1, s1, SIZE_N@rel32@hi+12
s_mov_b32 s5, 0
s_load_b32 s1, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v0, s1, v1
s_cmp_gt_u32 s1, s8
s_mul_i32 s4, s2, s1
s_cselect_b32 vcc_lo, -1, 0
s_cmp_gt_u32 s1, s9
s_cselect_b32 s0, -1, 0
.LBB0_5:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v2, s9, v0
v_add_nc_u32_e32 v3, s8, v0
v_add_nc_u32_e32 v0, s4, v0
v_add_nc_u32_e32 v1, s2, v1
v_cndmask_b32_e64 v2, -1, v2, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, -1, v3, vcc_lo
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 3, v[4:5]
v_add_co_u32 v2, s1, s6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s1, s7, v3, s1
v_add_co_u32 v4, s1, s6, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s1, s7, v5, s1
v_cmp_le_u32_e64 s1, s3, v1
s_clause 0x1
global_load_b64 v[6:7], v[2:3], off
global_load_b64 v[8:9], v[4:5], off
s_waitcnt vmcnt(1)
global_store_b64 v[4:5], v[6:7], off
s_waitcnt vmcnt(0)
global_store_b64 v[2:3], v[8:9], off
s_or_b32 s5, s1, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_5
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| SwapRows | 1,935 | 2,194 | stackv2-00000-of-00015 |
// Demangled: broadcast_multi(float*, float*, float*, int*, int*, int*, int, int)
Function : _Z15broadcast_multiPfS_S_PiS0_S0_ii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x3b0] &wr=0x2 ?trans7;
LDC R15, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R0, R15, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R12, c[0x0][0x390] &wr=0x0 ?trans1;
LDCU UR4, c[0x0][0x370] &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x2 ?trans6;
LDC.64 R8, c[0x0][0x380] &wr=0x3 ?trans8;
LDC.64 R10, c[0x0][0x388] &wr=0x4 ?trans1;
IMAD R15, R15, UR4, RZ &req={1} ?WAIT7_END_GROUP;
IMAD.WIDE R2, R0, 0x4, R8 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE R4, R0.reuse, 0x4, R10 &req={4} ?trans2;
LDG.E R2, desc[UR6][R2.64] &req={2} &wr=0x2 ?trans4;
LDG.E R5, desc[UR6][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE R6, R0, 0x4, R12 &req={1,0} ?trans1;
IADD3 R0, PT, PT, R15, R0, RZ ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, UR5, PT ?trans1;
FADD R17, R2, R5 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R17 &rd=0x1 ?trans7;
@!P0 BRA 0xe0 ?trans5;
EXIT ?trans5;
BRA 0x190;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: broadcast_multi(float*, float*, float*, int*, int*, int*, int, int)
_Z15broadcast_multiPfS_S_PiS0_S0_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x44
s_load_b32 s8, s[0:1], 0x30
s_add_u32 s2, s0, 56
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_3
s_load_b32 s10, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s10, s9
s_mov_b32 s9, 0
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, s0, s2, v2
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_nc_u32_e32 v1, s1, v1
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s8, v1
global_store_b32 v[2:3], v0, off
s_or_b32 s9, vcc_lo, s9
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| broadcast_multi | 709 | 765 | stackv2-00000-of-00015 |
// Demangled: matrix_Add(int (*) [32], int (*) [32], int (*) [32])
Function : _Z10matrix_AddPA32_iS0_S0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R9, SR_CTAID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
S2R R11, SR_TID.X &wr=0x2 ?trans6;
LDC.64 R4, c[0x0][0x388] &wr=0x3 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x4 ?trans1;
IMAD.WIDE.U32 R2, R9, 0x80, R2 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R9, 0x80, R4 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R2, R11.reuse, 0x4, R2 &req={2} ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans3;
IMAD.WIDE.U32 R4, R11, 0x4, R4 ?WAIT3_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans4;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R6, R9, 0x80, R6 &req={4} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R6, R11, 0x4, R6 ?trans1;
IADD3 R9, PT, PT, R2, R5, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x130;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: matrix_Add(int (*) [32], int (*) [32], int (*) [32])
_Z10matrix_AddPA32_iS0_S0_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
v_lshlrev_b32_e32 v0, 2, v0
s_lshl_b64 s[2:3], s[2:3], 7
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| matrix_Add | 565 | 352 | stackv2-00000-of-00015 |
// Demangled: compMatches(char*, char*, int, int, int, int*)
Function : _Z11compMatchesPcS_iiiPi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R18, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR36, c[0x0][0x358] &wr=0x2 ?trans1;
MOV R2, 0x0 ?trans1;
LDCU UR6, c[0x0][0x394] &wr=0x3 ?trans5;
LDC R3, c[0x0][0x360] &wr=0x1 ?trans8;
LDC.64 R16, c[0x0][0x3a0] &wr=0x4 ?trans1;
IMAD R18, R3, UR4, R18 &req={1} ?trans1;
UMOV.64 UR4, 0x4 ?WAIT6_END_GROUP;
LDC.64 R2, c[0x4][R2] &wr=0x1 ?trans1;
UIMAD.WIDE UR4, UR6, 0x4, UR4 &req={3} ?trans1;
IMAD.WIDE R16, R18, 0x4, R16 &req={4} ?WAIT5_END_GROUP;
MOV.64 R6, UR4 ?trans2;
MOV.64 R4, UR4 ?trans2;
STG.E desc[UR36][R16.64], RZ &req={2} &rd=0x2 ?trans2;
MOV R5, R7 &req={0} ?WAIT7_END_GROUP;
LEPC R20, 0x130 ?WAIT7_END_GROUP;
CALL.ABS.NOINC R2 &req={2,1} ?trans5;
LDC R3, c[0x0][0x390] &wr=0x0 ?trans2;
ISETP.GE.AND P0, PT, R18, R3, PT &req={0} ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
IADD3 R0, PT, PT, -R18, R3, RZ ?WAIT7_END_GROUP;
LDC.64 R2, c[0x0][0x390] &wr=0x0 ?trans1;
BSSY.RECONVERGENT B0, 0x1420 ?trans1;
IADD3 R2, PT, PT, -R18, R2, RZ &req={0} ?WAIT5_END_GROUP;
VIMNMX.S32 R15, R2, R3, PT ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R15, RZ, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x1410 ?trans5;
VIMNMX.S32 R2, R0, R3, PT ?trans1;
BSSY.RECONVERGENT B1, 0x500 ?trans1;
HFMA2 R7, -RZ, RZ, 0, 5.9604644775390625e-08 ?WAIT3_END_GROUP;
IADD3 R2, PT, PT, R2, 0x1, RZ ?WAIT5_END_GROUP;
VIMNMX.U32 R14, R2, 0x2, !PT ?WAIT5_END_GROUP;
IADD3 R2, PT, PT, R14.reuse, -0x2, RZ ?trans2;
IADD3 R20, PT, PT, R14, -0x1, RZ ?WAIT3_END_GROUP;
ISETP.GE.U32.AND P0, PT, R2, 0xf, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x4f0 ?trans5;
IADD.64 R2, R4, 0x20 ?trans2;
BSSY.RECONVERGENT B2, 0x4e0 ?trans1;
LOP3.LUT R6, R20, 0xfffffff0, RZ, 0xc0, !PT ?trans1;
MOV R7, RZ ?WAIT7_END_GROUP;
IADD3 R9, PT, PT, R7.reuse, 0x1, RZ ?trans2;
IADD3 R11, PT, PT, R7.reuse, 0x2, RZ ?trans2;
IADD3 R13, PT, PT, R7.reuse, 0x3, RZ ?trans2;
IADD3 R19, PT, PT, R7.reuse, 0x4, RZ ?trans2;
IADD3 R21, PT, PT, R7.reuse, 0x5, RZ ?trans1;
ST.E desc[UR36][R2.64+-0x1c], R9 &rd=0x0 ?trans1;
IADD3 R23, PT, PT, R7, 0x6, RZ ?WAIT2_END_GROUP;
IADD3 R25, PT, PT, R7.reuse, 0x7, RZ ?trans2;
IADD3 R27, PT, PT, R7.reuse, 0x8, RZ ?trans1;
ST.E desc[UR36][R2.64+-0x18], R11 &rd=0x1 ?trans1;
IADD3 R29, PT, PT, R7.reuse, 0xa, RZ ?trans2;
IADD3 R31, PT, PT, R7.reuse, 0xb, RZ ?trans1;
ST.E desc[UR36][R2.64+-0x14], R13 &rd=0x2 ?trans4;
ST.E desc[UR36][R2.64+-0x10], R19 &rd=0x3 ?trans1;
IADD3 R9, PT, PT, R7, 0x9, RZ &req={0} ?WAIT3_END_GROUP;
ST.E desc[UR36][R2.64+-0xc], R21 &rd=0x0 ?trans1;
IADD3 R11, PT, PT, R7.reuse, 0xc, RZ &req={1} ?trans2;
IADD3 R13, PT, PT, R7.reuse, 0xd, RZ &req={2} ?trans1;
ST.E desc[UR36][R2.64+-0x8], R23 ?trans1;
IADD3 R19, PT, PT, R7, 0xe, RZ &req={3} ?WAIT3_END_GROUP;
ST.E desc[UR36][R2.64+-0x4], R25 ?trans1;
IADD3 R21, PT, PT, R7.reuse, 0xf, RZ &req={0} ?trans2;
IADD3 R7, PT, PT, R7, 0x10, RZ ?trans1;
ST.E desc[UR36][R2.64], R27 ?trans4;
ISETP.NE.AND P0, PT, R7, R6, PT ?trans1;
ST.E desc[UR36][R2.64+0x4], R9 ?trans4;
ST.E desc[UR36][R2.64+0x8], R29 ?trans4;
ST.E desc[UR36][R2.64+0xc], R31 ?trans4;
ST.E desc[UR36][R2.64+0x10], R11 ?trans4;
ST.E desc[UR36][R2.64+0x14], R13 ?trans4;
ST.E desc[UR36][R2.64+0x18], R19 ?trans4;
ST.E desc[UR36][R2.64+0x1c], R21 ?trans4;
ST.E desc[UR36][R2.64+0x20], R7 &rd=0x0 ?trans2;
IADD.64 R2, R2, 0x40 &req={0} ?WAIT2_END_GROUP;
@P0 BRA 0x2a0 ?trans6;
BSYNC.RECONVERGENT B2 ?trans5;
IADD3 R7, PT, PT, R7, 0x1, RZ ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B1 ?trans5;
LOP3.LUT P0, RZ, R20, 0xf, RZ, 0xc0, !PT ?trans1;
BSSY.RECONVERGENT B1, 0x8a0 ?WAIT12_END_GROUP;
@!P0 BRA 0x890 ?trans5;
IADD3 R3, PT, PT, R14, 0xf, RZ ?trans1;
BSSY.RECONVERGENT B2, 0x6c0 ?trans3;
LOP3.LUT R2, R3.reuse, 0xf, RZ, 0xc0, !PT ?trans2;
LOP3.LUT P1, RZ, R3, 0x7, RZ, 0xc0, !PT ?trans2;
IADD3 R2, PT, PT, R2, -0x1, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R2, 0x7, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x6b0 ?trans5;
IADD3 R9, PT, PT, R7.reuse, 0x1, RZ ?trans1;
IMAD.WIDE.U32 R2, R7.reuse, 0x4, R4 ?trans1;
IADD3 R11, PT, PT, R7.reuse, 0x2, RZ ?trans2;
IADD3 R13, PT, PT, R7.reuse, 0x3, RZ ?trans2;
IADD3 R19, PT, PT, R7.reuse, 0x4, RZ ?trans2;
IADD3 R21, PT, PT, R7.reuse, 0x5, RZ ?trans2;
IADD3 R23, PT, PT, R7, 0x6, RZ ?WAIT2_END_GROUP;
IADD3 R25, PT, PT, R7.reuse, 0x7, RZ ?trans1;
ST.E desc[UR36][R2.64+0x4], R9 ?trans4;
ST.E desc[UR36][R2.64+0x8], R11 ?trans4;
ST.E desc[UR36][R2.64+0xc], R13 ?trans4;
ST.E desc[UR36][R2.64+0x10], R19 ?trans4;
ST.E desc[UR36][R2.64+0x14], R21 ?trans4;
ST.E desc[UR36][R2.64+0x18], R23 ?trans4;
ST.E desc[UR36][R2.64+0x1c], R25 ?trans4;
ST.E desc[UR36][R2.64], R7 &rd=0x0 ?trans2;
IADD3 R7, PT, PT, R7, 0x8, RZ &req={0} ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
@!P1 BRA 0x890 ?trans5;
IADD3 R2, PT, PT, R14, 0x7, RZ ?trans1;
BSSY.RECONVERGENT B2, 0x7f0 ?trans3;
LOP3.LUT R3, R2.reuse, 0x7, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R6, R2, 0x3, RZ, 0xc0, !PT ?trans2;
IADD3 R3, PT, PT, R3, -0x1, RZ ?WAIT3_END_GROUP;
ISETP.NE.AND P1, PT, R6, RZ, PT ?trans2;
ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x7e0 ?trans5;
IADD3 R9, PT, PT, R7.reuse, 0x1, RZ ?trans1;
IMAD.WIDE.U32 R2, R7.reuse, 0x4, R4 ?trans1;
IADD3 R11, PT, PT, R7.reuse, 0x2, RZ ?trans2;
IADD3 R13, PT, PT, R7.reuse, 0x3, RZ ?trans2;
ST.E desc[UR36][R2.64+0x4], R9 ?trans4;
ST.E desc[UR36][R2.64+0x8], R11 ?trans4;
ST.E desc[UR36][R2.64+0xc], R13 ?trans4;
ST.E desc[UR36][R2.64], R7 &rd=0x0 ?trans2;
IADD3 R7, PT, PT, R7, 0x4, RZ &req={0} ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
@!P1 BRA 0x890 ?trans5;
IMAD.WIDE.U32 R2, R7, 0x4, R4 ?trans1;
ISETP.NE.AND P0, PT, R6, 0x1, PT ?WAIT4_END_GROUP;
ST.E desc[UR36][R2.64], R7 &rd=0x0 ?trans9;
@!P0 BRA 0x890 ?trans5;
ISETP.NE.AND P0, PT, R6, 0x2, PT ?trans1;
IADD3 R9, PT, PT, R7, 0x1, RZ ?WAIT5_END_GROUP;
ST.E desc[UR36][R2.64+0x4], R9 &rd=0x1 ?trans7;
@P0 IADD3 R7, PT, PT, R7, 0x2, RZ &req={0} ?WAIT5_END_GROUP;
@P0 ST.E desc[UR36][R2.64+0x8], R7 &rd=0x1 ?trans2;
BSYNC.RECONVERGENT B1 ?trans5;
LOP3.LUT R20, R20, 0xfffffffc, RZ, 0xc0, !PT ?trans2;
SHF.R.S32.HI R19, RZ, 0x1f, R18 ?trans1;
MOV R21, 0x1 ?WAIT7_END_GROUP;
LDCU.64 UR4, c[0x0][0x388] &wr=0x2 ?trans1;
IADD3 R2, PT, PT, R14.reuse, -0x2, RZ &req={1,0} ?trans1;
ST.E desc[UR36][R4.64], R21 &rd=0x0 ?trans1;
IADD3 R24, PT, PT, R21, -0x1, RZ ?trans1;
HFMA2 R25, -RZ, RZ, 0, 0 ?trans1;
IADD3 R22, PT, PT, R14, -0x1, RZ ?trans1;
ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ?trans1;
BSSY.RECONVERGENT B1, 0xf90 ?trans1;
MOV R23, 0x1 ?trans1;
IADD.64 R2, R18, R24 ?trans2;
MOV R27, R21 ?trans1;
LOP3.LUT P0, RZ, R22, 0x3, RZ, 0xc0, !PT ?trans1;
IADD.64 R2, R2, UR4 &req={2} ?WAIT6_END_GROUP;
@!P1 BRA 0xf80 &req={0} ?trans6;
MOV R25, RZ ?trans1;
MOV R23, 0x1 ?trans1;
MOV R27, R21 ?WAIT7_END_GROUP;
IMAD.WIDE.U32 R6, R23.reuse, 0x4, R4 ?trans1;
LDCU.64 UR4, c[0x0][0x380] &wr=0x0 ?trans1;
IADD3 R10, PT, PT, R23, -0x1, RZ ?trans2;
HFMA2 R11, -RZ, RZ, 0, 0 ?trans1;
LDG.E.U8 R29, desc[UR36][R2.64] &wr=0x2 ?trans4;
LD.E R28, desc[UR36][R6.64] &wr=0x3 ?trans4;
LD.E R26, desc[UR36][R6.64+0x4] &wr=0x4 ?trans1;
ISETP.GE.AND P1, PT, R28, R27, PT &req={3} ?WAIT13_END_GROUP;
@!P1 MOV.64 R8, UR4 &req={0} ?WAIT4_END_GROUP;
@!P1 IADD.64 R12, R10, R8 ?trans2;
@P1 MOV.64 R8, UR4 ?WAIT4_END_GROUP;
@P1 IADD.64 R10, R10, R8 ?trans2;
@!P1 LDG.E.U8 R12, desc[UR36][R12.64] &rd=0x0 &wr=0x2 ?trans5;
@P1 LDG.E.U8 R10, desc[UR36][R10.64] &wr=0x3 ?trans1;
IADD3 R32, PT, PT, R24, 0x1, RZ ?WAIT5_END_GROUP;
@!P1 MOV R30, R32 ?trans1;
HFMA2 R13, -RZ, RZ, 0, 0 &req={0} ?trans1;
ISETP.NE.OR P3, PT, R12, R29.reuse, P1 &req={2} ?trans1;
ISETP.NE.OR P2, PT, R10, R29, !P1 &req={3} ?trans1;
IADD3 R29, PT, PT, R28, 0x1, RZ ?trans2;
@P1 IADD3 R10, PT, PT, R27, 0x1, RZ ?trans1;
MOV R12, R23 ?trans1;
LD.E R27, desc[UR36][R6.64+0x8] &wr=0x2 ?trans7;
@!P3 IADD3 R30, PT, PT, R24, RZ, RZ ?WAIT2_END_GROUP;
@!P2 IADD3 R32, PT, PT, R24, RZ, RZ ?WAIT3_END_GROUP;
@!P1 VIMNMX.U32 R31, R29, R30, PT ?trans2;
@P1 VIMNMX.U32 R31, R10, R32, PT ?WAIT5_END_GROUP;
ISETP.GE.AND P1, PT, R26, R31, PT &req={4} ?trans1;
ST.E desc[UR36][R6.64], R31 &rd=0x0 ?WAIT12_END_GROUP;
@P1 IADD.64 R10, R12.reuse, R8.reuse ?trans2;
@!P1 IADD.64 R12, R12, R8 ?trans2;
@P1 LDG.E.U8 R33, desc[UR36][R2.64] &wr=0x3 ?trans4;
@P1 LDG.E.U8 R10, desc[UR36][R10.64] &wr=0x3 ?trans4;
@!P1 LDG.E.U8 R12, desc[UR36][R12.64] &rd=0x1 &wr=0x4 ?trans4;
@!P1 LDG.E.U8 R35, desc[UR36][R2.64] &wr=0x4 ?trans1;
@P1 MOV R24, R29.reuse ?trans1;
@!P1 MOV R30, R29 ?trans1;
@P1 IADD3 R31, PT, PT, R31, 0x1, RZ &req={0} ?WAIT2_END_GROUP;
IADD3 R29, PT, PT, R26, 0x1, RZ ?trans1;
HFMA2 R13, -RZ, RZ, 0, 0 &req={1} ?trans1;
ISETP.NE.OR P3, PT, R10, R33, !P1 &req={3} ?trans1;
ISETP.NE.OR P2, PT, R12, R35, P1 &req={4} ?WAIT12_END_GROUP;
@!P3 IADD3 R24, PT, PT, R28.reuse, RZ, RZ ?trans2;
@!P2 IADD3 R30, PT, PT, R28, RZ, RZ ?WAIT3_END_GROUP;
@P1 VIMNMX.U32 R28, R31, R24, PT ?trans1;
IADD3 R12, PT, PT, R23, 0x1, RZ ?trans1;
LD.E R24, desc[UR36][R6.64+0xc] &wr=0x3 ?trans1;
@!P1 VIMNMX.U32 R28, R29, R30, PT ?WAIT5_END_GROUP;
ISETP.GE.AND P1, PT, R27, R28, PT &req={2} ?trans1;
ST.E desc[UR36][R6.64+0x4], R28 &rd=0x0 ?WAIT12_END_GROUP;
@P1 IADD.64 R10, R12.reuse, R8.reuse ?trans2;
@!P1 IADD.64 R12, R12, R8 ?trans2;
@P1 LDG.E.U8 R31, desc[UR36][R2.64] &wr=0x2 ?trans4;
@P1 LDG.E.U8 R10, desc[UR36][R10.64] &rd=0x1 &wr=0x2 ?trans4;
@!P1 LDG.E.U8 R12, desc[UR36][R12.64] &wr=0x4 ?trans4;
@!P1 LDG.E.U8 R33, desc[UR36][R2.64] &wr=0x4 ?trans1;
@P1 MOV R30, R29 ?trans1;
@P1 IADD3 R28, PT, PT, R28, 0x1, RZ &req={0} ?trans1;
HFMA2 R11, -RZ, RZ, 0, 0 &req={1} ?trans1;
ISETP.NE.OR P3, PT, R10, R31, !P1 &req={2} ?trans1;
ISETP.NE.OR P2, PT, R12, R33, P1 &req={4} ?trans1;
@!P1 MOV R31, R29 ?WAIT11_END_GROUP;
@!P3 IADD3 R30, PT, PT, R26.reuse, RZ, RZ ?trans2;
@!P2 IADD3 R31, PT, PT, R26, RZ, RZ ?trans2;
IADD3 R26, PT, PT, R27, 0x1, RZ ?trans1;
@P1 VIMNMX.U32 R29, R28, R30, PT ?WAIT4_END_GROUP;
@!P1 VIMNMX.U32 R29, R26, R31, PT ?WAIT5_END_GROUP;
ISETP.GE.AND P1, PT, R24, R29, PT &req={3} ?trans1;
IADD3 R10, PT, PT, R23, 0x2, RZ ?trans1;
ST.E desc[UR36][R6.64+0x8], R29 &rd=0x0 ?trans11;
@P1 IADD.64 R12, R10, R8 ?WAIT2_END_GROUP;
@!P1 IADD.64 R8, R10, R8 ?trans2;
@P1 LDG.E.U8 R11, desc[UR36][R2.64] &wr=0x2 ?trans4;
@P1 LDG.E.U8 R12, desc[UR36][R12.64] &wr=0x2 ?trans4;
@!P1 LDG.E.U8 R8, desc[UR36][R8.64] &wr=0x3 ?trans4;
@!P1 LDG.E.U8 R31, desc[UR36][R2.64] &wr=0x3 ?trans1;
@!P1 MOV R28, R26 ?trans1;
@P1 IADD3 R10, PT, PT, R29, 0x1, RZ ?WAIT2_END_GROUP;
IADD3 R25, PT, PT, R25, 0x4, RZ ?trans2;
IADD3 R23, PT, PT, R23, 0x4, RZ ?trans1;
ISETP.NE.OR P3, PT, R12, R11, !P1 &req={2} ?trans1;
ISETP.NE.OR P2, PT, R8, R31, P1 &req={3} ?trans1;
@!P1 IADD3 R11, PT, PT, R24, 0x1, RZ ?WAIT11_END_GROUP;
@!P3 IADD3 R26, PT, PT, R27.reuse, RZ, RZ ?trans2;
@!P2 IADD3 R28, PT, PT, R27, RZ, RZ ?WAIT3_END_GROUP;
@P1 VIMNMX.U32 R27, R10, R26, PT ?trans2;
@!P1 VIMNMX.U32 R27, R11, R28, PT ?WAIT5_END_GROUP;
ST.E desc[UR36][R6.64+0xc], R27 &rd=0x0 ?trans1;
ISETP.NE.AND P1, PT, R25, R20, PT ?WAIT13_END_GROUP;
@P1 BRA 0x9e0 &req={0} ?trans5;
BSYNC.RECONVERGENT B1 ?trans5;
BSSY.RECONVERGENT B1, 0x13e0 ?trans4;
@!P0 BRA 0x13d0 ?trans5;
IMAD.WIDE.U32 R8, R23.reuse, 0x4, R4 ?trans1;
LDCU.64 UR4, c[0x0][0x380] &wr=0x0 ?trans1;
IADD3 R10, PT, PT, R23, -0x1, RZ ?trans2;
HFMA2 R11, -RZ, RZ, 0, 0 ?trans1;
LDG.E.U8 R25, desc[UR36][R2.64] &wr=0x2 ?trans4;
LD.E R26, desc[UR36][R8.64] &wr=0x3 ?trans2;
ISETP.GE.AND P0, PT, R26, R27, PT &req={3} ?WAIT13_END_GROUP;
@P0 MOV.64 R6, UR4 &req={0} ?WAIT4_END_GROUP;
@P0 IADD.64 R12, R10, R6 ?trans2;
@!P0 MOV.64 R6, UR4 ?WAIT4_END_GROUP;
@!P0 IADD.64 R10, R10, R6 ?trans2;
@P0 LDG.E.U8 R12, desc[UR36][R12.64] &wr=0x2 ?trans5;
@!P0 LDG.E.U8 R10, desc[UR36][R10.64] &rd=0x0 &wr=0x3 ?trans1;
IADD3 R29, PT, PT, R24, 0x1, RZ ?WAIT5_END_GROUP;
@P0 MOV R28, R29 ?trans1;
LOP3.LUT R11, R22, 0x3, RZ, 0xc0, !PT &req={0} ?trans1;
ISETP.NE.OR P2, PT, R12, R25.reuse, !P0 &req={2} ?trans1;
ISETP.NE.OR P1, PT, R10, R25, P0 &req={3} ?trans1;
@P0 IADD3 R25, PT, PT, R27, 0x1, RZ ?trans2;
@!P0 IADD3 R12, PT, PT, R26, 0x1, RZ ?WAIT9_END_GROUP;
@!P2 IADD3 R28, PT, PT, R24.reuse, RZ, RZ ?trans2;
@!P1 IADD3 R29, PT, PT, R24, RZ, RZ ?WAIT3_END_GROUP;
@P0 VIMNMX.U32 R25, R25, R28, PT ?trans2;
@!P0 VIMNMX.U32 R25, R12, R29, PT ?WAIT5_END_GROUP;
ST.E desc[UR36][R8.64], R25 &rd=0x0 ?trans1;
ISETP.NE.AND P0, PT, R11, 0x1, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x13d0 &req={0} ?trans5;
IADD3 R10, PT, PT, R23, 0x1, RZ ?trans1;
MOV R22, R23 ?trans1;
MOV R23, RZ ?trans1;
LDG.E.U8 R27, desc[UR36][R2.64] &wr=0x2 ?trans2;
IMAD.WIDE.U32 R12, R10, 0x4, R4 ?trans2;
IADD.64 R22, R22, R6 ?WAIT3_END_GROUP;
LD.E R24, desc[UR36][R12.64] &wr=0x3 ?trans4;
LDG.E.U8 R22, desc[UR36][R22.64] &wr=0x2 ?trans1;
IADD3 R28, PT, PT, R26, 0x1, RZ ?trans1;
ISETP.GE.AND P0, PT, R24, R25, PT &req={3} ?WAIT5_END_GROUP;
ISETP.NE.OR P2, PT, R22.reuse, R27.reuse, !P0 &req={2} ?trans1;
ISETP.NE.OR P1, PT, R22, R27, P0 ?WAIT7_END_GROUP;
@P0 MOV R27, R28 ?trans1;
@P0 IADD3 R25, PT, PT, R25, 0x1, RZ ?trans2;
@!P0 IADD3 R22, PT, PT, R24, 0x1, RZ ?trans2;
@!P2 IADD3 R27, PT, PT, R26.reuse, RZ, RZ ?trans2;
@!P1 IADD3 R28, PT, PT, R26, RZ, RZ ?WAIT3_END_GROUP;
@P0 VIMNMX.U32 R25, R25, R27, PT ?trans2;
@!P0 VIMNMX.U32 R25, R22, R28, PT ?WAIT5_END_GROUP;
ST.E desc[UR36][R12.64], R25 &rd=0x0 ?trans1;
ISETP.NE.AND P0, PT, R11, 0x2, PT ?trans1;
MOV R11, RZ ?WAIT12_END_GROUP;
@!P0 BRA 0x13d0 &req={0} ?trans5;
IADD.64 R6, R10, R6 ?trans2;
LD.E R12, desc[UR36][R8.64+0x8] &wr=0x2 ?trans4;
LDG.E.U8 R3, desc[UR36][R2.64] &wr=0x3 ?trans4;
LDG.E.U8 R6, desc[UR36][R6.64] &wr=0x3 ?trans1;
IADD3 R10, PT, PT, R24, 0x1, RZ ?trans1;
ISETP.GE.AND P0, PT, R12, R25, PT &req={2} ?WAIT5_END_GROUP;
ISETP.NE.OR P2, PT, R6.reuse, R3.reuse, !P0 &req={3} ?trans1;
ISETP.NE.OR P1, PT, R6, R3, P0 ?WAIT7_END_GROUP;
@!P0 MOV R11, R10 ?trans1;
@P0 IADD3 R25, PT, PT, R25, 0x1, RZ ?trans2;
@!P0 IADD3 R2, PT, PT, R12, 0x1, RZ ?trans2;
@!P2 IADD3 R10, PT, PT, R24.reuse, RZ, RZ ?trans2;
@!P1 IADD3 R11, PT, PT, R24, RZ, RZ ?WAIT3_END_GROUP;
@P0 VIMNMX.U32 R25, R25, R10, PT ?trans2;
@!P0 VIMNMX.U32 R25, R2, R11, PT ?WAIT5_END_GROUP;
ST.E desc[UR36][R8.64+0x8], R25 &rd=0x0 ?trans2;
BSYNC.RECONVERGENT B1 ?trans5;
IADD3 R21, PT, PT, R21, 0x1, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R21, R14, PT ?WAIT13_END_GROUP;
@P0 BRA 0x8d0 ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
IMAD.WIDE R2, R15, 0x4, R4 ?trans1;
LDCU UR4, c[0x0][0x398] &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x390] &wr=0x2 ?trans4;
LD.E R2, desc[UR36][R2.64] &wr=0x1 ?trans2;
ISETP.GT.AND P0, PT, R2, UR4, PT &req={1} ?WAIT13_END_GROUP;
@!P0 LDG.E R6, desc[UR36][R16.64] &wr=0x3 ?trans1;
LDCU UR4, c[0x0][0x370] &wr=0x1 ?trans1;
LDC R9, c[0x0][0x360] &req={0} &wr=0x1 ?trans2;
IMAD R18, R9, UR4, R18 &req={1} ?trans1;
UIADD3 UR4, UPT, UPT, -UR4, URZ, URZ ?WAIT6_END_GROUP;
IMAD R0, R9, UR4, R0 ?trans1;
@!P0 IADD3 R7, PT, PT, R6, 0x1, RZ &req={3} ?WAIT5_END_GROUP;
@!P0 STG.E desc[UR36][R16.64], R7 &rd=0x0 ?trans1;
ISETP.GE.AND P0, PT, R18, UR5, PT &req={2} ?WAIT13_END_GROUP;
@!P0 BRA 0x170 &req={0} ?trans5;
EXIT ?trans5;
BRA 0x1520;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: compMatches(char*, char*, int, int, int, int*)
_Z11compMatchesPcS_iiiPi:
s_mov_b64 s[46:47], s[0:1]
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b128 s[48:51], s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x20
s_add_u32 s8, s46, 40
s_addc_u32 s9, s47, 0
s_mov_b32 s32, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s33, s2, 0xffff
s_ashr_i32 s3, s49, 31
v_mad_u64_u32 v[41:42], null, s15, s33, v[0:1]
s_mov_b32 s2, s49
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v42, 31, v41
v_mov_b32_e32 v44, 0
v_lshlrev_b64 v[0:1], 2, v[41:42]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v42, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v43, vcc_lo, s1, v1, vcc_lo
v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v0, s2
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, __ockl_dm_alloc@rel32@lo+4
s_addc_u32 s1, s1, __ockl_dm_alloc@rel32@hi+12
global_store_b32 v[42:43], v44, off
s_swappc_b64 s[30:31], s[0:1]
s_mov_b32 s0, exec_lo
v_cmpx_gt_i32_e64 s48, v41
s_cbranch_execz .LBB1_12
s_load_b32 s1, s[8:9], 0x0
s_load_b128 s[4:7], s[46:47], 0x0
v_add_co_u32 v2, vcc_lo, v0, 4
v_sub_nc_u32_e32 v9, s48, v41
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
s_mov_b32 s8, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s1, s33
.LBB1_2:
v_sub_nc_u32_e32 v4, s48, v41
s_mov_b32 s9, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_i32_e32 v4, s49, v4
v_cmpx_ne_u32_e32 0, v4
s_cbranch_execz .LBB1_9
v_min_i32_e32 v5, s49, v9
s_mov_b32 s3, 1
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, 1, v5
v_max_u32_e32 v10, 2, v5
v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v5, v2
.LBB1_4:
v_mov_b32_e32 v7, s3
s_add_i32 s3, s3, 1
s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, s3, v10
global_store_b32 v[5:6], v7, off
v_add_co_u32 v5, s0, v5, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v6, s0, 0, v6, s0
s_or_b32 s2, vcc_lo, s2
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB1_4
s_or_b32 exec_lo, exec_lo, s2
v_ashrrev_i32_e32 v5, 31, v41
v_add_co_u32 v12, vcc_lo, s6, v41
v_add_nc_u32_e32 v11, -1, v10
s_mov_b32 s10, 1
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v13, vcc_lo, s7, v5, vcc_lo
s_mov_b32 s11, 0
.LBB1_6:
s_add_i32 s0, s10, -1
v_mov_b32_e32 v8, v3
v_add_co_u32 v5, vcc_lo, v12, s0
v_dual_mov_b32 v14, s10 :: v_dual_mov_b32 v7, v2
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v13, vcc_lo
v_dual_mov_b32 v16, s0 :: v_dual_mov_b32 v15, v11
s_mov_b32 s12, 0
s_mov_b64 s[2:3], s[4:5]
global_store_b32 v[0:1], v14, off
.LBB1_7:
global_load_b32 v17, v[7:8], off
global_load_u8 v18, v44, s[2:3]
global_load_u8 v19, v[5:6], off
v_add_nc_u32_e32 v15, -1, v15
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
s_waitcnt vmcnt(2)
v_min_i32_e32 v14, v17, v14
s_waitcnt vmcnt(0)
v_cmp_ne_u16_e32 vcc_lo, v18, v19
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v14, 1, v14
v_add_co_ci_u32_e32 v16, vcc_lo, 0, v16, vcc_lo
v_min_u32_e32 v14, v14, v16
v_mov_b32_e32 v16, v17
v_cmp_eq_u32_e32 vcc_lo, 0, v15
global_store_b32 v[7:8], v14, off
v_add_co_u32 v7, s0, v7, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v8, s0, 0, v8, s0
s_or_b32 s12, vcc_lo, s12
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execnz .LBB1_7
s_or_b32 exec_lo, exec_lo, s12
s_add_i32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, s10, v10
s_or_b32 s11, vcc_lo, s11
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB1_6
.LBB1_9:
s_or_b32 exec_lo, exec_lo, s9
v_ashrrev_i32_e32 v5, 31, v4
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v4, vcc_lo, v0, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, v1, v5, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_cmpx_ge_i32_e64 s50, v4
s_cbranch_execz .LBB1_11
global_load_b32 v4, v[42:43], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, 1, v4
global_store_b32 v[42:43], v4, off
.LBB1_11:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v41, s1, v41
v_subrev_nc_u32_e32 v9, s1, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s48, v41
s_or_b32 s8, vcc_lo, s8
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB1_2
.LBB1_12:
s_endpgm
| compMatches | 8,883 | 2,645 | stackv2-00000-of-00015 |
// Demangled: myfirstkernel()
Function : _Z13myfirstkernelv
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
EXIT ?trans5;
BRA 0x20;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: myfirstkernel()
_Z13myfirstkernelv:
s_endpgm
| myfirstkernel | 94 | 14 | stackv2-00000-of-00015 |
// Demangled: imrotate(unsigned char*, unsigned char*, unsigned int, unsigned int, unsigned int, unsigned int, double, double)
Function : _Z8imrotatePhS_jjjjdd
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
LDC R5, c[0x0][0x398] &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x2 ?trans1;
LDCU UR4, c[0x0][0x394] &wr=0x3 ?trans6;
S2UR UR6, SR_CTAID.X &wr=0x4 ?trans1;
I2F.U32.RP R0, R5 &req={1} &wr=0x1 ?trans1;
ISETP.NE.U32.AND P2, PT, R5, RZ, PT ?trans1;
MUFU.RCP R0, R0 &req={1} &wr=0x1 ?trans2;
IADD3 R3, PT, PT, R0, 0xffffffe, RZ &req={1} ?WAIT2_END_GROUP;
S2R R0, SR_TID.X &wr=0x2 ?trans4;
F2I.FTZ.U32.TRUNC.NTZ R3, R3 &wr=0x1 ?trans2;
IADD3 R2, PT, PT, RZ, -R3, RZ &req={1} ?WAIT5_END_GROUP;
IMAD R7, R2, R5, RZ ?trans2;
HFMA2 R2, -RZ, RZ, 0, 0 ?WAIT5_END_GROUP;
IMAD.HI.U32 R2, R3, R7, R2 ?WAIT6_END_GROUP;
IMAD.HI.U32 R2, R2, UR6, RZ &req={4} ?WAIT5_END_GROUP;
IADD3 R4, PT, PT, -R2, RZ, RZ ?WAIT5_END_GROUP;
IMAD R4, R5, R4, UR6 ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R4, R5, PT ?WAIT13_END_GROUP;
@P0 IADD3 R4, PT, PT, R4, -R5, RZ ?trans2;
@P0 IADD3 R2, PT, PT, R2, 0x1, RZ ?WAIT3_END_GROUP;
ISETP.GE.U32.AND P1, PT, R4, R5, PT ?WAIT13_END_GROUP;
@P1 IADD3 R2, PT, PT, R2, 0x1, RZ ?trans2;
@!P2 LOP3.LUT R2, RZ, R5, RZ, 0x33, !PT ?WAIT4_END_GROUP;
IADD3 R4, PT, PT, -R2, RZ, RZ ?WAIT5_END_GROUP;
IMAD R3, R5, R4, UR6 ?WAIT4_END_GROUP;
IMAD R8, R3, UR5, R0 &req={2} ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R8, UR4, PT &req={3} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDCU UR5, c[0x0][0x390] &wr=0x0 ?trans1;
I2F.F64.U32 R10, UR4 &wr=0x1 ?trans1;
USHF.R.U32.HI UR4, URZ, 0x1, UR4 ?trans1;
LDCU.128 UR8, c[0x0][0x3a0] &wr=0x2 ?trans1;
LDCU UR6, c[0x0][0x39c] &wr=0x3 ?WAIT15_END_GROUP;
NOP ?trans1;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R12, R10, R10 &req={1} &rd=0x0 &wr=0x1 ?trans1;
IMAD R9, R2, UR6, RZ &req={3} ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
I2F.F64 R4, R8 &rd=0x3 ?trans2;
IMAD R8, R8, 0x3, R9 &req={3} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
I2F.F64.U32 R6, UR4 &wr=0x3 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R4, R4, -R6 &req={3} &wr=0x3 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
I2F.F64.U32 R10, UR5 &req={0} &wr=0x1 ?trans1;
USHF.R.U32.HI UR5, URZ, 0x1, UR5 ?WAIT6_END_GROUP;
IADD3 R14, PT, PT, -R2, UR5, RZ ?WAIT15_END_GROUP;
NOP ?WAIT12_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R10, R10, R12 &req={1} &rd=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2I.F64.TRUNC R3, R4 &req={3} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
I2F.F64 R14, R14 &wr=0x2 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R6, R14, UR10 &req={2} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
I2F.F64 R12, R3 &req={0} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R6, R12, UR8, -R6 &req={1} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R16, R12, UR10 &rd=0x0 &wr=0x1 ?trans2;
MUFU.RSQ64H R13, R11 &req={0} &wr=0x0 ?trans1;
IADD3 R12, PT, PT, R11, -0x3500000, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R12, 0x7ca00000, PT ?WAIT15_END_GROUP;
NOP ?WAIT11_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R4, R14, UR8, R16 &req={1} &rd=0x1 ?trans2;
MOV.64 R14, 0x3fd8000000000000 &req={1} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R18, R12, R12 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R10, -R18, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R14, R18, R14, 0.5 &req={0} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R18, R12, R18 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R14, R18, R12 &req={0} &wr=0x0 ?trans2;
IADD3 R23, PT, PT, R19, -0x100000, RZ &req={0} ?trans1;
MOV R22, R18 ?WAIT15_END_GROUP;
NOP ?trans1;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R16, R10, R18 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R20, R16, -R16, R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R14, R20, R22, R16 &req={0} &rd=0x0 &wr=0x1 ?trans2;
@!P0 BRA 0x960 &req={1,0} ?trans5;
MOV R2, 0x960 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x17e0 ?trans5;
LDCU.64 UR6, c[0x0][0x390] &wr=0x0 ?trans1;
MUFU.RCP64H R3, R15 &wr=0x1 ?trans1;
MOV R2, 0x1 ?trans1;
UVIMNMX.U32 UR6, UR7, UR6, UPT &req={0} ?WAIT5_END_GROUP;
DFMA R10, R2, -R14, 1 &req={1} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
I2F.F64.U32 R16, UR6 &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x2 ?trans1;
FSETP.GEU.AND P1, PT, |R17|, 6.5827683646048100446e-37, PT &req={1} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R10, R10, R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R2, R10, R2 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R10, -R14, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R10, R2, R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R10, R16, R2 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, R10, -R14, R16 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R2, R12, R10 &req={0} &wr=0x0 ?trans2;
FFMA R10, RZ, R15, R3 &req={0} ?WAIT5_END_GROUP;
FSETP.GT.AND P0, PT, |R10|, 1.469367938527859385e-39, PT ?WAIT13_END_GROUP;
@P0 BRA P1, 0xcc0 &req={2} ?trans5;
MOV R10, R14 ?trans1;
MOV R11, R15 ?trans1;
MOV R12, 0xcc0 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x1030 ?trans5;
LDCU.64 UR8, c[0x0][0x388] &wr=0x0 ?trans1;
IADD3 R10, PT, PT, R8.reuse, 0x1, RZ ?trans2;
IADD3 R12, PT, PT, R8.reuse, 0x2, RZ ?trans1;
MOV R9, RZ ?trans1;
MOV R11, RZ ?trans1;
MOV R13, RZ ?trans1;
S2R R15, SR_CgaCtaId &wr=0x1 ?trans1;
MOV R14, 0x400 ?trans1;
LDCU UR10, c[0x0][0x39c] &wr=0x2 ?trans1;
IADD.64 R8, R8, UR8 &req={0} ?WAIT2_END_GROUP;
IADD.64 R10, R10, UR8 ?trans2;
IADD.64 R12, R12, UR8 ?trans2;
DMUL R6, R6, R2 &wr=0x0 ?trans1;
LDG.E.U8 R8, desc[UR6][R8.64] &rd=0x3 &wr=0x4 ?trans1;
LDCU.64 UR8, c[0x0][0x380] &wr=0x5 ?trans3;
LDG.E.U8 R10, desc[UR6][R10.64] &wr=0x4 ?trans4;
LDG.E.U8 R12, desc[UR6][R12.64] &wr=0x4 ?WAIT15_END_GROUP;
NOP ?WAIT10_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2I.F64.TRUNC R6, R6 &req={0} &wr=0x0 ?trans1;
MOV R9, RZ &req={3} ?trans1;
IADD3 R6, PT, PT, R6, UR4, RZ &req={0} ?trans1;
MOV R7, RZ ?trans1;
LEA R15, R15, R14, 0x18 &req={1} ?WAIT5_END_GROUP;
IMAD R15, R0, 0x3, R15 ?WAIT15_END_GROUP;
NOP ?WAIT10_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R4, R4, R2 &rd=0x0 &wr=0x1 ?trans2;
IMAD R3, R6, 0x3, RZ &req={0} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2I.F64.TRUNC R4, R4 &req={1} &wr=0x0 ?trans2;
IADD3 R2, PT, PT, -R4, UR5, RZ &req={0} ?WAIT5_END_GROUP;
IMAD R2, R2, UR10, R3 &req={2} ?trans1;
MOV R3, RZ ?WAIT4_END_GROUP;
IADD3 R6, PT, PT, R2, 0x1, RZ ?WAIT5_END_GROUP;
IADD.64 R6, R6, UR8 &req={5} ?trans2;
STS.U8 [R15], R8 &req={4} &rd=0x0 ?trans4;
STS.U8 [R15+0x1], R10 ?trans4;
STS.U8 [R15+0x2], R12 ?trans1;
IADD3 R8, PT, PT, R2.reuse, 0x2, RZ &req={0} ?trans1;
IADD.64 R2, R2, UR8 ?WAIT2_END_GROUP;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans2;
IADD.64 R8, R8, UR8 ?WAIT4_END_GROUP;
LDS.U8 R11, [R15] &wr=0x0 ?trans4;
LDS.U8 R13, [R15+0x1] &wr=0x1 ?trans4;
LDS.U8 R17, [R15+0x2] &wr=0x2 ?trans4;
STG.E.U8 desc[UR6][R2.64], R11 &req={0} ?trans4;
STG.E.U8 desc[UR6][R6.64], R13 &req={1} ?trans4;
STG.E.U8 desc[UR6][R8.64], R17 &req={2} ?trans1;
EXIT ?trans5;
FSETP.GEU.AND P0, PT, |R11|.reuse, 1.469367938527859385e-39, PT ?trans1;
LOP3.LUT R2, R11.reuse, 0x800fffff, RZ, 0xc0, !PT ?trans1;
HFMA2 R13, -RZ, RZ, 0.0045166015625, 0 ?trans1;
MOV R14, 0x1 ?trans1;
LOP3.LUT R23, R11, 0x7ff00000, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R3, R2, 0x3ff00000, RZ, 0xfc, !PT ?trans1;
MOV R2, R10 ?WAIT6_END_GROUP;
@!P0 DMUL R2, R10, 8.98846567431157953865e+307 &wr=0x0 ?trans2;
MUFU.RCP64H R15, R3 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R14, -R2, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R18, R18, R18 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R14, R18, R14 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R20, R18, -R2, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R20, R18, R20, R18 &req={0} &rd=0x0 &wr=0x1 ?trans2;
MOV R19, R17 &req={0} ?trans1;
MOV R18, R16 ?WAIT4_END_GROUP;
LOP3.LUT R22, R19, 0x7ff00000, RZ, 0xc0, !PT ?trans1;
MOV R14, R18 ?WAIT4_END_GROUP;
ISETP.GE.U32.AND P1, PT, R22, R23, PT ?trans1;
MOV R26, R22 ?WAIT4_END_GROUP;
SEL R15, R13, 0x63400000, !P1 ?trans1;
FSETP.GEU.AND P1, PT, |R19|, 1.469367938527859385e-39, PT ?WAIT4_END_GROUP;
LOP3.LUT R15, R15, 0x800fffff, R19, 0xf8, !PT ?WAIT9_END_GROUP;
@P1 BRA 0x1370 &req={1} ?trans5;
LOP3.LUT R17, R11, 0x7ff00000, RZ, 0xc0, !PT ?trans1;
MOV R16, RZ ?WAIT4_END_GROUP;
ISETP.GE.U32.AND P1, PT, R22, R17, PT ?WAIT5_END_GROUP;
SEL R17, R13, 0x63400000, !P1 ?WAIT5_END_GROUP;
LOP3.LUT R17, R17, 0x80000000, R19, 0xf8, !PT ?WAIT4_END_GROUP;
LOP3.LUT R17, R17, 0x100000, RZ, 0xfc, !PT ?WAIT6_END_GROUP;
DFMA R14, R14, 2, -R16 &wr=0x0 ?trans2;
LOP3.LUT R26, R15, 0x7ff00000, RZ, 0xc0, !PT &req={0} ?WAIT7_END_GROUP;
@!P0 LOP3.LUT R23, R3, 0x7ff00000, RZ, 0xc0, !PT ?trans1;
DMUL R24, R20, R14 &wr=0x0 ?trans1;
IADD3 R27, PT, PT, R26, -0x1, RZ ?trans2;
IADD3 R28, PT, PT, R23, -0x1, RZ ?WAIT3_END_GROUP;
ISETP.GT.U32.AND P0, PT, R27, 0x7feffffe, PT ?WAIT5_END_GROUP;
ISETP.GT.U32.OR P0, PT, R28, 0x7feffffe, P0 ?WAIT15_END_GROUP;
NOP ?WAIT8_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, R24, -R2, R14 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, R20, R16, R24 &req={0} &rd=0x0 &wr=0x1 ?trans2;
@P0 BRA 0x1660 &req={1,0} ?trans5;
LOP3.LUT R19, R11, 0x7ff00000, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R18, PT, PT, R22.reuse, -R19.reuse, RZ ?trans1;
ISETP.GE.U32.AND P0, PT, R22, R19, PT ?WAIT4_END_GROUP;
VIMNMX.S32 R18, R18, -0x46a00000, !PT ?trans1;
SEL R13, R13, 0x63400000, !P0 ?WAIT4_END_GROUP;
VIMNMX.S32 R18, R18, 0x46a00000, PT ?WAIT5_END_GROUP;
IADD3 R13, PT, PT, -R13, R18, RZ ?trans1;
MOV R18, RZ ?WAIT3_END_GROUP;
IADD3 R19, PT, PT, R13, 0x7fe00000, RZ ?WAIT6_END_GROUP;
DMUL R20, R16, R18 &wr=0x0 ?trans2;
FSETP.GTU.AND P0, PT, |R21|, 1.469367938527859385e-39, PT &req={0} ?WAIT13_END_GROUP;
@P0 BRA 0x17a0 ?trans5;
DFMA R2, R16, -R2, R14 &wr=0x0 ?trans1;
MOV R18, RZ ?trans1;
FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT &req={0} ?trans1;
LOP3.LUT R11, R3, 0x80000000, R11, 0x48, !PT ?WAIT4_END_GROUP;
LOP3.LUT R19, R11, R19, RZ, 0xfc, !PT ?WAIT8_END_GROUP;
@!P0 BRA 0x17a0 ?trans5;
IADD3 R3, PT, PT, -R13, RZ, RZ ?trans1;
MOV R2, RZ ?WAIT6_END_GROUP;
DFMA R2, R20, -R2, R16 &wr=0x0 ?trans2;
IADD3 R2, PT, PT, -R13, -0x43300000, RZ &req={0} ?WAIT5_END_GROUP;
FSETP.NEU.AND P0, PT, |R3|, R2, PT ?WAIT15_END_GROUP;
NOP ?WAIT12_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL.RP R16, R16, R18 &wr=0x0 ?trans2;
LOP3.LUT R11, R17, R11, RZ, 0x3c, !PT &req={0} ?trans1;
FSEL R20, R16, R20, !P0 ?WAIT4_END_GROUP;
FSEL R21, R11, R21, !P0 ?trans1;
BRA 0x17a0 ?trans6;
DSETP.NAN.AND P0, PT, R18, R18, PT &wr=0x0 ?trans2;
@P0 BRA 0x1780 &req={0} ?trans5;
DSETP.NAN.AND P0, PT, R10, R10, PT &wr=0x0 ?trans2;
@P0 BRA 0x1750 &req={0} ?trans5;
ISETP.NE.AND P0, PT, R26, R23, PT ?trans1;
MOV.64 R20, 0xfff8000000000000 ?WAIT12_END_GROUP;
@!P0 BRA 0x17a0 ?trans5;
ISETP.NE.AND P0, PT, R26, 0x7ff00000, PT ?trans1;
LOP3.LUT R21, R19, 0x80000000, R11, 0x48, !PT ?WAIT4_END_GROUP;
ISETP.EQ.OR P0, PT, R23, RZ, !P0 ?WAIT13_END_GROUP;
@P0 LOP3.LUT R2, R21, 0x7ff00000, RZ, 0xfc, !PT ?trans1;
@!P0 MOV R20, RZ ?trans1;
@P0 MOV R20, RZ ?WAIT3_END_GROUP;
@P0 MOV R21, R2 ?trans1;
BRA 0x17a0 ?trans6;
LOP3.LUT R21, R11, 0x80000, RZ, 0xfc, !PT ?trans1;
MOV R20, R10 ?trans1;
BRA 0x17a0 ?trans6;
LOP3.LUT R21, R19, 0x80000, RZ, 0xfc, !PT ?trans1;
MOV R20, R18 ?WAIT7_END_GROUP;
MOV R13, 0x0 ?trans1;
MOV R2, R20 ?trans1;
MOV R3, R21 ?trans2;
RET.REL.NODEC R12 0x0 ?trans5;
ISETP.GE.U32.AND P0, PT, R12, -0x3400000, PT ?trans1;
MOV R19, R23 ?WAIT12_END_GROUP;
@!P0 BRA 0x1900 ?trans5;
DFMA.RM R16, R20, R18, R16 &wr=0x0 ?trans2;
IADD.64 R12, R16, 0x1 &req={0} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA.RP R10, -R16, R12, R10 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DSETP.GT.AND P0, PT, R10, RZ, PT &req={0} &wr=0x0 ?trans2;
FSEL R12, R12, R16, P0 &req={0} ?trans1;
FSEL R13, R13, R17, P0 ?trans1;
BRA 0x1c70 ?trans6;
DSETP.NE.AND P0, PT, R10, RZ, PT &wr=0x0 ?trans2;
@!P0 BRA 0x1c60 &req={0} ?trans5;
ISETP.GE.AND P0, PT, R11, RZ, PT ?WAIT13_END_GROUP;
@!P0 MOV.64 R12, 0xfff8000000000000 ?trans2;
@!P0 BRA 0x1c70 ?trans6;
ISETP.GT.AND P0, PT, R11, 0x7fefffff, PT ?WAIT13_END_GROUP;
@P0 BRA 0x1c60 ?trans5;
DMUL R10, R10, 8.11296384146066816958e+31 &wr=0x0 ?trans1;
MOV R12, RZ ?trans1;
MUFU.RSQ64H R13, R11 &req={0} &wr=0x0 ?trans1;
MOV.64 R16, 0x3fd8000000000000 ?WAIT15_END_GROUP;
NOP ?trans1;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R14, R12, R12 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R14, R10, -R14, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, R14, R16, 0.5 &req={0} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R14, R12, R14 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R14, R16, R14, R12 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R12, R10, R14 &req={0} &rd=0x0 &wr=0x1 ?trans2;
IADD3 R15, PT, PT, R15, -0x100000, RZ &req={0} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, R12, -R12, R10 &req={1} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, R14, R16, R12 &req={0} &wr=0x0 ?trans2;
IADD3 R13, PT, PT, R13, -0x3500000, RZ &req={0} ?trans1;
BRA 0x1c70 ?trans6;
DADD R12, R10, R10 &rd=0x0 &wr=0x1 ?trans2;
MOV R3, 0x0 ?trans1;
MOV R14, R12 &req={1} ?trans1;
MOV R15, R13 ?trans2;
RET.REL.NODEC R2 0x0 &req={0} ?trans5;
BRA 0x1cb0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: imrotate(unsigned char*, unsigned char*, unsigned int, unsigned int, unsigned int, unsigned int, double, double)
_Z8imrotatePhS_jjjjdd:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x10
s_load_b32 s2, s[0:1], 0x3c
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v1, s6
s_sub_i32 s8, 0, s6
s_and_b32 s9, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s3, v1
s_mul_i32 s8, s8, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s8, s3, s8
s_add_i32 s3, s3, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s3, s15, s3
s_mul_i32 s8, s3, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s2, s15, s8
s_add_i32 s8, s3, 1
s_sub_i32 s10, s2, s6
s_cmp_ge_u32 s2, s6
s_cselect_b32 s3, s8, s3
s_cselect_b32 s2, s10, s2
s_add_i32 s8, s3, 1
s_cmp_ge_u32 s2, s6
s_cselect_b32 s2, s8, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s3, s2, s6
s_sub_i32 s3, s15, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s3, s9, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e64 s5, v1
s_cbranch_execz .LBB0_2
v_cvt_f64_u32_e32 v[2:3], s5
v_cvt_f64_u32_e32 v[4:5], s4
s_lshr_b32 s6, s4, 1
s_lshr_b32 s12, s5, 1
s_sub_i32 s13, s6, s2
s_load_b128 s[8:11], s[0:1], 0x0
s_mul_i32 s2, s2, s7
v_cvt_f64_i32_e32 v[14:15], s13
v_mul_u32_u24_e32 v0, 3, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[2:3], v[2:3], v[2:3]
v_fma_f64 v[2:3], v[4:5], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[2:3]
v_cndmask_b32_e64 v4, 0, 1, vcc_lo
s_and_b32 s3, vcc_lo, exec_lo
s_cselect_b32 s3, 0xffffff80, 0
v_lshlrev_b32_e32 v4, 8, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[2:3], v[2:3], v4
v_rsq_f64_e32 v[4:5], v[2:3]
v_cmp_class_f64_e64 vcc_lo, v[2:3], 0x260
s_waitcnt_depctr 0xfff
v_mul_f64 v[6:7], v[2:3], v[4:5]
v_mul_f64 v[4:5], v[4:5], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], -v[4:5], v[6:7], 0.5
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_fma_f64 v[4:5], v[4:5], v[8:9], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], -v[6:7], v[6:7], v[2:3]
v_fma_f64 v[6:7], v[8:9], v[4:5], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], -v[6:7], v[6:7], v[2:3]
v_fma_f64 v[4:5], v[8:9], v[4:5], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ldexp_f64 v[4:5], v[4:5], s3
s_min_u32 s3, s5, s4
v_cvt_f64_u32_e32 v[6:7], s3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v3, v5, v3 :: v_dual_cndmask_b32 v2, v4, v2
v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[8:9], v[4:5]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[4:5], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_mad_u64_u32 v[10:11], null, v1, 3, s[2:3]
v_subrev_nc_u32_e32 v1, s12, v1
s_load_b128 s[0:3], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v11, 1, v10
v_add_nc_u32_e32 v12, 2, v10
s_waitcnt lgkmcnt(0)
s_clause 0x2
global_load_u8 v18, v10, s[10:11]
global_load_u8 v19, v11, s[10:11]
global_load_u8 v20, v12, s[10:11]
v_div_scale_f64 v[12:13], vcc_lo, v[6:7], v[2:3], v[6:7]
s_waitcnt vmcnt(2)
ds_store_b8 v0, v18
s_waitcnt vmcnt(1)
ds_store_b8 v0, v19 offset:1
s_waitcnt vmcnt(0)
ds_store_b8 v0, v20 offset:2
v_fma_f64 v[10:11], -v[4:5], v[8:9], 1.0
v_mul_f64 v[16:17], v[14:15], s[2:3]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[10:11], v[12:13], v[8:9]
v_fma_f64 v[4:5], -v[4:5], v[10:11], v[12:13]
v_cvt_f64_i32_e32 v[12:13], v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[4:5], v[4:5], v[8:9], v[10:11]
v_mul_f64 v[8:9], v[12:13], s[2:3]
v_fma_f64 v[10:11], v[12:13], s[0:1], -v[16:17]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fixup_f64 v[1:2], v[4:5], v[2:3], v[6:7]
v_fma_f64 v[3:4], v[14:15], s[0:1], v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[5:6], v[1:2], v[10:11]
v_mul_f64 v[1:2], v[1:2], v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_i32_f64_e32 v3, v[5:6]
v_cvt_i32_f64_e32 v1, v[1:2]
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v2, s12, v3
ds_load_u8 v3, v0
ds_load_u8 v4, v0 offset:1
ds_load_u8 v5, v0 offset:2
v_sub_nc_u32_e32 v6, s6, v1
v_lshl_add_u32 v0, v2, 1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, v6, s7, v[0:1]
v_add_nc_u32_e32 v0, 1, v1
v_add_nc_u32_e32 v2, 2, v1
s_waitcnt lgkmcnt(2)
global_store_b8 v1, v3, s[8:9]
s_waitcnt lgkmcnt(1)
global_store_b8 v0, v4, s[8:9]
s_waitcnt lgkmcnt(0)
global_store_b8 v2, v5, s[8:9]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| imrotate | 8,649 | 3,115 | stackv2-00000-of-00015 |
// Demangled: imrotate2(unsigned char*, unsigned char*, unsigned int, unsigned int, unsigned int, double, double, double)
Function : _Z9imrotate2PhS_jjjddd
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R2, SR_TID.X &wr=0x1 ?trans1;
LDCU UR8, c[0x0][0x394] &wr=0x2 ?trans1;
IMAD R3, R3, UR4, R2 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R3, UR8, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
S2UR UR5, SR_CTAID.Y &wr=0x0 ?trans1;
LDCU.64 UR10, c[0x0][0x388] &wr=0x1 ?trans1;
IMAD R5, R3, 0x3, RZ ?trans1;
MOV R7, RZ ?trans1;
HFMA2 R9, -RZ, RZ, 0, 0 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x2 ?trans3;
LDC R0, c[0x0][0x398] &wr=0x0 ?trans1;
USHF.R.U32.HI UR4, URZ, 0x1, UR8 ?trans1;
LDCU.128 UR12, c[0x0][0x3a0] &wr=0x3 ?trans1;
IMAD R4, R0, UR5, R5 &req={0} ?WAIT2_END_GROUP;
HFMA2 R5, -RZ, RZ, 0, 0 ?WAIT3_END_GROUP;
IADD3 R6, PT, PT, R4.reuse, 0x1, RZ ?trans2;
IADD3 R8, PT, PT, R4.reuse, 0x2, RZ ?trans1;
IADD.64 R10, R4, UR10 &req={1} ?trans2;
IADD.64 R14, R6, UR10 ?trans2;
IADD.64 R16, R8, UR10 ?trans2;
LDG.E.U8 R18, desc[UR6][R10.64] &req={2} &rd=0x0 &wr=0x2 ?trans1;
I2F.F64.U32 R4, UR4 ?trans1;
LDCU UR4, c[0x0][0x390] &wr=0x1 ?trans2;
LDG.E.U8 R14, desc[UR6][R14.64] &wr=0x4 ?trans1;
LDCU.64 UR10, c[0x0][0x3b0] &wr=0x5 ?trans3;
LDG.E.U8 R16, desc[UR6][R16.64] &wr=0x2 ?trans1;
USHF.R.U32.HI UR4, URZ, 0x1, UR4 &req={1} ?WAIT4_END_GROUP;
UIADD3 UR5, UPT, UPT, UR4, -UR5, URZ ?WAIT15_END_GROUP;
NOP ?WAIT7_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
I2F.F64.U32 R6, R3 &rd=0x1 &wr=0x0 ?trans2;
MOV R3, 0x400 &req={1} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R8, R6, -R4 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2I.F64.TRUNC R8, R8 &req={0} &rd=0x0 ?trans2;
MOV R9, RZ &req={0} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
I2F.F64 R12, UR5 &wr=0x3 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R6, R12, UR14 &req={3} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
I2F.F64 R10, R8 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R6, R10, UR12, -R6 &req={0} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R10, R10, UR14 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R12, UR12, R10 &req={0} &rd=0x0 &wr=0x5 ?trans1;
LDCU.64 UR12, c[0x0][0x380] &wr=0x1 ?trans1;
S2R R12, SR_CgaCtaId &req={0} &wr=0x0 ?trans2;
LEA R3, R12, R3, 0x18 &req={0} ?WAIT5_END_GROUP;
IMAD R13, R2, 0x3, R3 ?WAIT5_END_GROUP;
STS.U8 [R13], R18 &req={2} ?trans4;
STS.U8 [R13+0x1], R14 &req={4} ?trans4;
STS.U8 [R13+0x2], R16 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?WAIT15_END_GROUP;
NOP ?WAIT11_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R10, R10, UR10 &req={5} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2I.F64.TRUNC R10, R10 &req={0} &wr=0x0 ?trans2;
IADD3 R3, PT, PT, -R10, UR4, RZ &req={0} ?trans1;
LDS.U8 R15, [R13] &wr=0x0 ?trans4;
LDS.U8 R17, [R13+0x1] &wr=0x2 ?trans4;
LDS.U8 R11, [R13+0x2] &wr=0x3 ?WAIT15_END_GROUP;
NOP ?WAIT8_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R6, R6, UR10, R4 &wr=0x4 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2I.F64.TRUNC R6, R6 &req={4} &wr=0x4 ?trans1;
HFMA2 R5, -RZ, RZ, 0, 0 ?trans2;
IMAD R2, R6, 0x3, RZ &req={4} ?WAIT4_END_GROUP;
IMAD R2, R3, R0, R2 ?trans1;
MOV R3, RZ ?WAIT4_END_GROUP;
IADD3 R4, PT, PT, R2.reuse, 0x1, RZ ?trans2;
IADD3 R8, PT, PT, R2.reuse, 0x2, RZ ?trans1;
IADD.64 R2, R2, UR12 &req={1} ?trans2;
IADD.64 R4, R4, UR12 ?trans2;
IADD.64 R8, R8, UR12 ?trans2;
STG.E.U8 desc[UR6][R2.64], R15 &req={0} ?trans4;
STG.E.U8 desc[UR6][R4.64], R17 &req={2} ?trans4;
STG.E.U8 desc[UR6][R8.64], R11 &req={3} ?trans1;
EXIT ?trans5;
BRA 0x780;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: imrotate2(unsigned char*, unsigned char*, unsigned int, unsigned int, unsigned int, double, double, double)
_Z9imrotate2PhS_jjjddd:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b128 s[4:7], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s5, v1
s_cbranch_execz .LBB1_2
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b128 s[16:19], s[0:1], 0x20
s_mul_i32 s2, s15, s6
s_load_b64 s[0:1], s[0:1], 0x30
v_mad_u64_u32 v[2:3], null, v1, 3, s[2:3]
s_lshr_b32 s2, s5, 1
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v3, 1, v2
v_add_nc_u32_e32 v4, 2, v2
s_waitcnt lgkmcnt(0)
s_clause 0x2
global_load_u8 v11, v2, s[10:11]
global_load_u8 v12, v3, s[10:11]
global_load_u8 v13, v4, s[10:11]
v_cvt_f64_u32_e32 v[1:2], v1
v_cvt_f64_u32_e32 v[3:4], s2
s_lshr_b32 s2, s4, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_sub_i32 s3, s2, s15
v_add_f64 v[1:2], v[1:2], -v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cvt_i32_f64_e32 v5, v[1:2]
v_cvt_f64_i32_e32 v[1:2], s3
v_cvt_f64_i32_e32 v[5:6], v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[7:8], v[1:2], s[18:19]
v_mul_f64 v[9:10], v[5:6], s[18:19]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[5:6], v[5:6], s[16:17], -v[7:8]
v_fma_f64 v[1:2], v[1:2], s[16:17], v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[3:4], v[5:6], s[0:1], v[3:4]
v_mul_f64 v[1:2], v[1:2], s[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_i32_f64_e32 v3, v[3:4]
v_cvt_i32_f64_e32 v1, v[1:2]
v_mul_u32_u24_e32 v2, 3, v0
s_delay_alu instid0(VALU_DEP_3)
v_lshl_add_u32 v0, v3, 1, v3
s_waitcnt vmcnt(2)
ds_store_b8 v2, v11
s_waitcnt vmcnt(1)
ds_store_b8 v2, v12 offset:1
s_waitcnt vmcnt(0)
ds_store_b8 v2, v13 offset:2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_u8 v3, v2
ds_load_u8 v4, v2 offset:1
ds_load_u8 v5, v2 offset:2
v_sub_nc_u32_e32 v6, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, v6, s6, v[0:1]
v_add_nc_u32_e32 v0, 1, v1
v_add_nc_u32_e32 v2, 2, v1
s_waitcnt lgkmcnt(2)
global_store_b8 v1, v3, s[8:9]
s_waitcnt lgkmcnt(1)
global_store_b8 v0, v4, s[8:9]
s_waitcnt lgkmcnt(0)
global_store_b8 v2, v5, s[8:9]
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| imrotate2 | 2,254 | 1,420 | stackv2-00000-of-00015 |
// Demangled: imrotate3(unsigned char*, unsigned char*, unsigned int, unsigned int, unsigned int, double, double, double)
Function : _Z9imrotate3PhS_jjjddd
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R2, SR_TID.X &wr=0x1 ?trans1;
LDCU UR8, c[0x0][0x394] &wr=0x2 ?trans1;
IMAD R3, R3, UR4, R2 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R3, UR8, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
S2UR UR5, SR_CTAID.Y &wr=0x0 ?trans1;
LDCU.64 UR10, c[0x0][0x388] &wr=0x1 ?trans1;
IMAD R5, R3, 0x3, RZ ?trans1;
MOV R7, RZ ?trans1;
HFMA2 R9, -RZ, RZ, 0, 0 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x2 ?trans3;
LDC R0, c[0x0][0x398] &wr=0x0 ?trans1;
USHF.R.U32.HI UR4, URZ, 0x1, UR8 ?trans1;
LDCU.128 UR12, c[0x0][0x3a0] &wr=0x3 ?trans1;
IMAD R4, R0, UR5, R5 &req={0} ?WAIT2_END_GROUP;
HFMA2 R5, -RZ, RZ, 0, 0 ?WAIT3_END_GROUP;
IADD3 R6, PT, PT, R4.reuse, 0x1, RZ ?trans2;
IADD3 R8, PT, PT, R4.reuse, 0x2, RZ ?trans1;
IADD.64 R10, R4, UR10 &req={1} ?trans2;
IADD.64 R14, R6, UR10 ?trans2;
IADD.64 R16, R8, UR10 ?trans2;
LDG.E.U8 R18, desc[UR6][R10.64] &req={2} &rd=0x0 &wr=0x2 ?trans1;
I2F.F64.U32 R4, UR4 ?trans1;
LDCU UR4, c[0x0][0x390] &wr=0x1 ?trans2;
LDG.E.U8 R14, desc[UR6][R14.64] &wr=0x4 ?trans1;
LDCU.64 UR10, c[0x0][0x3b0] &wr=0x5 ?trans3;
LDG.E.U8 R16, desc[UR6][R16.64] &wr=0x2 ?trans1;
USHF.R.U32.HI UR4, URZ, 0x1, UR4 &req={1} ?WAIT4_END_GROUP;
UIADD3 UR5, UPT, UPT, UR4, -UR5, URZ ?WAIT15_END_GROUP;
NOP ?WAIT7_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
I2F.F64.U32 R6, R3 &rd=0x1 &wr=0x0 ?trans2;
MOV R3, 0x400 &req={1} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R8, R6, -R4 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2I.F64.TRUNC R8, R8 &req={0} &rd=0x0 ?trans2;
MOV R9, RZ &req={0} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
I2F.F64 R12, UR5 &wr=0x3 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R6, R12, UR14 &req={3} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
I2F.F64 R10, R8 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R6, R10, UR12, -R6 &req={0} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R10, R10, UR14 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R12, UR12, R10 &req={0} &rd=0x0 &wr=0x5 ?trans1;
LDCU.64 UR12, c[0x0][0x380] &wr=0x1 ?trans1;
S2R R12, SR_CgaCtaId &req={0} &wr=0x0 ?trans2;
LEA R3, R12, R3, 0x18 &req={0} ?WAIT5_END_GROUP;
IMAD R13, R2, 0x3, R3 ?WAIT5_END_GROUP;
STS.U8 [R13], R18 &req={2} ?trans4;
STS.U8 [R13+0x1], R14 &req={4} ?trans4;
STS.U8 [R13+0x2], R16 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?WAIT15_END_GROUP;
NOP ?WAIT11_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R10, R10, UR10 &req={5} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2I.F64.TRUNC R10, R10 &req={0} &wr=0x0 ?trans2;
IADD3 R3, PT, PT, -R10, UR4, RZ &req={0} ?trans1;
LDS.U8 R15, [R13] &wr=0x0 ?trans4;
LDS.U8 R17, [R13+0x1] &wr=0x2 ?trans4;
LDS.U8 R11, [R13+0x2] &wr=0x3 ?WAIT15_END_GROUP;
NOP ?WAIT8_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R6, R6, UR10, R4 &wr=0x4 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2I.F64.TRUNC R6, R6 &req={4} &wr=0x4 ?trans1;
HFMA2 R5, -RZ, RZ, 0, 0 ?trans2;
IMAD R2, R6, 0x3, RZ &req={4} ?WAIT4_END_GROUP;
IMAD R2, R3, R0, R2 ?trans1;
MOV R3, RZ ?WAIT4_END_GROUP;
IADD3 R4, PT, PT, R2.reuse, 0x1, RZ ?trans2;
IADD3 R8, PT, PT, R2.reuse, 0x2, RZ ?trans1;
IADD.64 R2, R2, UR12 &req={1} ?trans2;
IADD.64 R4, R4, UR12 ?trans2;
IADD.64 R8, R8, UR12 ?trans2;
STG.E.U8 desc[UR6][R2.64], R15 &req={0} ?trans4;
STG.E.U8 desc[UR6][R4.64], R17 &req={2} ?trans4;
STG.E.U8 desc[UR6][R8.64], R11 &req={3} ?trans1;
EXIT ?trans5;
BRA 0x780;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: imrotate3(unsigned char*, unsigned char*, unsigned int, unsigned int, unsigned int, double, double, double)
_Z9imrotate3PhS_jjjddd:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b128 s[4:7], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s5, v1
s_cbranch_execz .LBB2_2
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b128 s[16:19], s[0:1], 0x20
s_mul_i32 s2, s15, s6
s_load_b64 s[0:1], s[0:1], 0x30
v_mad_u64_u32 v[2:3], null, v1, 3, s[2:3]
s_lshr_b32 s2, s5, 1
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v3, 1, v2
v_add_nc_u32_e32 v4, 2, v2
s_waitcnt lgkmcnt(0)
s_clause 0x2
global_load_u8 v11, v2, s[10:11]
global_load_u8 v12, v3, s[10:11]
global_load_u8 v13, v4, s[10:11]
v_cvt_f64_u32_e32 v[1:2], v1
v_cvt_f64_u32_e32 v[3:4], s2
s_lshr_b32 s2, s4, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_sub_i32 s3, s2, s15
v_add_f64 v[1:2], v[1:2], -v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cvt_i32_f64_e32 v5, v[1:2]
v_cvt_f64_i32_e32 v[1:2], s3
v_cvt_f64_i32_e32 v[5:6], v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[7:8], v[1:2], s[18:19]
v_mul_f64 v[9:10], v[5:6], s[18:19]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[5:6], v[5:6], s[16:17], -v[7:8]
v_fma_f64 v[1:2], v[1:2], s[16:17], v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[3:4], v[5:6], s[0:1], v[3:4]
v_mul_f64 v[1:2], v[1:2], s[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_i32_f64_e32 v3, v[3:4]
v_cvt_i32_f64_e32 v1, v[1:2]
v_mul_u32_u24_e32 v2, 3, v0
s_delay_alu instid0(VALU_DEP_3)
v_lshl_add_u32 v0, v3, 1, v3
s_waitcnt vmcnt(2)
ds_store_b8 v2, v11
s_waitcnt vmcnt(1)
ds_store_b8 v2, v12 offset:1
s_waitcnt vmcnt(0)
ds_store_b8 v2, v13 offset:2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_u8 v3, v2
ds_load_u8 v4, v2 offset:1
ds_load_u8 v5, v2 offset:2
v_sub_nc_u32_e32 v6, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, v6, s6, v[0:1]
v_add_nc_u32_e32 v0, 1, v1
v_add_nc_u32_e32 v2, 2, v1
s_waitcnt lgkmcnt(2)
global_store_b8 v1, v3, s[8:9]
s_waitcnt lgkmcnt(1)
global_store_b8 v0, v4, s[8:9]
s_waitcnt lgkmcnt(0)
global_store_b8 v2, v5, s[8:9]
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| imrotate3 | 2,254 | 1,420 | stackv2-00000-of-00015 |
// Demangled: imrotate4(unsigned char*, unsigned char*, unsigned int, unsigned int, unsigned int, double, double, double)
Function : _Z9imrotate4PhS_jjjddd
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R2, SR_TID.X &wr=0x1 ?trans1;
LDCU UR8, c[0x0][0x394] &wr=0x2 ?trans1;
IMAD R22, R3, UR4, R2 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R22, UR8, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
S2UR UR5, SR_CTAID.Y &wr=0x0 ?trans1;
IADD3 R3, PT, PT, R22.reuse, 0x1, RZ ?trans1;
LDCU.64 UR10, c[0x0][0x388] &wr=0x1 ?trans1;
IMAD R5, R22, 0x3, RZ ?trans2;
HFMA2 R9, -RZ, RZ, 0, 0 ?trans1;
MOV R7, RZ ?trans1;
ISETP.GE.U32.AND P0, PT, R3, UR8, PT ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x2 ?trans1;
LDC R0, c[0x0][0x398] &wr=0x0 ?trans1;
USHF.R.U32.HI UR4, URZ, 0x1, UR8 ?trans1;
LDCU.128 UR12, c[0x0][0x3a0] &wr=0x3 ?trans9;
@!P0 MOV R11, RZ ?trans1;
@!P0 MOV R19, RZ ?trans1;
@!P0 MOV R21, RZ ?trans1;
IMAD R4, R0, UR5, R5 &req={0} ?WAIT2_END_GROUP;
HFMA2 R5, -RZ, RZ, 0, 0 ?WAIT3_END_GROUP;
IADD3 R8, PT, PT, R4.reuse, 0x2, RZ ?trans2;
@!P0 IADD3 R10, PT, PT, R4.reuse, 0x3, RZ ?trans2;
@!P0 IADD3 R18, PT, PT, R4.reuse, 0x4, RZ ?trans2;
@!P0 IADD3 R20, PT, PT, R4.reuse, 0x5, RZ ?trans2;
IADD3 R6, PT, PT, R4, 0x1, RZ ?trans1;
IADD.64 R16, R8, UR10 &req={1} ?trans2;
@!P0 IADD.64 R8, R10, UR10 ?WAIT2_END_GROUP;
@!P0 IADD.64 R18, R18, UR10 ?trans2;
@!P0 IADD.64 R20, R20, UR10 ?trans2;
IADD.64 R12, R4, UR10 ?trans2;
IADD.64 R14, R6, UR10 ?trans2;
LDG.E.U8 R7, desc[UR6][R16.64] &req={2} &wr=0x2 ?trans4;
@!P0 LDG.E.U8 R8, desc[UR6][R8.64] &rd=0x0 &wr=0x4 ?trans4;
@!P0 LDG.E.U8 R18, desc[UR6][R18.64] &wr=0x5 ?trans4;
@!P0 LDG.E.U8 R20, desc[UR6][R20.64] &wr=0x2 ?trans1;
I2F.F64.U32 R4, UR4 ?trans1;
LDCU UR4, c[0x0][0x390] &wr=0x1 ?trans2;
LDG.E.U8 R3, desc[UR6][R12.64] &rd=0x0 &wr=0x2 ?trans1;
LDCU.64 UR10, c[0x0][0x3b0] &wr=0x0 ?trans3;
LDG.E.U8 R6, desc[UR6][R14.64] &rd=0x0 &wr=0x2 ?trans1;
USHF.R.U32.HI UR4, URZ, 0x1, UR4 &req={1} ?WAIT4_END_GROUP;
UIADD3 UR5, UPT, UPT, UR4, -UR5, URZ ?WAIT15_END_GROUP;
NOP ?WAIT7_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
I2F.F64.U32 R10, R22 &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R10, R10, -R4 &req={1} &wr=0x1 ?trans1;
MOV R9, 0x400 &req={0} ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2I.F64.TRUNC R10, R10 &req={1} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
I2F.F64 R12, R10 &req={0} &wr=0x3 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R16, R12, UR14 &req={3} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
I2F.F64 R14, UR5 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, R14, UR12, R16 &req={0} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R14, R14, UR14 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R12, UR12, -R14 &req={0} &rd=0x0 ?trans1;
LDCU.64 UR12, c[0x0][0x380] &wr=0x1 ?trans1;
S2R R12, SR_CgaCtaId &req={0} &wr=0x0 ?trans2;
LEA R9, R12, R9, 0x18 &req={0} ?WAIT5_END_GROUP;
IMAD R9, R2, 0x3, R9 ?WAIT5_END_GROUP;
STS.U8 [R9], R3 &req={2} &rd=0x0 ?trans4;
STS.U8 [R9+0x1], R6 ?trans4;
STS.U8 [R9+0x2], R7 &rd=0x2 ?trans4;
@!P0 STS.U8 [R9+0x3], R8 &req={4} ?trans4;
@!P0 STS.U8 [R9+0x4], R18 &req={5} ?trans4;
@!P0 STS.U8 [R9+0x5], R20 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?WAIT15_END_GROUP;
NOP ?WAIT14_END_GROUP;
DMUL R16, R16, UR10 &wr=0x3 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2I.F64.TRUNC R16, R16 &req={3} &rd=0x3 &wr=0x0 ?trans1;
LDS.U8 R13, [R9] &wr=0x4 ?trans4;
LDS.U8 R15, [R9+0x1] &wr=0x5 ?trans4;
LDS.U8 R17, [R9+0x2] &req={3} &wr=0x3 ?trans1;
IADD3 R3, PT, PT, -R16, UR4, RZ &req={0} ?trans1;
MOV R7, RZ &req={2} ?WAIT15_END_GROUP;
NOP ?WAIT8_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R10, UR10, R4 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2I.F64.TRUNC R10, R10 &req={0} &wr=0x0 ?trans2;
IMAD R2, R10, 0x3, RZ &req={0} ?WAIT4_END_GROUP;
IMAD R2, R3, R0, R2 ?trans1;
MOV R3, RZ ?trans1;
HFMA2 R5, -RZ, RZ, 0, 0 ?WAIT3_END_GROUP;
IADD3 R4, PT, PT, R2.reuse, 0x1, RZ ?trans2;
IADD3 R6, PT, PT, R2.reuse, 0x2, RZ ?trans1;
IADD.64 R2, R2, UR12 &req={1} ?trans2;
IADD.64 R4, R4, UR12 ?trans2;
IADD.64 R6, R6, UR12 ?trans2;
STG.E.U8 desc[UR6][R2.64], R13 &req={4} &rd=0x0 ?trans4;
STG.E.U8 desc[UR6][R4.64], R15 &req={5} &rd=0x0 ?trans4;
STG.E.U8 desc[UR6][R6.64], R17 &req={3} &rd=0x0 ?trans1;
@P0 EXIT ?trans5;
LDS.U8 R11, [R9+0x3] &wr=0x1 ?trans4;
LDS.U8 R13, [R9+0x4] &req={0} &wr=0x0 ?trans4;
LDS.U8 R15, [R9+0x5] &wr=0x2 ?trans4;
STG.E.U8 desc[UR6][R2.64], R11 &req={1} ?trans4;
STG.E.U8 desc[UR6][R4.64], R13 &req={0} ?trans4;
STG.E.U8 desc[UR6][R6.64], R15 &req={2} ?trans1;
EXIT ?trans5;
BRA 0x8f0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: imrotate4(unsigned char*, unsigned char*, unsigned int, unsigned int, unsigned int, double, double, double)
_Z9imrotate4PhS_jjjddd:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b128 s[8:11], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s9, v1
s_cbranch_execz .LBB3_5
s_load_b128 s[4:7], s[0:1], 0x0
s_mul_i32 s2, s15, s10
v_add_nc_u32_e32 v7, 1, v1
v_mad_u64_u32 v[2:3], null, v1, 3, s[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_u32_e32 vcc_lo, s9, v7
v_add_nc_u32_e32 v3, 1, v2
v_add_nc_u32_e32 v4, 2, v2
s_waitcnt lgkmcnt(0)
s_clause 0x2
global_load_u8 v5, v2, s[6:7]
global_load_u8 v6, v3, s[6:7]
global_load_u8 v4, v4, s[6:7]
v_mul_u32_u24_e32 v3, 3, v0
s_waitcnt vmcnt(2)
ds_store_b8 v3, v5
s_waitcnt vmcnt(1)
ds_store_b8 v3, v6 offset:1
s_waitcnt vmcnt(0)
ds_store_b8 v3, v4 offset:2
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB3_3
v_add_nc_u32_e32 v0, 3, v2
v_add_nc_u32_e32 v4, 4, v2
v_add_nc_u32_e32 v2, 5, v2
s_clause 0x2
global_load_u8 v0, v0, s[6:7]
global_load_u8 v4, v4, s[6:7]
global_load_u8 v2, v2, s[6:7]
s_waitcnt vmcnt(2)
ds_store_b8 v3, v0 offset:3
s_waitcnt vmcnt(1)
ds_store_b8 v3, v4 offset:4
s_waitcnt vmcnt(0)
ds_store_b8 v3, v2 offset:5
.LBB3_3:
s_or_b32 exec_lo, exec_lo, s2
s_lshr_b32 s2, s9, 1
v_cvt_f64_u32_e32 v[0:1], v1
v_cvt_f64_u32_e32 v[4:5], s2
s_lshr_b32 s2, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s3, s2, s15
s_clause 0x1
s_load_b128 s[12:15], s[0:1], 0x20
s_load_b64 s[0:1], s[0:1], 0x30
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_add_f64 v[0:1], v[0:1], -v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cvt_i32_f64_e32 v2, v[0:1]
v_cvt_f64_i32_e32 v[0:1], s3
v_cvt_f64_i32_e32 v[6:7], v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[8:9], v[0:1], s[14:15]
v_mul_f64 v[10:11], v[6:7], s[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[6:7], v[6:7], s[12:13], -v[8:9]
v_fma_f64 v[0:1], v[0:1], s[12:13], v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[4:5], v[6:7], s[0:1], v[4:5]
v_mul_f64 v[0:1], v[0:1], s[0:1]
s_delay_alu instid0(VALU_DEP_2)
v_cvt_i32_f64_e32 v2, v[4:5]
ds_load_u8 v4, v3
ds_load_u8 v5, v3 offset:1
ds_load_u8 v6, v3 offset:2
v_cvt_i32_f64_e32 v0, v[0:1]
v_lshl_add_u32 v2, v2, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v7, s2, v0
v_mad_u64_u32 v[0:1], null, v7, s10, v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v1, 1, v0
v_add_nc_u32_e32 v2, 2, v0
s_waitcnt lgkmcnt(1)
s_clause 0x1
global_store_b8 v1, v5, s[4:5]
global_store_b8 v0, v4, s[4:5]
s_waitcnt lgkmcnt(0)
global_store_b8 v2, v6, s[4:5]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB3_5
ds_load_u8 v7, v3 offset:3
ds_load_u8 v8, v3 offset:4
ds_load_u8 v9, v3 offset:5
v_add_co_u32 v3, s0, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, null, s5, 0, s0
v_add_co_u32 v0, s0, s4, v1
v_add_co_ci_u32_e64 v1, null, s5, 0, s0
v_add_co_u32 v5, s0, s4, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, null, s5, 0, s0
s_waitcnt lgkmcnt(2)
global_store_b8 v[3:4], v7, off
s_waitcnt lgkmcnt(1)
global_store_b8 v[0:1], v8, off
s_waitcnt lgkmcnt(0)
global_store_b8 v[5:6], v9, off
.LBB3_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| imrotate4 | 2,894 | 1,963 | stackv2-00000-of-00015 |
// Demangled: imrotate5(unsigned char*, unsigned int*, unsigned int, unsigned int, unsigned int, unsigned int, double, double, double)
Function : _Z9imrotate5PhPjjjjjddd
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R14, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x39c] &wr=0x2 ?trans1;
IMAD R0, R3, UR4, R14 &req={1} ?WAIT4_END_GROUP;
IMAD R0, R0, 0x3, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R0, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
S2R R21, SR_CTAID.Y &wr=0x0 ?trans1;
LDC.64 R16, c[0x0][0x388] &wr=0x1 ?trans1;
LDCU.64 UR8, c[0x0][0x358] &wr=0x2 ?trans1;
I2F.F64.U32 R2, R0 &wr=0x3 ?trans1;
UMOV.64 UR6, 0x3ff4cccccccccccd ?trans1;
LDCU.128 UR12, c[0x0][0x3a0] &wr=0x4 ?trans1;
LDCU UR10, c[0x0][0x398] &wr=0x5 ?WAIT15_END_GROUP;
NOP ?trans1;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R2, R2, UR6 &req={3} &wr=0x3 ?trans1;
LDCU.64 UR6, c[0x0][0x390] &wr=0x2 ?trans1;
IMAD R7, R21, UR5, R0 &req={0} ?WAIT5_END_GROUP;
IADD3 R9, PT, PT, R7.reuse, 0x1, RZ ?trans2;
IADD3 R13, PT, PT, R7.reuse, 0x2, RZ ?trans1;
IMAD.WIDE.U32 R6, R7, 0x4, R16 &req={1} ?trans1;
USHF.R.U32.HI UR4, URZ, 0x1, UR7 &req={2} ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R8, R9, 0x4, R16.reuse ?trans1;
LDG.E R15, desc[UR8][R6.64] &rd=0x0 &wr=0x2 ?trans3;
IMAD.WIDE.U32 R16, R13, 0x4, R16 ?trans1;
LDG.E R0, desc[UR8][R8.64] &wr=0x2 ?trans5;
LDG.E R16, desc[UR8][R16.64] &rd=0x1 &wr=0x2 ?WAIT15_END_GROUP;
NOP ?WAIT10_END_GROUP;
NOP ?WAIT15_END_GROUP;
I2F.F64.U32 R4, UR4 ?trans1;
USHF.R.U32.HI UR4, URZ, 0x1, UR6 ?trans1;
LDCU.64 UR6, c[0x0][0x3b0] &wr=0x0 ?trans5;
IADD3 R12, PT, PT, -R21, UR4, RZ ?WAIT15_END_GROUP;
NOP ?WAIT12_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2I.U32.F64.TRUNC R2, R2 &req={3} &wr=0x3 ?trans2;
IADD3 R22, PT, PT, R2.reuse, 0x1, RZ &req={3} ?trans2;
IADD3 R6, PT, PT, R2.reuse, 0x2, RZ &req={0} ?trans2;
IADD3 R17, PT, PT, R2, 0x3, RZ &req={1} ?WAIT15_END_GROUP;
NOP ?WAIT13_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
I2F.F64.U32 R10, R2 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R18, R10, -R4 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
I2F.F64.U32 R20, R22 &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R20, -R4, R20 &req={1} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
I2F.F64.U32 R26, R6 &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R26, -R4, R26 &req={1} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
I2F.F64.U32 R24, R17 &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R24, -R4, R24 &req={1} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2I.F64.TRUNC R30, R18 &req={0} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
I2F.F64 R12, R12 &wr=0x4 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R10, R12, UR14 &req={4} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
I2F.F64 R2, R30 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R2, UR12, -R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2I.F64.TRUNC R20, R20 &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R8, R2, UR14 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2I.F64.TRUNC R26, R26 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R18, UR6, R4 &req={0} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
I2F.F64 R22, R20 &req={1} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R6, R22, UR12, -R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
I2F.F64 R28, R26 &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R28, UR12, -R10 &req={1} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2I.F64.TRUNC R24, R24 &wr=0x3 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R6, R6, UR6, R4 &req={0} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
I2F.F64 R30, R24 &req={3} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R30, UR12, -R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R2, UR6, R4 &req={1} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R4, R10, UR6, R4 &req={0} &rd=0x0 &wr=0x1 ?trans2;
S2R R10, SR_CgaCtaId &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2I.F64.TRUNC R4, R4 &req={1} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R12, UR12, R8 &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2I.F64.TRUNC R3, R2 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R8, R8, UR6 &req={1} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2I.F64.TRUNC R8, R8 &req={1} &rd=0x1 &wr=0x3 ?trans2;
MOV R9, 0x400 &req={1} ?WAIT5_END_GROUP;
LEA R9, R10, R9, 0x18 &req={0} ?WAIT5_END_GROUP;
IMAD R11, R14, 0xc, R9 ?WAIT5_END_GROUP;
STS [R11], R15 &req={2} ?trans4;
STS [R11+0x4], R0 ?trans4;
STS [R11+0x8], R16 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R5, [R11] ?trans4;
LDS R2, [R11+0x4] &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT13_END_GROUP;
DMUL R22, R22, UR14 &wr=0x1 ?trans1;
LDS R0, [R11+0x8] &rd=0x2 &wr=0x4 ?trans1;
IADD3 R8, PT, PT, -R8, UR4, RZ &req={3} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2I.F64.TRUNC R17, R18 &wr=0x3 ?trans2;
IMAD R17, R17, 0x3, RZ &req={3} ?WAIT4_END_GROUP;
IMAD R8, R8, UR10, R17 &req={5} ?trans1;
MOV R9, RZ ?trans1;
IMAD R19, R4, 0x3, RZ ?trans1;
MOV R11, RZ &req={2} ?trans1;
IMAD R3, R3, 0x3, RZ ?WAIT15_END_GROUP;
NOP ?WAIT9_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R28, R28, UR14 &wr=0x2 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2I.F64.TRUNC R6, R6 &wr=0x3 ?trans2;
IMAD R17, R6, 0x3, RZ &req={3} ?trans1;
IADD3 R6, PT, PT, R8, 0x1, RZ ?trans1;
HFMA2 R7, -RZ, RZ, 0, 0 ?trans1;
PRMT R25, R2.reuse, 0x7770, RZ &req={0} ?trans2;
PRMT R27, R2, 0x7771, RZ ?trans2;
PRMT R33, R0, 0x7772, RZ &req={4} ?WAIT15_END_GROUP;
NOP ?WAIT10_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R30, R30, UR14 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R22, R12, UR12, R22 &req={1} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R20, R12, UR12, R28 &req={2} &rd=0x2 ?trans2;
PRMT R29, R0, 0x7770, RZ &req={2} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, R12, UR12, R30 &req={0} &rd=0x0 ?trans1;
LDCU.64 UR12, c[0x0][0x380] &wr=0x2 ?trans2;
IADD.64 R14, R6, UR12 &req={2} ?WAIT3_END_GROUP;
PRMT R7, R5, 0x7771, RZ ?trans2;
PRMT R31, R0, 0x7771, RZ &req={0} ?WAIT15_END_GROUP;
NOP ?WAIT11_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R22, R22, UR6 &req={1} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2I.F64.TRUNC R22, R22 &req={0} &wr=0x0 ?trans2;
IADD3 R22, PT, PT, -R22, UR4, RZ &req={0} ?WAIT5_END_GROUP;
IMAD R10, R22, UR10, R17 ?trans1;
PRMT R23, R5, 0x7772, RZ ?trans1;
MOV R17, RZ ?WAIT3_END_GROUP;
IADD3 R16, PT, PT, R10.reuse, 0x1, RZ ?trans2;
IADD3 R18, PT, PT, R10.reuse, 0x2, RZ ?trans1;
IADD.64 R10, R10, UR12 ?trans2;
IADD.64 R16, R16, UR12 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R12, R12, UR6 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2I.F64.TRUNC R12, R12 &req={0} &wr=0x0 ?trans2;
IADD3 R4, PT, PT, -R12, UR4, RZ &req={0} ?trans1;
IADD.64 R12, R8, UR12 ?WAIT3_END_GROUP;
IADD3 R8, PT, PT, R8, 0x2, RZ ?trans1;
IMAD R4, R4, UR10, R19 ?WAIT4_END_GROUP;
IADD.64 R8, R8, UR12 ?trans2;
HFMA2 R19, -RZ, RZ, 0, 0 ?WAIT5_END_GROUP;
IADD.64 R18, R18, UR12 ?WAIT15_END_GROUP;
NOP ?trans1;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R20, R20, UR6 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2I.F64.TRUNC R20, R20 &req={0} &rd=0x0 &wr=0x1 ?trans2;
PRMT R21, R5, 0x7770, RZ &req={0} ?trans2;
IADD3 R20, PT, PT, -R20, UR4, RZ &req={1} ?WAIT3_END_GROUP;
STG.E.U8 desc[UR8][R12.64], R21 &rd=0x0 ?trans1;
PRMT R5, R5, 0x7773, RZ ?trans1;
IMAD R6, R20, UR10, R3 ?trans2;
STG.E.U8 desc[UR8][R14.64], R7 &rd=0x1 ?trans1;
HFMA2 R3, -RZ, RZ, 0, 0 ?WAIT3_END_GROUP;
STG.E.U8 desc[UR8][R8.64], R23 &rd=0x2 ?trans1;
PRMT R21, R2.reuse, 0x7773, RZ &req={0} ?trans1;
HFMA2 R7, -RZ, RZ, 0, 0 &req={1} ?trans1;
PRMT R15, R2, 0x7772, RZ ?trans1;
STG.E.U8 desc[UR8][R10.64], R5 &rd=0x0 ?trans1;
IADD3 R2, PT, PT, R6.reuse, 0x1, RZ ?trans2;
IADD.64 R12, R6, UR12 ?WAIT3_END_GROUP;
IADD3 R6, PT, PT, R6, 0x2, RZ ?trans2;
IADD3 R8, PT, PT, R4, 0x1, RZ &req={2} ?trans1;
MOV R9, RZ ?trans1;
IADD.64 R2, R2, UR12 ?trans2;
MOV R5, RZ &req={0} ?trans1;
IADD3 R10, PT, PT, R4, 0x2, RZ ?trans1;
HFMA2 R11, -RZ, RZ, 0, 0 ?trans1;
IADD.64 R6, R6, UR12 ?trans2;
STG.E.U8 desc[UR8][R16.64], R25 ?trans1;
IADD.64 R4, R4, UR12 ?WAIT2_END_GROUP;
IADD.64 R8, R8, UR12 ?trans2;
STG.E.U8 desc[UR8][R18.64], R27 ?trans1;
IADD.64 R10, R10, UR12 ?WAIT3_END_GROUP;
STG.E.U8 desc[UR8][R12.64], R15 &rd=0x0 ?trans4;
STG.E.U8 desc[UR8][R2.64], R21 ?trans4;
STG.E.U8 desc[UR8][R6.64], R29 ?trans1;
PRMT R13, R0, 0x7773, RZ &req={0} ?WAIT3_END_GROUP;
STG.E.U8 desc[UR8][R4.64], R31 ?trans4;
STG.E.U8 desc[UR8][R8.64], R33 ?trans4;
STG.E.U8 desc[UR8][R10.64], R13 ?trans1;
EXIT ?trans5;
BRA 0x1590;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: imrotate5(unsigned char*, unsigned int*, unsigned int, unsigned int, unsigned int, unsigned int, double, double, double)
_Z9imrotate5PhPjjjjjddd:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b128 s[8:11], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_lshl_add_u32 v1, v1, 1, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s11, v1
s_cbranch_execz .LBB4_2
v_cvt_f64_u32_e32 v[4:5], v1
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b128 s[16:19], s[0:1], 0x20
v_mad_u64_u32 v[2:3], null, s15, s11, v[1:2]
v_mov_b32_e32 v3, 0
s_mov_b32 s2, 0xcccccccd
s_mov_b32 s3, 0x3ff4cccc
s_load_b64 s[0:1], s[0:1], 0x30
v_mul_u32_u24_e32 v0, 3, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_mov_b32 v7, v3 :: v_dual_add_nc_u32 v6, 1, v2
v_lshlrev_b64 v[8:9], 2, v[2:3]
v_add_nc_u32_e32 v2, 2, v2
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[1:2], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v8, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
s_clause 0x2
global_load_b32 v21, v[8:9], off
global_load_b32 v22, v[6:7], off
global_load_b32 v23, v[1:2], off
v_mul_f64 v[1:2], v[4:5], s[2:3]
s_lshr_b32 s2, s9, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cvt_u32_f64_e32 v5, v[1:2]
v_cvt_f64_u32_e32 v[1:2], s2
s_lshr_b32 s2, s8, 1
s_sub_i32 s3, s2, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f64_i32_e32 v[11:12], s3
v_cvt_f64_u32_e32 v[3:4], v5
v_add_nc_u32_e32 v6, 1, v5
v_add_nc_u32_e32 v7, 2, v5
v_add_nc_u32_e32 v9, 3, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f64_u32_e32 v[5:6], v6
v_cvt_f64_u32_e32 v[7:8], v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cvt_f64_u32_e32 v[9:10], v9
v_add_f64 v[3:4], v[3:4], -v[1:2]
v_add_f64 v[5:6], v[5:6], -v[1:2]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[7:8], v[7:8], -v[1:2]
v_add_f64 v[9:10], v[9:10], -v[1:2]
s_delay_alu instid0(VALU_DEP_4)
v_cvt_i32_f64_e32 v13, v[3:4]
v_mul_f64 v[3:4], v[11:12], s[16:17]
v_cvt_i32_f64_e32 v14, v[5:6]
v_cvt_i32_f64_e32 v15, v[7:8]
v_cvt_i32_f64_e32 v16, v[9:10]
v_mul_f64 v[7:8], v[11:12], s[18:19]
v_cvt_f64_i32_e32 v[5:6], v13
v_cvt_f64_i32_e32 v[9:10], v14
v_cvt_f64_i32_e32 v[11:12], v15
v_cvt_f64_i32_e32 v[13:14], v16
s_delay_alu instid0(VALU_DEP_4)
v_fma_f64 v[15:16], v[5:6], s[18:19], v[3:4]
v_fma_f64 v[5:6], v[5:6], s[16:17], -v[7:8]
v_fma_f64 v[17:18], v[9:10], s[18:19], v[3:4]
v_fma_f64 v[9:10], v[9:10], s[16:17], -v[7:8]
v_fma_f64 v[19:20], v[11:12], s[18:19], v[3:4]
v_fma_f64 v[11:12], v[11:12], s[16:17], -v[7:8]
v_fma_f64 v[7:8], v[13:14], s[16:17], -v[7:8]
v_fma_f64 v[3:4], v[13:14], s[18:19], v[3:4]
v_mul_f64 v[13:14], v[15:16], s[0:1]
v_fma_f64 v[5:6], v[5:6], s[0:1], v[1:2]
v_mul_f64 v[15:16], v[17:18], s[0:1]
v_fma_f64 v[9:10], v[9:10], s[0:1], v[1:2]
v_mul_f64 v[17:18], v[19:20], s[0:1]
v_fma_f64 v[11:12], v[11:12], s[0:1], v[1:2]
v_fma_f64 v[1:2], v[7:8], s[0:1], v[1:2]
v_mul_f64 v[3:4], v[3:4], s[0:1]
v_lshlrev_b32_e32 v7, 2, v0
s_waitcnt vmcnt(1)
ds_store_2addr_b32 v7, v21, v22 offset1:1
s_waitcnt vmcnt(0)
ds_store_b32 v7, v23 offset:8
v_cvt_i32_f64_e32 v8, v[13:14]
v_cvt_i32_f64_e32 v5, v[5:6]
v_cvt_i32_f64_e32 v6, v[15:16]
v_cvt_i32_f64_e32 v9, v[9:10]
v_cvt_i32_f64_e32 v10, v[17:18]
v_cvt_i32_f64_e32 v11, v[11:12]
v_cvt_i32_f64_e32 v13, v[1:2]
v_cvt_i32_f64_e32 v12, v[3:4]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[0:1], v7 offset1:1
ds_load_b32 v14, v7 offset:8
s_waitcnt lgkmcnt(1)
v_lshrrev_b32_e32 v15, 8, v0
v_lshrrev_b32_e32 v16, 24, v0
v_lshrrev_b32_e32 v17, 8, v1
v_lshrrev_b32_e32 v18, 24, v1
s_waitcnt lgkmcnt(0)
v_lshrrev_b32_e32 v19, 8, v14
v_lshrrev_b32_e32 v20, 24, v14
v_sub_nc_u32_e32 v7, s2, v8
v_lshl_add_u32 v2, v5, 1, v5
v_sub_nc_u32_e32 v8, s2, v6
s_delay_alu instid0(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, v7, s10, v[2:3]
v_lshl_add_u32 v2, v9, 1, v9
v_sub_nc_u32_e32 v9, s2, v10
v_lshl_add_u32 v4, v11, 1, v11
v_lshl_add_u32 v5, v13, 1, v13
v_sub_nc_u32_e32 v10, s2, v12
v_mad_u64_u32 v[6:7], null, v8, s10, v[2:3]
s_delay_alu instid0(VALU_DEP_3)
v_mad_u64_u32 v[7:8], null, v9, s10, v[4:5]
v_add_nc_u32_e32 v2, 1, v3
v_add_nc_u32_e32 v4, 2, v3
s_clause 0x2
global_store_b8 v3, v0, s[4:5]
global_store_b8 v2, v15, s[4:5]
global_store_d16_hi_b8 v4, v0, s[4:5]
v_mad_u64_u32 v[8:9], null, v10, s10, v[5:6]
v_add_nc_u32_e32 v0, 1, v6
v_add_nc_u32_e32 v2, 2, v6
v_add_nc_u32_e32 v3, 1, v7
v_add_nc_u32_e32 v4, 2, v7
v_add_nc_u32_e32 v5, 1, v8
v_add_nc_u32_e32 v9, 2, v8
s_clause 0x8
global_store_b8 v6, v16, s[4:5]
global_store_b8 v0, v1, s[4:5]
global_store_b8 v2, v17, s[4:5]
global_store_d16_hi_b8 v7, v1, s[4:5]
global_store_b8 v3, v18, s[4:5]
global_store_b8 v4, v14, s[4:5]
global_store_b8 v8, v19, s[4:5]
global_store_d16_hi_b8 v5, v14, s[4:5]
global_store_b8 v9, v20, s[4:5]
.LBB4_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| imrotate5 | 5,638 | 3,305 | stackv2-00000-of-00015 |
// Demangled: Varianza(int*, float*)
Function : _Z8VarianzaPiPf
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.Y &wr=0x1 ?trans7;
LDC R7, c[0x0][0x360] &wr=0x2 ?trans1;
S2R R0, SR_TID.X &wr=0x3 ?trans7;
S2UR UR4, SR_CTAID.Y &wr=0x1 ?trans8;
LDC R2, c[0x0][0x364] &wr=0x1 ?trans1;
LDCU UR7, c[0x0][0x370] &wr=0x2 ?trans7;
S2UR UR6, SR_CTAID.X &wr=0x3 ?trans8;
LDC.64 R4, c[0x0][0x388] &wr=0x4 ?trans1;
IMAD R3, R2, UR4, R3 &req={1} ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD R2, R7, UR7, RZ &req={2} ?WAIT2_END_GROUP;
IMAD R0, R7, UR6, R0 &req={3} ?WAIT4_END_GROUP;
IMAD R7, R3, R2, R0 ?WAIT4_END_GROUP;
IMAD.WIDE R4, R7.reuse, 0x4, R4 &req={4} ?trans1;
ISETP.GT.AND P0, PT, R7, 0x1606bf, PT ?WAIT4_END_GROUP;
STG.E desc[UR4][R4.64], RZ &req={1} &rd=0x1 ?trans9;
@P0 EXIT &req={0} ?trans5;
LDCU.64 UR6, c[0x0][0x380] &wr=0x0 ?trans1;
ISETP.NE.AND P1, PT, R3, RZ, PT ?trans1;
SHF.R.S32.HI R2, RZ, 0x1f, R7 ?trans1;
BSSY.RECONVERGENT B1, 0x280 ?trans4;
BSSY.RELIABLE B0, 0x230 ?trans1;
ISETP.EQ.OR P0, PT, R0, RZ, !P1 ?trans1;
LEA R10, P2, R7, UR6, 0x2 &req={0} ?WAIT4_END_GROUP;
LEA.HI.X R11, R7, UR7, R2, 0x2, P2 ?WAIT8_END_GROUP;
@P0 BRA 0x1e0 ?trans5;
LDG.E R2, desc[UR4][R10.64+-0x15b4] &wr=0x2 ?trans2;
I2FP.F32.S32 R2, R2 &req={2} ?trans1;
BRA 0x220 ?trans6;
@!P1 BREAK.RELIABLE B0 ?trans5;
HFMA2 R2, -RZ, RZ, 0, 0 ?trans1;
MOV R9, RZ ?trans1;
@!P1 BRA 0x270 ?trans6;
BSYNC.RELIABLE B0 ?trans5;
LDG.E R0, desc[UR4][R10.64+-0x4] &wr=0x2 ?trans1;
MOV R9, R2 ?trans1;
I2FP.F32.S32 R0, R0 &req={2} ?WAIT5_END_GROUP;
MOV R2, R0 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B1 ?trans5;
WARPSYNC.ALL ?trans5;
NOP ?trans1;
ISETP.NE.AND P0, PT, R3, 0x56c, PT ?trans1;
LDG.E R8, desc[UR4][R10.64] &wr=0x2 ?WAIT12_END_GROUP;
@P0 LDG.E R0, desc[UR4][R10.64+0x4] &rd=0x0 &wr=0x3 ?trans1;
FADD R3, R9, 5 ?trans1;
HFMA2 R7, -RZ, RZ, 0, 0 ?trans1;
MOV R13, 0x3de38e39 ?trans1;
HFMA2 R6, -RZ, RZ, 2.53125, 0 ?trans2;
FADD R3, R3, 8 ?trans1;
BSSY.RECONVERGENT B1, 0x460 ?trans3;
FADD R3, R3, R2 ?trans1;
FFMA R10, R13, -R6, 1 &req={0} ?WAIT4_END_GROUP;
FFMA R10, R10, R13, 0.11111111193895339966 ?trans1;
I2FP.F32.S32 R8, R8 &req={2} ?trans2;
@P0 I2FP.F32.S32 R7, R0 &req={3} ?WAIT3_END_GROUP;
FADD R0, R3, R8 ?WAIT4_END_GROUP;
FADD R0, R0, R7 ?WAIT4_END_GROUP;
FADD R0, R0, 2 ?WAIT4_END_GROUP;
FADD R0, R0, 5 ?WAIT4_END_GROUP;
FADD R3, R0, 4 ?WAIT4_END_GROUP;
FCHK P0, R3, 9 &wr=0x0 ?trans1;
FFMA R0, R3, R10, RZ ?WAIT4_END_GROUP;
FFMA R11, R0, -9, R3 ?WAIT4_END_GROUP;
FFMA R10, R10, R11, R0 ?trans1;
@!P0 BRA 0x450 &req={0} ?trans6;
MOV R10, 0x440 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x660 &req={1} ?trans5;
MOV R10, R3 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B1 ?trans5;
FADD R0, R10.reuse, -R9 ?trans1;
FADD R3, R10.reuse, -5 ?trans1;
FADD R9, R10.reuse, -8 ?trans1;
FADD R11, R10, -R2 ?trans1;
FFMA R0, R0, R0, RZ ?trans1;
FADD R7, R10, -R7 ?trans1;
BSSY.RECONVERGENT B1, 0x640 ?trans2;
FFMA R0, R3, R3, R0 ?WAIT4_END_GROUP;
FFMA R0, R9, R9, R0 ?trans1;
FADD R9, -R8, R10 ?WAIT3_END_GROUP;
FFMA R0, R11, R11, R0 ?trans1;
HFMA2 R11, -RZ, RZ, 1.4716796875, -0.0003798007965087890625 ?WAIT3_END_GROUP;
FFMA R0, R9, R9, R0 ?trans1;
FADD R9, R10.reuse, -2 ?trans1;
FFMA R2, R11, -R6, 1 ?trans2;
FFMA R0, R7, R7, R0 ?trans1;
FADD R7, R10, -4 ?WAIT3_END_GROUP;
FFMA R0, R9, R9, R0 ?WAIT4_END_GROUP;
FFMA R0, R3, R3, R0 ?WAIT4_END_GROUP;
FFMA R8, R7, R7, R0 ?trans1;
FFMA R0, R2, R11, 0.11111111193895339966 ?WAIT3_END_GROUP;
FCHK P0, R8, 9 &wr=0x0 ?trans1;
FFMA R3, R0, R8, RZ ?WAIT4_END_GROUP;
FFMA R2, R3, -9, R8 ?WAIT4_END_GROUP;
FFMA R3, R0, R2, R3 ?trans1;
@!P0 BRA 0x630 &req={0} ?trans6;
MOV R3, R8 ?trans1;
MOV R10, 0x630 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x660 &req={1} ?trans5;
BSYNC.RECONVERGENT B1 ?trans5;
STG.E desc[UR4][R4.64], R3 ?trans1;
EXIT ?trans5;
SHF.R.U32.HI R11, RZ, 0x17, R6 ?trans1;
BSSY.RECONVERGENT B2, 0xcc0 ?trans1;
SHF.R.U32.HI R0, RZ, 0x17, R3 ?trans2;
LOP3.LUT R11, R11, 0xff, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R16, R0, 0xff, RZ, 0xc0, !PT ?trans1;
MOV R12, 0x41100000 ?trans1;
IADD3 R14, PT, PT, R11, -0x1, RZ ?trans2;
IADD3 R15, PT, PT, R16, -0x1, RZ ?WAIT3_END_GROUP;
ISETP.GT.U32.AND P0, PT, R14, 0xfd, PT ?WAIT5_END_GROUP;
ISETP.GT.U32.OR P0, PT, R15, 0xfd, P0 ?WAIT13_END_GROUP;
@!P0 MOV R13, RZ ?trans1;
@!P0 BRA 0x8a0 ?trans6;
HFMA2 R0, -RZ, RZ, 2.53125, 0 ?trans1;
FSETP.GTU.FTZ.AND P0, PT, |R3|, +INF , PT ?WAIT4_END_GROUP;
FSETP.GTU.FTZ.AND P1, PT, |R0|, +INF , PT ?WAIT5_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, PT, 0xf8, 0x8f ?WAIT13_END_GROUP;
@P0 BRA 0xca0 ?trans5;
LOP3.LUT P0, RZ, R12, 0x7fffffff, R3, 0xc8, !PT ?WAIT13_END_GROUP;
@!P0 BRA 0xc80 ?trans5;
FSETP.NEU.FTZ.AND P2, PT, |R3|.reuse, +INF , PT ?trans1;
FSETP.NEU.FTZ.AND P1, PT, |R0|, +INF , PT ?trans1;
FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ?WAIT12_END_GROUP;
@!P1 BRA !P2, 0xc80 ?trans5;
LOP3.LUT P2, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P1, PT, P1, P2, PT, 0x2f, 0xf2 ?WAIT13_END_GROUP;
@P1 BRA 0xc60 ?trans5;
LOP3.LUT P1, RZ, R12, 0x7fffffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, PT, 0x2f, 0xf2 ?WAIT13_END_GROUP;
@P0 BRA 0xc30 ?trans5;
ISETP.GE.AND P0, PT, R15, RZ, PT ?trans1;
ISETP.GE.AND P1, PT, R14, RZ, PT ?WAIT12_END_GROUP;
@P0 MOV R13, RZ ?trans1;
@!P0 MOV R13, 0xffffffc0 ?trans1;
@!P0 FFMA R3, R3, 1.84467440737095516160e+19, RZ ?trans1;
@!P1 FFMA R12, R0, 1.84467440737095516160e+19, RZ ?WAIT3_END_GROUP;
@!P1 IADD3 R13, PT, PT, R13, 0x40, RZ ?WAIT7_END_GROUP;
LEA R15, R11, 0xc0800000, 0x17 ?trans1;
BSSY.RECONVERGENT B3, 0xc20 ?trans3;
IADD3 R15, PT, PT, -R15, R12, RZ ?trans2;
IADD3 R12, PT, PT, R16, -0x7f, RZ ?trans2;
MUFU.RCP R14, R15 &wr=0x0 ?trans1;
FADD.FTZ R17, -R15, -RZ ?trans2;
IMAD R0, R12.reuse, -0x800000, R3 ?trans1;
IADD3 R12, PT, PT, R12, 0x7f, -R11 ?WAIT4_END_GROUP;
IADD3 R12, PT, PT, R12, R13, RZ ?trans1;
FFMA R19, R14, R17, 1 &req={0} ?WAIT4_END_GROUP;
FFMA R16, R14, R19, R14 ?WAIT4_END_GROUP;
FFMA R3, R0, R16, RZ ?WAIT4_END_GROUP;
FFMA R14, R17, R3, R0 ?WAIT4_END_GROUP;
FFMA R19, R16, R14, R3 ?WAIT4_END_GROUP;
FFMA R14, R17, R19, R0 ?WAIT4_END_GROUP;
FFMA R3, R16, R14, R19 ?WAIT5_END_GROUP;
SHF.R.U32.HI R0, RZ, 0x17, R3 ?WAIT4_END_GROUP;
LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R15, PT, PT, R0, R12, RZ ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R15, -0x1, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R0, 0xfe, PT ?WAIT13_END_GROUP;
@!P0 BRA 0xc00 ?trans5;
ISETP.GT.AND P0, PT, R15, 0xfe, PT ?WAIT13_END_GROUP;
@P0 BRA 0xbd0 ?trans5;
ISETP.GE.AND P0, PT, R15, 0x1, PT ?WAIT13_END_GROUP;
@P0 BRA 0xc10 ?trans5;
ISETP.GE.AND P0, PT, R15, -0x18, PT ?trans1;
LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ?WAIT12_END_GROUP;
@!P0 BRA 0xc10 ?trans5;
FFMA.RZ R0, R16.reuse, R14.reuse, R19.reuse ?trans1;
IADD3 R13, PT, PT, R15.reuse, 0x20, RZ ?trans1;
FFMA.RM R11, R16, R14, R19 ?trans1;
ISETP.NE.AND P1, PT, R15.reuse, RZ, PT ?trans1;
ISETP.NE.AND P2, PT, R15, RZ, PT ?trans1;
LOP3.LUT R0, R0, 0x7fffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
LOP3.LUT R12, R0, 0x800000, RZ, 0xfc, !PT ?trans1;
FFMA.RP R0, R16, R14, R19 ?trans1;
IADD3 R14, PT, PT, -R15, RZ, RZ ?trans2;
SHF.L.U32 R13, R12, R13, RZ ?trans2;
FSETP.NEU.FTZ.AND P0, PT, R0, R11, PT ?trans1;
SEL R11, R14, RZ, P2 ?trans2;
ISETP.NE.AND P1, PT, R13, RZ, P1 ?WAIT3_END_GROUP;
SHF.R.U32.HI R11, RZ, R11, R12 ?trans2;
PLOP3.LUT P0, PT, P0, P1, PT, 0xf8, 0x8f ?trans2;
SHF.R.U32.HI R13, RZ, 0x1, R11 ?WAIT3_END_GROUP;
SEL R0, RZ, 0x1, !P0 ?WAIT5_END_GROUP;
LOP3.LUT R0, R0, 0x1, R13, 0xf8, !PT ?WAIT4_END_GROUP;
LOP3.LUT R0, R0, R11, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R13, R0, RZ ?WAIT4_END_GROUP;
LOP3.LUT R3, R0, R3, RZ, 0xfc, !PT ?trans1;
BRA 0xc10 ?trans6;
LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ?trans1;
BRA 0xc10 ?trans6;
IMAD R3, R12, 0x800000, R3 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B3 ?trans5;
BRA 0xcb0 ?trans5;
LOP3.LUT R3, R12, 0x80000000, R3, 0x48, !PT ?WAIT4_END_GROUP;
LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ?trans1;
BRA 0xcb0 ?trans6;
LOP3.LUT R3, R12, 0x80000000, R3, 0x48, !PT ?trans1;
BRA 0xcb0 ?trans6;
MUFU.RSQ R3, -QNAN &wr=0x0 ?trans1;
BRA 0xcb0 ?trans5;
FADD.FTZ R3, R3, R0 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
HFMA2 R11, -RZ, RZ, 0, 0 ?WAIT4_END_GROUP;
RET.REL.NODEC R10 0x0 &req={0} ?trans5;
BRA 0xce0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: Varianza(int*, float*)
_Z8VarianzaPiPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, s14, s2, v[1:2]
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v0, 0
s_mul_i32 s3, s3, s2
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, s3, v1, v[3:4]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v7, vcc_lo
global_store_b32 v[9:10], v0, off
v_cmpx_gt_i32_e32 0x1606c0, v4
s_cbranch_execz .LBB0_12
v_cmp_ne_u32_e64 s0, 0, v3
v_cmp_ne_u32_e32 vcc_lo, 0, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, vcc_lo
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_3
v_add_co_u32 v0, s0, s4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v3, s0, s5, v7, s0
v_add_co_u32 v2, s0, 0xfffff000, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, -1, v3, s0
global_load_b32 v0, v[2:3], off offset:-1460
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v3, 0
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_5
v_add_co_u32 v2, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v7, vcc_lo
global_load_b32 v3, v[2:3], off offset:-4
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s0
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
s_mov_b32 s0, exec_lo
global_load_b32 v4, v[6:7], off
v_cmpx_ne_u32_e32 0x56c, v1
s_cbranch_execz .LBB0_7
global_load_b32 v5, v[6:7], off offset:4
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s0
v_dual_mov_b32 v1, 5 :: v_dual_mov_b32 v2, 8
v_mov_b32_e32 v6, 2
v_dual_mov_b32 v8, 4 :: v_dual_mov_b32 v11, 0
s_delay_alu instid0(VALU_DEP_3)
v_mov_b32_e32 v7, v1
s_mov_b64 s[0:1], 0
.LBB0_8:
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 m0, s0
s_add_u32 s0, s0, 1
s_waitcnt vmcnt(0)
v_movrels_b32_e32 v12, v0
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s0, 9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v12, v12
v_add_f32_e32 v11, v11, v12
s_cbranch_scc1 .LBB0_8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_scale_f32 v12, null, 0x41100000, 0x41100000, v11
v_div_scale_f32 v15, vcc_lo, v11, 0x41100000, v11
s_mov_b64 s[0:1], 0
v_rcp_f32_e32 v13, v12
s_waitcnt_depctr 0xfff
v_fma_f32 v14, -v12, v13, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v13, v14, v13
v_mul_f32_e32 v14, v15, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v16, -v12, v14, v15
v_fmac_f32_e32 v14, v16, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v12, -v12, v14, v15
v_div_fmas_f32 v12, v12, v13, v14
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v12, v12, 0x41100000, v11
v_mov_b32_e32 v11, 0
.LBB0_10:
s_mov_b32 m0, s0
s_add_u32 s0, s0, 1
v_movrels_b32_e32 v13, v0
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s0, 9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v13, v13
v_sub_f32_e32 v13, v12, v13
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v11, v13, v13
s_cbranch_scc1 .LBB0_10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v0, null, 0x41100000, 0x41100000, v11
v_rcp_f32_e32 v1, v0
s_waitcnt_depctr 0xfff
v_fma_f32 v2, -v0, v1, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v1, v2, v1
v_div_scale_f32 v2, vcc_lo, v11, 0x41100000, v11
v_mul_f32_e32 v3, v2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v0, v3, v2
v_fmac_f32_e32 v3, v4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v0, -v0, v3, v2
v_div_fmas_f32 v0, v0, v1, v3
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v0, v0, 0x41100000, v11
global_store_b32 v[9:10], v0, off
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| Varianza | 4,796 | 2,519 | stackv2-00000-of-00015 |
// Demangled: mandelKernel(int*, float, float, float, float, int, int)
Function : _Z12mandelKernelPiffffii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
LDC.64 R6, c[0x0][0x398] &wr=0x2 ?trans1;
LDCU.64 UR6, c[0x0][0x388] &wr=0x3 ?trans1;
S2R R5, SR_TID.Y &wr=0x4 ?trans6;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans8;
LDC R3, c[0x0][0x360] &wr=0x1 ?trans8;
S2UR UR5, SR_CTAID.Y &wr=0x4 ?trans1;
ISETP.GE.AND P0, PT, R7, 0x1, PT &req={2} ?WAIT7_END_GROUP;
LDC R2, c[0x0][0x364] &wr=0x4 ?trans8;
LDC.64 R8, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD R3, R3, UR4, R0 &req={1} ?WAIT5_END_GROUP;
I2FP.F32.S32 R7, R3 ?trans1;
IMAD R0, R2, UR5, R5 &req={4} ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans3;
IMAD R5, R0, R6, R3 ?trans1;
I2FP.F32.U32 R2, R0 ?trans1;
FFMA R7, R7, R8, UR6 &req={3} ?WAIT4_END_GROUP;
FFMA R2, R2, R9, UR7 ?trans1;
HFMA2 R9, -RZ, RZ, 0, 0 ?trans1;
@!P0 BRA 0x290 &req={0} ?trans6;
BSSY.RECONVERGENT B0, 0x290 ?trans1;
MOV R9, RZ ?trans1;
MOV R3, R2 ?trans1;
MOV R0, R7 ?trans1;
LDCU UR6, c[0x0][0x39c] &wr=0x0 ?trans1;
LDCU UR7, c[0x0][0x39c] &wr=0x2 ?trans5;
FMUL R4, R0, R0 ?trans1;
FMUL R13, R3, R3 ?WAIT4_END_GROUP;
FADD R6, R4, R13 ?WAIT5_END_GROUP;
FSETP.GT.AND P0, PT, R6, 4, PT ?WAIT13_END_GROUP;
@P0 BRA 0x280 ?trans5;
IADD3 R9, PT, PT, R9, 0x1, RZ ?trans1;
FADD R11, R0, R0 ?trans1;
FADD R0, R4, -R13 ?WAIT3_END_GROUP;
ISETP.NE.AND P0, PT, R9, UR7, PT &req={2} ?trans1;
FFMA R3, R11, R3, R2 ?trans1;
FADD R0, R7, R0 ?WAIT11_END_GROUP;
@P0 BRA 0x1b0 ?trans5;
MOV R9, UR6 &req={0} ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 &req={2,1,0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans2;
IMAD.WIDE R2, R5, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R9 &req={1} ?trans1;
EXIT ?trans5;
BRA 0x2d0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: mandelKernel(int*, float, float, float, float, int, int)
_Z12mandelKernelPiffffii:
s_clause 0x2
s_load_b32 s8, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s9, s8, 16
s_and_b32 s8, s8, 0xffff
s_cmp_lt_i32 s3, 1
v_mad_u64_u32 v[0:1], null, s14, s8, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s9, v[3:4]
s_cbranch_scc1 .LBB0_6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v2, v0
v_cvt_f32_i32_e32 v3, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v2, v2, s6, s4
v_fma_f32 v3, v3, s7, s5
s_mov_b32 s4, 0
s_mov_b32 s5, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v6, v2
v_mov_b32_e32 v4, v3
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v6, v6
s_or_b32 s6, s6, exec_lo
v_fma_f32 v5, v4, v4, v7
s_delay_alu instid0(VALU_DEP_1)
v_cmp_nlt_f32_e32 vcc_lo, 4.0, v5
v_mov_b32_e32 v5, s5
s_and_saveexec_b32 s7, vcc_lo
v_dual_mul_f32 v5, v4, v4 :: v_dual_add_f32 v6, v6, v6
s_add_i32 s5, s5, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, s5
v_sub_f32_e32 v7, v7, v5
s_cselect_b32 s8, -1, 0
v_mov_b32_e32 v5, s3
v_fma_f32 v4, v4, v6, v3
s_and_not1_b32 s6, s6, exec_lo
v_add_f32_e32 v6, v2, v7
s_and_b32 s8, s8, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s6, s6, s8
s_or_b32 exec_lo, exec_lo, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s7, exec_lo, s6
s_or_b32 s4, s7, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s4
s_branch .LBB0_7
.LBB0_6:
v_mov_b32_e32 v5, 0
.LBB0_7:
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| mandelKernel | 1,019 | 1,293 | stackv2-00000-of-00015 |
// Demangled: addKernel(int*, int const*, int const*)
Function : _Z9addKernelPiPKiS1_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R9, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x388] &wr=0x1 ?trans1;
LDCU UR6, c[0x0][0x360] &wr=0x0 ?trans1;
S2R R0, SR_TID.Y &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans5;
LDC.64 R4, c[0x0][0x390] &wr=0x3 ?trans8;
LDC.64 R6, c[0x0][0x380] &wr=0x4 ?trans1;
IMAD R9, R0, UR6, R9 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R9.reuse, 0x4, R4 &req={3} ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={2} &wr=0x2 ?trans4;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R6, R9, 0x4, R6 &req={4} ?trans1;
IADD3 R9, PT, PT, R2, R5, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x110;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: addKernel(int*, int const*, int const*)
_Z9addKernelPiPKiS1_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_u32_u24_e32 v1, s2, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_lshl_u32 v0, v1, v0, 2
s_clause 0x1
global_load_b32 v1, v0, s[6:7]
global_load_b32 v2, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[4:5]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| addKernel | 511 | 337 | stackv2-00000-of-00015 |
// Demangled: Driver(float*)
Function : _Z6DriverPf
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R5, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans1;
LDCU UR6, c[0x0][0x360] &wr=0x0 ?trans1;
S2R R0, SR_CTAID.X &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans1;
IMAD R5, R0, UR6, R5 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE R2, R5, 0x4, R2 &req={1} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR4][R2.64] &req={2} &wr=0x2 ?trans2;
FMUL R5, R0, R0 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R5 ?trans1;
EXIT ?trans5;
BRA 0xc0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: Driver(float*)
_Z6DriverPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| Driver | 342 | 361 | stackv2-00000-of-00015 |
// Demangled: vector_add(int*, int*, int*)
Function : _Z10vector_addPiS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R9, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R9.reuse, 0x4, R4 &req={2} ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans4;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R6, R9, 0x4, R6 &req={3} ?trans1;
IADD3 R9, PT, PT, R2, R5, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0xe0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: vector_add(int*, int*, int*)
_Z10vector_addPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| vector_add | 426 | 193 | stackv2-00000-of-00015 |
// Demangled: add(double*, double*, double*, int)
Function : _Z3addPdS_S_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x398] &wr=0x2 ?trans7;
LDC R7, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R7, R7, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R7, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans8;
LDC.64 R8, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD.WIDE R2, R7, 0x8, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E.64 R2, desc[UR4][R2.64] &req={1} &wr=0x4 ?trans1;
IMAD.WIDE R4, R7, 0x8, R4 &req={2} ?WAIT6_END_GROUP;
LDG.E.64 R4, desc[UR4][R4.64] &wr=0x4 ?trans1;
IMAD.WIDE R8, R7, 0x8, R8 &req={3} ?trans1;
DADD R6, R2, R4 &req={4} &wr=0x0 ?trans4;
STG.E.64 desc[UR4][R8.64], R6 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x140;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: add(double*, double*, double*, int)
_Z3addPdS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| add | 582 | 590 | stackv2-00000-of-00015 |
// Demangled: pattern(int*, int)
Function : _Z7patternPii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x388] &wr=0x1 ?trans2;
ISETP.GE.AND P0, PT, R0, UR4, PT &req={1} ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LDCU UR6, c[0x0][0x360] &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x370] &wr=0x1 ?trans1;
LDCU.64 UR8, c[0x0][0x358] &wr=0x2 ?trans1;
LDCU UR7, c[0x0][0x388] &wr=0x3 ?trans1;
LDCU.64 UR10, c[0x0][0x380] &wr=0x4 ?trans1;
UIMAD UR6, UR6, UR4, URZ &req={1} ?WAIT12_END_GROUP;
IMAD.WIDE R4, R0, 0x4d, RZ ?trans1;
BSSY.RECONVERGENT B0, 0x260 ?trans1;
SHF.R.S32.HI R3, RZ, 0x1f, R0 ?WAIT3_END_GROUP;
ISETP.NE.U32.AND P0, PT, R5, RZ, PT ?WAIT13_END_GROUP;
@P0 BRA 0x220 ?trans5;
UI2F.U32.RP UR4, UR7 &req={3} ?trans1;
HFMA2 R6, -RZ, RZ, 0, 0 ?trans1;
ISETP.NE.U32.AND P1, PT, RZ, UR7, PT ?WAIT7_END_GROUP;
MUFU.RCP R2, UR4 &wr=0x1 ?trans2;
IADD3 R2, PT, PT, R2, 0xffffffe, RZ &req={1} ?WAIT4_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R7, R2 &wr=0x1 ?trans2;
IADD3 R5, PT, PT, RZ, -R7, RZ &req={1} ?WAIT5_END_GROUP;
IMAD R5, R5, UR7, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R7, R7, R5, R6 ?WAIT6_END_GROUP;
IMAD.HI.U32 R7, R7, R4, RZ ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, -R7, RZ, RZ ?WAIT5_END_GROUP;
IMAD R4, R7, UR7, R4 ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R4, UR7, PT ?WAIT13_END_GROUP;
@P0 IADD3 R4, PT, PT, R4, -UR7, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R4, UR7, PT ?WAIT13_END_GROUP;
@P0 IADD3 R4, PT, PT, R4, -UR7, RZ ?trans2;
@!P1 LOP3.LUT R4, RZ, UR7, RZ, 0x33, !PT ?trans1;
BRA 0x250 ?trans6;
MOV R2, 0x240 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x2d0 &req={4,3,2,0} ?trans5;
MOV R4, R6 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 &req={4,2} ?trans5;
LEA R2, P0, R0, UR10, 0x2 ?WAIT4_END_GROUP;
LEA.HI.X R3, R0.reuse, UR11, R3, 0x2, P0 ?trans2;
IADD3 R0, PT, PT, R0, UR6, RZ ?WAIT3_END_GROUP;
STG.E desc[UR8][R2.64], R4 &rd=0x1 ?trans2;
ISETP.GE.AND P0, PT, R0, UR7, PT ?WAIT13_END_GROUP;
@!P0 BRA 0xb0 &req={1} ?trans5;
EXIT ?trans5;
LDCU UR4, c[0x0][0x388] &wr=0x0 ?trans1;
UMOV UR5, URZ ?trans2;
I2F.U64.RP R10, UR4 &req={0} &wr=0x0 ?trans2;
MUFU.RCP R10, R10 &req={0} &wr=0x0 ?trans2;
IADD3 R6, PT, PT, R10, 0x1ffffffe, RZ &req={0} ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2I.U64.TRUNC R6, R6 &wr=0x0 ?trans2;
IMAD.WIDE.U32 R8, R6, UR4, RZ &req={0} ?WAIT4_END_GROUP;
IMAD R9, R7, UR4, R9 ?trans1;
IADD3 R11, P0, PT, RZ, -R8, RZ ?WAIT4_END_GROUP;
IADD3.X R13, PT, PT, RZ, ~R9, RZ, P0, !PT ?trans1;
IMAD.HI.U32 R8, R6, R11, RZ ?trans1;
MOV R9, R6 ?WAIT3_END_GROUP;
IMAD R15, R7, R13.reuse, RZ ?trans2;
IMAD.WIDE.U32 R8, P0, R6, R13, R8 ?WAIT4_END_GROUP;
IMAD.HI.U32 R13, R7, R13, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R8, P1, R7, R11, R8 ?WAIT5_END_GROUP;
IADD3 R9, P2, PT, R15, R8, RZ ?trans2;
IADD3.X R8, PT, PT, R13, R7, RZ, P0, !PT ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R6, R9, UR4, RZ ?trans1;
IADD3.X R11, PT, PT, RZ, RZ, R8, P2, P1 ?trans2;
IADD3 R13, P0, PT, RZ, -R6, RZ ?WAIT3_END_GROUP;
IMAD R6, R11, UR4, R7 ?trans2;
IMAD.HI.U32 R8, R9, R13, RZ ?WAIT3_END_GROUP;
IADD3.X R10, PT, PT, RZ, ~R6, RZ, P0, !PT ?trans1;
ISETP.GE.AND P0, PT, R5, RZ, PT ?trans1;
IADD3 R6, P3, PT, RZ, -R4, RZ ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R8, P1, R9, R10, R8 ?trans1;
IADD3.X R7, PT, PT, RZ, ~R5, RZ, P3, !PT ?WAIT3_END_GROUP;
IMAD.HI.U32 R9, P2, R11, R13, R8 ?WAIT4_END_GROUP;
IMAD R8, R11.reuse, R10, RZ ?trans1;
@!P0 MOV R4, R6 ?trans1;
IMAD.HI.U32 R10, R11, R10, RZ ?trans1;
@!P0 MOV R5, R7 ?WAIT3_END_GROUP;
HFMA2 R7, -RZ, RZ, 0, 0 ?trans1;
IADD3 R9, P3, PT, R8, R9, RZ ?trans2;
IADD3.X R11, PT, PT, R10, R11, RZ, P1, !PT ?WAIT3_END_GROUP;
IMAD.HI.U32 R6, R9, R4, RZ ?trans1;
IADD3.X R11, PT, PT, RZ, RZ, R11, P3, P2 ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R6, R5, R9, R6 ?WAIT4_END_GROUP;
IMAD.HI.U32 R8, R5, R11, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R7, P1, R4, R11, R6 ?WAIT4_END_GROUP;
IMAD R10, R5, R11, RZ ?trans1;
IADD3.X R6, PT, PT, R8, RZ, RZ, P1, !PT ?WAIT4_END_GROUP;
IADD3 R7, P1, PT, R10, R7, RZ ?WAIT4_END_GROUP;
IADD3.X R9, PT, PT, RZ, R6, RZ, P1, !PT ?trans1;
IMAD.WIDE.U32 R6, R7, UR4, RZ ?WAIT4_END_GROUP;
IMAD R7, R9, UR4, R7 ?WAIT5_END_GROUP;
IADD.64 R4, R4, -R6 ?WAIT6_END_GROUP;
ISETP.GE.U64.AND P1, PT, R4, UR4, PT ?WAIT14_END_GROUP;
@P1 IADD.64 R4, R4, -UR4 ?WAIT6_END_GROUP;
ISETP.GE.U64.AND P1, PT, R4, UR4, PT ?WAIT14_END_GROUP;
@P1 IADD.64 R4, R4, -UR4 ?WAIT5_END_GROUP;
IADD3 R6, P1, PT, RZ, -R4, RZ ?WAIT4_END_GROUP;
IADD3.X R7, PT, PT, RZ, ~R5, RZ, P1, !PT ?trans1;
ISETP.NE.S64.AND P1, PT, RZ, UR4, PT ?trans2;
@!P0 MOV R4, R6 ?trans2;
@!P0 MOV R5, R7 ?WAIT5_END_GROUP;
SEL.64 R4, R4, -0x1, P1 ?trans2;
HFMA2 R5, -RZ, RZ, 0, 0 ?WAIT4_END_GROUP;
MOV R6, R4 ?trans1;
MOV R4, R2 ?WAIT4_END_GROUP;
RET.REL.NODEC R4 0x0 ?trans5;
BRA 0x6e0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: pattern(int*, int)
_Z7patternPii:
s_load_b32 s4, s[0:1], 0x8
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s4, v0
s_cbranch_execz .LBB0_3
v_cvt_f32_ubyte0_e32 v1, 0
v_cvt_f32_u32_e32 v2, s4
s_clause 0x2
s_load_b32 s5, s[0:1], 0x1c
s_load_b32 s6, s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x0
s_mov_b32 s1, 0
v_fmamk_f32 v1, v1, 0x4f800000, v2
s_delay_alu instid0(VALU_DEP_1)
v_rcp_f32_e32 v1, v1
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s5, 0xffff
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x5f7ffffc, v1
s_mul_i32 s5, s6, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v2, 0x2f800000, v1
v_trunc_f32_e32 v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmamk_f32 v1, v3, 0xcf800000, v1
v_cvt_u32_f32_e32 v3, v3
v_cvt_u32_f32_e32 v2, v1
.LBB0_2:
s_sub_u32 s0, 0, s4
s_subb_u32 s6, 0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mul_hi_u32 v1, s0, v2
v_mul_lo_u32 v4, s0, v3
v_mul_lo_u32 v5, s6, v2
v_add_nc_u32_e32 v1, v1, v4
v_mul_lo_u32 v4, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v1, v1, v5
v_mul_hi_u32 v5, v2, v4
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v6, v2, v1
v_mul_hi_u32 v7, v2, v1
v_mul_hi_u32 v8, v3, v4
v_mul_lo_u32 v4, v3, v4
v_mul_hi_u32 v9, v3, v1
v_mul_lo_u32 v1, v3, v1
v_add_co_u32 v5, vcc_lo, v5, v6
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, v5, v4
v_add_co_ci_u32_e32 v4, vcc_lo, v6, v8, vcc_lo
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, v4, v1
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, v2, v1
v_add_co_ci_u32_e32 v6, vcc_lo, v3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v4, s0, v1
v_mul_lo_u32 v7, s6, v1
v_mul_lo_u32 v5, s0, v6
v_mul_lo_u32 v9, s0, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v8, v4, v5
v_mad_i64_i32 v[4:5], null, 0x4d, v0, 0
v_mul_hi_u32 v13, v6, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v7, v8, v7
v_mul_hi_u32 v8, v1, v9
v_mul_lo_u32 v9, v6, v9
v_ashrrev_i32_e32 v12, 31, v5
v_mul_lo_u32 v10, v1, v7
v_mul_hi_u32 v11, v1, v7
v_mul_hi_u32 v14, v6, v7
v_mul_lo_u32 v7, v6, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v8, vcc_lo, v8, v10
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, v8, v9
v_add_co_ci_u32_e32 v8, vcc_lo, v10, v13, vcc_lo
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v14, vcc_lo
v_add_co_u32 v4, vcc_lo, v4, v12
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, v8, v7
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v10, v4, v12
v_add_co_u32 v1, vcc_lo, v1, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v11, vcc_lo, v6, v8, vcc_lo
v_xor_b32_e32 v13, v5, v12
v_mul_hi_u32 v14, v10, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[4:5], null, v10, v11, 0
v_mad_u64_u32 v[6:7], null, v13, v1, 0
v_mad_u64_u32 v[8:9], null, v13, v11, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, v14, v4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, v1, v6
v_add_co_ci_u32_e32 v1, vcc_lo, v4, v7, vcc_lo
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, v1, v8
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, s4, v1, 0
v_mov_b32_e32 v1, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v4, vcc_lo, v10, v4
v_mad_u64_u32 v[5:6], null, s4, v7, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_co_ci_u32_e32 v1, vcc_lo, v13, v5, vcc_lo
v_sub_co_u32 v5, vcc_lo, v4, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_subrev_co_ci_u32_e32 v6, vcc_lo, 0, v1, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s4, v5
v_cndmask_b32_e64 v7, 0, -1, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s4, v4
v_cndmask_b32_e64 v8, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v6
s_delay_alu instid0(VALU_DEP_4)
v_cndmask_b32_e32 v6, -1, v7, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v1
v_subrev_nc_u32_e32 v7, s4, v5
v_ashrrev_i32_e32 v1, 31, v0
v_cndmask_b32_e32 v8, -1, v8, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v5, v5, v7, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v6, v4, v5, vcc_lo
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_add_nc_u32_e32 v0, s5, v0
v_xor_b32_e32 v1, v6, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_le_i32_e32 vcc_lo, s4, v0
v_add_co_u32 v4, s0, s2, v4
s_delay_alu instid0(VALU_DEP_3)
v_sub_nc_u32_e32 v1, v1, v12
v_add_co_ci_u32_e64 v5, s0, s3, v5, s0
s_or_b32 s1, vcc_lo, s1
global_store_b32 v[4:5], v1, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| pattern | 2,644 | 3,299 | stackv2-00000-of-00015 |
// Demangled: torture(int*, int*, int*, int)
Function : _Z7torturePiS_S_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
LDCU UR6, c[0x0][0x360] &wr=0x1 ?trans7;
LDC R2, c[0x0][0x370] &wr=0x1 ?trans1;
S2R R0, SR_TID.X &wr=0x2 ?trans1;
BSSY.RECONVERGENT B0, 0x350 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x3 ?trans1;
HFMA2 R13, -RZ, RZ, 0, 0 ?WAIT4_END_GROUP;
LDC R3, c[0x0][0x398] &wr=0x4 ?trans1;
IMAD R2, R2, UR6, RZ &req={1} ?WAIT4_END_GROUP;
IMAD R3, R2, -0x3, R3 &req={4} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, R3, PT &req={2} ?WAIT13_END_GROUP;
@P0 BRA 0x340 &req={3,0} ?trans5;
BSSY.RECONVERGENT B1, 0x300 ?trans1;
CS2R R12, SRZ ?trans1;
MOV R25, RZ ?trans1;
MOV R22, RZ ?trans1;
MOV R21, RZ ?trans1;
CS2R R10, SRZ ?trans1;
MOV R14, RZ ?trans1;
MOV R5, R0 ?WAIT7_END_GROUP;
LDC.64 R6, c[0x0][0x380] &wr=0x0 ?trans1;
IADD3 R19, PT, PT, R2, R5, R2 ?WAIT4_END_GROUP;
IADD3 R15, PT, PT, R2, R19, RZ ?WAIT3_END_GROUP;
LDC.64 R8, c[0x0][0x388] &wr=0x1 ?trans1;
IMAD.WIDE R16, R5, 0x4, R6 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE R18, R19, 0x4, R6 ?WAIT4_END_GROUP;
IMAD.WIDE R4, R2, 0x4, R16 ?trans2;
LDG.E.CONSTANT R17, desc[UR4][R16.64] &wr=0x1 ?trans2;
IMAD.WIDE R6, R15, 0x4, R6 ?trans2;
LDG.E.CONSTANT R19, desc[UR4][R18.64] &wr=0x2 ?trans4;
LDG.E.CONSTANT R5, desc[UR4][R4.64] &wr=0x3 ?trans4;
LDG.E.CONSTANT R7, desc[UR4][R6.64] &wr=0x4 ?trans1;
IADD3 R12, PT, PT, R12, R21, RZ &req={5} ?WAIT2_END_GROUP;
IADD3 R11, PT, PT, R11, R22, RZ ?trans2;
IADD3 R10, PT, PT, R10, R25, RZ ?trans2;
IADD3 R14, PT, PT, R14, R13, RZ ?trans1;
IMAD.WIDE R20, R17, 0x4, R8 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE R24, R19, 0x4, R8.reuse &req={2} ?trans2;
LDG.E.CONSTANT R21, desc[UR4][R20.64] &rd=0x0 &wr=0x5 ?trans2;
IMAD.WIDE R22, R5, 0x4, R8.reuse &req={3} ?trans2;
LDG.E.CONSTANT R25, desc[UR4][R24.64] &rd=0x0 &wr=0x5 ?trans2;
IMAD.WIDE R8, R7, 0x4, R8 &req={4} ?trans2;
LDG.E.CONSTANT R22, desc[UR4][R22.64] &rd=0x0 &wr=0x5 ?trans4;
LDG.E.CONSTANT R13, desc[UR4][R8.64] &rd=0x0 &wr=0x5 ?trans1;
IADD3 R5, PT, PT, R2, R15, RZ ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R5, R3, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x140 &req={0} ?trans5;
BSYNC.RECONVERGENT B1 ?trans5;
IADD3 R10, PT, PT, R11, R10, R14 ?WAIT4_END_GROUP;
IADD3 R10, PT, PT, R21, R10, R12 &req={5} ?WAIT4_END_GROUP;
IADD3 R10, PT, PT, R25, R10, R22 ?WAIT4_END_GROUP;
IADD3 R13, PT, PT, R13, R10, RZ ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
S2R R5, SR_CTAID.X &wr=0x0 ?trans1;
LDC.64 R2, c[0x0][0x390] &wr=0x1 ?trans1;
IMAD R5, R5, UR6, R0 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R2, R5, 0x4, R2 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R13 ?trans1;
EXIT ?trans5;
BRA 0x3b0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: torture(int*, int*, int*, int)
_Z7torturePiS_S_i:
s_clause 0x3
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x20
s_load_b32 s6, s[0:1], 0x18
s_load_b64 s[4:5], s[0:1], 0x10
v_mov_b32_e32 v1, 0
s_mov_b32 s11, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s8, s3, s10
s_mul_i32 s12, s8, 3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_sub_i32 s13, s6, s12
v_cmpx_gt_i32_e64 s13, v0
s_cbranch_execz .LBB1_4
s_load_b128 s[0:3], s[0:1], 0x0
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v6, 0
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v8, 0
v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v10, 0
v_mov_b32_e32 v1, v0
s_ashr_i32 s9, s8, 31
s_lshl_b32 s14, s8, 1
s_mov_b32 s16, 0
s_lshl_b64 s[6:7], s[8:9], 2
s_add_i32 s8, s8, s8
.LBB1_2:
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v11, s14, v1
v_add_nc_u32_e32 v13, s12, v1
s_waitcnt vmcnt(2)
v_add_nc_u32_e32 v4, v4, v9
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v5, v5, v8
v_lshlrev_b64 v[15:16], 2, v[1:2]
v_ashrrev_i32_e32 v12, 31, v11
v_ashrrev_i32_e32 v14, 31, v13
v_add_nc_u32_e32 v3, v3, v10
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v6, v6, v7
v_add3_u32 v1, s8, s8, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v15, vcc_lo, s0, v15
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_ci_u32_e32 v16, vcc_lo, s1, v16, vcc_lo
v_lshlrev_b64 v[13:14], 2, v[13:14]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v17, vcc_lo, v15, s6
v_add_co_ci_u32_e32 v18, vcc_lo, s7, v16, vcc_lo
v_add_co_u32 v11, vcc_lo, s0, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s1, v12, vcc_lo
v_add_co_u32 v13, vcc_lo, s0, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s1, v14, vcc_lo
s_clause 0x3
global_load_b32 v15, v[15:16], off
global_load_b32 v17, v[17:18], off
global_load_b32 v11, v[11:12], off
global_load_b32 v13, v[13:14], off
s_waitcnt vmcnt(3)
v_ashrrev_i32_e32 v16, 31, v15
s_waitcnt vmcnt(2)
v_ashrrev_i32_e32 v18, 31, v17
s_waitcnt vmcnt(1)
v_ashrrev_i32_e32 v12, 31, v11
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[8:9], 2, v[15:16]
v_lshlrev_b64 v[15:16], 2, v[17:18]
v_lshlrev_b64 v[10:11], 2, v[11:12]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[12:13], 2, v[13:14]
v_add_co_u32 v8, vcc_lo, s2, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
v_add_co_u32 v14, vcc_lo, s2, v15
v_add_co_ci_u32_e32 v15, vcc_lo, s3, v16, vcc_lo
v_add_co_u32 v16, vcc_lo, s2, v10
v_add_co_ci_u32_e32 v17, vcc_lo, s3, v11, vcc_lo
v_add_co_u32 v11, vcc_lo, s2, v12
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v13, vcc_lo
s_clause 0x3
global_load_b32 v10, v[8:9], off
global_load_b32 v9, v[14:15], off
global_load_b32 v8, v[16:17], off
global_load_b32 v7, v[11:12], off
v_cmp_le_i32_e32 vcc_lo, s13, v1
s_or_b32 s16, vcc_lo, s16
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s16
s_cbranch_execnz .LBB1_2
s_or_b32 exec_lo, exec_lo, s16
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v1, v1, v10, v9
v_add3_u32 v1, v1, v8, v5
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v1, v1, v4, v3
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s10, v[0:1]
v_mov_b32_e32 v3, 0
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_store_b32 v[2:3], v1, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| torture | 1,529 | 2,144 | stackv2-00000-of-00015 |
// Demangled: torture2(int*, int*, int*, int)
Function : _Z8torture2PiS_S_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans1;
LDCU UR7, c[0x0][0x398] &wr=0x1 ?trans1;
BSSY.RECONVERGENT B2, 0xeb0 ?trans1;
HFMA2 R24, -RZ, RZ, 0, 0 ?trans1;
LDCU UR6, c[0x0][0x360] &wr=0x2 ?trans3;
LDC R21, c[0x0][0x370] &wr=0x3 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x4 ?trans1;
ISETP.GE.AND P0, PT, R0, UR7, PT &req={1} ?WAIT13_END_GROUP;
@P0 BRA 0xea0 &req={4,2} ?trans5;
IMAD R21, R21, UR6, RZ &req={3} ?trans1;
BSSY.RECONVERGENT B1, 0xdc0 ?trans1;
MOV R24, RZ ?trans2;
I2F.U32.RP R7, R21 &wr=0x1 ?trans1;
IADD3 R4, PT, PT, R21.reuse, R0, RZ ?trans2;
IADD3 R9, PT, PT, RZ, -R21, RZ ?trans1;
ISETP.NE.U32.AND P2, PT, R21, RZ, PT ?trans2;
ISETP.GE.AND P0, PT, R4.reuse, UR7, PT ?trans1;
VIMNMX.S32 R5, R4, UR7, !PT ?WAIT4_END_GROUP;
SEL R6, RZ, 0x1, P0 ?trans1;
MUFU.RCP R7, R7 &req={1} &wr=0x1 ?trans4;
IADD3 R4, PT, PT, R5, -R4, -R6 ?trans2;
IADD3 R2, PT, PT, R7, 0xffffffe, RZ &req={1} ?WAIT4_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R3, R2 &rd=0x1 &wr=0x2 ?trans2;
MOV R2, RZ &req={1} ?trans1;
IMAD R9, R9, R3, RZ &req={2} ?WAIT4_END_GROUP;
IMAD.HI.U32 R3, R3, R9, R2 ?WAIT6_END_GROUP;
IMAD.HI.U32 R3, R3, R4, RZ ?WAIT5_END_GROUP;
IADD3 R2, PT, PT, -R3, RZ, RZ ?WAIT5_END_GROUP;
IMAD R4, R21, R2, R4 ?trans1;
MOV R2, R0 ?WAIT4_END_GROUP;
ISETP.GE.U32.AND P0, PT, R4, R21, PT ?WAIT13_END_GROUP;
@P0 IADD3 R4, PT, PT, -R21, R4, RZ ?trans2;
@P0 IADD3 R3, PT, PT, R3, 0x1, RZ ?WAIT3_END_GROUP;
ISETP.GE.U32.AND P1, PT, R4, R21, PT ?WAIT13_END_GROUP;
@P1 IADD3 R3, PT, PT, R3, 0x1, RZ ?trans2;
@!P2 LOP3.LUT R3, RZ, R21, RZ, 0x33, !PT ?WAIT4_END_GROUP;
IADD3 R3, PT, PT, R6, R3, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R3.reuse, 0x3, PT ?trans1;
IADD3 R3, PT, PT, R3, 0x1, RZ ?WAIT4_END_GROUP;
LOP3.LUT R23, R3, 0x3, RZ, 0xc0, !PT ?WAIT8_END_GROUP;
@!P0 BRA 0xdb0 ?trans5;
LOP3.LUT R3, R3, 0xfffffffc, RZ, 0xc0, !PT ?trans1;
BSSY.RELIABLE B0, 0xc20 ?trans1;
MOV R24, RZ ?trans1;
MOV R2, R0 ?trans1;
IADD3 R20, PT, PT, -R3, RZ, RZ ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R20, RZ, PT ?WAIT13_END_GROUP;
@P0 BRA 0xc10 ?trans5;
IADD3 R3, PT, PT, -R20, RZ, RZ ?trans1;
BSSY.RECONVERGENT B3, 0x8d0 ?trans1;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x8 ?WAIT3_END_GROUP;
ISETP.GT.AND P1, PT, R3, 0xc, PT ?WAIT13_END_GROUP;
@!P1 BRA 0x8c0 ?trans5;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x80 ?WAIT13_END_GROUP;
LDC.64 R6, c[0x0][0x380] &wr=0x1 ?trans1;
IADD3 R4, PT, PT, R21, R2, R21 ?WAIT4_END_GROUP;
IADD3 R4, PT, PT, R21, R4, R21 ?trans1;
IMAD.WIDE R18, R2, 0x4, R6 &req={1} ?WAIT3_END_GROUP;
IADD3 R2, PT, PT, R21, R4, R21 ?trans1;
IMAD.WIDE R32, R4, 0x4, R6 ?WAIT3_END_GROUP;
IADD3 R2, PT, PT, R21.reuse, R2, R21 ?trans1;
LDG.E.CONSTANT R14, desc[UR4][R18.64] &rd=0x1 &wr=0x2 ?trans1;
IMAD.WIDE R26, R21.reuse, 0x4, R18 ?trans2;
IADD3 R22, PT, PT, R21.reuse, R2, R21 ?trans1;
LDG.E.CONSTANT R25, desc[UR4][R32.64] &wr=0x3 ?trans1;
IMAD.WIDE R4, R21, 0x4, R32 ?WAIT3_END_GROUP;
LDG.E.CONSTANT R15, desc[UR4][R26.64] &wr=0x4 ?trans1;
IMAD.WIDE R8, R21, 0x4, R26 ?WAIT4_END_GROUP;
IMAD.WIDE R10, R2, 0x4, R6 ?trans1;
IADD3 R22, PT, PT, R21.reuse, R22, R21 ?trans1;
LDG.E.CONSTANT R17, desc[UR4][R8.64] &wr=0x5 ?trans2;
IMAD.WIDE R36, R21.reuse, 0x4, R8 ?trans2;
LDG.E.CONSTANT R27, desc[UR4][R4.64] &rd=0x0 &wr=0x3 ?trans2;
IMAD.WIDE R2, R21.reuse, 0x4, R4 ?trans2;
LDG.E.CONSTANT R37, desc[UR4][R36.64] &wr=0x3 ?trans2;
IMAD.WIDE R12, R21, 0x4, R10 ?WAIT2_END_GROUP;
LDG.E.CONSTANT R29, desc[UR4][R2.64] &wr=0x3 ?trans2;
IMAD.WIDE R6, R22, 0x4, R6 ?trans2;
LDG.E.CONSTANT R33, desc[UR4][R10.64] &rd=0x0 &wr=0x3 ?trans2;
IMAD.WIDE R30, R21.reuse, 0x4, R2 ?trans2;
LDG.E.CONSTANT R35, desc[UR4][R12.64] &wr=0x3 ?trans2;
IMAD.WIDE R18, R21, 0x4, R12 &req={1} ?WAIT2_END_GROUP;
LDG.E.CONSTANT R31, desc[UR4][R30.64] &wr=0x3 ?trans2;
IMAD.WIDE R4, R21.reuse, 0x4, R6 &req={0} ?trans1;
LDC.64 R10, c[0x0][0x388] &wr=0x2 ?trans1;
LDG.E.CONSTANT R26, desc[UR4][R18.64] &wr=0x3 ?trans2;
IMAD.WIDE R8, R21.reuse, 0x4, R18 ?trans2;
LDG.E.CONSTANT R28, desc[UR4][R6.64] &rd=0x0 &wr=0x3 ?trans2;
IMAD.WIDE R2, R21, 0x4, R4 ?WAIT2_END_GROUP;
LDG.E.CONSTANT R9, desc[UR4][R8.64] &wr=0x3 ?trans4;
LDG.E.CONSTANT R5, desc[UR4][R4.64] &wr=0x3 ?trans1;
IMAD.WIDE R6, R21, 0x4, R2 &req={0} ?WAIT3_END_GROUP;
LDG.E.CONSTANT R3, desc[UR4][R2.64] &wr=0x3 ?trans4;
LDG.E.CONSTANT R30, desc[UR4][R6.64] &rd=0x3 &wr=0x3 ?trans1;
IMAD.WIDE R12, R14, 0x4, R10 &req={2} ?WAIT5_END_GROUP;
LDG.E.CONSTANT R8, desc[UR4][R12.64] &rd=0x0 &wr=0x2 ?trans1;
IMAD.WIDE R14, R15, 0x4, R10 &req={4} ?WAIT4_END_GROUP;
IMAD.WIDE R16, R17, 0x4, R10 &req={5} ?WAIT4_END_GROUP;
IMAD.WIDE R6, R27, 0x4, R10.reuse &req={3} ?trans2;
LDG.E.CONSTANT R16, desc[UR4][R16.64] &wr=0x3 ?trans2;
IMAD.WIDE R18, R37, 0x4, R10.reuse ?trans2;
LDG.E.CONSTANT R7, desc[UR4][R6.64] &wr=0x4 ?trans2;
IMAD.WIDE R36, R25, 0x4, R10.reuse ?trans2;
LDG.E.CONSTANT R25, desc[UR4][R14.64] &rd=0x1 &wr=0x2 ?trans2;
IMAD.WIDE R12, R29, 0x4, R10 &req={0} ?WAIT2_END_GROUP;
LDG.E.CONSTANT R19, desc[UR4][R18.64] &wr=0x3 ?trans2;
IMAD.WIDE R32, R33, 0x4, R10.reuse ?trans2;
LDG.E.CONSTANT R2, desc[UR4][R36.64] &rd=0x0 &wr=0x4 ?trans2;
IMAD.WIDE R14, R31, 0x4, R10.reuse &req={1} ?trans2;
LDG.E.CONSTANT R12, desc[UR4][R12.64] &wr=0x5 ?trans2;
IMAD.WIDE R34, R35, 0x4, R10 ?WAIT2_END_GROUP;
LDG.E.CONSTANT R31, desc[UR4][R14.64] &rd=0x1 &wr=0x5 ?trans2;
IMAD.WIDE R26, R26, 0x4, R10.reuse ?trans2;
LDG.E.CONSTANT R32, desc[UR4][R32.64] &wr=0x5 ?trans2;
IMAD.WIDE R36, R9, 0x4, R10.reuse &req={0} ?trans2;
LDG.E.CONSTANT R35, desc[UR4][R34.64] &wr=0x5 ?trans2;
IMAD.WIDE R28, R28, 0x4, R10 ?WAIT2_END_GROUP;
LDG.E.CONSTANT R26, desc[UR4][R26.64] &wr=0x5 ?trans2;
IMAD.WIDE R4, R5, 0x4, R10.reuse ?trans2;
LDG.E.CONSTANT R37, desc[UR4][R36.64] &wr=0x5 ?trans2;
IMAD.WIDE R14, R3, 0x4, R10.reuse &req={1} ?trans2;
LDG.E.CONSTANT R28, desc[UR4][R28.64] &wr=0x5 ?trans2;
IMAD.WIDE R10, R30, 0x4, R10 ?WAIT2_END_GROUP;
LDG.E.CONSTANT R4, desc[UR4][R4.64] &wr=0x5 ?trans4;
LDG.E.CONSTANT R15, desc[UR4][R14.64] &wr=0x5 ?trans4;
LDG.E.CONSTANT R10, desc[UR4][R10.64] &wr=0x5 ?trans1;
IADD3 R20, PT, PT, R20, 0x10, RZ ?WAIT5_END_GROUP;
ISETP.GE.AND P1, PT, R20, -0xc, PT ?trans1;
IADD3 R8, PT, PT, R25, R8, R24 &req={2} ?WAIT4_END_GROUP;
IADD3 R8, PT, PT, R19, R16, R8 &req={3} ?WAIT4_END_GROUP;
IADD3 R2, PT, PT, R7, R2, R8 &req={4} ?WAIT4_END_GROUP;
IADD3 R2, PT, PT, R31, R12, R2 &req={5} ?WAIT4_END_GROUP;
IADD3 R2, PT, PT, R35, R32, R2 ?WAIT4_END_GROUP;
IADD3 R37, PT, PT, R37, R26, R2 ?trans2;
IADD3 R2, PT, PT, R21.reuse, R22, R21 ?trans2;
IADD3 R4, PT, PT, R4, R28, R37 ?trans2;
IADD3 R2, PT, PT, R21, R2, R21 ?trans2;
IADD3 R24, PT, PT, R10, R15, R4 ?trans1;
@!P1 BRA 0x370 ?trans6;
BSYNC.RECONVERGENT B3 ?trans5;
IADD3 R3, PT, PT, -R20, RZ, RZ ?trans1;
BSSY.RECONVERGENT B3, 0xbe0 ?trans4;
ISETP.GT.AND P1, PT, R3, 0x4, PT ?WAIT13_END_GROUP;
@!P1 BRA 0xbd0 ?trans5;
LDC.64 R14, c[0x0][0x380] &wr=0x1 ?trans1;
IADD3 R6, PT, PT, R21, R2, R21 ?trans1;
IMAD.WIDE R4, R2, 0x4, R14 &req={1} ?WAIT3_END_GROUP;
IADD3 R2, PT, PT, R21.reuse, R6, R21 ?trans2;
LDG.E.CONSTANT R3, desc[UR4][R4.64] &rd=0x1 &wr=0x2 ?trans1;
IMAD.WIDE R6, R21, 0x4, R4 ?WAIT4_END_GROUP;
IMAD.WIDE R14, R2, 0x4, R14 ?trans1;
LDG.E.CONSTANT R9, desc[UR4][R6.64] &rd=0x2 &wr=0x3 ?trans3;
IMAD.WIDE R10, R21.reuse, 0x4, R6 ?trans1;
LDC.64 R4, c[0x0][0x388] &req={1} &wr=0x2 ?trans3;
IMAD.WIDE R16, R21.reuse, 0x4, R14 ?trans2;
LDG.E.CONSTANT R15, desc[UR4][R14.64] &wr=0x4 ?trans2;
IMAD.WIDE R12, R21, 0x4, R10 ?WAIT2_END_GROUP;
LDG.E.CONSTANT R11, desc[UR4][R10.64] &wr=0x5 ?trans2;
IMAD.WIDE R18, R21.reuse, 0x4, R16 ?trans2;
LDG.E.CONSTANT R13, desc[UR4][R12.64] &wr=0x5 ?trans2;
IMAD.WIDE R26, R21, 0x4, R18 ?trans2;
LDG.E.CONSTANT R17, desc[UR4][R16.64] &wr=0x5 ?trans4;
LDG.E.CONSTANT R19, desc[UR4][R18.64] &wr=0x5 ?trans4;
LDG.E.CONSTANT R27, desc[UR4][R26.64] &wr=0x5 ?trans1;
IMAD.WIDE R6, R3, 0x4, R4 &req={2} ?WAIT4_END_GROUP;
IMAD.WIDE R8, R9, 0x4, R4.reuse &req={3} ?trans2;
LDG.E.CONSTANT R7, desc[UR4][R6.64] &wr=0x2 ?trans4;
LDG.E.CONSTANT R8, desc[UR4][R8.64] &wr=0x2 ?trans1;
IMAD.WIDE R14, R15, 0x4, R4 &req={4} ?WAIT4_END_GROUP;
IMAD.WIDE R10, R11, 0x4, R4.reuse &req={5} ?trans2;
LDG.E.CONSTANT R14, desc[UR4][R14.64] &wr=0x3 ?trans2;
IMAD.WIDE R12, R13, 0x4, R4.reuse ?trans2;
LDG.E.CONSTANT R10, desc[UR4][R10.64] &wr=0x4 ?trans2;
IMAD.WIDE R16, R17, 0x4, R4.reuse ?trans2;
LDG.E.CONSTANT R12, desc[UR4][R12.64] &wr=0x4 ?trans2;
IMAD.WIDE R18, R19, 0x4, R4 ?WAIT2_END_GROUP;
LDG.E.CONSTANT R16, desc[UR4][R16.64] &wr=0x3 ?trans2;
IMAD.WIDE R4, R27, 0x4, R4 ?trans2;
LDG.E.CONSTANT R18, desc[UR4][R18.64] &wr=0x5 ?trans4;
LDG.E.CONSTANT R4, desc[UR4][R4.64] &wr=0x5 ?trans1;
IADD3 R2, PT, PT, R21, R2, R21 ?trans2;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x80 ?WAIT2_END_GROUP;
IADD3 R20, PT, PT, R20, 0x8, RZ ?trans2;
IADD3 R2, PT, PT, R21, R2, R21 ?trans2;
IADD3 R7, PT, PT, R8, R7, R24 &req={2} ?WAIT4_END_GROUP;
IADD3 R7, PT, PT, R12, R10, R7 &req={4} ?WAIT4_END_GROUP;
IADD3 R7, PT, PT, R16, R14, R7 &req={3} ?WAIT4_END_GROUP;
IADD3 R24, PT, PT, R4, R18, R7 &req={5} ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B3 ?trans5;
ISETP.NE.OR P0, PT, R20, RZ, P0 ?WAIT13_END_GROUP;
@!P0 BREAK.RELIABLE B0 ?trans5;
@!P0 BRA 0xdb0 ?trans5;
BSYNC.RELIABLE B0 ?trans5;
LDC.64 R4, c[0x0][0x380] &wr=0x1 ?trans8;
LDC.64 R6, c[0x0][0x388] &wr=0x2 ?trans1;
IMAD.WIDE R4, R2, 0x4, R4 &req={1} ?WAIT5_END_GROUP;
LDG.E.CONSTANT R9, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE R10, R21, 0x4, R4 ?WAIT5_END_GROUP;
LDG.E.CONSTANT R13, desc[UR4][R10.64] &wr=0x3 ?trans1;
IMAD.WIDE R14, R21, 0x4, R10 ?WAIT5_END_GROUP;
LDG.E.CONSTANT R17, desc[UR4][R14.64] &wr=0x4 ?trans1;
IMAD.WIDE R18, R21, 0x4, R14 ?WAIT6_END_GROUP;
LDG.E.CONSTANT R19, desc[UR4][R18.64] &wr=0x5 ?trans1;
IMAD.WIDE R8, R9, 0x4, R6 &req={2} ?WAIT4_END_GROUP;
IMAD.WIDE R12, R13, 0x4, R6.reuse &req={3} ?trans2;
LDG.E.CONSTANT R9, desc[UR4][R8.64] &wr=0x2 ?trans2;
IMAD.WIDE R16, R17, 0x4, R6.reuse &req={4} ?trans2;
LDG.E.CONSTANT R12, desc[UR4][R12.64] &wr=0x2 ?trans4;
LDG.E.CONSTANT R17, desc[UR4][R16.64] &wr=0x3 ?trans1;
IMAD.WIDE R6, R19, 0x4, R6 &req={5} ?WAIT6_END_GROUP;
LDG.E.CONSTANT R6, desc[UR4][R6.64] &wr=0x3 ?trans1;
IADD3 R20, PT, PT, R20, 0x4, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R20, RZ, PT ?trans1;
IADD3 R2, PT, PT, R21, R2, R21 ?WAIT4_END_GROUP;
IADD3 R2, PT, PT, R21, R2, R21 ?trans2;
IADD3 R24, PT, PT, R12, R9, R24 &req={2} ?WAIT4_END_GROUP;
IADD3 R24, PT, PT, R6, R17, R24 &req={3} ?trans2;
@P0 BRA 0xc20 ?trans5;
BSYNC.RECONVERGENT B1 ?trans5;
ISETP.NE.AND P0, PT, R23, RZ, PT ?WAIT13_END_GROUP;
@!P0 BRA 0xea0 ?trans5;
LDC.64 R4, c[0x0][0x380] &wr=0x1 ?trans1;
IADD3 R23, PT, PT, -R23, RZ, RZ ?WAIT7_END_GROUP;
LDC.64 R8, c[0x0][0x388] &wr=0x2 ?trans2;
IMAD.WIDE R6, R2, 0x4, R4 &req={1} ?WAIT6_END_GROUP;
LDG.E.CONSTANT R7, desc[UR4][R6.64] &wr=0x3 ?trans1;
IADD3 R23, PT, PT, R23, 0x1, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R23, RZ, PT ?trans1;
IMAD.WIDE R10, R7, 0x4, R8 &req={3,2} ?WAIT6_END_GROUP;
LDG.E.CONSTANT R11, desc[UR4][R10.64] &wr=0x2 ?trans1;
IADD3 R2, PT, PT, R21, R2, RZ ?trans2;
IADD3 R24, PT, PT, R11, R24, RZ &req={2} ?WAIT3_END_GROUP;
@P0 BRA 0xe10 ?trans5;
BSYNC.RECONVERGENT B2 ?trans5;
WARPSYNC.ALL ?trans5;
NOP ?trans1;
S2R R5, SR_CTAID.X &wr=0x1 ?trans1;
LDC.64 R2, c[0x0][0x390] &wr=0x2 ?trans1;
IMAD R5, R5, UR6, R0 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R2, R5, 0x4, R2 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R24 ?trans1;
EXIT ?trans5;
BRA 0xf30;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: torture2(int*, int*, int*, int)
_Z8torture2PiS_S_i:
s_clause 0x2
s_load_b32 s11, s[0:1], 0x18
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x10
v_mov_b32_e32 v3, 0
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_mov_b32 s12, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s6, 0xffff
v_cmpx_gt_i32_e64 s11, v0
s_cbranch_execz .LBB2_4
s_load_b32 s6, s[2:3], 0x0
s_load_b128 s[0:3], s[0:1], 0x0
v_dual_mov_b32 v4, v0 :: v_dual_lshlrev_b32 v1, 2, v0
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s6, s6, s10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s0, s0, v1
v_add_co_ci_u32_e64 v2, null, s1, 0, s0
s_ashr_i32 s7, s6, 31
s_mov_b32 s1, 0
s_lshl_b64 s[8:9], s[6:7], 2
.LBB2_2:
global_load_b32 v5, v[1:2], off
v_add_nc_u32_e32 v4, s6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s0, s11, v4
s_or_b32 s1, s0, s1
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, s8
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v5, v3
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB2_2
s_or_b32 exec_lo, exec_lo, s1
.LBB2_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s12
v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| torture2 | 6,559 | 1,055 | stackv2-00000-of-00015 |
// Demangled: funkcja(int*)
Function : _Z7funkcjaPi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R5, SR_TID.X &wr=0x1 ?trans7;
S2UR UR6, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans7;
LDC R0, c[0x0][0x360] &wr=0x1 ?trans8;
LDC.64 R2, c[0x0][0x380] &wr=0x3 ?trans1;
IMAD R5, R0, UR6, R5 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE R2, R5, 0x4, R2 &req={3} ?WAIT5_END_GROUP;
LDG.E R6, desc[UR4][R2.64] &req={2} &rd=0x1 &wr=0x5 ?trans1;
HFMA2 R0, -RZ, RZ, 0, 0 &req={0} ?WAIT7_END_GROUP;
IADD3 R4, PT, PT, R0, R0, RZ ?trans1;
MOV R5, RZ ?trans1;
MOV R10, RZ ?WAIT7_END_GROUP;
IADD3 R6, PT, PT, R5, R6, RZ &req={5} ?trans2;
IADD3 R10, PT, PT, R10, 0x10, RZ ?WAIT3_END_GROUP;
IMAD.HI R7, R6, 0x77975b9, RZ ?trans2;
ISETP.NE.AND P0, PT, R10, 0x7d0, PT ?WAIT3_END_GROUP;
SHF.R.U32.HI R8, RZ, 0x1f, R7 ?WAIT4_END_GROUP;
LEA.HI.SX32 R7, R7, R8, 0x1e ?WAIT5_END_GROUP;
IMAD R7, R7, -0x89, R6 ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R7, R0, R5 ?WAIT5_END_GROUP;
IMAD.HI R6, R7, 0x77975b9, RZ ?WAIT5_END_GROUP;
SHF.R.U32.HI R9, RZ, 0x1f, R6 ?WAIT4_END_GROUP;
LEA.HI.SX32 R6, R6, R9, 0x1e ?WAIT5_END_GROUP;
IMAD R6, R6, -0x89, R7 ?WAIT5_END_GROUP;
IADD3 R6, PT, PT, R6, R4, R5 ?WAIT5_END_GROUP;
IMAD.HI R7, R6, 0x77975b9, RZ ?WAIT5_END_GROUP;
SHF.R.U32.HI R8, RZ, 0x1f, R7 ?WAIT4_END_GROUP;
LEA.HI.SX32 R7, R7, R8, 0x1e ?trans1;
IMAD R8, R0, 0x3, R5 ?WAIT4_END_GROUP;
IMAD R7, R7, -0x89, R6 ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R7, R8, RZ ?WAIT5_END_GROUP;
IMAD.HI R6, R7, 0x77975b9, RZ ?WAIT5_END_GROUP;
SHF.R.U32.HI R9, RZ, 0x1f, R6 ?WAIT4_END_GROUP;
LEA.HI.SX32 R6, R6, R9, 0x1e ?trans1;
IMAD R9, R0, 0x4, R5 ?WAIT4_END_GROUP;
IMAD R6, R6, -0x89, R7 ?WAIT5_END_GROUP;
IADD3 R6, PT, PT, R6, R9, RZ ?WAIT5_END_GROUP;
IMAD.HI R7, R6, 0x77975b9, RZ ?WAIT5_END_GROUP;
SHF.R.U32.HI R8, RZ, 0x1f, R7 ?WAIT4_END_GROUP;
LEA.HI.SX32 R7, R7, R8, 0x1e ?trans1;
IMAD R8, R0, 0x5, R5 ?WAIT4_END_GROUP;
IMAD R7, R7, -0x89, R6 ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R7, R8, RZ ?WAIT5_END_GROUP;
IMAD.HI R6, R7, 0x77975b9, RZ ?WAIT5_END_GROUP;
SHF.R.U32.HI R9, RZ, 0x1f, R6 ?WAIT4_END_GROUP;
LEA.HI.SX32 R6, R6, R9, 0x1e ?trans1;
IMAD R9, R0, 0x6, R5 ?WAIT4_END_GROUP;
IMAD R6, R6, -0x89, R7 ?WAIT5_END_GROUP;
IADD3 R6, PT, PT, R6, R9, RZ ?WAIT5_END_GROUP;
IMAD.HI R7, R6, 0x77975b9, RZ ?WAIT5_END_GROUP;
SHF.R.U32.HI R8, RZ, 0x1f, R7 ?WAIT4_END_GROUP;
LEA.HI.SX32 R7, R7, R8, 0x1e ?trans1;
IMAD R8, R0, 0x7, R5 ?WAIT4_END_GROUP;
IMAD R7, R7, -0x89, R6 ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R7, R8, RZ ?WAIT5_END_GROUP;
IMAD.HI R6, R7, 0x77975b9, RZ ?WAIT5_END_GROUP;
SHF.R.U32.HI R9, RZ, 0x1f, R6 ?WAIT4_END_GROUP;
LEA.HI.SX32 R6, R6, R9, 0x1e ?trans1;
IMAD R9, R0, 0x8, R5 ?WAIT4_END_GROUP;
IMAD R6, R6, -0x89, R7 ?WAIT5_END_GROUP;
IADD3 R6, PT, PT, R6, R9, RZ ?WAIT5_END_GROUP;
IMAD.HI R7, R6, 0x77975b9, RZ ?WAIT5_END_GROUP;
SHF.R.U32.HI R8, RZ, 0x1f, R7 ?WAIT4_END_GROUP;
LEA.HI.SX32 R7, R7, R8, 0x1e ?trans1;
IMAD R8, R0, 0x9, R5 ?WAIT4_END_GROUP;
IMAD R7, R7, -0x89, R6 ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R7, R8, RZ ?WAIT5_END_GROUP;
IMAD.HI R6, R7, 0x77975b9, RZ ?WAIT5_END_GROUP;
SHF.R.U32.HI R9, RZ, 0x1f, R6 ?WAIT4_END_GROUP;
LEA.HI.SX32 R6, R6, R9, 0x1e ?trans1;
IMAD R9, R0, 0xa, R5 ?WAIT4_END_GROUP;
IMAD R6, R6, -0x89, R7 ?WAIT5_END_GROUP;
IADD3 R6, PT, PT, R6, R9, RZ ?WAIT5_END_GROUP;
IMAD.HI R7, R6, 0x77975b9, RZ ?WAIT5_END_GROUP;
SHF.R.U32.HI R8, RZ, 0x1f, R7 ?WAIT4_END_GROUP;
LEA.HI.SX32 R7, R7, R8, 0x1e ?trans1;
IMAD R8, R0, 0xb, R5 ?WAIT4_END_GROUP;
IMAD R7, R7, -0x89, R6 ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R7, R8, RZ ?WAIT5_END_GROUP;
IMAD.HI R6, R7, 0x77975b9, RZ ?WAIT5_END_GROUP;
SHF.R.U32.HI R9, RZ, 0x1f, R6 ?WAIT4_END_GROUP;
LEA.HI.SX32 R6, R6, R9, 0x1e ?trans1;
IMAD R9, R0, 0xc, R5 ?WAIT4_END_GROUP;
IMAD R6, R6, -0x89, R7 ?WAIT5_END_GROUP;
IADD3 R6, PT, PT, R6, R9, RZ ?WAIT5_END_GROUP;
IMAD.HI R7, R6, 0x77975b9, RZ ?WAIT5_END_GROUP;
SHF.R.U32.HI R8, RZ, 0x1f, R7 ?WAIT4_END_GROUP;
LEA.HI.SX32 R7, R7, R8, 0x1e ?trans1;
IMAD R8, R0, 0xd, R5 ?WAIT4_END_GROUP;
IMAD R7, R7, -0x89, R6 ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R7, R8, RZ ?WAIT5_END_GROUP;
IMAD.HI R6, R7, 0x77975b9, RZ ?WAIT5_END_GROUP;
SHF.R.U32.HI R9, RZ, 0x1f, R6 ?WAIT4_END_GROUP;
LEA.HI.SX32 R6, R6, R9, 0x1e ?trans1;
IMAD R9, R0, 0xe, R5 ?WAIT4_END_GROUP;
IMAD R6, R6, -0x89, R7 ?WAIT5_END_GROUP;
IADD3 R6, PT, PT, R6, R9, RZ ?WAIT5_END_GROUP;
IMAD.HI R7, R6, 0x77975b9, RZ ?WAIT5_END_GROUP;
SHF.R.U32.HI R8, RZ, 0x1f, R7 ?WAIT4_END_GROUP;
LEA.HI.SX32 R7, R7, R8, 0x1e ?trans1;
IMAD R8, R0.reuse, 0xf, R5.reuse ?trans2;
IMAD R5, R0, 0x10, R5 ?trans2;
IMAD R7, R7, -0x89, R6 ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R7, R8, RZ ?WAIT5_END_GROUP;
IMAD.HI R6, R7, 0x77975b9, RZ ?WAIT5_END_GROUP;
SHF.R.U32.HI R9, RZ, 0x1f, R6 ?WAIT4_END_GROUP;
LEA.HI.SX32 R6, R6, R9, 0x1e ?WAIT5_END_GROUP;
IMAD R6, R6, -0x89, R7 ?trans1;
@P0 BRA 0xd0 ?trans6;
IADD3 R0, PT, PT, R0, 0x1, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R0, 0x7d0, PT ?WAIT13_END_GROUP;
@P0 BRA 0xa0 ?trans5;
STG.E desc[UR4][R2.64], R6 ?trans1;
EXIT ?trans5;
BRA 0x730;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: funkcja(int*)
_Z7funkcjaPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s0, 0
global_load_b32 v2, v[0:1], off
.LBB0_1:
s_mov_b32 s1, 0
s_movk_i32 s2, 0x7d0
.LBB0_2:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, s1, v2
s_add_i32 s2, s2, -1
s_add_i32 s1, s1, s0
s_cmp_eq_u32 s2, 0
v_mul_hi_i32 v3, 0x77975b9, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v4, 31, v3
v_ashrrev_i32_e32 v3, 2, v3
v_add_nc_u32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, 0x89, v3
v_sub_nc_u32_e32 v2, v2, v3
s_cbranch_scc0 .LBB0_2
s_add_i32 s0, s0, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_eq_i32 s0, 0x7d0
s_cbranch_scc0 .LBB0_1
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| funkcja | 2,907 | 747 | stackv2-00000-of-00015 |
// Demangled: add(float*, float*, int*)
Function : _Z3addPfS_Pi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x390] &wr=0x1 ?trans2;
LDG.E R5, desc[UR4][R4.64] &req={1} &wr=0x2 ?trans6;
S2UR UR6, SR_CTAID.X &wr=0x1 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans7;
LDC R2, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R2, R2, UR6, R3 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R2, R5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R4, c[0x0][0x380] &wr=0x0 ?trans2;
IMAD.WIDE R4, R2, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR4][R4.64] &wr=0x2 ?trans1;
BSSY.RECONVERGENT B0, 0x810 ?trans1;
SHF.R.S32.HI R3, RZ, 0x1f, R2 ?trans1;
FMUL R6, R0.reuse, 0.63661974668502807617 &req={2} ?trans1;
FSETP.GE.AND P0, PT, |R0|, 105615, PT ?WAIT3_END_GROUP;
F2I.NTZ R9, R6 &wr=0x0 ?trans2;
I2FP.F32.S32 R7, R9 &req={0} ?WAIT5_END_GROUP;
FFMA R8, R7, -1.5707962512969970703, R0 ?WAIT4_END_GROUP;
FFMA R8, R7, -7.5497894158615963534e-08, R8 ?WAIT4_END_GROUP;
FFMA R7, R7, -5.3903029534742383927e-15, R8 ?trans1;
@!P0 BRA 0x800 ?trans6;
FSETP.NEU.AND P0, PT, |R0|, +INF , PT ?WAIT13_END_GROUP;
@!P0 FMUL R7, RZ, R0 ?trans1;
@!P0 MOV R9, RZ ?trans1;
@!P0 BRA 0x800 ?trans6;
LDCU.64 UR6, c[0x4][URZ] &wr=0x0 ?trans1;
IMAD.SHL.U32 R6, R0, 0x100, RZ ?trans2;
HFMA2 R10, -RZ, RZ, 0, 0 ?trans1;
MOV.64 R4, RZ ?trans2;
MOV.64 R8, RZ ?WAIT3_END_GROUP;
LOP3.LUT R11, R6, 0x80000000, RZ, 0xfc, !PT ?trans1;
MOV.64 R6, UR6 &req={0} ?WAIT8_END_GROUP;
LDG.E.CONSTANT R12, desc[UR4][R6.64] &rd=0x0 &wr=0x2 ?trans1;
IADD3 R10, PT, PT, R10, 0x1, RZ ?trans1;
ISETP.EQ.AND P1, PT, R8.reuse, RZ, PT ?trans1;
ISETP.EQ.AND P2, PT, R8.reuse, 0x4, PT ?trans1;
ISETP.EQ.AND P3, PT, R8.reuse, 0x8, PT ?trans1;
ISETP.EQ.AND P4, PT, R8.reuse, 0xc, PT ?trans1;
ISETP.EQ.AND P5, PT, R8.reuse, 0x10, PT ?trans1;
ISETP.EQ.AND P6, PT, R8, 0x14, PT ?trans1;
ISETP.NE.AND P0, PT, R10, 0x6, PT ?trans1;
IADD.64 R8, R8, 0x4 ?trans2;
IADD.64 R6, R6, 0x4 &req={0} ?WAIT2_END_GROUP;
IMAD.WIDE.U32 R4, R12, R11, R4 &req={2} ?WAIT3_END_GROUP;
@P1 MOV R13, R4.reuse ?trans1;
@P2 MOV R14, R4.reuse ?trans1;
@P3 MOV R15, R4.reuse ?trans1;
@P4 MOV R16, R4.reuse ?trans1;
@P5 MOV R17, R4.reuse ?trans1;
@P6 MOV R18, R4 ?trans1;
MOV R4, R5 ?trans1;
MOV R5, RZ ?trans1;
@P0 BRA 0x220 ?trans6;
SHF.R.U32.HI R6, RZ, 0x17, R0 ?trans1;
BSSY.RECONVERGENT B1, 0x670 ?trans3;
LOP3.LUT R7, R6.reuse, 0xe0, RZ, 0xc0, !PT ?trans2;
LOP3.LUT P5, RZ, R6, 0x1f, RZ, 0xc0, !PT ?trans2;
IADD3 R7, PT, PT, R7, -0x80, RZ ?WAIT4_END_GROUP;
SHF.R.U32.HI R7, RZ, 0x5, R7 ?WAIT5_END_GROUP;
IMAD.U32 R11, R7, -0x4, RZ ?WAIT5_END_GROUP;
ISETP.EQ.AND P2, PT, R11.reuse, -0x18, PT ?trans1;
ISETP.EQ.AND P3, PT, R11.reuse, -0x14, PT ?trans1;
ISETP.EQ.AND P1, PT, R11.reuse, -0x10, PT ?trans1;
ISETP.EQ.AND P0, PT, R11.reuse, -0xc, PT ?trans1;
ISETP.EQ.AND P6, PT, R11.reuse, -0x4, PT ?trans1;
ISETP.EQ.AND P4, PT, R11, RZ, PT ?WAIT8_END_GROUP;
@P2 MOV R7, R13.reuse ?trans1;
ISETP.EQ.AND P2, PT, R11.reuse, -0x8, PT ?trans1;
@P3 MOV R8, R13 ?trans1;
@P3 MOV R7, R14 ?trans1;
ISETP.EQ.AND P3, PT, R11, 0x4, PT ?trans1;
@P1 MOV R7, R15.reuse ?trans1;
@P0 MOV R7, R16 ?trans1;
@P1 MOV R8, R14 ?trans1;
@P0 MOV R8, R15 ?WAIT6_END_GROUP;
@P2 MOV R7, R17.reuse ?trans1;
@P6 MOV R7, R18 ?trans1;
@P4 MOV R7, R4 ?trans1;
@P2 MOV R8, R16 ?trans1;
@P6 MOV R8, R17 ?trans1;
@P4 MOV R8, R18 ?trans1;
@P3 MOV R8, R4 ?trans1;
MOV R9, R7 ?trans1;
@!P5 BRA 0x660 ?trans6;
@P1 MOV R10, R13 ?trans1;
@P0 MOV R10, R14 ?trans1;
ISETP.EQ.AND P0, PT, R11, 0x8, PT ?trans1;
LOP3.LUT R6, R6, 0x1f, RZ, 0xc0, !PT ?trans1;
@P2 MOV R10, R15 ?trans1;
@P6 MOV R10, R16 ?trans1;
@P4 MOV R10, R17 ?trans1;
@P3 MOV R10, R18 ?trans1;
IADD3 R5, PT, PT, -R6, 0x20, RZ ?trans2;
SHF.L.U32 R9, R9, R6, RZ ?WAIT2_END_GROUP;
SHF.L.U32 R6, R8, R6, RZ ?trans2;
SHF.R.U32.HI R8, RZ, R5, R8 ?trans1;
@P0 MOV R10, R4 ?WAIT3_END_GROUP;
IADD3 R9, PT, PT, R9, R8, RZ ?trans2;
SHF.R.U32.HI R5, RZ, R5, R10 ?WAIT4_END_GROUP;
IADD3 R8, PT, PT, R6, R5, RZ ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B1 ?trans5;
IMAD.SHL.U32 R10, R9, 0x4, RZ ?trans1;
SHF.L.U32.HI R11, R8.reuse, 0x2, R9.reuse ?trans1;
IMAD.SHL.U32 R6, R8, 0x4, RZ ?trans1;
SHF.R.U32.HI R9, RZ, 0x1e, R9 ?trans1;
UMOV.64 UR6, 0x3bf921fb54442d19 ?trans1;
SHF.R.S32.HI R4, RZ, 0x1f, R10 ?trans1;
ISETP.GE.AND P0, PT, R0, RZ, PT ?trans1;
LOP3.LUT R0, R11, R0, RZ, 0x3c, !PT ?trans2;
LOP3.LUT R6, R4.reuse, R6, RZ, 0x3c, !PT ?trans2;
LOP3.LUT R7, R4, R11, RZ, 0x3c, !PT ?WAIT2_END_GROUP;
LEA.HI R9, R10, R9, RZ, 0x1 ?trans2;
I2F.F64.S64 R4, R6 &wr=0x0 ?trans1;
ISETP.GE.AND P1, PT, R0, RZ, PT ?trans1;
IADD3 R0, PT, PT, -R9, RZ, RZ ?WAIT5_END_GROUP;
@!P0 MOV R9, R0 ?WAIT15_END_GROUP;
NOP ?WAIT12_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R4, R4, UR6 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2F.F32.F64 R4, R4 &req={0} &wr=0x0 ?trans2;
FSEL R7, -R4, R4, !P1 &req={0} ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
LOP3.LUT R4, R9, 0x1, RZ, 0xc0, !PT ?trans1;
HFMA2 R0, -RZ, RZ, 0.487060546875, -0.0625 ?trans2;
FMUL R5, R7, R7 ?trans1;
LDCU.64 UR6, c[0x0][0x388] &wr=0x0 ?trans1;
MOV R6, 0x3effffff ?trans1;
ISETP.NE.U32.AND P0, PT, R4, 0x1, PT ?trans1;
FFMA R0, R5, R0, -0.0013887860113754868507 ?trans1;
MOV R4, 0x3d2aaabb ?trans1;
LOP3.LUT P1, RZ, R9, 0x2, RZ, 0xc0, !PT ?trans2;
FSEL R9, -R6, -0.16666662693023681641, !P0 ?trans1;
FSEL R0, R0, -0.00019574658654164522886, !P0 ?trans1;
FSEL R4, R4, 0.0083327032625675201416, !P0 ?WAIT5_END_GROUP;
FFMA R4, R5, R0, R4 ?trans1;
FSEL R0, R7, 1, P0 ?WAIT3_END_GROUP;
FFMA R9, R5.reuse, R4, R9 ?trans1;
LEA R4, P0, R2, UR6, 0x2 &req={0} ?trans1;
FFMA R5, R5, R0, RZ ?WAIT4_END_GROUP;
FFMA R9, R5, R9, R0 ?trans1;
LEA.HI.X R5, R2, UR7, R3, 0x2, P0 ?WAIT3_END_GROUP;
@P1 FADD R9, RZ, -R9 ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x970;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: add(float*, float*, int*)
_Z3addPfS_Pi:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s4, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[2:3], 0x0
s_and_b32 s3, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_6
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v3, 0x7fffffff, v2
v_cmp_ngt_f32_e64 s0, 0x48000000, |v2|
s_and_saveexec_b32 s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s4, exec_lo, s1
s_cbranch_execz .LBB0_3
s_mov_b32 s0, 0x7fffff
v_mov_b32_e32 v6, 0
v_and_or_b32 v14, v3, s0, 0x800000
v_lshrrev_b32_e32 v11, 23, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[4:5], null, 0xfe5163ab, v14, 0
v_add_nc_u32_e32 v12, 0xffffff88, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_lt_u32_e32 vcc_lo, 63, v12
v_mad_u64_u32 v[7:8], null, 0x3c439041, v14, v[5:6]
v_cndmask_b32_e64 v13, 0, 0xffffffc0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v5, v8
v_add_nc_u32_e32 v13, v13, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[8:9], null, 0xdb629599, v14, v[5:6]
v_cmp_lt_u32_e64 s0, 31, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v15, 0, 0xffffffe0, s0
v_dual_mov_b32 v5, v9 :: v_dual_cndmask_b32 v4, v8, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v15, v15, v13
v_mad_u64_u32 v[9:10], null, 0xf534ddc0, v14, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e64 s1, 31, v15
v_mov_b32_e32 v5, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v7, v9, v7, vcc_lo
v_mad_u64_u32 v[10:11], null, 0xfc2757d1, v14, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v4, v7, v4, s0
v_mov_b32_e32 v5, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[11:12], null, 0x4e441529, v14, v[5:6]
v_mov_b32_e32 v5, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[12:13], null, 0xa2f9836e, v14, v[5:6]
v_cndmask_b32_e64 v5, 0, 0xffffffe0, s1
v_dual_cndmask_b32 v6, v11, v9 :: v_dual_add_nc_u32 v5, v5, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v12, v12, v10 :: v_dual_cndmask_b32 v11, v13, v11
v_cndmask_b32_e32 v10, v10, v8, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v9, v12, v6, s0
v_cndmask_b32_e64 v11, v11, v12, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v6, v6, v10, s0
v_sub_nc_u32_e32 v12, 32, v5
v_cndmask_b32_e64 v10, v10, v7, s0
v_cndmask_b32_e64 v11, v11, v9, s1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v9, v9, v6, s1
v_cndmask_b32_e64 v6, v6, v10, s1
v_cndmask_b32_e64 v4, v10, v4, s1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v13, v11, v9, v12
v_alignbit_b32 v8, v9, v6, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v5, v13, v11, vcc_lo
v_alignbit_b32 v11, v6, v4, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v7, v8, v9, vcc_lo
v_bfe_u32 v8, v5, 29, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v6, v11, v6, vcc_lo
v_alignbit_b32 v9, v5, v7, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v10, 0, v8
v_alignbit_b32 v7, v7, v6, 30
v_alignbit_b32 v4, v6, v4, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v9, v9, v10
v_xor_b32_e32 v6, v7, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v4, v4, v10
v_clz_i32_u32_e32 v11, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v11, 32, v11
v_sub_nc_u32_e32 v7, 31, v11
v_lshlrev_b32_e32 v13, 23, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_alignbit_b32 v9, v9, v6, v7
v_alignbit_b32 v4, v6, v4, v7
v_lshrrev_b32_e32 v7, 29, v5
v_alignbit_b32 v6, v9, v4, 9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v7, 31, v7
v_lshrrev_b32_e32 v9, 9, v9
v_clz_i32_u32_e32 v10, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v12, 0.5, v7
v_min_u32_e32 v10, 32, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v12, v12, v13
v_sub_nc_u32_e32 v14, 31, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v4, v6, v4, v14
v_or_b32_e32 v6, v9, v12
v_add_lshl_u32 v9, v10, v11, 23
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v4, 9, v4
v_mul_f32_e32 v10, 0x3fc90fda, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v4, v4, v9
v_fma_f32 v9, 0x3fc90fda, v6, -v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 0x33000000, v4
v_fmamk_f32 v6, v6, 0x33a22168, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v4, v4, v7
v_fmac_f32_e32 v6, 0x3fc90fda, v4
v_lshrrev_b32_e32 v5, 30, v5
s_delay_alu instid0(VALU_DEP_1)
v_dual_add_f32 v4, v10, v6 :: v_dual_add_nc_u32 v5, v8, v5
.LBB0_3:
s_and_not1_saveexec_b32 s0, s4
v_mul_f32_e64 v4, 0x3f22f983, |v2|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v5, v4
v_fma_f32 v4, 0xbfc90fda, v5, |v2|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v4, v5, 0xb3a22168, v4
v_fmamk_f32 v4, v5, 0xa7c234c4, v4
v_cvt_i32_f32_e32 v5, v5
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_dual_mul_f32 v6, v4, v4 :: v_dual_and_b32 v9, 1, v5
s_mov_b32 s0, 0xb94c1982
s_mov_b32 s1, 0x37d75334
v_xor_b32_e32 v3, v3, v2
v_fmaak_f32 v7, s0, v6, 0x3c0881c4
v_cmp_eq_u32_e32 vcc_lo, 0, v9
v_lshlrev_b32_e32 v5, 30, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmaak_f32 v7, v6, v7, 0xbe2aaa9d
v_fmaak_f32 v8, s1, v6, 0xbab64f3b
v_and_b32_e32 v5, 0x80000000, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f32_e32 v7, v6, v7
v_fmaak_f32 v8, v6, v8, 0x3d2aabf7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v4, v4, v7
v_fmaak_f32 v8, v6, v8, 0xbf000004
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, v6, v8, 1.0
v_cndmask_b32_e32 v4, v6, v4, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v2, 0x1f8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor3_b32 v3, v3, v5, v4
v_cndmask_b32_e32 v2, 0x7fc00000, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| add | 3,462 | 4,472 | stackv2-00000-of-00015 |
// Demangled: dotproduct(float*, float*, float*)
Function : _Z10dotproductPfS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R6, SR_TID.X &wr=0x1 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x2 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x3 ?trans1;
S2R R7, SR_CTAID.X &wr=0x1 ?trans6;
LDC.64 R4, c[0x0][0x388] &wr=0x4 ?trans1;
LEA R7, R7, R6, 0x5 &req={1} ?WAIT5_END_GROUP;
IMAD.WIDE.U32 R2, R7, 0x4, R2 &req={2} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x4, R4 &req={4} ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={3} &wr=0x2 ?trans4;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.NE.AND P0, PT, R6, RZ, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R7, R6, UR4, 0x2 ?trans1;
FMUL R0, R2, R5 &req={2} ?WAIT5_END_GROUP;
STS [R7], R0 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT &req={0} ?trans5;
BPT.TRAP 0x1 &req={1} ?trans5;
BRA 0x150;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: dotproduct(float*, float*, float*)
_Z10dotproductPfS_S_:
s_load_b128 s[4:7], s[2:3], 0x0
v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v3, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v1, s15, 5, v3
v_lshlrev_b64 v[4:5], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
s_mov_b32 s4, 0
global_load_b32 v1, v[6:7], off
global_load_b32 v4, v[4:5], off
v_lshlrev_b32_e32 v5, 2, v3
s_mov_b32 s5, exec_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v1, v1, v4
ds_store_b32 v5, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v3
s_cbranch_execz .LBB0_4
s_load_b64 s[6:7], s[0:1], 0x4
v_bfe_u32 v1, v0, 10, 10
s_load_b64 s[0:1], s[2:3], 0x10
v_bfe_u32 v0, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_u32_u24_e32 v1, s7, v1
s_lshr_b32 s5, s6, 16
s_mul_i32 s5, s5, s7
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[4:5], null, s5, v3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_lshl_u32 v1, v4, v0, 2
v_add_nc_u32_e32 v0, 0x80, v1
ds_store_b32 v1, v2 offset:128
.LBB0_2:
v_mov_b32_e32 v1, s4
s_add_i32 s4, s4, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_lg_i32 s4, 0x80
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v1
s_cbranch_scc1 .LBB0_2
s_load_b32 s2, s[0:1], 0x0
v_mov_b32_e32 v1, 0
ds_store_b32 v0, v2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, s2, v2
global_store_b32 v1, v3, s[0:1]
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| dotproduct | 557 | 990 | stackv2-00000-of-00015 |
// Demangled: hillis_steele(float*, float*, float*, int)
Function : _Z13hillis_steelePfS_S_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R9, SR_CTAID.X &wr=0x1 ?trans7;
LDC R6, c[0x0][0x360] &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x398] &wr=0x2 ?trans1;
HFMA2 R0, -RZ, RZ, 0, 0 ?trans1;
S2R R11, SR_TID.X &wr=0x1 ?trans1;
LDCU.64 UR10, c[0x0][0x358] &wr=0x3 ?trans1;
IMAD R5, R9, R6, R11 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R5, UR4, PT &req={2} ?WAIT5_END_GROUP;
ISETP.EQ.OR P0, PT, R5, RZ, P0 ?WAIT13_END_GROUP;
@!P0 LDC.64 R2, c[0x0][0x388] &wr=0x1 ?trans2;
@!P0 IMAD.WIDE R2, R5, 0x4, R2 &req={1} ?WAIT5_END_GROUP;
@!P0 LDG.E R0, desc[UR10][R2.64+-0x4] &req={3} &wr=0x2 ?trans1;
S2UR UR6, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GE.U32.AND P0, PT, R6, 0x2, PT ?trans1;
ULEA UR6, UR6, UR4, 0x18 &req={1} ?WAIT3_END_GROUP;
UMOV UR4, URZ ?WAIT3_END_GROUP;
LEA R7, R11, UR6, 0x2 ?WAIT5_END_GROUP;
STS [R7], R0 &req={2} &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 BRA 0x330 &req={0} ?trans5;
UMOV UR5, URZ ?trans1;
UMOV UR8, 0x1 ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R11, UR8, PT ?trans1;
UIADD3 UR4, UPT, UPT, -UR5, 0x1, URZ ?trans1;
BSSY.RECONVERGENT B0, 0x2e0 ?trans11;
@!P0 BRA 0x270 &req={1,0} ?trans5;
IMAD R0, R6.reuse, UR5, RZ &req={1} ?trans2;
IMAD R4, R6, UR4, RZ ?WAIT3_END_GROUP;
IADD3 R2, PT, PT, R0.reuse, -UR8, R11 ?trans1;
IMAD R0, R0, 0x4, R7 ?trans1;
LEA R4, R4, R7, 0x2 ?trans2;
LEA R2, R2, UR6, 0x2 ?WAIT3_END_GROUP;
LDS R0, [R0] ?trans4;
LDS R3, [R2] &wr=0x0 ?trans2;
FADD R3, R0, R3 &req={0} ?WAIT5_END_GROUP;
STS [R4], R3 &rd=0x0 ?trans1;
BRA 0x2d0 ?trans5;
IMAD R0, R6.reuse, UR5, RZ &req={1} ?trans2;
IMAD R2, R6, UR4, RZ ?trans2;
IMAD R0, R0, 0x4, R7 ?WAIT3_END_GROUP;
LEA R3, R2, R7, 0x2 ?WAIT3_END_GROUP;
LDS R0, [R0] &wr=0x0 ?trans4;
STS [R3], R0 &req={0} &rd=0x1 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
UIADD3 UR8, UPT, UPT, UR8, UR8, URZ ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans5;
ISETP.LE.U32.AND P0, PT, R6, UR8, PT ?trans1;
UMOV UR5, UR4 ?WAIT12_END_GROUP;
@!P0 BRA 0x180 ?trans5;
IMAD R0, R6, UR4, RZ &req={1} ?trans1;
LDCU UR7, c[0x0][0x398] &wr=0x1 ?trans1;
LDC.64 R2, c[0x0][0x380] &req={0} &wr=0x0 ?trans2;
IMAD R4, R0, 0x4, R7 ?trans1;
IADD3 R0, PT, PT, R6, -0x1, RZ ?WAIT4_END_GROUP;
LDS R7, [R4] &wr=0x2 ?trans1;
ISETP.NE.AND P1, PT, R11, R0, PT ?trans1;
UIADD3 UR7, UPT, UPT, UR7, -0x1, URZ &req={1} ?WAIT6_END_GROUP;
ISETP.NE.AND P0, PT, R5.reuse, UR7, PT ?trans1;
IMAD.WIDE R2, R5, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR10][R2.64], R7 &req={2} &rd=0x0 ?trans7;
@P0 EXIT P1 ?trans5;
LDS R5, [R4] &wr=0x1 ?trans1;
LDC.64 R2, c[0x0][0x390] &req={0} &wr=0x0 ?trans2;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR10][R2.64], R5 &req={1} ?trans1;
EXIT ?trans5;
BRA 0x440;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: hillis_steele(float*, float*, float*, int)
_Z13hillis_steelePfS_S_i:
s_clause 0x3
s_load_b32 s10, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
s_mov_b32 s2, s15
v_mov_b32_e32 v4, 0
s_mov_b32 s11, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s10, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s10, v[0:1]
v_cmp_ne_u32_e32 vcc_lo, 0, v1
v_cmp_gt_i32_e64 s0, s3, v1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s1, vcc_lo, s0
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v4, v[3:4], off offset:-4
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
v_lshl_add_u32 v3, v0, 2, 0
s_mov_b64 s[0:1], src_shared_base
s_cmp_lt_u32 s10, 2
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v3
v_cndmask_b32_e32 v5, 0, v3, vcc_lo
v_cndmask_b32_e64 v6, 0, s1, vcc_lo
s_waitcnt vmcnt(0)
flat_store_b32 v[5:6], v4 dlc
s_waitcnt_vscnt null, 0x0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
s_mov_b32 s0, 1
.LBB0_4:
s_mul_i32 s7, s11, s10
s_mov_b32 s6, exec_lo
v_lshl_add_u32 v4, s7, 2, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v4
v_cndmask_b32_e32 v4, 0, v4, vcc_lo
v_cndmask_b32_e64 v5, 0, s1, vcc_lo
flat_load_b32 v4, v[4:5] glc dlc
s_waitcnt vmcnt(0)
v_cmpx_le_u32_e64 s0, v0
s_cbranch_execz .LBB0_6
v_add_nc_u32_e32 v5, s7, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v5, s0, v5
v_lshl_add_u32 v5, v5, 2, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v5
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cndmask_b32_e64 v6, 0, s1, vcc_lo
flat_load_b32 v5, v[5:6] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v4, v4, v5
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s6
s_sub_i32 s11, 1, s11
s_lshl_b32 s0, s0, 1
s_mul_i32 s6, s11, s10
s_cmp_ge_u32 s0, s10
v_lshl_add_u32 v5, s6, 2, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v5
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cndmask_b32_e64 v6, 0, s1, vcc_lo
s_waitcnt lgkmcnt(0)
flat_store_b32 v[5:6], v4 dlc
s_waitcnt_vscnt null, 0x0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_4
.LBB0_7:
s_mul_i32 s0, s11, s10
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_lshl_add_u32 v3, s0, 2, v3
s_mov_b64 s[0:1], src_shared_base
s_add_i32 s10, s10, -1
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_eq_u32_e64 s0, s3, v1
v_cmp_ne_u32_e32 vcc_lo, -1, v3
s_mov_b32 s3, 0
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
v_cndmask_b32_e64 v4, 0, s1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, s10, v0
v_add_co_u32 v0, s1, s4, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, s1, s5, v6, s1
flat_load_b32 v7, v[3:4] glc dlc
s_waitcnt vmcnt(0)
s_or_b32 s0, vcc_lo, s0
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v7, off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_9
flat_load_b32 v0, v[3:4] glc dlc
s_waitcnt vmcnt(0)
s_lshl_b64 s[0:1], s[2:3], 2
v_mov_b32_e32 v1, 0
s_add_u32 s0, s8, s0
s_addc_u32 s1, s9, s1
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| hillis_steele | 1,595 | 1,935 | stackv2-00000-of-00015 |
// Demangled: sum_kernel(float*, float*, int)
Function : _Z10sum_kernelPfS_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R9, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x390] &wr=0x2 ?trans1;
IMAD R7, R9, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R7, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x388] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x380] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x3 ?trans1;
IMAD.WIDE R4, R7, 0x4, R4 &req={2} ?WAIT5_END_GROUP;
LDG.E R7, desc[UR4][R4.64] &wr=0x3 ?trans2;
FADD R7, R2, R7 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64], R7 ?trans1;
EXIT ?trans5;
BRA 0x120;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: sum_kernel(float*, float*, int)
_Z10sum_kernelPfS_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_lshl_b64 s[0:1], s[2:3], 2
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_add_u32 s0, s6, s0
s_addc_u32 s1, s7, s1
s_load_b32 s0, s[0:1], 0x0
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v2, s0, v2
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| sum_kernel | 517 | 559 | stackv2-00000-of-00015 |
// Demangled: calculate_inner_grid(double*, double*, double*, int, int, int)
Function : _Z20calculate_inner_gridPdS_S_iii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
LDC.64 R2, c[0x0][0x398] &wr=0x1 ?trans8;
LDC R0, c[0x0][0x3a0] &wr=0x2 ?trans1;
IADD3 R9, PT, PT, R2, 0x2, RZ &req={1} ?WAIT2_END_GROUP;
IADD3 R4, PT, PT, R3, 0x2, RZ ?trans2;
IABS R12, R9 ?WAIT3_END_GROUP;
IMAD R6, R9, R4, RZ ?trans1;
IADD3 R5, PT, PT, R0, R0, RZ &req={2} ?trans1;
I2F.RP R10, R12 &wr=0x1 ?trans4;
IMAD R8, R6, R5, RZ ?trans1;
IABS R6, R9 ?WAIT4_END_GROUP;
ISETP.GE.AND P2, PT, R8, RZ, PT ?trans1;
IADD3 R13, PT, PT, RZ, -R6, RZ ?trans1;
HFMA2 R6, -RZ, RZ, 0, 0 ?trans1;
MUFU.RCP R10, R10 &req={1} &wr=0x1 ?trans2;
IADD3 R7, PT, PT, R10, 0xffffffe, RZ &req={1} ?trans2;
IABS R10, R8 ?WAIT4_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R7, R7 &wr=0x1 ?trans2;
IADD3 R11, PT, PT, RZ, -R7, RZ &req={1} ?WAIT5_END_GROUP;
IMAD R11, R11, R12, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R6, R7, R11, R6 ?trans1;
MOV R7, R10 ?trans1;
MOV R10, R13 ?trans1;
LOP3.LUT R11, RZ, R9, RZ, 0x33, !PT ?WAIT3_END_GROUP;
IMAD.HI.U32 R6, R6, R7, RZ ?WAIT4_END_GROUP;
IMAD R7, R6, R10, R7 ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R12, R7, PT ?WAIT13_END_GROUP;
@!P0 IADD3 R7, PT, PT, R7, -R12, RZ ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P1, PT, R12, R7, PT ?trans1;
IADD3 R10, PT, PT, R7, -R12, RZ ?WAIT5_END_GROUP;
SEL R10, R10, R7, !P1 ?trans1;
ISETP.NE.AND P1, PT, R9, RZ, PT ?WAIT4_END_GROUP;
@!P2 IADD3 R10, PT, PT, -R10, RZ, RZ ?WAIT5_END_GROUP;
SEL R13, R11, R10, !P1 ?WAIT5_END_GROUP;
ISETP.GE.AND P2, PT, R13.reuse, R2, PT ?trans1;
ISETP.LT.AND P3, PT, R13, 0x2, PT ?WAIT13_END_GROUP;
@P2 EXIT P3 &req={0} ?trans5;
IABS R13, R4 ?trans1;
ISETP.GE.U32.AND P2, PT, R7, R12, PT ?trans1;
LOP3.LUT R8, R8, R9, RZ, 0x3c, !PT ?trans2;
I2F.RP R2, R13 &wr=0x0 ?trans1;
@!P0 IADD3 R6, PT, PT, R6, 0x1, RZ ?trans2;
ISETP.GE.AND P0, PT, R8, RZ, PT ?WAIT7_END_GROUP;
@P2 IADD3 R6, PT, PT, R6, 0x1, RZ ?trans1;
MUFU.RCP R2, R2 &req={0} &wr=0x0 ?trans5;
@!P0 IADD3 R6, PT, PT, -R6, RZ, RZ ?WAIT5_END_GROUP;
SEL R11, R11, R6, !P1 ?trans1;
IABS R6, R4 ?WAIT4_END_GROUP;
IABS R8, R11 ?trans1;
ISETP.GE.AND P1, PT, R11, RZ, PT ?trans1;
IADD3 R7, PT, PT, R2, 0xffffffe, RZ &req={0} ?WAIT6_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R7, R7 &wr=0x0 ?trans2;
IADD3 R2, PT, PT, RZ, -R7, RZ &req={0} ?WAIT5_END_GROUP;
IMAD R9, R2, R13, RZ ?trans1;
IADD3 R2, PT, PT, RZ, -R6, RZ ?trans1;
MOV R6, RZ ?WAIT5_END_GROUP;
IMAD.HI.U32 R6, R7, R9, R6 ?trans1;
MOV R7, R8 ?WAIT5_END_GROUP;
IMAD.HI.U32 R6, R6, R7, RZ ?WAIT4_END_GROUP;
IMAD R6, R6, R2, R7 ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R13, R6, PT ?WAIT13_END_GROUP;
@!P0 IADD3 R6, PT, PT, R6, -R13, RZ ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R13, R6, PT ?WAIT13_END_GROUP;
@!P0 IADD3 R6, PT, PT, R6, -R13, RZ ?trans1;
ISETP.NE.AND P0, PT, R4, RZ, PT ?WAIT3_END_GROUP;
@!P1 IADD3 R6, PT, PT, -R6, RZ, RZ ?WAIT10_END_GROUP;
@!P0 LOP3.LUT R6, RZ, R4, RZ, 0x33, !PT ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R6.reuse, R3, PT ?trans1;
ISETP.LT.AND P1, PT, R6, 0x2, PT ?WAIT13_END_GROUP;
@P0 EXIT P1 ?trans5;
ISETP.GE.AND P0, PT, R5, R0, PT ?trans1;
ISETP.LT.AND P1, PT, R0, 0x1, PT ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x0 ?WAIT12_END_GROUP;
@P0 EXIT P1 &req={0} ?trans5;
S2R R11, SR_TID.X &wr=0x0 ?trans1;
LDC.64 R2, c[0x0][0x388] &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x0 ?trans1;
S2R R0, SR_CTAID.X &wr=0x0 ?trans6;
LDC.64 R6, c[0x0][0x380] &wr=0x2 ?trans8;
LDC.64 R8, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD R11, R0, UR4, R11 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE R2, R11, 0x8, R2 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE R6, R11.reuse, 0x8, R6 &req={2} ?trans2;
LDG.E.64 R2, desc[UR6][R2.64] &wr=0x2 ?trans4;
LDG.E.64 R6, desc[UR6][R6.64] &wr=0x4 ?trans1;
IMAD.WIDE R8, R11, 0x8, R8 &req={3} ?trans1;
DADD R4, R2, R2 &req={2} &wr=0x4 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R4, R4, -R6 &req={4} &wr=0x0 ?trans2;
STG.E.64 desc[UR6][R8.64], R4 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x5e0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: calculate_inner_grid(double*, double*, double*, int, int, int)
_Z20calculate_inner_gridPdS_S_iii:
s_load_b128 s[4:7], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s4, 2
s_add_i32 s8, s5, 2
s_ashr_i32 s3, s2, 31
s_lshl_b32 s9, s6, 1
s_add_i32 s7, s2, s3
s_mul_i32 s10, s8, s2
s_xor_b32 s7, s7, s3
s_mul_i32 s10, s10, s9
v_cvt_f32_u32_e32 v1, s7
s_sub_i32 s12, 0, s7
s_ashr_i32 s13, s10, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_add_i32 s14, s10, s13
v_rcp_iflag_f32_e32 v1, v1
s_xor_b32 s14, s14, s13
s_xor_b32 s3, s13, s3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s11, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s12, s12, s11
s_mul_hi_u32 s12, s11, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s11, s11, s12
s_mul_hi_u32 s11, s14, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mul_i32 s12, s11, s7
s_add_i32 s13, s11, 1
s_sub_i32 s12, s14, s12
s_sub_i32 s14, s12, s7
s_cmp_ge_u32 s12, s7
s_cselect_b32 s11, s13, s11
s_cselect_b32 s12, s14, s12
s_add_i32 s13, s11, 1
s_cmp_ge_u32 s12, s7
s_cselect_b32 s7, s13, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s7, s7, s3
s_sub_i32 s3, s7, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s2, s3, s2
s_sub_i32 s2, s10, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_i32 s2, 1
s_cselect_b32 s7, -1, 0
s_cmp_lt_i32 s2, s4
s_cselect_b32 s2, -1, 0
s_ashr_i32 s4, s8, 31
s_ashr_i32 s11, s3, 31
s_add_i32 s8, s8, s4
s_add_i32 s3, s3, s11
s_xor_b32 s4, s8, s4
s_xor_b32 s3, s3, s11
v_cvt_f32_u32_e32 v1, s4
s_sub_i32 s10, 0, s4
s_or_b32 s2, s7, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s8, v1
s_mul_i32 s10, s10, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s10, s8, s10
s_add_i32 s8, s8, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s8, s3, s8
s_mul_i32 s8, s8, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_sub_i32 s3, s3, s8
s_sub_i32 s7, s3, s4
s_cmp_ge_u32 s3, s4
s_cselect_b32 s3, s7, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_sub_i32 s7, s3, s4
s_cmp_ge_u32 s3, s4
s_cselect_b32 s3, s7, s3
s_xor_b32 s3, s3, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_sub_i32 s3, s3, s11
s_cmp_gt_i32 s3, 1
s_cselect_b32 s4, -1, 0
s_cmp_lt_i32 s3, s5
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_or_b32 s3, s4, s3
s_min_i32 s4, s9, 0
s_and_b32 s2, s2, s3
s_cmp_lt_i32 s4, s6
s_cselect_b32 s3, -1, 0
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_2
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[2:3], 2.0, -v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| calculate_inner_grid | 2,248 | 2,304 | stackv2-00000-of-00015 |
// Demangled: Av_Product(float*, float*, float*, int)
Function : _Z10Av_ProductPfS_S_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
LDC R0, c[0x0][0x398] &wr=0x1 ?trans1;
S2R R3, SR_CTAID.X &wr=0x2 ?trans1;
LDCU.64 UR8, c[0x0][0x358] &wr=0x3 ?trans1;
HFMA2 R13, -RZ, RZ, 0, 0 ?trans1;
S2R R2, SR_TID.X &wr=0x4 ?trans1;
ISETP.GE.AND P0, PT, R0, 0x1, PT &req={1} ?WAIT13_END_GROUP;
@!P0 BRA 0x460 &req={4,3,2,0} ?trans5;
S2UR UR7, SR_CgaCtaId &wr=0x0 ?trans1;
UMOV UR4, 0x400 ?trans1;
IMAD R33, R3, R0.reuse, RZ ?trans1;
UIADD3 UR6, UPT, UPT, UR4, 0x400, URZ ?trans1;
IMAD R31, R0, R0, RZ ?trans1;
MOV R13, RZ ?trans2;
SHF.L.U32 R33, R33, 0x8, RZ ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R33, R0, RZ ?trans1;
ULEA UR5, UR7, UR4, 0x18 &req={0} ?trans1;
ULEA UR6, UR7, UR6, 0x18 ?trans2;
UMOV UR4, URZ ?WAIT3_END_GROUP;
LEA R30, R2.reuse, UR5, 0x2 ?trans2;
LEA R28, R2, UR6, 0x2 ?WAIT7_END_GROUP;
LDCU UR7, c[0x0][0x398] &wr=0x0 ?trans1;
IADD3 R11, PT, PT, R2.reuse, UR4, RZ ?trans2;
IADD3 R8, PT, PT, R2, R33, RZ ?trans1;
MOV R9, RZ ?WAIT4_END_GROUP;
ISETP.GE.AND P0, PT, R8, R31, PT ?trans1;
ISETP.GE.AND P1, PT, R11, UR7, PT &req={0} ?WAIT12_END_GROUP;
@!P0 LDC.64 R4, c[0x0][0x380] &wr=0x0 ?trans8;
@!P1 LDC.64 R6, c[0x0][0x388] &wr=0x1 ?trans1;
@!P0 IMAD.WIDE.U32 R4, R8, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
@!P0 LDG.E R9, desc[UR8][R4.64] &wr=0x2 ?trans1;
@!P1 IMAD.WIDE.U32 R6, R11, 0x4, R6 &req={1} ?WAIT4_END_GROUP;
HFMA2 R11, -RZ, RZ, 0, 0 ?WAIT6_END_GROUP;
@!P1 LDG.E R11, desc[UR8][R6.64] &wr=0x3 ?trans1;
IADD3 R33, PT, PT, R33, 0x100, RZ ?trans1;
MOV R29, 0x20 ?WAIT4_END_GROUP;
ISETP.GE.AND P1, PT, R33, R0, PT ?trans1;
STS [R30], R9 &req={2} &rd=0x0 ?trans4;
STS [R28], R11 &req={3} &rd=0x0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans7;
LDS.128 R20, [R29+UR5+-0x20] ?trans4;
LDS.128 R24, [R29+UR6+-0x20] &wr=0x1 ?trans4;
LDS.128 R4, [R29+UR5+-0x10] ?trans4;
LDS.128 R8, [R29+UR6+-0x10] &req={0} &wr=0x0 ?trans4;
LDS.128 R16, [R29+UR6] ?trans1;
FFMA R20, R20, R24, R13 &req={1} ?WAIT3_END_GROUP;
LDS.128 R12, [R29+UR5] &wr=0x1 ?trans1;
FFMA R21, R21, R25, R20 ?WAIT4_END_GROUP;
FFMA R22, R22, R26, R21 ?WAIT4_END_GROUP;
FFMA R35, R23, R27, R22 ?trans2;
LDS.128 R20, [R29+UR5+0x10] ?trans2;
FFMA R4, R4, R8, R35 &req={0} ?trans2;
LDS.128 R24, [R29+UR6+0x10] &rd=0x0 &wr=0x2 ?trans2;
FFMA R5, R5, R9, R4 ?WAIT4_END_GROUP;
FFMA R6, R6, R10, R5 ?trans1;
IADD3 R29, PT, PT, R29, 0x40, RZ &req={0} ?WAIT3_END_GROUP;
FFMA R7, R7, R11, R6 ?trans2;
ISETP.NE.AND P0, PT, R29, 0x420, PT ?trans2;
FFMA R12, R12, R16, R7 &req={1} ?WAIT4_END_GROUP;
FFMA R13, R13, R17, R12 ?WAIT4_END_GROUP;
FFMA R14, R14, R18, R13 ?WAIT4_END_GROUP;
FFMA R15, R15, R19, R14 ?WAIT4_END_GROUP;
FFMA R20, R20, R24, R15 &req={2} ?WAIT4_END_GROUP;
FFMA R21, R21, R25, R20 ?WAIT4_END_GROUP;
FFMA R22, R22, R26, R21 ?WAIT4_END_GROUP;
FFMA R13, R23, R27, R22 ?trans1;
@P0 BRA 0x280 ?trans6;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x100, URZ ?WAIT5_END_GROUP;
@!P1 BRA 0x150 ?trans7;
LDC.64 R4, c[0x0][0x390] &wr=0x0 ?trans1;
LEA R3, R3, R2, 0x8 ?WAIT5_END_GROUP;
IMAD.WIDE.U32 R2, R3, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR8][R2.64], R13 ?trans1;
EXIT ?trans5;
BRA 0x4b0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: Av_Product(float*, float*, float*, int)
_Z10Av_ProductPfS_S_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_9
v_dual_mov_b32 v5, 0 :: v_dual_lshlrev_b32 v6, 2, v0
s_mul_i32 s3, s2, s15
v_mov_b32_e32 v2, 0
s_lshl_b32 s3, s3, 8
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v7, 0x400, v6
s_add_i32 s8, s3, s2
s_mul_i32 s9, s2, s2
s_mov_b32 s10, 0
.LBB0_2:
v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s3, v0
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s9, v3
s_cbranch_execz .LBB0_4
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v4, v[3:4], off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s11
v_add_nc_u32_e32 v1, s10, v0
v_mov_b32_e32 v3, 0
s_mov_b32 s11, exec_lo
s_waitcnt vmcnt(0)
ds_store_b32 v6, v4
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_6
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v3, v[3:4], off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s11
s_mov_b32 s11, 0
s_waitcnt vmcnt(0)
ds_store_b32 v7, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_7:
v_mov_b32_e32 v1, s11
s_add_i32 s11, s11, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_eq_i32 s11, 0x400
ds_load_2addr_stride64_b32 v[3:4], v1 offset1:4
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v5, v3, v4
s_cbranch_scc0 .LBB0_7
s_addk_i32 s3, 0x100
s_addk_i32 s10, 0x100
s_cmp_ge_i32 s3, s8
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_10
.LBB0_9:
v_mov_b32_e32 v5, 0
.LBB0_10:
v_lshl_add_u32 v0, s15, 8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| Av_Product | 1,887 | 1,274 | stackv2-00000-of-00015 |
// Demangled: ComputeLamda(float*, float*, float*, int)
Function : _Z12ComputeLamdaPfS_S_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R9, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x398] &wr=0x2 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x3 ?trans6;
LDC R6, c[0x0][0x360] &wr=0x1 ?trans8;
LDC.64 R2, c[0x0][0x380] &wr=0x4 ?trans8;
LDC.64 R4, c[0x0][0x388] &wr=0x5 ?trans1;
IMAD R7, R6, UR4, R9 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P1, PT, R7, UR5, PT &req={2} ?WAIT13_END_GROUP;
@!P1 IMAD.WIDE.U32 R2, R7, 0x4, R2 &req={4} ?WAIT4_END_GROUP;
@!P1 IMAD.WIDE.U32 R4, R7, 0x4, R4 &req={5} ?trans2;
@!P1 LDG.E R2, desc[UR6][R2.64] &req={3} &wr=0x2 ?trans4;
@!P1 LDG.E R5, desc[UR6][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GE.U32.AND P2, PT, R6, 0x2, PT ?trans1;
ISETP.NE.AND P0, PT, R9, RZ, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R0, R9, UR4, 0x2 ?trans1;
@!P1 FMUL R7, R2, R5 &req={2} ?WAIT5_END_GROUP;
@!P1 STS [R0], R7 &rd=0x1 ?trans4;
@P1 STS [R0], RZ &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P2 BRA 0x240 &req={0} ?trans5;
SHF.R.U32.HI R4, RZ, 0x1, R6 ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P1, PT, R9, R4, PT ?WAIT13_END_GROUP;
@!P1 IMAD R3, R4, 0x4, R0 ?trans1;
@!P1 LDS R2, [R0] ?trans5;
@!P1 LDS R3, [R3] &wr=0x0 ?trans2;
@!P1 FADD R5, R2, R3 &req={0} ?WAIT5_END_GROUP;
@!P1 STS [R0], R5 &rd=0x0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P1, PT, R6, 0x3, PT ?trans1;
MOV R6, R4 ?WAIT12_END_GROUP;
@P1 BRA 0x190 &req={0} ?trans5;
@P0 EXIT ?trans5;
S2UR UR5, SR_CgaCtaId &wr=0x0 ?trans1;
UMOV UR4, 0x400 ?WAIT7_END_GROUP;
LDC.64 R2, c[0x0][0x390] &wr=0x2 ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={0} ?WAIT9_END_GROUP;
LDS R5, [UR4] &wr=0x2 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R2.64], R5 &req={2} ?trans1;
EXIT ?trans5;
BRA 0x2c0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: ComputeLamda(float*, float*, float*, int)
_Z12ComputeLamdaPfS_S_i:
s_clause 0x3
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_u32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB1_2
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v3, v[3:4], off
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v3, v1
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s3
v_lshl_add_u32 v1, v0, 2, 0
s_cmp_lt_u32 s2, 2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
.LBB1_3:
buffer_gl0_inv
s_cbranch_scc1 .LBB1_7
s_lshr_b32 s3, s2, 1
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB1_6
v_lshl_add_u32 v2, s3, 2, v1
ds_load_b32 v3, v1
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s2, 4
s_mov_b32 s2, s3
s_branch .LBB1_3
.LBB1_7:
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_11
s_mov_b32 s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v0, s2, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 s3, exec_lo, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 exec_lo, s3
s_cbranch_execz .LBB1_11
s_bcnt1_i32_b32 s2, s2
s_load_b32 s3, s[0:1], 0x0
v_cvt_f32_ubyte0_e32 v1, s2
v_mov_b32_e32 v2, 0
s_mov_b32 s2, 0
ds_load_b32 v0, v2
s_waitcnt lgkmcnt(0)
v_mul_f32_e32 v3, v0, v1
v_mov_b32_e32 v1, s3
.LBB1_10:
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v0, v1, v3
global_atomic_cmpswap_b32 v0, v2, v[0:1], s[0:1] glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v0, v1
v_mov_b32_e32 v1, v0
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB1_10
.LBB1_11:
s_endpgm
| ComputeLamda | 1,114 | 1,281 | stackv2-00000-of-00015 |
// Demangled: FindNormW(float*, float*, int)
Function : _Z9FindNormWPfS_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R7, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x390] &wr=0x2 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x3 ?trans6;
LDC R4, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R5, R4, UR4, R7 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R5, UR5, PT &req={2} ?WAIT13_END_GROUP;
@!P0 LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans2;
@!P0 IMAD.WIDE.U32 R2, R5, 0x4, R2 &req={1} ?WAIT6_END_GROUP;
@!P0 LDG.E R3, desc[UR6][R2.64] &req={3} &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GE.U32.AND P1, PT, R4, 0x2, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R0, R7, UR4, 0x2 ?WAIT5_END_GROUP;
@!P0 STS [R0], R3 &req={2} ?trans4;
@P0 STS [R0], RZ ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.NE.AND P0, PT, R7, RZ, PT ?WAIT5_END_GROUP;
LDS R5, [R0] &wr=0x1 ?trans2;
FMUL R5, R5, R5 &req={1} ?WAIT5_END_GROUP;
STS [R0], R5 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P1 BRA 0x240 &req={0} ?trans5;
SHF.R.U32.HI R6, RZ, 0x1, R4 ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P1, PT, R7, R6, PT ?WAIT13_END_GROUP;
@!P1 IMAD R3, R6, 0x4, R0 ?trans1;
@!P1 LDS R2, [R0] ?trans5;
@!P1 LDS R3, [R3] &wr=0x0 ?trans2;
@!P1 FADD R5, R2, R3 &req={1,0} ?WAIT5_END_GROUP;
@!P1 STS [R0], R5 &rd=0x0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P1, PT, R4, 0x3, PT ?trans1;
MOV R4, R6 ?WAIT12_END_GROUP;
@P1 BRA 0x190 &req={0} ?trans5;
@P0 EXIT ?trans5;
S2UR UR5, SR_CgaCtaId &wr=0x0 ?trans1;
UMOV UR4, 0x400 ?WAIT7_END_GROUP;
LDC.64 R2, c[0x0][0x388] &wr=0x2 ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={0} ?WAIT9_END_GROUP;
LDS R5, [UR4] &req={1} &wr=0x2 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R2.64], R5 &req={2} ?trans1;
EXIT ?trans5;
BRA 0x2c0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: FindNormW(float*, float*, int)
_Z9FindNormWPfS_i:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s5, s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_u32_e32 vcc_lo, s5, v1
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB2_2
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v2, v[1:2], off
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s5
v_lshl_add_u32 v1, v0, 2, 0
s_cmp_lt_u32 s4, 2
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v2, v1
s_waitcnt lgkmcnt(0)
v_mul_f32_e32 v2, v2, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
.LBB2_3:
buffer_gl0_inv
s_cbranch_scc1 .LBB2_7
s_lshr_b32 s0, s4, 1
s_mov_b32 s1, exec_lo
v_cmpx_gt_u32_e64 s0, v0
s_cbranch_execz .LBB2_6
v_lshl_add_u32 v2, s0, 2, v1
ds_load_b32 v3, v1
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
.LBB2_6:
s_or_b32 exec_lo, exec_lo, s1
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s4, 4
s_mov_b32 s4, s0
s_branch .LBB2_3
.LBB2_7:
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB2_11
s_mov_b32 s0, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v0, s0, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 s1, exec_lo, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 exec_lo, s1
s_cbranch_execz .LBB2_11
s_bcnt1_i32_b32 s0, s0
s_load_b32 s1, s[2:3], 0x0
v_cvt_f32_ubyte0_e32 v1, s0
v_mov_b32_e32 v2, 0
s_mov_b32 s0, 0
ds_load_b32 v0, v2
s_waitcnt lgkmcnt(0)
v_mul_f32_e32 v3, v0, v1
v_mov_b32_e32 v1, s1
.LBB2_10:
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v0, v1, v3
global_atomic_cmpswap_b32 v0, v2, v[0:1], s[2:3] glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v0, v1
v_mov_b32_e32 v1, v0
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB2_10
.LBB2_11:
s_endpgm
| FindNormW | 1,071 | 1,242 | stackv2-00000-of-00015 |
// Demangled: NormalizeW(float*, float*, float*, int)
Function : _Z10NormalizeWPfS_S_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R2, SR_TID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x2 ?trans6;
S2UR UR4, SR_CTAID.X &wr=0x3 ?trans1;
LDCU UR5, c[0x0][0x398] &wr=0x4 ?trans1;
ISETP.NE.AND P0, PT, R2, RZ, PT &req={1} ?WAIT13_END_GROUP;
@!P0 LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans2;
@!P0 LDG.E R4, desc[UR6][R4.64] &req={2} &wr=0x2 ?trans6;
LDC R7, c[0x0][0x360] &wr=0x3 ?trans1;
@!P0 MOV R0, 0x400 ?trans1;
@!P0 S2R R3, SR_CgaCtaId &wr=0x1 ?trans1;
IMAD R2, R7, UR4, R2 &req={3} ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P1, PT, R2, UR5, PT &req={4} ?trans1;
@!P0 LEA R3, R3, R0, 0x18 &req={1} ?WAIT5_END_GROUP;
@!P0 STS [R3], R4 &req={2} &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P1 EXIT &req={0} ?trans5;
LDC.64 R4, c[0x0][0x380] &req={1} &wr=0x0 ?trans2;
IMAD.WIDE.U32 R4, R2, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR6][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x0 ?trans1;
UMOV UR4, 0x400 ?trans1;
BSSY.RECONVERGENT B0, 0x240 ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={0} ?WAIT9_END_GROUP;
LDS R3, [UR4] &wr=0x0 ?trans2;
MUFU.RCP R6, R3 &req={0} &wr=0x0 ?trans2;
FFMA R7, -R3, R6, 1 &req={0} ?WAIT4_END_GROUP;
FFMA R7, R6, R7, R6 ?trans1;
FCHK P0, R0, R3 &req={2} &wr=0x0 ?trans3;
FFMA R6, R0, R7, RZ ?WAIT4_END_GROUP;
FFMA R8, -R3, R6, R0 ?WAIT4_END_GROUP;
FFMA R7, R7, R8, R6 ?trans1;
@!P0 BRA 0x230 &req={0} ?trans6;
MOV R4, 0x230 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x280 ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
LDC.64 R4, c[0x0][0x390] &wr=0x0 ?trans2;
IMAD.WIDE.U32 R2, R2, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R7 ?trans1;
EXIT ?trans5;
SHF.R.U32.HI R6, RZ, 0x17, R3 ?trans1;
BSSY.RECONVERGENT B1, 0x8e0 ?trans1;
SHF.R.U32.HI R5, RZ, 0x17, R0 ?trans2;
LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ?trans1;
MOV R7, R0 ?trans1;
IADD3 R11, PT, PT, R6, -0x1, RZ ?trans1;
MOV R8, R3 ?trans1;
IADD3 R10, PT, PT, R5, -0x1, RZ ?WAIT3_END_GROUP;
ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ?WAIT5_END_GROUP;
ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ?WAIT13_END_GROUP;
@!P0 MOV R9, RZ ?trans1;
@!P0 BRA 0x4c0 ?trans6;
FSETP.GTU.FTZ.AND P0, PT, |R0|, +INF , PT ?trans1;
FSETP.GTU.FTZ.AND P1, PT, |R3|, +INF , PT ?WAIT5_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, PT, 0xf8, 0x8f ?WAIT13_END_GROUP;
@P0 BRA 0x8c0 ?trans5;
LOP3.LUT P0, RZ, R8, 0x7fffffff, R7, 0xc8, !PT ?WAIT13_END_GROUP;
@!P0 BRA 0x8a0 ?trans5;
FSETP.NEU.FTZ.AND P2, PT, |R0|.reuse, +INF , PT ?trans1;
FSETP.NEU.FTZ.AND P1, PT, |R3|, +INF , PT ?trans1;
FSETP.NEU.FTZ.AND P0, PT, |R0|, +INF , PT ?WAIT12_END_GROUP;
@!P1 BRA !P2, 0x8a0 ?trans5;
LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P1, PT, P1, P2, PT, 0x2f, 0xf2 ?WAIT13_END_GROUP;
@P1 BRA 0x880 ?trans5;
LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, PT, 0x2f, 0xf2 ?WAIT13_END_GROUP;
@P0 BRA 0x850 ?trans5;
ISETP.GE.AND P0, PT, R10, RZ, PT ?trans1;
ISETP.GE.AND P1, PT, R11, RZ, PT ?WAIT12_END_GROUP;
@P0 MOV R9, RZ ?trans1;
@!P0 MOV R9, 0xffffffc0 ?trans1;
@!P0 FFMA R7, R0, 1.84467440737095516160e+19, RZ ?trans1;
@!P1 FFMA R8, R3, 1.84467440737095516160e+19, RZ ?WAIT3_END_GROUP;
@!P1 IADD3 R9, PT, PT, R9, 0x40, RZ ?WAIT7_END_GROUP;
LEA R3, R6, 0xc0800000, 0x17 ?trans1;
BSSY.RECONVERGENT B2, 0x840 ?trans1;
IADD3 R5, PT, PT, R5, -0x7f, RZ ?trans2;
IADD3 R3, PT, PT, -R3, R8, RZ ?WAIT3_END_GROUP;
IMAD R0, R5.reuse, -0x800000, R7 ?trans1;
IADD3 R6, PT, PT, R5, 0x7f, -R6 ?trans1;
MUFU.RCP R8, R3 &wr=0x0 ?trans1;
FADD.FTZ R11, -R3, -RZ ?trans2;
IADD3 R6, PT, PT, R6, R9, RZ ?trans2;
FFMA R13, R8, R11, 1 &req={0} ?WAIT4_END_GROUP;
FFMA R10, R8, R13, R8 ?WAIT4_END_GROUP;
FFMA R7, R0, R10, RZ ?WAIT4_END_GROUP;
FFMA R8, R11, R7, R0 ?WAIT4_END_GROUP;
FFMA R13, R10, R8, R7 ?WAIT4_END_GROUP;
FFMA R8, R11, R13, R0 ?WAIT4_END_GROUP;
FFMA R7, R10, R8, R13 ?WAIT5_END_GROUP;
SHF.R.U32.HI R0, RZ, 0x17, R7 ?WAIT4_END_GROUP;
LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R9, PT, PT, R0, R6, RZ ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R9, -0x1, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R0, 0xfe, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x820 ?trans5;
ISETP.GT.AND P0, PT, R9, 0xfe, PT ?WAIT13_END_GROUP;
@P0 BRA 0x7f0 ?trans5;
ISETP.GE.AND P0, PT, R9, 0x1, PT ?WAIT13_END_GROUP;
@P0 BRA 0x830 ?trans5;
ISETP.GE.AND P0, PT, R9, -0x18, PT ?trans1;
LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ?WAIT12_END_GROUP;
@!P0 BRA 0x830 ?trans5;
FFMA.RZ R0, R10.reuse, R8.reuse, R13.reuse ?trans1;
IADD3 R6, PT, PT, R9.reuse, 0x20, RZ ?trans1;
FFMA.RM R3, R10, R8, R13 ?trans1;
ISETP.NE.AND P1, PT, R9.reuse, RZ, PT ?trans1;
ISETP.NE.AND P2, PT, R9, RZ, PT ?trans1;
LOP3.LUT R0, R0, 0x7fffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
LOP3.LUT R5, R0, 0x800000, RZ, 0xfc, !PT ?trans1;
FFMA.RP R0, R10, R8, R13 ?trans1;
IADD3 R8, PT, PT, -R9, RZ, RZ ?trans2;
SHF.L.U32 R6, R5, R6, RZ ?trans2;
FSETP.NEU.FTZ.AND P0, PT, R0, R3, PT ?trans1;
SEL R0, R8, RZ, P2 ?trans2;
ISETP.NE.AND P1, PT, R6, RZ, P1 ?WAIT3_END_GROUP;
SHF.R.U32.HI R0, RZ, R0, R5 ?trans2;
PLOP3.LUT P0, PT, P0, P1, PT, 0xf8, 0x8f ?trans2;
SHF.R.U32.HI R6, RZ, 0x1, R0 ?WAIT3_END_GROUP;
SEL R3, RZ, 0x1, !P0 ?WAIT5_END_GROUP;
LOP3.LUT R3, R3, 0x1, R6, 0xf8, !PT ?WAIT4_END_GROUP;
LOP3.LUT R3, R3, R0, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R6, PT, PT, R6, R3, RZ ?WAIT4_END_GROUP;
LOP3.LUT R7, R6, R7, RZ, 0xfc, !PT ?trans1;
BRA 0x830 ?trans6;
LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ?trans1;
BRA 0x830 ?trans6;
IMAD R7, R6, 0x800000, R7 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
BRA 0x8d0 ?trans5;
LOP3.LUT R7, R8, 0x80000000, R7, 0x48, !PT ?WAIT4_END_GROUP;
LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ?trans1;
BRA 0x8d0 ?trans6;
LOP3.LUT R7, R8, 0x80000000, R7, 0x48, !PT ?trans1;
BRA 0x8d0 ?trans6;
MUFU.RSQ R7, -QNAN &wr=0x0 ?trans1;
BRA 0x8d0 ?trans5;
FADD.FTZ R7, R0, R3 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B1 ?trans5;
HFMA2 R5, -RZ, RZ, 0, 0 ?WAIT4_END_GROUP;
RET.REL.NODEC R4 0x0 &req={0} ?trans5;
BRA 0x900;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: NormalizeW(float*, float*, float*, int)
_Z10NormalizeWPfS_S_i:
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s8, s[0:1], 0x2c
s_mov_b32 s9, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB3_2
s_waitcnt lgkmcnt(0)
s_load_b32 s6, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s6
ds_store_b32 v1, v2
.LBB3_2:
s_or_b32 exec_lo, exec_lo, s9
s_load_b32 s0, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s1, 0xffff, s8
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s1, v[0:1]
s_barrier
buffer_gl0_inv
v_cmp_gt_u32_e32 vcc_lo, s0, v1
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB3_4
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
ds_load_b32 v2, v2
v_add_co_u32 v3, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v1, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_div_scale_f32 v4, null, v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v3, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v6, v5
v_fma_f32 v8, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v8, v5
v_fma_f32 v4, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f32 v4, v4, v5, v7
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_div_fixup_f32 v2, v4, v2, v3
global_store_b32 v[0:1], v2, off
.LBB3_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| NormalizeW | 3,546 | 942 | stackv2-00000-of-00015 |
// Demangled: kernel(int*, int*, int*)
Function : _Z6kernelPiS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans8;
LDC.64 R4, c[0x0][0x388] &wr=0x1 ?trans1;
LDG.E R2, desc[UR4][R2.64] &req={0} &wr=0x2 ?trans4;
LDG.E R5, desc[UR4][R4.64] &req={1} &wr=0x2 ?trans3;
LDC.64 R6, c[0x0][0x390] &wr=0x0 ?trans1;
IADD3 R9, PT, PT, R2, R5, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 &req={0} ?trans1;
EXIT ?trans5;
BRA 0xa0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: kernel(int*, int*, int*)
_Z6kernelPiS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_load_b32 s3, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| kernel | 331 | 211 | stackv2-00000-of-00015 |
// Demangled: MatAdd(float const*, float const*, float*, int)
Function : _Z6MatAddPKfS0_Pfi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x364] &wr=0x2 ?trans1;
S2R R7, SR_CTAID.Y &wr=0x2 ?trans1;
LDCU UR6, c[0x0][0x398] &wr=0x3 ?trans1;
S2R R2, SR_TID.Y &wr=0x2 ?trans1;
IMAD R0, R0, UR4, R3 &req={1} ?trans2;
IMAD R7, R7, UR5, R2 &req={2} ?WAIT5_END_GROUP;
VIMNMX.S32 R2, R0, R7, !PT ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R2, UR6, PT &req={3} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD R9, R7, UR6, R0 ?WAIT6_END_GROUP;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD.WIDE R2, R9, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x4 ?trans1;
IMAD.WIDE R4, R9, 0x4, R4 &req={2} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR4][R4.64] &wr=0x4 ?trans1;
IMAD.WIDE R6, R9, 0x4, R6 &req={3} ?WAIT4_END_GROUP;
FADD R9, R2, R5 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x1a0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: MatAdd(float const*, float const*, float*, int)
_Z6MatAddPKfS0_Pfi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v2, v0, v1
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| MatAdd | 707 | 750 | stackv2-00000-of-00015 |
// Demangled: foo(S)
Function : _Z3foo1S
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R9, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x388] &wr=0x1 ?trans1;
LDCU UR6, c[0x0][0x360] &wr=0x0 ?trans1;
S2R R0, SR_CTAID.X &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans5;
LDC.64 R4, c[0x0][0x380] &wr=0x3 ?trans1;
IMAD R7, R0, UR6, R9 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R2, R7, 0x4, R2 &req={1} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR4][R2.64] &req={2} &wr=0x2 ?trans1;
IMAD.WIDE.U32 R4, R7, 0x4, R4 &req={3} ?trans1;
IADD3 R7, PT, PT, R0, R9, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64], R7 ?trans4;
STG.E desc[UR4][R2.64], R9 ?trans1;
EXIT ?trans5;
BRA 0xf0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: foo(S)
_Z3foo1S:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v5, v[3:4], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, v5, v0
global_store_b32 v[1:2], v5, off
global_store_b32 v[3:4], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| foo | 426 | 405 | stackv2-00000-of-00015 |
// Demangled: voxel_pooling_forward_kernel(int, int, int, int, int, int, int const*, float const*, float*, int*)
Function : _Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans8;
LDC R3, c[0x0][0x360] &wr=0x1 ?trans8;
LDC.64 R4, c[0x0][0x380] &wr=0x2 ?trans1;
IMAD R0, R3, UR4, R0 &req={1} ?WAIT2_END_GROUP;
IMAD R3, R5, R4, RZ &req={2} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, R3, PT ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x398] &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD R9, R0, 0x3, RZ ?trans1;
IABS R13, R5 ?trans1;
LDCU.64 UR4, c[0x0][0x390] &wr=0x2 ?trans1;
LDCU UR8, c[0x0][0x38c] &wr=0x3 ?trans1;
IMAD.WIDE R2, R9, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E R8, desc[UR6][R2.64+0x4] &req={1} &wr=0x2 ?trans4;
LDG.E R11, desc[UR6][R2.64] &wr=0x4 ?trans4;
LDG.E R10, desc[UR6][R2.64+0x8] &rd=0x0 &wr=0x5 ?trans1;
I2F.RP R4, R13 &wr=0x1 ?trans1;
IABS R2, R0 &req={0} ?trans1;
MUFU.RCP R4, R4 &req={1} &wr=0x0 ?trans2;
IADD3 R6, PT, PT, R4, 0xffffffe, RZ &req={0} ?WAIT4_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R7, R6 &rd=0x0 &wr=0x1 ?trans2;
HFMA2 R6, -RZ, RZ, 0, 0 &req={0} ?trans1;
IADD3 R12, PT, PT, RZ, -R7, RZ &req={1} ?WAIT5_END_GROUP;
IMAD R3, R12, R13, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R7, R7, R3, R6 ?WAIT6_END_GROUP;
IMAD.HI.U32 R7, R7, R2, RZ ?WAIT5_END_GROUP;
IADD3 R3, PT, PT, -R7, RZ, RZ ?WAIT5_END_GROUP;
IMAD R2, R13, R3, R2 ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P1, PT, R13, R2, PT ?WAIT13_END_GROUP;
@!P1 IADD3 R2, PT, PT, R2, -R13, RZ ?trans1;
ISETP.GE.AND P0, PT, R8, UR4, PT &req={2} ?trans1;
LOP3.LUT R4, R11, R8, RZ, 0xfc, !PT &req={4} ?WAIT4_END_GROUP;
ISETP.GE.OR P0, PT, R11, UR8, P0 &req={3} ?WAIT5_END_GROUP;
ISETP.LT.OR P0, PT, R4, RZ, P0 ?WAIT5_END_GROUP;
ISETP.LT.OR P0, PT, R10, RZ, P0 &req={5} ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R10, UR5, P0 ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
ISETP.GE.U32.AND P0, PT, R2, R13, PT ?trans1;
LDC R3, c[0x0][0x388] &wr=0x0 ?trans1;
LOP3.LUT R2, R0, R5, RZ, 0x3c, !PT ?trans1;
LDCU.64 UR10, c[0x0][0x3b0] &wr=0x1 ?trans1;
@!P1 IADD3 R7, PT, PT, R7, 0x1, RZ ?WAIT3_END_GROUP;
ISETP.GE.AND P1, PT, R2, RZ, PT ?trans1;
SHF.R.S32.HI R2, RZ, 0x1f, R9 ?WAIT5_END_GROUP;
@P0 IADD3 R7, PT, PT, R7, 0x1, RZ ?trans1;
ISETP.NE.AND P0, PT, R5, RZ, PT ?WAIT4_END_GROUP;
MOV R13, R7 ?trans1;
LEA R6, P2, R9, UR10, 0x2 &req={1} ?WAIT4_END_GROUP;
@!P1 IADD3 R13, PT, PT, -R13, RZ, RZ ?trans1;
ISETP.GE.AND P1, PT, R3, 0x1, PT &req={0} ?trans1;
LEA.HI.X R7, R9, UR11, R2, 0x2, P2 ?trans2;
@!P0 LOP3.LUT R13, RZ, R5, RZ, 0x33, !PT ?WAIT3_END_GROUP;
STG.E desc[UR6][R6.64+0x4], R8 &rd=0x0 ?trans4;
STG.E desc[UR6][R6.64+0x8], R11 &rd=0x0 ?trans4;
STG.E desc[UR6][R6.64], R13 &rd=0x0 ?trans1;
@!P1 EXIT ?trans5;
ISETP.GE.U32.AND P0, PT, R3, 0x10, PT ?trans1;
IMAD R8, R13, UR4, R8 &req={0} ?trans1;
UMOV UR4, URZ ?trans1;
LOP3.LUT P1, R10, R3, 0xf, RZ, 0xc0, !PT ?trans1;
IMAD R0, R0, R3, RZ ?trans2;
IMAD R2, R8, UR8, R11 ?WAIT4_END_GROUP;
IMAD R2, R2, R3, RZ ?WAIT3_END_GROUP;
@!P0 BRA 0x720 ?trans5;
LOP3.LUT R4, R3, 0x7ffffff0, RZ, 0xc0, !PT ?trans1;
UMOV UR4, URZ ?trans1;
MOV R9, R0 ?trans1;
MOV R11, R2 ?trans1;
IADD3 R8, PT, PT, -R4, RZ, RZ ?WAIT7_END_GROUP;
LDC.64 R4, c[0x0][0x3a0] &wr=0x0 ?trans8;
LDC.64 R6, c[0x0][0x3a8] &req={4} &wr=0x1 ?trans1;
IMAD.WIDE R4, R9, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
LDG.E R13, desc[UR6][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE R6, R11, 0x4, R6 &req={1} ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R6.64], R13 &req={2} &rd=0x0 ?trans4;
LDG.E R15, desc[UR6][R4.64+0x4] &wr=0x2 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R6.64+0x4], R15 &req={2} &rd=0x1 ?trans4;
LDG.E R17, desc[UR6][R4.64+0x8] &wr=0x2 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R6.64+0x8], R17 &req={2} &rd=0x2 ?trans4;
LDG.E R19, desc[UR6][R4.64+0xc] &wr=0x3 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R6.64+0xc], R19 &req={3} &rd=0x3 ?trans4;
LDG.E R21, desc[UR6][R4.64+0x10] &wr=0x4 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R6.64+0x10], R21 &req={4} &rd=0x4 ?trans4;
LDG.E R23, desc[UR6][R4.64+0x14] &wr=0x5 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R6.64+0x14], R23 &req={5} &rd=0x5 ?trans4;
LDG.E R13, desc[UR6][R4.64+0x18] &req={0} &wr=0x2 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R6.64+0x18], R13 &req={2} &rd=0x0 ?trans4;
LDG.E R15, desc[UR6][R4.64+0x1c] &req={1} &wr=0x2 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R6.64+0x1c], R15 &req={2} &rd=0x1 ?trans4;
LDG.E R17, desc[UR6][R4.64+0x20] &wr=0x2 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R6.64+0x20], R17 &req={2} &rd=0x2 ?trans4;
LDG.E R19, desc[UR6][R4.64+0x24] &req={3} &wr=0x3 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R6.64+0x24], R19 &req={3} &rd=0x3 ?trans4;
LDG.E R21, desc[UR6][R4.64+0x28] &req={4} &wr=0x4 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R6.64+0x28], R21 &req={4} &rd=0x4 ?trans4;
LDG.E R23, desc[UR6][R4.64+0x2c] &req={5} &wr=0x5 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R6.64+0x2c], R23 &req={5} &rd=0x4 ?trans4;
LDG.E R13, desc[UR6][R4.64+0x30] &req={0} &wr=0x5 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R6.64+0x30], R13 &req={5} &rd=0x4 ?trans4;
LDG.E R15, desc[UR6][R4.64+0x34] &req={1} &wr=0x5 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R6.64+0x34], R15 &req={5} &rd=0x4 ?trans4;
LDG.E R17, desc[UR6][R4.64+0x38] &req={2} &wr=0x2 ?trans1;
IADD3 R8, PT, PT, R8, 0x10, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R8, RZ, PT ?trans1;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R6.64+0x38], R17 &req={2} &rd=0x4 ?trans4;
LDG.E R19, desc[UR6][R4.64+0x3c] &req={3} &wr=0x2 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x10, URZ ?trans1;
IADD3 R11, PT, PT, R11, 0x10, RZ ?trans2;
IADD3 R9, PT, PT, R9, 0x10, RZ ?trans1;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R6.64+0x3c], R19 &req={2} &rd=0x4 ?trans3;
@P0 BRA 0x480 ?trans5;
@!P1 EXIT ?trans5;
ISETP.GE.U32.AND P0, PT, R10, 0x8, PT ?trans1;
LOP3.LUT R8, R3, 0x7, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R8, RZ, PT ?WAIT7_END_GROUP;
@!P0 BRA 0x8e0 ?trans6;
LDC.64 R6, c[0x0][0x3a0] &req={4} &wr=0x0 ?trans1;
IADD3 R5, PT, PT, R0, UR4, RZ ?WAIT5_END_GROUP;
IMAD.WIDE R6, R5, 0x4, R6 &req={0} ?trans2;
LDC.64 R4, c[0x0][0x3a8] &wr=0x0 ?trans3;
LDG.E R11, desc[UR6][R6.64] &wr=0x2 ?trans1;
IADD3 R9, PT, PT, R2, UR4, RZ ?WAIT5_END_GROUP;
IMAD.WIDE R4, R9, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R4.64], R11 &req={2} &rd=0x0 ?trans4;
LDG.E R9, desc[UR6][R6.64+0x4] &wr=0x2 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R4.64+0x4], R9 &req={2} &rd=0x1 ?trans4;
LDG.E R13, desc[UR6][R6.64+0x8] &wr=0x2 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R4.64+0x8], R13 &req={2} &rd=0x2 ?trans4;
LDG.E R15, desc[UR6][R6.64+0xc] &wr=0x3 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R4.64+0xc], R15 &req={3} &rd=0x2 ?trans4;
LDG.E R17, desc[UR6][R6.64+0x10] &wr=0x3 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R4.64+0x10], R17 &req={3} &rd=0x2 ?trans4;
LDG.E R19, desc[UR6][R6.64+0x14] &wr=0x3 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R4.64+0x14], R19 &req={3} &rd=0x2 ?trans4;
LDG.E R11, desc[UR6][R6.64+0x18] &req={0} &wr=0x3 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R4.64+0x18], R11 &req={3} &rd=0x2 ?trans4;
LDG.E R9, desc[UR6][R6.64+0x1c] &req={1} &wr=0x3 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x8, URZ ?WAIT3_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R4.64+0x1c], R9 &req={3} &rd=0x2 ?trans9;
@!P1 EXIT ?trans5;
ISETP.GE.U32.AND P0, PT, R8, 0x4, PT ?trans1;
LOP3.LUT R3, R3, 0x3, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R3, RZ, PT ?WAIT7_END_GROUP;
@!P0 BRA 0xa20 ?trans6;
LDC.64 R4, c[0x0][0x3a0] &req={2} &wr=0x0 ?trans1;
IADD3 R7, PT, PT, R0, UR4, RZ &req={4} ?WAIT5_END_GROUP;
IMAD.WIDE R6, R7, 0x4, R4 &req={0} ?trans2;
LDC.64 R4, c[0x0][0x3a8] &wr=0x0 ?trans3;
LDG.E R9, desc[UR6][R6.64] &wr=0x2 ?trans1;
IADD3 R11, PT, PT, R2, UR4, RZ ?WAIT5_END_GROUP;
IMAD.WIDE R4, R11, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R4.64], R9 &req={2} &rd=0x0 ?trans4;
LDG.E R11, desc[UR6][R6.64+0x4] &wr=0x2 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R4.64+0x4], R11 &req={2} &rd=0x0 ?trans4;
LDG.E R13, desc[UR6][R6.64+0x8] &wr=0x2 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R4.64+0x8], R13 &req={2} &rd=0x0 ?trans4;
LDG.E R15, desc[UR6][R6.64+0xc] &wr=0x2 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x4, URZ ?WAIT3_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R4.64+0xc], R15 &req={2} &rd=0x0 ?trans9;
@!P1 EXIT ?trans5;
LDC.64 R6, c[0x0][0x3a0] &req={4} &wr=0x1 ?trans1;
IADD3 R11, PT, PT, R0, UR4, RZ &req={2,0} ?trans2;
IADD3 R13, PT, PT, R2, UR4, RZ ?trans2;
IADD3 R0, PT, PT, -R3, RZ, RZ ?WAIT3_END_GROUP;
LDC.64 R8, c[0x0][0x3a8] &wr=0x0 ?trans4;
IMAD.WIDE R2, R11, 0x4, R6 &req={2,1} ?WAIT6_END_GROUP;
LDG.E R3, desc[UR6][R2.64] &wr=0x2 ?trans1;
IADD3 R0, PT, PT, R0, 0x1, RZ ?trans1;
IMAD.WIDE R4, R13, 0x4, R8 &req={0} ?WAIT4_END_GROUP;
ISETP.NE.AND P0, PT, R0, RZ, PT ?trans1;
IADD3 R11, PT, PT, R11, 0x1, RZ ?trans2;
IADD3 R13, PT, PT, R13, 0x1, RZ ?trans1;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R4.64], R3 &req={2} &rd=0x2 ?trans9;
@P0 BRA 0xa80 ?trans5;
EXIT ?trans5;
BRA 0xb20;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: voxel_pooling_forward_kernel(int, int, int, int, int, int, int const*, float const*, float*, int*)
_Z28voxel_pooling_forward_kerneliiiiiiPKiPKfPfPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b128 s[16:19], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[5:6], null, s15, s2, v[0:1]
s_mul_i32 s2, s17, s16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v5
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_9
s_load_b256 s[4:11], s[0:1], 0x18
v_lshl_add_u32 v0, v5, 1, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[3:4], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v4, vcc_lo
global_load_b96 v[0:2], v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, -1, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_9
s_load_b64 s[2:3], s[0:1], 0x10
v_cmp_gt_i32_e32 vcc_lo, s19, v0
v_cmp_lt_i32_e64 s0, -1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_9
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
v_cmp_gt_i32_e64 s0, s3, v2
v_cmp_lt_i32_e64 s1, -1, v2
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_9
s_ashr_i32 s0, s17, 31
v_ashrrev_i32_e32 v7, 31, v5
s_add_i32 s1, s17, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s1, s1, s0
v_add_nc_u32_e32 v8, v5, v7
v_cvt_f32_u32_e32 v2, s1
s_sub_i32 s3, 0, s1
s_cmp_lt_i32 s18, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v8, v8, v7
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v2, v2
v_mul_lo_u32 v6, s3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v6, v2, v6
v_add_nc_u32_e32 v2, v2, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v8, v2
v_mul_lo_u32 v6, v2, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v6, v8, v6
v_add_nc_u32_e32 v8, 1, v2
v_subrev_nc_u32_e32 v9, s1, v6
v_cmp_le_u32_e32 vcc_lo, s1, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v2, v2, v8, vcc_lo
v_cndmask_b32_e32 v6, v6, v9, vcc_lo
v_xor_b32_e32 v9, s0, v7
s_mov_b32 s0, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v8, 1, v2
v_cmp_le_u32_e32 vcc_lo, s1, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v2, v2, v8, vcc_lo
v_add_co_u32 v6, vcc_lo, s10, v3
v_mov_b32_e32 v3, v1
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v4, vcc_lo
v_xor_b32_e32 v2, v2, v9
v_mov_b32_e32 v4, v0
s_delay_alu instid0(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v2, v9
global_store_b96 v[6:7], v[2:4], off
s_cbranch_scc1 .LBB0_9
v_mad_u64_u32 v[3:4], null, v2, s2, v[1:2]
v_mul_lo_u32 v5, v5, s18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, v3, s19, v[0:1]
v_mul_lo_u32 v4, v1, s18
.LBB0_6:
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v0, s0, v5
v_add_nc_u32_e32 v2, s0, v4
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v3, vcc_lo
global_load_b32 v6, v[6:7], off
global_load_b32 v3, v[0:1], off
.LBB0_7:
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v3, v6
global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v2, v3
v_mov_b32_e32 v3, v2
s_or_b32 s1, vcc_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_7
s_or_b32 exec_lo, exec_lo, s1
s_add_i32 s0, s0, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s0, s18
s_cbranch_scc1 .LBB0_6
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| voxel_pooling_forward_kernel | 5,461 | 2,591 | stackv2-00000-of-00015 |
// Demangled: doit(int, int)
Function : _Z4doitii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
EXIT ?trans5;
BRA 0x20;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: doit(int, int)
_Z4doitii:
v_mov_b32_e32 v0, 1.0
s_mov_b32 s0, 12
s_mov_b32 s1, 0
.LBB0_1:
v_mov_b32_e32 v1, s0
s_add_i32 s1, s1, 4
s_add_i32 s0, s0, 12
s_cmpk_lg_i32 s1, 0x1000
ds_store_b32 v1, v0
s_cbranch_scc1 .LBB0_1
s_endpgm
| doit | 92 | 144 | stackv2-00000-of-00015 |
// Demangled: vectorAddKernel(float*, float*, float*)
Function : _Z15vectorAddKernelPfS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R0, SR_TID.X &wr=0x0 ?trans7;
S2UR UR6, SR_CTAID.X &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC R9, c[0x0][0x360] &wr=0x0 ?trans8;
LDC.64 R2, c[0x0][0x380] &wr=0x2 ?trans8;
LDC.64 R4, c[0x0][0x388] &wr=0x3 ?trans1;
IMAD R9, R9, UR6, R0 &req={0} ?WAIT7_END_GROUP;
LDC.64 R6, c[0x0][0x390] &wr=0x0 ?trans1;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={2} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans1;
IMAD.WIDE.U32 R4, R9, 0x4, R4 &req={3} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R6, R9, 0x4, R6 &req={0} ?WAIT4_END_GROUP;
FADD R9, R2, R5 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x110;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: vectorAddKernel(float*, float*, float*)
_Z15vectorAddKernelPfS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| vectorAddKernel | 506 | 478 | stackv2-00000-of-00015 |
// Demangled: AddHistograms(int*, int*, int, int)
Function : _Z13AddHistogramsPiS_ii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
LDCU UR6, c[0x0][0x390] &wr=0x1 ?trans1;
S2R R5, SR_TID.X &wr=0x2 ?trans1;
HFMA2 R4, -RZ, RZ, 0, 0 ?trans1;
LDCU.64 UR32, c[0x0][0x358] &wr=0x3 ?trans1;
UISETP.GE.AND UP0, UPT, UR6, 0x1, UPT &req={1} ?WAIT6_END_GROUP;
PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x8 ?WAIT13_END_GROUP;
@!P0 BRA 0xd70 &req={3,2} ?trans5;
LDC R0, c[0x0][0x390] &wr=0x1 ?trans1;
UISETP.GE.U32.AND UP0, UPT, UR6, 0x10, UPT ?trans1;
UMOV UR4, URZ ?trans1;
MOV R4, RZ ?WAIT4_END_GROUP;
PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x8 ?trans2;
LOP3.LUT R28, R0, 0xf, RZ, 0xc0, !PT &req={1} ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R28, RZ, PT ?WAIT6_END_GROUP;
@!P0 BRA 0x880 ?trans7;
LDCU UR34, c[0x0][0x394] &wr=0x1 ?trans1;
ULOP3.LUT UR6, UR6, 0x7ffffff0, URZ, 0xc0, !UPT ?trans1;
UMOV UR4, URZ ?WAIT3_END_GROUP;
UIADD3 UR6, UPT, UPT, -UR6, URZ, URZ ?trans1;
USHF.R.S32.HI UR35, URZ, 0x1f, UR34 &req={1} ?WAIT4_END_GROUP;
UIADD3.64 UR8, UPT, UPT, UR34, UR34, URZ ?WAIT4_END_GROUP;
UIADD3.64 UR10, UPT, UPT, UR34, UR8, URZ ?trans1;
USHF.L.U64.HI UR5, UR8, 0x2, UR9 ?trans1;
USHF.L.U32 UR8, UR8, 0x2, URZ ?trans2;
UIADD3.64 UR12, UPT, UPT, UR34, UR10, URZ ?trans1;
USHF.L.U64.HI UR7, UR10, 0x2, UR11 ?trans1;
USHF.L.U32 UR10, UR10, 0x2, URZ ?trans2;
UIADD3.64 UR14, UPT, UPT, UR34, UR12, URZ ?trans1;
USHF.L.U64.HI UR9, UR12, 0x2, UR13 ?trans1;
USHF.L.U32 UR12, UR12, 0x2, URZ ?WAIT2_END_GROUP;
UIADD3.64 UR16, UPT, UPT, UR34, UR14, URZ ?trans1;
USHF.L.U64.HI UR11, UR14, 0x2, UR15 ?trans1;
USHF.L.U32 UR14, UR14, 0x2, URZ ?trans2;
UIADD3.64 UR18, UPT, UPT, UR34, UR16, URZ ?trans1;
USHF.L.U64.HI UR13, UR16, 0x2, UR17 ?trans1;
USHF.L.U32 UR16, UR16, 0x2, URZ ?trans2;
UIADD3.64 UR20, UPT, UPT, UR34, UR18, URZ ?trans1;
USHF.L.U64.HI UR15, UR18, 0x2, UR19 ?trans1;
USHF.L.U32 UR18, UR18, 0x2, URZ ?WAIT2_END_GROUP;
UIADD3.64 UR22, UPT, UPT, UR34, UR20, URZ ?trans1;
USHF.L.U64.HI UR17, UR20, 0x2, UR21 ?trans1;
USHF.L.U32 UR20, UR20, 0x2, URZ ?trans2;
UIADD3.64 UR24, UPT, UPT, UR34, UR22, URZ ?trans1;
USHF.L.U64.HI UR19, UR22, 0x2, UR23 ?trans1;
USHF.L.U32 UR46, UR22, 0x2, URZ ?trans2;
UIADD3.64 UR26, UPT, UPT, UR34, UR24, URZ ?trans1;
USHF.L.U64.HI UR45, UR24, 0x2, UR25 ?trans1;
USHF.L.U32 UR44, UR24, 0x2, URZ ?WAIT2_END_GROUP;
UIADD3.64 UR28, UPT, UPT, UR34, UR26, URZ ?trans1;
USHF.L.U64.HI UR31, UR26, 0x2, UR27 ?trans1;
USHF.L.U32 UR30, UR26, 0x2, URZ ?trans2;
UIADD3.64 UR22, UPT, UPT, UR34, UR28, URZ ?trans1;
USHF.L.U64.HI UR43, UR28, 0x2, UR29 ?trans1;
USHF.L.U32 UR42, UR28, 0x2, URZ ?trans2;
UIADD3.64 UR24, UPT, UPT, UR34, UR22, URZ ?trans1;
USHF.L.U64.HI UR41, UR22, 0x2, UR23 ?trans1;
USHF.L.U32 UR40, UR22, 0x2, URZ ?WAIT2_END_GROUP;
UIADD3.64 UR26, UPT, UPT, UR34, UR24, URZ ?trans1;
USHF.L.U64.HI UR39, UR24, 0x2, UR25 ?trans1;
USHF.L.U32 UR38, UR24, 0x2, URZ ?trans2;
USHF.L.U64.HI UR37, UR26, 0x2, UR27 ?trans1;
USHF.L.U32 UR36, UR26, 0x2, URZ ?WAIT12_END_GROUP;
LDC.64 R2, c[0x0][0x388] &wr=0x1 ?trans1;
MOV R7, UR34 ?trans1;
UMOV UR22, UR8 ?trans1;
UMOV UR23, UR5 ?trans1;
UMOV UR24, UR10 ?trans1;
UMOV UR25, UR7 ?trans1;
UMOV UR26, UR12 ?trans1;
UMOV UR27, UR9 ?trans1;
UMOV UR28, UR14 ?trans1;
UMOV UR29, UR11 ?trans1;
IMAD.WIDE R2, R5, 0x4, R2 &req={1} ?WAIT5_END_GROUP;
IADD.64 R8, R2, UR22 ?trans2;
IMAD.WIDE R6, R7, 0x4, R2 ?trans1;
IADD.64 R10, R2.reuse, UR24 ?trans2;
LDG.E R26, desc[UR32][R2.64] &wr=0x2 ?trans1;
IADD.64 R12, R2.reuse, UR26 ?trans2;
IADD.64 R14, R2.reuse, UR28 ?trans2;
LDG.E R17, desc[UR32][R6.64] &wr=0x2 ?trans1;
UMOV UR22, UR16 ?trans1;
UMOV UR23, UR13 ?trans1;
UMOV UR24, UR18 ?trans1;
LDG.E R16, desc[UR32][R8.64] &rd=0x1 &wr=0x3 ?trans1;
UMOV UR25, UR15 ?trans1;
IADD.64 R30, R2, UR22 ?WAIT2_END_GROUP;
LDG.E R19, desc[UR32][R10.64] &rd=0x4 &wr=0x3 ?trans1;
IADD.64 R32, R2.reuse, UR24 ?trans2;
UMOV UR21, UR17 ?trans1;
UMOV UR26, UR46 ?trans1;
UMOV UR27, UR19 ?trans1;
LDG.E R18, desc[UR32][R12.64] &rd=0x5 &wr=0x3 ?trans1;
IADD.64 R22, R2.reuse, UR20 ?trans2;
IADD.64 R20, R2.reuse, UR26 ?trans2;
LDG.E R25, desc[UR32][R14.64] &rd=0x0 &wr=0x3 ?trans1;
UMOV UR28, UR44 ?trans1;
UMOV UR29, UR45 ?trans1;
IADD.64 R8, R2, UR30 &req={1} ?WAIT2_END_GROUP;
LDG.E R24, desc[UR32][R30.64] &wr=0x3 ?trans1;
IADD.64 R6, R2, UR28 ?WAIT3_END_GROUP;
LDG.E R27, desc[UR32][R32.64] &wr=0x3 ?trans1;
UMOV UR22, UR42 ?trans1;
UMOV UR23, UR43 ?trans1;
UMOV UR24, UR40 ?trans1;
UMOV UR25, UR41 ?trans1;
LDG.E R22, desc[UR32][R22.64] &wr=0x3 ?trans1;
IADD.64 R10, R2.reuse, UR22 &req={4} ?trans2;
IADD.64 R12, R2.reuse, UR24 &req={5} ?trans2;
LDG.E R21, desc[UR32][R20.64] &wr=0x4 ?trans1;
UMOV UR26, UR38 ?trans1;
UMOV UR27, UR39 ?trans1;
UMOV UR28, UR36 ?trans1;
UMOV UR29, UR37 ?trans1;
LDG.E R7, desc[UR32][R6.64] &wr=0x5 ?trans1;
IADD.64 R14, R2, UR26 &req={0} ?WAIT2_END_GROUP;
IADD.64 R2, R2, UR28 ?trans2;
LDG.E R8, desc[UR32][R8.64] &wr=0x5 ?trans4;
LDG.E R10, desc[UR32][R10.64] &wr=0x5 ?trans4;
LDG.E R12, desc[UR32][R12.64] &wr=0x5 ?trans4;
LDG.E R14, desc[UR32][R14.64] &wr=0x5 ?trans4;
LDG.E R2, desc[UR32][R2.64] &wr=0x5 ?trans1;
UIADD3 UR6, UPT, UPT, UR6, 0x10, URZ ?WAIT6_END_GROUP;
ISETP.NE.AND P0, PT, RZ, UR6, PT ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x10, URZ ?trans1;
IADD3 R17, PT, PT, R17, R26, R4 &req={2} ?WAIT4_END_GROUP;
IADD3 R16, PT, PT, R19, R16, R17 &req={3} ?WAIT4_END_GROUP;
IADD3 R16, PT, PT, R25, R18, R16 ?WAIT4_END_GROUP;
IADD3 R16, PT, PT, R27, R24, R16 ?trans1;
MOV R4, UR34 ?WAIT3_END_GROUP;
IADD3 R16, PT, PT, R21, R22, R16 &req={4} ?trans2;
IMAD R5, R4, 0x10, R5 ?trans2;
IADD3 R7, PT, PT, R8, R7, R16 &req={5} ?WAIT4_END_GROUP;
IADD3 R7, PT, PT, R12, R10, R7 ?WAIT4_END_GROUP;
IADD3 R4, PT, PT, R2, R14, R7 ?trans1;
@P0 BRA 0x3f0 ?trans6;
@!P1 BRA 0xd70 ?trans5;
S2R R2, SR_TID.X &wr=0x1 ?trans1;
ISETP.GE.U32.AND P1, PT, R28, 0x8, PT ?trans1;
LOP3.LUT R5, R0, 0x7, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R5, RZ, PT ?WAIT7_END_GROUP;
@!P1 BRA 0xb30 ?trans6;
LDC R8, c[0x0][0x394] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x388] &wr=0x3 ?trans1;
SHF.R.S32.HI R9, RZ, 0x1f, R8 &req={2} ?trans1;
IMAD R3, R8, UR4, R2 &req={1} ?WAIT4_END_GROUP;
IADD.64 R10, R8, R8 ?trans2;
IMAD.WIDE R6, R3, 0x4, R6 &req={3} ?trans2;
IADD.64 R14, R8, R10 ?WAIT4_END_GROUP;
IADD.64 R16, R8.reuse, R14 ?trans2;
IMAD.WIDE R18, R8, 0x4, R6 ?trans1;
LEA R12, P2, R14, R6.reuse, 0x2 ?trans2;
LEA R20, P1, R10, R6, 0x2 ?trans2;
LEA.HI.X R13, R14, R7, R15, 0x2, P2 ?trans1;
IADD.64 R14, R8, R16 ?trans2;
LDG.E R3, desc[UR32][R18.64] &wr=0x2 ?trans1;
LEA.HI.X R21, R10, R7, R11, 0x2, P1 ?trans1;
IADD.64 R22, R8, R14 ?WAIT2_END_GROUP;
LDG.E R12, desc[UR32][R12.64] &wr=0x3 ?trans1;
LEA R10, P1, R16, R6, 0x2 ?trans1;
IADD.64 R24, R8, R22 ?trans2;
LDG.E R20, desc[UR32][R20.64] &wr=0x3 ?trans1;
LEA.HI.X R11, R16, R7.reuse, R17, 0x2, P1 ?trans2;
LEA R16, P2, R14, R6.reuse, 0x2 ?trans1;
LDG.E R18, desc[UR32][R6.64] &wr=0x2 ?trans1;
LEA R8, P1, R22, R6.reuse, 0x2 ?trans2;
LEA.HI.X R17, R14, R7, R15, 0x2, P2 ?trans1;
LDG.E R10, desc[UR32][R10.64] &wr=0x4 ?trans1;
LEA R14, P2, R24, R6, 0x2 ?WAIT2_END_GROUP;
LEA.HI.X R9, R22, R7.reuse, R23, 0x2, P1 ?trans1;
LDG.E R16, desc[UR32][R16.64] &wr=0x4 ?trans1;
LEA.HI.X R15, R24, R7, R25, 0x2, P2 ?WAIT3_END_GROUP;
LDG.E R8, desc[UR32][R8.64] &wr=0x5 ?trans4;
LDG.E R14, desc[UR32][R14.64] &wr=0x5 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x8, URZ ?trans1;
IADD3 R3, PT, PT, R3, R18, R4 &req={2} ?WAIT4_END_GROUP;
IADD3 R3, PT, PT, R12, R20, R3 &req={3} ?WAIT4_END_GROUP;
IADD3 R3, PT, PT, R16, R10, R3 &req={4} ?WAIT4_END_GROUP;
IADD3 R4, PT, PT, R14, R8, R3 &req={5} ?WAIT7_END_GROUP;
@!P0 BRA 0xd70 ?trans5;
ISETP.GE.U32.AND P1, PT, R5, 0x4, PT ?trans1;
LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R0, RZ, PT ?WAIT7_END_GROUP;
@!P1 BRA 0xcb0 ?trans6;
LDC R8, c[0x0][0x394] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x388] &wr=0x3 ?trans1;
SHF.R.S32.HI R9, RZ, 0x1f, R8 &req={2} ?trans1;
IMAD R3, R8, UR4, R2 &req={1} ?WAIT4_END_GROUP;
IADD.64 R10, R8, R8 ?trans2;
IMAD.WIDE R6, R3, 0x4, R6 &req={3} ?trans2;
IADD.64 R14, R8, R10 ?WAIT3_END_GROUP;
LEA R12, P1, R10, R6.reuse, 0x2 ?trans1;
IMAD.WIDE R8, R8, 0x4, R6 ?trans1;
LEA R16, P2, R14, R6, 0x2 ?trans2;
LEA.HI.X R13, R10, R7.reuse, R11, 0x2, P1 ?trans2;
LEA.HI.X R17, R14, R7, R15, 0x2, P2 ?trans1;
LDG.E R8, desc[UR32][R8.64] &wr=0x2 ?trans4;
LDG.E R7, desc[UR32][R6.64] &wr=0x2 ?trans4;
LDG.E R13, desc[UR32][R12.64] &wr=0x3 ?trans4;
LDG.E R16, desc[UR32][R16.64] &wr=0x3 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x4, URZ ?trans1;
IADD3 R4, PT, PT, R8, R7, R4 &req={2} ?WAIT4_END_GROUP;
IADD3 R4, PT, PT, R16, R13, R4 &req={3} ?WAIT7_END_GROUP;
@!P0 BRA 0xd70 ?trans5;
LDC R8, c[0x0][0x394] &wr=0x2 ?trans1;
IADD3 R0, PT, PT, -R0, RZ, RZ ?WAIT7_END_GROUP;
LDC.64 R6, c[0x0][0x388] &wr=0x3 ?trans1;
IMAD R5, R8, UR4, R2 &req={2,1} ?WAIT7_END_GROUP;
IMAD.WIDE R2, R5, 0x4, R6 &req={3} ?WAIT6_END_GROUP;
LDG.E R3, desc[UR32][R2.64] &wr=0x2 ?trans1;
IADD3 R0, PT, PT, R0, 0x1, RZ ?trans2;
IADD3 R5, PT, PT, R5, R8, RZ ?WAIT3_END_GROUP;
ISETP.NE.AND P0, PT, R0, RZ, PT ?trans1;
IADD3 R4, PT, PT, R3, R4, RZ &req={2} ?WAIT12_END_GROUP;
@P0 BRA 0xd00 ?trans5;
S2R R5, SR_TID.X &wr=0x2 ?trans1;
LDC.64 R2, c[0x0][0x380] &req={1} &wr=0x2 ?trans2;
IMAD.WIDE.U32 R2, R5, 0x4, R2 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR32][R2.64], R4 ?trans1;
EXIT ?trans5;
BRA 0xdc0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: AddHistograms(int*, int*, int, int)
_Z13AddHistogramsPiS_ii:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v2, 2, v0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB1_3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s2, s2, v2
v_add_co_ci_u32_e64 v1, null, s3, 0, s2
s_ashr_i32 s3, s5, 31
s_mov_b32 s2, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
.LBB1_2:
global_load_b32 v4, v[0:1], off
v_add_co_u32 v0, vcc_lo, v0, s2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_add_i32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s4, 0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
s_cbranch_scc1 .LBB1_2
.LBB1_3:
global_store_b32 v2, v3, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| AddHistograms | 5,506 | 465 | stackv2-00000-of-00015 |
// Demangled: imageCreate(unsigned char*, unsigned char*, int)
Function : _Z11imageCreatePhS_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R2, SR_TID.X &wr=0x1 ?trans7;
S2UR UR6, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x390] &wr=0x2 ?trans1;
HFMA2 R3, -RZ, RZ, 0, 0 ?WAIT6_END_GROUP;
LDC R5, c[0x0][0x360] &wr=0x1 ?trans1;
LDCU UR7, c[0x0][0x370] &wr=0x3 ?trans1;
USHF.R.S32.HI UR5, URZ, 0x1f, UR4 &req={2} ?trans1;
IMAD R2, R5.reuse, UR6, R2 &req={1} ?trans2;
IMAD R4, R5, UR7, RZ &req={3} ?WAIT3_END_GROUP;
ISETP.GE.U64.AND P0, PT, R2, UR4, PT ?WAIT14_END_GROUP;
@P0 EXIT &req={0} ?trans5;
MOV R5, RZ ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x0 ?trans1;
LDCU.128 UR8, c[0x0][0x380] &wr=0x1 ?trans5;
IADD.64 R6, R2, UR8 &req={1} ?WAIT7_END_GROUP;
LDG.E.U8 R6, desc[UR6][R6.64] &req={2,0} &wr=0x2 ?trans1;
IADD.64 R8, R2, UR10 ?trans2;
IADD.64 R2, R4, R2 ?WAIT6_END_GROUP;
ISETP.GE.U64.AND P0, PT, R2, UR4, PT ?trans2;
IMAD.SHL.U32 R0, R6, 0x4, RZ &req={2} ?WAIT4_END_GROUP;
LDC R11, c[0x3][R0] &wr=0x0 ?trans2;
STG.E.U8 desc[UR6][R8.64], R11 &req={0} &rd=0x2 ?trans6;
@!P0 BRA 0xf0 ?trans5;
EXIT ?trans5;
BRA 0x190;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: imageCreate(unsigned char*, unsigned char*, int)
_Z11imageCreatePhS_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x10
s_load_b32 s6, s[0:1], 0x24
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_ashr_i32 s5, s4, 31
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
v_mov_b32_e32 v2, 0
v_cmpx_gt_u64_e64 s[4:5], v[1:2]
s_cbranch_execz .LBB3_3
s_load_b32 s7, s[2:3], 0x0
s_load_b128 s[0:3], s[0:1], 0x0
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, d_lut@rel32@lo+4
s_addc_u32 s9, s9, d_lut@rel32@hi+12
s_waitcnt lgkmcnt(0)
s_mul_i32 s6, s7, s6
s_mov_b32 s7, 0
.LBB3_2:
v_add_co_u32 v3, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v2, vcc_lo
global_load_u8 v0, v[3:4], off
v_add_co_u32 v3, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, s6
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmp_le_u64_e32 vcc_lo, s[4:5], v[1:2]
s_or_b32 s7, vcc_lo, s7
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v0, 2, v0
global_load_b32 v0, v0, s[8:9]
s_waitcnt vmcnt(0)
global_store_b8 v[3:4], v0, off
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB3_2
.LBB3_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| imageCreate | 670 | 730 | stackv2-00000-of-00015 |
// Demangled: kernelHistogram(int*, unsigned char*, int, int)
Function : _Z15kernelHistogramPiPhii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R9, SR_TID.X &wr=0x1 ?trans7;
S2UR UR10, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR6, c[0x0][0x390] &wr=0x2 ?trans1;
HFMA2 R3, -RZ, RZ, 0, 0 ?trans1;
BSSY.RECONVERGENT B0, 0x1e0 ?trans1;
UMOV UR4, 0x400 ?trans1;
LDCU.64 UR8, c[0x0][0x358] &wr=0x3 ?trans3;
LDC R4, c[0x0][0x360] &wr=0x1 ?trans1;
LDCU UR11, c[0x0][0x370] &wr=0x4 ?trans1;
LDCU.64 UR12, c[0x0][0x388] &wr=0x0 ?trans6;
S2UR UR5, SR_CgaCtaId &wr=0x5 ?trans1;
USHF.R.S32.HI UR7, URZ, 0x1f, UR6 &req={2} ?trans1;
IMAD R2, R4, UR10, R9 &req={1} ?WAIT2_END_GROUP;
IMAD R4, R4, UR11, RZ &req={4} ?WAIT3_END_GROUP;
ISETP.GE.U64.AND P0, PT, R2, UR6, PT ?trans2;
ULEA UR4, UR5, UR4, 0x18 &req={5} ?WAIT6_END_GROUP;
LEA R0, R9, UR4, 0x2 ?WAIT5_END_GROUP;
STS [R0], RZ &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 BRA 0x1d0 &req={3,0} ?trans5;
MOV R5, RZ ?WAIT7_END_GROUP;
IADD.64 R6, R2, UR12 ?WAIT7_END_GROUP;
LDG.E.U8 R6, desc[UR8][R6.64] &wr=0x2 ?trans1;
IADD.64 R2, R4, R2 ?WAIT6_END_GROUP;
ISETP.GE.U64.AND P0, PT, R2, UR6, PT ?WAIT3_END_GROUP;
LEA R8, R6, UR4, 0x2 &req={2,0} ?WAIT5_END_GROUP;
ATOMS.POPC.INC.32 RZ, [R8+URZ] &rd=0x0 ?trans6;
@!P0 BRA 0x160 ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans8;
LDC R4, c[0x0][0x394] &wr=0x2 ?trans8;
LDC.64 R2, c[0x0][0x380] &wr=0x3 ?trans1;
LDS R5, [R0] &wr=0x4 ?trans1;
IMAD R7, R4, UR10, R9 &req={2} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R2, R7, 0x4, R2 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR8][R2.64], R5 &req={4} ?trans1;
EXIT ?trans5;
BRA 0x260;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: kernelHistogram(int*, unsigned char*, int, int)
_Z15kernelHistogramPiPhii:
s_clause 0x2
s_load_b32 s10, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
s_add_u32 s8, s0, 24
s_addc_u32 s9, s1, 0
v_lshlrev_b32_e32 v3, 2, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s10, 0xffff
s_ashr_i32 s1, s2, 31
v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s0, s2
s_mov_b32 s2, exec_lo
ds_store_b32 v3, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u64_e64 s[0:1], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b32 s8, s[8:9], 0x0
v_mov_b32_e32 v4, 1
s_mov_b32 s9, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s8, s10
.LBB0_2:
v_add_co_u32 v5, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, s8
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
global_load_u8 v5, v[5:6], off
v_cmp_le_u64_e32 vcc_lo, s[0:1], v[1:2]
s_or_b32 s9, vcc_lo, s9
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v5, 2, v5
ds_add_u32 v5, v4
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v3
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| kernelHistogram | 935 | 858 | stackv2-00000-of-00015 |
// Demangled: lutCalculate(int*, int, int, int)
Function : _Z12lutCalculatePiiii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R2, SR_TID.X &wr=0x1 ?trans1;
BSSY.RECONVERGENT B0, 0x250 ?trans1;
HFMA2 R12, -RZ, RZ, 0, 0 ?trans1;
MOV R0, RZ ?trans1;
ISETP.GE.U32.AND P0, PT, R2.reuse, 0xf, PT &req={1} ?trans1;
IADD3 R3, PT, PT, R2, 0x1, RZ ?WAIT4_END_GROUP;
LOP3.LUT R25, R3, 0xf, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R25, RZ, PT ?WAIT3_END_GROUP;
@!P0 BRA 0x240 ?trans10;
LOP3.LUT R6, R3, 0x7f0, RZ, 0xc0, !PT ?trans1;
MOV.64 R4, 0x420 ?trans2;
MOV R12, RZ ?trans1;
IADD3 R13, PT, PT, -R6, RZ, RZ ?WAIT7_END_GROUP;
MOV R24, R4 ?trans1;
IADD3 R13, PT, PT, R13, 0x10, RZ ?trans1;
IADD.64 R4, R4, 0x40 ?trans2;
LDC.64 R18, c[0x3][R24+-0x20] &wr=0x1 ?trans1;
IADD3 R0, PT, PT, R0, 0x10, RZ ?trans1;
ISETP.NE.AND P0, PT, R13, RZ, PT ?WAIT6_END_GROUP;
LDC.64 R20, c[0x3][R24+-0x18] &wr=0x2 ?trans8;
LDC.64 R22, c[0x3][R24+-0x10] &wr=0x3 ?trans8;
LDC.64 R16, c[0x3][R24+-0x8] &wr=0x4 ?trans8;
LDC.64 R14, c[0x3][R24] &wr=0x5 ?trans8;
LDC.64 R10, c[0x3][R24+0x8] &wr=0x0 ?trans8;
LDC.64 R8, c[0x3][R24+0x10] &wr=0x0 ?trans1;
IADD3 R18, PT, PT, R19, R18, R12 &req={1} ?WAIT7_END_GROUP;
LDC.64 R6, c[0x3][R24+0x18] &wr=0x1 ?trans1;
IADD3 R18, PT, PT, R21, R20, R18 &req={2} ?WAIT4_END_GROUP;
IADD3 R18, PT, PT, R23, R22, R18 &req={3} ?WAIT4_END_GROUP;
IADD3 R16, PT, PT, R17, R16, R18 &req={4} ?WAIT4_END_GROUP;
IADD3 R14, PT, PT, R15, R14, R16 &req={5} ?WAIT4_END_GROUP;
IADD3 R10, PT, PT, R11, R10, R14 &req={0} ?WAIT4_END_GROUP;
IADD3 R8, PT, PT, R9, R8, R10 ?WAIT4_END_GROUP;
IADD3 R12, PT, PT, R7, R6, R8 &req={1} ?trans1;
@P0 BRA 0xe0 ?trans6;
BSYNC.RECONVERGENT B0 ?trans5;
BSSY.RECONVERGENT B0, 0x4f0 ?trans4;
@!P1 BRA 0x4e0 ?trans5;
ISETP.GE.U32.AND P0, PT, R25, 0x8, PT ?trans1;
LOP3.LUT R5, R3, 0x7, RZ, 0xc0, !PT ?trans1;
BSSY.RECONVERGENT B1, 0x380 ?trans4;
ISETP.NE.AND P1, PT, R5, RZ, PT ?WAIT7_END_GROUP;
@!P0 BRA 0x370 ?trans6;
UMOV UR4, 0x400 ?trans2;
LEA R4, R0.reuse, UR4, 0x2 ?trans2;
IADD3 R0, PT, PT, R0, 0x8, RZ ?trans2;
LDC.64 R6, c[0x3][R4] &wr=0x1 ?trans8;
LDC.64 R8, c[0x3][R4+0x8] &wr=0x2 ?trans8;
LDC.64 R10, c[0x3][R4+0x10] &wr=0x3 ?trans8;
LDC.64 R14, c[0x3][R4+0x18] &wr=0x4 ?trans1;
IADD3 R6, PT, PT, R7, R6, R12 &req={1} ?WAIT4_END_GROUP;
IADD3 R6, PT, PT, R9, R8, R6 &req={2} ?WAIT4_END_GROUP;
IADD3 R6, PT, PT, R11, R10, R6 &req={3} ?WAIT4_END_GROUP;
IADD3 R12, PT, PT, R15, R14, R6 &req={4} ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B1 ?trans5;
@!P1 BRA 0x4e0 ?trans5;
ISETP.GE.U32.AND P0, PT, R5, 0x4, PT ?trans1;
LOP3.LUT R3, R3, 0x3, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R3, RZ, PT ?WAIT7_END_GROUP;
@P0 MOV R5, 0x400 ?WAIT5_END_GROUP;
@P0 IMAD R5, R0.reuse, 0x4, R5 ?trans1;
@P0 IADD3 R0, PT, PT, R0, 0x4, RZ ?WAIT3_END_GROUP;
@P0 LDC.64 R6, c[0x3][R5] &wr=0x1 ?trans8;
@P0 LDC.64 R8, c[0x3][R5+0x8] &wr=0x2 ?trans1;
@P0 IADD3 R6, PT, PT, R7, R6, R12 &req={1} ?WAIT4_END_GROUP;
@P0 IADD3 R12, PT, PT, R9, R8, R6 &req={2} ?trans1;
@!P1 BRA 0x4e0 ?trans6;
MOV.64 R4, 0x400 ?WAIT3_END_GROUP;
IADD3 R3, PT, PT, -R3, RZ, RZ ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R4, R0, 0x4, R4 ?WAIT7_END_GROUP;
MOV R0, R4 ?trans1;
IADD3 R3, PT, PT, R3, 0x1, RZ ?trans1;
IADD.64 R4, R4, 0x4 ?trans2;
LDC R7, c[0x3][R0] &wr=0x1 ?trans2;
ISETP.NE.AND P0, PT, R3, RZ, PT ?trans1;
IADD3 R12, PT, PT, R7, R12, RZ &req={1} ?WAIT12_END_GROUP;
@P0 BRA 0x470 ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
LDCU UR5, c[0x0][0x38c] &wr=0x1 ?trans1;
I2FP.F32.S32 R12, R12 ?trans1;
BSSY.RECONVERGENT B0, 0x630 ?trans1;
LDCU UR4, c[0x0][0x390] &wr=0x2 ?trans1;
I2FP.F32.S32 R3, UR5 &req={1} ?WAIT4_END_GROUP;
MUFU.RCP R4, R3 &wr=0x1 ?trans1;
UI2FP.F32.S32 UR4, UR4 &req={2} ?WAIT6_END_GROUP;
FADD R0, R12, -UR4 ?WAIT4_END_GROUP;
FMUL R0, R0, 255 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans3;
FCHK P0, R0, R3 &wr=0x3 ?trans1;
FFMA R5, -R3, R4, 1 &req={1} ?WAIT4_END_GROUP;
FFMA R5, R4, R5, R4 ?WAIT4_END_GROUP;
FFMA R4, R0, R5, RZ ?WAIT4_END_GROUP;
FFMA R6, -R3, R4, R0 ?WAIT4_END_GROUP;
FFMA R8, R5, R6, R4 ?trans1;
@!P0 BRA 0x620 &req={3,2} ?trans6;
MOV R4, 0x620 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x790 &req={0} ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
LDC.64 R6, c[0x0][0x380] &wr=0x1 ?trans1;
F2F.F64.F32 R4, R8 &wr=0x2 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R4, R4, 0.5 &req={2} &wr=0x2 ?trans1;
IMAD.WIDE.U32 R2, R2, 0x4, R6 &req={1} ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2I.F64.TRUNC R5, R4 &req={2} &wr=0x1 ?trans2;
ISETP.GT.AND P0, PT, R5, -0x1, PT &req={1} ?trans1;
STG.E desc[UR4][R2.64], R5 &rd=0x1 ?WAIT12_END_GROUP;
@!P0 STG.E desc[UR4][R2.64], RZ &rd=0x1 ?trans1;
@!P0 EXIT ?trans5;
ISETP.GE.U32.AND P0, PT, R5, 0x100, PT ?WAIT13_END_GROUP;
@!P0 EXIT ?trans5;
MOV R5, 0xff &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R5 ?trans1;
EXIT ?trans5;
SHF.R.U32.HI R6, RZ, 0x17, R3 ?trans1;
BSSY.RECONVERGENT B1, 0xdf0 ?trans1;
SHF.R.U32.HI R5, RZ, 0x17, R0 ?trans2;
LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R10, R5, 0xff, RZ, 0xc0, !PT ?trans1;
MOV R5, R0 ?trans1;
IADD3 R9, PT, PT, R6, -0x1, RZ ?trans1;
MOV R8, R3 ?trans1;
IADD3 R11, PT, PT, R10, -0x1, RZ ?WAIT3_END_GROUP;
ISETP.GT.U32.AND P0, PT, R9, 0xfd, PT ?WAIT5_END_GROUP;
ISETP.GT.U32.OR P0, PT, R11, 0xfd, P0 ?WAIT13_END_GROUP;
@!P0 MOV R7, RZ ?trans1;
@!P0 BRA 0x9d0 ?trans6;
FSETP.GTU.FTZ.AND P0, PT, |R0|, +INF , PT ?trans1;
FSETP.GTU.FTZ.AND P1, PT, |R3|, +INF , PT ?WAIT5_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, PT, 0xf8, 0x8f ?WAIT13_END_GROUP;
@P0 BRA 0xdd0 ?trans5;
LOP3.LUT P0, RZ, R8, 0x7fffffff, R5, 0xc8, !PT ?WAIT13_END_GROUP;
@!P0 BRA 0xdb0 ?trans5;
FSETP.NEU.FTZ.AND P2, PT, |R0|.reuse, +INF , PT ?trans1;
FSETP.NEU.FTZ.AND P1, PT, |R3|, +INF , PT ?trans1;
FSETP.NEU.FTZ.AND P0, PT, |R0|, +INF , PT ?WAIT12_END_GROUP;
@!P1 BRA !P2, 0xdb0 ?trans5;
LOP3.LUT P2, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P1, PT, P1, P2, PT, 0x2f, 0xf2 ?WAIT13_END_GROUP;
@P1 BRA 0xd90 ?trans5;
LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, PT, 0x2f, 0xf2 ?WAIT13_END_GROUP;
@P0 BRA 0xd60 ?trans5;
ISETP.GE.AND P0, PT, R11, RZ, PT ?trans1;
ISETP.GE.AND P1, PT, R9, RZ, PT ?WAIT12_END_GROUP;
@P0 MOV R7, RZ ?trans1;
@!P0 MOV R7, 0xffffffc0 ?trans1;
@!P0 FFMA R5, R0, 1.84467440737095516160e+19, RZ ?trans1;
@!P1 FFMA R8, R3, 1.84467440737095516160e+19, RZ ?WAIT3_END_GROUP;
@!P1 IADD3 R7, PT, PT, R7, 0x40, RZ ?WAIT7_END_GROUP;
LEA R3, R6, 0xc0800000, 0x17 ?trans1;
BSSY.RECONVERGENT B2, 0xd50 ?trans3;
IADD3 R8, PT, PT, -R3, R8, RZ ?trans2;
IADD3 R3, PT, PT, R10, -0x7f, RZ ?trans2;
MUFU.RCP R9, R8 &wr=0x0 ?trans1;
FADD.FTZ R11, -R8, -RZ ?trans2;
IMAD R0, R3.reuse, -0x800000, R5 ?trans1;
IADD3 R6, PT, PT, R3, 0x7f, -R6 ?WAIT4_END_GROUP;
IADD3 R6, PT, PT, R6, R7, RZ ?trans1;
FFMA R10, R9, R11, 1 &req={0} ?WAIT4_END_GROUP;
FFMA R12, R9, R10, R9 ?WAIT4_END_GROUP;
FFMA R5, R0, R12, RZ ?WAIT4_END_GROUP;
FFMA R10, R11, R5, R0 ?WAIT4_END_GROUP;
FFMA R9, R12, R10, R5 ?WAIT4_END_GROUP;
FFMA R10, R11, R9, R0 ?WAIT4_END_GROUP;
FFMA R5, R12, R10, R9 ?WAIT5_END_GROUP;
SHF.R.U32.HI R0, RZ, 0x17, R5 ?WAIT4_END_GROUP;
LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R8, PT, PT, R0, R6, RZ ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R8, -0x1, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R0, 0xfe, PT ?WAIT13_END_GROUP;
@!P0 BRA 0xd30 ?trans5;
ISETP.GT.AND P0, PT, R8, 0xfe, PT ?WAIT13_END_GROUP;
@P0 BRA 0xd00 ?trans5;
ISETP.GE.AND P0, PT, R8, 0x1, PT ?WAIT13_END_GROUP;
@P0 BRA 0xd40 ?trans5;
ISETP.GE.AND P0, PT, R8, -0x18, PT ?trans1;
LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ?WAIT12_END_GROUP;
@!P0 BRA 0xd40 ?trans5;
FFMA.RZ R0, R12, R10.reuse, R9.reuse ?trans1;
IADD3 R7, PT, PT, R8, 0x20, RZ ?trans1;
FFMA.RM R3, R12, R10.reuse, R9.reuse ?trans1;
ISETP.NE.AND P1, PT, R8.reuse, RZ, PT ?trans1;
ISETP.NE.AND P2, PT, R8, RZ, PT ?trans1;
LOP3.LUT R0, R0, 0x7fffff, RZ, 0xc0, !PT ?trans2;
IADD3 R8, PT, PT, -R8, RZ, RZ ?trans2;
LOP3.LUT R6, R0, 0x800000, RZ, 0xfc, !PT ?trans1;
FFMA.RP R0, R12, R10, R9 ?WAIT3_END_GROUP;
SHF.L.U32 R7, R6, R7, RZ ?trans2;
FSETP.NEU.FTZ.AND P0, PT, R0, R3, PT ?trans1;
SEL R3, R8, RZ, P2 ?trans2;
ISETP.NE.AND P1, PT, R7, RZ, P1 ?WAIT3_END_GROUP;
SHF.R.U32.HI R3, RZ, R3, R6 ?trans2;
PLOP3.LUT P0, PT, P0, P1, PT, 0xf8, 0x8f ?trans2;
SHF.R.U32.HI R7, RZ, 0x1, R3 ?WAIT3_END_GROUP;
SEL R0, RZ, 0x1, !P0 ?WAIT5_END_GROUP;
LOP3.LUT R0, R0, 0x1, R7, 0xf8, !PT ?WAIT4_END_GROUP;
LOP3.LUT R0, R0, R3, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R7, R0, RZ ?WAIT4_END_GROUP;
LOP3.LUT R5, R0, R5, RZ, 0xfc, !PT ?trans1;
BRA 0xd40 ?trans6;
LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ?trans1;
BRA 0xd40 ?trans6;
IMAD R5, R6, 0x800000, R5 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
BRA 0xde0 ?trans5;
LOP3.LUT R5, R8, 0x80000000, R5, 0x48, !PT ?WAIT4_END_GROUP;
LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ?trans1;
BRA 0xde0 ?trans6;
LOP3.LUT R5, R8, 0x80000000, R5, 0x48, !PT ?trans1;
BRA 0xde0 ?trans6;
MUFU.RSQ R5, -QNAN &wr=0x0 ?trans1;
BRA 0xde0 ?trans5;
FADD.FTZ R5, R0, R3 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B1 ?trans5;
MOV R8, R5 &req={0} ?trans1;
HFMA2 R5, -RZ, RZ, 0, 0 ?WAIT4_END_GROUP;
RET.REL.NODEC R4 0x0 ?trans5;
BRA 0xe20;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: lutCalculate(int*, int, int, int)
_Z12lutCalculatePiiii:
v_add_nc_u32_e32 v1, 1, v0
s_mov_b32 s4, 0
s_mov_b32 s5, 0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, d_hist@rel32@lo+4
s_addc_u32 s3, s3, d_hist@rel32@hi+12
.LBB2_1:
s_load_b32 s6, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s5, s6, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_dual_mov_b32 v2, s5 :: v_dual_add_nc_u32 v1, -1, v1
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v1
s_or_b32 s4, vcc_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB2_1
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[2:3], s[0:1], 0xc
v_cvt_f32_i32_e32 v1, v2
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
v_cvt_f32_i32_e32 v2, s3
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v1, v1, v2
v_cvt_f32_i32_e32 v2, s2
v_mul_f32_e32 v1, 0x437f0000, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v3, null, v2, v2, v1
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v4
v_div_scale_f32 v6, vcc_lo, v1, v2, v1
v_mul_f32_e32 v5, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v3, v5, v6
v_fmac_f32_e32 v5, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v5, v6
v_div_fmas_f32 v3, v3, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v1, v3, v2, v1
v_cvt_f64_f32_e32 v[1:2], v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[1:2], v[1:2], 0.5
v_cvt_i32_f64_e32 v2, v[1:2]
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_2)
v_cmp_gt_i32_e64 s2, 0, v2
global_store_b32 v0, v2, s[0:1]
v_cmpx_lt_i32_e32 -1, v2
v_cmp_lt_u32_e32 vcc_lo, 0xff, v2
v_mov_b32_e32 v1, 0xff
s_and_not1_b32 s2, s2, exec_lo
s_and_b32 s4, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s2, s2, s4
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB2_6
v_add_co_u32 v2, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, null, s1, 0, s0
global_store_b32 v[2:3], v1, off
.LBB2_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| lutCalculate | 5,383 | 1,350 | stackv2-00000-of-00015 |
// Demangled: sumReduction(int*, int*)
Function : _Z12sumReductionPiS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R9, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x2 ?trans1;
LDCU.64 UR8, c[0x0][0x358] &wr=0x3 ?trans7;
LDC R4, c[0x0][0x360] &wr=0x2 ?trans8;
LDC.64 R2, c[0x0][0x380] &wr=0x4 ?trans1;
IMAD R0, R4, UR4, RZ &req={2} ?WAIT5_END_GROUP;
IADD3 R5, PT, PT, R0, R9, RZ &req={1} ?WAIT5_END_GROUP;
IMAD.WIDE R2, R5, 0x4, R2 &req={4} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR8][R2.64] &req={3} &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.NE.AND P0, PT, R9, RZ, PT ?trans1;
ULEA UR5, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R7, R9, UR5, 0x2 ?WAIT5_END_GROUP;
STS [R7], R2 &req={2} &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT &req={0} ?trans5;
ISETP.GT.AND P0, PT, R5, 0x9, PT ?trans1;
BSSY.RECONVERGENT B0, 0x640 ?trans1;
HFMA2 R3, -RZ, RZ, 0, 0 ?WAIT11_END_GROUP;
@P0 BRA 0x630 ?trans5;
IADD3 R0, PT, PT, -R0, 0x9, RZ ?trans2;
IADD3 R3, PT, PT, R4, -0x1, RZ ?trans1;
UMOV UR4, URZ ?WAIT4_END_GROUP;
VIMNMX.U32 R0, R0, R3, PT ?trans1;
MOV R3, RZ ?WAIT4_END_GROUP;
ISETP.GE.U32.AND P0, PT, R0.reuse, 0x3, PT ?trans1;
IADD3 R2, PT, PT, R0, 0x1, RZ &req={1} ?WAIT4_END_GROUP;
LOP3.LUT R0, R2, 0x3, RZ, 0xc0, !PT ?WAIT8_END_GROUP;
@!P0 BRA 0x590 ?trans5;
LOP3.LUT R2, R2, 0xfffffffc, RZ, 0xc0, !PT ?trans1;
UIADD3 UR6, UPT, UPT, UR5, 0x8, URZ ?trans1;
UMOV UR4, URZ ?trans2;
IADD3 R2, PT, PT, -R2, RZ, RZ ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R2, RZ, PT ?WAIT13_END_GROUP;
@P0 BRA 0x500 ?trans5;
IADD3 R4, PT, PT, -R2, RZ, RZ ?trans2;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x8 ?WAIT3_END_GROUP;
ISETP.GT.AND P1, PT, R4, 0xc, PT ?WAIT13_END_GROUP;
@!P1 BRA 0x3f0 ?trans5;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x80 ?WAIT13_END_GROUP;
LDS.64 R4, [UR6+-0x8] &wr=0x0 ?trans1;
IADD3 R2, PT, PT, R2, 0x10, RZ ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x10, URZ ?trans2;
LDS.64 R6, [UR6] &wr=0x1 ?trans2;
ISETP.GE.AND P1, PT, R2, -0xc, PT ?trans2;
LDS.64 R8, [UR6+0x8] &wr=0x2 ?trans4;
LDS.64 R10, [UR6+0x10] &wr=0x3 ?trans4;
LDS.64 R12, [UR6+0x18] &wr=0x4 ?trans4;
LDS.64 R14, [UR6+0x20] &wr=0x5 ?trans4;
LDS.64 R16, [UR6+0x28] &wr=0x5 ?trans4;
LDS.64 R18, [UR6+0x30] &wr=0x5 ?trans1;
UIADD3 UR6, UPT, UPT, UR6, 0x40, URZ ?trans1;
IADD3 R4, PT, PT, R5, R4, R3 &req={0} ?WAIT4_END_GROUP;
IADD3 R4, PT, PT, R7, R6, R4 &req={1} ?WAIT4_END_GROUP;
IADD3 R4, PT, PT, R9, R8, R4 &req={2} ?WAIT4_END_GROUP;
IADD3 R4, PT, PT, R11, R10, R4 &req={3} ?WAIT4_END_GROUP;
IADD3 R4, PT, PT, R13, R12, R4 &req={4} ?WAIT4_END_GROUP;
IADD3 R4, PT, PT, R15, R14, R4 &req={5} ?WAIT4_END_GROUP;
IADD3 R4, PT, PT, R17, R16, R4 ?WAIT4_END_GROUP;
IADD3 R3, PT, PT, R19, R18, R4 ?trans1;
@!P1 BRA 0x2a0 ?trans6;
IADD3 R4, PT, PT, -R2, RZ, RZ ?WAIT5_END_GROUP;
ISETP.GT.AND P1, PT, R4, 0x4, PT ?WAIT13_END_GROUP;
@!P1 BRA 0x4e0 ?trans5;
LDS.64 R4, [UR6+-0x8] &wr=0x0 ?trans1;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x80 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x8, URZ ?trans1;
IADD3 R2, PT, PT, R2, 0x8, RZ ?trans1;
LDS.64 R6, [UR6] &wr=0x1 ?trans4;
LDS.64 R8, [UR6+0x8] &wr=0x2 ?trans4;
LDS.64 R10, [UR6+0x10] &wr=0x3 ?trans1;
UIADD3 UR6, UPT, UPT, UR6, 0x20, URZ ?trans1;
IADD3 R4, PT, PT, R5, R4, R3 &req={0} ?WAIT4_END_GROUP;
IADD3 R4, PT, PT, R7, R6, R4 &req={1} ?WAIT4_END_GROUP;
IADD3 R4, PT, PT, R9, R8, R4 &req={2} ?WAIT4_END_GROUP;
IADD3 R3, PT, PT, R11, R10, R4 &req={3} ?WAIT7_END_GROUP;
ISETP.NE.OR P0, PT, R2, RZ, P0 ?WAIT13_END_GROUP;
@!P0 BRA 0x590 ?trans5;
LDS.64 R4, [UR6+-0x8] &wr=0x0 ?trans1;
IADD3 R2, PT, PT, R2, 0x4, RZ ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x4, URZ ?trans2;
LDS.64 R6, [UR6] &wr=0x1 ?trans1;
UIADD3 UR6, UPT, UPT, UR6, 0x10, URZ ?trans1;
ISETP.NE.AND P0, PT, R2, RZ, PT ?trans1;
IADD3 R3, PT, PT, R5, R4, R3 &req={0} ?WAIT4_END_GROUP;
IADD3 R3, PT, PT, R7, R6, R3 &req={1} ?WAIT8_END_GROUP;
@P0 BRA 0x500 ?trans5;
ISETP.NE.AND P0, PT, R0, RZ, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x630 ?trans5;
IADD3 R0, PT, PT, -R0, RZ, RZ ?trans1;
ULEA UR4, UR4, UR5, 0x2 ?WAIT12_END_GROUP;
LDS R2, [UR4] &wr=0x0 ?trans1;
IADD3 R0, PT, PT, R0, 0x1, RZ ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x4, URZ ?WAIT4_END_GROUP;
ISETP.NE.AND P0, PT, R0, RZ, PT ?trans1;
IADD3 R3, PT, PT, R2, R3, RZ &req={0} ?WAIT12_END_GROUP;
@P0 BRA 0x5d0 ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
LDC.64 R4, c[0x0][0x388] &wr=0x0 ?trans2;
REDG.E.ADD.STRONG.GPU desc[UR8][R4.64], R3 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x670;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: sumReduction(int*, int*)
_Z12sumReductionPiS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_mov_b32 s0, exec_lo
global_load_b32 v2, v[2:3], off
v_lshlrev_b32_e32 v3, 2, v0
s_waitcnt vmcnt(0)
ds_store_b32 v3, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_9
v_cmp_gt_i32_e32 vcc_lo, 10, v1
s_cmp_lg_u32 s4, 0
v_mov_b32_e32 v0, 0
s_cselect_b32 s0, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s1, s0, vcc_lo
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v0, 0
s_mov_b32 s1, 1
s_mov_b32 s6, 0
s_mov_b32 s5, 0
.LBB0_3:
v_dual_mov_b32 v2, s6 :: v_dual_add_nc_u32 v3, s1, v1
s_cmp_ge_u32 s1, s4
s_cselect_b32 s7, -1, 0
ds_load_b32 v2, v2
v_cmp_lt_i32_e32 vcc_lo, 9, v3
s_add_i32 s1, s1, 1
s_add_i32 s6, s6, 4
s_or_b32 s7, s7, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s7, exec_lo, s7
s_or_b32 s5, s7, s5
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, v2, v0
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s0
s_mov_b32 s1, exec_lo
s_mov_b32 s0, 0
.LBB0_6:
s_ctz_i32_b32 s4, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s5, v0, s4
s_lshl_b32 s4, 1, s4
s_and_not1_b32 s1, s1, s4
s_delay_alu instid0(VALU_DEP_1)
s_add_i32 s0, s0, s5
s_cmp_lg_u32 s1, 0
s_cbranch_scc1 .LBB0_6
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB0_9
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_atomic_add_u32 v0, v1, s[2:3]
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| sumReduction | 2,550 | 1,231 | stackv2-00000-of-00015 |
// Demangled: vecDotProduct(float*, float*, float*)
Function : _Z13vecDotProductPfS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R13, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x2 ?trans1;
BSSY.RECONVERGENT B0, 0x190 ?trans1;
HFMA2 R11, -RZ, RZ, 0, 0 ?trans1;
S2R R12, SR_TID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x3 ?trans1;
MOV R10, UR4 &req={2} ?trans1;
IMAD R0, R13, UR4, R12 &req={1} ?WAIT5_END_GROUP;
ISETP.GT.AND P0, PT, R0, 0x83ff, PT ?WAIT13_END_GROUP;
@P0 BRA 0x180 &req={3,0} ?trans5;
LDC.64 R6, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU UR4, c[0x0][0x370] &wr=0x1 ?trans1;
MOV R11, RZ ?WAIT6_END_GROUP;
LDC.64 R8, c[0x0][0x388] &wr=0x2 ?trans1;
IMAD R15, R10, UR4, RZ &req={1} ?WAIT7_END_GROUP;
IMAD.WIDE R2, R0, 0x4, R6 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE R4, R0, 0x4, R8 &req={2} ?trans2;
LDG.E R2, desc[UR6][R2.64] &wr=0x2 ?trans4;
LDG.E R4, desc[UR6][R4.64] &wr=0x2 ?trans1;
IADD3 R0, PT, PT, R15, R0, RZ ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, 0x8400, PT ?trans1;
FFMA R11, R2, R4, R11 &req={2} ?WAIT12_END_GROUP;
@!P0 BRA 0x100 ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
S2UR UR5, SR_CgaCtaId &wr=0x0 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GE.U32.AND P1, PT, R10, 0x2, PT ?trans1;
ISETP.NE.AND P0, PT, R12, RZ, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={0} ?WAIT6_END_GROUP;
LEA R0, R12, UR4, 0x2 ?WAIT5_END_GROUP;
STS [R0], R11 &rd=0x0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P1 BRA 0x2d0 ?trans5;
SHF.R.U32.HI R5, RZ, 0x1, R10 ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P1, PT, R12, R5, PT ?WAIT13_END_GROUP;
@!P1 IMAD R2, R5, 0x4, R0 ?trans1;
@!P1 LDS R3, [R0] ?trans5;
@!P1 LDS R2, [R2] &wr=0x1 ?trans2;
@!P1 FADD R3, R2, R3 &req={1} ?WAIT5_END_GROUP;
@!P1 STS [R0], R3 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P1, PT, R10, 0x3, PT ?trans1;
MOV R10, R5 ?WAIT12_END_GROUP;
@P1 BRA 0x220 &req={1} ?trans5;
@P0 EXIT ?trans5;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?WAIT7_END_GROUP;
LDC.64 R2, c[0x0][0x390] &wr=0x2 ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?trans1;
IMAD.WIDE.U32 R2, R13, 0x4, R2 &req={2} ?WAIT8_END_GROUP;
LDS R5, [UR4] &wr=0x1 ?trans4;
STG.E desc[UR6][R2.64], R5 &req={1} ?trans1;
EXIT ?trans5;
BRA 0x360;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: vecDotProduct(float*, float*, float*)
_Z13vecDotProductPfS_S_:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
s_add_u32 s0, s0, 24
s_mov_b32 s2, s15
s_addc_u32 s1, s1, 0
v_mov_b32_e32 v3, 0
s_mov_b32 s10, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_cmpx_gt_i32_e32 0x8400, v1
s_cbranch_execz .LBB0_4
s_load_b32 s1, s[0:1], 0x0
v_mov_b32_e32 v3, 0
s_mov_b32 s0, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s1, s3
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v6, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 0x83ff, v1
global_load_b32 v2, v[6:7], off
global_load_b32 v4, v[4:5], off
s_or_b32 s0, vcc_lo, s0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, v2, v4
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s0
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
v_lshlrev_b32_e32 v1, 2, v0
s_cmp_lt_u32 s3, 2
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_8
.LBB0_5:
s_lshr_b32 s0, s3, 1
s_mov_b32 s1, exec_lo
v_cmpx_gt_u32_e64 s0, v0
s_cbranch_execz .LBB0_7
v_lshl_add_u32 v2, s0, 2, v1
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s1
s_cmp_gt_u32 s3, 3
s_mov_b32 s3, s0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
.LBB0_8:
s_mov_b32 s3, 0
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_10
v_mov_b32_e32 v0, 0
s_lshl_b64 s[0:1], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s8, s0
s_addc_u32 s1, s9, s1
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| vecDotProduct | 1,280 | 1,220 | stackv2-00000-of-00015 |
// Demangled: sumArraysOnGpu(float const*, float const*, float*)
Function : _Z14sumArraysOnGpuPKfS0_Pf
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R9, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R9.reuse, 0x4, R4 &req={2} ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans4;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R6, R9, 0x4, R6 &req={3} ?WAIT4_END_GROUP;
FADD R9, R2, R5 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0xe0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: sumArraysOnGpu(float const*, float const*, float*)
_Z14sumArraysOnGpuPKfS0_Pf:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| sumArraysOnGpu | 426 | 198 | stackv2-00000-of-00015 |
// Demangled: stencil_1d(int*, int*, int)
Function : _Z10stencil_1dPiS_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R10, SR_TID.X &wr=0x1 ?trans7;
LDC R15, c[0x0][0x390] &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x2 ?trans7;
S2UR UR8, SR_CTAID.X &wr=0x3 ?trans8;
LDC R3, c[0x0][0x360] &wr=0x4 ?trans8;
LDC.64 R8, c[0x0][0x380] &wr=0x5 ?trans1;
ISETP.GE.U32.AND P0, PT, R10, R15, PT &req={1} ?WAIT5_END_GROUP;
ISETP.EQ.OR P1, PT, RZ, UR8, P0 &req={3} ?trans1;
IMAD R0, R3, UR8, R10 &req={4} ?WAIT4_END_GROUP;
IMAD.WIDE R4, R0, 0x4, R8 &req={5} ?WAIT8_END_GROUP;
@!P1 IADD3 R7, PT, PT, R0, -R15.reuse, RZ ?trans1;
LDG.E R3, desc[UR6][R4.64] &req={2} &wr=0x2 ?trans4;
@!P1 IMAD.WIDE R6, R7, 0x4, R8 ?trans1;
@!P1 LDG.E R13, desc[UR6][R4.64+0x200] &wr=0x3 ?trans5;
@!P1 LDG.E R6, desc[UR6][R6.64] &wr=0x4 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
IADD3 R2, PT, PT, R10, R15, RZ ?WAIT5_END_GROUP;
IMAD.SHL.U32 R2, R2, 0x4, RZ ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
@!P1 LEA R11, R10, UR4, 0x2 ?trans1;
BSSY.RECONVERGENT B0, 0x230 ?trans2;
STS [R2+UR4], R3 &req={2} &rd=0x1 ?trans4;
@!P1 STS [R11], R6 &req={4} &rd=0x1 ?trans4;
@!P1 STS [R2+UR4+0x200], R13 &req={3} &rd=0x1 ?trans1;
@!P1 BRA 0x220 &req={0} ?trans5;
ISETP.NE.OR P0, PT, RZ, UR8, P0 ?WAIT13_END_GROUP;
@P0 BRA 0x220 ?trans5;
IMAD.WIDE.U32 R4, R0, 0x4, R8 ?WAIT6_END_GROUP;
LDG.E R5, desc[UR6][R4.64+0x200] &wr=0x2 ?trans1;
LEA R3, R10, UR4, 0x2 &req={1} ?WAIT5_END_GROUP;
STS [R3], RZ &rd=0x0 ?trans4;
STS [R2+UR4+0x200], R5 &req={2} &rd=0x0 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GE.AND P0, PT, R15, RZ, PT ?trans1;
HFMA2 R6, -RZ, RZ, 0, 0 &req={1} ?trans1;
SHF.R.S32.HI R3, RZ, 0x1f, R0 &req={0} ?trans2;
IADD3 R4, PT, PT, R2, UR4, RZ ?WAIT9_END_GROUP;
@!P0 BRA 0x7a0 ?trans5;
LDCU.U16 UR5, c[0x0][0x390] &wr=0x0 ?trans1;
ISETP.GE.U32.AND P2, PT, R15.reuse, 0x8, PT ?trans1;
IADD3 R7, PT, PT, R15, R15, RZ ?WAIT4_END_GROUP;
LOP3.LUT R5, R7.reuse, 0xe, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R6, R7, 0x6, RZ, 0xc0, !PT ?WAIT3_END_GROUP;
ISETP.GE.U32.AND P0, PT, R5, 0x7, PT ?trans1;
IADD3 R5, PT, PT, -R15, RZ, RZ ?trans1;
ISETP.GE.U32.AND P1, PT, R6, 0x3, PT ?trans1;
MOV R6, RZ ?trans1;
USHF.L.U32 UR5, UR5, 0x1, URZ &req={0} ?WAIT4_END_GROUP;
ULOP3.LUT UR5, UR5, 0x2, URZ, 0xe2, !UPT ?WAIT4_END_GROUP;
UIADD3 UR5, UPT, UPT, -UR5, URZ, URZ ?trans1;
@!P2 BRA 0x590 ?trans11;
IADD3 R7, PT, PT, R7, 0x1, RZ ?trans2;
LEA R8, R10, UR4, 0x2 ?trans1;
MOV R6, RZ ?trans1;
LOP3.LUT R7, R7, 0xfffffff0, RZ, 0xc0, !PT ?trans2;
IADD3 R8, PT, PT, R8, 0x20, RZ ?trans2;
IADD3 R7, PT, PT, -R7, RZ, RZ ?WAIT7_END_GROUP;
LDS R9, [R8+-0x20] ?trans1;
IADD3 R7, PT, PT, R7, 0x10, RZ ?trans2;
IADD3 R5, PT, PT, R5, 0x10, RZ ?trans1;
LDS R10, [R8+-0x1c] &wr=0x0 ?trans2;
ISETP.NE.AND P2, PT, R7, RZ, PT ?trans2;
LDS R12, [R8+-0x18] ?trans4;
LDS R11, [R8+-0x14] &wr=0x1 ?trans4;
LDS R14, [R8+-0x10] ?trans4;
LDS R13, [R8+-0xc] &wr=0x2 ?trans4;
LDS R16, [R8+-0x8] ?trans4;
LDS R15, [R8+-0x4] &wr=0x3 ?trans4;
LDS R18, [R8] ?trans4;
LDS R17, [R8+0x4] &wr=0x4 ?trans4;
LDS R20, [R8+0x8] ?trans4;
LDS R19, [R8+0xc] &wr=0x5 ?trans1;
IADD3 R9, PT, PT, R10, R9, R6 &req={0} ?WAIT3_END_GROUP;
LDS R22, [R8+0x10] ?trans4;
LDS R21, [R8+0x14] &wr=0x0 ?trans1;
IADD3 R9, PT, PT, R11, R12, R9 &req={1} ?WAIT3_END_GROUP;
LDS R24, [R8+0x18] ?trans4;
LDS R23, [R8+0x1c] &rd=0x1 &wr=0x0 ?trans1;
IADD3 R9, PT, PT, R13, R14, R9 &req={2} ?WAIT4_END_GROUP;
IADD3 R9, PT, PT, R15, R16, R9 &req={3} ?trans2;
IADD3 R8, PT, PT, R8, 0x40, RZ &req={1} ?trans2;
IADD3 R9, PT, PT, R17, R18, R9 &req={4} ?WAIT4_END_GROUP;
IADD3 R9, PT, PT, R19, R20, R9 &req={5} ?WAIT4_END_GROUP;
IADD3 R9, PT, PT, R21, R22, R9 &req={0} ?WAIT4_END_GROUP;
IADD3 R6, PT, PT, R23, R24, R9 ?trans1;
@P2 BRA 0x3c0 ?trans6;
@!P0 BRA 0x680 ?trans5;
IMAD R7, R5.reuse, 0x4, R4 ?trans1;
IADD3 R5, PT, PT, R5, 0x8, RZ ?WAIT4_END_GROUP;
LDS R9, [R7] ?trans4;
LDS R8, [R7+0x4] &wr=0x0 ?trans4;
LDS R11, [R7+0x8] ?trans4;
LDS R10, [R7+0xc] &wr=0x1 ?trans4;
LDS R13, [R7+0x10] ?trans4;
LDS R12, [R7+0x14] &wr=0x2 ?trans4;
LDS R15, [R7+0x18] ?trans4;
LDS R14, [R7+0x1c] &wr=0x3 ?trans1;
IADD3 R8, PT, PT, R8, R9, R6 &req={0} ?WAIT4_END_GROUP;
IADD3 R8, PT, PT, R10, R11, R8 &req={1} ?WAIT4_END_GROUP;
IADD3 R8, PT, PT, R12, R13, R8 &req={2} ?WAIT4_END_GROUP;
IADD3 R6, PT, PT, R14, R15, R8 &req={3} ?WAIT7_END_GROUP;
@!P1 BRA 0x710 ?trans5;
IMAD R4, R5.reuse, 0x4, R4 ?trans1;
IADD3 R5, PT, PT, R5, 0x4, RZ ?WAIT4_END_GROUP;
LDS R7, [R4] ?trans4;
LDS R8, [R4+0x4] &wr=0x0 ?trans4;
LDS R9, [R4+0x8] ?trans4;
LDS R10, [R4+0xc] &wr=0x1 ?trans1;
IADD3 R6, PT, PT, R8, R7, R6 &req={0} ?WAIT4_END_GROUP;
IADD3 R6, PT, PT, R10, R9, R6 &req={1} ?WAIT7_END_GROUP;
IMAD R2, R5, 0x4, R2 ?trans1;
MOV R4, UR5 ?WAIT4_END_GROUP;
IADD3 R2, PT, PT, R2, UR4, RZ ?WAIT7_END_GROUP;
LDS R5, [R2] &rd=0x0 &wr=0x1 ?trans1;
IADD3 R4, PT, PT, R4, 0x1, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R4, 0x1, PT ?trans1;
IADD3 R2, PT, PT, R2, 0x4, RZ &req={0} ?trans2;
IADD3 R6, PT, PT, R5, R6, RZ &req={1} ?WAIT10_END_GROUP;
@P0 BRA 0x740 ?trans5;
LDCU.64 UR8, c[0x0][0x388] &wr=0x0 ?trans2;
LEA R2, P0, R0, UR8, 0x2 &req={0} ?WAIT4_END_GROUP;
LEA.HI.X R3, R0, UR9, R3, 0x2, P0 ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R6 ?trans1;
EXIT ?trans5;
BRA 0x7f0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: stencil_1d(int*, int*, int)
_Z10stencil_1dPiS_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s1, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_cmp_lg_u32 s15, 0
v_mad_u64_u32 v[5:6], null, s15, s2, v[0:1]
v_cmp_gt_u32_e64 s0, s1, v0
v_add_lshl_u32 v7, v0, s1, 2
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s2, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[1:2], 2, v[5:6]
v_lshlrev_b32_e32 v6, 2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s1, v0
global_load_b32 v8, v[3:4], off
s_waitcnt vmcnt(0)
ds_store_b32 v7, v8
s_and_saveexec_b32 s2, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_2
v_subrev_nc_u32_e32 v8, s1, v5
v_lshlrev_b32_e32 v0, 2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v8, s0, s4, v8
v_add_co_ci_u32_e64 v9, s0, s5, v9, s0
s_clause 0x1
global_load_b32 v5, v[8:9], off
global_load_b32 v3, v[3:4], off offset:512
s_waitcnt vmcnt(1)
ds_store_b32 v0, v5
s_waitcnt vmcnt(0)
ds_store_b32 v7, v3 offset:512
.LBB0_2:
s_and_not1_saveexec_b32 s0, s2
s_cbranch_execz .LBB0_6
s_cmp_eq_u32 s15, 0
s_cselect_b32 s2, -1, 0
s_xor_b32 s3, vcc_lo, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s2, s3
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_5
global_load_b32 v3, v[3:4], off offset:512
v_lshlrev_b32_e32 v0, 2, v0
v_mov_b32_e32 v4, 0
ds_store_b32 v0, v4
s_waitcnt vmcnt(0)
ds_store_b32 v7, v3 offset:512
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s0
v_mov_b32_e32 v0, 0
s_cmp_lt_i32 s1, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_9
v_mov_b32_e32 v0, 0
s_lshl_b32 s0, s1, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s0, s0, 1
.LBB0_8:
ds_load_b32 v3, v6
v_add_nc_u32_e32 v6, 4, v6
s_add_i32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s0, 0
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, v3, v0
s_cbranch_scc0 .LBB0_8
.LBB0_9:
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| stencil_1d | 3,148 | 1,423 | stackv2-00000-of-00015 |
// Demangled: stencil_noMem(int*, int*, int, int)
Function : _Z13stencil_noMemPiS_ii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
LDC R8, c[0x0][0x390] &wr=0x1 ?trans1;
S2R R0, SR_TID.X &wr=0x2 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x3 ?trans1;
HFMA2 R2, -RZ, RZ, 0, 0 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x4 ?trans4;
S2UR UR4, SR_CTAID.X &wr=0x3 ?trans1;
ISETP.GE.AND P0, PT, R8, RZ, PT &req={1} ?trans1;
UIMAD UR4, UR4, UR5, URZ &req={3} ?WAIT6_END_GROUP;
IADD3 R3, PT, PT, R0, UR4, RZ &req={2} ?WAIT6_END_GROUP;
@!P0 BRA 0xfb0 &req={4,0} ?trans5;
ISETP.GE.U32.AND P0, PT, R8.reuse, 0x8, PT ?trans1;
IADD3 R4, PT, PT, R8.reuse, R8, RZ ?trans2;
IADD3 R6, PT, PT, -R8, RZ, RZ ?trans1;
MOV R2, RZ ?WAIT9_END_GROUP;
@!P0 BRA 0x8c0 ?trans5;
IADD3 R2, PT, PT, R4, 0x1, RZ ?trans2;
IADD3 R6, PT, PT, -R8, 0x7, RZ ?trans2;
IADD3 R5, PT, PT, R3, -R8, RZ ?trans1;
LDCU UR5, c[0x0][0x394] &wr=0x0 ?trans1;
LOP3.LUT R7, R2, 0xfffffff0, RZ, 0xc0, !PT ?trans1;
MOV R2, RZ ?WAIT3_END_GROUP;
IADD3 R7, PT, PT, -R7, RZ, RZ ?WAIT7_END_GROUP;
ISETP.GE.AND P1, PT, R5.reuse, UR5, PT &req={0} ?trans1;
IADD3 R13, PT, PT, R5, 0x1, RZ ?WAIT4_END_GROUP;
ISETP.LT.OR P1, PT, R5, 0x1, P1 ?trans1;
ISETP.GE.AND P2, PT, R13, UR5, PT ?WAIT5_END_GROUP;
ISETP.LT.OR P2, PT, R13, 0x1, P2 ?WAIT7_END_GROUP;
@!P1 LDC.64 R8, c[0x0][0x380] &wr=0x0 ?trans8;
@!P2 LDC.64 R10, c[0x0][0x380] &wr=0x1 ?trans1;
@!P1 IMAD.WIDE.U32 R8, R5, 0x4, R8 &req={0} ?WAIT6_END_GROUP;
@!P1 LDG.E R9, desc[UR6][R8.64] &wr=0x2 ?trans1;
@!P2 IMAD.WIDE.U32 R10, R13, 0x4, R10 &req={1} ?WAIT6_END_GROUP;
@!P2 LDG.E R11, desc[UR6][R10.64] &wr=0x3 ?trans1;
IADD3 R25, PT, PT, R5.reuse, 0x2, RZ ?trans2;
IADD3 R19, PT, PT, R5.reuse, 0x3, RZ ?trans2;
IADD3 R31, PT, PT, R5.reuse, 0x4, RZ ?trans2;
IADD3 R29, PT, PT, R5.reuse, 0x5, RZ ?trans2;
IADD3 R27, PT, PT, R5, 0x6, RZ ?trans1;
ISETP.GE.AND P4, PT, R25, UR5, PT ?trans1;
ISETP.GE.AND P6, PT, R19, UR5, PT ?trans1;
ISETP.GE.AND P5, PT, R31, UR5, PT ?trans1;
ISETP.GE.AND P0, PT, R29, UR5, PT ?trans1;
ISETP.GE.AND P3, PT, R27, UR5, PT ?trans1;
ISETP.LT.OR P4, PT, R25, 0x1, P4 ?trans1;
ISETP.LT.OR P6, PT, R19, 0x1, P6 ?trans1;
ISETP.LT.OR P5, PT, R31, 0x1, P5 ?trans1;
IADD3 R23, PT, PT, R5, 0x7, RZ ?trans1;
ISETP.LT.OR P0, PT, R29, 0x1, P0 ?trans1;
IADD3 R21, PT, PT, R5, 0x8, RZ ?WAIT8_END_GROUP;
@!P4 LDC.64 R12, c[0x0][0x380] &wr=0x0 ?trans8;
@!P6 LDC.64 R16, c[0x0][0x380] &wr=0x1 ?trans8;
@!P5 LDC.64 R14, c[0x0][0x380] &wr=0x4 ?trans1;
@!P4 IMAD.WIDE.U32 R24, R25, 0x4, R12 &req={0} ?WAIT6_END_GROUP;
@!P4 LDG.E R25, desc[UR6][R24.64] &wr=0x5 ?trans1;
@!P6 IMAD.WIDE.U32 R16, R19, 0x4, R16 &req={1} ?WAIT6_END_GROUP;
@!P6 LDG.E R17, desc[UR6][R16.64] &wr=0x5 ?trans1;
@!P5 IMAD.WIDE.U32 R14, R31, 0x4, R14 &req={4} ?WAIT6_END_GROUP;
@!P5 LDG.E R15, desc[UR6][R14.64] &wr=0x4 ?trans1;
@!P1 IADD3 R2, PT, PT, R2, R9, RZ &req={2} ?trans1;
ISETP.LT.OR P1, PT, R27, 0x1, P3 ?trans1;
ISETP.GE.AND P3, PT, R23, UR5, PT ?trans1;
@!P0 LDC.64 R8, c[0x0][0x380] &wr=0x0 ?trans1;
@!P2 IADD3 R2, PT, PT, R2, R11, RZ &req={3} ?WAIT3_END_GROUP;
ISETP.LT.OR P2, PT, R23, 0x1, P3 ?trans1;
ISETP.GE.AND P3, PT, R21, UR5, PT ?WAIT6_END_GROUP;
@!P1 LDC.64 R10, c[0x0][0x380] &wr=0x1 ?trans1;
ISETP.LT.OR P3, PT, R21, 0x1, P3 ?WAIT7_END_GROUP;
@!P2 LDC.64 R12, c[0x0][0x380] &wr=0x2 ?trans8;
@!P3 LDC.64 R18, c[0x0][0x380] &wr=0x3 ?trans1;
@!P0 IMAD.WIDE.U32 R8, R29, 0x4, R8 &req={0} ?WAIT6_END_GROUP;
@!P0 LDG.E R9, desc[UR6][R8.64] &wr=0x4 ?trans1;
@!P1 IMAD.WIDE.U32 R10, R27, 0x4, R10 &req={1} ?WAIT6_END_GROUP;
@!P1 LDG.E R11, desc[UR6][R10.64] &wr=0x4 ?trans1;
@!P2 IMAD.WIDE.U32 R12, R23, 0x4, R12 &req={2} ?WAIT6_END_GROUP;
@!P2 LDG.E R13, desc[UR6][R12.64] &wr=0x2 ?trans1;
@!P3 IMAD.WIDE.U32 R18, R21, 0x4, R18 &req={3} ?WAIT6_END_GROUP;
@!P3 LDG.E R19, desc[UR6][R18.64] &wr=0x3 ?trans1;
IADD3 R33, PT, PT, R5.reuse, 0x9, RZ ?trans2;
@!P4 IADD3 R2, PT, PT, R2, R25, RZ &req={5} ?trans2;
IADD3 R35, PT, PT, R5, 0xa, RZ ?trans1;
ISETP.GE.AND P4, PT, R33, UR5, PT ?trans1;
IADD3 R31, PT, PT, R5, 0xb, RZ ?trans2;
@!P6 IADD3 R2, PT, PT, R2, R17, RZ ?trans1;
ISETP.GE.AND P6, PT, R35, UR5, PT ?trans1;
ISETP.LT.OR P4, PT, R33, 0x1, P4 ?trans1;
IADD3 R29, PT, PT, R5, 0xc, RZ ?WAIT2_END_GROUP;
@!P5 IADD3 R2, PT, PT, R2, R15, RZ &req={4} ?trans1;
ISETP.LT.OR P5, PT, R35, 0x1, P6 ?trans1;
ISETP.GE.AND P6, PT, R31, UR5, PT ?trans1;
IADD3 R27, PT, PT, R5, 0xd, RZ ?WAIT4_END_GROUP;
ISETP.LT.OR P6, PT, R31, 0x1, P6 ?WAIT3_END_GROUP;
@!P4 LDC.64 R20, c[0x0][0x380] &wr=0x0 ?trans1;
IADD3 R25, PT, PT, R5.reuse, 0xe, RZ ?trans2;
IADD3 R23, PT, PT, R5, 0xf, RZ ?WAIT5_END_GROUP;
@!P5 LDC.64 R16, c[0x0][0x380] &wr=0x1 ?trans8;
@!P6 LDC.64 R14, c[0x0][0x380] &wr=0x4 ?trans1;
@!P4 IMAD.WIDE.U32 R20, R33, 0x4, R20 &req={0} ?WAIT6_END_GROUP;
@!P4 LDG.E R21, desc[UR6][R20.64] &wr=0x5 ?trans1;
@!P5 IMAD.WIDE.U32 R16, R35, 0x4, R16 &req={1} ?WAIT6_END_GROUP;
@!P5 LDG.E R17, desc[UR6][R16.64] &wr=0x5 ?trans1;
@!P6 IMAD.WIDE.U32 R14, R31, 0x4, R14 &req={4} ?WAIT6_END_GROUP;
@!P6 LDG.E R15, desc[UR6][R14.64] &wr=0x4 ?trans1;
@!P0 IADD3 R2, PT, PT, R2, R9, RZ ?trans1;
ISETP.GE.AND P0, PT, R29, UR5, PT ?WAIT5_END_GROUP;
ISETP.LT.OR P0, PT, R29, 0x1, P0 ?trans1;
@!P1 IADD3 R2, PT, PT, R2, R11, RZ ?trans1;
ISETP.GE.AND P1, PT, R27, UR5, PT ?WAIT5_END_GROUP;
ISETP.LT.OR P1, PT, R27, 0x1, P1 ?trans1;
@!P2 IADD3 R2, PT, PT, R2, R13, RZ &req={2} ?trans1;
ISETP.GE.AND P2, PT, R25, UR5, PT ?WAIT4_END_GROUP;
@!P0 LDC.64 R8, c[0x0][0x380] &wr=0x0 ?trans1;
ISETP.LT.OR P2, PT, R25, 0x1, P2 ?trans1;
@!P3 IADD3 R2, PT, PT, R2, R19, RZ &req={3} ?trans1;
ISETP.GE.AND P3, PT, R23, UR5, PT ?WAIT5_END_GROUP;
@!P1 LDC.64 R10, c[0x0][0x380] &wr=0x1 ?trans1;
ISETP.LT.OR P3, PT, R23, 0x1, P3 ?WAIT7_END_GROUP;
@!P2 LDC.64 R12, c[0x0][0x380] &wr=0x2 ?trans8;
@!P3 LDC.64 R18, c[0x0][0x380] &wr=0x3 ?trans1;
@!P0 IMAD.WIDE.U32 R8, R29, 0x4, R8 &req={0} ?WAIT6_END_GROUP;
@!P0 LDG.E R9, desc[UR6][R8.64] &wr=0x4 ?trans1;
@!P1 IMAD.WIDE.U32 R10, R27, 0x4, R10 &req={1} ?WAIT6_END_GROUP;
@!P1 LDG.E R11, desc[UR6][R10.64] &wr=0x4 ?trans1;
@!P2 IMAD.WIDE.U32 R12, R25, 0x4, R12 &req={2} ?WAIT6_END_GROUP;
@!P2 LDG.E R13, desc[UR6][R12.64] &wr=0x2 ?trans1;
@!P3 IMAD.WIDE.U32 R18, R23, 0x4, R18 &req={3} ?WAIT6_END_GROUP;
@!P3 LDG.E R19, desc[UR6][R18.64] &wr=0x3 ?trans1;
@!P4 IADD3 R2, PT, PT, R2, R21, RZ &req={5} ?trans2;
IADD3 R7, PT, PT, R7, 0x10, RZ ?trans2;
@!P5 IADD3 R2, PT, PT, R2, R17, RZ ?WAIT4_END_GROUP;
@!P6 IADD3 R2, PT, PT, R2, R15, RZ &req={4} ?trans2;
IADD3 R6, PT, PT, R6, 0x10, RZ ?trans2;
IADD3 R5, PT, PT, R5, 0x10, RZ ?trans2;
@!P0 IADD3 R2, PT, PT, R2, R9, RZ ?trans1;
ISETP.NE.AND P0, PT, R7, RZ, PT ?WAIT3_END_GROUP;
@!P1 IADD3 R2, PT, PT, R2, R11, RZ ?WAIT4_END_GROUP;
@!P2 IADD3 R2, PT, PT, R2, R13, RZ &req={2} ?WAIT4_END_GROUP;
@!P3 IADD3 R2, PT, PT, R2, R19, RZ &req={3} ?trans2;
@P0 BRA 0x170 ?trans5;
IADD3 R6, PT, PT, R6, -0x7, RZ ?WAIT7_END_GROUP;
LDCU.U16 UR5, c[0x0][0x390] &wr=0x0 ?trans1;
LOP3.LUT R5, R4.reuse, 0xe, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R4, R4, 0x6, RZ, 0xc0, !PT ?trans1;
LDCU UR9, c[0x0][0x394] &wr=0x1 ?trans2;
ISETP.GE.U32.AND P0, PT, R5, 0x7, PT ?trans2;
ISETP.GE.U32.AND P6, PT, R4, 0x3, PT ?trans1;
USHF.L.U32 UR5, UR5, 0x1, URZ &req={0} ?WAIT4_END_GROUP;
ULOP3.LUT UR5, UR5, 0x2, URZ, 0xe2, !UPT ?WAIT4_END_GROUP;
UIADD3 UR5, UPT, UPT, -UR5, URZ, URZ ?trans2;
@!P0 BRA 0xd00 &req={1} ?trans10;
LDCU UR8, c[0x0][0x394] &wr=0x0 ?trans1;
IADD3 R7, PT, PT, R3, R6, RZ ?WAIT4_END_GROUP;
IADD3 R11, PT, PT, R7.reuse, 0x1, RZ ?trans1;
ISETP.GE.AND P3, PT, R7, UR8, PT &req={0} ?WAIT4_END_GROUP;
ISETP.GE.AND P4, PT, R11, UR8, PT ?trans1;
ISETP.LT.OR P3, PT, R7, 0x1, P3 ?WAIT4_END_GROUP;
ISETP.LT.OR P4, PT, R11, 0x1, P4 ?WAIT9_END_GROUP;
@!P3 LDC.64 R4, c[0x0][0x380] &wr=0x0 ?trans8;
@!P4 LDC.64 R8, c[0x0][0x380] &wr=0x1 ?trans1;
@!P3 IMAD.WIDE.U32 R4, R7, 0x4, R4 &req={0} ?WAIT6_END_GROUP;
@!P3 LDG.E R5, desc[UR6][R4.64] &wr=0x2 ?trans1;
@!P4 IMAD.WIDE.U32 R8, R11, 0x4, R8 &req={1} ?WAIT6_END_GROUP;
@!P4 LDG.E R9, desc[UR6][R8.64] &wr=0x3 ?trans1;
IADD3 R19, PT, PT, R7.reuse, 0x2, RZ ?trans2;
IADD3 R21, PT, PT, R7.reuse, 0x3, RZ ?trans2;
IADD3 R23, PT, PT, R7.reuse, 0x4, RZ ?trans2;
IADD3 R25, PT, PT, R7.reuse, 0x5, RZ ?trans2;
IADD3 R27, PT, PT, R7, 0x6, RZ ?trans1;
ISETP.GE.AND P0, PT, R19, UR8, PT ?trans1;
ISETP.GE.AND P1, PT, R21, UR8, PT ?trans1;
ISETP.GE.AND P2, PT, R23, UR8, PT ?trans1;
ISETP.GE.AND P5, PT, R25, UR8, PT ?trans1;
IADD3 R7, PT, PT, R7, 0x7, RZ ?trans1;
ISETP.LT.OR P0, PT, R19, 0x1, P0 ?trans1;
ISETP.LT.OR P1, PT, R21, 0x1, P1 ?trans1;
ISETP.LT.OR P2, PT, R23, 0x1, P2 ?trans1;
ISETP.LT.OR P5, PT, R25, 0x1, P5 ?WAIT10_END_GROUP;
@!P0 LDC.64 R14, c[0x0][0x380] &wr=0x0 ?trans8;
@!P1 LDC.64 R16, c[0x0][0x380] &wr=0x1 ?trans8;
@!P2 LDC.64 R12, c[0x0][0x380] &wr=0x4 ?trans8;
@!P5 LDC.64 R10, c[0x0][0x380] &wr=0x5 ?trans1;
@!P0 IMAD.WIDE.U32 R14, R19, 0x4, R14 &req={0} ?WAIT6_END_GROUP;
@!P0 LDG.E R15, desc[UR6][R14.64] &wr=0x3 ?trans1;
@!P1 IMAD.WIDE.U32 R16, R21, 0x4, R16 &req={1} ?WAIT6_END_GROUP;
@!P1 LDG.E R17, desc[UR6][R16.64] &wr=0x3 ?trans1;
@!P2 IMAD.WIDE.U32 R12, R23, 0x4, R12 &req={4} ?WAIT6_END_GROUP;
@!P2 LDG.E R13, desc[UR6][R12.64] &wr=0x4 ?trans1;
@!P5 IMAD.WIDE.U32 R10, R25, 0x4, R10 &req={5} ?WAIT6_END_GROUP;
@!P5 LDG.E R11, desc[UR6][R10.64] &wr=0x5 ?trans1;
@!P3 IADD3 R2, PT, PT, R2, R5, RZ &req={2} ?trans1;
ISETP.GE.AND P3, PT, R27, UR8, PT ?WAIT5_END_GROUP;
ISETP.LT.OR P3, PT, R27, 0x1, P3 ?trans1;
@!P4 IADD3 R2, PT, PT, R2, R9, RZ &req={3} ?trans1;
ISETP.GE.AND P4, PT, R7, UR8, PT ?WAIT5_END_GROUP;
ISETP.LT.OR P4, PT, R7, 0x1, P4 ?WAIT6_END_GROUP;
@!P3 LDC.64 R8, c[0x0][0x380] &wr=0x0 ?trans8;
@!P4 LDC.64 R4, c[0x0][0x380] &wr=0x1 ?trans1;
@!P3 IMAD.WIDE.U32 R8, R27, 0x4, R8 &req={0} ?WAIT6_END_GROUP;
@!P3 LDG.E R9, desc[UR6][R8.64] &wr=0x2 ?trans1;
@!P4 IMAD.WIDE.U32 R4, R7, 0x4, R4 &req={1} ?WAIT6_END_GROUP;
@!P4 LDG.E R5, desc[UR6][R4.64] &wr=0x3 ?trans1;
@!P0 IADD3 R2, PT, PT, R2, R15, RZ ?WAIT4_END_GROUP;
@!P1 IADD3 R2, PT, PT, R2, R17, RZ ?WAIT4_END_GROUP;
@!P2 IADD3 R2, PT, PT, R2, R13, RZ &req={4} ?WAIT4_END_GROUP;
@!P5 IADD3 R2, PT, PT, R2, R11, RZ &req={5} ?trans2;
IADD3 R6, PT, PT, R6, 0x8, RZ ?trans2;
@!P3 IADD3 R2, PT, PT, R2, R9, RZ &req={2} ?WAIT4_END_GROUP;
@!P4 IADD3 R2, PT, PT, R2, R5, RZ &req={3} ?WAIT7_END_GROUP;
@!P6 BRA 0xef0 ?trans5;
LDCU UR8, c[0x0][0x394] &wr=0x0 ?trans1;
IADD3 R19, PT, PT, R3, R6, RZ ?WAIT4_END_GROUP;
IADD3 R7, PT, PT, R19.reuse, 0x1, RZ ?trans2;
IADD3 R15, PT, PT, R19.reuse, 0x2, RZ ?trans2;
IADD3 R17, PT, PT, R19.reuse, 0x3, RZ ?trans1;
ISETP.GE.AND P0, PT, R19, UR8, PT &req={0} ?trans1;
ISETP.GE.AND P1, PT, R7, UR8, PT ?trans1;
ISETP.GE.AND P2, PT, R15, UR8, PT ?trans2;
ISETP.GE.AND P3, PT, R17, UR8, PT ?trans1;
ISETP.LT.OR P0, PT, R19, 0x1, P0 ?trans1;
ISETP.LT.OR P1, PT, R7, 0x1, P1 ?trans1;
ISETP.LT.OR P2, PT, R15, 0x1, P2 ?WAIT2_END_GROUP;
ISETP.LT.OR P3, PT, R17, 0x1, P3 ?WAIT9_END_GROUP;
@!P0 LDC.64 R4, c[0x0][0x380] &wr=0x0 ?trans8;
@!P1 LDC.64 R8, c[0x0][0x380] &wr=0x1 ?trans8;
@!P2 LDC.64 R10, c[0x0][0x380] &wr=0x2 ?trans8;
@!P3 LDC.64 R12, c[0x0][0x380] &wr=0x3 ?trans1;
@!P0 IMAD.WIDE.U32 R4, R19, 0x4, R4 &req={0} ?WAIT6_END_GROUP;
@!P0 LDG.E R5, desc[UR6][R4.64] &wr=0x4 ?trans1;
@!P1 IMAD.WIDE.U32 R8, R7, 0x4, R8 &req={1} ?WAIT6_END_GROUP;
@!P1 LDG.E R9, desc[UR6][R8.64] &wr=0x5 ?trans1;
@!P2 IMAD.WIDE.U32 R10, R15, 0x4, R10 &req={2} ?WAIT6_END_GROUP;
@!P2 LDG.E R11, desc[UR6][R10.64] &wr=0x2 ?trans1;
@!P3 IMAD.WIDE.U32 R12, R17, 0x4, R12 &req={3} ?WAIT6_END_GROUP;
@!P3 LDG.E R13, desc[UR6][R12.64] &wr=0x3 ?trans1;
IADD3 R6, PT, PT, R6, 0x4, RZ ?trans2;
@!P0 IADD3 R2, PT, PT, R2, R5, RZ &req={4} ?WAIT4_END_GROUP;
@!P1 IADD3 R2, PT, PT, R2, R9, RZ &req={5} ?WAIT4_END_GROUP;
@!P2 IADD3 R2, PT, PT, R2, R11, RZ &req={2} ?WAIT4_END_GROUP;
@!P3 IADD3 R2, PT, PT, R2, R13, RZ &req={3} ?WAIT7_END_GROUP;
MOV R8, UR5 ?trans1;
IADD3 R7, PT, PT, R0, UR4, R6 ?WAIT7_END_GROUP;
ISETP.GE.AND P0, PT, R7, UR9, PT ?WAIT5_END_GROUP;
ISETP.LT.OR P0, PT, R7, 0x1, P0 ?WAIT13_END_GROUP;
@!P0 LDC.64 R4, c[0x0][0x380] &wr=0x0 ?trans2;
@!P0 IMAD.WIDE.U32 R4, R7, 0x4, R4 &req={0} ?WAIT6_END_GROUP;
@!P0 LDG.E R5, desc[UR6][R4.64] &wr=0x2 ?trans1;
IADD3 R8, PT, PT, R8, 0x1, RZ ?trans2;
IADD3 R7, PT, PT, R7, 0x1, RZ ?WAIT3_END_GROUP;
ISETP.NE.AND P1, PT, R8, 0x1, PT ?trans1;
@!P0 IADD3 R2, PT, PT, R2, R5, RZ &req={2} ?WAIT12_END_GROUP;
@P1 BRA 0xf10 ?trans5;
LDC.64 R4, c[0x0][0x388] &wr=0x0 ?trans2;
IMAD.WIDE R4, R3, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R4.64], R2 ?trans1;
EXIT ?trans5;
BRA 0xff0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: stencil_noMem(int*, int*, int, int)
_Z13stencil_noMemPiS_ii:
s_clause 0x2
s_load_b32 s8, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s8, 0xffff
s_cmp_lt_i32 s2, 0
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
v_mov_b32_e32 v0, 0
s_cbranch_scc1 .LBB1_5
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_subrev_nc_u32_e32 v2, s2, v1
s_lshl_b32 s0, s2, 1
s_or_b32 s1, s0, 1
s_delay_alu instid0(VALU_DEP_2)
v_mov_b32_e32 v0, v3
.LBB1_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, 0, v2
v_cmp_gt_i32_e64 s0, s3, v2
s_and_b32 s2, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s2
s_cbranch_execz .LBB1_4
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v4, v0
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v2, 1, v2
s_add_i32 s1, s1, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s1, 0
s_cbranch_scc0 .LBB1_2
.LBB1_5:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| stencil_noMem | 7,427 | 877 | stackv2-00000-of-00015 |
// Demangled: BFS(int*, int*, int*, int*, int, int, int*, int*, int*)
Function : _Z3BFSPiS_S_S_iiS_S_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R2, c[0x0][0x398] &wr=0x1 ?trans2;
LDG.E R2, desc[UR6][R2.64] &req={1} &wr=0x2 ?trans6;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
LDC R5, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R5, R5, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R5, R2, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x390] &wr=0x0 ?trans1;
LDCU UR4, c[0x0][0x3a0] &wr=0x1 ?trans1;
IMAD.WIDE R2, R5, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
LDC.64 R4, c[0x0][0x380] &wr=0x0 ?trans1;
LDG.E R3, desc[UR6][R2.64] &wr=0x2 ?trans1;
LDCU UR5, c[0x0][0x3a4] &wr=0x3 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, -0x1, URZ &req={1} ?trans1;
MOV R11, UR5 &req={3} ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R3.reuse, UR4, PT &req={2} ?trans1;
IMAD.WIDE R4, R3, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
LDG.E R10, desc[UR6][R4.64] &wr=0x2 ?trans7;
@P0 LDG.E R11, desc[UR6][R4.64+0x4] &wr=0x2 ?trans2;
ISETP.GE.AND P0, PT, R10, R11, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LDCU.64 UR4, c[0x0][0x3b8] &wr=0x0 ?trans1;
IADD3 R0, PT, PT, -R10, R11, RZ ?trans2;
SHF.R.S32.HI R4, RZ, 0x1f, R3 ?trans1;
BSSY.RECONVERGENT B0, 0x440 ?trans1;
LOP3.LUT P0, R18, R0, 0x3, RZ, 0xc0, !PT ?trans1;
MOV R0, R10 ?trans1;
LEA R2, P1, R3, UR4, 0x2 &req={0} ?WAIT4_END_GROUP;
LEA.HI.X R3, R3, UR5, R4, 0x2, P1 ?WAIT7_END_GROUP;
@!P0 BRA 0x430 ?trans5;
LDC.64 R4, c[0x0][0x3a8] &wr=0x0 ?trans1;
IADD3 R18, PT, PT, -R18, RZ, RZ ?trans1;
MOV R0, R10 ?WAIT6_END_GROUP;
LDC.64 R6, c[0x0][0x388] &wr=0x1 ?trans8;
LDC.64 R8, c[0x0][0x3b8] &wr=0x2 ?trans2;
IMAD.WIDE R12, R0, 0x4, R6 &req={1} ?WAIT5_END_GROUP;
LDG.E R23, desc[UR6][R12.64] &wr=0x3 ?trans2;
IMAD.WIDE R16, R23, 0x4, R8 &req={3,2} ?WAIT5_END_GROUP;
LDG.E R14, desc[UR6][R16.64] &wr=0x2 ?trans1;
IADD3 R18, PT, PT, R18, 0x1, RZ ?trans1;
BSSY.RECONVERGENT B1, 0x410 ?trans4;
ISETP.NE.AND P0, PT, R18, RZ, PT ?trans1;
ISETP.GT.AND P1, PT, R14, -0x1, PT &req={2} ?WAIT13_END_GROUP;
@P1 BRA 0x400 ?trans5;
LDG.E R14, desc[UR6][R2.64] &wr=0x2 ?trans1;
VOTEU.ANY UR4, UPT, PT ?trans2;
FLO.U32 R20, UR4 &wr=0x1 ?trans1;
S2R R13, SR_LANEID &wr=0x1 ?trans1;
POPC R21, UR4 &wr=0x3 ?trans1;
ISETP.EQ.U32.AND P1, PT, R20, R13, PT &req={1} ?trans2;
LDC.64 R12, c[0x0][0x3b0] &wr=0x3 ?trans1;
IADD3 R19, PT, PT, R14, 0x1, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R16.64], R19 ?trans5;
@P1 ATOMG.E.ADD.STRONG.GPU PT, R13, desc[UR6][R12.64], R21 &req={3} &wr=0x2 ?trans1;
S2R R14, SR_LTMASK &wr=0x1 ?trans2;
LOP3.LUT R22, R14, UR4, RZ, 0xc0, !PT &req={1} ?WAIT6_END_GROUP;
POPC R22, R22 &wr=0x1 ?trans1;
SHFL.IDX PT, R15, R13, R20, 0x1f &req={2} &wr=0x1 ?trans2;
IADD3 R15, PT, PT, R15, R22, RZ &req={1} ?WAIT5_END_GROUP;
IMAD.WIDE R14, R15, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R14.64], R23 &rd=0x1 ?trans2;
BSYNC.RECONVERGENT B1 ?trans5;
IADD3 R0, PT, PT, R0, 0x1, RZ ?trans1;
@P0 BRA 0x260 ?trans6;
BSYNC.RECONVERGENT B0 ?trans5;
IADD3 R4, PT, PT, R10, -R11, RZ &req={0} ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R4, -0x4, PT ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LDC.64 R8, c[0x0][0x388] &wr=0x0 ?trans1;
IADD3 R11, PT, PT, R0, -R11, RZ ?WAIT7_END_GROUP;
LDC.64 R4, c[0x0][0x3a8] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x3b8] &wr=0x3 ?trans1;
IADD.64 R8, R8, 0x8 &req={0} ?WAIT8_END_GROUP;
IMAD.WIDE R12, R0, 0x4, R8 &req={0} ?WAIT5_END_GROUP;
LDG.E R25, desc[UR6][R12.64+-0x8] &wr=0x4 ?trans2;
IMAD.WIDE R16, R25, 0x4, R6 &req={4,3} ?WAIT5_END_GROUP;
LDG.E R10, desc[UR6][R16.64] &wr=0x3 ?trans1;
BSSY.RECONVERGENT B0, 0x650 ?trans1;
ISETP.GT.AND P0, PT, R10, -0x1, PT &req={3} ?WAIT13_END_GROUP;
@P0 BRA 0x640 ?trans5;
LDG.E R10, desc[UR6][R2.64] &wr=0x3 ?trans1;
VOTEU.ANY UR4, UPT, PT ?trans1;
LDC.64 R18, c[0x0][0x3b0] &wr=0x0 ?trans1;
S2R R15, SR_LANEID &req={1} &wr=0x1 ?trans1;
FLO.U32 R20, UR4 &wr=0x1 ?trans1;
POPC R23, UR4 &wr=0x0 ?trans1;
ISETP.EQ.U32.AND P0, PT, R20, R15, PT &req={1} ?trans1;
IADD3 R21, PT, PT, R10, 0x1, RZ &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R16.64], R21 ?trans7;
@P0 ATOMG.E.ADD.STRONG.GPU PT, R19, desc[UR6][R18.64], R23 &req={0} &wr=0x3 ?trans1;
S2R R10, SR_LTMASK &wr=0x0 ?trans2;
LOP3.LUT R10, R10, UR4, RZ, 0xc0, !PT &req={0} ?WAIT6_END_GROUP;
POPC R10, R10 &wr=0x0 ?trans1;
SHFL.IDX PT, R15, R19, R20, 0x1f &req={3} &wr=0x0 ?trans2;
IADD3 R15, PT, PT, R15, R10, RZ &req={0} ?WAIT5_END_GROUP;
IMAD.WIDE R14, R15, 0x4, R4 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R14.64], R25 &rd=0x0 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
LDG.E R25, desc[UR6][R12.64+-0x4] &req={0} &wr=0x3 ?trans2;
IMAD.WIDE R16, R25, 0x4, R6 &req={3} ?WAIT5_END_GROUP;
LDG.E R10, desc[UR6][R16.64] &wr=0x3 ?trans1;
BSSY.RECONVERGENT B0, 0x7d0 ?trans1;
ISETP.GT.AND P0, PT, R10, -0x1, PT &req={3} ?WAIT13_END_GROUP;
@P0 BRA 0x7c0 ?trans5;
LDG.E R10, desc[UR6][R2.64] &wr=0x3 ?trans1;
VOTEU.ANY UR4, UPT, PT ?trans1;
LDC.64 R18, c[0x0][0x3b0] &wr=0x0 ?trans1;
S2R R15, SR_LANEID &req={1} &wr=0x1 ?trans1;
FLO.U32 R20, UR4 &wr=0x1 ?trans1;
POPC R23, UR4 &wr=0x0 ?trans1;
ISETP.EQ.U32.AND P0, PT, R20, R15, PT &req={1} ?trans1;
IADD3 R21, PT, PT, R10, 0x1, RZ &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R16.64], R21 ?trans7;
@P0 ATOMG.E.ADD.STRONG.GPU PT, R19, desc[UR6][R18.64], R23 &req={0} &wr=0x3 ?trans1;
S2R R10, SR_LTMASK &wr=0x0 ?trans2;
LOP3.LUT R10, R10, UR4, RZ, 0xc0, !PT &req={0} ?WAIT6_END_GROUP;
POPC R10, R10 &wr=0x0 ?trans1;
SHFL.IDX PT, R15, R19, R20, 0x1f &req={3} &wr=0x0 ?trans2;
IADD3 R15, PT, PT, R15, R10, RZ &req={0} ?WAIT5_END_GROUP;
IMAD.WIDE R14, R15, 0x4, R4 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R14.64], R25 &rd=0x0 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
LDG.E R25, desc[UR6][R12.64] &req={0} &wr=0x3 ?trans2;
IMAD.WIDE R16, R25, 0x4, R6 &req={3} ?WAIT5_END_GROUP;
LDG.E R10, desc[UR6][R16.64] &wr=0x3 ?trans1;
BSSY.RECONVERGENT B0, 0x950 ?trans1;
ISETP.GT.AND P0, PT, R10, -0x1, PT &req={3} ?WAIT13_END_GROUP;
@P0 BRA 0x940 ?trans5;
LDG.E R10, desc[UR6][R2.64] &wr=0x3 ?trans1;
VOTEU.ANY UR4, UPT, PT ?trans1;
LDC.64 R18, c[0x0][0x3b0] &wr=0x0 ?trans1;
S2R R15, SR_LANEID &req={1} &wr=0x1 ?trans1;
FLO.U32 R20, UR4 &wr=0x1 ?trans1;
POPC R23, UR4 &wr=0x0 ?trans1;
ISETP.EQ.U32.AND P0, PT, R20, R15, PT &req={1} ?trans1;
IADD3 R21, PT, PT, R10, 0x1, RZ &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R16.64], R21 ?trans7;
@P0 ATOMG.E.ADD.STRONG.GPU PT, R19, desc[UR6][R18.64], R23 &req={0} &wr=0x3 ?trans1;
S2R R10, SR_LTMASK &wr=0x0 ?trans2;
LOP3.LUT R10, R10, UR4, RZ, 0xc0, !PT &req={0} ?WAIT6_END_GROUP;
POPC R10, R10 &wr=0x0 ?trans1;
SHFL.IDX PT, R15, R19, R20, 0x1f &req={3} &wr=0x0 ?trans2;
IADD3 R15, PT, PT, R15, R10, RZ &req={0} ?WAIT5_END_GROUP;
IMAD.WIDE R14, R15, 0x4, R4 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R14.64], R25 &rd=0x0 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
LDG.E R23, desc[UR6][R12.64+0x4] &req={1} &wr=0x3 ?trans2;
IMAD.WIDE R14, R23, 0x4, R6 &req={3,0} ?WAIT5_END_GROUP;
LDG.E R10, desc[UR6][R14.64] &wr=0x3 ?trans1;
IADD3 R11, PT, PT, R11, 0x4, RZ ?trans1;
BSSY.RECONVERGENT B0, 0xaf0 ?trans4;
ISETP.NE.AND P0, PT, R11, RZ, PT ?trans1;
ISETP.GT.AND P1, PT, R10, -0x1, PT &req={3} ?WAIT13_END_GROUP;
@P1 BRA 0xae0 ?trans5;
LDG.E R10, desc[UR6][R2.64] &wr=0x3 ?trans1;
VOTEU.ANY UR4, UPT, PT ?trans1;
LDC.64 R16, c[0x0][0x3b0] &wr=0x0 ?trans1;
S2R R13, SR_LANEID &wr=0x1 ?trans1;
FLO.U32 R18, UR4 &wr=0x1 ?trans1;
POPC R21, UR4 &wr=0x0 ?trans1;
ISETP.EQ.U32.AND P1, PT, R18, R13, PT &req={1} ?trans1;
IADD3 R19, PT, PT, R10, 0x1, RZ &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R14.64], R19 ?trans7;
@P1 ATOMG.E.ADD.STRONG.GPU PT, R17, desc[UR6][R16.64], R21 &req={0} &wr=0x3 ?trans1;
S2R R10, SR_LTMASK &wr=0x0 ?trans2;
LOP3.LUT R10, R10, UR4, RZ, 0xc0, !PT &req={0} ?WAIT6_END_GROUP;
POPC R10, R10 &wr=0x0 ?trans1;
SHFL.IDX PT, R13, R17, R18, 0x1f &req={3} &wr=0x0 ?trans2;
IADD3 R13, PT, PT, R13, R10, RZ &req={0} ?WAIT5_END_GROUP;
IMAD.WIDE R12, R13, 0x4, R4 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R12.64], R23 &rd=0x0 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
IADD3 R0, PT, PT, R0, 0x4, RZ ?trans1;
@P0 BRA 0x4c0 ?trans6;
EXIT ?trans5;
BRA 0xb20;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: BFS(int*, int*, int*, int*, int, int, int*, int*, int*)
_Z3BFSPiS_S_S_iiS_S_S_:
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b32 s2, s[0:1], 0x4c
s_waitcnt lgkmcnt(0)
s_load_b32 s3, s[10:11], 0x0
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_10
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[2:3], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
global_load_b32 v5, v[0:1], off
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s2, -1
v_mov_b32_e32 v8, s3
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[5:6]
v_add_co_u32 v1, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v4, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, s2, v5
global_load_b32 v0, v[1:2], off
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_3
global_load_b32 v8, v[1:2], off offset:4
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v0, v8
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_10
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x38
s_load_b128 s[8:11], s[0:1], 0x28
v_ashrrev_i32_e32 v1, 31, v0
v_mov_b32_e32 v9, 0
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_add_co_u32 v1, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
.LBB0_5:
global_load_b32 v5, v[1:2], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_load_b32 v10, v[6:7], off
s_waitcnt vmcnt(0)
v_cmpx_gt_i32_e32 0, v10
s_cbranch_execz .LBB0_9
global_load_b32 v11, v[3:4], off
s_mov_b32 s4, exec_lo
s_mov_b32 s5, exec_lo
v_mbcnt_lo_u32_b32 v10, s4, 0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v11, 1, v11
global_store_b32 v[6:7], v11, off
v_cmpx_eq_u32_e32 0, v10
s_cbranch_execz .LBB0_8
s_bcnt1_i32_b32 s4, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v6, s4
global_atomic_add_u32 v6, v9, v6, s[10:11] glc
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v6, s4, v10
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_u32 v6, vcc_lo, s8, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
global_store_b32 v[6:7], v5, off
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v0, 1, v0
v_add_co_u32 v1, s0, v1, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v2, s0, 0, v2, s0
v_cmp_ge_i32_e32 vcc_lo, v0, v8
s_or_b32 s1, vcc_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_5
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| BFS | 4,786 | 1,924 | stackv2-00000-of-00015 |
// Demangled: addMatrix(float const*, float const*, float*, int)
Function : _Z9addMatrixPKfS0_Pfi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR6, c[0x0][0x398] &wr=0x2 ?trans1;
S2R R5, SR_TID.Y &wr=0x3 ?trans6;
LDC R0, c[0x0][0x360] &wr=0x1 ?trans8;
S2UR UR5, SR_CTAID.Y &wr=0x3 ?trans8;
LDC R2, c[0x0][0x364] &wr=0x3 ?trans1;
IMAD R0, R0, UR4, R3 &req={1} ?WAIT2_END_GROUP;
IMAD R3, R2, UR5, R5 &req={3} ?WAIT4_END_GROUP;
IMAD R9, R3, UR6, R0 &req={2} ?trans1;
VIMNMX.S32 R2, R0, R3, !PT ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R2, UR6, PT ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD.WIDE R2, R9, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x4 ?trans1;
IMAD.WIDE R4, R9, 0x4, R4 &req={2} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR4][R4.64] &wr=0x4 ?trans1;
IMAD.WIDE R6, R9, 0x4, R6 &req={3} ?WAIT4_END_GROUP;
FADD R9, R2, R5 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x1a0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: addMatrix(float const*, float const*, float*, int)
_Z9addMatrixPKfS0_Pfi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v2, v0, v1
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| addMatrix | 705 | 750 | stackv2-00000-of-00015 |
// Demangled: WaveStepE(float*, float*, float*, float*, float*, float*, int, int, int, float, float*, float*)
Function : _Z9WaveStepEPfS_S_S_S_S_iiifS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R4, SR_TID.Z &wr=0x1 ?trans7;
LDC R0, c[0x0][0x360] &wr=0x2 ?trans1;
S2R R2, SR_TID.Y &wr=0x3 ?trans1;
S2R R5, SR_TID.X &wr=0x2 ?trans6;
LDC R3, c[0x0][0x364] &wr=0x3 ?trans8;
S2UR UR6, SR_CTAID.Z &wr=0x1 ?trans8;
LDC R7, c[0x0][0x368] &wr=0x1 ?trans8;
S2UR UR5, SR_CTAID.Y &wr=0x3 ?trans8;
S2UR UR4, SR_CTAID.X &wr=0x2 ?trans1;
IMAD R7, R7, UR6, R4 &req={1} ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R7, RZ, PT ?trans1;
IMAD R3, R3, UR5, R2 &req={3} ?WAIT5_END_GROUP;
ISETP.EQ.OR P0, PT, R3, RZ, !P0 ?trans1;
IMAD R0, R0, UR4, R5 &req={2} ?WAIT5_END_GROUP;
ISETP.LT.OR P0, PT, R0, 0x1, P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R4, c[0x0][0x3b0] &wr=0x0 ?trans1;
SHF.L.U32 R0, R0, 0x2, RZ ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans6;
LDC.64 R16, c[0x0][0x390] &wr=0x2 ?trans8;
LDC.64 R12, c[0x0][0x388] &wr=0x3 ?trans1;
IMAD R9, R3, R4, -R4 &req={0} ?WAIT7_END_GROUP;
LDC.64 R14, c[0x0][0x398] &wr=0x0 ?trans1;
IMAD R2, R3, R4.reuse, R0 ?trans2;
IMAD R7, R7, R4, RZ ?trans1;
IADD3 R8, PT, PT, R0, R9, RZ ?WAIT3_END_GROUP;
IMAD R0, R7.reuse, R5.reuse, R2 ?trans1;
LDC.64 R10, c[0x0][0x3c0] &wr=0x4 ?trans1;
IMAD R8, R7.reuse, R5, R8 ?trans1;
IADD3 R9, PT, PT, R7, -R4, RZ ?trans1;
IMAD.WIDE R6, R0, 0x4, R16 &req={2} ?WAIT4_END_GROUP;
IMAD.WIDE R16, R8, 0x4, R16 ?trans1;
LDG.E R20, desc[UR4][R6.64] &req={1} &wr=0x2 ?trans3;
IMAD R9, R9, R5, R2 ?trans1;
LDG.E R21, desc[UR4][R16.64] &wr=0x2 ?trans1;
IMAD.WIDE R2, R0, 0x4, R12 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE R12, R9, 0x4, R12 ?trans1;
LDG.E R23, desc[UR4][R2.64] &wr=0x3 ?trans3;
IMAD.WIDE R14, R0.reuse, 0x4, R14 &req={0} ?trans1;
LDG.E R25, desc[UR4][R12.64] &wr=0x5 ?trans3;
IMAD.WIDE R10, R0, 0x4, R10 &req={4} ?trans1;
LDG.E R18, desc[UR4][R14.64] &wr=0x4 ?trans4;
LDG.E R19, desc[UR4][R10.64] &wr=0x4 ?trans4;
LDG.E R22, desc[UR4][R14.64+0xc] &wr=0x4 ?trans1;
FADD R20, R20, -R21 &req={2} ?WAIT4_END_GROUP;
FADD R20, R20, -R23 &req={3} ?WAIT4_END_GROUP;
FADD R20, R20, R25 &req={5} ?WAIT4_END_GROUP;
FFMA R19, R19, R20, R18 &req={4} ?trans2;
LDG.E R18, desc[UR4][R14.64+0x4] &wr=0x2 ?trans4;
STG.E desc[UR4][R14.64], R19 &rd=0x0 ?trans4;
LDG.E R20, desc[UR4][R6.64+0x4] &wr=0x3 ?trans4;
LDG.E R23, desc[UR4][R16.64+0x4] &wr=0x3 ?trans4;
LDG.E R25, desc[UR4][R2.64+0x4] &wr=0x4 ?trans4;
LDG.E R27, desc[UR4][R12.64+0x4] &wr=0x5 ?trans4;
LDG.E R21, desc[UR4][R10.64+0x4] &wr=0x2 ?trans1;
FADD R20, R20, -R23 &req={3} ?WAIT4_END_GROUP;
FADD R20, R20, -R25 &req={4} ?WAIT4_END_GROUP;
FADD R20, R20, R27 &req={5} ?WAIT4_END_GROUP;
FFMA R21, R21, R20, R18 &req={2} ?trans2;
LDG.E R18, desc[UR4][R14.64+0x8] &wr=0x2 ?trans4;
STG.E desc[UR4][R14.64+0x4], R21 &rd=0x1 ?trans4;
LDG.E R20, desc[UR4][R6.64+0x8] &wr=0x3 ?trans4;
LDG.E R23, desc[UR4][R16.64+0x8] &wr=0x3 ?trans4;
LDG.E R25, desc[UR4][R2.64+0x8] &wr=0x4 ?trans4;
LDG.E R27, desc[UR4][R12.64+0x8] &wr=0x5 ?trans4;
LDG.E R19, desc[UR4][R10.64+0x8] &req={0} &wr=0x2 ?trans1;
FADD R20, R20, -R23 &req={3} ?WAIT4_END_GROUP;
FADD R20, R20, -R25 &req={4} ?WAIT4_END_GROUP;
FADD R20, R20, R27 &req={5} ?WAIT4_END_GROUP;
FFMA R23, R19, R20, R18 &req={2} ?trans2;
LDC.64 R18, c[0x0][0x380] &wr=0x0 ?trans3;
STG.E desc[UR4][R14.64+0x8], R23 &rd=0x2 ?trans4;
LDG.E R21, desc[UR4][R16.64+0xc] &req={1} &rd=0x0 &wr=0x3 ?trans4;
LDG.E R20, desc[UR4][R6.64+0xc] &wr=0x3 ?trans4;
LDG.E R27, desc[UR4][R2.64+0xc] &wr=0x4 ?trans4;
LDG.E R13, desc[UR4][R12.64+0xc] &wr=0x5 ?trans4;
LDG.E R25, desc[UR4][R10.64+0xc] &wr=0x2 ?trans1;
IMAD.WIDE R16, R0, 0x4, R18 &req={0} ?WAIT4_END_GROUP;
FADD R24, R20, -R21 &req={3} ?trans2;
LDC.64 R20, c[0x0][0x3a0] &wr=0x0 ?trans2;
FADD R24, R24, -R27 &req={4} ?WAIT4_END_GROUP;
FADD R24, R24, R13 &req={5} ?WAIT4_END_GROUP;
FFMA R25, R25, R24, R22 &req={2} ?trans1;
IMAD.WIDE R22, R9, 0x4, R18 ?WAIT4_END_GROUP;
STG.E desc[UR4][R14.64+0xc], R25 &rd=0x1 ?trans4;
LDG.E R13, desc[UR4][R16.64] &wr=0x2 ?trans4;
LDG.E R24, desc[UR4][R22.64] &wr=0x2 ?trans1;
IMAD.WIDE R20, R0, 0x4, R20 &req={0} ?WAIT3_END_GROUP;
LDG.E R26, desc[UR4][R6.64] &wr=0x3 ?trans4;
LDG.E R28, desc[UR4][R6.64+-0x4] &wr=0x4 ?trans4;
LDG.E R12, desc[UR4][R10.64] &wr=0x5 ?trans4;
LDG.E R9, desc[UR4][R20.64] &wr=0x5 ?trans1;
FADD R13, R13, -R24 &req={2} ?WAIT4_END_GROUP;
FADD R13, R13, -R26 &req={3} ?WAIT4_END_GROUP;
FADD R13, R13, R28 &req={4} ?WAIT4_END_GROUP;
FFMA R9, R12, R13, R9 &req={5} ?trans2;
LDG.E R12, desc[UR4][R20.64+0x4] &wr=0x2 ?trans4;
STG.E desc[UR4][R20.64], R9 &rd=0x0 ?trans4;
LDG.E R14, desc[UR4][R16.64+0x4] &req={1} &wr=0x3 ?trans4;
LDG.E R15, desc[UR4][R22.64+0x4] &wr=0x3 ?trans4;
LDG.E R25, desc[UR4][R6.64+0x4] &wr=0x4 ?trans4;
LDG.E R27, desc[UR4][R6.64] &wr=0x5 ?trans4;
LDG.E R13, desc[UR4][R10.64+0x4] &wr=0x2 ?trans4;
LDG.E R9, desc[UR4][R20.64+0x8] &req={0} &wr=0x2 ?trans1;
FADD R14, R14, -R15 &req={3} ?WAIT4_END_GROUP;
FADD R14, R14, -R25 &req={4} ?WAIT4_END_GROUP;
FADD R14, R14, R27 &req={5} ?WAIT4_END_GROUP;
FFMA R13, R13, R14, R12 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R20.64+0x4], R13 &rd=0x0 ?trans4;
LDG.E R14, desc[UR4][R16.64+0x8] &wr=0x2 ?trans4;
LDG.E R15, desc[UR4][R22.64+0x8] &wr=0x2 ?trans4;
LDG.E R25, desc[UR4][R6.64+0x8] &wr=0x3 ?trans4;
LDG.E R27, desc[UR4][R6.64+0x4] &wr=0x4 ?trans4;
LDG.E R12, desc[UR4][R10.64+0x8] &wr=0x5 ?trans1;
FADD R14, R14, -R15 &req={2} ?WAIT4_END_GROUP;
FADD R14, R14, -R25 &req={3} ?WAIT4_END_GROUP;
FADD R14, R14, R27 &req={4} ?WAIT4_END_GROUP;
FFMA R9, R12, R14, R9 &req={5} ?trans2;
LDG.E R14, desc[UR4][R20.64+0xc] &wr=0x2 ?trans4;
STG.E desc[UR4][R20.64+0x8], R9 &rd=0x1 ?trans4;
LDG.E R13, desc[UR4][R22.64+0xc] &req={0} &wr=0x3 ?trans4;
LDG.E R12, desc[UR4][R16.64+0xc] &wr=0x3 ?trans4;
LDG.E R25, desc[UR4][R6.64+0xc] &wr=0x4 ?trans4;
LDG.E R27, desc[UR4][R6.64+0x8] &wr=0x5 ?trans4;
LDG.E R15, desc[UR4][R10.64+0xc] &wr=0x2 ?trans1;
IMAD.WIDE R8, R8, 0x4, R18 &req={1} ?WAIT4_END_GROUP;
FADD R24, R12, -R13 &req={3} ?trans2;
LDC.64 R12, c[0x0][0x3a8] &wr=0x0 ?trans2;
FADD R24, R24, -R25 &req={4} ?WAIT4_END_GROUP;
FADD R24, R24, R27 &req={5} ?WAIT4_END_GROUP;
FFMA R15, R15, R24, R14 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R20.64+0xc], R15 &rd=0x1 ?trans4;
LDG.E R22, desc[UR4][R2.64] &wr=0x2 ?trans4;
LDG.E R23, desc[UR4][R2.64+-0x4] &wr=0x2 ?trans1;
IMAD.WIDE R6, R0, 0x4, R12 &req={0} ?WAIT3_END_GROUP;
LDG.E R25, desc[UR4][R16.64] &wr=0x3 ?trans4;
LDG.E R27, desc[UR4][R8.64] &wr=0x4 ?trans4;
LDG.E R19, desc[UR4][R10.64] &wr=0x5 ?trans4;
LDG.E R14, desc[UR4][R6.64] &wr=0x5 ?trans1;
FADD R22, R22, -R23 &req={2} ?WAIT4_END_GROUP;
FADD R22, R22, -R25 &req={3} ?WAIT4_END_GROUP;
FADD R22, R22, R27 &req={4} ?WAIT4_END_GROUP;
FFMA R19, R19, R22, R14 &req={5} ?trans2;
LDG.E R14, desc[UR4][R6.64+0x4] &wr=0x2 ?trans4;
STG.E desc[UR4][R6.64], R19 &rd=0x0 ?trans4;
LDG.E R18, desc[UR4][R2.64+0x4] &wr=0x3 ?trans4;
LDG.E R21, desc[UR4][R2.64] &req={1} &wr=0x3 ?trans4;
LDG.E R23, desc[UR4][R16.64+0x4] &wr=0x4 ?trans4;
LDG.E R25, desc[UR4][R8.64+0x4] &wr=0x5 ?trans4;
LDG.E R15, desc[UR4][R10.64+0x4] &wr=0x2 ?trans1;
FADD R18, R18, -R21 &req={3} ?WAIT4_END_GROUP;
FADD R18, R18, -R23 &req={4} ?WAIT4_END_GROUP;
FADD R18, R18, R25 &req={5} ?WAIT4_END_GROUP;
FFMA R15, R15, R18, R14 &req={2} ?trans2;
LDG.E R14, desc[UR4][R6.64+0x8] &wr=0x2 ?trans4;
STG.E desc[UR4][R6.64+0x4], R15 &rd=0x1 ?trans4;
LDG.E R18, desc[UR4][R2.64+0x8] &wr=0x3 ?trans4;
LDG.E R21, desc[UR4][R2.64+0x4] &wr=0x3 ?trans4;
LDG.E R23, desc[UR4][R16.64+0x8] &wr=0x4 ?trans4;
LDG.E R25, desc[UR4][R8.64+0x8] &wr=0x5 ?trans4;
LDG.E R19, desc[UR4][R10.64+0x8] &req={0} &wr=0x2 ?trans1;
FADD R18, R18, -R21 &req={3} ?WAIT4_END_GROUP;
FADD R18, R18, -R23 &req={4} ?WAIT4_END_GROUP;
FADD R18, R18, R25 &req={5} ?WAIT4_END_GROUP;
FFMA R19, R19, R18, R14 &req={2} ?trans2;
LDG.E R18, desc[UR4][R6.64+0xc] &wr=0x2 ?trans1;
LDC.64 R14, c[0x0][0x3b8] &req={1} &wr=0x0 ?trans3;
STG.E desc[UR4][R6.64+0x8], R19 ?trans4;
LDG.E R20, desc[UR4][R2.64+0xc] &wr=0x3 ?trans4;
LDG.E R23, desc[UR4][R2.64+0x8] &rd=0x1 &wr=0x3 ?trans4;
LDG.E R17, desc[UR4][R16.64+0xc] &wr=0x4 ?trans4;
LDG.E R8, desc[UR4][R8.64+0xc] &wr=0x5 ?trans4;
LDG.E R21, desc[UR4][R10.64+0xc] &wr=0x2 ?trans1;
LEA.HI R22, R5, R5, RZ, 0x1 ?WAIT2_END_GROUP;
LEA.HI R24, R14, R14, RZ, 0x1 &req={0} ?trans2;
LEA.HI R14, R4, R4, RZ, 0x1 ?trans2;
SHF.R.S32.HI R22, RZ, 0x1, R22 ?trans2;
SHF.R.S32.HI R24, RZ, 0x1, R24 ?trans2;
SHF.R.S32.HI R3, RZ, 0x1, R14 &req={1} ?WAIT3_END_GROUP;
IMAD R22, R24, R5, R22 ?WAIT4_END_GROUP;
IMAD R3, R22, R4, R3 ?WAIT4_END_GROUP;
IMAD.WIDE R12, R3, 0x4, R12 ?trans2;
LDC.64 R2, c[0x0][0x3c8] &wr=0x0 ?trans2;
FADD R20, R20, -R23 &req={3} ?WAIT4_END_GROUP;
FADD R17, R20, -R17 &req={4} ?WAIT4_END_GROUP;
FADD R8, R17, R8 &req={5} ?WAIT4_END_GROUP;
FFMA R21, R21, R8, R18 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64+0xc], R21 ?trans4;
STG.E desc[UR4][R12.64], R15 ?trans4;
LDG.E R5, desc[UR4][R6.64] &wr=0x2 ?trans1;
IMAD.WIDE R2, R0, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R5 &req={2} ?trans4;
LDG.E R9, desc[UR4][R6.64+0x4] &wr=0x2 ?trans4;
STG.E desc[UR4][R2.64+0x4], R9 &req={2} ?trans4;
LDG.E R11, desc[UR4][R6.64+0x8] &wr=0x2 ?trans4;
STG.E desc[UR4][R2.64+0x8], R11 &req={2} ?trans4;
LDG.E R17, desc[UR4][R6.64+0xc] &wr=0x2 ?trans4;
STG.E desc[UR4][R2.64+0xc], R17 &req={2} ?trans1;
EXIT ?trans5;
BRA 0xc80;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: WaveStepE(float*, float*, float*, float*, float*, float*, int, int, int, float, float*, float*)
_Z9WaveStepEPfS_S_S_S_S_iiifS_S_:
s_load_b64 s[2:3], s[0:1], 0x5c
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v5, v0, 10, 10
v_bfe_u32 v6, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
s_and_b32 s3, s3, 0xffff
v_mad_u64_u32 v[0:1], null, s13, s2, v[2:3]
v_mad_u64_u32 v[3:4], null, s14, s4, v[5:6]
v_mad_u64_u32 v[1:2], null, s15, s3, v[6:7]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min3_i32 v2, v0, v3, v1
v_cmpx_lt_i32_e32 0, v2
s_cbranch_execz .LBB1_2
s_load_b256 s[4:11], s[0:1], 0x20
v_lshlrev_b32_e32 v20, 2, v0
s_load_b256 s[12:19], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v4, v3, s8
s_mul_i32 s2, s9, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v21, s2, v1
v_add_nc_u32_e32 v0, v4, v20
v_subrev_nc_u32_e32 v1, s8, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v22, s2, v21
s_load_b128 s[0:3], s[0:1], 0x40
v_add_nc_u32_e32 v5, v21, v0
s_delay_alu instid0(VALU_DEP_3)
v_add3_u32 v7, v21, v1, v20
v_ashrrev_i32_e32 v23, 31, v21
v_add_nc_u32_e32 v2, v22, v0
v_ashrrev_i32_e32 v27, 31, v22
v_ashrrev_i32_e32 v6, 31, v5
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[8:9], 2, v[7:8]
v_lshlrev_b64 v[10:11], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s18, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s19, v1, vcc_lo
v_add_co_u32 v12, vcc_lo, s16, v0
v_add_co_ci_u32_e32 v13, vcc_lo, s17, v1, vcc_lo
v_add_co_u32 v14, vcc_lo, s16, v8
v_add_co_ci_u32_e32 v15, vcc_lo, s17, v9, vcc_lo
v_add_co_u32 v16, vcc_lo, s14, v0
v_add_co_ci_u32_e32 v17, vcc_lo, s15, v1, vcc_lo
s_clause 0x1
global_load_b32 v6, v[12:13], off
global_load_b32 v24, v[14:15], off
v_add_co_u32 v14, vcc_lo, s14, v10
global_load_b32 v26, v[16:17], off
v_add_co_ci_u32_e32 v15, vcc_lo, s15, v11, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v18, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v19, vcc_lo, s1, v1, vcc_lo
global_load_b32 v28, v[14:15], off
global_load_b32 v32, v[2:3], off
global_load_b32 v30, v[18:19], off
v_ashrrev_i32_e32 v14, 31, v20
v_ashrrev_i32_e32 v15, 31, v4
v_add_co_u32 v4, vcc_lo, v20, v4
v_add_nc_u32_e32 v20, 1, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v25, vcc_lo, v14, v15, vcc_lo
v_add_co_u32 v14, vcc_lo, v21, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v21, 31, v20
v_add_co_ci_u32_e32 v15, vcc_lo, v23, v25, vcc_lo
v_add_co_u32 v22, vcc_lo, v22, v4
v_add_co_ci_u32_e32 v23, vcc_lo, v27, v25, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[14:15], 2, v[14:15]
v_lshlrev_b64 v[20:21], 2, v[20:21]
v_lshlrev_b64 v[22:23], 2, v[22:23]
s_waitcnt vmcnt(4)
v_sub_f32_e32 v4, v6, v24
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_co_u32 v24, vcc_lo, s18, v14
v_add_co_ci_u32_e32 v25, vcc_lo, s19, v15, vcc_lo
s_waitcnt vmcnt(3)
v_sub_f32_e32 v4, v4, v26
v_add_co_u32 v26, vcc_lo, s16, v14
v_add_co_ci_u32_e32 v27, vcc_lo, s17, v15, vcc_lo
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_add_f32_e32 v4, v4, v28
v_add_co_u32 v28, vcc_lo, s16, v20
v_add_co_ci_u32_e32 v29, vcc_lo, s17, v21, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v32, v30, v4
v_add_co_u32 v30, vcc_lo, s14, v14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v15, vcc_lo
global_store_b32 v[2:3], v32, off
s_clause 0x1
global_load_b32 v6, v[26:27], off offset:4
global_load_b32 v34, v[28:29], off
v_add_co_u32 v28, vcc_lo, s14, v22
global_load_b32 v35, v[30:31], off offset:4
v_add_co_ci_u32_e32 v29, vcc_lo, s15, v23, vcc_lo
v_add_co_u32 v32, vcc_lo, s0, v14
v_add_co_ci_u32_e32 v33, vcc_lo, s1, v15, vcc_lo
global_load_b32 v36, v[28:29], off offset:4
global_load_b96 v[2:4], v[24:25], off offset:4
global_load_b32 v37, v[32:33], off offset:4
s_lshr_b32 s1, s10, 31
s_lshr_b32 s0, s9, 31
s_add_i32 s1, s10, s1
s_add_i32 s0, s9, s0
s_ashr_i32 s1, s1, 1
s_ashr_i32 s0, s0, 1
s_mul_i32 s1, s1, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s1, s0
s_mul_i32 s0, s0, s8
s_waitcnt vmcnt(4)
v_sub_f32_e32 v6, v6, v34
v_add_nc_u32_e32 v34, 2, v7
s_waitcnt vmcnt(3)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v6, v6, v35
v_ashrrev_i32_e32 v35, 31, v34
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v6, v6, v36
v_lshlrev_b64 v[34:35], 2, v[34:35]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v2, v37, v6, v2
v_add_co_u32 v36, vcc_lo, s16, v34
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v37, vcc_lo, s17, v35, vcc_lo
global_store_b32 v[24:25], v2, off offset:4
s_clause 0x1
global_load_b32 v2, v[26:27], off offset:8
global_load_b32 v6, v[36:37], off
s_clause 0x1
global_load_b32 v36, v[30:31], off offset:8
global_load_b32 v37, v[28:29], off offset:8
global_load_b32 v38, v[32:33], off offset:8
s_waitcnt vmcnt(3)
v_sub_f32_e32 v2, v2, v6
v_add_nc_u32_e32 v6, 3, v7
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v2, v2, v36
v_ashrrev_i32_e32 v7, 31, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v2, v2, v37
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v36, v38, v2, v3
v_add_co_u32 v2, vcc_lo, s16, v6
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s17, v7, vcc_lo
global_store_b32 v[24:25], v36, off offset:8
s_clause 0x1
global_load_b32 v36, v[26:27], off offset:12
global_load_b32 v2, v[2:3], off
s_clause 0x1
global_load_b32 v3, v[30:31], off offset:12
global_load_b32 v28, v[28:29], off offset:12
global_load_b32 v37, v[32:33], off offset:12
s_waitcnt vmcnt(3)
v_dual_sub_f32 v29, v36, v2 :: v_dual_add_nc_u32 v2, -1, v5
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v5, v29, v3
v_ashrrev_i32_e32 v3, 31, v2
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_add_f32_e32 v5, v5, v28
v_add_co_u32 v28, vcc_lo, s12, v0
v_add_co_ci_u32_e32 v29, vcc_lo, s13, v1, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v4, v37, v5
v_add_co_u32 v10, vcc_lo, s12, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s13, v11, vcc_lo
v_lshlrev_b64 v[36:37], 2, v[2:3]
global_store_b32 v[24:25], v4, off offset:12
s_clause 0x1
global_load_b32 v24, v[28:29], off
global_load_b32 v10, v[10:11], off
global_load_b32 v11, v[12:13], off
v_add_co_u32 v2, vcc_lo, s16, v36
v_add_co_ci_u32_e32 v3, vcc_lo, s17, v37, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
global_load_b32 v25, v[18:19], off
s_waitcnt vmcnt(4)
v_sub_f32_e32 v10, v24, v10
s_waitcnt vmcnt(3)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_f32_e32 v10, v10, v11
s_waitcnt vmcnt(2)
v_add_f32_e32 v2, v10, v2
v_add_co_u32 v10, vcc_lo, s12, v14
v_add_co_ci_u32_e32 v11, vcc_lo, s13, v15, vcc_lo
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_3)
v_fmac_f32_e32 v3, v25, v2
v_add_co_u32 v22, vcc_lo, s12, v22
v_add_co_ci_u32_e32 v23, vcc_lo, s13, v23, vcc_lo
global_store_b32 v[4:5], v3, off
s_clause 0x1
global_load_b32 v5, v[10:11], off offset:4
global_load_b32 v38, v[22:23], off offset:4
global_load_b32 v39, v[26:27], off offset:4
v_add_co_u32 v24, vcc_lo, s4, v14
v_add_co_ci_u32_e32 v25, vcc_lo, s5, v15, vcc_lo
global_load_b32 v12, v[12:13], off
global_load_b96 v[2:4], v[24:25], off offset:4
global_load_b32 v13, v[32:33], off offset:4
s_lshr_b32 s4, s8, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s4, s8, s4
s_ashr_i32 s1, s4, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s0, s1
s_ashr_i32 s1, s0, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[0:1], 2
s_add_u32 s0, s6, s0
s_addc_u32 s1, s7, s1
s_waitcnt vmcnt(4)
v_sub_f32_e32 v5, v5, v38
s_waitcnt vmcnt(3)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_f32_e32 v5, v5, v39
s_waitcnt vmcnt(2)
v_add_f32_e32 v5, v5, v12
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fma_f32 v2, v13, v5, v2
global_store_b32 v[24:25], v2, off offset:4
s_clause 0x1
global_load_b32 v2, v[10:11], off offset:8
global_load_b32 v5, v[22:23], off offset:8
global_load_b64 v[12:13], v[26:27], off offset:4
global_load_b32 v38, v[32:33], off offset:8
s_waitcnt vmcnt(2)
v_sub_f32_e32 v2, v2, v5
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v2, v2, v13
v_add_f32_e32 v2, v2, v12
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fma_f32 v2, v38, v2, v3
global_store_b32 v[24:25], v2, off offset:8
s_clause 0x1
global_load_b32 v5, v[10:11], off offset:12
global_load_b32 v12, v[22:23], off offset:12
global_load_b64 v[2:3], v[26:27], off offset:8
global_load_b32 v13, v[32:33], off offset:12
s_waitcnt vmcnt(2)
v_sub_f32_e32 v5, v5, v12
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v3, v5, v3
v_add_f32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v4, v13, v2
v_add_co_u32 v2, vcc_lo, s14, v36
v_add_co_ci_u32_e32 v3, vcc_lo, s15, v37, vcc_lo
global_store_b32 v[24:25], v4, off offset:12
s_clause 0x1
global_load_b32 v4, v[16:17], off
global_load_b32 v5, v[2:3], off
v_add_co_u32 v2, vcc_lo, s12, v8
v_add_co_ci_u32_e32 v3, vcc_lo, s13, v9, vcc_lo
global_load_b32 v12, v[28:29], off
v_add_co_u32 v8, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[8:9], off
global_load_b32 v13, v[18:19], off
s_waitcnt vmcnt(4)
v_sub_f32_e32 v4, v4, v5
s_waitcnt vmcnt(3)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_f32_e32 v4, v4, v12
s_waitcnt vmcnt(2)
v_add_f32_e32 v2, v4, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v3, v13, v2
v_add_co_u32 v2, vcc_lo, s12, v20
global_store_b32 v[8:9], v3, off
s_clause 0x1
global_load_b32 v5, v[30:31], off offset:4
global_load_b32 v16, v[16:17], off
v_add_co_ci_u32_e32 v3, vcc_lo, s13, v21, vcc_lo
global_load_b32 v17, v[10:11], off offset:4
v_add_co_u32 v12, vcc_lo, s6, v14
v_add_co_ci_u32_e32 v13, vcc_lo, s7, v15, vcc_lo
global_load_b32 v18, v[2:3], off
global_load_b96 v[2:4], v[12:13], off offset:4
global_load_b32 v19, v[32:33], off offset:4
s_waitcnt vmcnt(4)
v_sub_f32_e32 v5, v5, v16
s_waitcnt vmcnt(3)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_f32_e32 v5, v5, v17
s_waitcnt vmcnt(2)
v_add_f32_e32 v5, v5, v18
v_add_co_u32 v18, vcc_lo, s12, v34
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2)
v_fma_f32 v2, v19, v5, v2
v_add_co_ci_u32_e32 v19, vcc_lo, s13, v35, vcc_lo
global_store_b32 v[12:13], v2, off offset:4
global_load_b64 v[16:17], v[30:31], off offset:4
s_clause 0x1
global_load_b32 v2, v[10:11], off offset:8
global_load_b32 v5, v[18:19], off
global_load_b32 v18, v[32:33], off offset:8
s_waitcnt vmcnt(3)
v_sub_f32_e32 v16, v17, v16
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_f32_e32 v2, v16, v2
s_waitcnt vmcnt(1)
v_add_f32_e32 v2, v2, v5
v_add_co_u32 v5, vcc_lo, s12, v6
v_add_co_ci_u32_e32 v6, vcc_lo, s13, v7, vcc_lo
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_3)
v_fma_f32 v2, v18, v2, v3
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[12:13], v2, off offset:8
global_load_b64 v[2:3], v[30:31], off offset:8
s_clause 0x1
global_load_b32 v7, v[10:11], off offset:12
global_load_b32 v5, v[5:6], off
global_load_b32 v6, v[32:33], off offset:12
s_waitcnt vmcnt(3)
v_dual_sub_f32 v2, v3, v2 :: v_dual_mov_b32 v3, 0
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_f32_e32 v2, v2, v7
s_waitcnt vmcnt(1)
v_dual_add_f32 v2, v2, v5 :: v_dual_mov_b32 v5, s11
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v4, v6, v2
s_clause 0x1
global_store_b32 v[12:13], v4, off offset:12
global_store_b32 v3, v5, s[0:1]
global_load_b32 v2, v[8:9], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
global_load_b32 v2, v[12:13], off offset:4
v_add_co_u32 v0, vcc_lo, s2, v14
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v15, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off offset:4
global_load_b32 v2, v[12:13], off offset:8
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off offset:8
global_load_b32 v2, v[12:13], off offset:12
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off offset:12
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| WaveStepE | 5,682 | 7,350 | stackv2-00000-of-00015 |
// Demangled: WaveStepH(float*, float*, float*, float*, float*, float*, int, int, int, float, float, float*)
Function : _Z9WaveStepHPfS_S_S_S_S_iiiffS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR7, c[0x0][0x3b8] &wr=0x2 ?trans1;
S2R R5, SR_TID.Y &wr=0x3 ?trans1;
S2R R6, SR_TID.Z &wr=0x4 ?trans5;
LDC R7, c[0x0][0x360] &wr=0x1 ?trans8;
S2UR UR5, SR_CTAID.Y &wr=0x3 ?trans8;
LDC R4, c[0x0][0x364] &wr=0x3 ?trans8;
LDC.64 R2, c[0x0][0x3b0] &wr=0x5 ?trans1;
IMAD R7, R7, UR4, R0 &req={1} ?WAIT7_END_GROUP;
S2UR UR6, SR_CTAID.Z &wr=0x4 ?trans8;
LDC R11, c[0x0][0x368] &wr=0x4 ?trans1;
IMAD R0, R4, UR5, R5 &req={3} ?trans1;
ISETP.GE.AND P0, PT, R7, R2, PT &req={5} ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R0, R3, P0 ?trans1;
IMAD R11, R11, UR6, R6 &req={4} ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R11, UR7, P0 &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R4, c[0x0][0x3a0] &wr=0x0 ?trans1;
SHF.L.U32 R7, R7, 0x2, RZ ?trans1;
IMAD R11, R11, R2.reuse, RZ ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans3;
IMAD R0, R0, R2.reuse, R7 ?trans1;
IADD3 R6, PT, PT, R11.reuse, R2, RZ ?trans1;
LDC.64 R8, c[0x0][0x3a8] &wr=0x2 ?trans1;
LDCU UR6, c[0x0][0x3bc] &wr=0x3 ?trans1;
IMAD R7, R11, R3, R0 ?WAIT2_END_GROUP;
IMAD R3, R6, R3, R0 ?WAIT3_END_GROUP;
IADD3 R15, PT, PT, R7, R2, RZ ?trans1;
LDC.64 R12, c[0x0][0x380] &wr=0x4 ?trans1;
IMAD.WIDE R10, R3, 0x4, R4 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE R4, R7, 0x4, R4 ?trans1;
LDG.E R6, desc[UR4][R10.64] &req={1} &wr=0x5 ?trans3;
IMAD.WIDE R14, R15, 0x4, R8.reuse &req={2} ?trans1;
LDG.E R17, desc[UR4][R4.64] &wr=0x5 ?trans3;
IMAD.WIDE R8, R7.reuse, 0x4, R8 ?trans1;
LDG.E R19, desc[UR4][R14.64] &wr=0x2 ?trans3;
IMAD.WIDE R12, R7, 0x4, R12 &req={4} ?trans1;
LDG.E R21, desc[UR4][R8.64] &wr=0x4 ?trans4;
LDG.E R0, desc[UR4][R12.64] &wr=0x3 ?trans1;
FADD R6, R6, -R17 &req={5} ?WAIT4_END_GROUP;
FADD R6, R6, -R19 &req={2} ?WAIT4_END_GROUP;
FADD R21, R6, R21 &req={4} ?WAIT4_END_GROUP;
FFMA R21, R21, UR6, R0 &req={3} ?trans2;
LDG.E R0, desc[UR4][R12.64+0x4] &wr=0x2 ?trans4;
STG.E desc[UR4][R12.64], R21 &rd=0x0 ?trans4;
LDG.E R6, desc[UR4][R10.64+0x4] &wr=0x3 ?trans4;
LDG.E R17, desc[UR4][R4.64+0x4] &wr=0x3 ?trans4;
LDG.E R19, desc[UR4][R14.64+0x4] &wr=0x4 ?trans4;
LDG.E R23, desc[UR4][R8.64+0x4] &wr=0x5 ?trans1;
FADD R6, R6, -R17 &req={3} ?WAIT4_END_GROUP;
FADD R6, R6, -R19 &req={4} ?WAIT4_END_GROUP;
FADD R23, R6, R23 &req={5} ?WAIT4_END_GROUP;
FFMA R23, R23, UR6, R0 &req={2} ?trans2;
LDG.E R0, desc[UR4][R12.64+0x8] &wr=0x2 ?trans4;
STG.E desc[UR4][R12.64+0x4], R23 &rd=0x1 ?trans4;
LDG.E R6, desc[UR4][R10.64+0x8] &wr=0x3 ?trans4;
LDG.E R17, desc[UR4][R4.64+0x8] &wr=0x3 ?trans4;
LDG.E R19, desc[UR4][R14.64+0x8] &wr=0x4 ?trans4;
LDG.E R21, desc[UR4][R8.64+0x8] &req={0} &wr=0x5 ?trans1;
FADD R6, R6, -R17 &req={3} ?WAIT2_END_GROUP;
LDC.64 R16, c[0x0][0x398] &wr=0x0 ?trans2;
FADD R6, R6, -R19 &req={4} ?WAIT4_END_GROUP;
FADD R21, R6, R21 &req={5} ?WAIT4_END_GROUP;
FFMA R21, R21, UR6, R0 &req={2} ?trans2;
LDG.E R0, desc[UR4][R12.64+0xc] &wr=0x2 ?trans4;
STG.E desc[UR4][R12.64+0x8], R21 ?trans4;
LDG.E R6, desc[UR4][R10.64+0xc] &rd=0x0 &wr=0x3 ?trans4;
LDG.E R19, desc[UR4][R4.64+0xc] &wr=0x3 ?trans4;
LDG.E R23, desc[UR4][R14.64+0xc] &req={1} &wr=0x4 ?trans4;
LDG.E R25, desc[UR4][R8.64+0xc] &wr=0x5 ?trans1;
IMAD.WIDE R10, R3, 0x4, R16 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE R16, R7, 0x4, R16 ?WAIT4_END_GROUP;
FADD R6, R6, -R19 &req={3} ?trans2;
LDC.64 R18, c[0x0][0x388] &wr=0x0 ?trans2;
FADD R6, R6, -R23 &req={4} ?WAIT4_END_GROUP;
FADD R25, R6, R25 &req={5} ?WAIT4_END_GROUP;
FFMA R25, R25, UR6, R0 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R12.64+0xc], R25 &rd=0x1 ?trans4;
LDG.E R3, desc[UR4][R8.64+0x4] &wr=0x2 ?trans4;
LDG.E R6, desc[UR4][R8.64] &wr=0x2 ?trans1;
IMAD.WIDE R18, R7, 0x4, R18 &req={0} ?WAIT3_END_GROUP;
LDG.E R14, desc[UR4][R10.64] &wr=0x3 ?trans4;
LDG.E R20, desc[UR4][R16.64] &wr=0x4 ?trans4;
LDG.E R0, desc[UR4][R18.64] &wr=0x5 ?trans1;
FADD R3, R3, -R6 &req={2} ?WAIT4_END_GROUP;
FADD R3, R3, -R14 &req={3} ?WAIT4_END_GROUP;
FADD R3, R3, R20 &req={4} ?WAIT4_END_GROUP;
FFMA R3, R3, UR6, R0 &req={5} ?trans2;
LDG.E R0, desc[UR4][R18.64+0x4] &wr=0x2 ?trans4;
STG.E desc[UR4][R18.64], R3 &rd=0x0 ?trans4;
LDG.E R6, desc[UR4][R8.64+0x8] &wr=0x3 ?trans4;
LDG.E R13, desc[UR4][R8.64+0x4] &req={1} &wr=0x3 ?trans4;
LDG.E R15, desc[UR4][R10.64+0x4] &wr=0x4 ?trans4;
LDG.E R21, desc[UR4][R16.64+0x4] &wr=0x5 ?trans1;
FADD R6, R6, -R13 &req={3} ?WAIT4_END_GROUP;
FADD R6, R6, -R15 &req={4} ?WAIT4_END_GROUP;
FADD R21, R6, R21 &req={5} ?WAIT4_END_GROUP;
FFMA R21, R21, UR6, R0 &req={2} ?trans2;
LDG.E R0, desc[UR4][R18.64+0x8] &wr=0x2 ?trans4;
STG.E desc[UR4][R18.64+0x4], R21 &rd=0x1 ?trans4;
LDG.E R3, desc[UR4][R8.64+0xc] &req={0} &wr=0x3 ?trans4;
LDG.E R6, desc[UR4][R8.64+0x8] &wr=0x3 ?trans4;
LDG.E R12, desc[UR4][R10.64+0x8] &wr=0x4 ?trans4;
LDG.E R14, desc[UR4][R16.64+0x8] &wr=0x5 ?trans1;
FADD R3, R3, -R6 &req={3} ?WAIT4_END_GROUP;
FADD R3, R3, -R12 &req={4} ?WAIT4_END_GROUP;
FADD R3, R3, R14 &req={5} ?WAIT4_END_GROUP;
FFMA R3, R3, UR6, R0 &req={2} ?trans2;
LDG.E R0, desc[UR4][R18.64+0xc] &wr=0x2 ?trans4;
STG.E desc[UR4][R18.64+0x8], R3 &rd=0x0 ?trans4;
LDG.E R6, desc[UR4][R8.64+0x10] &wr=0x3 ?trans4;
LDG.E R13, desc[UR4][R8.64+0xc] &wr=0x3 ?trans4;
LDG.E R15, desc[UR4][R10.64+0xc] &wr=0x4 ?trans4;
LDG.E R21, desc[UR4][R16.64+0xc] &req={1} &wr=0x5 ?trans1;
IMAD.WIDE R2, R2, 0x4, R16 &req={0} ?WAIT4_END_GROUP;
FADD R6, R6, -R13 &req={3} ?trans2;
LDC.64 R12, c[0x0][0x390] &wr=0x0 ?trans2;
FADD R6, R6, -R15 &req={4} ?WAIT4_END_GROUP;
FADD R21, R6, R21 &req={5} ?WAIT4_END_GROUP;
FFMA R21, R21, UR6, R0 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R18.64+0xc], R21 ?trans4;
LDG.E R8, desc[UR4][R2.64] &wr=0x2 ?trans4;
LDG.E R9, desc[UR4][R16.64] &wr=0x2 ?trans1;
IMAD.WIDE R6, R7, 0x4, R12 &req={0} ?WAIT3_END_GROUP;
LDG.E R11, desc[UR4][R4.64+0x4] &wr=0x3 ?trans4;
LDG.E R13, desc[UR4][R4.64] &wr=0x4 ?trans4;
LDG.E R0, desc[UR4][R6.64] &wr=0x5 ?trans1;
FADD R8, R8, -R9 &req={2} ?WAIT4_END_GROUP;
FADD R8, R8, -R11 &req={3} ?WAIT4_END_GROUP;
FADD R13, R8, R13 &req={4} ?WAIT4_END_GROUP;
FFMA R13, R13, UR6, R0 &req={5} ?trans2;
LDG.E R0, desc[UR4][R6.64+0x4] &wr=0x2 ?trans4;
STG.E desc[UR4][R6.64], R13 &rd=0x0 ?trans4;
LDG.E R8, desc[UR4][R2.64+0x4] &wr=0x3 ?trans4;
LDG.E R9, desc[UR4][R16.64+0x4] &wr=0x3 ?trans4;
LDG.E R11, desc[UR4][R4.64+0x8] &wr=0x4 ?trans4;
LDG.E R15, desc[UR4][R4.64+0x4] &wr=0x5 ?trans1;
FADD R8, R8, -R9 &req={3} ?WAIT4_END_GROUP;
FADD R8, R8, -R11 &req={4} ?WAIT4_END_GROUP;
FADD R15, R8, R15 &req={5} ?WAIT4_END_GROUP;
FFMA R15, R15, UR6, R0 &req={2} ?trans2;
LDG.E R0, desc[UR4][R6.64+0x8] &wr=0x2 ?trans4;
STG.E desc[UR4][R6.64+0x4], R15 &rd=0x1 ?trans4;
LDG.E R8, desc[UR4][R2.64+0x8] &wr=0x3 ?trans4;
LDG.E R9, desc[UR4][R16.64+0x8] &wr=0x3 ?trans4;
LDG.E R11, desc[UR4][R4.64+0xc] &wr=0x4 ?trans4;
LDG.E R13, desc[UR4][R4.64+0x8] &req={0} &wr=0x5 ?trans1;
FADD R8, R8, -R9 &req={3} ?WAIT4_END_GROUP;
FADD R8, R8, -R11 &req={4} ?WAIT4_END_GROUP;
FADD R13, R8, R13 &req={5} ?WAIT4_END_GROUP;
FFMA R13, R13, UR6, R0 &req={2} ?trans2;
LDG.E R0, desc[UR4][R6.64+0xc] &wr=0x2 ?trans4;
STG.E desc[UR4][R6.64+0x8], R13 ?trans4;
LDG.E R8, desc[UR4][R2.64+0xc] &wr=0x3 ?trans4;
LDG.E R9, desc[UR4][R16.64+0xc] &wr=0x3 ?trans4;
LDG.E R11, desc[UR4][R4.64+0x10] &wr=0x4 ?trans4;
LDG.E R15, desc[UR4][R4.64+0xc] &req={1} &wr=0x5 ?trans1;
FADD R8, R8, -R9 &req={3} ?WAIT4_END_GROUP;
FADD R8, R8, -R11 &req={4} ?WAIT4_END_GROUP;
FADD R15, R8, R15 &req={5} ?WAIT4_END_GROUP;
FFMA R15, R15, UR6, R0 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64+0xc], R15 ?trans1;
EXIT ?trans5;
BRA 0xa50;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: WaveStepH(float*, float*, float*, float*, float*, float*, int, int, int, float, float, float*)
_Z9WaveStepHPfS_S_S_S_S_iiiffS_:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x5c
s_load_b128 s[8:11], s[0:1], 0x30
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v1, v0, 10, 10
v_bfe_u32 v5, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[3:4], null, s14, s4, v[1:2]
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[0:1], null, s13, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[5:6]
v_cmp_gt_i32_e32 vcc_lo, s9, v3
v_cmp_gt_i32_e64 s2, s8, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e64 s3, s10, v1
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_mul_lo_u32 v2, v3, s8
s_mul_i32 s2, s9, s8
v_lshlrev_b32_e32 v19, 2, v0
v_mul_lo_u32 v20, s2, v1
s_load_b128 s[12:15], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v0, v2, v19
v_add_nc_u32_e32 v1, s8, v2
v_add_nc_u32_e32 v21, s2, v20
s_load_b256 s[0:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v3, v20, v0
v_add3_u32 v5, v20, v1, v19
v_ashrrev_i32_e32 v22, 31, v20
v_add_nc_u32_e32 v0, v21, v0
v_ashrrev_i32_e32 v26, 31, v21
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[7:8], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[9:10], 2, v[5:6]
v_lshlrev_b64 v[11:12], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v13, vcc_lo, s12, v7
v_add_co_ci_u32_e32 v14, vcc_lo, s13, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s12, v11
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v12, vcc_lo
v_add_co_u32 v15, vcc_lo, s14, v9
v_add_co_ci_u32_e32 v16, vcc_lo, s15, v10, vcc_lo
s_clause 0x1
global_load_b32 v4, v[0:1], off
global_load_b32 v6, v[13:14], off
v_add_co_u32 v17, vcc_lo, s14, v7
v_add_co_ci_u32_e32 v18, vcc_lo, s15, v8, vcc_lo
global_load_b32 v23, v[15:16], off
v_add_co_u32 v0, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v8, vcc_lo
global_load_b32 v25, v[17:18], off
global_load_b32 v29, v[0:1], off
v_ashrrev_i32_e32 v15, 31, v19
v_ashrrev_i32_e32 v16, 31, v2
v_add_co_u32 v2, vcc_lo, v19, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v24, vcc_lo, v15, v16, vcc_lo
v_add_co_u32 v15, vcc_lo, v20, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v16, vcc_lo, v22, v24, vcc_lo
v_add_co_u32 v21, vcc_lo, v21, v2
v_add_co_ci_u32_e32 v22, vcc_lo, v26, v24, vcc_lo
v_lshlrev_b64 v[15:16], 2, v[15:16]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[21:22], 2, v[21:22]
s_waitcnt vmcnt(3)
v_sub_f32_e32 v2, v4, v6
s_waitcnt vmcnt(2)
v_sub_f32_e32 v2, v2, v23
v_add_co_u32 v23, vcc_lo, s12, v15
v_add_co_ci_u32_e32 v24, vcc_lo, s13, v16, vcc_lo
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_add_f32_e32 v2, v2, v25
v_add_co_u32 v25, vcc_lo, s12, v21
v_add_co_ci_u32_e32 v26, vcc_lo, s13, v22, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v29, s11, v2
global_store_b32 v[0:1], v29, off
s_clause 0x1
global_load_b32 v4, v[25:26], off offset:4
global_load_b32 v6, v[23:24], off offset:4
s_waitcnt vmcnt(0)
v_dual_sub_f32 v4, v4, v6 :: v_dual_add_nc_u32 v19, 1, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v20, 31, v19
v_lshlrev_b64 v[19:20], 2, v[19:20]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v27, vcc_lo, s14, v19
v_add_co_ci_u32_e32 v28, vcc_lo, s15, v20, vcc_lo
v_add_co_u32 v29, vcc_lo, s14, v15
v_add_co_ci_u32_e32 v30, vcc_lo, s15, v16, vcc_lo
global_load_b32 v32, v[27:28], off
v_add_co_u32 v27, vcc_lo, s0, v15
v_add_co_ci_u32_e32 v28, vcc_lo, s1, v16, vcc_lo
global_load_b32 v33, v[29:30], off offset:4
global_load_b96 v[0:2], v[27:28], off offset:4
s_waitcnt vmcnt(2)
v_dual_sub_f32 v4, v4, v32 :: v_dual_add_nc_u32 v31, 2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v32, 31, v31
s_waitcnt vmcnt(1)
v_add_f32_e32 v4, v4, v33
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[31:32], 2, v[31:32]
s_waitcnt vmcnt(0)
v_fma_f32 v0, s11, v4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v33, vcc_lo, s14, v31
v_add_co_ci_u32_e32 v34, vcc_lo, s15, v32, vcc_lo
global_store_b32 v[27:28], v0, off offset:4
s_clause 0x1
global_load_b32 v0, v[25:26], off offset:8
global_load_b32 v4, v[23:24], off offset:8
s_clause 0x1
global_load_b32 v6, v[33:34], off
global_load_b32 v33, v[29:30], off offset:8
s_waitcnt vmcnt(2)
v_sub_f32_e32 v0, v0, v4
v_add_nc_u32_e32 v4, 3, v5
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v0, v0, v6
v_ashrrev_i32_e32 v5, 31, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v0, v0, v33
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v6, s11, v0, v1
v_add_co_u32 v0, vcc_lo, s14, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s15, v5, vcc_lo
global_store_b32 v[27:28], v6, off offset:8
s_clause 0x1
global_load_b32 v6, v[25:26], off offset:12
global_load_b32 v25, v[23:24], off offset:12
s_clause 0x1
global_load_b32 v0, v[0:1], off
global_load_b32 v1, v[29:30], off offset:12
s_waitcnt vmcnt(2)
v_sub_f32_e32 v6, v6, v25
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_f32_e32 v0, v6, v0
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v2, s11, v0
v_add_co_u32 v0, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v12, vcc_lo
global_store_b32 v[27:28], v2, off offset:12
s_clause 0x1
global_load_b32 v2, v[29:30], off offset:4
global_load_b32 v6, v[17:18], off
v_add_co_u32 v11, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v8, vcc_lo
global_load_b32 v17, v[0:1], off
v_add_co_u32 v0, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v8, vcc_lo
global_load_b32 v18, v[11:12], off
global_load_b32 v25, v[0:1], off
s_waitcnt vmcnt(3)
v_sub_f32_e32 v2, v2, v6
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_sub_f32_e32 v2, v2, v17
v_add_co_u32 v17, vcc_lo, s6, v21
s_waitcnt vmcnt(1)
v_add_f32_e32 v2, v2, v18
v_add_co_ci_u32_e32 v18, vcc_lo, s7, v22, vcc_lo
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2)
v_fmac_f32_e32 v25, s11, v2
global_store_b32 v[0:1], v25, off
global_load_b64 v[21:22], v[29:30], off offset:4
v_add_co_u32 v25, vcc_lo, s6, v15
v_add_co_ci_u32_e32 v26, vcc_lo, s7, v16, vcc_lo
global_load_b32 v6, v[17:18], off offset:4
v_add_co_u32 v27, vcc_lo, s2, v15
v_add_co_ci_u32_e32 v28, vcc_lo, s3, v16, vcc_lo
global_load_b32 v33, v[25:26], off offset:4
global_load_b96 v[0:2], v[27:28], off offset:4
s_waitcnt vmcnt(3)
v_sub_f32_e32 v21, v22, v21
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_f32_e32 v6, v21, v6
s_waitcnt vmcnt(1)
v_add_f32_e32 v6, v6, v33
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fma_f32 v0, s11, v6, v0
global_store_b32 v[27:28], v0, off offset:4
global_load_b64 v[21:22], v[29:30], off offset:8
s_clause 0x1
global_load_b32 v0, v[17:18], off offset:8
global_load_b32 v6, v[25:26], off offset:8
s_waitcnt vmcnt(2)
v_dual_sub_f32 v22, v22, v21 :: v_dual_add_nc_u32 v21, 4, v3
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v0, v22, v0
v_ashrrev_i32_e32 v22, 31, v21
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v0, v0, v6
v_lshlrev_b64 v[21:22], 2, v[21:22]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v3, s11, v0, v1
v_add_co_u32 v0, vcc_lo, s14, v21
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s15, v22, vcc_lo
global_store_b32 v[27:28], v3, off offset:8
s_clause 0x1
global_load_b32 v0, v[0:1], off
global_load_b32 v1, v[29:30], off offset:12
s_clause 0x1
global_load_b32 v3, v[17:18], off offset:12
global_load_b32 v6, v[25:26], off offset:12
s_waitcnt vmcnt(2)
v_sub_f32_e32 v0, v0, v1
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_f32_e32 v0, v0, v3
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v6
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v2, s11, v0
v_add_co_u32 v0, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v10, vcc_lo
global_store_b32 v[27:28], v2, off offset:12
s_clause 0x1
global_load_b32 v2, v[0:1], off
global_load_b32 v3, v[11:12], off
global_load_b32 v6, v[23:24], off offset:4
v_add_co_u32 v0, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v8, vcc_lo
global_load_b32 v7, v[13:14], off
global_load_b32 v8, v[0:1], off
s_waitcnt vmcnt(3)
v_sub_f32_e32 v2, v2, v3
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_f32_e32 v2, v2, v6
s_waitcnt vmcnt(1)
v_add_f32_e32 v2, v2, v7
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v8, s11, v2
v_add_co_u32 v2, vcc_lo, s6, v19
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v20, vcc_lo
global_store_b32 v[0:1], v8, off
s_clause 0x1
global_load_b32 v3, v[2:3], off
global_load_b32 v10, v[25:26], off offset:4
global_load_b64 v[6:7], v[23:24], off offset:4
v_add_co_u32 v8, vcc_lo, s4, v15
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v16, vcc_lo
global_load_b96 v[0:2], v[8:9], off offset:4
s_waitcnt vmcnt(2)
v_sub_f32_e32 v3, v3, v10
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v3, v3, v7
v_add_f32_e32 v3, v3, v6
v_add_co_u32 v6, vcc_lo, s6, v31
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v32, vcc_lo
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_3)
v_fma_f32 v0, s11, v3, v0
global_store_b32 v[8:9], v0, off offset:4
s_clause 0x1
global_load_b32 v0, v[6:7], off
global_load_b32 v3, v[25:26], off offset:8
global_load_b64 v[6:7], v[23:24], off offset:8
s_waitcnt vmcnt(1)
v_sub_f32_e32 v0, v0, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v0, v0, v7
v_add_f32_e32 v0, v0, v6
s_delay_alu instid0(VALU_DEP_1)
v_fma_f32 v3, s11, v0, v1
v_add_co_u32 v0, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v5, vcc_lo
global_store_b32 v[8:9], v3, off offset:8
s_clause 0x1
global_load_b32 v3, v[0:1], off
global_load_b32 v4, v[25:26], off offset:12
v_add_co_u32 v0, vcc_lo, s12, v21
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v22, vcc_lo
s_clause 0x1
global_load_b32 v0, v[0:1], off
global_load_b32 v1, v[23:24], off offset:12
s_waitcnt vmcnt(2)
v_sub_f32_e32 v3, v3, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_f32_e32 v0, v3, v0
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v2, s11, v0
global_store_b32 v[8:9], v2, off offset:12
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| WaveStepH | 4,542 | 6,392 | stackv2-00000-of-00015 |
// Demangled: superKernel(int volatile*, int, int*)
Function : _Z11superKernelPViiPi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R3, SR_TID.Y &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x2 ?trans1;
IMAD R0, R3, UR4, R0 &req={1} ?WAIT3_END_GROUP;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans1;
UMOV UR4, 0x1 ?trans1;
LOP3.LUT R5, R0, 0x1f, RZ, 0xc0, !PT &req={2} ?WAIT7_END_GROUP;
LDG.E.STRONG.SYS R4, desc[UR6][R2.64] &req={1} &wr=0x2 ?trans1;
MOV R7, UR4 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x1, URZ ?trans1;
ISETP.NE.AND P0, PT, R4, RZ, PT &req={2} ?WAIT13_END_GROUP;
@!P0 BRA 0x90 ?trans5;
LDCU UR4, c[0x0][0x388] &wr=0x1 ?trans1;
ISETP.NE.AND P1, PT, R5.reuse, RZ, PT ?trans1;
ISETP.GE.AND P0, PT, R5, UR4, PT &req={1} ?WAIT5_END_GROUP;
ISETP.GT.U32.OR P0, PT, R0, 0x1f, P0 ?WAIT13_END_GROUP;
@!P0 LDC.64 R2, c[0x0][0x390] &wr=0x1 ?trans2;
@!P0 IMAD.WIDE.U32 R2, R5, 0x4, R2 &req={1} ?WAIT5_END_GROUP;
@!P0 STG.E desc[UR6][R2.64+0x4], R7 &rd=0x1 ?trans1;
@P1 EXIT ?trans5;
LDC.64 R2, c[0x0][0x390] &req={1} &wr=0x1 ?trans2;
STG.E desc[UR6][R2.64], R7 &req={1} ?trans1;
EXIT ?trans5;
BRA 0x190;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: superKernel(int volatile*, int, int*)
_Z11superKernelPViiPi:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s4, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v2, s3
s_mov_b32 s2, 0
s_mov_b32 s3, 0
.LBB0_1:
flat_load_b32 v3, v[1:2] glc dlc
s_waitcnt vmcnt(0)
s_add_i32 s3, s3, 1
s_waitcnt lgkmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 0, v3
v_mov_b32_e32 v3, s3
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_1
s_or_b32 exec_lo, exec_lo, s2
s_clause 0x1
s_load_b32 s5, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_and_b32 s0, 0xffff, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u32_u24 v1, v0, s0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_and_b32_e32 v0, 31, v1
v_cmp_gt_u32_e64 s0, 32, v1
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s1, s0, vcc_lo
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_4
v_lshlrev_b32_e32 v1, 2, v0
global_store_b32 v1, v3, s[2:3] offset:4
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
global_store_b32 v0, v3, s[2:3]
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| superKernel | 708 | 776 | stackv2-00000-of-00015 |
// Demangled: scalar(int const*, int const*, int, int*)
Function : _Z6scalarPKiS0_iPi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x2 ?trans6;
LDC R4, c[0x0][0x370] &wr=0x2 ?trans1;
BSSY.RECONVERGENT B2, 0xf90 ?trans1;
S2R R2, SR_TID.X &wr=0x1 ?trans1;
LDCU UR8, c[0x0][0x390] &wr=0x3 ?trans1;
HFMA2 R16, -RZ, RZ, 0, 0 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x4 ?trans1;
IMAD R4, R4, UR4, RZ &req={2} ?WAIT2_END_GROUP;
IMAD R13, R0, UR4, R2 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R13, UR8, PT &req={3} ?WAIT13_END_GROUP;
@P0 BRA 0xf80 &req={4,0} ?trans5;
I2F.U32.RP R9, R4 &wr=0x0 ?trans1;
IADD3 R3, PT, PT, R4.reuse, R13, RZ ?trans2;
IADD3 R11, PT, PT, RZ, -R4, RZ ?trans1;
ISETP.NE.U32.AND P2, PT, R4, RZ, PT ?trans1;
BSSY.RECONVERGENT B1, 0xea0 ?trans1;
MOV R16, RZ ?trans1;
ISETP.GE.AND P0, PT, R3.reuse, UR8, PT ?trans1;
VIMNMX.S32 R8, R3, UR8, !PT ?WAIT4_END_GROUP;
SEL R5, RZ, 0x1, P0 ?trans1;
MUFU.RCP R9, R9 &req={0} &wr=0x0 ?trans4;
IADD3 R3, PT, PT, R8, -R3, -R5 ?trans2;
IADD3 R6, PT, PT, R9, 0xffffffe, RZ &req={0} ?WAIT4_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R7, R6 &rd=0x0 &wr=0x1 ?trans2;
MOV R6, RZ &req={0} ?trans1;
IMAD R11, R11, R7, RZ &req={1} ?WAIT4_END_GROUP;
IMAD.HI.U32 R10, R7, R11, R6 ?WAIT6_END_GROUP;
IMAD.HI.U32 R10, R10, R3, RZ ?WAIT5_END_GROUP;
IADD3 R6, PT, PT, -R10, RZ, RZ ?WAIT5_END_GROUP;
IMAD R3, R4, R6, R3 ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R3, R4, PT ?WAIT13_END_GROUP;
@P0 IADD3 R3, PT, PT, -R4, R3, RZ ?trans2;
@P0 IADD3 R10, PT, PT, R10, 0x1, RZ ?WAIT3_END_GROUP;
ISETP.GE.U32.AND P1, PT, R3, R4, PT ?WAIT13_END_GROUP;
@P1 IADD3 R10, PT, PT, R10, 0x1, RZ ?trans2;
@!P2 LOP3.LUT R10, RZ, R4, RZ, 0x33, !PT ?WAIT4_END_GROUP;
IADD3 R5, PT, PT, R5, R10, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R5.reuse, 0x3, PT ?trans1;
IADD3 R3, PT, PT, R5, 0x1, RZ ?WAIT4_END_GROUP;
LOP3.LUT R6, R3, 0x3, RZ, 0xc0, !PT ?WAIT8_END_GROUP;
@!P0 BRA 0xe90 ?trans5;
LOP3.LUT R3, R3, 0xfffffffc, RZ, 0xc0, !PT ?trans1;
BSSY.RELIABLE B0, 0xce0 ?trans1;
MOV R16, RZ ?trans2;
IADD3 R3, PT, PT, -R3, RZ, RZ ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R3, RZ, PT ?WAIT13_END_GROUP;
@P0 BRA 0xcd0 ?trans5;
IADD3 R5, PT, PT, -R3, RZ, RZ ?trans1;
BSSY.RECONVERGENT B3, 0x950 ?trans1;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x8 ?WAIT3_END_GROUP;
ISETP.GT.AND P1, PT, R5, 0xc, PT ?WAIT13_END_GROUP;
@!P1 BRA 0x940 ?trans5;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x80 ?WAIT13_END_GROUP;
LDC.64 R18, c[0x0][0x380] &wr=0x0 ?trans8;
LDC.64 R20, c[0x0][0x388] &wr=0x1 ?trans1;
IMAD.WIDE R8, R13, 0x4, R18 &req={0} ?WAIT5_END_GROUP;
LDG.E R22, desc[UR6][R8.64] &rd=0x0 &wr=0x2 ?trans1;
IMAD.WIDE R10, R13, 0x4, R20 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE R28, R4.reuse, 0x4, R8 ?trans1;
LDG.E R24, desc[UR6][R10.64] &wr=0x2 ?trans3;
IMAD.WIDE R32, R4.reuse, 0x4, R10 ?trans1;
LDG.E R5, desc[UR6][R28.64] &rd=0x1 &wr=0x3 ?trans4;
LDG.E R14, desc[UR6][R32.64] &wr=0x3 ?trans1;
IMAD.WIDE R26, R4, 0x4, R28 ?WAIT4_END_GROUP;
IMAD.WIDE R34, R4.reuse, 0x4, R32 ?trans1;
LDG.E R12, desc[UR6][R26.64] &wr=0x4 ?trans4;
LDG.E R7, desc[UR6][R34.64] &rd=0x5 &wr=0x4 ?trans1;
IADD3 R13, PT, PT, R4, R13, R4 ?WAIT4_END_GROUP;
IADD3 R13, PT, PT, R4, R13, R4 ?WAIT4_END_GROUP;
IADD3 R9, PT, PT, R4, R13, R4 &req={0} ?WAIT4_END_GROUP;
IADD3 R36, PT, PT, R4, R9, R4 ?WAIT5_END_GROUP;
IMAD.WIDE R40, R36, 0x4, R18 ?WAIT4_END_GROUP;
IMAD.WIDE R30, R13, 0x4, R18 ?trans1;
LDG.E R23, desc[UR6][R40.64] &rd=0x0 &wr=0x4 ?trans3;
IMAD.WIDE R8, R4, 0x4, R40 ?WAIT4_END_GROUP;
IMAD.WIDE R28, R4.reuse, 0x4, R30 &req={1} ?trans1;
LDG.E R17, desc[UR6][R8.64] &rd=0x1 &wr=0x4 ?trans3;
IMAD.WIDE R38, R4.reuse, 0x4, R8 ?trans1;
LDG.E R31, desc[UR6][R30.64] &wr=0x4 ?trans3;
IMAD.WIDE R34, R4, 0x4, R34 &req={5} ?WAIT4_END_GROUP;
IMAD.WIDE R26, R4.reuse, 0x4, R26 ?trans1;
IADD3 R41, PT, PT, R4.reuse, R36, R4 &req={0} ?trans1;
LDG.E R34, desc[UR6][R34.64] &wr=0x5 ?trans2;
IMAD.WIDE R8, R13, 0x4, R20 &req={1} ?trans2;
LDG.E R33, desc[UR6][R26.64] &wr=0x5 ?trans2;
IMAD.WIDE R10, R4, 0x4, R28 ?trans2;
LDG.E R32, desc[UR6][R8.64] &rd=0x0 &wr=0x5 ?trans2;
IMAD.WIDE R36, R36, 0x4, R20 ?WAIT2_END_GROUP;
LDG.E R29, desc[UR6][R28.64] &wr=0x5 ?trans4;
LDG.E R27, desc[UR6][R10.64] &rd=0x1 &wr=0x5 ?trans1;
IMAD.WIDE R8, R4, 0x4, R8 &req={0} ?WAIT3_END_GROUP;
LDG.E R15, desc[UR6][R38.64] &wr=0x5 ?trans4;
LDG.E R30, desc[UR6][R8.64] &rd=0x0 &wr=0x5 ?trans1;
IMAD.WIDE R10, R4, 0x4, R10 &req={1} ?WAIT5_END_GROUP;
LDG.E R25, desc[UR6][R10.64] &rd=0x1 &wr=0x5 ?trans1;
IMAD.WIDE R8, R4, 0x4, R8 &req={0} ?WAIT5_END_GROUP;
LDG.E R28, desc[UR6][R8.64] &rd=0x0 &wr=0x5 ?trans1;
IMAD.WIDE R10, R4, 0x4, R38 &req={1} ?WAIT5_END_GROUP;
LDG.E R13, desc[UR6][R10.64] &rd=0x1 &wr=0x5 ?trans1;
IMAD.WIDE R8, R4, 0x4, R8 &req={0} ?WAIT5_END_GROUP;
LDG.E R26, desc[UR6][R8.64] &rd=0x0 &wr=0x5 ?trans1;
IMAD.WIDE R10, R4, 0x4, R36 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE R8, R4, 0x4, R10 &req={0} ?WAIT4_END_GROUP;
IMAD R22, R22, R24, R16 &req={2} ?trans2;
LDG.E R24, desc[UR6][R36.64] &wr=0x2 ?trans4;
LDG.E R16, desc[UR6][R8.64] &rd=0x0 &wr=0x2 ?trans1;
IMAD R14, R5, R14, R22 &req={3} ?trans1;
IADD3 R5, PT, PT, R4, R41, R4 ?trans2;
LDG.E R22, desc[UR6][R10.64] &wr=0x3 ?trans3;
IMAD.WIDE R18, R5, 0x4, R18 ?WAIT4_END_GROUP;
IMAD.WIDE R20, R5, 0x4, R20 ?trans1;
LDG.E R11, desc[UR6][R18.64] &rd=0x1 &wr=0x3 ?trans3;
IMAD.WIDE R8, R4, 0x4, R8 &req={0} ?WAIT4_END_GROUP;
IMAD R7, R12, R7, R14 &req={4} ?trans2;
LDG.E R12, desc[UR6][R20.64] &rd=0x0 &wr=0x4 ?trans1;
IMAD.WIDE R18, R4, 0x4, R18 &req={1} ?WAIT3_END_GROUP;
LDG.E R14, desc[UR6][R8.64] &wr=0x4 ?trans1;
IMAD.WIDE R20, R4, 0x4, R20 &req={0} ?WAIT3_END_GROUP;
LDG.E R9, desc[UR6][R18.64] &rd=0x0 &wr=0x4 ?trans4;
LDG.E R10, desc[UR6][R20.64] &rd=0x1 &wr=0x4 ?trans1;
IMAD.WIDE R18, R4, 0x4, R18 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE R20, R4.reuse, 0x4, R20 &req={1} ?trans1;
LDG.E R8, desc[UR6][R18.64] &rd=0x0 &wr=0x4 ?trans4;
LDG.E R37, desc[UR6][R20.64] &rd=0x1 &wr=0x4 ?trans1;
IMAD.WIDE R18, R4, 0x4, R18 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE R20, R4, 0x4, R20 &req={1} ?trans1;
LDG.E R35, desc[UR6][R18.64] &wr=0x4 ?trans4;
LDG.E R36, desc[UR6][R20.64] &wr=0x4 ?trans1;
IMAD R7, R33, R34, R7 &req={5} ?WAIT4_END_GROUP;
IMAD R7, R31, R32, R7 ?WAIT4_END_GROUP;
IMAD R7, R29, R30, R7 ?WAIT4_END_GROUP;
IMAD R7, R27, R28, R7 ?trans1;
IADD3 R3, PT, PT, R3, 0x10, RZ ?WAIT3_END_GROUP;
IMAD R7, R25, R26, R7 ?trans2;
ISETP.GE.AND P1, PT, R3, -0xc, PT ?trans1;
IADD3 R5, PT, PT, R4, R5, R4 ?trans1;
IMAD R7, R23, R24, R7 &req={2} ?WAIT4_END_GROUP;
IMAD R7, R17, R22, R7 &req={3} ?WAIT4_END_GROUP;
IMAD R7, R15, R16, R7 ?WAIT4_END_GROUP;
IMAD R7, R13, R14, R7 &req={4} ?WAIT4_END_GROUP;
IMAD R7, R11, R12, R7 ?trans1;
IADD3 R13, PT, PT, R4, R5, R4 ?WAIT3_END_GROUP;
IMAD R7, R9, R10, R7 ?WAIT4_END_GROUP;
IMAD R7, R8, R37, R7 ?WAIT4_END_GROUP;
IMAD R16, R35, R36, R7 ?trans1;
@!P1 BRA 0x370 ?trans6;
BSYNC.RECONVERGENT B3 ?trans5;
IADD3 R5, PT, PT, -R3, RZ, RZ ?trans1;
BSSY.RECONVERGENT B3, 0xca0 ?trans4;
ISETP.GT.AND P1, PT, R5, 0x4, PT ?WAIT13_END_GROUP;
@!P1 BRA 0xc90 ?trans5;
LDC.64 R8, c[0x0][0x380] &wr=0x0 ?trans1;
IADD3 R5, PT, PT, R4, R13, R4 ?WAIT7_END_GROUP;
LDC.64 R10, c[0x0][0x388] &wr=0x1 ?trans1;
IADD3 R5, PT, PT, R4, R5, R4 ?trans1;
IMAD.WIDE R20, R13, 0x4, R8 &req={0} ?WAIT5_END_GROUP;
LDG.E R17, desc[UR6][R20.64] &rd=0x0 &wr=0x2 ?trans1;
IMAD.WIDE R24, R4, 0x4, R20 ?WAIT4_END_GROUP;
IMAD.WIDE R30, R13, 0x4, R10 &req={1} ?trans1;
LDG.E R7, desc[UR6][R24.64] &rd=0x1 &wr=0x3 ?trans3;
IMAD.WIDE R26, R4.reuse, 0x4, R24 ?trans1;
LDG.E R23, desc[UR6][R30.64] &rd=0x4 &wr=0x2 ?trans3;
IMAD.WIDE R28, R4, 0x4, R30 ?WAIT4_END_GROUP;
IMAD.WIDE R8, R5, 0x4, R8 ?trans1;
LDG.E R22, desc[UR6][R28.64] &rd=0x5 &wr=0x3 ?trans3;
IMAD.WIDE R18, R4, 0x4, R28 ?WAIT4_END_GROUP;
IMAD.WIDE R10, R5, 0x4, R10 ?WAIT4_END_GROUP;
IMAD.WIDE R14, R4.reuse, 0x4, R26 ?trans2;
LDG.E R26, desc[UR6][R26.64] &wr=0x3 ?trans2;
IMAD.WIDE R12, R4.reuse, 0x4, R18 ?trans2;
LDG.E R19, desc[UR6][R18.64] &wr=0x3 ?trans2;
IMAD.WIDE R20, R4.reuse, 0x4, R8 &req={0} ?trans2;
LDG.E R32, desc[UR6][R14.64] &rd=0x0 &wr=0x3 ?trans2;
IMAD.WIDE R24, R4, 0x4, R10 &req={1} ?WAIT2_END_GROUP;
LDG.E R33, desc[UR6][R12.64] &rd=0x1 &wr=0x3 ?trans2;
IMAD.WIDE R30, R4.reuse, 0x4, R20 &req={4} ?trans2;
LDG.E R8, desc[UR6][R8.64] &wr=0x4 ?trans2;
IMAD.WIDE R28, R4.reuse, 0x4, R24 &req={5} ?trans2;
LDG.E R11, desc[UR6][R10.64] &wr=0x4 ?trans2;
IMAD.WIDE R14, R4, 0x4, R30 &req={0} ?WAIT2_END_GROUP;
LDG.E R20, desc[UR6][R20.64] &wr=0x5 ?trans2;
IMAD.WIDE R12, R4.reuse, 0x4, R28 &req={1} ?trans2;
LDG.E R24, desc[UR6][R24.64] &wr=0x5 ?trans4;
LDG.E R18, desc[UR6][R30.64] &wr=0x5 ?trans4;
LDG.E R27, desc[UR6][R28.64] &wr=0x5 ?trans4;
LDG.E R14, desc[UR6][R14.64] &wr=0x5 ?trans4;
LDG.E R12, desc[UR6][R12.64] &rd=0x0 &wr=0x5 ?trans1;
IADD3 R5, PT, PT, R4, R5, R4 ?WAIT2_END_GROUP;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x80 ?trans2;
IADD3 R3, PT, PT, R3, 0x8, RZ ?trans2;
IADD3 R13, PT, PT, R4, R5, R4 &req={0} ?trans1;
IMAD R17, R17, R23, R16 &req={2} ?WAIT4_END_GROUP;
IMAD R7, R7, R22, R17 &req={3} ?WAIT4_END_GROUP;
IMAD R7, R26, R19, R7 ?WAIT4_END_GROUP;
IMAD R7, R32, R33, R7 ?WAIT4_END_GROUP;
IMAD R7, R8, R11, R7 &req={4} ?WAIT4_END_GROUP;
IMAD R7, R20, R24, R7 &req={5} ?WAIT4_END_GROUP;
IMAD R7, R18, R27, R7 ?WAIT4_END_GROUP;
IMAD R16, R14, R12, R7 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B3 ?trans5;
ISETP.NE.OR P0, PT, R3, RZ, P0 ?WAIT13_END_GROUP;
@!P0 BREAK.RELIABLE B0 ?trans5;
@!P0 BRA 0xe90 ?trans5;
BSYNC.RELIABLE B0 ?trans5;
LDC.64 R8, c[0x0][0x380] &wr=0x0 ?trans8;
LDC.64 R10, c[0x0][0x388] &wr=0x1 ?trans1;
IMAD.WIDE R8, R13, 0x4, R8 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE R14, R4, 0x4, R8 ?trans2;
LDG.E R9, desc[UR6][R8.64] &wr=0x2 ?trans2;
IMAD.WIDE R10, R13, 0x4, R10 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE R18, R4.reuse, 0x4, R10 ?trans2;
LDG.E R10, desc[UR6][R10.64] &wr=0x2 ?trans2;
IMAD.WIDE R20, R4.reuse, 0x4, R14 ?trans2;
LDG.E R14, desc[UR6][R14.64] &wr=0x3 ?trans2;
IMAD.WIDE R22, R4.reuse, 0x4, R18 ?trans2;
LDG.E R18, desc[UR6][R18.64] &wr=0x3 ?trans2;
IMAD.WIDE R24, R4, 0x4, R20 ?WAIT2_END_GROUP;
LDG.E R12, desc[UR6][R20.64] &wr=0x4 ?trans2;
IMAD.WIDE R26, R4, 0x4, R22 ?trans2;
LDG.E R22, desc[UR6][R22.64] &wr=0x4 ?trans4;
LDG.E R24, desc[UR6][R24.64] &wr=0x5 ?trans4;
LDG.E R26, desc[UR6][R26.64] &wr=0x5 ?trans1;
IADD3 R3, PT, PT, R3, 0x4, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R3, RZ, PT ?trans1;
IADD3 R13, PT, PT, R4, R13, R4 ?WAIT4_END_GROUP;
IADD3 R13, PT, PT, R4, R13, R4 ?trans1;
IMAD R9, R9, R10, R16 &req={2} ?WAIT4_END_GROUP;
IMAD R9, R14, R18, R9 &req={3} ?WAIT4_END_GROUP;
IMAD R9, R12, R22, R9 &req={4} ?WAIT4_END_GROUP;
IMAD R16, R24, R26, R9 &req={5} ?trans1;
@P0 BRA 0xce0 ?trans6;
BSYNC.RECONVERGENT B1 ?trans5;
ISETP.NE.AND P0, PT, R6, RZ, PT ?WAIT13_END_GROUP;
@!P0 BRA 0xf80 ?trans5;
LDC.64 R10, c[0x0][0x380] &wr=0x0 ?trans1;
IADD3 R3, PT, PT, -R6, RZ, RZ ?WAIT7_END_GROUP;
LDC.64 R8, c[0x0][0x388] &wr=0x1 ?trans2;
IMAD.WIDE R6, R13, 0x4, R8 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE R14, R13, 0x4, R10 &req={0} ?trans2;
LDG.E R6, desc[UR6][R6.64] &wr=0x2 ?trans4;
LDG.E R15, desc[UR6][R14.64] &wr=0x2 ?trans1;
IADD3 R3, PT, PT, R3, 0x1, RZ ?trans2;
IADD3 R13, PT, PT, R4, R13, RZ ?WAIT3_END_GROUP;
ISETP.NE.AND P0, PT, R3, RZ, PT ?trans1;
IMAD R16, R15, R6, R16 &req={2} ?WAIT12_END_GROUP;
@P0 BRA 0xef0 ?trans5;
BSYNC.RECONVERGENT B2 ?trans5;
WARPSYNC.ALL ?trans5;
NOP ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x0 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GT.U32.AND P0, PT, R2.reuse, 0x9, PT ?trans1;
ISETP.GT.U32.AND P1, PT, R2, 0x4, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={0} ?WAIT6_END_GROUP;
LEA R3, R2, UR4, 0x2 ?WAIT5_END_GROUP;
STS [R3], R16 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 LDS R4, [R3+0x28] ?trans4;
@!P0 LDS R5, [R3] &wr=0x0 ?trans2;
@!P0 IADD3 R4, PT, PT, R4, R5, RZ &req={0} ?WAIT5_END_GROUP;
@!P0 STS [R3], R4 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P0, PT, R2, 0x1, PT ?WAIT5_END_GROUP;
@!P1 LDS R5, [R3+0x14] ?trans4;
@!P1 LDS R6, [R3] &wr=0x0 ?trans2;
@!P1 IADD3 R6, PT, PT, R5, R6, RZ &req={0} ?WAIT5_END_GROUP;
@!P1 STS [R3], R6 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.NE.AND P1, PT, R2, RZ, PT ?WAIT5_END_GROUP;
@!P0 LDS R5, [R3+0x8] ?trans4;
@!P0 LDS R8, [R3] &wr=0x0 ?trans2;
@!P0 IADD3 R8, PT, PT, R5, R8, RZ &req={0} ?WAIT5_END_GROUP;
@!P0 STS [R3], R8 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P1 LDS R2, [UR4+0x4] ?trans4;
@!P1 LDS R5, [R3] &wr=0x0 ?trans2;
@!P1 IADD3 R2, PT, PT, R2, R5, RZ &req={0} ?WAIT5_END_GROUP;
@!P1 STS [R3], R2 &rd=0x0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P1 EXIT ?trans5;
LDS R5, [UR4] &wr=0x1 ?trans1;
LDC.64 R2, c[0x0][0x398] &req={0} &wr=0x0 ?trans2;
IMAD.WIDE.U32 R2, R0, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R5 &req={1} ?trans1;
EXIT ?trans5;
BRA 0x11f0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: scalar(int const*, int const*, int, int*)
_Z6scalarPKiS0_iPi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s9, s[0:1], 0x10
s_add_u32 s2, s0, 32
s_mov_b32 s8, s15
s_addc_u32 s3, s1, 0
v_mov_b32_e32 v3, 0
s_mov_b32 s14, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s8, s10, v[0:1]
v_cmpx_gt_i32_e64 s9, v1
s_cbranch_execz .LBB0_4
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v3, 0
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[4:5], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s10, s2, s10
s_ashr_i32 s11, s10, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[12:13], s[10:11], 2
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v5, vcc_lo
v_add_nc_u32_e32 v1, s10, v1
global_load_b32 v2, v[6:7], off
global_load_b32 v8, v[8:9], off
v_cmp_le_i32_e64 s2, s9, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
s_or_b32 s3, s2, s3
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v8, v2, v[3:4]
v_add_co_u32 v4, vcc_lo, v4, s12
v_add_co_ci_u32_e32 v5, vcc_lo, s13, v5, vcc_lo
v_mov_b32_e32 v3, v6
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s3
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s14
v_lshlrev_b32_e32 v1, 2, v0
s_mov_b32 s2, 10
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_5:
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e64 s2, v0
s_cbranch_execz .LBB0_7
v_lshl_add_u32 v2, s2, 2, v1
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s3
s_lshr_b32 s3, s2, 1
s_cmp_gt_u32 s2, 1
s_mov_b32 s2, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
s_mov_b32 s9, 0
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_10
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x18
s_lshl_b64 s[2:3], s[8:9], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| scalar | 7,398 | 1,366 | stackv2-00000-of-00015 |
// Demangled: unrollTestKernel(int*)
Function : _Z16unrollTestKernelPi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans2;
LDG.E R0, desc[UR4][R2.64] &req={0} &wr=0x2 ?trans2;
IADD3 R5, PT, PT, R0, 0x14, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R5 ?trans1;
EXIT ?trans5;
BRA 0x70;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: unrollTestKernel(int*)
_Z16unrollTestKernelPi:
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s2, 20
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| unrollTestKernel | 230 | 164 | stackv2-00000-of-00015 |
// Demangled: matAdd(float*, float*, float*)
Function : _Z6matAddPfS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R0, SR_CTAID.X &wr=0x0 ?trans1;
LDCU UR6, c[0x0][0x360] &wr=0x0 ?trans6;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans1;
S2R R7, SR_TID.X &wr=0x0 ?trans1;
LDCU UR7, c[0x0][0x364] &wr=0x2 ?trans1;
S2R R6, SR_CTAID.Y &wr=0x2 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x3 ?trans4;
LDC.64 R4, c[0x0][0x388] &wr=0x4 ?trans1;
S2R R9, SR_TID.Y &wr=0x2 ?trans1;
IMAD R0, R0, UR6, R7 &req={0} ?WAIT2_END_GROUP;
IMAD R7, R6, UR7, R9 &req={2} ?WAIT4_END_GROUP;
IMAD R9, R0, 0x64, R7 ?trans2;
LDC.64 R6, c[0x0][0x390] &wr=0x0 ?trans2;
IMAD.WIDE R2, R9, 0x4, R2 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE R4, R9.reuse, 0x4, R4 &req={4} ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={3} &wr=0x2 ?trans4;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE R6, R9, 0x4, R6 &req={0} ?WAIT4_END_GROUP;
FADD R0, R2, R5 &req={2} ?WAIT6_END_GROUP;
F2I.TRUNC.NTZ R0, R0 &wr=0x0 ?trans2;
I2FP.F32.S32 R9, R0 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x180;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: matAdd(float*, float*, float*)
_Z6matAddPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
s_mul_i32 s15, s15, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, 0x64, v2
v_add3_u32 v0, s15, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f32_e32 v2, v2
v_cvt_f32_i32_e32 v2, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| matAdd | 658 | 693 | stackv2-00000-of-00015 |
// Demangled: kernelSumHistogram(unsigned long long*, unsigned long long*, int, int, int)
Function : _Z18kernelSumHistogramPyS_iii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
LDC R4, c[0x0][0x398] &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x380] &wr=0x2 ?trans1;
BSSY.RECONVERGENT B0, 0x1910 ?trans6;
LDC R9, c[0x0][0x390] &wr=0x3 ?trans8;
S2UR UR4, SR_CTAID.X &wr=0x4 ?trans1;
IABS R5, R4 &req={1} ?WAIT7_END_GROUP;
LDC R11, c[0x0][0x394] &wr=0x1 ?trans1;
I2F.RP R0, R5 &wr=0x5 ?trans1;
IABS R8, R9 &req={3} ?trans1;
MUFU.RCP R0, R0 &req={5} &wr=0x3 ?trans2;
IADD3 R2, PT, PT, R0, 0xffffffe, RZ &req={3} ?WAIT4_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R3, R2 &rd=0x3 &wr=0x5 ?trans2;
HFMA2 R2, -RZ, RZ, 0, 0 &req={3} ?trans1;
IADD3 R6, PT, PT, RZ, -R3, RZ &req={5} ?WAIT5_END_GROUP;
IMAD R7, R6, R5, RZ ?trans1;
MOV R6, R8 ?WAIT3_END_GROUP;
IMAD.HI.U32 R3, R3, R7, R2 ?trans2;
S2R R2, SR_TID.X &wr=0x4 ?trans4;
IMAD.HI.U32 R3, R3, R6, RZ ?WAIT5_END_GROUP;
IADD3 R0, PT, PT, -R3, RZ, RZ ?WAIT5_END_GROUP;
IMAD R0, R5, R0, R6 ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P1, PT, R5, R0, PT ?WAIT13_END_GROUP;
@!P1 IADD3 R0, PT, PT, R0, -R5, RZ ?trans2;
@!P1 IADD3 R3, PT, PT, R3, 0x1, RZ ?WAIT3_END_GROUP;
ISETP.GE.U32.AND P0, PT, R0, R5, PT ?trans1;
LOP3.LUT R0, R9, R4, RZ, 0x3c, !PT ?trans1;
LDC R5, c[0x0][0x360] &wr=0x4 ?trans4;
ISETP.GE.AND P1, PT, R0, RZ, PT ?WAIT7_END_GROUP;
@P0 IADD3 R3, PT, PT, R3, 0x1, RZ ?trans1;
ISETP.NE.AND P0, PT, R4, RZ, PT ?WAIT5_END_GROUP;
@!P1 IADD3 R3, PT, PT, -R3, RZ, RZ ?WAIT8_END_GROUP;
@!P0 LOP3.LUT R3, RZ, R4, RZ, 0x33, !PT ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, -R3, RZ, RZ ?WAIT5_END_GROUP;
IMAD R0, R4, R0, R9 ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R0, RZ, PT ?trans1;
IMAD R0, R5, UR4, R2 &req={4} ?trans1;
IADD3 R2, PT, PT, R3, 0x1, RZ ?WAIT4_END_GROUP;
ISETP.GE.AND P1, PT, R0, R11, PT &req={1} ?WAIT7_END_GROUP;
@!P0 IADD3 R2, PT, PT, R3, RZ, RZ ?WAIT6_END_GROUP;
@P1 BRA 0x1900 &req={2,0} ?trans5;
LDCU UR4, c[0x0][0x370] &wr=0x0 ?trans1;
LDC.64 R18, c[0x0][0x358] &wr=0x1 ?trans1;
ISETP.NE.AND P0, PT, R2, RZ, PT ?trans1;
IMAD R3, R5, UR4, RZ &req={0} ?WAIT12_END_GROUP;
@P0 BRA 0x370 ?trans5;
LDC.64 R6, c[0x0][0x388] &wr=0x0 ?trans2;
IMAD.WIDE R4, R0, 0x8, R6 &req={2,0} ?trans1;
IADD3 R0, PT, PT, R3, R0, RZ ?trans2;
R2UR UR4, R18 &req={1} ?trans2;
R2UR UR5, R19 ?trans1;
ISETP.GE.AND P0, PT, R0, R11, PT ?WAIT12_END_GROUP;
STG.E.64 desc[UR4][R4.64], RZ &rd=0x2 ?trans1;
@!P0 BRA 0x2f0 ?trans5;
BRA 0x1900 ?trans5;
IMAD R4, R11.reuse, 0xd, RZ ?trans1;
LOP3.LUT R6, R2.reuse, 0xf, RZ, 0xc0, !PT ?trans1;
IMAD R5, R11, 0xf, RZ ?trans1;
LOP3.LUT R7, R2, 0x7, RZ, 0xc0, !PT ?WAIT7_END_GROUP;
ISETP.GE.U32.AND P1, PT, R2, 0x10, PT ?trans1;
HFMA2 R13, -RZ, RZ, 0, 0 ?trans1;
MOV.64 R24, RZ ?trans2;
ISETP.NE.AND P0, PT, R6, RZ, PT ?trans1;
SHF.R.S32.HI R17, RZ, 0x1f, R0 ?trans1;
MOV R16, R0 ?WAIT7_END_GROUP;
@!P1 BRA 0xe80 ?trans5;
LDCU UR4, c[0x0][0x394] &wr=0x0 ?trans1;
LDC R11, c[0x0][0x394] &wr=0x2 ?trans1;
LOP3.LUT R9, R2, 0xfffffff0, RZ, 0xc0, !PT ?trans1;
MOV.64 R24, RZ ?trans2;
LDCU UR5, c[0x0][0x394] &wr=0x3 ?trans1;
MOV R8, RZ ?trans1;
MOV R30, R5 ?trans1;
MOV R32, R4 ?trans1;
MOV R13, RZ ?trans1;
IADD3 R9, PT, PT, -R9, RZ, RZ ?trans1;
UIMAD UR8, UR4, 0xc, URZ &req={0} ?trans1;
UIADD3 UR9, UPT, UPT, UR4, UR4, URZ ?trans1;
UIMAD UR10, UR4, 0x3, URZ ?trans1;
USHF.L.U32 UR11, UR4, 0x2, URZ ?trans1;
UIMAD UR12, UR4, 0x5, URZ ?trans1;
USHF.L.U32 UR13, UR4, 0x3, URZ ?trans1;
UIMAD UR14, UR4, 0x9, URZ ?trans1;
UIMAD UR15, UR4, 0xa, URZ ?trans1;
UIMAD UR16, UR4, 0xb, URZ ?trans1;
UIMAD UR4, UR4, 0x7, URZ ?trans1;
MOV R10, UR5 &req={3} ?trans1;
IMAD R31, R11.reuse, 0x6, RZ &req={2} ?trans1;
MOV R34, UR8 ?trans1;
IMAD R14, R11, 0xe, RZ ?trans1;
MOV R36, UR16 ?trans1;
MOV R15, UR15 ?trans1;
MOV R27, UR14 ?trans1;
MOV R29, UR13 ?trans1;
MOV R28, UR4 ?trans1;
MOV R33, UR12 ?trans1;
MOV R35, UR11 ?trans1;
MOV R12, UR10 ?trans1;
MOV R26, UR9 ?WAIT7_END_GROUP;
SHF.R.S32.HI R21, RZ, 0x1f, R8 ?trans1;
MOV R20, R8 ?trans1;
R2UR UR4, R18 &req={1} ?trans2;
R2UR UR5, R19 ?trans2;
IADD.64 R22, R16, R20 ?WAIT5_END_GROUP;
LEA R20, P1, R22, UR6, 0x3 ?WAIT4_END_GROUP;
LEA.HI.X R21, R22, UR7, R23, 0x3, P1 ?WAIT6_END_GROUP;
LDG.E.64 R20, desc[UR4][R20.64] &wr=0x2 ?trans1;
SHF.R.S32.HI R23, RZ, 0x1f, R10 ?trans1;
MOV R22, R10 ?trans1;
IADD.64 R24, R20, R24 &req={2} ?WAIT4_END_GROUP;
IADD.64 R20, R16, R22 ?WAIT5_END_GROUP;
LEA R22, P1, R20, UR6, 0x3 ?WAIT4_END_GROUP;
LEA.HI.X R23, R20, UR7, R21, 0x3, P1 ?WAIT6_END_GROUP;
LDG.E.64 R22, desc[UR4][R22.64] &wr=0x2 ?trans1;
SHF.R.S32.HI R21, RZ, 0x1f, R26 ?trans1;
MOV R20, R26 ?trans1;
IADD.64 R24, R24, R22 &req={2} ?WAIT4_END_GROUP;
IADD.64 R22, R16, R20 ?WAIT5_END_GROUP;
LEA R20, P1, R22, UR6, 0x3 ?WAIT4_END_GROUP;
LEA.HI.X R21, R22, UR7, R23, 0x3, P1 ?WAIT6_END_GROUP;
LDG.E.64 R20, desc[UR4][R20.64] &wr=0x2 ?trans2;
IADD.64 R24, R24, R20 &req={2} ?trans2;
MOV R20, R12 ?trans1;
SHF.R.S32.HI R21, RZ, 0x1f, R12 ?WAIT5_END_GROUP;
IADD.64 R20, R16, R20 ?WAIT5_END_GROUP;
LEA R22, P1, R20, UR6, 0x3 ?WAIT4_END_GROUP;
LEA.HI.X R23, R20, UR7, R21, 0x3, P1 ?WAIT6_END_GROUP;
LDG.E.64 R22, desc[UR4][R22.64] &wr=0x2 ?trans1;
SHF.R.S32.HI R21, RZ, 0x1f, R35 ?trans1;
MOV R20, R35 ?trans1;
IADD.64 R24, R24, R22 &req={2} ?WAIT4_END_GROUP;
IADD.64 R22, R16, R20 ?WAIT5_END_GROUP;
LEA R20, P1, R22, UR6, 0x3 ?WAIT4_END_GROUP;
LEA.HI.X R21, R22, UR7, R23, 0x3, P1 ?WAIT6_END_GROUP;
LDG.E.64 R20, desc[UR4][R20.64] &wr=0x2 ?trans2;
IADD.64 R24, R24, R20 &req={2} ?trans2;
MOV R20, R33 ?trans1;
SHF.R.S32.HI R21, RZ, 0x1f, R33 ?WAIT5_END_GROUP;
IADD.64 R20, R16, R20 ?WAIT5_END_GROUP;
LEA R22, P1, R20, UR6, 0x3 ?WAIT4_END_GROUP;
LEA.HI.X R23, R20, UR7, R21, 0x3, P1 ?WAIT6_END_GROUP;
LDG.E.64 R22, desc[UR4][R22.64] &wr=0x2 ?trans1;
SHF.R.S32.HI R21, RZ, 0x1f, R31 ?trans1;
MOV R20, R31 ?trans1;
IADD.64 R24, R24, R22 &req={2} ?WAIT4_END_GROUP;
IADD.64 R22, R16, R20 ?WAIT5_END_GROUP;
LEA R20, P1, R22, UR6, 0x3 ?WAIT4_END_GROUP;
LEA.HI.X R21, R22, UR7, R23, 0x3, P1 ?WAIT6_END_GROUP;
LDG.E.64 R20, desc[UR4][R20.64] &wr=0x2 ?trans2;
IADD.64 R24, R24, R20 &req={2} ?trans2;
MOV R20, R28 ?trans1;
SHF.R.S32.HI R21, RZ, 0x1f, R28 ?WAIT5_END_GROUP;
IADD.64 R20, R16, R20 ?WAIT5_END_GROUP;
LEA R22, P1, R20, UR6, 0x3 ?WAIT4_END_GROUP;
LEA.HI.X R23, R20, UR7, R21, 0x3, P1 ?WAIT6_END_GROUP;
LDG.E.64 R22, desc[UR4][R22.64] &wr=0x2 ?trans1;
SHF.R.S32.HI R21, RZ, 0x1f, R29 ?trans1;
MOV R20, R29 ?trans1;
IADD.64 R24, R24, R22 &req={2} ?WAIT4_END_GROUP;
IADD.64 R22, R16, R20 ?WAIT5_END_GROUP;
LEA R20, P1, R22, UR6, 0x3 ?WAIT4_END_GROUP;
LEA.HI.X R21, R22, UR7, R23, 0x3, P1 ?WAIT6_END_GROUP;
LDG.E.64 R20, desc[UR4][R20.64] &wr=0x2 ?trans2;
IADD.64 R24, R24, R20 &req={2} ?trans2;
MOV R20, R27 ?trans1;
SHF.R.S32.HI R21, RZ, 0x1f, R27 ?WAIT5_END_GROUP;
IADD.64 R20, R16, R20 ?WAIT5_END_GROUP;
LEA R22, P1, R20, UR6, 0x3 ?WAIT4_END_GROUP;
LEA.HI.X R23, R20, UR7, R21, 0x3, P1 ?WAIT6_END_GROUP;
LDG.E.64 R22, desc[UR4][R22.64] &wr=0x2 ?trans1;
SHF.R.S32.HI R21, RZ, 0x1f, R15 ?trans1;
MOV R20, R15 ?trans1;
IADD.64 R24, R24, R22 &req={2} ?WAIT4_END_GROUP;
IADD.64 R22, R16, R20 ?WAIT5_END_GROUP;
LEA R20, P1, R22, UR6, 0x3 ?WAIT4_END_GROUP;
LEA.HI.X R21, R22, UR7, R23, 0x3, P1 ?WAIT6_END_GROUP;
LDG.E.64 R20, desc[UR4][R20.64] &wr=0x2 ?trans1;
SHF.R.S32.HI R37, RZ, 0x1f, R36 ?trans1;
IADD.64 R24, R24, R20 &req={2} ?WAIT4_END_GROUP;
IADD.64 R20, R16, R36 ?WAIT5_END_GROUP;
LEA R22, P1, R20, UR6, 0x3 ?WAIT4_END_GROUP;
LEA.HI.X R23, R20, UR7, R21, 0x3, P1 ?WAIT6_END_GROUP;
LDG.E.64 R22, desc[UR4][R22.64] &wr=0x2 ?trans1;
SHF.R.S32.HI R21, RZ, 0x1f, R34 ?trans1;
MOV R20, R34 ?trans1;
IADD.64 R24, R24, R22 &req={2} ?WAIT4_END_GROUP;
IADD.64 R22, R16, R20 ?WAIT5_END_GROUP;
LEA R20, P1, R22, UR6, 0x3 ?WAIT4_END_GROUP;
LEA.HI.X R21, R22, UR7, R23, 0x3, P1 ?WAIT6_END_GROUP;
LDG.E.64 R20, desc[UR4][R20.64] &wr=0x2 ?trans2;
IADD.64 R24, R24, R20 &req={2} ?trans2;
MOV R20, R32 ?trans1;
SHF.R.S32.HI R21, RZ, 0x1f, R32 ?WAIT5_END_GROUP;
IADD.64 R20, R16, R20 ?WAIT5_END_GROUP;
LEA R22, P1, R20, UR6, 0x3 ?WAIT4_END_GROUP;
LEA.HI.X R23, R20, UR7, R21, 0x3, P1 ?WAIT6_END_GROUP;
LDG.E.64 R22, desc[UR4][R22.64] &wr=0x2 ?trans1;
SHF.R.S32.HI R21, RZ, 0x1f, R14 ?trans1;
MOV R20, R14 ?trans1;
IADD.64 R24, R24, R22 &req={2} ?WAIT4_END_GROUP;
IADD.64 R22, R16, R20 ?WAIT5_END_GROUP;
LEA R20, P1, R22, UR6, 0x3 ?WAIT4_END_GROUP;
LEA.HI.X R21, R22, UR7, R23, 0x3, P1 ?WAIT6_END_GROUP;
LDG.E.64 R20, desc[UR4][R20.64] &wr=0x2 ?trans2;
IADD.64 R20, R24, R20 &req={2} ?trans2;
MOV R24, R30 ?trans1;
SHF.R.S32.HI R25, RZ, 0x1f, R30 ?WAIT5_END_GROUP;
IADD.64 R22, R16, R24 ?WAIT5_END_GROUP;
LEA R24, P1, R22, UR6, 0x3 ?WAIT4_END_GROUP;
LEA.HI.X R25, R22, UR7, R23, 0x3, P1 ?WAIT6_END_GROUP;
LDG.E.64 R24, desc[UR4][R24.64] &wr=0x2 ?trans1;
IADD3 R9, PT, PT, R9, 0x10, RZ ?trans2;
IADD3 R13, PT, PT, R13, 0x10, RZ ?trans1;
IMAD R8, R11.reuse, 0x10, R8 ?trans2;
IMAD R10, R11, 0x10, R10 ?trans1;
ISETP.NE.AND P1, PT, R9, RZ, PT ?trans1;
IMAD R26, R11.reuse, 0x10, R26 ?trans2;
IMAD R12, R11, 0x10, R12 ?WAIT2_END_GROUP;
IMAD R35, R11.reuse, 0x10, R35 ?trans2;
IMAD R33, R11.reuse, 0x10, R33 ?trans2;
IMAD R31, R11.reuse, 0x10, R31 ?trans2;
IMAD R28, R11.reuse, 0x10, R28 ?trans2;
IMAD R29, R11.reuse, 0x10, R29 ?trans2;
IMAD R27, R11, 0x10, R27 ?WAIT2_END_GROUP;
IMAD R15, R11.reuse, 0x10, R15 ?trans2;
IMAD R36, R11.reuse, 0x10, R36 ?trans2;
IMAD R34, R11.reuse, 0x10, R34 ?trans2;
IMAD R32, R11.reuse, 0x10, R32 ?trans2;
IMAD R14, R11.reuse, 0x10, R14 ?trans2;
IMAD R30, R11, 0x10, R30 ?trans1;
IADD.64 R24, R20, R24 &req={2} ?WAIT2_END_GROUP;
@P1 BRA 0x630 ?trans6;
@!P0 BRA 0x1850 ?trans5;
IADD3 R8, PT, PT, R6, -0x1, RZ ?trans1;
ISETP.NE.AND P0, PT, R7, RZ, PT ?WAIT4_END_GROUP;
ISETP.GE.U32.AND P1, PT, R8, 0x7, PT ?WAIT13_END_GROUP;
@!P1 BRA 0x1380 ?trans5;
LDCU UR4, c[0x0][0x394] &wr=0x0 ?trans1;
R2UR UR10, R18.reuse &req={1} ?trans2;
R2UR UR11, R19.reuse ?trans1;
LDCU.64 UR8, c[0x0][0x380] &wr=0x1 ?trans1;
R2UR UR12, R18.reuse ?trans2;
R2UR UR13, R19.reuse ?trans2;
R2UR UR14, R18 ?trans2;
R2UR UR15, R19 ?WAIT2_END_GROUP;
R2UR UR16, R18.reuse ?trans2;
R2UR UR17, R19 ?trans2;
R2UR UR18, R18.reuse ?trans1;
IMAD R8, R13, UR4, RZ &req={0} ?trans1;
R2UR UR19, R19 ?trans2;
R2UR UR20, R18 ?trans2;
IADD3 R10, PT, PT, R8, UR4, RZ ?WAIT2_END_GROUP;
SHF.R.S32.HI R9, RZ, 0x1f, R8 ?trans2;
R2UR UR21, R19 ?trans2;
IADD3 R22, PT, PT, R10, UR4, RZ ?trans2;
SHF.R.S32.HI R11, RZ, 0x1f, R10 ?trans1;
IADD.64 R14, R16, R8 ?WAIT3_END_GROUP;
IADD3 R34, PT, PT, R22, UR4, RZ ?trans1;
IADD.64 R20, R16, R10 ?WAIT3_END_GROUP;
SHF.R.S32.HI R23, RZ, 0x1f, R22 ?trans2;
IADD3 R32, PT, PT, R34, UR4, RZ ?trans2;
LEA R8, P2, R20, UR8, 0x3 &req={1} ?trans2;
LEA R10, P1, R14, UR8, 0x3 ?trans1;
IADD.64 R22, R16, R22 ?WAIT3_END_GROUP;
IADD3 R30, PT, PT, R32, UR4, RZ ?trans2;
LEA.HI.X R9, R20, UR9, R21, 0x3, P2 ?trans2;
SHF.R.S32.HI R35, RZ, 0x1f, R34 ?trans2;
SHF.R.S32.HI R31, RZ, 0x1f, R30 ?trans2;
LEA.HI.X R11, R14, UR9, R15, 0x3, P1 ?trans1;
IADD.64 R34, R16.reuse, R34 ?trans2;
IADD.64 R20, R16, R30 ?WAIT3_END_GROUP;
IADD3 R30, PT, PT, R30, UR4, RZ ?trans2;
SHF.R.S32.HI R33, RZ, 0x1f, R32 ?trans1;
LDG.E.64 R10, desc[UR10][R10.64] &wr=0x2 ?trans1;
LEA R14, P1, R22, UR8, 0x3 ?trans2;
LEA R28, P3, R20, UR8, 0x3 ?trans1;
IADD.64 R32, R16, R32 ?trans2;
LDG.E.64 R8, desc[UR12][R8.64] &wr=0x3 ?trans1;
LEA.HI.X R15, R22, UR9, R23, 0x3, P1 ?WAIT2_END_GROUP;
LEA.HI.X R29, R20, UR9, R21, 0x3, P3 ?trans2;
LEA R22, P1, R34, UR8, 0x3 ?trans2;
IADD3 R20, PT, PT, R30, UR4, RZ ?trans2;
SHF.R.S32.HI R31, RZ, 0x1f, R30 ?trans1;
LDG.E.64 R14, desc[UR14][R14.64] &wr=0x4 ?trans1;
LEA R26, P2, R32, UR8, 0x3 ?trans2;
LEA.HI.X R23, R34, UR9, R35, 0x3, P1 ?trans1;
IADD.64 R30, R16, R30 ?WAIT2_END_GROUP;
LDG.E.64 R28, desc[UR20][R28.64] &wr=0x5 ?trans1;
SHF.R.S32.HI R21, RZ, 0x1f, R20 ?trans2;
LEA.HI.X R27, R32, UR9, R33, 0x3, P2 ?trans1;
LDG.E.64 R22, desc[UR16][R22.64] &wr=0x5 ?trans1;
R2UR UR22, R18 ?trans1;
IADD.64 R32, R16, R20 ?WAIT3_END_GROUP;
R2UR UR23, R19.reuse ?trans1;
LDG.E.64 R26, desc[UR18][R26.64] &wr=0x5 ?trans1;
LEA R20, P1, R30, UR8, 0x3 ?trans2;
R2UR UR4, R18 ?trans2;
R2UR UR5, R19 ?trans2;
LEA.HI.X R21, R30, UR9, R31, 0x3, P1 ?trans2;
LEA R30, P1, R32, UR8, 0x3 ?WAIT4_END_GROUP;
LEA.HI.X R31, R32, UR9, R33, 0x3, P1 ?trans1;
LDG.E.64 R20, desc[UR22][R20.64] &wr=0x5 ?trans5;
LDG.E.64 R30, desc[UR4][R30.64] &wr=0x5 ?trans1;
IADD3 R13, PT, PT, R13, 0x8, RZ ?trans1;
IADD.64 R10, R24, R10 &req={2} ?WAIT4_END_GROUP;
IADD.64 R8, R10, R8 &req={3} ?WAIT4_END_GROUP;
IADD.64 R8, R8, R14 &req={4} ?WAIT4_END_GROUP;
IADD.64 R8, R8, R22 &req={5} ?WAIT4_END_GROUP;
IADD.64 R8, R8, R26 ?WAIT4_END_GROUP;
IADD.64 R8, R8, R28 ?WAIT4_END_GROUP;
IADD.64 R8, R8, R20 ?WAIT4_END_GROUP;
IADD.64 R24, R8, R30 ?WAIT8_END_GROUP;
@!P0 BRA 0x1850 ?trans5;
IADD3 R8, PT, PT, R7, -0x1, RZ ?trans2;
LOP3.LUT P0, R12, R2, 0x3, RZ, 0xc0, !PT ?WAIT3_END_GROUP;
ISETP.GE.U32.AND P1, PT, R8, 0x3, PT ?WAIT13_END_GROUP;
@!P1 BRA 0x1640 ?trans5;
LDCU UR4, c[0x0][0x394] &wr=0x0 ?trans1;
R2UR UR5, R19.reuse &req={1} ?trans2;
R2UR UR10, R18.reuse ?trans1;
LDCU.64 UR8, c[0x0][0x380] &wr=0x1 ?trans1;
R2UR UR11, R19.reuse ?trans2;
R2UR UR12, R18.reuse ?trans2;
R2UR UR13, R19 ?trans2;
R2UR UR14, R18 ?WAIT2_END_GROUP;
R2UR UR15, R19 ?trans1;
IMAD R8, R13, UR4, RZ &req={0} ?WAIT5_END_GROUP;
IADD3 R10, PT, PT, R8, UR4, RZ ?trans2;
SHF.R.S32.HI R9, RZ, 0x1f, R8 ?trans2;
SHF.R.S32.HI R11, RZ, 0x1f, R10 ?WAIT3_END_GROUP;
IADD.64 R8, R16, R8 ?WAIT3_END_GROUP;
IADD3 R26, PT, PT, R10, UR4, RZ ?trans1;
IADD.64 R22, R16, R10 ?WAIT3_END_GROUP;
IADD3 R10, PT, PT, R26, UR4, RZ ?trans2;
SHF.R.S32.HI R27, RZ, 0x1f, R26 ?trans2;
LEA R20, P2, R22, UR8, 0x3 &req={1} ?trans2;
R2UR UR4, R18 ?trans2;
LEA R14, P1, R8, UR8, 0x3 ?trans2;
LEA.HI.X R21, R22, UR9, R23, 0x3, P2 ?trans1;
IADD.64 R22, R16, R26 ?WAIT3_END_GROUP;
SHF.R.S32.HI R11, RZ, 0x1f, R10 ?trans2;
LEA.HI.X R15, R8, UR9, R9, 0x3, P1 ?trans1;
LDG.E.64 R20, desc[UR10][R20.64] &wr=0x2 ?trans1;
LEA R8, P1, R22, UR8, 0x3 ?trans1;
IADD.64 R10, R16, R10 ?WAIT3_END_GROUP;
LDG.E.64 R14, desc[UR4][R14.64] &wr=0x3 ?trans1;
LEA.HI.X R9, R22, UR9, R23, 0x3, P1 ?trans2;
LEA R22, P1, R10, UR8, 0x3 ?WAIT4_END_GROUP;
LEA.HI.X R23, R10, UR9, R11, 0x3, P1 ?trans1;
LDG.E.64 R8, desc[UR12][R8.64] &wr=0x4 ?trans5;
LDG.E.64 R22, desc[UR14][R22.64] &wr=0x5 ?trans1;
IADD3 R13, PT, PT, R13, 0x4, RZ ?trans1;
IADD.64 R24, R24, R14 &req={3} ?WAIT4_END_GROUP;
IADD.64 R24, R24, R20 &req={2} ?WAIT4_END_GROUP;
IADD.64 R24, R24, R8 &req={4} ?WAIT4_END_GROUP;
IADD.64 R24, R24, R22 &req={5} ?WAIT8_END_GROUP;
@!P0 BRA 0x1850 ?trans5;
LDC R15, c[0x0][0x394] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x380] &wr=0x2 ?trans1;
R2UR UR8, R18 &req={1} ?trans2;
R2UR UR9, R19 ?trans1;
IMAD R8, R13, R15, RZ &req={0} ?WAIT5_END_GROUP;
SHF.R.S32.HI R9, RZ, 0x1f, R8 ?WAIT5_END_GROUP;
IADD.64 R20, R16, R8 ?WAIT5_END_GROUP;
LEA R10, P0, R20, UR4, 0x3 &req={2} ?WAIT4_END_GROUP;
LEA.HI.X R11, R20, UR5, R21, 0x3, P0 ?WAIT6_END_GROUP;
LDG.E.64 R10, desc[UR8][R10.64] &wr=0x2 ?trans1;
ISETP.NE.AND P0, PT, R12, 0x1, PT ?trans1;
IADD.64 R24, R24, R10 &req={2} ?WAIT12_END_GROUP;
@!P0 BRA 0x1850 ?trans5;
ISETP.NE.AND P0, PT, R12, 0x2, PT ?trans1;
IADD3 R8, PT, PT, R8, R15, RZ ?trans2;
R2UR UR8, R18 ?trans2;
R2UR UR9, R19 ?trans2;
SHF.R.S32.HI R9, RZ, 0x1f, R8 ?WAIT6_END_GROUP;
@P0 IADD3 R10, PT, PT, R8, R15, RZ ?trans1;
IADD.64 R8, R16, R8 ?WAIT3_END_GROUP;
@P0 R2UR UR10, R18 ?trans2;
@P0 SHF.R.S32.HI R11, RZ, 0x1f, R10 ?trans2;
LEA R12, P1, R8, UR4, 0x3 ?trans2;
@P0 R2UR UR11, R19 ?trans1;
@P0 IADD.64 R10, R16, R10 ?WAIT3_END_GROUP;
LEA.HI.X R13, R8, UR5, R9, 0x3, P1 ?trans2;
@P0 LEA R14, P1, R10, UR4, 0x3 ?WAIT3_END_GROUP;
LDG.E.64 R8, desc[UR8][R12.64] &wr=0x2 ?trans1;
@P0 LEA.HI.X R15, R10, UR5, R11, 0x3, P1 ?WAIT5_END_GROUP;
@P0 LDG.E.64 R10, desc[UR10][R14.64] &wr=0x3 ?trans1;
IADD.64 R24, R24, R8 &req={2} ?WAIT4_END_GROUP;
@P0 IADD.64 R24, R24, R10 &req={3} ?WAIT8_END_GROUP;
LDCU.64 UR4, c[0x0][0x388] &wr=0x0 ?trans1;
SHF.R.S32.HI R9, RZ, 0x1f, R0 ?trans2;
R2UR UR8, R18 &req={1} ?trans2;
R2UR UR9, R19 ?trans2;
LEA R8, P0, R0.reuse, UR4, 0x3 &req={0} ?trans1;
LDCU UR4, c[0x0][0x394] &wr=0x0 ?trans3;
LEA.HI.X R9, R0, UR5, R9, 0x3, P0 ?WAIT2_END_GROUP;
IADD3 R0, PT, PT, R3, R0, RZ ?WAIT5_END_GROUP;
STG.E.64 desc[UR8][R8.64], R24 &rd=0x3 ?trans1;
ISETP.GE.AND P0, PT, R0, UR4, PT &req={0} ?WAIT13_END_GROUP;
@!P0 BRA 0x3b0 &req={3} ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
EXIT ?trans5;
BRA 0x1930;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: kernelSumHistogram(unsigned long long*, unsigned long long*, int, int, int)
_Z18kernelSumHistogramPyS_iii:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x10
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_mov_b32 s7, exec_lo
s_and_b32 s12, s8, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB0_6
s_ashr_i32 s8, s6, 31
s_ashr_i32 s13, s4, 31
s_add_i32 s9, s6, s8
s_add_i32 s14, s4, s13
s_xor_b32 s9, s9, s8
s_xor_b32 s14, s14, s13
v_cvt_f32_u32_e32 v0, s9
s_sub_i32 s11, 0, s9
s_xor_b32 s8, s13, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s10, v0
s_mul_i32 s11, s11, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s11, s10, s11
s_add_i32 s10, s10, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s10, s14, s10
s_mul_i32 s11, s10, s9
s_add_i32 s13, s10, 1
s_sub_i32 s11, s14, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s14, s11, s9
s_cmp_ge_u32 s11, s9
s_cselect_b32 s10, s13, s10
s_cselect_b32 s11, s14, s11
s_add_i32 s13, s10, 1
s_cmp_ge_u32 s11, s9
s_cselect_b32 s9, s13, s10
s_load_b32 s13, s[2:3], 0x0
s_xor_b32 s9, s9, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_sub_i32 s2, s9, s8
s_load_b128 s[8:11], s[0:1], 0x0
s_mul_i32 s3, s2, s6
s_sub_i32 s0, s4, s3
s_mov_b32 s4, 0
s_cmp_lg_u32 s0, 0
s_cselect_b32 s0, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s0, 0
s_addc_u32 s1, s2, 0
s_mov_b32 s2, s5
s_cmp_lg_u32 s1, 0
s_cselect_b32 s6, -1, 0
s_ashr_i32 s3, s5, 31
s_waitcnt lgkmcnt(0)
s_mul_i32 s12, s13, s12
s_lshl_b64 s[2:3], s[2:3], 3
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_and_not1_b32 vcc_lo, exec_lo, s6
s_delay_alu instid0(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 3, v[1:2]
s_cbranch_vccnz .LBB0_5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
s_mov_b32 s0, s1
.LBB0_4:
global_load_b64 v[8:9], v[6:7], off
v_add_co_u32 v6, vcc_lo, v6, s2
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_add_i32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s0, 0
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v8, v4
v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo
s_cbranch_scc0 .LBB0_4
.LBB0_5:
v_add_nc_u32_e32 v1, s12, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v2, s0, s10, v2
v_add_co_ci_u32_e64 v3, s0, s11, v3, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s5, v1
global_store_b64 v[2:3], v[4:5], off
s_or_b32 s4, vcc_lo, s4
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_2
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s7
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
| kernelSumHistogram | 9,763 | 1,798 | stackv2-00000-of-00015 |
// Demangled: matAdd(double*, double*)
Function : _Z6matAddPdS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R7, SR_TID.Y &wr=0x0 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x0 ?trans6;
LDC.64 R4, c[0x0][0x388] &wr=0x1 ?trans1;
S2R R0, SR_TID.X &wr=0x0 ?trans2;
IMAD R7, R7, UR4, R0 &req={0} ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans3;
IMAD.WIDE.U32 R4, R7.reuse, 0x8, R4 &req={1} ?trans1;
IADD3 R2, PT, PT, R7, 0x1, RZ ?WAIT6_END_GROUP;
I2F.F64.U32 R2, R2 &wr=0x0 ?trans2;
STG.E.64 desc[UR4][R4.64], R2 &req={0} ?trans1;
EXIT ?trans5;
BRA 0xc0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: matAdd(double*, double*)
_Z6matAddPdS_:
s_load_b32 s2, s[0:1], 0x1c
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u32_u24 v2, v0, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v0, 1, v2
v_lshlrev_b32_e32 v2, 3, v2
v_cvt_f64_i32_e32 v[0:1], v0
global_store_b64 v2, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| matAdd | 349 | 300 | stackv2-00000-of-00015 |
// Demangled: init_matrix(float*)
Function : _Z11init_matrixPf
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R0, SR_TID.Y &wr=0x0 ?trans1;
LDCU UR6, c[0x0][0x360] &wr=0x1 ?trans6;
S2UR UR7, SR_CTAID.X &wr=0x2 ?trans1;
S2R R7, SR_CTAID.Y &wr=0x0 ?trans1;
LDCU UR4, c[0x0][0x364] &wr=0x0 ?trans1;
S2R R5, SR_TID.X &wr=0x1 ?trans5;
LDC R9, c[0x0][0x370] &wr=0x2 ?trans8;
LDC.64 R2, c[0x0][0x380] &wr=0x3 ?trans1;
IMAD R0, R7, UR4, R0 &req={0} ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans3;
IMAD R0, R0, R9, UR7 &req={2} ?WAIT4_END_GROUP;
IMAD R5, R0, UR6, R5 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE R2, R5, 0x4, R2 &req={3} ?trans1;
I2FP.F32.S32 R5, R5 ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R5 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x110;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: init_matrix(float*)
_Z11init_matrixPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b32 s3, s[0:1], 0x8
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s3, s[14:15]
v_mad_u64_u32 v[1:2], null, v3, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_cvt_f32_i32_e32 v4, v1
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| init_matrix | 464 | 496 | stackv2-00000-of-00015 |
// Demangled: transpose(float const*, float*, int, int)
Function : _Z9transposePKfPfii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R5, SR_TID.X &wr=0x0 ?trans7;
LDC R0, c[0x0][0x360] &wr=0x0 ?trans1;
LDCU.64 UR8, c[0x0][0x390] &wr=0x1 ?trans1;
S2R R4, SR_TID.Y &wr=0x2 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x3 ?trans5;
S2UR UR6, SR_CTAID.X &wr=0x0 ?trans8;
S2UR UR7, SR_CTAID.Y &wr=0x2 ?trans8;
LDC R7, c[0x0][0x364] &wr=0x2 ?trans8;
LDC.64 R2, c[0x0][0x380] &wr=0x4 ?trans1;
IMAD R0, R0, UR6, R5 &req={0} ?WAIT2_END_GROUP;
IMAD R7, R7, UR7, R4 &req={2} ?WAIT4_END_GROUP;
IMAD R5, R0, UR9, R7 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE R2, R5, 0x4, R2 &req={4} ?trans2;
LDC.64 R4, c[0x0][0x388] &wr=0x0 ?trans4;
LDG.E R3, desc[UR4][R2.64] &req={3} &wr=0x2 ?trans1;
IMAD R7, R7, UR8, R0 ?WAIT4_END_GROUP;
IMAD.WIDE R4, R7, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64], R3 &req={2} ?trans1;
EXIT ?trans5;
BRA 0x140;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: transpose(float const*, float*, int, int)
_Z9transposePKfPfii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s14, s2, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s3, v[0:1]
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[0:1], null, v2, s5, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v4, v[0:1], off
v_mad_u64_u32 v[0:1], null, v3, s4, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| transpose | 552 | 701 | stackv2-00000-of-00015 |
// Demangled: convolutionColumnGPU(float*, float*, float*, int, int, int)
Function : _Z20convolutionColumnGPUPfS_S_iii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
LDC R4, c[0x0][0x3a0] &wr=0x1 ?trans1;
S2R R3, SR_TID.X &wr=0x2 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x3 ?trans1;
S2R R5, SR_TID.Y &wr=0x4 ?trans5;
S2UR UR6, SR_CTAID.X &wr=0x2 ?trans8;
LDC R0, c[0x0][0x360] &wr=0x2 ?trans8;
S2UR UR7, SR_CTAID.Y &wr=0x4 ?trans1;
ISETP.GE.AND P0, PT, R4, RZ, PT &req={1} ?WAIT7_END_GROUP;
LDC R2, c[0x0][0x364] &wr=0x4 ?trans1;
IMAD R0, R0, UR6, R3 &req={2} ?trans2;
IMAD R3, R2, UR7, R5 &req={4} ?trans2;
HFMA2 R2, -RZ, RZ, 0, 0 ?trans1;
@!P0 BRA 0xd90 &req={3,0} ?trans6;
ISETP.GE.U32.AND P0, PT, R4.reuse, 0x4, PT ?trans1;
IADD3 R8, PT, PT, -R4, RZ, RZ ?trans1;
MOV R2, RZ ?WAIT11_END_GROUP;
@!P0 BRA 0x7a0 ?trans5;
LDCU UR6, c[0x0][0x398] &wr=0x0 ?trans1;
LDC R7, c[0x0][0x398] &wr=0x1 ?trans1;
IADD3 R5, PT, PT, R3, -R4, RZ ?trans1;
IMAD.SHL.U32 R31, R4.reuse, 0x2, RZ ?trans1;
IADD3 R8, PT, PT, -R4, 0x3, RZ ?trans1;
MOV R2, RZ ?trans1;
LDCU UR7, c[0x0][0x39c] &wr=0x2 ?trans1;
IADD3 R9, PT, PT, R5.reuse, 0x7, RZ ?trans2;
IADD3 R11, PT, PT, R5.reuse, 0x6, RZ ?trans1;
LDC.64 R14, c[0x0][0x390] &wr=0x3 ?trans1;
IADD3 R13, PT, PT, R5, 0x5, RZ ?WAIT2_END_GROUP;
IADD3 R17, PT, PT, R5.reuse, 0x4, RZ ?trans2;
IADD3 R19, PT, PT, R5.reuse, 0x3, RZ ?trans2;
IADD3 R21, PT, PT, R5.reuse, 0x2, RZ ?trans2;
IADD3 R23, PT, PT, R5, 0x1, RZ ?trans2;
LOP3.LUT R32, R31, 0xfffffff8, RZ, 0xc0, !PT ?trans1;
IMAD R10, R9, UR6, R0.reuse &req={0} ?trans2;
IMAD R12, R11, UR6, R0.reuse ?trans1;
IADD3 R32, PT, PT, -R32, RZ, RZ ?trans1;
IMAD R9, R13, UR6, R0 ?WAIT2_END_GROUP;
IMAD R4, R5, UR6, R0.reuse ?trans2;
IMAD R11, R17, UR6, R0.reuse ?trans2;
IMAD R13, R19, UR6, R0.reuse ?trans2;
IMAD R30, R21, UR6, R0.reuse ?trans2;
IMAD R6, R23, UR6, R0 &req={2} ?WAIT7_END_GROUP;
ISETP.GE.AND P0, PT, R5, UR7, PT ?trans1;
IMAD.WIDE R16, R31, 0x4, R14 &req={3} ?WAIT4_END_GROUP;
ISETP.LT.OR P0, PT, R5, RZ, P0 ?WAIT13_END_GROUP;
@!P0 LDC.64 R18, c[0x0][0x388] &wr=0x0 ?trans1;
@!P0 LDG.E R22, desc[UR4][R16.64] &wr=0x2 ?trans1;
@!P0 IMAD.WIDE R18, R4, 0x4, R18 &req={0} ?WAIT5_END_GROUP;
@!P0 LDG.E R23, desc[UR4][R18.64] &rd=0x0 &wr=0x2 ?trans1;
IADD3 R20, PT, PT, R5.reuse, 0x1, RZ ?trans2;
IADD3 R21, PT, PT, R5.reuse, 0x2, RZ ?trans2;
IADD3 R24, PT, PT, R5, 0x3, RZ ?trans1;
ISETP.GE.AND P1, PT, R20, UR7, PT ?trans2;
ISETP.GE.AND P2, PT, R21, UR7, PT ?trans2;
ISETP.GE.AND P3, PT, R24, UR7, PT ?trans1;
ISETP.LT.OR P1, PT, R20, RZ, P1 ?trans1;
IADD3 R20, PT, PT, R5, 0x4, RZ ?trans1;
ISETP.LT.OR P2, PT, R21, RZ, P2 ?trans1;
IADD3 R21, PT, PT, R5, 0x5, RZ ?trans1;
ISETP.LT.OR P3, PT, R24, RZ, P3 ?WAIT2_END_GROUP;
ISETP.GE.AND P4, PT, R20.reuse, UR7, PT ?trans1;
IADD3 R24, PT, PT, R5, 0x6, RZ ?trans1;
ISETP.GE.AND P5, PT, R21, UR7, PT ?trans1;
IADD3 R26, PT, PT, R5, 0x7, RZ ?trans2;
ISETP.LT.OR P4, PT, R20, RZ, P4 ?trans2;
@!P1 LDC.64 R28, c[0x0][0x388] &wr=0x3 ?trans1;
ISETP.GE.AND P6, PT, R24.reuse, UR7, PT ?trans1;
ISETP.LT.OR P5, PT, R21, RZ, P5 ?trans1;
@!P1 LDG.E R33, desc[UR4][R16.64+-0x4] &wr=0x4 ?trans4;
@!P2 LDG.E R36, desc[UR4][R16.64+-0x8] &wr=0x5 ?trans1;
@!P2 LDC.64 R18, c[0x0][0x388] &req={0} &wr=0x0 ?trans1;
ISETP.LT.OR P6, PT, R24, RZ, P6 ?WAIT7_END_GROUP;
@!P3 LDC.64 R20, c[0x0][0x388] &wr=0x1 ?trans6;
@!P6 LDG.E R37, desc[UR4][R16.64+-0x18] &wr=0x4 ?trans2;
@!P5 LDC.64 R24, c[0x0][0x388] &wr=0x1 ?trans1;
@!P1 IMAD.WIDE R28, R6, 0x4, R28 &req={3} ?WAIT6_END_GROUP;
@!P1 LDG.E R29, desc[UR4][R28.64] &wr=0x4 ?trans1;
@!P2 IMAD.WIDE R18, R30, 0x4, R18 &req={0} ?WAIT6_END_GROUP;
@!P2 LDG.E R19, desc[UR4][R18.64] &wr=0x5 ?trans1;
@!P3 IMAD.WIDE R20, R13, 0x4, R20 &req={1} ?WAIT3_END_GROUP;
@!P3 LDG.E R28, desc[UR4][R16.64+-0xc] &wr=0x3 ?trans4;
@!P3 LDG.E R21, desc[UR4][R20.64] &wr=0x3 ?trans1;
@!P5 IMAD.WIDE R24, R9, 0x4, R24 ?WAIT3_END_GROUP;
@!P5 LDG.E R18, desc[UR4][R16.64+-0x14] &wr=0x3 ?trans4;
@!P5 LDG.E R25, desc[UR4][R24.64] &wr=0x3 ?trans4;
@!P4 LDG.E R20, desc[UR4][R16.64+-0x10] &wr=0x3 ?trans1;
@!P0 FFMA R2, R23, R22, R2 &req={2} ?trans1;
ISETP.GE.AND P0, PT, R26.reuse, UR7, PT ?trans1;
@!P4 LDC.64 R22, c[0x0][0x388] &wr=0x0 ?trans4;
ISETP.LT.OR P0, PT, R26, RZ, P0 ?WAIT4_END_GROUP;
@!P6 LDC.64 R26, c[0x0][0x388] &wr=0x1 ?trans9;
@!P0 LDC.64 R34, c[0x0][0x388] &wr=0x2 ?trans1;
@!P4 IMAD.WIDE R22, R11, 0x4, R22 &req={0} ?WAIT6_END_GROUP;
@!P4 LDG.E R23, desc[UR4][R22.64] &wr=0x3 ?trans1;
@!P6 IMAD.WIDE R26, R12, 0x4, R26 &req={1} ?WAIT6_END_GROUP;
@!P6 LDG.E R27, desc[UR4][R26.64] &wr=0x3 ?trans1;
@!P0 IMAD.WIDE R34, R10, 0x4, R34 &req={2} ?WAIT3_END_GROUP;
@!P0 LDG.E R22, desc[UR4][R16.64+-0x1c] &wr=0x2 ?trans4;
@!P0 LDG.E R35, desc[UR4][R34.64] &wr=0x2 ?trans1;
@!P1 FFMA R2, R29, R33, R2 &req={4} ?WAIT4_END_GROUP;
@!P2 FFMA R2, R19, R36, R2 &req={5} ?WAIT4_END_GROUP;
@!P3 FFMA R2, R21, R28, R2 &req={3} ?trans1;
IADD3 R32, PT, PT, R32, 0x8, RZ ?trans2;
IADD3 R8, PT, PT, R8, 0x8, RZ ?trans2;
IADD3 R31, PT, PT, R31, -0x8, RZ ?trans2;
IADD3 R5, PT, PT, R5, 0x8, RZ ?trans1;
IMAD R4, R7.reuse, 0x8, R4 ?trans2;
IMAD R6, R7, 0x8, R6 ?WAIT2_END_GROUP;
IMAD R30, R7.reuse, 0x8, R30 ?trans2;
IMAD R13, R7.reuse, 0x8, R13 ?trans2;
IMAD R11, R7.reuse, 0x8, R11 ?trans2;
IMAD R9, R7.reuse, 0x8, R9 ?trans2;
IMAD R12, R7.reuse, 0x8, R12 ?trans2;
IMAD R10, R7, 0x8, R10 ?WAIT2_END_GROUP;
@!P4 FFMA R2, R23, R20, R2 ?WAIT4_END_GROUP;
@!P5 FFMA R2, R25, R18, R2 ?WAIT4_END_GROUP;
@!P6 FFMA R2, R27, R37, R2 ?WAIT4_END_GROUP;
@!P0 FFMA R2, R35, R22, R2 &req={2} ?trans1;
ISETP.NE.AND P0, PT, R32, RZ, PT ?WAIT13_END_GROUP;
@P0 BRA 0x2b0 ?trans5;
IADD3 R8, PT, PT, R8, -0x3, RZ ?WAIT7_END_GROUP;
LDC R4, c[0x0][0x3a0] &wr=0x0 ?trans1;
LDCU UR7, c[0x0][0x39c] &wr=0x1 ?trans1;
IADD3 R5, PT, PT, R4.reuse, R4, RZ &req={0} ?trans2;
LOP3.LUT R6, R4, 0x1, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R5, R5, 0x6, RZ, 0xc0, !PT ?WAIT3_END_GROUP;
ISETP.NE.U32.AND P3, PT, R6, 0x1, PT ?trans2;
ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ?WAIT13_END_GROUP;
@!P0 BRA 0xaf0 &req={1} ?trans5;
LDCU UR6, c[0x0][0x39c] &wr=0x0 ?trans1;
IADD3 R21, PT, PT, R3, R8, RZ ?trans1;
LDC.64 R12, c[0x0][0x390] &wr=0x1 ?trans1;
IADD3 R19, PT, PT, -R8, R4, RZ ?trans2;
IADD3 R23, PT, PT, R21.reuse, 0x1, RZ ?trans2;
IADD3 R25, PT, PT, R21.reuse, 0x2, RZ ?trans2;
IADD3 R5, PT, PT, R21.reuse, 0x3, RZ ?trans1;
ISETP.GE.AND P0, PT, R21, UR6, PT &req={0} ?trans1;
ISETP.GE.AND P1, PT, R23, UR6, PT ?trans1;
ISETP.GE.AND P2, PT, R25, UR6, PT ?WAIT2_END_GROUP;
ISETP.GE.AND P4, PT, R5, UR6, PT ?trans1;
ISETP.LT.OR P0, PT, R21, RZ, P0 ?trans1;
ISETP.LT.OR P1, PT, R23, RZ, P1 ?trans1;
ISETP.LT.OR P2, PT, R25, RZ, P2 ?trans2;
ISETP.LT.OR P4, PT, R5, RZ, P4 ?trans1;
IMAD.WIDE R12, R19, 0x4, R12 &req={1} ?WAIT8_END_GROUP;
@!P0 LDC R18, c[0x0][0x398] &wr=0x0 ?trans8;
@!P1 LDC R20, c[0x0][0x398] &wr=0x1 ?trans8;
@!P0 LDC.64 R16, c[0x0][0x388] &wr=0x2 ?trans8;
@!P1 LDC.64 R14, c[0x0][0x388] &wr=0x3 ?trans1;
@!P0 IMAD R21, R21, R18, R0 &req={0} ?WAIT2_END_GROUP;
@!P0 LDG.E R18, desc[UR4][R12.64] &wr=0x4 ?trans5;
@!P2 LDC R22, c[0x0][0x398] &wr=0x0 ?trans1;
@!P1 IMAD R23, R23, R20, R0 &req={1} ?WAIT7_END_GROUP;
@!P2 LDC.64 R10, c[0x0][0x388] &wr=0x1 ?trans1;
@!P0 IMAD.WIDE R16, R21, 0x4, R16 &req={2} ?WAIT6_END_GROUP;
@!P0 LDG.E R17, desc[UR4][R16.64] &wr=0x4 ?trans1;
@!P4 LDC R9, c[0x0][0x398] &wr=0x2 ?trans1;
@!P1 IMAD.WIDE R14, R23, 0x4, R14 &req={3} ?WAIT6_END_GROUP;
@!P1 LDG.E R15, desc[UR4][R14.64] &wr=0x3 ?trans1;
@!P4 LDC.64 R6, c[0x0][0x388] &wr=0x5 ?trans1;
@!P2 IMAD R19, R25, R22, R0 &req={0} ?WAIT4_END_GROUP;
@!P2 IMAD.WIDE R10, R19, 0x4, R10 &req={1} ?trans2;
@!P4 LDG.E R19, desc[UR4][R12.64+-0xc] &wr=0x3 ?trans4;
@!P2 LDG.E R11, desc[UR4][R10.64] &wr=0x3 ?trans1;
@!P4 IMAD R9, R5, R9, R0 &req={2} ?WAIT3_END_GROUP;
@!P1 LDG.E R5, desc[UR4][R12.64+-0x4] &wr=0x3 ?trans1;
@!P4 IMAD.WIDE R6, R9, 0x4, R6 &req={5} ?WAIT3_END_GROUP;
@!P2 LDG.E R9, desc[UR4][R12.64+-0x8] &wr=0x2 ?trans4;
@!P4 LDG.E R7, desc[UR4][R6.64] &wr=0x5 ?trans1;
IADD3 R8, PT, PT, R8, 0x4, RZ ?trans1;
@!P0 FFMA R2, R17, R18, R2 &req={4} ?WAIT4_END_GROUP;
@!P1 FFMA R2, R15, R5, R2 &req={3} ?WAIT4_END_GROUP;
@!P2 FFMA R2, R11, R9, R2 &req={2} ?WAIT4_END_GROUP;
@!P4 FFMA R2, R7, R19, R2 &req={5} ?WAIT7_END_GROUP;
@P3 BRA 0xc90 ?trans5;
LDCU UR6, c[0x0][0x39c] &wr=0x0 ?trans1;
IADD3 R5, PT, PT, R3, R8, RZ ?trans1;
LDC.64 R6, c[0x0][0x390] &wr=0x1 ?trans1;
IADD3 R13, PT, PT, -R8, R4, RZ ?trans2;
IADD3 R9, PT, PT, R5.reuse, 0x1, RZ ?trans1;
ISETP.GE.AND P0, PT, R5, UR6, PT &req={0} ?WAIT4_END_GROUP;
ISETP.GE.AND P1, PT, R9, UR6, PT ?trans1;
ISETP.LT.OR P0, PT, R5, RZ, P0 ?WAIT4_END_GROUP;
ISETP.LT.OR P1, PT, R9, RZ, P1 ?WAIT9_END_GROUP;
@!P0 LDC R12, c[0x0][0x398] &wr=0x0 ?trans8;
@!P0 LDC.64 R10, c[0x0][0x388] &wr=0x2 ?trans8;
@!P1 LDC R16, c[0x0][0x398] &wr=0x3 ?trans8;
@!P1 LDC.64 R14, c[0x0][0x388] &wr=0x4 ?trans1;
@!P0 IMAD R5, R5, R12, R0 &req={0} ?WAIT2_END_GROUP;
IMAD.WIDE R12, R13, 0x4, R6 &req={1} ?WAIT4_END_GROUP;
@!P0 IMAD.WIDE R6, R5, 0x4, R10 &req={2} ?trans2;
@!P0 LDG.E R5, desc[UR4][R12.64] &wr=0x2 ?trans4;
@!P0 LDG.E R7, desc[UR4][R6.64] &wr=0x2 ?trans1;
@!P1 IMAD R11, R9, R16, R0 &req={3} ?WAIT3_END_GROUP;
@!P1 LDG.E R9, desc[UR4][R12.64+-0x4] &wr=0x3 ?trans1;
@!P1 IMAD.WIDE R10, R11, 0x4, R14 &req={4} ?WAIT6_END_GROUP;
@!P1 LDG.E R11, desc[UR4][R10.64] &wr=0x3 ?trans1;
IADD3 R8, PT, PT, R8, 0x2, RZ ?trans1;
@!P0 FFMA R2, R7, R5, R2 &req={2} ?WAIT4_END_GROUP;
@!P1 FFMA R2, R11, R9, R2 &req={3} ?WAIT7_END_GROUP;
IADD3 R5, PT, PT, R3, R8, RZ ?trans1;
BSSY.RECONVERGENT B0, 0xd90 ?trans4;
ISETP.GE.AND P0, PT, R5, UR7, PT ?WAIT5_END_GROUP;
ISETP.LT.OR P0, PT, R5, RZ, P0 ?WAIT13_END_GROUP;
@P0 BRA 0xd80 ?trans5;
LDC.64 R6, c[0x0][0x390] &wr=0x0 ?trans1;
LDCU UR6, c[0x0][0x398] &wr=0x1 ?trans1;
IADD3 R9, PT, PT, -R8, R4, RZ ?WAIT6_END_GROUP;
LDC.64 R10, c[0x0][0x388] &wr=0x2 ?trans1;
IMAD R5, R5, UR6, R0 &req={1} ?trans2;
IMAD.WIDE R6, R9, 0x4, R6 &req={0} ?WAIT6_END_GROUP;
LDG.E R6, desc[UR4][R6.64] &wr=0x3 ?trans1;
IMAD.WIDE R4, R5, 0x4, R10 &req={2} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR4][R4.64] &wr=0x3 ?trans2;
FFMA R2, R5, R6, R2 &req={3} ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
LDC.64 R4, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU UR6, c[0x0][0x398] &wr=0x1 ?trans2;
IMAD R3, R3, UR6, R0 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE R4, R3, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64], R2 ?trans1;
EXIT ?trans5;
BRA 0xdf0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: convolutionColumnGPU(float*, float*, float*, int, int, int)
_Z20convolutionColumnGPUPfS_S_iii:
s_clause 0x3
s_load_b32 s12, s[0:1], 0x34
s_load_b128 s[8:11], s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s0, s12, 16
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s0, v[3:4]
v_mov_b32_e32 v4, 0
s_and_b32 s0, s12, 0xffff
s_cmp_lt_i32 s10, 0
s_mul_i32 s14, s14, s0
s_cbranch_scc1 .LBB1_5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s10, v1
v_mov_b32_e32 v4, 0
s_lshl_b32 s10, s10, 1
v_mul_lo_u32 v2, s8, v5
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v2, v0, v2, s14
.LBB1_2:
v_cmp_lt_i32_e32 vcc_lo, -1, v5
v_cmp_gt_i32_e64 s0, s9, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s1, vcc_lo, s0
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB1_4
v_ashrrev_i32_e32 v3, 31, v2
s_ashr_i32 s11, s10, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[12:13], s[10:11], 2
s_add_u32 s12, s2, s12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[2:3]
s_addc_u32 s13, s3, s13
s_load_b32 s1, s[12:13], 0x0
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v3, v[6:7], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v4, s1, v3
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v5, 1, v5
v_add_nc_u32_e32 v2, s8, v2
s_add_i32 s10, s10, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s10, -1
s_cbranch_scc1 .LBB1_2
.LBB1_5:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v1, s8
v_add3_u32 v0, s14, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| convolutionColumnGPU | 6,203 | 1,263 | stackv2-00000-of-00015 |
// Demangled: convolutionRowGPU(float*, float*, float*, int, int, int)
Function : _Z17convolutionRowGPUPfS_S_iii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
LDC R11, c[0x0][0x3a0] &wr=0x1 ?trans1;
S2R R3, SR_TID.X &wr=0x2 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x3 ?trans1;
S2R R5, SR_TID.Y &wr=0x4 ?trans5;
S2UR UR6, SR_CTAID.X &wr=0x2 ?trans8;
LDC R2, c[0x0][0x360] &wr=0x2 ?trans8;
S2UR UR7, SR_CTAID.Y &wr=0x4 ?trans1;
ISETP.GE.AND P0, PT, R11, RZ, PT &req={1} ?WAIT7_END_GROUP;
LDC R0, c[0x0][0x364] &wr=0x4 ?trans1;
IMAD R2, R2, UR6, R3 &req={2} ?trans2;
IMAD R3, R0, UR7, R5 &req={4} ?trans2;
HFMA2 R0, -RZ, RZ, 0, 0 ?trans1;
@!P0 BRA 0xa30 &req={3,0} ?trans6;
ISETP.GE.U32.AND P0, PT, R11.reuse, 0x4, PT ?trans1;
IADD3 R5, PT, PT, -R11, RZ, RZ ?trans1;
MOV R0, RZ ?WAIT11_END_GROUP;
@!P0 BRA 0x570 ?trans5;
LDCU UR6, c[0x0][0x398] &wr=0x0 ?trans1;
IMAD.SHL.U32 R9, R11.reuse, 0x2, RZ ?trans1;
IADD3 R8, PT, PT, -R11, 0x3, RZ ?trans1;
MOV R0, RZ ?trans1;
LDCU UR7, c[0x0][0x398] &wr=0x1 ?trans2;
LOP3.LUT R12, R9, 0xfffffff8, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R12, PT, PT, -R12, RZ, RZ ?trans1;
IMAD R10, R3, UR6, R2 &req={0} ?WAIT5_END_GROUP;
IADD3 R10, PT, PT, R10, -R11.reuse, RZ ?trans2;
IADD3 R11, PT, PT, R2, -R11, RZ &req={1} ?WAIT7_END_GROUP;
LDC.64 R4, c[0x0][0x388] &wr=0x0 ?trans1;
ISETP.GE.AND P6, PT, R11, UR7, PT ?WAIT5_END_GROUP;
ISETP.LT.OR P6, PT, R11, RZ, P6 ?trans2;
LDC.64 R6, c[0x0][0x390] &wr=0x1 ?trans1;
IMAD.WIDE R4, R10, 0x4, R4 &req={0} ?WAIT10_END_GROUP;
@!P6 LDG.E R13, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE R6, R9, 0x4, R6 &req={1} ?WAIT5_END_GROUP;
@!P6 LDG.E R14, desc[UR4][R6.64] &wr=0x2 ?trans1;
IADD3 R15, PT, PT, R11.reuse, 0x1, RZ ?trans2;
IADD3 R16, PT, PT, R11.reuse, 0x2, RZ ?trans2;
IADD3 R17, PT, PT, R11, 0x3, RZ ?trans1;
ISETP.GE.AND P0, PT, R15, UR7, PT ?trans2;
ISETP.GE.AND P1, PT, R16.reuse, UR7, PT ?trans1;
IADD3 R18, PT, PT, R11, 0x4, RZ ?trans2;
ISETP.LT.OR P0, PT, R15, RZ, P0 ?trans1;
IADD3 R15, PT, PT, R11, 0x5, RZ ?trans1;
ISETP.GE.AND P2, PT, R17, UR7, PT ?trans1;
ISETP.LT.OR P1, PT, R16, RZ, P1 ?trans1;
ISETP.GE.AND P3, PT, R18, UR7, PT ?WAIT2_END_GROUP;
ISETP.GE.AND P4, PT, R15, UR7, PT ?trans1;
ISETP.LT.OR P2, PT, R17, RZ, P2 ?trans1;
IADD3 R17, PT, PT, R11, 0x6, RZ ?trans1;
ISETP.LT.OR P3, PT, R18, RZ, P3 ?trans2;
ISETP.LT.OR P4, PT, R15, RZ, P4 ?trans1;
IADD3 R19, PT, PT, R11, 0x7, RZ ?trans1;
@!P0 LDG.E R15, desc[UR4][R4.64+0x4] &wr=0x3 ?trans1;
ISETP.GE.AND P5, PT, R17, UR7, PT ?WAIT3_END_GROUP;
@!P0 LDG.E R16, desc[UR4][R6.64+-0x4] &wr=0x3 ?trans2;
ISETP.LT.OR P5, PT, R17, RZ, P5 ?trans2;
@!P2 LDG.E R17, desc[UR4][R4.64+0xc] &wr=0x4 ?trans4;
@!P2 LDG.E R18, desc[UR4][R6.64+-0xc] &wr=0x4 ?trans4;
@!P3 LDG.E R20, desc[UR4][R6.64+-0x10] &wr=0x5 ?trans4;
@!P4 LDG.E R21, desc[UR4][R4.64+0x14] &wr=0x4 ?trans4;
@!P4 LDG.E R22, desc[UR4][R6.64+-0x14] &wr=0x4 ?trans4;
@!P5 LDG.E R23, desc[UR4][R4.64+0x18] &wr=0x4 ?trans4;
@!P5 LDG.E R24, desc[UR4][R6.64+-0x18] &wr=0x4 ?trans1;
@!P6 FFMA R0, R13, R14, R0 &req={2} ?WAIT3_END_GROUP;
@!P1 LDG.E R13, desc[UR4][R4.64+0x8] &wr=0x2 ?trans1;
ISETP.GE.AND P6, PT, R19, UR7, PT ?WAIT3_END_GROUP;
@!P1 LDG.E R14, desc[UR4][R6.64+-0x8] &wr=0x2 ?trans2;
ISETP.LT.OR P6, PT, R19, RZ, P6 ?trans2;
@!P3 LDG.E R19, desc[UR4][R4.64+0x10] &wr=0x5 ?trans11;
@!P6 LDG.E R25, desc[UR4][R4.64+0x1c] &wr=0x5 ?trans4;
@!P6 LDG.E R26, desc[UR4][R6.64+-0x1c] &wr=0x5 ?trans1;
@!P0 FFMA R0, R15, R16, R0 &req={3} ?trans1;
IADD3 R12, PT, PT, R12, 0x8, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R12, RZ, PT ?trans1;
IADD3 R8, PT, PT, R8, 0x8, RZ ?trans2;
IADD3 R11, PT, PT, R11, 0x8, RZ ?trans2;
IADD3 R10, PT, PT, R10, 0x8, RZ ?trans2;
IADD3 R9, PT, PT, R9, -0x8, RZ ?trans1;
@!P1 FFMA R0, R13, R14, R0 &req={2} ?WAIT4_END_GROUP;
@!P2 FFMA R0, R17, R18, R0 &req={4} ?WAIT4_END_GROUP;
@!P3 FFMA R0, R19, R20, R0 &req={5} ?WAIT4_END_GROUP;
@!P4 FFMA R0, R21, R22, R0 ?WAIT4_END_GROUP;
@!P5 FFMA R0, R23, R24, R0 ?WAIT4_END_GROUP;
@!P6 FFMA R0, R25, R26, R0 ?trans1;
@P0 BRA 0x1c0 ?trans6;
IADD3 R5, PT, PT, R8, -0x3, RZ ?WAIT7_END_GROUP;
LDC R4, c[0x0][0x3a0] &wr=0x0 ?trans1;
LDCU UR7, c[0x0][0x398] &wr=0x1 ?trans1;
IADD3 R6, PT, PT, R4.reuse, R4, RZ &req={0} ?trans2;
LOP3.LUT R7, R4, 0x1, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R6, R6, 0x6, RZ, 0xc0, !PT ?WAIT3_END_GROUP;
ISETP.NE.U32.AND P3, PT, R7, 0x1, PT ?trans2;
ISETP.GE.U32.AND P0, PT, R6, 0x3, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x7f0 &req={1} ?trans5;
LDCU UR6, c[0x0][0x398] &wr=0x0 ?trans1;
LDC.64 R6, c[0x0][0x388] &wr=0x1 ?trans1;
IADD3 R10, PT, PT, R2, R5, RZ ?trans2;
IADD3 R13, PT, PT, -R5, R4, RZ ?trans2;
IADD3 R11, PT, PT, R10.reuse, 0x1, RZ ?trans2;
IADD3 R12, PT, PT, R10.reuse, 0x2, RZ ?trans1;
LDC.64 R8, c[0x0][0x390] &wr=0x2 ?trans1;
IADD3 R14, PT, PT, R10.reuse, 0x3, RZ ?trans1;
ISETP.GE.AND P1, PT, R10, UR6, PT &req={0} ?trans1;
ISETP.GE.AND P0, PT, R11, UR6, PT ?trans1;
ISETP.GE.AND P2, PT, R12, UR6, PT ?WAIT2_END_GROUP;
ISETP.GE.AND P4, PT, R14, UR6, PT ?trans1;
ISETP.LT.OR P1, PT, R10, RZ, P1 ?trans1;
ISETP.LT.OR P0, PT, R11, RZ, P0 ?trans1;
IMAD R11, R3, UR6, R10 ?trans1;
ISETP.LT.OR P2, PT, R12, RZ, P2 ?trans1;
ISETP.LT.OR P4, PT, R14, RZ, P4 ?trans2;
IMAD.WIDE R6, R11, 0x4, R6 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE R8, R13, 0x4, R8 &req={2} ?WAIT3_END_GROUP;
@!P1 LDG.E R11, desc[UR4][R6.64] &wr=0x2 ?trans4;
@!P1 LDG.E R10, desc[UR4][R8.64] &wr=0x2 ?trans4;
@!P0 LDG.E R13, desc[UR4][R6.64+0x4] &wr=0x3 ?trans4;
@!P0 LDG.E R12, desc[UR4][R8.64+-0x4] &wr=0x3 ?trans4;
@!P2 LDG.E R15, desc[UR4][R6.64+0x8] &wr=0x4 ?trans4;
@!P2 LDG.E R14, desc[UR4][R8.64+-0x8] &wr=0x4 ?trans4;
@!P4 LDG.E R17, desc[UR4][R6.64+0xc] &wr=0x5 ?trans4;
@!P4 LDG.E R16, desc[UR4][R8.64+-0xc] &wr=0x5 ?trans1;
IADD3 R5, PT, PT, R5, 0x4, RZ ?trans1;
@!P1 FFMA R0, R11, R10, R0 &req={2} ?WAIT4_END_GROUP;
@!P0 FFMA R0, R13, R12, R0 &req={3} ?WAIT4_END_GROUP;
@!P2 FFMA R0, R15, R14, R0 &req={4} ?WAIT4_END_GROUP;
@!P4 FFMA R0, R17, R16, R0 &req={5} ?WAIT7_END_GROUP;
@P3 BRA 0x940 ?trans5;
LDCU UR6, c[0x0][0x398] &wr=0x0 ?trans1;
LDC.64 R6, c[0x0][0x388] &wr=0x1 ?trans1;
IADD3 R10, PT, PT, R2, R5, RZ ?trans2;
IADD3 R13, PT, PT, -R5, R4, RZ ?trans2;
IADD3 R11, PT, PT, R10, 0x1, RZ ?WAIT3_END_GROUP;
LDC.64 R8, c[0x0][0x390] &wr=0x2 ?trans1;
ISETP.GE.AND P0, PT, R10, UR6, PT &req={0} ?trans1;
ISETP.GE.AND P1, PT, R11, UR6, PT ?WAIT4_END_GROUP;
ISETP.LT.OR P0, PT, R10, RZ, P0 ?trans1;
ISETP.LT.OR P1, PT, R11, RZ, P1 ?trans1;
IMAD R11, R3, UR6, R10 ?WAIT4_END_GROUP;
IMAD.WIDE R6, R11, 0x4, R6 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE R8, R13, 0x4, R8 &req={2} ?WAIT3_END_GROUP;
@!P0 LDG.E R11, desc[UR4][R6.64] &wr=0x2 ?trans4;
@!P0 LDG.E R10, desc[UR4][R8.64] &wr=0x2 ?trans4;
@!P1 LDG.E R13, desc[UR4][R6.64+0x4] &wr=0x3 ?trans4;
@!P1 LDG.E R12, desc[UR4][R8.64+-0x4] &wr=0x3 ?trans1;
IADD3 R5, PT, PT, R5, 0x2, RZ ?trans1;
@!P0 FFMA R0, R11, R10, R0 &req={2} ?WAIT4_END_GROUP;
@!P1 FFMA R0, R13, R12, R0 &req={3} ?WAIT7_END_GROUP;
IADD3 R10, PT, PT, R2, R5, RZ ?trans1;
BSSY.RECONVERGENT B0, 0xa30 ?trans4;
ISETP.GE.AND P0, PT, R10, UR7, PT ?WAIT5_END_GROUP;
ISETP.LT.OR P0, PT, R10, RZ, P0 ?WAIT13_END_GROUP;
@P0 BRA 0xa20 ?trans5;
LDC.64 R6, c[0x0][0x388] &wr=0x0 ?trans1;
IADD3 R11, PT, PT, -R5, R4, RZ ?trans1;
IMAD R5, R3, UR7, R10 ?WAIT6_END_GROUP;
LDC.64 R8, c[0x0][0x390] &wr=0x1 ?trans1;
IMAD.WIDE R4, R5, 0x4, R6 &req={0} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE R6, R11, 0x4, R8 &req={1} ?WAIT6_END_GROUP;
LDG.E R6, desc[UR4][R6.64] &wr=0x2 ?trans2;
FFMA R0, R5, R6, R0 &req={2} ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
LDC.64 R4, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU UR6, c[0x0][0x398] &wr=0x1 ?trans2;
IMAD R3, R3, UR6, R2 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE R2, R3, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R0 ?trans1;
EXIT ?trans5;
BRA 0xa90;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: convolutionRowGPU(float*, float*, float*, int, int, int)
_Z17convolutionRowGPUPfS_S_iii:
s_clause 0x2
s_load_b32 s9, s[0:1], 0x34
s_load_b32 s10, s[0:1], 0x18
s_load_b32 s8, s[0:1], 0x20
v_bfe_u32 v1, v0, 10, 10
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s0, s9, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s0, v[1:2]
v_and_b32_e32 v3, 0x3ff, v0
s_and_b32 s0, s9, 0xffff
s_cmp_gt_i32 s8, -1
v_mad_u64_u32 v[0:1], null, s14, s0, v[3:4]
s_delay_alu instid0(VALU_DEP_3)
v_mul_lo_u32 v1, v2, s10
s_cbranch_scc0 .LBB0_6
v_mul_lo_u32 v3, v2, s10
s_delay_alu instid0(VALU_DEP_3)
v_subrev_nc_u32_e32 v4, s8, v0
v_mov_b32_e32 v2, 0
s_lshl_b32 s8, s8, 1
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v4
v_cmp_gt_i32_e64 s0, s10, v4
s_and_b32 s1, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_4
v_add_nc_u32_e32 v5, v3, v4
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[12:13], s[8:9], 2
s_add_u32 s12, s2, s12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
s_addc_u32 s13, s3, s13
s_load_b32 s1, s[12:13], 0x0
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v2, s1, v5
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v4, 1, v4
s_add_i32 s8, s8, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s8, -1
s_cbranch_scc1 .LBB0_2
s_mov_b32 s0, 0
s_branch .LBB0_7
.LBB0_6:
s_mov_b32 s0, -1
.LBB0_7:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_9
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, v1
.LBB0_9:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v3, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| convolutionRowGPU | 4,630 | 1,385 | stackv2-00000-of-00015 |
// Demangled: Jacobi(float*, float*, float*, int)
Function : _Z6JacobiPfS_S_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.Y &wr=0x1 ?trans7;
LDC R2, c[0x0][0x360] &wr=0x2 ?trans1;
LDCU UR4, c[0x0][0x398] &wr=0x3 ?trans1;
S2R R5, SR_TID.X &wr=0x2 ?trans6;
S2UR UR6, SR_CTAID.Y &wr=0x1 ?trans8;
LDC R3, c[0x0][0x364] &wr=0x1 ?trans8;
S2UR UR5, SR_CTAID.X &wr=0x2 ?trans1;
IMAD R3, R3, UR6, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R3, RZ, PT ?trans1;
IMAD R2, R2, UR5, R5 &req={2} ?trans1;
UIADD3 UR5, UPT, UPT, UR4, 0x2, URZ &req={3} ?WAIT4_END_GROUP;
ISETP.LT.OR P0, PT, R2, 0x1, !P0 ?WAIT5_END_GROUP;
ISETP.GT.OR P0, PT, R2, UR4, P0 ?trans1;
IMAD R2, R3, UR5, R2 ?WAIT4_END_GROUP;
ISETP.GT.OR P0, PT, R3, UR4, P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDCU.64 UR8, c[0x0][0x388] &wr=0x0 ?trans1;
LDC.64 R4, c[0x0][0x388] &wr=0x1 ?trans1;
SHF.R.S32.HI R3, RZ, 0x1f, R2 ?trans1;
USHF.R.S32.HI UR5, URZ, 0x1f, UR4 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x2 ?trans5;
LDC.64 R6, c[0x0][0x390] &wr=0x3 ?trans1;
IADD.64 R14, R2, UR4 ?WAIT2_END_GROUP;
IADD.64 R12, R2, -UR4 ?WAIT3_END_GROUP;
LEA R10, P1, R14, UR8, 0x2 &req={0} ?trans2;
LEA R8, P0, R12, UR8, 0x2 ?trans2;
LEA.HI.X R11, R14, UR9, R15, 0x2, P1 ?trans2;
LEA.HI.X R9, R12, UR9, R13, 0x2, P0 ?trans1;
IMAD.WIDE R4, R2.reuse, 0x4, R4 &req={1} ?trans1;
LDC.64 R12, c[0x0][0x380] &wr=0x0 ?trans2;
LDG.E R11, desc[UR6][R10.64+0x8] &req={2} &wr=0x2 ?trans4;
LDG.E R8, desc[UR6][R8.64+-0x8] &wr=0x2 ?trans1;
IMAD.WIDE R6, R2, 0x4, R6 &req={3} ?WAIT3_END_GROUP;
LDG.E R3, desc[UR6][R4.64+-0x4] &wr=0x3 ?trans4;
LDG.E R15, desc[UR6][R4.64+0x4] &wr=0x4 ?trans4;
LDG.E R7, desc[UR6][R6.64] &wr=0x5 ?trans1;
FADD R0, -R8, -R11 &req={2} ?WAIT4_END_GROUP;
FADD R0, R0, -R3 &req={3} ?WAIT4_END_GROUP;
FADD R0, R0, -R15 &req={4} ?WAIT4_END_GROUP;
FADD R0, -R0, R7 &req={5} ?trans1;
IMAD.WIDE R2, R2, 0x4, R12 &req={0} ?WAIT4_END_GROUP;
FMUL R9, R0, 0.25 ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x2d0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: Jacobi(float*, float*, float*, int)
_Z6JacobiPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_min_i32_e32 v2, v0, v1
v_max_i32_e32 v3, v0, v1
v_cmp_lt_i32_e32 vcc_lo, 0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s2, s3, v3
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
s_add_i32 s2, s3, 2
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
s_ashr_i32 s2, s3, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_sub_co_u32 v0, vcc_lo, v2, s3
v_subrev_co_ci_u32_e32 v1, vcc_lo, s2, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, v2, s3
v_add_co_ci_u32_e32 v5, vcc_lo, s2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
s_clause 0x2
global_load_b32 v8, v[0:1], off offset:-8
global_load_b32 v4, v[4:5], off offset:8
global_load_b32 v5, v[6:7], off offset:-4
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_load_b32 v6, v[6:7], off offset:4
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(3)
v_sub_f32_e64 v1, -v8, v4
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_f32_e32 v1, v1, v5
s_waitcnt vmcnt(1)
v_sub_f32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v0, v0, v1
v_mul_f32_e32 v4, 0x3e800000, v0
v_add_co_u32 v0, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| Jacobi | 1,199 | 1,422 | stackv2-00000-of-00015 |
// Demangled: reduce2(int, float*, float*, float*)
Function : _Z7reduce2iPfS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R8, SR_TID.X &wr=0x1 ?trans1;
LDCU UR8, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R9, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x380] &wr=0x2 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x3 ?trans1;
IMAD R7, R9, UR8, R8 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P1, PT, R7, UR4, PT &req={2} ?WAIT13_END_GROUP;
@!P1 LDC.64 R2, c[0x0][0x388] &wr=0x1 ?trans8;
@!P1 LDC.64 R4, c[0x0][0x390] &wr=0x2 ?trans1;
@!P1 IMAD.WIDE R2, R7, 0x4, R2 &req={1} ?WAIT6_END_GROUP;
@!P1 LDG.E R2, desc[UR6][R2.64] &req={3} &wr=0x3 ?trans1;
@!P1 IMAD.WIDE R4, R7, 0x4, R4 &req={2} ?WAIT6_END_GROUP;
@!P1 LDG.E R5, desc[UR6][R4.64] &wr=0x3 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
MOV R6, UR8 ?trans1;
UMOV UR4, 0x400 ?WAIT4_END_GROUP;
ISETP.GE.U32.AND P0, PT, R6, 0x2, PT ?trans1;
HFMA2 R7, -RZ, RZ, 0, 0 ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?trans1;
@!P1 FADD R0, R2, -R5 &req={3} ?WAIT4_END_GROUP;
@!P1 FMUL R7, R0, R0 ?trans1;
LEA R0, R8, UR4, 0x2 ?WAIT5_END_GROUP;
STS [R0], R7 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.NE.AND P1, PT, R8, RZ, PT ?WAIT5_END_GROUP;
@!P0 BRA 0x260 &req={0} ?trans8;
SHF.R.U32.HI R5, RZ, 0x1, R6 ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R8, R5, PT ?WAIT13_END_GROUP;
@!P0 IMAD R2, R5, 0x4, R0 ?trans1;
@!P0 LDS R3, [R0] ?trans5;
@!P0 LDS R2, [R2] &wr=0x0 ?trans2;
@!P0 FADD R3, R2, R3 &req={0} ?WAIT5_END_GROUP;
@!P0 STS [R0], R3 &rd=0x0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P0, PT, R6, 0x3, PT ?trans1;
MOV R6, R5 ?WAIT12_END_GROUP;
@P0 BRA 0x1b0 &req={0} ?trans5;
@P1 EXIT ?trans5;
S2UR UR5, SR_CgaCtaId &wr=0x0 ?trans1;
UMOV UR4, 0x400 ?WAIT7_END_GROUP;
LDC.64 R2, c[0x0][0x398] &wr=0x2 ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={0} ?trans1;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={2} ?WAIT8_END_GROUP;
LDS R5, [UR4] &wr=0x0 ?trans4;
STG.E desc[UR6][R2.64], R5 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x2f0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: reduce2(int, float*, float*, float*)
_Z7reduce2iPfS_S_:
s_clause 0x3
s_load_b32 s5, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x0
s_load_b64 s[6:7], s[0:1], 0x18
s_load_b128 s[0:3], s[0:1], 0x8
s_mov_b32 s4, s15
v_lshlrev_b32_e32 v3, 2, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
v_mov_b32_e32 v2, 0
ds_store_b32 v3, v2
v_cmp_gt_i32_e32 vcc_lo, s8, v1
s_and_saveexec_b32 s8, vcc_lo
s_cbranch_execz .LBB1_2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v1, v4, v1
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v1, v1, v1
ds_store_b32 v3, v1
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s8
s_cmp_lt_u32 s5, 2
s_waitcnt lgkmcnt(0)
s_barrier
.LBB1_3:
buffer_gl0_inv
s_cbranch_scc1 .LBB1_7
s_lshr_b32 s0, s5, 1
s_mov_b32 s1, exec_lo
v_cmpx_gt_u32_e64 s0, v0
s_cbranch_execz .LBB1_6
v_lshl_add_u32 v1, s0, 2, v3
ds_load_b32 v1, v1
ds_load_b32 v2, v3
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v1, v2
ds_store_b32 v3, v1
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s1
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s5, 4
s_mov_b32 s5, s0
s_branch .LBB1_3
.LBB1_7:
s_mov_b32 s5, 0
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_9
v_mov_b32_e32 v0, 0
s_lshl_b64 s[0:1], s[4:5], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s6, s0
s_addc_u32 s1, s7, s1
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB1_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| reduce2 | 1,152 | 1,030 | stackv2-00000-of-00015 |
// Demangled: blank_function()
Function : _Z14blank_functionv
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
EXIT ?trans5;
BRA 0x20;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: blank_function()
_Z14blank_functionv:
s_endpgm
| blank_function | 93 | 13 | stackv2-00000-of-00015 |
// Demangled: computeFinalSums(float*, unsigned long, int, int, int, int, float*)
Function : _Z16computeFinalSumsPfmiiiiS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
LDCU UR4, c[0x0][0x394] &wr=0x1 ?trans1;
S2R R6, SR_TID.X &wr=0x2 ?trans6;
LDC R0, c[0x0][0x390] &wr=0x3 ?trans1;
LDCU UR8, c[0x0][0x398] &wr=0x3 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x4 ?trans6;
LDC.64 R4, c[0x0][0x380] &wr=0x5 ?trans1;
ISETP.NE.AND P0, PT, RZ, UR4, PT &req={1} ?WAIT13_END_GROUP;
@!P0 S2R R2, SR_CTAID.X &wr=0x2 ?trans1;
@!P0 LDC R3, c[0x0][0x360] &wr=0x2 ?trans8;
@P0 LDC R7, c[0x0][0x39c] &wr=0x1 ?trans1;
@!P0 IMAD R2, R2, R3, R6 &req={2} ?trans1;
@P0 IADD3 R2, PT, PT, R6, R7, RZ &req={1} ?trans1;
ISETP.LE.AND P0, PT, R0, UR8, PT &req={3} ?WAIT3_END_GROUP;
SHF.R.S32.HI R7, RZ, 0x1f, R2 ?trans1;
IMAD.WIDE R4, R2, 0x4, R4 &req={5} ?WAIT9_END_GROUP;
@!P0 BRA 0x130 &req={4,0} ?trans5;
LDG.E R3, desc[UR6][R4.64] &rd=0x0 &wr=0x5 ?trans1;
BRA 0x690 ?trans5;
LDG.E R3, desc[UR6][R4.64] &rd=0x0 &wr=0x5 ?trans1;
UI2F.U32.RP UR4, UR8 ?trans2;
ISETP.NE.U32.AND P2, PT, RZ, UR8, PT ?WAIT7_END_GROUP;
MUFU.RCP R6, UR4 &wr=0x1 ?trans1;
UIADD3 UR4, UPT, UPT, UR8, UR8, URZ ?WAIT6_END_GROUP;
ISETP.LE.AND P0, PT, R0, UR4, PT ?WAIT5_END_GROUP;
SEL R10, RZ, 0x1, P0 ?WAIT5_END_GROUP;
LOP3.LUT R11, R10, UR4, RZ, 0xfc, !PT ?trans2;
IADD3 R8, PT, PT, R6, 0xffffffe, RZ &req={1} ?trans1;
VIMNMX.S32 R6, R0, UR4, !PT ?trans1;
LDCU UR4, c[0x0][0x398] &wr=0x1 ?trans2;
F2I.FTZ.U32.TRUNC.NTZ R9, R8 &rd=0x2 &wr=0x3 ?trans2;
IADD3 R6, PT, PT, R6, -R11, RZ ?trans1;
HFMA2 R8, -RZ, RZ, 0, 0 &req={2} ?trans1;
IADD3 R13, PT, PT, RZ, -R9, RZ &req={3} ?WAIT5_END_GROUP;
IMAD R13, R13, UR8, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R9, R9, R13, R8 ?WAIT6_END_GROUP;
IMAD.HI.U32 R9, R9, R6, RZ ?WAIT5_END_GROUP;
IADD3 R11, PT, PT, -R9, RZ, RZ ?WAIT5_END_GROUP;
IMAD R6, R11, UR8, R6 ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R6, UR8, PT ?WAIT13_END_GROUP;
@P0 IADD3 R6, PT, PT, R6, -UR8, RZ ?trans2;
@P0 IADD3 R9, PT, PT, R9, 0x1, RZ ?WAIT3_END_GROUP;
ISETP.GE.U32.AND P1, PT, R6, UR8, PT ?WAIT13_END_GROUP;
@P1 IADD3 R9, PT, PT, R9, 0x1, RZ ?trans2;
@!P2 LOP3.LUT R9, RZ, UR8, RZ, 0x33, !PT ?WAIT4_END_GROUP;
IADD3 R10, PT, PT, R10, R9, RZ ?trans2;
LDC.64 R8, c[0x0][0x388] &wr=0x2 ?trans2;
IADD3 R6, PT, PT, R10.reuse, 0x1, RZ ?trans1;
ISETP.GE.U32.AND P1, PT, R10, 0x3, PT ?WAIT3_END_GROUP;
LOP3.LUT P0, R6, R6, 0x3, RZ, 0xc0, !PT ?WAIT13_END_GROUP;
@!P0 BRA 0x410 &req={1,0} ?trans5;
LDC.64 R14, c[0x0][0x388] &wr=0x0 ?trans1;
IADD3 R6, PT, PT, -R6, RZ, RZ ?WAIT7_END_GROUP;
USHF.R.S32.HI UR5, URZ, 0x1f, UR4 ?trans2;
IMAD.WIDE.U32 R10, R14, UR4, R4 &req={0} ?WAIT4_END_GROUP;
IMAD R12, R14, UR5, RZ ?WAIT4_END_GROUP;
IMAD R13, R15, UR4, R12 ?WAIT5_END_GROUP;
IADD3 R11, PT, PT, R11, R13, RZ ?WAIT5_END_GROUP;
LDG.E R10, desc[UR6][R10.64] &wr=0x3 ?trans1;
IADD3 R6, PT, PT, R6, 0x1, RZ ?trans1;
UIADD3 UR4, UPT, UPT, UR4, UR8, URZ ?WAIT4_END_GROUP;
ISETP.NE.AND P0, PT, R6, RZ, PT ?trans1;
FADD R3, R10, R3 &req={5,3,1} ?WAIT5_END_GROUP;
STG.E desc[UR6][R4.64], R3 &rd=0x1 ?trans7;
@P0 BRA 0x350 ?trans5;
@!P1 BRA 0x690 ?trans5;
USHF.R.S32.HI UR5, URZ, 0x1f, UR4 ?trans2;
IMAD.WIDE.U32 R10, R8, UR4, R4 &req={2} ?WAIT4_END_GROUP;
IMAD R6, R8, UR5, RZ ?trans1;
MOV R12, R10 ?WAIT3_END_GROUP;
IMAD R13, R9, UR4, R6 ?WAIT5_END_GROUP;
IADD3 R13, PT, PT, R11, R13, RZ ?WAIT5_END_GROUP;
LDG.E R12, desc[UR6][R12.64] &wr=0x2 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, UR8, URZ ?WAIT4_END_GROUP;
USHF.R.S32.HI UR5, URZ, 0x1f, UR4 ?trans2;
IMAD.WIDE.U32 R10, R8, UR4, R4 ?WAIT4_END_GROUP;
IMAD R6, R8, UR5, RZ ?WAIT4_END_GROUP;
IMAD R15, R9, UR4, R6 &req={3} ?WAIT5_END_GROUP;
IADD3 R11, PT, PT, R11, R15, RZ ?trans1;
FADD R3, R12, R3 &req={5,2,1} ?WAIT5_END_GROUP;
STG.E desc[UR6][R4.64], R3 &rd=0x0 ?trans4;
LDG.E R10, desc[UR6][R10.64] &wr=0x2 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, UR8, URZ ?WAIT4_END_GROUP;
USHF.R.S32.HI UR5, URZ, 0x1f, UR4 ?trans2;
IMAD.WIDE.U32 R12, R8, UR4, R4 ?WAIT4_END_GROUP;
IMAD R6, R8, UR5, RZ ?WAIT4_END_GROUP;
IMAD R15, R9, UR4, R6 ?WAIT5_END_GROUP;
IADD3 R13, PT, PT, R13, R15, RZ ?trans1;
FADD R15, R3, R10 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R4.64], R15 &rd=0x3 ?trans4;
LDG.E R12, desc[UR6][R12.64] &wr=0x2 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, UR8, URZ ?WAIT4_END_GROUP;
USHF.R.S32.HI UR5, URZ, 0x1f, UR4 ?trans2;
IMAD.WIDE.U32 R10, R8, UR4, R4 ?WAIT4_END_GROUP;
IMAD R6, R8, UR5, RZ ?WAIT4_END_GROUP;
IMAD R3, R9, UR4, R6 &req={0} ?WAIT5_END_GROUP;
IADD3 R11, PT, PT, R11, R3, RZ ?trans1;
FADD R17, R15, R12 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R4.64], R17 &rd=0x3 ?trans4;
LDG.E R10, desc[UR6][R10.64] &wr=0x2 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, UR8, URZ ?WAIT6_END_GROUP;
ISETP.LE.AND P0, PT, R0, UR4, PT ?trans1;
FADD R3, R17, R10 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R4.64], R3 &rd=0x3 ?trans7;
@!P0 BRA 0x420 ?trans5;
I2FP.F32.S32 R8, R0 &req={2} ?trans1;
BSSY.RECONVERGENT B0, 0x770 ?trans3;
MUFU.RCP R9, R8 &wr=0x2 ?trans1;
FCHK P0, R3, R8 &req={5} &wr=0x4 ?trans1;
FFMA R0, -R8, R9, 1 &req={2} ?WAIT4_END_GROUP;
FFMA R0, R9, R0, R9 ?WAIT4_END_GROUP;
FFMA R9, R0, R3, RZ ?WAIT4_END_GROUP;
FFMA R6, -R8, R9, R3 ?WAIT4_END_GROUP;
FFMA R9, R0, R6, R9 ?trans1;
@!P0 BRA 0x760 &req={4} ?trans6;
MOV R6, 0x750 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x7d0 &req={3,1,0} ?trans5;
MOV R9, R3 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
LDCU.64 UR4, c[0x0][0x3a0] &wr=0x2 ?trans1;
STG.E desc[UR6][R4.64], R9 ?trans1;
LEA R6, P0, R2, UR4, 0x2 &req={2} ?WAIT4_END_GROUP;
LEA.HI.X R7, R2, UR5, R7, 0x2, P0 ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R9 ?trans1;
EXIT ?trans5;
SHF.R.U32.HI R9, RZ, 0x17, R8 ?trans1;
BSSY.RECONVERGENT B1, 0xe20 ?trans1;
SHF.R.U32.HI R0, RZ, 0x17, R3 ?trans2;
LOP3.LUT R9, R9, 0xff, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R14, R0, 0xff, RZ, 0xc0, !PT ?trans2;
IADD3 R11, PT, PT, R9, -0x1, RZ ?trans2;
IADD3 R12, PT, PT, R14, -0x1, RZ ?WAIT3_END_GROUP;
ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ?WAIT5_END_GROUP;
ISETP.GT.U32.OR P0, PT, R12, 0xfd, P0 ?WAIT13_END_GROUP;
@!P0 MOV R10, RZ ?trans1;
@!P0 BRA 0xa00 ?trans6;
FSETP.GTU.FTZ.AND P0, PT, |R3|, +INF , PT ?trans1;
FSETP.GTU.FTZ.AND P1, PT, |R8|, +INF , PT ?trans1;
MOV R0, R8 ?WAIT4_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, PT, 0xf8, 0x8f ?WAIT13_END_GROUP;
@P0 BRA 0xe00 ?trans5;
LOP3.LUT P0, RZ, R8, 0x7fffffff, R3, 0xc8, !PT ?WAIT13_END_GROUP;
@!P0 BRA 0xde0 ?trans5;
FSETP.NEU.FTZ.AND P2, PT, |R3|.reuse, +INF , PT ?trans1;
FSETP.NEU.FTZ.AND P1, PT, |R0|, +INF , PT ?trans1;
FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ?WAIT12_END_GROUP;
@!P1 BRA !P2, 0xde0 ?trans5;
LOP3.LUT P2, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P1, PT, P1, P2, PT, 0x2f, 0xf2 ?WAIT13_END_GROUP;
@P1 BRA 0xdc0 ?trans5;
LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, PT, 0x2f, 0xf2 ?WAIT13_END_GROUP;
@P0 BRA 0xd90 ?trans5;
ISETP.GE.AND P0, PT, R12, RZ, PT ?trans1;
ISETP.GE.AND P1, PT, R11, RZ, PT ?WAIT12_END_GROUP;
@P0 MOV R10, RZ ?trans1;
@!P0 MOV R10, 0xffffffc0 ?trans1;
@!P0 FFMA R3, R3, 1.84467440737095516160e+19, RZ ?trans1;
@!P1 FFMA R8, R0, 1.84467440737095516160e+19, RZ ?WAIT3_END_GROUP;
@!P1 IADD3 R10, PT, PT, R10, 0x40, RZ ?WAIT7_END_GROUP;
LEA R11, R9, 0xc0800000, 0x17 ?trans1;
BSSY.RECONVERGENT B2, 0xd80 ?trans3;
IADD3 R11, PT, PT, -R11, R8, RZ ?trans2;
IADD3 R8, PT, PT, R14, -0x7f, RZ ?trans2;
MUFU.RCP R12, R11 &wr=0x0 ?trans1;
FADD.FTZ R13, -R11, -RZ ?trans2;
IMAD R0, R8.reuse, -0x800000, R3 ?trans1;
IADD3 R9, PT, PT, R8, 0x7f, -R9 ?WAIT4_END_GROUP;
IADD3 R9, PT, PT, R9, R10, RZ ?trans1;
FFMA R15, R12, R13, 1 &req={0} ?WAIT4_END_GROUP;
FFMA R14, R12, R15, R12 ?WAIT4_END_GROUP;
FFMA R3, R0, R14, RZ ?WAIT4_END_GROUP;
FFMA R12, R13, R3, R0 ?WAIT4_END_GROUP;
FFMA R15, R14, R12, R3 ?WAIT4_END_GROUP;
FFMA R12, R13, R15, R0 ?WAIT4_END_GROUP;
FFMA R3, R14, R12, R15 ?WAIT5_END_GROUP;
SHF.R.U32.HI R0, RZ, 0x17, R3 ?WAIT4_END_GROUP;
LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R10, PT, PT, R0, R9, RZ ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R10, -0x1, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R0, 0xfe, PT ?WAIT13_END_GROUP;
@!P0 BRA 0xd60 ?trans5;
ISETP.GT.AND P0, PT, R10, 0xfe, PT ?WAIT13_END_GROUP;
@P0 BRA 0xd30 ?trans5;
ISETP.GE.AND P0, PT, R10, 0x1, PT ?WAIT13_END_GROUP;
@P0 BRA 0xd70 ?trans5;
ISETP.GE.AND P0, PT, R10, -0x18, PT ?trans1;
LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ?WAIT12_END_GROUP;
@!P0 BRA 0xd70 ?trans5;
FFMA.RZ R0, R14, R12.reuse, R15.reuse ?trans1;
IADD3 R11, PT, PT, R10, 0x20, RZ ?trans1;
FFMA.RM R9, R14, R12.reuse, R15.reuse ?trans1;
ISETP.NE.AND P1, PT, R10.reuse, RZ, PT ?trans1;
ISETP.NE.AND P2, PT, R10, RZ, PT ?trans1;
LOP3.LUT R0, R0, 0x7fffff, RZ, 0xc0, !PT ?trans2;
IADD3 R10, PT, PT, -R10, RZ, RZ ?trans2;
LOP3.LUT R8, R0, 0x800000, RZ, 0xfc, !PT ?trans1;
FFMA.RP R0, R14, R12, R15 ?WAIT3_END_GROUP;
SHF.L.U32 R11, R8, R11, RZ ?trans2;
FSETP.NEU.FTZ.AND P0, PT, R0, R9, PT ?trans1;
SEL R9, R10, RZ, P2 ?trans2;
ISETP.NE.AND P1, PT, R11, RZ, P1 ?WAIT3_END_GROUP;
SHF.R.U32.HI R9, RZ, R9, R8 ?trans2;
PLOP3.LUT P0, PT, P0, P1, PT, 0xf8, 0x8f ?trans2;
SHF.R.U32.HI R11, RZ, 0x1, R9 ?WAIT3_END_GROUP;
SEL R0, RZ, 0x1, !P0 ?WAIT5_END_GROUP;
LOP3.LUT R0, R0, 0x1, R11, 0xf8, !PT ?WAIT4_END_GROUP;
LOP3.LUT R0, R0, R9, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R11, R0, RZ ?WAIT4_END_GROUP;
LOP3.LUT R3, R0, R3, RZ, 0xfc, !PT ?trans1;
BRA 0xd70 ?trans6;
LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ?trans1;
BRA 0xd70 ?trans6;
IMAD R3, R9, 0x800000, R3 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
BRA 0xe10 ?trans5;
LOP3.LUT R3, R8, 0x80000000, R3, 0x48, !PT ?WAIT4_END_GROUP;
LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ?trans1;
BRA 0xe10 ?trans6;
LOP3.LUT R3, R8, 0x80000000, R3, 0x48, !PT ?trans1;
BRA 0xe10 ?trans6;
MUFU.RSQ R3, -QNAN &wr=0x0 ?trans1;
BRA 0xe10 ?trans5;
FADD.FTZ R3, R3, R0 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B1 ?trans5;
MOV R8, R6 ?trans1;
HFMA2 R9, -RZ, RZ, 0, 0 ?WAIT4_END_GROUP;
RET.REL.NODEC R8 0x0 &req={0} ?trans5;
BRA 0xe50;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: computeFinalSums(float*, unsigned long, int, int, int, int, float*)
_Z16computeFinalSumsPfmiiiiS_:
s_load_b128 s[4:7], s[0:1], 0x10
s_mov_b32 s2, 0
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s5, 0
s_cbranch_scc0 .LBB2_2
v_mov_b32_e32 v1, v0
s_branch .LBB2_3
.LBB2_2:
s_mov_b32 s2, -1
.LBB2_3:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB2_5
s_load_b32 s2, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s2, s15, s2
v_mov_b32_e32 v1, s2
s_branch .LBB2_6
.LBB2_5:
v_mov_b32_e32 v0, s7
.LBB2_6:
s_load_b128 s[8:11], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v1, v0
s_cmp_ge_i32 s6, s4
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s8, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v3, vcc_lo
global_load_b32 v6, v[0:1], off
s_cbranch_scc1 .LBB2_9
s_ashr_i32 s2, s6, 31
s_mul_hi_u32 s3, s10, s6
s_mul_i32 s2, s10, s2
s_mul_i32 s5, s11, s6
s_add_i32 s3, s3, s2
s_mul_i32 s2, s10, s6
s_add_i32 s3, s3, s5
s_add_u32 s5, s8, s2
s_addc_u32 s7, s9, s3
v_add_co_u32 v4, vcc_lo, s5, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
s_mov_b32 s5, s6
.LBB2_8:
global_load_b32 v7, v[4:5], off
v_add_co_u32 v4, vcc_lo, v4, s2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_add_i32 s5, s5, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s5, s4
s_waitcnt vmcnt(0)
v_add_f32_e32 v6, v7, v6
global_store_b32 v[0:1], v6, off
s_cbranch_scc1 .LBB2_8
.LBB2_9:
v_cvt_f32_i32_e32 v4, s4
s_load_b64 s[0:1], s[0:1], 0x20
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v5, null, v4, v4, v6
v_div_scale_f32 v9, vcc_lo, v6, v4, v6
v_rcp_f32_e32 v7, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v5, v7, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v8, v7
v_mul_f32_e32 v8, v9, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v10, -v5, v8, v9
v_fmac_f32_e32 v8, v10, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, -v5, v8, v9
v_div_fmas_f32 v5, v5, v7, v8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_div_fixup_f32 v4, v5, v4, v6
global_store_b32 v[0:1], v4, off
global_store_b32 v[2:3], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| computeFinalSums | 5,706 | 1,473 | stackv2-00000-of-00015 |
// Demangled: computeNorms(float*, unsigned long, float*, float*, int, int, int)
Function : _Z12computeNormsPfmS_S_iii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R11, SR_CTAID.X &wr=0x1 ?trans7;
LDC.64 R2, c[0x0][0x398] &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans1;
LDCU.64 UR6, c[0x0][0x388] &wr=0x3 ?trans6;
LDC R0, c[0x0][0x3a4] &wr=0x4 ?trans8;
LDC.64 R4, c[0x0][0x380] &wr=0x3 ?trans1;
IMAD.WIDE.U32 R2, R11, 0x4, R2 &req={1} ?WAIT5_END_GROUP;
LDG.E R8, desc[UR4][R2.64] &req={2} &rd=0x3 &wr=0x2 ?trans1;
ISETP.NE.AND P0, PT, R0, 0x1, PT &req={4} ?trans2;
S2R R0, SR_TID.X &wr=0x1 ?trans11;
@P0 S2R R9, SR_CTAID.Y &wr=0x4 ?trans1;
@!P0 LDC R7, c[0x0][0x3a8] &wr=0x1 ?trans8;
@P0 LDC R6, c[0x0][0x360] &wr=0x4 ?trans1;
@!P0 IADD3 R7, PT, PT, R0, R7, RZ &req={1} ?trans1;
@P0 IMAD R7, R9, R6, R0 &req={4} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R2, R7, UR6, R4 &req={3} ?trans1;
SHF.R.S32.HI R0, RZ, 0x1f, R7 ?WAIT5_END_GROUP;
IMAD R0, R0, UR6, RZ ?WAIT4_END_GROUP;
IMAD R7, R7, UR7, R0 ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R3, R7, RZ ?trans1;
FSETP.NEU.AND P0, PT, R8, RZ, PT &req={2} ?WAIT13_END_GROUP;
@!P0 BRA 0x3b0 &req={0} ?trans5;
LDCU.64 UR6, c[0x0][0x390] &wr=0x0 ?trans1;
IMAD.SHL.U32 R4, R11, 0x4, RZ ?trans1;
SHF.R.U32.HI R5, RZ, 0x1e, R11 ?trans1;
MOV R6, R2 ?WAIT4_END_GROUP;
IADD.64 R2, R4.reuse, UR6 &req={0} ?trans2;
IADD.64 R4, R4, R6 ?WAIT5_END_GROUP;
LDG.E R3, desc[UR4][R2.64] &wr=0x2 ?trans4;
LDG.E R0, desc[UR4][R4.64] &wr=0x2 ?trans1;
IADD3 R6, PT, PT, R8, -0xd000000, RZ ?trans1;
MUFU.RSQ R7, R8 &rd=0x0 &wr=0x1 ?trans4;
ISETP.GT.U32.AND P0, PT, R6, 0x727fffff, PT ?trans1;
FADD R0, R0, -R3 &req={2} ?WAIT12_END_GROUP;
@!P0 BRA 0x280 &req={1,0} ?trans5;
MOV R9, 0x260 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x3f0 ?trans5;
MOV R3, R8 ?trans1;
BRA 0x2c0 ?trans6;
FMUL.FTZ R3, R8, R7 ?trans1;
FMUL.FTZ R7, R7, 0.5 ?WAIT3_END_GROUP;
FFMA R8, -R3, R3, R8 ?WAIT4_END_GROUP;
FFMA R3, R8, R7, R3 ?WAIT7_END_GROUP;
MUFU.RCP R2, R3 &wr=0x0 ?trans1;
BSSY.RECONVERGENT B0, 0x390 ?trans1;
FCHK P0, R0, R3 &wr=0x1 ?trans1;
FFMA R7, R2, -R3, 1 &req={0} ?WAIT4_END_GROUP;
FFMA R7, R2, R7, R2 ?WAIT4_END_GROUP;
FFMA R2, R0, R7, RZ ?WAIT4_END_GROUP;
FFMA R6, R2, -R3, R0 ?WAIT4_END_GROUP;
FFMA R7, R7, R6, R2 ?trans1;
@!P0 BRA 0x380 &req={1} ?trans6;
MOV R2, 0x370 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x560 ?trans5;
MOV R7, R9 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
STG.E desc[UR4][R4.64], R7 ?trans1;
EXIT ?trans5;
LEA R2, P0, R11, R2, 0x2 ?WAIT4_END_GROUP;
LEA.HI.X R3, R11, R7, RZ, 0x2, P0 ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], RZ ?trans1;
EXIT ?trans5;
LOP3.LUT P0, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ?WAIT13_END_GROUP;
@!P0 BRA 0x530 ?trans5;
FSETP.GEU.FTZ.AND P0, PT, R8, RZ, PT ?trans1;
MOV R2, R8 ?WAIT12_END_GROUP;
@!P0 MOV R8, 0x7fffffff ?trans1;
@!P0 BRA 0x530 ?trans6;
FSETP.GTU.FTZ.AND P0, PT, |R2|, +INF , PT ?WAIT13_END_GROUP;
@P0 FADD.FTZ R8, R2, 1 ?trans1;
@P0 BRA 0x530 ?trans6;
FSETP.NEU.FTZ.AND P0, PT, |R2|, +INF , PT ?WAIT13_END_GROUP;
@!P0 MOV R8, R2 ?trans1;
@!P0 BRA 0x530 ?trans6;
FFMA R2, R2, 1.84467440737095516160e+19, RZ ?WAIT4_END_GROUP;
MUFU.RSQ R3, R2 &wr=0x0 ?trans2;
FMUL.FTZ R7, R2, R3 &req={0} ?trans1;
FMUL.FTZ R3, R3, 0.5 ?WAIT3_END_GROUP;
FADD.FTZ R6, -R7, -RZ ?WAIT4_END_GROUP;
FFMA R6, R7, R6, R2 ?WAIT4_END_GROUP;
FFMA R3, R6, R3, R7 ?WAIT4_END_GROUP;
FMUL.FTZ R8, R3, 2.3283064365386962891e-10 ?WAIT7_END_GROUP;
MOV R2, R9 ?trans1;
HFMA2 R3, -RZ, RZ, 0, 0 ?WAIT4_END_GROUP;
RET.REL.NODEC R2 0x0 ?trans5;
SHF.R.U32.HI R7, RZ, 0x17, R3 ?trans1;
BSSY.RECONVERGENT B1, 0xbb0 ?trans1;
SHF.R.U32.HI R6, RZ, 0x17, R0 ?trans2;
LOP3.LUT R12, R7, 0xff, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R10, R6, 0xff, RZ, 0xc0, !PT ?trans1;
MOV R6, R0 ?trans1;
IADD3 R9, PT, PT, R12, -0x1, RZ ?trans2;
IADD3 R8, PT, PT, R10, -0x1, RZ ?WAIT3_END_GROUP;
ISETP.GT.U32.AND P0, PT, R9, 0xfd, PT ?WAIT5_END_GROUP;
ISETP.GT.U32.OR P0, PT, R8, 0xfd, P0 ?WAIT13_END_GROUP;
@!P0 MOV R7, RZ ?trans1;
@!P0 BRA 0x790 ?trans6;
FSETP.GTU.FTZ.AND P1, PT, |R3|, +INF , PT ?trans1;
FSETP.GTU.FTZ.AND P0, PT, |R0|, +INF , PT ?WAIT5_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, PT, 0xf8, 0x8f ?WAIT13_END_GROUP;
@P0 BRA 0xb90 ?trans5;
LOP3.LUT P0, RZ, R3, 0x7fffffff, R6, 0xc8, !PT ?WAIT13_END_GROUP;
@!P0 BRA 0xb70 ?trans5;
FSETP.NEU.FTZ.AND P2, PT, |R0|.reuse, +INF , PT ?trans1;
FSETP.NEU.FTZ.AND P1, PT, |R3|, +INF , PT ?trans1;
FSETP.NEU.FTZ.AND P0, PT, |R0|, +INF , PT ?WAIT12_END_GROUP;
@!P1 BRA !P2, 0xb70 ?trans5;
LOP3.LUT P2, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P1, PT, P1, P2, PT, 0x2f, 0xf2 ?WAIT13_END_GROUP;
@P1 BRA 0xb50 ?trans5;
LOP3.LUT P1, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, PT, 0x2f, 0xf2 ?WAIT13_END_GROUP;
@P0 BRA 0xb20 ?trans5;
ISETP.GE.AND P0, PT, R8, RZ, PT ?trans1;
ISETP.GE.AND P1, PT, R9, RZ, PT ?WAIT12_END_GROUP;
@P0 MOV R7, RZ ?trans1;
@!P0 MOV R7, 0xffffffc0 ?trans1;
@!P0 FFMA R6, R0, 1.84467440737095516160e+19, RZ ?trans1;
@!P1 FFMA R3, R3, 1.84467440737095516160e+19, RZ ?WAIT3_END_GROUP;
@!P1 IADD3 R7, PT, PT, R7, 0x40, RZ ?WAIT7_END_GROUP;
LEA R0, R12, 0xc0800000, 0x17 ?trans1;
BSSY.RECONVERGENT B2, 0xb10 ?trans3;
IADD3 R8, PT, PT, -R0, R3, RZ ?trans2;
IADD3 R3, PT, PT, R10, -0x7f, RZ ?trans2;
MUFU.RCP R9, R8 &wr=0x0 ?trans1;
FADD.FTZ R11, -R8, -RZ ?trans2;
IMAD R0, R3, -0x800000, R6 ?WAIT2_END_GROUP;
FFMA R10, R9, R11, 1 &req={0} ?WAIT4_END_GROUP;
FFMA R13, R9, R10, R9 ?WAIT4_END_GROUP;
FFMA R6, R0, R13, RZ ?WAIT4_END_GROUP;
FFMA R9, R11, R6, R0 ?WAIT4_END_GROUP;
FFMA R10, R13, R9, R6 ?trans1;
IADD3 R6, PT, PT, R3, 0x7f, -R12 ?WAIT3_END_GROUP;
FFMA R11, R11, R10, R0 ?trans1;
IADD3 R6, PT, PT, R6, R7, RZ ?WAIT3_END_GROUP;
FFMA R9, R13, R11, R10 ?WAIT5_END_GROUP;
SHF.R.U32.HI R0, RZ, 0x17, R9 ?WAIT4_END_GROUP;
LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R8, PT, PT, R0, R6, RZ ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R8, -0x1, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R0, 0xfe, PT ?WAIT13_END_GROUP;
@!P0 BRA 0xaf0 ?trans5;
ISETP.GT.AND P0, PT, R8, 0xfe, PT ?WAIT13_END_GROUP;
@P0 BRA 0xac0 ?trans5;
ISETP.GE.AND P0, PT, R8, 0x1, PT ?WAIT13_END_GROUP;
@P0 BRA 0xb00 ?trans5;
ISETP.GE.AND P0, PT, R8, -0x18, PT ?trans1;
LOP3.LUT R9, R9, 0x80000000, RZ, 0xc0, !PT ?WAIT12_END_GROUP;
@!P0 BRA 0xb00 ?trans5;
FFMA.RZ R0, R13.reuse, R11.reuse, R10.reuse ?trans1;
IADD3 R7, PT, PT, R8.reuse, 0x20, RZ ?trans1;
FFMA.RM R3, R13.reuse, R11.reuse, R10.reuse ?trans1;
ISETP.NE.AND P1, PT, R8.reuse, RZ, PT ?trans1;
ISETP.NE.AND P2, PT, R8, RZ, PT ?trans1;
LOP3.LUT R0, R0, 0x7fffff, RZ, 0xc0, !PT ?trans2;
IADD3 R8, PT, PT, -R8, RZ, RZ ?trans2;
LOP3.LUT R6, R0, 0x800000, RZ, 0xfc, !PT ?trans1;
FFMA.RP R0, R13, R11, R10 ?WAIT3_END_GROUP;
SHF.L.U32 R7, R6, R7, RZ ?trans2;
FSETP.NEU.FTZ.AND P0, PT, R0, R3, PT ?trans1;
SEL R3, R8, RZ, P2 ?trans2;
ISETP.NE.AND P1, PT, R7, RZ, P1 ?WAIT3_END_GROUP;
SHF.R.U32.HI R3, RZ, R3, R6 ?trans2;
PLOP3.LUT P0, PT, P0, P1, PT, 0xf8, 0x8f ?trans2;
SHF.R.U32.HI R7, RZ, 0x1, R3 ?WAIT3_END_GROUP;
SEL R0, RZ, 0x1, !P0 ?WAIT5_END_GROUP;
LOP3.LUT R0, R0, 0x1, R7, 0xf8, !PT ?WAIT4_END_GROUP;
LOP3.LUT R0, R0, R3, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R7, R0, RZ ?WAIT4_END_GROUP;
LOP3.LUT R9, R0, R9, RZ, 0xfc, !PT ?trans1;
BRA 0xb00 ?trans6;
LOP3.LUT R9, R9, 0x80000000, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
LOP3.LUT R9, R9, 0x7f800000, RZ, 0xfc, !PT ?trans1;
BRA 0xb00 ?trans6;
IMAD R9, R6, 0x800000, R9 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
BRA 0xba0 ?trans5;
LOP3.LUT R3, R3, 0x80000000, R6, 0x48, !PT ?WAIT4_END_GROUP;
LOP3.LUT R9, R3, 0x7f800000, RZ, 0xfc, !PT ?trans1;
BRA 0xba0 ?trans6;
LOP3.LUT R9, R3, 0x80000000, R6, 0x48, !PT ?trans1;
BRA 0xba0 ?trans6;
MUFU.RSQ R9, -QNAN &wr=0x0 ?trans1;
BRA 0xba0 ?trans5;
FADD.FTZ R9, R0, R3 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B1 ?trans5;
HFMA2 R3, -RZ, RZ, 0, 0 ?WAIT4_END_GROUP;
RET.REL.NODEC R2 0x0 &req={0} ?trans5;
BRA 0xbd0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: computeNorms(float*, unsigned long, float*, float*, int, int, int)
_Z12computeNormsPfmS_S_iii:
s_load_b64 s[2:3], s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s2, 1
s_cbranch_scc0 .LBB4_2
s_load_b32 s2, s[0:1], 0x3c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_mov_b32 s2, 0
s_branch .LBB4_3
.LBB4_2:
s_mov_b32 s2, -1
.LBB4_3:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB4_5
v_add_nc_u32_e32 v2, s3, v0
.LBB4_5:
s_load_b256 s[0:7], s[0:1], 0x0
s_ashr_i32 s15, s14, 31
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
s_lshl_b64 s[8:9], s[14:15], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s6, s8
s_addc_u32 s7, s7, s9
s_add_u32 s0, s8, s0
s_load_b32 s6, s[6:7], 0x0
s_addc_u32 s1, s9, s1
v_mul_lo_u32 v3, v3, s2
v_mad_u64_u32 v[0:1], null, v2, s2, s[0:1]
v_mul_lo_u32 v2, v2, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add3_u32 v1, v3, v1, v2
s_waitcnt lgkmcnt(0)
v_cmp_eq_f32_e64 s0, s6, 0
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB4_7
global_load_b32 v2, v[0:1], off
v_mul_f32_e64 v3, 0x4f800000, s6
v_cmp_gt_f32_e64 vcc_lo, 0xf800000, s6
s_add_u32 s2, s4, s8
s_addc_u32 s3, s5, s9
s_load_b32 s1, s[2:3], 0x0
v_cndmask_b32_e32 v3, s6, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v6, 1, v4
v_add_nc_u32_e32 v5, -1, v4
v_fma_f32 v8, -v6, v4, v3
s_waitcnt vmcnt(0) lgkmcnt(0)
v_subrev_f32_e32 v2, s1, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v5, v4, v3
v_cmp_ge_f32_e64 s0, 0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v4, v4, v5, s0
v_cmp_lt_f32_e64 s0, 0, v8
v_cndmask_b32_e64 v4, v4, v6, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, 0x37800000, v4
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v3, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v4, v3, vcc_lo
v_div_scale_f32 v4, null, v3, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v2, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v6, v5
v_fma_f32 v8, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v8, v5
v_fma_f32 v4, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v4, v4, v5, v7
v_div_fixup_f32 v2, v4, v3, v2
s_branch .LBB4_8
.LBB4_7:
v_mov_b32_e32 v2, 0
.LBB4_8:
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| computeNorms | 4,499 | 1,668 | stackv2-00000-of-00015 |
// Demangled: computeVarianceSquares(float*, unsigned long, float*, int, int, int)
Function : _Z22computeVarianceSquaresPfmS_iii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
LDC R0, c[0x0][0x39c] &wr=0x1 ?trans1;
S2R R9, SR_CTAID.X &wr=0x2 ?trans1;
LDCU.64 UR6, c[0x0][0x388] &wr=0x3 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x4 ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x3 ?trans1;
ISETP.NE.AND P0, PT, R0, 0x1, PT &req={1} ?WAIT2_END_GROUP;
S2R R0, SR_TID.X &wr=0x1 ?trans11;
@P0 S2R R7, SR_CTAID.Y &wr=0x5 ?trans1;
@!P0 LDC R5, c[0x0][0x3a0] &wr=0x1 ?trans8;
@P0 LDC R4, c[0x0][0x360] &wr=0x5 ?trans1;
@!P0 IADD3 R5, PT, PT, R0, R5, RZ &req={1} ?trans1;
@P0 IMAD R5, R7, R4, R0 &req={5} ?WAIT6_END_GROUP;
LDC.64 R6, c[0x0][0x390] &wr=0x1 ?trans1;
IMAD.WIDE.U32 R2, R5, UR6, R2 &req={3} ?trans1;
SHF.R.S32.HI R0, RZ, 0x1f, R5 ?WAIT5_END_GROUP;
IMAD R0, R0, UR6, RZ ?WAIT4_END_GROUP;
IMAD R11, R5, UR7, R0 ?WAIT5_END_GROUP;
IADD3 R3, PT, PT, R3, R11, RZ ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={2} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R6, R9, 0x4, R6 &req={1} ?trans1;
LDG.E R0, desc[UR4][R2.64] &req={4} &wr=0x2 ?trans5;
LDG.E R7, desc[UR4][R6.64] &rd=0x1 &wr=0x2 ?trans1;
BSSY.RECONVERGENT B0, 0x1d0 ?trans1;
MOV R6, 0x1c0 &req={1} ?trans1;
FADD R0, R0, -R7 &req={2} ?WAIT4_END_GROUP;
F2F.F64.F32 R4, R0 &req={0} &rd=0x1 &wr=0x2 ?trans3;
CALL.REL.NOINC 0x330 &req={2,1} ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
DADD R6, R4, 2 &wr=0x0 ?trans1;
FSETP.NEU.AND P0, PT, R0.reuse, RZ, PT ?trans1;
LOP3.LUT R6, R7, 0x7ff00000, RZ, 0xc0, !PT &req={0} ?trans1;
BSSY.RECONVERGENT B0, 0x2f0 ?trans1;
MOV R7, R9 ?trans1;
FSETP.NEU.AND P1, PT, R0, 1, PT ?trans2;
ISETP.NE.AND P2, PT, R6, 0x7ff00000, PT ?trans1;
MOV R6, R8 ?WAIT6_END_GROUP;
@!P0 MOV.64 R6, RZ ?WAIT6_END_GROUP;
@P2 BRA 0x2e0 ?trans5;
FSETP.NAN.AND P0, PT, R0, R0, PT ?WAIT13_END_GROUP;
@P0 DADD R6, R4, 2 &rd=0x0 &wr=0x1 ?trans2;
@P0 BRA 0x2e0 &req={1,0} ?trans5;
ISETP.NE.AND P0, PT, R4, RZ, PT ?trans1;
LOP3.LUT R4, R5, 0x7fffffff, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.OR P0, PT, R4, 0x7ff00000, P0 ?WAIT13_END_GROUP;
@!P0 MOV.64 R6, 0x7ff0000000000000 ?WAIT8_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
F2F.F32.F64 R6, R6 &wr=0x0 ?trans2;
FSEL R5, R6, 1, P1 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R5 ?trans1;
EXIT ?trans5;
DADD R10, -RZ, |R4| &wr=0x0 ?trans1;
UMOV.64 UR6, 0x4330000080000000 ?trans1;
ISETP.GT.U32.AND P0, PT, R11, 0xfffff, PT &req={0} ?trans1;
MOV R7, R11 ?trans1;
MOV R8, R10 ?trans1;
UMOV.64 UR8, 0x3c7abc9e3b39803f ?WAIT15_END_GROUP;
NOP ?WAIT14_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
@!P0 DMUL R16, R10, 1.80143985094819840000e+16 &wr=0x0 ?trans2;
@!P0 MOV R7, R17 &req={0} ?trans1;
@!P0 MOV R8, R16 ?trans1;
SHF.R.U32.HI R10, RZ, 0x14, R11 ?trans2;
@!P0 LEA.HI R10, R17, 0xffffffca, RZ, 0xc ?trans2;
LOP3.LUT R7, R7, 0x800fffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
LOP3.LUT R9, R7, 0x3ff00000, RZ, 0xfc, !PT ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P1, PT, R9, 0x3ff6a09f, PT ?WAIT13_END_GROUP;
@P1 IADD3 R7, PT, PT, R9, -0x100000, RZ ?WAIT5_END_GROUP;
@P1 MOV R9, R7 ?WAIT15_END_GROUP;
NOP ?WAIT14_END_GROUP;
DADD R14, R8, 1 &wr=0x0 ?trans2;
MUFU.RCP64H R11, R15 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R12, R8, -1 &rd=0x1 ?trans2;
IADD3 R8, PT, PT, R10.reuse, -0x3ff, RZ &req={1} ?trans2;
@P1 IADD3 R8, PT, PT, R10, -0x3fe, RZ ?trans1;
MOV R10, RZ ?trans1;
HFMA2 R9, -RZ, RZ, 3.59375, 0 ?trans2;
LOP3.LUT R8, R8, 0x80000000, RZ, 0x3c, !PT ?WAIT15_END_GROUP;
NOP ?WAIT11_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, -R14, R10, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, R16, R16, R16 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, R10, R16, R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R10, R12, R16 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R12, R16, R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R18, R12, -R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R18, R18, R18 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R20, R10, R10 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, R12, -R10, R18 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R12, R16, R12 &req={0} &wr=0x0 ?trans2;
IADD3 R17, PT, PT, R13, 0x100000, RZ &req={0} ?trans1;
MOV R16, R12 ?WAIT15_END_GROUP;
NOP ?trans1;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R14, R10, R20 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R10, R20, -R14 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R22, R10, R10, -R20 &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R12, R20, R18 &req={0} &rd=0x0 ?trans2;
MOV.64 R20, 0x3ed0f5d241ad3b5a &req={0} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R8, R8, -UR6 ?trans1;
UMOV.64 UR6, 0x3eb0f5ff7d2cafe2 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R22, R10, R16, R22 &req={1} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R16, R10, R10 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R20, R16, UR6, R20 &req={0} &wr=0x0 ?trans1;
UMOV.64 UR6, 0x3ef3b20a75488a3f ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R20, R16, R20, UR6 &req={0} &wr=0x0 ?trans1;
UMOV.64 UR6, 0x3f1745cde4faecd5 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R20, R16, R20, UR6 &req={0} &wr=0x0 ?trans1;
UMOV.64 UR6, 0x3f3c71c7258a578b ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R20, R16, R20, UR6 &req={0} &wr=0x0 ?trans1;
UMOV.64 UR6, 0x3f6249249242b910 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R20, R16, R20, UR6 &req={0} &wr=0x0 ?trans1;
UMOV.64 UR6, 0x3f89999999999dfb ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R20, R16, R20, UR6 &req={0} &wr=0x0 ?trans1;
UMOV.64 UR6, 0x3fb5555555555555 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R10, R22, R18 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R22, R16, R20, UR6 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R24, -R22, UR6 &req={0} &wr=0x0 ?trans1;
UMOV.64 UR6, 0x3c46a4cb00b9e7b0 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R24, R16, R20, R24 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R24, R24, -UR6 &req={0} &wr=0x0 ?trans1;
UMOV.64 UR6, 0x3fe62e42fefa39ef ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R16, R22, R24 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R22, R22, -R16 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R22, R24, R22 &req={0} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R20, R16, R14 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R24, R16, R14, -R20 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R16, R18, R24 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R22, R14, R18 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R14, R20, R18 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R16, R10, R14 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R20, R20, -R14 &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R10, R10, -R16 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R20, R18, R20 &req={1} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R10, R14, R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R10, R20, R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R10, R12, R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R12, R16, R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R14, R8, UR6, R12 &req={0} ?trans1;
UMOV.64 UR6, 0x3fe62e42fefa39ef ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R16, R16, -R12 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R16, R10, R16 &req={0} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R8, -UR6, R14 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R10, -R12, R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R10, R16, -R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R8, UR8, R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R8, R14, R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R14, R14, -R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R14, R10, R14 &req={0} &rd=0x0 ?trans2;
MOV.64 R10, 0x3ff71547652b82fe &req={0} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R12, R8, 2 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R8, 2, -R12 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R14, R14, 2, R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R8, R12, R14 &req={0} &wr=0x0 ?trans2;
FSETP.GEU.AND P0, PT, |R9|, 4.1917929649353027344, PT &req={0} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R12, R12, -R8 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R8, R10, 6.75539944105574400000e+15 &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R12, R14, R12 &req={0} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R14, R10, -6.75539944105574400000e+15 &req={1} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, R14, -UR6, R8 &req={0} &wr=0x0 ?trans1;
UMOV.64 UR6, 0x3c7abc9e3b39803f ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R14, R14, -UR6, R16 &req={0} &rd=0x0 &wr=0x1 ?trans1;
UMOV.64 UR6, 0x3e5ade1569ce2bdf ?trans1;
MOV.64 R16, 0x3e928af3fca213ea &req={0} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, R14, UR6, R16 &req={1} &wr=0x0 ?trans1;
UMOV.64 UR6, 0x3ec71dee62401315 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, R14, R16, UR6 &req={0} &wr=0x0 ?trans1;
UMOV.64 UR6, 0x3efa01997c89eb71 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, R14, R16, UR6 &req={0} &wr=0x0 ?trans1;
UMOV.64 UR6, 0x3f2a01a014761f65 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, R14, R16, UR6 &req={0} &wr=0x0 ?trans1;
UMOV.64 UR6, 0x3f56c16c1852b7af ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, R14, R16, UR6 &req={0} &wr=0x0 ?trans1;
UMOV.64 UR6, 0x3f81111111122322 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, R14, R16, UR6 &req={0} &wr=0x0 ?trans1;
UMOV.64 UR6, 0x3fa55555555502a1 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, R14, R16, UR6 &req={0} &wr=0x0 ?trans1;
UMOV.64 UR6, 0x3fc5555555555511 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, R14, R16, UR6 &req={0} &wr=0x0 ?trans1;
UMOV.64 UR6, 0x3fe000000000000b ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, R14, R16, UR6 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, R14, R16, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, R14, R16, 1 &req={0} &wr=0x0 ?trans2;
IMAD R15, R10, 0x100000, R17 &req={0} ?trans1;
MOV R14, R16 ?trans1;
@!P0 BRA 0x1f80 ?trans6;
FSETP.GEU.AND P1, PT, |R9|, 4.2275390625, PT ?trans1;
DSETP.GEU.AND P0, PT, R8, RZ, PT ?WAIT12_END_GROUP;
@!P1 LEA.HI R7, R10, R10, RZ, 0x1 ?WAIT4_END_GROUP;
@!P1 SHF.R.S32.HI R7, RZ, 0x1, R7 ?WAIT4_END_GROUP;
@!P1 IADD3 R10, PT, PT, R10, -R7, RZ ?WAIT4_END_GROUP;
@!P1 LEA R11, R10, 0x3ff00000, 0x14 ?trans1;
@!P1 MOV R10, RZ ?WAIT15_END_GROUP;
NOP ?WAIT9_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R14, R8, +INF &wr=0x0 ?trans2;
FSEL R14, R14, RZ, P0 &req={0} ?trans1;
FSEL R15, R15, RZ, P0 ?trans1;
@!P1 IMAD R9, R7, 0x100000, R17 ?trans1;
@!P1 MOV R8, R16 ?WAIT15_END_GROUP;
NOP ?WAIT14_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
@!P1 DMUL R14, R8, R10 &rd=0x0 &wr=0x1 ?trans2;
LOP3.LUT R7, R15, 0x7fffffff, RZ, 0xc0, !PT &req={1} ?trans1;
DFMA R12, R12, R14, R14 &wr=0x1 ?trans1;
ISETP.NE.AND P1, PT, R14, RZ, PT ?WAIT3_END_GROUP;
ISETP.NE.AND P0, PT, R7, 0x7ff00000, PT ?trans2;
FSEL R7, R14, R12, !P1 &req={1} ?trans1;
FSEL R9, R15, R13, !P1 &req={0} ?WAIT4_END_GROUP;
FSEL R8, R7, R12, !P0 ?trans1;
MOV R7, 0x0 ?trans1;
FSEL R9, R9, R13, !P0 ?WAIT3_END_GROUP;
RET.REL.NODEC R6 0x0 ?trans5;
BRA 0x2020;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: computeVarianceSquares(float*, unsigned long, float*, int, int, int)
_Z22computeVarianceSquaresPfmS_iii:
s_load_b64 s[2:3], s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s2, 1
s_cbranch_scc0 .LBB3_2
s_load_b32 s2, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, 0
s_branch .LBB3_3
.LBB3_2:
s_mov_b32 s2, -1
.LBB3_3:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB3_5
v_add_nc_u32_e32 v1, s3, v0
.LBB3_5:
s_load_b128 s[4:7], s[0:1], 0x0
s_ashr_i32 s15, s14, 31
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v0, 31, v1
s_lshl_b64 s[2:3], s[14:15], 2
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s2, s4
s_addc_u32 s5, s3, s5
v_mul_lo_u32 v4, v1, s7
v_mul_lo_u32 v0, v0, s6
v_mad_u64_u32 v[2:3], null, v1, s6, s[4:5]
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_load_b32 s0, s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add3_u32 v3, v0, v3, v4
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_subrev_f32_e32 v0, s0, v0
s_mov_b32 s0, 0x3e76c4e1
v_frexp_mant_f32_e64 v1, |v0|
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v1
v_cndmask_b32_e64 v4, 0, 1, vcc_lo
v_ldexp_f32 v1, v1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v4, 1.0, v1
v_add_f32_e32 v6, -1.0, v1
v_add_f32_e32 v8, -1.0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_sub_f32_e32 v1, v1, v8
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v7, v6, v5
v_mul_f32_e32 v9, v4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, v7, v4, -v9
v_fmac_f32_e32 v4, v7, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v1, v9, v4
v_sub_f32_e32 v8, v6, v1
v_sub_f32_e32 v9, v1, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v4, v9, v4
v_sub_f32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v1, v6, v1
v_add_f32_e32 v1, v4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v1, v8, v1
v_mul_f32_e32 v1, v5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, v7, v1
v_sub_f32_e32 v5, v4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v6, v4, v4 :: v_dual_sub_f32 v1, v1, v5
v_fma_f32 v5, v4, v4, -v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, v1, v1
v_fmac_f32_e32 v5, v4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, v6, v5
v_fmaak_f32 v8, s0, v7, 0x3e91f4c4
v_sub_f32_e32 v6, v7, v6
v_cmp_neq_f32_e64 s0, 0x7f800000, |v0|
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmaak_f32 v8, v7, v8, 0x3ecccdef :: v_dual_sub_f32 v5, v5, v6
v_mul_f32_e32 v9, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, v7, v8, -v9
v_fmac_f32_e32 v6, v5, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v8, v9, v6
v_dual_sub_f32 v9, v8, v9 :: v_dual_add_f32 v10, 0x3f2aaaaa, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_sub_f32 v6, v6, v9 :: v_dual_add_f32 v9, 0xbf2aaaaa, v10
v_mul_f32_e32 v11, v4, v7
v_sub_f32_e32 v8, v8, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v12, v7, v4, -v11
v_fmac_f32_e32 v12, v7, v1
v_ldexp_f32 v1, v1, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v12, v5, v4
v_ldexp_f32 v4, v4, 1
v_dual_add_f32 v7, v11, v12 :: v_dual_add_f32 v6, 0x31739010, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, v6, v8
v_add_f32_e32 v5, v10, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mul_f32_e32 v9, v7, v5
v_sub_f32_e32 v8, v10, v5
v_sub_f32_e32 v10, v7, v11
v_add_f32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v8, v7, v5, -v9
v_sub_f32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v8, v7, v6
v_frexp_exp_i32_f32_e32 v6, v0
v_fmac_f32_e32 v8, v10, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_subrev_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
v_add_f32_e32 v6, v9, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v5, v5
v_add_f32_e32 v7, v4, v6
v_sub_f32_e32 v9, v6, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f32_e32 v10, 0x3f317218, v5
v_sub_f32_e32 v4, v7, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v8, v8, v9
v_fma_f32 v9, 0x3f317218, v5, -v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v4, v6, v4
v_add_f32_e32 v1, v1, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v5, v5, 0xb102e308, v9
v_dual_add_f32 v1, v1, v4 :: v_dual_add_f32 v4, v10, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, v7, v1
v_dual_add_f32 v8, v4, v6 :: v_dual_sub_f32 v7, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v9, v8, v4
v_dual_sub_f32 v10, v4, v10 :: v_dual_sub_f32 v1, v1, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v11, v8, v9
v_dual_sub_f32 v5, v5, v10 :: v_dual_sub_f32 v6, v6, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v4, v4, v11 :: v_dual_add_f32 v7, v5, v1
v_add_f32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v6, v7, v5
v_add_f32_e32 v4, v7, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v7, v7, v6
v_sub_f32_e32 v1, v1, v6
v_sub_f32_e32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v9, v8, v4
v_add_f32_e32 v1, v1, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v6, v9, v8
v_sub_f32_e32 v4, v4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v1, v1, v4
v_add_f32_e32 v4, v9, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_sub_f32_e32 v5, v4, v9
v_add_f32_e32 v6, v4, v4
v_mul_f32_e32 v7, 0, v4
v_sub_f32_e32 v1, v1, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v4, v4, 2.0, -v6
v_cmp_class_f32_e64 vcc_lo, v6, 0x204
v_fmac_f32_e32 v7, 2.0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v1, v4, v7
v_add_f32_e32 v4, v6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, v4, v6, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v5
v_cndmask_b32_e64 v7, 0, 0x37000000, vcc_lo
v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v5|
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v8, v5, v7
v_mul_f32_e32 v9, 0x3fb8aa3b, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v10, 0x3fb8aa3b, v8, -v9
v_rndne_f32_e32 v11, v9
v_dual_fmamk_f32 v10, v8, 0x32a5705f, v10 :: v_dual_sub_f32 v9, v9, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_f32_e32 v9, v9, v10
v_sub_f32_e32 v4, v4, v6
v_cvt_i32_f32_e32 v6, v11
v_exp_f32_e32 v9, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v1, v1, v4
v_cndmask_b32_e32 v1, 0, v1, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v8
s_waitcnt_depctr 0xfff
v_ldexp_f32 v4, v9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_add_f32 v1, v7, v1 :: v_dual_cndmask_b32 v4, 0, v4
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v8
v_cndmask_b32_e32 v4, 0x7f800000, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v1, v4, v1, v4
v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v4
v_cndmask_b32_e32 v1, v1, v4, vcc_lo
v_cmp_neq_f32_e32 vcc_lo, 0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v1, 0x7f800000, |v1|, s0
v_cndmask_b32_e32 v0, 0, v1, vcc_lo
global_store_b32 v[2:3], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| computeVarianceSquares | 8,240 | 4,946 | stackv2-00000-of-00015 |
// Demangled: my_function(int, int*, int*)
Function : _Z11my_functioniPiS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
EXIT ?trans5;
BRA 0x20;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: my_function(int, int*, int*)
_Z11my_functioniPiS_:
s_endpgm
| my_function | 95 | 15 | stackv2-00000-of-00015 |
// Demangled: Mult_GPU(float*, float*, float*, int, int, int)
Function : _Z8Mult_GPUPfS_S_iii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.Y &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.Y &wr=0x1 ?trans1;
LDCU UR7, c[0x0][0x398] &wr=0x2 ?trans1;
S2R R5, SR_CTAID.X &wr=0x3 ?trans1;
S2R R7, SR_TID.X &wr=0x4 ?trans5;
LDC R0, c[0x0][0x364] &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x370] &wr=0x3 ?trans1;
LDCU UR6, c[0x0][0x360] &wr=0x4 ?trans6;
LDC R8, c[0x0][0x3a0] &wr=0x2 ?trans1;
IMAD R0, R0, UR4, R3 &req={1} ?WAIT4_END_GROUP;
IMAD R0, R0, UR5, R5 &req={3} ?trans2;
IMAD R2, R8, UR7, RZ &req={2} ?trans2;
IMAD R5, R0, UR6, R7 &req={4} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R5, R2, PT ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
IABS R13, R8 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans1;
IABS R6, R5 ?trans1;
HFMA2 R29, -RZ, RZ, 0, 0 ?trans1;
I2F.RP R0, R13 &wr=0x1 ?trans1;
ISETP.GE.AND P2, PT, R5, RZ, PT ?trans1;
MUFU.RCP R0, R0 &req={1} &wr=0x1 ?trans2;
IADD3 R2, PT, PT, R0, 0xffffffe, RZ &req={1} ?WAIT4_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R3, R2 &rd=0x1 &wr=0x2 ?trans2;
HFMA2 R2, -RZ, RZ, 0, 0 &req={1} ?trans1;
IADD3 R4, PT, PT, RZ, -R3, RZ &req={2} ?WAIT5_END_GROUP;
IMAD R7, R4, R13, RZ ?trans1;
MOV R4, R6 ?WAIT3_END_GROUP;
IMAD.HI.U32 R3, R3, R7, R2 ?trans2;
LDC.64 R6, c[0x0][0x390] &wr=0x1 ?trans4;
IMAD.HI.U32 R3, R3, R4, RZ ?WAIT5_END_GROUP;
IADD3 R0, PT, PT, -R3, RZ, RZ ?WAIT5_END_GROUP;
IMAD R2, R13.reuse, R0, R4 ?trans2;
LDC R0, c[0x0][0x39c] &wr=0x2 ?trans3;
ISETP.GT.U32.AND P0, PT, R13, R2, PT ?trans1;
IMAD.WIDE R6, R5, 0x4, R6 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], RZ &req={0} &rd=0x0 ?trans7;
@!P0 IADD3 R2, PT, PT, R2, -R13, RZ ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P1, PT, R13, R2, PT ?trans1;
IADD3 R11, PT, PT, R2, -R13, RZ ?trans1;
ISETP.GE.AND P3, PT, R0, 0x1, PT &req={2} ?WAIT4_END_GROUP;
SEL R4, R11, R2, !P1 ?WAIT5_END_GROUP;
@!P2 IADD3 R4, PT, PT, -R4, RZ, RZ ?WAIT4_END_GROUP;
@!P3 BRA 0xbe0 &req={0} ?trans5;
ISETP.GE.U32.AND P1, PT, R2, R13, PT ?trans1;
LOP3.LUT R5, R5, R8.reuse, RZ, 0x3c, !PT ?trans2;
@!P0 IADD3 R3, PT, PT, R3, 0x1, RZ ?trans1;
ISETP.NE.AND P0, PT, R8, RZ, PT ?trans1;
MOV R29, RZ ?trans1;
ISETP.GE.AND P2, PT, R5, RZ, PT ?trans1;
LOP3.LUT R5, RZ, R8, RZ, 0x33, !PT ?WAIT5_END_GROUP;
SEL R4, R5, R4, !P0 ?trans1;
@P1 IADD3 R3, PT, PT, R3, 0x1, RZ ?trans1;
ISETP.GE.U32.AND P1, PT, R0, 0x8, PT ?WAIT4_END_GROUP;
MOV R2, R3 ?trans1;
LOP3.LUT R3, R0, 0x7, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
@!P2 IADD3 R2, PT, PT, -R2, RZ, RZ ?trans1;
ISETP.NE.AND P2, PT, R3, RZ, PT ?WAIT4_END_GROUP;
SEL R11, R5, R2, !P0 ?trans1;
MOV R5, RZ ?WAIT4_END_GROUP;
IMAD R32, R11, R0, RZ ?trans1;
@!P1 BRA 0x820 ?trans6;
SHF.R.S32.HI R9, RZ, 0x1f, R8 ?trans1;
LDC.64 R22, c[0x0][0x380] &wr=0x0 ?trans1;
LOP3.LUT R36, R0, 0x7ffffff8, RZ, 0xc0, !PT ?trans1;
HFMA2 R5, -RZ, RZ, 0, 0 ?trans1;
MOV R29, RZ ?trans1;
IADD.64 R10, R8.reuse, R8 ?trans2;
MOV R2, R32 ?trans1;
MOV R33, R4 ?trans1;
IADD.64 R12, R8, R10 ?WAIT3_END_GROUP;
IADD3 R36, PT, PT, -R36, RZ, RZ ?trans2;
SHF.L.U64.HI R11, R10, 0x2, R11 ?trans1;
IADD.64 R14, R8, R12 ?trans2;
IMAD.SHL.U32 R10, R10, 0x4, RZ ?trans1;
SHF.L.U64.HI R13, R12, 0x2, R13 ?trans1;
IADD.64 R16, R8, R14 ?trans2;
IMAD.SHL.U32 R12, R12, 0x4, RZ ?trans1;
SHF.L.U64.HI R15, R14, 0x2, R15 ?trans1;
IADD.64 R18, R8, R16 ?WAIT2_END_GROUP;
IMAD.SHL.U32 R14, R14, 0x4, RZ ?trans1;
SHF.L.U64.HI R17, R16, 0x2, R17 ?trans1;
IADD.64 R20, R8, R18 ?trans2;
IADD.64 R22, R22, 0x10 &req={0} ?trans2;
IMAD.SHL.U32 R16, R16, 0x4, RZ ?trans1;
SHF.L.U64.HI R19, R18.reuse, 0x2, R19 ?trans1;
IMAD.SHL.U32 R18, R18, 0x4, RZ ?trans1;
SHF.L.U64.HI R21, R20.reuse, 0x2, R21 ?trans1;
IMAD.SHL.U32 R20, R20, 0x4, RZ ?WAIT7_END_GROUP;
LDC.64 R24, c[0x0][0x388] &wr=0x0 ?trans1;
IMAD.WIDE R26, R2, 0x4, R22 ?WAIT5_END_GROUP;
LDG.E R28, desc[UR4][R26.64+-0x10] &wr=0x2 ?trans4;
LDG.E R37, desc[UR4][R26.64+-0xc] &wr=0x3 ?trans1;
IMAD.WIDE R24, R33, 0x4, R24 &req={0} ?WAIT5_END_GROUP;
LDG.E R34, desc[UR4][R24.64] &wr=0x2 ?trans1;
IMAD.WIDE R30, R8, 0x4, R24 ?WAIT6_END_GROUP;
LDG.E R30, desc[UR4][R30.64] &wr=0x3 ?trans1;
FFMA R28, R28, R34, R29 &req={2} ?trans1;
IADD.64 R34, R24, R12 ?WAIT3_END_GROUP;
FFMA R37, R37, R30, R28 &req={3} ?trans1;
IADD.64 R28, R24, R10 ?WAIT3_END_GROUP;
LDG.E R34, desc[UR4][R34.64] &wr=0x2 ?trans4;
LDG.E R30, desc[UR4][R26.64+-0x4] &wr=0x2 ?trans4;
LDG.E R29, desc[UR4][R28.64] &wr=0x3 ?trans4;
LDG.E R28, desc[UR4][R26.64+-0x8] &wr=0x3 ?trans2;
FFMA R37, R28, R29, R37 &req={3} ?trans1;
IADD.64 R28, R24, R14 ?WAIT3_END_GROUP;
FFMA R37, R30, R34, R37 &req={2} ?trans1;
IADD.64 R30, R24, R16 ?trans2;
LDG.E R34, desc[UR4][R26.64+0x4] &wr=0x2 ?trans4;
LDG.E R28, desc[UR4][R28.64] &wr=0x3 ?trans4;
LDG.E R31, desc[UR4][R30.64] &wr=0x2 ?trans4;
LDG.E R29, desc[UR4][R26.64+0xc] &wr=0x4 ?trans4;
LDG.E R30, desc[UR4][R26.64] &wr=0x3 ?trans1;
IADD3 R36, PT, PT, R36, 0x8, RZ ?trans1;
FFMA R37, R30, R28, R37 &req={3} ?WAIT2_END_GROUP;
LDG.E R28, desc[UR4][R26.64+0x8] &wr=0x3 ?trans2;
FFMA R37, R34, R31, R37 &req={2} ?trans1;
IADD.64 R34, R24.reuse, R18 ?trans2;
IADD.64 R24, R24, R20 ?WAIT5_END_GROUP;
LDG.E R34, desc[UR4][R34.64] &wr=0x3 ?trans4;
LDG.E R24, desc[UR4][R24.64] &wr=0x4 ?trans1;
ISETP.NE.AND P0, PT, R36, RZ, PT ?trans1;
IADD3 R5, PT, PT, R5, 0x8, RZ ?trans2;
IADD3 R2, PT, PT, R2, 0x8, RZ ?trans1;
IMAD R33, R8, 0x8, R33 ?trans2;
FFMA R28, R28, R34, R37 &req={3} ?WAIT4_END_GROUP;
FFMA R29, R29, R24, R28 &req={4} ?WAIT3_END_GROUP;
@P0 BRA 0x5a0 ?trans5;
@!P2 BRA 0xbe0 ?trans5;
ISETP.GE.U32.AND P0, PT, R3, 0x4, PT ?trans1;
LOP3.LUT R21, R0, 0x3, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R21, RZ, PT ?WAIT7_END_GROUP;
@!P0 BRA 0xa30 ?trans6;
LDC.64 R10, c[0x0][0x388] &wr=0x0 ?trans1;
IMAD R3, R5, R8.reuse, R4 ?trans1;
SHF.R.S32.HI R15, RZ, 0x1f, R8 ?trans1;
MOV R14, R8 ?WAIT5_END_GROUP;
LDC.64 R12, c[0x0][0x380] &wr=0x1 ?trans1;
IADD.64 R16, R14, R14 ?WAIT4_END_GROUP;
IADD.64 R14, R14, R16 ?trans2;
IMAD.WIDE R10, R3, 0x4, R10 &req={0} ?trans1;
IADD3 R3, PT, PT, R32, R5, RZ ?trans2;
LEA R2, P0, R16, R10.reuse, 0x2 ?trans1;
IMAD.WIDE R18, R8, 0x4, R10 ?trans1;
LDG.E R22, desc[UR4][R10.64] &wr=0x2 ?trans3;
IMAD.WIDE R12, R3, 0x4, R12 &req={1} ?trans1;
LEA.HI.X R3, R16, R11, R17, 0x2, P0 ?trans1;
LDG.E R18, desc[UR4][R18.64] &wr=0x3 ?trans1;
LEA R16, P0, R14, R10, 0x2 ?WAIT3_END_GROUP;
LDG.E R20, desc[UR4][R12.64] &wr=0x2 ?trans1;
LEA.HI.X R17, R14, R11, R15, 0x2, P0 ?WAIT3_END_GROUP;
LDG.E R23, desc[UR4][R12.64+0x4] &wr=0x3 ?trans4;
LDG.E R2, desc[UR4][R2.64] &wr=0x4 ?trans4;
LDG.E R15, desc[UR4][R12.64+0x8] &wr=0x4 ?trans4;
LDG.E R14, desc[UR4][R12.64+0xc] &wr=0x5 ?trans4;
LDG.E R16, desc[UR4][R16.64] &wr=0x5 ?trans1;
IADD3 R5, PT, PT, R5, 0x4, RZ ?trans1;
FFMA R20, R20, R22, R29 &req={2} ?WAIT4_END_GROUP;
FFMA R20, R23, R18, R20 &req={3} ?WAIT4_END_GROUP;
FFMA R15, R15, R2, R20 &req={4} ?WAIT4_END_GROUP;
FFMA R29, R14, R16, R15 &req={5} ?WAIT7_END_GROUP;
@!P1 BRA 0xbe0 ?trans5;
LDC.64 R14, c[0x0][0x388] &wr=0x0 ?trans1;
ISETP.NE.AND P0, PT, R21, 0x1, PT ?trans1;
LOP3.LUT R0, R0, 0x1, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.U32.AND P1, PT, R0, 0x1, PT ?trans1;
LDC.64 R12, c[0x0][0x380] &wr=0x1 ?trans6;
@P0 IMAD R17, R5.reuse, R8, R4 ?trans1;
@P0 IADD3 R9, PT, PT, R32, R5, RZ ?trans1;
LDC.64 R10, c[0x0][0x380] &wr=0x2 ?trans1;
@P0 IADD3 R5, PT, PT, R5, 0x2, RZ ?WAIT7_END_GROUP;
LDC.64 R2, c[0x0][0x388] &wr=0x3 ?trans1;
@P0 IMAD.WIDE R14, R17, 0x4, R14 &req={0} ?trans1;
@!P1 IADD3 R17, PT, PT, R32, R5, RZ ?WAIT3_END_GROUP;
@!P1 IMAD R5, R5, R8, R4 ?trans2;
@P0 LDG.E R4, desc[UR4][R14.64] &wr=0x4 ?trans1;
@P0 IMAD.WIDE R12, R9, 0x4, R12 &req={1} ?WAIT4_END_GROUP;
@P0 IMAD.WIDE R8, R8, 0x4, R14 ?trans1;
@P0 LDG.E R0, desc[UR4][R12.64] &wr=0x4 ?trans3;
@!P1 IMAD.WIDE R10, R17, 0x4, R10 &req={2} ?trans1;
@P0 LDG.E R19, desc[UR4][R12.64+0x4] &wr=0x2 ?trans4;
@P0 LDG.E R8, desc[UR4][R8.64] &wr=0x2 ?trans1;
@!P1 IMAD.WIDE R2, R5, 0x4, R2 &req={3} ?WAIT3_END_GROUP;
@!P1 LDG.E R10, desc[UR4][R10.64] &wr=0x3 ?trans4;
@!P1 LDG.E R2, desc[UR4][R2.64] &wr=0x3 ?trans1;
@P0 FFMA R0, R0, R4, R29 &req={4} ?WAIT4_END_GROUP;
@P0 FFMA R29, R19, R8, R0 &req={2} ?WAIT4_END_GROUP;
@!P1 FFMA R29, R10, R2, R29 &req={3} ?WAIT7_END_GROUP;
STG.E desc[UR4][R6.64], R29 ?trans1;
EXIT ?trans5;
BRA 0xc00;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: Mult_GPU(float*, float*, float*, int, int, int)
_Z8Mult_GPUPfS_S_iii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x28
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_load_b128 s[4:7], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v2, s3, s[14:15]
v_mad_u64_u32 v[2:3], null, v4, s2, v[0:1]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s6, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v2
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_5
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v3, 31, v2
v_mov_b32_e32 v6, 0
s_cmp_lt_i32 s5, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_cbranch_scc1 .LBB0_4
s_ashr_i32 s2, s6, 31
v_add_nc_u32_e32 v6, v2, v3
s_add_i32 s3, s6, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s3, s3, s2
v_xor_b32_e32 v6, v6, v3
v_cvt_f32_u32_e32 v4, s3
s_sub_i32 s4, 0, s3
v_xor_b32_e32 v3, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
v_cvt_u32_f32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, s4, v4
v_mul_hi_u32 v5, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v4, v5
v_mul_hi_u32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v4, s3
v_sub_nc_u32_e32 v5, v6, v5
v_add_nc_u32_e32 v6, 1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v7, s3, v5
v_cmp_le_u32_e32 vcc_lo, s3, v5
v_dual_cndmask_b32 v5, v5, v7 :: v_dual_cndmask_b32 v4, v4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s3, v5
v_add_nc_u32_e32 v6, 1, v4
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, v4, v6, vcc_lo
v_xor_b32_e32 v4, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v4, v3
v_mul_lo_u32 v3, v5, s5
v_mul_lo_u32 v6, v5, s6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_sub_nc_u32_e32 v2, v2, v6
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
.LBB0_3:
v_ashrrev_i32_e32 v3, 31, v2
s_add_i32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s5, 0
v_lshlrev_b64 v[7:8], 2, v[2:3]
v_add_nc_u32_e32 v2, s6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
global_load_b32 v3, v[4:5], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v3, v7
s_cbranch_scc0 .LBB0_3
.LBB0_4:
global_store_b32 v[0:1], v6, off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| Mult_GPU | 4,967 | 2,030 | stackv2-00000-of-00015 |
// Demangled: dz(float*, float*, float*, int, int)
Function : _Z2dzPfS_S_ii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R5, SR_TID.Y &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.Y &wr=0x1 ?trans1;
S2R R7, SR_CTAID.X &wr=0x2 ?trans1;
S2R R9, SR_TID.X &wr=0x3 ?trans6;
LDC R0, c[0x0][0x364] &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x370] &wr=0x2 ?trans1;
LDCU UR6, c[0x0][0x360] &wr=0x3 ?trans6;
LDC.64 R2, c[0x0][0x398] &wr=0x4 ?trans1;
IMAD R0, R0, UR4, R5 &req={1} ?WAIT4_END_GROUP;
IMAD R0, R0, UR5, R7 &req={2} ?trans1;
ISETP.GE.AND P0, PT, R2, 0x1, PT &req={4} ?WAIT3_END_GROUP;
IMAD R0, R0, UR6, R9 &req={3} ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R0, R3, !P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
ISETP.GE.U32.AND P1, PT, R2.reuse, 0x10, PT ?trans1;
LOP3.LUT R20, R2, 0xf, RZ, 0xc0, !PT ?trans1;
UMOV UR4, URZ ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x0 ?trans1;
IMAD R0, R0, R2, RZ ?trans2;
ISETP.NE.AND P0, PT, R20, RZ, PT ?WAIT7_END_GROUP;
@!P1 BRA 0x680 ?trans6;
LDC.64 R4, c[0x0][0x380] &wr=0x1 ?trans1;
LOP3.LUT R16, R2, 0x7ffffff0, RZ, 0xc0, !PT ?trans1;
UMOV UR4, URZ ?trans1;
MOV R3, R0 ?trans2;
IADD3 R16, PT, PT, -R16, RZ, RZ ?WAIT3_END_GROUP;
LDC.64 R6, c[0x0][0x388] &wr=0x2 ?trans8;
LDC.64 R8, c[0x0][0x390] &wr=0x3 ?trans1;
IADD.64 R4, R4, 0x20 &req={1} ?trans2;
IADD.64 R6, R6, 0x20 &req={2} ?WAIT2_END_GROUP;
IADD.64 R8, R8, 0x20 &req={3} ?WAIT8_END_GROUP;
IMAD.WIDE R14, R3, 0x4, R4 ?WAIT4_END_GROUP;
IMAD.WIDE R12, R3.reuse, 0x4, R6 ?trans1;
LDG.E R17, desc[UR6][R14.64+-0x20] &req={4,0} &wr=0x2 ?trans4;
LDG.E R18, desc[UR6][R12.64+-0x20] &wr=0x2 ?trans1;
IMAD.WIDE R10, R3, 0x4, R8 ?WAIT4_END_GROUP;
FADD R17, R17, -R18 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R10.64+-0x20], R17 &rd=0x0 ?trans4;
LDG.E R18, desc[UR6][R14.64+-0x1c] &wr=0x2 ?trans4;
LDG.E R19, desc[UR6][R12.64+-0x1c] &wr=0x2 ?trans2;
FADD R19, R18, -R19 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R10.64+-0x1c], R19 &rd=0x1 ?trans4;
LDG.E R18, desc[UR6][R14.64+-0x18] &wr=0x2 ?trans4;
LDG.E R21, desc[UR6][R12.64+-0x18] &wr=0x2 ?trans2;
FADD R21, R18, -R21 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R10.64+-0x18], R21 &rd=0x2 ?trans4;
LDG.E R18, desc[UR6][R14.64+-0x14] &wr=0x3 ?trans4;
LDG.E R23, desc[UR6][R12.64+-0x14] &wr=0x3 ?trans2;
FADD R23, R18, -R23 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R10.64+-0x14], R23 &rd=0x3 ?trans4;
LDG.E R17, desc[UR6][R14.64+-0x10] &req={0} &wr=0x4 ?trans4;
LDG.E R18, desc[UR6][R12.64+-0x10] &wr=0x4 ?trans2;
FADD R17, R17, -R18 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R10.64+-0x10], R17 &rd=0x0 ?trans4;
LDG.E R18, desc[UR6][R14.64+-0xc] &wr=0x4 ?trans4;
LDG.E R19, desc[UR6][R12.64+-0xc] &req={1} &wr=0x4 ?trans2;
FADD R19, R18, -R19 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R10.64+-0xc], R19 &rd=0x1 ?trans4;
LDG.E R18, desc[UR6][R14.64+-0x8] &wr=0x4 ?trans4;
LDG.E R21, desc[UR6][R12.64+-0x8] &req={2} &wr=0x4 ?trans2;
FADD R21, R18, -R21 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R10.64+-0x8], R21 &rd=0x2 ?trans4;
LDG.E R18, desc[UR6][R14.64+-0x4] &wr=0x4 ?trans4;
LDG.E R23, desc[UR6][R12.64+-0x4] &req={3} &wr=0x4 ?trans2;
FADD R23, R18, -R23 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R10.64+-0x4], R23 &rd=0x3 ?trans4;
LDG.E R17, desc[UR6][R14.64] &req={0} &wr=0x4 ?trans4;
LDG.E R18, desc[UR6][R12.64] &wr=0x4 ?trans2;
FADD R17, R17, -R18 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R10.64], R17 &rd=0x0 ?trans4;
LDG.E R18, desc[UR6][R14.64+0x4] &wr=0x4 ?trans4;
LDG.E R19, desc[UR6][R12.64+0x4] &req={1} &wr=0x4 ?trans2;
FADD R19, R18, -R19 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R10.64+0x4], R19 &rd=0x1 ?trans4;
LDG.E R18, desc[UR6][R14.64+0x8] &wr=0x4 ?trans4;
LDG.E R21, desc[UR6][R12.64+0x8] &req={2} &wr=0x4 ?trans2;
FADD R21, R18, -R21 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R10.64+0x8], R21 &rd=0x2 ?trans4;
LDG.E R18, desc[UR6][R14.64+0xc] &wr=0x4 ?trans4;
LDG.E R23, desc[UR6][R12.64+0xc] &req={3} &wr=0x4 ?trans2;
FADD R23, R18, -R23 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R10.64+0xc], R23 &rd=0x3 ?trans4;
LDG.E R17, desc[UR6][R14.64+0x10] &req={0} &wr=0x4 ?trans4;
LDG.E R18, desc[UR6][R12.64+0x10] &wr=0x4 ?trans2;
FADD R17, R17, -R18 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R10.64+0x10], R17 &rd=0x4 ?trans4;
LDG.E R18, desc[UR6][R14.64+0x14] &wr=0x5 ?trans4;
LDG.E R19, desc[UR6][R12.64+0x14] &req={1} &wr=0x5 ?trans2;
FADD R19, R18, -R19 &req={5} ?WAIT5_END_GROUP;
STG.E desc[UR6][R10.64+0x14], R19 &rd=0x4 ?trans4;
LDG.E R18, desc[UR6][R14.64+0x18] &wr=0x5 ?trans4;
LDG.E R21, desc[UR6][R12.64+0x18] &req={2} &wr=0x5 ?trans1;
IADD3 R16, PT, PT, R16, 0x10, RZ ?trans1;
FADD R21, R18, -R21 &req={5} ?WAIT5_END_GROUP;
STG.E desc[UR6][R10.64+0x18], R21 &rd=0x4 ?trans4;
LDG.E R18, desc[UR6][R14.64+0x1c] &wr=0x2 ?trans4;
LDG.E R23, desc[UR6][R12.64+0x1c] &req={3} &wr=0x2 ?trans1;
ISETP.NE.AND P1, PT, R16, RZ, PT ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x10, URZ ?trans1;
IADD3 R3, PT, PT, R3, 0x10, RZ ?trans1;
FADD R23, R18, -R23 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R10.64+0x1c], R23 &rd=0x4 ?trans5;
@P1 BRA 0x200 ?trans5;
@!P0 EXIT &req={0} ?trans5;
ISETP.GE.U32.AND P0, PT, R20, 0x8, PT ?trans1;
LOP3.LUT R12, R2, 0x7, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R12, RZ, PT ?WAIT7_END_GROUP;
@!P0 BRA 0x950 ?trans6;
LDC.64 R4, c[0x0][0x380] &wr=0x0 ?trans1;
IADD3 R3, PT, PT, R0, UR4, RZ ?WAIT7_END_GROUP;
LDC.64 R6, c[0x0][0x388] &wr=0x1 ?trans8;
LDC.64 R8, c[0x0][0x390] &wr=0x2 ?trans1;
IMAD.WIDE R4, R3, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
LDG.E R10, desc[UR6][R4.64] &req={4} &wr=0x3 ?trans1;
IMAD.WIDE R6, R3, 0x4, R6 &req={1} ?WAIT5_END_GROUP;
LDG.E R11, desc[UR6][R6.64] &wr=0x3 ?trans1;
IMAD.WIDE R8, R3, 0x4, R8 &req={2} ?WAIT4_END_GROUP;
FADD R11, R10, -R11 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R8.64], R11 &rd=0x0 ?trans4;
LDG.E R3, desc[UR6][R4.64+0x4] &wr=0x2 ?trans4;
LDG.E R10, desc[UR6][R6.64+0x4] &wr=0x2 ?trans2;
FADD R3, R3, -R10 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R8.64+0x4], R3 &rd=0x1 ?trans4;
LDG.E R10, desc[UR6][R4.64+0x8] &wr=0x2 ?trans4;
LDG.E R13, desc[UR6][R6.64+0x8] &wr=0x2 ?trans2;
FADD R13, R10, -R13 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R8.64+0x8], R13 &rd=0x2 ?trans4;
LDG.E R10, desc[UR6][R4.64+0xc] &wr=0x3 ?trans4;
LDG.E R15, desc[UR6][R6.64+0xc] &wr=0x3 ?trans2;
FADD R15, R10, -R15 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R8.64+0xc], R15 &rd=0x3 ?trans4;
LDG.E R10, desc[UR6][R4.64+0x10] &wr=0x4 ?trans4;
LDG.E R11, desc[UR6][R6.64+0x10] &req={0} &wr=0x4 ?trans2;
FADD R11, R10, -R11 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R8.64+0x10], R11 &rd=0x0 ?trans4;
LDG.E R3, desc[UR6][R4.64+0x14] &req={1} &wr=0x4 ?trans4;
LDG.E R10, desc[UR6][R6.64+0x14] &wr=0x4 ?trans2;
FADD R3, R3, -R10 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R8.64+0x14], R3 &rd=0x0 ?trans4;
LDG.E R10, desc[UR6][R4.64+0x18] &wr=0x4 ?trans4;
LDG.E R13, desc[UR6][R6.64+0x18] &req={2} &wr=0x4 ?trans2;
FADD R13, R10, -R13 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R8.64+0x18], R13 &rd=0x0 ?trans4;
LDG.E R10, desc[UR6][R4.64+0x1c] &wr=0x2 ?trans4;
LDG.E R15, desc[UR6][R6.64+0x1c] &req={3} &wr=0x2 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x8, URZ ?trans1;
FADD R15, R10, -R15 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R8.64+0x1c], R15 &rd=0x0 ?trans6;
@!P1 EXIT ?trans5;
ISETP.GE.U32.AND P0, PT, R12, 0x4, PT ?trans1;
LOP3.LUT R14, R2, 0x3, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R14, RZ, PT ?WAIT7_END_GROUP;
@!P0 BRA 0xb20 ?trans6;
LDC.64 R2, c[0x0][0x380] &req={0} &wr=0x0 ?trans1;
IADD3 R11, PT, PT, R0, UR4, RZ &req={4} ?WAIT7_END_GROUP;
LDC.64 R4, c[0x0][0x388] &wr=0x1 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x2 ?trans1;
IMAD.WIDE R2, R11, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E R8, desc[UR6][R2.64] &wr=0x3 ?trans1;
IMAD.WIDE R4, R11, 0x4, R4 &req={1} ?WAIT5_END_GROUP;
LDG.E R9, desc[UR6][R4.64] &wr=0x3 ?trans1;
IMAD.WIDE R6, R11, 0x4, R6 &req={2} ?WAIT4_END_GROUP;
FADD R9, R8, -R9 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R9 &rd=0x1 ?trans4;
LDG.E R8, desc[UR6][R2.64+0x4] &wr=0x2 ?trans4;
LDG.E R11, desc[UR6][R4.64+0x4] &wr=0x2 ?trans2;
FADD R11, R8, -R11 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64+0x4], R11 &rd=0x1 ?trans4;
LDG.E R8, desc[UR6][R2.64+0x8] &wr=0x2 ?trans4;
LDG.E R13, desc[UR6][R4.64+0x8] &wr=0x2 ?trans2;
FADD R13, R8, -R13 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64+0x8], R13 &rd=0x1 ?trans4;
LDG.E R8, desc[UR6][R2.64+0xc] &wr=0x2 ?trans4;
LDG.E R15, desc[UR6][R4.64+0xc] &wr=0x2 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x4, URZ ?trans1;
FADD R15, R8, -R15 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64+0xc], R15 &rd=0x1 ?trans6;
@!P1 EXIT ?trans5;
LDC.64 R8, c[0x0][0x390] &req={1,0} &wr=0x0 ?trans1;
IADD3 R15, PT, PT, R0, UR4, RZ ?trans2;
IADD3 R14, PT, PT, -R14, RZ, RZ ?WAIT5_END_GROUP;
LDC.64 R12, c[0x0][0x380] &wr=0x1 ?trans8;
LDC.64 R10, c[0x0][0x388] &req={4} &wr=0x2 ?trans2;
IMAD.WIDE R4, R15, 0x4, R10 &req={2} ?WAIT4_END_GROUP;
IMAD.WIDE R6, R15.reuse, 0x4, R12 &req={1} ?trans2;
LDG.E R5, desc[UR6][R4.64] &wr=0x2 ?trans4;
LDG.E R6, desc[UR6][R6.64] &wr=0x2 ?trans1;
IADD3 R14, PT, PT, R14, 0x1, RZ ?trans1;
IMAD.WIDE R2, R15.reuse, 0x4, R8 &req={3,0} ?trans1;
IADD3 R15, PT, PT, R15, 0x1, RZ ?WAIT3_END_GROUP;
ISETP.NE.AND P0, PT, R14, RZ, PT ?trans1;
FADD R17, R6, -R5 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R17 &rd=0x3 ?trans7;
@P0 BRA 0xb80 ?trans5;
EXIT ?trans5;
BRA 0xc40;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: dz(float*, float*, float*, int, int)
_Z2dzPfS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s5, s[0:1], 0x20
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s4, 16
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_load_b64 s[2:3], s[0:1], 0x18
v_mad_u64_u32 v[3:4], null, v2, s5, s[14:15]
v_and_b32_e32 v2, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v3, s4, v[2:3]
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s2, 0
v_cmp_gt_i32_e32 vcc_lo, s3, v0
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, vcc_lo, s3
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB5_3
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v0, v0, s2
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
.LBB5_2:
global_load_b32 v6, v[0:1], off
global_load_b32 v7, v[2:3], off
v_add_co_u32 v0, vcc_lo, v0, 4
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s2, 0
s_waitcnt vmcnt(0)
v_sub_f32_e32 v6, v6, v7
global_store_b32 v[4:5], v6, off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_cbranch_scc1 .LBB5_2
.LBB5_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| dz | 5,635 | 1,070 | stackv2-00000-of-00015 |
// Demangled: grad(float*, float*, float*, int, int, int)
Function : _Z4gradPfS_S_iii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.Y &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.Y &wr=0x1 ?trans1;
LDCU UR9, c[0x0][0x398] &wr=0x2 ?trans1;
S2R R5, SR_CTAID.X &wr=0x3 ?trans1;
LDCU UR8, c[0x0][0x3a0] &wr=0x4 ?trans1;
S2R R7, SR_TID.X &wr=0x5 ?trans4;
LDC R0, c[0x0][0x364] &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x370] &wr=0x3 ?trans1;
LDCU UR6, c[0x0][0x360] &wr=0x5 ?trans1;
UISETP.GE.AND UP0, UPT, UR9, 0x1, UPT &req={2} ?WAIT6_END_GROUP;
PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x8 ?trans1;
IMAD R0, R0, UR4, R3 &req={1} ?WAIT4_END_GROUP;
IMAD R0, R0, UR5, R5 &req={3} ?WAIT4_END_GROUP;
IMAD R0, R0, UR6, R7 &req={5} ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R0, UR8, !P0 &req={4} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC R2, c[0x0][0x39c] &wr=0x0 ?trans2;
ISETP.GE.AND P0, PT, R2, 0x1, PT &req={0} ?WAIT13_END_GROUP;
@!P0 EXIT ?trans5;
USHF.R.S32.HI UR5, URZ, 0x1f, UR8 ?trans2;
UMOV UR4, UR8 ?trans1;
LDCU.64 UR12, c[0x0][0x358] &wr=0x0 ?trans1;
UIADD3.64 UR6, UPT, UPT, UR4, UR4, URZ ?trans1;
USHF.L.U32 UR11, UR9, 0x3, URZ ?WAIT3_END_GROUP;
UIADD3.64 UR4, UPT, UPT, UR4, UR6, URZ ?trans1;
USHF.L.U64.HI UR7, UR6, 0x2, UR7 ?trans1;
USHF.L.U32 UR6, UR6, 0x2, URZ ?trans2;
USHF.L.U64.HI UR5, UR4, 0x2, UR5 ?trans1;
USHF.L.U32 UR4, UR4, 0x2, URZ ?trans2;
MOV R3, UR7 ?trans1;
MOV R2, UR6 ?trans2;
MOV R5, UR5 ?trans1;
MOV R4, UR4 ?trans1;
UMOV UR4, URZ ?WAIT6_END_GROUP;
LDCU.64 UR14, c[0x0][0x398] &wr=0x1 ?trans1;
LDC.64 R12, c[0x0][0x390] &req={0} &wr=0x2 ?trans1;
LDCU UR7, c[0x0][0x39c] &wr=0x3 ?trans1;
UISETP.GE.U32.AND UP0, UPT, UR15, 0x8, UPT &req={1} ?trans1;
MOV R7, UR14 ?WAIT5_END_GROUP;
PLOP3.LUT P1, PT, PT, PT, UP0, 0x80, 0x8 ?trans1;
IMAD R7, R0, R7, UR4 ?trans1;
ULOP3.LUT UR8, UR7, 0x7, URZ, 0xc0, !UPT &req={3} ?WAIT3_END_GROUP;
IMAD.WIDE R12, R7, 0x4, R12 &req={2} ?trans1;
UMOV UR5, URZ ?trans2;
ISETP.NE.AND P0, PT, RZ, UR8, PT ?trans2;
LDG.E R27, desc[UR12][R12.64] &req={0} &rd=0x0 &wr=0x5 ?trans3;
@!P1 BRA 0x8f0 ?trans8;
LDC R14, c[0x0][0x3a0] &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x39c] &wr=0x2 ?trans1;
LDCU.64 UR26, c[0x0][0x388] &wr=0x3 ?trans1;
UIADD3 UR9, UPT, UPT, UR4, UR14, URZ ?trans1;
UIADD3 UR10, UPT, UPT, UR4, UR14, UR14 ?trans1;
UIMAD UR15, UR14, 0x3, UR4 ?trans1;
ULEA UR16, UR14, UR4, 0x2 ?trans1;
UIMAD UR17, UR14, 0x5, UR4 ?trans1;
UIMAD UR18, UR14, 0x6, UR4 ?trans1;
UIMAD UR19, UR14, 0x7, UR4 ?trans1;
ULOP3.LUT UR5, UR5, 0x7ffffff8, URZ, 0xc0, !UPT &req={2} ?WAIT4_END_GROUP;
UIADD3 UR6, UPT, UPT, -UR5, URZ, URZ ?trans1;
SHF.R.S32.HI R15, RZ, 0x1f, R14 &req={1} ?trans1;
UIMAD.WIDE.U32 UR20, UR4, 0x4, UR26 &req={3} ?trans1;
UMOV UR5, URZ ?WAIT3_END_GROUP;
IADD.64 R4, R14, R14 ?WAIT5_END_GROUP;
SHF.L.U64.HI R3, R4.reuse, 0x2, R5 ?trans1;
IMAD.SHL.U32 R2, R4, 0x4, RZ ?trans1;
IADD.64 R4, R14, R4 ?WAIT4_END_GROUP;
IADD.64 R6, R14, R4 ?WAIT3_END_GROUP;
SHF.L.U64.HI R5, R4.reuse, 0x2, R5 ?trans1;
IMAD.SHL.U32 R4, R4, 0x4, RZ ?trans1;
SHF.L.U64.HI R17, R6.reuse, 0x2, R7 ?trans1;
IMAD.SHL.U32 R16, R6, 0x4, RZ ?trans1;
IADD.64 R6, R14, R6 ?WAIT5_END_GROUP;
SHF.L.U64.HI R19, R6.reuse, 0x2, R7 ?trans1;
IMAD.SHL.U32 R18, R6, 0x4, RZ ?trans1;
IADD.64 R6, R14, R6 ?WAIT4_END_GROUP;
IADD.64 R8, R14, R6 ?trans2;
IMAD.SHL.U32 R20, R6.reuse, 0x4, RZ ?trans1;
SHF.L.U64.HI R21, R6, 0x2, R7 ?trans2;
SHF.L.U64.HI R23, R8.reuse, 0x2, R9 ?trans1;
IMAD.SHL.U32 R22, R8, 0x4, RZ ?trans1;
MOV R6, R0 ?WAIT7_END_GROUP;
LDC.64 R24, c[0x0][0x380] &wr=0x1 ?trans1;
MOV.64 R28, UR20 ?WAIT7_END_GROUP;
LDG.E R28, desc[UR12][R28.64] &wr=0x2 ?trans1;
IMAD.WIDE R24, R6, 0x4, R24 &req={1} ?WAIT5_END_GROUP;
LDG.E R26, desc[UR12][R24.64] &wr=0x2 ?trans1;
UIMAD.WIDE.U32 UR22, UR9, 0x4, UR26 ?trans1;
UIMAD.WIDE.U32 UR24, UR10, 0x4, UR26 ?WAIT5_END_GROUP;
MOV.64 R8, UR22 ?trans2;
MOV.64 R34, UR24 ?trans2;
UIMAD.WIDE.U32 UR22, UR15, 0x4, UR26 ?trans2;
LDG.E R7, desc[UR12][R8.64] &rd=0x1 &wr=0x3 ?trans1;
IADD.64 R32, R24.reuse, R2 ?trans2;
IADD.64 R10, R24.reuse, R16 ?trans2;
LDG.E R34, desc[UR12][R34.64] &wr=0x4 ?trans1;
IADD.64 R36, R24, R18 ?WAIT2_END_GROUP;
IADD.64 R30, R24, R4 ?trans2;
IMAD.WIDE R8, R14, 0x4, R24 &req={1} ?trans1;
UIMAD.WIDE.U32 UR24, UR16, 0x4, UR26 ?trans1;
LDG.E R33, desc[UR12][R32.64] &wr=0x4 ?trans4;
LDG.E R35, desc[UR12][R8.64] &rd=0x1 &wr=0x3 ?trans4;
LDG.E R11, desc[UR12][R10.64] &wr=0x4 ?trans4;
LDG.E R31, desc[UR12][R30.64] &wr=0x4 ?trans1;
MOV.64 R8, UR22 &req={1} ?WAIT2_END_GROUP;
UIMAD.WIDE.U32 UR22, UR17, 0x4, UR26 ?trans1;
LDG.E R10, desc[UR12][R36.64] &rd=0x1 &wr=0x4 ?trans4;
LDG.E R32, desc[UR12][R8.64] &wr=0x4 ?trans1;
MOV.64 R36, UR24 &req={1} ?trans2;
UIMAD.WIDE.U32 UR24, UR18, 0x4, UR26 ?WAIT4_END_GROUP;
LDG.E R30, desc[UR12][R36.64] &rd=0x1 &wr=0x4 ?trans2;
IADD.64 R36, R24, R22 &req={1} ?WAIT7_END_GROUP;
LDG.E R36, desc[UR12][R36.64] &wr=0x4 ?trans1;
FFMA R8, R26, R28, R27 &req={5,2} ?trans1;
IADD.64 R28, R24, R20 ?trans2;
MOV.64 R26, UR22 ?trans2;
UIMAD.WIDE.U32 UR22, UR19, 0x4, UR26 ?trans2;
LDG.E R9, desc[UR12][R28.64] &rd=0x1 &wr=0x2 ?trans4;
LDG.E R27, desc[UR12][R26.64] &wr=0x2 ?trans1;
MOV.64 R24, UR22 ?WAIT2_END_GROUP;
MOV.64 R28, UR24 &req={1} ?WAIT5_END_GROUP;
LDG.E R25, desc[UR12][R24.64] &wr=0x2 ?trans4;
LDG.E R28, desc[UR12][R28.64] &wr=0x2 ?trans1;
UIADD3 UR6, UPT, UPT, UR6, 0x8, URZ ?trans1;
FFMA R8, R35, R7, R8 &req={3} ?WAIT4_END_GROUP;
FFMA R8, R33, R34, R8 &req={4} ?trans1;
ISETP.NE.AND P1, PT, RZ, UR6, PT ?WAIT3_END_GROUP;
FFMA R8, R31, R32, R8 ?trans1;
UIADD3 UR5, UPT, UPT, UR5, 0x8, URZ ?trans1;
UIADD3 UR9, UPT, UPT, UR11, UR9, URZ ?trans2;
FFMA R11, R11, R30, R8 ?trans1;
UIADD3 UR10, UPT, UPT, UR11, UR10, URZ ?trans1;
UIADD3 UR15, UPT, UPT, UR11, UR15, URZ ?trans1;
UIADD3 UR16, UPT, UPT, UR11, UR16, URZ ?trans1;
UIADD3 UR17, UPT, UPT, UR11, UR17, URZ ?trans1;
UIADD3 UR18, UPT, UPT, UR11, UR18, URZ ?trans1;
UIADD3 UR19, UPT, UPT, UR11, UR19, URZ ?trans1;
UIMAD.WIDE.U32 UR20, UR11, 0x4, UR20 ?trans1;
IMAD R6, R14, 0x8, R6 ?WAIT2_END_GROUP;
FFMA R10, R10, R27, R11 &req={2} ?WAIT4_END_GROUP;
FFMA R9, R9, R28, R10 ?WAIT4_END_GROUP;
FFMA R27, R36, R25, R9 ?trans1;
@P1 BRA 0x520 ?trans6;
@!P0 BRA 0xdd0 ?trans5;
UIADD3 UR6, UPT, UPT, UR8, -0x1, URZ ?trans1;
ULOP3.LUT UR10, UR7, 0x3, URZ, 0xc0, !UPT ?WAIT3_END_GROUP;
UISETP.GE.U32.AND UP0, UPT, UR6, 0x3, UPT ?WAIT3_END_GROUP;
ISETP.NE.AND P0, PT, RZ, UR10, PT ?WAIT3_END_GROUP;
PLOP3.LUT P1, PT, PT, PT, UP0, 0x80, 0x8 ?WAIT13_END_GROUP;
@!P1 BRA 0xb70 ?trans5;
LDC R11, c[0x0][0x3a0] &wr=0x1 ?trans1;
LDCU.128 UR16, c[0x0][0x380] &wr=0x2 ?trans1;
UIMAD UR6, UR5, UR14, UR4 ?WAIT4_END_GROUP;
UIADD3 UR8, UPT, UPT, UR6, UR14, URZ ?trans1;
UIMAD.WIDE.U32 UR6, UR6, 0x4, UR18 &req={2} ?trans1;
MOV.64 R6, UR16 ?trans2;
UIMAD.WIDE.U32 UR16, UR8, 0x4, UR18 ?trans1;
IMAD R9, R11, UR5, R0 &req={1} ?trans2;
MOV.64 R14, UR6 ?trans2;
UIADD3 UR6, UPT, UPT, UR8, UR14, URZ ?trans1;
MOV.64 R16, UR16 ?WAIT2_END_GROUP;
IMAD.WIDE R6, R9, 0x4, R6 ?trans1;
UIADD3 UR8, UPT, UPT, UR6, UR14, URZ ?trans1;
UIMAD.WIDE.U32 UR6, UR6, 0x4, UR18 ?trans1;
LDG.E R23, desc[UR12][R14.64] &rd=0x1 &wr=0x2 ?trans1;
IMAD.WIDE R8, R11, 0x4, R6 ?trans1;
UIMAD.WIDE.U32 UR8, UR8, 0x4, UR18 ?trans2;
LDG.E R22, desc[UR12][R6.64] &wr=0x2 ?trans1;
IADD.64 R10, R6, R2 ?trans2;
MOV.64 R18, UR6 ?WAIT2_END_GROUP;
LDG.E R16, desc[UR12][R16.64] &wr=0x3 ?trans1;
MOV.64 R20, UR8 ?trans2;
IADD.64 R14, R6, R4 &req={1} ?trans2;
LDG.E R9, desc[UR12][R8.64] &wr=0x3 ?trans4;
LDG.E R18, desc[UR12][R18.64] &wr=0x4 ?trans4;
LDG.E R10, desc[UR12][R10.64] &wr=0x4 ?trans4;
LDG.E R20, desc[UR12][R20.64] &wr=0x4 ?trans4;
LDG.E R14, desc[UR12][R14.64] &wr=0x4 ?trans1;
UIADD3 UR5, UPT, UPT, UR5, 0x4, URZ ?trans1;
FFMA R22, R22, R23, R27 &req={5,2} ?WAIT4_END_GROUP;
FFMA R9, R9, R16, R22 &req={3} ?WAIT4_END_GROUP;
FFMA R9, R10, R18, R9 &req={4} ?WAIT4_END_GROUP;
FFMA R27, R14, R20, R9 ?WAIT7_END_GROUP;
@!P0 BRA 0xdd0 ?trans5;
LDCU UR6, c[0x0][0x39c] &wr=0x1 ?trans1;
UISETP.NE.AND UP0, UPT, UR10, 0x1, UPT ?WAIT6_END_GROUP;
PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x8 ?WAIT5_END_GROUP;
@UP0 LDCU UR7, c[0x0][0x3a0] &wr=0x2 ?trans1;
ULOP3.LUT UP1, URZ, UR6, 0x1, URZ, 0xc0, !UPT &req={1} ?trans1;
@UP0 LDCU.128 UR16, c[0x0][0x380] &wr=0x1 ?trans1;
@UP0 UIMAD UR6, UR5, UR14, UR4 ?WAIT4_END_GROUP;
PLOP3.LUT P1, PT, PT, PT, UP1, 0x80, 0x8 ?WAIT5_END_GROUP;
@UP1 LDCU UR10, c[0x0][0x3a0] &wr=0x3 ?trans1;
MOV R11, UR7 &req={2} ?trans1;
@UP1 LDCU.128 UR20, c[0x0][0x380] &wr=0x2 ?trans1;
@UP0 UIMAD.WIDE.U32 UR8, UR6, 0x4, UR18 &req={1} ?trans1;
@UP0 UIADD3 UR6, UPT, UPT, UR6, UR14, URZ ?trans1;
MOV.64 R8, UR16 ?trans2;
@P0 IMAD R7, R11, UR5, R0 ?trans1;
@UP0 UIADD3 UR5, UPT, UPT, UR5, 0x2, URZ ?trans1;
@UP0 UIMAD.WIDE.U32 UR6, UR6, 0x4, UR18 ?trans1;
MOV.64 R14, UR8 ?WAIT2_END_GROUP;
@P0 IMAD.WIDE R8, R7, 0x4, R8 ?trans1;
@UP1 UIMAD UR8, UR5, UR14, UR4 ?trans1;
MOV R19, UR10 &req={3} ?trans1;
MOV.64 R16, UR6 ?trans2;
@P0 LDG.E R14, desc[UR12][R14.64] &wr=0x3 ?trans1;
@P0 IMAD.WIDE R10, R11, 0x4, R8 ?trans1;
MOV.64 R6, UR20 &req={2} ?trans2;
@UP1 UIMAD.WIDE.U32 UR6, UR8, 0x4, UR22 ?trans1;
@P0 LDG.E R8, desc[UR12][R8.64] &wr=0x3 ?trans1;
@P1 IMAD R19, R19, UR5, R0 ?WAIT3_END_GROUP;
@P0 LDG.E R16, desc[UR12][R16.64] &wr=0x2 ?trans1;
@P1 IMAD.WIDE R6, R19, 0x4, R6 ?trans1;
MOV.64 R18, UR6 ?trans2;
@P0 LDG.E R11, desc[UR12][R10.64] &wr=0x2 ?trans4;
@P1 LDG.E R6, desc[UR12][R6.64] &wr=0x4 ?trans4;
@P1 LDG.E R18, desc[UR12][R18.64] &wr=0x4 ?trans1;
@P0 FFMA R14, R8, R14, R27 &req={5,3} ?WAIT4_END_GROUP;
@P0 FFMA R27, R11, R16, R14 &req={2} ?WAIT4_END_GROUP;
@P1 FFMA R27, R6, R18, R27 &req={4} ?WAIT7_END_GROUP;
UIADD3 UR4, UPT, UPT, UR4, 0x1, URZ ?trans1;
STG.E desc[UR12][R12.64], R27 &req={5} &rd=0x1 ?trans3;
UISETP.NE.AND UP0, UPT, UR4, UR14, UPT ?WAIT6_END_GROUP;
PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x8 ?WAIT13_END_GROUP;
@P0 BRA 0x230 &req={1} ?trans5;
EXIT ?trans5;
BRA 0xe30;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: grad(float*, float*, float*, int, int, int)
_Z4gradPfS_S_iii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x28
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_load_b128 s[4:7], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mov_b32 s7, 0
v_mad_u64_u32 v[3:4], null, v2, s3, s[14:15]
v_and_b32_e32 v2, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v3, s2, v[2:3]
s_cmp_gt_i32 s4, 0
s_cselect_b32 s2, -1, 0
v_cmp_gt_i32_e32 vcc_lo, s6, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB6_5
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mul_lo_u32 v5, v0, s4
s_cmp_gt_i32 s5, 0
v_mov_b32_e32 v6, 0
s_cselect_b32 s14, -1, 0
s_ashr_i32 s3, s4, 31
s_mov_b32 s2, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
.LBB6_2:
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v1, s7, v5
v_mov_b32_e32 v3, v0
s_waitcnt lgkmcnt(0)
s_mov_b64 s[12:13], s[10:11]
s_mov_b32 s15, s5
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_and_not1_b32 vcc_lo, exec_lo, s14
global_load_b32 v7, v[1:2], off
s_cbranch_vccnz .LBB6_4
.LBB6_3:
v_ashrrev_i32_e32 v4, 31, v3
s_add_i32 s15, s15, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[8:9], 2, v[3:4]
v_add_nc_u32_e32 v3, s6, v3
v_add_co_u32 v8, vcc_lo, s8, v8
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
global_load_b32 v4, v6, s[12:13]
global_load_b32 v8, v[8:9], off
s_add_u32 s12, s12, s2
s_addc_u32 s13, s13, s3
s_cmp_eq_u32 s15, 0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v7, v8, v4
s_cbranch_scc0 .LBB6_3
.LBB6_4:
s_add_i32 s7, s7, 1
s_add_u32 s10, s10, 4
s_addc_u32 s11, s11, 0
s_cmp_eq_u32 s7, s4
s_waitcnt vmcnt(0)
global_store_b32 v[1:2], v7, off
s_cbranch_scc0 .LBB6_2
.LBB6_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| grad | 5,799 | 1,335 | stackv2-00000-of-00015 |
// Demangled: initialize(float*, float*, int, int)
Function : _Z10initializePfS_ii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.Y &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.Y &wr=0x1 ?trans1;
LDCU UR7, c[0x0][0x390] &wr=0x2 ?trans1;
S2R R5, SR_CTAID.X &wr=0x3 ?trans1;
S2R R7, SR_TID.X &wr=0x4 ?trans5;
LDC R0, c[0x0][0x364] &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x370] &wr=0x3 ?trans1;
LDCU UR6, c[0x0][0x360] &wr=0x4 ?trans1;
IMAD R0, R0, UR4, R3 &req={1} ?WAIT4_END_GROUP;
IMAD R0, R0, UR5, R5 &req={3} ?WAIT4_END_GROUP;
IMAD R5, R0, UR6, R7 &req={4} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R5, UR7, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC R8, c[0x0][0x394] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x2 ?trans1;
ISETP.GE.AND P0, PT, R8, 0x1, PT &req={0} ?trans1;
IMAD.WIDE R2, R5, 0x4, R2 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], RZ &req={1} &rd=0x0 ?trans7;
@!P0 EXIT ?trans5;
ISETP.GE.U32.AND P1, PT, R8.reuse, 0x8, PT ?trans1;
LOP3.LUT R10, R8, 0x7, RZ, 0xc0, !PT ?trans1;
HFMA2 R7, -RZ, RZ, 0, 0 ?trans2;
IMAD R0, R5, R8, RZ ?trans2;
ISETP.NE.AND P0, PT, R10, RZ, PT ?WAIT7_END_GROUP;
@!P1 BRA 0x2f0 ?trans6;
LDC.64 R2, c[0x0][0x388] &req={0} &wr=0x0 ?trans1;
LOP3.LUT R4, R8, 0x7ffffff8, RZ, 0xc0, !PT ?trans1;
MOV R7, RZ ?trans1;
MOV R9, R0 ?trans2;
IADD3 R6, PT, PT, -R4, RZ, RZ ?trans1;
IADD.64 R2, R2, 0x10 &req={0} ?WAIT8_END_GROUP;
IADD3 R6, PT, PT, R6, 0x8, RZ ?trans1;
IMAD.WIDE R4, R9, 0x4, R2 &req={1} ?trans1;
IADD3 R7, PT, PT, R7, 0x8, RZ ?trans2;
IADD3 R9, PT, PT, R9, 0x8, RZ ?trans1;
ISETP.NE.AND P1, PT, R6, RZ, PT ?trans1;
STG.E desc[UR4][R4.64+-0x10], RZ &rd=0x1 ?trans4;
STG.E desc[UR4][R4.64+-0xc], RZ &rd=0x1 ?trans4;
STG.E desc[UR4][R4.64+-0x8], RZ &rd=0x1 ?trans4;
STG.E desc[UR4][R4.64+-0x4], RZ &rd=0x1 ?trans4;
STG.E desc[UR4][R4.64], RZ &rd=0x1 ?trans4;
STG.E desc[UR4][R4.64+0x4], RZ &rd=0x1 ?trans4;
STG.E desc[UR4][R4.64+0x8], RZ &rd=0x1 ?trans4;
STG.E desc[UR4][R4.64+0xc], RZ &rd=0x1 ?trans1;
@P1 BRA 0x210 ?trans5;
@!P0 EXIT ?trans5;
ISETP.GE.U32.AND P0, PT, R10, 0x4, PT ?trans1;
LOP3.LUT R4, R8, 0x3, RZ, 0xc0, !PT &req={1} ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R4, RZ, PT ?WAIT7_END_GROUP;
@!P0 BRA 0x3c0 ?trans6;
LDC.64 R2, c[0x0][0x388] &req={0} &wr=0x0 ?trans1;
IADD3 R5, PT, PT, R0, R7, RZ ?trans2;
IADD3 R7, PT, PT, R7, 0x4, RZ ?WAIT3_END_GROUP;
IMAD.WIDE R2, R5, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], RZ &rd=0x1 ?trans4;
STG.E desc[UR4][R2.64+0x4], RZ &rd=0x1 ?trans4;
STG.E desc[UR4][R2.64+0x8], RZ &rd=0x1 ?trans4;
STG.E desc[UR4][R2.64+0xc], RZ &rd=0x1 ?trans2;
@!P1 EXIT ?trans5;
ISETP.NE.AND P0, PT, R4, 0x1, PT ?trans1;
LOP3.LUT R4, R8, 0x1, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.U32.AND P1, PT, R4, 0x1, PT ?WAIT7_END_GROUP;
@P0 LDC.64 R2, c[0x0][0x388] &req={1,0} &wr=0x0 ?trans1;
@P0 IADD3 R5, PT, PT, R0, R7, RZ ?WAIT5_END_GROUP;
@P0 IMAD.WIDE R2, R5, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
@P0 STG.E desc[UR4][R2.64], RZ &rd=0x0 ?trans4;
@P0 STG.E desc[UR4][R2.64+0x4], RZ &rd=0x0 ?trans1;
@P1 EXIT ?trans5;
LDC.64 R2, c[0x0][0x388] &req={0} &wr=0x0 ?trans1;
@P0 IADD3 R7, PT, PT, R7, 0x2, RZ ?WAIT4_END_GROUP;
IADD3 R7, PT, PT, R0, R7, RZ ?WAIT5_END_GROUP;
IMAD.WIDE R2, R7, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], RZ ?trans1;
EXIT ?trans5;
BRA 0x4c0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: initialize(float*, float*, int, int)
_Z10initializePfS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_load_b64 s[4:5], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v2, s3, s[14:15]
v_and_b32_e32 v2, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v3, s2, v[2:3]
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s4, v0
s_cbranch_execz .LBB10_4
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_cmp_lt_i32 s5, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v2, vcc_lo
v_mov_b32_e32 v2, 0
global_store_b32 v[3:4], v2, off
s_cbranch_scc1 .LBB10_4
v_mul_lo_u32 v0, v0, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
.LBB10_3:
global_store_b32 v[0:1], v2, off
v_add_co_u32 v0, vcc_lo, v0, 4
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_add_i32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s5, 0
s_cbranch_scc1 .LBB10_3
.LBB10_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| initialize | 1,974 | 928 | stackv2-00000-of-00015 |
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