sass stringlengths 231 30.8k | rdna stringlengths 69 28.4k | function_name stringlengths 1 85 | sass_tokens int64 90 14.4k ⌀ | rdna_tokens int64 11 14.5k ⌀ | source stringclasses 15 values |
|---|---|---|---|---|---|
// Demangled: initialize_dz(float*, int, int)
Function : _Z13initialize_dzPfii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R5, SR_TID.Y &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.Y &wr=0x1 ?trans1;
S2R R7, SR_CTAID.X &wr=0x2 ?trans1;
S2R R9, SR_TID.X &wr=0x3 ?trans6;
LDC R0, c[0x0][0x364] &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x370] &wr=0x2 ?trans1;
LDCU UR6, c[0x0][0x360] &wr=0x3 ?trans6;
LDC.64 R2, c[0x0][0x388] &wr=0x4 ?trans1;
IMAD R0, R0, UR4, R5 &req={1} ?WAIT4_END_GROUP;
IMAD R0, R0, UR5, R7 &req={2} ?trans1;
ISETP.GE.AND P0, PT, R2, 0x1, PT &req={4} ?WAIT3_END_GROUP;
IMAD R0, R0, UR6, R9 &req={3} ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R0, R3, !P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
ISETP.GE.U32.AND P1, PT, R2.reuse, 0x8, PT ?trans1;
LOP3.LUT R8, R2, 0x7, RZ, 0xc0, !PT ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans1;
HFMA2 R9, -RZ, RZ, 0, 0 ?trans2;
IMAD R0, R0, R2, RZ ?trans1;
ISETP.NE.AND P0, PT, R8, RZ, PT ?WAIT7_END_GROUP;
@!P1 BRA 0x2a0 ?trans6;
LDC.64 R4, c[0x0][0x380] &wr=0x1 ?trans1;
LOP3.LUT R3, R2, 0x7ffffff8, RZ, 0xc0, !PT ?trans1;
MOV R9, RZ ?trans1;
MOV R11, R0 ?trans2;
IADD3 R3, PT, PT, -R3, RZ, RZ ?trans1;
IADD.64 R4, R4, 0x10 &req={1} ?WAIT8_END_GROUP;
IADD3 R3, PT, PT, R3, 0x8, RZ ?trans1;
IMAD.WIDE R6, R11, 0x4, R4 &req={1} ?trans1;
IADD3 R9, PT, PT, R9, 0x8, RZ ?trans2;
IADD3 R11, PT, PT, R11, 0x8, RZ ?trans1;
ISETP.NE.AND P1, PT, R3, RZ, PT ?trans1;
STG.E desc[UR4][R6.64+-0x10], RZ &req={0} &rd=0x1 ?trans4;
STG.E desc[UR4][R6.64+-0xc], RZ &rd=0x1 ?trans4;
STG.E desc[UR4][R6.64+-0x8], RZ &rd=0x1 ?trans4;
STG.E desc[UR4][R6.64+-0x4], RZ &rd=0x1 ?trans4;
STG.E desc[UR4][R6.64], RZ &rd=0x1 ?trans4;
STG.E desc[UR4][R6.64+0x4], RZ &rd=0x1 ?trans4;
STG.E desc[UR4][R6.64+0x8], RZ &rd=0x1 ?trans4;
STG.E desc[UR4][R6.64+0xc], RZ &rd=0x1 ?trans1;
@P1 BRA 0x1c0 ?trans5;
@!P0 EXIT &req={0} ?trans5;
ISETP.GE.U32.AND P0, PT, R8, 0x4, PT ?trans1;
LOP3.LUT R6, R2, 0x3, RZ, 0xc0, !PT &req={1} ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R6, RZ, PT ?WAIT7_END_GROUP;
@!P0 BRA 0x370 ?trans6;
LDC.64 R4, c[0x0][0x380] &wr=0x0 ?trans1;
IADD3 R3, PT, PT, R0, R9, RZ ?trans2;
IADD3 R9, PT, PT, R9, 0x4, RZ ?WAIT3_END_GROUP;
IMAD.WIDE R4, R3, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64], RZ &rd=0x0 ?trans4;
STG.E desc[UR4][R4.64+0x4], RZ &rd=0x0 ?trans4;
STG.E desc[UR4][R4.64+0x8], RZ &rd=0x0 ?trans4;
STG.E desc[UR4][R4.64+0xc], RZ &rd=0x0 ?trans2;
@!P1 EXIT ?trans5;
ISETP.NE.AND P0, PT, R6, 0x1, PT ?trans1;
LOP3.LUT R2, R2, 0x1, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.U32.AND P1, PT, R2, 0x1, PT ?WAIT7_END_GROUP;
@P0 LDC.64 R4, c[0x0][0x380] &req={0} &wr=0x0 ?trans1;
@P0 IADD3 R3, PT, PT, R0, R9, RZ ?WAIT5_END_GROUP;
@P0 IMAD.WIDE R4, R3, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
@P0 STG.E desc[UR4][R4.64], RZ &rd=0x0 ?trans4;
@P0 STG.E desc[UR4][R4.64+0x4], RZ &rd=0x0 ?trans1;
@P1 EXIT ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans1;
@P0 IADD3 R9, PT, PT, R9, 0x2, RZ ?WAIT4_END_GROUP;
IADD3 R9, PT, PT, R0, R9, RZ ?WAIT5_END_GROUP;
IMAD.WIDE R2, R9, 0x4, R2 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], RZ ?trans1;
EXIT ?trans5;
BRA 0x470;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: initialize_dz(float*, int, int)
_Z13initialize_dzPfii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b32 s5, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s4, 16
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_load_b64 s[2:3], s[0:1], 0x8
v_mad_u64_u32 v[3:4], null, v2, s5, s[14:15]
v_and_b32_e32 v2, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v3, s4, v[2:3]
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s2, 0
v_cmp_gt_i32_e32 vcc_lo, s3, v0
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, vcc_lo, s3
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB8_3
s_load_b64 s[0:1], s[0:1], 0x0
v_mul_lo_u32 v0, v0, s2
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
.LBB8_2:
global_store_b32 v[0:1], v2, off
v_add_co_u32 v0, vcc_lo, v0, 4
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s2, 0
s_cbranch_scc1 .LBB8_2
.LBB8_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| initialize_dz | 1,835 | 818 | stackv2-00000-of-00015 |
// Demangled: initialize_grad(float*, int, int)
Function : _Z15initialize_gradPfii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R5, SR_TID.Y &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.Y &wr=0x1 ?trans1;
S2R R7, SR_CTAID.X &wr=0x2 ?trans1;
S2R R9, SR_TID.X &wr=0x3 ?trans6;
LDC R0, c[0x0][0x364] &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x370] &wr=0x2 ?trans1;
LDCU UR6, c[0x0][0x360] &wr=0x3 ?trans6;
LDC.64 R2, c[0x0][0x388] &wr=0x4 ?trans1;
IMAD R0, R0, UR4, R5 &req={1} ?WAIT4_END_GROUP;
IMAD R0, R0, UR5, R7 &req={2} ?trans1;
ISETP.GE.AND P0, PT, R2, 0x1, PT &req={4} ?WAIT3_END_GROUP;
IMAD R0, R0, UR6, R9 &req={3} ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R0, R3, !P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
ISETP.GE.U32.AND P1, PT, R2.reuse, 0x8, PT ?trans1;
LOP3.LUT R8, R2, 0x7, RZ, 0xc0, !PT ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans1;
HFMA2 R9, -RZ, RZ, 0, 0 ?trans2;
IMAD R0, R0, R2, RZ ?trans1;
ISETP.NE.AND P0, PT, R8, RZ, PT ?WAIT7_END_GROUP;
@!P1 BRA 0x2a0 ?trans6;
LDC.64 R4, c[0x0][0x380] &wr=0x1 ?trans1;
LOP3.LUT R3, R2, 0x7ffffff8, RZ, 0xc0, !PT ?trans1;
MOV R9, RZ ?trans1;
MOV R11, R0 ?trans2;
IADD3 R3, PT, PT, -R3, RZ, RZ ?trans1;
IADD.64 R4, R4, 0x10 &req={1} ?WAIT8_END_GROUP;
IADD3 R3, PT, PT, R3, 0x8, RZ ?trans1;
IMAD.WIDE R6, R11, 0x4, R4 &req={1} ?trans1;
IADD3 R9, PT, PT, R9, 0x8, RZ ?trans2;
IADD3 R11, PT, PT, R11, 0x8, RZ ?trans1;
ISETP.NE.AND P1, PT, R3, RZ, PT ?trans1;
STG.E desc[UR4][R6.64+-0x10], RZ &req={0} &rd=0x1 ?trans4;
STG.E desc[UR4][R6.64+-0xc], RZ &rd=0x1 ?trans4;
STG.E desc[UR4][R6.64+-0x8], RZ &rd=0x1 ?trans4;
STG.E desc[UR4][R6.64+-0x4], RZ &rd=0x1 ?trans4;
STG.E desc[UR4][R6.64], RZ &rd=0x1 ?trans4;
STG.E desc[UR4][R6.64+0x4], RZ &rd=0x1 ?trans4;
STG.E desc[UR4][R6.64+0x8], RZ &rd=0x1 ?trans4;
STG.E desc[UR4][R6.64+0xc], RZ &rd=0x1 ?trans1;
@P1 BRA 0x1c0 ?trans5;
@!P0 EXIT &req={0} ?trans5;
ISETP.GE.U32.AND P0, PT, R8, 0x4, PT ?trans1;
LOP3.LUT R6, R2, 0x3, RZ, 0xc0, !PT &req={1} ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R6, RZ, PT ?WAIT7_END_GROUP;
@!P0 BRA 0x370 ?trans6;
LDC.64 R4, c[0x0][0x380] &wr=0x0 ?trans1;
IADD3 R3, PT, PT, R0, R9, RZ ?trans2;
IADD3 R9, PT, PT, R9, 0x4, RZ ?WAIT3_END_GROUP;
IMAD.WIDE R4, R3, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64], RZ &rd=0x0 ?trans4;
STG.E desc[UR4][R4.64+0x4], RZ &rd=0x0 ?trans4;
STG.E desc[UR4][R4.64+0x8], RZ &rd=0x0 ?trans4;
STG.E desc[UR4][R4.64+0xc], RZ &rd=0x0 ?trans2;
@!P1 EXIT ?trans5;
ISETP.NE.AND P0, PT, R6, 0x1, PT ?trans1;
LOP3.LUT R2, R2, 0x1, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.U32.AND P1, PT, R2, 0x1, PT ?WAIT7_END_GROUP;
@P0 LDC.64 R4, c[0x0][0x380] &req={0} &wr=0x0 ?trans1;
@P0 IADD3 R3, PT, PT, R0, R9, RZ ?WAIT5_END_GROUP;
@P0 IMAD.WIDE R4, R3, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
@P0 STG.E desc[UR4][R4.64], RZ &rd=0x0 ?trans4;
@P0 STG.E desc[UR4][R4.64+0x4], RZ &rd=0x0 ?trans1;
@P1 EXIT ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans1;
@P0 IADD3 R9, PT, PT, R9, 0x2, RZ ?WAIT4_END_GROUP;
IADD3 R9, PT, PT, R0, R9, RZ ?WAIT5_END_GROUP;
IMAD.WIDE R2, R9, 0x4, R2 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], RZ ?trans1;
EXIT ?trans5;
BRA 0x470;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: initialize_grad(float*, int, int)
_Z15initialize_gradPfii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b32 s5, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s4, 16
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_load_b64 s[2:3], s[0:1], 0x8
v_mad_u64_u32 v[3:4], null, v2, s5, s[14:15]
v_and_b32_e32 v2, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v3, s4, v[2:3]
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s2, 0
v_cmp_gt_i32_e32 vcc_lo, s3, v0
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, vcc_lo, s3
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB9_3
s_load_b64 s[0:1], s[0:1], 0x0
v_mul_lo_u32 v0, v0, s2
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
.LBB9_2:
global_store_b32 v[0:1], v2, off
v_add_co_u32 v0, vcc_lo, v0, 4
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s2, 0
s_cbranch_scc1 .LBB9_2
.LBB9_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| initialize_grad | 1,834 | 817 | stackv2-00000-of-00015 |
// Demangled: max(float*, float*, int, int)
Function : _Z3maxPfS_ii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.Y &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.Y &wr=0x1 ?trans1;
S2R R5, SR_CTAID.X &wr=0x2 ?trans1;
S2R R7, SR_TID.X &wr=0x3 ?trans6;
LDC R0, c[0x0][0x364] &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x370] &wr=0x2 ?trans1;
LDCU UR6, c[0x0][0x360] &wr=0x3 ?trans6;
LDC.64 R10, c[0x0][0x390] &wr=0x4 ?trans1;
IMAD R0, R0, UR4, R3 &req={1} ?WAIT4_END_GROUP;
IMAD R0, R0, UR5, R5 &req={2} ?trans1;
ISETP.GE.AND P0, PT, R10, 0x1, PT &req={4} ?WAIT3_END_GROUP;
IMAD R7, R0, UR6, R7 &req={3} ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R7, R11, !P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x388] &wr=0x0 ?trans1;
ISETP.GE.U32.AND P1, PT, R10.reuse, 0x8, PT ?trans1;
LOP3.LUT R16, R10, 0x7, RZ, 0xc0, !PT ?trans1;
IMAD R9, R7.reuse, R10, RZ ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans3;
ISETP.NE.AND P0, PT, R16, RZ, PT ?trans1;
LDC.64 R4, c[0x0][0x380] &wr=0x2 ?trans1;
IMAD.WIDE R2, R7, 0x4, R2 &req={0} ?WAIT4_END_GROUP;
HFMA2 R7, -RZ, RZ, 0, 0 ?trans2;
IMAD.WIDE R4, R9, 0x4, R4 &req={2} ?trans1;
@!P1 BRA 0x560 &req={1} ?trans6;
LDCU.64 UR6, c[0x0][0x380] &wr=0x0 ?trans1;
SHF.R.S32.HI R0, RZ, 0x1f, R9 ?trans1;
MOV R7, RZ ?trans1;
LEA R8, P1, R9, UR6, 0x2 &req={0} ?WAIT4_END_GROUP;
LEA.HI.X R9, R9, UR7, R0, 0x2, P1 ?trans2;
LOP3.LUT R0, R10, 0x7ffffff8, RZ, 0xc0, !PT ?WAIT3_END_GROUP;
IADD.64 R8, R8, 0x10 ?WAIT3_END_GROUP;
IADD3 R0, PT, PT, -R0, RZ, RZ ?WAIT7_END_GROUP;
LDG.E R11, desc[UR4][R4.64] &wr=0x2 ?trans4;
STG.E desc[UR4][R2.64], R11 &req={2} &rd=0x0 ?trans4;
LDG.E R6, desc[UR4][R8.64+-0x10] &wr=0x2 ?trans2;
FSETP.GEU.AND P1, PT, R11, R6, PT &req={2} ?WAIT13_END_GROUP;
@!P1 STG.E desc[UR4][R2.64], R6 ?trans4;
@!P1 LDG.E R11, desc[UR4][R4.64] &req={0} &wr=0x2 ?trans4;
STG.E desc[UR4][R2.64], R11 &req={2} &rd=0x0 ?trans4;
LDG.E R13, desc[UR4][R4.64] &wr=0x2 ?trans4;
LDG.E R10, desc[UR4][R8.64+-0xc] &wr=0x2 ?trans2;
FSETP.GEU.AND P1, PT, R13, R10, PT &req={2} ?WAIT13_END_GROUP;
@!P1 STG.E desc[UR4][R2.64], R10 ?trans4;
@!P1 LDG.E R13, desc[UR4][R4.64] &wr=0x2 ?trans4;
STG.E desc[UR4][R2.64], R13 &req={2} &rd=0x1 ?trans4;
LDG.E R15, desc[UR4][R4.64] &wr=0x2 ?trans4;
LDG.E R12, desc[UR4][R8.64+-0x8] &wr=0x2 ?trans2;
FSETP.GEU.AND P1, PT, R15, R12, PT &req={2} ?WAIT13_END_GROUP;
@!P1 STG.E desc[UR4][R2.64], R12 ?trans4;
@!P1 LDG.E R15, desc[UR4][R4.64] &wr=0x2 ?trans4;
STG.E desc[UR4][R2.64], R15 &req={2} &rd=0x2 ?trans4;
LDG.E R11, desc[UR4][R4.64] &req={0} &wr=0x3 ?trans4;
LDG.E R6, desc[UR4][R8.64+-0x4] &wr=0x3 ?trans2;
FSETP.GEU.AND P1, PT, R11, R6, PT &req={3} ?WAIT13_END_GROUP;
@!P1 STG.E desc[UR4][R2.64], R6 ?trans4;
@!P1 LDG.E R11, desc[UR4][R4.64] &wr=0x3 ?trans4;
STG.E desc[UR4][R2.64], R11 &req={3} &rd=0x0 ?trans4;
LDG.E R13, desc[UR4][R4.64] &req={1} &wr=0x3 ?trans4;
LDG.E R10, desc[UR4][R8.64] &wr=0x3 ?trans2;
FSETP.GEU.AND P1, PT, R13, R10, PT &req={3} ?WAIT13_END_GROUP;
@!P1 STG.E desc[UR4][R2.64], R10 ?trans4;
@!P1 LDG.E R13, desc[UR4][R4.64] &wr=0x3 ?trans4;
STG.E desc[UR4][R2.64], R13 &req={3} &rd=0x1 ?trans4;
LDG.E R15, desc[UR4][R4.64] &req={2} &wr=0x2 ?trans4;
LDG.E R12, desc[UR4][R8.64+0x4] &wr=0x2 ?trans2;
FSETP.GEU.AND P1, PT, R15, R12, PT &req={2} ?WAIT13_END_GROUP;
@!P1 STG.E desc[UR4][R2.64], R12 &rd=0x2 ?trans4;
@!P1 LDG.E R15, desc[UR4][R4.64] &wr=0x3 ?trans4;
STG.E desc[UR4][R2.64], R15 &req={3} &rd=0x2 ?trans4;
LDG.E R11, desc[UR4][R4.64] &req={0} &wr=0x3 ?trans4;
LDG.E R14, desc[UR4][R8.64+0x8] &wr=0x3 ?trans2;
FSETP.GEU.AND P1, PT, R11, R14, PT &req={3} ?WAIT13_END_GROUP;
@!P1 STG.E desc[UR4][R2.64], R14 &rd=0x2 ?trans4;
@!P1 LDG.E R11, desc[UR4][R4.64] &wr=0x3 ?trans4;
STG.E desc[UR4][R2.64], R11 &req={3} &rd=0x2 ?trans4;
LDG.E R6, desc[UR4][R4.64] &wr=0x3 ?trans4;
LDG.E R13, desc[UR4][R8.64+0xc] &req={1} &rd=0x0 &wr=0x3 ?trans1;
IADD3 R0, PT, PT, R0, 0x8, RZ ?WAIT2_END_GROUP;
IADD3 R7, PT, PT, R7, 0x8, RZ ?trans1;
IADD.64 R8, R8, 0x20 &req={0} ?trans2;
FSETP.GEU.AND P1, PT, R6, R13, PT &req={3} ?WAIT13_END_GROUP;
@!P1 STG.E desc[UR4][R2.64], R13 &rd=0x2 ?trans1;
ISETP.NE.AND P1, PT, R0, RZ, PT ?WAIT13_END_GROUP;
@P1 BRA 0x220 &req={2} ?trans5;
@!P0 EXIT ?trans5;
LDC R12, c[0x0][0x390] &wr=0x0 ?trans1;
ISETP.GE.U32.AND P1, PT, R16, 0x4, PT ?trans1;
LOP3.LUT R14, R12, 0x3, RZ, 0xc0, !PT &req={0} ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R14, RZ, PT ?WAIT7_END_GROUP;
@!P1 BRA 0x750 ?trans6;
LDG.E R11, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE R8, R7, 0x4, R4 ?WAIT3_END_GROUP;
STG.E desc[UR4][R2.64], R11 &req={2} &rd=0x0 ?trans4;
LDG.E R0, desc[UR4][R8.64] &wr=0x2 ?trans2;
FSETP.GEU.AND P1, PT, R11, R0, PT &req={2} ?WAIT13_END_GROUP;
@!P1 STG.E desc[UR4][R2.64], R0 ?trans4;
@!P1 LDG.E R11, desc[UR4][R4.64] &req={0} &wr=0x2 ?trans4;
STG.E desc[UR4][R2.64], R11 &req={2} &rd=0x0 ?trans4;
LDG.E R13, desc[UR4][R4.64] &wr=0x2 ?trans4;
LDG.E R6, desc[UR4][R8.64+0x4] &wr=0x2 ?trans2;
FSETP.GEU.AND P1, PT, R13, R6, PT &req={2} ?WAIT13_END_GROUP;
@!P1 STG.E desc[UR4][R2.64], R6 &rd=0x1 ?trans4;
@!P1 LDG.E R13, desc[UR4][R4.64] &wr=0x2 ?trans4;
STG.E desc[UR4][R2.64], R13 &req={2} &rd=0x1 ?trans4;
LDG.E R15, desc[UR4][R4.64] &wr=0x2 ?trans4;
LDG.E R10, desc[UR4][R8.64+0x8] &wr=0x2 ?trans2;
FSETP.GEU.AND P1, PT, R15, R10, PT &req={2} ?WAIT13_END_GROUP;
@!P1 STG.E desc[UR4][R2.64], R10 &rd=0x1 ?trans4;
@!P1 LDG.E R15, desc[UR4][R4.64] &wr=0x2 ?trans4;
STG.E desc[UR4][R2.64], R15 &req={2} &rd=0x1 ?trans4;
LDG.E R11, desc[UR4][R8.64+0xc] &req={0} &wr=0x2 ?trans4;
LDG.E R0, desc[UR4][R4.64] &wr=0x2 ?trans1;
IADD3 R7, PT, PT, R7, 0x4, RZ ?trans1;
FSETP.GEU.AND P1, PT, R0, R11, PT &req={2} ?WAIT13_END_GROUP;
@!P1 STG.E desc[UR4][R2.64], R11 &rd=0x1 ?trans2;
@!P0 EXIT ?trans5;
ISETP.NE.AND P1, PT, R14, 0x1, PT ?trans1;
LOP3.LUT R0, R12, 0x1, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.U32.AND P0, PT, R0, 0x1, PT ?WAIT7_END_GROUP;
@!P1 BRA 0x870 ?trans6;
LDG.E R11, desc[UR4][R4.64] &req={1} &wr=0x2 ?trans1;
IMAD.WIDE R8, R7, 0x4, R4 ?WAIT3_END_GROUP;
STG.E desc[UR4][R2.64], R11 &req={2} &rd=0x0 ?trans4;
LDG.E R6, desc[UR4][R8.64] &wr=0x2 ?trans2;
FSETP.GEU.AND P1, PT, R11, R6, PT &req={2} ?WAIT13_END_GROUP;
@!P1 STG.E desc[UR4][R2.64], R6 &rd=0x2 ?trans4;
@!P1 LDG.E R11, desc[UR4][R4.64] &req={0} &wr=0x3 ?trans4;
STG.E desc[UR4][R2.64], R11 &req={3} &rd=0x2 ?trans4;
LDG.E R13, desc[UR4][R8.64+0x4] &wr=0x3 ?trans4;
LDG.E R0, desc[UR4][R4.64] &wr=0x3 ?trans1;
IADD3 R7, PT, PT, R7, 0x2, RZ ?trans1;
FSETP.GEU.AND P1, PT, R0, R13, PT &req={3} ?WAIT13_END_GROUP;
@!P1 STG.E desc[UR4][R2.64], R13 &rd=0x2 ?trans2;
@P0 EXIT ?trans5;
LDG.E R9, desc[UR4][R4.64] &wr=0x3 ?trans1;
IMAD.WIDE R6, R7, 0x4, R4 &req={2,1} ?WAIT3_END_GROUP;
STG.E desc[UR4][R2.64], R9 &req={3} &rd=0x0 ?trans4;
LDG.E R6, desc[UR4][R6.64] &wr=0x2 ?trans2;
FSETP.GEU.AND P0, PT, R9, R6, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
STG.E desc[UR4][R2.64], R6 ?trans1;
EXIT ?trans5;
BRA 0x900;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: max(float*, float*, int, int)
_Z3maxPfS_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s5, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s4, 16
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_load_b64 s[2:3], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v2, s5, s[14:15]
v_and_b32_e32 v2, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v3, s4, v[2:3]
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s2, 0
v_cmp_gt_i32_e32 vcc_lo, s3, v0
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, vcc_lo, s3
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB2_5
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v5, vcc_lo
v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
.LBB2_2:
global_load_b32 v7, v[0:1], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v7, off
global_load_b32 v6, v[4:5], off
s_waitcnt vmcnt(0)
v_cmpx_lt_f32_e32 v7, v6
s_cbranch_execz .LBB2_4
global_store_b32 v[2:3], v6, off
.LBB2_4:
s_or_b32 exec_lo, exec_lo, s0
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s2, 0
s_cbranch_scc1 .LBB2_2
.LBB2_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| max | 4,118 | 1,080 | stackv2-00000-of-00015 |
// Demangled: normalize(float*, float*, int, int)
Function : _Z9normalizePfS_ii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.Y &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.Y &wr=0x1 ?trans1;
S2R R7, SR_CTAID.X &wr=0x2 ?trans1;
S2R R9, SR_TID.X &wr=0x3 ?trans6;
LDC R0, c[0x0][0x364] &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x370] &wr=0x2 ?trans1;
LDCU UR6, c[0x0][0x360] &wr=0x3 ?trans6;
LDC.64 R4, c[0x0][0x390] &wr=0x4 ?trans1;
IMAD R0, R0, UR4, R3 &req={1} ?WAIT4_END_GROUP;
IMAD R0, R0, UR5, R7 &req={2} ?trans1;
ISETP.GE.AND P0, PT, R4, 0x1, PT &req={4} ?WAIT3_END_GROUP;
IMAD R7, R0, UR6, R9 &req={3} ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R7, R5, !P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x388] &wr=0x0 ?trans1;
ISETP.GE.U32.AND P1, PT, R4.reuse, 0x10, PT ?trans1;
LOP3.LUT R14, R4, 0xf, RZ, 0xc0, !PT ?trans1;
UMOV UR4, URZ ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD R0, R7.reuse, R4, RZ ?trans2;
ISETP.NE.AND P0, PT, R14, RZ, PT ?trans1;
IMAD.WIDE R2, R7, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
@!P1 BRA 0x640 &req={1} ?trans6;
LDC.64 R6, c[0x0][0x380] &wr=0x0 ?trans1;
LOP3.LUT R10, R4, 0x7ffffff0, RZ, 0xc0, !PT ?trans1;
UMOV UR4, URZ ?trans1;
MOV R5, R0 ?trans2;
IADD3 R10, PT, PT, -R10, RZ, RZ ?trans1;
IADD.64 R6, R6, 0x20 &req={0} ?WAIT8_END_GROUP;
IMAD.WIDE R8, R5, 0x4, R6 &req={0} ?trans1;
LDG.E R11, desc[UR6][R2.64] &wr=0x2 ?trans4;
LDG.E R12, desc[UR6][R8.64+-0x20] &wr=0x2 ?trans4;
LDG.E R13, desc[UR6][R8.64+-0x1c] &wr=0x3 ?trans4;
LDG.E R15, desc[UR6][R8.64+-0x18] &wr=0x4 ?trans4;
LDG.E R17, desc[UR6][R8.64+-0x14] &wr=0x5 ?trans1;
FADD R11, -R11, R12 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R8.64+-0x20], R11 ?trans4;
LDG.E R12, desc[UR6][R2.64] &wr=0x3 ?trans2;
FADD R13, -R12, R13 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R8.64+-0x1c], R13 &rd=0x0 ?trans4;
LDG.E R12, desc[UR6][R2.64] &wr=0x4 ?trans4;
LDG.E R13, desc[UR6][R8.64+-0xc] &req={0} &wr=0x2 ?trans1;
FADD R15, -R12, R15 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R8.64+-0x18], R15 &rd=0x0 ?trans4;
LDG.E R12, desc[UR6][R2.64] &wr=0x5 ?trans4;
LDG.E R15, desc[UR6][R8.64+-0x8] &req={0} &wr=0x3 ?trans1;
FADD R17, -R12, R17 &req={5} ?WAIT3_END_GROUP;
LDG.E R12, desc[UR6][R8.64+-0x10] &wr=0x4 ?trans4;
STG.E desc[UR6][R8.64+-0x14], R17 &rd=0x0 ?trans4;
LDG.E R11, desc[UR6][R2.64] &wr=0x4 ?trans4;
LDG.E R17, desc[UR6][R8.64+-0x4] &req={0} &wr=0x5 ?trans1;
FADD R11, -R11, R12 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R8.64+-0x10], R11 ?trans4;
LDG.E R12, desc[UR6][R2.64] &wr=0x2 ?trans2;
FADD R13, -R12, R13 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R8.64+-0xc], R13 &rd=0x0 ?trans4;
LDG.E R12, desc[UR6][R2.64] &wr=0x3 ?trans4;
LDG.E R13, desc[UR6][R8.64+0x4] &req={0} &wr=0x2 ?trans1;
FADD R15, -R12, R15 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R8.64+-0x8], R15 &rd=0x0 ?trans4;
LDG.E R12, desc[UR6][R2.64] &wr=0x5 ?trans4;
LDG.E R15, desc[UR6][R8.64+0x8] &req={0} &wr=0x3 ?trans1;
FADD R17, -R12, R17 &req={5} ?WAIT3_END_GROUP;
LDG.E R12, desc[UR6][R8.64] &wr=0x4 ?trans4;
STG.E desc[UR6][R8.64+-0x4], R17 &rd=0x0 ?trans4;
LDG.E R11, desc[UR6][R2.64] &wr=0x4 ?trans4;
LDG.E R17, desc[UR6][R8.64+0xc] &req={0} &wr=0x5 ?trans1;
FADD R11, -R11, R12 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R8.64], R11 ?trans4;
LDG.E R12, desc[UR6][R2.64] &wr=0x2 ?trans2;
FADD R13, -R12, R13 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R8.64+0x4], R13 &rd=0x0 ?trans4;
LDG.E R12, desc[UR6][R2.64] &wr=0x3 ?trans4;
LDG.E R13, desc[UR6][R8.64+0x14] &req={0} &wr=0x2 ?trans1;
FADD R15, -R12, R15 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R8.64+0x8], R15 &rd=0x0 ?trans4;
LDG.E R12, desc[UR6][R2.64] &wr=0x5 ?trans4;
LDG.E R15, desc[UR6][R8.64+0x18] &req={0} &wr=0x3 ?trans1;
FADD R17, -R12, R17 &req={5} ?WAIT3_END_GROUP;
LDG.E R12, desc[UR6][R8.64+0x10] &wr=0x4 ?trans4;
STG.E desc[UR6][R8.64+0xc], R17 &rd=0x0 ?trans4;
LDG.E R11, desc[UR6][R2.64] &wr=0x4 ?trans4;
LDG.E R17, desc[UR6][R8.64+0x1c] &req={0} &wr=0x5 ?trans1;
FADD R11, -R11, R12 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R8.64+0x10], R11 &rd=0x0 ?trans4;
LDG.E R12, desc[UR6][R2.64] &wr=0x2 ?trans2;
FADD R13, -R12, R13 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R8.64+0x14], R13 &rd=0x0 ?trans4;
LDG.E R12, desc[UR6][R2.64] &wr=0x3 ?trans1;
IADD3 R10, PT, PT, R10, 0x10, RZ ?trans1;
FADD R15, -R12, R15 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R8.64+0x18], R15 &rd=0x0 ?trans4;
LDG.E R12, desc[UR6][R2.64] &wr=0x5 ?trans1;
ISETP.NE.AND P1, PT, R10, RZ, PT ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x10, URZ ?trans1;
IADD3 R5, PT, PT, R5, 0x10, RZ ?trans1;
FADD R17, -R12, R17 &req={5} ?WAIT5_END_GROUP;
STG.E desc[UR6][R8.64+0x1c], R17 &rd=0x0 ?trans5;
@P1 BRA 0x1e0 ?trans5;
@!P0 EXIT ?trans5;
ISETP.GE.U32.AND P0, PT, R14, 0x8, PT ?trans1;
LOP3.LUT R10, R4, 0x7, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R10, RZ, PT ?WAIT7_END_GROUP;
@!P0 BRA 0x8d0 ?trans6;
LDC.64 R6, c[0x0][0x380] &wr=0x1 ?trans1;
IADD3 R5, PT, PT, R0, UR4, RZ ?WAIT5_END_GROUP;
IMAD.WIDE R6, R5, 0x4, R6 &req={1} ?trans2;
LDG.E R5, desc[UR6][R2.64] &wr=0x2 ?trans4;
LDG.E R8, desc[UR6][R6.64] &req={0} &wr=0x2 ?trans4;
LDG.E R9, desc[UR6][R6.64+0x4] &wr=0x3 ?trans4;
LDG.E R11, desc[UR6][R6.64+0x8] &wr=0x4 ?trans4;
LDG.E R13, desc[UR6][R6.64+0xc] &wr=0x5 ?trans1;
FADD R5, -R5, R8 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R5 ?trans4;
LDG.E R8, desc[UR6][R2.64] &wr=0x3 ?trans2;
FADD R9, -R8, R9 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64+0x4], R9 &rd=0x0 ?trans4;
LDG.E R8, desc[UR6][R2.64] &wr=0x4 ?trans4;
LDG.E R9, desc[UR6][R6.64+0x14] &req={0} &wr=0x2 ?trans1;
FADD R11, -R8, R11 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64+0x8], R11 &rd=0x0 ?trans4;
LDG.E R8, desc[UR6][R2.64] &wr=0x5 ?trans4;
LDG.E R11, desc[UR6][R6.64+0x18] &req={0} &wr=0x3 ?trans1;
FADD R13, -R8, R13 &req={5} ?WAIT3_END_GROUP;
LDG.E R8, desc[UR6][R6.64+0x10] &wr=0x4 ?trans4;
STG.E desc[UR6][R6.64+0xc], R13 &rd=0x0 ?trans4;
LDG.E R5, desc[UR6][R2.64] &wr=0x4 ?trans4;
LDG.E R13, desc[UR6][R6.64+0x1c] &req={0} &wr=0x5 ?trans1;
FADD R5, -R5, R8 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64+0x10], R5 &rd=0x1 ?trans4;
LDG.E R8, desc[UR6][R2.64] &wr=0x2 ?trans2;
FADD R9, -R8, R9 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64+0x14], R9 &rd=0x1 ?trans4;
LDG.E R8, desc[UR6][R2.64] &wr=0x3 ?trans2;
FADD R11, -R8, R11 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64+0x18], R11 &rd=0x1 ?trans4;
LDG.E R8, desc[UR6][R2.64] &wr=0x5 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x8, URZ ?trans1;
FADD R13, -R8, R13 &req={5} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64+0x1c], R13 &rd=0x1 ?trans6;
@!P1 EXIT ?trans5;
ISETP.GE.U32.AND P0, PT, R10, 0x4, PT ?trans1;
LOP3.LUT R8, R4, 0x3, RZ, 0xc0, !PT &req={0} ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R8, RZ, PT ?WAIT7_END_GROUP;
@!P0 BRA 0xa60 ?trans6;
LDC.64 R4, c[0x0][0x380] &req={1} &wr=0x0 ?trans1;
IADD3 R7, PT, PT, R0, UR4, RZ ?trans1;
LDG.E R6, desc[UR6][R2.64] &wr=0x2 ?trans4;
IMAD.WIDE R4, R7, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
LDG.E R7, desc[UR6][R4.64] &wr=0x2 ?trans4;
LDG.E R9, desc[UR6][R4.64+0x4] &wr=0x3 ?trans4;
LDG.E R11, desc[UR6][R4.64+0x8] &wr=0x4 ?trans4;
LDG.E R13, desc[UR6][R4.64+0xc] &wr=0x5 ?trans1;
FADD R7, -R6, R7 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R4.64], R7 &rd=0x0 ?trans4;
LDG.E R6, desc[UR6][R2.64] &wr=0x3 ?trans2;
FADD R9, -R6, R9 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R4.64+0x4], R9 &rd=0x0 ?trans4;
LDG.E R6, desc[UR6][R2.64] &wr=0x4 ?trans2;
FADD R11, -R6, R11 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R4.64+0x8], R11 &rd=0x0 ?trans4;
LDG.E R6, desc[UR6][R2.64] &wr=0x5 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x4, URZ ?trans1;
FADD R13, -R6, R13 &req={5} ?WAIT5_END_GROUP;
STG.E desc[UR6][R4.64+0xc], R13 &rd=0x0 ?trans6;
@!P1 EXIT ?trans5;
LDC.64 R6, c[0x0][0x380] &req={1,0} &wr=0x0 ?trans1;
IADD3 R9, PT, PT, R0, UR4, RZ ?trans2;
IADD3 R8, PT, PT, -R8, RZ, RZ ?WAIT7_END_GROUP;
IMAD.WIDE R4, R9.reuse, 0x4, R6 &req={1,0} ?trans1;
LDG.E R0, desc[UR6][R2.64] &wr=0x2 ?trans4;
LDG.E R11, desc[UR6][R4.64] &wr=0x2 ?trans1;
IADD3 R8, PT, PT, R8, 0x1, RZ ?trans2;
IADD3 R9, PT, PT, R9, 0x1, RZ ?WAIT3_END_GROUP;
ISETP.NE.AND P0, PT, R8, RZ, PT ?trans1;
FADD R11, -R0, R11 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R4.64], R11 &rd=0x1 ?trans7;
@P0 BRA 0xaa0 ?trans5;
EXIT ?trans5;
BRA 0xb40;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: normalize(float*, float*, int, int)
_Z9normalizePfS_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s5, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s4, 16
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_load_b64 s[2:3], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v2, s5, s[14:15]
v_and_b32_e32 v2, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v3, s4, v[2:3]
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s2, 0
v_cmp_gt_i32_e32 vcc_lo, s3, v0
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, vcc_lo, s3
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB3_3
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.LBB3_2:
global_load_b32 v4, v[0:1], off
global_load_b32 v5, v[2:3], off
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s2, 0
s_waitcnt vmcnt(0)
v_sub_f32_e32 v4, v5, v4
global_store_b32 v[2:3], v4, off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_cbranch_scc1 .LBB3_2
.LBB3_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| normalize | 4,919 | 1,002 | stackv2-00000-of-00015 |
// Demangled: softmax_sum(float*, float*, int, int)
Function : _Z11softmax_sumPfS_ii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.Y &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.Y &wr=0x1 ?trans1;
LDCU UR7, c[0x0][0x394] &wr=0x2 ?trans1;
S2R R5, SR_CTAID.X &wr=0x3 ?trans1;
S2R R7, SR_TID.X &wr=0x4 ?trans5;
LDC R0, c[0x0][0x364] &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x370] &wr=0x3 ?trans1;
LDCU UR6, c[0x0][0x360] &wr=0x4 ?trans1;
IMAD R0, R0, UR4, R3 &req={1} ?WAIT4_END_GROUP;
IMAD R0, R0, UR5, R5 &req={3} ?WAIT4_END_GROUP;
IMAD R4, R0, UR6, R7 &req={4} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R4, UR7, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC R5, c[0x0][0x390] &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x1 ?trans1;
HFMA2 R0, -RZ, RZ, 0, 0 ?trans1;
ISETP.GE.AND P0, PT, R5, 0x1, PT &req={0} ?WAIT13_END_GROUP;
@!P0 BRA 0xcc0 &req={1} ?trans5;
ISETP.GE.U32.AND P1, PT, R5.reuse, 0x8, PT ?trans1;
LOP3.LUT R26, R5, 0x7, RZ, 0xc0, !PT ?trans1;
UMOV UR4, URZ ?trans1;
IMAD R6, R4, R5, RZ ?trans1;
MOV R0, RZ ?trans2;
ISETP.NE.AND P0, PT, R26, RZ, PT ?WAIT7_END_GROUP;
@!P1 BRA 0x710 ?trans6;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LOP3.LUT R8, R5, 0x7ffffff8, RZ, 0xc0, !PT ?trans1;
UMOV UR4, URZ ?trans1;
MOV R0, RZ ?trans1;
MOV R7, R6 ?trans1;
IADD3 R8, PT, PT, -R8, RZ, RZ ?trans1;
IADD.64 R2, R2, 0x10 &req={0} ?WAIT8_END_GROUP;
IMAD.WIDE R22, R7, 0x4, R2 ?WAIT5_END_GROUP;
LDG.E R16, desc[UR6][R22.64+-0x10] &wr=0x2 ?trans4;
LDG.E R24, desc[UR6][R22.64+-0xc] &wr=0x3 ?trans4;
LDG.E R20, desc[UR6][R22.64+-0x8] &wr=0x4 ?trans4;
LDG.E R18, desc[UR6][R22.64+-0x4] &wr=0x5 ?trans4;
LDG.E R14, desc[UR6][R22.64] &wr=0x5 ?trans4;
LDG.E R11, desc[UR6][R22.64+0x4] &wr=0x5 ?trans4;
LDG.E R9, desc[UR6][R22.64+0x8] &wr=0x5 ?trans4;
LDG.E R10, desc[UR6][R22.64+0xc] &rd=0x0 &wr=0x5 ?trans1;
HFMA2 R15, -RZ, RZ, 0.96630859375, -0.0022525787353515625 ?trans1;
MOV R13, 0x437c0000 ?trans1;
IADD3 R8, PT, PT, R8, 0x8, RZ ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x8, URZ ?trans1;
IADD3 R7, PT, PT, R7, 0x8, RZ ?WAIT3_END_GROUP;
ISETP.NE.AND P1, PT, R8, RZ, PT ?trans1;
FFMA.SAT R12, R16, R15, 0.5 &req={2} ?WAIT4_END_GROUP;
FFMA.RM R17, R12, R13, 12582913 ?trans1;
FFMA.SAT R12, R24, R15, 0.5 &req={3} ?WAIT3_END_GROUP;
FADD R19, R17.reuse, -12583039 ?trans1;
FFMA.RM R12, R12, R13, 12582913 ?trans1;
FFMA.SAT R28, R20, R15, 0.5 &req={4} ?trans1;
SHF.L.U32 R17, R17, 0x17, RZ ?trans1;
FFMA R19, R16, 1.4426950216293334961, -R19 ?trans1;
FADD R25, R12.reuse, -12583039 ?trans1;
SHF.L.U32 R12, R12, 0x17, RZ ?trans2;
FFMA R21, R16, 1.925963033500011079e-08, R19 ?trans1;
FFMA.RM R16, R28, R13, 12582913 ?trans1;
FFMA R25, R24, 1.4426950216293334961, -R25 ?trans1;
FFMA.SAT R28, R18, R15, 0.5 &req={5} ?WAIT2_END_GROUP;
FADD R23, R16, -12583039 &req={0} ?trans1;
FFMA R22, R24, 1.925963033500011079e-08, R25 ?trans1;
FFMA.RM R19, R28, R13, 12582913 ?trans1;
FFMA.SAT R24, R14, R15.reuse, 0.5 ?trans1;
FFMA R23, R20.reuse, 1.4426950216293334961, -R23 ?trans1;
MUFU.EX2 R21, R21 &wr=0x0 ?trans1;
FADD R25, R19, -12583039 ?trans1;
FFMA.SAT R28, R11, R15, 0.5 ?trans1;
FFMA R23, R20, 1.925963033500011079e-08, R23 ?trans1;
FFMA.RM R20, R24, R13, 12582913 ?trans1;
FFMA R25, R18, 1.4426950216293334961, -R25 ?trans1;
FFMA.SAT R30, R9, R15.reuse, 0.5 ?trans1;
FFMA.SAT R32, R10, R15, 0.5 ?trans1;
FADD R27, R20, -12583039 ?trans1;
FFMA R24, R18, 1.925963033500011079e-08, R25 ?trans1;
MUFU.EX2 R22, R22 &wr=0x1 ?trans1;
FFMA.RM R18, R28, R13, 12582913 ?trans1;
FFMA R27, R14, 1.4426950216293334961, -R27 ?WAIT3_END_GROUP;
FADD R28, R18, -12583039 ?trans1;
FFMA R25, R14, 1.925963033500011079e-08, R27 ?trans1;
FFMA.RM R14, R30, R13.reuse, 12582913 ?trans1;
MUFU.EX2 R23, R23 &wr=0x2 ?trans1;
FFMA R28, R11, 1.4426950216293334961, -R28 ?trans1;
FFMA.RM R13, R32, R13, 12582913 ?trans1;
FADD R30, R14, -12583039 ?trans1;
FFMA R17, R17, R21, R0 &req={0} ?trans1;
FFMA R11, R11, 1.925963033500011079e-08, R28 ?trans1;
FADD R15, R13, -12583039 ?trans1;
FFMA R30, R9, 1.4426950216293334961, -R30 ?trans1;
MUFU.EX2 R24, R24 &wr=0x0 ?trans1;
SHF.L.U32 R0, R19, 0x17, RZ ?trans1;
FFMA R15, R10, 1.4426950216293334961, -R15 ?trans1;
FFMA R30, R9, 1.925963033500011079e-08, R30 ?trans1;
SHF.L.U32 R9, R16, 0x17, RZ ?trans1;
FFMA R12, R12, R22, R17 &req={1} ?trans1;
FFMA R10, R10, 1.925963033500011079e-08, R15 ?trans1;
SHF.L.U32 R15, R18, 0x17, RZ ?trans1;
MUFU.EX2 R25, R25 &wr=0x1 ?trans1;
SHF.L.U32 R13, R13, 0x17, RZ ?trans1;
FFMA R9, R9, R23, R12 &req={2} ?trans1;
MUFU.EX2 R11, R11 &wr=0x2 ?trans3;
FFMA R0, R0, R24, R9 &req={0} ?trans1;
SHF.L.U32 R9, R20, 0x17, RZ ?trans1;
MUFU.EX2 R30, R30 &wr=0x0 ?trans4;
FFMA R0, R9, R25, R0 &req={1} ?trans1;
SHF.L.U32 R9, R14, 0x17, RZ ?trans1;
MUFU.EX2 R10, R10 &wr=0x1 ?trans2;
FFMA R0, R15, R11, R0 &req={2} ?WAIT4_END_GROUP;
FFMA R0, R9, R30, R0 &req={0} ?WAIT4_END_GROUP;
FFMA R0, R13, R10, R0 &req={1} ?trans1;
@P1 BRA 0x210 ?trans6;
@!P0 BRA 0xcc0 ?trans5;
ISETP.GE.U32.AND P0, PT, R26, 0x4, PT ?trans1;
LOP3.LUT R15, R5, 0x3, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R15, RZ, PT ?WAIT7_END_GROUP;
@!P0 BRA 0xa00 ?trans6;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
IADD3 R7, PT, PT, R6, UR4, RZ ?WAIT5_END_GROUP;
IMAD.WIDE R2, R7, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E R9, desc[UR6][R2.64+0x4] &wr=0x2 ?trans4;
LDG.E R7, desc[UR6][R2.64] &wr=0x3 ?trans4;
LDG.E R13, desc[UR6][R2.64+0x8] &wr=0x4 ?trans4;
LDG.E R16, desc[UR6][R2.64+0xc] &wr=0x5 ?trans1;
HFMA2 R18, -RZ, RZ, 0.96630859375, -0.0022525787353515625 ?trans1;
MOV R17, 0x437c0000 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x4, URZ ?WAIT3_END_GROUP;
FFMA.SAT R11, R9, R18.reuse, 0.5 &req={2} ?trans1;
FFMA.SAT R8, R7, R18, 0.5 &req={3} ?WAIT3_END_GROUP;
FFMA.RM R11, R11, R17.reuse, 12582913 ?trans1;
FFMA.RM R8, R8, R17, 12582913 ?WAIT3_END_GROUP;
FADD R12, R11, -12583039 ?trans1;
FFMA.SAT R14, R13, R18.reuse, 0.5 &req={4} ?trans1;
FADD R10, R8, -12583039 ?trans2;
FFMA R12, R9, 1.4426950216293334961, -R12 ?trans1;
FFMA.RM R14, R14, R17.reuse, 12582913 ?trans1;
FFMA.SAT R3, R16, R18, 0.5 &req={5} ?trans1;
FFMA R10, R7, 1.4426950216293334961, -R10 ?trans1;
FFMA R12, R9, 1.925963033500011079e-08, R12 ?trans1;
FADD R2, R14, -12583039 ?trans1;
FFMA.RM R9, R3, R17, 12582913 ?trans1;
FFMA R10, R7, 1.925963033500011079e-08, R10 ?WAIT2_END_GROUP;
FFMA R2, R13, 1.4426950216293334961, -R2 ?trans1;
FADD R3, R9, -12583039 ?WAIT3_END_GROUP;
MUFU.EX2 R10, R10 &wr=0x0 ?trans1;
FFMA R13, R13, 1.925963033500011079e-08, R2 ?trans1;
FFMA R3, R16, 1.4426950216293334961, -R3 ?WAIT4_END_GROUP;
FFMA R16, R16, 1.925963033500011079e-08, R3 ?trans1;
MUFU.EX2 R12, R12 &wr=0x1 ?trans1;
SHF.L.U32 R3, R8, 0x17, RZ ?trans1;
MUFU.EX2 R13, R13 &wr=0x2 ?trans1;
SHF.L.U32 R2, R11, 0x17, RZ ?WAIT3_END_GROUP;
FFMA R3, R3, R10, R0 &req={0} ?trans1;
MUFU.EX2 R16, R16 &wr=0x0 ?trans1;
SHF.L.U32 R7, R14, 0x17, RZ ?trans2;
FFMA R2, R2, R12, R3 &req={1} ?trans1;
SHF.L.U32 R9, R9, 0x17, RZ ?WAIT3_END_GROUP;
FFMA R2, R7, R13, R2 &req={2} ?WAIT4_END_GROUP;
FFMA R0, R9, R16, R2 &req={0} ?WAIT7_END_GROUP;
@!P1 BRA 0xcc0 ?trans5;
ISETP.NE.AND P0, PT, R15, 0x1, PT ?trans1;
LOP3.LUT R5, R5, 0x1, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.U32.AND P1, PT, R5, 0x1, PT ?WAIT7_END_GROUP;
@!P0 BRA 0xbd0 ?trans6;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
IADD3 R5, PT, PT, R6, UR4, RZ ?WAIT5_END_GROUP;
IMAD.WIDE R2, R5, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E R5, desc[UR6][R2.64] &wr=0x2 ?trans4;
LDG.E R9, desc[UR6][R2.64+0x4] &wr=0x3 ?trans1;
HFMA2 R8, -RZ, RZ, 0.96630859375, -0.0022525787353515625 ?trans1;
MOV R10, 0x437c0000 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x2, URZ ?WAIT3_END_GROUP;
FFMA.SAT R7, R5, R8, 0.5 &req={2} ?WAIT4_END_GROUP;
FFMA.RM R7, R7, R10, 12582913 ?trans1;
FFMA.SAT R11, R9, R8, 0.5 &req={3} ?WAIT3_END_GROUP;
FADD R8, R7, -12583039 ?trans1;
FFMA.RM R11, R11, R10, 12582913 ?trans1;
SHF.L.U32 R7, R7, 0x17, RZ ?trans2;
FFMA R8, R5, 1.4426950216293334961, -R8 ?trans1;
FADD R10, R11.reuse, -12583039 ?trans1;
SHF.L.U32 R11, R11, 0x17, RZ ?trans2;
FFMA R8, R5, 1.925963033500011079e-08, R8 ?trans1;
FFMA R10, R9, 1.4426950216293334961, -R10 ?WAIT4_END_GROUP;
FFMA R10, R9, 1.925963033500011079e-08, R10 ?trans1;
MUFU.EX2 R8, R8 &wr=0x0 ?trans5;
MUFU.EX2 R10, R10 &wr=0x1 ?trans1;
FFMA R0, R7, R8, R0 &req={0} ?WAIT4_END_GROUP;
FFMA R0, R11, R10, R0 &req={1} ?WAIT7_END_GROUP;
@P1 BRA 0xcc0 ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
IADD3 R5, PT, PT, R6, UR4, RZ ?WAIT5_END_GROUP;
IMAD.WIDE R2, R5, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR6][R2.64] &wr=0x2 ?trans1;
HFMA2 R5, -RZ, RZ, 0.96630859375, -0.0022525787353515625 ?trans1;
MOV R6, 0x437c0000 ?WAIT4_END_GROUP;
FFMA.SAT R5, R2, R5, 0.5 &req={2} ?WAIT4_END_GROUP;
FFMA.RM R5, R5, R6, 12582913 ?WAIT4_END_GROUP;
FADD R7, R5.reuse, -12583039 ?trans1;
SHF.L.U32 R5, R5, 0x17, RZ ?WAIT3_END_GROUP;
FFMA R7, R2, 1.4426950216293334961, -R7 ?WAIT4_END_GROUP;
FFMA R7, R2, 1.925963033500011079e-08, R7 ?WAIT6_END_GROUP;
MUFU.EX2 R7, R7 &wr=0x0 ?trans2;
FFMA R0, R5, R7, R0 &req={0} ?WAIT7_END_GROUP;
LDC.64 R2, c[0x0][0x388] &wr=0x0 ?trans2;
IMAD.WIDE R4, R4, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R4.64], R0 ?trans1;
EXIT ?trans5;
BRA 0xd00;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: softmax_sum(float*, float*, int, int)
_Z11softmax_sumPfS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_load_b64 s[4:5], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v2, s3, s[14:15]
v_and_b32_e32 v2, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v3, s2, v[2:3]
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s5, v0
s_cbranch_execz .LBB1_6
s_load_b128 s[0:3], s[0:1], 0x0
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB1_4
v_mul_lo_u32 v1, v0, s4
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
.LBB1_3:
global_load_b32 v4, v[1:2], off
s_add_i32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s4, 0
s_waitcnt vmcnt(0)
v_mul_f32_e32 v5, 0x3fb8aa3b, v4
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v4
v_rndne_f32_e32 v6, v5
v_fma_f32 v7, 0x3fb8aa3b, v4, -v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v5, v5, v6
v_fmac_f32_e32 v7, 0x32a5705f, v4
v_cvt_i32_f32_e32 v6, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v5, v7
v_exp_f32_e32 v5, v5
s_waitcnt_depctr 0xfff
v_ldexp_f32 v5, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v4
v_cndmask_b32_e32 v4, 0x7f800000, v5, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, 4
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_add_f32_e32 v3, v3, v4
s_cbranch_scc0 .LBB1_3
s_branch .LBB1_5
.LBB1_4:
v_mov_b32_e32 v3, 0
.LBB1_5:
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB1_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| softmax_sum | 5,882 | 1,422 | stackv2-00000-of-00015 |
// Demangled: weight_update(float*, float*, int, int, float)
Function : _Z13weight_updatePfS_iif
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.Y &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.Y &wr=0x1 ?trans1;
S2R R5, SR_CTAID.X &wr=0x2 ?trans1;
S2R R7, SR_TID.X &wr=0x3 ?trans6;
LDC R0, c[0x0][0x364] &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x370] &wr=0x2 ?trans1;
LDCU UR6, c[0x0][0x360] &wr=0x3 ?trans6;
LDC.64 R18, c[0x0][0x390] &wr=0x4 ?trans1;
IMAD R0, R0, UR4, R3 &req={1} ?WAIT4_END_GROUP;
IMAD R0, R0, UR5, R5 &req={2} ?trans1;
ISETP.GE.AND P0, PT, R18, 0x1, PT &req={4} ?WAIT3_END_GROUP;
IMAD R0, R0, UR6, R7 &req={3} ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R0, R19, !P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
ISETP.GE.U32.AND P0, PT, R18, 0x8, PT ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x0 ?trans1;
HFMA2 R2, -RZ, RZ, 3.390625, 0 ?trans2;
IMAD R12, R0, R18, RZ ?trans1;
LOP3.LUT R21, R18, 0x7, RZ, 0xc0, !PT ?trans1;
UMOV UR4, URZ ?WAIT7_END_GROUP;
@!P0 BRA 0xbc0 ?trans5;
LDC.64 R4, c[0x0][0x388] &wr=0x1 ?trans1;
LOP3.LUT R18, R18, 0x7ffffff8, RZ, 0xc0, !PT ?trans1;
LDCU UR5, c[0x0][0x398] &wr=0x2 ?trans1;
MOV R17, R12 ?trans2;
IADD3 R18, PT, PT, -R18, RZ, RZ ?trans1;
UMOV UR4, URZ ?trans2;
LDC.64 R6, c[0x0][0x380] &wr=0x3 ?trans1;
IADD.64 R4, R4, 0x10 &req={1} ?trans2;
IADD.64 R6, R6, 0x10 &req={3,2} ?WAIT8_END_GROUP;
IMAD.WIDE R8, R17, 0x4, R4 &req={1} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR6][R8.64+-0x10] &req={0} &wr=0x2 ?trans1;
HFMA2 R10, -RZ, RZ, 1.0341796875, -112.625 ?trans1;
BSSY.RECONVERGENT B2, 0x2e0 ?trans4;
FFMA R3, R10, -R2, 1 ?WAIT4_END_GROUP;
FFMA R3, R3, R10, 0.0099999997764825820923 ?trans1;
IMAD.WIDE R10, R17, 0x4, R6 ?trans1;
FCHK P0, R0, 100 &req={2} &wr=0x0 ?trans3;
FFMA R13, R0, R3, RZ ?WAIT4_END_GROUP;
FFMA R14, R13, -100, R0 ?WAIT4_END_GROUP;
FFMA R3, R3, R14, R13 ?trans1;
@!P0 BRA 0x2d0 &req={0} ?trans6;
MOV R14, 0x2d0 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x1660 ?trans5;
BSYNC.RECONVERGENT B2 ?trans5;
STG.E desc[UR6][R8.64+-0x10], R3 &rd=0x0 ?trans4;
LDG.E R0, desc[UR6][R10.64+-0x10] &wr=0x2 ?trans2;
FFMA R13, -R3, UR5, R0 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R10.64+-0x10], R13 &rd=0x0 ?trans4;
LDG.E R16, desc[UR6][R8.64+-0xc] &wr=0x2 ?trans1;
MOV R15, 0x3c23d70a ?trans1;
BSSY.RECONVERGENT B2, 0x410 ?trans4;
FFMA R0, R15, -R2, 1 ?WAIT4_END_GROUP;
FFMA R0, R0, R15, 0.0099999997764825820923 ?trans1;
FCHK P0, R16, 100 &req={2} &wr=0x1 ?trans3;
FFMA R15, R0, R16, RZ ?WAIT4_END_GROUP;
FFMA R14, R15, -100, R16 ?WAIT4_END_GROUP;
FFMA R15, R0, R14, R15 ?trans1;
@!P0 BRA 0x400 &req={1,0} ?trans6;
MOV R0, R16 ?trans1;
MOV R14, 0x3f0 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x1660 ?trans5;
MOV R15, R3 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
STG.E desc[UR6][R8.64+-0xc], R15 &rd=0x0 ?trans4;
LDG.E R0, desc[UR6][R10.64+-0xc] &wr=0x2 ?trans2;
FFMA R3, -R15, UR5, R0 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R10.64+-0xc], R3 &rd=0x0 ?trans4;
LDG.E R16, desc[UR6][R8.64+-0x8] &wr=0x2 ?trans1;
HFMA2 R13, -RZ, RZ, 1.0341796875, -112.625 ?trans1;
BSSY.RECONVERGENT B2, 0x540 ?trans4;
FFMA R0, R13, -R2, 1 ?WAIT4_END_GROUP;
FFMA R0, R0, R13, 0.0099999997764825820923 ?trans1;
FCHK P0, R16, 100 &req={2} &wr=0x1 ?trans3;
FFMA R13, R0, R16, RZ ?WAIT4_END_GROUP;
FFMA R14, R13, -100, R16 ?WAIT4_END_GROUP;
FFMA R13, R0, R14, R13 ?trans1;
@!P0 BRA 0x530 &req={1,0} ?trans6;
MOV R0, R16 ?trans1;
MOV R14, 0x520 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x1660 ?trans5;
MOV R13, R3 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
STG.E desc[UR6][R8.64+-0x8], R13 &rd=0x0 ?trans4;
LDG.E R0, desc[UR6][R10.64+-0x8] &wr=0x2 ?trans2;
FFMA R3, -R13, UR5, R0 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R10.64+-0x8], R3 &rd=0x0 ?trans4;
LDG.E R16, desc[UR6][R8.64+-0x4] &wr=0x2 ?trans1;
HFMA2 R15, -RZ, RZ, 1.0341796875, -112.625 ?trans1;
BSSY.RECONVERGENT B2, 0x670 ?trans4;
FFMA R0, R15, -R2, 1 ?WAIT4_END_GROUP;
FFMA R0, R0, R15, 0.0099999997764825820923 ?trans1;
FCHK P0, R16, 100 &req={2} &wr=0x1 ?trans3;
FFMA R15, R0, R16, RZ ?WAIT4_END_GROUP;
FFMA R14, R15, -100, R16 ?WAIT4_END_GROUP;
FFMA R15, R0, R14, R15 ?trans1;
@!P0 BRA 0x660 &req={1,0} ?trans6;
MOV R0, R16 ?trans1;
MOV R14, 0x650 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x1660 ?trans5;
MOV R15, R3 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
STG.E desc[UR6][R8.64+-0x4], R15 &rd=0x0 ?trans4;
LDG.E R0, desc[UR6][R10.64+-0x4] &wr=0x2 ?trans2;
FFMA R3, -R15, UR5, R0 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R10.64+-0x4], R3 &rd=0x0 ?trans4;
LDG.E R16, desc[UR6][R8.64] &wr=0x2 ?trans1;
HFMA2 R13, -RZ, RZ, 1.0341796875, -112.625 ?trans1;
BSSY.RECONVERGENT B2, 0x7a0 ?trans4;
FFMA R0, R13, -R2, 1 ?WAIT4_END_GROUP;
FFMA R0, R0, R13, 0.0099999997764825820923 ?trans1;
FCHK P0, R16, 100 &req={2} &wr=0x1 ?trans3;
FFMA R13, R0, R16, RZ ?WAIT4_END_GROUP;
FFMA R14, R13, -100, R16 ?WAIT4_END_GROUP;
FFMA R13, R0, R14, R13 ?trans1;
@!P0 BRA 0x790 &req={1,0} ?trans6;
MOV R0, R16 ?trans1;
MOV R14, 0x780 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x1660 ?trans5;
MOV R13, R3 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
STG.E desc[UR6][R8.64], R13 &rd=0x0 ?trans4;
LDG.E R0, desc[UR6][R10.64] &wr=0x2 ?trans2;
FFMA R3, -R13, UR5, R0 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R10.64], R3 &rd=0x0 ?trans4;
LDG.E R16, desc[UR6][R8.64+0x4] &wr=0x2 ?trans1;
HFMA2 R15, -RZ, RZ, 1.0341796875, -112.625 ?trans1;
BSSY.RECONVERGENT B2, 0x8d0 ?trans4;
FFMA R0, R15, -R2, 1 ?WAIT4_END_GROUP;
FFMA R0, R0, R15, 0.0099999997764825820923 ?trans1;
FCHK P0, R16, 100 &req={2} &wr=0x1 ?trans3;
FFMA R15, R0, R16, RZ ?WAIT4_END_GROUP;
FFMA R14, R15, -100, R16 ?WAIT4_END_GROUP;
FFMA R15, R0, R14, R15 ?trans1;
@!P0 BRA 0x8c0 &req={1,0} ?trans6;
MOV R0, R16 ?trans1;
MOV R14, 0x8b0 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x1660 ?trans5;
MOV R15, R3 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
STG.E desc[UR6][R8.64+0x4], R15 &rd=0x0 ?trans4;
LDG.E R0, desc[UR6][R10.64+0x4] &wr=0x2 ?trans2;
FFMA R3, -R15, UR5, R0 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R10.64+0x4], R3 &rd=0x0 ?trans4;
LDG.E R16, desc[UR6][R8.64+0x8] &wr=0x2 ?trans1;
HFMA2 R13, -RZ, RZ, 1.0341796875, -112.625 ?trans1;
BSSY.RECONVERGENT B2, 0xa00 ?trans4;
FFMA R0, R13, -R2, 1 ?WAIT4_END_GROUP;
FFMA R0, R0, R13, 0.0099999997764825820923 ?trans1;
FCHK P0, R16, 100 &req={2} &wr=0x1 ?trans3;
FFMA R13, R0, R16, RZ ?WAIT4_END_GROUP;
FFMA R14, R13, -100, R16 ?WAIT4_END_GROUP;
FFMA R13, R0, R14, R13 ?trans1;
@!P0 BRA 0x9f0 &req={1,0} ?trans6;
MOV R0, R16 ?trans1;
MOV R14, 0x9e0 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x1660 ?trans5;
MOV R13, R3 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
STG.E desc[UR6][R8.64+0x8], R13 &rd=0x0 ?trans4;
LDG.E R0, desc[UR6][R10.64+0x8] &wr=0x2 ?trans2;
FFMA R3, -R13, UR5, R0 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R10.64+0x8], R3 &rd=0x0 ?trans4;
LDG.E R16, desc[UR6][R8.64+0xc] &wr=0x2 ?trans1;
HFMA2 R15, -RZ, RZ, 1.0341796875, -112.625 ?trans1;
BSSY.RECONVERGENT B2, 0xb30 ?trans4;
FFMA R0, R15, -R2, 1 ?WAIT4_END_GROUP;
FFMA R0, R0, R15, 0.0099999997764825820923 ?trans1;
FCHK P0, R16, 100 &req={2} &wr=0x1 ?trans3;
FFMA R15, R0, R16, RZ ?WAIT4_END_GROUP;
FFMA R14, R15, -100, R16 ?WAIT4_END_GROUP;
FFMA R15, R0, R14, R15 ?trans1;
@!P0 BRA 0xb20 &req={1,0} ?trans6;
MOV R0, R16 ?trans1;
MOV R14, 0xb10 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x1660 ?trans5;
MOV R15, R3 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
STG.E desc[UR6][R8.64+0xc], R15 &rd=0x1 ?trans4;
LDG.E R0, desc[UR6][R10.64+0xc] &wr=0x2 ?trans1;
IADD3 R18, PT, PT, R18, 0x8, RZ ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x8, URZ ?trans1;
IADD3 R17, PT, PT, R17, 0x8, RZ ?WAIT3_END_GROUP;
ISETP.NE.AND P0, PT, R18, RZ, PT ?trans1;
FFMA R3, -R15, UR5, R0 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R10.64+0xc], R3 &rd=0x1 ?trans7;
@P0 BRA 0x1f0 ?trans5;
ISETP.NE.AND P0, PT, R21, RZ, PT ?WAIT13_END_GROUP;
@!P0 EXIT &req={0} ?trans5;
LDC R8, c[0x0][0x390] &req={1} &wr=0x0 ?trans1;
ISETP.GE.U32.AND P0, PT, R21, 0x4, PT ?trans1;
LOP3.LUT R8, R8, 0x3, RZ, 0xc0, !PT &req={0} ?WAIT12_END_GROUP;
@!P0 BRA 0x1170 ?trans5;
LDC.64 R4, c[0x0][0x388] &wr=0x0 ?trans1;
IADD3 R6, PT, PT, R12, UR4, RZ ?WAIT5_END_GROUP;
IMAD.WIDE R4, R6, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
LDG.E R14, desc[UR6][R4.64] &wr=0x2 ?trans1;
HFMA2 R3, -RZ, RZ, 1.0341796875, -112.625 ?trans1;
BSSY.RECONVERGENT B2, 0xd30 ?trans4;
FFMA R0, R3, -R2, 1 ?WAIT4_END_GROUP;
FFMA R0, R0, R3, 0.0099999997764825820923 ?trans1;
FCHK P0, R14, 100 &req={2} &wr=0x0 ?trans3;
FFMA R3, R0, R14, RZ ?WAIT4_END_GROUP;
FFMA R10, R3, -100, R14 ?WAIT4_END_GROUP;
FFMA R3, R0, R10, R3 ?trans1;
@!P0 BRA 0xd20 &req={0} ?trans6;
MOV R0, R14 ?trans1;
MOV R14, 0xd20 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x1660 ?trans5;
BSYNC.RECONVERGENT B2 ?trans5;
LDC.64 R10, c[0x0][0x380] &wr=0x0 ?trans1;
STG.E desc[UR6][R4.64], R3 &rd=0x1 ?trans1;
LDCU UR5, c[0x0][0x398] &wr=0x2 ?trans1;
IMAD.WIDE R6, R6, 0x4, R10 &req={0} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR6][R6.64] &wr=0x2 ?trans2;
FFMA R9, -R3, UR5, R0 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R9 &rd=0x1 ?trans4;
LDG.E R14, desc[UR6][R4.64+0x4] &wr=0x2 ?trans1;
MOV R11, 0x3c23d70a ?trans1;
BSSY.RECONVERGENT B2, 0xe90 ?trans4;
FFMA R0, R11, -R2, 1 ?WAIT4_END_GROUP;
FFMA R0, R0, R11, 0.0099999997764825820923 ?trans1;
FCHK P0, R14, 100 &req={2} &wr=0x0 ?trans3;
FFMA R11, R0, R14, RZ ?WAIT4_END_GROUP;
FFMA R10, R11, -100, R14 ?WAIT4_END_GROUP;
FFMA R11, R0, R10, R11 ?trans1;
@!P0 BRA 0xe80 &req={1,0} ?trans6;
MOV R0, R14 ?trans1;
MOV R14, 0xe70 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x1660 ?trans5;
MOV R11, R3 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
STG.E desc[UR6][R4.64+0x4], R11 &rd=0x0 ?trans1;
LDCU UR5, c[0x0][0x398] &wr=0x1 ?trans3;
LDG.E R0, desc[UR6][R6.64+0x4] &wr=0x1 ?trans2;
FFMA R3, -R11, UR5, R0 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64+0x4], R3 &rd=0x0 ?trans4;
LDG.E R14, desc[UR6][R4.64+0x8] &wr=0x2 ?trans1;
HFMA2 R9, -RZ, RZ, 1.0341796875, -112.625 ?trans1;
BSSY.RECONVERGENT B2, 0xfd0 ?trans4;
FFMA R0, R9, -R2, 1 ?WAIT4_END_GROUP;
FFMA R0, R0, R9, 0.0099999997764825820923 ?trans1;
FCHK P0, R14, 100 &req={2} &wr=0x1 ?trans3;
FFMA R9, R0, R14, RZ ?WAIT4_END_GROUP;
FFMA R10, R9, -100, R14 ?WAIT4_END_GROUP;
FFMA R9, R0, R10, R9 ?trans1;
@!P0 BRA 0xfc0 &req={1,0} ?trans6;
MOV R0, R14 ?trans1;
MOV R14, 0xfb0 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x1660 ?trans5;
MOV R9, R3 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
STG.E desc[UR6][R4.64+0x8], R9 &rd=0x0 ?trans1;
LDCU UR5, c[0x0][0x398] &wr=0x1 ?trans3;
LDG.E R0, desc[UR6][R6.64+0x8] &wr=0x1 ?trans2;
FFMA R3, -R9, UR5, R0 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64+0x8], R3 &rd=0x0 ?trans4;
LDG.E R14, desc[UR6][R4.64+0xc] &wr=0x2 ?trans1;
HFMA2 R11, -RZ, RZ, 1.0341796875, -112.625 ?trans1;
BSSY.RECONVERGENT B2, 0x1110 ?trans4;
FFMA R0, R11, -R2, 1 ?WAIT4_END_GROUP;
FFMA R0, R0, R11, 0.0099999997764825820923 ?trans1;
FCHK P0, R14, 100 &req={2} &wr=0x1 ?trans3;
FFMA R11, R0, R14, RZ ?WAIT4_END_GROUP;
FFMA R10, R11, -100, R14 ?WAIT4_END_GROUP;
FFMA R11, R0, R10, R11 ?trans1;
@!P0 BRA 0x1100 &req={1,0} ?trans6;
MOV R0, R14 ?trans1;
MOV R14, 0x10f0 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x1660 ?trans5;
MOV R11, R3 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
STG.E desc[UR6][R4.64+0xc], R11 &rd=0x0 ?trans1;
LDCU UR5, c[0x0][0x398] &wr=0x1 ?trans3;
LDG.E R0, desc[UR6][R6.64+0xc] &wr=0x1 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x4, URZ ?trans1;
FFMA R3, -R11, UR5, R0 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64+0xc], R3 &rd=0x0 ?trans6;
ISETP.NE.AND P0, PT, R8, RZ, PT ?WAIT13_END_GROUP;
@!P0 EXIT ?trans5;
ISETP.NE.AND P0, PT, R8, 0x1, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x1480 ?trans5;
LDC.64 R4, c[0x0][0x388] &req={0} &wr=0x0 ?trans1;
IADD3 R6, PT, PT, R12, UR4, RZ ?WAIT5_END_GROUP;
IMAD.WIDE R4, R6, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
LDG.E R10, desc[UR6][R4.64] &wr=0x2 ?trans1;
HFMA2 R3, -RZ, RZ, 1.0341796875, -112.625 ?trans1;
BSSY.RECONVERGENT B2, 0x12c0 ?trans4;
FFMA R0, R3, -R2, 1 ?WAIT4_END_GROUP;
FFMA R0, R0, R3, 0.0099999997764825820923 ?trans1;
FCHK P0, R10, 100 &req={2} &wr=0x0 ?trans3;
FFMA R3, R0, R10, RZ ?WAIT4_END_GROUP;
FFMA R8, R3, -100, R10 ?WAIT4_END_GROUP;
FFMA R3, R0, R8, R3 ?trans1;
@!P0 BRA 0x12b0 &req={0} ?trans6;
MOV R0, R10 ?trans1;
MOV R14, 0x12b0 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x1660 ?trans5;
BSYNC.RECONVERGENT B2 ?trans5;
LDC.64 R8, c[0x0][0x380] &wr=0x0 ?trans1;
STG.E desc[UR6][R4.64], R3 &rd=0x1 ?trans1;
LDCU UR5, c[0x0][0x398] &wr=0x2 ?trans1;
IMAD.WIDE R6, R6, 0x4, R8 &req={0} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR6][R6.64] &wr=0x2 ?trans2;
FFMA R9, -R3, UR5, R0 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R9 &rd=0x1 ?trans4;
LDG.E R10, desc[UR6][R4.64+0x4] &wr=0x2 ?trans1;
MOV R11, 0x3c23d70a ?trans1;
BSSY.RECONVERGENT B2, 0x1420 ?trans4;
FFMA R0, R11, -R2, 1 ?WAIT4_END_GROUP;
FFMA R0, R0, R11, 0.0099999997764825820923 ?trans1;
FCHK P0, R10, 100 &req={2} &wr=0x0 ?trans3;
FFMA R11, R0, R10, RZ ?WAIT4_END_GROUP;
FFMA R8, R11, -100, R10 ?WAIT4_END_GROUP;
FFMA R11, R0, R8, R11 ?trans1;
@!P0 BRA 0x1410 &req={1,0} ?trans6;
MOV R0, R10 ?trans1;
MOV R14, 0x1400 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x1660 ?trans5;
MOV R11, R3 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
STG.E desc[UR6][R4.64+0x4], R11 &rd=0x1 ?trans1;
LDCU UR5, c[0x0][0x398] &wr=0x0 ?trans3;
LDG.E R0, desc[UR6][R6.64+0x4] &wr=0x0 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x2, URZ ?trans1;
FFMA R3, -R11, UR5, R0 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64+0x4], R3 &rd=0x1 ?trans6;
LDC R0, c[0x0][0x390] &wr=0x2 ?trans2;
LOP3.LUT R0, R0, 0x1, RZ, 0xc0, !PT &req={2} ?WAIT5_END_GROUP;
ISETP.NE.U32.AND P0, PT, R0, 0x1, PT ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LDC.64 R4, c[0x0][0x388] &req={1,0} &wr=0x0 ?trans1;
IADD3 R12, PT, PT, R12, UR4, RZ ?WAIT5_END_GROUP;
IMAD.WIDE R4, R12, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
LDG.E R8, desc[UR6][R4.64] &wr=0x2 ?trans1;
HFMA2 R3, -RZ, RZ, 1.0341796875, -112.625 ?trans1;
BSSY.RECONVERGENT B2, 0x15e0 ?trans4;
FFMA R0, R3, -R2, 1 ?WAIT4_END_GROUP;
FFMA R0, R0, R3, 0.0099999997764825820923 ?trans1;
FCHK P0, R8, 100 &req={2} &wr=0x0 ?trans3;
FFMA R3, R0, R8, RZ ?WAIT4_END_GROUP;
FFMA R6, R3, -100, R8 ?WAIT4_END_GROUP;
FFMA R7, R0, R6, R3 ?trans1;
@!P0 BRA 0x15d0 &req={0} ?trans6;
MOV R0, R8 ?trans1;
MOV R14, 0x15c0 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x1660 ?trans5;
MOV R7, R3 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
STG.E desc[UR6][R4.64], R7 ?trans1;
LDCU UR4, c[0x0][0x398] &wr=0x1 ?trans1;
IMAD.WIDE R12, R12, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR6][R12.64] &wr=0x1 ?trans2;
FFMA R3, -R7, UR4, R0 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR6][R12.64], R3 ?trans1;
EXIT ?trans5;
SHF.R.U32.HI R13, RZ, 0x17, R2 ?trans1;
BSSY.RECONVERGENT B0, 0x1cc0 ?trans1;
SHF.R.U32.HI R16, RZ, 0x17, R0 ?trans1;
HFMA2 R19, -RZ, RZ, 3.390625, 0 ?trans1;
LOP3.LUT R13, R13, 0xff, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R16, R16, 0xff, RZ, 0xc0, !PT ?trans2;
IADD3 R20, PT, PT, R13, -0x1, RZ ?trans2;
IADD3 R22, PT, PT, R16, -0x1, RZ ?WAIT3_END_GROUP;
ISETP.GT.U32.AND P0, PT, R20, 0xfd, PT ?WAIT5_END_GROUP;
ISETP.GT.U32.OR P0, PT, R22, 0xfd, P0 ?WAIT13_END_GROUP;
@!P0 MOV R15, RZ ?trans1;
@!P0 BRA 0x18a0 ?trans6;
MOV R3, 0x42c80000 ?trans1;
FSETP.GTU.FTZ.AND P0, PT, |R0|, +INF , PT ?WAIT4_END_GROUP;
FSETP.GTU.FTZ.AND P1, PT, |R3|, +INF , PT ?WAIT5_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, PT, 0xf8, 0x8f ?WAIT13_END_GROUP;
@P0 BRA 0x1ca0 ?trans5;
LOP3.LUT P0, RZ, R19, 0x7fffffff, R0, 0xc8, !PT ?WAIT13_END_GROUP;
@!P0 BRA 0x1c80 ?trans5;
FSETP.NEU.FTZ.AND P2, PT, |R0|.reuse, +INF , PT ?trans1;
FSETP.NEU.FTZ.AND P1, PT, |R3|, +INF , PT ?trans1;
FSETP.NEU.FTZ.AND P0, PT, |R0|, +INF , PT ?WAIT12_END_GROUP;
@!P1 BRA !P2, 0x1c80 ?trans5;
LOP3.LUT P2, RZ, R0, 0x7fffffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P1, PT, P1, P2, PT, 0x2f, 0xf2 ?WAIT13_END_GROUP;
@P1 BRA 0x1c60 ?trans5;
LOP3.LUT P1, RZ, R19, 0x7fffffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, PT, 0x2f, 0xf2 ?WAIT13_END_GROUP;
@P0 BRA 0x1c30 ?trans5;
ISETP.GE.AND P0, PT, R22, RZ, PT ?trans1;
ISETP.GE.AND P1, PT, R20, RZ, PT ?WAIT12_END_GROUP;
@P0 MOV R15, RZ ?trans1;
@!P0 MOV R15, 0xffffffc0 ?trans1;
@!P0 FFMA R0, R0, 1.84467440737095516160e+19, RZ ?trans1;
@!P1 FFMA R19, R3, 1.84467440737095516160e+19, RZ ?WAIT3_END_GROUP;
@!P1 IADD3 R15, PT, PT, R15, 0x40, RZ ?WAIT7_END_GROUP;
LEA R20, R13, 0xc0800000, 0x17 ?trans1;
BSSY.RECONVERGENT B1, 0x1c20 ?trans1;
IADD3 R16, PT, PT, R16, -0x7f, RZ ?trans2;
IADD3 R23, PT, PT, -R20, R19, RZ ?WAIT3_END_GROUP;
IMAD R0, R16.reuse, -0x800000, R0 ?trans1;
IADD3 R16, PT, PT, R16, 0x7f, -R13 ?trans1;
MUFU.RCP R20, R23 &wr=0x0 ?trans1;
FADD.FTZ R3, -R23, -RZ ?trans2;
IADD3 R16, PT, PT, R16, R15, RZ ?trans2;
FFMA R19, R20, R3, 1 &req={0} ?WAIT4_END_GROUP;
FFMA R20, R20, R19, R20 ?WAIT4_END_GROUP;
FFMA R19, R0, R20, RZ ?WAIT4_END_GROUP;
FFMA R22, R3, R19, R0 ?WAIT4_END_GROUP;
FFMA R19, R20, R22, R19 ?WAIT4_END_GROUP;
FFMA R22, R3, R19, R0 ?WAIT4_END_GROUP;
FFMA R0, R20, R22, R19 ?WAIT5_END_GROUP;
SHF.R.U32.HI R3, RZ, 0x17, R0 ?WAIT4_END_GROUP;
LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R3, PT, PT, R3, R16, RZ ?WAIT4_END_GROUP;
IADD3 R13, PT, PT, R3, -0x1, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R13, 0xfe, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x1c00 ?trans5;
ISETP.GT.AND P0, PT, R3, 0xfe, PT ?WAIT13_END_GROUP;
@P0 BRA 0x1bd0 ?trans5;
ISETP.GE.AND P0, PT, R3, 0x1, PT ?WAIT13_END_GROUP;
@P0 BRA 0x1c10 ?trans5;
ISETP.GE.AND P0, PT, R3, -0x18, PT ?trans1;
LOP3.LUT R0, R0, 0x80000000, RZ, 0xc0, !PT ?WAIT12_END_GROUP;
@!P0 BRA 0x1c10 ?trans5;
FFMA.RZ R13, R20.reuse, R22.reuse, R19.reuse ?trans1;
FFMA.RP R15, R20.reuse, R22.reuse, R19.reuse ?trans1;
FFMA.RM R20, R20, R22, R19 ?trans1;
ISETP.NE.AND P1, PT, R3.reuse, RZ, PT ?trans1;
ISETP.NE.AND P2, PT, R3, RZ, PT ?trans1;
LOP3.LUT R16, R13, 0x7fffff, RZ, 0xc0, !PT ?trans2;
IADD3 R13, PT, PT, R3.reuse, 0x20, RZ ?trans2;
IADD3 R3, PT, PT, -R3, RZ, RZ ?trans2;
LOP3.LUT R16, R16, 0x800000, RZ, 0xfc, !PT ?trans1;
FSETP.NEU.FTZ.AND P0, PT, R15, R20, PT ?WAIT3_END_GROUP;
SHF.L.U32 R13, R16, R13, RZ ?trans1;
SEL R3, R3, RZ, P2 ?WAIT4_END_GROUP;
ISETP.NE.AND P1, PT, R13, RZ, P1 ?trans1;
SHF.R.U32.HI R3, RZ, R3, R16 ?WAIT4_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, PT, 0xf8, 0x8f ?trans2;
SHF.R.U32.HI R16, RZ, 0x1, R3 ?WAIT3_END_GROUP;
SEL R13, RZ, 0x1, !P0 ?WAIT5_END_GROUP;
LOP3.LUT R20, R13, 0x1, R16, 0xf8, !PT ?WAIT4_END_GROUP;
LOP3.LUT R3, R20, R3, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R3, PT, PT, R16, R3, RZ ?WAIT4_END_GROUP;
LOP3.LUT R0, R3, R0, RZ, 0xfc, !PT ?trans1;
BRA 0x1c10 ?trans6;
LOP3.LUT R0, R0, 0x80000000, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
LOP3.LUT R0, R0, 0x7f800000, RZ, 0xfc, !PT ?trans1;
BRA 0x1c10 ?trans6;
IMAD R0, R16, 0x800000, R0 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B1 ?trans5;
BRA 0x1cb0 ?trans5;
LOP3.LUT R0, R19, 0x80000000, R0, 0x48, !PT ?WAIT4_END_GROUP;
LOP3.LUT R0, R0, 0x7f800000, RZ, 0xfc, !PT ?trans1;
BRA 0x1cb0 ?trans6;
LOP3.LUT R0, R19, 0x80000000, R0, 0x48, !PT ?trans1;
BRA 0x1cb0 ?trans6;
MUFU.RSQ R0, -QNAN &wr=0x0 ?trans1;
BRA 0x1cb0 ?trans5;
FADD.FTZ R0, R0, R3 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
HFMA2 R15, -RZ, RZ, 0, 0 ?trans1;
MOV R3, R0 &req={0} ?WAIT3_END_GROUP;
RET.REL.NODEC R14 0x0 ?trans5;
BRA 0x1cf0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: weight_update(float*, float*, int, int, float)
_Z13weight_updatePfS_iif:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x20
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_load_b128 s[4:7], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v2, s3, s[14:15]
v_and_b32_e32 v2, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v3, s2, v[2:3]
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s4, 0
s_cselect_b32 s2, -1, 0
v_cmp_gt_i32_e32 vcc_lo, s5, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB7_3
s_load_b128 s[0:3], s[0:1], 0x0
v_mul_lo_u32 v0, v0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
.LBB7_2:
global_load_b32 v4, v[0:1], off
s_add_i32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
s_cmp_lg_u32 s4, 0
s_waitcnt vmcnt(0)
v_div_scale_f32 v5, null, 0x42c80000, 0x42c80000, v4
v_div_scale_f32 v7, vcc_lo, v4, 0x42c80000, v4
v_rcp_f32_e32 v6, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v5, v6, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v8, v6
v_mul_f32_e32 v8, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v9, -v5, v8, v7
v_fmac_f32_e32 v8, v9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, -v5, v8, v7
v_div_fmas_f32 v5, v5, v6, v8
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v4, v5, 0x42c80000, v4
global_store_b32 v[0:1], v4, off
global_load_b32 v5, v[2:3], off
v_add_co_u32 v0, vcc_lo, v0, 4
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_waitcnt vmcnt(0)
v_fma_f32 v4, -v4, s6, v5
global_store_b32 v[2:3], v4, off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_cbranch_scc1 .LBB7_2
.LBB7_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| weight_update | 11,315 | 1,352 | stackv2-00000-of-00015 |
// Demangled: kDivide(float*, float*, float*, unsigned int)
Function : _Z7kDividePfS_S_j
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x398] &wr=0x2 ?trans7;
LDC R15, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R0, R15, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R0, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R10, c[0x0][0x390] &wr=0x0 ?trans1;
LDCU UR4, c[0x0][0x370] &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x2 ?trans6;
LDC.64 R12, c[0x0][0x380] &wr=0x3 ?trans8;
LDC.64 R8, c[0x0][0x388] &wr=0x4 ?trans1;
IMAD R15, R15, UR4, RZ &req={1} ?WAIT7_END_GROUP;
IMAD.WIDE R4, R0, 0x4, R10 &req={0} ?WAIT5_END_GROUP;
LDG.E R16, desc[UR6][R4.64] &req={2} &wr=0x2 ?trans1;
IMAD.WIDE R2, R0, 0x4, R8 &req={4} ?WAIT5_END_GROUP;
LDG.E R14, desc[UR6][R2.64] &wr=0x4 ?trans1;
IMAD.WIDE R6, R0, 0x4, R12 &req={3,1} ?trans1;
IADD3 R0, PT, PT, R15, R0, RZ ?trans1;
FSETP.GEU.AND P0, PT, |R16|, 1.175494350822287508e-38, PT &req={2} ?WAIT13_END_GROUP;
@!P0 FMUL R16, R16, 16777216 ?trans1;
@!P0 FMUL R14, R14, 16777216 &req={4} ?trans1;
ISETP.GE.U32.AND P0, PT, R0, UR5, PT ?trans2;
MUFU.RCP R17, R16 &wr=0x0 ?trans2;
FMUL R17, R17, R14 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R17 &rd=0x1 ?trans4;
@!P0 BRA 0xe0 ?trans5;
EXIT ?trans5;
BRA 0x1d0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: kDivide(float*, float*, float*, unsigned int)
_Z7kDividePfS_S_j:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s8, v1
s_cbranch_execz .LBB2_3
s_load_b32 s10, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s10, s9
s_mov_b32 s9, 0
.LBB2_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_co_u32 v2, s0, s4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v3, s0, s5, v3, s0
s_waitcnt vmcnt(0)
v_div_scale_f32 v5, null, v4, v4, v0
v_div_scale_f32 v8, vcc_lo, v0, v4, v0
v_rcp_f32_e32 v6, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v7, -v5, v6, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v7, v6
v_mul_f32_e32 v7, v8, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v9, -v5, v7, v8
v_fmac_f32_e32 v7, v9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, -v5, v7, v8
v_div_fmas_f32 v5, v5, v6, v7
v_cmp_le_u32_e32 vcc_lo, s8, v1
s_delay_alu instid0(VALU_DEP_2)
v_div_fixup_f32 v0, v5, v4, v0
s_or_b32 s9, vcc_lo, s9
global_store_b32 v[2:3], v0, off
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB2_2
.LBB2_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| kDivide | 840 | 1,074 | stackv2-00000-of-00015 |
// Demangled: kExp(float*, float*, unsigned int)
Function : _Z4kExpPfS_j
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x390] &wr=0x2 ?trans7;
LDC R11, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R0, R11, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R0, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R8, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU UR4, c[0x0][0x370] &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x2 ?trans6;
LDC.64 R6, c[0x0][0x388] &wr=0x3 ?trans1;
IMAD R11, R11, UR4, RZ &req={1} ?WAIT7_END_GROUP;
IMAD.WIDE R2, R0, 0x4, R6 &req={3} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR6][R2.64] &req={2} &wr=0x2 ?trans1;
IMAD.WIDE R4, R0, 0x4, R8 &req={1,0} ?trans1;
IADD3 R0, PT, PT, R11, R0, RZ ?WAIT3_END_GROUP;
FMUL R10, R2, 1.4426950216293334961 &req={2} ?WAIT5_END_GROUP;
FSETP.GEU.AND P0, PT, R10, -126, PT ?WAIT13_END_GROUP;
@!P0 FMUL R10, R10, 0.5 ?WAIT4_END_GROUP;
MUFU.EX2 R13, R10 &wr=0x0 ?trans2;
@!P0 FMUL R13, R13, R13 &req={0} ?trans1;
ISETP.GE.U32.AND P0, PT, R0, UR5, PT ?WAIT4_END_GROUP;
STG.E desc[UR6][R4.64], R13 &rd=0x1 ?trans9;
@!P0 BRA 0xd0 ?trans5;
EXIT ?trans5;
BRA 0x1a0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: kExp(float*, float*, unsigned int)
_Z4kExpPfS_j:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s8, v1
s_cbranch_execz .LBB1_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s2, s9
s_mov_b32 s2, 0
.LBB1_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, s0, s4, v2
v_add_co_ci_u32_e64 v3, s0, s5, v3, s0
global_load_b32 v0, v[4:5], off
v_cmp_le_u32_e32 vcc_lo, s8, v1
s_or_b32 s2, vcc_lo, s2
s_waitcnt vmcnt(0)
v_mul_f32_e32 v0, 0x3fb8aa3b, v0
s_delay_alu instid0(VALU_DEP_1)
v_exp_f32_e32 v0, v0
global_store_b32 v[2:3], v0, off
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| kExp | 738 | 686 | stackv2-00000-of-00015 |
// Demangled: kSampleMultinomial(int*, float*, float*, int, int)
Function : _Z18kSampleMultinomialPiPfS0_ii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R5, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x39c] &wr=0x2 ?trans7;
LDC R0, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R5, R0, UR4, R5 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R5, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC R0, c[0x0][0x398] &wr=0x0 ?trans8;
LDC.64 R2, c[0x0][0x390] &wr=0x1 ?trans1;
ISETP.GE.AND P0, PT, R0, 0x1, PT &req={0} ?WAIT13_END_GROUP;
@!P0 EXIT &req={1} ?trans5;
ISETP.GE.U32.AND P0, PT, R0.reuse, 0x8, PT ?trans1;
LOP3.LUT R16, R0, 0x7, RZ, 0xc0, !PT ?trans1;
UMOV UR4, URZ ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x0 ?trans1;
HFMA2 R11, -RZ, RZ, 0, 0 ?trans2;
IMAD.WIDE.U32 R2, R5, 0x4, R2 ?trans1;
ISETP.NE.AND P1, PT, R16, RZ, PT ?WAIT3_END_GROUP;
IMAD R4, R5, R0, RZ ?WAIT3_END_GROUP;
@!P0 BRA 0x5c0 ?trans7;
LDCU.128 UR8, c[0x0][0x380] &wr=0x1 ?trans1;
LEA R8, P0, R4, 0x10, 0x2 ?trans2;
LOP3.LUT R10, R0, 0x7ffffff8, RZ, 0xc0, !PT ?trans1;
UMOV UR4, URZ ?trans1;
LEA.HI.X R9, R4, RZ, RZ, 0x2, P0 ?trans1;
MOV R11, RZ ?trans1;
IADD3 R10, PT, PT, -R10, RZ, RZ ?WAIT3_END_GROUP;
IADD.64 R6, R8.reuse, UR10 &req={1} ?trans2;
IADD.64 R8, R8, UR8 ?WAIT8_END_GROUP;
LDG.E R12, desc[UR6][R6.64+-0x10] &req={0} &wr=0x2 ?trans4;
LDG.E R13, desc[UR6][R2.64] &wr=0x3 ?trans1;
FADD R12, R12, R11 &req={2} ?WAIT5_END_GROUP;
FSETP.GEU.AND P0, PT, R13, R12, PT &req={3} ?WAIT5_END_GROUP;
FSETP.GE.AND P0, PT, R13, R11, !P0 ?WAIT5_END_GROUP;
SEL R11, RZ, 0x1, !P0 ?WAIT5_END_GROUP;
STG.E desc[UR6][R8.64+-0x10], R11 &rd=0x0 ?trans4;
LDG.E R13, desc[UR6][R6.64+-0xc] &wr=0x2 ?trans4;
LDG.E R14, desc[UR6][R2.64] &wr=0x3 ?trans1;
FADD R13, R12, R13 &req={2} ?WAIT5_END_GROUP;
FSETP.GEU.AND P0, PT, R14, R13, PT &req={3} ?WAIT5_END_GROUP;
FSETP.GE.AND P0, PT, R14, R12, !P0 ?WAIT5_END_GROUP;
SEL R15, RZ, 0x1, !P0 ?WAIT5_END_GROUP;
STG.E desc[UR6][R8.64+-0xc], R15 &rd=0x1 ?trans4;
LDG.E R12, desc[UR6][R6.64+-0x8] &wr=0x2 ?trans4;
LDG.E R14, desc[UR6][R2.64] &wr=0x3 ?trans1;
FADD R12, R13, R12 &req={2} ?WAIT5_END_GROUP;
FSETP.GEU.AND P0, PT, R14, R12, PT &req={3} ?WAIT5_END_GROUP;
FSETP.GE.AND P0, PT, R14, R13, !P0 ?WAIT5_END_GROUP;
SEL R11, RZ, 0x1, !P0 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R8.64+-0x8], R11 &rd=0x0 ?trans4;
LDG.E R13, desc[UR6][R6.64+-0x4] &wr=0x2 ?trans4;
LDG.E R14, desc[UR6][R2.64] &wr=0x3 ?trans1;
FADD R13, R12, R13 &req={2} ?WAIT5_END_GROUP;
FSETP.GEU.AND P0, PT, R14, R13, PT &req={3} ?WAIT5_END_GROUP;
FSETP.GE.AND P0, PT, R14, R12, !P0 ?WAIT5_END_GROUP;
SEL R15, RZ, 0x1, !P0 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR6][R8.64+-0x4], R15 &rd=0x1 ?trans4;
LDG.E R12, desc[UR6][R6.64] &wr=0x2 ?trans4;
LDG.E R14, desc[UR6][R2.64] &wr=0x3 ?trans1;
FADD R12, R13, R12 &req={2} ?WAIT5_END_GROUP;
FSETP.GEU.AND P0, PT, R14, R12, PT &req={3} ?WAIT5_END_GROUP;
FSETP.GE.AND P0, PT, R14, R13, !P0 ?WAIT5_END_GROUP;
SEL R11, RZ, 0x1, !P0 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R8.64], R11 &rd=0x0 ?trans4;
LDG.E R13, desc[UR6][R6.64+0x4] &wr=0x2 ?trans4;
LDG.E R14, desc[UR6][R2.64] &wr=0x3 ?trans1;
FADD R13, R12, R13 &req={2} ?WAIT5_END_GROUP;
FSETP.GEU.AND P0, PT, R14, R13, PT &req={3} ?WAIT5_END_GROUP;
FSETP.GE.AND P0, PT, R14, R12, !P0 ?WAIT5_END_GROUP;
SEL R15, RZ, 0x1, !P0 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR6][R8.64+0x4], R15 &rd=0x1 ?trans4;
LDG.E R12, desc[UR6][R6.64+0x8] &wr=0x2 ?trans4;
LDG.E R14, desc[UR6][R2.64] &wr=0x3 ?trans1;
FADD R12, R13, R12 &req={2} ?WAIT5_END_GROUP;
FSETP.GEU.AND P0, PT, R14, R12, PT &req={3} ?WAIT5_END_GROUP;
FSETP.GE.AND P0, PT, R14, R13, !P0 ?WAIT5_END_GROUP;
SEL R13, RZ, 0x1, !P0 ?WAIT5_END_GROUP;
STG.E desc[UR6][R8.64+0x8], R13 ?trans4;
LDG.E R11, desc[UR6][R6.64+0xc] &req={0} &rd=0x0 &wr=0x2 ?trans4;
LDG.E R14, desc[UR6][R2.64] &wr=0x3 ?trans1;
IADD3 R10, PT, PT, R10, 0x8, RZ ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x8, URZ ?trans1;
IADD.64 R6, R6, 0x20 &req={0} ?WAIT2_END_GROUP;
FADD R11, R12, R11 &req={2} ?WAIT5_END_GROUP;
FSETP.GEU.AND P0, PT, R14, R11, PT &req={3} ?WAIT5_END_GROUP;
FSETP.GE.AND P0, PT, R14, R12, !P0 ?WAIT5_END_GROUP;
SEL R15, RZ, 0x1, !P0 &req={1} ?trans1;
ISETP.NE.AND P0, PT, R10, RZ, PT ?WAIT4_END_GROUP;
STG.E desc[UR6][R8.64+0xc], R15 &rd=0x0 ?trans2;
IADD.64 R8, R8, 0x20 &req={0} ?WAIT7_END_GROUP;
@P0 BRA 0x1e0 ?trans5;
@!P1 EXIT &req={0} ?trans5;
ISETP.GE.U32.AND P0, PT, R16, 0x4, PT ?trans1;
LOP3.LUT R14, R0, 0x3, RZ, 0xc0, !PT ?trans1;
MOV R5, RZ ?WAIT4_END_GROUP;
ISETP.NE.AND P1, PT, R14, RZ, PT ?WAIT7_END_GROUP;
@!P0 BRA 0x860 ?trans6;
LDCU.128 UR8, c[0x0][0x380] &wr=0x0 ?trans1;
LDG.E R12, desc[UR6][R2.64] &wr=0x2 ?trans1;
UMOV UR5, URZ ?trans2;
IADD.64 R6, R4, UR4 ?WAIT5_END_GROUP;
SHF.L.U64.HI R9, R6.reuse, 0x2, R7 ?trans1;
IMAD.SHL.U32 R8, R6, 0x4, RZ ?WAIT5_END_GROUP;
IADD.64 R6, R8, UR10 &req={0} ?WAIT6_END_GROUP;
LDG.E R10, desc[UR6][R6.64] &wr=0x3 ?trans1;
IADD.64 R8, R8, UR8 ?trans2;
FADD R10, R11, R10 &req={3} ?WAIT5_END_GROUP;
FSETP.GEU.AND P0, PT, R12, R10, PT &req={2} ?WAIT5_END_GROUP;
FSETP.GE.AND P0, PT, R12, R11, !P0 ?WAIT5_END_GROUP;
SEL R11, RZ, 0x1, !P0 ?WAIT5_END_GROUP;
STG.E desc[UR6][R8.64], R11 &rd=0x0 ?trans4;
LDG.E R13, desc[UR6][R6.64+0x4] &wr=0x2 ?trans4;
LDG.E R12, desc[UR6][R2.64] &wr=0x3 ?trans1;
FADD R13, R10, R13 &req={2} ?WAIT5_END_GROUP;
FSETP.GEU.AND P0, PT, R12, R13, PT &req={3} ?WAIT5_END_GROUP;
FSETP.GE.AND P0, PT, R12, R10, !P0 ?WAIT5_END_GROUP;
SEL R15, RZ, 0x1, !P0 ?WAIT5_END_GROUP;
STG.E desc[UR6][R8.64+0x4], R15 &rd=0x1 ?trans4;
LDG.E R10, desc[UR6][R6.64+0x8] &wr=0x2 ?trans4;
LDG.E R12, desc[UR6][R2.64] &wr=0x3 ?trans1;
FADD R10, R13, R10 &req={2} ?WAIT5_END_GROUP;
FSETP.GEU.AND P0, PT, R12, R10, PT &req={3} ?WAIT5_END_GROUP;
FSETP.GE.AND P0, PT, R12, R13, !P0 ?WAIT5_END_GROUP;
SEL R13, RZ, 0x1, !P0 ?WAIT5_END_GROUP;
STG.E desc[UR6][R8.64+0x8], R13 &rd=0x2 ?trans4;
LDG.E R11, desc[UR6][R6.64+0xc] &req={0} &wr=0x3 ?trans4;
LDG.E R12, desc[UR6][R2.64] &wr=0x4 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x4, URZ ?trans1;
FADD R11, R10, R11 &req={3} ?WAIT5_END_GROUP;
FSETP.GEU.AND P0, PT, R12, R11, PT &req={4} ?WAIT5_END_GROUP;
FSETP.GE.AND P0, PT, R12, R10, !P0 ?WAIT5_END_GROUP;
SEL R15, RZ, 0x1, !P0 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR6][R8.64+0xc], R15 &rd=0x2 ?trans3;
@!P1 EXIT ?trans5;
ISETP.NE.AND P0, PT, R14, 0x1, PT ?trans1;
LOP3.LUT R0, R0, 0x1, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.U32.AND P1, PT, R0, 0x1, PT ?WAIT7_END_GROUP;
@!P0 BRA 0xa10 ?trans6;
LDCU.128 UR8, c[0x0][0x380] &wr=0x0 ?trans1;
LDG.E R10, desc[UR6][R2.64] &wr=0x3 ?trans1;
UMOV UR5, URZ ?trans2;
IADD.64 R6, R4, UR4 ?WAIT5_END_GROUP;
SHF.L.U64.HI R7, R6.reuse, 0x2, R7 ?trans1;
IMAD.SHL.U32 R6, R6, 0x4, RZ ?WAIT5_END_GROUP;
IADD.64 R8, R6, UR10 &req={2,0} ?WAIT6_END_GROUP;
LDG.E R0, desc[UR6][R8.64] &wr=0x2 ?trans1;
IADD.64 R6, R6, UR8 ?trans2;
FADD R0, R11, R0 &req={2} ?WAIT5_END_GROUP;
FSETP.GEU.AND P0, PT, R10, R0, PT &req={3} ?WAIT5_END_GROUP;
FSETP.GE.AND P0, PT, R10, R11, !P0 ?WAIT5_END_GROUP;
SEL R13, RZ, 0x1, !P0 ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R13 &rd=0x0 ?trans4;
LDG.E R11, desc[UR6][R8.64+0x4] &wr=0x2 ?trans4;
LDG.E R10, desc[UR6][R2.64] &wr=0x3 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x2, URZ ?trans1;
FADD R11, R0, R11 &req={2} ?WAIT5_END_GROUP;
FSETP.GEU.AND P0, PT, R10, R11, PT &req={3} ?WAIT5_END_GROUP;
FSETP.GE.AND P0, PT, R10, R0, !P0 ?WAIT5_END_GROUP;
SEL R15, RZ, 0x1, !P0 ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64+0x4], R15 &rd=0x0 ?trans3;
@P1 EXIT ?trans5;
LDCU.128 UR8, c[0x0][0x380] &wr=0x1 ?trans1;
LDG.E R2, desc[UR6][R2.64] &wr=0x3 ?trans1;
UMOV UR5, URZ ?trans2;
IADD.64 R4, R4, UR4 ?WAIT5_END_GROUP;
SHF.L.U64.HI R5, R4.reuse, 0x2, R5 ?trans1;
IMAD.SHL.U32 R4, R4, 0x4, RZ ?WAIT5_END_GROUP;
IADD.64 R6, R4, UR10 &req={1,0} ?WAIT7_END_GROUP;
LDG.E R6, desc[UR6][R6.64] &wr=0x4 ?trans1;
IADD.64 R4, R4, UR8 ?trans2;
FADD R0, R6, R11 &req={4} ?WAIT5_END_GROUP;
FSETP.GEU.AND P0, PT, R2, R0, PT &req={3} ?WAIT5_END_GROUP;
FSETP.GE.AND P0, PT, R2, R11, !P0 ?WAIT5_END_GROUP;
SEL R9, RZ, 0x1, !P0 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R4.64], R9 ?trans1;
EXIT ?trans5;
BRA 0xb10;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: kSampleMultinomial(int*, float*, float*, int, int)
_Z18kSampleMultinomialPiPfS0_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s4, v[0:1]
v_cmp_gt_u32_e32 vcc_lo, s3, v2
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_4
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b64 s[4:5], s[0:1], 0x10
v_mov_b32_e32 v1, 0
v_mul_lo_u32 v0, v2, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v3, v1
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_load_b128 s[4:7], s[0:1], 0x0
global_load_b32 v6, v[3:4], off
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.LBB0_3:
global_load_b32 v0, v[2:3], off
v_add_co_u32 v2, s0, v2, 4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
s_waitcnt vmcnt(1)
v_cmp_ge_f32_e32 vcc_lo, v6, v1
s_add_i32 s2, s2, -1
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_lt_f32_e64 s0, v6, v0
v_mov_b32_e32 v1, v0
s_and_b32 s0, vcc_lo, s0
s_cmp_lg_u32 s2, 0
v_cndmask_b32_e64 v0, 0, 1, s0
global_store_b32 v[4:5], v0, off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_cbranch_scc1 .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| kSampleMultinomial | 4,673 | 1,001 | stackv2-00000-of-00015 |
// Demangled: pack_matrix(double*, double*, int)
Function : _Z11pack_matrixPdS_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R7, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans8;
LDC R12, c[0x0][0x360] &wr=0x1 ?trans8;
LDC R14, c[0x0][0x390] &wr=0x2 ?trans1;
IMAD R7, R12, UR4, R7 &req={1} ?WAIT2_END_GROUP;
IMAD R0, R14, R14, RZ &req={2} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R7, R0, PT ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
IABS R6, R14.reuse ?trans1;
LDC R15, c[0x0][0x390] &wr=0x0 ?trans1;
LDCU UR4, c[0x0][0x370] &wr=0x1 ?trans1;
ISETP.NE.AND P0, PT, R14, RZ, PT ?trans1;
I2F.RP R10, R6 &wr=0x2 ?trans1;
LOP3.LUT R14, RZ, R14, RZ, 0x33, !PT ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x3 ?trans3;
LDC.64 R2, c[0x0][0x380] &wr=0x4 ?trans8;
LDC.64 R4, c[0x0][0x388] &wr=0x0 ?trans1;
MUFU.RCP R10, R10 &req={2} &wr=0x2 ?trans1;
IMAD R12, R12, UR4, RZ &req={1} ?trans1;
IADD3 R8, PT, PT, R10, 0xffffffe, RZ &req={2} ?WAIT4_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R9, R8 &rd=0x1 &wr=0x2 ?trans2;
HFMA2 R8, -RZ, RZ, 0, 0 &req={1} ?trans1;
IADD3 R13, PT, PT, RZ, -R9, RZ &req={2} ?WAIT5_END_GROUP;
IMAD R13, R13, R6, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R13, R9, R13, R8 &req={4,3,0} ?WAIT7_END_GROUP;
IABS R10, R7 &req={0} ?trans2;
IABS R16, R15 ?trans1;
ISETP.GE.AND P2, PT, R7, RZ, PT ?trans2;
IMAD.HI.U32 R8, R13, R10, RZ ?WAIT5_END_GROUP;
IADD3 R9, PT, PT, -R8, RZ, RZ ?WAIT5_END_GROUP;
IMAD R9, R16, R9, R10 ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P1, PT, R6, R9, PT ?WAIT13_END_GROUP;
@!P1 IADD3 R9, PT, PT, R9, -R16, RZ ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P1, PT, R6, R9, PT ?WAIT13_END_GROUP;
@!P1 IADD3 R9, PT, PT, R9, -R16, RZ ?WAIT4_END_GROUP;
@!P2 IADD3 R9, PT, PT, -R9, RZ, RZ ?WAIT5_END_GROUP;
SEL R8, R14, R9, !P0 ?WAIT5_END_GROUP;
IADD3 R9, PT, PT, -R8, R7, RZ ?WAIT5_END_GROUP;
IMAD R9, R9, R15, R8 ?WAIT4_END_GROUP;
IMAD.WIDE R8, R9, 0x8, R2 ?WAIT6_END_GROUP;
LDG.E.64.CONSTANT R8, desc[UR6][R8.64] &wr=0x2 ?trans1;
IMAD.WIDE R10, R7, 0x8, R4 ?trans1;
IADD3 R7, PT, PT, R12, R7, RZ ?WAIT5_END_GROUP;
ISETP.GE.AND P1, PT, R7, R0, PT ?trans1;
STG.E.64 desc[UR6][R10.64], R8 &req={2} &rd=0x0 ?WAIT12_END_GROUP;
@!P1 BRA 0x1a0 ?trans5;
EXIT ?trans5;
BRA 0x300;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: pack_matrix(double*, double*, int)
_ZL11pack_matrixPdS_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s11, s4, 0xffff
s_mul_i32 s9, s8, s8
v_mad_u64_u32 v[1:2], null, s15, s11, v[0:1]
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s9, v1
s_cbranch_execz .LBB0_3
s_ashr_i32 s4, s8, 31
s_load_b32 s2, s[2:3], 0x0
s_add_i32 s5, s8, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_xor_b32 s10, s5, s4
s_load_b128 s[4:7], s[0:1], 0x0
v_cvt_f32_u32_e32 v0, s10
s_sub_i32 s3, 0, s10
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s2, s11
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v2
v_xor_b32_e32 v3, v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v5, v3, v0
v_mul_lo_u32 v5, v5, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v3, v5
v_subrev_nc_u32_e32 v5, s10, v3
v_cmp_le_u32_e32 vcc_lo, s10, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v3, v5, vcc_lo
v_subrev_nc_u32_e32 v5, s10, v3
v_cmp_le_u32_e32 vcc_lo, s10, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v3, v5, vcc_lo
v_xor_b32_e32 v5, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v5, v2
v_sub_nc_u32_e32 v6, v4, v5
v_mad_u64_u32 v[4:5], null, v6, s8, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[3:4], 3, v[4:5]
v_lshlrev_b64 v[5:6], 3, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_cmp_le_i32_e32 vcc_lo, s9, v1
v_add_co_u32 v5, s0, s6, v5
global_load_b64 v[3:4], v[3:4], off
v_add_co_ci_u32_e64 v6, s0, s7, v6, s0
s_or_b32 s2, vcc_lo, s2
s_waitcnt vmcnt(0)
global_store_b64 v[5:6], v[3:4], off
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| pack_matrix | 1,271 | 1,500 | stackv2-00000-of-00015 |
// Demangled: unpack_matrix(double*, double*, int)
Function : _Z13unpack_matrixPdS_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R9, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans8;
LDC R12, c[0x0][0x360] &wr=0x1 ?trans8;
LDC R14, c[0x0][0x390] &wr=0x2 ?trans1;
IMAD R9, R12, UR4, R9 &req={1} ?WAIT2_END_GROUP;
IMAD R0, R14, R14, RZ &req={2} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R9, R0, PT ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
IABS R8, R14.reuse ?trans1;
LDC R18, c[0x0][0x390] &wr=0x0 ?trans1;
LDCU UR4, c[0x0][0x370] &wr=0x1 ?trans1;
ISETP.NE.AND P0, PT, R14, RZ, PT ?trans1;
I2F.RP R10, R8 &wr=0x2 ?trans1;
LOP3.LUT R14, RZ, R14, RZ, 0x33, !PT ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x3 ?trans3;
LDC.64 R2, c[0x0][0x380] &wr=0x4 ?trans8;
LDC.64 R4, c[0x0][0x388] &wr=0x0 ?trans1;
MUFU.RCP R10, R10 &req={2} &wr=0x2 ?trans1;
IMAD R12, R12, UR4, RZ &req={1} ?trans1;
IADD3 R6, PT, PT, R10, 0xffffffe, RZ &req={2} ?WAIT4_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R7, R6 &rd=0x1 &wr=0x2 ?trans2;
HFMA2 R6, -RZ, RZ, 0, 0 &req={1} ?trans1;
IADD3 R13, PT, PT, RZ, -R7, RZ &req={2} ?WAIT5_END_GROUP;
IMAD R13, R13, R8, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R13, R7, R13, R6 &req={4,3,0} ?WAIT7_END_GROUP;
IMAD.WIDE R6, R9, 0x8, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E.64.CONSTANT R6, desc[UR6][R6.64] &wr=0x2 ?trans1;
IABS R16, R9 ?trans2;
IABS R20, R18 ?trans1;
ISETP.GE.AND P2, PT, R9, RZ, PT ?trans2;
IMAD.HI.U32 R10, R13, R16, RZ ?WAIT5_END_GROUP;
IADD3 R11, PT, PT, -R10, RZ, RZ ?trans2;
IADD3 R10, PT, PT, R9, -0x1, R18 ?trans2;
IADD3 R9, PT, PT, R12, R9, RZ ?trans1;
IMAD R11, R20, R11, R16 ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P1, PT, R8, R11, PT ?WAIT13_END_GROUP;
@!P1 IADD3 R11, PT, PT, R11, -R20, RZ ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P1, PT, R8, R11, PT ?WAIT13_END_GROUP;
@!P1 IADD3 R11, PT, PT, R11, -R20, RZ ?trans1;
ISETP.GE.AND P1, PT, R9, R0, PT ?WAIT3_END_GROUP;
@!P2 IADD3 R11, PT, PT, -R11, RZ, RZ ?WAIT5_END_GROUP;
SEL R11, R14, R11, !P0 ?WAIT5_END_GROUP;
IADD3 R10, PT, PT, -R11, R10, RZ ?WAIT5_END_GROUP;
IMAD R11, R10, R18, R11 ?WAIT4_END_GROUP;
IMAD.WIDE R10, R11, 0x8, R4 ?WAIT5_END_GROUP;
STG.E.64 desc[UR6][R10.64], R6 &req={2} &rd=0x0 ?trans1;
@!P1 BRA 0x1a0 ?trans5;
EXIT ?trans5;
BRA 0x310;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: unpack_matrix(double*, double*, int)
_ZL13unpack_matrixPdS_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s11, s4, 0xffff
s_mul_i32 s9, s8, s8
v_mad_u64_u32 v[1:2], null, s15, s11, v[0:1]
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s9, v1
s_cbranch_execz .LBB1_3
s_ashr_i32 s4, s8, 31
s_load_b32 s2, s[2:3], 0x0
s_add_i32 s5, s8, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_xor_b32 s10, s5, s4
s_load_b128 s[4:7], s[0:1], 0x0
v_cvt_f32_u32_e32 v0, s10
s_sub_i32 s3, 0, s10
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s2, s11
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s3, v0
s_add_i32 s3, s8, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
.LBB1_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_add_nc_u32_e32 v5, v1, v2
v_add_nc_u32_e32 v1, s1, v1
v_xor_b32_e32 v6, v5, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_mul_hi_u32 v7, v6, v0
global_load_b64 v[3:4], v[3:4], off
v_mul_lo_u32 v7, v7, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v6, v6, v7
v_subrev_nc_u32_e32 v7, s10, v6
v_cmp_le_u32_e32 vcc_lo, s10, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v6, v6, v7 :: v_dual_add_nc_u32 v5, s3, v5
v_subrev_nc_u32_e32 v7, s10, v6
v_cmp_le_u32_e32 vcc_lo, s10, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v6, v6, v7, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s9, v1
v_xor_b32_e32 v6, v6, v2
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v6, v2
v_sub_nc_u32_e32 v7, v5, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[5:6], null, v7, s8, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 3, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v5, s0, s6, v5
v_add_co_ci_u32_e64 v6, s0, s7, v6, s0
global_store_b64 v[5:6], v[3:4], off
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| unpack_matrix | 1,312 | 1,515 | stackv2-00000-of-00015 |
// Demangled: monteKarlo(float, unsigned int*)
Function : _Z10monteKarlofPj
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R5, SR_TID.Y &wr=0x1 ?trans7;
LDC R0, c[0x0][0x360] &wr=0x2 ?trans1;
LDCU UR6, c[0x0][0x380] &wr=0x3 ?trans1;
BSSY.RECONVERGENT B0, 0x1d0 ?trans1;
S2R R3, SR_TID.X &wr=0x2 ?trans5;
S2UR UR5, SR_CTAID.Y &wr=0x1 ?trans8;
LDC R2, c[0x0][0x364] &wr=0x1 ?trans8;
S2UR UR4, SR_CTAID.X &wr=0x2 ?trans1;
IMAD R2, R2, UR5, R5 &req={1} ?WAIT5_END_GROUP;
I2FP.F32.U32 R2, R2 ?trans1;
IMAD R0, R0, UR4, R3 &req={2} ?WAIT4_END_GROUP;
FMUL R2, R2, UR6 &req={3} ?trans1;
I2FP.F32.S32 R0, R0 ?WAIT3_END_GROUP;
FMUL R3, R2, R2 ?trans2;
FMUL R0, R0, UR6 ?WAIT4_END_GROUP;
FFMA R0, R0, R0, R3 ?WAIT4_END_GROUP;
MUFU.RSQ R3, R0 &rd=0x1 &wr=0x2 ?trans1;
IADD3 R2, PT, PT, R0, -0xd000000, RZ ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R2, 0x727fffff, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x180 &req={2,1,0} ?trans5;
MOV R7, 0x170 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x280 ?trans5;
BRA 0x1c0 ?trans5;
FMUL.FTZ R5, R0, R3 ?trans1;
FMUL.FTZ R3, R3, 0.5 ?WAIT3_END_GROUP;
FFMA R0, -R5, R5, R0 ?WAIT4_END_GROUP;
FFMA R0, R0, R3, R5 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
FSETP.GEU.AND P0, PT, R0, 100, PT ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
S2R R0, SR_LANEID &wr=0x0 ?trans1;
VOTEU.ANY UR6, UPT, PT ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
POPC R5, UR6 &wr=0x1 ?trans1;
LDC.64 R2, c[0x0][0x388] &wr=0x1 ?trans1;
UFLO.U32 UR7, UR6 ?WAIT6_END_GROUP;
ISETP.EQ.U32.AND P0, PT, R0, UR7, PT &req={0} ?WAIT13_END_GROUP;
@P0 REDG.E.ADD.STRONG.GPU desc[UR4][R2.64], R5 &req={1} ?trans1;
EXIT ?trans5;
LOP3.LUT P0, RZ, R0, 0x7fffffff, RZ, 0xc0, !PT ?WAIT13_END_GROUP;
@!P0 MOV R2, R0 ?trans1;
@!P0 BRA 0x3b0 ?trans6;
FSETP.GEU.FTZ.AND P0, PT, R0, RZ, PT ?WAIT13_END_GROUP;
@!P0 MOV R2, 0x7fffffff ?trans1;
@!P0 BRA 0x3b0 ?trans6;
FSETP.GTU.FTZ.AND P0, PT, |R0|, +INF , PT ?WAIT13_END_GROUP;
@P0 FADD.FTZ R2, R0, 1 ?trans1;
@P0 BRA 0x3b0 ?trans6;
FSETP.NEU.FTZ.AND P0, PT, |R0|, +INF , PT ?WAIT13_END_GROUP;
@P0 FFMA R3, R0, 1.84467440737095516160e+19, RZ ?WAIT4_END_GROUP;
@P0 MUFU.RSQ R2, R3 &wr=0x0 ?trans2;
@P0 FMUL.FTZ R4, R3, R2 &req={0} ?trans1;
@P0 FMUL.FTZ R6, R2, 0.5 ?trans1;
@!P0 MOV R2, R0 ?trans2;
@P0 FADD.FTZ R5, -R4, -RZ ?WAIT4_END_GROUP;
@P0 FFMA R5, R4, R5, R3 ?WAIT4_END_GROUP;
@P0 FFMA R5, R5, R6, R4 ?WAIT4_END_GROUP;
@P0 FMUL.FTZ R2, R5, 2.3283064365386962891e-10 ?WAIT7_END_GROUP;
MOV R0, R2 ?trans1;
MOV R2, R7 ?trans1;
HFMA2 R3, -RZ, RZ, 0, 0 ?WAIT4_END_GROUP;
RET.REL.NODEC R2 0x0 ?trans5;
BRA 0x3f0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: monteKarlo(float, unsigned int*)
_Z10monteKarlofPj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x0
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
v_mad_u64_u32 v[3:4], null, s14, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v0, v2
v_cvt_f32_i32_e32 v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v0, s3, v0 :: v_dual_mul_f32 v1, s3, v1
v_mul_f32_e32 v0, v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v0, v1, v1
v_mul_f32_e32 v1, 0x4f800000, v0
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v1, vcc_lo
v_sqrt_f32_e32 v1, v0
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v2, -1, v1
v_add_nc_u32_e32 v3, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v4, -v2, v1, v0
v_fma_f32 v5, -v3, v1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s2, 0, v4
v_cndmask_b32_e64 v1, v1, v2, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s2, 0, v5
v_cndmask_b32_e64 v1, v1, v3, s2
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v2, 0x37800000, v1
v_cndmask_b32_e32 v1, v1, v2, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v0, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v1, v0, vcc_lo
v_cmpx_gt_f32_e32 0x42c80000, v0
s_cbranch_execz .LBB0_3
s_mov_b32 s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v0, s2, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 s3, exec_lo, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 exec_lo, s3
s_cbranch_execz .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x8
s_bcnt1_i32_b32 s2, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| monteKarlo | 1,430 | 1,259 | stackv2-00000-of-00015 |
// Demangled: k(int volatile*)
Function : _Z1kPVi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R5, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans1;
LDCU UR6, c[0x0][0x360] &wr=0x0 ?trans1;
S2R R0, SR_CTAID.X &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans1;
IMAD R5, R0, UR6, R5 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE R2, R5, 0x4, R2 &req={1} ?WAIT5_END_GROUP;
LDG.E.STRONG.SYS R0, desc[UR4][R2.64] &req={2} &wr=0x2 ?trans1;
MOV R4, 0x400 ?trans1;
S2R R9, SR_CgaCtaId &wr=0x0 ?trans4;
LEA R6, R9, R4, 0x18 &req={0} ?trans2;
IADD3 R4, PT, PT, R4, 0x80, RZ ?WAIT3_END_GROUP;
IMAD R7, R5.reuse, 0x4, R6.reuse ?trans2;
IMAD R6, R5, -0x4, R6 ?trans1;
LEA R4, R9, R4, 0x18 ?WAIT4_END_GROUP;
LEA R5, R5, R4, 0x2 ?trans1;
STS [R7], R0 &req={2} ?trans4;
LDS R6, [R6+0x7c] &wr=0x0 ?trans4;
STS [R5], R6 &req={0} ?trans4;
LDS R9, [R5] &wr=0x0 ?trans4;
STG.E.STRONG.SYS desc[UR4][R2.64], R9 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x170;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: k(int volatile*)
_Z1kPVi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b64 s[2:3], src_shared_base
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b32_e32 v7, 2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v7
flat_load_b32 v6, v[2:3] glc dlc
s_waitcnt vmcnt(0)
v_cndmask_b32_e32 v0, 0, v7, vcc_lo
v_cndmask_b32_e64 v1, 0, s3, vcc_lo
s_waitcnt lgkmcnt(0)
flat_store_b32 v[0:1], v6 dlc
s_waitcnt_vscnt null, 0x0
v_add_nc_u32_e32 v0, 0x80, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e32 vcc_lo, -1, v0
v_cndmask_b32_e32 v0, 0, v0, vcc_lo
v_sub_nc_u32_e32 v4, 0x7c, v7
v_cndmask_b32_e64 v1, 0, s3, vcc_lo
v_cmp_ne_u32_e64 s0, -1, v4
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v4, 0, v4, s0
v_cndmask_b32_e64 v5, 0, s3, s0
flat_load_b32 v4, v[4:5] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_store_b32 v[0:1], v4 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v0, v[0:1] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_store_b32 v[2:3], v0 dlc
s_waitcnt_vscnt null, 0x0
s_endpgm
| k | 578 | 823 | stackv2-00000-of-00015 |
// Demangled: vecAdd(int*, int*, int*)
Function : _Z6vecAddPiS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans8;
LDC R9, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R9, R9, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GT.AND P0, PT, R9, 0x241, PT ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD.WIDE R2, R9, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x4 ?trans1;
IMAD.WIDE R4, R9, 0x4, R4 &req={2} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR4][R4.64] &wr=0x4 ?trans1;
IMAD.WIDE R6, R9, 0x4, R6 &req={3} ?trans1;
IADD3 R9, PT, PT, R2, R5, RZ &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x130;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: vecAdd(int*, int*, int*)
_Z6vecAddPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x242, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| vecAdd | 544 | 552 | stackv2-00000-of-00015 |
// Demangled: MatrixMul(int*, int*, int*, int, int)
Function : _Z9MatrixMulPiS_S_ii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R11, SR_TID.X &wr=0x1 ?trans7;
LDC R5, c[0x0][0x364] &wr=0x2 ?trans1;
S2R R0, SR_TID.Y &wr=0x2 ?trans7;
S2UR UR5, SR_CTAID.X &wr=0x1 ?trans8;
LDC R4, c[0x0][0x360] &wr=0x1 ?trans8;
S2UR UR4, SR_CTAID.Y &wr=0x2 ?trans8;
LDC.64 R2, c[0x0][0x398] &wr=0x3 ?trans1;
IMAD R11, R4, UR5, R11 &req={1} ?WAIT2_END_GROUP;
IMAD R0, R5, UR4, R0 &req={2} ?WAIT3_END_GROUP;
ISETP.GE.AND P0, PT, R11, R2, PT &req={3} ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R0, R3, P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
ISETP.GE.AND P0, PT, R2, 0x1, PT ?WAIT13_END_GROUP;
@!P0 EXIT ?trans5;
LDC.64 R4, c[0x0][0x380] &wr=0x0 ?trans1;
ISETP.GE.U32.AND P1, PT, R2.reuse, 0x10, PT ?trans1;
LOP3.LUT R14, R2, 0xf, RZ, 0xc0, !PT ?trans1;
IMAD R11, R0, R2, R11 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans3;
ISETP.NE.AND P0, PT, R14, RZ, PT ?trans1;
LDC.64 R6, c[0x0][0x388] &wr=0x2 ?trans8;
LDC.64 R8, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD.WIDE R4, R11, 0x4, R4 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE R6, R11, 0x4, R6 &req={2} ?WAIT4_END_GROUP;
IMAD.WIDE R8, R11, 0x4, R8 &req={3} ?trans1;
@!P1 BRA 0x610 &req={1} ?trans6;
LDG.E R3, desc[UR4][R8.64] &rd=0x0 &wr=0x5 ?trans1;
LOP3.LUT R0, R2, 0x7ffffff0, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, -R0, RZ, RZ ?WAIT7_END_GROUP;
LDG.E R10, desc[UR4][R4.64] &wr=0x2 ?trans4;
LDG.E R11, desc[UR4][R6.64] &req={1} &wr=0x2 ?trans2;
IMAD R11, R10, R11, R3 &req={5,2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R8.64], R11 &rd=0x1 ?trans4;
LDG.E R10, desc[UR4][R4.64] &wr=0x2 ?trans4;
LDG.E R3, desc[UR4][R6.64] &wr=0x2 ?trans2;
IMAD R3, R10, R3, R11 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R8.64], R3 &rd=0x2 ?trans4;
LDG.E R10, desc[UR4][R4.64] &wr=0x3 ?trans4;
LDG.E R12, desc[UR4][R6.64] &wr=0x3 ?trans2;
IMAD R13, R10, R12, R3 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R8.64], R13 &rd=0x3 ?trans4;
LDG.E R10, desc[UR4][R4.64] &wr=0x1 ?trans4;
LDG.E R12, desc[UR4][R6.64] &wr=0x1 ?trans2;
IMAD R11, R10, R12, R13 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR4][R8.64], R11 &rd=0x1 ?trans4;
LDG.E R10, desc[UR4][R4.64] &wr=0x2 ?trans4;
LDG.E R12, desc[UR4][R6.64] &wr=0x2 ?trans2;
IMAD R3, R10, R12, R11 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R8.64], R3 &rd=0x2 ?trans4;
LDG.E R10, desc[UR4][R4.64] &wr=0x3 ?trans4;
LDG.E R12, desc[UR4][R6.64] &wr=0x3 ?trans2;
IMAD R13, R10, R12, R3 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R8.64], R13 &rd=0x3 ?trans4;
LDG.E R10, desc[UR4][R4.64] &wr=0x1 ?trans4;
LDG.E R12, desc[UR4][R6.64] &wr=0x1 ?trans2;
IMAD R11, R10, R12, R13 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR4][R8.64], R11 &rd=0x1 ?trans4;
LDG.E R10, desc[UR4][R4.64] &wr=0x2 ?trans4;
LDG.E R12, desc[UR4][R6.64] &wr=0x2 ?trans2;
IMAD R3, R10, R12, R11 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R8.64], R3 &rd=0x2 ?trans4;
LDG.E R10, desc[UR4][R4.64] &wr=0x3 ?trans4;
LDG.E R12, desc[UR4][R6.64] &wr=0x3 ?trans2;
IMAD R13, R10, R12, R3 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R8.64], R13 &rd=0x3 ?trans4;
LDG.E R10, desc[UR4][R4.64] &wr=0x1 ?trans4;
LDG.E R12, desc[UR4][R6.64] &wr=0x1 ?trans2;
IMAD R11, R10, R12, R13 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR4][R8.64], R11 &rd=0x1 ?trans4;
LDG.E R10, desc[UR4][R4.64] &wr=0x2 ?trans4;
LDG.E R12, desc[UR4][R6.64] &wr=0x2 ?trans2;
IMAD R3, R10, R12, R11 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R8.64], R3 &rd=0x2 ?trans4;
LDG.E R10, desc[UR4][R4.64] &wr=0x3 ?trans4;
LDG.E R12, desc[UR4][R6.64] &wr=0x3 ?trans2;
IMAD R13, R10, R12, R3 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R8.64], R13 &rd=0x3 ?trans4;
LDG.E R10, desc[UR4][R4.64] &wr=0x1 ?trans4;
LDG.E R12, desc[UR4][R6.64] &wr=0x1 ?trans2;
IMAD R11, R10, R12, R13 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR4][R8.64], R11 &rd=0x1 ?trans4;
LDG.E R10, desc[UR4][R4.64] &wr=0x4 ?trans4;
LDG.E R12, desc[UR4][R6.64] &wr=0x4 ?trans2;
IMAD R15, R10, R12, R11 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R8.64], R15 &rd=0x1 ?trans4;
LDG.E R10, desc[UR4][R4.64] &wr=0x3 ?trans4;
LDG.E R3, desc[UR4][R6.64] &req={2} &wr=0x3 ?trans1;
IADD3 R0, PT, PT, R0, 0x10, RZ ?trans1;
IMAD R13, R10, R3, R15 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R8.64], R13 &rd=0x1 ?trans4;
LDG.E R10, desc[UR4][R4.64] &wr=0x2 ?trans4;
LDG.E R3, desc[UR4][R6.64] &wr=0x2 ?trans1;
ISETP.NE.AND P1, PT, R0, RZ, PT ?trans1;
IMAD R3, R10, R3, R13 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R8.64], R3 &rd=0x1 ?trans7;
@P1 BRA 0x1e0 ?trans5;
@!P0 EXIT ?trans5;
ISETP.GE.U32.AND P0, PT, R14, 0x8, PT ?trans1;
LOP3.LUT R12, R2, 0x7, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R12, RZ, PT ?WAIT7_END_GROUP;
@!P0 BRA 0x870 ?trans6;
LDG.E R0, desc[UR4][R4.64] &wr=0x2 ?trans4;
LDG.E R3, desc[UR4][R6.64] &req={1} &wr=0x2 ?trans4;
LDG.E R10, desc[UR4][R8.64] &wr=0x2 ?trans2;
IMAD R3, R0, R3, R10 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R8.64], R3 &rd=0x1 ?trans4;
LDG.E R0, desc[UR4][R4.64] &wr=0x2 ?trans4;
LDG.E R10, desc[UR4][R6.64] &wr=0x2 ?trans2;
IMAD R11, R0, R10, R3 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R8.64], R11 &rd=0x2 ?trans4;
LDG.E R0, desc[UR4][R4.64] &wr=0x3 ?trans4;
LDG.E R10, desc[UR4][R6.64] &wr=0x3 ?trans2;
IMAD R13, R0, R10, R11 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R8.64], R13 &rd=0x3 ?trans4;
LDG.E R0, desc[UR4][R4.64] &wr=0x1 ?trans4;
LDG.E R10, desc[UR4][R6.64] &wr=0x1 ?trans2;
IMAD R3, R0, R10, R13 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR4][R8.64], R3 &rd=0x1 ?trans4;
LDG.E R0, desc[UR4][R4.64] &wr=0x2 ?trans4;
LDG.E R10, desc[UR4][R6.64] &wr=0x2 ?trans2;
IMAD R11, R0, R10, R3 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R8.64], R11 &rd=0x2 ?trans4;
LDG.E R0, desc[UR4][R4.64] &wr=0x3 ?trans4;
LDG.E R10, desc[UR4][R6.64] &wr=0x3 ?trans2;
IMAD R13, R0, R10, R11 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R8.64], R13 &rd=0x3 ?trans4;
LDG.E R0, desc[UR4][R4.64] &wr=0x1 ?trans4;
LDG.E R10, desc[UR4][R6.64] &wr=0x1 ?trans2;
IMAD R3, R0, R10, R13 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR4][R8.64], R3 &rd=0x3 ?trans4;
LDG.E R0, desc[UR4][R4.64] &wr=0x2 ?trans4;
LDG.E R10, desc[UR4][R6.64] &wr=0x2 ?trans2;
IMAD R11, R0, R10, R3 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R8.64], R11 &rd=0x3 ?trans2;
@!P1 EXIT ?trans5;
ISETP.GE.U32.AND P0, PT, R12, 0x4, PT ?trans1;
LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R2, RZ, PT ?WAIT7_END_GROUP;
@!P0 BRA 0x9d0 ?trans6;
LDG.E R0, desc[UR4][R4.64] &wr=0x2 ?trans4;
LDG.E R3, desc[UR4][R6.64] &req={3,1} &wr=0x2 ?trans4;
LDG.E R10, desc[UR4][R8.64] &wr=0x2 ?trans2;
IMAD R3, R0, R3, R10 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R8.64], R3 &rd=0x1 ?trans4;
LDG.E R0, desc[UR4][R4.64] &wr=0x2 ?trans4;
LDG.E R10, desc[UR4][R6.64] &wr=0x2 ?trans2;
IMAD R11, R0, R10, R3 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R8.64], R11 &rd=0x2 ?trans4;
LDG.E R0, desc[UR4][R4.64] &wr=0x3 ?trans4;
LDG.E R10, desc[UR4][R6.64] &wr=0x3 ?trans2;
IMAD R13, R0, R10, R11 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R8.64], R13 &rd=0x2 ?trans4;
LDG.E R0, desc[UR4][R4.64] &wr=0x1 ?trans4;
LDG.E R10, desc[UR4][R6.64] &wr=0x1 ?trans2;
IMAD R3, R0, R10, R13 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR4][R8.64], R3 &rd=0x2 ?trans2;
@!P1 EXIT ?trans5;
LDG.E R3, desc[UR4][R8.64] &req={3,2,1} &rd=0x1 &wr=0x5 ?trans1;
IADD3 R2, PT, PT, -R2, RZ, RZ ?WAIT7_END_GROUP;
LDG.E R0, desc[UR4][R4.64] &req={2} &wr=0x2 ?trans4;
LDG.E R10, desc[UR4][R6.64] &wr=0x2 ?trans1;
IADD3 R2, PT, PT, R2, 0x1, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R2, RZ, PT ?trans1;
IMAD R3, R0, R10, R3 &req={5,2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R8.64], R3 &rd=0x2 ?trans7;
@P0 BRA 0xa00 ?trans5;
EXIT ?trans5;
BRA 0xa80;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: MatrixMul(int*, int*, int*, int, int)
_Z9MatrixMulPiS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s4, v1
s_and_b32 s2, vcc_lo, s2
s_cmp_gt_i32 s4, 0
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_3
s_load_b64 s[2:3], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v0, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v5, vcc_lo
s_load_b128 s[0:3], s[0:1], 0x0
global_load_b32 v6, v[0:1], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
.LBB0_2:
global_load_b32 v9, v[2:3], off
global_load_b32 v10, v[4:5], off
s_add_i32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s4, 0
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[7:8], null, v10, v9, v[6:7]
v_mov_b32_e32 v6, v7
global_store_b32 v[0:1], v7, off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| MatrixMul | 4,501 | 990 | stackv2-00000-of-00015 |
// Demangled: vectorAddition(float const*, float const*, float*, float)
Function : _Z14vectorAdditionPKfS0_Pff
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R0, SR_TID.X &wr=0x0 ?trans7;
S2UR UR6, SR_CTAID.X &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC R9, c[0x0][0x360] &wr=0x0 ?trans8;
LDC.64 R2, c[0x0][0x380] &wr=0x2 ?trans8;
LDC.64 R4, c[0x0][0x388] &wr=0x3 ?trans1;
IMAD R9, R9, UR6, R0 &req={0} ?WAIT7_END_GROUP;
LDC.64 R6, c[0x0][0x390] &wr=0x0 ?trans1;
LDCU UR6, c[0x0][0x398] &wr=0x4 ?trans1;
IMAD.WIDE R2, R9, 0x4, R2 &req={2} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans1;
IMAD.WIDE R4, R9, 0x4, R4 &req={3} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE R6, R9, 0x4, R6 &req={0} ?WAIT4_END_GROUP;
FADD R0, R2, R5 &req={2} ?WAIT4_END_GROUP;
FADD R9, R0, UR6 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x130;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: vectorAddition(float const*, float const*, float*, float)
_Z14vectorAdditionPKfS0_Pff:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s0, s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v2, s0, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| vectorAddition | 544 | 571 | stackv2-00000-of-00015 |
// Demangled: kernel(unsigned long*, float*)
Function : _Z6kernelPmPf
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
MOV.64 R6, 0x29a ?WAIT7_END_GROUP;
LDC.64 R4, c[0x0][0x388] &wr=0x1 ?trans1;
HFMA2 R9, -RZ, RZ, 4.1484375, -0.0 ?trans1;
STG.E.64 desc[UR4][R2.64], R6 &req={0} ?trans4;
STG.E desc[UR4][R4.64], R9 &req={1} ?trans1;
EXIT ?trans5;
BRA 0x90;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: kernel(unsigned long*, float*)
_Z6kernelPmPf:
s_load_b128 s[0:3], s[0:1], 0x0
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, 0x29a
v_mov_b32_e32 v2, 0x44268000
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_store_b64 v1, v[0:1], s[0:1]
global_store_b32 v1, v2, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| kernel | 291 | 160 | stackv2-00000-of-00015 |
// Demangled: global_mem(int*, int, int)
Function : _Z10global_memPiii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans8;
LDC R9, c[0x0][0x360] &wr=0x1 ?trans8;
LDC R11, c[0x0][0x388] &wr=0x2 ?trans1;
IMAD R0, R9, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, R11, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
ISETP.GE.AND P0, PT, R11, 0x1, PT ?WAIT13_END_GROUP;
@!P0 EXIT ?trans5;
LDC.64 R4, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
LDCU UR6, c[0x0][0x38c] &wr=0x2 ?trans2;
IMAD.WIDE R2, R0, 0x4, R4 &req={3,0} ?WAIT5_END_GROUP;
LDG.E R6, desc[UR4][R2.64] &req={1} &wr=0x3 ?trans1;
IMAD R0, R9, UR6, R0 &req={2} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, R11.reuse, PT ?trans1;
IADD3 R7, PT, PT, R6, R11, RZ &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R7 &rd=0x3 ?trans7;
@!P0 BRA 0xd0 ?trans5;
EXIT ?trans5;
BRA 0x150;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: global_mem(int*, int, int)
_Z10global_memPiii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB1_5
s_load_b64 s[0:1], s[0:1], 0x0
s_cmp_gt_i32 s2, 0
s_mov_b32 s5, 0
s_cselect_b32 s4, -1, 0
s_mul_i32 s3, s6, s3
.LBB1_2:
s_and_not1_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB1_4
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, s2, v0
global_store_b32 v[2:3], v0, off
.LBB1_4:
v_add_nc_u32_e32 v1, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s2, v1
s_or_b32 s5, vcc_lo, s5
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB1_2
.LBB1_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| global_mem | 565 | 637 | stackv2-00000-of-00015 |
// Demangled: shared_mem(int*, int, int)
Function : _Z10shared_memPiii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans8;
LDC R0, c[0x0][0x360] &wr=0x1 ?trans8;
LDC R2, c[0x0][0x388] &wr=0x2 ?trans1;
IMAD R3, R0, UR4, R3 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R3, R2, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
ISETP.GT.AND P0, PT, R2, RZ, PT ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x0 ?WAIT12_END_GROUP;
@P0 BRA 0x170 ?trans5;
BSSY.RECONVERGENT B0, 0x120 ?trans1;
LDCU UR4, c[0x0][0x38c] &wr=0x1 ?trans2;
MOV R5, R3 ?trans1;
IMAD R3, R0, UR4, R3 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R3, R2, PT ?WAIT13_END_GROUP;
@!P0 BRA 0xd0 ?trans5;
BSYNC.RECONVERGENT B0 &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans2;
IMAD.WIDE R2, R5, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E.CONSTANT R2, desc[UR6][R2.64] &wr=0x2 ?trans2;
I2FP.F32.S32 R5, R2 &req={2} ?trans1;
BRA 0x600 ?trans6;
LOP3.LUT R10, R2.reuse, 0x7ffffffc, RZ, 0xc0, !PT ?trans1;
BSSY.RECONVERGENT B0, 0x600 ?trans1;
LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ?trans2;
IADD3 R4, PT, PT, -R10, RZ, RZ ?WAIT7_END_GROUP;
LDC.64 R6, c[0x0][0x380] &wr=0x1 ?trans8;
LDC.64 R8, c[0x0][0x388] &wr=0x2 ?trans1;
IMAD.WIDE R6, R3, 0x4, R6 &req={1} ?WAIT6_END_GROUP;
LDG.E.CONSTANT R6, desc[UR6][R6.64] &req={0} &wr=0x3 ?trans1;
ISETP.GE.U32.AND P0, PT, R8, 0x4, PT &req={2} ?trans1;
IMAD R3, R0, R9, R3 ?WAIT5_END_GROUP;
ISETP.GE.AND P1, PT, R3, R8, PT ?trans1;
I2FP.F32.S32 R5, R6 &req={3} ?WAIT6_END_GROUP;
@!P0 BRA 0x560 ?trans6;
IADD3 R6, PT, PT, -R10, RZ, RZ ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R6, RZ, PT ?trans1;
MOV R6, R4 ?WAIT12_END_GROUP;
@P0 BRA 0x4f0 ?trans5;
IADD3 R7, PT, PT, -R6, RZ, RZ ?trans2;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x8 ?WAIT3_END_GROUP;
ISETP.GT.AND P2, PT, R7, 0xc, PT ?WAIT13_END_GROUP;
@!P2 BRA 0x400 ?trans5;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x80 ?WAIT13_END_GROUP;
FADD R5, R5, 1 ?trans1;
IADD3 R6, PT, PT, R6, 0x10, RZ ?WAIT3_END_GROUP;
FADD R5, R5, 1 ?trans2;
ISETP.GE.AND P2, PT, R6, -0xc, PT ?trans2;
FADD R5, R5, 1 ?WAIT4_END_GROUP;
FADD R5, R5, 1 ?WAIT4_END_GROUP;
FADD R5, R5, 1 ?WAIT4_END_GROUP;
FADD R5, R5, 1 ?WAIT4_END_GROUP;
FADD R5, R5, 1 ?WAIT4_END_GROUP;
FADD R5, R5, 1 ?WAIT4_END_GROUP;
FADD R5, R5, 1 ?WAIT4_END_GROUP;
FADD R5, R5, 1 ?WAIT4_END_GROUP;
FADD R5, R5, 1 ?WAIT4_END_GROUP;
FADD R5, R5, 1 ?WAIT4_END_GROUP;
FADD R5, R5, 1 ?WAIT4_END_GROUP;
FADD R5, R5, 1 ?WAIT4_END_GROUP;
FADD R5, R5, 1 ?WAIT4_END_GROUP;
FADD R5, R5, 1 ?trans1;
@!P2 BRA 0x2d0 ?trans6;
IADD3 R7, PT, PT, -R6, RZ, RZ ?WAIT5_END_GROUP;
ISETP.GT.AND P2, PT, R7, 0x4, PT ?WAIT13_END_GROUP;
@!P2 BRA 0x4d0 ?trans5;
FADD R5, R5, 1 ?trans1;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x80 ?trans2;
IADD3 R6, PT, PT, R6, 0x8, RZ ?trans1;
FADD R5, R5, 1 ?WAIT4_END_GROUP;
FADD R5, R5, 1 ?WAIT4_END_GROUP;
FADD R5, R5, 1 ?WAIT4_END_GROUP;
FADD R5, R5, 1 ?WAIT4_END_GROUP;
FADD R5, R5, 1 ?WAIT4_END_GROUP;
FADD R5, R5, 1 ?WAIT4_END_GROUP;
FADD R5, R5, 1 ?WAIT7_END_GROUP;
ISETP.NE.OR P0, PT, R6, RZ, P0 ?WAIT13_END_GROUP;
@!P0 BRA 0x560 ?trans5;
IADD3 R6, PT, PT, R6, 0x4, RZ ?trans1;
FADD R5, R5, 1 ?WAIT4_END_GROUP;
ISETP.NE.AND P0, PT, R6, RZ, PT ?trans1;
FADD R5, R5, 1 ?WAIT4_END_GROUP;
FADD R5, R5, 1 ?WAIT4_END_GROUP;
FADD R5, R5, 1 ?WAIT4_END_GROUP;
@P0 BRA 0x4f0 ?trans5;
ISETP.NE.AND P0, PT, R2, RZ, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x5e0 ?trans5;
ISETP.NE.AND P0, PT, R2, 0x1, PT ?trans1;
FADD R5, R5, 1 ?WAIT4_END_GROUP;
ISETP.NE.AND P2, PT, R2, 0x2, P0 ?WAIT8_END_GROUP;
@P0 FADD R6, R5, 1 ?WAIT5_END_GROUP;
@P2 FADD R6, R6, 1 ?WAIT5_END_GROUP;
@P0 MOV R5, R6 ?WAIT7_END_GROUP;
@!P1 BRA 0x1b0 ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
S2UR UR5, SR_CgaCtaId &wr=0x0 ?trans1;
UMOV UR4, 0x400 ?trans2;
ULEA UR4, UR5, UR4, 0x18 &req={0} ?WAIT9_END_GROUP;
STS [UR4], R5 ?trans1;
EXIT ?trans5;
BRA 0x650;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: shared_mem(int*, int, int)
_Z10shared_memPiii:
s_endpgm
| shared_mem | 2,133 | 14 | stackv2-00000-of-00015 |
// Demangled: add(int*, int*, int*)
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R9, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R9.reuse, 0x4, R4 &req={2} ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans4;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R6, R9, 0x4, R6 &req={3} ?trans1;
IADD3 R9, PT, PT, R2, R5, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0xe0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: add(int*, int*, int*)
_Z3addPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| add | 424 | 191 | stackv2-00000-of-00015 |
// Demangled: conv1d(float*, float*)
Function : _Z6conv1dPfS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R7, SR_TID.X &wr=0x0 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x2 ?trans7;
LDC R0, c[0x0][0x360] &wr=0x1 ?trans8;
LDC.64 R2, c[0x0][0x380] &wr=0x3 ?trans1;
ISETP.NE.AND P0, PT, R7, RZ, PT &req={0} ?trans1;
IMAD R5, R0, UR4, R7 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE R2, R5, 0x4, R2 &req={3} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR6][R2.64+0x4] &req={2} &wr=0x2 ?trans4;
@!P0 LDG.E R4, desc[UR6][R2.64] &wr=0x3 ?trans4;
@!P0 LDG.E R6, desc[UR6][R2.64+0x14] &wr=0x4 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x0 ?trans1;
UMOV UR4, 0x400 ?trans1;
SHF.R.S32.HI R10, RZ, 0x1f, R5 ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={0} ?WAIT6_END_GROUP;
LEA R7, R7, UR4, 0x2 ?WAIT5_END_GROUP;
STS [R7+0x4], R0 &req={2} ?trans4;
@!P0 STS [UR4], R4 &req={3} ?trans4;
@!P0 STS [UR4+0x14], R6 &req={4} ?trans1;
LDCU.64 UR4, c[0x0][0x388] &wr=0x0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
LEA R2, P0, R5, UR4, 0x2 &req={0} ?WAIT4_END_GROUP;
LEA.HI.X R3, R5, UR5, R10, 0x2, P0 ?trans1;
LDS R8, [R7] &wr=0x0 ?trans4;
LDS R9, [R7+0x4] &wr=0x1 ?trans4;
LDS R11, [R7+0x8] &wr=0x2 ?trans1;
FADD R8, RZ, R8 &req={0} ?WAIT4_END_GROUP;
FADD R8, R8, R9 &req={1} ?WAIT4_END_GROUP;
FADD R11, R8, R11 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R11 ?trans1;
EXIT ?trans5;
BRA 0x200;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: conv1d(float*, float*)
_Z6conv1dPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v5, 2, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v2, vcc_lo
s_mov_b32 s0, exec_lo
global_load_b32 v6, v[3:4], off offset:4
s_waitcnt vmcnt(0)
ds_store_b32 v5, v6 offset:4
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_2
s_clause 0x1
global_load_b32 v0, v[3:4], off
global_load_b32 v3, v[3:4], off offset:20
v_mov_b32_e32 v4, 0
s_waitcnt vmcnt(0)
ds_store_2addr_b32 v4, v0, v3 offset1:5
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[3:4], v5 offset1:1
ds_load_b32 v0, v5 offset:8
s_waitcnt lgkmcnt(1)
v_add_f32_e32 v3, 0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v3, v4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v0
v_add_co_u32 v0, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v2, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| conv1d | 846 | 736 | stackv2-00000-of-00015 |
// Demangled: cuda_xor(char*, char*, int, unsigned long)
Function : _Z8cuda_xorPcS_im
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R5, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x390] &wr=0x2 ?trans1;
IMAD R4, R4, UR4, R5 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R4, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDCU.64 UR4, c[0x0][0x380] &wr=0x0 ?trans1;
SHF.R.S32.HI R5, RZ, 0x1f, R4 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x1 ?trans4;
IADD.64 R2, R4, UR4 &req={0} ?trans2;
LDCU UR4, c[0x0][0x39c] &wr=0x0 ?trans4;
LDG.E.U8 R0, desc[UR6][R2.64] &req={1} &rd=0x1 &wr=0x5 ?trans1;
BSSY.RECONVERGENT B0, 0x290 ?trans1;
LOP3.LUT R6, R5, UR4, RZ, 0xfc, !PT &req={0} ?WAIT5_END_GROUP;
ISETP.NE.U32.AND P0, PT, R6, RZ, PT ?WAIT13_END_GROUP;
@P0 BRA 0x260 &req={1} ?trans5;
LDCU UR5, c[0x0][0x398] &wr=0x0 ?trans1;
HFMA2 R6, -RZ, RZ, 0, 0 ?trans1;
UI2F.U32.RP UR4, UR5 &req={0} ?trans2;
ISETP.NE.U32.AND P1, PT, RZ, UR5, PT ?WAIT7_END_GROUP;
MUFU.RCP R5, UR4 &wr=0x0 ?trans2;
IADD3 R5, PT, PT, R5, 0xffffffe, RZ &req={0} ?WAIT4_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R7, R5 &rd=0x0 &wr=0x1 ?trans2;
MOV R5, RZ &req={0} ?trans1;
IADD3 R9, PT, PT, RZ, -R7, RZ &req={1} ?WAIT5_END_GROUP;
IMAD R9, R9, UR5, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R7, R7, R9, R6 ?WAIT6_END_GROUP;
IMAD.HI.U32 R7, R7, R4, RZ ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, -R7, RZ, RZ ?WAIT5_END_GROUP;
IMAD R4, R7, UR5, R4 ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R4, UR5, PT ?WAIT13_END_GROUP;
@P0 IADD3 R4, PT, PT, R4, -UR5, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R4, UR5, PT ?WAIT13_END_GROUP;
@P0 IADD3 R4, PT, PT, R4, -UR5, RZ ?trans2;
@!P1 LOP3.LUT R4, RZ, UR5, RZ, 0x33, !PT ?trans1;
BRA 0x280 ?trans6;
MOV R6, 0x280 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x2f0 &req={5} ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
LDCU.64 UR4, c[0x0][0x388] &wr=0x0 ?trans2;
IADD.64 R4, R4, UR4 &req={0} ?WAIT7_END_GROUP;
LDG.E.U8 R5, desc[UR6][R4.64] &wr=0x2 ?trans2;
LOP3.LUT R7, R5, R0, RZ, 0x3c, !PT &req={5,2} ?WAIT5_END_GROUP;
STG.E.U8 desc[UR6][R2.64], R7 ?trans1;
EXIT ?trans5;
LDCU.64 UR4, c[0x0][0x398] &wr=0x0 ?trans1;
LDC.64 R8, c[0x0][0x398] &wr=0x1 ?trans1;
I2F.U64.RP R7, UR4 &req={0} &wr=0x0 ?trans2;
MUFU.RCP R7, R7 &req={0} &wr=0x0 ?trans2;
IADD3 R10, PT, PT, R7, 0x1ffffffe, RZ &req={0} ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2I.U64.TRUNC R10, R10 &wr=0x1 ?trans2;
IMAD.WIDE.U32 R12, R10, R8, RZ &req={1} ?WAIT4_END_GROUP;
IMAD R13, R10, R9, R13 ?trans1;
IADD3 R15, P0, PT, RZ, -R12, RZ ?WAIT3_END_GROUP;
IMAD R13, R11, R8, R13 ?trans2;
IMAD.HI.U32 R12, R10, R15, RZ ?WAIT3_END_GROUP;
IADD3.X R17, PT, PT, RZ, ~R13, RZ, P0, !PT ?trans1;
MOV R13, R10 ?WAIT4_END_GROUP;
IMAD R19, R11, R17.reuse, RZ ?trans2;
IMAD.WIDE.U32 R12, P0, R10, R17, R12 ?WAIT4_END_GROUP;
IMAD.HI.U32 R7, R11, R17, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R12, P1, R11, R15, R12 ?trans1;
IADD3.X R7, PT, PT, R7, R11, RZ, P0, !PT ?WAIT4_END_GROUP;
IADD3 R13, P2, PT, R19, R12, RZ ?WAIT4_END_GROUP;
IADD3.X R7, PT, PT, RZ, RZ, R7, P2, P1 ?trans1;
IMAD.WIDE.U32 R10, R13, R8, RZ ?WAIT4_END_GROUP;
IMAD R11, R13, R9, R11 ?trans1;
IADD3 R15, P0, PT, RZ, -R10, RZ ?WAIT3_END_GROUP;
IMAD R11, R7, R8, R11 ?trans2;
IMAD.HI.U32 R12, R13, R15, RZ ?WAIT3_END_GROUP;
IADD3.X R10, PT, PT, RZ, ~R11, RZ, P0, !PT ?trans1;
HFMA2 R11, -RZ, RZ, 0, 0 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R12, P0, R13, R10, R12 ?WAIT4_END_GROUP;
IMAD R14, R7.reuse, R10, RZ ?trans2;
IMAD.HI.U32 R13, P1, R7, R15, R12 ?WAIT4_END_GROUP;
IMAD.HI.U32 R10, R7, R10, RZ ?trans1;
IADD3 R13, P2, PT, R14, R13, RZ ?WAIT4_END_GROUP;
IADD3.X R7, PT, PT, R10, R7, RZ, P0, !PT ?trans1;
IMAD.HI.U32 R10, R13, R4, RZ ?WAIT3_END_GROUP;
IADD3.X R7, PT, PT, RZ, RZ, R7, P2, P1 ?trans1;
IMAD.WIDE.U32 R10, R13, R5, R10 ?WAIT4_END_GROUP;
IMAD R13, R7.reuse, R5, RZ ?trans2;
IMAD.HI.U32 R10, P0, R7, R4, R10 ?WAIT4_END_GROUP;
IMAD.HI.U32 R7, R7, R5, RZ ?trans1;
IADD3 R13, P1, PT, R13, R10, RZ ?WAIT4_END_GROUP;
IADD3.X R7, PT, PT, R7, RZ, RZ, P0, !PT ?trans1;
IMAD.WIDE.U32 R10, R13, R8, RZ ?WAIT3_END_GROUP;
IADD3.X R7, PT, PT, RZ, R7, RZ, P1, !PT ?trans1;
IMAD R9, R13, R9, R11 ?trans1;
ISETP.NE.S64.AND P1, PT, RZ, UR4, PT ?WAIT3_END_GROUP;
IMAD R9, R7, R8, R9 ?trans1;
MOV R8, R10 ?trans1;
HFMA2 R7, -RZ, RZ, 0, 0 ?WAIT4_END_GROUP;
IADD.64 R4, R4, -R8 ?WAIT6_END_GROUP;
ISETP.GE.U64.AND P0, PT, R4, UR4, PT ?WAIT14_END_GROUP;
@P0 IADD.64 R4, R4, -UR4 ?WAIT6_END_GROUP;
ISETP.GE.U64.AND P0, PT, R4, UR4, PT ?WAIT14_END_GROUP;
@P0 IADD.64 R4, R4, -UR4 ?WAIT4_END_GROUP;
SEL.64 R4, R4, -0x1, P1 ?trans2;
RET.REL.NODEC R6 0x0 ?trans6;
BRA 0x690;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: cuda_xor(char*, char*, int, unsigned long)
_Z8cuda_xorPcS_im:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v0, s2
v_cvt_f32_u32_e32 v2, s3
s_sub_u32 s4, 0, s2
s_subb_u32 s5, 0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v0, v2, 0x4f800000, v0
v_rcp_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x5f7ffffc, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v2, 0x2f800000, v0
v_trunc_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmamk_f32 v0, v2, 0xcf800000, v0
v_cvt_u32_f32_e32 v2, v2
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, s4, v2
v_mul_hi_u32 v4, s4, v0
v_mul_lo_u32 v5, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, v4, v3
v_mul_lo_u32 v4, s4, v0
v_add_nc_u32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v0, v4
v_mul_lo_u32 v6, v0, v3
v_mul_hi_u32 v7, v0, v3
v_mul_hi_u32 v8, v2, v4
v_mul_lo_u32 v4, v2, v4
v_mul_hi_u32 v9, v2, v3
v_mul_lo_u32 v3, v2, v3
v_add_co_u32 v5, vcc_lo, v5, v6
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, v5, v4
v_add_co_ci_u32_e32 v4, vcc_lo, v6, v8, vcc_lo
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, v4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v3
v_add_co_ci_u32_e32 v2, vcc_lo, v2, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v3, s4, v0
v_mul_lo_u32 v5, s5, v0
v_mul_lo_u32 v4, s4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, v3, v4
v_mul_lo_u32 v4, s4, v0
s_load_b128 s[4:7], s[0:1], 0x0
v_add_nc_u32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v0, v4
v_mul_lo_u32 v6, v0, v3
v_mul_hi_u32 v7, v0, v3
v_mul_hi_u32 v8, v2, v4
v_mul_lo_u32 v4, v2, v4
v_mul_hi_u32 v9, v2, v3
v_mul_lo_u32 v3, v2, v3
v_add_co_u32 v5, vcc_lo, v5, v6
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, v5, v4
v_add_co_ci_u32_e32 v4, vcc_lo, v6, v8, vcc_lo
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v9, vcc_lo
v_ashrrev_i32_e32 v9, 31, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, v4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v3
v_add_co_ci_u32_e32 v8, vcc_lo, v2, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v10, v1, v0
v_mad_u64_u32 v[4:5], null, v9, v0, 0
v_mad_u64_u32 v[2:3], null, v1, v8, 0
v_mad_u64_u32 v[6:7], null, v9, v8, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, v10, v2
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v4
v_add_co_ci_u32_e32 v0, vcc_lo, v2, v5, vcc_lo
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v6
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v5, s3, v0
v_mad_u64_u32 v[2:3], null, s2, v0, 0
v_mul_lo_u32 v0, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v2, vcc_lo, v1, v2
v_add3_u32 v0, v3, v0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v9, v0
v_subrev_co_ci_u32_e64 v3, s0, s3, v3, vcc_lo
v_sub_co_ci_u32_e32 v0, vcc_lo, v9, v0, vcc_lo
v_sub_co_u32 v4, vcc_lo, v2, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_subrev_co_ci_u32_e64 v5, s0, 0, v3, vcc_lo
v_cmp_le_u32_e64 s0, s2, v2
v_subrev_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s3, v0
v_cndmask_b32_e64 v6, 0, -1, s0
v_cmp_le_u32_e64 s0, s2, v4
v_cndmask_b32_e64 v10, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, s3, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v7, 0, -1, s0
v_cmp_le_u32_e64 s0, s3, v5
v_cndmask_b32_e64 v8, 0, -1, s0
v_cmp_eq_u32_e64 s0, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v7, v8, v7, vcc_lo
v_sub_co_u32 v8, vcc_lo, v4, s2
v_subrev_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v7
v_cndmask_b32_e64 v6, v10, v6, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v3, v5, v3 :: v_dual_cndmask_b32 v4, v4, v8
v_cmp_ne_u32_e32 vcc_lo, 0, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v3, v0, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v9, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_u8 v4, v[0:1], off
global_load_u8 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_xor_b32_e32 v2, v2, v4
global_store_b8 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| cuda_xor | 2,664 | 3,339 | stackv2-00000-of-00015 |
// Demangled: gpu_matrixmult(int*, int*, int*, int)
Function : _Z14gpu_matrixmultPiS_S_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R7, SR_TID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R0, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x364] &wr=0x2 ?trans1;
S2R R2, SR_TID.Y &wr=0x2 ?trans1;
LDCU UR18, c[0x0][0x398] &wr=0x3 ?trans1;
S2R R3, SR_CTAID.Y &wr=0x2 ?trans1;
IMAD R7, R0, UR4, R7 &req={1} ?trans2;
IMAD R2, R3, UR5, R2 &req={2} ?WAIT5_END_GROUP;
VIMNMX.S32 R0, R7, R2, !PT ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, UR18, PT &req={3} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
UISETP.GE.U32.AND UP0, UPT, UR18, 0x8, UPT ?trans1;
UMOV UR4, URZ ?trans1;
LDCU.64 UR16, c[0x0][0x358] &wr=0x0 ?trans1;
HFMA2 R0, -RZ, RZ, 0, 0 ?trans2;
IMAD R2, R2, UR18, RZ ?trans1;
PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x8 ?WAIT13_END_GROUP;
@!P0 BRA 0x510 ?trans5;
LDCU.128 UR20, c[0x0][0x380] &wr=0x1 ?trans1;
MOV R0, RZ ?trans1;
MOV R6, R7 ?trans1;
ULOP3.LUT UR5, UR18, 0x7ffffff8, URZ, 0xc0, !UPT ?WAIT4_END_GROUP;
UIADD3 UR5, UPT, UPT, -UR5, URZ, URZ ?trans1;
MOV.64 R4, UR20 &req={1} ?trans2;
UIMAD.WIDE UR6, UR18, 0x1c, UR22 ?trans1;
UIMAD.WIDE UR8, UR18, 0x18, UR22 ?trans1;
UIMAD.WIDE UR10, UR18, 0x14, UR22 ?trans1;
UIMAD.WIDE UR12, UR18, 0x10, UR22 ?trans1;
IMAD.WIDE.U32 R4, R2, 0x4, R4 ?trans1;
UIMAD.WIDE UR14, UR18, 0xc, UR22 ?WAIT4_END_GROUP;
IADD.64 R4, R4, 0x10 ?WAIT8_END_GROUP;
MOV R21, 0x4 ?trans1;
UIMAD.WIDE UR20, UR18, 0x4, UR22 ?trans1;
HFMA2 R11, -RZ, RZ, 0, 2.384185791015625e-07 ?trans1;
UIMAD.WIDE UR24, UR18, 0x8, UR22 ?trans1;
MOV R9, 0x4 ?trans1;
IMAD.WIDE R20, R6.reuse, R21, UR22 ?trans1;
LDG.E R12, desc[UR16][R4.64+-0x10] &req={0} &wr=0x2 ?trans3;
HFMA2 R19, -RZ, RZ, 0, 2.384185791015625e-07 ?trans2;
IMAD.WIDE R10, R6, R11, UR20 ?trans1;
LDG.E R13, desc[UR16][R20.64] &rd=0x0 &wr=0x2 ?trans1;
MOV R23, 0x4 ?WAIT2_END_GROUP;
IMAD.WIDE R8, R6.reuse, R9, UR24 ?trans1;
LDG.E R14, desc[UR16][R10.64] &rd=0x1 &wr=0x3 ?trans4;
LDG.E R15, desc[UR16][R4.64+-0xc] &wr=0x3 ?trans1;
IMAD.WIDE R18, R6, R19, UR14 ?WAIT4_END_GROUP;
HFMA2 R25, -RZ, RZ, 0, 2.384185791015625e-07 ?trans1;
LDG.E R16, desc[UR16][R8.64] &rd=0x4 &wr=0x5 ?trans1;
IMAD.WIDE R22, R6, R23, UR12 ?WAIT3_END_GROUP;
LDG.E R17, desc[UR16][R4.64+-0x8] &wr=0x5 ?trans1;
IMAD.WIDE R20, R6, R25, UR10 &req={0} ?WAIT3_END_GROUP;
LDG.E R18, desc[UR16][R18.64] &wr=0x5 ?trans4;
LDG.E R24, desc[UR16][R4.64+-0x4] &wr=0x5 ?trans1;
MOV R11, 0x4 &req={1} ?trans1;
IMAD.WIDE R8, R6.reuse, R25, UR8 &req={4} ?trans2;
LDG.E R22, desc[UR16][R22.64] &wr=0x4 ?trans4;
LDG.E R26, desc[UR16][R4.64] &wr=0x4 ?trans1;
IMAD.WIDE R10, R6, R11, UR6 ?WAIT3_END_GROUP;
LDG.E R20, desc[UR16][R20.64] &wr=0x4 ?trans4;
LDG.E R28, desc[UR16][R4.64+0x4] &wr=0x4 ?trans4;
LDG.E R8, desc[UR16][R8.64] &rd=0x0 &wr=0x4 ?trans4;
LDG.E R30, desc[UR16][R4.64+0x8] &wr=0x4 ?trans4;
LDG.E R10, desc[UR16][R10.64] &wr=0x4 ?trans4;
LDG.E R19, desc[UR16][R4.64+0xc] &rd=0x1 &wr=0x4 ?trans1;
UIADD3 UR5, UPT, UPT, UR5, 0x8, URZ ?WAIT6_END_GROUP;
ISETP.NE.AND P0, PT, RZ, UR5, PT ?trans1;
MOV R9, UR18 &req={0} ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x8, URZ ?trans1;
IADD.64 R4, R4, 0x20 &req={1} ?WAIT3_END_GROUP;
IMAD R6, R9, 0x8, R6 ?trans2;
IMAD R12, R12, R13, R0 &req={2} ?WAIT4_END_GROUP;
IMAD R12, R15, R14, R12 &req={3} ?WAIT4_END_GROUP;
IMAD R17, R17, R16, R12 &req={5} ?WAIT4_END_GROUP;
IMAD R17, R24, R18, R17 ?WAIT4_END_GROUP;
IMAD R17, R26, R22, R17 &req={4} ?WAIT4_END_GROUP;
IMAD R17, R28, R20, R17 ?WAIT4_END_GROUP;
IMAD R8, R30, R8, R17 ?WAIT4_END_GROUP;
IMAD R0, R19, R10, R8 ?trans1;
@P0 BRA 0x210 ?trans6;
ULOP3.LUT UR5, UR18, 0x7, URZ, 0xc0, !UPT ?WAIT6_END_GROUP;
ISETP.NE.AND P0, PT, RZ, UR5, PT ?WAIT13_END_GROUP;
@!P0 BRA 0xa80 ?trans5;
UISETP.GE.U32.AND UP0, UPT, UR5, 0x4, UPT ?trans1;
ULOP3.LUT UR6, UR18, 0x3, URZ, 0xc0, !UPT ?WAIT5_END_GROUP;
PLOP3.LUT P1, PT, PT, PT, UP0, 0x80, 0x8 ?trans1;
ISETP.NE.AND P0, PT, RZ, UR6, PT ?WAIT12_END_GROUP;
@!P1 BRA 0x7e0 ?trans5;
LDC.64 R8, c[0x0][0x388] &wr=0x1 ?trans1;
LDCU.64 UR8, c[0x0][0x380] &wr=0x2 ?trans1;
HFMA2 R3, -RZ, RZ, 0, 0 ?trans1;
MOV R4, UR4 ?trans1;
MOV R12, UR18 ?trans1;
UMOV UR5, URZ ?trans1;
USHF.R.S32.HI UR7, URZ, 0x1f, UR18 ?trans1;
IADD.64 R18, R2, UR4 ?trans2;
LDC.64 R10, c[0x0][0x380] &wr=0x3 ?trans1;
IMAD R5, R4, UR18, R7 ?trans1;
IADD3 R17, PT, PT, R2, UR4, RZ ?trans1;
MOV R13, UR7 ?WAIT5_END_GROUP;
IADD.64 R14, R12, R12 ?WAIT3_END_GROUP;
LEA R4, P1, R18, UR8, 0x2 &req={2} ?trans1;
IMAD.WIDE R8, R5, 0x4, R8 &req={1} ?WAIT3_END_GROUP;
LEA.HI.X R5, R18, UR9, R19, 0x2, P1 ?trans1;
MOV R19, UR18 ?trans1;
LEA R18, P1, R14, R8, 0x2 ?trans1;
LDG.E R6, desc[UR16][R8.64] &req={0} &wr=0x2 ?trans1;
IMAD.WIDE.U32 R10, R17, 0x4, R10 &req={3} ?trans1;
IADD.64 R16, R12, R14 ?trans2;
LDG.E R21, desc[UR16][R4.64+0x4] &wr=0x3 ?trans1;
IMAD.WIDE R12, R19, 0x4, R8 ?trans1;
LEA.HI.X R19, R14, R9, R15, 0x2, P1 ?trans2;
LDG.E R11, desc[UR16][R10.64] &wr=0x2 ?trans1;
LEA R14, P1, R16, R8, 0x2 ?WAIT3_END_GROUP;
LDG.E R12, desc[UR16][R12.64] &wr=0x3 ?trans1;
LEA.HI.X R15, R16, R9, R17, 0x2, P1 ?WAIT3_END_GROUP;
LDG.E R18, desc[UR16][R18.64] &wr=0x4 ?trans4;
LDG.E R17, desc[UR16][R4.64+0x8] &wr=0x4 ?trans4;
LDG.E R23, desc[UR16][R4.64+0xc] &wr=0x5 ?trans4;
LDG.E R14, desc[UR16][R14.64] &wr=0x5 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x4, URZ ?trans1;
IMAD R6, R11, R6, R0 &req={2} ?WAIT4_END_GROUP;
IMAD R6, R21, R12, R6 &req={3} ?WAIT4_END_GROUP;
IMAD R6, R17, R18, R6 &req={4} ?WAIT4_END_GROUP;
IMAD R0, R23, R14, R6 &req={5} ?WAIT7_END_GROUP;
@!P0 BRA 0xa80 ?trans5;
UISETP.NE.AND UP0, UPT, UR6, 0x1, UPT ?trans1;
ULOP3.LUT UR5, UR18, 0x1, URZ, 0xc0, !UPT ?trans1;
MOV R6, UR4 ?WAIT3_END_GROUP;
UISETP.NE.U32.AND UP1, UPT, UR5, 0x1, UPT ?trans1;
PLOP3.LUT P1, PT, PT, PT, UP0, 0x80, 0x8 ?WAIT5_END_GROUP;
@UP0 LDCU.128 UR8, c[0x0][0x380] &wr=0x1 ?trans1;
PLOP3.LUT P2, PT, PT, PT, UP1, 0x80, 0x8 ?trans1;
@UP0 LDCU.64 UR12, c[0x0][0x380] &wr=0x2 ?trans3;
@!UP1 LDCU.128 UR20, c[0x0][0x380] &wr=0x3 ?trans3;
@P1 MOV R4, R2 ?trans1;
@P1 MOV R5, RZ ?trans1;
@P1 IADD3 R15, PT, PT, R2, UR4, RZ ?trans1;
@UP0 UMOV UR6, UR4 ?trans1;
@UP0 UMOV UR7, URZ ?trans1;
@UP0 UIADD3 UR4, UPT, UPT, UR4, 0x2, URZ ?trans1;
@P1 IADD.64 R8, R4, UR6 ?WAIT2_END_GROUP;
@P1 IMAD R5, R6, UR18, R7 ?trans1;
MOV.64 R10, UR8 &req={1} ?trans2;
MOV.64 R12, UR10 ?trans2;
MOV R6, UR4 ?trans1;
@P1 LEA R4, P0, R8, UR12, 0x2 &req={2} ?trans1;
@P1 IMAD.WIDE.U32 R10, R15, 0x4, R10 ?trans1;
MOV R15, UR18 ?WAIT3_END_GROUP;
@P1 IMAD.WIDE R12, R5, 0x4, R12 ?trans1;
@P1 LEA.HI.X R5, R8, UR13, R9, 0x2, P0 ?trans1;
@P1 LDG.E R23, desc[UR16][R10.64] &req={0} &rd=0x0 &wr=0x2 ?trans1;
MOV.64 R8, UR20 &req={3} ?WAIT3_END_GROUP;
@!P2 IADD3 R19, PT, PT, R2, UR4, RZ ?trans1;
MOV.64 R16, UR22 ?trans2;
@P1 IMAD.WIDE R14, R15, 0x4, R12 ?trans1;
@P1 LDG.E R4, desc[UR16][R4.64+0x4] &wr=0x3 ?trans3;
@!P2 IMAD R21, R6, UR18, R7 ?trans1;
@P1 LDG.E R12, desc[UR16][R12.64] &wr=0x2 ?trans1;
@!P2 IMAD.WIDE.U32 R8, R19, 0x4, R8 ?WAIT3_END_GROUP;
@P1 LDG.E R14, desc[UR16][R14.64] &wr=0x3 ?trans1;
@!P2 IMAD.WIDE R10, R21, 0x4, R16 &req={0} ?WAIT3_END_GROUP;
@!P2 LDG.E R9, desc[UR16][R8.64] &wr=0x4 ?trans4;
@!P2 LDG.E R10, desc[UR16][R10.64] &wr=0x4 ?trans1;
@P1 IMAD R23, R23, R12, R0 &req={2} ?WAIT4_END_GROUP;
@P1 IMAD R0, R4, R14, R23 &req={3} ?WAIT4_END_GROUP;
@!P2 IMAD R0, R9, R10, R0 &req={4} ?WAIT7_END_GROUP;
LDC.64 R4, c[0x0][0x390] &wr=0x1 ?trans1;
IADD3 R3, PT, PT, R7, R2, RZ ?WAIT5_END_GROUP;
IMAD.WIDE R2, R3, 0x4, R4 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR16][R2.64], R0 &req={0} ?trans1;
EXIT ?trans5;
BRA 0xad0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: gpu_matrixmult(int*, int*, int*, int)
_Z14gpu_matrixmultPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v2, v0, v1
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mul_lo_u32 v1, v1, s2
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s3, s2
v_mov_b32_e32 v5, v0
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s3, s3, -1
s_cmp_lg_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v8, v[3:4], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s2, v5
s_cbranch_scc1 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
.LBB0_5:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v1, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| gpu_matrixmult | 4,507 | 1,274 | stackv2-00000-of-00015 |
// Demangled: velocityMagnitude(float*, float const*, float const*, float const*)
Function : _Z17velocityMagnitudePfPKfS1_S1_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
EXIT ?trans5;
BRA 0x20;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: velocityMagnitude(float*, float const*, float const*, float const*)
_Z17velocityMagnitudePfPKfS1_S1_:
s_endpgm
| velocityMagnitude | 100 | 20 | stackv2-00000-of-00015 |
// Demangled: test_builtin_variables()
Function : _Z22test_builtin_variablesv
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
EXIT ?trans5;
BRA 0x20;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: test_builtin_variables()
_Z22test_builtin_variablesv:
s_endpgm
| test_builtin_variables | 94 | 14 | stackv2-00000-of-00015 |
// Demangled: add(int*, int*, int*)
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R9, SR_CTAID.X &wr=0x1 ?trans2;
ISETP.GT.U32.AND P0, PT, R9, 0x9, PT &req={1} ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x3 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x4 ?trans1;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={1} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &req={2} &wr=0x2 ?trans1;
IMAD.WIDE.U32 R4, R9, 0x4, R4 &req={3} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R6, R9, 0x4, R6 &req={4} ?trans1;
IADD3 R9, PT, PT, R2, R5, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x100;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: add(int*, int*, int*)
_Z3addPiS_S_:
s_cmp_gt_i32 s15, 9
s_cbranch_scc1 .LBB0_2
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s8, s0
s_addc_u32 s3, s9, s1
s_add_u32 s6, s6, s0
s_addc_u32 s7, s7, s1
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
s_load_b32 s0, s[0:1], 0x0
s_load_b32 s1, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[2:3]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| add | 488 | 396 | stackv2-00000-of-00015 |
// Demangled: im2colN(float*, float const*, int, int, int, int, int, int)
Function : _Z7im2colNPfPKfiiiiii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R8, SR_TID.X &wr=0x1 ?trans7;
S2UR UR6, SR_CTAID.X &wr=0x2 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x2 ?trans1;
S2R R5, SR_TID.Y &wr=0x3 ?trans1;
LDCU.64 UR12, c[0x0][0x3a0] &wr=0x4 ?trans5;
S2UR UR5, SR_CTAID.Y &wr=0x3 ?trans8;
LDC R2, c[0x0][0x364] &wr=0x3 ?trans1;
UIMAD UR6, UR6, UR4, URZ &req={2} ?WAIT6_END_GROUP;
IADD3 R0, PT, PT, R8, UR6, RZ &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, UR13, PT &req={4} ?trans1;
IMAD R5, R2, UR5, R5 &req={3} ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R5, UR12, P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
S2UR UR4, SR_CTAID.Z &wr=0x0 ?trans1;
LDCU.64 UR8, c[0x0][0x390] &wr=0x1 ?trans1;
IMAD R2, R5, UR12, R0 ?trans1;
UIMAD UR7, UR13, UR12, URZ ?trans1;
LDCU.64 UR14, c[0x0][0x380] &wr=0x2 ?trans3;
SHF.R.S32.HI R3, RZ, 0x1f, R2 ?trans1;
LDC R10, c[0x0][0x39c] &wr=0x3 ?trans1;
UIMAD UR10, UR7, UR4, URZ &req={0} ?trans1;
UIMAD UR4, UR4, UR8, URZ &req={1} ?WAIT3_END_GROUP;
USHF.R.S32.HI UR11, URZ, 0x1f, UR10 ?trans1;
UIMAD UR4, UR4, UR9, URZ ?trans1;
ISETP.GE.AND P0, PT, R10, 0x1, PT &req={3} ?WAIT3_END_GROUP;
USHF.R.S32.HI UR5, URZ, 0x1f, UR4 ?trans1;
IADD.64 R2, R2, UR10 ?WAIT5_END_GROUP;
LEA R6, P1, R2, UR14, 0x2 &req={2} ?WAIT4_END_GROUP;
LEA.HI.X R7, R2, UR15, R3, 0x2, P1 ?trans1;
@!P0 EXIT ?trans8;
LDC R11, c[0x0][0x398] &wr=0x0 ?trans1;
IADD3 R4, PT, PT, R0.reuse, R10, RZ ?trans2;
IADD3 R9, PT, PT, R0.reuse, 0x1, RZ ?trans2;
IADD3 R12, PT, PT, R0, 0x3, RZ ?trans1;
LDCU.64 UR8, c[0x0][0x358] &wr=0x1 ?trans2;
VIMNMX.S32 R13, R4, R9, !PT ?trans1;
LDCU.64 UR12, c[0x0][0x388] &wr=0x2 ?trans4;
IADD3 R2, PT, PT, R8, UR6, -R13 ?WAIT2_END_GROUP;
IADD3 R13, PT, PT, -R0.reuse, R13, RZ ?trans2;
IADD3 R8, PT, PT, R5, R10, RZ ?trans2;
IADD3 R10, PT, PT, R0, 0x2, RZ ?trans1;
ISETP.GT.U32.AND P0, PT, R2, -0x4, PT ?trans1;
MOV.64 R2, R6 ?WAIT3_END_GROUP;
LOP3.LUT R13, R13, 0x3, RZ, 0xc0, !PT ?trans1;
IMAD R11, R11, UR7, RZ &req={0} ?WAIT5_END_GROUP;
SHF.R.S32.HI R14, RZ, 0x1f, R11 &req={2,1} ?WAIT7_END_GROUP;
ISETP.NE.AND P1, PT, R13, RZ, PT ?trans1;
BSSY.RECONVERGENT B0, 0x4d0 ?trans1;
MOV R15, R0 ?WAIT11_END_GROUP;
@!P1 BRA 0x4c0 &req={1} ?trans5;
LDCU UR10, c[0x0][0x394] &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x388] &wr=0x1 ?trans1;
IMAD R6, R5, UR10, R0 &req={0} ?WAIT5_END_GROUP;
SHF.R.S32.HI R7, RZ, 0x1f, R6 ?WAIT5_END_GROUP;
IADD.64 R6, R6, UR4 ?WAIT5_END_GROUP;
LEA R16, P1, R6, UR6, 0x2 &req={1} ?WAIT4_END_GROUP;
LEA.HI.X R17, R6, UR7, R7, 0x2, P1 ?WAIT5_END_GROUP;
LDG.E R19, desc[UR8][R16.64] &wr=0x2 ?trans1;
ISETP.NE.AND P1, PT, R13, 0x1, PT ?trans1;
SHF.L.U64.HI R7, R11.reuse, 0x2, R14 ?trans1;
IMAD.SHL.U32 R6, R11, 0x4, RZ ?trans1;
MOV R15, R9 ?trans1;
STG.E desc[UR8][R2.64], R19 &req={2} &rd=0x0 ?trans3;
IADD.64 R2, R2, R6 &req={0} ?WAIT6_END_GROUP;
@!P1 BRA 0x4c0 ?trans5;
LDG.E R19, desc[UR8][R16.64+0x4] &wr=0x2 ?trans1;
ISETP.NE.AND P1, PT, R13, 0x2, PT ?trans1;
MOV R15, R10 ?trans2;
STG.E desc[UR8][R2.64], R19 &req={2} &rd=0x0 ?trans2;
IMAD.WIDE R2, R11, 0x4, R2 &req={0} ?WAIT8_END_GROUP;
@!P1 BRA 0x4c0 ?trans5;
LDG.E R17, desc[UR8][R16.64+0x8] &wr=0x2 ?trans1;
MOV R15, R12 ?WAIT3_END_GROUP;
STG.E desc[UR8][R2.64], R17 &req={2} &rd=0x0 ?trans2;
IADD.64 R2, R2, R6 &req={0} ?WAIT8_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
BSSY.RECONVERGENT B0, 0x6b0 ?trans4;
@P0 BRA 0x6a0 ?trans5;
LDCU UR6, c[0x0][0x394] &wr=0x0 ?trans1;
SHF.L.U64.HI R7, R11.reuse, 0x3, R14 ?trans1;
IMAD.SHL.U32 R6, R11, 0x8, RZ ?trans2;
IMAD R25, R5, UR6, R15 &req={0} ?WAIT7_END_GROUP;
SHF.R.S32.HI R17, RZ, 0x1f, R25 ?trans1;
MOV R16, R25 ?WAIT5_END_GROUP;
IADD.64 R18, R16, UR4 &req={1} ?WAIT5_END_GROUP;
LEA R16, P1, R18, UR12, 0x2 ?WAIT4_END_GROUP;
LEA.HI.X R17, R18, UR13, R19, 0x2, P1 ?WAIT5_END_GROUP;
LDG.E R27, desc[UR8][R16.64] &wr=0x2 ?trans1;
IMAD.WIDE R18, R11, 0x4, R2 ?WAIT3_END_GROUP;
STG.E desc[UR8][R2.64], R27 &req={2} &rd=0x0 ?trans4;
LDG.E R29, desc[UR8][R16.64+0x4] &wr=0x2 ?trans1;
IADD.64 R20, R2, R6 ?WAIT3_END_GROUP;
STG.E desc[UR8][R18.64], R29 &req={2} &rd=0x1 ?trans4;
LDG.E R31, desc[UR8][R16.64+0x8] &wr=0x2 ?trans1;
IMAD R35, R14, 0xc, RZ ?trans2;
IMAD.WIDE.U32 R22, R11, 0xc, R2 ?trans1;
STG.E desc[UR8][R20.64], R31 &req={2} &rd=0x1 ?trans4;
LDG.E R33, desc[UR8][R16.64+0xc] &wr=0x2 ?trans1;
IADD3 R23, PT, PT, R23, R35, RZ ?WAIT2_END_GROUP;
IADD3 R15, PT, PT, R15, 0x4, RZ ?trans2;
IADD3 R25, PT, PT, R25, 0x4, RZ ?trans1;
IMAD.WIDE R2, R11, 0x10, R2 &req={0} ?trans2;
ISETP.GE.AND P1, PT, R15, R4, PT ?trans1;
STG.E desc[UR8][R22.64], R33 &req={2} &rd=0x1 ?WAIT12_END_GROUP;
@!P1 BRA 0x530 ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
IADD3 R5, PT, PT, R5, 0x1, RZ ?WAIT5_END_GROUP;
ISETP.GE.AND P1, PT, R5, R8, PT ?WAIT13_END_GROUP;
@!P1 BRA 0x2f0 ?trans5;
EXIT ?trans5;
BRA 0x6f0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: im2colN(float*, float const*, int, int, int, int, int, int)
_Z7im2colNPfPKfiiiiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[8:9], s[0:1], 0x20
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
s_mul_i32 s13, s13, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v1, s13, v4
v_cmp_gt_i32_e32 vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s9, v1
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_6
s_load_b128 s[4:7], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s7, 1
s_cbranch_scc1 .LBB0_6
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v0, s8, v[1:2]
v_add_nc_u32_e32 v7, s7, v0
v_add_nc_u32_e32 v8, s7, v1
s_mul_i32 s7, s9, s8
s_mul_i32 s4, s15, s4
s_mul_i32 s10, s7, s15
v_mul_lo_u32 v5, s5, v0
s_delay_alu instid0(VALU_DEP_4)
v_ashrrev_i32_e32 v3, 31, v2
s_ashr_i32 s11, s10, 31
s_mul_i32 s8, s4, s5
s_lshl_b64 s[10:11], s[10:11], 2
s_ashr_i32 s9, s8, 31
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_mul_i32 s6, s7, s6
v_add3_u32 v4, v4, v5, s13
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s10
s_addc_u32 s1, s1, s11
v_add_co_u32 v2, vcc_lo, s0, v2
s_lshl_b64 s[8:9], s[8:9], 2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_ashr_i32 s7, s6, 31
s_add_u32 s1, s2, s8
s_addc_u32 s4, s3, s9
s_lshl_b64 s[2:3], s[6:7], 2
s_mov_b32 s6, 0
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
v_mov_b32_e32 v9, v1
s_mov_b32 s7, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[4:5]
v_add_co_u32 v5, vcc_lo, s1, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s4, v6, vcc_lo
.LBB0_4:
global_load_b32 v10, v[5:6], off
v_add_nc_u32_e32 v9, 1, v9
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e32 vcc_lo, v9, v8
s_or_b32 s7, vcc_lo, s7
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v10, off
v_add_co_u32 v2, s0, v2, s2
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_4
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v0, 1, v0
v_add_nc_u32_e32 v4, s5, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, v0, v7
s_or_b32 s6, vcc_lo, s6
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_3
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| im2colN | 2,825 | 1,528 | stackv2-00000-of-00015 |
// Demangled: naiveKernel(double*, double const*, double const*)
Function : _Z11naiveKernelPdPKdS1_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R0, SR_TID.Y &wr=0x0 ?trans7;
S2UR UR6, SR_CTAID.Y &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
S2R R9, SR_TID.X &wr=0x2 ?trans6;
LDC R7, c[0x0][0x364] &wr=0x0 ?trans8;
S2UR UR7, SR_CTAID.X &wr=0x2 ?trans8;
LDC R6, c[0x0][0x360] &wr=0x2 ?trans8;
LDC.64 R4, c[0x0][0x388] &wr=0x3 ?trans1;
IMAD R7, R7, UR6, R0 &req={0} ?WAIT5_END_GROUP;
SHF.L.U32 R7, R7, 0x4, RZ ?trans2;
LDC.64 R2, c[0x0][0x390] &wr=0x0 ?trans1;
IMAD R0, R6, UR7, R9 &req={2} ?trans2;
IMAD.WIDE.U32 R4, R7, 0x8, R4 &req={3} ?WAIT5_END_GROUP;
LDG.E.64 R12, desc[UR4][R4.64] &req={1} &wr=0x2 ?trans1;
IMAD.WIDE R2, R0, 0x8, R2 &req={0} ?WAIT3_END_GROUP;
LDG.E.64 R16, desc[UR4][R4.64+0x8] &wr=0x3 ?trans4;
LDG.E.64 R14, desc[UR4][R2.64] &wr=0x2 ?trans4;
LDG.E.64 R18, desc[UR4][R2.64+0x80] &wr=0x3 ?trans4;
LDG.E.64 R8, desc[UR4][R4.64+0x10] &wr=0x4 ?trans4;
LDG.E.64 R10, desc[UR4][R2.64+0x100] &wr=0x4 ?trans4;
LDG.E.64 R22, desc[UR4][R2.64+0x180] &wr=0x5 ?trans4;
LDG.E.64 R24, desc[UR4][R2.64+0x200] &wr=0x3 ?trans4;
LDG.E.64 R26, desc[UR4][R2.64+0x280] &wr=0x3 ?trans4;
LDG.E.64 R28, desc[UR4][R2.64+0x300] &wr=0x3 ?trans4;
LDG.E.64 R20, desc[UR4][R4.64+0x38] &wr=0x3 ?trans4;
LDG.E.64 R30, desc[UR4][R2.64+0x380] &wr=0x3 ?trans4;
LDG.E.64 R34, desc[UR4][R2.64+0x400] &wr=0x3 ?trans4;
LDG.E.64 R36, desc[UR4][R2.64+0x780] &wr=0x3 ?trans1;
DFMA R12, R12, R14, RZ &req={2} &rd=0x0 &wr=0x3 ?trans3;
LDG.E.64 R14, desc[UR4][R4.64+0x20] &req={0} &wr=0x2 ?WAIT15_END_GROUP;
NOP ?trans1;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R32, R16, R18, R12 &req={3} &rd=0x0 &wr=0x4 ?trans2;
LDG.E.64 R12, desc[UR4][R4.64+0x18] &req={0} &wr=0x5 ?trans4;
LDG.E.64 R16, desc[UR4][R4.64+0x28] &wr=0x3 ?trans4;
LDG.E.64 R18, desc[UR4][R4.64+0x30] &wr=0x2 ?WAIT15_END_GROUP;
NOP ?WAIT9_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R8, R10, R32 &req={4} &rd=0x0 &wr=0x5 ?trans2;
LDG.E.64 R32, desc[UR4][R4.64+0x40] &req={0} &wr=0x4 ?trans4;
LDG.E.64 R10, desc[UR4][R4.64+0x50] &wr=0x3 ?WAIT15_END_GROUP;
NOP ?WAIT13_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R12, R22, R8 &req={5} &rd=0x0 &wr=0x2 ?trans2;
LDG.E.64 R22, desc[UR4][R2.64+0x600] &req={0} &wr=0x5 ?trans4;
LDG.E.64 R12, desc[UR4][R4.64+0x70] &wr=0x4 ?WAIT15_END_GROUP;
NOP ?WAIT13_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R14, R24, R8 &req={2} &rd=0x0 &wr=0x3 ?trans2;
LDG.E.64 R24, desc[UR4][R4.64+0x58] &req={0} &wr=0x2 ?trans4;
LDG.E.64 R14, desc[UR4][R2.64+0x700] &wr=0x2 ?WAIT15_END_GROUP;
NOP ?WAIT13_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R16, R26, R8 &req={3} &rd=0x0 &wr=0x1 ?trans2;
LDG.E.64 R26, desc[UR4][R2.64+0x580] &req={0} &wr=0x2 ?trans4;
LDG.E.64 R16, desc[UR4][R4.64+0x68] &wr=0x3 ?WAIT15_END_GROUP;
NOP ?WAIT13_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R18, R28, R8 &req={1} &rd=0x0 &wr=0x1 ?trans2;
LDG.E.64 R28, desc[UR4][R2.64+0x500] &req={0} &wr=0x2 ?trans4;
LDG.E.64 R18, desc[UR4][R2.64+0x680] &wr=0x3 ?WAIT15_END_GROUP;
NOP ?WAIT13_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R20, R20, R30, R8 &req={1} &rd=0x0 &wr=0x4 ?trans2;
LDG.E.64 R8, desc[UR4][R4.64+0x48] &req={0} &wr=0x2 ?trans4;
LDG.E.64 R30, desc[UR4][R2.64+0x480] &wr=0x2 ?WAIT15_END_GROUP;
NOP ?WAIT13_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R32, R32, R34, R20 &req={4} &rd=0x0 &wr=0x2 ?trans2;
LDG.E.64 R20, desc[UR4][R4.64+0x60] &req={0} &wr=0x5 ?trans4;
LDG.E.64 R34, desc[UR4][R4.64+0x78] &wr=0x4 ?trans1;
IADD3 R7, PT, PT, R0, R7, RZ ?WAIT15_END_GROUP;
NOP ?WAIT12_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R8, R30, R32 &req={2} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R10, R28, R8 &req={0} &rd=0x0 &wr=0x1 ?trans2;
LDC.64 R10, c[0x0][0x380] &req={0} &wr=0x0 ?trans2;
IMAD.WIDE R6, R7, 0x8, R10 &req={0} ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R24, R26, R8 &req={1} &wr=0x5 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R20, R22, R8 &req={5} &wr=0x3 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R16, R18, R8 &req={3} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R12, R14, R8 &req={0} &wr=0x4 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R34, R36, R8 &req={4} &wr=0x0 ?trans2;
STG.E.64 desc[UR4][R6.64], R8 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x770;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: naiveKernel(double*, double const*, double const*)
_Z11naiveKernelPdPKdS1_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_bfe_u32 v1, v0, 10, 10
s_load_b64 s[0:1], s[0:1], 0x10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_mul_i32 s15, s15, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_lshl_u32 v1, s15, v1, 4
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[6:7], 3, v[1:2]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
v_mad_u64_u32 v[4:5], null, s14, s2, v[0:1]
s_mov_b64 s[2:3], 0
v_add_co_u32 v0, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_mov_b32_e32 v5, v4
.LBB0_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v6, 31, v5
v_add_co_u32 v8, vcc_lo, v0, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v7, vcc_lo
v_lshlrev_b64 v[10:11], 3, v[5:6]
v_add_nc_u32_e32 v5, 16, v5
s_add_u32 s2, s2, 8
s_addc_u32 s3, s3, 0
s_cmpk_eq_i32 s2, 0x80
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, s0, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s1, v11, vcc_lo
global_load_b64 v[8:9], v[8:9], off
global_load_b64 v[10:11], v[10:11], off
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[8:9], v[10:11], v[2:3]
s_cbranch_scc0 .LBB0_1
v_add_nc_u32_e32 v0, v1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| naiveKernel | 2,751 | 1,068 | stackv2-00000-of-00015 |
// Demangled: tilingKernel(double*, double const*, double const*)
Function : _Z12tilingKernelPdPKdS1_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R11, SR_TID.Y &wr=0x0 ?trans7;
LDC.64 R22, c[0x0][0x388] &wr=0x1 ?trans1;
LDCU.64 UR8, c[0x0][0x358] &wr=0x2 ?trans1;
S2R R0, SR_CTAID.Y &wr=0x3 ?trans1;
S2R R4, SR_TID.X &wr=0x4 ?trans5;
LDC.64 R6, c[0x0][0x390] &wr=0x5 ?trans1;
S2R R2, SR_CTAID.X &wr=0x2 ?trans1;
IMAD.SHL.U32 R13, R11, 0x10, RZ &req={0} ?WAIT5_END_GROUP;
LEA R5, R0, R13, 0x7 &req={3} ?WAIT4_END_GROUP;
IADD3 R3, PT, PT, R5, R4, RZ &req={4} ?trans1;
IMAD R2, R2, 0x8, R4 &req={2} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R22, R3, 0x8, R22 &req={1} ?trans1;
IADD3 R13, PT, PT, R2, R13, RZ ?WAIT4_END_GROUP;
LDG.E.64 R14, desc[UR8][R22.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R8, R13, 0x8, R6 &req={5} ?WAIT5_END_GROUP;
LDG.E.64 R16, desc[UR8][R8.64] &wr=0x3 ?trans1;
S2UR UR6, SR_CgaCtaId &wr=0x0 ?trans1;
UMOV UR4, 0x400 ?trans2;
UIADD3 UR5, UPT, UPT, UR4, 0x200, URZ ?trans1;
ULEA UR4, UR6, UR4, 0x18 &req={0} ?WAIT3_END_GROUP;
ULEA UR5, UR6, UR5, 0x18 ?WAIT3_END_GROUP;
LEA R3, R11, UR4, 0x6 ?WAIT3_END_GROUP;
LEA R0, R4.reuse, UR5, 0x3 ?trans2;
LEA R4, R4, R3, 0x3 ?WAIT3_END_GROUP;
IMAD R32, R11, 0x40, R0 ?trans1;
IADD3 R13, PT, PT, R13, 0x80, RZ ?WAIT5_END_GROUP;
IMAD.WIDE.U32 R6, R13, 0x8, R6 ?trans1;
STS.64 [R4], R14 &req={2} ?trans4;
STS.64 [R32], R16 &req={3} ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS.64 R18, [R0] ?trans4;
LDS.128 R8, [R3] &wr=0x0 ?trans4;
LDS.64 R24, [R0+0x80] ?trans4;
LDS.64 R20, [R0+0xc0] ?trans4;
LDS.64 R30, [R0+0x100] ?trans4;
LDS.64 R28, [R0+0x140] ?trans4;
LDS.64 R26, [R0+0x180] ?trans4;
LDS.128 R12, [R3+0x20] ?trans1;
DFMA R8, R8, R18, RZ &req={0} &rd=0x0 &wr=0x1 ?trans3;
LDS.64 R18, [R0+0x40] &req={0} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?trans1;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R18, R10, R8 &req={1} &rd=0x0 &wr=0x1 ?trans2;
LDS.128 R8, [R3+0x10] &req={0} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R8, R24, R18 &req={1} &rd=0x0 &wr=0x1 ?trans2;
LDS.64 R24, [R0+0x1c0] &req={0} ?trans4;
LDS.128 R16, [R3+0x30] &wr=0x0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDG.E.64 R22, desc[UR8][R22.64+0x40] &wr=0x2 ?trans4;
LDG.E.64 R6, desc[UR8][R6.64] &wr=0x3 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R20, R10, R8 &req={1} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R12, R30, R8 &req={1} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R28, R14, R8 &req={1} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R16, R26, R8 &req={0} &wr=0x0 ?trans1;
STS.64 [R4], R22 &req={2} ?trans4;
STS.64 [R32], R6 &req={3} ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?WAIT15_END_GROUP;
NOP ?WAIT13_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R24, R18, R8 &req={0} &rd=0x0 &wr=0x1 ?trans1;
LDS.64 R12, [R0] ?trans4;
LDS.128 R8, [R3] &req={0} &wr=0x1 ?trans4;
LDS.64 R14, [R0+0x80] ?trans4;
LDS.64 R6, [R0+0x100] ?WAIT15_END_GROUP;
NOP ?WAIT6_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R8, R12, R18 &req={1} &rd=0x0 &wr=0x1 ?trans2;
LDS.64 R12, [R0+0x40] &req={0} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, R12, R10, R8 &req={1} &rd=0x0 &wr=0x1 ?trans2;
LDS.128 R8, [R3+0x10] &req={0} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R8, R14, R12 &req={1} &rd=0x0 &wr=0x1 ?trans2;
LDS.64 R12, [R0+0xc0] &req={0} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, R12, R10, R8 &req={1} &rd=0x0 &wr=0x1 ?trans2;
LDS.128 R8, [R3+0x20] &req={0} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R6, R8, R6, R12 &req={1} &rd=0x0 &wr=0x1 ?trans2;
LDS.64 R8, [R0+0x140] &req={0} &wr=0x1 ?trans4;
LDS.64 R12, [R0+0x180] ?WAIT15_END_GROUP;
NOP ?WAIT13_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R6, R8, R10, R6 &req={1} &rd=0x0 &wr=0x1 ?trans2;
LDS.128 R8, [R3+0x30] &req={0} &wr=0x1 ?trans1;
IADD3 R5, PT, PT, R2, R5, RZ ?WAIT15_END_GROUP;
NOP ?trans1;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R6, R8, R12, R6 &req={1} &rd=0x0 &wr=0x1 ?trans2;
LDS.64 R8, [R0+0x1c0] &req={0} &wr=0x1 ?trans1;
LDC.64 R12, c[0x0][0x380] &wr=0x0 ?trans2;
IMAD.WIDE R4, R5, 0x8, R12 &req={0} ?WAIT15_END_GROUP;
NOP ?WAIT14_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R6, R8, R10, R6 &req={1} &wr=0x0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
STG.E.64 desc[UR8][R4.64], R6 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x8a0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: tilingKernel(double*, double const*, double const*)
_Z12tilingKernelPdPKdS1_:
v_bfe_u32 v4, v0, 10, 10
v_and_b32_e32 v2, 0x3ff, v0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_mov_b32 s3, 0
s_mov_b32 s2, -1
v_lshlrev_b32_e32 v0, 4, v4
v_lshlrev_b32_e32 v6, 6, v4
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v5, s15, 7, v0
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v1, 0
v_lshlrev_b32_e32 v3, 3, v2
v_lshl_add_u32 v8, s14, 3, v2
v_add_nc_u32_e32 v10, v5, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v9, v6, v3
v_add_nc_u32_e32 v7, 0x200, v3
v_mov_b32_e32 v3, 0
v_add_nc_u32_e32 v11, v7, v6
.LBB1_1:
v_add_nc_u32_e32 v2, s3, v10
v_add_nc_u32_e32 v14, s3, v4
s_xor_b32 s2, s2, -1
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[12:13], 3, v[2:3]
v_lshl_add_u32 v2, v14, 4, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[14:15], 3, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v12, vcc_lo, s6, v12
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
v_mov_b32_e32 v2, v7
v_add_co_u32 v14, vcc_lo, s0, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s1, v15, vcc_lo
global_load_b64 v[12:13], v[12:13], off
global_load_b64 v[14:15], v[14:15], off
s_waitcnt vmcnt(1)
ds_store_b64 v9, v[12:13]
s_waitcnt vmcnt(0)
ds_store_b64 v11, v[14:15]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB1_2:
v_add_nc_u32_e32 v14, s3, v6
s_add_i32 s3, s3, 8
ds_load_b64 v[12:13], v2
ds_load_b64 v[14:15], v14
v_add_nc_u32_e32 v2, 64, v2
s_cmp_eq_u32 s3, 64
s_waitcnt lgkmcnt(0)
v_fma_f64 v[0:1], v[14:15], v[12:13], v[0:1]
s_cbranch_scc0 .LBB1_2
s_mov_b32 s3, 8
s_and_b32 vcc_lo, exec_lo, s2
s_mov_b32 s2, 0
s_barrier
buffer_gl0_inv
s_cbranch_vccz .LBB1_1
v_add_nc_u32_e32 v2, v5, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_store_b64 v[2:3], v[0:1], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| tilingKernel | 2,753 | 1,318 | stackv2-00000-of-00015 |
// Demangled: MatAdd(int (*) [2], int (*) [2], int (*) [2])
Function : _Z6MatAddPA2_iS0_S0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R9, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
S2R R11, SR_TID.Y &wr=0x2 ?trans6;
LDC.64 R4, c[0x0][0x388] &wr=0x3 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x4 ?trans1;
IMAD.WIDE.U32 R2, R9, 0x8, R2 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R9, 0x8, R4 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R2, R11, 0x4, R2 &req={2} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R11, 0x4, R4 ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans4;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R6, R9, 0x8, R6 &req={4} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R6, R11, 0x4, R6 ?trans1;
IADD3 R9, PT, PT, R2, R5, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x120;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: MatAdd(int (*) [2], int (*) [2], int (*) [2])
_Z6MatAddPA2_iS0_S0_:
s_load_b128 s[4:7], s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_lshrrev_b32_e32 v0, 8, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v4, 3, v1
v_and_b32_e32 v5, 0xffc, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s2, s4, v4
v_add_co_ci_u32_e64 v1, null, s5, 0, s2
v_add_co_u32 v2, s2, s6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e64 v3, null, s7, 0, s2
v_add_co_u32 v0, vcc_lo, v0, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
global_load_b32 v0, v[0:1], off
global_load_b32 v1, v[2:3], off
v_add_co_u32 v2, s0, s0, v4
v_add_co_ci_u32_e64 v3, null, s1, 0, s0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, v1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, v2, v5
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v3, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| MatAdd | 544 | 708 | stackv2-00000-of-00015 |
// Demangled: gpu_basic_mm(float*, float*, float*, unsigned long)
Function : _Z12gpu_basic_mmPfS_S_m
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x398] &wr=0x1 ?trans2;
ISETP.NE.S64.AND P0, PT, RZ, UR4, PT &req={1} ?WAIT14_END_GROUP;
@!P0 EXIT ?trans5;
S2R R2, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
HFMA2 R27, -RZ, RZ, 0, 0 ?trans1;
MOV R29, RZ ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x398] &wr=0x2 ?trans1;
LDCU.64 UR14, c[0x0][0x358] &wr=0x3 ?trans1;
ULOP3.LUT UR5, UR6, 0x3, URZ, 0xc0, !UPT &req={2} ?trans1;
USHF.L.U64.HI UR11, UR6, 0x5, UR7 ?trans1;
ULOP3.LUT UR12, UR6, 0xfffffff8, URZ, 0xc0, !UPT ?trans1;
USHF.L.U32 UR10, UR6, 0x5, URZ ?trans1;
USHF.L.U64.HI UR7, UR6, 0x2, UR7 ?WAIT2_END_GROUP;
MOV R28, UR5 ?trans1;
IMAD R2, R2, UR4, R3 &req={1} ?trans1;
ULOP3.LUT UR4, UR6, 0x7, URZ, 0xc0, !UPT ?trans1;
USHF.L.U32 UR6, UR6, 0x2, URZ ?WAIT3_END_GROUP;
SHF.R.S32.HI R3, RZ, 0x1f, R2 ?trans2;
MOV R26, UR4 ?trans1;
UMOV.64 UR4, URZ &req={3} ?WAIT6_END_GROUP;
LDC.64 R30, c[0x0][0x398] &req={1} &wr=0x1 ?trans1;
ISETP.NE.S64.AND P0, PT, R26, RZ, PT ?trans2;
MOV.64 R4, RZ ?trans2;
MOV R0, RZ ?trans1;
ISETP.GE.U64.AND P1, PT, R30, 0x8, PT &req={1} ?WAIT14_END_GROUP;
@!P1 BRA 0x530 ?trans5;
LDCU.64 UR8, c[0x0][0x380] &wr=0x1 ?trans1;
HFMA2 R0, -RZ, RZ, 0, 0 ?trans1;
MOV.64 R4, RZ ?trans2;
LDCU.64 UR16, c[0x0][0x388] &wr=0x2 ?trans1;
UIMAD UR13, UR7, UR4, URZ ?WAIT4_END_GROUP;
UIMAD UR13, UR5, UR6, UR13 ?trans1;
UIMAD.WIDE.U32 UR8, UR4, UR6, UR8 &req={1} ?WAIT4_END_GROUP;
UIADD3 UR9, UPT, UPT, UR9, UR13, URZ ?trans1;
LEA R6, P1, R2, UR16, 0x2 &req={2} ?WAIT5_END_GROUP;
LDCU UR13, c[0x0][0x39c] &wr=0x1 ?trans1;
LEA.HI.X R7, R2, UR17, R3, 0x2, P1 ?trans1;
UIADD3.64 UR8, UPT, UPT, UR8, 0x10, URZ ?WAIT6_END_GROUP;
MOV.64 R8, UR8 ?WAIT8_END_GROUP;
IADD.64 R12, R6, UR6 ?trans2;
LDG.E R23, desc[UR14][R8.64+-0x10] &wr=0x2 ?trans2;
IADD.64 R14, R12, UR6 ?trans2;
LDG.E R22, desc[UR14][R6.64] &wr=0x2 ?trans2;
IADD.64 R36, R14, UR6 ?trans2;
LDG.E R21, desc[UR14][R12.64] &rd=0x3 &wr=0x4 ?trans4;
LDG.E R20, desc[UR14][R8.64+-0xc] &wr=0x4 ?trans1;
IADD.64 R24, R36, UR6 ?WAIT3_END_GROUP;
LDG.E R19, desc[UR14][R14.64] &rd=0x5 &wr=0x4 ?trans4;
LDG.E R18, desc[UR14][R8.64+-0x8] &wr=0x4 ?trans1;
IADD.64 R10, R24, UR6 ?WAIT3_END_GROUP;
LDG.E R17, desc[UR14][R36.64] &wr=0x4 ?trans4;
LDG.E R16, desc[UR14][R8.64+-0x4] &wr=0x4 ?trans1;
IADD.64 R12, R10, UR6 &req={3} ?WAIT3_END_GROUP;
LDG.E R25, desc[UR14][R24.64] &wr=0x3 ?trans4;
LDG.E R34, desc[UR14][R8.64] &wr=0x3 ?trans1;
IADD.64 R14, R12, UR6 &req={5} ?WAIT3_END_GROUP;
LDG.E R10, desc[UR14][R10.64] &wr=0x5 ?trans4;
LDG.E R33, desc[UR14][R8.64+0x4] &wr=0x5 ?trans4;
LDG.E R32, desc[UR14][R12.64] &rd=0x1 &wr=0x5 ?trans4;
LDG.E R35, desc[UR14][R8.64+0x8] &wr=0x5 ?trans4;
LDG.E R15, desc[UR14][R14.64] &wr=0x5 ?trans4;
LDG.E R36, desc[UR14][R8.64+0xc] &rd=0x0 &wr=0x5 ?trans1;
IADD.64 R4, R4, 0x8 ?WAIT2_END_GROUP;
UMOV UR8, UR12 ?trans1;
UMOV UR9, UR13 &req={1} ?trans2;
IADD.64 R12, R4, -UR8 ?trans2;
UMOV UR8, UR10 ?trans1;
UMOV UR9, UR11 ?trans1;
IADD.64 R8, R8, 0x20 &req={0} ?trans2;
ISETP.NE.S64.AND P1, PT, R12, RZ, PT ?trans2;
IADD.64 R6, R6, UR8 ?WAIT2_END_GROUP;
FFMA R23, R23, R22, R0 &req={2} ?WAIT4_END_GROUP;
FFMA R21, R20, R21, R23 &req={4} ?WAIT4_END_GROUP;
FFMA R19, R18, R19, R21 ?WAIT4_END_GROUP;
FFMA R17, R16, R17, R19 ?WAIT4_END_GROUP;
FFMA R34, R34, R25, R17 &req={3} ?WAIT4_END_GROUP;
FFMA R10, R33, R10, R34 &req={5} ?WAIT4_END_GROUP;
FFMA R35, R35, R32, R10 ?WAIT4_END_GROUP;
FFMA R0, R36, R15, R35 ?trans1;
@P1 BRA 0x2a0 ?trans6;
@!P0 BRA 0xd30 ?trans5;
IADD.64 R6, R26, -0x1 ?trans2;
ISETP.NE.S64.AND P0, PT, R28, RZ, PT ?WAIT4_END_GROUP;
ISETP.GE.U64.AND P1, PT, R6, 0x3, PT ?WAIT14_END_GROUP;
@!P1 BRA 0x950 ?trans5;
LDC.64 R14, c[0x0][0x398] &wr=0x1 ?trans1;
IADD.64 R20, R4, 0x1 ?trans2;
HFMA2 R21, -RZ, RZ, 0, 0 ?WAIT5_END_GROUP;
LDC.64 R10, c[0x0][0x388] &wr=0x2 ?trans8;
LDC.64 R8, c[0x0][0x380] &wr=0x3 ?trans1;
IMAD R6, R5, R14.reuse, RZ &req={1} ?trans2;
IMAD.WIDE.U32 R18, R20, R14, R2 ?WAIT4_END_GROUP;
IMAD R13, R4, R15.reuse, R6 ?trans2;
IMAD R7, R20, R15, R19 ?trans1;
LEA R6, P2, R18, R10, 0x2 &req={2} ?trans1;
IMAD.WIDE.U32 R24, R4, R14, R2 ?WAIT3_END_GROUP;
LEA.HI.X R7, R18, R11, R7, 0x2, P2 ?trans1;
IMAD R22, R14.reuse, UR5, RZ ?trans1;
IADD3 R13, PT, PT, R25, R13, RZ ?trans1;
IMAD.WIDE.U32 R16, R14, UR4, R4 ?trans1;
IADD.64 R18, R4, 0x2 ?WAIT3_END_GROUP;
HFMA2 R25, -RZ, RZ, 0, 0 ?trans2;
IMAD R22, R15, UR4, R22 ?trans1;
LEA R12, P1, R24, R10, 0x2 ?trans1;
IMAD.WIDE.U32 R20, R14, UR4, R20 ?WAIT4_END_GROUP;
HFMA2 R33, -RZ, RZ, 0, 0 ?trans1;
LDG.E R6, desc[UR14][R6.64] &wr=0x2 ?trans1;
LEA.HI.X R13, R24, R11, R13, 0x2, P1 ?trans2;
IADD3 R17, PT, PT, R17, R22, RZ ?trans2;
LEA R36, P1, R16.reuse, R8, 0x2 &req={3} ?trans1;
MOV R24, R18 ?trans1;
LDG.E R12, desc[UR14][R12.64] &wr=0x3 ?trans2;
LEA.HI.X R37, R16, R9, R17, 0x2, P1 ?WAIT2_END_GROUP;
IADD3 R16, PT, PT, R22, R21, RZ ?trans1;
IMAD.WIDE.U32 R24, R14, UR4, R24 ?trans1;
LEA R34, P1, R20.reuse, R8, 0x2 ?trans1;
LDG.E R23, desc[UR14][R36.64] &wr=0x3 ?trans3;
LEA.HI.X R35, R20, R9, R16, 0x2, P1 ?trans1;
IMAD.WIDE.U32 R20, R18, R14, R2 ?trans1;
IADD3 R17, PT, PT, R22, R25, RZ ?trans2;
LEA R16, P1, R24, R8, 0x2 ?trans1;
IMAD R19, R18, R15, R21 ?trans1;
LDG.E R34, desc[UR14][R34.64] &wr=0x2 ?trans2;
LEA.HI.X R17, R24, R9, R17, 0x2, P1 ?WAIT2_END_GROUP;
LEA R18, P1, R20, R10, 0x2 ?WAIT3_END_GROUP;
LDG.E R16, desc[UR14][R16.64] &wr=0x4 ?trans1;
LEA.HI.X R19, R20, R11, R19, 0x2, P1 ?trans1;
IADD.64 R20, R4, 0x3 ?WAIT4_END_GROUP;
LDG.E R18, desc[UR14][R18.64] &wr=0x4 ?trans2;
MOV R32, R20 ?WAIT5_END_GROUP;
IMAD.WIDE.U32 R32, R14, UR4, R32 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R24, R20, R14, R2 ?trans1;
IADD3 R22, PT, PT, R22, R33, RZ ?trans2;
LEA R8, P1, R32, R8, 0x2 ?trans1;
IMAD R15, R20, R15, R25 ?WAIT3_END_GROUP;
LEA.HI.X R9, R32, R9, R22, 0x2, P1 ?trans2;
LEA R10, P1, R24, R10, 0x2 ?WAIT3_END_GROUP;
LDG.E R8, desc[UR14][R8.64] &wr=0x5 ?trans1;
LEA.HI.X R11, R24, R11, R15, 0x2, P1 ?WAIT5_END_GROUP;
LDG.E R10, desc[UR14][R10.64] &wr=0x5 ?trans1;
IADD.64 R4, R4, 0x4 ?trans2;
MOV R5, RZ ?trans1;
FFMA R23, R23, R12, R0 &req={3} ?WAIT4_END_GROUP;
FFMA R23, R34, R6, R23 &req={2} ?WAIT4_END_GROUP;
FFMA R23, R16, R18, R23 &req={4} ?WAIT4_END_GROUP;
FFMA R0, R8, R10, R23 &req={5} ?WAIT7_END_GROUP;
@!P0 BRA 0xd30 ?trans5;
LDC R7, c[0x0][0x398] &wr=0x1 ?trans1;
ISETP.NE.S64.AND P1, PT, R28, 0x1, PT ?WAIT3_END_GROUP;
LOP3.LUT P0, RZ, R7, 0x1, RZ, 0xc0, !PT &req={1} ?WAIT11_END_GROUP;
@!P1 BRA 0xbe0 ?trans5;
LDC.64 R22, c[0x0][0x398] &wr=0x1 ?trans1;
IADD.64 R20, R4, 0x1 ?trans2;
MOV R10, R2 ?trans1;
MOV R11, R3 ?trans1;
HFMA2 R13, -RZ, RZ, 0, 0 ?trans2;
MOV R12, R20 ?trans1;
LDC.64 R14, c[0x0][0x380] &wr=0x2 ?trans8;
LDC.64 R16, c[0x0][0x388] &wr=0x3 ?trans1;
IMAD R6, R22, UR5, RZ &req={1} ?WAIT2_END_GROUP;
IMAD R8, R5, R22, RZ ?trans2;
IMAD.WIDE.U32 R24, R22, UR4, R4 ?WAIT4_END_GROUP;
IMAD R21, R23, UR4, R6 ?trans2;
IMAD.WIDE.U32 R18, R4, R22, R10 ?WAIT3_END_GROUP;
IADD3 R6, PT, PT, R25, R21, RZ ?trans1;
IMAD R33, R4, R23, R8 ?trans1;
LEA R8, P1, R24, R14, 0x2 &req={2} ?trans1;
IMAD.WIDE.U32 R12, R22, UR4, R12 ?WAIT3_END_GROUP;
IADD3 R33, PT, PT, R19, R33, RZ ?trans1;
IMAD.WIDE.U32 R10, R20, R22, R10 ?trans1;
LEA R22, P2, R18, R16, 0x2 &req={3} ?trans2;
LEA.HI.X R9, R24, R15, R6, 0x2, P1 ?trans1;
IMAD R20, R20, R23, R11 ?trans1;
IADD3 R21, PT, PT, R21, R13, RZ ?trans2;
LEA R14, P1, R12, R14, 0x2 ?trans2;
LEA.HI.X R23, R18, R17, R33, 0x2, P2 ?trans1;
LDG.E R9, desc[UR14][R8.64] &wr=0x2 ?trans1;
LEA R16, P2, R10, R16, 0x2 ?WAIT2_END_GROUP;
LEA.HI.X R15, R12, R15, R21, 0x2, P1 ?trans1;
LDG.E R22, desc[UR14][R22.64] &wr=0x2 ?trans1;
LEA.HI.X R17, R10, R17, R20, 0x2, P2 ?WAIT4_END_GROUP;
LDG.E R15, desc[UR14][R14.64] &wr=0x3 ?trans4;
LDG.E R16, desc[UR14][R16.64] &wr=0x3 ?trans1;
IADD.64 R4, R4, 0x2 ?trans2;
MOV R5, RZ ?trans1;
FFMA R0, R9, R22, R0 &req={2} ?WAIT4_END_GROUP;
FFMA R0, R15, R16, R0 &req={3} ?WAIT7_END_GROUP;
@!P0 BRA 0xd30 ?trans5;
LDC R17, c[0x0][0x39c] &wr=0x1 ?trans1;
MOV R12, R4 ?trans1;
MOV R13, R5 ?trans1;
IMAD R14, R7, UR5, RZ ?trans2;
IMAD R15, R5, R7.reuse, RZ ?trans2;
IMAD.WIDE.U32 R12, R7, UR4, R12 ?trans1;
LDC.64 R10, c[0x0][0x380] &wr=0x2 ?trans3;
IMAD.WIDE.U32 R6, R4, R7, R2 ?WAIT5_END_GROUP;
LDC.64 R8, c[0x0][0x388] &wr=0x3 ?trans1;
IMAD R5, R17, UR4, R14 &req={1} ?trans2;
IMAD R15, R4, R17, R15 ?WAIT3_END_GROUP;
IADD3 R5, PT, PT, R5, R13, RZ ?trans2;
IADD3 R4, PT, PT, R7, R15, RZ ?trans2;
LEA R10, P0, R12, R10, 0x2 &req={2} ?WAIT4_END_GROUP;
LEA.HI.X R11, R12, R11, R5, 0x2, P0 ?trans2;
LEA R8, P1, R6, R8, 0x2 &req={3} ?WAIT4_END_GROUP;
LDG.E R11, desc[UR14][R10.64] &wr=0x2 ?trans1;
LEA.HI.X R9, R6, R9, R4, 0x2, P1 ?WAIT5_END_GROUP;
LDG.E R8, desc[UR14][R8.64] &wr=0x2 ?trans2;
FFMA R0, R11, R8, R0 &req={2} ?WAIT7_END_GROUP;
LDC.64 R10, c[0x0][0x398] &wr=0x1 ?trans8;
LDC.64 R8, c[0x0][0x390] &wr=0x2 ?trans1;
IMAD R6, R3, R10.reuse, RZ &req={1} ?trans2;
IMAD.WIDE.U32 R4, R2, R10, UR4 ?trans1;
UIADD3.64 UR4, UPT, UPT, UR4, 0x1, URZ ?WAIT3_END_GROUP;
IMAD R7, R2, R11, R6 ?trans1;
LEA R6, P0, R4, R8, 0x2 &req={2} ?WAIT4_END_GROUP;
IADD3 R5, PT, PT, R5, R7, RZ ?WAIT4_END_GROUP;
LEA.HI.X R7, R4, R9, R5, 0x2, P0 ?trans1;
ISETP.LE.U64.AND P0, PT, R30, UR4, PT ?WAIT4_END_GROUP;
STG.E desc[UR14][R6.64], R0 &rd=0x1 ?trans10;
@!P0 BRA 0x170 ?trans5;
EXIT ?trans5;
BRA 0xe00;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: gpu_basic_mm(float*, float*, float*, unsigned long)
_Z12gpu_basic_mmPfS_S_m:
s_load_b256 s[4:11], s[0:1], 0x0
s_mov_b64 s[2:3], 0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u64 s[10:11], 0
s_cbranch_scc1 .LBB0_5
s_load_b32 s0, s[0:1], 0x2c
v_mov_b32_e32 v6, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s0, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
s_lshl_b64 s[0:1], s[10:11], 2
v_ashrrev_i32_e32 v2, 31, v1
v_mul_lo_u32 v0, v1, s11
v_mad_u64_u32 v[3:4], null, v1, s10, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v2, s10
v_add3_u32 v4, v4, v0, v5
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[3:4]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s8, v2
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
.LBB0_2:
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
v_mov_b32_e32 v7, 0
s_mov_b64 s[6:7], 0
s_mov_b64 s[8:9], s[4:5]
.LBB0_3:
global_load_b32 v8, v6, s[8:9]
global_load_b32 v9, v[2:3], off
s_add_u32 s6, s6, 1
s_addc_u32 s7, s7, 0
v_add_co_u32 v2, vcc_lo, v2, s0
v_cmp_ge_u64_e64 s12, s[6:7], s[10:11]
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_add_u32 s8, s8, 4
s_addc_u32 s9, s9, 0
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 vcc_lo, exec_lo, s12
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v7, v8, v9
s_cbranch_vccz .LBB0_3
s_lshl_b64 s[6:7], s[2:3], 2
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
v_add_co_u32 v2, vcc_lo, v4, s6
v_cmp_ge_u64_e64 s8, s[2:3], s[10:11]
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v5, vcc_lo
s_add_u32 s4, s4, s0
s_addc_u32 s5, s5, s1
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 vcc_lo, exec_lo, s8
global_store_b32 v[2:3], v7, off
s_cbranch_vccz .LBB0_2
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| gpu_basic_mm | 5,667 | 1,161 | stackv2-00000-of-00015 |
// Demangled: gpu_better_mm(float*, float*, float*, unsigned long)
Function : _Z13gpu_better_mmPfS_S_m
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
LDC.64 R2, c[0x0][0x398] &wr=0x1 ?trans1;
S2R R7, SR_TID.X &wr=0x2 ?trans1;
LDCU.64 UR20, c[0x0][0x358] &wr=0x3 ?trans1;
HFMA2 R0, -RZ, RZ, 0, 0 ?WAIT5_END_GROUP;
S2UR UR4, SR_CTAID.Y &wr=0x2 ?trans8;
LDC R6, c[0x0][0x364] &wr=0x2 ?trans1;
ISETP.NE.S64.AND P0, PT, R2, RZ, PT &req={1} ?WAIT7_END_GROUP;
S2UR UR8, SR_CTAID.X &wr=0x1 ?trans1;
IMAD R6, R6, UR4, R7 &req={2} ?WAIT6_END_GROUP;
@!P0 BRA 0xc30 &req={3,0} ?trans5;
LDCU.64 UR22, c[0x0][0x398] &wr=0x0 ?trans1;
ISETP.GE.U64.AND P1, PT, R2, 0x8, PT ?trans2;
MOV R25, RZ ?trans1;
MOV.64 R8, RZ ?trans2;
MOV R0, RZ ?trans1;
ULOP3.LUT UR4, UR22, 0x7, URZ, 0xc0, !UPT &req={0} ?trans1;
UIMAD.WIDE.U32 UR6, UR8, UR22, URZ &req={1} ?WAIT4_END_GROUP;
UIMAD UR12, UR8, UR23, UR7 ?trans1;
MOV R24, UR4 ?WAIT5_END_GROUP;
ISETP.NE.S64.AND P0, PT, R24, RZ, PT ?trans2;
@!P1 BRA 0x4d0 ?WAIT12_END_GROUP;
LDCU.128 UR16, c[0x0][0x380] &wr=0x0 ?trans1;
MOV.64 R8, RZ ?trans2;
MOV R0, RZ ?trans1;
ULOP3.LUT UR11, UR22, 0xfffffff8, URZ, 0xc0, !UPT ?trans1;
USHF.L.U64.HI UR10, UR22, 0x5, UR23 ?trans1;
USHF.L.U32 UR9, UR22, 0x5, URZ ?trans1;
USHF.L.U64.HI UR15, UR22, 0x2, UR23 ?trans1;
USHF.L.U32 UR14, UR22, 0x2, URZ ?trans1;
ULEA UR4, UP0, UR6, UR16, 0x2 &req={0} ?trans1;
LEA R2, P1, R6, UR18, 0x2 ?WAIT3_END_GROUP;
ULEA.HI.X UR5, UR6, UR17, UR12, 0x2, UP0 ?trans1;
LEA.HI.X R3, R6, UR19, RZ, 0x2, P1 ?WAIT3_END_GROUP;
UIADD3.64 UR4, UPT, UPT, UR4, 0x10, URZ ?WAIT6_END_GROUP;
MOV.64 R4, UR4 ?WAIT8_END_GROUP;
IADD.64 R10, R2, UR14 ?trans2;
LDG.E R17, desc[UR20][R4.64+-0x10] &wr=0x2 ?trans2;
IADD.64 R12, R10, UR14 ?trans2;
LDG.E R15, desc[UR20][R2.64] &wr=0x2 ?trans2;
IADD.64 R28, R12, UR14 ?trans2;
LDG.E R21, desc[UR20][R10.64] &rd=0x0 &wr=0x3 ?trans4;
LDG.E R14, desc[UR20][R4.64+-0xc] &wr=0x3 ?trans1;
IADD.64 R30, R28, UR14 ?WAIT3_END_GROUP;
LDG.E R23, desc[UR20][R12.64] &rd=0x1 &wr=0x4 ?trans4;
LDG.E R20, desc[UR20][R4.64+-0x8] &wr=0x4 ?trans1;
IADD.64 R18, R30, UR14 ?WAIT3_END_GROUP;
LDG.E R29, desc[UR20][R28.64] &wr=0x5 ?trans4;
LDG.E R22, desc[UR20][R4.64+-0x4] &wr=0x5 ?trans1;
IADD.64 R10, R18, UR14 &req={0} ?WAIT3_END_GROUP;
LDG.E R30, desc[UR20][R30.64] &wr=0x5 ?trans4;
LDG.E R26, desc[UR20][R4.64] &wr=0x5 ?trans1;
IADD.64 R12, R10, UR14 &req={1} ?WAIT3_END_GROUP;
LDG.E R18, desc[UR20][R18.64] &wr=0x5 ?trans4;
LDG.E R27, desc[UR20][R4.64+0x4] &wr=0x5 ?trans4;
LDG.E R16, desc[UR20][R10.64] &rd=0x0 &wr=0x5 ?trans4;
LDG.E R32, desc[UR20][R4.64+0x8] &wr=0x5 ?trans4;
LDG.E R12, desc[UR20][R12.64] &wr=0x5 ?trans4;
LDG.E R33, desc[UR20][R4.64+0xc] &rd=0x1 &wr=0x5 ?trans1;
IADD.64 R8, R8, 0x8 ?WAIT2_END_GROUP;
UMOV UR4, UR11 ?trans1;
UMOV UR5, UR23 ?trans2;
IADD.64 R10, R8, -UR4 &req={0} ?trans2;
UMOV UR4, UR9 ?trans1;
UMOV UR5, UR10 ?trans1;
IADD.64 R4, R4, 0x20 &req={1} ?trans2;
ISETP.NE.S64.AND P1, PT, R10, RZ, PT ?trans2;
IADD.64 R2, R2, UR4 ?WAIT2_END_GROUP;
FFMA R15, R17, R15, R0 &req={2} ?WAIT4_END_GROUP;
FFMA R15, R14, R21, R15 &req={3} ?WAIT4_END_GROUP;
FFMA R15, R20, R23, R15 &req={4} ?WAIT4_END_GROUP;
FFMA R15, R22, R29, R15 &req={5} ?WAIT4_END_GROUP;
FFMA R26, R26, R30, R15 ?WAIT4_END_GROUP;
FFMA R27, R27, R18, R26 ?WAIT4_END_GROUP;
FFMA R16, R32, R16, R27 ?WAIT4_END_GROUP;
FFMA R0, R33, R12, R16 ?trans1;
@P1 BRA 0x240 ?trans6;
UMOV UR4, UR6 ?trans1;
UMOV UR5, UR12 ?trans1;
@!P0 BRA 0xc30 ?trans5;
ISETP.GE.U64.AND P1, PT, R24, 0x4, PT ?trans2;
ULOP3.LUT UR6, UR22, 0x3, URZ, 0xc0, !UPT ?trans1;
HFMA2 R11, -RZ, RZ, 0, 0 ?WAIT5_END_GROUP;
MOV R10, UR6 ?WAIT5_END_GROUP;
ISETP.NE.S64.AND P0, PT, R10, RZ, PT ?trans2;
@!P1 BRA 0x8b0 ?WAIT12_END_GROUP;
LDC.64 R12, c[0x0][0x380] &wr=0x0 ?trans1;
IADD.64 R34, R8.reuse, 0x1 ?trans2;
IADD.64 R2, R8.reuse, UR4 ?trans2;
IADD.64 R32, R8.reuse, 0x2 ?trans2;
MOV R7, RZ ?trans1;
LDC.64 R18, c[0x0][0x388] &wr=0x1 ?trans1;
IADD.64 R30, R8, 0x3 ?trans2;
MOV R35, RZ ?trans1;
IMAD.WIDE.U32 R20, R34, UR22, R6 ?trans1;
MOV R33, RZ ?trans1;
MOV R31, RZ ?WAIT2_END_GROUP;
IMAD.WIDE.U32 R24, R32, UR22, R6 ?WAIT4_END_GROUP;
IMAD R4, R34.reuse, UR23, R21 ?trans1;
IADD.64 R34, R34, UR4 ?trans2;
IMAD.WIDE.U32 R22, R30, UR22, R6 ?trans1;
LEA R28, P1, R2, R12, 0x2 &req={0} ?WAIT3_END_GROUP;
IMAD R5, R9, UR22, RZ ?trans1;
LEA.HI.X R29, R2, R13.reuse, R3, 0x2, P1 ?trans1;
IMAD R3, R32.reuse, UR23, R25 ?trans1;
IADD.64 R32, R32, UR4 ?trans2;
IMAD R2, R30.reuse, UR23, R23 ?trans1;
IADD.64 R30, R30, UR4 ?trans2;
IMAD R5, R8, UR23, R5 ?trans1;
LEA R16, P1, R34, R12.reuse, 0x2 ?trans1;
IMAD.WIDE.U32 R26, R8, UR22, R6 ?trans1;
LEA R14, P2, R32, R12, 0x2 ?trans1;
LDG.E R29, desc[UR20][R28.64] &wr=0x2 ?trans1;
LEA.HI.X R17, R34, R13, R35, 0x2, P1 ?WAIT2_END_GROUP;
LEA R12, P1, R30, R12, 0x2 ?trans2;
LEA.HI.X R15, R32, R13, R33, 0x2, P2 ?trans1;
LDG.E R16, desc[UR20][R16.64] &wr=0x3 ?trans1;
IADD3 R5, PT, PT, R27, R5, RZ ?trans2;
LEA R32, P2, R26, R18, 0x2 &req={1} ?trans2;
LEA.HI.X R13, R30, R13, R31, 0x2, P1 ?trans1;
LDG.E R15, desc[UR20][R14.64] &wr=0x4 ?trans1;
LEA.HI.X R33, R26, R19, R5, 0x2, P2 ?WAIT2_END_GROUP;
LEA R30, P1, R20, R18.reuse, 0x2 ?trans2;
LEA R26, P2, R24, R18.reuse, 0x2 ?trans1;
LDG.E R32, desc[UR20][R32.64] &wr=0x2 ?trans1;
LEA.HI.X R31, R20, R19.reuse, R4, 0x2, P1 ?trans2;
LEA.HI.X R27, R24, R19, R3, 0x2, P2 ?trans1;
LDG.E R13, desc[UR20][R12.64] &wr=0x5 ?trans1;
LEA R18, P1, R22, R18, 0x2 ?WAIT3_END_GROUP;
LDG.E R30, desc[UR20][R30.64] &wr=0x3 ?trans1;
LEA.HI.X R19, R22, R19, R2, 0x2, P1 ?WAIT3_END_GROUP;
LDG.E R26, desc[UR20][R26.64] &wr=0x4 ?trans4;
LDG.E R18, desc[UR20][R18.64] &wr=0x5 ?trans1;
IADD.64 R8, R8, 0x4 ?trans2;
MOV R9, RZ ?trans1;
FFMA R29, R29, R32, R0 &req={2} ?WAIT4_END_GROUP;
FFMA R16, R16, R30, R29 &req={3} ?WAIT4_END_GROUP;
FFMA R16, R15, R26, R16 &req={4} ?WAIT4_END_GROUP;
FFMA R0, R13, R18, R16 &req={5} ?WAIT7_END_GROUP;
@!P0 BRA 0xc30 ?trans5;
ISETP.NE.S64.AND P1, PT, R10, 0x1, PT ?trans2;
ULOP3.LUT UR6, UR22, 0x1, URZ, 0xc0, !UPT ?trans1;
MOV R3, RZ ?WAIT5_END_GROUP;
MOV R2, UR6 ?WAIT5_END_GROUP;
ISETP.NE.U64.AND P0, PT, R2, 0x1, PT ?trans2;
@!P1 BRA 0xb00 ?WAIT12_END_GROUP;
LDC.64 R4, c[0x0][0x380] &wr=0x0 ?trans1;
MOV R14, R6 ?trans1;
HFMA2 R15, -RZ, RZ, 0, 0 ?trans2;
IMAD R11, R9.reuse, UR22, RZ ?trans1;
IADD.64 R18, R8.reuse, 0x1 ?trans2;
IADD.64 R12, R8, UR4 ?trans2;
LDC.64 R2, c[0x0][0x388] &wr=0x1 ?trans1;
IMAD R11, R8.reuse, UR23, R11 ?trans1;
MOV R19, RZ ?trans1;
IMAD.WIDE.U32 R16, R8, UR22, R14 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R22, R18.reuse, UR22, R14 ?trans1;
IADD.64 R20, R18, UR4 ?WAIT3_END_GROUP;
IADD3 R15, PT, PT, R17, R11, RZ ?trans1;
IMAD R18, R18, UR23, R23 ?trans1;
LEA R10, P2, R12, R4, 0x2 &req={0} ?WAIT4_END_GROUP;
LEA.HI.X R11, R12, R5.reuse, R13, 0x2, P2 ?trans2;
LEA R4, P2, R20, R4, 0x2 ?trans2;
LEA R14, P1, R16, R2.reuse, 0x2 &req={1} ?trans2;
LEA.HI.X R5, R20, R5, R21, 0x2, P2 ?trans1;
LDG.E R11, desc[UR20][R10.64] &wr=0x2 ?trans1;
LEA.HI.X R15, R16, R3, R15, 0x2, P1 ?trans2;
LEA R2, P1, R22, R2, 0x2 ?WAIT2_END_GROUP;
LDG.E R5, desc[UR20][R4.64] &wr=0x3 ?trans2;
LEA.HI.X R3, R22, R3, R18, 0x2, P1 ?trans2;
LDG.E R14, desc[UR20][R14.64] &wr=0x2 ?trans4;
LDG.E R2, desc[UR20][R2.64] &wr=0x3 ?trans1;
IADD.64 R8, R8, 0x2 ?trans2;
HFMA2 R9, -RZ, RZ, 0, 0 ?WAIT2_END_GROUP;
FFMA R0, R11, R14, R0 &req={2} ?WAIT4_END_GROUP;
FFMA R0, R5, R2, R0 &req={3} ?WAIT7_END_GROUP;
@P0 BRA 0xc30 ?trans5;
LDC.64 R12, c[0x0][0x380] &wr=0x0 ?trans1;
IMAD R3, R9, UR22, RZ ?trans1;
MOV R10, R6 ?trans1;
HFMA2 R11, -RZ, RZ, 0, 0 ?trans1;
MOV R2, R8 ?trans1;
IMAD R5, R8.reuse, UR23, R3 ?trans1;
MOV R3, R9 ?trans2;
LDC.64 R14, c[0x0][0x388] &wr=0x1 ?trans1;
IMAD.WIDE.U32 R10, R8, UR22, R10 ?trans2;
IADD.64 R2, R2, UR4 ?WAIT3_END_GROUP;
IADD3 R9, PT, PT, R11, R5, RZ ?trans2;
LEA R4, P0, R2, R12, 0x2 &req={0} ?WAIT4_END_GROUP;
LEA.HI.X R5, R2, R13, R3, 0x2, P0 ?trans2;
LEA R8, P1, R10, R14, 0x2 &req={1} ?WAIT4_END_GROUP;
LDG.E R5, desc[UR20][R4.64] &wr=0x2 ?trans1;
LEA.HI.X R9, R10, R15, R9, 0x2, P1 ?WAIT5_END_GROUP;
LDG.E R8, desc[UR20][R8.64] &wr=0x2 ?trans2;
FFMA R0, R5, R8, R0 &req={2} ?WAIT7_END_GROUP;
LDC.64 R8, c[0x0][0x398] &wr=0x0 ?trans1;
UMOV UR4, UR8 &req={1} ?trans1;
UMOV UR5, URZ ?WAIT6_END_GROUP;
LDC.64 R4, c[0x0][0x390] &wr=0x1 ?trans1;
IMAD.WIDE.U32 R2, R6, R8, UR4 &req={0} ?WAIT4_END_GROUP;
IMAD R6, R6, R9, R3 ?trans1;
LEA R4, P0, R2, R4, 0x2 &req={1} ?WAIT4_END_GROUP;
LEA.HI.X R5, R2, R5, R6, 0x2, P0 ?WAIT5_END_GROUP;
STG.E desc[UR20][R4.64], R0 ?trans1;
EXIT ?trans5;
BRA 0xcd0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: gpu_better_mm(float*, float*, float*, unsigned long)
_Z13gpu_better_mmPfS_S_m:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x2c
s_load_b256 s[0:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s8, s8, 16
s_cmp_lg_u64 s[6:7], 0
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_mov_b64 s[8:9], 0
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
s_cbranch_scc0 .LBB1_4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_mul_i32 s10, s14, s7
s_mul_hi_u32 s11, s14, s6
s_ashr_i32 s15, s14, 31
s_add_i32 s10, s11, s10
s_mul_i32 s11, s15, s6
v_add_co_u32 v3, vcc_lo, s2, v3
s_add_i32 s11, s10, s11
s_mul_i32 s10, s14, s6
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_lshl_b64 s[10:11], s[10:11], 2
v_mov_b32_e32 v0, 0
s_add_u32 s0, s0, s10
s_addc_u32 s1, s1, s11
s_lshl_b64 s[2:3], s[6:7], 2
.LBB1_2:
global_load_b32 v5, v[3:4], off
s_load_b32 s10, s[0:1], 0x0
s_add_u32 s8, s8, 1
s_addc_u32 s9, s9, 0
v_add_co_u32 v3, vcc_lo, v3, s2
v_cmp_ge_u64_e64 s11, s[8:9], s[6:7]
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 vcc_lo, exec_lo, s11
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v0, s10, v5
s_cbranch_vccz .LBB1_2
s_mov_b32 s0, 0
s_branch .LBB1_5
.LBB1_4:
s_mov_b32 s0, -1
.LBB1_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB1_7
v_mov_b32_e32 v0, 0
s_ashr_i32 s15, s14, 31
.LBB1_7:
v_mul_lo_u32 v4, v2, s6
v_mul_lo_u32 v5, v1, s7
v_mad_u64_u32 v[2:3], null, v1, s6, 0
s_lshl_b64 s[0:1], s[14:15], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_add_u32 s0, s0, s4
s_addc_u32 s1, s1, s5
v_add3_u32 v3, v3, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[2:3]
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| gpu_better_mm | 5,055 | 1,187 | stackv2-00000-of-00015 |
// Demangled: gpu_optimized_mm(float*, float*, float*, int)
Function : _Z16gpu_optimized_mmPfS_S_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
LDC R7, c[0x0][0x360] &wr=0x1 ?trans1;
LDCU.64 UR8, c[0x0][0x358] &wr=0x2 ?trans1;
HFMA2 R27, -RZ, RZ, 0, 0 ?WAIT6_END_GROUP;
LDC R6, c[0x0][0x398] &wr=0x3 ?trans8;
S2UR UR4, SR_CTAID.Y &wr=0x4 ?trans1;
IABS R5, R7 &req={1} ?WAIT7_END_GROUP;
S2UR UR5, SR_CTAID.X &wr=0x1 ?trans1;
IABS R8, R7.reuse ?trans1;
IMAD R23, R7, R7, RZ ?trans1;
I2F.RP R0, R5 &wr=0x5 ?trans2;
IADD3 R8, PT, PT, RZ, -R8, RZ ?trans1;
IMAD R26, R23, UR4, RZ &req={4} ?trans1;
MUFU.RCP R0, R0 &req={5} &wr=0x4 ?trans1;
IMAD R21, R7, UR5, RZ &req={1} ?trans1;
IADD3 R2, PT, PT, R0, 0xffffffe, RZ &req={4} ?trans2;
IABS R0, R6 &req={3} ?WAIT2_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R3, R2 &rd=0x1 &wr=0x3 ?trans2;
HFMA2 R2, -RZ, RZ, 0, 0 &req={1} ?trans1;
IADD3 R4, PT, PT, RZ, -R3, RZ &req={3} ?WAIT5_END_GROUP;
IMAD R9, R4, R5, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R3, R3, R9, R2 ?trans1;
MOV R9, R8 ?WAIT5_END_GROUP;
IMAD.HI.U32 R4, R3, R0, RZ ?WAIT4_END_GROUP;
IMAD R0, R4, R9, R0 ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P1, PT, R5, R0, PT ?WAIT13_END_GROUP;
@!P1 IADD3 R0, PT, PT, R0, -R5, RZ ?trans2;
@!P1 IADD3 R4, PT, PT, R4, 0x1, RZ ?WAIT3_END_GROUP;
ISETP.GE.U32.AND P0, PT, R0, R5, PT ?trans1;
LOP3.LUT R0, R7.reuse, R6, RZ, 0x3c, !PT ?trans1;
S2R R5, SR_TID.X &wr=0x1 ?trans4;
ISETP.GE.AND P1, PT, R0, RZ, PT ?trans1;
S2R R6, SR_TID.Y &wr=0x3 ?trans6;
@P0 IADD3 R4, PT, PT, R4, 0x1, RZ ?trans1;
ISETP.NE.AND P0, PT, R7, RZ, PT ?WAIT5_END_GROUP;
@!P1 IADD3 R4, PT, PT, -R4, RZ, RZ ?WAIT8_END_GROUP;
@!P0 LOP3.LUT R4, RZ, R7, RZ, 0x33, !PT ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R4, 0x1, PT ?WAIT13_END_GROUP;
@!P0 BRA 0xb40 &req={3,2,1,0} ?trans5;
S2UR UR6, SR_CgaCtaId &wr=0x0 ?trans1;
UMOV UR4, 0x400 ?trans1;
IMAD R20, R7.reuse, R6, R5 ?trans1;
UIADD3 UR5, UPT, UPT, UR4, 0x1000, URZ ?trans1;
LOP3.LUT R17, R7.reuse, 0xf, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R16, R7.reuse, 0x7, RZ, 0xc0, !PT ?trans2;
IADD3 R24, PT, PT, R26, R20.reuse, RZ ?trans2;
LOP3.LUT R3, R7, 0x3, RZ, 0xc0, !PT ?trans1;
MOV R27, RZ ?trans1;
IADD3 R20, PT, PT, R21, R20, RZ ?trans1;
ULEA UR4, UR6, UR4, 0x18 &req={0} ?trans1;
ULEA UR5, UR6, UR5, 0x18 ?WAIT5_END_GROUP;
LEA R22, R6, UR4, 0x7 ?trans1;
UMOV UR4, URZ ?trans1;
LEA R19, R5, UR5, 0x2 ?trans2;
IADD3 R2, PT, PT, R22, 0x20, RZ ?WAIT3_END_GROUP;
IMAD R18, R6, 0x80, R19 ?trans1;
IADD3 R0, PT, PT, R19, 0x400, RZ ?WAIT7_END_GROUP;
LDC.64 R10, c[0x0][0x380] &req={0} &wr=0x0 ?trans1;
IMAD R13, R7, UR4, R24 ?trans2;
IMAD R15, R23, UR4, R20 ?WAIT5_END_GROUP;
LDC.64 R8, c[0x0][0x388] &wr=0x1 ?trans1;
IMAD.WIDE.U32 R10, R13, 0x4, R10 &req={0} ?WAIT6_END_GROUP;
LDG.E R10, desc[UR8][R10.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R8, R15, 0x4, R8 &req={1} ?WAIT6_END_GROUP;
LDG.E R9, desc[UR8][R8.64] &wr=0x3 ?trans1;
ISETP.GE.U32.AND P2, PT, R7, 0x10, PT ?trans1;
IMAD R13, R5, 0x4, R22 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x1, URZ ?trans1;
ISETP.NE.AND P0, PT, R17, RZ, PT ?trans1;
MOV R25, RZ ?WAIT4_END_GROUP;
ISETP.NE.AND P1, PT, R4, UR4, PT ?trans1;
STS [R13], R10 &req={2} &rd=0x0 ?trans4;
STS [R18], R9 &req={3} &rd=0x0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P2 BRA 0x7a0 ?trans5;
LOP3.LUT R30, R7, 0xfffffff0, RZ, 0xc0, !PT ?trans1;
HFMA2 R25, -RZ, RZ, 0, 0 ?trans1;
MOV R29, R0 ?trans1;
MOV R28, R2 ?trans1;
IADD3 R30, PT, PT, -R30, RZ, RZ ?WAIT7_END_GROUP;
LDS R8, [R29+-0x400] ?trans1;
IADD3 R30, PT, PT, R30, 0x10, RZ ?trans2;
IADD3 R25, PT, PT, R25, 0x10, RZ ?trans1;
LDS.128 R12, [R28+-0x20] &req={0} &wr=0x0 ?trans2;
ISETP.NE.AND P2, PT, R30, RZ, PT ?trans2;
LDS R33, [R29+-0x380] &wr=0x1 ?trans4;
LDS R31, [R29+-0x300] &wr=0x2 ?trans4;
LDS R34, [R29+-0x280] &wr=0x3 ?trans4;
LDS R32, [R29+-0x180] ?trans1;
FFMA R12, R12, R8, R27 &req={0} ?WAIT3_END_GROUP;
LDS R27, [R29+-0x200] ?trans1;
FFMA R12, R33, R13, R12 &req={1} ?WAIT3_END_GROUP;
LDS.128 R8, [R28+-0x10] &wr=0x0 ?trans1;
FFMA R13, R31, R14, R12 &req={2} ?WAIT3_END_GROUP;
LDS R31, [R29+-0x100] &wr=0x1 ?trans1;
FFMA R13, R34, R15, R13 &req={3} ?WAIT3_END_GROUP;
LDS R34, [R29+-0x80] &wr=0x2 ?trans1;
FFMA R33, R8, R27, R13 &req={0} ?WAIT3_END_GROUP;
LDS R27, [R29] ?trans1;
FFMA R32, R32, R9, R33 ?WAIT3_END_GROUP;
LDS.128 R12, [R28] &wr=0x0 ?trans1;
FFMA R31, R31, R10, R32 &req={1} ?WAIT3_END_GROUP;
LDS R8, [R29+0x80] &wr=0x1 ?trans1;
FFMA R11, R34, R11, R31 &req={2} ?WAIT3_END_GROUP;
LDS R31, [R29+0x100] &wr=0x2 ?trans4;
LDS R33, [R29+0x280] ?trans4;
LDS R32, [R29+0x380] ?trans1;
FFMA R11, R12, R27, R11 &req={0} ?WAIT3_END_GROUP;
LDS R12, [R29+0x180] &wr=0x0 ?trans1;
FFMA R34, R8, R13, R11 &req={1} ?WAIT3_END_GROUP;
LDS R27, [R29+0x200] ?trans1;
FFMA R31, R31, R14, R34 &req={2} ?WAIT3_END_GROUP;
LDS.128 R8, [R28+0x10] &rd=0x1 &wr=0x2 ?trans4;
LDS R13, [R29+0x300] &rd=0x3 &wr=0x4 ?trans1;
IADD3 R28, PT, PT, R28, 0x40, RZ &req={1} ?trans2;
IADD3 R29, PT, PT, R29, 0x800, RZ &req={3} ?trans1;
FFMA R15, R12, R15, R31 &req={0} ?WAIT4_END_GROUP;
FFMA R8, R8, R27, R15 &req={2} ?WAIT4_END_GROUP;
FFMA R8, R33, R9, R8 ?WAIT4_END_GROUP;
FFMA R13, R13, R10, R8 &req={4} ?WAIT4_END_GROUP;
FFMA R27, R32, R11, R13 ?trans1;
@P2 BRA 0x500 ?trans6;
@!P0 BRA 0xb20 ?trans5;
IADD3 R8, PT, PT, R17, -0x1, RZ ?trans1;
ISETP.NE.AND P2, PT, R16, RZ, PT ?WAIT4_END_GROUP;
ISETP.GE.U32.AND P0, PT, R8, 0x7, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x940 ?trans5;
IMAD R34, R25.reuse, 0x80, R19 ?trans2;
IMAD R33, R25.reuse, 0x4, R22 ?trans1;
IADD3 R25, PT, PT, R25, 0x8, RZ ?trans2;
LDS R32, [R34] ?trans4;
LDS.128 R8, [R33] &req={0} &wr=0x0 ?trans4;
LDS R30, [R34+0x80] &wr=0x1 ?trans4;
LDS R31, [R34+0x100] &wr=0x2 ?trans4;
LDS R28, [R34+0x180] &wr=0x3 ?trans4;
LDS R29, [R34+0x200] ?trans4;
LDS.128 R12, [R33+0x10] &wr=0x4 ?trans1;
FFMA R35, R8, R32, R27 &req={0} ?WAIT3_END_GROUP;
LDS R8, [R34+0x280] &wr=0x0 ?trans1;
FFMA R30, R30, R9, R35 &req={1} ?WAIT3_END_GROUP;
LDS R27, [R34+0x300] &wr=0x1 ?trans1;
FFMA R31, R31, R10, R30 &req={2} ?WAIT3_END_GROUP;
LDS R32, [R34+0x380] &wr=0x2 ?trans1;
FFMA R11, R28, R11, R31 &req={3} ?WAIT4_END_GROUP;
FFMA R11, R12, R29, R11 &req={4} ?WAIT4_END_GROUP;
FFMA R8, R8, R13, R11 &req={0} ?WAIT4_END_GROUP;
FFMA R27, R27, R14, R8 &req={1} ?WAIT4_END_GROUP;
FFMA R27, R32, R15, R27 &req={2} ?WAIT7_END_GROUP;
@!P2 BRA 0xb20 ?trans5;
IADD3 R8, PT, PT, R16, -0x1, RZ ?trans1;
ISETP.NE.AND P2, PT, R3, RZ, PT ?WAIT4_END_GROUP;
ISETP.GE.U32.AND P0, PT, R8, 0x3, PT ?WAIT13_END_GROUP;
@!P0 BRA 0xa50 ?trans5;
IMAD R8, R25.reuse, 0x4, R22 ?trans2;
IMAD R12, R25.reuse, 0x80, R19 ?trans1;
IADD3 R25, PT, PT, R25, 0x4, RZ ?WAIT3_END_GROUP;
LDS.128 R8, [R8] &req={0} ?trans4;
LDS R13, [R12] &wr=0x0 ?trans4;
LDS R15, [R12+0x80] &wr=0x1 ?trans4;
LDS R28, [R12+0x100] &wr=0x2 ?trans4;
LDS R29, [R12+0x180] &wr=0x3 ?trans1;
FFMA R14, R8, R13, R27 &req={0} ?WAIT4_END_GROUP;
FFMA R9, R15, R9, R14 &req={1} ?WAIT4_END_GROUP;
FFMA R10, R28, R10, R9 &req={2} ?WAIT4_END_GROUP;
FFMA R27, R29, R11, R10 &req={3} ?WAIT7_END_GROUP;
@!P2 BRA 0xb20 ?trans5;
IMAD R8, R25, 0x4, R22 ?trans1;
ISETP.NE.AND P0, PT, R3, 0x1, PT ?trans1;
IMAD R25, R25, 0x80, R19 ?WAIT4_END_GROUP;
LDS.128 R8, [R8] &req={0} ?trans4;
LDS R12, [R25] &wr=0x0 ?trans2;
FFMA R27, R8, R12, R27 &req={0} ?trans2;
@!P0 BRA 0xb20 ?trans5;
ISETP.NE.AND P0, PT, R3, 0x2, PT ?trans1;
LDS R8, [R25+0x80] &wr=0x0 ?WAIT12_END_GROUP;
@P0 LDS R12, [R25+0x100] &wr=0x1 ?trans1;
FFMA R27, R8, R9, R27 &req={0} ?WAIT4_END_GROUP;
@P0 FFMA R27, R12, R10, R27 &req={1} ?WAIT7_END_GROUP;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P1 BRA 0x390 ?trans5;
LDC.64 R2, c[0x0][0x390] &wr=0x1 ?trans1;
IMAD R5, R7, R6, R5 ?WAIT5_END_GROUP;
IADD3 R21, PT, PT, R26, R5, R21 ?WAIT5_END_GROUP;
IMAD.WIDE.U32 R2, R21, 0x4, R2 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR8][R2.64], R27 ?trans1;
EXIT ?trans5;
BRA 0xba0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: gpu_optimized_mm(float*, float*, float*, int)
_Z16gpu_optimized_mmPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_ashr_i32 s9, s3, 31
v_cvt_f32_u32_e32 v1, s2
v_mad_u32_u24 v0, v2, s2, v3
s_sub_i32 s5, 0, s2
s_add_i32 s3, s3, s9
s_mul_i32 s14, s14, s2
v_rcp_iflag_f32_e32 v1, v1
s_xor_b32 s3, s3, s9
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v1, 0x4f7ffffe, v1 :: v_dual_lshlrev_b32 v0, 2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s4, v1
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s5, s5, s4
s_mul_hi_u32 s5, s4, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s4, s4, s5
s_mul_hi_u32 s8, s3, s4
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_mul_i32 s10, s8, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s3, s3, s10
s_add_i32 s10, s8, 1
s_sub_i32 s11, s3, s2
s_cmp_ge_u32 s3, s2
s_cselect_b32 s8, s10, s8
s_cselect_b32 s3, s11, s3
s_add_i32 s10, s8, 1
s_cmp_ge_u32 s3, s2
s_cselect_b32 s3, s10, s8
s_mul_i32 s8, s2, s2
s_xor_b32 s10, s3, s9
s_mul_i32 s3, s8, s15
s_sub_i32 s9, s10, s9
s_mov_b32 s10, 0
s_cmp_lt_i32 s9, 1
s_cbranch_scc1 .LBB2_5
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v6, 2, v3
v_lshlrev_b32_e32 v2, 7, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, s4, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v4, null, s5, 0, s4
v_add_nc_u32_e32 v5, v2, v6
v_or_b32_e32 v6, 0x1000, v6
v_add_co_u32 v7, s4, s6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v8, null, s7, 0, s4
v_add_nc_u32_e32 v9, v6, v2
s_max_u32 s4, s2, 1
.LBB2_2:
s_mul_i32 s5, s10, s2
s_mul_i32 s7, s10, s8
s_add_i32 s6, s5, s3
s_add_i32 s12, s7, s14
s_ashr_i32 s7, s6, 31
s_ashr_i32 s13, s12, 31
s_lshl_b64 s[6:7], s[6:7], 2
s_mov_b32 s5, s4
v_add_co_u32 v10, vcc_lo, v3, s6
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v4, vcc_lo
s_lshl_b64 s[6:7], s[12:13], 2
s_delay_alu instid0(SALU_CYCLE_1)
v_add_co_u32 v12, vcc_lo, v7, s6
v_add_co_ci_u32_e32 v13, vcc_lo, s7, v8, vcc_lo
global_load_b32 v14, v[10:11], off
global_load_b32 v12, v[12:13], off
v_mov_b32_e32 v10, v6
v_mov_b32_e32 v11, v2
s_waitcnt vmcnt(1)
ds_store_b32 v5, v14
s_waitcnt vmcnt(0)
ds_store_b32 v9, v12
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB2_3:
ds_load_b32 v12, v11
ds_load_b32 v13, v10
v_add_nc_u32_e32 v11, 4, v11
v_add_nc_u32_e32 v10, 0x80, v10
s_add_i32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s5, 0
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v1, v12, v13
s_cbranch_scc0 .LBB2_3
s_add_i32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s10, s9
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB2_2
.LBB2_5:
s_add_i32 s2, s3, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s3, s2, 31
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| gpu_optimized_mm | 4,608 | 1,886 | stackv2-00000-of-00015 |
// Demangled: transpose(int*, int*)
Function : _Z9transposePiS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R7, SR_TID.X &wr=0x0 ?trans7;
S2UR UR6, SR_CTAID.X &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC R0, c[0x0][0x360] &wr=0x0 ?trans8;
LDC.64 R2, c[0x0][0x380] &wr=0x2 ?trans1;
IMAD R5, R0, UR6, R7 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R2, R5, 0x4, R2 &req={2} ?WAIT3_END_GROUP;
LDC R0, c[0x0][0x370] &wr=0x0 ?trans3;
LDG.E R3, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans5;
LDC.64 R4, c[0x0][0x388] &wr=0x1 ?trans1;
IMAD R7, R7, R0, UR6 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x4, R4 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64], R3 &req={2} ?trans1;
EXIT ?trans5;
BRA 0xf0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: transpose(int*, int*)
_Z9transposePiS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_load_b32 s0, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v3, v[1:2], off
v_mad_u64_u32 v[1:2], null, s0, v0, s[2:3]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| transpose | 434 | 563 | stackv2-00000-of-00015 |
// Demangled: voxel2col_grad_gpu_kernel(int, int, int, int, float const*, int const*, float const*, float*)
Function : _Z25voxel2col_grad_gpu_kerneliiiiPKfPKiS0_Pf
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R5, SR_TID.X &wr=0x1 ?trans7;
S2UR UR7, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x380] &wr=0x2 ?trans1;
LDCU UR6, c[0x0][0x388] &wr=0x3 ?trans6;
LDC R0, c[0x0][0x360] &wr=0x1 ?trans1;
UIMAD UR4, UR5, UR4, URZ &req={2} ?WAIT4_END_GROUP;
UIMAD UR4, UR4, UR6, URZ &req={3} ?trans1;
IMAD R5, R0, UR7, R5 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R5, UR4, PT ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x398] &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x1 ?trans7;
LDC R4, c[0x0][0x38c] &wr=0x2 ?trans1;
IMAD.WIDE R2, R5, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E R3, desc[UR6][R2.64] &req={1} &wr=0x3 ?trans1;
ISETP.GE.AND P0, PT, R4, 0x1, PT &req={2} ?WAIT5_END_GROUP;
ISETP.LT.OR P0, PT, R3, RZ, !P0 &req={3} ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
ISETP.GE.U32.AND P1, PT, R4.reuse, 0x10, PT ?trans1;
UMOV UR4, URZ ?trans1;
LOP3.LUT P0, R10, R4, 0xf, RZ, 0xc0, !PT ?trans1;
IMAD R2, R3, R4.reuse, RZ ?trans2;
IMAD R0, R5, R4, RZ ?WAIT8_END_GROUP;
@!P1 BRA 0x480 ?trans5;
LDC.64 R6, c[0x0][0x3a8] &wr=0x0 ?trans1;
LOP3.LUT R5, R4, 0x7ffffff0, RZ, 0xc0, !PT ?trans1;
UMOV UR4, URZ ?trans1;
MOV R11, R0 ?trans2;
IADD3 R5, PT, PT, -R5, RZ, RZ ?trans1;
IMAD.WIDE.U32 R6, R2, 0x4, R6 &req={0} ?WAIT5_END_GROUP;
IADD.64 R6, R6, 0x20 ?WAIT8_END_GROUP;
LDC.64 R8, c[0x0][0x3a0] &wr=0x0 ?trans2;
IMAD.WIDE R8, R11, 0x4, R8 &req={0} ?WAIT5_END_GROUP;
LDG.E R13, desc[UR6][R8.64] &wr=0x2 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R6.64+-0x20], R13 &req={2} &rd=0x0 ?trans4;
LDG.E R15, desc[UR6][R8.64+0x4] &wr=0x2 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R6.64+-0x1c], R15 &req={2} &rd=0x1 ?trans4;
LDG.E R17, desc[UR6][R8.64+0x8] &wr=0x2 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R6.64+-0x18], R17 &req={2} &rd=0x2 ?trans4;
LDG.E R19, desc[UR6][R8.64+0xc] &wr=0x3 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R6.64+-0x14], R19 &req={3} &rd=0x3 ?trans4;
LDG.E R21, desc[UR6][R8.64+0x10] &wr=0x4 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R6.64+-0x10], R21 &req={4} &rd=0x4 ?trans4;
LDG.E R23, desc[UR6][R8.64+0x14] &wr=0x5 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R6.64+-0xc], R23 &req={5} &rd=0x5 ?trans4;
LDG.E R13, desc[UR6][R8.64+0x18] &req={0} &wr=0x2 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R6.64+-0x8], R13 &req={2} &rd=0x0 ?trans4;
LDG.E R15, desc[UR6][R8.64+0x1c] &req={1} &wr=0x2 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R6.64+-0x4], R15 &req={2} &rd=0x1 ?trans4;
LDG.E R17, desc[UR6][R8.64+0x20] &wr=0x2 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R6.64], R17 &req={2} &rd=0x2 ?trans4;
LDG.E R19, desc[UR6][R8.64+0x24] &req={3} &wr=0x3 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R6.64+0x4], R19 &req={3} &rd=0x3 ?trans4;
LDG.E R21, desc[UR6][R8.64+0x28] &req={4} &wr=0x4 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R6.64+0x8], R21 &req={4} ?trans4;
LDG.E R23, desc[UR6][R8.64+0x2c] &req={5} &wr=0x4 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R6.64+0xc], R23 &req={4} ?trans4;
LDG.E R13, desc[UR6][R8.64+0x30] &req={0} &wr=0x4 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R6.64+0x10], R13 &req={4} ?trans4;
LDG.E R15, desc[UR6][R8.64+0x34] &req={1} &wr=0x4 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R6.64+0x14], R15 &req={4} ?trans4;
LDG.E R17, desc[UR6][R8.64+0x38] &req={2} &wr=0x2 ?trans1;
IADD3 R5, PT, PT, R5, 0x10, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R5, RZ, PT ?trans1;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R6.64+0x18], R17 &req={2} ?trans4;
LDG.E R19, desc[UR6][R8.64+0x3c] &req={3} &wr=0x2 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x10, URZ ?trans1;
IADD3 R11, PT, PT, R11, 0x10, RZ ?trans2;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R6.64+0x1c], R19 &req={2} &rd=0x0 ?trans2;
IADD.64 R6, R6, 0x40 &req={0} ?WAIT2_END_GROUP;
@P1 BRA 0x200 ?trans6;
@!P0 EXIT ?trans5;
ISETP.GE.U32.AND P1, PT, R10, 0x8, PT ?trans1;
LOP3.LUT R14, R4, 0x7, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R14, RZ, PT ?WAIT7_END_GROUP;
@!P1 BRA 0x6a0 ?trans6;
LDC.64 R8, c[0x0][0x3a0] &wr=0x0 ?trans1;
IADD3 R3, PT, PT, R0, UR4, RZ ?trans1;
LDCU.64 UR8, c[0x0][0x3a8] &wr=0x1 ?trans6;
LDC.64 R6, c[0x0][0x3a8] &wr=0x2 ?trans1;
IMAD.WIDE R8, R3, 0x4, R8 &req={0} ?WAIT5_END_GROUP;
LDG.E R5, desc[UR6][R8.64] &wr=0x3 ?trans1;
IADD3 R3, PT, PT, R2, UR4, RZ ?WAIT5_END_GROUP;
IMAD.WIDE.U32 R6, R3, 0x4, R6 &req={2} ?WAIT4_END_GROUP;
HFMA2 R3, -RZ, RZ, 0, 0 ?trans1;
UMOV UR5, URZ ?WAIT4_END_GROUP;
IADD.64 R10, R2, UR4 ?trans2;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R6.64], R5 &req={3} &rd=0x0 ?trans4;
LDG.E R15, desc[UR6][R8.64+0x4] &wr=0x2 ?trans1;
LEA R12, P1, R10, UR8, 0x2 &req={1} ?WAIT4_END_GROUP;
LEA.HI.X R13, R10, UR9, R11, 0x2, P1 ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R12.64+0x4], R15 &req={2} &rd=0x1 ?trans4;
LDG.E R11, desc[UR6][R8.64+0x8] &wr=0x2 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R12.64+0x8], R11 &req={2} &rd=0x2 ?trans4;
LDG.E R5, desc[UR6][R8.64+0xc] &req={0} &wr=0x3 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R12.64+0xc], R5 &req={3} &rd=0x2 ?trans4;
LDG.E R7, desc[UR6][R8.64+0x10] &wr=0x3 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R12.64+0x10], R7 &req={3} &rd=0x2 ?trans4;
LDG.E R17, desc[UR6][R8.64+0x14] &wr=0x3 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R12.64+0x14], R17 &req={3} &rd=0x2 ?trans4;
LDG.E R19, desc[UR6][R8.64+0x18] &wr=0x3 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R12.64+0x18], R19 &req={3} &rd=0x2 ?trans4;
LDG.E R15, desc[UR6][R8.64+0x1c] &req={1} &wr=0x3 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x8, URZ ?WAIT3_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R12.64+0x1c], R15 &req={3} &rd=0x2 ?trans9;
@!P0 EXIT ?trans5;
ISETP.GE.U32.AND P1, PT, R14, 0x4, PT ?trans1;
LOP3.LUT R12, R4, 0x3, RZ, 0xc0, !PT &req={2} ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R12, RZ, PT ?WAIT7_END_GROUP;
@!P1 BRA 0x850 ?trans6;
LDC.64 R4, c[0x0][0x3a0] &wr=0x0 ?trans1;
IADD3 R7, PT, PT, R0, UR4, RZ ?trans2;
IADD3 R9, PT, PT, R2, UR4, RZ ?trans1;
LDCU.64 UR8, c[0x0][0x3a8] &wr=0x1 ?trans2;
IMAD.WIDE R6, R7, 0x4, R4 &req={0} ?trans2;
LDC.64 R4, c[0x0][0x3a8] &wr=0x0 ?trans3;
LDG.E R13, desc[UR6][R6.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R4, R9, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R4.64], R13 &req={2} &rd=0x0 ?trans4;
LDG.E R15, desc[UR6][R6.64+0x4] &wr=0x2 ?trans1;
UMOV UR5, URZ ?trans1;
MOV R4, R2 &req={0} ?trans1;
HFMA2 R5, -RZ, RZ, 0, 0 ?WAIT5_END_GROUP;
IADD.64 R8, R4, UR4 ?WAIT5_END_GROUP;
LEA R10, P1, R8, UR8, 0x2 &req={1} ?WAIT4_END_GROUP;
LEA.HI.X R11, R8, UR9, R9, 0x2, P1 ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R10.64+0x4], R15 &req={2} &rd=0x0 ?trans4;
LDG.E R9, desc[UR6][R6.64+0x8] &wr=0x2 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R10.64+0x8], R9 &req={2} &rd=0x0 ?trans4;
LDG.E R5, desc[UR6][R6.64+0xc] &wr=0x2 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x4, URZ ?WAIT3_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R10.64+0xc], R5 &req={2} &rd=0x0 ?trans9;
@!P0 EXIT ?trans5;
LDC.64 R4, c[0x0][0x3a8] &req={0} &wr=0x0 ?trans1;
IADD3 R3, PT, PT, R2, UR4, RZ ?trans2;
IADD3 R9, PT, PT, R0, UR4, RZ ?trans2;
IADD3 R12, PT, PT, -R12, RZ, RZ ?WAIT3_END_GROUP;
LDC.64 R6, c[0x0][0x3a0] &wr=0x1 ?trans1;
IMAD.WIDE.U32 R2, R3, 0x4, R4 &req={0} ?WAIT7_END_GROUP;
IMAD.WIDE R4, R9, 0x4, R6 &req={1} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR6][R4.64] &wr=0x2 ?trans1;
IADD3 R12, PT, PT, R12, 0x1, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R12, RZ, PT ?trans1;
IADD3 R9, PT, PT, R9, 0x1, RZ ?trans1;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R2.64], R5 &req={2} &rd=0x0 ?trans2;
IADD.64 R2, R2, 0x4 &req={0} ?WAIT9_END_GROUP;
@P0 BRA 0x8c0 ?trans5;
EXIT ?trans5;
BRA 0x950;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: voxel2col_grad_gpu_kernel(int, int, int, int, float const*, int const*, float const*, float*)
_Z25voxel2col_grad_gpu_kerneliiiiPKfPKiS0_Pf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mul_i32 s2, s5, s4
s_mul_i32 s2, s2, s6
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_6
s_load_b128 s[8:11], s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
s_cmp_gt_i32 s7, 0
s_mov_b32 s2, 0
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s8, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, -1, v0
s_and_b32 s3, vcc_lo, s3
s_and_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB1_6
s_load_b64 s[0:1], s[0:1], 0x28
v_mul_lo_u32 v4, v0, s7
v_mul_lo_u32 v5, v1, s7
.LBB1_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v0, s2, v5
v_add_nc_u32_e32 v2, s2, v4
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v1, vcc_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_load_b32 v6, v[6:7], off
global_load_b32 v3, v[0:1], off
.LBB1_4:
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v3, v6
global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v2, v3
v_mov_b32_e32 v3, v2
s_or_b32 s3, vcc_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB1_4
s_or_b32 exec_lo, exec_lo, s3
s_add_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s2, s7
s_cbranch_scc1 .LBB1_3
.LBB1_6:
s_endpgm
| voxel2col_grad_gpu_kernel | 4,650 | 1,307 | stackv2-00000-of-00015 |
// Demangled: vecAdd_kernel(int const*, int const*, int*)
Function : _Z13vecAdd_kernelPKiS0_Pi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R0, SR_TID.X &wr=0x0 ?trans7;
S2UR UR6, SR_CTAID.X &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC R9, c[0x0][0x360] &wr=0x0 ?trans8;
LDC.64 R2, c[0x0][0x380] &wr=0x2 ?trans8;
LDC.64 R4, c[0x0][0x388] &wr=0x3 ?trans1;
IMAD R9, R9, UR6, R0 &req={0} ?WAIT7_END_GROUP;
LDC.64 R6, c[0x0][0x390] &wr=0x0 ?trans1;
IMAD.WIDE R2, R9, 0x4, R2 &req={2} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans1;
IMAD.WIDE R4, R9, 0x4, R4 &req={3} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE R6, R9, 0x4, R6 &req={0} ?trans1;
IADD3 R9, PT, PT, R2, R5, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x110;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: vecAdd_kernel(int const*, int const*, int*)
_Z13vecAdd_kernelPKiS0_Pi:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| vecAdd_kernel | 505 | 501 | stackv2-00000-of-00015 |
// Demangled: matrixMultiply1(float*, float*, int)
Function : _Z15matrixMultiply1PfS_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
LDC R10, c[0x0][0x390] &wr=0x1 ?trans1;
S2R R0, SR_CTAID.X &wr=0x2 ?trans1;
LDCU UR5, c[0x0][0x364] &wr=0x3 ?trans1;
S2R R3, SR_TID.X &wr=0x2 ?trans1;
LDCU UR6, c[0x0][0x360] &wr=0x2 ?trans4;
S2UR UR4, SR_CTAID.Y &wr=0x3 ?trans1;
ISETP.GE.AND P0, PT, R10, 0x1, PT &req={1} ?trans1;
UIMAD UR5, UR5, UR4, URZ &req={3} ?trans1;
IMAD R0, R0, UR6, R3 &req={2} ?WAIT11_END_GROUP;
@!P0 EXIT &req={0} ?trans5;
S2R R35, SR_TID.Y &wr=0x0 ?trans1;
LDC.64 R12, c[0x0][0x388] &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x2 ?trans1;
ISETP.GE.U32.AND P0, PT, R10, 0x8, PT ?trans1;
UMOV UR4, URZ ?trans1;
IADD3 R3, PT, PT, R35, UR5, RZ &req={0} ?WAIT5_END_GROUP;
IMAD R5, R0, R10, R3 ?WAIT4_END_GROUP;
IMAD.WIDE R12, R5, 0x4, R12 &req={1} ?WAIT5_END_GROUP;
LDG.E R36, desc[UR6][R12.64] &req={2} &rd=0x0 &wr=0x5 ?trans1;
@!P0 BRA 0x690 ?trans5;
LDC.64 R14, c[0x0][0x380] &wr=0x1 ?trans1;
SHF.L.U32 R4, R10.reuse, 0x1, RZ ?trans1;
IMAD R34, R10.reuse, 0x3, R3.reuse ?trans1;
LOP3.LUT R2, R10.reuse, 0x7ffffff8, RZ, 0xc0, !PT ?trans1;
IMAD R6, R10.reuse, 0x5, R3 ?trans1;
IADD3 R35, PT, PT, R10, UR5, R35 ?trans1;
IMAD.WIDE.U32 R16, R4, 0x4, RZ ?trans1;
LEA R5, R10.reuse, R3.reuse, 0x2 ?trans1;
UMOV UR4, URZ ?trans1;
MOV R37, R0 ?trans1;
IMAD R7, R10.reuse, 0x6, R3 ?trans1;
MOV R9, R3 ?trans1;
IMAD.WIDE.U32 R18, R10, 0x14, R16 ?trans1;
IADD3 R4, PT, PT, R3, R4, RZ ?WAIT2_END_GROUP;
IADD3 R2, PT, PT, -R2, RZ, RZ ?trans1;
IMAD.WIDE.U32 R20, R10, 0x10, R16 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R22, R10, 0xc, R16 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R24, R10, 0x8, R16 ?trans1;
IADD.64 R18, R18, R14.reuse &req={1} ?trans2;
IADD.64 R20, R20, R14.reuse ?trans2;
IADD.64 R22, R22, R14.reuse ?trans2;
IADD.64 R24, R24, R14 ?trans2;
IMAD R8, R10, 0x7, R3 ?WAIT7_END_GROUP;
IMAD.WIDE.U32 R32, R9, 0x4, R14 ?WAIT4_END_GROUP;
IMAD.WIDE R30, R37, 0x4, R14.reuse ?trans2;
LDG.E R32, desc[UR6][R32.64] &wr=0x2 ?trans4;
LDG.E R27, desc[UR6][R30.64] &req={1} &wr=0x2 ?trans1;
IMAD.WIDE.U32 R28, R35, 0x4, R14 ?WAIT4_END_GROUP;
FFMA R33, R27, R32, R36 &req={5,2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R12.64], R33 ?trans4;
LDG.E R26, desc[UR6][R28.64] &rd=0x1 &wr=0x2 ?trans2;
IMAD.WIDE.U32 R28, R10, 0x4, R30 &req={1} ?WAIT5_END_GROUP;
LDG.E R36, desc[UR6][R28.64] &wr=0x2 ?trans2;
FFMA R36, R36, R26, R33 &req={2} ?trans1;
IADD.64 R26, R16, R30 ?WAIT4_END_GROUP;
STG.E desc[UR6][R12.64], R36 &rd=0x1 ?trans4;
LDG.E R32, desc[UR6][R26.64] &rd=0x2 &wr=0x1 ?trans2;
IMAD.WIDE.U32 R26, R4, 0x4, R14 &req={2} ?WAIT5_END_GROUP;
LDG.E R31, desc[UR6][R26.64] &wr=0x1 ?trans2;
FFMA R36, R32, R31, R36 &req={1} ?trans1;
IADD.64 R32, R16, R28 ?trans2;
IMAD.WIDE.U32 R30, R34, 0x4, R14 ?trans2;
STG.E desc[UR6][R12.64], R36 &rd=0x1 ?trans4;
LDG.E R33, desc[UR6][R32.64] &wr=0x2 ?trans4;
LDG.E R30, desc[UR6][R30.64] &wr=0x2 ?trans2;
FFMA R29, R33, R30, R36 &req={2} ?trans1;
IMAD.WIDE R32, R37, 0x4, R24 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R30, R5, 0x4, R14 ?trans1;
STG.E desc[UR6][R12.64], R29 &rd=0x2 ?trans4;
LDG.E R26, desc[UR6][R32.64] &wr=0x1 ?trans4;
LDG.E R27, desc[UR6][R30.64] &wr=0x1 ?trans2;
FFMA R36, R26, R27, R29 &req={1} ?trans1;
IMAD.WIDE R26, R37, 0x4, R22 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R28, R6, 0x4, R14 &req={2} ?trans1;
STG.E desc[UR6][R12.64], R36 ?trans4;
LDG.E R27, desc[UR6][R26.64] &wr=0x2 ?trans4;
LDG.E R28, desc[UR6][R28.64] &wr=0x2 ?trans2;
FFMA R31, R27, R28, R36 &req={2} ?trans1;
IMAD.WIDE R26, R37, 0x4, R20 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R28, R7, 0x4, R14 ?trans1;
STG.E desc[UR6][R12.64], R31 &rd=0x1 ?trans4;
LDG.E R30, desc[UR6][R26.64] &wr=0x2 ?trans4;
LDG.E R32, desc[UR6][R28.64] &wr=0x2 ?trans1;
IADD3 R2, PT, PT, R2, 0x8, RZ ?trans1;
FFMA R27, R30, R32, R31 &req={2} ?trans1;
IMAD.WIDE R30, R37, 0x4, R18 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R32, R8, 0x4, R14 ?trans1;
STG.E desc[UR6][R12.64], R27 &rd=0x1 ?trans4;
LDG.E R30, desc[UR6][R30.64] &wr=0x2 ?trans4;
LDG.E R32, desc[UR6][R32.64] &wr=0x2 ?trans1;
ISETP.NE.AND P0, PT, R2, RZ, PT ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x8, URZ ?trans1;
LEA R35, R10, R35, 0x3 ?WAIT2_END_GROUP;
LEA R4, R10.reuse, R4, 0x3 ?trans2;
LEA R34, R10.reuse, R34, 0x3 ?trans2;
LEA R5, R10.reuse, R5, 0x3 ?trans2;
LEA R6, R10.reuse, R6, 0x3 ?trans2;
LEA R7, R10.reuse, R7, 0x3 ?trans2;
LEA R8, R10, R8, 0x3 ?WAIT2_END_GROUP;
LEA R9, R10.reuse, R9, 0x3 ?trans2;
LEA R37, R10, R37, 0x3 ?trans1;
FFMA R36, R30, R32, R27 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R12.64], R36 &rd=0x1 ?trans1;
@P0 BRA 0x2c0 ?trans5;
LOP3.LUT R4, R10, 0x7, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R4, RZ, PT ?WAIT13_END_GROUP;
@!P0 EXIT ?trans5;
ISETP.GE.U32.AND P1, PT, R4, 0x4, PT ?trans1;
LOP3.LUT R2, R10, 0x3, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R2, RZ, PT ?WAIT7_END_GROUP;
@!P1 BRA 0x940 ?trans6;
LDC.64 R4, c[0x0][0x380] &wr=0x2 ?trans1;
IMAD R15, R10.reuse, UR4, R3 ?trans2;
IMAD R7, R10, UR4, R0 ?trans2;
IMAD.WIDE.U32 R8, R15, 0x4, R4 &req={2} ?WAIT4_END_GROUP;
IMAD.WIDE R6, R7, 0x4, R4 ?trans2;
LDG.E R8, desc[UR6][R8.64] &wr=0x2 ?trans4;
LDG.E R11, desc[UR6][R6.64] &wr=0x2 ?trans1;
IADD3 R19, PT, PT, R15, R10, RZ ?trans1;
IMAD.WIDE.U32 R14, R10, 0x4, R6 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R16, R19, 0x4, R4 ?WAIT4_END_GROUP;
FFMA R11, R11, R8, R36 &req={5,2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R12.64], R11 &rd=0x2 ?trans4;
LDG.E R14, desc[UR6][R14.64] &wr=0x3 ?trans4;
LDG.E R16, desc[UR6][R16.64] &wr=0x3 ?trans1;
IADD3 R25, PT, PT, R19, R10.reuse, RZ ?trans2;
IADD3 R18, PT, PT, R10, R10, RZ ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R20, R25, 0x4, R4 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R8, R18, 0x4, R6 ?WAIT4_END_GROUP;
FFMA R23, R14, R16, R11 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R12.64], R23 &rd=0x3 ?trans4;
LDG.E R20, desc[UR6][R20.64] &wr=0x4 ?trans4;
LDG.E R8, desc[UR6][R8.64] &wr=0x4 ?trans1;
HFMA2 R11, -RZ, RZ, 0, 0 &req={2} ?trans1;
MOV R19, RZ ?trans1;
IADD3 R25, PT, PT, R25, R10, RZ ?WAIT4_END_GROUP;
IADD.64 R18, R10, R18 ?trans2;
IMAD.WIDE.U32 R4, R25, 0x4, R4 ?WAIT3_END_GROUP;
LEA R6, P1, R18, R6, 0x2 ?WAIT4_END_GROUP;
LEA.HI.X R7, R18, R7, R19, 0x2, P1 ?trans1;
FFMA R15, R8, R20, R23 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R12.64], R15 &rd=0x3 ?trans4;
LDG.E R4, desc[UR6][R4.64] &wr=0x2 ?trans4;
LDG.E R6, desc[UR6][R6.64] &wr=0x2 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x4, URZ ?trans1;
FFMA R36, R6, R4, R15 &req={2,1} ?WAIT5_END_GROUP;
STG.E desc[UR6][R12.64], R36 &rd=0x3 ?trans6;
@!P0 EXIT ?trans5;
ISETP.NE.AND P0, PT, R2, 0x1, PT ?trans1;
LOP3.LUT R4, R10, 0x1, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.U32.AND P1, PT, R4, 0x1, PT ?WAIT7_END_GROUP;
@!P0 BRA 0xaa0 ?trans6;
LDC.64 R4, c[0x0][0x380] &wr=0x2 ?trans1;
IMAD R17, R10.reuse, UR4, R3 ?trans2;
IMAD R7, R10, UR4, R0 ?trans2;
IMAD.WIDE.U32 R8, R17, 0x4, R4 &req={2} ?WAIT4_END_GROUP;
IMAD.WIDE R6, R7, 0x4, R4 ?trans2;
LDG.E R8, desc[UR6][R8.64] &wr=0x2 ?trans4;
LDG.E R15, desc[UR6][R6.64] &req={3} &wr=0x2 ?trans1;
IADD3 R19, PT, PT, R17, R10, RZ ?WAIT5_END_GROUP;
IMAD.WIDE.U32 R4, R19, 0x4, R4 ?WAIT4_END_GROUP;
FFMA R17, R15, R8, R36 &req={5,2} ?trans1;
IMAD.WIDE.U32 R14, R10, 0x4, R6 ?WAIT4_END_GROUP;
STG.E desc[UR6][R12.64], R17 &rd=0x2 ?trans4;
LDG.E R14, desc[UR6][R14.64] &wr=0x3 ?trans4;
LDG.E R4, desc[UR6][R4.64] &wr=0x3 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x2, URZ ?trans1;
FFMA R36, R14, R4, R17 &req={3,1} ?WAIT5_END_GROUP;
STG.E desc[UR6][R12.64], R36 &rd=0x2 ?trans6;
@P1 EXIT ?trans5;
LDC.64 R4, c[0x0][0x380] &wr=0x4 ?trans1;
IMAD R7, R10.reuse, UR4, R0 ?trans2;
IMAD R11, R10, UR4, R3 ?trans2;
IMAD.WIDE R2, R7, 0x4, R4 &req={4} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R11, 0x4, R4 ?trans2;
LDG.E R3, desc[UR6][R2.64] &wr=0x4 ?trans4;
LDG.E R4, desc[UR6][R4.64] &wr=0x4 ?trans2;
FFMA R7, R3, R4, R36 &req={5,4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R12.64], R7 ?trans1;
EXIT ?trans5;
BRA 0xb50;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: matrixMultiply1(float*, float*, int)
_Z15matrixMultiply1PfS_i:
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_3
s_load_b32 s2, s[0:1], 0x24
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_mov_b32 s2, 0
s_mov_b32 s3, s4
global_load_b32 v4, v[2:3], off
.LBB0_2:
v_add_nc_u32_e32 v5, s2, v1
v_add_nc_u32_e32 v7, s2, v0
s_add_i32 s3, s3, -1
s_add_i32 s2, s2, s4
s_cmp_eq_u32 s3, 0
v_ashrrev_i32_e32 v6, 31, v5
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
s_clause 0x1
global_load_b32 v5, v[5:6], off
global_load_b32 v6, v[7:8], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v4, v5, v6
global_store_b32 v[2:3], v4, off
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| matrixMultiply1 | 4,681 | 1,005 | stackv2-00000-of-00015 |
// Demangled: matrixMultiply2(float*, float*, int)
Function : _Z15matrixMultiply2PfS_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR12, c[0x0][0x390] &wr=0x2 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans1;
S2R R5, SR_CTAID.Y &wr=0x3 ?trans1;
S2R R2, SR_TID.Y &wr=0x3 ?trans1;
IMAD R3, R3, 0x20, R0 &req={1} ?trans2;
IMAD R4, R5, 0x20, R2 &req={3} ?WAIT5_END_GROUP;
VIMNMX.S32 R0, R3, R4, !PT ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, UR12, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
UISETP.GE.U32.AND UP0, UPT, UR12, 0x8, UPT ?trans1;
UMOV UR4, URZ ?trans1;
LDCU.64 UR10, c[0x0][0x358] &wr=0x0 ?trans1;
HFMA2 R13, -RZ, RZ, 0, 0 ?WAIT3_END_GROUP;
PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x8 ?WAIT13_END_GROUP;
@!P0 BRA 0x760 ?trans5;
LDCU.64 UR14, c[0x0][0x380] &wr=0x1 ?trans1;
MOV R9, UR12 ?trans1;
IADD3 R0, PT, PT, R2, UR12, RZ ?trans1;
MOV R7, UR12 ?trans1;
MOV R11, UR12 ?trans1;
MOV R31, UR12 ?trans1;
MOV R15, UR12 ?trans1;
MOV R17, UR12 ?trans1;
ULOP3.LUT UR4, UR12, 0x7ffffff8, URZ, 0xc0, !UPT ?trans1;
IMAD R10, R9, 0x4, R4 ?trans1;
MOV R13, RZ ?trans1;
IMAD R0, R5, 0x20, R0 ?trans1;
MOV R5, R4 ?trans1;
IMAD R30, R7, 0x3, R4.reuse ?trans1;
MOV R2, R3 ?trans1;
IMAD R9, R11, 0x5, R4.reuse ?trans1;
IADD3 R31, PT, PT, R4, UR12, R31 ?trans1;
IMAD R7, R15, 0x6, R4.reuse ?trans1;
UIADD3 UR5, UPT, UPT, -UR4, URZ, URZ ?trans1;
IMAD R11, R17, 0x7, R4 ?trans1;
UIMAD.WIDE UR6, UR12, 0x14, UR14 &req={1} ?trans1;
UIMAD.WIDE UR8, UR12, 0x10, UR14 ?trans1;
UMOV UR4, URZ ?WAIT11_END_GROUP;
MOV R14, 0x4 ?trans1;
UIMAD.WIDE UR16, UR12, 0x4, UR14 ?trans1;
HFMA2 R25, -RZ, RZ, 0, 2.384185791015625e-07 ?trans2;
HFMA2 R17, -RZ, RZ, 0, 2.384185791015625e-07 ?trans2;
IMAD.WIDE.U32 R14, R5, R14, UR14 ?trans1;
MOV R19, 0x4 ?WAIT3_END_GROUP;
HFMA2 R21, -RZ, RZ, 0, 2.384185791015625e-07 ?trans2;
IMAD.WIDE R16, R2, R17, UR16 ?trans1;
LDG.E R12, desc[UR10][R14.64] &req={0} &rd=0x0 &wr=0x2 ?trans1;
UIMAD.WIDE UR16, UR12, 0x8, UR14 ?trans1;
MOV R22, 0x4 ?trans1;
IMAD.WIDE.U32 R18, R0, R19, UR14 ?trans1;
LDG.E R8, desc[UR10][R16.64] &rd=0x1 &wr=0x3 ?trans3;
IMAD.WIDE R14, R2, R25, UR14 &req={0} ?trans1;
UIMAD.WIDE UR18, UR12, 0xc, UR14 ?trans1;
MOV R29, 0x4 ?trans1;
LDG.E R25, desc[UR10][R18.64] &rd=0x0 &wr=0x3 ?trans1;
HFMA2 R17, -RZ, RZ, 0, 2.384185791015625e-07 &req={1} ?WAIT3_END_GROUP;
LDG.E R24, desc[UR10][R14.64] &wr=0x2 ?trans1;
IMAD.WIDE R20, R2, R21, UR16 ?WAIT4_END_GROUP;
HFMA2 R37, -RZ, RZ, 0, 2.384185791015625e-07 ?trans2;
IMAD.WIDE.U32 R22, R31, R22, UR14 ?trans1;
MOV R27, 0x4 ?trans1;
MOV R35, 0x4 ?trans1;
LDG.E R33, desc[UR10][R20.64] &rd=0x1 &wr=0x4 ?trans1;
IMAD.WIDE R28, R2, R29, UR18 ?WAIT4_END_GROUP;
HFMA2 R26, -RZ, RZ, 0, 2.384185791015625e-07 ?trans1;
LDG.E R32, desc[UR10][R22.64] &rd=0x5 &wr=0x4 ?trans1;
IMAD.WIDE.U32 R16, R30, R17, UR14 ?trans1;
MOV R36, UR12 ?trans2;
LDG.E R6, desc[UR10][R28.64] &rd=0x5 &wr=0x4 ?trans1;
IMAD.WIDE R18, R2, R27, UR8 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R20, R10, R37, UR14 &req={1} ?trans1;
LDG.E R34, desc[UR10][R18.64] &wr=0x4 ?trans3;
IMAD.WIDE R22, R2, R35, UR6 &req={5} ?trans1;
MOV R28, 0x4 ?trans1;
LDG.E R35, desc[UR10][R16.64] &rd=0x0 &wr=0x5 ?trans2;
IMAD.WIDE.U32 R26, R9, R26, UR14 ?trans1;
MOV R37, UR12 ?trans1;
LDG.E R21, desc[UR10][R20.64] &rd=0x1 &wr=0x5 ?trans2;
IMAD.WIDE.U32 R28, R7, R28, UR14 ?WAIT2_END_GROUP;
LDG.E R22, desc[UR10][R22.64] &rd=0x1 &wr=0x5 ?trans2;
IMAD.WIDE R16, R36, 0x18, R14.reuse &req={0} ?trans2;
LDG.E R27, desc[UR10][R26.64] &wr=0x5 ?trans2;
HFMA2 R20, -RZ, RZ, 0, 2.384185791015625e-07 &req={1} ?trans2;
IMAD.WIDE R18, R37, 0x1c, R14 ?trans1;
LDG.E R28, desc[UR10][R28.64] &wr=0x5 ?trans3;
IMAD.WIDE.U32 R14, R11, R20, UR14 ?trans1;
LDG.E R17, desc[UR10][R16.64] &wr=0x5 ?trans4;
LDG.E R19, desc[UR10][R18.64] &wr=0x5 ?trans4;
LDG.E R14, desc[UR10][R14.64] &rd=0x0 &wr=0x5 ?trans1;
UIADD3 UR5, UPT, UPT, UR5, 0x8, URZ ?WAIT6_END_GROUP;
ISETP.NE.AND P0, PT, RZ, UR5, PT ?trans1;
MOV R23, UR12 ?trans1;
MOV R15, UR12 &req={0} ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x8, URZ ?WAIT3_END_GROUP;
IMAD R0, R23, 0x8, R0 ?trans2;
IMAD R10, R15, 0x8, R10 ?trans2;
FFMA R12, R12, R24, R13 &req={2} ?WAIT4_END_GROUP;
FFMA R25, R25, R8, R12 &req={3} ?WAIT4_END_GROUP;
FFMA R32, R32, R33, R25 &req={4} ?trans1;
MOV R13, UR12 ?trans1;
MOV R8, UR12 ?trans1;
MOV R12, UR12 ?trans1;
FFMA R6, R35, R6, R32 &req={5} ?WAIT4_END_GROUP;
FFMA R6, R21, R34, R6 ?trans1;
IMAD R2, R13, 0x8, R2 ?WAIT3_END_GROUP;
FFMA R27, R27, R22, R6 ?trans1;
MOV R6, UR12 ?trans1;
IMAD R30, R13, 0x8, R30 ?trans1;
LEA R31, R8.reuse, R31, 0x3 ?trans1;
IMAD R9, R8, 0x8, R9 ?trans2;
FFMA R17, R28, R17, R27 ?trans1;
LEA R7, R6, R7, 0x3 ?trans1;
IMAD R11, R8, 0x8, R11 ?trans2;
IMAD R5, R12, 0x8, R5 ?WAIT2_END_GROUP;
FFMA R13, R14, R19, R17 ?trans1;
@P0 BRA 0x280 ?trans6;
ULOP3.LUT UR5, UR12, 0x7, URZ, 0xc0, !UPT ?WAIT6_END_GROUP;
ISETP.NE.AND P0, PT, RZ, UR5, PT ?WAIT13_END_GROUP;
@!P0 BRA 0xc90 ?trans5;
UISETP.GE.U32.AND UP0, UPT, UR5, 0x4, UPT ?trans1;
ULOP3.LUT UR5, UR12, 0x3, URZ, 0xc0, !UPT ?WAIT5_END_GROUP;
PLOP3.LUT P1, PT, PT, PT, UP0, 0x80, 0x8 ?trans1;
ISETP.NE.AND P0, PT, RZ, UR5, PT ?WAIT12_END_GROUP;
@!P1 BRA 0xa30 ?trans5;
LDC.64 R6, c[0x0][0x380] &wr=0x1 ?trans1;
MOV R17, UR4 ?trans1;
USHF.R.S32.HI UR6, URZ, 0x1f, UR12 ?trans1;
MOV R0, UR4 ?trans1;
MOV R14, UR12 ?trans2;
IMAD R17, R17, UR12, R4 ?trans2;
IMAD R9, R0, UR12, R3 ?trans1;
MOV R15, UR6 ?trans2;
IADD3 R5, PT, PT, R17, UR12, RZ ?trans1;
MOV R21, UR12 ?WAIT2_END_GROUP;
IADD.64 R24, R14, R14 ?WAIT4_END_GROUP;
IADD.64 R14, R14, R24 ?trans2;
IMAD.WIDE R8, R9, 0x4, R6 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R18, R5.reuse, 0x4, R6 ?trans1;
IADD3 R5, PT, PT, R5, UR12, RZ ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R16, R17, 0x4, R6 ?trans1;
LEA R10, P1, R24.reuse, R8.reuse, 0x2 ?trans1;
LDG.E R2, desc[UR10][R8.64] &req={0} &wr=0x2 ?trans2;
IMAD.WIDE R20, R21, 0x4, R8 ?trans2;
LDG.E R0, desc[UR10][R16.64] &rd=0x0 &wr=0x2 ?trans2;
IMAD.WIDE.U32 R22, R5.reuse, 0x4, R6 ?trans1;
IADD3 R5, PT, PT, R5, UR12, RZ ?trans2;
LEA.HI.X R11, R24, R9, R25, 0x2, P1 ?trans1;
LDG.E R19, desc[UR10][R18.64] &wr=0x3 ?trans4;
LDG.E R20, desc[UR10][R20.64] &wr=0x3 ?trans1;
LEA R16, P1, R14, R8, 0x2 &req={0} ?trans1;
IMAD.WIDE.U32 R6, R5, 0x4, R6 ?WAIT2_END_GROUP;
LDG.E R23, desc[UR10][R22.64] &wr=0x4 ?trans1;
LEA.HI.X R17, R14, R9, R15, 0x2, P1 ?WAIT3_END_GROUP;
LDG.E R10, desc[UR10][R10.64] &wr=0x4 ?trans4;
LDG.E R7, desc[UR10][R6.64] &wr=0x5 ?trans4;
LDG.E R16, desc[UR10][R16.64] &wr=0x5 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x4, URZ ?trans1;
FFMA R0, R0, R2, R13 &req={2} ?WAIT4_END_GROUP;
FFMA R0, R19, R20, R0 &req={3} ?WAIT4_END_GROUP;
FFMA R0, R23, R10, R0 &req={4} ?WAIT4_END_GROUP;
FFMA R13, R7, R16, R0 &req={5} ?WAIT7_END_GROUP;
@!P0 BRA 0xc90 ?trans5;
UISETP.NE.AND UP0, UPT, UR5, 0x1, UPT ?trans1;
ULOP3.LUT UR5, UR12, 0x1, URZ, 0xc0, !UPT ?trans1;
MOV R5, UR4 ?trans1;
MOV R0, UR4 ?trans2;
UISETP.NE.U32.AND UP1, UPT, UR5, 0x1, UPT ?trans1;
PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x8 ?WAIT5_END_GROUP;
@UP0 LDCU.64 UR6, c[0x0][0x380] &wr=0x1 ?trans1;
PLOP3.LUT P1, PT, PT, PT, UP1, 0x80, 0x8 ?trans1;
@UP0 UIADD3 UR4, UPT, UPT, UR4, 0x2, URZ ?WAIT3_END_GROUP;
@!UP1 LDCU.64 UR8, c[0x0][0x380] &wr=0x2 ?trans3;
@P0 IMAD R5, R5, UR12, R4 ?trans2;
@P0 IMAD R7, R0, UR12, R3 ?trans1;
MOV.64 R14, UR6 &req={1} ?trans2;
MOV.64 R10, UR6 ?WAIT4_END_GROUP;
@P0 IMAD.WIDE.U32 R8, R5.reuse, 0x4, R14 ?trans1;
@P0 IADD3 R5, PT, PT, R5, UR12, RZ ?WAIT3_END_GROUP;
@P0 IMAD.WIDE R10, R7, 0x4, R10 ?trans1;
MOV R7, UR4 ?trans1;
MOV R2, UR4 ?trans1;
MOV R17, UR12 ?trans1;
@P0 IMAD.WIDE.U32 R14, R5, 0x4, R14 ?trans1;
MOV.64 R18, UR8 &req={2} ?trans2;
@P0 LDG.E R0, desc[UR10][R8.64] &req={0} &rd=0x0 &wr=0x2 ?trans1;
@!P1 IMAD R5, R7, UR12, R4 ?trans1;
MOV.64 R6, UR8 ?trans2;
@!P1 IMAD R21, R2, UR12, R3 ?trans1;
@P0 LDG.E R15, desc[UR10][R14.64] &wr=0x3 ?trans1;
@P0 IMAD.WIDE R16, R17, 0x4, R10 ?WAIT3_END_GROUP;
@P0 LDG.E R10, desc[UR10][R10.64] &wr=0x2 ?trans1;
@!P1 IMAD.WIDE.U32 R6, R5, 0x4, R6 ?WAIT3_END_GROUP;
@P0 LDG.E R16, desc[UR10][R16.64] &wr=0x3 ?trans1;
@!P1 IMAD.WIDE R8, R21, 0x4, R18 &req={0} ?WAIT3_END_GROUP;
@!P1 LDG.E R6, desc[UR10][R6.64] &wr=0x4 ?trans4;
@!P1 LDG.E R8, desc[UR10][R8.64] &wr=0x4 ?trans1;
@P0 FFMA R0, R0, R10, R13 &req={2} ?WAIT4_END_GROUP;
@P0 FFMA R13, R15, R16, R0 &req={3} ?WAIT4_END_GROUP;
@!P1 FFMA R13, R6, R8, R13 &req={4} ?WAIT7_END_GROUP;
LDC.64 R6, c[0x0][0x388] &wr=0x1 ?trans1;
IMAD R3, R4, UR12, R3 ?WAIT4_END_GROUP;
IMAD.WIDE R2, R3, 0x4, R6 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR10][R2.64], R13 &req={0} ?trans1;
EXIT ?trans5;
BRA 0xce0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: matrixMultiply2(float*, float*, int)
_Z15matrixMultiply2PfS_i:
s_load_b32 s4, s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v2, v0, 10, 10
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v0, s14, 5, v1
v_lshl_add_u32 v1, s15, 5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_max_i32_e32 v2, v0, v1
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s4, v2
s_cbranch_execz .LBB1_5
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB1_4
s_mov_b32 s5, 0
s_mov_b32 s6, s4
.LBB1_3:
v_add_nc_u32_e32 v3, s5, v1
v_add_nc_u32_e32 v5, s5, v0
s_add_i32 s6, s6, -1
s_add_i32 s5, s5, s4
s_cmp_eq_u32 s6, 0
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v4, v[5:6], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v2, v3, v4
s_cbranch_scc0 .LBB1_3
.LBB1_4:
v_mad_u64_u32 v[3:4], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB1_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| matrixMultiply2 | 5,129 | 1,029 | stackv2-00000-of-00015 |
// Demangled: matrixMultiply3(float*, float*, int)
Function : _Z15matrixMultiply3PfS_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
LDCU UR4, c[0x0][0x390] &wr=0x1 ?trans1;
S2R R7, SR_CTAID.Y &wr=0x2 ?trans1;
HFMA2 R17, -RZ, RZ, 0, 0 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x3 ?trans1;
S2R R0, SR_CTAID.X &wr=0x4 ?trans1;
S2R R3, SR_TID.X &wr=0x4 ?trans1;
S2R R2, SR_TID.Y &wr=0x2 ?trans1;
MOV R4, UR4 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R4, 0x1, PT ?trans1;
LEA R27, R0, R3, 0x5 &req={4} ?trans2;
LEA R6, R7, R2, 0x5 &req={2} ?WAIT5_END_GROUP;
VIMNMX.S32 R21, R27, R6, !PT ?WAIT5_END_GROUP;
@!P0 BRA 0x730 &req={3} ?trans5;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
IADD3 R6, PT, PT, R4, 0x1f, RZ ?trans1;
IMAD R25, R2, R4, R3 ?trans1;
MOV R17, RZ ?trans1;
MOV R23, R2 ?trans1;
SHF.R.U32.HI R6, RZ, 0x5, R6 ?trans2;
LDC R5, c[0x0][0x390] &wr=0x2 ?trans1;
LEA R25, R0, R25, 0x5 ?trans2;
IADD3 R6, PT, PT, -R6, RZ, RZ ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R24, R2, UR4, 0x7 ?trans2;
LEA R20, R3.reuse, UR4, 0x2 ?trans2;
LEA R22, R3, R24, 0x2 ?WAIT7_END_GROUP;
MOV R4, R5 &req={2} ?trans1;
HFMA2 R33, -RZ, RZ, 0, 0 ?WAIT4_END_GROUP;
ISETP.GE.U32.AND P0, PT, R23, R4, PT ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R27, R4, P0 ?WAIT13_END_GROUP;
@!P0 LDC.64 R18, c[0x0][0x380] &wr=0x1 ?trans2;
@!P0 IMAD.WIDE.U32 R18, R25, 0x4, R18 &req={1} ?WAIT5_END_GROUP;
@!P0 LDG.E R33, desc[UR6][R18.64] &wr=0x2 ?trans1;
IADD3 R6, PT, PT, R6, 0x1, RZ ?trans2;
IADD3 R23, PT, PT, R23, 0x20, RZ ?trans2;
LEA R25, R4, R25, 0x5 ?trans1;
ISETP.NE.AND P0, PT, R6, RZ, PT ?trans1;
STS [R22], R33 &req={2} ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R16, [R20] ?trans4;
LDS.128 R8, [R24] &wr=0x1 ?trans4;
LDS R37, [R20+0x80] &wr=0x2 ?trans4;
LDS R29, [R20+0x100] &wr=0x3 ?trans4;
LDS R30, [R20+0x180] &wr=0x4 ?trans4;
LDS R35, [R20+0x200] ?trans4;
LDS.128 R12, [R24+0x10] &wr=0x5 ?trans4;
LDS R28, [R20+0x280] &wr=0x0 ?trans4;
LDS R31, [R20+0x300] &wr=0x0 ?trans4;
LDS R26, [R20+0x380] &wr=0x0 ?trans4;
LDS R33, [R20+0x400] ?trans1;
FFMA R8, R8, R16, R17 &req={1} ?WAIT3_END_GROUP;
LDS R32, [R20+0x480] ?trans1;
FFMA R8, R37, R9, R8 &req={2} ?WAIT3_END_GROUP;
LDS.128 R16, [R24+0x20] &wr=0x1 ?trans1;
FFMA R29, R29, R10, R8 &req={3} ?WAIT3_END_GROUP;
LDS R37, [R20+0x600] ?trans1;
FFMA R11, R30, R11, R29 &req={4} ?WAIT3_END_GROUP;
LDS R29, [R20+0x500] &wr=0x2 ?trans4;
LDS R30, [R20+0x580] &wr=0x3 ?trans1;
FFMA R11, R12, R35, R11 &req={5} ?WAIT3_END_GROUP;
LDS R35, [R20+0x800] ?trans1;
FFMA R12, R28, R13, R11 &req={0} ?WAIT3_END_GROUP;
LDS.128 R8, [R24+0x30] &wr=0x0 ?trans1;
FFMA R31, R31, R14, R12 ?WAIT3_END_GROUP;
LDS R28, [R20+0x680] &wr=0x4 ?trans1;
FFMA R15, R26, R15, R31 ?WAIT3_END_GROUP;
LDS R31, [R20+0x700] &wr=0x5 ?trans4;
LDS R26, [R20+0x780] &wr=0x5 ?trans1;
FFMA R15, R16, R33, R15 &req={1} ?WAIT3_END_GROUP;
LDS R33, [R20+0x900] ?trans1;
FFMA R32, R32, R17, R15 ?WAIT3_END_GROUP;
LDS.128 R12, [R24+0x40] &wr=0x1 ?trans1;
FFMA R29, R29, R18, R32 &req={2} ?WAIT3_END_GROUP;
LDS R32, [R20+0x880] &wr=0x2 ?trans1;
FFMA R19, R30, R19, R29 &req={3} ?WAIT3_END_GROUP;
LDS R30, [R20+0x980] &wr=0x3 ?trans4;
LDS R29, [R20+0xb00] ?trans1;
FFMA R19, R8, R37, R19 &req={0} ?WAIT3_END_GROUP;
LDS R37, [R20+0xa00] ?trans1;
FFMA R8, R28, R9, R19 &req={4} ?WAIT3_END_GROUP;
LDS.128 R16, [R24+0x50] &wr=0x0 ?trans1;
FFMA R31, R31, R10, R8 &req={5} ?WAIT3_END_GROUP;
LDS R28, [R20+0xa80] &wr=0x4 ?trans1;
FFMA R11, R26, R11, R31 ?WAIT3_END_GROUP;
LDS R26, [R20+0xb80] &wr=0x5 ?trans4;
LDS R31, [R20+0xc00] ?trans1;
FFMA R11, R12, R35, R11 &req={1} ?WAIT4_END_GROUP;
FFMA R32, R32, R13, R11 &req={2} ?trans2;
LDS.128 R8, [R24+0x60] &wr=0x1 ?trans2;
FFMA R33, R33, R14, R32 ?trans2;
LDS R32, [R20+0xc80] &wr=0x2 ?trans2;
FFMA R15, R30, R15, R33 &req={3} ?trans2;
LDS R33, [R20+0xd00] &wr=0x3 ?trans2;
FFMA R15, R16, R37, R15 &req={0} ?WAIT2_END_GROUP;
LDS R16, [R20+0xd80] &wr=0x0 ?trans2;
FFMA R28, R28, R17, R15 &req={4} ?trans2;
LDS R17, [R20+0xe00] ?trans2;
FFMA R35, R29, R18, R28 ?trans2;
LDS.128 R12, [R24+0x70] &wr=0x4 ?trans2;
FFMA R19, R26, R19, R35 &req={5} ?WAIT2_END_GROUP;
LDS R28, [R20+0xe80] &wr=0x5 ?trans4;
LDS R29, [R20+0xf00] &wr=0x5 ?trans4;
LDS R18, [R20+0xf80] &wr=0x5 ?trans1;
FFMA R19, R8, R31, R19 &req={1} ?WAIT4_END_GROUP;
FFMA R32, R32, R9, R19 &req={2} ?WAIT4_END_GROUP;
FFMA R33, R33, R10, R32 &req={3} ?WAIT4_END_GROUP;
FFMA R11, R16, R11, R33 &req={0} ?WAIT4_END_GROUP;
FFMA R11, R12, R17, R11 &req={4} ?WAIT4_END_GROUP;
FFMA R28, R28, R13, R11 &req={5} ?WAIT4_END_GROUP;
FFMA R29, R29, R14, R28 ?WAIT4_END_GROUP;
FFMA R17, R18, R15, R29 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 BRA 0x1c0 ?trans5;
ISETP.GE.AND P0, PT, R21, R4, PT ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LDCU UR4, c[0x0][0x364] &wr=0x1 ?trans1;
LDC.64 R8, c[0x0][0x388] &wr=0x2 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x3 ?trans1;
IMAD R7, R7, UR4, R2 &req={1} ?trans2;
IMAD R0, R0, UR5, R3 &req={3} ?WAIT4_END_GROUP;
IMAD R3, R7, R4, R0 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R2, R3, 0x4, R8 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R17 ?trans1;
EXIT ?trans5;
BRA 0x7e0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: matrixMultiply3(float*, float*, int)
_Z15matrixMultiply3PfS_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v1, s14, 5, v2
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB2_7
v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v4, 2, v2
v_dual_mov_b32 v6, 0 :: v_dual_lshlrev_b32 v5, 7, v0
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_add_i32 s2, s3, 31
s_mov_b32 s9, 0
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v7, v5, v4
s_lshr_b32 s8, s2, 5
.LBB2_2:
v_lshl_add_u32 v8, s9, 5, v0
v_mov_b32_e32 v9, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s3, v8
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s10, s2
s_cbranch_execz .LBB2_4
v_mad_u64_u32 v[9:10], null, v8, s3, v[1:2]
v_mov_b32_e32 v10, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[9:10]
v_add_co_u32 v8, s2, s4, v8
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v9, s2, s5, v9, s2
global_load_b32 v9, v[8:9], off
.LBB2_4:
s_or_b32 exec_lo, exec_lo, s10
v_mov_b32_e32 v8, v4
s_mov_b32 s2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v7, v9
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB2_5:
v_add_nc_u32_e32 v9, s2, v5
s_add_i32 s2, s2, 4
ds_load_b32 v10, v8
ds_load_b32 v9, v9
v_add_nc_u32_e32 v8, 0x80, v8
s_cmpk_eq_i32 s2, 0x80
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v3, v9, v10
s_cbranch_scc0 .LBB2_5
s_add_i32 s9, s9, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s9, s8
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB2_2
s_branch .LBB2_8
.LBB2_7:
v_mov_b32_e32 v3, 0
.LBB2_8:
v_lshl_add_u32 v4, s15, 5, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v1, v4, v1
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB2_10
s_load_b32 s0, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_lshr_b32 s1, s0, 16
s_and_b32 s0, s0, 0xffff
v_mad_u64_u32 v[4:5], null, s15, s1, v[0:1]
s_mul_i32 s14, s14, s0
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v4, s3
v_add3_u32 v0, s14, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB2_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| matrixMultiply3 | 3,124 | 1,433 | stackv2-00000-of-00015 |
// Demangled: gpu_where(float*, float*, float*, float*, long)
Function : _Z9gpu_wherePfS_S_S_l
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x3a0] &wr=0x2 ?trans7;
LDC R2, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R2, R2, UR4, R3 &req={1} ?WAIT2_END_GROUP;
HFMA2 R3, -RZ, RZ, 0, 0 ?WAIT5_END_GROUP;
ISETP.GE.S64.AND P0, PT, R2, UR6, PT &req={2} ?WAIT14_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDCU.64 UR6, c[0x0][0x380] &wr=0x0 ?trans1;
IMAD.SHL.U32 R4, R2, 0x4, RZ ?trans1;
SHF.R.U32.HI R5, RZ, 0x1e, R2 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans4;
IADD.64 R2, R4, UR6 &req={0} ?WAIT7_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans2;
FSETP.NEU.AND P0, PT, R2, RZ, PT &req={2} ?WAIT13_END_GROUP;
@!P0 BRA 0x180 ?trans5;
LDCU.64 UR6, c[0x0][0x388] &wr=0x0 ?trans2;
IADD.64 R2, R4.reuse, UR6 &req={0} ?trans2;
LDCU.64 UR6, c[0x0][0x398] &wr=0x0 ?trans5;
LDG.E R3, desc[UR4][R2.64] &wr=0x2 ?trans1;
IADD.64 R4, R4, UR6 &req={0} ?WAIT6_END_GROUP;
STG.E desc[UR4][R4.64], R3 &req={2} ?trans1;
EXIT ?trans5;
LDCU.128 UR8, c[0x0][0x390] &wr=0x0 ?trans2;
IADD.64 R2, R4, UR8 &req={0} ?WAIT7_END_GROUP;
LDG.E R3, desc[UR4][R2.64] &wr=0x2 ?trans1;
IADD.64 R4, R4, UR10 ?WAIT6_END_GROUP;
STG.E desc[UR4][R4.64], R3 &req={2} ?trans1;
EXIT ?trans5;
BRA 0x1e0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: gpu_where(float*, float*, float*, float*, long)
_Z9gpu_wherePfS_S_S_l:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b256 s[0:7], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_mov_b32_e32 v4, s2
global_load_b32 v2, v[2:3], off
v_mov_b32_e32 v3, s3
s_waitcnt vmcnt(0)
v_cmp_neq_f32_e32 vcc_lo, 0, v2
v_cndmask_b32_e32 v2, s4, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, s5, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, v3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| gpu_where | 798 | 678 | stackv2-00000-of-00015 |
// Demangled: gpu_where_back(float*, float*, float*, float*, long)
Function : _Z14gpu_where_backPfS_S_S_l
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x3a0] &wr=0x2 ?trans7;
LDC R2, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R2, R2, UR4, R3 &req={1} ?WAIT2_END_GROUP;
HFMA2 R3, -RZ, RZ, 0, 0 ?WAIT5_END_GROUP;
ISETP.GE.S64.AND P0, PT, R2, UR6, PT &req={2} ?WAIT14_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDCU.64 UR6, c[0x0][0x380] &wr=0x0 ?trans1;
IMAD.SHL.U32 R4, R2, 0x4, RZ ?trans1;
SHF.R.U32.HI R5, RZ, 0x1e, R2 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans4;
IADD.64 R2, R4, UR6 &req={0} ?WAIT7_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans2;
FSETP.NEU.AND P0, PT, R2, RZ, PT &req={2} ?WAIT13_END_GROUP;
@!P0 BRA 0x1a0 ?trans5;
LDCU.64 UR6, c[0x0][0x398] &wr=0x0 ?trans1;
LDCU.64 UR8, c[0x0][0x388] &wr=0x1 ?trans1;
IADD.64 R2, R4.reuse, UR6 &req={0} ?trans2;
IADD.64 R4, R4, UR8 &req={1} ?WAIT5_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &wr=0x2 ?trans4;
LDG.E R7, desc[UR4][R4.64] &wr=0x2 ?trans2;
FADD R7, R2, R7 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64], R7 ?trans1;
EXIT ?trans5;
LDCU.128 UR8, c[0x0][0x390] &wr=0x0 ?trans2;
IADD.64 R2, R4.reuse, UR10 &req={0} ?trans2;
IADD.64 R4, R4, UR8 ?WAIT5_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &wr=0x2 ?trans4;
LDG.E R7, desc[UR4][R4.64] &wr=0x2 ?trans2;
FADD R7, R2, R7 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64], R7 ?trans1;
EXIT ?trans5;
BRA 0x220;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: gpu_where_back(float*, float*, float*, float*, long)
_Z14gpu_where_backPfS_S_S_l:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_2
s_load_b256 s[0:7], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_mov_b32_e32 v4, s2
global_load_b32 v2, v[2:3], off
v_mov_b32_e32 v3, s3
s_waitcnt vmcnt(0)
v_cmp_neq_f32_e32 vcc_lo, 0, v2
v_cndmask_b32_e32 v4, s4, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v5, s5, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, v4, v0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| gpu_where_back | 894 | 715 | stackv2-00000-of-00015 |
// Demangled: accel_update(float3*, float3*, int, int)
Function : _Z12accel_updateP6float3S0_ii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
LDC R16, c[0x0][0x390] &wr=0x1 ?trans1;
S2R R0, SR_CTAID.X &wr=0x2 ?trans1;
LDCU UR6, c[0x0][0x360] &wr=0x2 ?trans1;
HFMA2 R22, -RZ, RZ, 0, 0 ?trans1;
CS2R R24, SRZ ?trans1;
S2R R23, SR_TID.X &wr=0x2 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x3 ?trans1;
ISETP.GE.AND P0, PT, R16, 0x1, PT &req={1} ?trans1;
IMAD R21, R0, UR6, R23 &req={2} ?WAIT5_END_GROUP;
SHF.R.S32.HI R19, RZ, 0x1f, R21 ?WAIT7_END_GROUP;
@!P0 BRA 0x1860 &req={3,0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans2;
IMAD.WIDE R2, R21, 0xc, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E R17, desc[UR4][R2.64] &rd=0x0 &wr=0x5 ?trans4;
LDG.E R20, desc[UR4][R2.64+0x4] &rd=0x0 &wr=0x5 ?trans4;
LDG.E R18, desc[UR4][R2.64+0x8] &rd=0x0 &wr=0x5 ?trans1;
BSSY B1, 0x1860 ?trans1;
LOP3.LUT R16, R16, 0x3ff, RZ, 0xc0, !PT ?trans1;
CS2R R6, SRZ ?trans1;
MOV R22, RZ ?trans1;
CS2R R24, SRZ ?WAIT7_END_GROUP;
LDC.64 R2, c[0x0][0x390] &req={0} &wr=0x0 ?trans1;
IMAD R0, R6, UR6, R23 ?trans1;
IADD3 R7, PT, PT, R7, UR6, RZ ?WAIT4_END_GROUP;
ISETP.GT.AND P0, PT, R0, R3, PT &req={0} ?trans1;
ISETP.GE.AND P3, PT, R7, R2, PT ?WAIT12_END_GROUP;
@P0 BRA 0x1840 ?trans5;
LDC.64 R4, c[0x0][0x380] &wr=0x0 ?trans2;
IMAD.WIDE R4, R0, 0xc, R4 &req={0} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR4][R4.64] &wr=0x2 ?trans4;
LDG.E R3, desc[UR4][R4.64+0x4] &wr=0x3 ?trans4;
LDG.E R8, desc[UR4][R4.64+0x8] &rd=0x0 &wr=0x4 ?trans1;
IADD3 R6, PT, PT, R6, 0x1, RZ ?trans1;
MOV R9, 0x400 ?trans1;
WARPSYNC.ALL ?trans5;
NOP ?trans1;
S2R R10, SR_CgaCtaId &wr=0x1 ?trans1;
SHF.L.U32 R11, R6, 0xa, RZ ?trans1;
BSSY.RECONVERGENT B0, 0x1830 ?trans4;
ISETP.GT.AND P0, PT, R11, R2, PT ?WAIT5_END_GROUP;
SEL R5, R16, 0x400, P0 &req={0} ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R5, RZ, PT ?trans1;
LEA R10, R10, R9, 0x18 &req={1} ?WAIT5_END_GROUP;
IMAD R9, R23, 0xc, R10 ?WAIT5_END_GROUP;
STS [R9], R0 &req={2} &rd=0x0 ?trans4;
STS [R9+0x4], R3 &req={3} &rd=0x0 ?trans4;
STS [R9+0x8], R8 &req={4} &rd=0x0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 BRA 0x1820 ?trans5;
ISETP.GE.U32.AND P0, PT, R5, 0x4, PT ?trans1;
BSSY.RECONVERGENT B2, 0xec0 ?trans1;
MOV R4, RZ ?WAIT11_END_GROUP;
@!P0 BRA 0xeb0 ?trans5;
LOP3.LUT R2, R5, 0x7fc, RZ, 0xc0, !PT ?trans1;
HFMA2 R4, -RZ, RZ, 0, 0 ?trans1;
IADD3 R3, PT, PT, R10, 0x20, RZ &req={0} ?trans2;
IADD3 R2, PT, PT, -R2, RZ, RZ ?WAIT7_END_GROUP;
LDS.128 R12, [R3+-0x20] &wr=0x0 ?trans1;
BSSY.RECONVERGENT B3, 0x520 ?trans1;
FADD R13, -R20, R13 &req={5,0} ?trans1;
FADD R27, -R17, R12 ?trans1;
FADD R14, -R18, R14 ?trans2;
FMUL R0, R13, R13 ?WAIT4_END_GROUP;
FFMA R9, R27, R27, R0 ?WAIT4_END_GROUP;
FFMA R9, R14, R14, R9 ?WAIT4_END_GROUP;
FADD R9, R9, 1 ?WAIT4_END_GROUP;
FMUL R0, R9, R9 ?WAIT4_END_GROUP;
FMUL R12, R9, R0 ?WAIT4_END_GROUP;
MUFU.RSQ R9, R12 &rd=0x0 &wr=0x1 ?trans1;
IADD3 R0, PT, PT, R12, -0xd000000, RZ ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R0, 0x727fffff, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x4d0 &req={1,0} ?trans5;
MOV R0, 0x4b0 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x1c30 ?trans5;
MOV R0, R32 ?trans1;
BRA 0x510 ?trans6;
FMUL.FTZ R0, R12, R9 ?trans1;
FMUL.FTZ R8, R9, 0.5 ?WAIT3_END_GROUP;
FFMA R9, -R0, R0, R12 ?WAIT4_END_GROUP;
FFMA R0, R9, R8, R0 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B3 ?trans5;
IADD3 R8, PT, PT, R0, 0x1800000, RZ ?trans1;
BSSY.RECONVERGENT B3, 0x5f0 ?trans3;
LOP3.LUT R8, R8, 0x7f800000, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R8, 0x1ffffff, PT ?WAIT13_END_GROUP;
@P0 BRA 0x5a0 ?trans5;
MOV R12, 0x590 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x18e0 ?trans5;
BRA 0x5e0 ?trans5;
MUFU.RCP R9, R0 &wr=0x0 ?trans2;
FFMA R8, R9, R0, -1 &req={0} ?WAIT4_END_GROUP;
FADD.FTZ R8, -R8, -RZ ?WAIT4_END_GROUP;
FFMA R30, R9, R8, R9 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B3 ?trans5;
LDS.128 R8, [R3+-0x10] &wr=0x0 ?trans1;
FADD R26, -R17, R15 ?trans1;
FMUL R27, R27, R30.reuse ?trans1;
FMUL R13, R13, R30.reuse ?trans1;
FMUL R14, R14, R30 ?trans1;
BSSY.RECONVERGENT B3, 0x7e0 ?trans1;
FFMA R22, R27, 10000, R22 ?trans1;
FFMA R24, R13, 10000, R24 ?trans1;
FFMA R25, R14, 10000, R25 ?trans1;
FADD R8, -R20, R8 &req={0} ?trans1;
FADD R9, -R18, R9 ?WAIT3_END_GROUP;
FMUL R15, R8, R8 ?WAIT4_END_GROUP;
FFMA R0, R26, R26, R15 ?WAIT4_END_GROUP;
FFMA R0, R9, R9, R0 ?WAIT4_END_GROUP;
FADD R0, R0, 1 ?WAIT4_END_GROUP;
FMUL R15, R0, R0 ?WAIT4_END_GROUP;
FMUL R15, R0, R15 ?WAIT4_END_GROUP;
MUFU.RSQ R12, R15 &rd=0x0 &wr=0x1 ?trans1;
IADD3 R0, PT, PT, R15, -0xd000000, RZ ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R0, 0x727fffff, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x790 &req={1,0} ?trans5;
MOV R12, R15 ?trans1;
MOV R0, 0x770 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x1c30 ?trans5;
MOV R0, R32 ?trans1;
BRA 0x7d0 ?trans6;
FMUL.FTZ R0, R15, R12 ?trans1;
FMUL.FTZ R12, R12, 0.5 ?WAIT3_END_GROUP;
FFMA R13, -R0, R0, R15 ?WAIT4_END_GROUP;
FFMA R0, R13, R12, R0 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B3 ?trans5;
IADD3 R12, PT, PT, R0, 0x1800000, RZ ?trans1;
BSSY.RECONVERGENT B3, 0x8b0 ?trans3;
LOP3.LUT R12, R12, 0x7f800000, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R12, 0x1ffffff, PT ?WAIT13_END_GROUP;
@P0 BRA 0x860 ?trans5;
MOV R12, 0x850 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x18e0 ?trans5;
BRA 0x8a0 ?trans5;
MUFU.RCP R13, R0 &wr=0x0 ?trans2;
FFMA R12, R13, R0, -1 &req={0} ?WAIT4_END_GROUP;
FADD.FTZ R12, -R12, -RZ ?WAIT4_END_GROUP;
FFMA R30, R13, R12, R13 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B3 ?trans5;
LDS.128 R12, [R3] &wr=0x0 ?trans1;
FADD R11, -R20, R11 ?trans1;
FADD R10, -R17, R10 ?trans1;
FMUL R31, R8, R30 ?trans1;
BSSY.RECONVERGENT B3, 0xa90 ?trans1;
FMUL R29, R11, R11 ?trans2;
FFMA R24, R31, 10000, R24 ?trans2;
FFMA R0, R10, R10, R29 ?trans1;
FADD R27, -R18, R12 &req={0} ?WAIT4_END_GROUP;
FFMA R0, R27, R27, R0 ?WAIT4_END_GROUP;
FADD R0, R0, 1 ?WAIT4_END_GROUP;
FMUL R29, R0, R0 ?WAIT4_END_GROUP;
FMUL R12, R0, R29 ?trans1;
FMUL R29, R26, R30.reuse ?trans1;
FMUL R30, R9, R30 ?trans2;
MUFU.RSQ R33, R12 &rd=0x0 &wr=0x1 ?trans1;
IADD3 R0, PT, PT, R12, -0xd000000, RZ ?trans1;
FFMA R22, R29, 10000, R22 ?trans1;
FFMA R25, R30, 10000, R25 ?WAIT3_END_GROUP;
ISETP.GT.U32.AND P0, PT, R0, 0x727fffff, PT ?WAIT13_END_GROUP;
@!P0 BRA 0xa40 &req={1,0} ?trans5;
MOV R0, 0xa20 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x1c30 ?trans5;
MOV R0, R32 ?trans1;
BRA 0xa80 ?trans6;
FMUL.FTZ R0, R12, R33 ?trans1;
FMUL.FTZ R8, R33, 0.5 ?WAIT3_END_GROUP;
FFMA R9, -R0, R0, R12 ?WAIT4_END_GROUP;
FFMA R0, R9, R8, R0 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B3 ?trans5;
IADD3 R8, PT, PT, R0, 0x1800000, RZ ?trans1;
BSSY.RECONVERGENT B3, 0xb60 ?trans3;
LOP3.LUT R8, R8, 0x7f800000, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R8, 0x1ffffff, PT ?WAIT13_END_GROUP;
@P0 BRA 0xb10 ?trans5;
MOV R12, 0xb00 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x18e0 ?trans5;
BRA 0xb50 ?trans5;
MUFU.RCP R9, R0 &wr=0x0 ?trans2;
FFMA R8, R9, R0, -1 &req={0} ?WAIT4_END_GROUP;
FADD.FTZ R8, -R8, -RZ ?WAIT4_END_GROUP;
FFMA R30, R9, R8, R9 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B3 ?trans5;
FADD R14, -R20, R14 ?trans1;
FADD R13, -R17, R13 ?trans1;
FADD R15, -R18, R15 ?trans1;
FMUL R11, R11, R30 ?trans1;
FMUL R0, R14, R14 ?trans1;
BSSY.RECONVERGENT B3, 0xd30 ?trans2;
FFMA R24, R11, 10000, R24 ?trans1;
FFMA R0, R13, R13, R0 ?WAIT4_END_GROUP;
FFMA R0, R15, R15, R0 ?WAIT4_END_GROUP;
FADD R0, R0, 1 ?WAIT4_END_GROUP;
FMUL R9, R0, R0 ?WAIT4_END_GROUP;
FMUL R12, R0, R9 ?trans1;
FMUL R9, R10, R30.reuse ?trans1;
FMUL R30, R27, R30 ?trans2;
MUFU.RSQ R29, R12 &rd=0x0 &wr=0x1 ?trans1;
IADD3 R0, PT, PT, R12, -0xd000000, RZ ?trans1;
FFMA R22, R9, 10000, R22 ?trans1;
FFMA R25, R30, 10000, R25 ?WAIT3_END_GROUP;
ISETP.GT.U32.AND P0, PT, R0, 0x727fffff, PT ?WAIT13_END_GROUP;
@!P0 BRA 0xce0 &req={1,0} ?trans5;
MOV R0, 0xcc0 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x1c30 ?trans5;
MOV R0, R32 ?trans1;
BRA 0xd20 ?trans6;
FMUL.FTZ R0, R12, R29 ?trans1;
FMUL.FTZ R8, R29, 0.5 ?WAIT3_END_GROUP;
FFMA R9, -R0, R0, R12 ?WAIT4_END_GROUP;
FFMA R0, R9, R8, R0 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B3 ?trans5;
IADD3 R8, PT, PT, R0, 0x1800000, RZ ?trans1;
BSSY.RECONVERGENT B3, 0xe00 ?trans3;
LOP3.LUT R8, R8, 0x7f800000, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R8, 0x1ffffff, PT ?WAIT13_END_GROUP;
@P0 BRA 0xdb0 ?trans5;
MOV R12, 0xda0 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x18e0 ?trans5;
BRA 0xdf0 ?trans5;
MUFU.RCP R9, R0 &wr=0x0 ?trans2;
FFMA R8, R9, R0, -1 &req={0} ?WAIT4_END_GROUP;
FADD.FTZ R8, -R8, -RZ ?WAIT4_END_GROUP;
FFMA R30, R9, R8, R9 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B3 ?trans5;
IADD3 R2, PT, PT, R2, 0x4, RZ ?trans1;
FMUL R13, R13, R30.reuse ?trans1;
FMUL R9, R14, R30.reuse ?trans1;
FMUL R30, R15, R30 ?trans1;
IADD3 R4, PT, PT, R4, 0x4, RZ ?trans1;
ISETP.NE.AND P0, PT, R2, RZ, PT ?trans1;
FFMA R22, R13, 10000, R22 ?trans1;
FFMA R24, R9, 10000, R24 ?trans1;
FFMA R25, R30, 10000, R25 ?trans1;
IADD3 R3, PT, PT, R3, 0x30, RZ ?WAIT9_END_GROUP;
@P0 BRA 0x3a0 ?trans5;
BSYNC.RECONVERGENT B2 ?trans5;
LOP3.LUT P0, R0, R5, 0x3, RZ, 0xc0, !PT &req={0} ?WAIT13_END_GROUP;
@!P0 BRA 0x1820 ?trans5;
ISETP.NE.AND P0, PT, R0, 0x1, PT ?trans1;
BSSY.RECONVERGENT B2, 0x14f0 ?WAIT12_END_GROUP;
@!P0 BRA 0x14e0 ?trans5;
S2R R3, SR_CgaCtaId &wr=0x0 ?trans1;
MOV R0, 0x400 ?trans1;
BSSY.RECONVERGENT B3, 0x10e0 ?trans4;
LEA R3, R3, R0, 0x18 &req={0} ?WAIT5_END_GROUP;
IMAD R13, R4, 0xc, R3 ?WAIT5_END_GROUP;
LDS.64 R2, [R13] &wr=0x0 ?trans4;
LDS R9, [R13+0x8] &wr=0x1 ?trans1;
FADD R3, -R20, R3 &req={5,0} ?trans1;
FADD R8, -R17, R2 ?WAIT3_END_GROUP;
FMUL R11, R3, R3 ?trans1;
FADD R2, -R18, R9 &req={1} ?WAIT3_END_GROUP;
FFMA R11, R8, R8, R11 ?WAIT4_END_GROUP;
FFMA R11, R2, R2, R11 ?WAIT4_END_GROUP;
FADD R11, R11, 1 ?WAIT4_END_GROUP;
FMUL R0, R11, R11 ?WAIT4_END_GROUP;
FMUL R12, R11, R0 ?WAIT4_END_GROUP;
MUFU.RSQ R9, R12 &rd=0x0 &wr=0x1 ?trans1;
IADD3 R0, PT, PT, R12, -0xd000000, RZ ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R0, 0x727fffff, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x1090 &req={1,0} ?trans5;
MOV R0, 0x1070 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x1c30 ?trans5;
MOV R0, R32 ?trans1;
BRA 0x10d0 ?trans6;
FMUL.FTZ R0, R12, R9 ?trans1;
FMUL.FTZ R10, R9, 0.5 ?WAIT3_END_GROUP;
FFMA R9, -R0, R0, R12 ?WAIT4_END_GROUP;
FFMA R0, R9, R10, R0 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B3 ?trans5;
IADD3 R9, PT, PT, R0, 0x1800000, RZ ?trans1;
BSSY.RECONVERGENT B3, 0x11b0 ?trans3;
LOP3.LUT R9, R9, 0x7f800000, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R9, 0x1ffffff, PT ?WAIT13_END_GROUP;
@P0 BRA 0x1160 ?trans5;
MOV R12, 0x1150 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x18e0 ?trans5;
BRA 0x11a0 ?trans5;
MUFU.RCP R9, R0 &wr=0x0 ?trans2;
FFMA R10, R9, R0, -1 &req={0} ?WAIT4_END_GROUP;
FADD.FTZ R10, -R10, -RZ ?WAIT4_END_GROUP;
FFMA R30, R9, R10, R9 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B3 ?trans5;
LDS.64 R10, [R13+0x10] &wr=0x0 ?trans1;
FMUL R3, R3, R30.reuse ?trans1;
FMUL R2, R2, R30.reuse ?trans1;
BSSY.RECONVERGENT B3, 0x13a0 ?trans1;
LDS R0, [R13+0xc] &rd=0x1 &wr=0x2 ?trans1;
FFMA R24, R3, 10000, R24 ?trans1;
FFMA R25, R2, 10000, R25 ?trans1;
FMUL R13, R8, R30 &req={1} ?WAIT4_END_GROUP;
FFMA R22, R13, 10000, R22 ?trans1;
FADD R10, -R20, R10 &req={0} ?trans1;
FADD R11, -R18, R11 ?trans1;
FADD R9, -R17, R0 &req={2} ?trans2;
FMUL R0, R10, R10 ?WAIT4_END_GROUP;
FFMA R0, R9, R9, R0 ?WAIT4_END_GROUP;
FFMA R0, R11, R11, R0 ?WAIT4_END_GROUP;
FADD R0, R0, 1 ?WAIT4_END_GROUP;
FMUL R15, R0, R0 ?WAIT4_END_GROUP;
FMUL R12, R0, R15 ?WAIT4_END_GROUP;
MUFU.RSQ R15, R12 &rd=0x0 &wr=0x1 ?trans1;
IADD3 R0, PT, PT, R12, -0xd000000, RZ ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R0, 0x727fffff, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x1350 &req={1,0} ?trans5;
MOV R0, 0x1330 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x1c30 ?trans5;
MOV R0, R32 ?trans1;
BRA 0x1390 ?trans6;
FMUL.FTZ R0, R12, R15 ?trans1;
FMUL.FTZ R2, R15, 0.5 ?WAIT3_END_GROUP;
FFMA R3, -R0, R0, R12 ?WAIT4_END_GROUP;
FFMA R0, R3, R2, R0 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B3 ?trans5;
IADD3 R2, PT, PT, R0, 0x1800000, RZ ?trans1;
BSSY.RECONVERGENT B3, 0x1470 ?trans3;
LOP3.LUT R2, R2, 0x7f800000, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R2, 0x1ffffff, PT ?WAIT13_END_GROUP;
@P0 BRA 0x1420 ?trans5;
MOV R12, 0x1410 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x18e0 ?trans5;
BRA 0x1460 ?trans5;
MUFU.RCP R3, R0 &wr=0x0 ?trans2;
FFMA R2, R3, R0, -1 &req={0} ?WAIT4_END_GROUP;
FADD.FTZ R2, -R2, -RZ ?WAIT4_END_GROUP;
FFMA R30, R3, R2, R3 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B3 ?trans5;
FMUL R9, R9, R30.reuse ?trans1;
FMUL R3, R10, R30.reuse ?trans1;
FMUL R30, R11, R30 ?trans1;
IADD3 R4, PT, PT, R4, 0x2, RZ ?trans1;
FFMA R22, R9, 10000, R22 ?trans1;
FFMA R24, R3, 10000, R24 ?trans1;
FFMA R25, R30, 10000, R25 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
LOP3.LUT R5, R5, 0x1, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.U32.AND P0, PT, R5, 0x1, PT ?WAIT13_END_GROUP;
@P0 BRA 0x1820 ?trans5;
S2R R3, SR_CgaCtaId &wr=0x0 ?trans1;
MOV R0, 0x400 ?trans1;
BSSY.RECONVERGENT B2, 0x16f0 ?trans4;
LEA R3, R3, R0, 0x18 &req={0} ?WAIT5_END_GROUP;
IMAD R0, R4, 0xc, R3 ?WAIT5_END_GROUP;
LDS.64 R2, [R0] &wr=0x0 ?trans4;
LDS R5, [R0+0x8] &wr=0x1 ?trans1;
FADD R3, -R20, R3 &req={5,0} ?trans1;
FADD R4, -R17, R2 ?WAIT3_END_GROUP;
FMUL R9, R3, R3 ?trans1;
FADD R2, -R18, R5 &req={1} ?WAIT3_END_GROUP;
FFMA R9, R4, R4, R9 ?WAIT4_END_GROUP;
FFMA R9, R2, R2, R9 ?WAIT4_END_GROUP;
FADD R9, R9, 1 ?WAIT4_END_GROUP;
FMUL R8, R9, R9 ?WAIT4_END_GROUP;
FMUL R12, R9, R8 ?WAIT4_END_GROUP;
MUFU.RSQ R9, R12 &rd=0x0 &wr=0x1 ?trans1;
IADD3 R5, PT, PT, R12, -0xd000000, RZ ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R5, 0x727fffff, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x16a0 &req={1,0} ?trans5;
MOV R0, 0x1680 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x1c30 ?trans5;
MOV R0, R32 ?trans1;
BRA 0x16e0 ?trans6;
FMUL.FTZ R0, R12, R9 ?trans1;
FMUL.FTZ R8, R9, 0.5 ?WAIT3_END_GROUP;
FFMA R5, -R0, R0, R12 ?WAIT4_END_GROUP;
FFMA R0, R5, R8, R0 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
IADD3 R5, PT, PT, R0, 0x1800000, RZ ?trans1;
BSSY.RECONVERGENT B2, 0x17c0 ?trans3;
LOP3.LUT R5, R5, 0x7f800000, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R5, 0x1ffffff, PT ?WAIT13_END_GROUP;
@P0 BRA 0x1770 ?trans5;
MOV R12, 0x1760 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x18e0 ?trans5;
BRA 0x17b0 ?trans5;
MUFU.RCP R5, R0 &wr=0x0 ?trans2;
FFMA R8, R5, R0, -1 &req={0} ?WAIT4_END_GROUP;
FADD.FTZ R8, -R8, -RZ ?WAIT4_END_GROUP;
FFMA R30, R5, R8, R5 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
FMUL R5, R4, R30.reuse ?trans1;
FMUL R3, R3, R30.reuse ?trans1;
FMUL R2, R2, R30 ?trans2;
FFMA R22, R5, 10000, R22 ?trans1;
FFMA R24, R3, 10000, R24 ?trans1;
FFMA R25, R2, 10000, R25 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P3 BRA 0x160 ?trans5;
BSYNC B1 ?trans5;
LDC.64 R2, c[0x0][0x388] &req={0} &wr=0x0 ?trans1;
IMAD R19, R19, 0xc, RZ ?trans2;
IMAD.WIDE.U32 R2, R21, 0xc, R2 &req={0} ?WAIT5_END_GROUP;
IADD3 R3, PT, PT, R3, R19, RZ ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R22 ?trans4;
STG.E desc[UR4][R2.64+0x4], R24 ?trans4;
STG.E desc[UR4][R2.64+0x8], R25 ?trans1;
EXIT ?trans5;
SHF.L.U32 R29, R0, 0x1, RZ ?trans1;
BSSY.RECONVERGENT B4, 0x1c00 ?trans3;
SHF.R.U32.HI R29, RZ, 0x18, R29 ?WAIT5_END_GROUP;
ISETP.NE.U32.AND P0, PT, R29, RZ, PT ?WAIT13_END_GROUP;
@P0 BRA 0x19d0 ?trans5;
SHF.L.U32 R28, R0, 0x1, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R28, RZ, PT ?WAIT13_END_GROUP;
@P0 FFMA R29, R0, 1.84467440737095516160e+19, RZ ?trans1;
@!P0 MUFU.RCP R30, R0 ?trans3;
@P0 MUFU.RCP R28, R29 &wr=0x0 ?trans2;
@P0 FFMA R31, R29, R28, -1 &req={0} ?WAIT4_END_GROUP;
@P0 FADD.FTZ R31, -R31, -RZ ?WAIT4_END_GROUP;
@P0 FFMA R31, R28, R31, R28 ?WAIT4_END_GROUP;
@P0 FFMA R30, R31, 1.84467440737095516160e+19, RZ ?trans1;
BRA 0x1bf0 ?trans6;
IADD3 R31, PT, PT, R29, -0xfd, RZ ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R31, 0x1, PT ?WAIT13_END_GROUP;
@P0 BRA 0x1be0 ?trans5;
LOP3.LUT R32, R0, 0x7fffff, RZ, 0xc0, !PT ?trans1;
HFMA2 R30, -RZ, RZ, 0, 1.78813934326171875e-07 ?trans1;
IADD3 R29, PT, PT, R29, -0xfc, RZ ?trans2;
LOP3.LUT R32, R32, 0x3f800000, RZ, 0xfc, !PT ?WAIT4_END_GROUP;
MUFU.RCP R35, R32 &wr=0x0 ?trans2;
FFMA R28, R32, R35, -1 &req={0} ?WAIT4_END_GROUP;
FADD.FTZ R28, -R28, -RZ ?WAIT4_END_GROUP;
FFMA.RM R33, R35.reuse, R28.reuse, R35.reuse ?trans1;
FFMA.RP R28, R35, R28, R35 ?WAIT5_END_GROUP;
FSETP.NEU.FTZ.AND P0, PT, R33.reuse, R28, PT ?trans1;
LOP3.LUT R28, R33, 0x7fffff, RZ, 0xc0, !PT ?trans2;
SHF.L.U32 R33, R30, R31, RZ ?trans2;
LOP3.LUT R28, R28, 0x800000, RZ, 0xfc, !PT ?trans1;
SEL R30, RZ, 0xffffffff, !P0 ?WAIT3_END_GROUP;
LOP3.LUT R32, R33, R28, RZ, 0xc0, !PT ?trans2;
SHF.R.U32.HI R29, RZ, R29, R28 ?trans2;
IADD3 R30, PT, PT, -R30, RZ, RZ ?trans2;
SHF.R.U32.HI R32, RZ, R31.reuse, R32 ?trans2;
LOP3.LUT P1, RZ, R30, R31, R28, 0xf8, !PT ?trans2;
LOP3.LUT P0, RZ, R32, 0x1, RZ, 0xc0, !PT ?WAIT2_END_GROUP;
LOP3.LUT P2, RZ, R32, 0x2, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ?trans2;
LOP3.LUT P1, RZ, R0, 0x7fffff, RZ, 0xc0, !PT ?WAIT3_END_GROUP;
SEL R30, RZ, 0x1, !P0 ?WAIT5_END_GROUP;
IADD3 R30, PT, PT, -R30, RZ, RZ ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R30, RZ, PT ?WAIT13_END_GROUP;
@!P0 IADD3 R29, PT, PT, R29, 0x1, RZ ?WAIT4_END_GROUP;
@!P1 SHF.L.U32 R29, R29, 0x1, RZ ?WAIT4_END_GROUP;
LOP3.LUT R30, R29, 0x80000000, R0, 0xf8, !PT ?trans1;
BRA 0x1bf0 ?trans6;
MUFU.RCP R30, R0 &rd=0x0 &wr=0x1 ?trans2;
BSYNC.RECONVERGENT B4 ?trans5;
MOV R28, R12 ?trans1;
HFMA2 R29, -RZ, RZ, 0, 0 ?WAIT4_END_GROUP;
RET.REL.NODEC R28 0x0 &req={1,0} ?trans5;
LOP3.LUT P0, RZ, R12, 0x7fffffff, RZ, 0xc0, !PT ?WAIT13_END_GROUP;
@!P0 MOV R32, R12 ?trans1;
@!P0 BRA 0x1d60 ?trans6;
FSETP.GEU.FTZ.AND P0, PT, R12, RZ, PT ?WAIT13_END_GROUP;
@!P0 MOV R32, 0x7fffffff ?trans1;
@!P0 BRA 0x1d60 ?trans6;
FSETP.GTU.FTZ.AND P0, PT, |R12|, +INF , PT ?WAIT13_END_GROUP;
@P0 FADD.FTZ R32, R12, 1 ?trans1;
@P0 BRA 0x1d60 ?trans6;
FSETP.NEU.FTZ.AND P0, PT, |R12|, +INF , PT ?WAIT13_END_GROUP;
@P0 FFMA R31, R12, 1.84467440737095516160e+19, RZ ?trans1;
@!P0 MOV R32, R12 ?WAIT3_END_GROUP;
@P0 MUFU.RSQ R28, R31 &wr=0x0 ?trans2;
@P0 FMUL.FTZ R30, R31, R28 &req={0} ?trans1;
@P0 FMUL.FTZ R28, R28, 0.5 ?WAIT3_END_GROUP;
@P0 FADD.FTZ R29, -R30, -RZ ?WAIT4_END_GROUP;
@P0 FFMA R29, R30, R29, R31 ?WAIT4_END_GROUP;
@P0 FFMA R28, R29, R28, R30 ?WAIT4_END_GROUP;
@P0 FMUL.FTZ R32, R28, 2.3283064365386962891e-10 ?WAIT7_END_GROUP;
MOV R28, R0 ?trans1;
HFMA2 R29, -RZ, RZ, 0, 0 ?WAIT4_END_GROUP;
RET.REL.NODEC R28 0x0 ?trans5;
BRA 0x1d90;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: accel_update(HIP_vector_type<float, 3u>*, HIP_vector_type<float, 3u>*, int, int)
_Z12accel_updateP15HIP_vector_typeIfLj3EES1_ii:
s_clause 0x2
s_load_b32 s8, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s8, 0xffff
s_cmp_lt_i32 s2, 1
v_mad_u64_u32 v[7:8], null, s15, s1, v[0:1]
v_mov_b32_e32 v1, 0
s_cbranch_scc1 .LBB0_9
s_delay_alu instid0(VALU_DEP_2)
v_mad_i64_i32 v[1:2], null, v7, 12, s[4:5]
v_mad_u32_u24 v10, v0, 12, 0
v_mov_b32_e32 v11, 0
v_mov_b32_e32 v3, 0
s_and_b32 s8, s2, 0x3ff
s_mov_b32 s9, 0
global_load_b96 v[4:6], v[1:2], off
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, 0
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[8:9], null, v11, s1, v[0:1]
s_mov_b32 s10, exec_lo
v_cmpx_ge_i32_e64 s3, v8
s_cbranch_execz .LBB0_8
v_mad_i64_i32 v[12:13], null, v8, 12, s[4:5]
v_lshl_add_u32 v8, v11, 10, 0x400
v_mov_b32_e32 v9, s8
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_cmp_lt_i32_e32 vcc_lo, s2, v8
global_load_b96 v[12:14], v[12:13], off
s_waitcnt vmcnt(0)
ds_store_2addr_b32 v10, v12, v13 offset1:1
ds_store_b32 v10, v14 offset:8
v_cndmask_b32_e32 v8, 0x400, v9, vcc_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_ne_u32_e32 0, v8
s_cbranch_execz .LBB0_7
s_mov_b32 s13, 0
s_mov_b32 s12, 0
.LBB0_5:
v_mov_b32_e32 v9, s13
s_add_i32 s13, s13, 12
ds_load_2addr_b32 v[12:13], v9 offset1:1
ds_load_b32 v9, v9 offset:8
v_add_nc_u32_e32 v8, -1, v8
s_waitcnt lgkmcnt(1)
v_dual_sub_f32 v12, v12, v4 :: v_dual_sub_f32 v13, v13, v5
s_waitcnt lgkmcnt(0)
v_sub_f32_e32 v9, v9, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v14, v13, v13
v_fmac_f32_e32 v14, v12, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v14, v9, v9
v_add_f32_e32 v14, 1.0, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v15, v14, v14
v_mul_f32_e32 v14, v14, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v15, 0x4f800000, v14
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v14
v_cndmask_b32_e32 v14, v14, v15, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v15, v14
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v16, -1, v15
v_add_nc_u32_e32 v17, 1, v15
v_fma_f32 v18, -v16, v15, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v19, -v17, v15, v14
v_cmp_ge_f32_e64 s0, 0, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v15, v15, v16, s0
v_cmp_lt_f32_e64 s0, 0, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v15, v15, v17, s0
v_mul_f32_e32 v16, 0x37800000, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v15, v15, v16, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v14, 0x260
v_cndmask_b32_e32 v14, v15, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v15, null, v14, v14, 1.0
v_div_scale_f32 v18, vcc_lo, 1.0, v14, 1.0
v_rcp_f32_e32 v16, v15
s_waitcnt_depctr 0xfff
v_fma_f32 v17, -v15, v16, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v16, v17, v16
v_mul_f32_e32 v17, v18, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v19, -v15, v17, v18
v_fmac_f32_e32 v17, v19, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v15, -v15, v17, v18
v_div_fmas_f32 v15, v15, v16, v17
v_cmp_eq_u32_e32 vcc_lo, 0, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fixup_f32 v14, v15, v14, 1.0
s_or_b32 s12, vcc_lo, s12
v_mul_f32_e32 v13, v13, v14
v_mul_f32_e32 v9, v9, v14
v_mul_f32_e32 v12, v12, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v2, 0x461c4000, v13
v_fmac_f32_e32 v3, 0x461c4000, v9
s_delay_alu instid0(VALU_DEP_3)
v_fmac_f32_e32 v1, 0x461c4000, v12
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execnz .LBB0_5
s_or_b32 exec_lo, exec_lo, s12
.LBB0_7:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s11
v_add_nc_u32_e32 v11, 1, v11
s_barrier
buffer_gl0_inv
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s10
s_add_i32 s9, s9, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s9, s2
s_cbranch_scc1 .LBB0_2
.LBB0_9:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2)
v_mad_i64_i32 v[4:5], null, v7, 12, s[6:7]
global_store_b96 v[4:5], v[1:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| accel_update | 10,466 | 2,689 | stackv2-00000-of-00015 |
// Demangled: pos_update(float3*, float3*, float3*, float, int)
Function : _Z10pos_updateP6float3S0_S0_fi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R9, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x39c] &wr=0x2 ?trans1;
IMAD R9, R9, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R9, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x388] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
LDCU UR6, c[0x0][0x398] &wr=0x2 ?trans6;
LDC.64 R4, c[0x0][0x380] &wr=0x3 ?trans1;
IMAD.WIDE R2, R9, 0xc, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans1;
IMAD.WIDE R4, R9, 0xc, R4 &req={3} ?WAIT5_END_GROUP;
LDG.E R7, desc[UR4][R4.64] &wr=0x2 ?trans4;
LDG.E R15, desc[UR4][R4.64+0x8] &wr=0x3 ?trans1;
FFMA R11, R0, UR6, R7 &req={2} ?WAIT3_END_GROUP;
LDG.E R7, desc[UR4][R4.64+0x4] &wr=0x2 ?trans4;
STG.E desc[UR4][R4.64], R11 &rd=0x0 ?trans4;
LDG.E R0, desc[UR4][R2.64+0x4] &wr=0x2 ?trans2;
FFMA R13, R0, UR6, R7 &req={2} ?WAIT2_END_GROUP;
LDC.64 R6, c[0x0][0x390] &wr=0x1 ?trans3;
STG.E desc[UR4][R4.64+0x4], R13 &rd=0x2 ?trans4;
LDG.E R0, desc[UR4][R2.64+0x8] &wr=0x3 ?trans1;
IMAD.WIDE R6, R9, 0xc, R6 &req={1} ?WAIT4_END_GROUP;
FFMA R15, R0, UR6, R15 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64+0x8], R15 ?trans4;
LDG.E R9, desc[UR4][R2.64] &wr=0x3 ?trans4;
LDG.E R0, desc[UR4][R6.64] &wr=0x3 ?trans4;
LDG.E R11, desc[UR4][R2.64+0x4] &req={0} &wr=0x4 ?trans4;
LDG.E R13, desc[UR4][R2.64+0x8] &req={2} &wr=0x2 ?trans1;
FFMA R9, R0, UR6, R9 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R9 ?trans4;
LDG.E R0, desc[UR4][R6.64+0x4] &wr=0x4 ?trans2;
FFMA R11, R0, UR6, R11 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64+0x4], R11 ?trans4;
LDG.E R0, desc[UR4][R6.64+0x8] &wr=0x2 ?trans2;
FFMA R13, R0, UR6, R13 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64+0x8], R13 ?trans1;
EXIT ?trans5;
BRA 0x290;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: pos_update(HIP_vector_type<float, 3u>*, HIP_vector_type<float, 3u>*, HIP_vector_type<float, 3u>*, float, int)
_Z10pos_updateP15HIP_vector_typeIfLj3EES1_S1_fi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_i64_i32 v[3:4], null, v1, 12, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s0, v3
global_load_b32 v9, v[5:6], off
global_load_b96 v[0:2], v[7:8], off
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_waitcnt vmcnt(0)
v_fma_f32 v0, s2, v9, v0
global_store_b32 v[7:8], v0, off
global_load_b32 v0, v[5:6], off offset:4
s_waitcnt vmcnt(0)
v_fma_f32 v0, s2, v0, v1
global_store_b32 v[7:8], v0, off offset:4
global_load_b32 v0, v[5:6], off offset:8
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v2, s2, v0
global_store_b32 v[7:8], v2, off offset:8
global_load_b32 v7, v[3:4], off
global_load_b96 v[0:2], v[5:6], off
s_waitcnt vmcnt(0)
v_fma_f32 v0, s2, v7, v0
global_store_b32 v[5:6], v0, off
global_load_b32 v0, v[3:4], off offset:4
s_waitcnt vmcnt(0)
v_fma_f32 v0, s2, v0, v1
global_store_b32 v[5:6], v0, off offset:4
global_load_b32 v0, v[3:4], off offset:8
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v2, s2, v0
global_store_b32 v[5:6], v2, off offset:8
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| pos_update | 1,184 | 899 | stackv2-00000-of-00015 |
// Demangled: sumMatrixRowsKernel(int, double*, double*)
Function : _Z19sumMatrixRowsKerneliPdS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
LDC R0, c[0x0][0x380] &wr=0x1 ?trans1;
S2R R3, SR_TID.X &wr=0x2 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x3 ?trans1;
MOV.64 R34, RZ ?WAIT2_END_GROUP;
ISETP.GE.AND P0, PT, R0, 0x1, PT &req={1} ?WAIT13_END_GROUP;
@!P0 BRA 0xd30 &req={3,2,0} ?trans5;
ISETP.GE.U32.AND P1, PT, R0.reuse, 0x10, PT ?trans1;
LOP3.LUT R36, R0, 0xf, RZ, 0xc0, !PT ?trans1;
UMOV UR4, URZ ?trans1;
MOV.64 R34, RZ ?trans2;
IMAD R4, R3, R0, RZ ?trans1;
ISETP.NE.AND P0, PT, R36, RZ, PT ?WAIT7_END_GROUP;
@!P1 BRA 0x760 ?trans6;
LDC.64 R6, c[0x0][0x388] &wr=0x0 ?trans1;
LOP3.LUT R5, R0, 0x7ffffff0, RZ, 0xc0, !PT ?trans1;
MOV.64 R34, RZ ?trans2;
MOV R2, R4 ?trans1;
UMOV UR4, URZ ?trans1;
IADD3 R5, PT, PT, -R5, RZ, RZ ?trans1;
IADD.64 R6, R6, 0x40 &req={0} ?WAIT8_END_GROUP;
IMAD.WIDE R32, R2, 0x8, R6 ?WAIT5_END_GROUP;
LDG.E.64 R8, desc[UR6][R32.64+-0x40] &wr=0x2 ?trans4;
LDG.E.64 R10, desc[UR6][R32.64+-0x38] &wr=0x3 ?trans4;
LDG.E.64 R12, desc[UR6][R32.64+-0x30] &wr=0x4 ?trans4;
LDG.E.64 R28, desc[UR6][R32.64+-0x28] &wr=0x5 ?trans4;
LDG.E.64 R30, desc[UR6][R32.64+-0x20] &wr=0x3 ?trans4;
LDG.E.64 R26, desc[UR6][R32.64+-0x18] &wr=0x3 ?trans4;
LDG.E.64 R24, desc[UR6][R32.64+-0x10] &wr=0x3 ?trans4;
LDG.E.64 R22, desc[UR6][R32.64+-0x8] &wr=0x3 ?trans4;
LDG.E.64 R20, desc[UR6][R32.64] &wr=0x3 ?trans4;
LDG.E.64 R18, desc[UR6][R32.64+0x8] &wr=0x3 ?trans4;
LDG.E.64 R16, desc[UR6][R32.64+0x10] &wr=0x3 ?trans4;
LDG.E.64 R14, desc[UR6][R32.64+0x18] &wr=0x3 ?trans1;
DADD R8, R8, R34 &req={2} &rd=0x0 &wr=0x3 ?trans3;
LDG.E.64 R34, desc[UR6][R32.64+0x38] &req={0} &wr=0x2 ?WAIT15_END_GROUP;
NOP ?trans1;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R8, R8, R10 &req={3} &rd=0x0 &wr=0x4 ?trans2;
LDG.E.64 R10, desc[UR6][R32.64+0x28] &req={0} &wr=0x3 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R8, R8, R12 &req={4} &rd=0x0 &wr=0x5 ?trans2;
LDG.E.64 R12, desc[UR6][R32.64+0x20] &req={0} &wr=0x4 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R28, R8, R28 &req={5} &rd=0x0 &wr=0x1 ?trans2;
LDG.E.64 R8, desc[UR6][R32.64+0x30] &req={0} &wr=0x5 ?trans1;
IADD3 R5, PT, PT, R5, 0x10, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R5, RZ, PT ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x10, URZ ?trans1;
IADD3 R2, PT, PT, R2, 0x10, RZ ?WAIT15_END_GROUP;
NOP ?WAIT9_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R28, R28, R30 &req={1} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R26, R28, R26 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R24, R26, R24 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R22, R24, R22 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R20, R22, R20 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R18, R20, R18 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R16, R18, R16 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R14, R16, R14 &req={0} &wr=0x4 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R12, R14, R12 &req={4} &wr=0x3 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R10, R12, R10 &req={3} &wr=0x5 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R8, R10, R8 &req={5} &wr=0x2 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R34, R8, R34 &req={2} &rd=0x0 &wr=0x1 ?trans2;
@P1 BRA 0x150 &req={1,0} ?trans5;
@!P0 BRA 0xd30 ?trans5;
ISETP.GE.U32.AND P0, PT, R36, 0x8, PT ?trans1;
LOP3.LUT R2, R0, 0x7, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R2, RZ, PT ?WAIT7_END_GROUP;
@!P0 BRA 0xab0 ?trans6;
LDC.64 R12, c[0x0][0x388] &wr=0x0 ?trans1;
IADD3 R5, PT, PT, R4, UR4, RZ ?WAIT5_END_GROUP;
IMAD.WIDE R12, R5, 0x8, R12 &req={0} ?WAIT5_END_GROUP;
LDG.E.64 R14, desc[UR6][R12.64] &wr=0x2 ?trans4;
LDG.E.64 R16, desc[UR6][R12.64+0x8] &wr=0x3 ?trans4;
LDG.E.64 R18, desc[UR6][R12.64+0x10] &wr=0x4 ?trans4;
LDG.E.64 R20, desc[UR6][R12.64+0x18] &wr=0x5 ?trans4;
LDG.E.64 R22, desc[UR6][R12.64+0x20] &wr=0x3 ?trans4;
LDG.E.64 R8, desc[UR6][R12.64+0x28] &wr=0x3 ?trans4;
LDG.E.64 R6, desc[UR6][R12.64+0x30] &wr=0x3 ?trans4;
LDG.E.64 R10, desc[UR6][R12.64+0x38] &wr=0x3 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x8, URZ ?trans1;
DADD R14, R34, R14 &req={2} &wr=0x3 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R14, R14, R16 &req={3} &wr=0x4 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R14, R14, R18 &req={4} &wr=0x5 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R14, R14, R20 &req={5} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R14, R14, R22 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R8, R14, R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R6, R8, R6 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R34, R6, R10 &req={0} &rd=0x0 &wr=0x1 ?trans2;
@!P1 BRA 0xd30 ?trans5;
ISETP.GE.U32.AND P0, PT, R2, 0x4, PT ?trans1;
LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R0, RZ, PT ?WAIT7_END_GROUP;
@!P0 BRA 0xc80 ?trans6;
LDC.64 R6, c[0x0][0x388] &req={0} &wr=0x0 ?trans1;
IADD3 R5, PT, PT, R4, UR4, RZ ?WAIT5_END_GROUP;
IMAD.WIDE R6, R5, 0x8, R6 &req={0} ?WAIT5_END_GROUP;
LDG.E.64 R8, desc[UR6][R6.64] &wr=0x2 ?trans4;
LDG.E.64 R10, desc[UR6][R6.64+0x8] &wr=0x3 ?trans4;
LDG.E.64 R12, desc[UR6][R6.64+0x10] &wr=0x4 ?trans4;
LDG.E.64 R14, desc[UR6][R6.64+0x18] &wr=0x5 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x4, URZ ?trans1;
DADD R8, R34, R8 &req={2,1} &wr=0x3 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R8, R8, R10 &req={3} &wr=0x4 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R8, R8, R12 &req={4} &wr=0x5 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R34, R8, R14 &req={5} &rd=0x2 &wr=0x3 ?trans2;
@!P1 BRA 0xd30 ?trans5;
LDC.64 R6, c[0x0][0x388] &req={0} &wr=0x0 ?trans1;
IADD3 R9, PT, PT, R4, UR4, RZ &req={2} ?trans2;
IADD3 R0, PT, PT, -R0, RZ, RZ ?WAIT7_END_GROUP;
IMAD.WIDE R4, R9, 0x8, R6 &req={0} ?WAIT6_END_GROUP;
LDG.E.64 R4, desc[UR6][R4.64] &wr=0x2 ?trans1;
IADD3 R0, PT, PT, R0, 0x1, RZ ?trans2;
IADD3 R9, PT, PT, R9, 0x1, RZ ?WAIT3_END_GROUP;
ISETP.NE.AND P0, PT, R0, RZ, PT ?trans1;
DADD R34, R4, R34 &req={3,2,1} &rd=0x4 &wr=0x0 ?WAIT12_END_GROUP;
@P0 BRA 0xcc0 &req={4,0} ?trans5;
LDC.64 R4, c[0x0][0x390] &wr=0x4 ?trans2;
IMAD.WIDE.U32 R2, R3, 0x8, R4 &req={4} ?WAIT5_END_GROUP;
STG.E.64 desc[UR6][R2.64], R34 &req={3,1} ?trans1;
EXIT ?trans5;
BRA 0xd70;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: sumMatrixRowsKernel(int, double*, double*)
_Z19sumMatrixRowsKerneliPdS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x0
s_load_b128 s[0:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_3
v_mul_lo_u32 v1, v0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
.LBB0_2:
global_load_b64 v[5:6], v[3:4], off
v_add_co_u32 v3, vcc_lo, v3, 8
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_add_i32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s4, 0
s_waitcnt vmcnt(0)
v_add_f64 v[1:2], v[1:2], v[5:6]
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
.LBB0_4:
v_lshlrev_b32_e32 v0, 3, v0
global_store_b64 v0, v[1:2], s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| sumMatrixRowsKernel | 4,175 | 565 | stackv2-00000-of-00015 |
// Demangled: init()
Function : _Z4initv
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
EXIT ?trans5;
BRA 0x20;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: init()
_Z4initv:
s_endpgm
| init | 91 | 11 | stackv2-00000-of-00015 |
// Demangled: scatterSum(int, float*, float*)
Function : _Z10scatterSumiPfS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x2 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x2 ?trans1;
LDCU UR6, c[0x0][0x380] &wr=0x3 ?trans2;
MOV R4, UR6 &req={3} ?trans1;
UIMAD UR4, UR4, UR5, URZ &req={2} ?WAIT6_END_GROUP;
IADD3 R7, PT, PT, R0, UR4, RZ &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R7, R4, PT ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
ISETP.GE.AND P0, PT, R4, 0x1, PT ?WAIT13_END_GROUP;
@!P0 EXIT ?trans5;
LDC.64 R2, c[0x0][0x388] &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x1 ?trans1;
ISETP.GE.U32.AND P0, PT, R4.reuse, 0x4, PT ?trans1;
HFMA2 R11, -RZ, RZ, 0, 0 ?trans1;
LOP3.LUT R6, R4, 0x3, RZ, 0xc0, !PT ?trans1;
IMAD.WIDE R2, R7, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E R5, desc[UR6][R2.64] &req={1} &rd=0x0 &wr=0x5 ?trans5;
@!P0 BRA 0x6d0 ?trans5;
IABS R8, R4 ?trans1;
LDC R9, c[0x0][0x380] &wr=0x1 ?trans1;
MOV R10, RZ ?trans1;
LOP3.LUT R12, R4, 0x7ffffffc, RZ, 0xc0, !PT ?trans1;
I2F.RP R13, R8 &wr=0x2 ?trans3;
IADD3 R12, PT, PT, -R12, RZ, RZ ?trans2;
LDC.64 R2, c[0x0][0x390] &req={0} &wr=0x0 ?trans1;
MUFU.RCP R13, R13 &req={2} &wr=0x2 ?trans2;
IADD3 R14, PT, PT, R13, 0xffffffe, RZ &req={2} ?WAIT4_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R11, R14 &wr=0x2 ?trans2;
IADD3 R15, PT, PT, RZ, -R11, RZ &req={2} ?WAIT5_END_GROUP;
IMAD R15, R15, R8, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R11, R11, R15, R10 ?trans1;
MOV R10, 0x1 &req={1,0} ?WAIT7_END_GROUP;
MOV R4, R9 ?trans1;
IABS R18, R7 &req={0} ?trans2;
IADD3 R17, PT, PT, R7.reuse, 0x2, RZ ?trans2;
IADD3 R16, PT, PT, R7, 0x1, RZ ?trans2;
IABS R13, R4 ?trans1;
IMAD.HI.U32 R11, R11, R18, RZ ?trans1;
ISETP.GE.AND P4, PT, R7, RZ, PT ?trans1;
IABS R24, R17 ?trans1;
I2F.RP R19, R13 &wr=0x0 ?trans1;
IABS R22, R16 ?WAIT2_END_GROUP;
IADD3 R11, PT, PT, -R11, RZ, RZ ?trans1;
ISETP.GE.AND P3, PT, R16, RZ, PT ?trans1;
ISETP.GE.AND P5, PT, R17, RZ, PT ?trans1;
LOP3.LUT R21, RZ, R4, RZ, 0x33, !PT ?trans2;
IMAD R18, R13, R11, R18 ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R8, R18, PT ?trans1;
MUFU.RCP R19, R19 &req={0} &wr=0x0 ?WAIT12_END_GROUP;
@!P0 IADD3 R18, PT, PT, R18, -R13, RZ ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P6, PT, R8, R18, PT ?trans1;
MOV R8, R13 ?trans1;
IADD3 R14, PT, PT, R19, 0xffffffe, RZ &req={0} ?trans2;
IADD3 R19, PT, PT, R7, 0x3, RZ ?trans2;
F2I.FTZ.U32.TRUNC.NTZ R15, R14 &rd=0x0 &wr=0x1 ?trans2;
IABS R26, R19 ?WAIT5_END_GROUP;
@!P6 IADD3 R18, PT, PT, R18, -R13, RZ ?trans1;
ISETP.GE.AND P6, PT, R19, RZ, PT ?trans1;
HFMA2 R14, -RZ, RZ, 0, 0 &req={0} ?trans1;
IADD3 R12, PT, PT, R12, 0x4, RZ ?trans2;
@!P4 IADD3 R18, PT, PT, -R18, RZ, RZ ?trans2;
IADD3 R20, PT, PT, RZ, -R15, RZ &req={1} ?WAIT5_END_GROUP;
IMAD R11, R20, R13, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R11, R15, R11, R14 ?WAIT6_END_GROUP;
IMAD.HI.U32 R15, R11, R24, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R14, R11, R22, RZ ?trans1;
IADD3 R15, PT, PT, -R15, RZ, RZ ?WAIT3_END_GROUP;
IMAD.HI.U32 R20, R11, R26, RZ ?trans1;
IADD3 R14, PT, PT, -R14, RZ, RZ ?WAIT3_END_GROUP;
IMAD R15, R13.reuse, R15, R24 ?trans1;
IADD3 R20, PT, PT, -R20, RZ, RZ ?trans1;
IMAD R14, R13, R14, R22 ?WAIT3_END_GROUP;
ISETP.GT.U32.AND P1, PT, R8.reuse, R15, PT ?trans1;
IMAD R20, R13, R20, R26 ?trans1;
ISETP.GT.U32.AND P0, PT, R8, R14, PT ?WAIT4_END_GROUP;
ISETP.GT.U32.AND P2, PT, R8, R20, PT ?WAIT7_END_GROUP;
@!P1 IADD3 R15, PT, PT, R15, -R13.reuse, RZ ?trans2;
@!P0 IADD3 R14, PT, PT, R14, -R13, RZ ?WAIT3_END_GROUP;
ISETP.GT.U32.AND P1, PT, R8, R15, PT ?trans1;
@!P2 IADD3 R20, PT, PT, R20, -R13, RZ ?trans1;
ISETP.GT.U32.AND P0, PT, R8, R14, PT ?WAIT4_END_GROUP;
ISETP.GT.U32.AND P2, PT, R8, R20, PT ?WAIT7_END_GROUP;
@!P1 IADD3 R15, PT, PT, R15, -R13.reuse, RZ ?trans2;
@!P0 IADD3 R14, PT, PT, R14, -R13, RZ ?trans1;
ISETP.NE.AND P0, PT, R4, RZ, PT ?WAIT3_END_GROUP;
@!P2 IADD3 R20, PT, PT, R20, -R13, RZ ?trans1;
MOV R13, R15 ?trans1;
@!P3 IADD3 R14, PT, PT, -R14, RZ, RZ ?trans1;
SEL R15, R21, R18, !P0 ?trans1;
@!P6 IADD3 R20, PT, PT, -R20, RZ, RZ ?trans2;
@!P5 IADD3 R13, PT, PT, -R13, RZ, RZ ?trans1;
SEL R17, R21, R14, !P0 ?trans1;
IMAD.WIDE R14, R15, 0x4, R2 ?WAIT3_END_GROUP;
SEL R19, R21.reuse, R13, !P0 ?trans1;
SEL R21, R21, R20, !P0 ?trans1;
ISETP.NE.AND P0, PT, R12, RZ, PT ?trans1;
IMAD.WIDE R16, R17, 0x4, R2.reuse ?trans1;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R14.64], R5 &req={5} &rd=0x0 ?trans3;
IMAD.WIDE R18, R19, 0x4, R2.reuse ?trans1;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R16.64], R5 &rd=0x0 ?trans3;
IMAD.WIDE R20, R21, 0x4, R2 ?trans1;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R18.64], R5 &rd=0x0 ?trans1;
IADD3 R10, PT, PT, R10, 0x4, RZ ?WAIT3_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R20.64], R5 &rd=0x0 ?trans1;
IADD3 R7, PT, PT, R7, 0x4, RZ ?trans1;
@P0 BRA 0x220 ?trans6;
IADD3 R11, PT, PT, R10, -0x1, RZ ?WAIT7_END_GROUP;
ISETP.NE.AND P0, PT, R6, RZ, PT ?WAIT13_END_GROUP;
@!P0 EXIT ?trans5;
IABS R13, R4 ?trans1;
LDC R10, c[0x0][0x380] &wr=0x1 ?trans1;
IADD3 R0, PT, PT, R0, UR4, R11 ?trans2;
I2F.RP R7, R13 &wr=0x2 ?trans1;
ISETP.NE.AND P2, PT, R4, RZ, PT ?WAIT4_END_GROUP;
LDC.64 R2, c[0x0][0x390] &req={0} &wr=0x0 ?trans1;
MUFU.RCP R7, R7 &req={2} &wr=0x2 ?trans1;
IABS R15, R10 &req={1} ?trans2;
IADD3 R8, PT, PT, R7, 0xffffffe, RZ &req={2} ?WAIT4_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R9, R8 &rd=0x1 &wr=0x2 ?trans2;
HFMA2 R8, -RZ, RZ, 0, 0 &req={1} ?trans1;
IADD3 R12, PT, PT, RZ, -R9, RZ &req={2} ?WAIT5_END_GROUP;
IMAD R11, R12, R13, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R11, R9, R11, R8 ?trans1;
IADD3 R8, PT, PT, -R6, RZ, RZ ?trans2;
LOP3.LUT R9, RZ, R4, RZ, 0x33, !PT &req={0} ?WAIT7_END_GROUP;
IABS R6, R0 &req={0} ?trans1;
ISETP.GE.AND P1, PT, R0, RZ, PT ?WAIT4_END_GROUP;
IMAD.HI.U32 R4, R11, R6, RZ ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, -R4, RZ, RZ ?WAIT5_END_GROUP;
IMAD R4, R15, R7, R6 ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R13, R4, PT ?WAIT13_END_GROUP;
@!P0 IADD3 R4, PT, PT, R4, -R15, RZ ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R13, R4, PT ?trans1;
IADD3 R8, PT, PT, R8, 0x1, RZ ?WAIT12_END_GROUP;
@!P0 IADD3 R4, PT, PT, R4, -R15, RZ ?trans1;
ISETP.NE.AND P0, PT, R8, RZ, PT ?WAIT3_END_GROUP;
@!P1 IADD3 R4, PT, PT, -R4, RZ, RZ ?WAIT5_END_GROUP;
SEL R7, R9, R4, !P2 ?WAIT5_END_GROUP;
IMAD.WIDE R6, R7, 0x4, R2 ?trans1;
IADD3 R0, PT, PT, R0, 0x1, RZ ?WAIT4_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R6.64], R5 &req={5} &rd=0x0 ?trans1;
@P0 BRA 0x7f0 ?trans5;
EXIT ?trans5;
BRA 0x910;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: scatterSum(int, float*, float*)
_Z10scatterSumiPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB1_6
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB1_6
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_ashr_i32 s0, s4, 31
s_add_i32 s1, s4, s0
global_load_b32 v0, v[2:3], off
s_xor_b32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v2, s0
s_sub_i32 s1, 0, s0
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v2, v2
v_mul_lo_u32 v3, s1, v2
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v2, v3
v_add_nc_u32_e32 v6, v2, v3
.LBB1_3:
v_add_nc_u32_e32 v2, s1, v1
s_mov_b32 s5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_add_nc_u32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, v2, v3
v_mul_hi_u32 v4, v2, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v4, s0
v_sub_nc_u32_e32 v2, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v4, s0, v2
v_cmp_le_u32_e32 vcc_lo, s0, v2
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v4, s0, v2
v_cmp_le_u32_e32 vcc_lo, s0, v2
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, v2, v3
v_sub_nc_u32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v5, v[2:3], off
.LBB1_4:
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v5, v0
global_atomic_cmpswap_b32 v4, v[2:3], v[4:5], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v4, v5
v_mov_b32_e32 v5, v4
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB1_4
s_or_b32 exec_lo, exec_lo, s5
s_add_i32 s1, s1, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s1, s4
s_cbranch_scc1 .LBB1_3
.LBB1_6:
s_endpgm
| scatterSum | 3,717 | 1,628 | stackv2-00000-of-00015 |
// Demangled: data_trans(double*, double*, int)
Function : _Z10data_transPdS_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R7, SR_TID.X &wr=0x1 ?trans7;
LDC R0, c[0x0][0x390] &wr=0x1 ?trans2;
ISETP.GE.AND P0, PT, R7, R0, PT &req={1} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LOP3.LUT R3, RZ, R7, RZ, 0x33, !PT ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans1;
BSSY.RECONVERGENT B0, 0x1b0 ?trans2;
IADD3 R3, PT, PT, R3, R0, RZ ?WAIT4_END_GROUP;
LEA.HI R2, R3.reuse, 0x1, RZ, 0x17 ?trans1;
ISETP.GE.U32.AND P0, PT, R3, 0x600, PT ?WAIT3_END_GROUP;
LOP3.LUT P1, R8, R2, 0x3, RZ, 0xc0, !PT ?WAIT13_END_GROUP;
@!P1 BRA 0x1a0 &req={0} ?trans5;
LDC.64 R2, c[0x0][0x388] &wr=0x0 ?trans1;
IADD3 R6, PT, PT, -R8, RZ, RZ ?WAIT7_END_GROUP;
LDC.64 R4, c[0x0][0x380] &wr=0x1 ?trans1;
IMAD.WIDE.U32 R2, R7, 0x8, R2 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x8, R4 &req={1} ?WAIT4_END_GROUP;
IMAD R7, R8, 0x200, R7 ?WAIT7_END_GROUP;
LDG.E.64 R8, desc[UR4][R4.64] &rd=0x0 &wr=0x2 ?trans1;
IADD3 R6, PT, PT, R6, 0x1, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R6, RZ, PT ?trans1;
IADD.64 R4, R4, 0x1000 &req={0} ?trans2;
STG.E.64 desc[UR4][R2.64], R8 &req={2} &rd=0x0 ?trans2;
IADD.64 R2, R2, 0x1000 &req={0} ?WAIT8_END_GROUP;
@P1 BRA 0x130 ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
@!P0 EXIT ?trans5;
LDCU.128 UR8, c[0x0][0x380] &wr=0x0 ?trans1;
IADD3 R2, PT, PT, -R7.reuse, R0, RZ ?trans1;
MOV.64 R4, 0x2000 ?trans2;
BSSY.RECONVERGENT B0, 0x4e0 ?trans1;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x8 ?trans1;
ISETP.GT.AND P1, PT, R2, 0x1800, PT ?trans2;
IMAD.WIDE.U32 R4, R7, 0x8, R4 ?WAIT5_END_GROUP;
IADD.64 R2, R4.reuse, UR8 &req={0} ?trans2;
IADD.64 R4, R4, UR10 ?WAIT4_END_GROUP;
@!P1 BRA 0x4d0 ?trans5;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x80 ?trans2;
IADD3 R6, PT, PT, R0, -0x1800, RZ ?WAIT11_END_GROUP;
LDG.E.64 R8, desc[UR4][R2.64+-0x2000] &wr=0x2 ?trans4;
STG.E.64 desc[UR4][R4.64+-0x2000], R8 &req={2} &rd=0x0 ?trans4;
LDG.E.64 R10, desc[UR4][R2.64+-0x1000] &wr=0x2 ?trans4;
STG.E.64 desc[UR4][R4.64+-0x1000], R10 &req={2} &rd=0x1 ?trans4;
LDG.E.64 R12, desc[UR4][R2.64] &wr=0x2 ?trans4;
STG.E.64 desc[UR4][R4.64], R12 &req={2} &rd=0x2 ?trans4;
LDG.E.64 R14, desc[UR4][R2.64+0x1000] &wr=0x3 ?trans4;
STG.E.64 desc[UR4][R4.64+0x1000], R14 &req={3} &rd=0x3 ?trans4;
LDG.E.64 R16, desc[UR4][R2.64+0x2000] &wr=0x4 ?trans4;
STG.E.64 desc[UR4][R4.64+0x2000], R16 &req={4} &rd=0x4 ?trans4;
LDG.E.64 R18, desc[UR4][R2.64+0x3000] &wr=0x5 ?trans4;
STG.E.64 desc[UR4][R4.64+0x3000], R18 &req={5} &rd=0x5 ?trans4;
LDG.E.64 R8, desc[UR4][R2.64+0x4000] &req={0} &wr=0x2 ?trans4;
STG.E.64 desc[UR4][R4.64+0x4000], R8 &req={2} &rd=0x0 ?trans4;
LDG.E.64 R10, desc[UR4][R2.64+0x5000] &req={1} &wr=0x2 ?trans4;
STG.E.64 desc[UR4][R4.64+0x5000], R10 &req={2} &rd=0x1 ?trans4;
LDG.E.64 R12, desc[UR4][R2.64+0x6000] &wr=0x2 ?trans4;
STG.E.64 desc[UR4][R4.64+0x6000], R12 &req={2} &rd=0x2 ?trans4;
LDG.E.64 R14, desc[UR4][R2.64+0x7000] &req={3} &wr=0x3 ?trans4;
STG.E.64 desc[UR4][R4.64+0x7000], R14 &req={3} &rd=0x3 ?trans4;
LDG.E.64 R16, desc[UR4][R2.64+0x8000] &req={4} &wr=0x4 ?trans4;
STG.E.64 desc[UR4][R4.64+0x8000], R16 &req={4} ?trans4;
LDG.E.64 R18, desc[UR4][R2.64+0x9000] &req={5} &wr=0x4 ?trans4;
STG.E.64 desc[UR4][R4.64+0x9000], R18 &req={4} ?trans4;
LDG.E.64 R8, desc[UR4][R2.64+0xa000] &req={0} &wr=0x4 ?trans4;
STG.E.64 desc[UR4][R4.64+0xa000], R8 &req={4} ?trans4;
LDG.E.64 R10, desc[UR4][R2.64+0xb000] &req={1} &wr=0x4 ?trans4;
STG.E.64 desc[UR4][R4.64+0xb000], R10 &req={4} ?trans4;
LDG.E.64 R12, desc[UR4][R2.64+0xc000] &req={2} &wr=0x2 ?trans1;
IADD3 R7, PT, PT, R7, 0x2000, RZ ?WAIT5_END_GROUP;
ISETP.GE.AND P1, PT, R7, R6, PT ?trans1;
STG.E.64 desc[UR4][R4.64+0xc000], R12 &req={2} ?trans4;
LDG.E.64 R14, desc[UR4][R2.64+0xd000] &req={3} &rd=0x0 &wr=0x2 ?trans2;
IADD.64 R2, R2, 0x10000 &req={0} ?trans2;
STG.E.64 desc[UR4][R4.64+0xd000], R14 &req={2} &rd=0x0 ?trans2;
IADD.64 R4, R4, 0x10000 &req={0} ?WAIT2_END_GROUP;
@!P1 BRA 0x280 ?trans6;
BSYNC.RECONVERGENT B0 ?trans5;
IADD3 R6, PT, PT, -R7, R0, RZ ?WAIT5_END_GROUP;
ISETP.GT.AND P1, PT, R6, 0x800, PT ?WAIT13_END_GROUP;
@P1 LDG.E.64 R8, desc[UR4][R2.64+-0x2000] &wr=0x2 ?trans4;
@P1 STG.E.64 desc[UR4][R4.64+-0x2000], R8 &req={2} &rd=0x0 ?trans4;
@P1 LDG.E.64 R10, desc[UR4][R2.64+-0x1000] &wr=0x2 ?trans4;
@P1 STG.E.64 desc[UR4][R4.64+-0x1000], R10 &req={2} &rd=0x1 ?trans4;
@P1 LDG.E.64 R12, desc[UR4][R2.64] &wr=0x2 ?trans4;
@P1 STG.E.64 desc[UR4][R4.64], R12 &req={2} &rd=0x2 ?trans4;
@P1 LDG.E.64 R14, desc[UR4][R2.64+0x1000] &wr=0x3 ?trans4;
@P1 STG.E.64 desc[UR4][R4.64+0x1000], R14 &req={3} &rd=0x2 ?trans4;
@P1 LDG.E.64 R16, desc[UR4][R2.64+0x2000] &wr=0x3 ?trans4;
@P1 STG.E.64 desc[UR4][R4.64+0x2000], R16 &req={3} &rd=0x2 ?trans4;
@P1 LDG.E.64 R18, desc[UR4][R2.64+0x3000] &wr=0x3 ?trans4;
@P1 STG.E.64 desc[UR4][R4.64+0x3000], R18 &req={3} &rd=0x2 ?trans4;
@P1 LDG.E.64 R8, desc[UR4][R2.64+0x4000] &req={0} &wr=0x3 ?trans1;
@P1 PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x80 ?WAIT2_END_GROUP;
@P1 IADD3 R7, PT, PT, R7, 0x1000, RZ ?WAIT5_END_GROUP;
ISETP.LT.OR P0, PT, R7, R0, P0 ?trans1;
@P1 STG.E.64 desc[UR4][R4.64+0x4000], R8 &req={3} &rd=0x2 ?trans4;
@P1 LDG.E.64 R10, desc[UR4][R2.64+0x5000] &req={1} &rd=0x0 &wr=0x3 ?trans2;
@P1 IADD.64 R2, R2, 0x8000 &req={0} ?trans2;
@P1 STG.E.64 desc[UR4][R4.64+0x5000], R10 &req={3} &rd=0x2 ?trans4;
@!P0 EXIT ?trans5;
LDG.E.64 R6, desc[UR4][R2.64+-0x2000] &wr=0x3 ?trans1;
@P1 IADD.64 R4, R4, 0x8000 &req={2} ?WAIT6_END_GROUP;
STG.E.64 desc[UR4][R4.64+-0x2000], R6 &req={3} ?trans4;
LDG.E.64 R8, desc[UR4][R2.64+-0x1000] &wr=0x2 ?trans4;
STG.E.64 desc[UR4][R4.64+-0x1000], R8 &req={2} ?trans4;
LDG.E.64 R10, desc[UR4][R2.64] &wr=0x2 ?trans4;
STG.E.64 desc[UR4][R4.64], R10 &req={2} ?trans4;
LDG.E.64 R12, desc[UR4][R2.64+0x1000] &wr=0x2 ?trans4;
STG.E.64 desc[UR4][R4.64+0x1000], R12 &req={2} ?trans1;
EXIT ?trans5;
BRA 0x6f0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: data_trans(double*, double*, int)
_Z10data_transPdS_i:
s_load_b32 s2, s[0:1], 0x10
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 3, v0
s_mov_b32 s1, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s0, s4, v3
v_add_co_ci_u32_e64 v2, null, s5, 0, s0
v_add_co_u32 v3, s0, s6, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, null, s7, 0, s0
.LBB0_2:
global_load_b64 v[5:6], v[1:2], off
v_add_nc_u32_e32 v0, 0x200, v0
v_add_co_u32 v1, vcc_lo, 0x1000, v1
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_cmp_le_i32_e32 vcc_lo, s2, v0
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
global_store_b64 v[3:4], v[5:6], off
v_add_co_u32 v3, s0, 0x1000, v3
v_add_co_ci_u32_e64 v4, s0, 0, v4, s0
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| data_trans | 3,673 | 577 | stackv2-00000-of-00015 |
// Demangled: MatrixMulKernel(float*, float*, float*, int)
Function : _Z15MatrixMulKernelPfS_S_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R9, SR_TID.Y &wr=0x0 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans1;
S2R R16, SR_TID.X &wr=0x1 ?trans6;
LDC.64 R2, c[0x0][0x380] &wr=0x3 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x4 ?trans1;
LEA R9, R9, R9, 0x2 &req={0} ?trans1;
IMAD.WIDE.U32 R4, R16, 0x4, R4 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R2, R9.reuse, 0x4, R2 &req={3} ?trans1;
LDG.E R11, desc[UR4][R4.64] &req={2} &wr=0x2 ?trans4;
LDG.E R0, desc[UR4][R2.64] &wr=0x2 ?trans4;
LDG.E R8, desc[UR4][R4.64+0x14] &wr=0x3 ?trans4;
LDG.E R13, desc[UR4][R2.64+0x4] &wr=0x3 ?trans4;
LDG.E R10, desc[UR4][R4.64+0x28] &wr=0x5 ?trans4;
LDG.E R15, desc[UR4][R2.64+0x8] &wr=0x5 ?trans4;
LDG.E R12, desc[UR4][R4.64+0x3c] &wr=0x5 ?trans4;
LDG.E R17, desc[UR4][R2.64+0xc] &wr=0x5 ?trans4;
LDG.E R19, desc[UR4][R2.64+0x10] &wr=0x5 ?trans4;
LDG.E R14, desc[UR4][R4.64+0x50] &wr=0x5 ?trans1;
IADD3 R9, PT, PT, R9, R16, RZ ?WAIT5_END_GROUP;
IMAD.WIDE.U32 R6, R9, 0x4, R6 &req={4} ?WAIT4_END_GROUP;
FFMA R0, R0, R11, RZ &req={2} ?WAIT4_END_GROUP;
FFMA R0, R13, R8, R0 &req={3} ?WAIT4_END_GROUP;
FFMA R0, R15, R10, R0 &req={5} ?WAIT4_END_GROUP;
FFMA R0, R17, R12, R0 ?WAIT4_END_GROUP;
FFMA R19, R19, R14, R0 ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R19 ?trans1;
EXIT ?trans5;
BRA 0x1d0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: MatrixMulKernel(float*, float*, float*, int)
_Z15MatrixMulKernelPfS_S_i:
s_load_b128 s[4:7], s[0:1], 0x0
v_bfe_u32 v1, v0, 10, 10
s_load_b64 s[0:1], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_u32_u24_e32 v3, 5, v1
v_lshlrev_b32_e32 v0, 2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v4, 2, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, s2, s6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v1, null, s7, 0, s2
v_add_co_u32 v5, s2, s4, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, null, s5, 0, s2
v_mov_b32_e32 v4, 0
s_mov_b64 s[2:3], 0
.LBB0_1:
s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
v_add_co_u32 v7, vcc_lo, v5, s2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v6, vcc_lo
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
global_load_b32 v9, v[0:1], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_cmp_eq_u32 s2, 20
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v4, v7, v9
s_cbranch_scc0 .LBB0_1
v_add_lshl_u32 v0, v3, v2, 2
global_store_b32 v0, v4, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| MatrixMulKernel | 857 | 711 | stackv2-00000-of-00015 |
// Demangled: kernel(Shape*)
Function : _Z6kernelP5Shape
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans2;
LDG.E.64 R2, desc[UR4][R2.64] &req={0} &wr=0x2 ?trans4;
LDG.E.64 R4, desc[UR4][R2.64+0x8] &req={2} &wr=0x2 ?trans4;
LDG.E.64 R6, desc[UR4][R2.64+0x10] &wr=0x3 ?trans4;
LDG.E R4, desc[UR4][R4.64] &req={2} &wr=0x2 ?trans4;
LDG.E R7, desc[UR4][R6.64] &req={3} &wr=0x2 ?trans2;
IMAD R9, R4, R7, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R9 ?trans1;
EXIT ?trans5;
BRA 0xb0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: kernel(Shape*)
_Z6kernelP5Shape:
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b64 s[4:5], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b128 s[0:3], s[4:5], 0x8
s_waitcnt lgkmcnt(0)
s_load_b32 s0, s[0:1], 0x0
s_load_b32 s1, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[4:5]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| kernel | 368 | 245 | stackv2-00000-of-00015 |
// Demangled: add(int*, int*, int*, int*)
Function : _Z3addPiS_S_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R2, c[0x0][0x398] &wr=0x1 ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans6;
S2UR UR6, SR_CTAID.X &wr=0x1 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
LDC R9, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R9, R9, UR6, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R9, R2, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans8;
LDC.64 R4, c[0x0][0x388] &wr=0x1 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x2 ?trans1;
IMAD.WIDE R2, R9, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &wr=0x3 ?trans1;
IMAD.WIDE R4, R9, 0x4, R4 &req={1} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR4][R4.64] &wr=0x3 ?trans1;
IMAD.WIDE R6, R9, 0x4, R6 &req={2} ?trans1;
IADD3 R9, PT, PT, R2, R5, RZ &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x150;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: add(int*, int*, int*, int*)
_Z3addPiS_S_S_:
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_load_b32 s1, s[10:11], 0x0
s_and_b32 s0, s0, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s1, v1
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s8, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| add | 598 | 552 | stackv2-00000-of-00015 |
// Demangled: calc(double*, double*, int)
Function : _Z4calcPdS_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R7, SR_TID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x390] &wr=0x1 ?trans2;
ISETP.GE.AND P0, PT, R7, UR4, PT &req={1} ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x3 ?trans1;
IMAD.WIDE.U32 R2, R7, 0x8, R2 &req={1} ?WAIT6_END_GROUP;
LDG.E.64 R2, desc[UR4][R2.64] &req={2} &wr=0x2 ?trans1;
IMAD.WIDE.U32 R4, R7, 0x8, R4 &req={3} ?WAIT5_END_GROUP;
STG.E.64 desc[UR4][R4.64], R2 &req={2} ?trans1;
EXIT ?trans5;
BRA 0xd0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: calc(double*, double*, int)
_Z4calcPdS_i:
s_load_b32 s2, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 3, v0
s_waitcnt lgkmcnt(0)
global_load_b64 v[0:1], v2, s[0:1]
s_waitcnt vmcnt(0)
global_store_b64 v2, v[0:1], s[2:3]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| calc | 395 | 214 | stackv2-00000-of-00015 |
// Demangled: copyHorizontalBoundaries(int, int, double*)
Function : _Z24copyHorizontalBoundariesiiPd
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R14, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans7;
LDC.64 R18, c[0x0][0x388] &wr=0x3 ?trans8;
LDC.64 R16, c[0x0][0x388] &wr=0x4 ?trans1;
IADD3 R21, PT, PT, R3, 0x2, RZ &req={1} ?WAIT5_END_GROUP;
IMAD R5, R21, R14, R21 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE R4, R5, 0x8, R18 &req={3} ?WAIT5_END_GROUP;
LDG.E.64 R6, desc[UR4][R4.64+0x10] &req={2} &wr=0x2 ?trans1;
IMAD.WIDE R8, R3, 0x8, R4 ?trans1;
IADD3 R12, PT, PT, R21, R21, RZ ?WAIT3_END_GROUP;
HFMA2 R15, -RZ, RZ, 0, 0 ?trans1;
SHF.R.S32.HI R13, RZ, 0x1f, R12 ?WAIT5_END_GROUP;
IADD.64 R12, R12, R14 ?trans2;
STG.E.64 desc[UR4][R4.64], R6 &req={2} &rd=0x0 ?trans4;
LDG.E.64 R10, desc[UR4][R8.64+-0x8] &wr=0x2 ?trans1;
LEA R16, P0, R12, R16, 0x3 &req={4} ?WAIT4_END_GROUP;
LEA.HI.X R17, R12, R17, R13, 0x3, P0 ?trans2;
IADD3 R0, PT, PT, R2, -0x1, RZ ?trans1;
IMAD.WIDE.U32 R14, R14, 0x8, R18 ?trans1;
STG.E.64 desc[UR4][R8.64+0x8], R10 &req={2} ?trans4;
LDG.E.64 R12, desc[UR4][R16.64+0x8] &wr=0x2 ?trans1;
IMAD R5, R21, R0, RZ &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE R4, R5, 0x8, R14 ?trans1;
STG.E.64 desc[UR4][R14.64+0x8], R12 &req={2} ?trans5;
LDG.E.64 R4, desc[UR4][R4.64+0x8] &wr=0x2 ?trans1;
IMAD R3, R21, R2, R21 ?WAIT4_END_GROUP;
IMAD.WIDE R2, R3, 0x8, R14 ?WAIT5_END_GROUP;
STG.E.64 desc[UR4][R2.64+0x8], R4 &req={2} ?trans1;
EXIT ?trans5;
BRA 0x1f0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: copyHorizontalBoundaries(int, int, double*)
_Z24copyHorizontalBoundariesiiPd:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s1, 2
s_add_i32 s0, s0, -1
v_mad_u64_u32 v[1:2], null, s4, v0, s[4:5]
s_lshl_b32 s6, s4, 1
s_mul_i32 s0, s4, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
s_ashr_i32 s1, s6, 31
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v6, -1, v1
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
v_ashrrev_i32_e32 v7, 31, v6
global_load_b64 v[4:5], v[2:3], off offset:16
v_lshlrev_b64 v[6:7], 3, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_waitcnt vmcnt(0)
global_store_b64 v[2:3], v[4:5], off
global_load_b64 v[3:4], v[6:7], off
v_ashrrev_i32_e32 v2, 31, v1
v_add_co_u32 v5, s5, s6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v6, null, s1, 0, s5
v_lshlrev_b64 v[1:2], 3, v[1:2]
v_lshlrev_b32_e32 v0, 3, v0
s_ashr_i32 s1, s0, 31
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[5:6], 3, v[5:6]
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
s_waitcnt vmcnt(0)
global_store_b64 v[1:2], v[3:4], off offset:8
global_load_b64 v[1:2], v[5:6], off offset:8
v_add_co_u32 v5, s4, s2, v0
v_add_co_ci_u32_e64 v6, null, s3, 0, s4
s_lshl_b64 s[4:5], s[0:1], 3
s_add_i32 s0, s0, s6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, v5, s4
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v6, vcc_lo
s_ashr_i32 s1, s0, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[0:1], 3
s_waitcnt vmcnt(0)
global_store_b64 v0, v[1:2], s[2:3] offset:8
global_load_b64 v[0:1], v[3:4], off offset:8
v_add_co_u32 v2, vcc_lo, v5, s0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v6, vcc_lo
s_waitcnt vmcnt(0)
global_store_b64 v[2:3], v[0:1], off offset:8
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| copyHorizontalBoundaries | 926 | 1,353 | stackv2-00000-of-00015 |
// Demangled: odeSolver(int, int, double*, double*, double*, double, double, double, double, double, double, double, double**, double**)
Function : _Z9odeSolveriiPdS_S_dddddddPS_S0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R7, SR_TID.X &wr=0x1 ?trans7;
LDC R0, c[0x0][0x364] &wr=0x2 ?trans1;
LDCU UR4, c[0x0][0x384] &wr=0x3 ?trans1;
S2R R5, SR_TID.Y &wr=0x2 ?trans1;
LDCU.128 UR12, c[0x0][0x3b0] &wr=0x4 ?trans5;
S2UR UR6, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.128 UR8, c[0x0][0x3c0] &wr=0x5 ?trans7;
LDC R4, c[0x0][0x360] &wr=0x1 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x2, URZ &req={3} ?WAIT7_END_GROUP;
S2UR UR5, SR_CTAID.Y &wr=0x2 ?trans8;
LDC.64 R2, c[0x0][0x388] &wr=0x3 ?trans1;
IMAD R4, R4, UR6, R7 &req={1} ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x1 ?trans6;
LDC.64 R6, c[0x0][0x390] &wr=0x0 ?trans1;
IMAD R0, R0, UR5, R5 &req={2} ?trans1;
IADD3 R5, PT, PT, R4, 0x1, RZ ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R0, 0x1, RZ ?WAIT5_END_GROUP;
IMAD R9, R0, UR4, R5 ?trans1;
LDCU.64 UR4, c[0x0][0x3a8] &wr=0x2 ?trans3;
IMAD.WIDE R2, R9, 0x8, R2 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE R6, R9, 0x8, R6 &req={0} ?trans1;
LDG.E.64 R4, desc[UR6][R2.64] &req={1} &wr=0x4 ?trans4;
LDG.E.64 R14, desc[UR6][R6.64] &wr=0x3 ?trans1;
DMUL R8, R4, UR14 &req={4} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R10, R4, -UR10 &req={5} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R12, R4, -1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R8, R8, R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R8, R8, R12 &req={0} &wr=0x3 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R4, R14, R8 &req={3} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R4, -R8, UR8, R4 &req={0} &wr=0x0 ?trans2;
STG.E.64 desc[UR6][R2.64], R4 &req={0} &rd=0x0 ?trans4;
LDG.E.64 R8, desc[UR6][R6.64] &wr=0x2 ?trans1;
MOV R14, 0x1 ?trans1;
BSSY.RECONVERGENT B0, 0x760 ?WAIT15_END_GROUP;
NOP ?WAIT11_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R10, R4, UR12 &wr=0x1 ?trans2;
MUFU.RCP64H R15, R11 &req={1} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, -R10, R14, 1 &req={1} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, R16, R16, R16 &req={1} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, R14, R16, R14 &req={1} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R14, -R10, R16, 1 &req={1} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R12, R8, UR4 &req={2} &wr=0x1 ?trans2;
FSETP.GEU.AND P1, PT, |R13|, 6.5827683646048100446e-37, PT &req={1} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R14, R16, R14, R16 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R2, R12, R14 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, -R10, R2, R12 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R14, R16, R2 &req={0} &wr=0x0 ?trans2;
FFMA R0, RZ, R11, R3 &req={0} ?WAIT5_END_GROUP;
FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ?WAIT13_END_GROUP;
@P0 BRA P1, 0x750 ?trans5;
MOV R0, 0x730 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x9b0 ?trans5;
MOV R2, R16 ?trans1;
MOV R3, R17 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
LDCU.64 UR4, c[0x0][0x3a0] &wr=0x0 ?trans2;
DADD R2, R2, UR4 &req={0} ?trans1;
LDCU.64 UR4, c[0x0][0x3b8] &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R10, R4, UR4 &req={0} ?trans1;
LDCU.64 UR4, c[0x0][0x3d0] &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R4, R4, -UR4 &req={0} &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x3c0] &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R4, R4, -1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R2, R2, UR4 &req={1} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R4, -R10, R4, -R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R2, R4, R8 &req={0} &wr=0x0 ?trans2;
STG.E.64 desc[UR6][R6.64], R2 &req={0} ?trans1;
EXIT ?trans5;
FSETP.GEU.AND P2, PT, |R13|.reuse, 1.469367938527859385e-39, PT ?trans1;
LOP3.LUT R16, R13, 0x7ff00000, RZ, 0xc0, !PT ?trans1;
BSSY.RECONVERGENT B1, 0x1190 ?trans1;
LOP3.LUT R21, R11.reuse, 0x7ff00000, RZ, 0xc0, !PT ?trans1;
MOV R17, 0x1ca00000 ?trans1;
FSETP.GEU.AND P0, PT, |R11|.reuse, 1.469367938527859385e-39, PT ?trans1;
LOP3.LUT R2, R11, 0x800fffff, RZ, 0xc0, !PT ?trans2;
ISETP.GE.U32.AND P1, PT, R16, R21, PT ?trans1;
MOV R14, R12 ?trans1;
LOP3.LUT R3, R2, 0x3ff00000, RZ, 0xfc, !PT ?WAIT3_END_GROUP;
@!P2 LOP3.LUT R15, R11, 0x7ff00000, RZ, 0xc0, !PT ?trans1;
@!P2 MOV R24, RZ ?trans1;
MOV R2, R10 ?trans1;
MOV R20, R16 ?trans2;
@!P2 ISETP.GE.U32.AND P3, PT, R16, R15, PT ?trans1;
SEL R15, R17.reuse, 0x63400000, !P1 ?trans1;
MOV R18, 0x1 ?trans1;
@!P0 DMUL R2, R10, 8.98846567431157953865e+307 &wr=0x0 ?trans2;
@!P2 SEL R25, R17, 0x63400000, !P3 ?trans1;
LOP3.LUT R15, R15, 0x800fffff, R13, 0xf8, !PT ?trans1;
MUFU.RCP64H R19, R3 &req={0} &wr=0x0 ?trans1;
@!P0 LOP3.LUT R21, R3, 0x7ff00000, RZ, 0xc0, !PT ?WAIT2_END_GROUP;
@!P2 LOP3.LUT R25, R25, 0x80000000, R13, 0xf8, !PT ?trans2;
IADD3 R27, PT, PT, R21, -0x1, RZ ?trans2;
@!P2 LOP3.LUT R25, R25, 0x100000, RZ, 0xfc, !PT ?WAIT15_END_GROUP;
NOP ?WAIT8_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
@!P2 DFMA R14, R14, 2, -R24 &wr=0x1 ?trans2;
@!P2 LOP3.LUT R20, R15, 0x7ff00000, RZ, 0xc0, !PT &req={1} ?WAIT4_END_GROUP;
IADD3 R26, PT, PT, R20, -0x1, RZ ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R26, 0x7feffffe, PT ?WAIT5_END_GROUP;
ISETP.GT.U32.OR P0, PT, R27, 0x7feffffe, P0 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R22, R18, -R2, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R22, R22, R22, R22 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R22, R18, R22, R18 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R22, -R2, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R22, R18, R22 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R22, R18, R14 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R24, R22, -R2, R14 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R18, R24, R22 &req={0} &rd=0x0 &wr=0x1 ?trans2;
@P0 BRA 0x1040 &req={1,0} ?trans5;
LOP3.LUT R13, R11, 0x7ff00000, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R12, PT, PT, R16.reuse, -R13.reuse, RZ ?trans1;
ISETP.GE.U32.AND P0, PT, R16, R13, PT ?WAIT4_END_GROUP;
VIMNMX.S32 R12, R12, -0x46a00000, !PT ?trans1;
SEL R17, R17, 0x63400000, !P0 ?WAIT4_END_GROUP;
VIMNMX.S32 R12, R12, 0x46a00000, PT ?WAIT5_END_GROUP;
IADD3 R20, PT, PT, -R17, R12, RZ ?trans1;
MOV R12, RZ ?WAIT3_END_GROUP;
IADD3 R13, PT, PT, R20, 0x7fe00000, RZ ?WAIT6_END_GROUP;
DMUL R16, R18, R12 &wr=0x0 ?trans2;
FSETP.GTU.AND P0, PT, |R17|, 1.469367938527859385e-39, PT &req={0} ?WAIT13_END_GROUP;
@P0 BRA 0x1180 ?trans5;
DFMA R2, R18, -R2, R14 &wr=0x0 ?trans1;
MOV R12, RZ ?trans1;
FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT &req={0} ?trans1;
LOP3.LUT R11, R3, 0x80000000, R11, 0x48, !PT ?WAIT4_END_GROUP;
LOP3.LUT R13, R11, R13, RZ, 0xfc, !PT ?WAIT8_END_GROUP;
@!P0 BRA 0x1180 ?trans5;
IADD3 R3, PT, PT, -R20, RZ, RZ ?trans1;
MOV R2, RZ ?trans1;
DMUL.RP R12, R18, R12 &wr=0x0 ?trans2;
LOP3.LUT R11, R13, R11, RZ, 0x3c, !PT &req={0} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R16, -R2, R18 &wr=0x0 ?trans2;
IADD3 R2, PT, PT, -R20, -0x43300000, RZ &req={0} ?WAIT5_END_GROUP;
FSETP.NEU.AND P0, PT, |R3|, R2, PT ?WAIT5_END_GROUP;
FSEL R16, R12, R16, !P0 ?trans1;
FSEL R17, R11, R17, !P0 ?trans1;
BRA 0x1180 ?trans6;
DSETP.NAN.AND P0, PT, R12, R12, PT &wr=0x0 ?trans2;
@P0 BRA 0x1160 &req={0} ?trans5;
DSETP.NAN.AND P0, PT, R10, R10, PT &wr=0x0 ?trans2;
@P0 BRA 0x1130 &req={0} ?trans5;
ISETP.NE.AND P0, PT, R20, R21, PT ?trans1;
MOV.64 R16, 0xfff8000000000000 ?WAIT12_END_GROUP;
@!P0 BRA 0x1180 ?trans5;
ISETP.NE.AND P0, PT, R20, 0x7ff00000, PT ?trans1;
LOP3.LUT R17, R13, 0x80000000, R11, 0x48, !PT ?WAIT4_END_GROUP;
ISETP.EQ.OR P0, PT, R21, RZ, !P0 ?WAIT13_END_GROUP;
@P0 LOP3.LUT R2, R17, 0x7ff00000, RZ, 0xfc, !PT ?trans1;
@!P0 MOV R16, RZ ?trans1;
@P0 MOV R16, RZ ?WAIT3_END_GROUP;
@P0 MOV R17, R2 ?trans1;
BRA 0x1180 ?trans6;
LOP3.LUT R17, R11, 0x80000, RZ, 0xfc, !PT ?trans1;
MOV R16, R10 ?trans1;
BRA 0x1180 ?trans6;
LOP3.LUT R17, R13, 0x80000, RZ, 0xfc, !PT ?trans1;
MOV R16, R12 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B1 ?trans5;
MOV R2, R0 ?trans1;
HFMA2 R3, -RZ, RZ, 0, 0 ?WAIT4_END_GROUP;
RET.REL.NODEC R2 0x0 ?trans5;
BRA 0x11c0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: odeSolver(int, int, double*, double*, double*, double, double, double, double, double, double, double, double**, double**)
_Z9odeSolveriiPdS_S_dddddddPS_S0_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x74
s_load_b32 s3, s[0:1], 0x4
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s8, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_add_i32 s2, s3, 2
v_mad_u64_u32 v[3:4], null, s14, s8, v[0:1]
s_load_b128 s[4:7], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s2, v2, s[2:3]
v_add3_u32 v0, v3, v0, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b64 v[4:5], v[2:3], off
global_load_b64 v[6:7], v[0:1], off
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x20
s_load_b256 s[12:19], s[0:1], 0x40
s_waitcnt vmcnt(1) lgkmcnt(0)
v_mul_f64 v[8:9], v[4:5], s[10:11]
v_add_f64 v[10:11], v[4:5], -s[14:15]
v_add_f64 v[12:13], v[4:5], -1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[8:9], v[8:9], v[10:11]
v_mul_f64 v[8:9], v[12:13], v[8:9]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
v_fma_f64 v[4:5], -v[6:7], s[12:13], v[4:5]
global_store_b64 v[2:3], v[4:5], off
global_load_b64 v[2:3], v[0:1], off
v_add_f64 v[6:7], v[4:5], s[8:9]
s_waitcnt vmcnt(0)
v_mul_f64 v[8:9], v[2:3], s[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[10:11], null, v[6:7], v[6:7], v[8:9]
v_div_scale_f64 v[16:17], vcc_lo, v[8:9], v[6:7], v[8:9]
v_rcp_f64_e32 v[12:13], v[10:11]
s_waitcnt_depctr 0xfff
v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
v_mul_f64 v[14:15], v[16:17], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[10:11], v[14:15], v[16:17]
v_div_fmas_f64 v[10:11], v[10:11], v[12:13], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fixup_f64 v[6:7], v[10:11], v[6:7], v[8:9]
v_add_f64 v[8:9], v[4:5], -s[16:17]
v_mul_f64 v[4:5], v[4:5], s[10:11]
v_add_f64 v[6:7], v[6:7], s[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[8:9], v[8:9], -1.0
v_mul_f64 v[6:7], v[6:7], s[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], -v[4:5], v[8:9], -v[2:3]
v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| odeSolver | 5,449 | 1,852 | stackv2-00000-of-00015 |
// Demangled: pdeSolver(int, int, double*, double*, double)
Function : _Z9pdeSolveriiPdS_d
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R3, SR_TID.Y &wr=0x0 ?trans7;
S2UR UR5, SR_CTAID.Y &wr=0x0 ?trans1;
LDCU UR4, c[0x0][0x384] &wr=0x1 ?trans1;
S2R R5, SR_TID.X &wr=0x2 ?trans6;
LDC R0, c[0x0][0x364] &wr=0x0 ?trans8;
S2UR UR6, SR_CTAID.X &wr=0x2 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x2, URZ &req={1} ?WAIT7_END_GROUP;
LDC R2, c[0x0][0x360] &wr=0x2 ?trans8;
LDC.64 R12, c[0x0][0x388] &wr=0x1 ?trans1;
IMAD R0, R0, UR5, R3 &req={0} ?WAIT7_END_GROUP;
LDC.64 R14, c[0x0][0x398] &wr=0x0 ?trans1;
IMAD R3, R2, UR6, R5 &req={2} ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x2 ?trans1;
IADD3 R2, PT, PT, R0, 0x1, RZ ?WAIT3_END_GROUP;
IADD3 R3, PT, PT, R3, 0x1, RZ ?WAIT5_END_GROUP;
IMAD R17, R2, UR4, R3.reuse ?trans2;
IMAD R5, R0, UR4, R3 ?trans2;
IMAD.WIDE R2, R17.reuse, 0x8, R12 &req={1} ?trans1;
IADD3 R11, PT, PT, R17, UR4, RZ ?WAIT4_END_GROUP;
LDG.E.64 R6, desc[UR6][R2.64+0x8] &req={2} &wr=0x2 ?trans1;
IMAD.WIDE R10, R11, 0x8, R12 ?WAIT3_END_GROUP;
LDG.E.64 R8, desc[UR6][R2.64+-0x8] &wr=0x2 ?trans1;
IMAD.WIDE R12, R5, 0x8, R12 ?WAIT3_END_GROUP;
LDG.E.64 R4, desc[UR6][R2.64] &wr=0x3 ?trans4;
LDG.E.64 R10, desc[UR6][R10.64] &wr=0x4 ?trans4;
LDG.E.64 R12, desc[UR6][R12.64] &wr=0x5 ?trans1;
DADD R6, R6, R8 &req={2} &rd=0x1 &wr=0x3 ?trans2;
LDC.64 R8, c[0x0][0x390] &req={1} &wr=0x1 ?trans2;
IMAD.WIDE R8, R17, 0x8, R8 &req={1} ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R6, R4, -4, R6 &req={3} &wr=0x4 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R6, R6, R10 &req={4} &wr=0x5 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R6, R6, R12 &req={5} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R6, R6, R14, R4 &req={0} &wr=0x0 ?trans2;
STG.E.64 desc[UR6][R8.64], R6 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x330;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: pdeSolver(int, int, double*, double*, double)
_Z9pdeSolveriiPdS_d:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x4
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_add_i32 s3, s3, 2
v_mad_u64_u32 v[3:4], null, s14, s2, v[0:1]
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v11, v2, s3
v_add_nc_u32_e32 v12, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, s3, v11
v_add_nc_u32_e32 v11, v12, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v0, v2, v12
v_add_nc_u32_e32 v3, v2, v3
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v1, s3, v0
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[11:12], 3, v[11:12]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 3, v[3:4]
v_lshlrev_b64 v[1:2], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_clause 0x2
global_load_b64 v[5:6], v[1:2], off
global_load_b64 v[7:8], v[3:4], off offset:16
global_load_b64 v[2:3], v[3:4], off
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
v_add_co_u32 v9, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v11, vcc_lo, s4, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
global_load_b64 v[9:10], v[9:10], off
v_add_co_u32 v0, vcc_lo, s6, v0
global_load_b64 v[11:12], v[11:12], off
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(2)
v_add_f64 v[2:3], v[7:8], v[2:3]
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[9:10], -4.0, v[2:3]
v_add_f64 v[2:3], v[5:6], v[2:3]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[11:12], v[2:3]
v_fma_f64 v[2:3], v[2:3], s[0:1], v[9:10]
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| pdeSolver | 1,154 | 1,495 | stackv2-00000-of-00015 |
// Demangled: vecAdd(int*, int*, int*, int*, int)
Function : _Z6vecAddPiS_S_S_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R11, SR_TID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R0, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x3a0] &wr=0x2 ?trans1;
IMAD R11, R0, UR4, R11 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R11, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD.WIDE R2, R11, 0x4, R2 &req={0} ?WAIT7_END_GROUP;
LDC.64 R8, c[0x0][0x398] &wr=0x0 ?trans1;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x4 ?trans1;
IMAD.WIDE R4, R11, 0x4, R4 &req={2} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR4][R4.64] &wr=0x4 ?trans1;
IMAD.WIDE R6, R11, 0x4, R6 &req={3} ?WAIT6_END_GROUP;
LDG.E R6, desc[UR4][R6.64] &wr=0x4 ?trans1;
IMAD.WIDE R8, R11, 0x4, R8 &req={0} ?trans1;
IADD3 R11, PT, PT, R6, R5, R2 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R8.64], R11 ?trans1;
EXIT ?trans5;
BRA 0x170;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: vecAdd(int*, int*, int*, int*, int)
_Z6vecAddPiS_S_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b256 s[0:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v6, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add3_u32 v2, v3, v2, v4
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| vecAdd | 663 | 616 | stackv2-00000-of-00015 |
// Demangled: relabel_k(float const*, float const*, int, int, int*)
Function : _Z9relabel_kPKfS0_iiPi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x390] &wr=0x2 ?trans7;
LDC R3, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R0, R3, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC R8, c[0x0][0x394] &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x1 ?trans1;
HFMA2 R4, -RZ, RZ, 0, 0 ?trans1;
ISETP.GE.AND P0, PT, R8, 0x1, PT &req={0} ?WAIT13_END_GROUP;
@!P0 BRA 0xe70 &req={1} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
ISETP.GE.U32.AND P1, PT, R8.reuse, 0x10, PT ?trans1;
LOP3.LUT R9, R8, 0xf, RZ, 0xc0, !PT ?trans1;
CS2R R4, SRZ ?trans1;
MOV R7, 0x3f800000 ?WAIT3_END_GROUP;
ISETP.NE.AND P0, PT, R9, RZ, PT ?trans1;
IMAD.WIDE R2, R0, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E R6, desc[UR6][R2.64] &rd=0x0 &wr=0x5 ?trans1;
@!P1 BRA 0x800 ?trans6;
LDCU.64 UR4, c[0x0][0x388] &wr=0x1 ?trans1;
HFMA2 R5, -RZ, RZ, 0, 0 ?trans1;
LOP3.LUT R10, R8, 0x7ffffff0, RZ, 0xc0, !PT ?trans1;
MOV R7, 0x3f800000 ?trans1;
UIADD3.64 UR4, UPT, UPT, UR4, 0x20, URZ &req={1} ?WAIT6_END_GROUP;
MOV.64 R2, UR4 &req={0} ?WAIT8_END_GROUP;
LDG.E R33, desc[UR6][R2.64+-0x20] &wr=0x2 ?trans4;
LDG.E R35, desc[UR6][R2.64+-0x1c] &wr=0x3 ?trans4;
LDG.E R37, desc[UR6][R2.64+-0x18] &wr=0x4 ?trans4;
LDG.E R14, desc[UR6][R2.64+-0x14] &wr=0x4 ?trans4;
LDG.E R16, desc[UR6][R2.64+-0x10] &wr=0x4 ?trans4;
LDG.E R29, desc[UR6][R2.64+-0xc] &wr=0x4 ?trans4;
LDG.E R31, desc[UR6][R2.64+-0x8] &wr=0x4 ?trans4;
LDG.E R11, desc[UR6][R2.64+-0x4] &wr=0x4 ?trans4;
LDG.E R27, desc[UR6][R2.64] &wr=0x4 ?trans4;
LDG.E R25, desc[UR6][R2.64+0x4] &wr=0x4 ?trans4;
LDG.E R23, desc[UR6][R2.64+0x8] &wr=0x4 ?trans4;
LDG.E R21, desc[UR6][R2.64+0xc] &wr=0x4 ?trans4;
LDG.E R19, desc[UR6][R2.64+0x10] &wr=0x4 ?trans4;
LDG.E R17, desc[UR6][R2.64+0x14] &wr=0x4 ?trans4;
LDG.E R15, desc[UR6][R2.64+0x18] &wr=0x4 ?trans4;
LDG.E R13, desc[UR6][R2.64+0x1c] &rd=0x0 &wr=0x4 ?trans2;
IADD.64 R2, R2, 0x40 &req={0} ?WAIT2_END_GROUP;
FADD R33, R6, -R33 &req={5,2} ?WAIT4_END_GROUP;
FMUL R12, R33, R33 ?trans1;
FADD R35, R6.reuse, -R35 &req={3} ?trans1;
FADD R37, R6, -R37 &req={4} ?WAIT3_END_GROUP;
FSETP.GTU.AND P2, PT, R12, R7, PT ?trans1;
FADD R14, R6, -R14 ?WAIT4_END_GROUP;
FSEL R7, R12, R7, !P2 ?trans1;
FMUL R12, R35, R35 ?trans1;
FMUL R14, R14, R14 ?trans1;
FADD R16, R6, -R16 ?trans1;
SEL R4, R5, R4, !P2 ?trans2;
FSETP.GTU.AND P3, PT, R12, R7.reuse, PT ?trans1;
FMUL R16, R16, R16 ?trans1;
FADD R29, R6.reuse, -R29 ?trans1;
FADD R31, R6, -R31 ?trans2;
FSEL R7, R12, R7, !P3 ?trans1;
FMUL R12, R37, R37 ?trans1;
FADD R11, R6, -R11 ?WAIT4_END_GROUP;
FSETP.GTU.AND P4, PT, R12, R7, PT ?trans1;
FADD R27, R6, -R27 ?trans1;
@!P3 IADD3 R4, PT, PT, R5, 0x1, RZ ?WAIT3_END_GROUP;
FSEL R7, R12, R7, !P4 ?trans1;
FMUL R12, R29, R29 ?trans1;
FADD R25, R6.reuse, -R25 ?trans1;
FADD R23, R6, -R23 ?trans2;
FSETP.GTU.AND P1, PT, R14, R7, PT ?WAIT3_END_GROUP;
@!P4 IADD3 R4, PT, PT, R5, 0x2, RZ ?trans1;
FADD R21, R6, -R21 ?trans1;
FSEL R7, R14, R7, !P1 ?trans1;
FADD R19, R6, -R19 ?WAIT4_END_GROUP;
FSETP.GTU.AND P6, PT, R16, R7.reuse, PT ?trans1;
FADD R17, R6, -R17 ?trans2;
@!P1 IADD3 R4, PT, PT, R5, 0x3, RZ ?trans2;
FSEL R7, R16, R7, !P6 ?trans1;
FADD R15, R6.reuse, -R15 ?trans1;
FADD R13, R6, -R13 ?WAIT3_END_GROUP;
FSETP.GTU.AND P5, PT, R12, R7, PT ?WAIT3_END_GROUP;
@!P6 IADD3 R4, PT, PT, R5, 0x4, RZ ?trans1;
FMUL R14, R13, R13 ?trans1;
FSEL R7, R12, R7, !P5 ?trans1;
FMUL R12, R31, R31 ?WAIT5_END_GROUP;
FSETP.GTU.AND P2, PT, R12, R7, PT ?trans2;
@!P5 IADD3 R4, PT, PT, R5, 0x5, RZ ?WAIT3_END_GROUP;
FSEL R7, R12, R7, !P2 ?trans1;
FMUL R12, R11, R11 ?WAIT5_END_GROUP;
FSETP.GTU.AND P3, PT, R12, R7, PT ?trans2;
@!P2 IADD3 R4, PT, PT, R5, 0x6, RZ ?WAIT3_END_GROUP;
FSEL R7, R12, R7, !P3 ?trans1;
FMUL R12, R27, R27 ?WAIT5_END_GROUP;
FSETP.GTU.AND P4, PT, R12, R7, PT ?trans2;
@!P3 IADD3 R4, PT, PT, R5, 0x7, RZ ?WAIT3_END_GROUP;
FSEL R7, R12, R7, !P4 ?trans1;
FMUL R12, R25, R25 ?WAIT5_END_GROUP;
FSETP.GTU.AND P1, PT, R12, R7, PT ?trans2;
@!P4 IADD3 R4, PT, PT, R5, 0x8, RZ ?WAIT3_END_GROUP;
FSEL R7, R12, R7, !P1 ?trans1;
FMUL R12, R23, R23 ?WAIT5_END_GROUP;
FSETP.GTU.AND P6, PT, R12, R7, PT ?trans2;
@!P1 IADD3 R4, PT, PT, R5, 0x9, RZ ?WAIT3_END_GROUP;
FSEL R7, R12, R7, !P6 ?trans1;
FMUL R12, R21, R21 ?WAIT5_END_GROUP;
FSETP.GTU.AND P5, PT, R12, R7, PT ?trans2;
@!P6 IADD3 R4, PT, PT, R5, 0xa, RZ ?WAIT3_END_GROUP;
FSEL R7, R12, R7, !P5 ?trans1;
FMUL R12, R19, R19 ?WAIT5_END_GROUP;
FSETP.GTU.AND P2, PT, R12, R7, PT ?trans2;
@!P5 IADD3 R4, PT, PT, R5, 0xb, RZ ?WAIT3_END_GROUP;
FSEL R7, R12, R7, !P2 ?trans1;
FMUL R12, R17, R17 ?WAIT5_END_GROUP;
FSETP.GTU.AND P3, PT, R12, R7, PT ?trans2;
@!P2 IADD3 R4, PT, PT, R5, 0xc, RZ ?WAIT3_END_GROUP;
FSEL R7, R12, R7, !P3 ?trans1;
FMUL R12, R15, R15 ?WAIT5_END_GROUP;
FSETP.GTU.AND P1, PT, R12, R7, PT ?trans2;
@!P3 IADD3 R4, PT, PT, R5, 0xd, RZ ?WAIT3_END_GROUP;
FSEL R7, R12, R7, !P1 ?WAIT5_END_GROUP;
FSETP.GTU.AND P2, PT, R14, R7, PT ?WAIT3_END_GROUP;
@!P1 IADD3 R4, PT, PT, R5, 0xe, RZ ?trans2;
FSEL R7, R14, R7, !P2 ?WAIT8_END_GROUP;
@!P2 IADD3 R4, PT, PT, R5.reuse, 0xf, RZ ?trans2;
IADD3 R5, PT, PT, R5, 0x10, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R5, R10, PT ?WAIT13_END_GROUP;
@P1 BRA 0x1c0 ?trans5;
@!P0 BRA 0xe70 ?trans5;
ISETP.GE.U32.AND P1, PT, R9, 0x8, PT ?trans1;
LOP3.LUT R12, R8, 0x7, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R12, RZ, PT ?WAIT7_END_GROUP;
@!P1 BRA 0xb80 ?trans6;
LDC.64 R2, c[0x0][0x388] &req={0} &wr=0x0 ?trans2;
IMAD.WIDE.U32 R2, R5, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E R9, desc[UR6][R2.64] &wr=0x2 ?trans4;
LDG.E R11, desc[UR6][R2.64+0x4] &wr=0x3 ?trans4;
LDG.E R13, desc[UR6][R2.64+0x8] &wr=0x4 ?trans4;
LDG.E R15, desc[UR6][R2.64+0xc] &wr=0x4 ?trans4;
LDG.E R17, desc[UR6][R2.64+0x10] &wr=0x4 ?trans4;
LDG.E R19, desc[UR6][R2.64+0x14] &wr=0x4 ?trans4;
LDG.E R21, desc[UR6][R2.64+0x18] &wr=0x4 ?trans4;
LDG.E R23, desc[UR6][R2.64+0x1c] &rd=0x0 &wr=0x4 ?trans1;
FADD R9, R6, -R9 &req={5,2} ?WAIT4_END_GROUP;
FMUL R10, R9, R9 ?trans1;
FADD R11, R6.reuse, -R11 &req={3} ?trans1;
FADD R13, R6, -R13 &req={4} ?WAIT3_END_GROUP;
FSETP.GTU.AND P3, PT, R10, R7, PT ?trans1;
FADD R15, R6, -R15 ?WAIT4_END_GROUP;
FSEL R7, R10, R7, !P3 ?trans1;
FMUL R10, R11, R11 ?trans1;
FMUL R2, R15, R15 &req={0} ?trans1;
FADD R17, R6, -R17 ?trans1;
SEL R4, R5, R4, !P3 ?trans2;
FSETP.GTU.AND P4, PT, R10, R7, PT ?trans1;
FMUL R17, R17, R17 ?trans1;
FADD R19, R6.reuse, -R19 ?trans1;
FADD R21, R6, -R21 ?trans2;
FSEL R7, R10, R7, !P4 ?trans1;
FMUL R10, R13, R13 ?trans1;
FMUL R19, R19, R19 ?trans1;
FMUL R21, R21, R21 ?trans1;
FADD R23, R6, -R23 ?WAIT2_END_GROUP;
FSETP.GTU.AND P5, PT, R10, R7, PT ?trans2;
@!P4 IADD3 R4, PT, PT, R5, 0x1, RZ ?WAIT3_END_GROUP;
FSEL R7, R10, R7, !P5 ?WAIT5_END_GROUP;
FSETP.GTU.AND P2, PT, R2, R7, PT ?WAIT3_END_GROUP;
@!P5 IADD3 R4, PT, PT, R5, 0x2, RZ ?trans2;
FSEL R2, R2, R7, !P2 ?trans1;
FMUL R7, R23, R23 ?WAIT4_END_GROUP;
FSETP.GTU.AND P1, PT, R17, R2, PT ?WAIT3_END_GROUP;
@!P2 IADD3 R4, PT, PT, R5, 0x3, RZ ?trans2;
FSEL R2, R17, R2, !P1 ?WAIT5_END_GROUP;
FSETP.GTU.AND P3, PT, R19, R2, PT ?WAIT3_END_GROUP;
@!P1 IADD3 R4, PT, PT, R5, 0x4, RZ ?trans2;
FSEL R2, R19, R2, !P3 ?WAIT5_END_GROUP;
FSETP.GTU.AND P4, PT, R21, R2, PT ?WAIT3_END_GROUP;
@!P3 IADD3 R4, PT, PT, R5, 0x5, RZ ?trans2;
FSEL R2, R21, R2, !P4 ?WAIT5_END_GROUP;
FSETP.GTU.AND P1, PT, R7, R2, PT ?WAIT3_END_GROUP;
@!P4 IADD3 R4, PT, PT, R5, 0x6, RZ ?trans2;
FSEL R7, R7, R2, !P1 ?WAIT8_END_GROUP;
@!P1 IADD3 R4, PT, PT, R5.reuse, 0x7, RZ ?trans2;
IADD3 R5, PT, PT, R5, 0x8, RZ ?WAIT7_END_GROUP;
@!P0 BRA 0xe70 ?trans5;
ISETP.GE.U32.AND P0, PT, R12, 0x4, PT ?trans1;
LOP3.LUT R8, R8, 0x3, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R8, RZ, PT ?WAIT7_END_GROUP;
@!P0 BRA 0xd80 ?trans6;
LDC.64 R2, c[0x0][0x388] &req={0} &wr=0x0 ?trans2;
IMAD.WIDE.U32 R2, R5, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E R9, desc[UR6][R2.64] &wr=0x2 ?trans4;
LDG.E R11, desc[UR6][R2.64+0x4] &wr=0x3 ?trans4;
LDG.E R13, desc[UR6][R2.64+0x8] &wr=0x4 ?trans4;
LDG.E R15, desc[UR6][R2.64+0xc] &wr=0x4 ?trans1;
FADD R9, R6, -R9 &req={5,2} ?WAIT4_END_GROUP;
FMUL R10, R9, R9 ?trans1;
FADD R11, R6.reuse, -R11 &req={3} ?trans1;
FADD R13, R6, -R13 &req={4} ?WAIT3_END_GROUP;
FSETP.GTU.AND P0, PT, R10, R7, PT ?trans1;
FMUL R12, R13, R13 ?trans1;
FADD R15, R6, -R15 ?WAIT3_END_GROUP;
FSEL R7, R10, R7, !P0 ?trans1;
FMUL R10, R11, R11 ?trans1;
SEL R4, R5, R4, !P0 ?trans1;
FMUL R2, R15, R15 ?WAIT3_END_GROUP;
FSETP.GTU.AND P2, PT, R10, R7, PT ?WAIT5_END_GROUP;
FSEL R7, R10, R7, !P2 ?WAIT5_END_GROUP;
FSETP.GTU.AND P3, PT, R12, R7, PT ?WAIT3_END_GROUP;
@!P2 IADD3 R4, PT, PT, R5, 0x1, RZ ?trans2;
FSEL R7, R12, R7, !P3 ?WAIT5_END_GROUP;
FSETP.GTU.AND P0, PT, R2, R7, PT ?WAIT3_END_GROUP;
@!P3 IADD3 R4, PT, PT, R5, 0x2, RZ ?trans2;
FSEL R7, R2, R7, !P0 ?WAIT8_END_GROUP;
@!P0 IADD3 R4, PT, PT, R5.reuse, 0x3, RZ ?trans2;
IADD3 R5, PT, PT, R5, 0x4, RZ ?WAIT7_END_GROUP;
@!P1 BRA 0xe70 ?trans5;
LDC.64 R2, c[0x0][0x388] &req={0} &wr=0x0 ?trans1;
IADD3 R8, PT, PT, -R8, RZ, RZ ?trans1;
IMAD.WIDE.U32 R2, R5, 0x4, R2 &req={0} ?WAIT7_END_GROUP;
LDG.E R9, desc[UR6][R2.64] &rd=0x0 &wr=0x2 ?trans1;
IADD3 R8, PT, PT, R8, 0x1, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R8, RZ, PT ?trans1;
IADD.64 R2, R2, 0x4 &req={0} ?trans2;
FADD R9, R6, -R9 &req={5,2} ?WAIT4_END_GROUP;
FMUL R10, R9, R9 ?WAIT5_END_GROUP;
FSETP.GTU.AND P0, PT, R10, R7, PT ?WAIT5_END_GROUP;
SEL R4, R5.reuse, R4, !P0 ?trans1;
FSEL R7, R10, R7, !P0 ?trans1;
IADD3 R5, PT, PT, R5, 0x1, RZ ?trans1;
@P1 BRA 0xdc0 ?trans6;
LDC.64 R2, c[0x0][0x398] &req={0} &wr=0x0 ?trans2;
IMAD.WIDE R2, R0, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R4 ?trans1;
EXIT ?trans5;
BRA 0xeb0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: relabel_k(float const*, float const*, int, int, int*)
_Z9relabel_kPKfS0_iiPi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_6
v_ashrrev_i32_e32 v2, 31, v1
s_cmp_lt_i32 s3, 1
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v4, 1.0
s_mov_b32 s2, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
global_load_b32 v3, v[2:3], off
v_mov_b32_e32 v2, 0
.LBB0_3:
s_load_b32 s4, s[6:7], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_subrev_f32_e32 v5, s4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v5, v5
v_cmp_nle_f32_e32 vcc_lo, v5, v4
v_cndmask_b32_e32 v2, s2, v2, vcc_lo
s_add_i32 s2, s2, 1
v_cndmask_b32_e32 v4, v5, v4, vcc_lo
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s3, s2
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| relabel_k | 5,692 | 834 | stackv2-00000-of-00015 |
// Demangled: AddArray(float*, float*)
Function : _Z8AddArrayPfS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
LDC R0, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R8, SR_TID.X &wr=0x2 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x3 ?trans6;
S2UR UR6, SR_CTAID.X &wr=0x2 ?trans8;
LDC.64 R2, c[0x0][0x380] &wr=0x4 ?trans1;
ISETP.GE.U32.AND P0, PT, R0.reuse, 0x2, PT &req={1} ?trans1;
IMAD R9, R0, UR6, R8 &req={2} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={4} ?WAIT8_END_GROUP;
@!P0 BRA 0x1a0 &req={3,0} ?trans5;
LDC.64 R6, c[0x0][0x380] &wr=0x0 ?trans2;
SHF.R.U32.HI R10, RZ, 0x1, R0 ?trans1;
BSSY.RECONVERGENT B0, 0x160 ?trans4;
ISETP.GE.U32.AND P0, PT, R8, R10, PT ?WAIT13_END_GROUP;
@P0 BRA 0x150 &req={1} ?trans5;
IADD3 R5, PT, PT, R9, R10, RZ ?trans1;
LDG.E R11, desc[UR4][R2.64] &wr=0x2 ?trans4;
IMAD.WIDE.U32 R4, R5, 0x4, R6 &req={0} ?WAIT6_END_GROUP;
LDG.E R4, desc[UR4][R4.64] &wr=0x2 ?trans2;
FADD R11, R4, R11 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R11 &rd=0x1 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P0, PT, R0, 0x3, PT ?trans1;
MOV R0, R10 ?WAIT12_END_GROUP;
@P0 BRA 0xb0 ?trans5;
ISETP.NE.AND P0, PT, R8, RZ, PT ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LDG.E R3, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans1;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans3;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR4][R4.64], R3 &req={2} ?trans1;
EXIT ?trans5;
BRA 0x200;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: AddArray(float*, float*)
_Z8AddArrayPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_cmp_lt_u32 s4, 2
s_cbranch_scc1 .LBB0_5
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v2, v3
v_lshlrev_b64 v[4:5], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
.LBB0_2:
s_lshr_b32 s5, s4, 1
s_mov_b32 s6, exec_lo
v_cmpx_gt_u32_e64 s5, v0
s_cbranch_execz .LBB0_4
v_add_nc_u32_e32 v2, s5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_add_co_u32 v6, vcc_lo, s0, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
s_clause 0x1
global_load_b32 v2, v[6:7], off
global_load_b32 v6, v[4:5], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v6
global_store_b32 v[4:5], v2, off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s6
s_cmp_lt_u32 s4, 4
s_mov_b32 s4, s5
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_5:
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_11
v_mov_b32_e32 v2, 0
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_bfrev_b32_e32 v2, 1
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v0, v[0:1], off
.LBB0_7:
s_ctz_i32_b32 s0, s4
s_waitcnt vmcnt(0)
v_readlane_b32 s1, v0, s0
s_lshl_b32 s0, 1, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s4, s4, s0
s_cmp_lg_u32 s4, 0
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v2, s1, v2
s_cbranch_scc1 .LBB0_7
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_mov_b32 s0, 0
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB0_11
v_mov_b32_e32 v3, 0
global_load_b32 v1, v3, s[2:3]
.LBB0_10:
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v1, v2
global_atomic_cmpswap_b32 v0, v3, v[0:1], s[2:3] glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v0, v1
v_mov_b32_e32 v1, v0
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_10
.LBB0_11:
s_endpgm
| AddArray | 843 | 1,363 | stackv2-00000-of-00015 |
// Demangled: AtualizaC_1(aresta_E*, int*, int*, int)
Function : _Z11AtualizaC_1P8aresta_EPiS1_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R5, SR_TID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R0, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x398] &wr=0x2 ?trans1;
IMAD R5, R0, UR4, R5 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R5, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R6, c[0x0][0x388] &wr=0x2 ?trans1;
IMAD.WIDE R2, R5, 0x8, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E R5, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans4;
LDG.E R9, desc[UR4][R2.64+0x4] &wr=0x3 ?trans1;
IMAD.WIDE R4, R5, 0x4, R6 &req={2} ?WAIT4_END_GROUP;
IMAD.WIDE R6, R9, 0x4, R6 &req={3} ?trans2;
LDG.E R9, desc[UR4][R4.64] &wr=0x2 ?trans4;
LDG.E R0, desc[UR4][R6.64] &wr=0x2 ?trans2;
ISETP.GE.AND P0, PT, R9, R0, PT &req={2} ?WAIT13_END_GROUP;
@P0 BRA 0x190 ?trans5;
LDC.64 R2, c[0x0][0x390] &wr=0x0 ?trans1;
HFMA2 R5, -RZ, RZ, 0, 5.9604644775390625e-08 ?trans1;
REDG.E.MIN.S32.STRONG.GPU desc[UR4][R6.64], R9 ?trans4;
STG.E desc[UR4][R2.64], R5 &req={0} ?trans1;
EXIT ?trans5;
ISETP.GE.AND P0, PT, R0, R9, PT ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LDC.64 R2, c[0x0][0x390] &wr=0x0 ?trans1;
HFMA2 R7, -RZ, RZ, 0, 5.9604644775390625e-08 ?trans1;
REDG.E.MIN.S32.STRONG.GPU desc[UR4][R4.64], R0 ?trans4;
STG.E desc[UR4][R2.64], R7 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x200;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: AtualizaC_1(aresta_E*, int*, int*, int)
_Z11AtualizaC_1P8aresta_EPiS1_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB5_9
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s2, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b64 v[0:1], v[0:1], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v3, 31, v0
v_mov_b32_e32 v2, v0
v_ashrrev_i32_e32 v5, 31, v1
v_mov_b32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_lshlrev_b64 v[2:3], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_clause 0x1
global_load_b32 v4, v[0:1], off
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(0)
v_cmpx_ge_i32_e64 v4, v5
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB5_5
s_mov_b32 s4, exec_lo
v_cmpx_lt_i32_e64 v5, v4
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB5_4
global_atomic_min_i32 v[0:1], v5, off
s_mov_b32 s2, exec_lo
.LBB5_4:
s_or_b32 exec_lo, exec_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s2, s2, exec_lo
.LBB5_5:
s_and_not1_saveexec_b32 s3, s3
s_cbranch_execz .LBB5_7
global_atomic_min_i32 v[2:3], v4, off
s_or_b32 s2, s2, exec_lo
.LBB5_7:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB5_9
s_load_b64 s[0:1], s[0:1], 0x10
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB5_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| AtualizaC_1 | 905 | 1,171 | stackv2-00000-of-00015 |
// Demangled: AtualizaC_3(int*, int, char*)
Function : _Z11AtualizaC_3PiiPc
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R4, SR_TID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R5, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x388] &wr=0x2 ?trans1;
IMAD R4, R5, UR4, R4 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R4, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDCU.64 UR6, c[0x0][0x390] &wr=0x0 ?trans1;
SHF.R.S32.HI R5, RZ, 0x1f, R4 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans4;
IADD.64 R2, R4, UR6 &req={0} ?WAIT7_END_GROUP;
LDG.E.U8 R2, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans2;
ISETP.NE.AND P0, PT, R2, RZ, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LDCU.64 UR6, c[0x0][0x380] &wr=0x0 ?trans2;
LEA R2, P0, R4, UR6, 0x2 &req={0} ?WAIT4_END_GROUP;
LEA.HI.X R3, R4, UR7, R5, 0x2, P0 ?trans2;
LDC.64 R4, c[0x0][0x380] &wr=0x0 ?trans3;
LDG.E R7, desc[UR4][R2.64] &wr=0x0 ?trans2;
IMAD.WIDE R4, R7, 0x4, R4 &req={0} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans4;
STG.E desc[UR4][R2.64], R5 &req={2} ?trans1;
EXIT ?trans5;
BRA 0x180;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: AtualizaC_3(int*, int, char*)
_Z11AtualizaC_3PiiPc:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB7_3
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
global_load_u8 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, 0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB7_3
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB7_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| AtualizaC_3 | 683 | 737 | stackv2-00000-of-00015 |
// Demangled: Calcula_num_zerodiff(aresta*, float*, int, int*, unsigned int*, unsigned int*, double*)
Function : _Z20Calcula_num_zerodiffP6arestaPfiPiPjS3_Pd
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R9, SR_TID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R0, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x390] &wr=0x2 ?trans1;
IMAD R9, R0, UR4, R9 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R9, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD.WIDE R2, R9, 0xc, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR4][R2.64+0x8] &req={1} &wr=0x2 ?trans2;
ISETP.NE.AND P0, PT, R0, RZ, PT &req={2} ?WAIT13_END_GROUP;
@!P0 EXIT ?trans5;
S2R R15, SR_LANEID &wr=0x0 ?trans1;
VOTEU.ANY UR6, UPT, PT ?trans1;
LDC.64 R4, c[0x0][0x3a0] &wr=0x1 ?trans1;
FLO.U32 R0, UR6 &wr=0x0 ?trans1;
S2R R8, SR_LTMASK &wr=0x2 ?trans6;
LDC.64 R6, c[0x0][0x398] &wr=0x3 ?trans1;
POPC R13, UR6 &wr=0x1 ?trans1;
ISETP.EQ.U32.AND P0, PT, R0, R15, PT &req={0} ?WAIT13_END_GROUP;
@P0 ATOMG.E.ADD.STRONG.GPU PT, R5, desc[UR4][R4.64], R13 &req={1} &wr=0x4 ?trans1;
LOP3.LUT R8, R8, UR6, RZ, 0xc0, !PT &req={2} ?WAIT6_END_GROUP;
POPC R8, R8 &wr=0x0 ?trans1;
SHFL.IDX PT, R11, R5, R0, 0x1f &req={4} &wr=0x0 ?trans2;
IADD3 R11, PT, PT, R11, R8, RZ &req={0} ?WAIT5_END_GROUP;
IMAD.WIDE R6, R11, 0x4, R6 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 &rd=0x0 ?trans4;
LDG.E R2, desc[UR4][R2.64+0x8] &wr=0x2 ?trans2;
ISETP.NE.AND P0, PT, R2, 0x2, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
VOTEU.ANY UR6, UPT, PT ?trans1;
LDC.64 R2, c[0x0][0x3a8] &wr=0x0 ?trans1;
UFLO.U32 UR7, UR6 ?trans2;
POPC R5, UR6 &wr=0x0 ?trans4;
ISETP.EQ.U32.AND P0, PT, R15, UR7, PT ?WAIT13_END_GROUP;
@P0 REDG.E.ADD.STRONG.GPU desc[UR4][R2.64], R5 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x270;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: Calcula_num_zerodiff(aresta*, float*, int, int*, unsigned int*, unsigned int*, double*)
_Z20Calcula_num_zerodiffP6arestaPfiPiPjS3_Pd:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB3_4
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[2:3], null, v1, 12, s[2:3]
global_load_b32 v0, v[2:3], off offset:8
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB3_4
s_load_b128 s[4:7], s[0:1], 0x18
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v4, -1
s_waitcnt lgkmcnt(0)
global_atomic_inc_u32 v5, v0, v4, s[6:7] glc
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, 8
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
global_store_b32 v[5:6], v1, off
global_load_b32 v1, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 2, v1
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB3_4
s_load_b64 s[0:1], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
global_atomic_inc_u32 v0, v4, s[0:1]
.LBB3_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| Calcula_num_zerodiff | 1,059 | 779 | stackv2-00000-of-00015 |
// Demangled: DefineNovosVU(int*, int, char*, unsigned int*)
Function : _Z13DefineNovosVUPiiPcPj
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R2, SR_TID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R3, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x388] &wr=0x2 ?trans1;
IMAD R2, R3, UR4, R2 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R2, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R4, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD.WIDE R4, R2, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
LDG.E R7, desc[UR4][R4.64] &req={1} &wr=0x2 ?trans2;
ISETP.NE.AND P0, PT, R7, R2, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
S2R R3, SR_LANEID &wr=0x0 ?trans1;
VOTEU.ANY UR6, UPT, PT ?trans1;
LDC.64 R6, c[0x0][0x398] &wr=0x1 ?trans1;
FLO.U32 R0, UR6 &wr=0x0 ?trans1;
LDCU.64 UR8, c[0x0][0x390] &wr=0x2 ?trans1;
POPC R11, UR6 &wr=0x1 ?trans1;
ISETP.EQ.U32.AND P0, PT, R0, R3, PT &req={0} ?WAIT13_END_GROUP;
@P0 ATOMG.E.ADD.STRONG.GPU PT, R7, desc[UR4][R6.64], R11 &req={1} &wr=0x3 ?trans1;
HFMA2 R10, -RZ, RZ, 0, 5.9604644775390625e-08 ?trans1;
S2R R3, SR_LTMASK &wr=0x0 ?trans2;
LOP3.LUT R8, R3, UR6, RZ, 0xc0, !PT &req={0} ?trans2;
SHF.R.S32.HI R3, RZ, 0x1f, R2 ?WAIT4_END_GROUP;
POPC R8, R8 &wr=0x0 ?trans1;
IADD.64 R2, R2, UR8 &req={2} ?trans2;
SHFL.IDX PT, R9, R7, R0, 0x1f &req={3} &wr=0x0 ?trans2;
IADD3 R9, PT, PT, R9, R8, RZ &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64], R9 ?trans4;
STG.E.U8 desc[UR4][R2.64], R10 ?trans1;
EXIT ?trans5;
BRA 0x210;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: DefineNovosVU(int*, int, char*, unsigned int*)
_Z13DefineNovosVUPiiPcPj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB6_3
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v0, v1
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB6_3
s_load_b128 s[0:3], s[0:1], 0x10
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v5, -1
v_mov_b32_e32 v6, 1
s_waitcnt lgkmcnt(0)
global_atomic_inc_u32 v5, v0, v5, s[2:3] glc
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[3:4], v5, off
global_store_b8 v[0:1], v6, off
.LBB6_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| DefineNovosVU | 917 | 641 | stackv2-00000-of-00015 |
// Demangled: EncontraMenorAresta1(aresta*, float*, int*, int, int)
Function : _Z20EncontraMenorAresta1P6arestaPfPiii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R0, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x398] &wr=0x2 ?trans1;
IMAD R3, R0, UR4, R3 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R3, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R4, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
LDCU UR6, c[0x0][0x39c] &wr=0x2 ?trans1;
IMAD.WIDE R4, R3, 0xc, R4 &req={0} ?WAIT5_END_GROUP;
LDG.E R7, desc[UR4][R4.64] &req={1} &wr=0x2 ?trans2;
ISETP.NE.AND P0, PT, R7, UR6, PT &req={2} ?WAIT13_END_GROUP;
@!P0 EXIT ?trans5;
LDC.64 R4, c[0x0][0x390] &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x388] &wr=0x1 ?trans1;
IMAD.WIDE R4, R7, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
LDG.E R8, desc[UR4][R4.64] &wr=0x2 ?trans1;
SHF.R.S32.HI R0, RZ, 0x1f, R3 ?trans1;
BSSY.RECONVERGENT B0, 0x240 ?trans1;
LEA R6, P1, R3, UR6, 0x2 &req={1} ?WAIT4_END_GROUP;
LEA.HI.X R7, R3, UR7, R0, 0x2, P1 ?trans2;
SHF.R.S32.HI R9, RZ, 0x1f, R8 &req={2} ?WAIT5_END_GROUP;
ISETP.NE.S64.AND P0, PT, R8, -0x1, PT ?WAIT14_END_GROUP;
@!P0 BRA 0x230 ?trans5;
LEA R10, P0, R8.reuse, UR6, 0x2 ?trans1;
LDG.E R13, desc[UR4][R6.64] &wr=0x2 ?trans3;
LEA.HI.X R11, R8, UR7, R9, 0x2, P0 ?WAIT5_END_GROUP;
LDG.E R10, desc[UR4][R10.64] &wr=0x2 ?trans2;
FSETP.GT.AND P0, PT, R10, R13, PT &req={2} ?WAIT13_END_GROUP;
@P0 BRA 0x230 ?trans5;
ISETP.GT.AND P0, PT, R8, R3, PT ?WAIT5_END_GROUP;
FSETP.NEU.OR P0, PT, R10, R13, !P0 ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
MOV R2, 0xffffffff ?WAIT6_END_GROUP;
ATOMG.E.CAS.STRONG.GPU PT, R2, [R4], R2, R3 &wr=0x2 ?trans2;
ISETP.NE.AND P0, PT, R2, -0x1, PT &req={2} ?WAIT13_END_GROUP;
@!P0 EXIT ?trans5;
LDC.64 R10, c[0x0][0x388] &wr=0x0 ?trans1;
MOV R13, 0xffffffff ?WAIT7_END_GROUP;
IMAD.WIDE R8, R2, 0x4, R10 &req={0} ?trans1;
LDG.E R0, desc[UR4][R6.64] &wr=0x2 ?trans5;
LDG.E R9, desc[UR4][R8.64] &wr=0x2 ?trans1;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x8 ?trans1;
FSETP.GT.AND P1, PT, R9, R0, PT &req={2} ?WAIT13_END_GROUP;
@!P1 FSETP.NEU.AND P2, PT, R9, R0, PT ?WAIT5_END_GROUP;
@!P1 ISETP.GT.AND P0, PT, R2, R3, !P2 ?WAIT5_END_GROUP;
ISETP.EQ.OR P0, PT, R2, R13, !P0 ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
ATOMG.E.CAS.STRONG.GPU PT, R9, [R4], R2, R3 &wr=0x2 ?trans2;
ISETP.NE.AND P0, PT, R2, R9.reuse, PT &req={2} ?trans1;
MOV R2, R9 ?WAIT4_END_GROUP;
SEL R13, R9, 0xffffffff, !P0 ?trans1;
BRA 0x2a0 ?trans7;
BRA 0x380;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: EncontraMenorAresta1(aresta*, float*, int*, int, int)
_Z20EncontraMenorAresta1P6arestaPfPiii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_16
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[2:3], null, v1, 12, s[4:5]
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, s3, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_16
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v3, 31, v2
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_load_b32 v5, v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s1, -1, v5
v_cmpx_ne_u32_e32 -1, v5
s_cbranch_execz .LBB0_6
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[8:9], 2, v[1:2]
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
s_clause 0x1
global_load_b32 v0, v[6:7], off
global_load_b32 v6, v[8:9], off
s_waitcnt vmcnt(0)
v_cmp_gt_f32_e64 s3, v0, v6
v_cmpx_ngt_f32_e32 v0, v6
v_cmp_eq_f32_e32 vcc_lo, v0, v6
v_cmp_gt_i32_e64 s0, v5, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_not1_b32 s3, s3, exec_lo
s_and_b32 s0, s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, exec_lo
s_or_b32 s3, s3, s0
s_or_b32 exec_lo, exec_lo, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s0, s1, exec_lo
s_and_b32 s1, s3, exec_lo
s_or_b32 s1, s0, s1
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v9, -1 :: v_dual_mov_b32 v8, v1
global_atomic_cmpswap_b32 v5, v[3:4], v[8:9], off glc
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, -1, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_16
v_lshlrev_b64 v[7:8], 2, v[1:2]
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
.LBB0_9:
v_ashrrev_i32_e32 v6, 31, v5
s_mov_b32 s0, 0
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], 2, v[5:6]
v_add_co_u32 v10, vcc_lo, s6, v10
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
s_clause 0x1
global_load_b32 v0, v[10:11], off
global_load_b32 v2, v[7:8], off
s_waitcnt vmcnt(0)
v_cmpx_ngt_f32_e32 v0, v2
s_xor_b32 s3, exec_lo, s1
v_cmp_eq_f32_e32 vcc_lo, v0, v2
v_cmp_gt_i32_e64 s0, v5, v1
v_cmp_ne_u32_e64 s1, v5, v9
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s0, s0, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s0, s0, exec_lo
s_and_not1_saveexec_b32 s1, s3
v_cmp_ne_u32_e32 vcc_lo, v5, v9
s_and_not1_b32 s0, s0, exec_lo
s_and_b32 s3, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s0, s0, s3
s_or_b32 exec_lo, exec_lo, s1
s_mov_b32 s3, -1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_15
v_mov_b32_e32 v2, v5
s_xor_b32 s3, exec_lo, -1
global_atomic_cmpswap_b32 v0, v[3:4], v[1:2], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v5, v0
v_mov_b32_e32 v5, v0
v_cndmask_b32_e32 v9, -1, v0, vcc_lo
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, exec_lo, s3
s_or_b32 s2, s0, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_9
.LBB0_16:
s_endpgm
| EncontraMenorAresta1 | 1,472 | 2,278 | stackv2-00000-of-00015 |
// Demangled: EncontraMenorAresta2(aresta*, float*, int*, int, int)
Function : _Z20EncontraMenorAresta2P6arestaPfPiii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R0, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x398] &wr=0x2 ?trans1;
IMAD R3, R0, UR4, R3 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R3, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R4, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
LDCU UR6, c[0x0][0x39c] &wr=0x2 ?trans1;
IMAD.WIDE R4, R3, 0xc, R4 &req={0} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR4][R4.64] &req={1} &wr=0x2 ?trans2;
ISETP.NE.AND P0, PT, R0, UR6, PT &req={2} ?WAIT13_END_GROUP;
@!P0 EXIT ?trans5;
LDG.E R5, desc[UR4][R4.64+0x4] &wr=0x2 ?trans1;
LDC.64 R6, c[0x0][0x390] &wr=0x2 ?trans1;
LDCU.64 UR6, c[0x0][0x388] &wr=0x0 ?trans1;
IMAD.WIDE R6, R5, 0x4, R6 &req={2} ?WAIT5_END_GROUP;
LDG.E R10, desc[UR4][R6.64] &wr=0x2 ?trans1;
SHF.R.S32.HI R0, RZ, 0x1f, R3 ?trans1;
BSSY.RECONVERGENT B0, 0x250 ?trans1;
LEA R8, P1, R3, UR6, 0x2 &req={0} ?WAIT4_END_GROUP;
LEA.HI.X R9, R3, UR7, R0, 0x2, P1 ?trans2;
SHF.R.S32.HI R11, RZ, 0x1f, R10 &req={2} ?WAIT5_END_GROUP;
ISETP.NE.S64.AND P0, PT, R10, -0x1, PT ?WAIT14_END_GROUP;
@!P0 BRA 0x240 ?trans5;
LEA R4, P0, R10.reuse, UR6, 0x2 ?trans1;
LDG.E R13, desc[UR4][R8.64] &wr=0x2 ?trans3;
LEA.HI.X R5, R10, UR7, R11, 0x2, P0 ?WAIT5_END_GROUP;
LDG.E R4, desc[UR4][R4.64] &wr=0x2 ?trans2;
FSETP.GT.AND P0, PT, R4, R13, PT &req={2} ?WAIT13_END_GROUP;
@P0 BRA 0x240 ?trans5;
ISETP.GT.AND P0, PT, R10, R3, PT ?WAIT5_END_GROUP;
FSETP.NEU.OR P0, PT, R4, R13, !P0 ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
MOV R2, 0xffffffff ?WAIT6_END_GROUP;
ATOMG.E.CAS.STRONG.GPU PT, R2, [R6], R2, R3 &wr=0x2 ?trans2;
ISETP.NE.AND P0, PT, R2, -0x1, PT &req={2} ?WAIT13_END_GROUP;
@!P0 EXIT ?trans5;
LDC.64 R10, c[0x0][0x388] &wr=0x0 ?trans1;
MOV R13, 0xffffffff ?WAIT7_END_GROUP;
IMAD.WIDE R4, R2, 0x4, R10 &req={0} ?trans1;
LDG.E R0, desc[UR4][R8.64] &wr=0x2 ?trans5;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x8 ?trans1;
FSETP.GT.AND P1, PT, R5, R0, PT &req={2} ?WAIT13_END_GROUP;
@!P1 FSETP.NEU.AND P2, PT, R5, R0, PT ?WAIT5_END_GROUP;
@!P1 ISETP.GT.AND P0, PT, R2, R3, !P2 ?WAIT5_END_GROUP;
ISETP.EQ.OR P0, PT, R2, R13, !P0 ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
ATOMG.E.CAS.STRONG.GPU PT, R5, [R6], R2, R3 &wr=0x2 ?trans2;
ISETP.NE.AND P0, PT, R2, R5.reuse, PT &req={2} ?trans1;
MOV R2, R5 ?WAIT4_END_GROUP;
SEL R13, R5, 0xffffffff, !P0 ?trans1;
BRA 0x2b0 ?trans7;
BRA 0x390;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: EncontraMenorAresta2(aresta*, float*, int*, int, int)
_Z20EncontraMenorAresta2P6arestaPfPiii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_16
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[2:3], null, v1, 12, s[4:5]
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, s3, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_16
v_mad_i64_i32 v[2:3], null, v1, 12, s[4:5]
s_load_b64 s[0:1], s[0:1], 0x10
s_mov_b32 s2, exec_lo
global_load_b32 v2, v[2:3], off offset:4
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_load_b32 v5, v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s1, -1, v5
v_cmpx_ne_u32_e32 -1, v5
s_cbranch_execz .LBB1_6
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[8:9], 2, v[1:2]
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
s_clause 0x1
global_load_b32 v0, v[6:7], off
global_load_b32 v6, v[8:9], off
s_waitcnt vmcnt(0)
v_cmp_gt_f32_e64 s3, v0, v6
v_cmpx_ngt_f32_e32 v0, v6
v_cmp_eq_f32_e32 vcc_lo, v0, v6
v_cmp_gt_i32_e64 s0, v5, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_not1_b32 s3, s3, exec_lo
s_and_b32 s0, s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, exec_lo
s_or_b32 s3, s3, s0
s_or_b32 exec_lo, exec_lo, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s0, s1, exec_lo
s_and_b32 s1, s3, exec_lo
s_or_b32 s1, s0, s1
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB1_16
v_dual_mov_b32 v9, -1 :: v_dual_mov_b32 v8, v1
global_atomic_cmpswap_b32 v5, v[3:4], v[8:9], off glc
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, -1, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_16
v_lshlrev_b64 v[7:8], 2, v[1:2]
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
.LBB1_9:
v_ashrrev_i32_e32 v6, 31, v5
s_mov_b32 s0, 0
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], 2, v[5:6]
v_add_co_u32 v10, vcc_lo, s6, v10
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
s_clause 0x1
global_load_b32 v0, v[10:11], off
global_load_b32 v2, v[7:8], off
s_waitcnt vmcnt(0)
v_cmpx_ngt_f32_e32 v0, v2
s_xor_b32 s3, exec_lo, s1
v_cmp_eq_f32_e32 vcc_lo, v0, v2
v_cmp_gt_i32_e64 s0, v5, v1
v_cmp_ne_u32_e64 s1, v5, v9
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s0, s0, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s0, s0, exec_lo
s_and_not1_saveexec_b32 s1, s3
v_cmp_ne_u32_e32 vcc_lo, v5, v9
s_and_not1_b32 s0, s0, exec_lo
s_and_b32 s3, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s0, s0, s3
s_or_b32 exec_lo, exec_lo, s1
s_mov_b32 s3, -1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB1_15
v_mov_b32_e32 v2, v5
s_xor_b32 s3, exec_lo, -1
global_atomic_cmpswap_b32 v0, v[3:4], v[1:2], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v5, v0
v_mov_b32_e32 v5, v0
v_cndmask_b32_e32 v9, -1, v0, vcc_lo
.LBB1_15:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, exec_lo, s3
s_or_b32 s2, s0, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB1_9
.LBB1_16:
s_endpgm
| EncontraMenorAresta2 | 1,503 | 2,335 | stackv2-00000-of-00015 |
// Demangled: Inicializa_arestasE_C(aresta*, int*, int, int*, aresta_E*, unsigned int*)
Function : _Z21Inicializa_arestasE_CP6arestaPiiS1_P8aresta_EPj
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R3, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x390] &wr=0x2 ?trans1;
IMAD R0, R3, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R4, c[0x0][0x388] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x2 ?trans1;
IMAD.WIDE R4, R0, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
LDG.E R7, desc[UR4][R4.64] &req={1} &wr=0x2 ?trans2;
IMAD.WIDE R6, R7, 0xc, R2 &req={2} ?WAIT5_END_GROUP;
LDG.E R8, desc[UR4][R6.64+0x8] &wr=0x2 ?trans1;
BSSY.RECONVERGENT B0, 0x330 ?trans4;
BSSY.RELIABLE B1, 0x1c0 ?trans1;
SHF.R.S32.HI R17, RZ, 0x1f, R0 ?trans1;
ISETP.NE.AND P0, PT, R8, 0x1, PT &req={2} ?WAIT13_END_GROUP;
@!P0 BRA 0x1b0 ?trans5;
ISETP.NE.AND P0, PT, R8, 0x2, PT ?WAIT13_END_GROUP;
@P0 BREAK.RELIABLE B1 ?trans5;
@P0 BRA 0x320 ?trans5;
LDG.E R7, desc[UR4][R6.64] &wr=0x2 ?trans2;
ISETP.NE.AND P0, PT, R0, R7, PT &req={2} ?WAIT13_END_GROUP;
@P0 BREAK.RELIABLE B1 ?trans5;
@P0 BRA 0x320 ?trans5;
BSYNC.RELIABLE B1 ?trans5;
S2R R7, SR_LANEID &wr=0x0 ?trans1;
VOTEU.ANY UR6, UPT, PT ?trans1;
LDC.64 R10, c[0x0][0x3a0] &wr=0x1 ?trans1;
FLO.U32 R12, UR6 &wr=0x0 ?trans1;
POPC R15, UR6 &wr=0x2 ?trans1;
ISETP.EQ.U32.AND P0, PT, R12, R7, PT &req={0} ?WAIT5_END_GROUP;
LDC.64 R6, c[0x0][0x3a8] &wr=0x2 ?trans8;
@P0 ATOMG.E.ADD.STRONG.GPU PT, R7, desc[UR4][R6.64], R15 &req={2} &wr=0x2 ?trans4;
LDG.E R9, desc[UR4][R4.64] &wr=0x3 ?trans1;
S2R R14, SR_LTMASK &wr=0x0 ?trans1;
IMAD.WIDE R8, R9, 0xc, R2 &req={3} ?WAIT6_END_GROUP;
LDG.E R9, desc[UR4][R8.64] &wr=0x3 ?trans1;
LOP3.LUT R14, R14, UR6, RZ, 0xc0, !PT &req={0} ?WAIT3_END_GROUP;
SHFL.IDX PT, R13, R7, R12, 0x1f &req={2} &wr=0x0 ?trans3;
POPC R14, R14 &wr=0x0 ?trans2;
IADD3 R13, PT, PT, R13, R14, RZ &req={0} ?WAIT5_END_GROUP;
IMAD.WIDE R10, R13, 0x8, R10 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR4][R10.64], R9 &req={3} &rd=0x0 ?trans4;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans2;
IMAD.WIDE R2, R5, 0xc, R2 &req={2} ?WAIT6_END_GROUP;
LDG.E R3, desc[UR4][R2.64+0x4] &wr=0x2 ?trans4;
STG.E desc[UR4][R10.64+0x4], R3 &req={2} &rd=0x0 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
WARPSYNC.ALL ?trans5;
NOP ?trans1;
LDCU.64 UR6, c[0x0][0x398] &wr=0x1 ?trans2;
LEA R2, P0, R0, UR6, 0x2 &req={1} ?WAIT4_END_GROUP;
LEA.HI.X R3, R0, UR7, R17, 0x2, P0 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R0 ?trans1;
EXIT ?trans5;
BRA 0x3a0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: Inicializa_arestasE_C(aresta*, int*, int, int*, aresta_E*, unsigned int*)
_Z21Inicializa_arestasE_CP6arestaPiiS1_P8aresta_EPj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB4_10
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b128 s[8:11], s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x28
s_mov_b32 s2, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
global_load_b32 v0, v[4:5], off
s_waitcnt vmcnt(0)
v_mad_i64_i32 v[6:7], null, v0, 12, s[4:5]
global_load_b32 v0, v[6:7], off offset:8
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e32 1, v0
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB4_5
s_mov_b32 s6, exec_lo
v_cmpx_eq_u32_e32 2, v0
s_cbranch_execz .LBB4_4
global_load_b32 v0, v[6:7], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v1, v0
s_and_b32 s2, vcc_lo, exec_lo
.LBB4_4:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s2, s2, exec_lo
.LBB4_5:
s_and_not1_saveexec_b32 s3, s3
v_cmp_eq_u32_e32 vcc_lo, 1, v0
s_and_not1_b32 s2, s2, exec_lo
s_and_b32 s6, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s2, s2, s6
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB4_9
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v6, -1
global_atomic_inc_u32 v6, v0, v6, s[0:1] glc
global_load_b32 v0, v[4:5], off
s_waitcnt vmcnt(0)
v_mad_i64_i32 v[7:8], null, v0, 12, s[4:5]
global_load_b32 v0, v[7:8], off
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 3, v[6:7]
v_add_co_u32 v6, vcc_lo, s10, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[6:7], v0, off
global_load_b32 v0, v[4:5], off
s_waitcnt vmcnt(0)
v_mad_i64_i32 v[4:5], null, v0, 12, s[4:5]
global_load_b32 v0, v[4:5], off offset:4
s_waitcnt vmcnt(0)
global_store_b32 v[6:7], v0, off offset:4
.LBB4_9:
s_or_b32 exec_lo, exec_lo, s3
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
global_store_b32 v[2:3], v1, off
.LBB4_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| Inicializa_arestasE_C | 1,521 | 1,357 | stackv2-00000-of-00015 |
// Demangled: MarcarArestas(aresta*, int*, int, int)
Function : _Z13MarcarArestasP6arestaPiii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R5, SR_TID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R0, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x390] &wr=0x2 ?trans1;
IMAD R5, R0, UR4, R5 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R5, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
LDCU UR6, c[0x0][0x394] &wr=0x2 ?trans1;
IMAD.WIDE R2, R5, 0xc, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E R5, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans2;
ISETP.NE.AND P0, PT, R5, UR6, PT &req={2} ?WAIT13_END_GROUP;
@!P0 EXIT ?trans5;
LDG.E R9, desc[UR4][R2.64+0x4] &wr=0x2 ?trans1;
LDC.64 R6, c[0x0][0x388] &wr=0x0 ?trans2;
IMAD.WIDE.U32 R4, R5, 0x4, R6 &req={0} ?WAIT6_END_GROUP;
LDG.E R4, desc[UR4][R4.64] &wr=0x3 ?trans1;
IMAD.WIDE.U32 R6, R9, 0x4, R6 &req={2} ?WAIT6_END_GROUP;
LDG.E R7, desc[UR4][R6.64] &wr=0x3 ?trans4;
STG.E desc[UR4][R2.64+0x8], RZ ?trans1;
ISETP.NE.AND P0, PT, R4, R7, PT &req={3} ?WAIT5_END_GROUP;
SEL R9, R4, UR6, P0 ?trans1;
SEL R11, R7, UR6, P0 ?WAIT4_END_GROUP;
STG.E desc[UR4][R2.64], R9 ?trans4;
STG.E desc[UR4][R2.64+0x4], R11 ?trans1;
EXIT ?trans5;
BRA 0x1c0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: MarcarArestas(aresta*, int*, int, int)
_Z13MarcarArestasP6arestaPiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v2
s_cbranch_execz .LBB8_3
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[3:4], null, v2, 12, s[0:1]
global_load_b32 v1, v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, s5, v1
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB8_3
v_mad_i64_i32 v[5:6], null, v2, 12, s[0:1]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[1:2]
global_load_b32 v1, v[5:6], off offset:4
v_add_co_u32 v5, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v8, vcc_lo
s_waitcnt vmcnt(0)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_clause 0x1
global_load_b32 v5, v[5:6], off
global_load_b32 v1, v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v5, v1
v_cndmask_b32_e64 v0, v5, s5, vcc_lo
v_cndmask_b32_e64 v1, v1, s5, vcc_lo
global_store_b96 v[3:4], v[0:2], off
.LBB8_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| MarcarArestas | 765 | 744 | stackv2-00000-of-00015 |
// Demangled: MarcarArestas_Strut(aresta*, int*, int)
Function : _Z19MarcarArestas_StrutP6arestaPii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R5, SR_TID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R0, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x390] &wr=0x2 ?trans1;
IMAD R5, R0, UR4, R5 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R5, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x388] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD.WIDE R2, R5, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
LDC.64 R4, c[0x0][0x380] &wr=0x0 ?trans1;
LDG.E R3, desc[UR4][R2.64] &req={1} &wr=0x0 ?trans1;
HFMA2 R7, -RZ, RZ, 0, 5.9604644775390625e-08 ?trans2;
IMAD.WIDE R4, R3, 0xc, R4 &req={0} ?WAIT5_END_GROUP;
REDG.E.ADD.STRONG.GPU desc[UR4][R4.64+0x8], R7 ?trans1;
EXIT ?trans5;
BRA 0x110;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: MarcarArestas_Strut(aresta*, int*, int)
_Z19MarcarArestas_StrutP6arestaPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB2_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mad_i64_i32 v[0:1], null, v2, 12, s[0:1]
v_mov_b32_e32 v2, -1
global_atomic_inc_u32 v[0:1], v2, off offset:8
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| MarcarArestas_Strut | 527 | 483 | stackv2-00000-of-00015 |
// Demangled: backward_step1(float*, float*, float*, unsigned int, unsigned int)
Function : _Z14backward_step1PfS_S_jj
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R5, SR_TID.Y &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x2 ?trans6;
LDC R2, c[0x0][0x370] &wr=0x3 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x364] &wr=0x2 ?trans1;
S2R R3, SR_CTAID.Y &wr=0x3 ?trans1;
LDCU UR6, c[0x0][0x39c] &wr=0x4 ?trans4;
LDC.64 R8, c[0x0][0x388] &wr=0x5 ?trans1;
S2R R4, SR_CTAID.X &wr=0x3 ?trans7;
LDC.64 R6, c[0x0][0x380] &wr=0x0 ?trans1;
UIMAD UR4, UR5, UR4, URZ &req={2} ?WAIT2_END_GROUP;
IMAD R5, R5, UR5, R0 &req={1} ?trans2;
IMAD R0, R2, R3, R4 &req={3} ?trans2;
S2R R3, SR_CTAID.Z &wr=0x1 ?trans2;
IMAD R2, R0, UR4, R5 ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P1, PT, R2, UR6, PT &req={4} ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x2 ?WAIT12_END_GROUP;
@!P1 LDC R11, c[0x0][0x398] &wr=0x1 ?trans1;
@!P1 IMAD.WIDE.U32 R8, R2, 0x4, R8 &req={5} ?WAIT6_END_GROUP;
@!P1 LDG.E R9, desc[UR6][R8.64] &req={2} &wr=0x2 ?trans1;
@!P1 IMAD R11, R2, R11, R3 &req={1} ?WAIT4_END_GROUP;
@!P1 IMAD.WIDE.U32 R6, R11, 0x4, R6 &req={0} ?WAIT6_END_GROUP;
@!P1 LDG.E R6, desc[UR6][R6.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x0 ?trans1;
UMOV UR4, 0x400 ?trans2;
ULEA UR4, UR5, UR4, 0x18 &req={0} ?WAIT6_END_GROUP;
LEA R2, R5.reuse, UR4, 0x2 ?trans1;
ISETP.GT.U32.AND P0, PT, R5, 0x1ff, PT ?trans1;
@!P1 FMUL R11, R6, R9 &req={2} ?WAIT5_END_GROUP;
@!P1 STS [R2], R11 ?trans4;
@P1 STS [R2], RZ ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 LDS R4, [R2+0x800] ?trans4;
@!P0 LDS R7, [R2] &wr=0x0 ?trans1;
ISETP.GT.U32.AND P1, PT, R5, 0xff, PT ?trans1;
@!P0 FADD R7, R4, R7 &req={0} ?WAIT5_END_GROUP;
@!P0 STS [R2], R7 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P1 LDS R4, [R2+0x400] ?trans4;
@!P1 LDS R9, [R2] &wr=0x0 ?trans1;
ISETP.GT.U32.AND P0, PT, R5, 0x7f, PT ?trans1;
@!P1 FADD R9, R4, R9 &req={0} ?WAIT5_END_GROUP;
@!P1 STS [R2], R9 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 LDS R4, [R2+0x200] ?trans4;
@!P0 LDS R11, [R2] &wr=0x0 ?trans1;
ISETP.GT.U32.AND P1, PT, R5, 0x3f, PT ?trans1;
@!P0 FADD R11, R4, R11 &req={0} ?WAIT5_END_GROUP;
@!P0 STS [R2], R11 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P1 LDS R4, [R2+0x100] ?trans4;
@!P1 LDS R7, [R2] &wr=0x0 ?trans1;
ISETP.GT.U32.AND P0, PT, R5, 0x1f, PT ?trans1;
@!P1 FADD R7, R4, R7 &req={0} ?WAIT5_END_GROUP;
@!P1 STS [R2], R7 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 LDS R4, [R2+0x80] ?trans4;
@!P0 LDS R9, [R2] &wr=0x0 ?trans1;
ISETP.GT.U32.AND P1, PT, R5, 0xf, PT ?trans1;
@!P0 FADD R9, R4, R9 &req={0} ?WAIT5_END_GROUP;
@!P0 STS [R2], R9 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P1 LDS R4, [R2+0x40] ?trans4;
@!P1 LDS R11, [R2] &wr=0x0 ?trans1;
ISETP.GT.U32.AND P0, PT, R5, 0x7, PT ?trans1;
@!P1 FADD R11, R4, R11 &req={0} ?WAIT5_END_GROUP;
@!P1 STS [R2], R11 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 LDS R4, [R2+0x20] ?trans4;
@!P0 LDS R7, [R2] &wr=0x0 ?trans1;
ISETP.GT.U32.AND P1, PT, R5, 0x3, PT ?trans1;
@!P0 FADD R7, R4, R7 &req={0} ?WAIT5_END_GROUP;
@!P0 STS [R2], R7 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P1 LDS R4, [R2+0x10] ?trans4;
@!P1 LDS R9, [R2] &wr=0x0 ?trans1;
ISETP.GT.U32.AND P0, PT, R5, 0x1, PT ?trans1;
@!P1 FADD R9, R4, R9 &req={0} ?WAIT5_END_GROUP;
@!P1 STS [R2], R9 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 LDS R4, [R2+0x8] ?trans4;
@!P0 LDS R11, [R2] &wr=0x0 ?trans1;
ISETP.NE.AND P1, PT, R5, RZ, PT ?trans1;
@!P0 FADD R11, R4, R11 &req={0} ?WAIT5_END_GROUP;
@!P0 STS [R2], R11 &rd=0x0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P1 EXIT ?trans5;
LDS.64 R6, [UR4] &wr=0x1 ?trans1;
LDC.64 R4, c[0x0][0x390] &wr=0x2 ?trans1;
LEA R3, R3, R0, 0x6 ?WAIT5_END_GROUP;
IMAD.WIDE.U32 R2, R3, 0x4, R4 &req={2,0} ?WAIT4_END_GROUP;
FADD R7, R6, R7 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R7 ?trans1;
EXIT ?trans5;
BRA 0x5f0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: backward_step1(float*, float*, float*, unsigned int, unsigned int)
_Z14backward_step1PfS_S_jj:
s_clause 0x2
s_load_b32 s10, s[0:1], 0x2c
s_load_b32 s9, s[0:1], 0x20
s_load_b256 s[0:7], s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s8, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s11, s10, 0xffff
s_mul_i32 s9, s9, s14
v_mad_u32_u24 v0, v0, s11, v1
s_add_i32 s9, s9, s13
s_lshr_b32 s10, s10, 16
s_mul_i32 s11, s9, s11
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s11, s10, v[0:1]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_2)
v_cmp_gt_u32_e32 vcc_lo, s7, v1
s_and_saveexec_b32 s7, vcc_lo
s_cbranch_execz .LBB3_2
v_mad_u64_u32 v[3:4], null, v1, s6, s[8:9]
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mov_b32_e32 v2, v4
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_load_b32 v3, v[3:4], off
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v3, v1
.LBB3_2:
s_or_b32 exec_lo, exec_lo, s7
v_lshlrev_b32_e32 v1, 2, v0
s_mov_b32 s0, exec_lo
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 0x200, v0
s_cbranch_execz .LBB3_4
ds_load_2addr_stride64_b32 v[2:3], v1 offset1:8
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
.LBB3_4:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 0x100, v0
s_cbranch_execz .LBB3_6
ds_load_b32 v2, v1 offset:1024
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB3_6:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 0x80, v0
s_cbranch_execz .LBB3_8
ds_load_b32 v2, v1 offset:512
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB3_8:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 64, v0
s_cbranch_execz .LBB3_10
ds_load_b32 v2, v1 offset:256
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB3_10:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB3_12
ds_load_b32 v2, v1 offset:128
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB3_12:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 16, v0
s_cbranch_execz .LBB3_14
ds_load_b32 v2, v1 offset:64
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB3_14:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 8, v0
s_cbranch_execz .LBB3_16
ds_load_b32 v2, v1 offset:32
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB3_16:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 4, v0
s_cbranch_execz .LBB3_18
ds_load_b32 v2, v1 offset:16
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB3_18:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 2, v0
s_cbranch_execz .LBB3_20
ds_load_b32 v2, v1 offset:8
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB3_20:
s_or_b32 exec_lo, exec_lo, s0
s_mov_b32 s1, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB3_22
v_mov_b32_e32 v2, 0
s_lshl_b32 s0, s8, 6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s9, s0
s_lshl_b64 s[0:1], s[0:1], 2
ds_load_b64 v[0:1], v2
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v0, v1
global_store_b32 v2, v0, s[0:1]
.LBB3_22:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| backward_step1 | 2,214 | 2,490 | stackv2-00000-of-00015 |
// Demangled: backward_step2(float*, float*, float*)
Function : _Z14backward_step2PfS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R5, SR_TID.Y &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans6;
LDC.64 R2, c[0x0][0x380] &wr=0x2 ?trans1;
S2R R4, SR_TID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x3 ?trans1;
S2R R0, SR_CTAID.Z &wr=0x4 ?trans1;
IMAD R5, R5, UR4, R4 &req={1} ?WAIT5_END_GROUP;
LEA R7, R0, R5, 0x6 &req={4} ?WAIT5_END_GROUP;
IMAD.WIDE.U32 R2, R7, 0x4, R2 &req={2} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR6][R2.64] &req={3} &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GT.U32.AND P0, PT, R5.reuse, 0x1f, PT ?trans1;
ISETP.GT.U32.AND P1, PT, R5, 0xf, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R7, R5, UR4, 0x2 ?WAIT5_END_GROUP;
STS [R7], R2 &req={2} ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 LDS R4, [R7+0x80] ?trans4;
@!P0 LDS R9, [R7] &wr=0x1 ?trans2;
@!P0 FADD R4, R4, R9 &req={1} ?WAIT5_END_GROUP;
@!P0 STS [R7], R4 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P0, PT, R5, 0x7, PT ?WAIT5_END_GROUP;
@!P1 LDS R3, [R7+0x40] ?trans4;
@!P1 LDS R6, [R7] &wr=0x1 ?trans2;
@!P1 FADD R6, R3, R6 &req={1} ?WAIT5_END_GROUP;
@!P1 STS [R7], R6 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P1, PT, R5, 0x3, PT ?WAIT5_END_GROUP;
@!P0 LDS R2, [R7+0x20] ?trans4;
@!P0 LDS R3, [R7] &wr=0x1 ?trans2;
@!P0 FADD R2, R2, R3 &req={1} ?WAIT5_END_GROUP;
@!P0 STS [R7], R2 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P0, PT, R5, 0x1, PT ?WAIT5_END_GROUP;
@!P1 LDS R3, [R7+0x10] ?trans4;
@!P1 LDS R4, [R7] &wr=0x1 ?trans2;
@!P1 FADD R4, R3, R4 &req={1} ?WAIT5_END_GROUP;
@!P1 STS [R7], R4 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.NE.AND P1, PT, R5, RZ, PT ?WAIT5_END_GROUP;
@!P0 LDS R3, [R7+0x8] ?trans4;
@!P0 LDS R6, [R7] &wr=0x1 ?trans2;
@!P0 FADD R6, R3, R6 &req={1} ?WAIT5_END_GROUP;
@!P0 STS [R7], R6 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P1 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x388] &wr=0x0 ?trans1;
LDS.64 R6, [UR4] &req={1} &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x390] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R2, R0, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E R3, desc[UR6][R2.64] &wr=0x3 ?trans1;
IMAD.WIDE.U32 R4, R0, 0x4, R4 &req={2} ?WAIT4_END_GROUP;
FADD R6, R7, R6 &req={1} ?WAIT5_END_GROUP;
STS [UR4], R6 ?trans1;
FMUL R7, R6, R3 &req={3} ?trans1;
FADD R8, -R3, 1 ?WAIT4_END_GROUP;
FMUL R7, R7, R8 ?WAIT5_END_GROUP;
STG.E desc[UR6][R4.64], R7 ?trans1;
EXIT ?trans5;
BRA 0x3e0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: backward_step2(float*, float*, float*)
_Z14backward_step2PfS_S_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u32_u24 v0, v0, s3, v1
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v1, s2, 6, v0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB4_2
ds_load_2addr_b32 v[2:3], v1 offset1:32
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
.LBB4_2:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 16, v0
s_cbranch_execz .LBB4_4
ds_load_b32 v2, v1 offset:64
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB4_4:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 8, v0
s_cbranch_execz .LBB4_6
ds_load_b32 v2, v1 offset:32
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB4_6:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 4, v0
s_cbranch_execz .LBB4_8
ds_load_b32 v2, v1 offset:16
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB4_8:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 2, v0
s_cbranch_execz .LBB4_10
ds_load_b32 v2, v1 offset:8
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB4_10:
s_or_b32 exec_lo, exec_lo, s3
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB4_12
v_mov_b32_e32 v2, 0
s_lshl_b64 s[2:3], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s4, s6, s2
s_addc_u32 s5, s7, s3
ds_load_b64 v[0:1], v2
s_load_b32 s4, s[4:5], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_sub_f32_e64 v3, 1.0, s4
v_add_f32_e32 v0, v1, v0
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v1, s4, v0
v_mul_f32_e32 v1, v1, v3
ds_store_b32 v2, v0
global_store_b32 v2, v1, s[0:1]
.LBB4_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| backward_step2 | 1,435 | 1,570 | stackv2-00000-of-00015 |
// Demangled: forward_step1(float*, float*, float*, unsigned int)
Function : _Z13forward_step1PfS_S_j
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R2, SR_TID.Y &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x2 ?trans6;
LDC R4, c[0x0][0x370] &wr=0x3 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x364] &wr=0x2 ?trans1;
S2R R5, SR_CTAID.Y &wr=0x3 ?trans1;
LDCU UR8, c[0x0][0x398] &wr=0x4 ?trans1;
S2R R6, SR_CTAID.X &wr=0x3 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x5 ?trans1;
S2R R0, SR_CTAID.Z &wr=0x0 ?trans1;
UIMAD UR4, UR5, UR4, URZ &req={2} ?WAIT2_END_GROUP;
IMAD R2, R2, UR5, R3 &req={1} ?trans2;
IMAD R3, R4, R5, R6 &req={3} ?trans2;
LDC.64 R4, c[0x0][0x388] &wr=0x1 ?trans2;
IMAD R9, R3, UR4, R2 ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P1, PT, R9, UR8, PT &req={4} ?trans1;
LDC.64 R6, c[0x0][0x380] &wr=0x2 ?WAIT12_END_GROUP;
@!P1 IMAD R11, R0, UR8, R9 &req={0} ?trans2;
@!P1 IMAD.WIDE.U32 R4, R9, 0x4, R4 &req={1} ?WAIT6_END_GROUP;
@!P1 LDG.E R4, desc[UR6][R4.64] &req={5} &wr=0x3 ?trans1;
@!P1 IMAD.WIDE.U32 R6, R11, 0x4, R6 &req={2} ?WAIT6_END_GROUP;
@!P1 LDG.E R7, desc[UR6][R6.64] &wr=0x3 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x0 ?trans1;
UMOV UR4, 0x400 ?trans2;
ULEA UR4, UR5, UR4, 0x18 &req={0} ?WAIT6_END_GROUP;
LEA R8, R2.reuse, UR4, 0x2 ?trans1;
ISETP.GT.U32.AND P0, PT, R2, 0x1ff, PT ?trans1;
@!P1 FMUL R9, R4, R7 &req={3} ?WAIT5_END_GROUP;
@!P1 STS [R8], R9 ?trans4;
@P1 STS [R8], RZ ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 LDS R4, [R8+0x800] ?trans4;
@!P0 LDS R5, [R8] &wr=0x0 ?trans1;
ISETP.GT.U32.AND P1, PT, R2, 0xff, PT ?trans1;
@!P0 FADD R5, R4, R5 &req={0} ?WAIT5_END_GROUP;
@!P0 STS [R8], R5 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P1 LDS R4, [R8+0x400] ?trans4;
@!P1 LDS R7, [R8] &wr=0x0 ?trans1;
ISETP.GT.U32.AND P0, PT, R2, 0x7f, PT ?trans1;
@!P1 FADD R7, R4, R7 &req={0} ?WAIT5_END_GROUP;
@!P1 STS [R8], R7 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 LDS R4, [R8+0x200] ?trans4;
@!P0 LDS R9, [R8] &wr=0x0 ?trans1;
ISETP.GT.U32.AND P1, PT, R2, 0x3f, PT ?trans1;
@!P0 FADD R9, R4, R9 &req={0} ?WAIT5_END_GROUP;
@!P0 STS [R8], R9 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P1 LDS R4, [R8+0x100] ?trans4;
@!P1 LDS R5, [R8] &wr=0x0 ?trans1;
ISETP.GT.U32.AND P0, PT, R2, 0x1f, PT ?trans1;
@!P1 FADD R5, R4, R5 &req={0} ?WAIT5_END_GROUP;
@!P1 STS [R8], R5 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 LDS R4, [R8+0x80] ?trans4;
@!P0 LDS R7, [R8] &wr=0x0 ?trans1;
ISETP.GT.U32.AND P1, PT, R2, 0xf, PT ?trans1;
@!P0 FADD R7, R4, R7 &req={0} ?WAIT5_END_GROUP;
@!P0 STS [R8], R7 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P1 LDS R4, [R8+0x40] ?trans4;
@!P1 LDS R9, [R8] &wr=0x0 ?trans1;
ISETP.GT.U32.AND P0, PT, R2, 0x7, PT ?trans1;
@!P1 FADD R9, R4, R9 &req={0} ?WAIT5_END_GROUP;
@!P1 STS [R8], R9 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 LDS R4, [R8+0x20] ?trans4;
@!P0 LDS R5, [R8] &wr=0x0 ?trans1;
ISETP.GT.U32.AND P1, PT, R2, 0x3, PT ?trans1;
@!P0 FADD R5, R4, R5 &req={0} ?WAIT5_END_GROUP;
@!P0 STS [R8], R5 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P1 LDS R4, [R8+0x10] ?trans4;
@!P1 LDS R7, [R8] &wr=0x0 ?trans1;
ISETP.GT.U32.AND P0, PT, R2, 0x1, PT ?trans1;
@!P1 FADD R7, R4, R7 &req={0} ?WAIT5_END_GROUP;
@!P1 STS [R8], R7 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 LDS R4, [R8+0x8] ?trans4;
@!P0 LDS R9, [R8] &wr=0x0 ?trans1;
ISETP.NE.AND P1, PT, R2, RZ, PT ?trans1;
@!P0 FADD R9, R4, R9 &req={0} ?WAIT5_END_GROUP;
@!P0 STS [R8], R9 &rd=0x0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P1 EXIT ?trans5;
LDS.64 R6, [UR4] &wr=0x1 ?trans1;
LDC.64 R4, c[0x0][0x390] &wr=0x2 ?trans1;
LEA R3, R0, R3, 0x6 ?WAIT5_END_GROUP;
IMAD.WIDE.U32 R2, R3, 0x4, R4 &req={2} ?WAIT4_END_GROUP;
FADD R7, R6, R7 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R7 ?trans1;
EXIT ?trans5;
BRA 0x5e0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: forward_step1(float*, float*, float*, unsigned int)
_Z13forward_step1PfS_S_j:
s_clause 0x4
s_load_b32 s8, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x20
s_load_b32 s3, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s8, 0xffff
s_mul_i32 s2, s2, s14
s_delay_alu instid0(VALU_DEP_1)
v_mad_u32_u24 v0, v0, s9, v1
s_add_i32 s2, s2, s13
s_lshr_b32 s8, s8, 16
s_mul_i32 s9, s2, s9
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s9, s8, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s8, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, s15, s3, v[1:2]
v_mov_b32_e32 v4, v2
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v1, v[1:2], off
global_load_b32 v2, v[3:4], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v1, v2
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s8
v_lshlrev_b32_e32 v1, 2, v0
s_mov_b32 s3, exec_lo
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 0x200, v0
s_cbranch_execz .LBB0_4
ds_load_2addr_stride64_b32 v[2:3], v1 offset1:8
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 0x100, v0
s_cbranch_execz .LBB0_6
ds_load_b32 v2, v1 offset:1024
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 0x80, v0
s_cbranch_execz .LBB0_8
ds_load_b32 v2, v1 offset:512
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 64, v0
s_cbranch_execz .LBB0_10
ds_load_b32 v2, v1 offset:256
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB0_12
ds_load_b32 v2, v1 offset:128
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 16, v0
s_cbranch_execz .LBB0_14
ds_load_b32 v2, v1 offset:64
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 8, v0
s_cbranch_execz .LBB0_16
ds_load_b32 v2, v1 offset:32
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 4, v0
s_cbranch_execz .LBB0_18
ds_load_b32 v2, v1 offset:16
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB0_18:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 2, v0
s_cbranch_execz .LBB0_20
ds_load_b32 v2, v1 offset:8
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB0_20:
s_or_b32 exec_lo, exec_lo, s3
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_22
v_mov_b32_e32 v2, 0
s_lshl_b32 s4, s15, 6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s4
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b64 v[0:1], v2
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v0, v1
global_store_b32 v2, v0, s[0:1]
.LBB0_22:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| forward_step1 | 2,164 | 2,508 | stackv2-00000-of-00015 |
// Demangled: forward_step2(float*, float*, float*)
Function : _Z13forward_step2PfS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.Y &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans6;
LDC.64 R4, c[0x0][0x380] &wr=0x2 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x3 ?trans1;
S2R R2, SR_CTAID.Z &wr=0x4 ?trans1;
IMAD R3, R3, UR4, R0 &req={1} ?WAIT4_END_GROUP;
IMAD R7, R2, 0x40, R3 &req={4} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x4, R4 &req={2} ?WAIT6_END_GROUP;
LDG.E R4, desc[UR6][R4.64] &req={3} &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GT.U32.AND P0, PT, R3.reuse, 0x1f, PT ?trans1;
ISETP.GT.U32.AND P1, PT, R3, 0xf, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R7, R3, UR4, 0x2 ?WAIT5_END_GROUP;
STS [R7], R4 &req={2} ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 LDS R0, [R7+0x80] ?trans4;
@!P0 LDS R9, [R7] &wr=0x1 ?trans2;
@!P0 FADD R0, R0, R9 &req={1} ?WAIT5_END_GROUP;
@!P0 STS [R7], R0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P0, PT, R3, 0x7, PT ?WAIT5_END_GROUP;
@!P1 LDS R5, [R7+0x40] ?trans4;
@!P1 LDS R6, [R7] &wr=0x1 ?trans2;
@!P1 FADD R6, R5, R6 &req={1} ?WAIT5_END_GROUP;
@!P1 STS [R7], R6 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P1, PT, R3, 0x3, PT ?WAIT5_END_GROUP;
@!P0 LDS R4, [R7+0x20] ?trans4;
@!P0 LDS R5, [R7] &wr=0x1 ?trans2;
@!P0 FADD R4, R4, R5 &req={1} ?WAIT5_END_GROUP;
@!P0 STS [R7], R4 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P0, PT, R3, 0x1, PT ?WAIT5_END_GROUP;
@!P1 LDS R0, [R7+0x10] ?trans4;
@!P1 LDS R5, [R7] &wr=0x1 ?trans2;
@!P1 FADD R0, R0, R5 &req={1} ?WAIT5_END_GROUP;
@!P1 STS [R7], R0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.NE.AND P1, PT, R3, RZ, PT ?WAIT5_END_GROUP;
@!P0 LDS R5, [R7+0x8] ?trans4;
@!P0 LDS R6, [R7] &wr=0x1 ?trans2;
@!P0 FADD R6, R5, R6 &req={1} ?WAIT5_END_GROUP;
@!P0 STS [R7], R6 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P1 EXIT &req={0} ?trans5;
LDC.64 R4, c[0x0][0x388] &wr=0x0 ?trans1;
LDS.64 R6, [UR4] &req={1} &wr=0x1 ?trans1;
IMAD.WIDE.U32 R4, R2, 0x4, R4 &req={0} ?WAIT6_END_GROUP;
LDG.E R4, desc[UR6][R4.64] &wr=0x1 ?trans1;
HFMA2 R0, -RZ, RZ, 0.96630859375, -0.0022525787353515625 ?trans2;
FADD R3, R7, R4 &req={1} ?trans1;
MOV R7, 0x437c0000 ?WAIT3_END_GROUP;
FADD R3, R3, R6 ?WAIT4_END_GROUP;
FFMA.SAT R0, R3, -R0, 0.5 ?trans1;
STS [UR4], R3 &rd=0x0 ?trans3;
FFMA.RM R0, R0, R7, 12582913 ?WAIT4_END_GROUP;
FADD R6, R0.reuse, -12583039 ?trans1;
IMAD.SHL.U32 R0, R0, 0x800000, RZ ?WAIT3_END_GROUP;
FFMA R6, R3, -1.4426950216293334961, -R6 ?WAIT4_END_GROUP;
FFMA R6, R3, -1.925963033500011079e-08, R6 ?WAIT4_END_GROUP;
MUFU.EX2 R5, R6 &wr=0x1 ?trans2;
FFMA R0, R0, R5, 1 &req={1} ?WAIT5_END_GROUP;
IADD3 R4, PT, PT, R0, 0x1800000, RZ ?WAIT4_END_GROUP;
LOP3.LUT R4, R4, 0x7f800000, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R4, 0x1ffffff, PT ?WAIT13_END_GROUP;
@P0 BRA 0x4a0 &req={0} ?trans5;
MOV R9, 0x480 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x520 ?trans5;
MOV R7, R3 ?trans1;
BRA 0x4e0 ?trans6;
MUFU.RCP R7, R0 &wr=0x0 ?trans2;
FFMA R3, R0, R7, -1 &req={0} ?WAIT4_END_GROUP;
FADD.FTZ R4, -R3, -RZ ?WAIT4_END_GROUP;
FFMA R7, R7, R4, R7 ?WAIT7_END_GROUP;
LDC.64 R4, c[0x0][0x390] &wr=0x0 ?trans2;
IMAD.WIDE.U32 R2, R2, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R7 ?trans1;
EXIT ?trans5;
IMAD.SHL.U32 R3, R0, 0x2, RZ ?WAIT5_END_GROUP;
SHF.R.U32.HI R3, RZ, 0x18, R3 ?WAIT5_END_GROUP;
ISETP.NE.U32.AND P0, PT, R3, RZ, PT ?WAIT13_END_GROUP;
@P0 BRA 0x610 ?trans5;
IMAD.SHL.U32 R3, R0, 0x2, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R3, RZ, PT ?WAIT13_END_GROUP;
@!P0 MUFU.RCP R3, R0 &rd=0x2 &wr=0x3 ?trans1;
@!P0 BRA 0x830 ?trans5;
FFMA R4, R0, 1.84467440737095516160e+19, RZ ?WAIT4_END_GROUP;
MUFU.RCP R3, R4 &req={3} &wr=0x0 ?trans2;
FFMA R0, R4, R3, -1 &req={2,0} ?WAIT4_END_GROUP;
FADD.FTZ R0, -R0, -RZ ?WAIT4_END_GROUP;
FFMA R0, R3, R0, R3 ?WAIT4_END_GROUP;
FFMA R3, R0, 1.84467440737095516160e+19, RZ ?trans1;
BRA 0x830 ?trans6;
IADD3 R4, PT, PT, R3, -0xfd, RZ ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R4, 0x1, PT ?WAIT13_END_GROUP;
@P0 BRA 0x820 ?trans5;
LOP3.LUT R5, R0, 0x7fffff, RZ, 0xc0, !PT ?trans1;
HFMA2 R11, -RZ, RZ, 0, 1.78813934326171875e-07 ?WAIT3_END_GROUP;
LOP3.LUT R5, R5, 0x3f800000, RZ, 0xfc, !PT ?trans2;
SHF.L.U32 R10, R11, R4, RZ ?trans2;
MUFU.RCP R6, R5 &wr=0x0 ?trans2;
FFMA R7, R5, R6, -1 &req={0} ?WAIT4_END_GROUP;
FADD.FTZ R7, -R7, -RZ ?WAIT4_END_GROUP;
FFMA.RM R8, R6.reuse, R7.reuse, R6.reuse ?trans1;
FFMA.RP R7, R6, R7, R6 ?WAIT5_END_GROUP;
FSETP.NEU.FTZ.AND P0, PT, R8.reuse, R7, PT ?trans1;
LOP3.LUT R8, R8, 0x7fffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
LOP3.LUT R7, R8, 0x800000, RZ, 0xfc, !PT ?trans1;
SEL R6, RZ, 0xffffffff, !P0 ?WAIT3_END_GROUP;
LOP3.LUT R5, R10, R7, RZ, 0xc0, !PT ?trans2;
IADD3 R6, PT, PT, -R6, RZ, RZ ?trans2;
SHF.R.U32.HI R5, RZ, R4.reuse, R5 ?trans2;
LOP3.LUT P1, RZ, R6, R4, R7, 0xf8, !PT ?trans2;
LOP3.LUT P0, RZ, R5.reuse, 0x1, RZ, 0xc0, !PT ?trans2;
LOP3.LUT P2, RZ, R5, 0x2, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ?trans2;
LOP3.LUT P1, RZ, R0, 0x7fffff, RZ, 0xc0, !PT ?WAIT3_END_GROUP;
SEL R4, RZ, 0x1, !P0 ?WAIT5_END_GROUP;
IADD3 R4, PT, PT, -R4, RZ, RZ ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R4, RZ, PT ?trans1;
IADD3 R4, PT, PT, R3, -0xfc, RZ ?WAIT4_END_GROUP;
SHF.R.U32.HI R3, RZ, R4, R7 ?WAIT8_END_GROUP;
@!P0 IADD3 R3, PT, PT, R3, 0x1, RZ ?WAIT5_END_GROUP;
@!P1 IMAD.SHL.U32 R3, R3, 0x2, RZ ?WAIT5_END_GROUP;
LOP3.LUT R3, R3, 0x80000000, R0, 0xf8, !PT ?trans1;
BRA 0x830 ?trans6;
MUFU.RCP R3, R0 &rd=0x0 &wr=0x1 ?trans2;
MOV R4, R9 ?trans1;
MOV R5, 0x0 ?WAIT4_END_GROUP;
RET.REL.NODEC R4 0x0 &req={3,2,1,0} ?trans5;
BRA 0x860;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: forward_step2(float*, float*, float*)
_Z13forward_step2PfS_S_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u32_u24 v0, v0, s3, v1
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v1, s2, 6, v0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB1_2
ds_load_2addr_b32 v[2:3], v1 offset1:32
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 16, v0
s_cbranch_execz .LBB1_4
ds_load_b32 v2, v1 offset:64
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 8, v0
s_cbranch_execz .LBB1_6
ds_load_b32 v2, v1 offset:32
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 4, v0
s_cbranch_execz .LBB1_8
ds_load_b32 v2, v1 offset:16
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB1_8:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 2, v0
s_cbranch_execz .LBB1_10
ds_load_b32 v2, v1 offset:8
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB1_10:
s_or_b32 exec_lo, exec_lo, s3
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_12
s_lshl_b64 s[2:3], s[2:3], 2
s_load_b64 s[0:1], s[0:1], 0x10
s_add_u32 s4, s6, s2
s_addc_u32 s5, s7, s3
s_load_b32 s4, s[4:5], 0x0
v_mov_b32_e32 v2, 0
ds_load_b64 v[0:1], v2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
v_add_f32_e32 v1, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, v0, v1
v_mul_f32_e32 v1, 0xbfb8aa3b, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v3, 0xbfb8aa3b, v0, -v1
v_rndne_f32_e32 v4, v1
v_sub_f32_e32 v1, v1, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmamk_f32 v3, v0, 0xb2a5705f, v3
v_cmp_nlt_f32_e32 vcc_lo, 0x42ce8ed0, v0
v_add_f32_e32 v1, v1, v3
v_cvt_i32_f32_e32 v3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_ldexp_f32 v1, v1, v3
v_cndmask_b32_e32 v1, 0, v1, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2b17218, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, 0x7f800000, v1, vcc_lo
v_add_f32_e32 v1, 1.0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v3, null, v1, v1, 1.0
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v4
v_div_scale_f32 v5, vcc_lo, 1.0, v1, 1.0
v_mul_f32_e32 v6, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v3, v6, v5
v_fmac_f32_e32 v6, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v6, v5
v_div_fmas_f32 v3, v3, v4, v6
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v1, v3, v1, 1.0
ds_store_b32 v2, v0
global_store_b32 v2, v1, s[0:1]
.LBB1_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| forward_step2 | 3,329 | 2,341 | stackv2-00000-of-00015 |
// Demangled: grad_desc(float*, float*, unsigned int, unsigned int, float)
Function : _Z9grad_descPfS_jjf
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_CTAID.Z &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x2 ?trans1;
S2R R3, SR_CTAID.Y &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x364] &wr=0x3 ?trans1;
S2R R5, SR_CTAID.X &wr=0x4 ?trans1;
LDCU UR6, c[0x0][0x368] &wr=0x5 ?trans1;
S2R R7, SR_TID.Z &wr=0x5 ?trans1;
LDCU UR7, c[0x0][0x370] &wr=0x4 ?trans1;
S2R R9, SR_TID.Y &wr=0x3 ?trans1;
LDCU UR8, c[0x0][0x374] &wr=0x1 ?trans1;
S2R R11, SR_TID.X &wr=0x2 ?trans1;
IMAD R0, R0, UR8, R3 &req={1} ?trans1;
LDCU UR8, c[0x0][0x390] &wr=0x1 ?trans3;
IMAD R0, R0, UR7, R5 &req={4} ?WAIT4_END_GROUP;
IMAD R0, R0, UR6, R7 &req={5} ?WAIT4_END_GROUP;
IMAD R0, R0, UR5, R9 &req={3} ?WAIT4_END_GROUP;
IMAD R3, R0, UR4, R11 &req={2} ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R3, UR8, PT &req={1} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R6, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
LDCU UR6, c[0x0][0x394] &wr=0x2 ?trans6;
LDC.64 R4, c[0x0][0x388] &wr=0x3 ?trans1;
IMAD.WIDE.U32 R6, R3, 0x4, R6 &req={0} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR4][R6.64] &req={1} &wr=0x4 ?trans1;
IMAD.WIDE.U32 R4, R3, 0x4, R4 &req={3} ?WAIT5_END_GROUP;
LDG.E R2, desc[UR4][R4.64] &rd=0x0 &wr=0x5 ?trans1;
I2FP.F32.U32 R3, UR6 &req={2} ?trans1;
LDCU UR6, c[0x0][0x398] &wr=0x4 ?trans1;
BSSY.RECONVERGENT B0, 0x2c0 ?trans2;
MUFU.RCP R8, R3 &wr=0x1 ?trans2;
FFMA R9, -R3, R8, 1 &req={1} ?WAIT4_END_GROUP;
FFMA R9, R8, R9, R8 ?trans1;
FMUL R0, R0, UR6 &req={4} ?WAIT4_END_GROUP;
FCHK P0, R0, R3 &wr=0x1 ?trans1;
FFMA R6, R0, R9, RZ ?WAIT4_END_GROUP;
FFMA R7, -R3, R6, R0 ?WAIT4_END_GROUP;
FFMA R7, R9, R7, R6 ?trans1;
@!P0 BRA 0x2b0 &req={1,0} ?trans6;
MOV R6, 0x2a0 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x2f0 &req={5} ?trans5;
MOV R7, R9 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
FADD R7, R2, -R7 &req={5} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64], R7 ?trans1;
EXIT ?trans5;
SHF.R.U32.HI R8, RZ, 0x17, R3 ?trans1;
BSSY.RECONVERGENT B1, 0x950 ?trans1;
SHF.R.U32.HI R7, RZ, 0x17, R0 ?trans2;
LOP3.LUT R8, R8, 0xff, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ?trans1;
MOV R9, R0 ?trans1;
IADD3 R13, PT, PT, R8, -0x1, RZ ?trans1;
MOV R10, R3 ?trans1;
IADD3 R12, PT, PT, R7, -0x1, RZ ?WAIT3_END_GROUP;
ISETP.GT.U32.AND P0, PT, R13, 0xfd, PT ?WAIT5_END_GROUP;
ISETP.GT.U32.OR P0, PT, R12, 0xfd, P0 ?WAIT13_END_GROUP;
@!P0 MOV R11, RZ ?trans1;
@!P0 BRA 0x530 ?trans6;
FSETP.GTU.FTZ.AND P0, PT, |R0|, +INF , PT ?trans1;
FSETP.GTU.FTZ.AND P1, PT, |R3|, +INF , PT ?WAIT5_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, PT, 0xf8, 0x8f ?WAIT13_END_GROUP;
@P0 BRA 0x930 ?trans5;
LOP3.LUT P0, RZ, R10, 0x7fffffff, R9, 0xc8, !PT ?WAIT13_END_GROUP;
@!P0 BRA 0x910 ?trans5;
FSETP.NEU.FTZ.AND P2, PT, |R0|.reuse, +INF , PT ?trans1;
FSETP.NEU.FTZ.AND P1, PT, |R3|, +INF , PT ?trans1;
FSETP.NEU.FTZ.AND P0, PT, |R0|, +INF , PT ?WAIT12_END_GROUP;
@!P1 BRA !P2, 0x910 ?trans5;
LOP3.LUT P2, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P1, PT, P1, P2, PT, 0x2f, 0xf2 ?WAIT13_END_GROUP;
@P1 BRA 0x8f0 ?trans5;
LOP3.LUT P1, RZ, R10, 0x7fffffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, PT, 0x2f, 0xf2 ?WAIT13_END_GROUP;
@P0 BRA 0x8c0 ?trans5;
ISETP.GE.AND P0, PT, R12, RZ, PT ?trans1;
ISETP.GE.AND P1, PT, R13, RZ, PT ?WAIT12_END_GROUP;
@P0 MOV R11, RZ ?trans1;
@!P0 MOV R11, 0xffffffc0 ?trans1;
@!P0 FFMA R9, R0, 1.84467440737095516160e+19, RZ ?trans1;
@!P1 FFMA R10, R3, 1.84467440737095516160e+19, RZ ?WAIT3_END_GROUP;
@!P1 IADD3 R11, PT, PT, R11, 0x40, RZ ?WAIT7_END_GROUP;
LEA R3, R8, 0xc0800000, 0x17 ?trans1;
BSSY.RECONVERGENT B2, 0x8b0 ?trans1;
IADD3 R7, PT, PT, R7, -0x7f, RZ ?trans2;
IADD3 R3, PT, PT, -R3, R10, RZ ?WAIT3_END_GROUP;
IMAD R0, R7.reuse, -0x800000, R9 ?trans1;
IADD3 R8, PT, PT, R7, 0x7f, -R8 ?trans1;
MUFU.RCP R10, R3 &wr=0x0 ?trans1;
FADD.FTZ R13, -R3, -RZ ?trans2;
IADD3 R8, PT, PT, R8, R11, RZ ?trans2;
FFMA R15, R10, R13, 1 &req={0} ?WAIT4_END_GROUP;
FFMA R12, R10, R15, R10 ?WAIT4_END_GROUP;
FFMA R9, R0, R12, RZ ?WAIT4_END_GROUP;
FFMA R10, R13, R9, R0 ?WAIT4_END_GROUP;
FFMA R15, R12, R10, R9 ?WAIT4_END_GROUP;
FFMA R10, R13, R15, R0 ?WAIT4_END_GROUP;
FFMA R9, R12, R10, R15 ?WAIT5_END_GROUP;
SHF.R.U32.HI R0, RZ, 0x17, R9 ?WAIT4_END_GROUP;
LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R11, PT, PT, R0, R8, RZ ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R11, -0x1, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R0, 0xfe, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x890 ?trans5;
ISETP.GT.AND P0, PT, R11, 0xfe, PT ?WAIT13_END_GROUP;
@P0 BRA 0x860 ?trans5;
ISETP.GE.AND P0, PT, R11, 0x1, PT ?WAIT13_END_GROUP;
@P0 BRA 0x8a0 ?trans5;
ISETP.GE.AND P0, PT, R11, -0x18, PT ?trans1;
LOP3.LUT R9, R9, 0x80000000, RZ, 0xc0, !PT ?WAIT12_END_GROUP;
@!P0 BRA 0x8a0 ?trans5;
FFMA.RZ R0, R12.reuse, R10.reuse, R15.reuse ?trans1;
IADD3 R8, PT, PT, R11.reuse, 0x20, RZ ?trans1;
FFMA.RM R3, R12, R10, R15 ?trans1;
ISETP.NE.AND P1, PT, R11.reuse, RZ, PT ?trans1;
ISETP.NE.AND P2, PT, R11, RZ, PT ?trans1;
LOP3.LUT R0, R0, 0x7fffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
LOP3.LUT R7, R0, 0x800000, RZ, 0xfc, !PT ?trans1;
FFMA.RP R0, R12, R10, R15 ?trans1;
IADD3 R10, PT, PT, -R11, RZ, RZ ?trans2;
SHF.L.U32 R8, R7, R8, RZ ?trans2;
FSETP.NEU.FTZ.AND P0, PT, R0, R3, PT ?trans1;
SEL R0, R10, RZ, P2 ?trans2;
ISETP.NE.AND P1, PT, R8, RZ, P1 ?WAIT3_END_GROUP;
SHF.R.U32.HI R0, RZ, R0, R7 ?trans2;
PLOP3.LUT P0, PT, P0, P1, PT, 0xf8, 0x8f ?trans2;
SHF.R.U32.HI R8, RZ, 0x1, R0 ?WAIT3_END_GROUP;
SEL R3, RZ, 0x1, !P0 ?WAIT5_END_GROUP;
LOP3.LUT R3, R3, 0x1, R8, 0xf8, !PT ?WAIT4_END_GROUP;
LOP3.LUT R3, R3, R0, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R8, PT, PT, R8, R3, RZ ?WAIT4_END_GROUP;
LOP3.LUT R9, R8, R9, RZ, 0xfc, !PT ?trans1;
BRA 0x8a0 ?trans6;
LOP3.LUT R9, R9, 0x80000000, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
LOP3.LUT R9, R9, 0x7f800000, RZ, 0xfc, !PT ?trans1;
BRA 0x8a0 ?trans6;
IMAD R9, R8, 0x800000, R9 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
BRA 0x940 ?trans5;
LOP3.LUT R9, R10, 0x80000000, R9, 0x48, !PT ?WAIT4_END_GROUP;
LOP3.LUT R9, R9, 0x7f800000, RZ, 0xfc, !PT ?trans1;
BRA 0x940 ?trans6;
LOP3.LUT R9, R10, 0x80000000, R9, 0x48, !PT ?trans1;
BRA 0x940 ?trans6;
MUFU.RSQ R9, -QNAN &wr=0x0 ?trans1;
BRA 0x940 ?trans5;
FADD.FTZ R9, R0, R3 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B1 ?trans5;
HFMA2 R7, -RZ, RZ, 0, 0 ?WAIT4_END_GROUP;
RET.REL.NODEC R6 0x0 &req={0} ?trans5;
BRA 0x970;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: grad_desc(float*, float*, unsigned int, unsigned int, float)
_Z9grad_descPfS_jjf:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x20
s_load_b64 s[8:9], s[0:1], 0x2c
v_bfe_u32 v1, v0, 20, 10
s_load_b128 s[4:7], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s14
s_mul_i32 s2, s3, s2
s_and_b32 s3, s9, 0xffff
s_add_i32 s2, s2, s13
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s2, s3, v[1:2]
v_bfe_u32 v1, v0, 10, 10
s_lshr_b32 s2, s8, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, v2, s2, v[1:2]
v_and_b32_e32 v2, 0x3ff, v0
s_and_b32 s2, s8, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, v3, s2, v[2:3]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB7_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v1, 0
v_cvt_f32_u32_e32 v4, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(1)
v_mul_f32_e32 v2, s6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v5, null, v4, v4, v2
v_rcp_f32_e32 v6, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v7, -v5, v6, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v7, v6
v_div_scale_f32 v7, vcc_lo, v2, v4, v2
v_mul_f32_e32 v8, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v9, -v5, v8, v7
v_fmac_f32_e32 v8, v9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, -v5, v8, v7
v_div_fmas_f32 v5, v5, v6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fixup_f32 v2, v5, v4, v2
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB7_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| grad_desc | 3,725 | 1,243 | stackv2-00000-of-00015 |
// Demangled: output_error(float*, float*, float*)
Function : _Z12output_errorPfS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R11, SR_CTAID.Z &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD.WIDE.U32 R2, R11, 0x4, R2 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R11.reuse, 0x4, R4 &req={2} ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans4;
LDG.E R5, desc[UR4][R4.64] &wr=0x4 ?trans1;
IMAD.WIDE.U32 R6, R11, 0x4, R6 &req={3} ?WAIT4_END_GROUP;
FADD R0, -R2.reuse, 1 &req={2} ?trans1;
FADD R9, R2, -R5 &req={4} ?WAIT4_END_GROUP;
FMUL R9, R2, R9 ?WAIT4_END_GROUP;
FMUL R9, R9, R0 ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x110;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: output_error(float*, float*, float*)
_Z12output_errorPfS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_mov_b32 s3, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt lgkmcnt(0)
v_sub_f32_e64 v1, 1.0, s4
v_sub_f32_e64 v0, s4, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v0, s4, v0
v_dual_mul_f32 v0, v1, v0 :: v_dual_mov_b32 v1, 0
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| output_error | 493 | 400 | stackv2-00000-of-00015 |
// Demangled: sum_of_1024(float*, float*, unsigned int, unsigned int)
Function : _Z11sum_of_1024PfS_jj
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R5, SR_TID.Y &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans6;
S2UR UR6, SR_CTAID.Y ?trans1;
S2R R2, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x394] &wr=0x2 ?trans1;
S2R R0, SR_CTAID.X &wr=0x3 ?trans1;
LDCU.64 UR8, c[0x0][0x358] &wr=0x4 ?trans1;
IMAD R5, R5, UR4, R2 &req={1} ?trans1;
LDCU UR4, c[0x0][0x374] &wr=0x1 ?trans4;
LEA R4, R0, R5, 0xa &req={3} ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R4, UR5, PT &req={2} ?trans1;
S2UR UR5, SR_CTAID.Z &wr=0x1 ?WAIT12_END_GROUP;
@!P0 LDC R7, c[0x0][0x390] &wr=0x2 ?trans8;
@!P0 LDC.64 R2, c[0x0][0x380] &wr=0x3 ?trans1;
UIMAD UR4, UR4, UR5, UR6 &req={1} ?WAIT6_END_GROUP;
@!P0 IMAD R7, R4, R7, UR4 &req={2} ?trans2;
HFMA2 R4, -RZ, RZ, 0, 0 ?trans2;
@!P0 IMAD.WIDE.U32 R2, R7, 0x4, R2 &req={3} ?WAIT5_END_GROUP;
@!P0 LDG.E R4, desc[UR8][R2.64] &req={4} &wr=0x2 ?trans1;
S2UR UR6, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR5, 0x400 ?trans1;
ISETP.GT.U32.AND P0, PT, R5.reuse, 0x1ff, PT ?trans1;
ISETP.GT.U32.AND P1, PT, R5, 0xff, PT ?trans1;
ULEA UR5, UR6, UR5, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R7, R5, UR5, 0x2 ?WAIT5_END_GROUP;
STS [R7], R4 &req={2} ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 LDS R6, [R7+0x800] ?trans4;
@!P0 LDS R9, [R7] &wr=0x1 ?trans2;
@!P0 FADD R6, R6, R9 &req={1} ?WAIT5_END_GROUP;
@!P0 STS [R7], R6 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P0, PT, R5, 0x7f, PT ?WAIT5_END_GROUP;
@!P1 LDS R2, [R7+0x400] ?trans4;
@!P1 LDS R3, [R7] &wr=0x1 ?trans2;
@!P1 FADD R2, R2, R3 &req={1} ?WAIT5_END_GROUP;
@!P1 STS [R7], R2 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P1, PT, R5, 0x3f, PT ?WAIT5_END_GROUP;
@!P0 LDS R3, [R7+0x200] ?trans4;
@!P0 LDS R4, [R7] &wr=0x1 ?trans2;
@!P0 FADD R4, R3, R4 &req={1} ?WAIT5_END_GROUP;
@!P0 STS [R7], R4 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P0, PT, R5, 0x1f, PT ?WAIT5_END_GROUP;
@!P1 LDS R3, [R7+0x100] ?trans4;
@!P1 LDS R6, [R7] &wr=0x1 ?trans2;
@!P1 FADD R6, R3, R6 &req={1} ?WAIT5_END_GROUP;
@!P1 STS [R7], R6 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P1, PT, R5, 0xf, PT ?WAIT5_END_GROUP;
@!P0 LDS R2, [R7+0x80] ?trans4;
@!P0 LDS R3, [R7] &wr=0x1 ?trans2;
@!P0 FADD R2, R2, R3 &req={1} ?WAIT5_END_GROUP;
@!P0 STS [R7], R2 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P0, PT, R5, 0x7, PT ?WAIT5_END_GROUP;
@!P1 LDS R3, [R7+0x40] ?trans4;
@!P1 LDS R4, [R7] &wr=0x1 ?trans2;
@!P1 FADD R4, R3, R4 &req={1} ?WAIT5_END_GROUP;
@!P1 STS [R7], R4 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P1, PT, R5, 0x3, PT ?WAIT5_END_GROUP;
@!P0 LDS R3, [R7+0x20] ?trans4;
@!P0 LDS R6, [R7] &wr=0x1 ?trans2;
@!P0 FADD R6, R3, R6 &req={1} ?WAIT5_END_GROUP;
@!P0 STS [R7], R6 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P0, PT, R5, 0x1, PT ?WAIT5_END_GROUP;
@!P1 LDS R2, [R7+0x10] ?trans4;
@!P1 LDS R3, [R7] &wr=0x1 ?trans2;
@!P1 FADD R2, R2, R3 &req={1} ?WAIT5_END_GROUP;
@!P1 STS [R7], R2 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.NE.AND P1, PT, R5, RZ, PT ?WAIT5_END_GROUP;
@!P0 LDS R3, [R7+0x8] ?trans4;
@!P0 LDS R4, [R7] &wr=0x1 ?trans2;
@!P0 FADD R4, R3, R4 &req={1} ?WAIT5_END_GROUP;
@!P0 STS [R7], R4 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P1 EXIT &req={0} ?trans5;
LDS.64 R4, [UR5] &req={1} &wr=0x0 ?trans1;
LDC R7, c[0x0][0x390] &wr=0x1 ?trans8;
LDC.64 R2, c[0x0][0x388] &wr=0x2 ?trans1;
IMAD R7, R0, R7, UR4 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R2, R7, 0x4, R2 &req={2} ?WAIT4_END_GROUP;
FADD R5, R4, R5 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR8][R2.64], R5 ?trans1;
EXIT ?trans5;
BRA 0x5a0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: sum_of_1024(float*, float*, unsigned int, unsigned int)
_Z11sum_of_1024PfS_jj:
s_clause 0x2
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b32 s7, s[0:1], 0x1c
v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u32_u24 v0, v0, s6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v1, s13, 10, v0
v_cmp_gt_u32_e32 vcc_lo, s5, v1
s_mul_i32 s5, s7, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s6, s5, s14
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB6_2
v_mad_u64_u32 v[2:3], null, v1, s4, s[6:7]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[2:3]
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v2, v[1:2], off
.LBB6_2:
s_or_b32 exec_lo, exec_lo, s5
v_lshlrev_b32_e32 v1, 2, v0
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 0x200, v0
s_cbranch_execz .LBB6_4
ds_load_2addr_stride64_b32 v[2:3], v1 offset1:8
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
.LBB6_4:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 0x100, v0
s_cbranch_execz .LBB6_6
ds_load_b32 v2, v1 offset:1024
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB6_6:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 0x80, v0
s_cbranch_execz .LBB6_8
ds_load_b32 v2, v1 offset:512
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB6_8:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 64, v0
s_cbranch_execz .LBB6_10
ds_load_b32 v2, v1 offset:256
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB6_10:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB6_12
ds_load_b32 v2, v1 offset:128
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB6_12:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 16, v0
s_cbranch_execz .LBB6_14
ds_load_b32 v2, v1 offset:64
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB6_14:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 8, v0
s_cbranch_execz .LBB6_16
ds_load_b32 v2, v1 offset:32
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB6_16:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 4, v0
s_cbranch_execz .LBB6_18
ds_load_b32 v2, v1 offset:16
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB6_18:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 2, v0
s_cbranch_execz .LBB6_20
ds_load_b32 v2, v1 offset:8
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB6_20:
s_or_b32 exec_lo, exec_lo, s0
s_mov_b32 s1, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB6_22
v_mov_b32_e32 v2, 0
s_mul_i32 s13, s13, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s6, s13
s_lshl_b64 s[0:1], s[0:1], 2
ds_load_b64 v[0:1], v2
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v0, v1
global_store_b32 v2, v0, s[0:1]
.LBB6_22:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| sum_of_1024 | 2,104 | 2,304 | stackv2-00000-of-00015 |
// Demangled: weight_gradient(float*, float*, float*, unsigned int, unsigned int)
Function : _Z15weight_gradientPfS_S_jj
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.Y &wr=0x1 ?trans7;
LDC R9, c[0x0][0x360] &wr=0x2 ?trans1;
LDCU.64 UR6, c[0x0][0x398] &wr=0x3 ?trans1;
S2R R2, SR_TID.X &wr=0x2 ?trans6;
S2UR UR5, SR_CTAID.Y &wr=0x1 ?trans8;
LDC R0, c[0x0][0x364] &wr=0x1 ?trans8;
S2UR UR4, SR_CTAID.X &wr=0x2 ?trans1;
IMAD R0, R0, UR5, R3 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R0, UR7, PT &req={3} ?trans1;
IMAD R9, R9, UR4, R2 &req={2} ?WAIT5_END_GROUP;
ISETP.GE.U32.OR P0, PT, R9, UR6, P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x4 ?trans1;
IMAD.WIDE.U32 R4, R0, 0x4, R4 &req={2} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR4][R4.64] &wr=0x4 ?trans1;
IMAD R9, R0, UR6, R9 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R6, R9, 0x4, R6 &req={3} ?WAIT4_END_GROUP;
FMUL R9, R2, R5 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x1a0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: weight_gradient(float*, float*, float*, unsigned int, unsigned int)
_Z15weight_gradientPfS_S_jj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_mad_u64_u32 v[2:3], null, s15, s3, v[4:5]
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s5, v2
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB5_2
s_load_b128 s[8:11], s[0:1], 0x0
v_mov_b32_e32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mov_b32_e32 v3, v1
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_lshlrev_b64 v[6:7], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s10, v6
v_add_co_ci_u32_e32 v6, vcc_lo, s11, v7, vcc_lo
global_load_b32 v7, v[3:4], off
global_load_b32 v5, v[5:6], off
v_mad_u64_u32 v[3:4], null, v2, s4, v[0:1]
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v7, v5
v_mov_b32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB5_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| weight_gradient | 724 | 950 | stackv2-00000-of-00015 |
// Demangled: vecAdd(int*, int*, int*, int)
Function : _Z6vecAddPiS_S_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x398] &wr=0x2 ?trans7;
LDC R9, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R9, R9, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R9, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD.WIDE R2, R9, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x4 ?trans1;
IMAD.WIDE R4, R9, 0x4, R4 &req={2} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR4][R4.64] &wr=0x4 ?trans1;
IMAD.WIDE R6, R9, 0x4, R6 &req={3} ?trans1;
IADD3 R9, PT, PT, R2, R5, RZ &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x140;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: vecAdd(int*, int*, int*, int)
_Z6vecAddPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| vecAdd | 572 | 576 | stackv2-00000-of-00015 |
// Demangled: bitonicsort(int*, int, int)
Function : _Z11bitonicsortPiii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R7, SR_TID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R0, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x388] &wr=0x2 ?trans1;
IMAD R7, R0, UR4, R7 &req={1} ?WAIT5_END_GROUP;
LOP3.LUT R9, R7, UR5, RZ, 0x3c, !PT &req={2} ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R9, R7, PT ?WAIT13_END_GROUP;
@!P0 EXIT &req={0} ?trans5;
LDCU UR4, c[0x0][0x38c] &wr=0x0 ?trans2;
LOP3.LUT P0, RZ, R7, UR4, RZ, 0xc0, !PT &req={0} ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?WAIT12_END_GROUP;
@P0 BRA 0x170 ?trans5;
LDC.64 R4, c[0x0][0x380] &wr=0x1 ?trans2;
IMAD.WIDE.U32 R2, R7, 0x4, R4 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R9, 0x4, R4 ?trans1;
LDG.E R7, desc[UR4][R2.64] &req={0} &wr=0x2 ?trans4;
LDG.E R0, desc[UR4][R4.64] &wr=0x2 ?trans2;
ISETP.GT.AND P0, PT, R7, R0, PT &req={2} ?WAIT13_END_GROUP;
@!P0 EXIT ?trans5;
STG.E desc[UR4][R2.64], R0 ?trans4;
STG.E desc[UR4][R4.64], R7 ?trans1;
EXIT ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans2;
IMAD.WIDE.U32 R4, R7, 0x4, R2 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R2, R9, 0x4, R2 ?trans1;
LDG.E R7, desc[UR4][R4.64] &req={0} &wr=0x2 ?trans4;
LDG.E R0, desc[UR4][R2.64] &wr=0x2 ?trans2;
ISETP.GE.AND P0, PT, R7, R0, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
STG.E desc[UR4][R4.64], R0 ?trans4;
STG.E desc[UR4][R2.64], R7 ?trans1;
EXIT ?trans5;
BRA 0x210;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: bitonicsort(int*, int, int)
_Z11bitonicsortPiii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, s15, s4, v[0:1]
v_xor_b32_e32 v0, s2, v4
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 v0, v4
s_cbranch_execz .LBB0_7
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[4:5]
v_dual_mov_b32 v1, v5 :: v_dual_and_b32 v4, s3, v4
v_lshlrev_b64 v[5:6], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v6, vcc_lo
s_mov_b32 s0, 0
s_clause 0x1
global_load_b32 v5, v[0:1], off
global_load_b32 v6, v[2:3], off
s_mov_b32 s1, exec_lo
v_cmpx_ne_u32_e32 0, v4
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB0_3
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v5, v6
s_and_b32 s0, vcc_lo, exec_lo
.LBB0_3:
s_and_not1_saveexec_b32 s1, s1
s_cbranch_execz .LBB0_5
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v5, v6
s_and_not1_b32 s0, s0, exec_lo
s_and_b32 s2, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s0, s0, s2
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_7
s_waitcnt vmcnt(0)
s_clause 0x1
global_store_b32 v[0:1], v6, off
global_store_b32 v[2:3], v5, off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| bitonicsort | 866 | 932 | stackv2-00000-of-00015 |
// Demangled: add_kernel(int*, int*, int*)
Function : _Z10add_kernelPiS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R9, SR_TID.X &wr=0x1 ?trans1;
S2R R0, SR_TID.Y &wr=0x1 ?trans2;
LOP3.LUT P0, RZ, R9, 0x3e0, R0, 0xc8, !PT &req={1} ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans1;
LEA R9, R9, R0, 0x5 ?WAIT6_END_GROUP;
LDC.64 R4, c[0x0][0x388] &wr=0x3 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x4 ?trans1;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={1} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &req={2} &wr=0x2 ?trans1;
IMAD.WIDE.U32 R4, R9, 0x4, R4 &req={3} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R6, R9, 0x4, R6 &req={4} ?trans1;
IADD3 R9, PT, PT, R2, R5, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x120;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: add_kernel(int*, int*, int*)
_Z10add_kernelPiS_S_:
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v2, v1, v0
v_cmpx_gt_u32_e32 32, v2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 5, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1)
v_add_lshl_u32 v0, v1, v0, 2
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| add_kernel | 534 | 364 | stackv2-00000-of-00015 |
// Demangled: add(int*, int*, int*)
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R9, SR_CTAID.X &wr=0x1 ?trans2;
ISETP.GT.U32.AND P0, PT, R9, 0x1869f, PT &req={1} ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x3 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x4 ?trans1;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={1} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &req={2} &wr=0x2 ?trans1;
IMAD.WIDE.U32 R4, R9, 0x4, R4 &req={3} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R6, R9, 0x4, R6 &req={4} ?trans1;
IADD3 R9, PT, PT, R2, R5, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x100;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: add(int*, int*, int*)
_Z3addPiS_S_:
s_cmp_gt_i32 s15, 0x1869f
s_cbranch_scc1 .LBB0_2
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s8, s0
s_addc_u32 s3, s9, s1
s_add_u32 s6, s6, s0
s_addc_u32 s7, s7, s1
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
s_load_b32 s0, s[0:1], 0x0
s_load_b32 s1, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[2:3]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| add | 492 | 402 | stackv2-00000-of-00015 |
// Demangled: rounding(float*, int*, Stack<Node>*)
Function : _Z8roundingPfPiP5StackI4NodeE
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R7, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x3 ?trans1;
LEA R7, R7, R7, 0x1 &req={0} ?WAIT5_END_GROUP;
IMAD.WIDE.U32 R2, R7, 0x4, R2 &req={1} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR4][R2.64] &req={2} &wr=0x2 ?trans1;
IMAD.WIDE.U32 R4, R7, 0x4, R4 &req={3} ?trans1;
F2I.FLOOR.NTZ R9, R0 &req={2} &wr=0x0 ?trans4;
STG.E desc[UR4][R4.64], R9 &req={0} ?trans4;
LDG.E R6, desc[UR4][R2.64+0x4] &wr=0x2 ?trans2;
F2I.FLOOR.NTZ R7, R6 &req={2} &wr=0x0 ?trans2;
STG.E desc[UR4][R4.64+0x4], R7 &req={0} ?trans4;
LDG.E R8, desc[UR4][R2.64+0x8] &wr=0x2 ?trans2;
F2I.FLOOR.NTZ R11, R8 &req={2} &wr=0x0 ?trans2;
STG.E desc[UR4][R4.64+0x8], R11 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x120;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: rounding(float*, int*, Stack<Node>*)
_Z8roundingPfPiP5StackI4NodeE:
s_load_b128 s[0:3], s[0:1], 0x0
v_mul_u32_u24_e32 v0, 3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v2, 2, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, s0, s0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
v_add_co_u32 v2, s0, s2, v2
v_add_co_ci_u32_e64 v3, null, s3, 0, s0
s_mov_b64 s[0:1], 0
.LBB0_1:
s_delay_alu instid0(SALU_CYCLE_1)
v_add_co_u32 v4, vcc_lo, v0, s0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_floor_f32_e32 v6, v4
v_add_co_u32 v4, vcc_lo, v2, s0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_cvt_i32_f32_e32 v6, v6
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s0, 12
global_store_b32 v[4:5], v6, off
s_cbranch_scc0 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| rounding | 559 | 535 | stackv2-00000-of-00015 |
// Demangled: seive(int*, int)
Function : _Z5seivePii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R4, SR_TID.X &wr=0x1 ?trans7;
S2UR UR5, SR_CgaCtaId &wr=0x2 ?trans1;
UMOV UR4, 0x400 ?WAIT7_END_GROUP;
S2UR UR6, SR_CTAID.X &wr=0x3 ?trans8;
LDC R5, c[0x0][0x360] &wr=0x3 ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={2} ?WAIT7_END_GROUP;
LDC.64 R2, c[0x0][0x380] &wr=0x2 ?trans1;
ISETP.GE.U32.AND P0, PT, R4.reuse, 0x100, PT &req={1} ?trans1;
LEA R0, R4, UR4, 0x2 ?WAIT6_END_GROUP;
LDC R9, c[0x0][0x388] &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x4 ?trans1;
IMAD R5, R5, UR6, R4 &req={3} ?WAIT4_END_GROUP;
@P0 LDS R7, [R0] &wr=0x3 ?trans1;
IMAD.WIDE R2, R5, 0x4, R2 &req={2} ?WAIT5_END_GROUP;
@!P0 LDG.E R7, desc[UR4][R2.64] &req={4} &wr=0x3 ?trans1;
IABS R8, R9 &req={1} ?WAIT4_END_GROUP;
I2F.RP R6, R8 &wr=0x1 ?trans2;
MUFU.RCP R6, R6 &req={1} &wr=0x1 ?trans2;
IADD3 R4, PT, PT, R6, 0xffffffe, RZ &req={1} ?WAIT4_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R5, R4 &rd=0x1 &wr=0x2 ?trans2;
HFMA2 R4, -RZ, RZ, 0, 0 &req={1} ?trans1;
IADD3 R11, PT, PT, RZ, -R5, RZ &req={2} ?WAIT5_END_GROUP;
IMAD R11, R11, R8, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R5, R5, R11, R4 ?trans1;
IABS R10, R7 &req={3} ?trans1;
@!P0 STS [R0], R7 &rd=0x1 ?trans4;
IMAD.HI.U32 R5, R5, R10, RZ ?WAIT5_END_GROUP;
IADD3 R5, PT, PT, -R5, RZ, RZ ?WAIT5_END_GROUP;
IMAD R5, R8, R5, R10 ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P1, PT, R8, R5, PT ?WAIT13_END_GROUP;
@!P1 IADD3 R5, PT, PT, R5, -R8, RZ ?trans1;
ISETP.GE.AND P1, PT, R7, RZ, PT ?WAIT4_END_GROUP;
ISETP.GT.U32.AND P2, PT, R8, R5, PT ?WAIT13_END_GROUP;
@!P2 IADD3 R5, PT, PT, R5, -R8, RZ ?trans1;
ISETP.NE.AND P2, PT, R9, RZ, PT ?WAIT3_END_GROUP;
@!P1 IADD3 R5, PT, PT, -R5, RZ, RZ ?WAIT10_END_GROUP;
@!P2 LOP3.LUT R5, RZ, R9, RZ, 0x33, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R5, RZ, PT ?WAIT13_END_GROUP;
@P1 EXIT &req={1,0} ?trans5;
STG.E desc[UR4][R2.64], RZ ?trans1;
EXIT ?trans5;
BRA 0x2a0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: seive(int*, int)
_Z5seivePii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x0
v_cmp_lt_u32_e32 vcc_lo, 0xff, v0
v_lshlrev_b32_e32 v3, 2, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_and_saveexec_b32 s4, vcc_lo
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_2
ds_load_b32 v0, v3
.LBB0_2:
s_or_saveexec_b32 s4, s4
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
s_xor_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB0_4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_waitcnt lgkmcnt(0)
global_load_b32 v0, v[4:5], off
s_waitcnt vmcnt(0)
ds_store_b32 v3, v0
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s4
s_load_b32 s0, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_ashrrev_i32_e32 v5, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v5
v_xor_b32_e32 v0, v0, v5
s_ashr_i32 s1, s0, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s0, s1
s_xor_b32 s0, s0, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v3, s0
s_sub_i32 s1, 0, s0
v_rcp_iflag_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v3, v3
v_mul_lo_u32 v4, s1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v3, v4
v_add_nc_u32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v0, v3
v_mul_lo_u32 v3, v3, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v3
v_subrev_nc_u32_e32 v3, s0, v0
v_cmp_le_u32_e32 vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
v_subrev_nc_u32_e32 v3, s0, v0
v_cmp_le_u32_e32 vcc_lo, s0, v0
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
v_xor_b32_e32 v0, v0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v5
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_6
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| seive | 1,109 | 1,511 | stackv2-00000-of-00015 |
// Demangled: matrixMul(float*, float*, float*, int, int)
Function : _Z9matrixMulPfS_S_ii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
LDC R0, c[0x0][0x398] &wr=0x1 ?trans1;
S2R R2, SR_TID.X &wr=0x2 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x3 ?trans1;
HFMA2 R22, -RZ, RZ, 0, 0 ?trans1;
S2R R4, SR_TID.Y &wr=0x4 ?trans4;
LDC R29, c[0x0][0x360] &wr=0x2 ?trans8;
S2UR UR4, SR_CTAID.X &wr=0x2 ?trans8;
S2UR UR5, SR_CTAID.Y &wr=0x4 ?trans1;
ISETP.GE.AND P0, PT, R0, 0x1, PT &req={1} ?WAIT7_END_GROUP;
LDC R31, c[0x0][0x364] &wr=0x4 ?trans1;
IMAD R29, R29, UR4, R2 &req={2} ?trans2;
IMAD R31, R31, UR5, R4 &req={4} ?WAIT3_END_GROUP;
@!P0 BRA 0xa50 &req={3,0} ?trans5;
ISETP.GE.U32.AND P1, PT, R0.reuse, 0x8, PT ?trans1;
LOP3.LUT R17, R0, 0x7, RZ, 0xc0, !PT ?trans1;
UMOV UR4, URZ ?trans1;
IMAD R16, R31, R0, RZ ?trans1;
MOV R22, RZ ?trans2;
ISETP.NE.AND P0, PT, R17, RZ, PT ?WAIT7_END_GROUP;
@!P1 BRA 0x580 ?trans6;
LDC R14, c[0x0][0x39c] &wr=0x0 ?trans1;
LOP3.LUT R28, R0, 0x7ffffff8, RZ, 0xc0, !PT ?trans1;
UMOV UR4, URZ ?trans1;
MOV R22, RZ ?trans1;
MOV R33, R29 ?trans1;
IADD3 R28, PT, PT, -R28, RZ, RZ ?WAIT3_END_GROUP;
LDC.64 R18, c[0x0][0x388] &wr=0x1 ?trans1;
SHF.R.S32.HI R15, RZ, 0x1f, R14 &req={0} ?WAIT5_END_GROUP;
IADD.64 R2, R14, R14 ?trans2;
IMAD.WIDE.U32 R18, R16, 0x4, R18 &req={1} ?trans2;
IADD.64 R4, R14, R2 ?WAIT3_END_GROUP;
SHF.L.U64.HI R13, R2, 0x2, R3 ?trans1;
IADD.64 R6, R14, R4 ?trans2;
IMAD.SHL.U32 R12, R2, 0x4, RZ ?trans1;
SHF.L.U64.HI R11, R4, 0x2, R5 ?trans1;
IADD.64 R2, R14, R6 ?trans2;
IMAD.SHL.U32 R10, R4, 0x4, RZ ?trans1;
SHF.L.U64.HI R9, R6, 0x2, R7 ?trans1;
IADD.64 R4, R14, R2 ?trans2;
IMAD.SHL.U32 R8, R6, 0x4, RZ ?trans1;
IADD.64 R18, R18, 0x10 ?WAIT2_END_GROUP;
IADD.64 R20, R14, R4 ?trans2;
IMAD.SHL.U32 R6, R2.reuse, 0x4, RZ ?trans1;
SHF.L.U64.HI R7, R2, 0x2, R3 ?trans2;
SHF.L.U64.HI R5, R4.reuse, 0x2, R5 ?trans1;
IMAD.SHL.U32 R4, R4, 0x4, RZ ?trans1;
SHF.L.U64.HI R3, R20.reuse, 0x2, R21 ?trans1;
IMAD.SHL.U32 R2, R20, 0x4, RZ ?WAIT7_END_GROUP;
LDC.64 R26, c[0x0][0x390] &wr=0x0 ?trans1;
LDG.E R23, desc[UR6][R18.64+-0x10] &wr=0x2 ?trans4;
LDG.E R32, desc[UR6][R18.64+-0xc] &wr=0x3 ?trans4;
LDG.E R37, desc[UR6][R18.64+-0x8] &wr=0x4 ?trans4;
LDG.E R36, desc[UR6][R18.64+-0x4] &wr=0x5 ?trans1;
IMAD.WIDE R26, R33, 0x4, R26 &req={0} ?WAIT5_END_GROUP;
LDG.E R30, desc[UR6][R26.64] &wr=0x2 ?trans1;
IMAD.WIDE R24, R14, 0x4, R26 ?trans1;
IADD.64 R20, R26.reuse, R12 ?trans2;
IADD.64 R34, R26, R10 ?WAIT3_END_GROUP;
LDG.E R25, desc[UR6][R24.64] &wr=0x3 ?trans4;
LDG.E R20, desc[UR6][R20.64] &wr=0x4 ?trans4;
LDG.E R35, desc[UR6][R34.64] &wr=0x5 ?trans4;
LDG.E R34, desc[UR6][R18.64+0xc] &wr=0x5 ?trans1;
FFMA R23, R23, R30, R22 &req={2} ?WAIT4_END_GROUP;
FFMA R23, R32, R25, R23 &req={3} ?trans2;
LDG.E R32, desc[UR6][R18.64+0x4] &wr=0x2 ?trans2;
FFMA R23, R37, R20, R23 &req={4} ?trans1;
IADD.64 R20, R26.reuse, R8 ?trans2;
IADD.64 R24, R26, R4 ?trans2;
FFMA R30, R36, R35, R23 &req={5} ?trans1;
IADD.64 R22, R26, R6 ?WAIT2_END_GROUP;
LDG.E R20, desc[UR6][R20.64] &wr=0x3 ?trans4;
LDG.E R35, desc[UR6][R18.64] &wr=0x3 ?trans1;
IADD.64 R26, R26, R2 ?WAIT3_END_GROUP;
LDG.E R23, desc[UR6][R22.64] &wr=0x2 ?trans4;
LDG.E R24, desc[UR6][R24.64] &wr=0x4 ?trans4;
LDG.E R37, desc[UR6][R18.64+0x8] &rd=0x0 &wr=0x4 ?trans4;
LDG.E R27, desc[UR6][R26.64] &wr=0x5 ?trans1;
IADD3 R28, PT, PT, R28, 0x8, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R28, RZ, PT ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x8, URZ ?trans1;
IADD.64 R18, R18, 0x20 &req={0} ?trans2;
IMAD R33, R14, 0x8, R33 ?trans2;
FFMA R35, R35, R20, R30 &req={3} ?WAIT4_END_GROUP;
FFMA R32, R32, R23, R35 &req={2} ?WAIT4_END_GROUP;
FFMA R32, R37, R24, R32 &req={4} ?WAIT4_END_GROUP;
FFMA R22, R34, R27, R32 &req={5} ?trans1;
@P1 BRA 0x310 ?trans6;
@!P0 BRA 0xa50 ?trans5;
ISETP.GE.U32.AND P1, PT, R17, 0x4, PT ?trans1;
LOP3.LUT R19, R0, 0x3, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R19, RZ, PT ?WAIT7_END_GROUP;
@!P1 BRA 0x7f0 ?trans6;
LDC R12, c[0x0][0x39c] &wr=0x0 ?trans1;
LDCU.64 UR8, c[0x0][0x388] &wr=0x1 ?trans1;
HFMA2 R17, -RZ, RZ, 0, 0 ?trans1;
IADD3 R7, PT, PT, R16, UR4, RZ ?trans1;
UMOV UR5, URZ ?WAIT3_END_GROUP;
IADD.64 R8, R16, UR4 ?trans2;
LDC.64 R4, c[0x0][0x390] &wr=0x2 ?trans8;
LDC.64 R10, c[0x0][0x388] &wr=0x3 ?trans1;
LEA R2, P1, R8, UR8, 0x2 &req={1} ?trans1;
IMAD R3, R12, UR4, R29 &req={0} ?trans1;
SHF.R.S32.HI R13, RZ, 0x1f, R12 ?WAIT5_END_GROUP;
IADD.64 R14, R12, R12 ?trans2;
IMAD.WIDE R4, R3, 0x4, R4 &req={2} ?trans1;
LEA.HI.X R3, R8, UR9, R9, 0x2, P1 ?trans1;
IADD.64 R8, R12, R14 ?WAIT3_END_GROUP;
LEA R6, P1, R14, R4.reuse, 0x2 ?trans1;
IMAD.WIDE R12, R12, 0x4, R4 ?trans1;
LDG.E R18, desc[UR6][R4.64] &wr=0x2 ?trans3;
IMAD.WIDE.U32 R10, R7, 0x4, R10 &req={3} ?trans1;
LEA.HI.X R7, R14, R5, R15, 0x2, P1 ?trans1;
LDG.E R12, desc[UR6][R12.64] &wr=0x3 ?trans1;
LEA R14, P1, R8, R4, 0x2 ?WAIT3_END_GROUP;
LDG.E R11, desc[UR6][R10.64] &wr=0x2 ?trans1;
LEA.HI.X R15, R8, R5, R9, 0x2, P1 ?WAIT3_END_GROUP;
LDG.E R20, desc[UR6][R2.64+0x4] &wr=0x3 ?trans4;
LDG.E R6, desc[UR6][R6.64] &wr=0x4 ?trans4;
LDG.E R8, desc[UR6][R2.64+0x8] &wr=0x4 ?trans4;
LDG.E R9, desc[UR6][R2.64+0xc] &wr=0x5 ?trans4;
LDG.E R14, desc[UR6][R14.64] &wr=0x5 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x4, URZ ?trans1;
FFMA R11, R11, R18, R22 &req={2} ?WAIT4_END_GROUP;
FFMA R11, R20, R12, R11 &req={3} ?WAIT4_END_GROUP;
FFMA R8, R8, R6, R11 &req={4} ?WAIT4_END_GROUP;
FFMA R22, R9, R14, R8 &req={5} ?WAIT7_END_GROUP;
@!P0 BRA 0xa50 ?trans5;
ISETP.NE.AND P1, PT, R19, 0x1, PT ?trans1;
LOP3.LUT R2, R0, 0x1, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.U32.AND P0, PT, R2, 0x1, PT ?WAIT7_END_GROUP;
@!P1 BRA 0x9a0 ?trans6;
LDC R10, c[0x0][0x39c] &wr=0x0 ?trans1;
LDCU.64 UR8, c[0x0][0x388] &wr=0x1 ?trans1;
MOV R6, R16 ?trans1;
HFMA2 R7, -RZ, RZ, 0, 0 ?trans1;
IADD3 R9, PT, PT, R16, UR4, RZ ?trans1;
UMOV UR5, URZ ?WAIT3_END_GROUP;
LDC.64 R4, c[0x0][0x390] &wr=0x2 ?trans1;
IADD.64 R6, R6, UR4 ?WAIT7_END_GROUP;
LDC.64 R2, c[0x0][0x388] &wr=0x3 ?trans1;
LEA R8, P1, R6, UR8, 0x2 &req={1} ?trans1;
IMAD R11, R10, UR4, R29 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE R4, R11, 0x4, R4 &req={2} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={3} ?trans1;
LEA.HI.X R9, R6, UR9, R7, 0x2, P1 ?WAIT3_END_GROUP;
IMAD.WIDE R6, R10, 0x4, R4 ?trans2;
LDG.E R3, desc[UR6][R2.64] &wr=0x2 ?trans4;
LDG.E R4, desc[UR6][R4.64] &wr=0x2 ?trans4;
LDG.E R9, desc[UR6][R8.64+0x4] &wr=0x3 ?trans4;
LDG.E R6, desc[UR6][R6.64] &wr=0x3 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x2, URZ ?trans1;
FFMA R22, R3, R4, R22 &req={2} ?WAIT4_END_GROUP;
FFMA R22, R9, R6, R22 &req={3} ?WAIT7_END_GROUP;
@P0 BRA 0xa50 ?trans5;
LDC R6, c[0x0][0x39c] &wr=0x0 ?trans1;
IADD3 R17, PT, PT, R16, UR4, RZ ?WAIT7_END_GROUP;
LDC.64 R2, c[0x0][0x388] &wr=0x1 ?trans8;
LDC.64 R4, c[0x0][0x390] &wr=0x2 ?trans1;
IMAD R7, R6, UR4, R29 &req={0} ?trans2;
IMAD.WIDE.U32 R2, R17, 0x4, R2 &req={1} ?WAIT6_END_GROUP;
LDG.E R3, desc[UR6][R2.64] &wr=0x3 ?trans1;
IMAD.WIDE R4, R7, 0x4, R4 &req={2} ?WAIT6_END_GROUP;
LDG.E R4, desc[UR6][R4.64] &wr=0x3 ?trans2;
FFMA R22, R3, R4, R22 &req={3} ?WAIT7_END_GROUP;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
IMAD R29, R31, R0, R29 ?WAIT4_END_GROUP;
IMAD.WIDE R2, R29, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R22 ?trans1;
EXIT ?trans5;
BRA 0xaa0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: matrixMul(float*, float*, float*, int, int)
_Z9matrixMulPfS_S_ii:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x2c
s_load_b256 s[0:7], s[0:1], 0x0
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s9, s8, 16
s_and_b32 s8, s8, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s9, v[1:2]
v_and_b32_e32 v3, 0x3ff, v0
s_cmp_lt_i32 s6, 1
v_mad_u64_u32 v[0:1], null, s14, s8, v[3:4]
s_delay_alu instid0(VALU_DEP_3)
v_mul_lo_u32 v1, v2, s6
s_cbranch_scc1 .LBB0_3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
.LBB0_2:
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s6, s6, -1
s_cmp_lg_u32 s6, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s7, v4
v_add_co_u32 v7, vcc_lo, s4, v7
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc1 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v1, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| matrixMul | 4,382 | 1,101 | stackv2-00000-of-00015 |
// Demangled: matrixVectorMultiplication(int*, int*, int*, int)
Function : _Z26matrixVectorMultiplicationPiS_S_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R3, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR8, c[0x0][0x398] &wr=0x2 ?trans1;
IMAD R0, R3, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, UR8, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
UISETP.GE.AND UP0, UPT, UR8, 0x1, UPT ?trans1;
LDCU.64 UR30, c[0x0][0x358] &wr=0x0 ?trans1;
HFMA2 R32, -RZ, RZ, 0, 0 ?WAIT4_END_GROUP;
PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x8 ?WAIT13_END_GROUP;
@!P0 BRA 0x1190 &req={0} ?trans5;
UIADD3 UR4, UPT, UPT, UR8, -0x1, URZ ?trans1;
ULOP3.LUT UR34, UR8, 0xf, URZ, 0xc0, !UPT ?trans1;
UMOV UR6, URZ ?trans1;
MOV R32, RZ ?trans1;
UISETP.GE.U32.AND UP0, UPT, UR4, 0xf, UPT ?WAIT3_END_GROUP;
ISETP.NE.AND P1, PT, RZ, UR34, PT ?WAIT3_END_GROUP;
PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x8 ?WAIT13_END_GROUP;
@!P0 BRA 0xa40 ?trans5;
USHF.L.U32 UR4, UR8, 0x1, URZ ?trans1;
UMOV UR9, URZ ?trans1;
UMOV UR5, URZ ?trans1;
HFMA2 R17, -RZ, RZ, 0, 0 ?trans1;
UIADD3.64 UR10, UPT, UPT, UR8, UR4, URZ ?trans1;
MOV R32, RZ ?trans1;
ULOP3.LUT UR6, UR8, 0x7ffffff0, URZ, 0xc0, !UPT ?trans2;
UIADD3.64 UR12, UPT, UPT, UR8, UR10, URZ ?trans1;
USHF.L.U64.HI UR7, UR10, 0x2, UR11 ?trans1;
USHF.L.U32 UR10, UR10, 0x2, URZ ?WAIT2_END_GROUP;
UIADD3.64 UR14, UPT, UPT, UR8, UR12, URZ ?trans1;
USHF.L.U64.HI UR11, UR12, 0x2, UR13 ?trans1;
USHF.L.U32 UR12, UR12, 0x2, URZ ?trans2;
UIADD3.64 UR16, UPT, UPT, UR8, UR14, URZ ?trans1;
USHF.L.U64.HI UR13, UR14, 0x2, UR15 ?trans1;
USHF.L.U32 UR14, UR14, 0x2, URZ ?trans2;
UIADD3.64 UR18, UPT, UPT, UR8, UR16, URZ ?trans1;
USHF.L.U64.HI UR15, UR16, 0x2, UR17 ?trans1;
USHF.L.U32 UR16, UR16, 0x2, URZ ?WAIT2_END_GROUP;
UIADD3.64 UR20, UPT, UPT, UR8, UR18, URZ ?trans1;
USHF.L.U64.HI UR17, UR18, 0x2, UR19 ?trans1;
USHF.L.U32 UR18, UR18, 0x2, URZ ?trans2;
UIADD3.64 UR22, UPT, UPT, UR8, UR20, URZ ?trans1;
USHF.L.U64.HI UR19, UR20, 0x2, UR21 ?trans1;
USHF.L.U32 UR20, UR20, 0x2, URZ ?trans2;
UIADD3.64 UR24, UPT, UPT, UR8, UR22, URZ ?trans1;
USHF.L.U64.HI UR21, UR22, 0x2, UR23 ?trans1;
USHF.L.U32 UR32, UR22, 0x2, URZ ?WAIT2_END_GROUP;
UIADD3.64 UR26, UPT, UPT, UR8, UR24, URZ ?trans1;
USHF.L.U64.HI UR45, UR24, 0x2, UR25 ?trans1;
USHF.L.U32 UR44, UR24, 0x2, URZ ?trans2;
UIADD3.64 UR28, UPT, UPT, UR8, UR26, URZ ?trans1;
USHF.L.U64.HI UR43, UR26, 0x2, UR27 ?trans1;
USHF.L.U32 UR42, UR26, 0x2, URZ ?trans2;
UIADD3.64 UR22, UPT, UPT, UR8, UR28, URZ ?trans1;
USHF.L.U64.HI UR41, UR28, 0x2, UR29 ?trans1;
USHF.L.U32 UR40, UR28, 0x2, URZ ?WAIT2_END_GROUP;
UIADD3.64 UR24, UPT, UPT, UR8, UR22, URZ ?trans1;
USHF.L.U64.HI UR39, UR22, 0x2, UR23 ?trans1;
USHF.L.U32 UR38, UR22, 0x2, URZ ?trans2;
UIADD3.64 UR26, UPT, UPT, UR8, UR24, URZ ?trans1;
USHF.L.U64.HI UR37, UR24, 0x2, UR25 ?trans1;
USHF.L.U32 UR36, UR24, 0x2, URZ ?trans2;
USHF.L.U64.HI UR35, UR26, 0x2, UR27 ?trans1;
USHF.L.U32 UR9, UR26, 0x2, URZ ?WAIT12_END_GROUP;
LDC.64 R4, c[0x0][0x380] &wr=0x0 ?trans1;
IMAD R7, R17, UR8, R0 ?WAIT7_END_GROUP;
LDC.64 R2, c[0x0][0x388] &wr=0x1 ?trans1;
IMAD.WIDE R4, R7, 0x4, R4 &req={0} ?trans1;
MOV R7, UR8 ?WAIT4_END_GROUP;
LDG.E R12, desc[UR30][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R2, R17, 0x4, R2 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R6, R7, 0x4, R4.reuse ?trans1;
LDG.E R13, desc[UR30][R2.64] &wr=0x2 ?trans4;
LDG.E R15, desc[UR30][R6.64] &rd=0x0 &wr=0x3 ?trans4;
LDG.E R14, desc[UR30][R2.64+0x4] &wr=0x3 ?trans1;
MOV R9, UR4 ?trans1;
UMOV UR22, UR10 ?trans1;
UMOV UR23, UR7 ?trans1;
UMOV UR24, UR12 ?trans1;
UMOV UR25, UR11 ?trans1;
IMAD.WIDE.U32 R8, R9, 0x4, R4 ?trans1;
IADD.64 R10, R4, UR22 ?WAIT2_END_GROUP;
LDG.E R16, desc[UR30][R2.64+0x8] &wr=0x4 ?trans1;
IADD.64 R20, R4, UR24 ?WAIT3_END_GROUP;
LDG.E R19, desc[UR30][R8.64] &rd=0x1 &wr=0x4 ?trans1;
UMOV UR22, UR14 ?trans1;
UMOV UR23, UR13 ?trans2;
LDG.E R18, desc[UR30][R10.64] &rd=0x5 &wr=0x4 ?trans1;
IADD.64 R34, R4, UR22 ?WAIT3_END_GROUP;
LDG.E R23, desc[UR30][R2.64+0xc] &wr=0x4 ?trans1;
UMOV UR24, UR16 ?trans1;
UMOV UR25, UR15 ?trans2;
LDG.E R20, desc[UR30][R20.64] &wr=0x4 ?trans1;
IADD.64 R28, R4, UR24 ?WAIT3_END_GROUP;
LDG.E R27, desc[UR30][R2.64+0x10] &wr=0x4 ?trans1;
UMOV UR26, UR18 ?trans1;
UMOV UR27, UR17 ?trans2;
LDG.E R30, desc[UR30][R2.64+0x14] &wr=0x4 ?trans1;
IADD.64 R6, R4, UR26 &req={0} ?WAIT3_END_GROUP;
LDG.E R21, desc[UR30][R34.64] &wr=0x4 ?trans1;
UMOV UR28, UR20 ?trans1;
UMOV UR29, UR19 ?trans2;
LDG.E R22, desc[UR30][R28.64] &wr=0x4 ?trans1;
IADD.64 R8, R4, UR28 &req={1} ?WAIT3_END_GROUP;
LDG.E R31, desc[UR30][R2.64+0x18] &wr=0x4 ?trans1;
UMOV UR33, UR21 ?WAIT3_END_GROUP;
LDG.E R24, desc[UR30][R6.64] &rd=0x0 &wr=0x4 ?trans1;
IADD.64 R10, R4, UR32 &req={5} ?WAIT3_END_GROUP;
LDG.E R29, desc[UR30][R2.64+0x1c] &wr=0x5 ?trans1;
UMOV UR22, UR44 ?trans1;
UMOV UR23, UR45 ?trans2;
LDG.E R25, desc[UR30][R8.64] &rd=0x1 &wr=0x5 ?trans1;
IADD.64 R6, R4, UR22 &req={0} ?WAIT3_END_GROUP;
LDG.E R28, desc[UR30][R2.64+0x20] &wr=0x5 ?trans1;
UMOV UR24, UR42 ?trans1;
UMOV UR25, UR43 ?trans2;
LDG.E R26, desc[UR30][R10.64] &rd=0x0 &wr=0x5 ?trans1;
IADD.64 R8, R4, UR24 &req={1} ?WAIT3_END_GROUP;
LDG.E R33, desc[UR30][R2.64+0x24] &wr=0x5 ?trans1;
UMOV UR26, UR40 ?trans1;
UMOV UR27, UR41 ?trans2;
LDG.E R6, desc[UR30][R6.64] &wr=0x5 ?trans1;
IADD.64 R10, R4, UR26 &req={0} ?WAIT3_END_GROUP;
LDG.E R35, desc[UR30][R2.64+0x28] &wr=0x5 ?trans1;
UMOV UR28, UR38 ?trans1;
UMOV UR29, UR39 ?trans2;
LDG.E R8, desc[UR30][R8.64] &wr=0x5 ?trans1;
UMOV UR22, UR36 ?WAIT3_END_GROUP;
LDG.E R37, desc[UR30][R2.64+0x2c] &wr=0x5 ?trans1;
UMOV UR23, UR37 ?WAIT3_END_GROUP;
LDG.E R10, desc[UR30][R10.64] &wr=0x5 ?trans4;
LDG.E R7, desc[UR30][R2.64+0x30] &wr=0x5 ?trans4;
LDG.E R9, desc[UR30][R2.64+0x34] &wr=0x5 ?trans4;
LDG.E R11, desc[UR30][R2.64+0x38] &wr=0x5 ?trans1;
IMAD R32, R12, R13, R32 &req={2} ?trans1;
IADD.64 R12, R4, UR28 ?WAIT3_END_GROUP;
IMAD R32, R15, R14, R32 &req={3} ?trans1;
IADD.64 R14, R4.reuse, UR22 ?trans2;
UMOV UR22, UR9 ?trans1;
UMOV UR23, UR35 ?trans1;
LDG.E R12, desc[UR30][R12.64] &wr=0x2 ?trans1;
IADD.64 R4, R4, UR22 ?WAIT3_END_GROUP;
LDG.E R14, desc[UR30][R14.64] &wr=0x3 ?trans4;
LDG.E R4, desc[UR30][R4.64] &wr=0x3 ?trans4;
LDG.E R13, desc[UR30][R2.64+0x3c] &wr=0x3 ?trans1;
IMAD R16, R19, R16, R32 &req={4} ?WAIT4_END_GROUP;
IMAD R16, R18, R23, R16 ?WAIT4_END_GROUP;
IMAD R16, R20, R27, R16 ?WAIT4_END_GROUP;
IMAD R16, R21, R30, R16 ?WAIT4_END_GROUP;
IMAD R16, R22, R31, R16 ?WAIT4_END_GROUP;
IMAD R16, R24, R29, R16 &req={5} ?WAIT4_END_GROUP;
IMAD R16, R25, R28, R16 ?trans1;
IADD3 R17, PT, PT, R17, 0x10, RZ ?WAIT3_END_GROUP;
IMAD R16, R26, R33, R16 ?trans2;
ISETP.NE.AND P0, PT, R17, UR6, PT ?trans2;
IMAD R6, R6, R35, R16 ?WAIT4_END_GROUP;
IMAD R6, R8, R37, R6 ?WAIT4_END_GROUP;
IMAD R6, R10, R7, R6 ?WAIT4_END_GROUP;
IMAD R6, R12, R9, R6 &req={2} ?WAIT4_END_GROUP;
IMAD R6, R14, R11, R6 &req={3} ?WAIT4_END_GROUP;
IMAD R32, R4, R13, R6 ?trans1;
@P0 BRA 0x420 ?trans6;
@!P1 BRA 0x1190 ?trans5;
UISETP.GE.U32.AND UP0, UPT, UR34, 0x8, UPT ?trans1;
ULOP3.LUT UR7, UR8, 0x7, URZ, 0xc0, !UPT ?WAIT5_END_GROUP;
PLOP3.LUT P1, PT, PT, PT, UP0, 0x80, 0x8 ?trans1;
ISETP.NE.AND P0, PT, RZ, UR7, PT ?WAIT12_END_GROUP;
@!P1 BRA 0xe20 ?trans5;
LDCU.128 UR12, c[0x0][0x380] &wr=0x0 ?trans1;
MOV R3, UR6 ?trans1;
MOV R14, UR8 ?trans1;
HFMA2 R15, -RZ, RZ, 0, 0 ?trans1;
UIADD3 UR4, UPT, UPT, UR8, UR8, URZ ?trans2;
MOV R11, UR8 ?trans1;
IMAD R3, R3, UR8, R0 ?WAIT3_END_GROUP;
MOV R2, UR4 ?trans1;
MOV R13, UR4 ?trans1;
MOV.64 R8, UR12 &req={0} ?trans2;
UIMAD.WIDE.U32 UR4, UR6, 0x4, UR14 ?WAIT4_END_GROUP;
IMAD.WIDE R8, R3, 0x4, R8 ?trans1;
MOV R3, RZ ?trans1;
MOV.64 R4, UR4 ?WAIT3_END_GROUP;
LDG.E R23, desc[UR30][R8.64] &wr=0x2 ?trans1;
IADD.64 R2, R14, R2 ?trans2;
IMAD.WIDE.U32 R10, R11, 0x4, R8.reuse ?trans1;
LDG.E R22, desc[UR30][R4.64+0x8] &wr=0x3 ?trans1;
IADD.64 R20, R14, R2 ?trans2;
IMAD.WIDE.U32 R12, R13, 0x4, R8 ?trans1;
LEA R18, P1, R2, R8.reuse, 0x2 ?trans1;
LDG.E R16, desc[UR30][R10.64] &rd=0x0 &wr=0x4 ?trans1;
LEA R6, P2, R20, R8, 0x2 ?trans1;
IADD.64 R24, R14, R20 ?WAIT2_END_GROUP;
LDG.E R17, desc[UR30][R12.64] &rd=0x1 &wr=0x3 ?trans1;
LEA.HI.X R7, R20, R9.reuse, R21, 0x2, P2 ?trans2;
LEA.HI.X R19, R2, R9, R3, 0x2, P1 ?trans1;
LDG.E R20, desc[UR30][R4.64] &wr=0x2 ?trans1;
LEA R2, P1, R24, R8, 0x2 ?trans1;
IADD.64 R10, R14, R24 &req={0} ?trans2;
LDG.E R21, desc[UR30][R4.64+0x4] &wr=0x4 ?trans1;
LEA.HI.X R3, R24, R9, R25, 0x2, P1 ?trans2;
LEA R12, P1, R10, R8, 0x2 &req={1} ?trans1;
LDG.E R18, desc[UR30][R18.64] &wr=0x5 ?trans1;
IADD.64 R14, R14, R10 ?WAIT3_END_GROUP;
LDG.E R25, desc[UR30][R4.64+0xc] &wr=0x5 ?trans1;
LEA.HI.X R13, R10, R9, R11, 0x2, P1 ?WAIT3_END_GROUP;
LDG.E R7, desc[UR30][R6.64] &wr=0x5 ?trans1;
LEA R8, P1, R14, R8, 0x2 ?WAIT3_END_GROUP;
LDG.E R10, desc[UR30][R4.64+0x10] &wr=0x5 ?trans1;
LEA.HI.X R9, R14, R9, R15, 0x2, P1 ?WAIT3_END_GROUP;
LDG.E R2, desc[UR30][R2.64] &wr=0x5 ?trans4;
LDG.E R11, desc[UR30][R4.64+0x14] &wr=0x5 ?trans4;
LDG.E R13, desc[UR30][R12.64] &wr=0x5 ?trans4;
LDG.E R14, desc[UR30][R4.64+0x18] &wr=0x5 ?trans4;
LDG.E R15, desc[UR30][R4.64+0x1c] &wr=0x5 ?trans4;
LDG.E R9, desc[UR30][R8.64] &wr=0x5 ?trans1;
UIADD3 UR6, UPT, UPT, UR6, 0x8, URZ ?trans1;
IMAD R20, R23, R20, R32 &req={2} ?WAIT4_END_GROUP;
IMAD R16, R16, R21, R20 &req={4} ?WAIT4_END_GROUP;
IMAD R16, R17, R22, R16 &req={3} ?WAIT4_END_GROUP;
IMAD R16, R18, R25, R16 &req={5} ?WAIT4_END_GROUP;
IMAD R7, R7, R10, R16 ?WAIT4_END_GROUP;
IMAD R2, R2, R11, R7 ?WAIT4_END_GROUP;
IMAD R2, R13, R14, R2 ?WAIT4_END_GROUP;
IMAD R32, R9, R15, R2 ?WAIT7_END_GROUP;
@!P0 BRA 0x1190 ?trans5;
UISETP.GE.U32.AND UP0, UPT, UR7, 0x4, UPT ?trans1;
ULOP3.LUT UR9, UR8, 0x3, URZ, 0xc0, !UPT ?WAIT5_END_GROUP;
PLOP3.LUT P1, PT, PT, PT, UP0, 0x80, 0x8 ?trans1;
ISETP.NE.AND P0, PT, RZ, UR9, PT ?WAIT12_END_GROUP;
@!P1 BRA 0x1080 ?trans5;
LDCU.128 UR12, c[0x0][0x380] &wr=0x0 ?trans1;
MOV R5, UR6 ?trans1;
MOV R4, UR8 ?trans1;
MOV R7, RZ ?trans1;
UIADD3 UR7, UPT, UPT, UR8, UR8, URZ ?trans2;
MOV R15, UR8 ?trans1;
IMAD R5, R5, UR8, R0 ?WAIT3_END_GROUP;
MOV R6, UR7 ?trans1;
MOV R11, UR7 ?trans1;
MOV.64 R2, UR12 &req={0} ?trans2;
UIMAD.WIDE.U32 UR4, UR6, 0x4, UR14 ?WAIT4_END_GROUP;
IMAD.WIDE R2, R5, 0x4, R2 ?WAIT4_END_GROUP;
HFMA2 R5, -RZ, RZ, 0, 0 ?trans1;
MOV.64 R12, UR4 ?WAIT4_END_GROUP;
IADD.64 R8, R4, R6 ?trans2;
IMAD.WIDE.U32 R4, R15, 0x4, R2.reuse ?trans1;
LDG.E R14, desc[UR30][R12.64] &wr=0x2 ?trans2;
LEA R10, P1, R8.reuse, R2, 0x2 ?trans2;
LDG.E R15, desc[UR30][R2.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R6, R11, 0x4, R2 ?trans1;
LEA.HI.X R11, R8, R3, R9, 0x2, P1 ?trans2;
LDG.E R5, desc[UR30][R4.64] &wr=0x3 ?trans4;
LDG.E R16, desc[UR30][R12.64+0x4] &wr=0x3 ?trans4;
LDG.E R7, desc[UR30][R6.64] &wr=0x4 ?trans4;
LDG.E R8, desc[UR30][R12.64+0x8] &wr=0x4 ?trans4;
LDG.E R9, desc[UR30][R12.64+0xc] &wr=0x5 ?trans4;
LDG.E R11, desc[UR30][R10.64] &wr=0x5 ?trans1;
UIADD3 UR6, UPT, UPT, UR6, 0x4, URZ ?trans1;
IMAD R14, R15, R14, R32 &req={2} ?WAIT4_END_GROUP;
IMAD R14, R5, R16, R14 &req={3} ?WAIT4_END_GROUP;
IMAD R8, R7, R8, R14 &req={4} ?WAIT4_END_GROUP;
IMAD R32, R11, R9, R8 &req={5} ?WAIT7_END_GROUP;
@!P0 BRA 0x1190 ?trans5;
LDCU.64 UR4, c[0x0][0x388] &wr=0x0 ?trans1;
LDC.64 R6, c[0x0][0x380] &wr=0x1 ?trans1;
MOV R9, UR6 ?trans1;
IADD3 R8, PT, PT, RZ, -UR9, RZ ?WAIT4_END_GROUP;
IMAD R9, R9, UR8, R0 ?trans1;
UIMAD.WIDE.U32 UR6, UR6, 0x4, UR4 &req={0} ?WAIT6_END_GROUP;
MOV.64 R2, UR6 ?WAIT8_END_GROUP;
IMAD.WIDE R4, R9.reuse, 0x4, R6 &req={1} ?trans1;
LDG.E R10, desc[UR30][R2.64] &rd=0x0 &wr=0x2 ?trans5;
LDG.E R5, desc[UR30][R4.64] &wr=0x2 ?trans1;
IADD3 R8, PT, PT, R8, 0x1, RZ ?trans2;
IADD3 R9, PT, PT, R9, UR8, RZ ?trans1;
IADD.64 R2, R2, 0x4 &req={0} ?WAIT2_END_GROUP;
ISETP.NE.AND P0, PT, R8, RZ, PT ?trans1;
IMAD R32, R5, R10, R32 &req={2} ?WAIT12_END_GROUP;
@P0 BRA 0x1100 ?trans5;
LDC.64 R2, c[0x0][0x390] &wr=0x0 ?trans2;
IMAD.WIDE R2, R0, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR30][R2.64], R32 ?trans1;
EXIT ?trans5;
BRA 0x11d0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: matrixVectorMultiplication(int*, int*, int*, int)
_Z26matrixVectorMultiplicationPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_5
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v0, 0
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
v_mov_b32_e32 v2, v1
s_mov_b32 s3, s2
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
s_waitcnt lgkmcnt(0)
s_load_b32 s8, s[6:7], 0x0
s_add_i32 s3, s3, -1
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_add_nc_u32_e32 v2, s2, v2
s_cmp_eq_u32 s3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v5, v[3:4], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mad_u64_u32 v[3:4], null, s8, v5, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v0, v3
s_cbranch_scc0 .LBB0_3
.LBB0_4:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| matrixVectorMultiplication | 7,035 | 856 | stackv2-00000-of-00015 |
// Demangled: move(View)
Function : _Z4move4View
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x380] &wr=0x2 ?trans7;
LDC R0, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R0, R0, UR4, R3 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R8, c[0x0][0x3a0] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R2, c[0x0][0x3b8] &wr=0x2 ?trans8;
LDC.64 R4, c[0x0][0x388] &wr=0x3 ?trans1;
IMAD.WIDE R8, R0, 0x8, R8 &req={0} ?WAIT7_END_GROUP;
LDC.64 R10, c[0x0][0x3a8] &wr=0x0 ?trans1;
LDG.E.64 R8, desc[UR4][R8.64] &req={1} &wr=0x4 ?trans1;
IMAD.WIDE R2, R0, 0x8, R2 &req={2} ?WAIT6_END_GROUP;
LDC.64 R6, c[0x0][0x390] &wr=0x1 ?trans1;
LDG.E.64 R2, desc[UR4][R2.64] &wr=0x4 ?trans1;
IMAD.WIDE R4, R0, 0x8, R4 &req={3} ?WAIT5_END_GROUP;
LDG.E.64 R12, desc[UR4][R4.64] &wr=0x4 ?trans1;
IMAD.WIDE R10, R0, 0x8, R10 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE R6, R0.reuse, 0x8, R6 &req={1} ?trans1;
DFMA R14, R2, R8, R12 &req={4} &wr=0x0 ?trans2;
STG.E.64 desc[UR4][R4.64], R14 &req={0} ?trans1;
LDC.64 R12, c[0x0][0x3b0] &wr=0x0 ?trans3;
LDG.E.64 R10, desc[UR4][R10.64] &wr=0x2 ?trans4;
LDG.E.64 R16, desc[UR4][R6.64] &wr=0x2 ?trans1;
LDC.64 R8, c[0x0][0x398] &wr=0x1 ?trans1;
IMAD.WIDE R12, R0, 0x8, R12 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE R8, R0, 0x8, R8 &req={1} ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, R2, R10, R16 &req={2} &wr=0x0 ?trans2;
STG.E.64 desc[UR4][R6.64], R16 &req={0} ?trans4;
LDG.E.64 R12, desc[UR4][R12.64] &wr=0x2 ?trans4;
LDG.E.64 R18, desc[UR4][R8.64] &wr=0x2 ?WAIT15_END_GROUP;
NOP ?WAIT9_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R2, R12, R18 &req={2} &wr=0x0 ?trans2;
STG.E.64 desc[UR4][R8.64], R18 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x2b0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: move(View)
_Z4move4View:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x4c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x38
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s10, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v6, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v1, vcc_lo
global_load_b64 v[4:5], v[4:5], off
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[8:9], v[6:7], off
s_load_b128 s[0:3], s[0:1], 0x28
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[4:5], v[2:3], v[8:9]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v8, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v10, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v1, vcc_lo
global_store_b64 v[6:7], v[2:3], off
global_load_b64 v[2:3], v[8:9], off
global_load_b64 v[6:7], v[10:11], off
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[4:5], v[2:3], v[6:7]
v_add_co_u32 v6, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
global_store_b64 v[10:11], v[2:3], off
global_load_b64 v[2:3], v[6:7], off
global_load_b64 v[6:7], v[0:1], off
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[4:5], v[2:3], v[6:7]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| move | 1,154 | 1,036 | stackv2-00000-of-00015 |
// Demangled: add(int*, int*, int*)
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R9, SR_CTAID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R9.reuse, 0x4, R4 &req={2} ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans4;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R6, R9, 0x4, R6 &req={3} ?trans1;
IADD3 R9, PT, PT, R2, R5, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0xe0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: add(int*, int*, int*)
_Z3addPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_mov_b32 s3, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| add | 425 | 336 | stackv2-00000-of-00015 |
// Demangled: findMaxNaivelyKernel(int*)
Function : _Z20findMaxNaivelyKernelPi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
LDC R9, c[0x0][0x360] &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x370] &wr=0x1 ?trans1;
S2R R0, SR_TID.X &wr=0x2 ?trans1;
IMAD R8, R9, UR4, RZ &req={1} ?WAIT5_END_GROUP;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
ISETP.GE.U32.AND P0, PT, R8, 0x2, PT ?WAIT13_END_GROUP;
@!P0 EXIT &req={2,1,0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
IMAD R9, R9, UR4, R0 ?trans1;
LDCU.64 UR8, c[0x0][0x358] &wr=0x1 ?trans1;
UMOV UR4, 0x1 ?WAIT5_END_GROUP;
LDC.64 R6, c[0x0][0x380] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={1,0} ?WAIT7_END_GROUP;
UMOV UR5, UR4 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, UR4, URZ ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans3;
UIADD3 UR6, UPT, UPT, UR4, -0x1, URZ ?trans2;
ISETP.LE.U32.AND P0, PT, R8, UR4, PT ?trans1;
BSSY.RECONVERGENT B0, 0x1d0 ?trans3;
LOP3.LUT P1, RZ, R9, UR6, RZ, 0xc0, !PT ?WAIT13_END_GROUP;
@P1 BRA 0x1c0 &req={0} ?trans5;
IADD3 R5, PT, PT, R9, UR5, RZ ?trans1;
LDG.E R0, desc[UR8][R2.64] &wr=0x3 ?trans4;
IMAD.WIDE.U32 R4, R5, 0x4, R6 &req={2} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR8][R4.64] &wr=0x3 ?trans2;
ISETP.GE.AND P1, PT, R0, R5, PT &req={3} ?WAIT13_END_GROUP;
@!P1 STG.E desc[UR8][R2.64], R5 &rd=0x0 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
@!P0 BRA 0xe0 ?trans5;
EXIT ?trans5;
BRA 0x1f0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: findMaxNaivelyKernel(int*)
_Z20findMaxNaivelyKernelPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b32 s4, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s2, s4, s3
s_cmp_lt_u32 s2, 2
s_cbranch_scc1 .LBB0_6
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s3, v[0:1]
v_mov_b32_e32 v3, v1
s_mov_b32 s3, 1
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
.LBB0_2:
s_mov_b32 s5, s3
s_lshl_b32 s3, s3, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s4, s3, -1
s_waitcnt_vscnt null, 0x0
s_barrier
v_and_b32_e32 v0, s4, v2
s_mov_b32 s4, exec_lo
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_5
v_add_nc_u32_e32 v0, s5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[0:1]
v_add_co_u32 v5, vcc_lo, s0, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_clause 0x1
global_load_b32 v0, v[5:6], off
global_load_b32 v5, v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v5, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
global_store_b32 v[3:4], v0, off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s4
s_cmp_ge_u32 s3, s2
s_cbranch_scc0 .LBB0_2
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| findMaxNaivelyKernel | 784 | 849 | stackv2-00000-of-00015 |
// Demangled: findMaxWithSharedMemoryKernel(int*)
Function : _Z29findMaxWithSharedMemoryKernelPi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R7, SR_TID.X &wr=0x1 ?trans1;
LDCU UR8, c[0x0][0x360] &wr=0x2 ?trans6;
LDC.64 R2, c[0x0][0x380] &wr=0x3 ?trans1;
HFMA2 R4, -RZ, RZ, 0, 0 ?trans1;
S2R R10, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR9, c[0x0][0x370] &wr=0x2 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x4 ?trans1;
UIMAD UR4, UR8, UR9, URZ &req={2} ?WAIT2_END_GROUP;
IMAD R9, R10, UR8, R7 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R2, R9.reuse, 0x4, R2 &req={3} ?trans1;
ISETP.GE.U32.AND P0, PT, R9, UR4, PT ?WAIT13_END_GROUP;
@!P0 LDG.E R4, desc[UR6][R2.64] &req={4} &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
MOV R0, UR8 ?trans1;
MOV R8, UR9 ?WAIT4_END_GROUP;
ISETP.GE.U32.AND P0, PT, R0, 0x2, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R5, R7, UR4, 0x2 ?WAIT5_END_GROUP;
STS [R5], R4 &req={2} &rd=0x1 ?trans1;
@!P0 BRA 0x240 &req={0} ?trans5;
MOV R4, R0 &req={1,0} ?trans1;
SHF.R.U32.HI R0, RZ, 0x1, R0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans3;
ISETP.GT.U32.AND P0, PT, R4, 0x3, PT ?trans1;
ISETP.GE.U32.AND P1, PT, R7, R0, PT ?trans2;
BSSY.RECONVERGENT B0, 0x230 ?trans11;
@P1 BRA 0x220 ?trans5;
IMAD R4, R0, 0x4, R5 ?trans1;
LDS R6, [R5] ?trans5;
LDS R4, [R4] &wr=0x0 ?trans2;
ISETP.GE.AND P1, PT, R6, R4, PT &req={0} ?WAIT13_END_GROUP;
@!P1 STS [R5], R4 &rd=0x0 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
@P0 BRA 0x160 ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.NE.AND P1, PT, R7, RZ, PT ?trans1;
ISETP.GE.U32.AND P0, PT, R8, 0x2, PT ?WAIT5_END_GROUP;
ISETP.GE.U32.OR P0, PT, R9, R8, !P0 ?WAIT7_END_GROUP;
@!P1 S2R R5, SR_CgaCtaId &req={1,0} &wr=0x0 ?trans1;
@!P1 MOV R0, 0x400 ?WAIT5_END_GROUP;
@!P1 LEA R0, R5, R0, 0x18 &req={0} ?trans2;
@!P1 LDC.64 R4, c[0x0][0x380] &wr=0x0 ?trans3;
@!P1 LDS R7, [R0] &wr=0x1 ?trans1;
@!P1 IMAD.WIDE.U32 R4, R10, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
@!P1 STG.E desc[UR6][R4.64], R7 &req={1} &rd=0x0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT ?trans5;
LDG.E R0, desc[UR6][R2.64] &rd=0x1 &wr=0x5 ?trans1;
LDC.64 R6, c[0x0][0x380] &req={0} &wr=0x0 ?trans2;
SHF.R.U32.HI R10, RZ, 0x1, R8 ?WAIT4_END_GROUP;
IADD3 R5, PT, PT, R9, R10, RZ &req={2} ?WAIT5_END_GROUP;
IMAD.WIDE.U32 R4, R5, 0x4, R6 &req={0} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR6][R4.64] &wr=0x2 ?trans1;
ISETP.GT.U32.AND P1, PT, R8, 0x3, PT ?trans1;
MOV R8, R10 ?trans1;
ISETP.GE.AND P0, PT, R0, R5, PT &req={5,2} ?WAIT13_END_GROUP;
@!P0 STG.E desc[UR6][R2.64], R5 &rd=0x2 ?trans1;
@!P0 MOV R0, R5 ?trans1;
@P1 BRA 0x330 ?trans6;
EXIT ?trans5;
BRA 0x3e0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: findMaxWithSharedMemoryKernel(int*)
_Z29findMaxWithSharedMemoryKernelPi:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x14
s_load_b32 s4, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b32 s2, s15
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mul_i32 s5, s4, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s5, v1
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB2_2
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v3, v[2:3], off
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s5
v_lshlrev_b32_e32 v2, 2, v0
s_cmp_lt_u32 s3, 2
s_waitcnt vmcnt(0)
ds_store_b32 v2, v3
s_cbranch_scc1 .LBB2_7
.LBB2_3:
s_mov_b32 s5, s3
s_lshr_b32 s3, s3, 1
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB2_6
v_lshl_add_u32 v3, s3, 2, v2
ds_load_b32 v3, v3
ds_load_b32 v4, v2
s_waitcnt lgkmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v4, v3
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_6
ds_store_b32 v2, v3
.LBB2_6:
s_or_b32 exec_lo, exec_lo, s6
s_cmp_lt_u32 s5, 4
s_cbranch_scc0 .LBB2_3
.LBB2_7:
s_mov_b32 s3, 0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB2_9
v_mov_b32_e32 v0, 0
s_lshl_b64 s[2:3], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s2, s0, s2
s_addc_u32 s3, s1, s3
ds_load_b32 v2, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v2, s[2:3]
.LBB2_9:
s_or_b32 exec_lo, exec_lo, s5
v_max_u32_e32 v0, 1, v1
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB2_14
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v2, v3
v_lshlrev_b64 v[4:5], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_load_b32 v0, v[4:5], off
.LBB2_11:
s_lshr_b32 s2, s4, 1
s_mov_b32 s3, exec_lo
v_add_nc_u32_e32 v2, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_add_co_u32 v6, vcc_lo, s0, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
global_load_b32 v2, v[6:7], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v0, v2
s_cbranch_execz .LBB2_13
v_mov_b32_e32 v0, v2
global_store_b32 v[4:5], v2, off
.LBB2_13:
s_or_b32 exec_lo, exec_lo, s3
s_cmp_gt_u32 s4, 3
s_mov_b32 s4, s2
s_cbranch_scc1 .LBB2_11
.LBB2_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| findMaxWithSharedMemoryKernel | 1,511 | 1,546 | stackv2-00000-of-00015 |
// Demangled: findMaxWithoutDivergenceKernel(int*)
Function : _Z30findMaxWithoutDivergenceKernelPi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
LDC R9, c[0x0][0x360] &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x370] &wr=0x1 ?trans1;
S2R R4, SR_TID.X &wr=0x2 ?trans1;
IMAD R0, R9, UR4, RZ &req={1} ?WAIT5_END_GROUP;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
ISETP.GE.U32.AND P0, PT, R0, 0x2, PT ?WAIT13_END_GROUP;
@!P0 EXIT &req={2,1,0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
IMAD R9, R9, UR4, R4 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x1 ?trans6;
LDC.64 R6, c[0x0][0x380] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={1,0} ?WAIT7_END_GROUP;
MOV R4, R0 ?trans1;
SHF.R.U32.HI R0, RZ, 0x1, R0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans3;
ISETP.GT.U32.AND P0, PT, R4, 0x3, PT ?trans1;
ISETP.GE.U32.AND P1, PT, R9, R0, PT ?trans2;
BSSY.RECONVERGENT B0, 0x1b0 ?trans11;
@P1 BRA 0x1a0 &req={0} ?trans5;
IADD3 R5, PT, PT, R9, R0, RZ ?trans1;
LDG.E R8, desc[UR6][R2.64] &wr=0x3 ?trans4;
IMAD.WIDE.U32 R4, R5, 0x4, R6 &req={2} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR6][R4.64] &wr=0x3 ?trans2;
ISETP.GE.AND P1, PT, R8, R5, PT &req={3} ?WAIT13_END_GROUP;
@!P1 STG.E desc[UR6][R2.64], R5 &rd=0x0 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
@P0 BRA 0xd0 ?trans5;
EXIT ?trans5;
BRA 0x1d0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: findMaxWithoutDivergenceKernel(int*)
_Z30findMaxWithoutDivergenceKernelPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b32 s4, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s2, s4, s3
s_cmp_lt_u32 s2, 2
s_cbranch_scc1 .LBB1_6
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s3, v[0:1]
v_mov_b32_e32 v3, v1
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
.LBB1_2:
s_mov_b32 s3, s2
s_lshr_b32 s2, s2, 1
s_mov_b32 s4, exec_lo
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s2, v2
s_cbranch_execz .LBB1_5
v_add_nc_u32_e32 v0, s2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[0:1]
v_add_co_u32 v5, vcc_lo, s0, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_clause 0x1
global_load_b32 v0, v[5:6], off
global_load_b32 v5, v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v5, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_5
global_store_b32 v[3:4], v0, off
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s4
s_cmp_lt_u32 s3, 4
s_cbranch_scc0 .LBB1_2
.LBB1_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| findMaxWithoutDivergenceKernel | 743 | 794 | stackv2-00000-of-00015 |
// Demangled: bins_to_inclusive(int*, int)
Function : _Z17bins_to_inclusivePii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x2 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x2 ?trans7;
LDC R4, c[0x0][0x388] &wr=0x3 ?trans1;
UIMAD UR4, UR4, UR5, URZ &req={2} ?trans1;
IADD3 R0, PT, PT, -R0, RZ, RZ &req={1} ?trans1;
ISETP.GE.AND P0, PT, R4, 0x1, PT &req={3} ?WAIT5_END_GROUP;
ISETP.NE.OR P0, PT, R0, UR4, !P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
ISETP.GE.U32.AND P1, PT, R4.reuse, 0x10, PT ?trans1;
LOP3.LUT R35, R4, 0xf, RZ, 0xc0, !PT ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x0 ?trans1;
HFMA2 R0, -RZ, RZ, 0, 0 ?WAIT3_END_GROUP;
ISETP.NE.AND P0, PT, R35, RZ, PT ?WAIT7_END_GROUP;
@!P1 BRA 0x4c0 ?trans6;
LDCU.64 UR4, c[0x0][0x380] &wr=0x1 ?trans1;
LOP3.LUT R5, R4, 0x7ffffff0, RZ, 0xc0, !PT ?trans1;
MOV R0, RZ ?WAIT3_END_GROUP;
IADD3 R5, PT, PT, -R5, RZ, RZ ?trans1;
UIADD3.64 UR4, UPT, UPT, UR4, 0x1c, URZ &req={1} ?WAIT6_END_GROUP;
MOV.64 R2, UR4 ?WAIT8_END_GROUP;
LDG.E R7, desc[UR6][R2.64+-0x20] &req={0} &wr=0x2 ?trans4;
LDG.E R8, desc[UR6][R2.64+-0x1c] &wr=0x2 ?trans4;
LDG.E R10, desc[UR6][R2.64+-0x18] &wr=0x3 ?trans4;
LDG.E R12, desc[UR6][R2.64+-0x14] &wr=0x4 ?trans4;
LDG.E R14, desc[UR6][R2.64+-0x10] &wr=0x5 ?trans4;
LDG.E R16, desc[UR6][R2.64+-0xc] &wr=0x5 ?trans4;
LDG.E R18, desc[UR6][R2.64+-0x8] &wr=0x5 ?trans4;
LDG.E R20, desc[UR6][R2.64+-0x4] &wr=0x5 ?trans4;
LDG.E R22, desc[UR6][R2.64] &wr=0x5 ?trans4;
LDG.E R24, desc[UR6][R2.64+0x4] &wr=0x5 ?trans4;
LDG.E R26, desc[UR6][R2.64+0x8] &wr=0x5 ?trans4;
LDG.E R28, desc[UR6][R2.64+0xc] &wr=0x5 ?trans4;
LDG.E R30, desc[UR6][R2.64+0x10] &wr=0x5 ?trans4;
LDG.E R32, desc[UR6][R2.64+0x14] &wr=0x5 ?trans4;
LDG.E R34, desc[UR6][R2.64+0x18] &wr=0x5 ?trans4;
LDG.E R36, desc[UR6][R2.64+0x1c] &wr=0x5 ?trans4;
LDG.E R6, desc[UR6][R2.64+0x20] &wr=0x5 ?trans1;
IADD3 R5, PT, PT, R5, 0x10, RZ ?WAIT2_END_GROUP;
IADD3 R0, PT, PT, R0, 0x10, RZ ?WAIT3_END_GROUP;
ISETP.NE.AND P1, PT, R5, RZ, PT ?trans1;
IADD3 R7, PT, PT, R7, R8, RZ &req={2} ?WAIT4_END_GROUP;
IADD3 R9, PT, PT, R7, R10, RZ &req={3} ?trans1;
STG.E desc[UR6][R2.64+-0x1c], R7 &rd=0x0 ?trans3;
IADD3 R11, PT, PT, R9, R12, RZ &req={4} ?trans1;
STG.E desc[UR6][R2.64+-0x18], R9 ?trans3;
IADD3 R13, PT, PT, R11, R14, RZ &req={5} ?trans1;
STG.E desc[UR6][R2.64+-0x14], R11 ?trans3;
IADD3 R15, PT, PT, R13, R16, RZ ?trans1;
STG.E desc[UR6][R2.64+-0x10], R13 ?trans3;
IADD3 R17, PT, PT, R15, R18, RZ ?trans1;
STG.E desc[UR6][R2.64+-0xc], R15 ?trans3;
IADD3 R19, PT, PT, R17, R20, RZ ?trans1;
STG.E desc[UR6][R2.64+-0x8], R17 ?trans3;
IADD3 R21, PT, PT, R19, R22, RZ ?trans1;
STG.E desc[UR6][R2.64+-0x4], R19 ?trans3;
IADD3 R23, PT, PT, R21, R24, RZ ?trans1;
STG.E desc[UR6][R2.64], R21 ?trans3;
IADD3 R25, PT, PT, R23, R26, RZ ?trans1;
STG.E desc[UR6][R2.64+0x4], R23 ?trans3;
IADD3 R27, PT, PT, R25, R28, RZ ?trans1;
STG.E desc[UR6][R2.64+0x8], R25 ?trans3;
IADD3 R29, PT, PT, R27, R30, RZ ?trans1;
STG.E desc[UR6][R2.64+0xc], R27 ?trans3;
IADD3 R31, PT, PT, R29, R32, RZ ?trans1;
STG.E desc[UR6][R2.64+0x10], R29 ?trans3;
IADD3 R33, PT, PT, R31, R34, RZ ?trans1;
STG.E desc[UR6][R2.64+0x14], R31 ?trans3;
IADD3 R37, PT, PT, R33, R36, RZ ?trans1;
STG.E desc[UR6][R2.64+0x18], R33 ?trans3;
IADD3 R7, PT, PT, R37, R6, RZ &req={0} ?trans1;
STG.E desc[UR6][R2.64+0x1c], R37 ?trans4;
STG.E desc[UR6][R2.64+0x20], R7 &rd=0x0 ?trans2;
IADD.64 R2, R2, 0x40 &req={0} ?WAIT2_END_GROUP;
@P1 BRA 0x160 ?trans6;
@!P0 EXIT &req={0} ?trans5;
ISETP.GE.U32.AND P0, PT, R35, 0x8, PT ?trans1;
LOP3.LUT R21, R4, 0x7, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R21, RZ, PT ?WAIT7_END_GROUP;
@!P0 BRA 0x6d0 ?trans6;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans2;
IMAD.WIDE R2, R0, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E R5, desc[UR6][R2.64+-0x4] &wr=0x2 ?trans4;
LDG.E R6, desc[UR6][R2.64] &wr=0x2 ?trans4;
LDG.E R8, desc[UR6][R2.64+0x4] &wr=0x3 ?trans4;
LDG.E R10, desc[UR6][R2.64+0x8] &wr=0x4 ?trans4;
LDG.E R12, desc[UR6][R2.64+0xc] &wr=0x5 ?trans4;
LDG.E R14, desc[UR6][R2.64+0x10] &wr=0x5 ?trans4;
LDG.E R16, desc[UR6][R2.64+0x14] &wr=0x5 ?trans4;
LDG.E R18, desc[UR6][R2.64+0x18] &wr=0x5 ?trans4;
LDG.E R20, desc[UR6][R2.64+0x1c] &wr=0x5 ?trans1;
IADD3 R0, PT, PT, R0, 0x8, RZ ?WAIT2_END_GROUP;
IADD3 R5, PT, PT, R5, R6, RZ &req={2} ?WAIT4_END_GROUP;
IADD3 R7, PT, PT, R5, R8, RZ &req={3} ?trans1;
STG.E desc[UR6][R2.64], R5 &rd=0x0 ?trans3;
IADD3 R9, PT, PT, R7, R10, RZ &req={4} ?trans1;
STG.E desc[UR6][R2.64+0x4], R7 &rd=0x0 ?trans3;
IADD3 R11, PT, PT, R9, R12, RZ &req={5} ?trans1;
STG.E desc[UR6][R2.64+0x8], R9 &rd=0x0 ?trans3;
IADD3 R13, PT, PT, R11, R14, RZ ?trans1;
STG.E desc[UR6][R2.64+0xc], R11 &rd=0x0 ?trans3;
IADD3 R15, PT, PT, R13, R16, RZ ?trans1;
STG.E desc[UR6][R2.64+0x10], R13 &rd=0x0 ?trans3;
IADD3 R17, PT, PT, R15, R18, RZ ?trans1;
STG.E desc[UR6][R2.64+0x14], R15 &rd=0x0 ?trans3;
IADD3 R19, PT, PT, R17, R20, RZ ?trans1;
STG.E desc[UR6][R2.64+0x18], R17 &rd=0x0 ?trans4;
STG.E desc[UR6][R2.64+0x1c], R19 &rd=0x0 ?trans2;
@!P1 EXIT ?trans5;
ISETP.GE.U32.AND P0, PT, R21, 0x4, PT ?trans1;
LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R4, RZ, PT ?WAIT7_END_GROUP;
@!P0 BRA 0x820 ?trans6;
LDC.64 R2, c[0x0][0x380] &req={0} &wr=0x0 ?trans2;
IMAD.WIDE R2, R0, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E R5, desc[UR6][R2.64+-0x4] &wr=0x2 ?trans4;
LDG.E R6, desc[UR6][R2.64] &wr=0x2 ?trans4;
LDG.E R8, desc[UR6][R2.64+0x4] &wr=0x3 ?trans4;
LDG.E R10, desc[UR6][R2.64+0x8] &wr=0x4 ?trans4;
LDG.E R12, desc[UR6][R2.64+0xc] &wr=0x5 ?trans1;
IADD3 R0, PT, PT, R0, 0x4, RZ ?WAIT2_END_GROUP;
IADD3 R5, PT, PT, R5, R6, RZ &req={2} ?WAIT4_END_GROUP;
IADD3 R7, PT, PT, R5, R8, RZ &req={3} ?trans1;
STG.E desc[UR6][R2.64], R5 &rd=0x1 ?trans3;
IADD3 R9, PT, PT, R7, R10, RZ &req={4} ?trans1;
STG.E desc[UR6][R2.64+0x4], R7 &rd=0x1 ?trans3;
IADD3 R11, PT, PT, R9, R12, RZ &req={5} ?trans1;
STG.E desc[UR6][R2.64+0x8], R9 &rd=0x1 ?trans4;
STG.E desc[UR6][R2.64+0xc], R11 &rd=0x1 ?trans2;
@!P1 EXIT ?trans5;
LDC.64 R2, c[0x0][0x380] &req={1,0} &wr=0x0 ?trans1;
IADD3 R4, PT, PT, -R4, RZ, RZ ?trans1;
IMAD.WIDE.U32 R2, R0, 0x4, R2 &req={0} ?WAIT7_END_GROUP;
LDG.E R0, desc[UR6][R2.64+-0x4] &wr=0x2 ?trans4;
LDG.E R5, desc[UR6][R2.64] &wr=0x2 ?trans1;
IADD3 R4, PT, PT, R4, 0x1, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R4, RZ, PT ?trans1;
IADD3 R5, PT, PT, R0, R5, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R5 &rd=0x0 ?trans2;
IADD.64 R2, R2, 0x4 &req={0} ?WAIT5_END_GROUP;
@P0 BRA 0x860 ?trans5;
EXIT ?trans5;
BRA 0x8f0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: bins_to_inclusive(int*, int)
_Z17bins_to_inclusivePii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x8
v_sub_nc_u32_e32 v0, 0, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_cmp_gt_i32 s2, 0
s_mul_i32 s15, s15, s3
s_cselect_b32 s3, -1, 0
v_cmp_eq_u32_e32 vcc_lo, s15, v0
s_and_b32 s3, vcc_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB1_3
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s0, -4
s_addc_u32 s5, s1, -1
s_load_b32 s3, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v0, s3
.LBB1_2:
global_load_b32 v2, v1, s[0:1]
s_add_i32 s2, s2, -1
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v2, v0
global_store_b32 v1, v0, s[0:1]
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s2, 0
s_cbranch_scc1 .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| bins_to_inclusive | 3,932 | 501 | stackv2-00000-of-00015 |
// Demangled: counting_sort_kernel(int*, int*, int)
Function : _Z20counting_sort_kernelPiS_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x390] &wr=0x2 ?trans7;
LDC R5, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R5, R5, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R5, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x388] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD.WIDE R2, R5, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
LDC.64 R4, c[0x0][0x380] &wr=0x0 ?trans1;
LDG.E R3, desc[UR4][R2.64] &req={1} &wr=0x0 ?trans1;
HFMA2 R7, -RZ, RZ, 0, 5.9604644775390625e-08 ?trans2;
IMAD.WIDE R4, R3, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
REDG.E.ADD.STRONG.GPU desc[UR4][R4.64], R7 ?trans1;
EXIT ?trans5;
BRA 0x110;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: counting_sort_kernel(int*, int*, int)
_Z20counting_sort_kernelPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_atomic_add_u32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| counting_sort_kernel | 517 | 587 | stackv2-00000-of-00015 |
// Demangled: inclusive_to_sorted(int*, int*)
Function : _Z19inclusive_to_sortedPiS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR6, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans1;
HFMA2 R11, -RZ, RZ, 0, 0 ?WAIT6_END_GROUP;
LDC R9, c[0x0][0x360] &wr=0x1 ?trans8;
LDC.64 R2, c[0x0][0x380] &wr=0x3 ?trans8;
LDC.64 R6, c[0x0][0x388] &wr=0x4 ?trans1;
IMAD R9, R9, UR6, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R9.reuse, RZ, PT ?trans1;
IMAD.WIDE R2, R9, 0x4, R2 &req={3} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR4][R2.64] &req={2} &wr=0x2 ?trans7;
@P0 LDG.E R11, desc[UR4][R2.64+-0x4] &wr=0x2 ?trans2;
ISETP.GE.AND P0, PT, R11, R0, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={4,0} ?trans5;
IMAD.WIDE R4, R11, 0x4, R6 ?WAIT5_END_GROUP;
REDG.E.ADD.STRONG.GPU desc[UR4][R4.64], R9 &rd=0x0 ?trans4;
LDG.E R0, desc[UR4][R2.64] &wr=0x2 ?trans1;
IADD3 R11, PT, PT, R11, 0x1, RZ ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R11, R0, PT &req={2} ?WAIT13_END_GROUP;
@!P0 BRA 0xf0 &req={0} ?trans5;
EXIT ?trans5;
BRA 0x160;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: inclusive_to_sorted(int*, int*)
_Z19inclusive_to_sortedPiS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v3, 0
v_mov_b32_e32 v5, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_mov_b32 s4, exec_lo
v_cmpx_ne_u32_e32 0, v1
s_cbranch_execz .LBB2_2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_load_b32 v3, v[3:4], off offset:-4
v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v4, v1
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[4:5]
v_add_co_u32 v5, vcc_lo, s0, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_mov_b32 s0, exec_lo
global_load_b32 v0, v[5:6], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v3, v0
s_cbranch_execz .LBB2_5
v_ashrrev_i32_e32 v4, 31, v3
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[3:4]
v_add_co_u32 v7, vcc_lo, s2, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
.LBB2_4:
global_atomic_add_u32 v[7:8], v1, off
global_load_b32 v0, v[5:6], off
v_add_nc_u32_e32 v3, 1, v3
v_add_co_u32 v7, s0, v7, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v8, s0, 0, v8, s0
s_waitcnt vmcnt(0)
v_cmp_ge_i32_e32 vcc_lo, v3, v0
s_or_b32 s1, vcc_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB2_4
.LBB2_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| inclusive_to_sorted | 627 | 1,007 | stackv2-00000-of-00015 |
// Demangled: markFilterEdges_gpu(int*, int*, int*, int*, int)
Function : _Z19markFilterEdges_gpuPiS_S_S_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x3a0] &wr=0x2 ?trans1;
IMAD R0, R0, UR4, R3 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R8, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU UR5, c[0x0][0x370] &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x2 ?trans6;
LDC.64 R10, c[0x0][0x390] &wr=0x3 ?trans1;
LDCU UR14, c[0x0][0x3a0] &wr=0x4 ?trans1;
LDCU.64 UR8, c[0x0][0x388] &wr=0x0 ?trans1;
LDCU.64 UR10, c[0x0][0x398] &wr=0x0 ?trans1;
LDCU.64 UR12, c[0x0][0x398] &wr=0x0 ?trans1;
UIMAD UR4, UR4, UR5, URZ &req={1} ?WAIT12_END_GROUP;
IMAD.WIDE R2, R0, 0x4, R8 &req={1,0} ?WAIT6_END_GROUP;
LDG.E R3, desc[UR6][R2.64] &req={2} &wr=0x2 ?trans2;
IMAD.WIDE R4, R3, 0x4, R10 &req={3,2} ?WAIT6_END_GROUP;
LDG.E R4, desc[UR6][R4.64] &wr=0x2 ?trans1;
BSSY.RECONVERGENT B0, 0x290 ?trans1;
SHF.R.S32.HI R7, RZ, 0x1f, R0 ?trans1;
ISETP.NE.AND P0, PT, R4, -0x1, PT &req={2} ?WAIT13_END_GROUP;
@P0 BRA 0x250 ?trans5;
SHF.L.U64.HI R7, R0.reuse, 0x2, R7 ?trans1;
IMAD.SHL.U32 R6, R0, 0x4, RZ ?WAIT5_END_GROUP;
IADD.64 R2, R6, UR8 ?WAIT7_END_GROUP;
LDG.E R3, desc[UR6][R2.64] &wr=0x2 ?trans2;
IMAD.WIDE R4, R3, 0x4, R10 &req={2} ?WAIT6_END_GROUP;
LDG.E R4, desc[UR6][R4.64] &wr=0x2 ?trans1;
IADD.64 R6, R6, UR10 ?trans2;
ISETP.NE.AND P0, PT, R4, -0x1, PT &req={2} ?WAIT13_END_GROUP;
@!P0 MOV R13, 0x1 ?WAIT5_END_GROUP;
@!P0 STG.E desc[UR6][R6.64], R13 &rd=0x0 ?trans4;
@P0 STG.E desc[UR6][R6.64], RZ &rd=0x0 ?trans1;
BRA 0x280 ?trans5;
LEA R2, P0, R0, UR12, 0x2 ?WAIT4_END_GROUP;
LEA.HI.X R3, R0, UR13, R7, 0x2, P0 ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], RZ &rd=0x1 ?trans4;
BSYNC.RECONVERGENT B0 &req={4} ?trans5;
IADD3 R0, PT, PT, R0, UR4, RZ ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, UR14, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x110 ?trans5;
EXIT ?trans5;
BRA 0x2d0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: markFilterEdges_gpu(int*, int*, int*, int*, int)
_Z19markFilterEdges_gpuPiS_S_S_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s14, s[0:1], 0x20
s_add_u32 s2, s0, 40
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s12, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s14, v1
s_cbranch_execz .LBB0_11
s_load_b32 s2, s[2:3], 0x0
s_load_b256 s[4:11], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v6, 1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s12
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[12:13], s[2:3], 2
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
s_mov_b32 s0, exec_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v4, vcc_lo, s8, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_cmpx_ne_u32_e32 -1, v4
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_4
v_add_co_u32 v4, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v3, vcc_lo
global_store_b32 v[4:5], v0, off
.LBB0_4:
s_and_not1_saveexec_b32 s3, s0
s_cbranch_execz .LBB0_10
v_add_co_u32 v4, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v4, vcc_lo, s8, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, -1, v4
v_add_co_u32 v4, s0, s10, v2
v_add_co_ci_u32_e64 v5, s0, s11, v3, s0
s_and_saveexec_b32 s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_7
global_store_b32 v[4:5], v0, off
.LBB0_7:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_9
global_store_b32 v[4:5], v6, off
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_10:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s3
v_add_nc_u32_e32 v1, s2, v1
v_add_co_u32 v2, s0, v2, s12
v_add_co_ci_u32_e64 v3, s0, s13, v3, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s14, v1
s_or_b32 s1, vcc_lo, s1
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| markFilterEdges_gpu | 1,208 | 1,555 | stackv2-00000-of-00015 |
// Demangled: isingAnnealingStep(int*, int*, int*, int*, int, int)
Function : _Z18isingAnnealingStepPiS_S_S_ii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R9, SR_CTAID.X &wr=0x1 ?trans7;
LDC.64 R2, c[0x0][0x3a0] &wr=0x2 ?trans1;
LDCU UR6, c[0x0][0x360] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x398] &wr=0x2 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans2;
STG.E desc[UR4][R4.64], R3 &req={2} &rd=0x2 ?trans1;
IMAD R9, R9, UR6, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R9, R2, PT ?WAIT13_END_GROUP;
@P0 EXIT &req={2,0} ?trans5;
LDC.64 R10, c[0x0][0x388] &wr=0x0 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x1 ?trans1;
IMAD.WIDE R10, R9, 0x4, R10 &req={0} ?WAIT5_END_GROUP;
LDG.E R27, desc[UR4][R10.64] &wr=0x2 ?trans4;
LDG.E R12, desc[UR4][R10.64+0x4] &wr=0x2 ?trans1;
IMAD.WIDE R8, R9, 0x4, R6 &req={1} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR4][R8.64] &rd=0x0 &wr=0x5 ?trans1;
BSSY.RECONVERGENT B0, 0x9c0 ?trans1;
HFMA2 R3, -RZ, RZ, 0, 0 ?trans1;
ISETP.GE.AND P0, PT, R27, R12, PT &req={2} ?WAIT13_END_GROUP;
@P0 BRA 0x9b0 &req={0} ?trans5;
IADD3 R3, PT, PT, R27, 0x2, RZ ?trans2;
LOP3.LUT R24, RZ, R27, RZ, 0x33, !PT ?trans1;
BSSY.RECONVERGENT B1, 0x5d0 ?trans2;
VIMNMX.S32 R3, R12, R3, !PT ?WAIT5_END_GROUP;
IADD3 R24, PT, PT, R3, R24, RZ ?trans1;
MOV R3, RZ ?WAIT4_END_GROUP;
ISETP.GE.U32.AND P1, PT, R24.reuse, 0xe, PT ?trans1;
LEA.HI R25, R24, 0x1, RZ, 0x1f ?WAIT4_END_GROUP;
LOP3.LUT R32, R25, 0x7, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R32, RZ, PT ?WAIT3_END_GROUP;
@!P1 BRA 0x5c0 ?trans10;
LDC.64 R10, c[0x0][0x380] &wr=0x0 ?trans1;
LOP3.LUT R26, R25, 0xfffffff8, RZ, 0xc0, !PT ?trans1;
MOV R3, RZ ?WAIT3_END_GROUP;
IADD3 R26, PT, PT, -R26, RZ, RZ ?trans1;
IADD.64 R10, R10, 0x20 &req={0} ?WAIT8_END_GROUP;
IMAD.WIDE R12, R27, 0x4, R10 ?WAIT5_END_GROUP;
LDG.E R17, desc[UR4][R12.64+-0x18] &wr=0x2 ?trans4;
LDG.E R37, desc[UR4][R12.64+-0x20] &wr=0x3 ?trans4;
LDG.E R19, desc[UR4][R12.64+-0x10] &wr=0x4 ?trans4;
LDG.E R35, desc[UR4][R12.64+-0x8] &wr=0x4 ?trans4;
LDG.E R21, desc[UR4][R12.64] &wr=0x4 ?trans4;
LDG.E R15, desc[UR4][R12.64+0x8] &wr=0x4 ?trans4;
LDG.E R23, desc[UR4][R12.64+0x10] &wr=0x4 ?trans4;
LDG.E R33, desc[UR4][R12.64+0x18] &wr=0x4 ?trans4;
LDG.E R28, desc[UR4][R12.64+-0x14] &wr=0x4 ?trans4;
LDG.E R30, desc[UR4][R12.64+-0x1c] &wr=0x4 ?trans4;
LDG.E R34, desc[UR4][R12.64+-0xc] &wr=0x4 ?trans1;
IMAD.WIDE R16, R17, 0x4, R6 &req={2} ?WAIT4_END_GROUP;
IMAD.WIDE R36, R37, 0x4, R6.reuse &req={3} ?trans1;
LDG.E R29, desc[UR4][R16.64] &rd=0x4 &wr=0x2 ?trans4;
LDG.E R31, desc[UR4][R36.64] &wr=0x3 ?trans1;
IMAD.WIDE R16, R19, 0x4, R6 &req={4} ?WAIT4_END_GROUP;
IMAD.WIDE R18, R35, 0x4, R6.reuse ?trans1;
LDG.E R36, desc[UR4][R12.64+0x4] &wr=0x4 ?trans4;
LDG.E R35, desc[UR4][R16.64] &rd=0x0 &wr=0x4 ?trans1;
IMAD.WIDE R20, R21, 0x4, R6 ?WAIT3_END_GROUP;
LDG.E R19, desc[UR4][R18.64] &wr=0x4 ?trans1;
IMAD.WIDE R14, R15, 0x4, R6 ?WAIT3_END_GROUP;
LDG.E R21, desc[UR4][R20.64] &wr=0x4 ?trans1;
IMAD.WIDE R22, R23, 0x4, R6 ?WAIT3_END_GROUP;
LDG.E R15, desc[UR4][R14.64] &wr=0x4 ?trans4;
LDG.E R18, desc[UR4][R12.64+-0x4] &wr=0x4 ?trans1;
IMAD.WIDE R16, R33, 0x4, R6 &req={0} ?WAIT3_END_GROUP;
LDG.E R23, desc[UR4][R22.64] &wr=0x4 ?trans4;
LDG.E R33, desc[UR4][R12.64+0xc] &wr=0x4 ?trans4;
LDG.E R17, desc[UR4][R16.64] &wr=0x4 ?trans4;
LDG.E R37, desc[UR4][R12.64+0x14] &wr=0x4 ?trans4;
LDG.E R14, desc[UR4][R12.64+0x1c] &wr=0x4 ?trans1;
IADD3 R26, PT, PT, R26, 0x8, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R26, RZ, PT ?trans1;
IADD3 R27, PT, PT, R27, 0x10, RZ ?trans1;
IMAD R29, R0, R29, RZ &req={5,2} ?WAIT4_END_GROUP;
IMAD R28, R28, R29, RZ ?trans2;
IMAD R31, R0, R31, RZ &req={3} ?WAIT4_END_GROUP;
IMAD R31, R30, R31, R28 ?trans2;
IMAD R35, R0, R35, RZ &req={4} ?WAIT4_END_GROUP;
IMAD R31, R34, R35, R31 ?trans2;
IMAD R19, R0.reuse, R19, RZ ?trans2;
IMAD R21, R0.reuse, R21, RZ ?trans2;
IMAD R15, R0, R15, RZ ?trans2;
IMAD R19, R18, R19, R31 ?WAIT4_END_GROUP;
IMAD R36, R36, R21, R19 ?trans2;
IMAD R23, R0.reuse, R23, RZ ?trans2;
IMAD R36, R33, R15, R36 ?trans2;
IMAD R17, R0, R17, RZ ?trans2;
IMAD R23, R37, R23, R36 ?WAIT4_END_GROUP;
IMAD R14, R14, R17, R23 ?WAIT5_END_GROUP;
IADD3 R3, PT, PT, -R14, R3, RZ ?trans1;
@P1 BRA 0x260 ?trans6;
BSYNC.RECONVERGENT B1 ?trans5;
@!P0 BRA 0x9b0 ?trans5;
ISETP.GE.U32.AND P0, PT, R32, 0x4, PT ?trans1;
BSSY.RECONVERGENT B1, 0x7f0 ?trans1;
LOP3.LUT P1, R25, R25, 0x3, RZ, 0xc0, !PT ?WAIT11_END_GROUP;
@!P0 BRA 0x7e0 ?trans5;
LDC.64 R10, c[0x0][0x380] &wr=0x0 ?trans2;
IMAD.WIDE R10, R27, 0x4, R10 &req={0} ?WAIT5_END_GROUP;
LDG.E R15, desc[UR4][R10.64+0x8] &wr=0x2 ?trans4;
LDG.E R13, desc[UR4][R10.64] &wr=0x3 ?trans4;
LDG.E R17, desc[UR4][R10.64+0x10] &wr=0x4 ?trans4;
LDG.E R19, desc[UR4][R10.64+0x18] &wr=0x4 ?trans4;
LDG.E R21, desc[UR4][R10.64+0xc] &wr=0x4 ?trans4;
LDG.E R20, desc[UR4][R10.64+0x4] &wr=0x4 ?trans4;
LDG.E R26, desc[UR4][R10.64+0x14] &wr=0x4 ?trans4;
LDG.E R23, desc[UR4][R10.64+0x1c] &wr=0x4 ?trans1;
IMAD.WIDE R14, R15, 0x4, R6 &req={2} ?WAIT4_END_GROUP;
IMAD.WIDE R12, R13, 0x4, R6.reuse &req={3} ?trans2;
LDG.E R15, desc[UR4][R14.64] &wr=0x2 ?trans2;
IMAD.WIDE R16, R17, 0x4, R6.reuse &req={4} ?trans2;
LDG.E R13, desc[UR4][R12.64] &wr=0x3 ?trans2;
IMAD.WIDE R18, R19, 0x4, R6 ?trans2;
LDG.E R17, desc[UR4][R16.64] &wr=0x4 ?trans4;
LDG.E R19, desc[UR4][R18.64] &wr=0x4 ?trans1;
IADD3 R27, PT, PT, R27, 0x8, RZ ?trans1;
IMAD R22, R0, R15, RZ &req={5,2} ?WAIT4_END_GROUP;
IMAD R21, R21, R22, RZ ?trans2;
IMAD R13, R0.reuse, R13, RZ &req={3} ?trans2;
IMAD R12, R0, R17, RZ &req={4} ?trans2;
IMAD R13, R20, R13, R21 ?trans2;
IMAD R14, R0, R19, RZ ?trans2;
IMAD R12, R26, R12, R13 ?WAIT4_END_GROUP;
IMAD R12, R23, R14, R12 ?WAIT5_END_GROUP;
IADD3 R3, PT, PT, R3, -R12, RZ ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B1 ?trans5;
@!P1 BRA 0x9b0 ?trans5;
ISETP.NE.AND P1, PT, R25, 0x1, PT ?trans1;
LOP3.LUT P0, RZ, R24, 0x2, RZ, 0xc0, !PT ?WAIT12_END_GROUP;
@P1 LDC.64 R10, c[0x0][0x380] &wr=0x0 ?trans8;
@!P0 LDC.64 R12, c[0x0][0x380] &wr=0x1 ?trans1;
@P1 IMAD.WIDE R14, R27.reuse, 0x4, R10 &req={0} ?trans1;
@P1 IADD3 R27, PT, PT, R27, 0x4, RZ ?WAIT4_END_GROUP;
@P1 LDG.E R19, desc[UR4][R14.64+0x8] &wr=0x2 ?trans4;
@P1 LDG.E R17, desc[UR4][R14.64] &wr=0x3 ?trans1;
@!P0 IMAD.WIDE R10, R27, 0x4, R12 &req={1} ?WAIT3_END_GROUP;
@P1 LDG.E R22, desc[UR4][R14.64+0xc] &wr=0x4 ?trans4;
@!P0 LDG.E R13, desc[UR4][R10.64] &wr=0x4 ?trans4;
@P1 LDG.E R21, desc[UR4][R14.64+0x4] &wr=0x4 ?trans4;
@!P0 LDG.E R20, desc[UR4][R10.64+0x4] &wr=0x4 ?trans1;
@P1 IMAD.WIDE R18, R19, 0x4, R6 &req={2} ?WAIT4_END_GROUP;
@P1 IMAD.WIDE R16, R17, 0x4, R6.reuse &req={3} ?trans2;
@P1 LDG.E R19, desc[UR4][R18.64] &wr=0x2 ?trans4;
@P1 LDG.E R17, desc[UR4][R16.64] &wr=0x3 ?trans1;
@!P0 IMAD.WIDE R12, R13, 0x4, R6 &req={4} ?WAIT6_END_GROUP;
@!P0 LDG.E R12, desc[UR4][R12.64] &wr=0x4 ?trans1;
@P1 IMAD R23, R0, R19, RZ &req={5,2} ?WAIT4_END_GROUP;
@P1 IMAD R22, R22, R23, RZ ?trans2;
@P1 IMAD R18, R0, R17, RZ &req={3} ?trans1;
IADD3 R19, PT, PT, RZ, -R0, RZ ?WAIT3_END_GROUP;
@P1 IMAD R18, R21, R18, R22 ?trans2;
@!P0 IMAD R14, R19, R12, RZ &req={4} ?WAIT3_END_GROUP;
@P1 IADD3 R3, PT, PT, R3, -R18, RZ ?WAIT5_END_GROUP;
@!P0 IMAD R3, R20, R14, R3 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
IABS R13, R0.reuse &req={5} ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
IABS R16, R0 ?WAIT5_END_GROUP;
I2F.RP R12, R13 &wr=0x0 ?trans1;
BSSY.RECONVERGENT B0, 0xbf0 ?trans1;
MUFU.RCP R12, R12 &req={0} &wr=0x0 ?trans2;
IADD3 R10, PT, PT, R12, 0xffffffe, RZ &req={0} ?trans2;
IABS R12, R3 ?trans2;
LOP3.LUT R3, R3, R0, RZ, 0x3c, !PT ?trans1;
F2I.FTZ.U32.TRUNC.NTZ R11, R10 &rd=0x0 &wr=0x1 ?trans2;
HFMA2 R10, -RZ, RZ, 0, 0 &req={0} ?trans1;
IADD3 R14, PT, PT, RZ, -R11, RZ &req={1} ?WAIT5_END_GROUP;
IMAD R15, R14, R13, RZ ?trans1;
IADD3 R14, PT, PT, RZ, -R16, RZ ?WAIT3_END_GROUP;
IMAD.HI.U32 R11, R11, R15, R10 ?WAIT6_END_GROUP;
IMAD.HI.U32 R11, R11, R12, RZ ?WAIT4_END_GROUP;
IMAD R10, R11, R14, R12 ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R13, R10, PT ?WAIT13_END_GROUP;
@!P0 IADD3 R10, PT, PT, R10, -R13.reuse, RZ ?trans2;
@!P0 IADD3 R11, PT, PT, R11, 0x1, RZ ?trans1;
ISETP.GE.AND P0, PT, R3, RZ, PT ?trans2;
ISETP.GE.U32.AND P1, PT, R10, R13, PT ?WAIT13_END_GROUP;
@P1 IADD3 R11, PT, PT, R11, 0x1, RZ ?trans1;
ISETP.NE.AND P1, PT, R0, RZ, PT ?WAIT3_END_GROUP;
@!P0 IADD3 R11, PT, PT, -R11, RZ, RZ ?WAIT10_END_GROUP;
@!P1 LOP3.LUT R11, RZ, R0, RZ, 0x33, !PT ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R11, 0x1, PT ?WAIT13_END_GROUP;
@P0 MOV R3, 0xffffffff ?WAIT5_END_GROUP;
@P0 STG.E desc[UR4][R8.64], R3 &rd=0x0 ?trans1;
@P0 BRA 0xbe0 ?trans5;
ISETP.GT.AND P0, PT, R11, -0x1, PT ?trans1;
MOV R3, 0x1 &req={0} ?WAIT12_END_GROUP;
@!P0 STG.E desc[UR4][R8.64], R3 &rd=0x1 ?trans4;
@P0 STG.E desc[UR4][R8.64], R3 &rd=0x1 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDG.E R4, desc[UR4][R4.64] &wr=0x2 ?trans2;
ISETP.GE.AND P0, PT, R4, 0x1, PT &req={2} ?WAIT13_END_GROUP;
@!P0 EXIT ?trans5;
I2F.U32.RP R0, R2 &wr=0x2 ?trans1;
ISETP.NE.U32.AND P1, PT, R2, RZ, PT ?trans1;
MUFU.RCP R0, R0 &req={2} &wr=0x2 ?trans2;
IADD3 R4, PT, PT, R0, 0xffffffe, RZ &req={2} ?WAIT4_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R5, R4 &rd=0x2 &wr=0x3 ?trans2;
HFMA2 R4, -RZ, RZ, 0, 0 &req={2} ?trans1;
IADD3 R3, PT, PT, RZ, -R5, RZ &req={3,1,0} ?WAIT5_END_GROUP;
IMAD R3, R3, R2, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R5, R5, R3, R4 ?WAIT6_END_GROUP;
IMAD.HI.U32 R5, R5, -0x4280fc4a, RZ ?WAIT5_END_GROUP;
IADD3 R5, PT, PT, -R5, RZ, RZ ?WAIT5_END_GROUP;
IMAD R3, R2, R5, -0x4280fc4a ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R3, R2, PT ?WAIT13_END_GROUP;
@P0 IADD3 R3, PT, PT, R3, -R2, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R3, R2, PT ?WAIT13_END_GROUP;
@P0 IADD3 R3, PT, PT, R3, -R2.reuse, RZ ?trans2;
@!P1 LOP3.LUT R3, RZ, R2, RZ, 0x33, !PT ?WAIT5_END_GROUP;
IMAD.WIDE R6, R3, 0x4, R6 ?WAIT5_END_GROUP;
LDG.E R0, desc[UR4][R6.64] &wr=0x2 ?trans2;
ISETP.NE.AND P0, PT, R0, 0x1, PT &req={2} ?WAIT13_END_GROUP;
@!P0 MOV R3, 0xffffffff ?WAIT5_END_GROUP;
@!P0 STG.E desc[UR4][R6.64], R3 &rd=0x0 ?trans1;
@!P0 EXIT ?trans5;
MOV R3, 0x1 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R3 ?trans1;
EXIT ?trans5;
BRA 0xdd0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: isingAnnealingStep(int*, int*, int*, int*, int, int)
_Z18isingAnnealingStepPiS_S_S_ii:
s_clause 0x2
s_load_b32 s10, s[0:1], 0x34
s_load_b64 s[8:9], s[0:1], 0x20
s_load_b256 s[0:7], s[0:1], 0x0
v_mov_b32_e32 v6, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s10, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
v_mov_b32_e32 v0, s9
s_mov_b32 s9, exec_lo
global_store_b32 v6, v0, s[6:7]
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_7
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_mov_b32 s2, exec_lo
global_load_b64 v[2:3], v[2:3], off
global_load_b32 v7, v[0:1], off
s_waitcnt vmcnt(1)
v_cmpx_lt_i32_e64 v2, v3
s_cbranch_execz .LBB0_5
v_ashrrev_i32_e32 v5, 31, v2
v_mov_b32_e32 v4, v2
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v4, vcc_lo, v4, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_mov_b32 s1, 0
v_add_co_u32 v4, vcc_lo, v4, 4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
.LBB0_3:
global_load_b64 v[8:9], v[4:5], off offset:-4
v_add_nc_u32_e32 v2, 2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s0, v2, v3
s_or_b32 s1, s0, s1
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v11, 31, v8
v_mov_b32_e32 v10, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], 2, v[10:11]
v_add_co_u32 v10, vcc_lo, s4, v10
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
v_add_co_u32 v4, vcc_lo, v4, 8
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
global_load_b32 v8, v[10:11], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v8, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v8, v8, v9
v_sub_nc_u32_e32 v6, v6, v8
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s1
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v2, 31, v7
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_mov_b32 s1, 0
v_add_nc_u32_e32 v3, v7, v2
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v3, v3, v2
v_add_nc_u32_e32 v6, v6, v7
v_xor_b32_e32 v2, v7, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cvt_f32_u32_e32 v4, v3
v_sub_nc_u32_e32 v5, 0, v3
v_xor_b32_e32 v6, v6, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
v_cvt_u32_f32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v5, v4
v_mul_hi_u32 v5, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v4, v5
v_mul_hi_u32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v4, v3
v_sub_nc_u32_e32 v5, v6, v5
v_add_nc_u32_e32 v6, 1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v8, v5, v3
v_cmp_ge_u32_e32 vcc_lo, v5, v3
v_dual_cndmask_b32 v5, v5, v8 :: v_dual_cndmask_b32 v4, v4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ge_u32_e32 vcc_lo, v5, v3
v_add_nc_u32_e32 v6, 1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v4, v6, vcc_lo
v_xor_b32_e32 v3, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v3, v2
v_cmp_lt_i32_e32 vcc_lo, -1, v2
v_mov_b32_e32 v2, 0
v_cndmask_b32_e64 v3, 1, -1, vcc_lo
global_store_b32 v[0:1], v3, off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
global_load_b32 v0, v2, s[6:7]
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, 0, v0
s_cbranch_vccz .LBB0_7
v_cvt_f32_u32_e32 v0, s8
s_sub_i32 s2, 0, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v0
s_mul_i32 s2, s2, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s2, s0, s2
s_add_i32 s0, s0, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s0, s0, 0x62d407df
s_mul_i32 s0, s0, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_sub_i32 s0, 0x62d407df, s0
s_sub_i32 s2, s0, s8
s_cmp_ge_u32 s0, s8
s_cselect_b32 s0, s2, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_sub_i32 s2, s0, s8
s_cmp_ge_u32 s0, s8
s_cselect_b32 s0, s2, s0
s_lshl_b64 s[0:1], s[0:1], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
global_load_b32 v0, v2, s[0:1]
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 1, v0
v_cndmask_b32_e64 v0, 1, -1, vcc_lo
global_store_b32 v2, v0, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| isingAnnealingStep | 5,977 | 2,987 | stackv2-00000-of-00015 |
// Demangled: dot(int*, int*, int*)
Function : _Z3dotPiS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x2 ?trans7;
LDC R7, c[0x0][0x360] &wr=0x1 ?trans8;
LDC.64 R2, c[0x0][0x380] &wr=0x3 ?trans8;
LDC.64 R4, c[0x0][0x388] &wr=0x4 ?trans1;
IMAD R7, R7, UR4, R0 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE R2, R7, 0x4, R2 &req={3} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR6][R2.64] &req={2} &wr=0x2 ?trans1;
IMAD.WIDE R4, R7, 0x4, R4 &req={4} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR6][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.NE.AND P0, PT, R0, RZ, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R7, R0, UR4, 0x2 ?trans1;
IMAD R0, R2, R5, RZ &req={2} ?WAIT5_END_GROUP;
STS [R7], R0 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT &req={0} ?trans5;
LDS R7, [R7] &req={1} &wr=0x0 ?trans1;
LDC.64 R2, c[0x0][0x390] &wr=0x1 ?trans1;
SHF.L.U32 R5, R7, 0x7, RZ &req={0} ?WAIT5_END_GROUP;
REDG.E.ADD.STRONG.GPU desc[UR6][R2.64], R5 &req={1} ?trans1;
EXIT ?trans5;
BRA 0x1a0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: dot(int*, int*, int*)
_Z3dotPiS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, 0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v3, v[3:4], off
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v1, v3
v_lshlrev_b32_e32 v1, 2, v0
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_5
ds_load_b32 v0, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
v_lshlrev_b32_e32 v0, 7, v0
.LBB0_2:
s_ctz_i32_b32 s4, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s5, v0, s4
s_lshl_b32 s4, 1, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_not1_b32 s3, s3, s4
s_add_i32 s2, s2, s5
s_cmp_lg_u32 s3, 0
s_cbranch_scc1 .LBB0_2
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_5
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| dot | 687 | 887 | stackv2-00000-of-00015 |
// Demangled: symmetrize2D(float*, int)
Function : _Z12symmetrize2DPfi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans7;
LDC R5, c[0x0][0x388] &wr=0x2 ?trans8;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans8;
LDC R0, c[0x0][0x360] &wr=0x1 ?trans1;
IMAD R5, R5, 0x3, RZ &req={2} ?WAIT2_END_GROUP;
IMAD R0, R0, UR4, R3 &req={1} ?trans2;
IMAD R3, R5, R5, RZ ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, R3, PT ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
IABS R7, R5.reuse ?trans2;
IABS R8, R5 ?trans2;
I2F.RP R4, R7 &wr=0x0 ?trans2;
MUFU.RCP R4, R4 &req={0} &wr=0x0 ?trans2;
IADD3 R2, PT, PT, R4, 0xffffffe, RZ &req={0} ?trans2;
IABS R4, R0 ?WAIT2_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R3, R2 &rd=0x0 &wr=0x1 ?trans2;
HFMA2 R2, -RZ, RZ, 0, 0 &req={0} ?trans1;
IADD3 R6, PT, PT, RZ, -R3, RZ &req={1} ?WAIT5_END_GROUP;
IMAD R9, R6, R7, RZ ?trans1;
IADD3 R6, PT, PT, RZ, -R8, RZ ?WAIT3_END_GROUP;
IMAD.HI.U32 R3, R3, R9, R2 ?WAIT6_END_GROUP;
IMAD.HI.U32 R3, R3, R4, RZ ?WAIT4_END_GROUP;
IMAD R2, R3, R6, R4 ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R7, R2, PT ?WAIT13_END_GROUP;
@!P0 IADD3 R2, PT, PT, R2, -R7, RZ ?trans2;
@!P0 IADD3 R3, PT, PT, R3, 0x1, RZ ?WAIT3_END_GROUP;
ISETP.GE.U32.AND P1, PT, R2, R7, PT ?trans1;
LOP3.LUT R2, R0, R5, RZ, 0x3c, !PT ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R2, RZ, PT ?WAIT7_END_GROUP;
@P1 IADD3 R3, PT, PT, R3, 0x1, RZ ?trans1;
ISETP.NE.AND P1, PT, R5, RZ, PT ?WAIT4_END_GROUP;
MOV R4, R3 ?WAIT5_END_GROUP;
@!P0 IADD3 R4, PT, PT, -R4, RZ, RZ ?WAIT4_END_GROUP;
@!P1 LOP3.LUT R4, RZ, R5, RZ, 0x33, !PT ?WAIT4_END_GROUP;
IADD3 R2, PT, PT, -R4, RZ, RZ ?WAIT5_END_GROUP;
IMAD R7, R5, R2, R0 ?WAIT5_END_GROUP;
ISETP.GT.AND P0, PT, R4, R7, PT ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD R9, R5.reuse, R7, R4 ?trans2;
IMAD R7, R5, R4, R7 ?trans2;
IMAD.WIDE R4, R9, 0x4, R2 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE R2, R7, 0x4, R2 ?trans2;
LDG.E R7, desc[UR4][R4.64] &req={1} &wr=0x2 ?trans4;
LDG.E R0, desc[UR4][R2.64] &wr=0x2 ?trans2;
FADD R0, R0, R7 &req={2} ?WAIT4_END_GROUP;
FMUL R7, R0, 0.5 ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R7 ?trans4;
STG.E desc[UR4][R4.64], R7 ?trans1;
EXIT ?trans5;
BRA 0x340;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: symmetrize2D(float*, int)
_Z12symmetrize2DPfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mul_i32 s2, s3, 3
s_mul_i32 s3, s2, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_3
s_ashr_i32 s3, s2, 31
v_ashrrev_i32_e32 v3, 31, v1
s_add_i32 s4, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s4, s4, s3
v_add_nc_u32_e32 v4, v1, v3
v_cvt_f32_u32_e32 v0, s4
s_sub_i32 s5, 0, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v4, v3
v_rcp_iflag_f32_e32 v0, v0
v_xor_b32_e32 v3, s3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v4, v0
v_mul_lo_u32 v2, v0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v0
v_subrev_nc_u32_e32 v5, s4, v2
v_cmp_le_u32_e32 vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 1, v0
v_cmp_le_u32_e32 vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v3
v_mul_lo_u32 v2, v0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v1, v1, v2
v_cmp_le_i32_e32 vcc_lo, v0, v1
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
v_mad_u64_u32 v[4:5], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_lshlrev_b64 v[2:3], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_load_b32 v4, v[0:1], off
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v4, 0.5, v4
s_clause 0x1
global_store_b32 v[0:1], v4, off
global_store_b32 v[2:3], v4, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| symmetrize2D | 1,263 | 1,766 | stackv2-00000-of-00015 |
// Demangled: distanceKernel(float*, int, int, float2)
Function : _Z14distanceKernelPfii6float2
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.Y &wr=0x1 ?trans7;
LDC R4, c[0x0][0x360] &wr=0x2 ?trans1;
LDCU.64 UR6, c[0x0][0x388] &wr=0x3 ?trans1;
S2R R3, SR_TID.X &wr=0x2 ?trans6;
S2UR UR5, SR_CTAID.Y &wr=0x1 ?trans8;
LDC R5, c[0x0][0x364] &wr=0x1 ?trans8;
S2UR UR4, SR_CTAID.X &wr=0x2 ?trans1;
IMAD R5, R5, UR5, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R5, UR7, PT &req={3} ?trans1;
IMAD R4, R4, UR4, R3 &req={2} ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R4, UR6, P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDCU.64 UR4, c[0x0][0x390] &wr=0x0 ?trans1;
I2FP.F32.U32 R2, R5 ?trans1;
BSSY.RECONVERGENT B0, 0x220 ?trans1;
I2FP.F32.S32 R0, R4 ?WAIT3_END_GROUP;
FADD R2, R2, -UR5 &req={0} ?trans2;
FADD R0, R0, -UR4 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans1;
FMUL R3, R2, R2 ?WAIT4_END_GROUP;
FFMA R0, R0, R0, R3 ?WAIT4_END_GROUP;
MUFU.RSQ R3, R0 &rd=0x1 &wr=0x2 ?trans1;
IADD3 R2, PT, PT, R0, -0xd000000, RZ ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R2, 0x727fffff, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x1d0 &req={2,1,0} ?trans5;
MOV R9, 0x1c0 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x280 ?trans5;
BRA 0x210 ?trans5;
FMUL.FTZ R7, R0, R3 ?trans1;
FMUL.FTZ R3, R3, 0.5 ?WAIT3_END_GROUP;
FFMA R0, -R7, R7, R0 ?WAIT4_END_GROUP;
FFMA R7, R0, R3, R7 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU UR6, c[0x0][0x388] &wr=0x1 ?trans2;
IMAD R5, R5, UR6, R4 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE R2, R5, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R7 ?trans1;
EXIT ?trans5;
LOP3.LUT P0, RZ, R0, 0x7fffffff, RZ, 0xc0, !PT ?WAIT13_END_GROUP;
@!P0 MOV R2, R0 ?trans1;
@!P0 BRA 0x3b0 ?trans6;
FSETP.GEU.FTZ.AND P0, PT, R0, RZ, PT ?WAIT13_END_GROUP;
@!P0 MOV R2, 0x7fffffff ?trans1;
@!P0 BRA 0x3b0 ?trans6;
FSETP.GTU.FTZ.AND P0, PT, |R0|, +INF , PT ?WAIT13_END_GROUP;
@P0 FADD.FTZ R2, R0, 1 ?trans1;
@P0 BRA 0x3b0 ?trans6;
FSETP.NEU.FTZ.AND P0, PT, |R0|, +INF , PT ?WAIT13_END_GROUP;
@P0 FFMA R3, R0, 1.84467440737095516160e+19, RZ ?WAIT4_END_GROUP;
@P0 MUFU.RSQ R2, R3 &wr=0x0 ?trans2;
@P0 FMUL.FTZ R6, R3, R2 &req={0} ?trans1;
@P0 FMUL.FTZ R8, R2, 0.5 ?trans1;
@!P0 MOV R2, R0 ?trans2;
@P0 FADD.FTZ R7, -R6, -RZ ?WAIT4_END_GROUP;
@P0 FFMA R7, R6, R7, R3 ?WAIT4_END_GROUP;
@P0 FFMA R7, R7, R8, R6 ?WAIT4_END_GROUP;
@P0 FMUL.FTZ R2, R7, 2.3283064365386962891e-10 ?WAIT7_END_GROUP;
MOV R7, R2 ?trans1;
MOV R2, R9 ?trans1;
HFMA2 R3, -RZ, RZ, 0, 0 ?WAIT4_END_GROUP;
RET.REL.NODEC R2 0x0 ?trans5;
BRA 0x3f0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: distanceKernel(float*, int, int, HIP_vector_type<float, 2u>)
_Z14distanceKernelPfii15HIP_vector_typeIfLj2EE:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v0
v_cmp_gt_i32_e64 s2, s5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[0:1], 0x10
v_cvt_f32_i32_e32 v2, v0
v_cvt_f32_i32_e32 v3, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_subrev_f32 v2, s2, v2 :: v_dual_subrev_f32 v3, s3, v3
v_mul_f32_e32 v2, v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, v3, v3
v_mul_f32_e32 v3, 0x4f800000, v2
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, v2, v3, vcc_lo
v_sqrt_f32_e32 v2, v4
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v3, -1, v2
v_add_nc_u32_e32 v5, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v6, -v3, v2, v4
v_fma_f32 v7, -v5, v2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s2, 0, v6
v_cndmask_b32_e64 v6, v2, v3, s2
s_load_b64 s[2:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_lt_f32_e64 s0, 0, v7
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
v_cndmask_b32_e64 v0, v6, v5, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_mul_f32_e32 v1, 0x37800000, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v5, v0, v1, vcc_lo
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_cmp_class_f32_e64 vcc_lo, v4, 0x260
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v2, v5, v4, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| distanceKernel | 1,461 | 1,373 | stackv2-00000-of-00015 |
// Demangled: add_vec_kernel(double const*, double const*, double*, int)
Function : _Z14add_vec_kernelPKdS0_Pdi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x398] &wr=0x2 ?trans7;
LDC R7, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R7, R7, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R7, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans8;
LDC.64 R8, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD.WIDE R2, R7, 0x8, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E.64.CONSTANT R2, desc[UR4][R2.64] &req={1} &wr=0x4 ?trans1;
IMAD.WIDE R4, R7, 0x8, R4 &req={2} ?WAIT6_END_GROUP;
LDG.E.64.CONSTANT R4, desc[UR4][R4.64] &wr=0x4 ?trans1;
IMAD.WIDE R8, R7, 0x8, R8 &req={3} ?trans1;
DADD R6, R2, R4 &req={4} &wr=0x0 ?trans4;
STG.E.64 desc[UR4][R8.64], R6 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x140;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: add_vec_kernel(double const*, double const*, double*, int)
_Z14add_vec_kernelPKdS0_Pdi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| add_vec_kernel | 592 | 594 | stackv2-00000-of-00015 |
// Demangled: points_inside_boxes(int, int, float const*, float const*, int*)
Function : _Z19points_inside_boxesiiPKfS0_Pi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
S2UR UR5, SR_CTAID.X &wr=0x1 ?trans8;
LDC R0, c[0x0][0x380] &wr=0x1 ?trans2;
ISETP.LE.AND P0, PT, R0, UR5, PT &req={1} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDCU UR6, c[0x0][0x360] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans1;
LDC.64 R16, c[0x0][0x388] &wr=0x2 ?trans1;
LDCU.64 UR8, c[0x0][0x358] &wr=0x3 ?trans1;
UI2F.U32.RP UR4, UR6 &req={0} ?trans2;
ISETP.NE.U32.AND P2, PT, RZ, UR6, PT ?WAIT7_END_GROUP;
MUFU.RCP R2, UR4 &wr=0x0 ?trans2;
LDCU UR4, c[0x0][0x384] &wr=0x4 ?trans1;
IMAD R13, R0, 0x3, RZ &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R12, R13, 0x4, R16 &req={2} ?trans1;
IADD3 R4, PT, PT, R2, 0xffffffe, RZ &req={0} ?trans2;
IADD3 R2, PT, PT, R0, UR6, RZ ?trans2;
F2I.FTZ.U32.TRUNC.NTZ R5, R4 &rd=0x0 &wr=0x1 ?trans3;
ISETP.GE.AND P0, PT, R2.reuse, UR4, PT &req={4} ?trans1;
VIMNMX.S32 R3, R2.reuse, UR4, !PT ?trans1;
IMAD R15, R2, 0x3, RZ ?WAIT3_END_GROUP;
SEL R6, RZ, 0x1, P0 ?trans1;
IMAD.WIDE.U32 R14, R15, 0x4, R16 ?WAIT4_END_GROUP;
HFMA2 R4, -RZ, RZ, 0, 0 &req={0} ?trans1;
IADD3 R3, PT, PT, R3, -R2, -R6 ?trans2;
IADD3 R7, PT, PT, RZ, -R5, RZ &req={1} ?WAIT5_END_GROUP;
IMAD R7, R7, UR6, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R8, R5, R7, R4 ?WAIT6_END_GROUP;
IMAD.HI.U32 R5, R8, R3, RZ ?trans1;
MOV R8, UR5 ?WAIT4_END_GROUP;
IADD3 R4, PT, PT, -R5, RZ, RZ ?WAIT5_END_GROUP;
IMAD R3, R4, UR6, R3 ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R3, UR6, PT ?WAIT13_END_GROUP;
@P0 IADD3 R3, PT, PT, R3, -UR6, RZ ?trans2;
@P0 IADD3 R5, PT, PT, R5, 0x1, RZ ?WAIT3_END_GROUP;
ISETP.GE.U32.AND P1, PT, R3, UR6, PT ?trans2;
LDC R3, c[0x0][0x370] &wr=0x0 ?trans11;
@P1 IADD3 R5, PT, PT, R5, 0x1, RZ ?WAIT2_END_GROUP;
@!P2 LOP3.LUT R5, RZ, UR6, RZ, 0x33, !PT ?WAIT4_END_GROUP;
IADD3 R4, PT, PT, R6, R5, RZ ?trans2;
IADD3 R6, PT, PT, R2, UR6, RZ ?trans2;
IADD3 R7, PT, PT, R4, 0x1, RZ ?WAIT3_END_GROUP;
IMAD R5, R6, 0x3, RZ ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R16, R5, 0x4, R16 ?trans1;
IADD3 R5, PT, PT, R6, UR6, RZ ?trans2;
LOP3.LUT R7, R7, 0x3, RZ, 0xc0, !PT &req={3} ?WAIT7_END_GROUP;
LDC.64 R24, c[0x0][0x390] &req={3,1,0} &wr=0x1 ?trans1;
IMAD R9, R8, 0x6, RZ ?trans1;
LDCU.64 UR4, c[0x0][0x380] &req={2} &wr=0x2 ?trans1;
LDCU.64 UR10, c[0x0][0x398] &wr=0x3 ?trans2;
IMAD.WIDE R24, R9, 0x4, R24 &req={1} ?WAIT5_END_GROUP;
LDG.E R9, desc[UR8][R24.64] &wr=0x4 ?trans4;
LDG.E R28, desc[UR8][R24.64+0xc] &wr=0x5 ?trans4;
LDG.E R32, desc[UR8][R24.64+0x8] &wr=0x3 ?trans4;
LDG.E R29, desc[UR8][R24.64+0x14] &wr=0x3 ?trans1;
ISETP.GE.AND P0, PT, R0, UR5, PT &req={2} ?trans1;
IMAD R18, R8, UR5, RZ ?trans1;
IADD3 R8, PT, PT, R3, R8, RZ &req={0} ?trans1;
BSSY.RECONVERGENT B0, 0x1080 ?trans3;
SHF.R.S32.HI R19, RZ, 0x1f, R18 ?trans1;
ISETP.GE.AND P2, PT, R8, UR4, PT ?trans1;
F2F.F64.F32 R20, R9 &req={4} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2F.F64.F32 R10, R28 &req={5} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R26, R10, -0.5, R20 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2F.F64.F32 R32, R32 &req={3} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R20, R10, 0.5, R20 &rd=0x1 &wr=0x2 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2F.F64.F32 R10, R29 &req={1} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R22, R10, -0.5, R32 &req={1} &rd=0x1 &wr=0x3 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R32, R10, 0.5, R32 &rd=0x1 &wr=0x4 ?trans2;
@P0 BRA 0x1070 &req={4,3,2,1,0} ?trans5;
LDG.E R9, desc[UR8][R24.64+0x4] &wr=0x2 ?trans4;
LDG.E R28, desc[UR8][R24.64+0x10] &wr=0x2 ?trans1;
ISETP.NE.AND P0, PT, R7, RZ, PT ?trans1;
F2F.F32.F64 R10, R26 &rd=0x0 &wr=0x1 ?trans1;
BSSY.RECONVERGENT B1, 0xb50 ?trans1;
MOV R34, R0 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2F.F32.F64 R11, R22 &rd=0x0 &wr=0x3 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2F.F32.F64 R30, R20 &rd=0x0 &wr=0x4 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2F.F32.F64 R32, R32 &rd=0x0 &wr=0x0 ?trans1;
FADD R31, R9, -R28 &req={2} ?trans1;
@!P0 BRA 0xb40 &req={4,3,1,0} ?trans6;
LDG.E R23, desc[UR8][R12.64] &wr=0x2 ?trans1;
LDC.64 R20, c[0x0][0x398] &wr=0x0 ?trans3;
LDG.E R22, desc[UR8][R12.64+0x4] &wr=0x3 ?trans4;
LDG.E R26, desc[UR8][R12.64+0x8] &wr=0x4 ?trans1;
MOV R34, R2 ?trans1;
FSETP.GTU.AND P0, PT, R23, R30, PT &req={2} ?trans1;
FSETP.GTU.AND P1, PT, R22, R9, PT &req={3} ?WAIT4_END_GROUP;
FSETP.GE.AND P0, PT, R23, R10, !P0 ?trans1;
HFMA2 R23, -RZ, RZ, 0, 0 ?trans1;
FSETP.GTU.AND P3, PT, R26, R32, PT &req={4} ?trans1;
FSETP.GE.AND P1, PT, R22, R31, !P1 ?trans1;
MOV R22, R0 ?WAIT3_END_GROUP;
FSETP.GE.AND P3, PT, R26, R11, !P3 ?trans2;
IADD.64 R24, R18, R22 ?WAIT3_END_GROUP;
PLOP3.LUT P0, PT, P3, P0, P1, 0x80, 0x0 ?trans2;
LEA R22, P4, R24, R20, 0x2 &req={0} ?WAIT4_END_GROUP;
LEA.HI.X R23, R24, R21, R25, 0x2, P4 ?trans1;
SEL R25, RZ, 0x1, !P0 ?trans1;
ISETP.NE.AND P0, PT, R7, 0x1, PT ?WAIT4_END_GROUP;
STG.E desc[UR8][R22.64], R25 &rd=0x0 ?trans9;
@!P0 BRA 0xb40 ?trans5;
LDG.E R23, desc[UR8][R14.64] &req={0} &wr=0x2 ?trans4;
LDG.E R22, desc[UR8][R14.64+0x4] &wr=0x3 ?trans4;
LDG.E R26, desc[UR8][R14.64+0x8] &wr=0x4 ?trans1;
MOV R34, R6 ?trans1;
FSETP.GTU.AND P0, PT, R23, R30, PT &req={2} ?trans1;
FSETP.GTU.AND P1, PT, R22, R9, PT &req={3} ?WAIT4_END_GROUP;
FSETP.GE.AND P0, PT, R23, R10, !P0 ?trans1;
MOV R23, RZ ?trans1;
FSETP.GTU.AND P3, PT, R26, R32, PT &req={4} ?trans1;
FSETP.GE.AND P1, PT, R22, R31, !P1 ?trans1;
MOV R22, R2 ?WAIT3_END_GROUP;
FSETP.GE.AND P3, PT, R26, R11, !P3 ?trans2;
IADD.64 R24, R18, R22 ?WAIT3_END_GROUP;
PLOP3.LUT P0, PT, P3, P0, P1, 0x80, 0x0 ?trans2;
LEA R22, P4, R24, R20, 0x2 ?WAIT4_END_GROUP;
LEA.HI.X R23, R24, R21, R25, 0x2, P4 ?trans1;
SEL R25, RZ, 0x1, !P0 ?trans1;
ISETP.NE.AND P0, PT, R7, 0x2, PT ?WAIT4_END_GROUP;
STG.E desc[UR8][R22.64], R25 &rd=0x1 ?trans9;
@!P0 BRA 0xb40 ?trans5;
LDG.E R22, desc[UR8][R16.64+0x4] &req={1} &wr=0x2 ?trans4;
LDG.E R23, desc[UR8][R16.64+0x8] &wr=0x3 ?trans4;
LDG.E R25, desc[UR8][R16.64] &wr=0x4 ?trans1;
MOV R34, R5 ?trans1;
FSETP.GTU.AND P1, PT, R22, R9, PT &req={2} ?trans1;
FSETP.GTU.AND P0, PT, R23, R32, PT &req={3} ?WAIT4_END_GROUP;
FSETP.GE.AND P1, PT, R22, R31, !P1 ?trans1;
MOV R22, R6 ?trans1;
FSETP.GTU.AND P3, PT, R25, R30, PT &req={4} ?trans1;
FSETP.GE.AND P0, PT, R23, R11, !P0 ?trans1;
HFMA2 R23, -RZ, RZ, 0, 0 ?WAIT3_END_GROUP;
FSETP.GE.AND P3, PT, R25, R10, !P3 ?trans2;
IADD.64 R22, R18, R22 ?WAIT3_END_GROUP;
PLOP3.LUT P0, PT, P0, P3, P1, 0x80, 0x0 ?trans2;
LEA R20, P4, R22, R20, 0x2 ?WAIT4_END_GROUP;
LEA.HI.X R21, R22, R21, R23, 0x2, P4 ?trans1;
SEL R23, RZ, 0x1, !P0 ?WAIT5_END_GROUP;
STG.E desc[UR8][R20.64], R23 &rd=0x2 ?trans3;
BSYNC.RECONVERGENT B1 ?trans5;
LDC.64 R20, c[0x0][0x388] &req={2} &wr=0x2 ?trans1;
ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x1070 ?trans5;
IMAD R29, R34, 0x3, RZ ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R28, R29, 0x4, R20 &req={2} ?WAIT5_END_GROUP;
LDG.E R23, desc[UR8][R28.64] &req={3,1,0} &wr=0x2 ?trans4;
LDG.E R22, desc[UR8][R28.64+0x4] &wr=0x3 ?trans4;
LDG.E R24, desc[UR8][R28.64+0x8] &wr=0x4 ?trans1;
FSETP.GTU.AND P0, PT, R23, R30, PT &req={2} ?trans1;
FSETP.GTU.AND P1, PT, R22, R9, PT &req={3} ?WAIT4_END_GROUP;
FSETP.GE.AND P0, PT, R23, R10, !P0 ?trans1;
HFMA2 R23, -RZ, RZ, 0, 0 ?trans1;
FSETP.GTU.AND P3, PT, R24, R32, PT &req={4} ?trans1;
FSETP.GE.AND P1, PT, R22, R31, !P1 ?trans1;
MOV R22, R34 ?WAIT3_END_GROUP;
FSETP.GE.AND P3, PT, R24, R11, !P3 ?trans2;
IADD.64 R26, R18, R22 ?WAIT3_END_GROUP;
IADD3 R22, PT, PT, R34, UR6, RZ ?trans2;
PLOP3.LUT P0, PT, P3, P0, P1, 0x80, 0x0 ?trans2;
LEA R24, P4, R26, UR10, 0x2 ?trans1;
IMAD R29, R22, 0x3, RZ ?trans2;
SEL R23, RZ, 0x1, !P0 ?trans1;
LEA.HI.X R25, R26, UR11, R27, 0x2, P4 ?trans1;
IMAD.WIDE.U32 R28, R29, 0x4, R20 ?WAIT4_END_GROUP;
STG.E desc[UR8][R24.64], R23 &rd=0x0 ?trans4;
LDG.E R27, desc[UR8][R28.64] &wr=0x2 ?trans4;
LDG.E R26, desc[UR8][R28.64+0x4] &wr=0x3 ?trans4;
LDG.E R33, desc[UR8][R28.64+0x8] &wr=0x4 ?trans1;
MOV R23, RZ &req={0} ?trans1;
FSETP.GTU.AND P0, PT, R27, R30, PT &req={2} ?trans1;
FSETP.GTU.AND P1, PT, R26, R9, PT &req={3} ?WAIT4_END_GROUP;
FSETP.GE.AND P0, PT, R27, R10, !P0 ?trans1;
FSETP.GTU.AND P3, PT, R33, R32, PT &req={4} ?trans1;
FSETP.GE.AND P1, PT, R26, R31, !P1 ?trans1;
IADD.64 R26, R18, R22 ?WAIT3_END_GROUP;
IADD3 R22, PT, PT, R22, UR6, RZ ?trans1;
FSETP.GE.AND P3, PT, R33, R11, !P3 ?trans1;
LEA R24, P4, R26, UR10, 0x2 ?WAIT3_END_GROUP;
IMAD R29, R22, 0x3, RZ ?trans1;
PLOP3.LUT P0, PT, P3, P0, P1, 0x80, 0x0 ?trans2;
LEA.HI.X R25, R26, UR11, R27, 0x2, P4 ?trans1;
IMAD.WIDE.U32 R28, R29, 0x4, R20 ?trans2;
SEL R23, RZ, 0x1, !P0 ?WAIT5_END_GROUP;
STG.E desc[UR8][R24.64], R23 &rd=0x0 ?trans4;
LDG.E R27, desc[UR8][R28.64] &wr=0x2 ?trans4;
LDG.E R26, desc[UR8][R28.64+0x4] &wr=0x3 ?trans4;
LDG.E R33, desc[UR8][R28.64+0x8] &wr=0x4 ?trans1;
HFMA2 R23, -RZ, RZ, 0, 0 &req={0} ?trans1;
FSETP.GTU.AND P0, PT, R27, R30, PT &req={2} ?trans1;
FSETP.GTU.AND P1, PT, R26, R9, PT &req={3} ?WAIT4_END_GROUP;
FSETP.GE.AND P0, PT, R27, R10, !P0 ?trans1;
FSETP.GTU.AND P3, PT, R33, R32, PT &req={4} ?trans1;
FSETP.GE.AND P1, PT, R26, R31, !P1 ?trans1;
IADD.64 R26, R18, R22 ?WAIT3_END_GROUP;
IADD3 R22, PT, PT, R22, UR6, RZ ?trans1;
FSETP.GE.AND P3, PT, R33, R11, !P3 ?trans1;
LEA R24, P4, R26, UR10, 0x2 ?WAIT3_END_GROUP;
IMAD R29, R22, 0x3, RZ ?trans1;
PLOP3.LUT P0, PT, P3, P0, P1, 0x80, 0x0 ?trans2;
LEA.HI.X R25, R26, UR11, R27, 0x2, P4 ?trans1;
IMAD.WIDE.U32 R26, R29, 0x4, R20 ?trans2;
SEL R23, RZ, 0x1, !P0 ?WAIT5_END_GROUP;
STG.E desc[UR8][R24.64], R23 &rd=0x0 ?trans4;
LDG.E R29, desc[UR8][R26.64] &wr=0x2 ?trans4;
LDG.E R28, desc[UR8][R26.64+0x4] &wr=0x3 ?trans4;
LDG.E R33, desc[UR8][R26.64+0x8] &wr=0x4 ?trans1;
MOV R23, RZ &req={0} ?trans1;
IADD3 R34, PT, PT, R22, UR6, RZ ?trans1;
FSETP.GTU.AND P0, PT, R29, R30, PT &req={2} ?trans1;
FSETP.GTU.AND P1, PT, R28, R9, PT &req={3} ?WAIT4_END_GROUP;
FSETP.GE.AND P0, PT, R29, R10, !P0 ?trans1;
FSETP.GTU.AND P3, PT, R33, R32, PT &req={4} ?trans1;
FSETP.GE.AND P1, PT, R28, R31, !P1 ?trans1;
IADD.64 R28, R18, R22 ?WAIT3_END_GROUP;
FSETP.GE.AND P3, PT, R33, R11, !P3 ?trans2;
LEA R24, P4, R28, UR10, 0x2 ?WAIT3_END_GROUP;
PLOP3.LUT P0, PT, P3, P0, P1, 0x80, 0x0 ?trans2;
LEA.HI.X R25, R28, UR11, R29, 0x2, P4 ?WAIT3_END_GROUP;
SEL R23, RZ, 0x1, !P0 ?trans1;
ISETP.GE.AND P0, PT, R34, UR5, PT ?WAIT4_END_GROUP;
STG.E desc[UR8][R24.64], R23 &rd=0x3 ?trans9;
@!P0 BRA 0xb80 ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
@!P2 BRA 0x2e0 ?trans5;
EXIT ?trans5;
BRA 0x10a0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: points_inside_boxes(int, int, float const*, float const*, int*)
_Z19points_inside_boxesiiPKfS0_Pi:
s_load_b64 s[12:13], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s12
s_cbranch_scc1 .LBB0_6
s_clause 0x3
s_load_b128 s[8:11], s[0:1], 0x8
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b32 s7, s[0:1], 0x20
v_lshlrev_b32_e32 v3, 2, v0
v_cmp_gt_i32_e32 vcc_lo, s13, v0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, v0, 12, s[8:9]
s_and_b32 s14, s4, 0xffff
s_mul_i32 s8, s15, s13
s_mul_i32 s20, s14, 12
s_mul_i32 s21, s7, s13
s_lshl_b32 s22, s14, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s0, v1, 4
v_add_co_ci_u32_e64 v2, s0, 0, v2, s0
v_add_co_u32 v7, s0, s2, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v8, null, s3, 0, s0
.LBB0_2:
s_and_saveexec_b32 s23, vcc_lo
s_cbranch_execz .LBB0_5
s_mul_i32 s0, s15, 6
s_ashr_i32 s9, s8, 31
s_ashr_i32 s1, s0, 31
s_lshl_b64 s[2:3], s[8:9], 2
s_lshl_b64 s[0:1], s[0:1], 2
s_mov_b32 s9, 0
s_add_u32 s0, s10, s0
s_addc_u32 s1, s11, s1
s_clause 0x1
s_load_b128 s[16:19], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[3:4], s16
v_cvt_f64_f32_e32 v[5:6], s19
v_cvt_f64_f32_e32 v[9:10], s18
v_cvt_f64_f32_e32 v[11:12], s5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[13:14], v[5:6], -0.5, v[3:4]
v_fma_f64 v[3:4], v[5:6], 0.5, v[3:4]
v_fma_f64 v[15:16], v[11:12], -0.5, v[9:10]
v_fma_f64 v[5:6], v[11:12], 0.5, v[9:10]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cvt_f32_f64_e32 v9, v[13:14]
v_cvt_f32_f64_e32 v11, v[3:4]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cvt_f32_f64_e32 v10, v[15:16]
v_cvt_f32_f64_e32 v12, v[5:6]
v_add_co_u32 v3, s0, v7, s2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s0, s3, v8, s0
v_sub_f32_e64 v13, s17, s4
v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v5, v1
v_mov_b32_e32 v14, v0
.LBB0_4:
global_load_b96 v[15:17], v[5:6], off offset:-4
v_add_nc_u32_e32 v14, s14, v14
v_add_co_u32 v5, s0, v5, s20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v6, s0, 0, v6, s0
v_cmp_le_i32_e64 s0, s13, v14
s_waitcnt vmcnt(0)
v_cmp_ge_f32_e64 s1, v15, v9
v_cmp_le_f32_e64 s2, v15, v11
v_cmp_ge_f32_e64 s3, v16, v13
v_cmp_ge_f32_e64 s4, s17, v16
v_cmp_ge_f32_e64 s5, v17, v10
v_cmp_le_f32_e64 s6, v17, v12
s_and_b32 s1, s1, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_b32 s2, s3, s4
s_and_b32 s3, s5, s6
s_and_b32 s1, s1, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
s_and_b32 s1, s1, s3
s_or_b32 s9, s0, s9
v_cndmask_b32_e64 v15, 0, 1, s1
global_store_b32 v[3:4], v15, off
v_add_co_u32 v3, s1, v3, s22
v_add_co_ci_u32_e64 v4, s1, 0, v4, s1
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_4
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s23
s_add_i32 s15, s7, s15
s_add_i32 s8, s8, s21
s_cmp_ge_i32 s15, s12
s_cbranch_scc0 .LBB0_2
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| points_inside_boxes | 6,425 | 1,873 | stackv2-00000-of-00015 |
// Demangled: points_iou_kernel(int, int, int const*, float*)
Function : _Z17points_iou_kerneliiPKiPf
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
S2UR UR7, SR_CTAID.X &wr=0x1 ?trans8;
LDC R0, c[0x0][0x380] &wr=0x1 ?trans2;
ISETP.LE.AND P0, PT, R0, UR7, PT &req={1} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
S2R R4, SR_TID.X &wr=0x0 ?trans1;
S2UR UR6, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
HFMA2 R5, -RZ, RZ, 0, 0 ?trans1;
UIADD3 UR5, UPT, UPT, UR4, 0x100, URZ ?trans1;
LDCU.64 UR12, c[0x0][0x358] &wr=0x2 ?trans4;
S2UR UR8, SR_CTAID.Y &wr=0x3 ?trans8;
LDC R10, c[0x0][0x360] &wr=0x4 ?trans1;
LDCU UR9, c[0x0][0x374] &wr=0x2 ?trans1;
LDCU UR10, c[0x0][0x370] &wr=0x2 ?trans1;
ULEA UR4, UR6, UR4, 0x18 &req={1} ?trans1;
ULEA UR5, UR6, UR5, 0x18 ?WAIT3_END_GROUP;
UMOV UR6, UR7 ?trans2;
LEA R9, R4.reuse, UR4, 0x2 &req={0} ?trans2;
LEA R8, R4, UR5, 0x2 &req={3} ?WAIT7_END_GROUP;
LDCU UR4, c[0x0][0x380] &req={0} &wr=0x0 ?trans2;
MOV R15, UR4 &req={0} ?WAIT5_END_GROUP;
ISETP.LE.U32.AND P0, PT, R15, UR8, PT ?WAIT13_END_GROUP;
@P0 BRA 0xad0 &req={1} ?trans5;
LDCU UR4, c[0x0][0x384] &wr=0x0 ?trans1;
MOV R0, UR8 ?trans1;
UIMAD UR4, UR6, UR4, URZ &req={0} ?WAIT4_END_GROUP;
USHF.R.S32.HI UR5, URZ, 0x1f, UR4 ?WAIT6_END_GROUP;
IADD.64 R2, R4, UR4 ?WAIT5_END_GROUP;
SHF.L.U64.HI R7, R2.reuse, 0x2, R3 ?trans1;
IMAD.SHL.U32 R6, R2, 0x4, RZ ?WAIT7_END_GROUP;
LDCU UR7, c[0x0][0x384] &req={0} &wr=0x0 ?trans1;
STS [R9], RZ &req={1} &rd=0x1 ?trans1;
BSSY.RECONVERGENT B0, 0x490 ?trans1;
LDCU UR11, c[0x0][0x384] &wr=0x3 ?trans2;
STS [R8], RZ &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GE.AND P0, PT, R4, UR7, PT &req={0} ?WAIT13_END_GROUP;
@P0 BRA 0x480 &req={3,2,1} ?trans5;
LDS R18, [R9] &rd=0x0 &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x388] &wr=0x3 ?trans1;
IMAD R2, R0, UR7, RZ ?trans1;
BSSY.RECONVERGENT B1, 0x460 ?trans1;
LDS R11, [R8] &rd=0x0 &wr=0x4 ?trans1;
MOV R19, R4 ?trans2;
SHF.R.S32.HI R3, RZ, 0x1f, R2 ?WAIT5_END_GROUP;
IADD.64 R2, R4, R2 ?WAIT5_END_GROUP;
SHF.L.U64.HI R13, R2.reuse, 0x2, R3 ?trans1;
IMAD.SHL.U32 R12, R2, 0x4, RZ ?trans1;
MOV.64 R2, UR4 &req={3,0} ?WAIT8_END_GROUP;
IADD.64 R14, R2, R6 ?WAIT7_END_GROUP;
LDG.E R14, desc[UR12][R14.64] &req={2} &wr=0x2 ?trans1;
IADD.64 R16, R2, R12 ?trans2;
ISETP.NE.AND P0, PT, R14.reuse, RZ, PT &req={2} ?trans1;
ISETP.NE.AND P1, PT, R14, RZ, PT ?WAIT12_END_GROUP;
@P0 LDG.E R20, desc[UR12][R16.64] &wr=0x2 ?trans4;
@!P1 LDG.E R21, desc[UR12][R16.64] &wr=0x3 ?trans1;
IADD3 R19, PT, PT, R10.reuse, R19, RZ &req={4} ?trans1;
IMAD.WIDE.U32 R2, R10, 0x4, R2 ?trans1;
ISETP.NE.AND P0, PT, R20, RZ, P0 &req={2} ?trans1;
ISETP.NE.OR P1, PT, R21, RZ, P1 &req={3} ?WAIT4_END_GROUP;
SEL R20, RZ, 0x1, !P0 ?trans1;
ISETP.GE.AND P0, PT, R19, UR11, PT ?trans1;
SEL R21, RZ, 0x1, !P1 ?WAIT3_END_GROUP;
I2FP.F32.U32 R15, R20 ?trans2;
I2FP.F32.U32 R14, R21 ?WAIT3_END_GROUP;
FADD R18, R15, R18 &req={1} ?trans2;
FADD R11, R14, R11 ?trans2;
@!P0 BRA 0x320 ?trans5;
BSYNC.RECONVERGENT B1 ?trans5;
STS [R9], R18 &rd=0x0 ?trans4;
STS [R8], R11 &rd=0x0 ?trans2;
BSYNC.RECONVERGENT B0 &req={2} ?trans5;
S2UR UR7, SR_CgaCtaId &wr=0x1 ?trans8;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
UMOV UR5, 0x400 ?trans1;
BSSY.RECONVERGENT B0, 0x5b0 ?trans1;
UIADD3 UR4, UPT, UPT, UR5, 0x200, URZ ?trans1;
ULEA UR11, UR7, UR5, 0x18 &req={1} ?trans1;
UIADD3 UR5, UPT, UPT, UR5, 0x204, URZ ?WAIT2_END_GROUP;
ULEA UR4, UR7, UR4, 0x18 ?trans2;
ULEA UR5, UR7, UR5, 0x18 ?WAIT4_END_GROUP;
STS.64 [UR11+0x200], RZ ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R3, [R9] &rd=0x1 &wr=0x2 ?trans2;
LDS R12, [UR4] &wr=0x3 ?trans1;
MOV R2, UR4 ?trans1;
FADD R13, R3, R12 &req={3,2} ?WAIT5_END_GROUP;
ATOMS.CAST.SPIN P0, [R2], R12, R13 &wr=0x2 ?trans2;
@!P0 BRA 0x550 &req={2} ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
LDS R3, [R8] &rd=0x2 &wr=0x3 ?trans1;
BSSY.RECONVERGENT B0, 0x630 ?trans1;
LDS R12, [UR5] &wr=0x5 ?trans1;
MOV R2, UR5 ?trans1;
FADD R13, R3, R12 &req={5,3} ?WAIT5_END_GROUP;
ATOMS.CAST.SPIN P0, [R2], R12, R13 &wr=0x3 ?trans2;
@!P0 BRA 0x5d0 &req={3} ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
MOV R14, 0x80000 ?WAIT5_END_GROUP;
LDS.64 R16, [UR11+0x200] &wr=0x3 ?trans2;
F2F.F64.F32 R2, R17 &req={3} &wr=0x3 ?trans2;
MOV R11, R3 &req={3,0} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DSETP.MAX.AND P0, P1, R2, 1, PT &wr=0x0 ?trans2;
SEL R12, R2, RZ, P0 &req={0} ?trans1;
HFMA2 R2, -RZ, RZ, 0, 5.9604644775390625e-08 ?trans1;
FSEL R13, R11, 1.875, P0 ?trans1;
@P1 LOP3.LUT R13, R14, 0x3ff00000, RZ, 0xfc, !PT ?WAIT4_END_GROUP;
MUFU.RCP64H R3, R13 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT10_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2F.F64.F32 R16, R16 &wr=0x3 ?trans2;
FSETP.GEU.AND P1, PT, |R17|, 6.5827683646048100446e-37, PT &req={3} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R14, -R12, R2, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R14, R14, R14, R14 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R14, R2, R14, R2 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, -R12, R14, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R14, R2, R14 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R14, R16, R2 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, -R12, R14, R16 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R2, R18, R14 &req={0} &wr=0x0 ?trans2;
FFMA R11, RZ, R13, R3 &req={0} ?WAIT5_END_GROUP;
FSETP.GT.AND P0, PT, |R11|, 1.469367938527859385e-39, PT ?WAIT13_END_GROUP;
@P0 BRA P1, 0xa40 ?trans5;
MOV R20, 0xa40 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0xb10 &req={4,2,1} ?trans5;
LDC R15, c[0x0][0x380] &wr=0x0 ?trans1;
F2F.F32.F64 R3, R2 &wr=0x3 ?trans7;
LDC.64 R12, c[0x0][0x390] &wr=0x5 ?trans1;
IMAD R11, R15, UR6, R0 &req={0} ?trans1;
IADD3 R0, PT, PT, R0, UR9, RZ ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, R15, PT ?trans1;
IMAD.WIDE R12, R11, 0x4, R12 &req={5} ?WAIT5_END_GROUP;
STG.E desc[UR12][R12.64], R3 &req={3} &rd=0x0 ?trans7;
@!P0 BRA 0x1f0 ?trans5;
UIADD3 UR6, UPT, UPT, UR10, UR6, URZ &req={2} ?WAIT6_END_GROUP;
ISETP.LE.AND P0, PT, R15, UR6, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x140 ?trans5;
EXIT ?trans5;
FSETP.GEU.AND P0, PT, |R13|.reuse, 1.469367938527859385e-39, PT ?trans1;
LOP3.LUT R2, R13.reuse, 0x800fffff, RZ, 0xc0, !PT ?trans1;
MOV R14, 0x1 ?trans1;
LOP3.LUT R26, R13, 0x7ff00000, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R3, R2, 0x3ff00000, RZ, 0xfc, !PT ?trans1;
MOV R2, R12 ?trans1;
LOP3.LUT R21, R17, 0x7ff00000, RZ, 0xc0, !PT ?trans1;
MOV R11, 0x1ca00000 ?WAIT5_END_GROUP;
@!P0 DMUL R2, R12, 8.98846567431157953865e+307 &wr=0x0 ?trans1;
ISETP.GE.U32.AND P1, PT, R21, R26, PT ?trans1;
MUFU.RCP64H R15, R3 &req={0} &wr=0x0 ?trans1;
MOV R27, R21 ?WAIT15_END_GROUP;
NOP ?trans1;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R14, -R2, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R18, R18, R18 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R14, R14, R18, R14 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R14, -R2, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R14, R14, R18, R14 &req={0} &rd=0x0 &wr=0x1 ?trans2;
SEL R19, R11, 0x63400000, !P1 &req={0} ?trans1;
FSETP.GEU.AND P1, PT, |R17|, 1.469367938527859385e-39, PT ?trans1;
MOV R18, R16 ?WAIT3_END_GROUP;
LOP3.LUT R19, R19, 0x800fffff, R17, 0xf8, !PT ?WAIT9_END_GROUP;
@P1 BRA 0xe30 &req={1} ?trans5;
LOP3.LUT R22, R13, 0x7ff00000, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P1, PT, R21, R22, PT ?trans1;
MOV R22, RZ ?WAIT4_END_GROUP;
SEL R23, R11, 0x63400000, !P1 ?WAIT5_END_GROUP;
LOP3.LUT R23, R23, 0x80000000, R17, 0xf8, !PT ?WAIT4_END_GROUP;
LOP3.LUT R23, R23, 0x100000, RZ, 0xfc, !PT ?WAIT6_END_GROUP;
DFMA R18, R18, 2, -R22 &wr=0x0 ?trans2;
LOP3.LUT R27, R19, 0x7ff00000, RZ, 0xc0, !PT &req={0} ?WAIT7_END_GROUP;
@!P0 LOP3.LUT R26, R3, 0x7ff00000, RZ, 0xc0, !PT ?trans1;
DMUL R22, R14, R18 &wr=0x0 ?trans1;
IADD3 R28, PT, PT, R27, -0x1, RZ ?trans2;
IADD3 R29, PT, PT, R26, -0x1, RZ ?WAIT3_END_GROUP;
ISETP.GT.U32.AND P0, PT, R28, 0x7feffffe, PT ?WAIT5_END_GROUP;
ISETP.GT.U32.OR P0, PT, R29, 0x7feffffe, P0 ?WAIT15_END_GROUP;
NOP ?WAIT8_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R24, R22, -R2, R18 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R14, R14, R24, R22 &req={0} &rd=0x0 &wr=0x1 ?trans2;
@P0 BRA 0x1130 &req={1,0} ?trans5;
LOP3.LUT R22, R13, 0x7ff00000, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R16, PT, PT, R21.reuse, -R22.reuse, RZ ?trans1;
ISETP.GE.U32.AND P0, PT, R21, R22, PT ?WAIT4_END_GROUP;
VIMNMX.S32 R16, R16, -0x46a00000, !PT ?trans1;
SEL R11, R11, 0x63400000, !P0 ?WAIT4_END_GROUP;
VIMNMX.S32 R16, R16, 0x46a00000, PT ?WAIT5_END_GROUP;
IADD3 R11, PT, PT, -R11, R16, RZ ?trans1;
MOV R16, RZ ?WAIT3_END_GROUP;
IADD3 R17, PT, PT, R11, 0x7fe00000, RZ ?WAIT6_END_GROUP;
DMUL R22, R14, R16 &wr=0x0 ?trans2;
FSETP.GTU.AND P0, PT, |R23|, 1.469367938527859385e-39, PT &req={0} ?WAIT13_END_GROUP;
@P0 BRA 0x1270 ?trans5;
DFMA R2, R14, -R2, R18 &wr=0x0 ?trans1;
MOV R16, RZ ?trans1;
FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT &req={0} ?trans1;
LOP3.LUT R13, R3, 0x80000000, R13, 0x48, !PT ?WAIT4_END_GROUP;
LOP3.LUT R17, R13, R17, RZ, 0xfc, !PT ?WAIT8_END_GROUP;
@!P0 BRA 0x1270 ?trans5;
IADD3 R3, PT, PT, -R11.reuse, RZ, RZ ?trans1;
MOV R2, RZ ?trans1;
IADD3 R11, PT, PT, -R11, -0x43300000, RZ ?WAIT5_END_GROUP;
DFMA R2, R22, -R2, R14 &wr=0x0 ?trans2;
FSETP.NEU.AND P0, PT, |R3|, R11, PT &req={0} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL.RP R14, R14, R16 &wr=0x0 ?trans2;
LOP3.LUT R13, R15, R13, RZ, 0x3c, !PT &req={0} ?trans1;
FSEL R22, R14, R22, !P0 ?WAIT4_END_GROUP;
FSEL R23, R13, R23, !P0 ?trans1;
BRA 0x1270 ?trans6;
DSETP.NAN.AND P0, PT, R16, R16, PT &wr=0x0 ?trans2;
@P0 BRA 0x1250 &req={0} ?trans5;
DSETP.NAN.AND P0, PT, R12, R12, PT &wr=0x0 ?trans2;
@P0 BRA 0x1220 &req={0} ?trans5;
ISETP.NE.AND P0, PT, R27, R26, PT ?trans1;
MOV.64 R22, 0xfff8000000000000 ?WAIT12_END_GROUP;
@!P0 BRA 0x1270 ?trans5;
ISETP.NE.AND P0, PT, R27, 0x7ff00000, PT ?trans1;
LOP3.LUT R23, R17, 0x80000000, R13, 0x48, !PT ?WAIT4_END_GROUP;
ISETP.EQ.OR P0, PT, R26, RZ, !P0 ?WAIT13_END_GROUP;
@P0 LOP3.LUT R2, R23, 0x7ff00000, RZ, 0xfc, !PT ?trans1;
@!P0 MOV R22, RZ ?trans1;
@P0 MOV R22, RZ ?WAIT3_END_GROUP;
@P0 MOV R23, R2 ?trans1;
BRA 0x1270 ?trans6;
LOP3.LUT R23, R13, 0x80000, RZ, 0xfc, !PT ?trans1;
MOV R22, R12 ?trans1;
BRA 0x1270 ?trans6;
LOP3.LUT R23, R17, 0x80000, RZ, 0xfc, !PT ?trans1;
MOV R22, R16 ?WAIT7_END_GROUP;
MOV R21, 0x0 ?trans1;
MOV R2, R22 ?trans1;
MOV R3, R23 ?trans2;
RET.REL.NODEC R20 0x0 ?trans5;
BRA 0x12b0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: points_iou_kernel(int, int, int const*, float*)
_Z17points_iou_kerneliiPKiPf:
s_load_b64 s[8:9], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s14, s8
s_cbranch_scc1 .LBB1_22
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b32 s3, s[0:1], 0x18
v_lshlrev_b32_e32 v7, 2, v0
s_cmp_lt_i32 s15, s8
v_cmp_gt_i32_e64 s2, s9, v0
s_cselect_b32 s20, -1, 0
s_add_u32 s10, s0, 24
v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v8, 0x100, v7
s_addc_u32 s11, s1, 0
s_mul_i32 s21, s15, s9
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, s0, s4, v7
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, null, s5, 0, s0
s_mul_i32 s4, s14, s9
s_mul_i32 s1, s3, s9
.LBB1_2:
s_and_not1_b32 vcc_lo, exec_lo, s20
s_cbranch_vccnz .LBB1_21
s_clause 0x1
s_load_b32 s0, s[10:11], 0xc
s_load_b32 s22, s[10:11], 0x4
s_ashr_i32 s5, s4, 31
s_mul_i32 s23, s14, s8
s_lshl_b64 s[16:17], s[4:5], 2
s_mov_b32 s12, s21
s_mov_b32 s26, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s0, 0xffff
s_mul_i32 s24, s9, s22
s_lshl_b32 s25, s5, 2
.LBB1_4:
ds_store_b32 v8, v1
ds_store_b32 v7, v1
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s27, s2
s_cbranch_execz .LBB1_12
ds_load_b32 v9, v8
ds_load_b32 v2, v7
v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
v_mov_b32_e32 v10, v0
s_ashr_i32 s13, s12, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[18:19], s[12:13], 2
s_mov_b32 s13, 0
.LBB1_6:
v_add_co_u32 v11, vcc_lo, v5, s16
v_add_co_ci_u32_e32 v12, vcc_lo, s17, v6, vcc_lo
s_mov_b32 s28, 0
s_mov_b32 s29, exec_lo
global_load_b32 v11, v[11:12], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 0, v11
v_cmpx_ne_u32_e32 0, v11
s_cbranch_execz .LBB1_8
v_add_co_u32 v11, s0, v5, s18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v12, s0, s19, v6, s0
global_load_b32 v11, v[11:12], off
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e64 s0, 0, v11
s_and_b32 s28, s0, exec_lo
.LBB1_8:
s_or_b32 exec_lo, exec_lo, s29
s_mov_b32 s29, -1
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB1_10
v_add_co_u32 v11, vcc_lo, v5, s18
v_add_co_ci_u32_e32 v12, vcc_lo, s19, v6, vcc_lo
global_load_b32 v11, v[11:12], off
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 0, v11
s_or_not1_b32 s29, vcc_lo, exec_lo
.LBB1_10:
s_or_b32 exec_lo, exec_lo, s0
v_cndmask_b32_e64 v11, 0, 1.0, s28
v_add_nc_u32_e32 v10, s5, v10
v_cndmask_b32_e64 v12, 0, 1.0, s29
v_add_co_u32 v5, s0, v5, s25
s_waitcnt lgkmcnt(1)
v_add_f32_e32 v9, v9, v11
v_cmp_le_i32_e32 vcc_lo, s9, v10
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v12
v_add_co_ci_u32_e64 v6, s0, 0, v6, s0
s_or_b32 s13, vcc_lo, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execnz .LBB1_6
s_or_b32 exec_lo, exec_lo, s13
ds_store_b32 v8, v9
ds_store_b32 v7, v2
.LBB1_12:
s_or_b32 exec_lo, exec_lo, s27
v_mov_b32_e32 v2, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s0, exec_lo
ds_store_b64 v1, v[1:2] offset:512
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v5, v8
v_bfrev_b32_e32 v2, 1
.LBB1_13:
s_ctz_i32_b32 s13, s0
s_waitcnt lgkmcnt(0)
v_readlane_b32 s18, v5, s13
s_lshl_b32 s13, 1, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s0, s0, s13
s_cmp_lg_u32 s0, 0
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v2, s18, v2
s_cbranch_scc1 .LBB1_13
v_mbcnt_lo_u32_b32 v5, exec_lo, 0
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v5
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB1_16
ds_add_f32 v1, v2 offset:512
.LBB1_16:
s_or_b32 exec_lo, exec_lo, s0
ds_load_b32 v5, v7
v_bfrev_b32_e32 v2, 1
s_mov_b32 s0, exec_lo
.LBB1_17:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_ctz_i32_b32 s13, s0
s_waitcnt lgkmcnt(0)
v_readlane_b32 s18, v5, s13
s_lshl_b32 s13, 1, s13
s_and_not1_b32 s0, s0, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s0, 0
v_add_f32_e32 v2, s18, v2
s_cbranch_scc1 .LBB1_17
v_mbcnt_lo_u32_b32 v5, exec_lo, 0
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v5
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB1_20
ds_add_f32 v1, v2 offset:516
.LBB1_20:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b64 v[5:6], v1 offset:512
s_add_i32 s18, s26, s23
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s19, s18, 31
s_lshl_b64 s[18:19], s[18:19], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s18, s6, s18
s_addc_u32 s19, s7, s19
s_add_i32 s26, s22, s26
s_add_i32 s12, s12, s24
s_cmp_ge_i32 s26, s8
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[9:10], v6
v_cvt_f64_f32_e32 v[5:6], v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_f64 v[9:10], v[9:10], 1.0
v_div_scale_f64 v[11:12], null, v[9:10], v[9:10], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[13:14], v[11:12]
s_waitcnt_depctr 0xfff
v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
v_div_scale_f64 v[15:16], vcc_lo, v[5:6], v[9:10], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[17:18], v[15:16], v[13:14]
v_fma_f64 v[11:12], -v[11:12], v[17:18], v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[11:12], v[11:12], v[13:14], v[17:18]
v_div_fixup_f64 v[5:6], v[11:12], v[9:10], v[5:6]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v2, v[5:6]
global_store_b32 v1, v2, s[18:19]
s_cbranch_scc0 .LBB1_4
.LBB1_21:
s_add_i32 s14, s3, s14
s_add_i32 s4, s4, s1
s_cmp_ge_i32 s14, s8
s_cbranch_scc0 .LBB1_2
.LBB1_22:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| points_iou_kernel | 6,499 | 3,424 | stackv2-00000-of-00015 |
// Demangled: points_nms_kernel(int, int, int, float, float const*, int const*, int*, int*)
Function : _Z17points_nms_kerneliiifPKfPKiPiS3_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
S2UR UR6, SR_CTAID.X &wr=0x1 ?trans8;
LDC R0, c[0x0][0x380] &wr=0x1 ?trans2;
ISETP.LE.AND P0, PT, R0, UR6, PT &req={1} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
S2R R0, SR_TID.X &wr=0x0 ?trans1;
S2UR UR9, SR_CTAID.Y &wr=0x1 ?trans1;
LDCU.64 UR12, c[0x0][0x358] &wr=0x2 ?trans7;
LDC R4, c[0x0][0x360] &wr=0x3 ?trans1;
LDCU UR10, c[0x0][0x374] &wr=0x4 ?trans2;
LDCU UR4, c[0x0][0x380] &wr=0x5 ?trans2;
MOV R12, UR4 &req={5} ?WAIT5_END_GROUP;
ISETP.LE.U32.AND P0, PT, R12, UR9, PT &req={1} ?WAIT13_END_GROUP;
@P0 BRA 0x890 &req={3,2,0} ?trans5;
LDC R6, c[0x0][0x388] &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x384] &wr=0x5 ?trans1;
IMAD R2, R12, UR6, RZ ?trans1;
MOV R5, UR9 ?WAIT4_END_GROUP;
SHF.R.S32.HI R3, RZ, 0x1f, R2 ?trans1;
UIMAD UR7, UR6, UR4, URZ &req={5} ?WAIT4_END_GROUP;
USHF.R.S32.HI UR8, URZ, 0x1f, UR7 ?trans1;
ISETP.NE.AND P0, PT, R6, RZ, PT &req={1} ?WAIT13_END_GROUP;
@!P0 BRA 0x5b0 ?trans5;
LDC R12, c[0x0][0x380] &wr=0x1 ?trans1;
ISETP.NE.AND P0, PT, R6, 0x1, PT ?trans1;
LDCU.64 UR4, c[0x0][0x390] &wr=0x4 ?trans1;
MOV R5, UR9 ?trans1;
LDCU UR11, c[0x0][0x38c] &wr=0x3 ?trans10;
@P0 BRA 0x490 ?trans5;
LDCU.64 UR4, c[0x0][0x3a8] &req={4} &wr=0x4 ?trans1;
MOV R5, UR9 ?trans1;
ULEA UR4, UP0, UR7, UR4, 0x2 &req={4} ?WAIT4_END_GROUP;
ULEA.HI.X UR5, UR7, UR5, UR8, 0x2, UP0 ?WAIT12_END_GROUP;
ISETP.NE.AND P0, PT, R5, UR6, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x440 &req={2,0} ?trans5;
LDCU.64 UR14, c[0x0][0x390] &wr=0x4 ?trans1;
SHF.R.S32.HI R7, RZ, 0x1f, R5 ?trans1;
MOV R6, R5 ?trans1;
LDCU UR7, c[0x0][0x38c] &wr=0x5 ?trans4;
IADD.64 R6, R2, R6 ?WAIT5_END_GROUP;
SHF.L.U64.HI R9, R6.reuse, 0x2, R7 ?trans1;
IMAD.SHL.U32 R8, R6, 0x4, RZ ?WAIT5_END_GROUP;
IADD.64 R6, R8, UR14 &req={4} ?WAIT7_END_GROUP;
LDG.E R6, desc[UR12][R6.64] &req={2} &wr=0x5 ?trans2;
FSETP.GT.AND P0, PT, R6, UR7, PT &req={5} ?WAIT13_END_GROUP;
@!P0 BRA 0x440 ?trans5;
LDCU.64 UR14, c[0x0][0x3a0] &wr=0x2 ?trans1;
BSSY.RECONVERGENT B0, 0x440 ?trans1;
LDCU UR7, c[0x0][0x384] &wr=0x4 ?trans1;
IADD.64 R6, R8, UR14 &req={2} ?trans2;
HFMA2 R9, -RZ, RZ, 0, 5.9604644775390625e-08 ?trans1;
ISETP.GE.AND P0, PT, R0, UR7, PT &req={4,0} ?WAIT4_END_GROUP;
STG.E desc[UR12][R6.64], R9 &rd=0x0 ?trans9;
@P0 BRA 0x430 ?trans5;
LDC.64 R8, c[0x0][0x398] &req={0} &wr=0x0 ?trans1;
IMAD R13, R5, UR7, RZ ?trans1;
MOV R15, R0 ?trans1;
IMAD.WIDE.U32 R6, R0, 0x4, RZ ?WAIT4_END_GROUP;
IMAD.WIDE R12, R13, 0x4, R8 &req={1,0} ?WAIT7_END_GROUP;
IADD.64 R10, R12, R6 &req={2} ?WAIT7_END_GROUP;
LDG.E R11, desc[UR12][R10.64] &wr=0x2 ?trans1;
IADD3 R15, PT, PT, R4, R15, RZ &req={3} ?trans1;
IADD.64 R8, R6, UR4 ?WAIT4_END_GROUP;
ISETP.GE.AND P0, PT, R15, UR7, PT ?trans1;
IMAD.WIDE.U32 R6, R4, 0x4, R6 ?trans1;
REDG.E.AND.STRONG.GPU desc[UR12][R8.64], R11 &req={2} &rd=0x2 ?trans11;
@!P0 BRA 0x3b0 ?trans5;
BSYNC.RECONVERGENT B0 &req={3} ?trans5;
LDC R12, c[0x0][0x380] &req={1} &wr=0x1 ?trans1;
IADD3 R5, PT, PT, R5, UR10, RZ ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R5, R12, PT &req={1} ?WAIT13_END_GROUP;
@!P0 BRA 0x210 ?trans5;
BRA 0x890 ?trans5;
ISETP.NE.AND P0, PT, R5, UR6, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x570 &req={2} ?trans5;
SHF.R.S32.HI R7, RZ, 0x1f, R5 ?trans1;
MOV R6, R5 ?WAIT5_END_GROUP;
IADD.64 R6, R2, R6 ?WAIT5_END_GROUP;
SHF.L.U64.HI R9, R6.reuse, 0x2, R7 ?trans1;
IMAD.SHL.U32 R8, R6, 0x4, RZ ?WAIT5_END_GROUP;
IADD.64 R6, R8, UR4 &req={4} ?WAIT7_END_GROUP;
LDG.E R6, desc[UR12][R6.64] &req={2} &wr=0x2 ?trans2;
FSETP.GT.AND P0, PT, R6, UR11, PT &req={3,2} ?WAIT13_END_GROUP;
@P0 LDC.64 R10, c[0x0][0x3a0] &wr=0x2 ?trans2;
@P0 IADD.64 R8, R8, R10 &req={2} ?trans2;
@P0 MOV R11, 0x1 ?WAIT5_END_GROUP;
@P0 STG.E desc[UR12][R8.64], R11 &rd=0x2 ?trans2;
IADD3 R5, PT, PT, R5, UR10, RZ &req={4} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R5, R12, PT &req={1} ?WAIT13_END_GROUP;
@!P0 BRA 0x490 ?trans5;
BRA 0x890 ?trans5;
ISETP.NE.AND P0, PT, R5, UR6, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x850 &req={1,0} ?trans5;
LDCU.64 UR4, c[0x0][0x390] &wr=0x1 ?trans1;
SHF.R.S32.HI R7, RZ, 0x1f, R5 ?trans1;
MOV R6, R5 ?WAIT5_END_GROUP;
IADD.64 R6, R2, R6 ?WAIT5_END_GROUP;
SHF.L.U64.HI R9, R6.reuse, 0x2, R7 ?trans1;
IMAD.SHL.U32 R8, R6, 0x4, RZ ?WAIT5_END_GROUP;
IADD.64 R6, R8, UR4 &req={1} ?trans2;
LDCU UR4, c[0x0][0x38c] &wr=0x1 ?trans5;
LDG.E R6, desc[UR12][R6.64] &req={2} &wr=0x1 ?trans2;
FSETP.GT.AND P0, PT, R6, UR4, PT &req={1} ?WAIT13_END_GROUP;
@!P0 BRA 0x850 ?trans5;
LDCU.64 UR4, c[0x0][0x3a0] &wr=0x1 ?trans1;
BSSY.RECONVERGENT B0, 0x850 ?trans1;
LDCU UR11, c[0x0][0x384] &wr=0x2 ?trans1;
LDCU.64 UR16, c[0x0][0x3a8] &wr=0x4 ?trans1;
LDCU.64 UR14, c[0x0][0x398] &wr=0x3 ?trans1;
IADD.64 R6, R8, UR4 &req={1} ?trans2;
HFMA2 R9, -RZ, RZ, 0, 5.9604644775390625e-08 ?trans1;
ISETP.GE.AND P0, PT, R0, UR11, PT &req={2,0} ?WAIT4_END_GROUP;
STG.E desc[UR12][R6.64], R9 &rd=0x0 ?trans9;
@P0 BRA 0x840 &req={4,3} ?trans5;
IMAD R12, R5, UR11, RZ ?trans1;
MOV R15, R0 ?WAIT4_END_GROUP;
SHF.R.S32.HI R13, RZ, 0x1f, R12 ?WAIT7_END_GROUP;
MOV R6, R15 &req={0} ?trans1;
HFMA2 R7, -RZ, RZ, 0, 0 ?WAIT5_END_GROUP;
IADD.64 R10, R12, R6 &req={1} ?WAIT5_END_GROUP;
LEA R8, P0, R10, UR14, 0x2 ?WAIT4_END_GROUP;
LEA.HI.X R9, R10, UR15, R11, 0x2, P0 ?WAIT6_END_GROUP;
LDG.E R9, desc[UR12][R8.64] &wr=0x2 ?trans1;
UMOV UR4, UR7 ?trans1;
UMOV UR5, UR8 ?trans2;
IADD.64 R6, R6, UR4 ?WAIT3_END_GROUP;
IADD3 R15, PT, PT, R4, R15, RZ ?trans2;
LEA R10, P0, R6, UR16, 0x2 ?WAIT4_END_GROUP;
LEA.HI.X R11, R6, UR17, R7, 0x2, P0 ?trans1;
ISETP.GE.AND P0, PT, R15, UR11, PT ?WAIT4_END_GROUP;
REDG.E.OR.STRONG.GPU desc[UR12][R10.64], R9 &req={2} &rd=0x1 ?trans9;
@!P0 BRA 0x750 ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
LDC R12, c[0x0][0x380] &wr=0x5 ?trans1;
IADD3 R5, PT, PT, R5, UR10, RZ &req={4} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R5, R12, PT &req={5} ?WAIT13_END_GROUP;
@!P0 BRA 0x5b0 ?trans5;
LDCU UR4, c[0x0][0x370] &wr=0x5 ?trans2;
UIADD3 UR6, UPT, UPT, UR4, UR6, URZ &req={5} ?WAIT6_END_GROUP;
ISETP.LE.AND P0, PT, R12, UR6, PT ?WAIT13_END_GROUP;
@!P0 BRA 0xa0 ?trans5;
EXIT &req={4,3,2} ?trans5;
BRA 0x8e0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: points_nms_kernel(int, int, int, float, float const*, int const*, int*, int*)
_Z17points_nms_kerneliiifPKfPKiPiS3_:
s_load_b128 s[16:19], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s14, s16
s_cbranch_scc1 .LBB3_19
s_clause 0x1
s_load_b32 s26, s[0:1], 0x30
s_load_b256 s[4:11], s[0:1], 0x10
s_cmp_lt_i32 s15, s16
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v0
s_cselect_b32 s27, -1, 0
s_add_u32 s2, s0, 48
v_cmp_gt_i32_e64 s0, s17, v0
v_mov_b32_e32 v5, 1
s_addc_u32 s3, s1, 0
s_mul_i32 s28, s15, s17
s_mul_i32 s12, s14, s17
s_waitcnt lgkmcnt(0)
s_mul_i32 s29, s26, s17
.LBB3_2:
s_and_not1_b32 vcc_lo, exec_lo, s27
s_cbranch_vccnz .LBB3_18
s_load_b32 s30, s[2:3], 0x4
s_ashr_i32 s13, s12, 31
s_mul_i32 s22, s14, s16
s_lshl_b64 s[20:21], s[12:13], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_add_u32 s13, s10, s20
s_addc_u32 s31, s11, s21
s_ashr_i32 s23, s22, 31
s_mov_b32 s20, s28
s_lshl_b64 s[22:23], s[22:23], 2
s_add_u32 s33, s4, s22
s_addc_u32 s34, s5, s23
s_add_u32 s35, s8, s22
s_addc_u32 s36, s9, s23
s_mov_b32 s22, s15
s_waitcnt lgkmcnt(0)
s_mul_i32 s37, s17, s30
.LBB3_4:
s_cmp_eq_u32 s14, s22
s_cbranch_scc1 .LBB3_17
s_ashr_i32 s23, s22, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[24:25], s[22:23], 2
s_add_u32 s38, s33, s24
s_addc_u32 s39, s34, s25
global_load_b32 v3, v2, s[38:39]
s_waitcnt vmcnt(0)
v_cmp_nlt_f32_e32 vcc_lo, s19, v3
s_cbranch_vccnz .LBB3_17
s_add_u32 s24, s35, s24
s_addc_u32 s25, s36, s25
global_store_b32 v2, v5, s[24:25]
s_and_saveexec_b32 s23, s0
s_cbranch_execz .LBB3_16
s_load_b32 s1, s[2:3], 0xc
s_ashr_i32 s21, s20, 31
v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
v_mov_b32_e32 v6, v0
s_lshl_b64 s[24:25], s[20:21], 2
s_mov_b32 s39, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s21, s1, 0xffff
s_add_u32 s24, s6, s24
s_addc_u32 s25, s7, s25
s_lshl_b32 s38, s21, 2
.LBB3_8:
s_cmp_lt_i32 s18, 1
s_mov_b32 s1, -1
s_cbranch_scc1 .LBB3_12
s_cmp_eq_u32 s18, 1
s_cbranch_scc0 .LBB3_11
v_add_co_u32 v7, vcc_lo, s24, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s25, v4, vcc_lo
global_load_b32 v9, v[7:8], off
v_add_co_u32 v7, vcc_lo, s13, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s31, v4, vcc_lo
s_waitcnt vmcnt(0)
global_atomic_and_b32 v[7:8], v9, off
.LBB3_11:
s_mov_b32 s1, 0
.LBB3_12:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB3_15
s_cmp_lg_u32 s18, 0
s_cbranch_scc1 .LBB3_15
v_add_co_u32 v7, vcc_lo, s24, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s25, v4, vcc_lo
global_load_b32 v9, v[7:8], off
v_add_co_u32 v7, vcc_lo, s13, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s31, v4, vcc_lo
s_waitcnt vmcnt(0)
global_atomic_or_b32 v[7:8], v9, off
.LBB3_15:
v_add_nc_u32_e32 v6, s21, v6
v_add_co_u32 v3, s1, v3, s38
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v4, s1, 0, v4, s1
v_cmp_le_i32_e32 vcc_lo, s17, v6
s_or_b32 s39, vcc_lo, s39
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s39
s_cbranch_execnz .LBB3_8
.LBB3_16:
s_or_b32 exec_lo, exec_lo, s23
.LBB3_17:
s_add_i32 s22, s30, s22
s_add_i32 s20, s20, s37
s_cmp_ge_i32 s22, s16
s_cbranch_scc0 .LBB3_4
.LBB3_18:
s_add_i32 s14, s26, s14
s_add_i32 s12, s12, s29
s_cmp_ge_i32 s14, s16
s_cbranch_scc0 .LBB3_2
.LBB3_19:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| points_nms_kernel | 3,563 | 1,972 | stackv2-00000-of-00015 |
// Demangled: points_nms_sample(int, int, int, int*, int*)
Function : _Z17points_nms_sampleiiiPiS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
S2UR UR6, SR_CTAID.X &wr=0x1 ?trans8;
LDC R0, c[0x0][0x380] &wr=0x1 ?trans2;
ISETP.LE.AND P0, PT, R0, UR6, PT &req={1} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC R5, c[0x0][0x384] &wr=0x0 ?trans2;
ISETP.GE.AND P0, PT, R5, 0x1, PT &req={0} ?WAIT13_END_GROUP;
@!P0 EXIT ?trans5;
LDCU UR11, c[0x0][0x388] &wr=0x0 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans1;
IMAD R0, R0, R5, RZ ?trans1;
LDCU UR7, c[0x0][0x360] &wr=0x2 ?trans1;
LDCU UR10, c[0x0][0x370] &wr=0x3 ?trans1;
LDCU.64 UR8, c[0x0][0x358] &wr=0x4 ?trans1;
UIADD3 UR4, UPT, UPT, UR11, -0x1, URZ &req={0} ?WAIT4_END_GROUP;
UVIMNMX.U32 UR4, UR4, 0x2, UPT ?WAIT4_END_GROUP;
USHF.L.U32 UR4, UR4, 0x2, URZ ?WAIT12_END_GROUP;
LDCU UR4, c[0x2][UR4] &wr=0x0 ?trans2;
USHF.R.S32.HI UR5, URZ, 0x1f, UR4 &req={0} ?WAIT10_END_GROUP;
BRXU UR4 -0x140 &req={4,3,2,1} ?trans5;
ISETP.NE.AND P0, PT, RZ, UR11, PT ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LOP3.LUT R12, R5.reuse, 0x7ffffff8, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R2, R5, 0x7, RZ, 0xc0, !PT ?trans2;
IADD3 R12, PT, PT, -R12, RZ, RZ ?WAIT7_END_GROUP;
LDC.64 R8, c[0x0][0x380] &req={0} &wr=0x0 ?trans1;
IMAD R4, R0, UR6, RZ ?trans1;
BSSY.RECONVERGENT B0, 0xc60 ?trans4;
SHF.R.S32.HI R5, RZ, 0x1f, R4 ?trans1;
ISETP.GE.U32.AND P1, PT, R3, R8, PT &req={0} ?trans1;
IMAD R6, R9, UR6, RZ ?trans1;
UIADD3 UR6, UPT, UPT, UR10, UR6, URZ ?WAIT6_END_GROUP;
ISETP.LE.AND P0, PT, R8, UR6, PT ?WAIT5_END_GROUP;
@P1 BRA 0xc50 &req={2,1} ?trans8;
LDC.64 R8, c[0x0][0x398] &wr=0x0 ?trans1;
SHF.R.S32.HI R7, RZ, 0x1f, R6 ?trans1;
MOV R13, R3 ?trans1;
LEA R8, P1, R6, R8, 0x2 &req={0} ?WAIT4_END_GROUP;
LEA.HI.X R9, R6, R9, R7, 0x2, P1 ?WAIT5_END_GROUP;
IADD.64 R8, R8, 0x10 ?WAIT8_END_GROUP;
LDC.64 R10, c[0x0][0x380] &req={2,0} &wr=0x0 ?trans1;
ISETP.NE.AND P3, PT, R2, RZ, PT ?trans1;
ISETP.GE.U32.AND P2, PT, R11, 0x8, PT &req={0} ?trans1;
IMAD R14, R13.reuse, R11, RZ ?trans1;
IADD3 R13, PT, PT, R13, UR7, RZ ?WAIT5_END_GROUP;
ISETP.GE.AND P1, PT, R13, R10, PT ?trans1;
HFMA2 R10, -RZ, RZ, 0, 0 ?WAIT5_END_GROUP;
@!P2 BRA 0x630 &req={1} ?trans7;
LDCU.64 UR4, c[0x0][0x390] &wr=0x0 ?trans1;
MOV R15, RZ ?trans1;
MOV R10, RZ ?WAIT4_END_GROUP;
IADD.64 R16, R4, R14 ?trans2;
MOV R15, R12 ?WAIT3_END_GROUP;
LEA R18, P2, R16, UR4, 0x2 &req={0} ?WAIT4_END_GROUP;
LEA.HI.X R19, R16, UR5, R17, 0x2, P2 ?trans1;
MOV.64 R16, R8 ?WAIT4_END_GROUP;
IADD.64 R18, R18, 0x10 ?WAIT8_END_GROUP;
LDG.E R20, desc[UR8][R18.64+-0x10] &wr=0x2 ?trans1;
VOTEU.ANY UR4, UPT, PT ?trans2;
UFLO.U32 UR4, UR4 ?trans1;
S2R R21, SR_LANEID &wr=0x0 ?trans5;
ISETP.EQ.U32.AND P2, PT, R21, UR4, PT &req={0} ?trans1;
REDUX.OR UR5, R20 &req={2} &wr=0x0 ?trans2;
MOV R23, UR5 &req={0} ?WAIT10_END_GROUP;
@P2 REDG.E.OR.STRONG.GPU desc[UR8][R16.64+-0x10], R23 &rd=0x0 ?trans4;
LDG.E R21, desc[UR8][R18.64+-0xc] &wr=0x2 ?trans2;
REDUX.OR UR4, R21 &req={2} &wr=0x1 ?trans2;
MOV R25, UR4 &req={1} ?WAIT5_END_GROUP;
@P2 REDG.E.OR.STRONG.GPU desc[UR8][R16.64+-0xc], R25 &rd=0x1 ?trans4;
LDG.E R22, desc[UR8][R18.64+-0x8] &wr=0x2 ?trans2;
REDUX.OR UR4, R22 &req={2} &wr=0x2 ?trans2;
MOV R27, UR4 &req={2} ?WAIT5_END_GROUP;
@P2 REDG.E.OR.STRONG.GPU desc[UR8][R16.64+-0x8], R27 &rd=0x2 ?trans4;
LDG.E R20, desc[UR8][R18.64+-0x4] &wr=0x3 ?trans2;
REDUX.OR UR4, R20 &req={3} &wr=0x0 ?trans2;
MOV R23, UR4 &req={0} ?WAIT5_END_GROUP;
@P2 REDG.E.OR.STRONG.GPU desc[UR8][R16.64+-0x4], R23 &rd=0x0 ?trans4;
LDG.E R21, desc[UR8][R18.64] &wr=0x3 ?trans2;
REDUX.OR UR4, R21 &req={3} &wr=0x1 ?trans2;
MOV R25, UR4 &req={1} ?WAIT5_END_GROUP;
@P2 REDG.E.OR.STRONG.GPU desc[UR8][R16.64], R25 &rd=0x1 ?trans4;
LDG.E R22, desc[UR8][R18.64+0x4] &wr=0x3 ?trans2;
REDUX.OR UR4, R22 &req={3} &wr=0x2 ?trans2;
MOV R27, UR4 &req={2} ?WAIT5_END_GROUP;
@P2 REDG.E.OR.STRONG.GPU desc[UR8][R16.64+0x4], R27 ?trans4;
LDG.E R20, desc[UR8][R18.64+0x8] &wr=0x2 ?trans2;
REDUX.OR UR4, R20 &req={2} &wr=0x0 ?trans2;
MOV R23, UR4 &req={0} ?WAIT5_END_GROUP;
@P2 REDG.E.OR.STRONG.GPU desc[UR8][R16.64+0x8], R23 ?trans4;
LDG.E R21, desc[UR8][R18.64+0xc] &rd=0x0 &wr=0x2 ?trans1;
IADD3 R15, PT, PT, R15, 0x8, RZ ?trans2;
IADD3 R10, PT, PT, R10, 0x8, RZ ?trans1;
IADD.64 R18, R18, 0x20 &req={0} ?trans2;
REDUX.OR UR4, R21 &req={2} &wr=0x1 ?trans2;
MOV R25, UR4 &req={1} ?WAIT5_END_GROUP;
@P2 REDG.E.OR.STRONG.GPU desc[UR8][R16.64+0xc], R25 &rd=0x0 ?trans1;
ISETP.NE.AND P2, PT, R15, RZ, PT ?trans1;
IADD.64 R16, R16, 0x20 &req={0} ?WAIT12_END_GROUP;
@P2 BRA 0x390 ?trans5;
@!P3 BRA 0xc40 ?trans5;
IADD3 R15, PT, PT, R2, -0x1, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P3, PT, R15, 0x3, PT ?trans1;
LOP3.LUT P2, R15, R11, 0x3, RZ, 0xc0, !PT ?WAIT12_END_GROUP;
@!P3 BRA 0x8f0 ?trans5;
LDC.64 R16, c[0x0][0x390] &wr=0x0 ?trans1;
IADD3 R18, PT, PT, R14, R10, RZ ?trans1;
MOV R19, RZ ?WAIT5_END_GROUP;
IADD.64 R18, R4, R18 ?WAIT5_END_GROUP;
LEA R24, P3, R18, R16, 0x2 &req={0} ?WAIT4_END_GROUP;
LEA.HI.X R25, R18, R17, R19, 0x2, P3 ?trans1;
S2R R26, SR_LANEID &wr=0x0 ?trans1;
LDC.64 R18, c[0x0][0x398] &wr=0x1 ?trans3;
LDG.E R24, desc[UR8][R24.64] &wr=0x2 ?trans1;
MOV R22, R14 ?trans1;
HFMA2 R23, -RZ, RZ, 0, 0 ?trans1;
MOV R20, R10 ?trans1;
HFMA2 R21, -RZ, RZ, 0, 0 ?trans1;
VOTEU.ANY UR4, UPT, PT ?WAIT2_END_GROUP;
UFLO.U32 UR4, UR4 ?trans2;
IADD.64 R22, R22, R20.reuse ?trans2;
IADD.64 R20, R6, R20 ?trans2;
IADD.64 R22, R4, R22 ?WAIT5_END_GROUP;
LEA R16, P5, R22, R16, 0x2 ?trans2;
LEA R18, P4, R20, R18, 0x2 &req={1} ?trans2;
LEA.HI.X R17, R22, R17, R23, 0x2, P5 ?trans2;
LEA.HI.X R19, R20, R19, R21, 0x2, P4 ?trans1;
ISETP.EQ.U32.AND P3, PT, R26, UR4, PT &req={0} ?trans1;
REDUX.OR UR5, R24 &req={2} &wr=0x0 ?trans2;
MOV R23, UR5 &req={0} ?WAIT10_END_GROUP;
@P3 REDG.E.OR.STRONG.GPU desc[UR8][R18.64], R23 &rd=0x0 ?trans4;
LDG.E R20, desc[UR8][R16.64+0x4] &wr=0x2 ?trans2;
REDUX.OR UR4, R20 &req={2} &wr=0x1 ?trans2;
MOV R25, UR4 &req={1} ?WAIT5_END_GROUP;
@P3 REDG.E.OR.STRONG.GPU desc[UR8][R18.64+0x4], R25 &rd=0x1 ?trans4;
LDG.E R21, desc[UR8][R16.64+0x8] &wr=0x2 ?trans2;
REDUX.OR UR4, R21 &req={2} &wr=0x2 ?trans2;
MOV R27, UR4 &req={2} ?WAIT5_END_GROUP;
@P3 REDG.E.OR.STRONG.GPU desc[UR8][R18.64+0x8], R27 &rd=0x1 ?trans4;
LDG.E R22, desc[UR8][R16.64+0xc] &wr=0x2 ?trans2;
REDUX.OR UR4, R22 &req={2} &wr=0x0 ?trans2;
MOV R23, UR4 &req={0} ?WAIT5_END_GROUP;
@P3 REDG.E.OR.STRONG.GPU desc[UR8][R18.64+0xc], R23 &rd=0x1 ?trans1;
IADD3 R10, PT, PT, R10, 0x4, RZ ?WAIT7_END_GROUP;
@!P2 BRA 0xc40 ?trans5;
ISETP.NE.AND P3, PT, R15, 0x1, PT ?trans1;
LOP3.LUT P2, RZ, R11, 0x1, RZ, 0xc0, !PT ?WAIT12_END_GROUP;
@!P3 BRA 0xb00 ?trans5;
LDC.64 R16, c[0x0][0x390] &wr=0x0 ?trans1;
IADD3 R18, PT, PT, R14, R10, RZ &req={1} ?trans1;
MOV R19, RZ ?WAIT5_END_GROUP;
IADD.64 R18, R4, R18 ?WAIT5_END_GROUP;
LEA R22, P3, R18, R16, 0x2 &req={0} ?WAIT4_END_GROUP;
LEA.HI.X R23, R18, R17, R19, 0x2, P3 ?trans1;
S2R R26, SR_LANEID &wr=0x0 ?trans1;
LDC.64 R18, c[0x0][0x398] &wr=0x1 ?trans3;
LDG.E R22, desc[UR8][R22.64] &wr=0x2 ?trans1;
HFMA2 R15, -RZ, RZ, 0, 0 ?trans1;
MOV R11, RZ ?trans1;
VOTEU.ANY UR4, UPT, PT ?trans2;
UFLO.U32 UR4, UR4 ?WAIT2_END_GROUP;
IADD.64 R24, R14, R10.reuse ?trans2;
IADD.64 R20, R6, R10 ?trans2;
IADD.64 R24, R4, R24 ?WAIT5_END_GROUP;
LEA R16, P5, R24, R16, 0x2 ?WAIT4_END_GROUP;
LEA.HI.X R17, R24, R17, R25, 0x2, P5 ?trans2;
LEA R18, P4, R20, R18, 0x2 &req={1} ?WAIT4_END_GROUP;
LEA.HI.X R19, R20, R19, R21, 0x2, P4 ?trans1;
ISETP.EQ.U32.AND P3, PT, R26, UR4, PT &req={0} ?trans1;
REDUX.OR UR5, R22 &req={2} &wr=0x0 ?trans2;
MOV R11, UR5 &req={0} ?WAIT10_END_GROUP;
@P3 REDG.E.OR.STRONG.GPU desc[UR8][R18.64], R11 &rd=0x0 ?trans4;
LDG.E R16, desc[UR8][R16.64+0x4] &wr=0x2 ?trans2;
REDUX.OR UR4, R16 &req={2} &wr=0x1 ?trans2;
MOV R15, UR4 &req={1} ?WAIT5_END_GROUP;
@P3 REDG.E.OR.STRONG.GPU desc[UR8][R18.64+0x4], R15 &rd=0x0 ?trans1;
IADD3 R10, PT, PT, R10, 0x2, RZ ?WAIT7_END_GROUP;
@!P2 BRA 0xc40 ?trans5;
LDC.64 R16, c[0x0][0x390] &wr=0x2 ?trans1;
IADD3 R14, PT, PT, R14, R10, RZ ?trans1;
HFMA2 R15, -RZ, RZ, 0, 0 &req={0} ?WAIT5_END_GROUP;
IADD.64 R14, R4, R14 ?WAIT5_END_GROUP;
LEA R16, P2, R14, R16, 0x2 &req={2} ?WAIT4_END_GROUP;
LEA.HI.X R17, R14, R17, R15, 0x2, P2 ?trans1;
S2R R18, SR_LANEID &req={1} &wr=0x0 ?trans1;
LDC.64 R14, c[0x0][0x398] &wr=0x1 ?trans3;
LDG.E R16, desc[UR8][R16.64] &wr=0x2 ?trans1;
VOTEU.ANY UR4, UPT, PT ?trans1;
MOV R11, RZ ?trans1;
UFLO.U32 UR4, UR4 ?WAIT4_END_GROUP;
IADD.64 R10, R6, R10 ?WAIT5_END_GROUP;
LEA R14, P3, R10, R14, 0x2 &req={1} ?WAIT4_END_GROUP;
LEA.HI.X R15, R10, R15, R11, 0x2, P3 ?trans1;
ISETP.EQ.U32.AND P2, PT, R18, UR4, PT &req={0} ?trans1;
REDUX.OR UR5, R16 &req={2} &wr=0x0 ?trans2;
MOV R11, UR5 &req={0} ?WAIT10_END_GROUP;
@P2 REDG.E.OR.STRONG.GPU desc[UR8][R14.64], R11 &rd=0x2 ?trans2;
@!P1 BRA 0x280 ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
@!P0 BRA 0x190 ?trans5;
EXIT ?trans5;
LOP3.LUT R13, R5.reuse, 0x7, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R22, R5, 0x3, RZ, 0xc0, !PT ?trans2;
IADD3 R2, PT, PT, R13, -0x1, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ?trans1;
LOP3.LUT R2, R5, 0x7ffffff8, RZ, 0xc0, !PT ?WAIT12_END_GROUP;
LDC.64 R8, c[0x0][0x380] &req={2,0} &wr=0x0 ?trans1;
IMAD R4, R0, UR6, RZ ?trans1;
BSSY.RECONVERGENT B0, 0x1770 ?trans4;
SHF.R.S32.HI R5, RZ, 0x1f, R4 ?trans1;
ISETP.GE.U32.AND P2, PT, R3, R8, PT &req={0} ?trans1;
IMAD R6, R9, UR6, RZ ?trans1;
UIADD3 UR6, UPT, UPT, UR10, UR6, URZ ?WAIT4_END_GROUP;
SHF.R.S32.HI R7, RZ, 0x1f, R6 ?trans2;
ISETP.LE.AND P1, PT, R8, UR6, PT ?WAIT5_END_GROUP;
@P2 BRA 0x1760 &req={1} ?trans8;
MOV R10, R3 ?WAIT7_END_GROUP;
LDC.64 R8, c[0x0][0x380] &req={2,0} &wr=0x0 ?trans2;
ISETP.GE.U32.AND P3, PT, R9, 0x8, PT &req={0} ?trans1;
IMAD R12, R10.reuse, R9, RZ ?trans1;
IADD3 R10, PT, PT, R10, UR7, RZ ?WAIT5_END_GROUP;
ISETP.GE.AND P2, PT, R10, R8, PT ?trans1;
HFMA2 R8, -RZ, RZ, 0, 0 ?WAIT5_END_GROUP;
@!P3 BRA 0x1140 &req={1} ?trans7;
LDC.64 R14, c[0x0][0x390] &wr=0x0 ?trans1;
MOV R11, RZ ?WAIT7_END_GROUP;
LDC.64 R16, c[0x0][0x398] &wr=0x1 ?trans2;
IADD3 R18, PT, PT, R12, R11, RZ ?trans1;
MOV R19, RZ ?WAIT5_END_GROUP;
IADD.64 R20, R4, R18 ?WAIT5_END_GROUP;
LEA R18, P3, R20, R14, 0x2 &req={0} ?WAIT4_END_GROUP;
LEA.HI.X R19, R20, R15, R21, 0x2, P3 ?WAIT5_END_GROUP;
LDG.E R8, desc[UR8][R18.64] &wr=0x2 ?trans1;
VOTEU.ANY UR4, UPT, PT ?trans1;
MOV R20, R11 ?trans1;
HFMA2 R21, -RZ, RZ, 0, 0 ?trans1;
S2R R23, SR_LANEID &wr=0x0 ?trans1;
UFLO.U32 UR4, UR4 ?WAIT3_END_GROUP;
IADD.64 R24, R6, R20 ?WAIT5_END_GROUP;
LEA R20, P4, R24, R16, 0x2 &req={1} ?WAIT4_END_GROUP;
LEA.HI.X R21, R24, R17, R25, 0x2, P4 ?trans1;
ISETP.EQ.U32.AND P3, PT, R23, UR4, PT &req={0} ?trans1;
REDUX UR5, R8 &req={2} &wr=0x0 ?trans2;
MOV R25, UR5 &req={0} ?WAIT10_END_GROUP;
@P3 REDG.E.AND.STRONG.GPU desc[UR8][R20.64], R25 &rd=0x0 ?trans4;
LDG.E R23, desc[UR8][R18.64+0x4] &wr=0x2 ?trans2;
REDUX UR4, R23 &req={2} &wr=0x1 ?trans2;
MOV R27, UR4 &req={1} ?WAIT5_END_GROUP;
@P3 REDG.E.AND.STRONG.GPU desc[UR8][R20.64+0x4], R27 &rd=0x1 ?trans4;
LDG.E R8, desc[UR8][R18.64+0x8] &wr=0x2 ?trans2;
REDUX UR4, R8 &req={2} &wr=0x2 ?trans2;
MOV R29, UR4 &req={2} ?WAIT5_END_GROUP;
@P3 REDG.E.AND.STRONG.GPU desc[UR8][R20.64+0x8], R29 &rd=0x2 ?trans4;
LDG.E R24, desc[UR8][R18.64+0xc] &wr=0x3 ?trans2;
REDUX UR4, R24 &req={3} &wr=0x0 ?trans2;
MOV R25, UR4 &req={0} ?WAIT5_END_GROUP;
@P3 REDG.E.AND.STRONG.GPU desc[UR8][R20.64+0xc], R25 &rd=0x0 ?trans4;
LDG.E R23, desc[UR8][R18.64+0x10] &wr=0x3 ?trans2;
REDUX UR4, R23 &req={3} &wr=0x1 ?trans2;
MOV R27, UR4 &req={1} ?WAIT5_END_GROUP;
@P3 REDG.E.AND.STRONG.GPU desc[UR8][R20.64+0x10], R27 &rd=0x1 ?trans4;
LDG.E R8, desc[UR8][R18.64+0x14] &wr=0x3 ?trans2;
REDUX UR4, R8 &req={3} &wr=0x2 ?trans2;
MOV R29, UR4 &req={2} ?WAIT5_END_GROUP;
@P3 REDG.E.AND.STRONG.GPU desc[UR8][R20.64+0x14], R29 &rd=0x2 ?trans4;
LDG.E R24, desc[UR8][R18.64+0x18] &wr=0x3 ?trans2;
REDUX UR4, R24 &req={3} &wr=0x0 ?trans2;
MOV R25, UR4 &req={0} ?WAIT5_END_GROUP;
@P3 REDG.E.AND.STRONG.GPU desc[UR8][R20.64+0x18], R25 &rd=0x2 ?trans4;
LDG.E R23, desc[UR8][R18.64+0x1c] &wr=0x3 ?trans1;
IADD3 R11, PT, PT, R11, 0x8, RZ ?trans1;
REDUX UR4, R23 &req={3} &wr=0x1 ?trans2;
MOV R27, UR4 &req={1} ?WAIT5_END_GROUP;
@P3 REDG.E.AND.STRONG.GPU desc[UR8][R20.64+0x1c], R27 &rd=0x2 ?trans1;
ISETP.NE.AND P3, PT, R11, R2, PT ?WAIT13_END_GROUP;
@P3 BRA 0xe20 &req={2} ?trans5;
MOV R8, R2 ?WAIT7_END_GROUP;
ISETP.NE.AND P3, PT, R13, RZ, PT ?WAIT13_END_GROUP;
@!P3 BRA 0x1750 ?trans5;
ISETP.NE.AND P3, PT, R22, RZ, PT ?trans1;
@!P0 BRA 0x13f0 ?WAIT12_END_GROUP;
LDC.64 R14, c[0x0][0x390] &wr=0x0 ?trans1;
IADD3 R16, PT, PT, R12, R8, RZ ?trans1;
MOV R17, RZ ?WAIT5_END_GROUP;
IADD.64 R16, R4, R16 ?WAIT5_END_GROUP;
LEA R24, P4, R16, R14, 0x2 &req={0} ?WAIT4_END_GROUP;
LEA.HI.X R25, R16, R15, R17, 0x2, P4 ?trans1;
S2R R11, SR_LANEID &wr=0x0 ?trans1;
LDC.64 R16, c[0x0][0x398] &wr=0x1 ?trans3;
LDG.E R24, desc[UR8][R24.64] &wr=0x2 ?trans1;
MOV R20, R12 ?trans1;
HFMA2 R21, -RZ, RZ, 0, 0 ?trans1;
MOV R18, R8 ?trans1;
HFMA2 R19, -RZ, RZ, 0, 0 ?trans1;
VOTEU.ANY UR4, UPT, PT ?WAIT2_END_GROUP;
UFLO.U32 UR4, UR4 ?trans2;
IADD.64 R20, R18, R20 ?trans2;
IADD.64 R18, R6, R18 ?trans2;
IADD.64 R20, R4, R20 ?WAIT5_END_GROUP;
LEA R14, P6, R20, R14, 0x2 ?trans2;
LEA R16, P5, R18, R16, 0x2 &req={1} ?trans2;
LEA.HI.X R15, R20, R15, R21, 0x2, P6 ?trans2;
LEA.HI.X R17, R18, R17, R19, 0x2, P5 ?trans1;
ISETP.EQ.U32.AND P4, PT, R11, UR4, PT &req={0} ?trans1;
REDUX UR5, R24 &req={2} &wr=0x0 ?trans2;
MOV R21, UR5 &req={0} ?WAIT10_END_GROUP;
@P4 REDG.E.AND.STRONG.GPU desc[UR8][R16.64], R21 &rd=0x0 ?trans4;
LDG.E R11, desc[UR8][R14.64+0x4] &wr=0x2 ?trans2;
REDUX UR4, R11 &req={2} &wr=0x1 ?trans2;
MOV R23, UR4 &req={1} ?WAIT5_END_GROUP;
@P4 REDG.E.AND.STRONG.GPU desc[UR8][R16.64+0x4], R23 &rd=0x1 ?trans4;
LDG.E R18, desc[UR8][R14.64+0x8] &wr=0x2 ?trans2;
REDUX UR4, R18 &req={2} &wr=0x2 ?trans2;
MOV R25, UR4 &req={2} ?WAIT5_END_GROUP;
@P4 REDG.E.AND.STRONG.GPU desc[UR8][R16.64+0x8], R25 &rd=0x1 ?trans4;
LDG.E R19, desc[UR8][R14.64+0xc] &wr=0x2 ?trans2;
REDUX UR4, R19 &req={2} &wr=0x0 ?trans2;
MOV R21, UR4 &req={0} ?WAIT5_END_GROUP;
@P4 REDG.E.AND.STRONG.GPU desc[UR8][R16.64+0xc], R21 &rd=0x1 ?trans1;
IADD3 R8, PT, PT, R8, 0x4, RZ ?WAIT7_END_GROUP;
@!P3 BRA 0x1750 ?trans5;
ISETP.NE.AND P4, PT, R22, 0x1, PT ?trans1;
LOP3.LUT P3, RZ, R9, 0x1, RZ, 0xc0, !PT ?WAIT12_END_GROUP;
@!P4 BRA 0x1610 ?trans5;
LDC.64 R14, c[0x0][0x390] &wr=0x0 ?trans1;
IADD3 R16, PT, PT, R12, R8, RZ &req={1} ?trans1;
MOV R17, RZ ?WAIT5_END_GROUP;
IADD.64 R16, R4, R16 ?WAIT5_END_GROUP;
LEA R20, P4, R16, R14, 0x2 &req={0} ?WAIT4_END_GROUP;
LEA.HI.X R21, R16, R15, R17, 0x2, P4 ?trans1;
S2R R11, SR_LANEID &wr=0x0 ?trans1;
LDC.64 R16, c[0x0][0x398] &wr=0x1 ?trans3;
LDG.E R20, desc[UR8][R20.64] &wr=0x2 ?trans1;
MOV R18, R12 ?trans1;
HFMA2 R19, -RZ, RZ, 0, 0 ?trans1;
MOV R9, RZ ?trans1;
VOTEU.ANY UR4, UPT, PT ?trans2;
UFLO.U32 UR4, UR4 ?WAIT2_END_GROUP;
IADD.64 R24, R8, R18 ?trans2;
IADD.64 R18, R6, R8 ?trans2;
IADD.64 R24, R4, R24 ?WAIT5_END_GROUP;
LEA R14, P6, R24, R14, 0x2 ?trans2;
LEA R16, P5, R18, R16, 0x2 &req={1} ?trans2;
LEA.HI.X R15, R24, R15, R25, 0x2, P6 ?trans2;
LEA.HI.X R17, R18, R17, R19, 0x2, P5 ?trans1;
ISETP.EQ.U32.AND P4, PT, R11, UR4, PT &req={0} ?trans1;
REDUX UR5, R20 &req={2} &wr=0x0 ?trans2;
MOV R9, UR5 &req={0} ?WAIT10_END_GROUP;
@P4 REDG.E.AND.STRONG.GPU desc[UR8][R16.64], R9 &rd=0x0 ?trans4;
LDG.E R14, desc[UR8][R14.64+0x4] &wr=0x2 ?trans2;
REDUX UR4, R14 &req={2} &wr=0x1 ?trans2;
MOV R11, UR4 &req={1} ?WAIT5_END_GROUP;
@P4 REDG.E.AND.STRONG.GPU desc[UR8][R16.64+0x4], R11 &rd=0x0 ?trans1;
IADD3 R8, PT, PT, R8, 0x2, RZ ?WAIT7_END_GROUP;
@!P3 BRA 0x1750 ?trans5;
LDC.64 R16, c[0x0][0x390] &req={1,0} &wr=0x0 ?trans1;
IADD3 R14, PT, PT, R12, R8, RZ ?trans1;
HFMA2 R15, -RZ, RZ, 0, 0 ?WAIT5_END_GROUP;
IADD.64 R14, R4, R14 ?WAIT5_END_GROUP;
LEA R16, P3, R14, R16, 0x2 &req={0} ?WAIT4_END_GROUP;
LEA.HI.X R17, R14, R17, R15, 0x2, P3 ?trans1;
S2R R11, SR_LANEID &wr=0x0 ?trans1;
LDC.64 R14, c[0x0][0x398] &wr=0x1 ?trans3;
LDG.E R16, desc[UR8][R16.64] &wr=0x2 ?trans1;
VOTEU.ANY UR4, UPT, PT ?trans1;
MOV R9, RZ ?trans1;
UFLO.U32 UR4, UR4 ?WAIT4_END_GROUP;
IADD.64 R8, R6, R8 ?WAIT5_END_GROUP;
LEA R14, P4, R8, R14, 0x2 &req={1} ?WAIT4_END_GROUP;
LEA.HI.X R15, R8, R15, R9, 0x2, P4 ?trans1;
ISETP.EQ.U32.AND P3, PT, R11, UR4, PT &req={0} ?trans1;
REDUX UR5, R16 &req={2} &wr=0x0 ?trans2;
MOV R9, UR5 &req={0} ?WAIT10_END_GROUP;
@P3 REDG.E.AND.STRONG.GPU desc[UR8][R14.64], R9 &rd=0x2 ?trans2;
@!P2 BRA 0xd80 ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
@!P1 BRA 0xcd0 ?trans5;
EXIT ?trans5;
BRA 0x1790;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: points_nms_sample(int, int, int, int*, int*)
_Z17points_nms_sampleiiiPiS_:
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s4
s_cbranch_scc1 .LBB4_24
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[8:11], s[0:1], 0x10
s_load_b32 s1, s[0:1], 0x20
v_mov_b32_e32 v2, 0
s_mul_i32 s14, s5, s4
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s2, 0xffff
s_cmp_gt_i32 s5, 0
s_cselect_b32 s12, -1, 0
s_and_b32 s0, s6, -3
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s0, 0
v_cmp_gt_i32_e64 s0, s4, v0
s_cselect_b32 s13, -1, 0
s_cmp_eq_u32 s6, 1
s_cselect_b32 s6, -1, 0
.LBB4_2:
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s16, s0
s_cbranch_execz .LBB4_23
s_mul_i32 s18, s14, s15
s_mul_i32 s20, s15, s5
s_ashr_i32 s19, s18, 31
v_mov_b32_e32 v3, v0
s_lshl_b64 s[18:19], s[18:19], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_u32 s17, s8, s18
s_addc_u32 s18, s9, s19
s_ashr_i32 s21, s20, 31
s_lshl_b64 s[20:21], s[20:21], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s19, s10, s20
s_addc_u32 s20, s11, s21
s_mov_b32 s21, 0
.LBB4_4:
s_and_not1_b32 vcc_lo, exec_lo, s12
s_cbranch_vccnz .LBB4_22
v_mul_lo_u32 v4, v3, s5
s_mov_b32 s2, 0
.LBB4_6:
s_and_b32 vcc_lo, exec_lo, s13
s_cbranch_vccz .LBB4_14
s_and_not1_b32 vcc_lo, exec_lo, s6
s_cbranch_vccnz .LBB4_13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, s2, v4
s_mov_b32 s23, exec_lo
s_mov_b32 s22, -1
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s17, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s18, v6, vcc_lo
global_load_b32 v1, v[5:6], off
.LBB4_9:
s_ctz_i32_b32 s24, s23
s_waitcnt vmcnt(0)
v_readlane_b32 s25, v1, s24
s_lshl_b32 s24, 1, s24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_not1_b32 s23, s23, s24
s_and_b32 s22, s22, s25
s_cmp_lg_u32 s23, 0
s_cbranch_scc1 .LBB4_9
v_mbcnt_lo_u32_b32 v1, exec_lo, 0
s_mov_b32 s23, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v1
s_xor_b32 s23, exec_lo, s23
s_cbranch_execz .LBB4_12
s_lshl_b64 s[24:25], s[2:3], 2
v_mov_b32_e32 v1, s22
s_add_u32 s24, s19, s24
s_addc_u32 s25, s20, s25
global_atomic_and_b32 v2, v1, s[24:25]
.LBB4_12:
s_or_b32 exec_lo, exec_lo, s23
.LBB4_13:
s_mov_b32 s22, 0
s_branch .LBB4_15
.LBB4_14:
s_mov_b32 s22, -1
.LBB4_15:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s22
s_cbranch_vccnz .LBB4_21
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, s2, v4
s_mov_b32 s23, exec_lo
s_mov_b32 s22, 0
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s17, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s18, v6, vcc_lo
global_load_b32 v1, v[5:6], off
.LBB4_17:
s_ctz_i32_b32 s24, s23
s_waitcnt vmcnt(0)
v_readlane_b32 s25, v1, s24
s_lshl_b32 s24, 1, s24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_not1_b32 s23, s23, s24
s_or_b32 s22, s22, s25
s_cmp_lg_u32 s23, 0
s_cbranch_scc1 .LBB4_17
v_mbcnt_lo_u32_b32 v1, exec_lo, 0
s_mov_b32 s23, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v1
s_xor_b32 s23, exec_lo, s23
s_cbranch_execz .LBB4_20
s_lshl_b64 s[24:25], s[2:3], 2
v_mov_b32_e32 v1, s22
s_add_u32 s24, s19, s24
s_addc_u32 s25, s20, s25
global_atomic_or_b32 v2, v1, s[24:25]
.LBB4_20:
s_or_b32 exec_lo, exec_lo, s23
.LBB4_21:
s_add_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, s5
s_cbranch_scc0 .LBB4_6
.LBB4_22:
v_add_nc_u32_e32 v3, s7, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s4, v3
s_or_b32 s21, vcc_lo, s21
s_and_not1_b32 exec_lo, exec_lo, s21
s_cbranch_execnz .LBB4_4
.LBB4_23:
s_or_b32 exec_lo, exec_lo, s16
s_add_i32 s15, s1, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s15, s4
s_cbranch_scc0 .LBB4_2
.LBB4_24:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| points_nms_sample | 9,591 | 2,323 | stackv2-00000-of-00015 |
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