id stringlengths 22 129 | text stringlengths 60 19.5k | arch stringclasses 9
values | syntax stringclasses 5
values | kind stringclasses 4
values | repo stringclasses 32
values | path stringlengths 7 108 | license stringclasses 10
values | commit stringlengths 40 40 | source_host stringclasses 1
value | category stringclasses 15
values | source_url stringlengths 85 192 | line_start int64 1 5.48k | line_end int64 4 5.5k |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:15 | /* Restore argument registers from user stack */
lr a0, __struct_arch_esf_a0_OFFSET(sp)
lr a1, __struct_arch_esf_a1_OFFSET(sp)
lr a2, __struct_arch_esf_a2_OFFSET(sp)
lr a3, __struct_arch_esf_a3_OFFSET(sp)
lr a4, __struct_arch_esf_a4_OFFSET(sp)
lr a5, __struct_arch_esf_a5_OFFSET(sp)
lr t0, __struct_arch_esf_t0_OF... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 26af854046c533bc50069ebff9eb56176d4b9edc | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/26af854046c533bc50069ebff9eb56176d4b9edc/arch/riscv/core/isr.S | 561 | 620 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:16 | /* Update a0 (return value) on the stack */
sr a0, __struct_arch_esf_a0_OFFSET(sp)
/* Disable IRQs again before leaving */
csrc mstatus, MSTATUS_IEN
j might_have_rescheduled
#endif /* CONFIG_USERSPACE */
is_interrupt:
#ifdef CONFIG_PMP_KERNEL_MODE_DYNAMIC
#ifdef CONFIG_USERSPACE
/*
* If we came from userspace... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 26af854046c533bc50069ebff9eb56176d4b9edc | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/26af854046c533bc50069ebff9eb56176d4b9edc/arch/riscv/core/isr.S | 601 | 660 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:17 | /* Disable the custom stack guard */
call z_riscv_custom_stack_guard_disable
#endif /* CONFIG_CUSTOM_STACK_GUARD */
/* Switch to interrupt stack */
mv t0, sp
lr sp, ___cpu_t_irq_stack_OFFSET(s0)
/*
* Save thread stack pointer on interrupt stack
* In RISC-V, stack pointer needs to be 16-byte aligned
*/
add... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 26af854046c533bc50069ebff9eb56176d4b9edc | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/26af854046c533bc50069ebff9eb56176d4b9edc/arch/riscv/core/isr.S | 641 | 700 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:19 | /* Disable the custom stack guard for interrupt stack */
call z_riscv_custom_stack_guard_disable
#endif /* CONFIG_CUSTOM_STACK_GUARD */
/* nested count is back to 0: Return to thread stack */
lr sp, 0(sp)
#ifdef CONFIG_CUSTOM_STACK_GUARD
/* Enable the custom stack guard for thread stack */
lr a0, ___cpu_t_curren... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 26af854046c533bc50069ebff9eb56176d4b9edc | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/26af854046c533bc50069ebff9eb56176d4b9edc/arch/riscv/core/isr.S | 721 | 780 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:20 | * Perform context switch:
* a0 = new thread
* a1 = old thread
*/
call z_riscv_switch
z_riscv_thread_start:
might_have_rescheduled:
/* reload s0 with &_current_cpu as it might have changed or be unset */
get_current_cpu s0
#endif /* CONFIG_MULTITHREADING */
no_reschedule:
#ifdef CONFIG_RISCV_SOC_CONTEXT_SAV... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 26af854046c533bc50069ebff9eb56176d4b9edc | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/26af854046c533bc50069ebff9eb56176d4b9edc/arch/riscv/core/isr.S | 761 | 820 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:21 | lr t1, __struct_arch_esf_mcause_OFFSET(sp)
csrw mcause, t1
#endif /* CONFIG_CLIC_SUPPORT_INTERRUPT_LEVEL */
csrw mepc, t0
csrw mstatus, t2
#ifdef CONFIG_USERSPACE
/*
* Check if we are returning to user mode. If so then we must
* set is_user_mode to true and preserve our kernel mode stack for
* the next exce... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 26af854046c533bc50069ebff9eb56176d4b9edc | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/26af854046c533bc50069ebff9eb56176d4b9edc/arch/riscv/core/isr.S | 801 | 860 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:22 | /*
* We are returning to kernel mode. Store the stack pointer to
* be re-loaded further down.
*/
addi t0, sp, __struct_arch_esf_SIZEOF
sr t0, __struct_arch_esf_sp_OFFSET(sp)
2:
#endif
/* Restore s0 (it is no longer ours) */
lr s0, __struct_arch_esf_s0_OFFSET(sp)
#ifdef CONFIG_RISCV_SOC_HAS_ISR_STACKING
SOC... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 26af854046c533bc50069ebff9eb56176d4b9edc | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/26af854046c533bc50069ebff9eb56176d4b9edc/arch/riscv/core/isr.S | 841 | 869 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:8 | andi t1, t2, 1
bnez t1, no_fp
/*
* 001...........00 = C.FLD RV32/64 (RV128 = C.LQ)
* 001...........10 = C.FLDSP RV32/64 (RV128 = C.LQSP)
* 011...........00 = C.FLW RV32 (RV64/128 = C.LD)
* 011...........10 = C.FLWSPP RV32 (RV64/128 = C.LDSP)
* 101...........00 = C.FSD RV32/64 (RV128 = C... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | a88b3c545352bb0deb45cab004bce878839643b7 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/a88b3c545352bb0deb45cab004bce878839643b7/arch/riscv/core/isr.S | 281 | 340 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:9 | #ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
/* Handle context saving at SOC level. */
addi a0, sp, __struct_arch_esf_soc_context_OFFSET
jal ra, __soc_save_context
#endif /* CONFIG_RISCV_SOC_CONTEXT_SAVE */
/*
* Check if exception is the result of an interrupt or not.
* (SOC dependent). Following the RISC-V architectu... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | a88b3c545352bb0deb45cab004bce878839643b7 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/a88b3c545352bb0deb45cab004bce878839643b7/arch/riscv/core/isr.S | 321 | 380 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:10 | #endif /* CONFIG_CUSTOM_STACK_GUARD */
/*
* If mcause == RISCV_EXC_ECALLU, handle system call
* for user mode thread.
*/
li t1, RISCV_EXC_ECALLU
beq t0, t1, is_user_syscall
#ifdef CONFIG_PMP_KERNEL_MODE_DYNAMIC
/*
* Determine if we come from user space. If so, reconfigure the PMP for
* kernel mode confi... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | a88b3c545352bb0deb45cab004bce878839643b7 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/a88b3c545352bb0deb45cab004bce878839643b7/arch/riscv/core/isr.S | 361 | 420 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:11 | /* Restore SP if z_riscv_fault returns before jumping to no_reschedule */
addi sp, sp, __callee_saved_t_SIZEOF
j no_reschedule
#else
la ra, no_reschedule
tail z_riscv_fault
#endif /* CONFIG_EXCEPTION_DEBUG */
is_kernel_syscall:
/*
* A syscall is the result of an ecall instruction, in which case the
* MEPC wi... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | a88b3c545352bb0deb45cab004bce878839643b7 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/a88b3c545352bb0deb45cab004bce878839643b7/arch/riscv/core/isr.S | 401 | 460 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:12 | #endif
#ifdef CONFIG_RISCV_ALWAYS_SWITCH_THROUGH_ECALL
li t1, RV_ECALL_SCHEDULE
bne t0, t1, skip_schedule
lr a0, __struct_arch_esf_a0_OFFSET(sp)
lr a1, __struct_arch_esf_a1_OFFSET(sp)
#ifdef CONFIG_FPU_SHARING
/*
* When an ECALL is used for a context-switch, the current thread has
* been updated to the next ... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | a88b3c545352bb0deb45cab004bce878839643b7 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/a88b3c545352bb0deb45cab004bce878839643b7/arch/riscv/core/isr.S | 441 | 500 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:13 | call z_riscv_fatal_error
j check_reschedule
#if defined(CONFIG_IRQ_OFFLOAD)
do_irq_offload:
/*
* Retrieve provided routine and argument from the stack.
* Routine pointer is in saved a0, argument in saved a1
* so we load them with a1/a0 (reversed).
*/
lr a1, __struct_arch_esf_a0_OFFSET(sp)
lr a0, __struct_a... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | a88b3c545352bb0deb45cab004bce878839643b7 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/a88b3c545352bb0deb45cab004bce878839643b7/arch/riscv/core/isr.S | 481 | 540 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:14 | lr t0, 0(sp)
lr a1, __struct_arch_esf_a0_OFFSET(t0)
lr a0, __struct_arch_esf_a1_OFFSET(t0)
#endif /* CONFIG_CUSTOM_STACK_GUARD */
1:
/* Execute provided routine (argument is in a0 already). */
jalr ra, a1, 0
/* Leave through the regular IRQ exit path */
j irq_done
#endif /* CONFIG_IRQ_OFFLOAD */
#ifdef CONFIG_... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | a88b3c545352bb0deb45cab004bce878839643b7 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/a88b3c545352bb0deb45cab004bce878839643b7/arch/riscv/core/isr.S | 521 | 580 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:15 | lr a3, __struct_arch_esf_a3_OFFSET(sp)
lr a4, __struct_arch_esf_a4_OFFSET(sp)
lr a5, __struct_arch_esf_a5_OFFSET(sp)
lr t0, __struct_arch_esf_t0_OFFSET(sp)
#if defined(CONFIG_RISCV_ISA_RV32E)
/* Stack alignment for RV32E is 4 bytes */
addi sp, sp, -4
mv t1, sp
sw t1, 0(sp)
#else
mv a6, sp
#endif /* CONFIG_RISCV... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | a88b3c545352bb0deb45cab004bce878839643b7 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/a88b3c545352bb0deb45cab004bce878839643b7/arch/riscv/core/isr.S | 561 | 620 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:16 | csrc mstatus, MSTATUS_IEN
j might_have_rescheduled
#endif /* CONFIG_USERSPACE */
is_interrupt:
#ifdef CONFIG_PMP_KERNEL_MODE_DYNAMIC
#ifdef CONFIG_USERSPACE
/*
* If we came from userspace then we need to reconfigure the
* PMP for kernel mode configuration.
*/
lr t0, __struct_arch_esf_mstatus_OFFSET(sp)
li t... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | a88b3c545352bb0deb45cab004bce878839643b7 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/a88b3c545352bb0deb45cab004bce878839643b7/arch/riscv/core/isr.S | 601 | 660 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:17 | mv t0, sp
lr sp, ___cpu_t_irq_stack_OFFSET(s0)
/*
* Save thread stack pointer on interrupt stack
* In RISC-V, stack pointer needs to be 16-byte aligned
*/
addi sp, sp, -16
sr t0, 0(sp)
#ifdef CONFIG_CUSTOM_STACK_GUARD
/* Enable the custom stack guard for interrupt stack */
lr a0, ___cpu_t_current_OFFSET(s... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | a88b3c545352bb0deb45cab004bce878839643b7 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/a88b3c545352bb0deb45cab004bce878839643b7/arch/riscv/core/isr.S | 641 | 700 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:18 | * (table is 2-word wide, we should shift index accordingly)
*/
la t0, _sw_isr_table
slli a0, a0, (RV_REGSHIFT + 1)
add t0, t0, a0
/* Load argument in a0 register */
lr a0, 0(t0)
/* Load ISR function address in register t1 */
lr t1, RV_REGSIZE(t0)
#else
/* Load spurious interrupt function in case _sw_isr_tab... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | a88b3c545352bb0deb45cab004bce878839643b7 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/a88b3c545352bb0deb45cab004bce878839643b7/arch/riscv/core/isr.S | 681 | 740 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:19 | lr sp, 0(sp)
#ifdef CONFIG_CUSTOM_STACK_GUARD
/* Enable the custom stack guard for thread stack */
lr a0, ___cpu_t_current_OFFSET(s0)
call z_riscv_custom_stack_guard_enable
#endif /* CONFIG_CUSTOM_STACK_GUARD */
#ifdef CONFIG_STACK_SENTINEL
call z_check_stack_sentinel
#endif
check_reschedule:
#ifdef CONFIG_MULT... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | a88b3c545352bb0deb45cab004bce878839643b7 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/a88b3c545352bb0deb45cab004bce878839643b7/arch/riscv/core/isr.S | 721 | 780 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:20 | z_riscv_thread_start:
might_have_rescheduled:
/* reload s0 with &_current_cpu as it might have changed or be unset */
get_current_cpu s0
#endif /* CONFIG_MULTITHREADING */
no_reschedule:
#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
/* Restore context at SOC level */
addi a0, sp, __struct_arch_esf_soc_context_OFFSET
jal... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | a88b3c545352bb0deb45cab004bce878839643b7 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/a88b3c545352bb0deb45cab004bce878839643b7/arch/riscv/core/isr.S | 761 | 820 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:21 | csrw mstatus, t2
#ifdef CONFIG_USERSPACE
/*
* Check if we are returning to user mode. If so then we must
* set is_user_mode to true and preserve our kernel mode stack for
* the next exception to come.
*/
li t1, MSTATUS_MPP
and t0, t2, t1
bnez t0, 1f
#ifdef CONFIG_PMP_KERNEL_MODE_DYNAMIC
/* Remove kernel ... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | a88b3c545352bb0deb45cab004bce878839643b7 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/a88b3c545352bb0deb45cab004bce878839643b7/arch/riscv/core/isr.S | 801 | 860 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:22 | sr t0, __struct_arch_esf_sp_OFFSET(sp)
2:
#endif
/* Restore s0 (it is no longer ours) */
lr s0, __struct_arch_esf_s0_OFFSET(sp)
#ifdef CONFIG_RISCV_SOC_HAS_ISR_STACKING
SOC_ISR_SW_UNSTACKING
#else
/* Restore caller-saved registers from thread stack */
DO_CALLER_SAVED(lr)
#ifdef CONFIG_USERSPACE
/* retrieve sav... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | a88b3c545352bb0deb45cab004bce878839643b7 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/a88b3c545352bb0deb45cab004bce878839643b7/arch/riscv/core/isr.S | 841 | 864 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:3 | #ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
GTEXT(__soc_save_context)
GTEXT(__soc_restore_context)
#endif /* CONFIG_RISCV_SOC_CONTEXT_SAVE */
GTEXT(z_riscv_fatal_error)
GTEXT(z_get_next_switch_handle)
GTEXT(z_riscv_switch)
GTEXT(z_riscv_thread_start)
#ifdef CONFIG_TRACING
GTEXT(sys_trace_isr_enter)
GTEXT(sys_trace_isr_exit)... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 742812e580df88aa2680aa7382a8d88006f6f1de | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/742812e580df88aa2680aa7382a8d88006f6f1de/arch/riscv/core/isr.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:4 | *
* - __soc_handle_irq: handle SoC-specific details for a pending IRQ
* (e.g. clear a pending bit in a SoC-specific register)
*
* If CONFIG_RISCV_SOC_CONTEXT_SAVE=y, calls to SoC-level context save/restore
* routines are also made here. For details, see the Kconfig help text.
*/
/*
* Handler called up... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 742812e580df88aa2680aa7382a8d88006f6f1de | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/742812e580df88aa2680aa7382a8d88006f6f1de/arch/riscv/core/isr.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:5 | lr t0, ___cpu_t_current_OFFSET(s0)
lr tp, _thread_offset_to_tls(t0)
/* Make sure global pointer is sane */
#ifdef CONFIG_RISCV_GP
.option push
.option norelax
la gp, __global_pointer$
.option pop
#elif defined(CONFIG_RISCV_CURRENT_VIA_GP)
lr gp, ___cpu_t_current_OFFSET(s0)
#endif /* CONFIG_RISCV_GP / CONFIG_RIS... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 742812e580df88aa2680aa7382a8d88006f6f1de | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/742812e580df88aa2680aa7382a8d88006f6f1de/arch/riscv/core/isr.S | 161 | 220 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:6 | csrr t0, mcause
sr t0, __struct_arch_esf_mcause_OFFSET(sp)
#endif /* CONFIG_CLIC_SUPPORT_INTERRUPT_LEVEL */
/* Save MEPC register */
csrr t0, mepc
sr t0, __struct_arch_esf_mepc_OFFSET(sp)
/* Save MSTATUS register */
csrr t2, mstatus
sr t2, __struct_arch_esf_mstatus_OFFSET(sp)
#if defined(CONFIG_FPU_SHARING)
... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 742812e580df88aa2680aa7382a8d88006f6f1de | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/742812e580df88aa2680aa7382a8d88006f6f1de/arch/riscv/core/isr.S | 201 | 260 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:7 | * 1000111 = MSUB
* 1001011 = NMSUB
* 1001111 = NMADD
* 1010011 = OP-FP
*/
xori t1, t0, 0b1010011 /* OP-FP */
beqz t1, is_fp
ori t1, t0, 0b0100000
xori t1, t1, 0b0100111 /* LOAD-FP / STORE-FP */
beqz t1, is_fp
ori t1, t0, 0b0001100
xori t1, t1, 0b1001111 /* MADD / MSUB / NMSUB / NMADD */
beqz t1, is_fp... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 742812e580df88aa2680aa7382a8d88006f6f1de | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/742812e580df88aa2680aa7382a8d88006f6f1de/arch/riscv/core/isr.S | 241 | 300 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:8 | * 011...........00 = C.FLW RV32 (RV64/128 = C.LD)
* 011...........10 = C.FLWSPP RV32 (RV64/128 = C.LDSP)
* 101...........00 = C.FSD RV32/64 (RV128 = C.SQ)
* 101...........10 = C.FSDSP RV32/64 (RV128 = C.SQSP)
* 111...........00 = C.FSW RV32 (RV64/128 = C.SD)
* 111...........10 = C.FSWS... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 742812e580df88aa2680aa7382a8d88006f6f1de | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/742812e580df88aa2680aa7382a8d88006f6f1de/arch/riscv/core/isr.S | 281 | 340 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:9 | /*
* Check if exception is the result of an interrupt or not.
* (SOC dependent). Following the RISC-V architecture spec, the MSB
* of the mcause register is used to indicate whether an exception
* is the result of an interrupt or an exception/fault.
*/
csrr t0, mcause
bltz t0, is_interrupt
/*
* If the e... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 742812e580df88aa2680aa7382a8d88006f6f1de | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/742812e580df88aa2680aa7382a8d88006f6f1de/arch/riscv/core/isr.S | 321 | 380 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:10 | 1:
#endif /* CONFIG_PMP_KERNEL_MODE_DYNAMIC */
#endif /* CONFIG_USERSPACE */
/*
* Call z_riscv_fault to handle exception.
* Stack pointer is pointing to a struct_arch_esf structure, pass it
* to z_riscv_fault (via register a0).
* If z_riscv_fault shall return, set return address to
* no_reschedule to resto... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 742812e580df88aa2680aa7382a8d88006f6f1de | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/742812e580df88aa2680aa7382a8d88006f6f1de/arch/riscv/core/isr.S | 361 | 420 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:11 | addi t0, t0, 4
sr t0, __struct_arch_esf_mepc_OFFSET(sp)
#ifdef CONFIG_PMP_KERNEL_MODE_DYNAMIC
/* Re-activate PMP for m-mode */
li t1, MSTATUS_MPP
csrc mstatus, t1
li t1, MSTATUS_MPRV
csrs mstatus, t1
#endif
/* Determine what to do. Operation code is in t0. */
lr t0, __struct_arch_esf_t0_OFFSET(sp)
.if RV_EC... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 742812e580df88aa2680aa7382a8d88006f6f1de | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/742812e580df88aa2680aa7382a8d88006f6f1de/arch/riscv/core/isr.S | 401 | 460 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:12 | sb t1, _thread_offset_to_exception_depth(a1)
#endif
j reschedule
skip_schedule:
#endif
/* default fault code is K_ERR_KERNEL_OOPS */
li a0, 3
j 1f
do_fault:
/* Handle RV_ECALL_RUNTIME_EXCEPT. Retrieve reason in a0, esf in A1. */
lr a0, __struct_arch_esf_a0_OFFSET(sp)
1: mv a1, sp
#ifdef CONFIG_EXCEPTION_DEBUG... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 742812e580df88aa2680aa7382a8d88006f6f1de | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/742812e580df88aa2680aa7382a8d88006f6f1de/arch/riscv/core/isr.S | 441 | 500 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:13 | mv t0, sp
lr sp, ___cpu_t_irq_stack_OFFSET(s0)
/* Save thread stack pointer on interrupt stack */
addi sp, sp, -16
sr t0, 0(sp)
1:
/* Execute provided routine (argument is in a0 already). */
jalr ra, a1, 0
/* Leave through the regular IRQ exit path */
j irq_done
#endif /* CONFIG_IRQ_OFFLOAD */
#ifdef CONFIG_... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 742812e580df88aa2680aa7382a8d88006f6f1de | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/742812e580df88aa2680aa7382a8d88006f6f1de/arch/riscv/core/isr.S | 481 | 540 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:14 | lr a2, __struct_arch_esf_a2_OFFSET(sp)
lr a3, __struct_arch_esf_a3_OFFSET(sp)
lr a4, __struct_arch_esf_a4_OFFSET(sp)
lr a5, __struct_arch_esf_a5_OFFSET(sp)
lr t0, __struct_arch_esf_t0_OFFSET(sp)
#if defined(CONFIG_RISCV_ISA_RV32E)
/* Stack alignment for RV32E is 4 bytes */
addi sp, sp, -4
mv t1, sp
sw t1, 0(sp)... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 742812e580df88aa2680aa7382a8d88006f6f1de | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/742812e580df88aa2680aa7382a8d88006f6f1de/arch/riscv/core/isr.S | 521 | 580 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:15 | /* Disable IRQs again before leaving */
csrc mstatus, MSTATUS_IEN
j might_have_rescheduled
#endif /* CONFIG_USERSPACE */
is_interrupt:
#ifdef CONFIG_PMP_KERNEL_MODE_DYNAMIC
#ifdef CONFIG_USERSPACE
/*
* If we came from userspace then we need to reconfigure the
* PMP for kernel mode configuration.
*/
lr t0, _... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 742812e580df88aa2680aa7382a8d88006f6f1de | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/742812e580df88aa2680aa7382a8d88006f6f1de/arch/riscv/core/isr.S | 561 | 620 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:16 | * Save thread stack pointer on interrupt stack
* In RISC-V, stack pointer needs to be 16-byte aligned
*/
addi sp, sp, -16
sr t0, 0(sp)
on_irq_stack:
#ifdef CONFIG_RISCV_SOC_HAS_CUSTOM_IRQ_HANDLING
call __soc_handle_all_irqs
#else
#ifdef CONFIG_TRACING_ISR
call sys_trace_isr_enter
#endif
/* Get IRQ causing ... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 742812e580df88aa2680aa7382a8d88006f6f1de | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/742812e580df88aa2680aa7382a8d88006f6f1de/arch/riscv/core/isr.S | 601 | 660 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:17 | lr t1, RV_REGSIZE(t0)
#else
/* Load spurious interrupt function in case _sw_isr_table does not exist */
la t1, z_irq_spurious
/* NULL as parameter */
li a0, 0
#endif
/* Call ISR function */
jalr ra, t1, 0
#ifdef CONFIG_TRACING_ISR
call sys_trace_isr_exit
#endif
#endif
irq_done:
/* Decrement _current_cpu->ne... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 742812e580df88aa2680aa7382a8d88006f6f1de | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/742812e580df88aa2680aa7382a8d88006f6f1de/arch/riscv/core/isr.S | 641 | 700 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:18 | * We pass it a NULL as we didn't save the whole thread context yet.
* If no scheduling is necessary then NULL will be returned.
*/
addi sp, sp, -16
sr a1, 0(sp)
mv a0, zero
call z_get_next_switch_handle
lr a1, 0(sp)
addi sp, sp, 16
beqz a0, no_reschedule
reschedule:
/*
* Perform context switch:
* a0 =... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 742812e580df88aa2680aa7382a8d88006f6f1de | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/742812e580df88aa2680aa7382a8d88006f6f1de/arch/riscv/core/isr.S | 681 | 740 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:19 | /* decrement _current->arch.exception_depth */
lr t0, ___cpu_t_current_OFFSET(s0)
lb t1, _thread_offset_to_exception_depth(t0)
add t1, t1, -1
sb t1, _thread_offset_to_exception_depth(t0)
fp_trap_exit:
#endif
/* Restore MEPC and MSTATUS registers */
lr t0, __struct_arch_esf_mepc_OFFSET(sp)
lr t2, __struct_arch_e... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 742812e580df88aa2680aa7382a8d88006f6f1de | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/742812e580df88aa2680aa7382a8d88006f6f1de/arch/riscv/core/isr.S | 721 | 780 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:20 | add t0, t0, tp, %tprel_add(is_user_mode)
sb t1, %tprel_lo(is_user_mode)(t0)
/* preserve stack pointer for next exception entry */
add t0, sp, __struct_arch_esf_SIZEOF
sr t0, _curr_cpu_arch_user_exc_sp(s0)
j 2f
1:
/*
* We are returning to kernel mode. Store the stack pointer to
* be re-loaded further down.
... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 742812e580df88aa2680aa7382a8d88006f6f1de | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/742812e580df88aa2680aa7382a8d88006f6f1de/arch/riscv/core/isr.S | 761 | 798 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:8 | * 011...........00 = C.FLW RV32 (RV64/128 = C.LD)
* 011...........10 = C.FLWSPP RV32 (RV64/128 = C.LDSP)
* 101...........00 = C.FSD RV32/64 (RV128 = C.SQ)
* 101...........10 = C.FSDSP RV32/64 (RV128 = C.SQSP)
* 111...........00 = C.FSW RV32 (RV64/128 = C.SD)
* 111...........10 = C.FSWS... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 1d67c392a717134133b1687088489d19cba690af | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/1d67c392a717134133b1687088489d19cba690af/arch/riscv/core/isr.S | 281 | 340 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:9 | /*
* Check if exception is the result of an interrupt or not.
* (SOC dependent). Following the RISC-V architecture spec, the MSB
* of the mcause register is used to indicate whether an exception
* is the result of an interrupt or an exception/fault.
*/
csrr t0, mcause
srli t0, t0, RISCV_MCAUSE_IRQ_POS
bnez... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 1d67c392a717134133b1687088489d19cba690af | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/1d67c392a717134133b1687088489d19cba690af/arch/riscv/core/isr.S | 321 | 380 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:10 | csrr t0, mstatus
li t1, MSTATUS_MPP
and t0, t0, t1
bnez t0, 1f
lr a0, ___cpu_t_current_OFFSET(s0)
call z_riscv_pmp_kernelmode_enable
1:
#endif /* CONFIG_PMP_KERNEL_MODE_DYNAMIC */
#endif /* CONFIG_USERSPACE */
/*
* Call z_riscv_fault to handle exception.
* Stack pointer is pointing to a struct_arch_esf stru... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 1d67c392a717134133b1687088489d19cba690af | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/1d67c392a717134133b1687088489d19cba690af/arch/riscv/core/isr.S | 361 | 420 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:11 | * again upon exiting the ISR.
*
* It's safe to always increment by 4, even with compressed
* instructions, because the ecall instruction is always 4 bytes.
*/
lr t0, __struct_arch_esf_mepc_OFFSET(sp)
addi t0, t0, 4
sr t0, __struct_arch_esf_mepc_OFFSET(sp)
#ifdef CONFIG_PMP_KERNEL_MODE_DYNAMIC
/* Re-activat... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 1d67c392a717134133b1687088489d19cba690af | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/1d67c392a717134133b1687088489d19cba690af/arch/riscv/core/isr.S | 401 | 460 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:12 | lb t1, _thread_offset_to_exception_depth(a0)
add t1, t1, -1
sb t1, _thread_offset_to_exception_depth(a0)
lb t1, _thread_offset_to_exception_depth(a1)
add t1, t1, 1
sb t1, _thread_offset_to_exception_depth(a1)
#endif
j reschedule
skip_schedule:
#endif
/* default fault code is K_ERR_KERNEL_OOPS */
li a0, 3
j ... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 1d67c392a717134133b1687088489d19cba690af | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/1d67c392a717134133b1687088489d19cba690af/arch/riscv/core/isr.S | 441 | 500 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:13 | lw t1, ___cpu_t_nested_OFFSET(s0)
addi t2, t1, 1
sw t2, ___cpu_t_nested_OFFSET(s0)
bnez t1, 1f
/* Switch to interrupt stack */
mv t0, sp
lr sp, ___cpu_t_irq_stack_OFFSET(s0)
/* Save thread stack pointer on interrupt stack */
addi sp, sp, -16
sr t0, 0(sp)
1:
/* Execute provided routine (argument is in a0 alr... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 1d67c392a717134133b1687088489d19cba690af | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/1d67c392a717134133b1687088489d19cba690af/arch/riscv/core/isr.S | 481 | 540 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:14 | addi t1, t1, 4
sr t1, __struct_arch_esf_mepc_OFFSET(sp)
/* Restore argument registers from user stack */
lr a0, __struct_arch_esf_a0_OFFSET(sp)
lr a1, __struct_arch_esf_a1_OFFSET(sp)
lr a2, __struct_arch_esf_a2_OFFSET(sp)
lr a3, __struct_arch_esf_a3_OFFSET(sp)
lr a4, __struct_arch_esf_a4_OFFSET(sp)
lr a5, __st... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 1d67c392a717134133b1687088489d19cba690af | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/1d67c392a717134133b1687088489d19cba690af/arch/riscv/core/isr.S | 521 | 580 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:15 | addi sp, sp, 4
#endif /* CONFIG_RISCV_ISA_RV32E */
/* Update a0 (return value) on the stack */
sr a0, __struct_arch_esf_a0_OFFSET(sp)
/* Disable IRQs again before leaving */
csrc mstatus, MSTATUS_IEN
j might_have_rescheduled
#endif /* CONFIG_USERSPACE */
is_interrupt:
#ifdef CONFIG_PMP_KERNEL_MODE_DYNAMIC
#ifd... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 1d67c392a717134133b1687088489d19cba690af | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/1d67c392a717134133b1687088489d19cba690af/arch/riscv/core/isr.S | 561 | 620 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:16 | /* Switch to interrupt stack */
mv t0, sp
lr sp, ___cpu_t_irq_stack_OFFSET(s0)
/*
* Save thread stack pointer on interrupt stack
* In RISC-V, stack pointer needs to be 16-byte aligned
*/
addi sp, sp, -16
sr t0, 0(sp)
on_irq_stack:
#ifdef CONFIG_RISCV_SOC_HAS_CUSTOM_IRQ_HANDLING
call __soc_handle_all_irqs... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 1d67c392a717134133b1687088489d19cba690af | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/1d67c392a717134133b1687088489d19cba690af/arch/riscv/core/isr.S | 601 | 660 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:17 | add t0, t0, a0
/* Load argument in a0 register */
lr a0, 0(t0)
/* Load ISR function address in register t1 */
lr t1, RV_REGSIZE(t0)
#else
/* Load spurious interrupt function in case _sw_isr_table does not exist */
la t1, z_irq_spurious
/* NULL as parameter */
li a0, 0
#endif
/* Call ISR function */
jalr ra... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 1d67c392a717134133b1687088489d19cba690af | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/1d67c392a717134133b1687088489d19cba690af/arch/riscv/core/isr.S | 641 | 700 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:18 | /* Get pointer to current thread on this CPU */
lr a1, ___cpu_t_current_OFFSET(s0)
/*
* Get next thread to schedule with z_get_next_switch_handle().
* We pass it a NULL as we didn't save the whole thread context yet.
* If no scheduling is necessary then NULL will be returned.
*/
addi sp, sp, -16
sr a1, 0(s... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 1d67c392a717134133b1687088489d19cba690af | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/1d67c392a717134133b1687088489d19cba690af/arch/riscv/core/isr.S | 681 | 740 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:19 | #if defined(CONFIG_FPU_SHARING)
/* FPU handling upon exception mode exit */
mv a0, sp
call z_riscv_fpu_exit_exc
/* decrement _current->arch.exception_depth */
lr t0, ___cpu_t_current_OFFSET(s0)
lb t1, _thread_offset_to_exception_depth(t0)
add t1, t1, -1
sb t1, _thread_offset_to_exception_depth(t0)
fp_trap_exit... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 1d67c392a717134133b1687088489d19cba690af | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/1d67c392a717134133b1687088489d19cba690af/arch/riscv/core/isr.S | 721 | 780 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:20 | call z_riscv_pmp_usermode_enable
#endif
/* Set our per-thread usermode flag */
li t1, 1
lui t0, %tprel_hi(is_user_mode)
add t0, t0, tp, %tprel_add(is_user_mode)
sb t1, %tprel_lo(is_user_mode)(t0)
/* preserve stack pointer for next exception entry */
add t0, sp, __struct_arch_esf_SIZEOF
sr t0, _curr_cpu_arch_u... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 1d67c392a717134133b1687088489d19cba690af | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/1d67c392a717134133b1687088489d19cba690af/arch/riscv/core/isr.S | 761 | 804 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:2 | RV_I( op a7, __struct_arch_esf_a7_OFFSET(sp) );\
RV_E( op ra, __struct_arch_esf_ra_OFFSET(sp) )
#ifdef CONFIG_EXCEPTION_DEBUG
/*
* Convenience macro for storing callee saved register [s0 - s11] states.
* Note: s0 is callee-saved and the exception entry code already saved it
* in struct arch_esf so it could be used... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 81c77d59d12c4685a2135184e45f4bda9ce5777b | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/81c77d59d12c4685a2135184e45f4bda9ce5777b/arch/riscv/core/isr.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:3 | GTEXT(__soc_handle_irq)
GTEXT(z_riscv_fault)
GTEXT(z_irq_spurious)
#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
GTEXT(__soc_save_context)
GTEXT(__soc_restore_context)
#endif /* CONFIG_RISCV_SOC_CONTEXT_SAVE */
GTEXT(z_riscv_fatal_error)
GTEXT(z_get_next_switch_handle)
GTEXT(z_riscv_switch)
GTEXT(z_riscv_thread_start)
#ifdef ... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 81c77d59d12c4685a2135184e45f4bda9ce5777b | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/81c77d59d12c4685a2135184e45f4bda9ce5777b/arch/riscv/core/isr.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:4 | * implementations vary (some implementations also deviate from
* what standard behavior is defined). Hence, the arch level code expects
* the following functions to be provided at the SOC level:
*
* - __soc_is_irq (optional): decide if we're handling an interrupt or an
exception
* - __soc_handle_i... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 81c77d59d12c4685a2135184e45f4bda9ce5777b | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/81c77d59d12c4685a2135184e45f4bda9ce5777b/arch/riscv/core/isr.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:8 | andi t1, t2, 1
bnez t1, no_fp
/*
* 001...........00 = C.FLD RV32/64 (RV128 = C.LQ)
* 001...........10 = C.FLDSP RV32/64 (RV128 = C.LQSP)
* 011...........00 = C.FLW RV32 (RV64/128 = C.LD)
* 011...........10 = C.FLWSPP RV32 (RV64/128 = C.LDSP)
* 101...........00 = C.FSD RV32/64 (RV128 = C... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 81c77d59d12c4685a2135184e45f4bda9ce5777b | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/81c77d59d12c4685a2135184e45f4bda9ce5777b/arch/riscv/core/isr.S | 281 | 340 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:9 | #ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
/* Handle context saving at SOC level. */
addi a0, sp, __struct_arch_esf_soc_context_OFFSET
jal ra, __soc_save_context
#endif /* CONFIG_RISCV_SOC_CONTEXT_SAVE */
/*
* Check if exception is the result of an interrupt or not.
* (SOC dependent). Following the RISC-V architectu... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 81c77d59d12c4685a2135184e45f4bda9ce5777b | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/81c77d59d12c4685a2135184e45f4bda9ce5777b/arch/riscv/core/isr.S | 321 | 380 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:10 | beq t0, t1, is_kernel_syscall
#ifdef CONFIG_USERSPACE
/*
* If mcause == RISCV_EXC_ECALLU, handle system call
* for user mode thread.
*/
li t1, RISCV_EXC_ECALLU
beq t0, t1, is_user_syscall
#ifdef CONFIG_PMP_KERNEL_MODE_DYNAMIC
/*
* Determine if we come from user space. If so, reconfigure the PMP for
* ke... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 81c77d59d12c4685a2135184e45f4bda9ce5777b | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/81c77d59d12c4685a2135184e45f4bda9ce5777b/arch/riscv/core/isr.S | 361 | 420 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:11 | /* Restore SP if z_riscv_fault returns before jumping to no_reschedule */
addi sp, sp, __callee_saved_t_SIZEOF
j no_reschedule
#else
la ra, no_reschedule
tail z_riscv_fault
#endif /* CONFIG_EXCEPTION_DEBUG */
is_kernel_syscall:
/*
* A syscall is the result of an ecall instruction, in which case the
* MEPC wi... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 81c77d59d12c4685a2135184e45f4bda9ce5777b | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/81c77d59d12c4685a2135184e45f4bda9ce5777b/arch/riscv/core/isr.S | 401 | 460 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:13 | #endif /* CONFIG_EXCEPTION_DEBUG */
call z_riscv_fatal_error
j check_reschedule
#if defined(CONFIG_IRQ_OFFLOAD)
do_irq_offload:
/*
* Retrieve provided routine and argument from the stack.
* Routine pointer is in saved a0, argument in saved a1
* so we load them with a1/a0 (reversed).
*/
lr a1, __struct_arch... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 81c77d59d12c4685a2135184e45f4bda9ce5777b | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/81c77d59d12c4685a2135184e45f4bda9ce5777b/arch/riscv/core/isr.S | 481 | 540 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:14 | * We came from userspace and need to reconfigure the
* PMP for kernel mode configuration.
*/
lr a0, ___cpu_t_current_OFFSET(s0)
call z_riscv_pmp_kernelmode_enable
#endif
/* It is safe to re-enable IRQs now */
csrs mstatus, MSTATUS_IEN
/*
* Same as for is_kernel_syscall: increment saved MEPC by 4 to
* pre... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 81c77d59d12c4685a2135184e45f4bda9ce5777b | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/81c77d59d12c4685a2135184e45f4bda9ce5777b/arch/riscv/core/isr.S | 521 | 580 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:15 | mv a0, t0
li t0, K_SYSCALL_BAD
valid_syscall_id:
la t2, _k_syscall_table
slli t1, t0, RV_REGSHIFT # Determine offset from indice value
add t2, t2, t1 # Table addr + offset = function addr
lr t2, 0(t2) # Load function address
/* Execute syscall function */
jalr ra, t2, 0
#if defined(CONFIG_RISCV_ISA_RV32... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 81c77d59d12c4685a2135184e45f4bda9ce5777b | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/81c77d59d12c4685a2135184e45f4bda9ce5777b/arch/riscv/core/isr.S | 561 | 620 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:16 | j 2f
#endif /* CONFIG_USERSPACE */
1: /* Re-activate PMP for m-mode */
li t1, MSTATUS_MPP
csrc mstatus, t1
li t1, MSTATUS_MPRV
csrs mstatus, t1
2:
#endif
/* Increment _current_cpu->nested */
lw t1, ___cpu_t_nested_OFFSET(s0)
addi t2, t1, 1
sw t2, ___cpu_t_nested_OFFSET(s0)
bnez t1, on_irq_stack
/* Switch to... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 81c77d59d12c4685a2135184e45f4bda9ce5777b | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/81c77d59d12c4685a2135184e45f4bda9ce5777b/arch/riscv/core/isr.S | 601 | 660 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:17 | and a0, a0, t0
/*
* Clear pending IRQ generating the interrupt at SOC level
* Pass IRQ number to __soc_handle_irq via register a0
*/
jal ra, __soc_handle_irq
#if defined CONFIG_GEN_SW_ISR_TABLE
/*
* Call corresponding registered function in _sw_isr_table.
* (table is 2-word wide, we should shift index ac... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 81c77d59d12c4685a2135184e45f4bda9ce5777b | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/81c77d59d12c4685a2135184e45f4bda9ce5777b/arch/riscv/core/isr.S | 641 | 700 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:18 | lw t2, ___cpu_t_nested_OFFSET(s0)
addi t2, t2, -1
sw t2, ___cpu_t_nested_OFFSET(s0)
bnez t2, no_reschedule
/* nested count is back to 0: Return to thread stack */
lr sp, 0(sp)
#ifdef CONFIG_STACK_SENTINEL
call z_check_stack_sentinel
#endif
check_reschedule:
#ifdef CONFIG_MULTITHREADING
/* Get pointer to cur... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 81c77d59d12c4685a2135184e45f4bda9ce5777b | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/81c77d59d12c4685a2135184e45f4bda9ce5777b/arch/riscv/core/isr.S | 681 | 740 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:19 | z_riscv_thread_start:
might_have_rescheduled:
/* reload s0 with &_current_cpu as it might have changed or be unset */
get_current_cpu s0
#endif /* CONFIG_MULTITHREADING */
no_reschedule:
#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
/* Restore context at SOC level */
addi a0, sp, __struct_arch_esf_soc_context_OFFSET
jal... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 81c77d59d12c4685a2135184e45f4bda9ce5777b | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/81c77d59d12c4685a2135184e45f4bda9ce5777b/arch/riscv/core/isr.S | 721 | 780 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:20 | csrw mstatus, t2
#ifdef CONFIG_USERSPACE
/*
* Check if we are returning to user mode. If so then we must
* set is_user_mode to true and preserve our kernel mode stack for
* the next exception to come.
*/
li t1, MSTATUS_MPP
and t0, t2, t1
bnez t0, 1f
#ifdef CONFIG_PMP_KERNEL_MODE_DYNAMIC
/* Remove kernel ... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 81c77d59d12c4685a2135184e45f4bda9ce5777b | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/81c77d59d12c4685a2135184e45f4bda9ce5777b/arch/riscv/core/isr.S | 761 | 819 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:21 | lr s0, __struct_arch_esf_s0_OFFSET(sp)
#ifdef CONFIG_RISCV_SOC_HAS_ISR_STACKING
SOC_ISR_SW_UNSTACKING
#else
/* Restore caller-saved registers from thread stack */
DO_CALLER_SAVED(lr)
#ifdef CONFIG_USERSPACE
/* retrieve saved stack pointer */
lr sp, __struct_arch_esf_sp_OFFSET(sp)
#else
/* remove esf from the st... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 81c77d59d12c4685a2135184e45f4bda9ce5777b | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/81c77d59d12c4685a2135184e45f4bda9ce5777b/arch/riscv/core/isr.S | 801 | 819 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:6 | sr s0, __struct_arch_esf_s0_OFFSET(sp)
get_current_cpu s0
#ifdef CONFIG_CLIC_SUPPORT_INTERRUPT_LEVEL
/* Save mcause register */
csrr t0, mcause
sr t0, __struct_arch_esf_mcause_OFFSET(sp)
#endif /* CONFIG_CLIC_SUPPORT_INTERRUPT_LEVEL */
/* Save MEPC register */
csrr t0, mepc
sr t0, __struct_arch_esf_mepc_OFFSET... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | faa65388d3f88d79d9a37e4ed4cd86d6e68bdf14 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/faa65388d3f88d79d9a37e4ed4cd86d6e68bdf14/arch/riscv/core/isr.S | 201 | 260 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:12 | beq t0, t1, do_irq_offload
#endif
#ifdef CONFIG_RISCV_ALWAYS_SWITCH_THROUGH_ECALL
li t1, RV_ECALL_SCHEDULE
bne t0, t1, skip_schedule
lr a0, __struct_arch_esf_a0_OFFSET(sp)
lr a1, __struct_arch_esf_a1_OFFSET(sp)
#ifdef CONFIG_FPU_SHARING
/*
* When an ECALL is used for a context-switch, the current thread has
... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/riscv/core/isr.S | 441 | 500 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:13 | #endif /* CONFIG_EXCEPTION_DEBUG */
tail z_riscv_fatal_error
#if defined(CONFIG_IRQ_OFFLOAD)
do_irq_offload:
/*
* Retrieve provided routine and argument from the stack.
* Routine pointer is in saved a0, argument in saved a1
* so we load them with a1/a0 (reversed).
*/
lr a1, __struct_arch_esf_a0_OFFSET(sp)
... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/riscv/core/isr.S | 481 | 540 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:14 | * PMP for kernel mode configuration.
*/
lr a0, ___cpu_t_current_OFFSET(s0)
call z_riscv_pmp_kernelmode_enable
#endif
/* It is safe to re-enable IRQs now */
csrs mstatus, MSTATUS_IEN
/*
* Same as for is_kernel_syscall: increment saved MEPC by 4 to
* prevent triggering the same ecall again upon exiting the I... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/riscv/core/isr.S | 521 | 580 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:15 | li t0, K_SYSCALL_BAD
valid_syscall_id:
la t2, _k_syscall_table
slli t1, t0, RV_REGSHIFT # Determine offset from indice value
add t2, t2, t1 # Table addr + offset = function addr
lr t2, 0(t2) # Load function address
/* Execute syscall function */
jalr ra, t2, 0
#if defined(CONFIG_RISCV_ISA_RV32E)
addi sp... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/riscv/core/isr.S | 561 | 620 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:16 | #endif /* CONFIG_USERSPACE */
1: /* Re-activate PMP for m-mode */
li t1, MSTATUS_MPP
csrc mstatus, t1
li t1, MSTATUS_MPRV
csrs mstatus, t1
2:
#endif
/* Increment _current_cpu->nested */
lw t1, ___cpu_t_nested_OFFSET(s0)
addi t2, t1, 1
sw t2, ___cpu_t_nested_OFFSET(s0)
bnez t1, on_irq_stack
/* Switch to inte... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/riscv/core/isr.S | 601 | 660 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:17 | /*
* Clear pending IRQ generating the interrupt at SOC level
* Pass IRQ number to __soc_handle_irq via register a0
*/
jal ra, __soc_handle_irq
#if defined CONFIG_GEN_SW_ISR_TABLE
/*
* Call corresponding registered function in _sw_isr_table.
* (table is 2-word wide, we should shift index accordingly)
*/
... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/riscv/core/isr.S | 641 | 700 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:18 | addi t2, t2, -1
sw t2, ___cpu_t_nested_OFFSET(s0)
bnez t2, no_reschedule
/* nested count is back to 0: Return to thread stack */
lr sp, 0(sp)
#ifdef CONFIG_STACK_SENTINEL
call z_check_stack_sentinel
#endif
check_reschedule:
#ifdef CONFIG_MULTITHREADING
/* Get pointer to current thread on this CPU */
lr a1, ... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/riscv/core/isr.S | 681 | 740 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:19 | z_riscv_thread_start:
might_have_rescheduled:
/* reload s0 with &_current_cpu as it might have changed or be unset */
get_current_cpu s0
#endif /* CONFIG_MULTITHREADING */
no_reschedule:
#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
/* Restore context at SOC level */
addi a0, sp, __struct_arch_esf_soc_context_OFFSET
jal... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/riscv/core/isr.S | 721 | 780 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:20 | #ifdef CONFIG_USERSPACE
/*
* Check if we are returning to user mode. If so then we must
* set is_user_mode to true and preserve our kernel mode stack for
* the next exception to come.
*/
li t1, MSTATUS_MPP
and t0, t2, t1
bnez t0, 1f
#ifdef CONFIG_PMP_KERNEL_MODE_DYNAMIC
/* Remove kernel mode configuration... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/riscv/core/isr.S | 761 | 818 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:21 | #ifdef CONFIG_RISCV_SOC_HAS_ISR_STACKING
SOC_ISR_SW_UNSTACKING
#else
/* Restore caller-saved registers from thread stack */
DO_CALLER_SAVED(lr)
#ifdef CONFIG_USERSPACE
/* retrieve saved stack pointer */
lr sp, __struct_arch_esf_sp_OFFSET(sp)
#else
/* remove esf from the stack */
addi sp, sp, __struct_arch_esf_S... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/riscv/core/isr.S | 801 | 818 |
zephyrproject-rtos/zephyr:arch/riscv/core/pm_s2ram.S:2 | #ifdef CONFIG_RISCV_ISA_RV32E
#define GPR_AREA_BYTES (5 * REGBYTES)
#else
#define GPR_AREA_BYTES (15 * REGBYTES)
#endif
#ifdef CONFIG_FPU
#define FPR_AREA_OFF GPR_AREA_BYTES
#define FCSR_OFF (FPR_AREA_OFF + 12 * FREGBYTES)
#define STACK_RAW_BYTES (FCSR_OFF + REGBYTES)
#else
#define STACK_RAW_BYTES GPR_AREA_BY... | riscv | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/riscv/core/pm_s2ram.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/pm_s2ram.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/riscv/core/pm_s2ram.S:3 | * only the load/store work is skipped when there's no FP state.
*/
#ifdef CONFIG_FPU
#define DO_STACK_FPRS(op) \
op fs0, (FPR_AREA_OFF + 0 * FREGBYTES)(sp); \
op fs1, (FPR_AREA_OFF + 1 * FREGBYTES)(sp); \
op fs2, (FPR_AREA_OFF + 2 * FREGBYTES)(sp); \
op fs3, (FPR_AREA_OFF + 3 * FREGBYTES)(sp); \
op fs4, ... | riscv | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/riscv/core/pm_s2ram.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/pm_s2ram.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/riscv/core/pm_s2ram.S:4 | GTEXT(arch_pm_s2ram_suspend)
GTEXT(arch_pm_s2ram_resume)
GTEXT(pm_s2ram_mark_set)
GTEXT(pm_s2ram_mark_check_and_clear)
GDATA(_cpu_context)
SECTION_FUNC(TEXT, arch_pm_s2ram_suspend)
/* a0 = system_off function pointer. */
addi sp, sp, -STACK_FRAME_BYTES
DO_STACK_GPRS(sr)
PM_S2RAM_SAVE_FP
/* Stash system_off in a... | riscv | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/riscv/core/pm_s2ram.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/pm_s2ram.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/riscv/core/pm_s2ram.S:5 | /* Order context/marker stores before any SoC cache maintenance. */
fence rw, rw
/* On success this never returns; on abort, fall through. system_off
* must preserve mstatus across return (abort uses live FS bits).
*/
jalr s0
/* Abort path: a0 holds system_off()'s return value; preserve it
* across the mark... | riscv | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/riscv/core/pm_s2ram.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/pm_s2ram.S | 161 | 220 |
zephyrproject-rtos/zephyr:arch/riscv/core/pm_s2ram.S:6 | .option push
.option norelax
la a0, _cpu_context
.option pop
/* Defer mstatus write until after FP restore: the saved FS bits
* may demand a powered FPU, and we should not arm FS until we are
* about to touch FP regs.
*/
lr t1, ___cpu_context_t_mstatus_OFFSET(a0)
/* mscratch before mtvec: _isr_wrapper rea... | riscv | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/riscv/core/pm_s2ram.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/pm_s2ram.S | 201 | 245 |
zephyrproject-rtos/zephyr:arch/riscv/core/pmp.S:1 | /*
* Copyright (c) 2022 BayLibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
#include <zephyr/arch/cpu.h>
#include "asm_macros.inc"
#define CSR_PMPCFG_BASE 0x3a0
#define CSR_PMPADDR_BASE 0x3b0
/*
* Prototype:
*
* void z_riscv_write_pmp_ent... | riscv | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/riscv/core/pmp.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/pmp.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/riscv/core/pmp.S:2 | add t0, t0, t1
jr t0
pmpaddr_store:
.option push
.option norvc
.set _index, 0
.rept CONFIG_PMP_SLOTS
lr t0, (RV_REGSIZE * _index)(a3)
li t1, _index + 1
csrw (CSR_PMPADDR_BASE + _index), t0
beq t1, a1, pmpaddr_done
.set _index, _index + 1
.endr
.option pop
pmpaddr_done:
/*
* Move to the pmpcfg space:
... | riscv | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/riscv/core/pmp.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/pmp.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/riscv/core/pmp.S:3 | csrw (CSR_PMPCFG_BASE + RV_REGSIZE/4 * _index), t0
beq a0, a1, pmpcfg_done
.set _index, _index + 1
.endr
.option pop
pmpcfg_done:
beqz a2, done
la t0, pmpcfg_zerotail
slli a0, a0, 2 /* 4-byte instruction blocks */
add t0, t0, a0
jr t0
/*
* Prototype:
*
* void z_riscv_clear_all_pmp_entries(void)
*
* C... | riscv | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/riscv/core/pmp.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/pmp.S | 81 | 119 |
zephyrproject-rtos/zephyr:arch/riscv/core/reset.S:1 | /*
* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
* Contributors: 2018 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/offsets.h>
#include <zephyr/arch/riscv/csr.... | riscv | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/reset.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/reset.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/riscv/core/reset.S:2 | * This will be dependent on linker.ld configuration.
*/
call __initialize
#endif /* CONFIG_INCLUDE_RESET_VECTOR */
/* use ABI name of registers for the sake of simplicity */
#ifdef CONFIG_THREAD_LOCAL_STORAGE
/*
* Allocate a TLS area on the current stack, initialize it via
* arch_riscv_early_tls_stack_update(), ... | riscv | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/reset.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/reset.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/riscv/core/reset.S:3 | */
SECTION_FUNC(TEXT, __initialize)
csrr a0, mhartid
li t0, CONFIG_RV_BOOT_HART
beq a0, t0, boot_first_core
j boot_secondary_core
boot_first_core:
#ifdef CONFIG_FPU
/*
* Enable floating-point.
*/
li t0, MSTATUS_FS_INIT
csrs mstatus, t0
/*
* Floating-point rounding mode set to IEEE-754 default, and clea... | riscv | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/reset.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/reset.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/riscv/core/reset.S:4 | * z_interrupt_stacks + __z_interrupt_stack_SIZEOF
*/
la sp, z_interrupt_stacks
li t0, __z_interrupt_stack_SIZEOF
add sp, sp, t0
#ifdef CONFIG_THREAD_LOCAL_STORAGE
/*
* Initialize TLS before the first C function call. The compiler inserts
* stack canary checks into C functions, and the canary value is read fr... | riscv | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/reset.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/reset.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/riscv/core/reset.S:5 | csrw mideleg, t0
/* PMP entry 0: NAPOT, RWX, covers all memory so S-mode can
* access everything
*/
li t0, -1
csrw pmpaddr0, t0
li t0, (PMP_NAPOT | PMP_R | PMP_W | PMP_X)
csrw pmpcfg0, t0
/* Initialize mscratch to M-mode stack top */
la t0, m_mode_stack_top
csrw mscratch, t0
/* Allow S-mode to read cycle,... | riscv | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/reset.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/reset.S | 161 | 220 |
zephyrproject-rtos/zephyr:arch/riscv/core/reset.S:6 | boot_secondary_core:
#if CONFIG_MP_MAX_NUM_CPUS > 1
la t0, riscv_cpu_wake_flag
li t1, -1
sr t1, 0(t0)
la t0, riscv_cpu_boot_flag
sr zero, 0(t0)
wait_secondary_wake_flag:
la t0, riscv_cpu_wake_flag
lr t0, 0(t0)
bne a0, t0, wait_secondary_wake_flag
/* Set up stack */
la t0, riscv_cpu_sp
lr sp, 0(t0)
#ifdef ... | riscv | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/reset.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/reset.S | 201 | 235 |
zephyrproject-rtos/zephyr:arch/riscv/core/reset.S:3 | */
SECTION_FUNC(TEXT, __initialize)
csrr a0, mhartid
li t0, CONFIG_RV_BOOT_HART
beq a0, t0, boot_first_core
j boot_secondary_core
boot_first_core:
#ifdef CONFIG_FPU
/*
* Enable floating-point.
*/
li t0, MSTATUS_FS_INIT
csrs mstatus, t0
/*
* Floating-point rounding mode set to IEEE-754 default, and clea... | riscv | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/reset.S | Apache-2.0 | 2d6bdab5dc038881052ec2804e38713160782be9 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/2d6bdab5dc038881052ec2804e38713160782be9/arch/riscv/core/reset.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/riscv/core/reset.S:4 | * z_interrupt_stacks + __z_interrupt_stack_SIZEOF
*/
la sp, z_interrupt_stacks
li t0, __z_interrupt_stack_SIZEOF
add sp, sp, t0
#ifdef CONFIG_THREAD_LOCAL_STORAGE
/*
* Initialize TLS before the first C function call. Compiler
* inserts stack canary checks into C functions, and the canary
* value is read fr... | riscv | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/reset.S | Apache-2.0 | 2d6bdab5dc038881052ec2804e38713160782be9 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/2d6bdab5dc038881052ec2804e38713160782be9/arch/riscv/core/reset.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/riscv/core/reset.S:5 | li t0, (MIP_SSIP | MIP_STIP | MIP_SEIP)
csrw mideleg, t0
/* PMP entry 0: NAPOT, RWX, covers all memory so S-mode can
* access everything
*/
li t0, -1
csrw pmpaddr0, t0
li t0, (PMP_NAPOT | PMP_R | PMP_W | PMP_X)
csrw pmpcfg0, t0
/* Initialize mscratch to M-mode stack top */
la t0, m_mode_stack_top
csrw mscr... | riscv | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/reset.S | Apache-2.0 | 2d6bdab5dc038881052ec2804e38713160782be9 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/2d6bdab5dc038881052ec2804e38713160782be9/arch/riscv/core/reset.S | 161 | 220 |
zephyrproject-rtos/zephyr:arch/riscv/core/reset.S:1 | /*
* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
* Contributors: 2018 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/offsets.h>
#include <zephyr/arch/riscv/csr.... | riscv | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/reset.S | Apache-2.0 | 729110c12fec2cf1843e39f19f88a86c7c676513 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/729110c12fec2cf1843e39f19f88a86c7c676513/arch/riscv/core/reset.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/riscv/core/reset.S:2 | * This will be dependent on linker.ld configuration.
*/
call __initialize
#endif /* CONFIG_INCLUDE_RESET_VECTOR */
/* use ABI name of registers for the sake of simplicity */
#ifdef CONFIG_THREAD_LOCAL_STORAGE
/*
* Allocate a TLS area on the current stack, initialize it via
* arch_riscv_early_tls_stack_update(), ... | riscv | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/reset.S | Apache-2.0 | 729110c12fec2cf1843e39f19f88a86c7c676513 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/729110c12fec2cf1843e39f19f88a86c7c676513/arch/riscv/core/reset.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/riscv/core/reset.S:3 | #ifdef CONFIG_FPU
/*
* Enable floating-point.
*/
li t0, MSTATUS_FS_INIT
csrs mstatus, t0
/*
* Floating-point rounding mode set to IEEE-754 default, and clear
* all exception flags.
*/
fscsr zero
#endif
#ifdef CONFIG_INIT_STACKS
/* Pre-populate all bytes in z_interrupt_stacks with 0xAA */
la t0, z_int... | riscv | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/reset.S | Apache-2.0 | 729110c12fec2cf1843e39f19f88a86c7c676513 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/729110c12fec2cf1843e39f19f88a86c7c676513/arch/riscv/core/reset.S | 81 | 140 |
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