system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
__device__ int smallerDst (int a, int b){
if(a < b){
return a;
}
else {
return b;
}
} /*ending of device funtion */
__global__ void strongestNeighborScan_gpu(int * src, int * oldDst, int * newDst, int * oldWeight, int * newWeight, int * madeChanges, int distance, int numEdges) {
/*YOUR CODE HERE*/
int i;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int total_threads = blockDim.x * gridDim.x;
for(i = tid; i < numEdges; i += total_threads){
if(tid >= numEdges){
return;
}
if (src[i] == src[i-distance]){ /* if the element is in the same segment */
if(oldWeight[i] == oldWeight[i-distance]){ /*if the two weights are equal */
newDst[i] = smallerDst (oldDst[i], oldDst[i-distance]);
newWeight[i] = oldWeight[i];
} /*second if statement */
else {
newWeight[i] = max (oldWeight[i], oldWeight[i-distance]);
if (newWeight[i] == oldWeight[i])
newDst[i] = oldDst[i];
if (newWeight[i] == oldWeight[i-distance])
newDst[i] = oldDst[i-distance];
}
} /*first if statement */
else {
newWeight[i] = oldWeight[i]; /* when the element is in a different segment, it takes its old weight as the new weight */
newDst[i] = oldDst[i];
}
if(oldDst[i] != newDst[i]){
* madeChanges = 1;
}
} /*ending of for loop */
} /*ending of main */ | .file "tmpxft_00014d4d_00000000-6_strongestNeighborScan.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10smallerDstii
.type _Z10smallerDstii, @function
_Z10smallerDstii:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z10smallerDstii, .-_Z10smallerDstii
.globl _Z57__device_stub__Z25strongestNeighborScan_gpuPiS_S_S_S_S_iiPiS_S_S_S_S_ii
.type _Z57__device_stub__Z25strongestNeighborScan_gpuPiS_S_S_S_S_iiPiS_S_S_S_S_ii, @function
_Z57__device_stub__Z25strongestNeighborScan_gpuPiS_S_S_S_S_iiPiS_S_S_S_S_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z57__device_stub__Z25strongestNeighborScan_gpuPiS_S_S_S_S_iiPiS_S_S_S_S_ii, .-_Z57__device_stub__Z25strongestNeighborScan_gpuPiS_S_S_S_S_iiPiS_S_S_S_S_ii
.globl _Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii
.type _Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii, @function
_Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z57__device_stub__Z25strongestNeighborScan_gpuPiS_S_S_S_S_iiPiS_S_S_S_S_ii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii, .-_Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
__device__ int smallerDst (int a, int b){
if(a < b){
return a;
}
else {
return b;
}
} /*ending of device funtion */
__global__ void strongestNeighborScan_gpu(int * src, int * oldDst, int * newDst, int * oldWeight, int * newWeight, int * madeChanges, int distance, int numEdges) {
/*YOUR CODE HERE*/
int i;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int total_threads = blockDim.x * gridDim.x;
for(i = tid; i < numEdges; i += total_threads){
if(tid >= numEdges){
return;
}
if (src[i] == src[i-distance]){ /* if the element is in the same segment */
if(oldWeight[i] == oldWeight[i-distance]){ /*if the two weights are equal */
newDst[i] = smallerDst (oldDst[i], oldDst[i-distance]);
newWeight[i] = oldWeight[i];
} /*second if statement */
else {
newWeight[i] = max (oldWeight[i], oldWeight[i-distance]);
if (newWeight[i] == oldWeight[i])
newDst[i] = oldDst[i];
if (newWeight[i] == oldWeight[i-distance])
newDst[i] = oldDst[i-distance];
}
} /*first if statement */
else {
newWeight[i] = oldWeight[i]; /* when the element is in a different segment, it takes its old weight as the new weight */
newDst[i] = oldDst[i];
}
if(oldDst[i] != newDst[i]){
* madeChanges = 1;
}
} /*ending of for loop */
} /*ending of main */ | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__device__ int smallerDst (int a, int b){
if(a < b){
return a;
}
else {
return b;
}
} /*ending of device funtion */
__global__ void strongestNeighborScan_gpu(int * src, int * oldDst, int * newDst, int * oldWeight, int * newWeight, int * madeChanges, int distance, int numEdges) {
/*YOUR CODE HERE*/
int i;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int total_threads = blockDim.x * gridDim.x;
for(i = tid; i < numEdges; i += total_threads){
if(tid >= numEdges){
return;
}
if (src[i] == src[i-distance]){ /* if the element is in the same segment */
if(oldWeight[i] == oldWeight[i-distance]){ /*if the two weights are equal */
newDst[i] = smallerDst (oldDst[i], oldDst[i-distance]);
newWeight[i] = oldWeight[i];
} /*second if statement */
else {
newWeight[i] = max (oldWeight[i], oldWeight[i-distance]);
if (newWeight[i] == oldWeight[i])
newDst[i] = oldDst[i];
if (newWeight[i] == oldWeight[i-distance])
newDst[i] = oldDst[i-distance];
}
} /*first if statement */
else {
newWeight[i] = oldWeight[i]; /* when the element is in a different segment, it takes its old weight as the new weight */
newDst[i] = oldDst[i];
}
if(oldDst[i] != newDst[i]){
* madeChanges = 1;
}
} /*ending of for loop */
} /*ending of main */ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__device__ int smallerDst (int a, int b){
if(a < b){
return a;
}
else {
return b;
}
} /*ending of device funtion */
__global__ void strongestNeighborScan_gpu(int * src, int * oldDst, int * newDst, int * oldWeight, int * newWeight, int * madeChanges, int distance, int numEdges) {
/*YOUR CODE HERE*/
int i;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int total_threads = blockDim.x * gridDim.x;
for(i = tid; i < numEdges; i += total_threads){
if(tid >= numEdges){
return;
}
if (src[i] == src[i-distance]){ /* if the element is in the same segment */
if(oldWeight[i] == oldWeight[i-distance]){ /*if the two weights are equal */
newDst[i] = smallerDst (oldDst[i], oldDst[i-distance]);
newWeight[i] = oldWeight[i];
} /*second if statement */
else {
newWeight[i] = max (oldWeight[i], oldWeight[i-distance]);
if (newWeight[i] == oldWeight[i])
newDst[i] = oldDst[i];
if (newWeight[i] == oldWeight[i-distance])
newDst[i] = oldDst[i-distance];
}
} /*first if statement */
else {
newWeight[i] = oldWeight[i]; /* when the element is in a different segment, it takes its old weight as the new weight */
newDst[i] = oldDst[i];
}
if(oldDst[i] != newDst[i]){
* madeChanges = 1;
}
} /*ending of for loop */
} /*ending of main */ | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii
.globl _Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii
.p2align 8
.type _Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii,@function
_Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x44
s_load_b32 s16, s[0:1], 0x34
s_add_u32 s2, s0, 56
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s14, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s14, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s16, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_19
s_load_b32 s18, s[0:1], 0x30
s_load_b32 s13, s[2:3], 0x0
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b128 s[0:3], s[0:1], 0x20
v_ashrrev_i32_e32 v2, 31, v1
v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v13, 1
s_mov_b32 s17, 0
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_ashr_i32 s19, s18, 31
s_mul_i32 s12, s13, s14
s_lshl_b64 s[22:23], s[18:19], 2
s_add_i32 s15, s15, s13
s_sub_u32 s18, s4, s22
s_subb_u32 s19, s5, s23
s_ashr_i32 s13, s12, 31
v_mad_u64_u32 v[5:6], null, s15, s14, v[0:1]
s_lshl_b64 s[14:15], s[12:13], 2
s_sub_u32 s13, s10, s22
s_subb_u32 s20, s11, s23
s_sub_u32 s21, s6, s22
s_subb_u32 s22, s7, s23
s_xor_b32 s23, vcc_lo, -1
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s24
v_cmp_le_i32_e32 vcc_lo, s16, v5
v_add_nc_u32_e32 v1, s12, v1
v_add_nc_u32_e32 v5, s12, v5
s_or_b32 s24, s23, vcc_lo
v_add_co_u32 v3, vcc_lo, v3, s14
v_add_co_ci_u32_e32 v4, vcc_lo, s15, v4, vcc_lo
s_and_b32 s24, exec_lo, s24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s17, s24, s17
s_and_not1_b32 exec_lo, exec_lo, s17
s_cbranch_execz .LBB0_19
.LBB0_3:
v_add_co_u32 v6, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v8, vcc_lo, s18, v3
v_add_co_ci_u32_e32 v9, vcc_lo, s19, v4, vcc_lo
v_ashrrev_i32_e32 v2, 31, v1
s_clause 0x1
global_load_b32 v6, v[6:7], off
global_load_b32 v7, v[8:9], off
v_add_co_u32 v8, vcc_lo, s10, v3
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v4, vcc_lo
s_mov_b32 s24, 0
global_load_b32 v0, v[8:9], off
s_waitcnt vmcnt(1)
v_cmp_ne_u32_e32 vcc_lo, v6, v7
s_and_saveexec_b32 s25, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s25, exec_lo, s25
s_cbranch_execz .LBB0_5
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_add_co_u32 v8, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v4, vcc_lo
s_mov_b32 s24, exec_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[8:9], v0, off
.LBB0_5:
s_or_saveexec_b32 s25, s25
v_dual_mov_b32 v11, s9 :: v_dual_mov_b32 v10, s8
s_xor_b32 exec_lo, exec_lo, s25
s_cbranch_execz .LBB0_15
v_add_co_u32 v10, vcc_lo, s13, v3
v_add_co_ci_u32_e32 v11, vcc_lo, s20, v4, vcc_lo
s_mov_b32 s27, s24
s_mov_b32 s26, exec_lo
global_load_b32 v14, v[10:11], off
s_waitcnt vmcnt(0)
v_cmpx_ne_u32_e64 v0, v14
s_xor_b32 s26, exec_lo, s26
s_cbranch_execz .LBB0_12
v_add_co_u32 v6, vcc_lo, s0, v3
v_max_i32_e32 v0, v0, v14
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v4, vcc_lo
s_mov_b32 s27, exec_lo
global_store_b32 v[6:7], v0, off
global_load_b32 v8, v[8:9], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e64 v0, v8
s_cbranch_execz .LBB0_9
v_add_co_u32 v8, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v4, vcc_lo
global_load_b32 v0, v[8:9], off
v_add_co_u32 v8, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v4, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[8:9], v0, off
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s27
global_load_b32 v0, v[6:7], off
global_load_b32 v6, v[10:11], off
s_mov_b32 s27, s24
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v0, v6
s_and_saveexec_b32 s28, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s28, exec_lo, s28
v_add_co_u32 v6, vcc_lo, s21, v3
v_add_co_ci_u32_e32 v7, vcc_lo, s22, v4, vcc_lo
s_or_b32 s27, s24, exec_lo
s_or_b32 exec_lo, exec_lo, s28
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s28, s24, exec_lo
s_and_b32 s27, s27, exec_lo
s_or_b32 s27, s28, s27
.LBB0_12:
s_or_saveexec_b32 s26, s26
v_dual_mov_b32 v11, s9 :: v_dual_mov_b32 v10, s8
s_xor_b32 exec_lo, exec_lo, s26
s_cbranch_execz .LBB0_14
v_add_co_u32 v6, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v8, vcc_lo, s21, v3
v_add_co_ci_u32_e32 v9, vcc_lo, s22, v4, vcc_lo
v_dual_mov_b32 v11, s1 :: v_dual_mov_b32 v10, s0
s_clause 0x1
global_load_b32 v0, v[6:7], off
global_load_b32 v8, v[8:9], off
v_lshlrev_b64 v[6:7], 2, v[1:2]
s_or_b32 s27, s27, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s10, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
s_waitcnt vmcnt(0)
v_min_i32_e32 v0, v0, v8
v_add_co_u32 v8, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v4, vcc_lo
global_store_b32 v[8:9], v0, off
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s26
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s24, s24, exec_lo
s_and_b32 s26, s27, exec_lo
s_or_b32 s24, s24, s26
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s25
s_and_saveexec_b32 s25, s24
s_cbranch_execz .LBB0_17
global_load_b32 v0, v[6:7], off
v_add_co_u32 v6, vcc_lo, v10, v3
v_add_co_ci_u32_e32 v7, vcc_lo, v11, v4, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[6:7], v0, off
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s25
v_add_co_u32 v6, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v8, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v4, vcc_lo
s_mov_b32 s24, exec_lo
global_load_b32 v0, v[6:7], off
global_load_b32 v2, v[8:9], off
s_waitcnt vmcnt(0)
v_cmpx_ne_u32_e64 v0, v2
s_cbranch_execz .LBB0_2
global_store_b32 v12, v13, s[2:3]
s_branch .LBB0_2
.LBB0_19:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 29
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii, .Lfunc_end0-_Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 31
.sgpr_spill_count: 0
.symbol: _Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__device__ int smallerDst (int a, int b){
if(a < b){
return a;
}
else {
return b;
}
} /*ending of device funtion */
__global__ void strongestNeighborScan_gpu(int * src, int * oldDst, int * newDst, int * oldWeight, int * newWeight, int * madeChanges, int distance, int numEdges) {
/*YOUR CODE HERE*/
int i;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int total_threads = blockDim.x * gridDim.x;
for(i = tid; i < numEdges; i += total_threads){
if(tid >= numEdges){
return;
}
if (src[i] == src[i-distance]){ /* if the element is in the same segment */
if(oldWeight[i] == oldWeight[i-distance]){ /*if the two weights are equal */
newDst[i] = smallerDst (oldDst[i], oldDst[i-distance]);
newWeight[i] = oldWeight[i];
} /*second if statement */
else {
newWeight[i] = max (oldWeight[i], oldWeight[i-distance]);
if (newWeight[i] == oldWeight[i])
newDst[i] = oldDst[i];
if (newWeight[i] == oldWeight[i-distance])
newDst[i] = oldDst[i-distance];
}
} /*first if statement */
else {
newWeight[i] = oldWeight[i]; /* when the element is in a different segment, it takes its old weight as the new weight */
newDst[i] = oldDst[i];
}
if(oldDst[i] != newDst[i]){
* madeChanges = 1;
}
} /*ending of for loop */
} /*ending of main */ | .text
.file "strongestNeighborScan.hip"
.globl _Z40__device_stub__strongestNeighborScan_gpuPiS_S_S_S_S_ii # -- Begin function _Z40__device_stub__strongestNeighborScan_gpuPiS_S_S_S_S_ii
.p2align 4, 0x90
.type _Z40__device_stub__strongestNeighborScan_gpuPiS_S_S_S_S_ii,@function
_Z40__device_stub__strongestNeighborScan_gpuPiS_S_S_S_S_ii: # @_Z40__device_stub__strongestNeighborScan_gpuPiS_S_S_S_S_ii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z40__device_stub__strongestNeighborScan_gpuPiS_S_S_S_S_ii, .Lfunc_end0-_Z40__device_stub__strongestNeighborScan_gpuPiS_S_S_S_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii,@object # @_Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii
.section .rodata,"a",@progbits
.globl _Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii
.p2align 3, 0x0
_Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii:
.quad _Z40__device_stub__strongestNeighborScan_gpuPiS_S_S_S_S_ii
.size _Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii"
.size .L__unnamed_1, 44
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__strongestNeighborScan_gpuPiS_S_S_S_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x194], PT ; /* 0x0000650000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R10, -R0.reuse, c[0x0][0x190], RZ ; /* 0x00006400000a7a10 */
/* 0x040fe20007ffe1ff */
/*0070*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff077624 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD.WIDE R2, R0, 0x4, RZ ; /* 0x0000000400027825 */
/* 0x000fc800078e02ff */
/*00a0*/ IMAD.WIDE R10, R10, 0x4, RZ ; /* 0x000000040a0a7825 */
/* 0x000fc800078e02ff */
/*00b0*/ IMAD R7, R7, c[0x0][0xc], RZ ; /* 0x0000030007077a24 */
/* 0x000fe200078e02ff */
/*00c0*/ IADD3 R9, P0, RZ, -R10, RZ ; /* 0x8000000aff097210 */
/* 0x000fc60007f1e0ff */
/*00d0*/ IMAD.MOV R4, RZ, RZ, -R7 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0a07 */
/*00e0*/ IMAD.X R11, RZ, RZ, ~R11, P0 ; /* 0x000000ffff0b7224 */
/* 0x000fe400000e0e0b */
/*00f0*/ IMAD.WIDE R4, R4, 0x4, RZ ; /* 0x0000000404047825 */
/* 0x000fc800078e02ff */
/*0100*/ IADD3 R16, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002107a10 */
/* 0x000fe40007f1e0ff */
/*0110*/ IADD3 R14, P1, R9, c[0x0][0x160], RZ ; /* 0x00005800090e7a10 */
/* 0x000fe40007f3e0ff */
/*0120*/ IADD3.X R17, R3, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590003117a10 */
/* 0x000fe400007fe4ff */
/*0130*/ IADD3.X R15, R11, c[0x0][0x164], RZ, P1, !PT ; /* 0x000059000b0f7a10 */
/* 0x000fc80000ffe4ff */
/*0140*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ea8000c1e1900 */
/*0150*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea2000c1e1900 */
/*0160*/ IADD3 R22, P0, R2, c[0x0][0x178], RZ ; /* 0x00005e0002167a10 */
/* 0x000fc80007f1e0ff */
/*0170*/ IADD3.X R23, R3, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f0003177a10 */
/* 0x000fca00007fe4ff */
/*0180*/ LDG.E R25, [R22.64] ; /* 0x0000000416197981 */
/* 0x000ee2000c1e1900 */
/*0190*/ IADD3 R20, P1, R2.reuse, c[0x0][0x180], RZ ; /* 0x0000600002147a10 */
/* 0x040fe40007f3e0ff */
/*01a0*/ IADD3 R12, P2, R2, c[0x0][0x168], RZ ; /* 0x00005a00020c7a10 */
/* 0x000fe40007f5e0ff */
/*01b0*/ IADD3.X R21, R3.reuse, c[0x0][0x184], RZ, P1, !PT ; /* 0x0000610003157a10 */
/* 0x040fe40000ffe4ff */
/*01c0*/ IADD3.X R13, R3, c[0x0][0x16c], RZ, P2, !PT ; /* 0x00005b00030d7a10 */
/* 0x000fe400017fe4ff */
/*01d0*/ ISETP.NE.AND P0, PT, R17, R14, PT ; /* 0x0000000e1100720c */
/* 0x004fda0003f05270 */
/*01e0*/ @P0 STG.E [R20.64], R25 ; /* 0x0000001914000986 */
/* 0x0081e8000c101904 */
/*01f0*/ @P0 LDG.E R19, [R12.64] ; /* 0x000000040c130981 */
/* 0x000ea2000c1e1900 */
/*0200*/ IADD3 R14, P1, R2, c[0x0][0x170], RZ ; /* 0x00005c00020e7a10 */
/* 0x000fc80007f3e0ff */
/*0210*/ IADD3.X R15, R3, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d00030f7a10 */
/* 0x000fe20000ffe4ff */
/*0220*/ BSSY B0, 0x400 ; /* 0x000001d000007945 */
/* 0x000fe80003800000 */
/*0230*/ @P0 STG.E [R14.64], R19 ; /* 0x000000130e000986 */
/* 0x0041e2000c101904 */
/*0240*/ @P0 BRA 0x3f0 ; /* 0x000001a000000947 */
/* 0x000fea0003800000 */
/*0250*/ IADD3 R18, P0, R9, c[0x0][0x178], RZ ; /* 0x00005e0009127a10 */
/* 0x000fc80007f1e0ff */
/*0260*/ IADD3.X R19, R11, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f000b137a10 */
/* 0x001fca00007fe4ff */
/*0270*/ LDG.E R6, [R18.64] ; /* 0x0000000412067981 */
/* 0x000ea2000c1e1900 */
/*0280*/ IADD3 R16, P1, R9, c[0x0][0x168], RZ ; /* 0x00005a0009107a10 */
/* 0x000fc80007f3e0ff */
/*0290*/ IADD3.X R17, R11, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b000b117a10 */
/* 0x000fe40000ffe4ff */
/*02a0*/ ISETP.NE.AND P0, PT, R25, R6, PT ; /* 0x000000061900720c */
/* 0x004fda0003f05270 */
/*02b0*/ @!P0 BRA 0x390 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*02c0*/ IMNMX R25, R25, R6, !PT ; /* 0x0000000619197217 */
/* 0x000fca0007800200 */
/*02d0*/ STG.E [R20.64], R25 ; /* 0x0000001914007986 */
/* 0x0001e8000c101904 */
/*02e0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000ea4000c1e1900 */
/*02f0*/ ISETP.NE.AND P0, PT, R25, R22, PT ; /* 0x000000161900720c */
/* 0x004fda0003f05270 */
/*0300*/ @!P0 LDG.E R27, [R12.64] ; /* 0x000000040c1b8981 */
/* 0x000ea8000c1e1900 */
/*0310*/ @!P0 STG.E [R14.64], R27 ; /* 0x0000001b0e008986 */
/* 0x0043e8000c101904 */
/*0320*/ @!P0 LDG.E R25, [R20.64] ; /* 0x0000000414198981 */
/* 0x001ea8000c1e1900 */
/*0330*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea4000c1e1900 */
/*0340*/ ISETP.NE.AND P0, PT, R25, R18, PT ; /* 0x000000121900720c */
/* 0x004fda0003f05270 */
/*0350*/ @P0 BRA 0x3f0 ; /* 0x0000009000000947 */
/* 0x000fea0003800000 */
/*0360*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x002ea8000c1e1900 */
/*0370*/ STG.E [R14.64], R17 ; /* 0x000000110e007986 */
/* 0x0041e2000c101904 */
/*0380*/ BRA 0x3f0 ; /* 0x0000006000007947 */
/* 0x000fea0003800000 */
/*0390*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ea8000c1e1900 */
/*03a0*/ LDG.E R6, [R12.64] ; /* 0x000000040c067981 */
/* 0x000ea4000c1e1900 */
/*03b0*/ IMNMX R19, R6, R17, PT ; /* 0x0000001106137217 */
/* 0x004fca0003800200 */
/*03c0*/ STG.E [R14.64], R19 ; /* 0x000000130e007986 */
/* 0x0001e8000c101904 */
/*03d0*/ LDG.E R23, [R22.64] ; /* 0x0000000416177981 */
/* 0x000ea8000c1e1900 */
/*03e0*/ STG.E [R20.64], R23 ; /* 0x0000001714007986 */
/* 0x0041e4000c101904 */
/*03f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0400*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea8000c1e1900 */
/*0410*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x001ea2000c1e1900 */
/*0420*/ IMAD.IADD R0, R7.reuse, 0x1, R0 ; /* 0x0000000107007824 */
/* 0x040fe200078e0200 */
/*0430*/ IADD3 R9, P1, -R4, R9, RZ ; /* 0x0000000904097210 */
/* 0x000fe20007f3e1ff */
/*0440*/ IMAD.WIDE R2, R7, 0x4, R2 ; /* 0x0000000407027825 */
/* 0x000fc800078e0202 */
/*0450*/ IMAD.X R11, R11, 0x1, ~R5, P1 ; /* 0x000000010b0b7824 */
/* 0x000fe200008e0e05 */
/*0460*/ ISETP.NE.AND P0, PT, R12, R15, PT ; /* 0x0000000f0c00720c */
/* 0x004fda0003f05270 */
/*0470*/ @P0 IMAD.MOV.U32 R19, RZ, RZ, 0x1 ; /* 0x00000001ff130424 */
/* 0x000fe400078e00ff */
/*0480*/ @P0 IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff100624 */
/* 0x000fe400078e00ff */
/*0490*/ @P0 IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff110624 */
/* 0x000fca00078e00ff */
/*04a0*/ @P0 STG.E [R16.64], R19 ; /* 0x0000001310000986 */
/* 0x0001e2000c101904 */
/*04b0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x194], PT ; /* 0x0000650000007a0c */
/* 0x000fda0003f06270 */
/*04c0*/ @!P0 BRA 0x100 ; /* 0xfffffc3000008947 */
/* 0x001fea000383ffff */
/*04d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04e0*/ BRA 0x4e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii
.globl _Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii
.p2align 8
.type _Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii,@function
_Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x44
s_load_b32 s16, s[0:1], 0x34
s_add_u32 s2, s0, 56
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s14, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s14, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s16, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_19
s_load_b32 s18, s[0:1], 0x30
s_load_b32 s13, s[2:3], 0x0
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b128 s[0:3], s[0:1], 0x20
v_ashrrev_i32_e32 v2, 31, v1
v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v13, 1
s_mov_b32 s17, 0
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_ashr_i32 s19, s18, 31
s_mul_i32 s12, s13, s14
s_lshl_b64 s[22:23], s[18:19], 2
s_add_i32 s15, s15, s13
s_sub_u32 s18, s4, s22
s_subb_u32 s19, s5, s23
s_ashr_i32 s13, s12, 31
v_mad_u64_u32 v[5:6], null, s15, s14, v[0:1]
s_lshl_b64 s[14:15], s[12:13], 2
s_sub_u32 s13, s10, s22
s_subb_u32 s20, s11, s23
s_sub_u32 s21, s6, s22
s_subb_u32 s22, s7, s23
s_xor_b32 s23, vcc_lo, -1
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s24
v_cmp_le_i32_e32 vcc_lo, s16, v5
v_add_nc_u32_e32 v1, s12, v1
v_add_nc_u32_e32 v5, s12, v5
s_or_b32 s24, s23, vcc_lo
v_add_co_u32 v3, vcc_lo, v3, s14
v_add_co_ci_u32_e32 v4, vcc_lo, s15, v4, vcc_lo
s_and_b32 s24, exec_lo, s24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s17, s24, s17
s_and_not1_b32 exec_lo, exec_lo, s17
s_cbranch_execz .LBB0_19
.LBB0_3:
v_add_co_u32 v6, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v8, vcc_lo, s18, v3
v_add_co_ci_u32_e32 v9, vcc_lo, s19, v4, vcc_lo
v_ashrrev_i32_e32 v2, 31, v1
s_clause 0x1
global_load_b32 v6, v[6:7], off
global_load_b32 v7, v[8:9], off
v_add_co_u32 v8, vcc_lo, s10, v3
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v4, vcc_lo
s_mov_b32 s24, 0
global_load_b32 v0, v[8:9], off
s_waitcnt vmcnt(1)
v_cmp_ne_u32_e32 vcc_lo, v6, v7
s_and_saveexec_b32 s25, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s25, exec_lo, s25
s_cbranch_execz .LBB0_5
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_add_co_u32 v8, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v4, vcc_lo
s_mov_b32 s24, exec_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[8:9], v0, off
.LBB0_5:
s_or_saveexec_b32 s25, s25
v_dual_mov_b32 v11, s9 :: v_dual_mov_b32 v10, s8
s_xor_b32 exec_lo, exec_lo, s25
s_cbranch_execz .LBB0_15
v_add_co_u32 v10, vcc_lo, s13, v3
v_add_co_ci_u32_e32 v11, vcc_lo, s20, v4, vcc_lo
s_mov_b32 s27, s24
s_mov_b32 s26, exec_lo
global_load_b32 v14, v[10:11], off
s_waitcnt vmcnt(0)
v_cmpx_ne_u32_e64 v0, v14
s_xor_b32 s26, exec_lo, s26
s_cbranch_execz .LBB0_12
v_add_co_u32 v6, vcc_lo, s0, v3
v_max_i32_e32 v0, v0, v14
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v4, vcc_lo
s_mov_b32 s27, exec_lo
global_store_b32 v[6:7], v0, off
global_load_b32 v8, v[8:9], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e64 v0, v8
s_cbranch_execz .LBB0_9
v_add_co_u32 v8, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v4, vcc_lo
global_load_b32 v0, v[8:9], off
v_add_co_u32 v8, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v4, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[8:9], v0, off
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s27
global_load_b32 v0, v[6:7], off
global_load_b32 v6, v[10:11], off
s_mov_b32 s27, s24
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v0, v6
s_and_saveexec_b32 s28, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s28, exec_lo, s28
v_add_co_u32 v6, vcc_lo, s21, v3
v_add_co_ci_u32_e32 v7, vcc_lo, s22, v4, vcc_lo
s_or_b32 s27, s24, exec_lo
s_or_b32 exec_lo, exec_lo, s28
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s28, s24, exec_lo
s_and_b32 s27, s27, exec_lo
s_or_b32 s27, s28, s27
.LBB0_12:
s_or_saveexec_b32 s26, s26
v_dual_mov_b32 v11, s9 :: v_dual_mov_b32 v10, s8
s_xor_b32 exec_lo, exec_lo, s26
s_cbranch_execz .LBB0_14
v_add_co_u32 v6, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v8, vcc_lo, s21, v3
v_add_co_ci_u32_e32 v9, vcc_lo, s22, v4, vcc_lo
v_dual_mov_b32 v11, s1 :: v_dual_mov_b32 v10, s0
s_clause 0x1
global_load_b32 v0, v[6:7], off
global_load_b32 v8, v[8:9], off
v_lshlrev_b64 v[6:7], 2, v[1:2]
s_or_b32 s27, s27, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s10, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
s_waitcnt vmcnt(0)
v_min_i32_e32 v0, v0, v8
v_add_co_u32 v8, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v4, vcc_lo
global_store_b32 v[8:9], v0, off
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s26
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s24, s24, exec_lo
s_and_b32 s26, s27, exec_lo
s_or_b32 s24, s24, s26
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s25
s_and_saveexec_b32 s25, s24
s_cbranch_execz .LBB0_17
global_load_b32 v0, v[6:7], off
v_add_co_u32 v6, vcc_lo, v10, v3
v_add_co_ci_u32_e32 v7, vcc_lo, v11, v4, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[6:7], v0, off
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s25
v_add_co_u32 v6, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v8, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v4, vcc_lo
s_mov_b32 s24, exec_lo
global_load_b32 v0, v[6:7], off
global_load_b32 v2, v[8:9], off
s_waitcnt vmcnt(0)
v_cmpx_ne_u32_e64 v0, v2
s_cbranch_execz .LBB0_2
global_store_b32 v12, v13, s[2:3]
s_branch .LBB0_2
.LBB0_19:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 29
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii, .Lfunc_end0-_Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 31
.sgpr_spill_count: 0
.symbol: _Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00014d4d_00000000-6_strongestNeighborScan.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10smallerDstii
.type _Z10smallerDstii, @function
_Z10smallerDstii:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z10smallerDstii, .-_Z10smallerDstii
.globl _Z57__device_stub__Z25strongestNeighborScan_gpuPiS_S_S_S_S_iiPiS_S_S_S_S_ii
.type _Z57__device_stub__Z25strongestNeighborScan_gpuPiS_S_S_S_S_iiPiS_S_S_S_S_ii, @function
_Z57__device_stub__Z25strongestNeighborScan_gpuPiS_S_S_S_S_iiPiS_S_S_S_S_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z57__device_stub__Z25strongestNeighborScan_gpuPiS_S_S_S_S_iiPiS_S_S_S_S_ii, .-_Z57__device_stub__Z25strongestNeighborScan_gpuPiS_S_S_S_S_iiPiS_S_S_S_S_ii
.globl _Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii
.type _Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii, @function
_Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z57__device_stub__Z25strongestNeighborScan_gpuPiS_S_S_S_S_iiPiS_S_S_S_S_ii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii, .-_Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "strongestNeighborScan.hip"
.globl _Z40__device_stub__strongestNeighborScan_gpuPiS_S_S_S_S_ii # -- Begin function _Z40__device_stub__strongestNeighborScan_gpuPiS_S_S_S_S_ii
.p2align 4, 0x90
.type _Z40__device_stub__strongestNeighborScan_gpuPiS_S_S_S_S_ii,@function
_Z40__device_stub__strongestNeighborScan_gpuPiS_S_S_S_S_ii: # @_Z40__device_stub__strongestNeighborScan_gpuPiS_S_S_S_S_ii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z40__device_stub__strongestNeighborScan_gpuPiS_S_S_S_S_ii, .Lfunc_end0-_Z40__device_stub__strongestNeighborScan_gpuPiS_S_S_S_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii,@object # @_Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii
.section .rodata,"a",@progbits
.globl _Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii
.p2align 3, 0x0
_Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii:
.quad _Z40__device_stub__strongestNeighborScan_gpuPiS_S_S_S_S_ii
.size _Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii"
.size .L__unnamed_1, 44
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__strongestNeighborScan_gpuPiS_S_S_S_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "KernelMath.cuh"
#include <stdio.h>
__global__ void addKernel(int* c, const int* a, const int* b, const int N)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < N) {
c[tid] = a[tid] + b[tid];
}
}
__global__ void subKernel(int* c, const int* a, const int* b, const int N)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < N) {
c[tid] = a[tid] - b[tid];
}
}
__global__ void mulKernel(int* c, const int* a, const int* b, const int N)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < N) {
c[tid] = a[tid] * b[tid];
}
}
__global__ void divKernel(int* c, const int* a, const int* b, const int N)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < N) {
c[tid] = a[tid] / b[tid];
}
}
__global__ void mul2DKernel(int* c, const int* a, const int* b, int widthA, int heightA)
{
int aROW = blockIdx.y * blockDim.y + threadIdx.y;
int bCOL = blockIdx.x * blockDim.x + threadIdx.x;
// Checking if the ROW/COL exceed the actual number of ROW/COL
// widthA = heightB
// heightA = widthB
if (aROW < widthA && bCOL < heightA) {
int dotProduct = 0;
for (int k = 0; k < widthA; k++) {
printf("Row %d, Col %d, loop num %d, A index %d, B index %d\n", aROW, bCOL, k, (aROW * widthA + k), (k * heightA + bCOL));
dotProduct += a[aROW * widthA + k] * b[k * heightA + bCOL]; // widthA = heightB
}
c[aROW * heightA + bCOL] = dotProduct;
printf("Output value at row %d, col %d is %d\n", aROW, bCOL, c[aROW * heightA + bCOL]);
}
} | .file "tmpxft_000a5c82_00000000-6_KernelMath.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z9addKernelPiPKiS1_iPiPKiS1_i
.type _Z35__device_stub__Z9addKernelPiPKiS1_iPiPKiS1_i, @function
_Z35__device_stub__Z9addKernelPiPKiS1_iPiPKiS1_i:
.LFB2081:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addKernelPiPKiS1_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z35__device_stub__Z9addKernelPiPKiS1_iPiPKiS1_i, .-_Z35__device_stub__Z9addKernelPiPKiS1_iPiPKiS1_i
.globl _Z9addKernelPiPKiS1_i
.type _Z9addKernelPiPKiS1_i, @function
_Z9addKernelPiPKiS1_i:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z9addKernelPiPKiS1_iPiPKiS1_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z9addKernelPiPKiS1_i, .-_Z9addKernelPiPKiS1_i
.globl _Z35__device_stub__Z9subKernelPiPKiS1_iPiPKiS1_i
.type _Z35__device_stub__Z9subKernelPiPKiS1_iPiPKiS1_i, @function
_Z35__device_stub__Z9subKernelPiPKiS1_iPiPKiS1_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9subKernelPiPKiS1_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z35__device_stub__Z9subKernelPiPKiS1_iPiPKiS1_i, .-_Z35__device_stub__Z9subKernelPiPKiS1_iPiPKiS1_i
.globl _Z9subKernelPiPKiS1_i
.type _Z9subKernelPiPKiS1_i, @function
_Z9subKernelPiPKiS1_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z9subKernelPiPKiS1_iPiPKiS1_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9subKernelPiPKiS1_i, .-_Z9subKernelPiPKiS1_i
.globl _Z35__device_stub__Z9mulKernelPiPKiS1_iPiPKiS1_i
.type _Z35__device_stub__Z9mulKernelPiPKiS1_iPiPKiS1_i, @function
_Z35__device_stub__Z9mulKernelPiPKiS1_iPiPKiS1_i:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9mulKernelPiPKiS1_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z35__device_stub__Z9mulKernelPiPKiS1_iPiPKiS1_i, .-_Z35__device_stub__Z9mulKernelPiPKiS1_iPiPKiS1_i
.globl _Z9mulKernelPiPKiS1_i
.type _Z9mulKernelPiPKiS1_i, @function
_Z9mulKernelPiPKiS1_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z9mulKernelPiPKiS1_iPiPKiS1_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z9mulKernelPiPKiS1_i, .-_Z9mulKernelPiPKiS1_i
.globl _Z35__device_stub__Z9divKernelPiPKiS1_iPiPKiS1_i
.type _Z35__device_stub__Z9divKernelPiPKiS1_iPiPKiS1_i, @function
_Z35__device_stub__Z9divKernelPiPKiS1_iPiPKiS1_i:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9divKernelPiPKiS1_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z35__device_stub__Z9divKernelPiPKiS1_iPiPKiS1_i, .-_Z35__device_stub__Z9divKernelPiPKiS1_iPiPKiS1_i
.globl _Z9divKernelPiPKiS1_i
.type _Z9divKernelPiPKiS1_i, @function
_Z9divKernelPiPKiS1_i:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z9divKernelPiPKiS1_iPiPKiS1_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z9divKernelPiPKiS1_i, .-_Z9divKernelPiPKiS1_i
.globl _Z39__device_stub__Z11mul2DKernelPiPKiS1_iiPiPKiS1_ii
.type _Z39__device_stub__Z11mul2DKernelPiPKiS1_iiPiPKiS1_ii, @function
_Z39__device_stub__Z11mul2DKernelPiPKiS1_iiPiPKiS1_ii:
.LFB2089:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11mul2DKernelPiPKiS1_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z39__device_stub__Z11mul2DKernelPiPKiS1_iiPiPKiS1_ii, .-_Z39__device_stub__Z11mul2DKernelPiPKiS1_iiPiPKiS1_ii
.globl _Z11mul2DKernelPiPKiS1_ii
.type _Z11mul2DKernelPiPKiS1_ii, @function
_Z11mul2DKernelPiPKiS1_ii:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z11mul2DKernelPiPKiS1_iiPiPKiS1_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z11mul2DKernelPiPKiS1_ii, .-_Z11mul2DKernelPiPKiS1_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11mul2DKernelPiPKiS1_ii"
.LC1:
.string "_Z9divKernelPiPKiS1_i"
.LC2:
.string "_Z9mulKernelPiPKiS1_i"
.LC3:
.string "_Z9subKernelPiPKiS1_i"
.LC4:
.string "_Z9addKernelPiPKiS1_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11mul2DKernelPiPKiS1_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9divKernelPiPKiS1_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z9mulKernelPiPKiS1_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9subKernelPiPKiS1_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addKernelPiPKiS1_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "KernelMath.cuh"
#include <stdio.h>
__global__ void addKernel(int* c, const int* a, const int* b, const int N)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < N) {
c[tid] = a[tid] + b[tid];
}
}
__global__ void subKernel(int* c, const int* a, const int* b, const int N)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < N) {
c[tid] = a[tid] - b[tid];
}
}
__global__ void mulKernel(int* c, const int* a, const int* b, const int N)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < N) {
c[tid] = a[tid] * b[tid];
}
}
__global__ void divKernel(int* c, const int* a, const int* b, const int N)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < N) {
c[tid] = a[tid] / b[tid];
}
}
__global__ void mul2DKernel(int* c, const int* a, const int* b, int widthA, int heightA)
{
int aROW = blockIdx.y * blockDim.y + threadIdx.y;
int bCOL = blockIdx.x * blockDim.x + threadIdx.x;
// Checking if the ROW/COL exceed the actual number of ROW/COL
// widthA = heightB
// heightA = widthB
if (aROW < widthA && bCOL < heightA) {
int dotProduct = 0;
for (int k = 0; k < widthA; k++) {
printf("Row %d, Col %d, loop num %d, A index %d, B index %d\n", aROW, bCOL, k, (aROW * widthA + k), (k * heightA + bCOL));
dotProduct += a[aROW * widthA + k] * b[k * heightA + bCOL]; // widthA = heightB
}
c[aROW * heightA + bCOL] = dotProduct;
printf("Output value at row %d, col %d is %d\n", aROW, bCOL, c[aROW * heightA + bCOL]);
}
} | #ifndef KERNELMATH_H
#define KERNELMATH_H
#include "hip/hip_runtime.h"
__global__ void addKernel(int* c, const int* a, const int* b, const int N);
__global__ void subKernel(int* c, const int* a, const int* b, const int N);
__global__ void mulKernel(int* c, const int* a, const int* b, const int N);
__global__ void divKernel(int* c, const int* a, const int* b, const int N);
/// <summary>
/// width is the width of the matrix
/// For a AxB, A is NxM, B is MxN
/// then width = M
/// </summary>
/// <param name="c"></param>
/// <param name="a"></param>
/// <param name="b"></param>
/// <param name="N"></param>
/// <returns></returns>
__global__ void mul2DKernel(int* c, const int* a, const int* b, int widthA, int heightA);
#endif // !KERNELMATH_H |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifndef KERNELMATH_H
#define KERNELMATH_H
#include "hip/hip_runtime.h"
__global__ void addKernel(int* c, const int* a, const int* b, const int N);
__global__ void subKernel(int* c, const int* a, const int* b, const int N);
__global__ void mulKernel(int* c, const int* a, const int* b, const int N);
__global__ void divKernel(int* c, const int* a, const int* b, const int N);
/// <summary>
/// width is the width of the matrix
/// For a AxB, A is NxM, B is MxN
/// then width = M
/// </summary>
/// <param name="c"></param>
/// <param name="a"></param>
/// <param name="b"></param>
/// <param name="N"></param>
/// <returns></returns>
__global__ void mul2DKernel(int* c, const int* a, const int* b, int widthA, int heightA);
#endif // !KERNELMATH_H | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef KERNELMATH_H
#define KERNELMATH_H
#include "hip/hip_runtime.h"
__global__ void addKernel(int* c, const int* a, const int* b, const int N);
__global__ void subKernel(int* c, const int* a, const int* b, const int N);
__global__ void mulKernel(int* c, const int* a, const int* b, const int N);
__global__ void divKernel(int* c, const int* a, const int* b, const int N);
/// <summary>
/// width is the width of the matrix
/// For a AxB, A is NxM, B is MxN
/// then width = M
/// </summary>
/// <param name="c"></param>
/// <param name="a"></param>
/// <param name="b"></param>
/// <param name="N"></param>
/// <returns></returns>
__global__ void mul2DKernel(int* c, const int* a, const int* b, int widthA, int heightA);
#endif // !KERNELMATH_H | .text
.file "KernelMath.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a5c82_00000000-6_KernelMath.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z9addKernelPiPKiS1_iPiPKiS1_i
.type _Z35__device_stub__Z9addKernelPiPKiS1_iPiPKiS1_i, @function
_Z35__device_stub__Z9addKernelPiPKiS1_iPiPKiS1_i:
.LFB2081:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addKernelPiPKiS1_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z35__device_stub__Z9addKernelPiPKiS1_iPiPKiS1_i, .-_Z35__device_stub__Z9addKernelPiPKiS1_iPiPKiS1_i
.globl _Z9addKernelPiPKiS1_i
.type _Z9addKernelPiPKiS1_i, @function
_Z9addKernelPiPKiS1_i:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z9addKernelPiPKiS1_iPiPKiS1_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z9addKernelPiPKiS1_i, .-_Z9addKernelPiPKiS1_i
.globl _Z35__device_stub__Z9subKernelPiPKiS1_iPiPKiS1_i
.type _Z35__device_stub__Z9subKernelPiPKiS1_iPiPKiS1_i, @function
_Z35__device_stub__Z9subKernelPiPKiS1_iPiPKiS1_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9subKernelPiPKiS1_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z35__device_stub__Z9subKernelPiPKiS1_iPiPKiS1_i, .-_Z35__device_stub__Z9subKernelPiPKiS1_iPiPKiS1_i
.globl _Z9subKernelPiPKiS1_i
.type _Z9subKernelPiPKiS1_i, @function
_Z9subKernelPiPKiS1_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z9subKernelPiPKiS1_iPiPKiS1_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9subKernelPiPKiS1_i, .-_Z9subKernelPiPKiS1_i
.globl _Z35__device_stub__Z9mulKernelPiPKiS1_iPiPKiS1_i
.type _Z35__device_stub__Z9mulKernelPiPKiS1_iPiPKiS1_i, @function
_Z35__device_stub__Z9mulKernelPiPKiS1_iPiPKiS1_i:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9mulKernelPiPKiS1_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z35__device_stub__Z9mulKernelPiPKiS1_iPiPKiS1_i, .-_Z35__device_stub__Z9mulKernelPiPKiS1_iPiPKiS1_i
.globl _Z9mulKernelPiPKiS1_i
.type _Z9mulKernelPiPKiS1_i, @function
_Z9mulKernelPiPKiS1_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z9mulKernelPiPKiS1_iPiPKiS1_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z9mulKernelPiPKiS1_i, .-_Z9mulKernelPiPKiS1_i
.globl _Z35__device_stub__Z9divKernelPiPKiS1_iPiPKiS1_i
.type _Z35__device_stub__Z9divKernelPiPKiS1_iPiPKiS1_i, @function
_Z35__device_stub__Z9divKernelPiPKiS1_iPiPKiS1_i:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9divKernelPiPKiS1_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z35__device_stub__Z9divKernelPiPKiS1_iPiPKiS1_i, .-_Z35__device_stub__Z9divKernelPiPKiS1_iPiPKiS1_i
.globl _Z9divKernelPiPKiS1_i
.type _Z9divKernelPiPKiS1_i, @function
_Z9divKernelPiPKiS1_i:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z9divKernelPiPKiS1_iPiPKiS1_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z9divKernelPiPKiS1_i, .-_Z9divKernelPiPKiS1_i
.globl _Z39__device_stub__Z11mul2DKernelPiPKiS1_iiPiPKiS1_ii
.type _Z39__device_stub__Z11mul2DKernelPiPKiS1_iiPiPKiS1_ii, @function
_Z39__device_stub__Z11mul2DKernelPiPKiS1_iiPiPKiS1_ii:
.LFB2089:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11mul2DKernelPiPKiS1_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z39__device_stub__Z11mul2DKernelPiPKiS1_iiPiPKiS1_ii, .-_Z39__device_stub__Z11mul2DKernelPiPKiS1_iiPiPKiS1_ii
.globl _Z11mul2DKernelPiPKiS1_ii
.type _Z11mul2DKernelPiPKiS1_ii, @function
_Z11mul2DKernelPiPKiS1_ii:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z11mul2DKernelPiPKiS1_iiPiPKiS1_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z11mul2DKernelPiPKiS1_ii, .-_Z11mul2DKernelPiPKiS1_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11mul2DKernelPiPKiS1_ii"
.LC1:
.string "_Z9divKernelPiPKiS1_i"
.LC2:
.string "_Z9mulKernelPiPKiS1_i"
.LC3:
.string "_Z9subKernelPiPKiS1_i"
.LC4:
.string "_Z9addKernelPiPKiS1_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11mul2DKernelPiPKiS1_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9divKernelPiPKiS1_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z9mulKernelPiPKiS1_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9subKernelPiPKiS1_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addKernelPiPKiS1_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "KernelMath.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define SEED
#define BLOCK_SIZE 32
typedef struct _data {
char * values;
char * next_values;
int width;
int height;
} data;
__global__ void operate(char * source, char * goal, int sizex, int sizey) {
__shared__ char local[BLOCK_SIZE + MASK_WIDTH - 1][BLOCK_SIZE + MASK_WIDTH - 1];
int i = blockIdx.y * blockDim.y + threadIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
int index = i * sizex + j;
int prim_x = j - MASK_RADIUS;
int first_x = prim_x;
for(; first_x - prim_x + threadIdx.x < MASK_WIDTH + BLOCK_SIZE - 1; first_x += BLOCK_SIZE) {
int prim_y = i - MASK_RADIUS;
int first_y = prim_y;
for(; first_y - prim_y + threadIdx.y < MASK_WIDTH + BLOCK_SIZE - 1; first_y += BLOCK_SIZE) {
if(first_y >= 0 && first_y < sizey && first_x >= 0 && first_x < sizex) {
local[first_y - prim_y + threadIdx.y][first_x - prim_x + threadIdx.x] =
source[first_y * sizex + first_x];
}
else {
local[first_y - prim_y + threadIdx.y][first_x - prim_x + threadIdx.x] = '0';
}
}
}
__syncthreads();
if(i < sizey && j < sizex) {
int l_j, l_i;
int amount = 0;
for(l_i = 0; l_i < MASK_WIDTH; l_i++) {
if( ( (int) threadIdx.y + l_i >= 0 ) && ( (int) threadIdx.y + l_i < BLOCK_SIZE + MASK_WIDTH - 1) ) {
for(l_j = 0; l_j < MASK_WIDTH; l_j++){
if( ( (int) threadIdx.x + l_j >= 0 ) && ( (int) threadIdx.x + l_j < BLOCK_SIZE + MASK_WIDTH - 1) ) {
if(local[threadIdx.y + l_i][threadIdx.x + l_j] == '1')
amount++;
}
}
}
}
if(source[index] == '1')
amount--;
if(source[index] == '1') {
if(amount < 2 || amount > 3)
goal[index] = '0';
else
goal[index] = '1';
}
else {
if(amount == 3)
goal[index] = '1';
else
goal[index] = '0';
}
}
} | code for sm_80
Function : _Z7operatePcS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R28, SR_TID.X ; /* 0x00000000001c7919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B2, 0x9e0 ; /* 0x000009a000027945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000ea80000002500 */
/*0060*/ S2R R21, SR_TID.Y ; /* 0x0000000000157919 */
/* 0x000ee20000002200 */
/*0070*/ ISETP.GT.U32.AND P3, PT, R28, 0x21, PT ; /* 0x000000211c00780c */
/* 0x001fe20003f64070 */
/*0080*/ IMAD R0, R0, c[0x0][0x4], RZ ; /* 0x0000010000007a24 */
/* 0x002fc400078e02ff */
/*0090*/ IMAD R26, R3, c[0x0][0x0], R28 ; /* 0x00000000031a7a24 */
/* 0x004fe400078e021c */
/*00a0*/ IMAD.IADD R19, R0, 0x1, R21 ; /* 0x0000000100137824 */
/* 0x008fd000078e0215 */
/*00b0*/ @P3 BRA 0x9d0 ; /* 0x0000091000003947 */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff037624 */
/* 0x000fe200078e00ff */
/*00d0*/ IADD3 R27, -R21, 0x21, RZ ; /* 0x00000021151b7810 */
/* 0x000fe20007ffe1ff */
/*00e0*/ IMAD.MOV.U32 R9, RZ, RZ, -0x22 ; /* 0xffffffdeff097424 */
/* 0x000fe200078e00ff */
/*00f0*/ IADD3 R24, R26, -0x1, RZ ; /* 0xffffffff1a187810 */
/* 0x000fe20007ffe0ff */
/*0100*/ IMAD R16, R19, R3, -c[0x0][0x170] ; /* 0x80005c0013107624 */
/* 0x000fe200078e0203 */
/*0110*/ LEA.HI R8, R27, 0x1, RZ, 0x1b ; /* 0x000000011b087811 */
/* 0x000fe200078fd8ff */
/*0120*/ IMAD R9, R0, R9, 0x41e ; /* 0x0000041e00097424 */
/* 0x000fe200078e0209 */
/*0130*/ IADD3 R22, R19, -0x1, RZ ; /* 0xffffffff13167810 */
/* 0x000fe20007ffe0ff */
/*0140*/ IMAD R10, R3, 0x20, R16 ; /* 0x00000020030a7824 */
/* 0x000fe200078e0210 */
/*0150*/ IADD3 R20, R19, 0x1f, RZ ; /* 0x0000001f13147810 */
/* 0x000fe20007ffe0ff */
/*0160*/ IMAD.MOV.U32 R12, RZ, RZ, R28 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e001c */
/*0170*/ IADD3 R17, R21, 0x20, RZ ; /* 0x0000002015117810 */
/* 0x000fe20007ffe0ff */
/*0180*/ IMAD.MOV.U32 R11, RZ, RZ, R24 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0018 */
/*0190*/ IADD3 R18, R19, 0x3f, RZ ; /* 0x0000003f13127810 */
/* 0x000fe20007ffe0ff */
/*01a0*/ IMAD R0, R3, 0x20, R10 ; /* 0x0000002003007824 */
/* 0x000fe200078e020a */
/*01b0*/ IADD3 R15, R21, 0x40, RZ ; /* 0x00000040150f7810 */
/* 0x000fc40007ffe0ff */
/*01c0*/ IADD3 R14, R19, 0x5f, RZ ; /* 0x0000005f130e7810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ IADD3 R13, R21, 0x60, RZ ; /* 0x00000060150d7810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ IADD3 R9, R9, 0x484, RZ ; /* 0x0000048409097810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ LOP3.LUT R8, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308087812 */
/* 0x000fe400078ec0ff */
/*0200*/ ISETP.GT.U32.AND P0, PT, R21, 0x21, PT ; /* 0x000000211500780c */
/* 0x000fe20003f04070 */
/*0210*/ BSSY B1, 0x990 ; /* 0x0000077000017945 */
/* 0x000fd80003800000 */
/*0220*/ @P0 BRA 0x980 ; /* 0x0000075000000947 */
/* 0x003fea0003800000 */
/*0230*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0240*/ BSSY B0, 0x580 ; /* 0x0000033000007945 */
/* 0x000fe20003800000 */
/*0250*/ IMAD.MOV.U32 R23, RZ, RZ, R21 ; /* 0x000000ffff177224 */
/* 0x000fe400078e0015 */
/*0260*/ IMAD.MOV.U32 R25, RZ, RZ, R22 ; /* 0x000000ffff197224 */
/* 0x000fd200078e0016 */
/*0270*/ @!P0 BRA 0x570 ; /* 0x000002f000008947 */
/* 0x000fea0003800000 */
/*0280*/ LOP3.LUT R2, R22, R11, RZ, 0xfc, !PT ; /* 0x0000000b16027212 */
/* 0x000fe200078efcff */
/*0290*/ IMAD.MOV.U32 R4, RZ, RZ, 0x30 ; /* 0x00000030ff047424 */
/* 0x000fc600078e00ff */
/*02a0*/ ISETP.GE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fc80003f06270 */
/*02b0*/ ISETP.GT.OR P0, PT, R19, c[0x0][0x174], !P0 ; /* 0x00005d0013007a0c */
/* 0x000fc80004704670 */
/*02c0*/ ISETP.GE.OR P0, PT, R11, c[0x0][0x170], P0 ; /* 0x00005c000b007a0c */
/* 0x000fda0000706670 */
/*02d0*/ @!P0 IMAD.IADD R3, R16, 0x1, R11 ; /* 0x0000000110038824 */
/* 0x000fca00078e020b */
/*02e0*/ @!P0 IADD3 R2, P1, R3, c[0x0][0x160], RZ ; /* 0x0000580003028a10 */
/* 0x000fc80007f3e0ff */
/*02f0*/ @!P0 LEA.HI.X.SX32 R3, R3, c[0x0][0x164], 0x1, P1 ; /* 0x0000590003038a11 */
/* 0x000fca00008f0eff */
/*0300*/ @!P0 LDG.E.U8 R4, [R2.64] ; /* 0x0000000402048981 */
/* 0x000ea2000c1e1100 */
/*0310*/ IMAD R5, R21, 0x22, R12 ; /* 0x0000002215057824 */
/* 0x000fe200078e020c */
/*0320*/ ISETP.NE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fe20003f05270 */
/*0330*/ IMAD.MOV.U32 R23, RZ, RZ, R17 ; /* 0x000000ffff177224 */
/* 0x000fe400078e0011 */
/*0340*/ IMAD.MOV.U32 R25, RZ, RZ, R20 ; /* 0x000000ffff197224 */
/* 0x000fe200078e0014 */
/*0350*/ STS.U8 [R5], R4 ; /* 0x0000000405007388 */
/* 0x0041f20000000000 */
/*0360*/ @!P0 BRA 0x570 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0370*/ LOP3.LUT R2, R20, R11, RZ, 0xfc, !PT ; /* 0x0000000b14027212 */
/* 0x000fe200078efcff */
/*0380*/ BSSY B3, 0x430 ; /* 0x000000a000037945 */
/* 0x000fe60003800000 */
/*0390*/ ISETP.GE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f06270 */
/*03a0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x30 ; /* 0x00000030ff027424 */
/* 0x000fc600078e00ff */
/*03b0*/ ISETP.GE.OR P0, PT, R20, c[0x0][0x174], !P0 ; /* 0x00005d0014007a0c */
/* 0x000fc80004706670 */
/*03c0*/ ISETP.GE.OR P0, PT, R11, c[0x0][0x170], P0 ; /* 0x00005c000b007a0c */
/* 0x000fda0000706670 */
/*03d0*/ @P0 BRA 0x420 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*03e0*/ IMAD.IADD R3, R10, 0x1, R11 ; /* 0x000000010a037824 */
/* 0x000fca00078e020b */
/*03f0*/ IADD3 R2, P0, R3, c[0x0][0x160], RZ ; /* 0x0000580003027a10 */
/* 0x000fc80007f1e0ff */
/*0400*/ LEA.HI.X.SX32 R3, R3, c[0x0][0x164], 0x1, P0 ; /* 0x0000590003037a11 */
/* 0x000fca00000f0eff */
/*0410*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000368000c1e1100 */
/*0420*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0430*/ STS.U8 [R5+0x440], R2 ; /* 0x0004400205007388 */
/* 0x0205e20000000000 */
/*0440*/ ISETP.NE.AND P0, PT, R8, 0x2, PT ; /* 0x000000020800780c */
/* 0x000fe20003f05270 */
/*0450*/ IMAD.MOV.U32 R23, RZ, RZ, R15 ; /* 0x000000ffff177224 */
/* 0x000fe400078e000f */
/*0460*/ IMAD.MOV.U32 R25, RZ, RZ, R18 ; /* 0x000000ffff197224 */
/* 0x000fd400078e0012 */
/*0470*/ @!P0 BRA 0x570 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0480*/ LOP3.LUT R2, R18, R11, RZ, 0xfc, !PT ; /* 0x0000000b12027212 */
/* 0x004fe200078efcff */
/*0490*/ BSSY B3, 0x540 ; /* 0x000000a000037945 */
/* 0x000fe60003800000 */
/*04a0*/ ISETP.GE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f06270 */
/*04b0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x30 ; /* 0x00000030ff027424 */
/* 0x000fc600078e00ff */
/*04c0*/ ISETP.GE.OR P0, PT, R18, c[0x0][0x174], !P0 ; /* 0x00005d0012007a0c */
/* 0x000fc80004706670 */
/*04d0*/ ISETP.GE.OR P0, PT, R11, c[0x0][0x170], P0 ; /* 0x00005c000b007a0c */
/* 0x000fda0000706670 */
/*04e0*/ @P0 BRA 0x530 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*04f0*/ IMAD.IADD R3, R0, 0x1, R11 ; /* 0x0000000100037824 */
/* 0x002fca00078e020b */
/*0500*/ IADD3 R2, P0, R3, c[0x0][0x160], RZ ; /* 0x0000580003027a10 */
/* 0x000fc80007f1e0ff */
/*0510*/ LEA.HI.X.SX32 R3, R3, c[0x0][0x164], 0x1, P0 ; /* 0x0000590003037a11 */
/* 0x000fca00000f0eff */
/*0520*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000368000c1e1100 */
/*0530*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0540*/ STS.U8 [R5+0x880], R2 ; /* 0x0008800205007388 */
/* 0x0205e20000000000 */
/*0550*/ IMAD.MOV.U32 R23, RZ, RZ, R13 ; /* 0x000000ffff177224 */
/* 0x000fe400078e000d */
/*0560*/ IMAD.MOV.U32 R25, RZ, RZ, R14 ; /* 0x000000ffff197224 */
/* 0x000fe400078e000e */
/*0570*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x004fea0003800000 */
/*0580*/ ISETP.GE.U32.AND P0, PT, R27, 0x60, PT ; /* 0x000000601b00780c */
/* 0x000fda0003f06070 */
/*0590*/ @!P0 BRA 0x980 ; /* 0x000003e000008947 */
/* 0x000fea0003800000 */
/*05a0*/ IADD3 R2, R25.reuse, 0x60, RZ ; /* 0x0000006019027810 */
/* 0x040fe20007ffe0ff */
/*05b0*/ IMAD R32, R25.reuse, 0x22, R12 ; /* 0x0000002219207824 */
/* 0x040fe200078e020c */
/*05c0*/ IADD3 R4, R25.reuse, 0x40, RZ ; /* 0x0000004019047810 */
/* 0x041fe20007ffe0ff */
/*05d0*/ IMAD R30, R25.reuse, c[0x0][0x170], RZ ; /* 0x00005c00191e7a24 */
/* 0x040fe200078e02ff */
/*05e0*/ IADD3 R34, R25, 0x20, RZ ; /* 0x0000002019227810 */
/* 0x000fe20007ffe0ff */
/*05f0*/ IMAD R29, R2, c[0x0][0x170], R11.reuse ; /* 0x00005c00021d7a24 */
/* 0x100fe400078e020b */
/*0600*/ IMAD R31, R4, c[0x0][0x170], R11 ; /* 0x00005c00041f7a24 */
/* 0x000fe400078e020b */
/*0610*/ IMAD.IADD R32, R9, 0x1, R32 ; /* 0x0000000109207824 */
/* 0x000fe400078e0220 */
/*0620*/ IMAD R34, R34, c[0x0][0x170], RZ ; /* 0x00005c0022227a24 */
/* 0x000fc400078e02ff */
/*0630*/ LOP3.LUT R2, R25.reuse, R11, RZ, 0xfc, !PT ; /* 0x0000000b19027212 */
/* 0x040fe200078efcff */
/*0640*/ IMAD.MOV.U32 R33, RZ, RZ, 0x30 ; /* 0x00000030ff217424 */
/* 0x000fe200078e00ff */
/*0650*/ IADD3 R4, R25, 0x20, RZ ; /* 0x0000002019047810 */
/* 0x000fc40007ffe0ff */
/*0660*/ ISETP.GE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f06270 */
/*0670*/ IADD3 R2, R25.reuse, 0x40, RZ ; /* 0x0000004019027810 */
/* 0x040fe40007ffe0ff */
/*0680*/ ISETP.GE.OR P0, PT, R25, c[0x0][0x174], !P0 ; /* 0x00005d0019007a0c */
/* 0x000fe40004706670 */
/*0690*/ LOP3.LUT R3, R2, R11, RZ, 0xfc, !PT ; /* 0x0000000b02037212 */
/* 0x002fe400078efcff */
/*06a0*/ ISETP.GE.OR P0, PT, R11, c[0x0][0x170], P0 ; /* 0x00005c000b007a0c */
/* 0x000fe40000706670 */
/*06b0*/ ISETP.GE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fc40003f26270 */
/*06c0*/ LOP3.LUT R5, R4, R11, RZ, 0xfc, !PT ; /* 0x0000000b04057212 */
/* 0x000fe400078efcff */
/*06d0*/ ISETP.GE.OR P1, PT, R2, c[0x0][0x174], !P1 ; /* 0x00005d0002007a0c */
/* 0x000fe40004f26670 */
/*06e0*/ ISETP.GE.AND P2, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f46270 */
/*06f0*/ IADD3 R6, R25, 0x60, RZ ; /* 0x0000006019067810 */
/* 0x000fe40007ffe0ff */
/*0700*/ ISETP.GE.OR P1, PT, R11, c[0x0][0x170], P1 ; /* 0x00005c000b007a0c */
/* 0x000fe20000f26670 */
/*0710*/ @!P0 IMAD.IADD R3, R30, 0x1, R11 ; /* 0x000000011e038824 */
/* 0x000fe200078e020b */
/*0720*/ ISETP.GE.OR P2, PT, R4, c[0x0][0x174], !P2 ; /* 0x00005d0004007a0c */
/* 0x000fc80005746670 */
/*0730*/ @!P0 IADD3 R2, P4, R3.reuse, c[0x0][0x160], RZ ; /* 0x0000580003028a10 */
/* 0x040fe40007f9e0ff */
/*0740*/ LOP3.LUT R5, R6, R11, RZ, 0xfc, !PT ; /* 0x0000000b06057212 */
/* 0x000fe400078efcff */
/*0750*/ @!P0 LEA.HI.X.SX32 R3, R3, c[0x0][0x164], 0x1, P4 ; /* 0x0000590003038a11 */
/* 0x000fe400020f0eff */
/*0760*/ ISETP.GE.OR P2, PT, R11, c[0x0][0x170], P2 ; /* 0x00005c000b007a0c */
/* 0x000fc60001746670 */
/*0770*/ @!P0 LDG.E.U8 R33, [R2.64] ; /* 0x0000000402218981 */
/* 0x0000a2000c1e1100 */
/*0780*/ ISETP.GE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f06270 */
/*0790*/ IMAD.MOV.U32 R35, RZ, RZ, 0x30 ; /* 0x00000030ff237424 */
/* 0x000fe200078e00ff */
/*07a0*/ @!P1 IADD3 R4, P4, R31.reuse, c[0x0][0x160], RZ ; /* 0x000058001f049a10 */
/* 0x040fe40007f9e0ff */
/*07b0*/ ISETP.GE.OR P0, PT, R6, c[0x0][0x174], !P0 ; /* 0x00005d0006007a0c */
/* 0x000fe40004706670 */
/*07c0*/ @!P1 LEA.HI.X.SX32 R5, R31, c[0x0][0x164], 0x1, P4 ; /* 0x000059001f059a11 */
/* 0x000fe400020f0eff */
/*07d0*/ ISETP.GE.OR P0, PT, R11, c[0x0][0x170], P0 ; /* 0x00005c000b007a0c */
/* 0x000fe20000706670 */
/*07e0*/ @!P2 IMAD.IADD R6, R34, 0x1, R11 ; /* 0x000000012206a824 */
/* 0x000fc400078e020b */
/*07f0*/ @!P1 LDG.E.U8 R35, [R4.64] ; /* 0x0000000404239981 */
/* 0x0002e2000c1e1100 */
/*0800*/ IMAD.MOV.U32 R37, RZ, RZ, 0x30 ; /* 0x00000030ff257424 */
/* 0x000fe400078e00ff */
/*0810*/ @!P2 IADD3 R2, P1, R6, c[0x0][0x160], RZ ; /* 0x000058000602aa10 */
/* 0x001fc80007f3e0ff */
/*0820*/ @!P2 LEA.HI.X.SX32 R3, R6, c[0x0][0x164], 0x1, P1 ; /* 0x000059000603aa11 */
/* 0x000fc600008f0eff */
/*0830*/ @!P0 IADD3 R6, P1, R29.reuse, c[0x0][0x160], RZ ; /* 0x000058001d068a10 */
/* 0x040fe20007f3e0ff */
/*0840*/ IMAD.MOV.U32 R36, RZ, RZ, 0x30 ; /* 0x00000030ff247424 */
/* 0x000fe200078e00ff */
/*0850*/ @!P2 LDG.E.U8 R37, [R2.64] ; /* 0x000000040225a981 */
/* 0x000124000c1e1100 */
/*0860*/ @!P0 LEA.HI.X.SX32 R7, R29, c[0x0][0x164], 0x1, P1 ; /* 0x000059001d078a11 */
/* 0x000fca00008f0eff */
/*0870*/ @!P0 LDG.E.U8 R36, [R6.64] ; /* 0x0000000406248981 */
/* 0x000f62000c1e1100 */
/*0880*/ IMAD R4, R23, 0x22, R12 ; /* 0x0000002217047824 */
/* 0x002fe200078e020c */
/*0890*/ IADD3 R2, -R22, 0x80, R25 ; /* 0x0000008016027810 */
/* 0x001fe40007ffe119 */
/*08a0*/ IADD3 R25, R25, 0x80, RZ ; /* 0x0000008019197810 */
/* 0x000fc60007ffe0ff */
/*08b0*/ IMAD.IADD R23, R2, 0x1, R21 ; /* 0x0000000102177824 */
/* 0x000fe400078e0215 */
/*08c0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fc600078e00ff */
/*08d0*/ ISETP.GE.U32.AND P0, PT, R23, 0x22, PT ; /* 0x000000221700780c */
/* 0x000fe20003f06070 */
/*08e0*/ IMAD R30, R2.reuse, 0x80, R30 ; /* 0x00000080021e7824 */
/* 0x040fe400078e021e */
/*08f0*/ IMAD R34, R2.reuse, 0x80, R34 ; /* 0x0000008002227824 */
/* 0x040fe400078e0222 */
/*0900*/ IMAD R29, R2.reuse, 0x80, R29 ; /* 0x00000080021d7824 */
/* 0x040fe400078e021d */
/*0910*/ IMAD R31, R2, 0x80, R31 ; /* 0x00000080021f7824 */
/* 0x000fe200078e021f */
/*0920*/ STS.U8 [R4], R33 ; /* 0x0000002104007388 */
/* 0x004fe80000000000 */
/*0930*/ STS.U8 [R32], R35 ; /* 0x0000002320007388 */
/* 0x008fe80000000000 */
/*0940*/ STS.U8 [R32+-0x440], R37 ; /* 0xfffbc02520007388 */
/* 0x010fe80000000000 */
/*0950*/ STS.U8 [R32+0x440], R36 ; /* 0x0004402420007388 */
/* 0x0201e40000000000 */
/*0960*/ IADD3 R32, R32, 0x1100, RZ ; /* 0x0000110020207810 */
/* 0x001fe20007ffe0ff */
/*0970*/ @!P0 BRA 0x630 ; /* 0xfffffcb000008947 */
/* 0x000fea000383ffff */
/*0980*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0990*/ IADD3 R11, R11, 0x20, RZ ; /* 0x000000200b0b7810 */
/* 0x000fc80007ffe0ff */
/*09a0*/ IADD3 R12, R28, R11, -R24 ; /* 0x0000000b1c0c7210 */
/* 0x000fc80007ffe818 */
/*09b0*/ ISETP.GE.U32.AND P0, PT, R12, 0x22, PT ; /* 0x000000220c00780c */
/* 0x000fda0003f06070 */
/*09c0*/ @!P0 BRA 0x200 ; /* 0xfffff83000008947 */
/* 0x000fea000383ffff */
/*09d0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*09e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*09f0*/ ISETP.GE.AND P0, PT, R19.reuse, c[0x0][0x174], PT ; /* 0x00005d0013007a0c */
/* 0x040fe20003f06270 */
/*0a00*/ IMAD R2, R19, c[0x0][0x170], R26 ; /* 0x00005c0013027a24 */
/* 0x000fc600078e021a */
/*0a10*/ ISETP.GE.OR P0, PT, R26, c[0x0][0x170], P0 ; /* 0x00005c001a007a0c */
/* 0x000fda0000706670 */
/*0a20*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0a30*/ SHF.R.S32.HI R6, RZ, 0x1f, R2 ; /* 0x0000001fff067819 */
/* 0x000fe40000011402 */
/*0a40*/ IADD3 R4, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x001fc80007f1e0ff */
/*0a50*/ IADD3.X R5, R6, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590006057a10 */
/* 0x000fca00007fe4ff */
/*0a60*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1100 */
/*0a70*/ ISETP.GT.U32.AND P5, PT, R21.reuse, 0x21, PT ; /* 0x000000211500780c */
/* 0x040fe20003fa4070 */
/*0a80*/ BSSY B0, 0xc60 ; /* 0x000001d000007945 */
/* 0x000fe20003800000 */
/*0a90*/ IADD3 R0, R21.reuse, 0x1, RZ ; /* 0x0000000115007810 */
/* 0x040fe40007ffe0ff */
/*0aa0*/ IADD3 R3, R21.reuse, 0x2, RZ ; /* 0x0000000215037810 */
/* 0x042fe20007ffe0ff */
/*0ab0*/ IMAD R21, R21, 0x22, R28 ; /* 0x0000002215157824 */
/* 0x000fe200078e021c */
/*0ac0*/ IADD3 R2, P4, R2, c[0x0][0x168], RZ ; /* 0x00005a0002027a10 */
/* 0x000fe40007f9e0ff */
/*0ad0*/ ISETP.GT.U32.AND P2, PT, R0, 0x21, PT ; /* 0x000000210000780c */
/* 0x000fe20003f44070 */
/*0ae0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0af0*/ ISETP.GT.U32.AND P0, PT, R3, 0x21, PT ; /* 0x000000210300780c */
/* 0x000fc40003f04070 */
/*0b00*/ IADD3.X R3, R6, c[0x0][0x16c], RZ, P4, !PT ; /* 0x00005b0006037a10 */
/* 0x000fe400027fe4ff */
/*0b10*/ ISETP.NE.AND P1, PT, R4, 0x31, PT ; /* 0x000000310400780c */
/* 0x004fe20003f25270 */
/*0b20*/ @P5 BRA 0xc50 ; /* 0x0000012000005947 */
/* 0x000fee0003800000 */
/*0b30*/ IADD3 R0, R28, 0x1, RZ ; /* 0x000000011c007810 */
/* 0x000fe20007ffe0ff */
/*0b40*/ @!P3 LDS.U8 R6, [R21] ; /* 0x000000001506b984 */
/* 0x000e260000000000 */
/*0b50*/ ISETP.GT.U32.AND P5, PT, R0, 0x21, PT ; /* 0x000000210000780c */
/* 0x000fe40003fa4070 */
/*0b60*/ IADD3 R0, R28, 0x2, RZ ; /* 0x000000021c007810 */
/* 0x000fc80007ffe0ff */
/*0b70*/ ISETP.GT.U32.AND P4, PT, R0, 0x21, PT ; /* 0x000000210000780c */
/* 0x000fe20003f84070 */
/*0b80*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fcc00078e00ff */
/*0b90*/ @!P5 LDS.U8 R4, [R21+0x1] ; /* 0x000001001504d984 */
/* 0x000e6c0000000000 */
/*0ba0*/ @!P4 LDS.U8 R5, [R21+0x2] ; /* 0x000002001505c984 */
/* 0x000ea20000000000 */
/*0bb0*/ @!P3 ISETP.NE.AND P6, PT, R6, 0x31, PT ; /* 0x000000310600b80c */
/* 0x001fc80003fc5270 */
/*0bc0*/ @!P3 SEL R0, RZ, 0x1, P6 ; /* 0x00000001ff00b807 */
/* 0x000fe40003000000 */
/*0bd0*/ ISETP.NE.AND P6, PT, R4, 0x31, !P5 ; /* 0x000000310400780c */
/* 0x002fe40006fc5270 */
/*0be0*/ @!P5 IADD3 R4, R0, 0x1, RZ ; /* 0x000000010004d810 */
/* 0x000fd60007ffe0ff */
/*0bf0*/ @P6 IMAD.MOV R4, RZ, RZ, R0 ; /* 0x000000ffff046224 */
/* 0x000fe200078e0200 */
/*0c00*/ ISETP.NE.AND P6, PT, R5, 0x31, !P4 ; /* 0x000000310500780c */
/* 0x004fc600067c5270 */
/*0c10*/ @!P5 IMAD.MOV.U32 R0, RZ, RZ, R4 ; /* 0x000000ffff00d224 */
/* 0x000fca00078e0004 */
/*0c20*/ @!P4 IADD3 R4, R0, 0x1, RZ ; /* 0x000000010004c810 */
/* 0x000fca0007ffe0ff */
/*0c30*/ @P6 IMAD.MOV R4, RZ, RZ, R0 ; /* 0x000000ffff046224 */
/* 0x000fc800078e0200 */
/*0c40*/ @!P4 IMAD.MOV.U32 R0, RZ, RZ, R4 ; /* 0x000000ffff00c224 */
/* 0x000fe400078e0004 */
/*0c50*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0c60*/ BSSY B0, 0xdc0 ; /* 0x0000015000007945 */
/* 0x000fe20003800000 */
/*0c70*/ @P2 BRA 0xdb0 ; /* 0x0000013000002947 */
/* 0x000fea0003800000 */
/*0c80*/ IADD3 R4, R28, 0x1, RZ ; /* 0x000000011c047810 */
/* 0x000fe20007ffe0ff */
/*0c90*/ @!P3 LDS.U8 R7, [R21+0x22] ; /* 0x000022001507b984 */
/* 0x000e260000000000 */
/*0ca0*/ ISETP.GT.U32.AND P4, PT, R4, 0x21, PT ; /* 0x000000210400780c */
/* 0x000fe40003f84070 */
/*0cb0*/ IADD3 R4, R28, 0x2, RZ ; /* 0x000000021c047810 */
/* 0x000fc80007ffe0ff */
/*0cc0*/ ISETP.GT.U32.AND P2, PT, R4, 0x21, PT ; /* 0x000000210400780c */
/* 0x000fe40003f44070 */
/*0cd0*/ @!P3 IADD3 R4, R0, 0x1, RZ ; /* 0x000000010004b810 */
/* 0x000fca0007ffe0ff */
/*0ce0*/ @!P4 LDS.U8 R5, [R21+0x23] ; /* 0x000023001505c984 */
/* 0x000e6c0000000000 */
/*0cf0*/ @!P2 LDS.U8 R6, [R21+0x24] ; /* 0x000024001506a984 */
/* 0x000ea20000000000 */
/*0d00*/ ISETP.NE.AND P6, PT, R7, 0x31, !P3 ; /* 0x000000310700780c */
/* 0x001fda0005fc5270 */
/*0d10*/ @P6 IMAD.MOV R4, RZ, RZ, R0 ; /* 0x000000ffff046224 */
/* 0x000fe200078e0200 */
/*0d20*/ ISETP.NE.AND P5, PT, R5, 0x31, !P4 ; /* 0x000000310500780c */
/* 0x002fc600067a5270 */
/*0d30*/ @!P3 IMAD.MOV.U32 R0, RZ, RZ, R4 ; /* 0x000000ffff00b224 */
/* 0x000fe200078e0004 */
/*0d40*/ ISETP.NE.AND P6, PT, R6, 0x31, !P2 ; /* 0x000000310600780c */
/* 0x004fc800057c5270 */
/*0d50*/ @!P4 IADD3 R4, R0, 0x1, RZ ; /* 0x000000010004c810 */
/* 0x000fca0007ffe0ff */
/*0d60*/ @P5 IMAD.MOV R4, RZ, RZ, R0 ; /* 0x000000ffff045224 */
/* 0x000fc800078e0200 */
/*0d70*/ @!P4 IMAD.MOV.U32 R0, RZ, RZ, R4 ; /* 0x000000ffff00c224 */
/* 0x000fca00078e0004 */
/*0d80*/ @!P2 IADD3 R4, R0, 0x1, RZ ; /* 0x000000010004a810 */
/* 0x000fe20007ffe0ff */
/*0d90*/ @P6 IMAD.MOV R4, RZ, RZ, R0 ; /* 0x000000ffff046224 */
/* 0x000fc800078e0200 */
/*0da0*/ @!P2 IMAD.MOV.U32 R0, RZ, RZ, R4 ; /* 0x000000ffff00a224 */
/* 0x000fe400078e0004 */
/*0db0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0dc0*/ BSSY B0, 0xf20 ; /* 0x0000015000007945 */
/* 0x000fe20003800000 */
/*0dd0*/ @P0 BRA 0xf10 ; /* 0x0000013000000947 */
/* 0x000fea0003800000 */
/*0de0*/ IADD3 R4, R28.reuse, 0x1, RZ ; /* 0x000000011c047810 */
/* 0x040fe40007ffe0ff */
/*0df0*/ IADD3 R28, R28, 0x2, RZ ; /* 0x000000021c1c7810 */
/* 0x000fe40007ffe0ff */
/*0e00*/ ISETP.GT.U32.AND P0, PT, R4, 0x21, PT ; /* 0x000000210400780c */
/* 0x000fe40003f04070 */
/*0e10*/ @!P3 LDS.U8 R4, [R21+0x44] ; /* 0x000044001504b984 */
/* 0x000e220000000000 */
/*0e20*/ ISETP.GT.U32.AND P2, PT, R28, 0x21, PT ; /* 0x000000211c00780c */
/* 0x000fd40003f44070 */
/*0e30*/ @!P0 LDS.U8 R5, [R21+0x45] ; /* 0x0000450015058984 */
/* 0x000e680000000000 */
/*0e40*/ @!P2 LDS.U8 R6, [R21+0x46] ; /* 0x000046001506a984 */
/* 0x000ea20000000000 */
/*0e50*/ ISETP.NE.AND P4, PT, R4, 0x31, !P3 ; /* 0x000000310400780c */
/* 0x001fe40005f85270 */
/*0e60*/ @!P3 IADD3 R4, R0, 0x1, RZ ; /* 0x000000010004b810 */
/* 0x000fe40007ffe0ff */
/*0e70*/ ISETP.NE.AND P5, PT, R5, 0x31, !P0 ; /* 0x000000310500780c */
/* 0x002fd200047a5270 */
/*0e80*/ @P4 IMAD.MOV R4, RZ, RZ, R0 ; /* 0x000000ffff044224 */
/* 0x000fc800078e0200 */
/*0e90*/ @!P3 IMAD.MOV.U32 R0, RZ, RZ, R4 ; /* 0x000000ffff00b224 */
/* 0x000fe200078e0004 */
/*0ea0*/ ISETP.NE.AND P3, PT, R6, 0x31, !P2 ; /* 0x000000310600780c */
/* 0x004fc80005765270 */
/*0eb0*/ @!P0 IADD3 R4, R0, 0x1, RZ ; /* 0x0000000100048810 */
/* 0x000fe20007ffe0ff */
/*0ec0*/ @P5 IMAD.MOV R4, RZ, RZ, R0 ; /* 0x000000ffff045224 */
/* 0x000fc800078e0200 */
/*0ed0*/ @!P0 IMAD.MOV.U32 R0, RZ, RZ, R4 ; /* 0x000000ffff008224 */
/* 0x000fca00078e0004 */
/*0ee0*/ @!P2 IADD3 R4, R0, 0x1, RZ ; /* 0x000000010004a810 */
/* 0x000fe20007ffe0ff */
/*0ef0*/ @P3 IMAD.MOV R4, RZ, RZ, R0 ; /* 0x000000ffff043224 */
/* 0x000fc800078e0200 */
/*0f00*/ @!P2 IMAD.MOV.U32 R0, RZ, RZ, R4 ; /* 0x000000ffff00a224 */
/* 0x000fe400078e0004 */
/*0f10*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0f20*/ IADD3 R4, R0, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x000fe20007ffe0ff */
/*0f30*/ @P1 IMAD.MOV R4, RZ, RZ, R0 ; /* 0x000000ffff041224 */
/* 0x000fe200078e0200 */
/*0f40*/ @!P1 BRA 0xfc0 ; /* 0x0000007000009947 */
/* 0x000fea0003800000 */
/*0f50*/ ISETP.NE.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f05270 */
/*0f60*/ IMAD.MOV.U32 R0, RZ, RZ, 0x30 ; /* 0x00000030ff007424 */
/* 0x000fd800078e00ff */
/*0f70*/ @P0 STG.E.U8 [R2.64], R0 ; /* 0x0000000002000986 */
/* 0x0001e2000c101104 */
/*0f80*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0f90*/ IMAD.MOV.U32 R0, RZ, RZ, 0x31 ; /* 0x00000031ff007424 */
/* 0x001fca00078e00ff */
/*0fa0*/ STG.E.U8 [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101104 */
/*0fb0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0fc0*/ LOP3.LUT R4, R4, 0xfffffffe, RZ, 0xc0, !PT ; /* 0xfffffffe04047812 */
/* 0x000fe200078ec0ff */
/*0fd0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x30 ; /* 0x00000030ff007424 */
/* 0x000fc600078e00ff */
/*0fe0*/ ISETP.NE.AND P0, PT, R4, 0x2, PT ; /* 0x000000020400780c */
/* 0x000fda0003f05270 */
/*0ff0*/ @P0 STG.E.U8 [R2.64], R0 ; /* 0x0000000002000986 */
/* 0x0001e2000c101104 */
/*1000*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*1010*/ IMAD.MOV.U32 R0, RZ, RZ, 0x31 ; /* 0x00000031ff007424 */
/* 0x001fca00078e00ff */
/*1020*/ STG.E.U8 [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101104 */
/*1030*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1040*/ BRA 0x1040; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define SEED
#define BLOCK_SIZE 32
typedef struct _data {
char * values;
char * next_values;
int width;
int height;
} data;
__global__ void operate(char * source, char * goal, int sizex, int sizey) {
__shared__ char local[BLOCK_SIZE + MASK_WIDTH - 1][BLOCK_SIZE + MASK_WIDTH - 1];
int i = blockIdx.y * blockDim.y + threadIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
int index = i * sizex + j;
int prim_x = j - MASK_RADIUS;
int first_x = prim_x;
for(; first_x - prim_x + threadIdx.x < MASK_WIDTH + BLOCK_SIZE - 1; first_x += BLOCK_SIZE) {
int prim_y = i - MASK_RADIUS;
int first_y = prim_y;
for(; first_y - prim_y + threadIdx.y < MASK_WIDTH + BLOCK_SIZE - 1; first_y += BLOCK_SIZE) {
if(first_y >= 0 && first_y < sizey && first_x >= 0 && first_x < sizex) {
local[first_y - prim_y + threadIdx.y][first_x - prim_x + threadIdx.x] =
source[first_y * sizex + first_x];
}
else {
local[first_y - prim_y + threadIdx.y][first_x - prim_x + threadIdx.x] = '0';
}
}
}
__syncthreads();
if(i < sizey && j < sizex) {
int l_j, l_i;
int amount = 0;
for(l_i = 0; l_i < MASK_WIDTH; l_i++) {
if( ( (int) threadIdx.y + l_i >= 0 ) && ( (int) threadIdx.y + l_i < BLOCK_SIZE + MASK_WIDTH - 1) ) {
for(l_j = 0; l_j < MASK_WIDTH; l_j++){
if( ( (int) threadIdx.x + l_j >= 0 ) && ( (int) threadIdx.x + l_j < BLOCK_SIZE + MASK_WIDTH - 1) ) {
if(local[threadIdx.y + l_i][threadIdx.x + l_j] == '1')
amount++;
}
}
}
}
if(source[index] == '1')
amount--;
if(source[index] == '1') {
if(amount < 2 || amount > 3)
goal[index] = '0';
else
goal[index] = '1';
}
else {
if(amount == 3)
goal[index] = '1';
else
goal[index] = '0';
}
}
} | .file "tmpxft_0009cf3f_00000000-6_operate.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z7operatePcS_iiPcS_ii
.type _Z30__device_stub__Z7operatePcS_iiPcS_ii, @function
_Z30__device_stub__Z7operatePcS_iiPcS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7operatePcS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z7operatePcS_iiPcS_ii, .-_Z30__device_stub__Z7operatePcS_iiPcS_ii
.globl _Z7operatePcS_ii
.type _Z7operatePcS_ii, @function
_Z7operatePcS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7operatePcS_iiPcS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7operatePcS_ii, .-_Z7operatePcS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7operatePcS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7operatePcS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define SEED
#define BLOCK_SIZE 32
typedef struct _data {
char * values;
char * next_values;
int width;
int height;
} data;
__global__ void operate(char * source, char * goal, int sizex, int sizey) {
__shared__ char local[BLOCK_SIZE + MASK_WIDTH - 1][BLOCK_SIZE + MASK_WIDTH - 1];
int i = blockIdx.y * blockDim.y + threadIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
int index = i * sizex + j;
int prim_x = j - MASK_RADIUS;
int first_x = prim_x;
for(; first_x - prim_x + threadIdx.x < MASK_WIDTH + BLOCK_SIZE - 1; first_x += BLOCK_SIZE) {
int prim_y = i - MASK_RADIUS;
int first_y = prim_y;
for(; first_y - prim_y + threadIdx.y < MASK_WIDTH + BLOCK_SIZE - 1; first_y += BLOCK_SIZE) {
if(first_y >= 0 && first_y < sizey && first_x >= 0 && first_x < sizex) {
local[first_y - prim_y + threadIdx.y][first_x - prim_x + threadIdx.x] =
source[first_y * sizex + first_x];
}
else {
local[first_y - prim_y + threadIdx.y][first_x - prim_x + threadIdx.x] = '0';
}
}
}
__syncthreads();
if(i < sizey && j < sizex) {
int l_j, l_i;
int amount = 0;
for(l_i = 0; l_i < MASK_WIDTH; l_i++) {
if( ( (int) threadIdx.y + l_i >= 0 ) && ( (int) threadIdx.y + l_i < BLOCK_SIZE + MASK_WIDTH - 1) ) {
for(l_j = 0; l_j < MASK_WIDTH; l_j++){
if( ( (int) threadIdx.x + l_j >= 0 ) && ( (int) threadIdx.x + l_j < BLOCK_SIZE + MASK_WIDTH - 1) ) {
if(local[threadIdx.y + l_i][threadIdx.x + l_j] == '1')
amount++;
}
}
}
}
if(source[index] == '1')
amount--;
if(source[index] == '1') {
if(amount < 2 || amount > 3)
goal[index] = '0';
else
goal[index] = '1';
}
else {
if(amount == 3)
goal[index] = '1';
else
goal[index] = '0';
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define SEED
#define BLOCK_SIZE 32
typedef struct _data {
char * values;
char * next_values;
int width;
int height;
} data;
__global__ void operate(char * source, char * goal, int sizex, int sizey) {
__shared__ char local[BLOCK_SIZE + MASK_WIDTH - 1][BLOCK_SIZE + MASK_WIDTH - 1];
int i = blockIdx.y * blockDim.y + threadIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
int index = i * sizex + j;
int prim_x = j - MASK_RADIUS;
int first_x = prim_x;
for(; first_x - prim_x + threadIdx.x < MASK_WIDTH + BLOCK_SIZE - 1; first_x += BLOCK_SIZE) {
int prim_y = i - MASK_RADIUS;
int first_y = prim_y;
for(; first_y - prim_y + threadIdx.y < MASK_WIDTH + BLOCK_SIZE - 1; first_y += BLOCK_SIZE) {
if(first_y >= 0 && first_y < sizey && first_x >= 0 && first_x < sizex) {
local[first_y - prim_y + threadIdx.y][first_x - prim_x + threadIdx.x] =
source[first_y * sizex + first_x];
}
else {
local[first_y - prim_y + threadIdx.y][first_x - prim_x + threadIdx.x] = '0';
}
}
}
__syncthreads();
if(i < sizey && j < sizex) {
int l_j, l_i;
int amount = 0;
for(l_i = 0; l_i < MASK_WIDTH; l_i++) {
if( ( (int) threadIdx.y + l_i >= 0 ) && ( (int) threadIdx.y + l_i < BLOCK_SIZE + MASK_WIDTH - 1) ) {
for(l_j = 0; l_j < MASK_WIDTH; l_j++){
if( ( (int) threadIdx.x + l_j >= 0 ) && ( (int) threadIdx.x + l_j < BLOCK_SIZE + MASK_WIDTH - 1) ) {
if(local[threadIdx.y + l_i][threadIdx.x + l_j] == '1')
amount++;
}
}
}
}
if(source[index] == '1')
amount--;
if(source[index] == '1') {
if(amount < 2 || amount > 3)
goal[index] = '0';
else
goal[index] = '1';
}
else {
if(amount == 3)
goal[index] = '1';
else
goal[index] = '0';
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define SEED
#define BLOCK_SIZE 32
typedef struct _data {
char * values;
char * next_values;
int width;
int height;
} data;
__global__ void operate(char * source, char * goal, int sizex, int sizey) {
__shared__ char local[BLOCK_SIZE + MASK_WIDTH - 1][BLOCK_SIZE + MASK_WIDTH - 1];
int i = blockIdx.y * blockDim.y + threadIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
int index = i * sizex + j;
int prim_x = j - MASK_RADIUS;
int first_x = prim_x;
for(; first_x - prim_x + threadIdx.x < MASK_WIDTH + BLOCK_SIZE - 1; first_x += BLOCK_SIZE) {
int prim_y = i - MASK_RADIUS;
int first_y = prim_y;
for(; first_y - prim_y + threadIdx.y < MASK_WIDTH + BLOCK_SIZE - 1; first_y += BLOCK_SIZE) {
if(first_y >= 0 && first_y < sizey && first_x >= 0 && first_x < sizex) {
local[first_y - prim_y + threadIdx.y][first_x - prim_x + threadIdx.x] =
source[first_y * sizex + first_x];
}
else {
local[first_y - prim_y + threadIdx.y][first_x - prim_x + threadIdx.x] = '0';
}
}
}
__syncthreads();
if(i < sizey && j < sizex) {
int l_j, l_i;
int amount = 0;
for(l_i = 0; l_i < MASK_WIDTH; l_i++) {
if( ( (int) threadIdx.y + l_i >= 0 ) && ( (int) threadIdx.y + l_i < BLOCK_SIZE + MASK_WIDTH - 1) ) {
for(l_j = 0; l_j < MASK_WIDTH; l_j++){
if( ( (int) threadIdx.x + l_j >= 0 ) && ( (int) threadIdx.x + l_j < BLOCK_SIZE + MASK_WIDTH - 1) ) {
if(local[threadIdx.y + l_i][threadIdx.x + l_j] == '1')
amount++;
}
}
}
}
if(source[index] == '1')
amount--;
if(source[index] == '1') {
if(amount < 2 || amount > 3)
goal[index] = '0';
else
goal[index] = '1';
}
else {
if(amount == 3)
goal[index] = '1';
else
goal[index] = '0';
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7operatePcS_ii
.globl _Z7operatePcS_ii
.p2align 8
.type _Z7operatePcS_ii,@function
_Z7operatePcS_ii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[6:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_mul_i32 s10, s15, s3
s_mul_i32 s14, s14, s2
v_add_nc_u32_e32 v4, s10, v2
v_add_nc_u32_e32 v1, s14, v0
v_cmpx_gt_u32_e32 34, v0
s_cbranch_execz .LBB0_10
s_delay_alu instid0(VALU_DEP_3)
v_add_nc_u32_e32 v3, -1, v4
v_cmp_gt_u32_e32 vcc_lo, 34, v2
v_mad_u32_u24 v5, v2, 34, v0
s_add_i32 s10, s10, -1
s_lshl_b32 s11, s8, 5
v_mad_u64_u32 v[6:7], null, s8, v3, v[0:1]
v_add_nc_u32_e32 v3, -1, v1
s_mov_b32 s12, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mov_b32_e32 v7, v3
v_add3_u32 v6, v6, s14, -1
s_branch .LBB0_3
.LBB0_2:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s13
v_add_nc_u32_e32 v7, 32, v7
v_add_nc_u32_e32 v5, 32, v5
v_add_nc_u32_e32 v6, 32, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v8, v7, v3
v_add_nc_u32_e32 v8, v8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_u32_e64 s2, 33, v8
s_or_b32 s12, s2, s12
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execz .LBB0_10
.LBB0_3:
s_and_saveexec_b32 s13, vcc_lo
s_cbranch_execz .LBB0_2
v_cmp_lt_i32_e64 s2, -1, v7
v_cmp_gt_i32_e64 s3, s8, v7
v_mov_b32_e32 v8, v6
v_dual_mov_b32 v9, v2 :: v_dual_mov_b32 v10, v5
s_mov_b32 s14, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_7
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s16
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s15
v_add_nc_u32_e32 v9, 32, v9
s_waitcnt vmcnt(0)
ds_store_b8 v10, v11
v_add_nc_u32_e32 v10, 0x440, v10
v_add_nc_u32_e32 v8, s11, v8
v_cmp_lt_u32_e64 s4, 33, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s14, s4, s14
s_and_not1_b32 exec_lo, exec_lo, s14
s_cbranch_execz .LBB0_2
.LBB0_7:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v11, 48 :: v_dual_add_nc_u32 v12, s10, v9
s_mov_b32 s15, exec_lo
v_cmpx_lt_i32_e32 -1, v12
s_cbranch_execz .LBB0_6
v_cmp_gt_i32_e64 s4, s9, v12
v_mov_b32_e32 v11, 48
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s4, s2, s4
s_and_b32 s4, s3, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s16, s4
s_cbranch_execz .LBB0_5
v_ashrrev_i32_e32 v12, 31, v8
v_add_co_u32 v11, s4, s6, v8
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v12, s4, s7, v12, s4
global_load_u8 v11, v[11:12], off
s_branch .LBB0_5
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s5
v_cmp_gt_i32_e32 vcc_lo, s9, v4
v_cmp_gt_i32_e64 s2, s8, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_29
v_mad_u32_u24 v3, v2, 34, v0
v_mov_b32_e32 v5, 0
s_mov_b32 s2, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_13
.p2align 6
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s3
v_add_nc_u32_e32 v3, 34, v3
s_add_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s2, 3
s_cbranch_scc0 .LBB0_18
.LBB0_13:
v_add_nc_u32_e32 v6, s2, v2
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e32 34, v6
s_cbranch_execz .LBB0_12
s_mov_b32 s4, 0
s_branch .LBB0_16
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s5
s_add_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s4, 3
s_cbranch_scc0 .LBB0_12
.LBB0_16:
v_add_nc_u32_e32 v6, s4, v0
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e32 34, v6
s_cbranch_execz .LBB0_15
v_add_nc_u32_e32 v6, s4, v3
ds_load_u8 v6, v6
s_waitcnt lgkmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, 49, v6
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_branch .LBB0_15
.LBB0_18:
s_set_inst_prefetch_distance 0x2
v_mad_u64_u32 v[2:3], null, v4, s8, v[1:2]
s_load_b64 s[2:3], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_add_co_u32 v0, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v3, vcc_lo
global_load_u8 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e64 s0, 49, v0
v_cmp_ne_u16_e32 vcc_lo, 49, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_subrev_co_ci_u32_e64 v0, s0, 0, v5, s0
s_and_saveexec_b32 s0, vcc_lo
s_xor_b32 s1, exec_lo, s0
s_cbranch_execz .LBB0_24
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, 3, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, s0, s2, v2
v_add_co_ci_u32_e64 v1, s0, s3, v3, s0
s_and_saveexec_b32 s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_21
v_mov_b32_e32 v2, 48
global_store_b8 v[0:1], v2, off
.LBB0_21:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_23
v_mov_b32_e32 v2, 49
global_store_b8 v[0:1], v2, off
.LBB0_23:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_24:
s_and_not1_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_29
v_add_nc_u32_e32 v0, -4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_lt_u32_e32 vcc_lo, -3, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, s0, s2, v2
v_add_co_ci_u32_e64 v1, s0, s3, v3, s0
s_and_saveexec_b32 s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_27
v_mov_b32_e32 v2, 49
global_store_b8 v[0:1], v2, off
.LBB0_27:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_29
v_mov_b32_e32 v2, 48
global_store_b8 v[0:1], v2, off
.LBB0_29:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7operatePcS_ii
.amdhsa_group_segment_fixed_size 1156
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7operatePcS_ii, .Lfunc_end0-_Z7operatePcS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1156
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7operatePcS_ii
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z7operatePcS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define SEED
#define BLOCK_SIZE 32
typedef struct _data {
char * values;
char * next_values;
int width;
int height;
} data;
__global__ void operate(char * source, char * goal, int sizex, int sizey) {
__shared__ char local[BLOCK_SIZE + MASK_WIDTH - 1][BLOCK_SIZE + MASK_WIDTH - 1];
int i = blockIdx.y * blockDim.y + threadIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
int index = i * sizex + j;
int prim_x = j - MASK_RADIUS;
int first_x = prim_x;
for(; first_x - prim_x + threadIdx.x < MASK_WIDTH + BLOCK_SIZE - 1; first_x += BLOCK_SIZE) {
int prim_y = i - MASK_RADIUS;
int first_y = prim_y;
for(; first_y - prim_y + threadIdx.y < MASK_WIDTH + BLOCK_SIZE - 1; first_y += BLOCK_SIZE) {
if(first_y >= 0 && first_y < sizey && first_x >= 0 && first_x < sizex) {
local[first_y - prim_y + threadIdx.y][first_x - prim_x + threadIdx.x] =
source[first_y * sizex + first_x];
}
else {
local[first_y - prim_y + threadIdx.y][first_x - prim_x + threadIdx.x] = '0';
}
}
}
__syncthreads();
if(i < sizey && j < sizex) {
int l_j, l_i;
int amount = 0;
for(l_i = 0; l_i < MASK_WIDTH; l_i++) {
if( ( (int) threadIdx.y + l_i >= 0 ) && ( (int) threadIdx.y + l_i < BLOCK_SIZE + MASK_WIDTH - 1) ) {
for(l_j = 0; l_j < MASK_WIDTH; l_j++){
if( ( (int) threadIdx.x + l_j >= 0 ) && ( (int) threadIdx.x + l_j < BLOCK_SIZE + MASK_WIDTH - 1) ) {
if(local[threadIdx.y + l_i][threadIdx.x + l_j] == '1')
amount++;
}
}
}
}
if(source[index] == '1')
amount--;
if(source[index] == '1') {
if(amount < 2 || amount > 3)
goal[index] = '0';
else
goal[index] = '1';
}
else {
if(amount == 3)
goal[index] = '1';
else
goal[index] = '0';
}
}
} | .text
.file "operate.hip"
.globl _Z22__device_stub__operatePcS_ii # -- Begin function _Z22__device_stub__operatePcS_ii
.p2align 4, 0x90
.type _Z22__device_stub__operatePcS_ii,@function
_Z22__device_stub__operatePcS_ii: # @_Z22__device_stub__operatePcS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7operatePcS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__operatePcS_ii, .Lfunc_end0-_Z22__device_stub__operatePcS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7operatePcS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7operatePcS_ii,@object # @_Z7operatePcS_ii
.section .rodata,"a",@progbits
.globl _Z7operatePcS_ii
.p2align 3, 0x0
_Z7operatePcS_ii:
.quad _Z22__device_stub__operatePcS_ii
.size _Z7operatePcS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7operatePcS_ii"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__operatePcS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7operatePcS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009cf3f_00000000-6_operate.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z7operatePcS_iiPcS_ii
.type _Z30__device_stub__Z7operatePcS_iiPcS_ii, @function
_Z30__device_stub__Z7operatePcS_iiPcS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7operatePcS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z7operatePcS_iiPcS_ii, .-_Z30__device_stub__Z7operatePcS_iiPcS_ii
.globl _Z7operatePcS_ii
.type _Z7operatePcS_ii, @function
_Z7operatePcS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7operatePcS_iiPcS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7operatePcS_ii, .-_Z7operatePcS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7operatePcS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7operatePcS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "operate.hip"
.globl _Z22__device_stub__operatePcS_ii # -- Begin function _Z22__device_stub__operatePcS_ii
.p2align 4, 0x90
.type _Z22__device_stub__operatePcS_ii,@function
_Z22__device_stub__operatePcS_ii: # @_Z22__device_stub__operatePcS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7operatePcS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__operatePcS_ii, .Lfunc_end0-_Z22__device_stub__operatePcS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7operatePcS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7operatePcS_ii,@object # @_Z7operatePcS_ii
.section .rodata,"a",@progbits
.globl _Z7operatePcS_ii
.p2align 3, 0x0
_Z7operatePcS_ii:
.quad _Z22__device_stub__operatePcS_ii
.size _Z7operatePcS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7operatePcS_ii"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__operatePcS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7operatePcS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
using namespace std;
__global__ void setValue(float *data, int idx, float value) {
if(threadIdx.x == 0) {
data[idx] = value;
}
} | code for sm_80
Function : _Z8setValuePfif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fda0003f05270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0050*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*0060*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fce0000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
using namespace std;
__global__ void setValue(float *data, int idx, float value) {
if(threadIdx.x == 0) {
data[idx] = value;
}
} | .file "tmpxft_00124501_00000000-6_setValue.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z8setValuePfifPfif
.type _Z29__device_stub__Z8setValuePfifPfif, @function
_Z29__device_stub__Z8setValuePfifPfif:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movss %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8setValuePfif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z8setValuePfifPfif, .-_Z29__device_stub__Z8setValuePfifPfif
.globl _Z8setValuePfif
.type _Z8setValuePfif, @function
_Z8setValuePfif:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z8setValuePfifPfif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8setValuePfif, .-_Z8setValuePfif
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8setValuePfif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8setValuePfif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
using namespace std;
__global__ void setValue(float *data, int idx, float value) {
if(threadIdx.x == 0) {
data[idx] = value;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
using namespace std;
__global__ void setValue(float *data, int idx, float value) {
if(threadIdx.x == 0) {
data[idx] = value;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
using namespace std;
__global__ void setValue(float *data, int idx, float value) {
if(threadIdx.x == 0) {
data[idx] = value;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8setValuePfif
.globl _Z8setValuePfif
.p2align 8
.type _Z8setValuePfif,@function
_Z8setValuePfif:
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s3
s_ashr_i32 s5, s2, 31
s_mov_b32 s4, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[4:5], 2
s_add_u32 s0, s0, s4
s_addc_u32 s1, s1, s5
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8setValuePfif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 6
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8setValuePfif, .Lfunc_end0-_Z8setValuePfif
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8setValuePfif
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z8setValuePfif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
using namespace std;
__global__ void setValue(float *data, int idx, float value) {
if(threadIdx.x == 0) {
data[idx] = value;
}
} | .text
.file "setValue.hip"
.globl _Z23__device_stub__setValuePfif # -- Begin function _Z23__device_stub__setValuePfif
.p2align 4, 0x90
.type _Z23__device_stub__setValuePfif,@function
_Z23__device_stub__setValuePfif: # @_Z23__device_stub__setValuePfif
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movss %xmm0, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8setValuePfif, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__setValuePfif, .Lfunc_end0-_Z23__device_stub__setValuePfif
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8setValuePfif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8setValuePfif,@object # @_Z8setValuePfif
.section .rodata,"a",@progbits
.globl _Z8setValuePfif
.p2align 3, 0x0
_Z8setValuePfif:
.quad _Z23__device_stub__setValuePfif
.size _Z8setValuePfif, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8setValuePfif"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__setValuePfif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8setValuePfif
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8setValuePfif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fda0003f05270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0050*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*0060*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fce0000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8setValuePfif
.globl _Z8setValuePfif
.p2align 8
.type _Z8setValuePfif,@function
_Z8setValuePfif:
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s3
s_ashr_i32 s5, s2, 31
s_mov_b32 s4, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[4:5], 2
s_add_u32 s0, s0, s4
s_addc_u32 s1, s1, s5
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8setValuePfif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 6
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8setValuePfif, .Lfunc_end0-_Z8setValuePfif
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8setValuePfif
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z8setValuePfif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00124501_00000000-6_setValue.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z8setValuePfifPfif
.type _Z29__device_stub__Z8setValuePfifPfif, @function
_Z29__device_stub__Z8setValuePfifPfif:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movss %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8setValuePfif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z8setValuePfifPfif, .-_Z29__device_stub__Z8setValuePfifPfif
.globl _Z8setValuePfif
.type _Z8setValuePfif, @function
_Z8setValuePfif:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z8setValuePfifPfif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8setValuePfif, .-_Z8setValuePfif
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8setValuePfif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8setValuePfif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "setValue.hip"
.globl _Z23__device_stub__setValuePfif # -- Begin function _Z23__device_stub__setValuePfif
.p2align 4, 0x90
.type _Z23__device_stub__setValuePfif,@function
_Z23__device_stub__setValuePfif: # @_Z23__device_stub__setValuePfif
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movss %xmm0, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8setValuePfif, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__setValuePfif, .Lfunc_end0-_Z23__device_stub__setValuePfif
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8setValuePfif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8setValuePfif,@object # @_Z8setValuePfif
.section .rodata,"a",@progbits
.globl _Z8setValuePfif
.p2align 3, 0x0
_Z8setValuePfif:
.quad _Z23__device_stub__setValuePfif
.size _Z8setValuePfif, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8setValuePfif"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__setValuePfif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8setValuePfif
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cassert>
// Intentionally doing a cuda assert to generate xid error 43
extern "C" __global__ void make_assert(int* buf, size_t size, int iterations)
{
assert(false);
} | code for sm_80
Function : make_assert
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cassert>
// Intentionally doing a cuda assert to generate xid error 43
extern "C" __global__ void make_assert(int* buf, size_t size, int iterations)
{
assert(false);
} | .file "tmpxft_000386b5_00000000-6_cuda_assert.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z11make_assertPimiPimi
.type _Z33__device_stub__Z11make_assertPimiPimi, @function
_Z33__device_stub__Z11make_assertPimiPimi:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq make_assert(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z11make_assertPimiPimi, .-_Z33__device_stub__Z11make_assertPimiPimi
.globl make_assert
.type make_assert, @function
make_assert:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z11make_assertPimiPimi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size make_assert, .-make_assert
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "make_assert"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq make_assert(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cassert>
// Intentionally doing a cuda assert to generate xid error 43
extern "C" __global__ void make_assert(int* buf, size_t size, int iterations)
{
assert(false);
} | #include <hip/hip_runtime.h>
#include <cassert>
// Intentionally doing a cuda assert to generate xid error 43
extern "C" __global__ void make_assert(int* buf, size_t size, int iterations)
{
assert(false);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cassert>
// Intentionally doing a cuda assert to generate xid error 43
extern "C" __global__ void make_assert(int* buf, size_t size, int iterations)
{
assert(false);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected make_assert
.globl make_assert
.p2align 8
.type make_assert,@function
make_assert:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel make_assert
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size make_assert, .Lfunc_end0-make_assert
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: make_assert
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: make_assert.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cassert>
// Intentionally doing a cuda assert to generate xid error 43
extern "C" __global__ void make_assert(int* buf, size_t size, int iterations)
{
assert(false);
} | .text
.file "cuda_assert.hip"
.globl __device_stub__make_assert # -- Begin function __device_stub__make_assert
.p2align 4, 0x90
.type __device_stub__make_assert,@function
__device_stub__make_assert: # @__device_stub__make_assert
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $make_assert, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size __device_stub__make_assert, .Lfunc_end0-__device_stub__make_assert
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $make_assert, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type make_assert,@object # @make_assert
.section .rodata,"a",@progbits
.globl make_assert
.p2align 3, 0x0
make_assert:
.quad __device_stub__make_assert
.size make_assert, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "make_assert"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__make_assert
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym make_assert
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : make_assert
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected make_assert
.globl make_assert
.p2align 8
.type make_assert,@function
make_assert:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel make_assert
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size make_assert, .Lfunc_end0-make_assert
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: make_assert
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: make_assert.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000386b5_00000000-6_cuda_assert.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z11make_assertPimiPimi
.type _Z33__device_stub__Z11make_assertPimiPimi, @function
_Z33__device_stub__Z11make_assertPimiPimi:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq make_assert(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z11make_assertPimiPimi, .-_Z33__device_stub__Z11make_assertPimiPimi
.globl make_assert
.type make_assert, @function
make_assert:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z11make_assertPimiPimi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size make_assert, .-make_assert
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "make_assert"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq make_assert(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_assert.hip"
.globl __device_stub__make_assert # -- Begin function __device_stub__make_assert
.p2align 4, 0x90
.type __device_stub__make_assert,@function
__device_stub__make_assert: # @__device_stub__make_assert
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $make_assert, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size __device_stub__make_assert, .Lfunc_end0-__device_stub__make_assert
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $make_assert, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type make_assert,@object # @make_assert
.section .rodata,"a",@progbits
.globl make_assert
.p2align 3, 0x0
make_assert:
.quad __device_stub__make_assert
.size make_assert, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "make_assert"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__make_assert
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym make_assert
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "CUDAHelper.cuh"
#if !defined(__CUDA_ARCH__) || __CUDA_ARCH__ >= 600
#else
__device__ double atomicAdd(double* address, double val) {
unsigned long long int* address_as_ull =
(unsigned long long int*)address;
unsigned long long int old = *address_as_ull, assumed;
do {
assumed = old;
old = atomicCAS(address_as_ull, assumed,
__double_as_longlong(val +
__longlong_as_double(assumed)));
} while (assumed != old);
return __longlong_as_double(old);
}
#endif
template <class T>
__host__ void setPointerToNull(T **d_ptr) {
if (*d_ptr != nullptr){
cudaFree(*d_ptr);
cudaCheckErrors("ERROR");
*d_ptr = nullptr;
}
} | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "CUDAHelper.cuh"
#if !defined(__CUDA_ARCH__) || __CUDA_ARCH__ >= 600
#else
__device__ double atomicAdd(double* address, double val) {
unsigned long long int* address_as_ull =
(unsigned long long int*)address;
unsigned long long int old = *address_as_ull, assumed;
do {
assumed = old;
old = atomicCAS(address_as_ull, assumed,
__double_as_longlong(val +
__longlong_as_double(assumed)));
} while (assumed != old);
return __longlong_as_double(old);
}
#endif
template <class T>
__host__ void setPointerToNull(T **d_ptr) {
if (*d_ptr != nullptr){
cudaFree(*d_ptr);
cudaCheckErrors("ERROR");
*d_ptr = nullptr;
}
} | #ifndef CUDAHELPERS__CUH
#define CUDAHELPERS__CUH
#include <hip/hip_runtime.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <iostream>
#define cudaCheckErrors(msg) \
do { \
hipError_t __err = hipGetLastError(); \
if (__err != hipSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
msg, hipGetErrorString(__err), \
__FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
__device__ double atomicAdd(double* address, double val);
template <class T>
__host__ void setPointerToNull(T **d_ptr);
class CUDAHelper {
public:
CUDAHelper() {
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, 0);
_maxNumberOfThreadsPerBlock = prop.maxThreadsPerBlock;
_maxNumberOBlocks = prop.maxGridSize[0];
}
int2 calcThreadPerBlock(int numOfThreads) {
int2 r;
r.x = 0;
r.y = 0;
return r;
}
private:
int _maxNumberOfThreadsPerBlock;
int _maxNumberOBlocks;
};
#endif //CUDAHELPERS__CUH |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifndef CUDAHELPERS__CUH
#define CUDAHELPERS__CUH
#include <hip/hip_runtime.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <iostream>
#define cudaCheckErrors(msg) \
do { \
hipError_t __err = hipGetLastError(); \
if (__err != hipSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
msg, hipGetErrorString(__err), \
__FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
__device__ double atomicAdd(double* address, double val);
template <class T>
__host__ void setPointerToNull(T **d_ptr);
class CUDAHelper {
public:
CUDAHelper() {
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, 0);
_maxNumberOfThreadsPerBlock = prop.maxThreadsPerBlock;
_maxNumberOBlocks = prop.maxGridSize[0];
}
int2 calcThreadPerBlock(int numOfThreads) {
int2 r;
r.x = 0;
r.y = 0;
return r;
}
private:
int _maxNumberOfThreadsPerBlock;
int _maxNumberOBlocks;
};
#endif //CUDAHELPERS__CUH | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef CUDAHELPERS__CUH
#define CUDAHELPERS__CUH
#include <hip/hip_runtime.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <iostream>
#define cudaCheckErrors(msg) \
do { \
hipError_t __err = hipGetLastError(); \
if (__err != hipSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
msg, hipGetErrorString(__err), \
__FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
__device__ double atomicAdd(double* address, double val);
template <class T>
__host__ void setPointerToNull(T **d_ptr);
class CUDAHelper {
public:
CUDAHelper() {
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, 0);
_maxNumberOfThreadsPerBlock = prop.maxThreadsPerBlock;
_maxNumberOBlocks = prop.maxGridSize[0];
}
int2 calcThreadPerBlock(int numOfThreads) {
int2 r;
r.x = 0;
r.y = 0;
return r;
}
private:
int _maxNumberOfThreadsPerBlock;
int _maxNumberOBlocks;
};
#endif //CUDAHELPERS__CUH | .text
.file "CUDAHelper.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kApplyTanh(float* mat, float* target, unsigned int len) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
float mat_i, exp2x;
for (unsigned int i = idx; i < len; i += numThreads) {
mat_i = mat[i];
exp2x = __expf(2 * mat_i);
target[i] = 1 - 2 / (exp2x + 1);
}
} | code for sm_80
Function : _Z10kApplyTanhPfS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0070*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x001fc800078e00ff */
/*0080*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0003 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x0000a2000c1e1900 */
/*00a0*/ UMOV UR4, 0x40000000 ; /* 0x4000000000047882 */
/* 0x000fe20000000000 */
/*00b0*/ BSSY B1, 0x240 ; /* 0x0000018000017945 */
/* 0x000fe20003800000 */
/*00c0*/ IMAD.U32 R7, RZ, RZ, UR4 ; /* 0x00000004ff077e24 */
/* 0x000fe4000f8e00ff */
/*00d0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff037624 */
/* 0x001fe400078e00ff */
/*00e0*/ FADD R4, R2, R2 ; /* 0x0000000202047221 */
/* 0x004fe40000000000 */
/*00f0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*0100*/ FMUL R4, R4, 1.4426950216293334961 ; /* 0x3fb8aa3b04047820 */
/* 0x000fc40000400000 */
/*0110*/ IMAD R0, R3, c[0x0][0xc], R0 ; /* 0x0000030003007a24 */
/* 0x000fc600078e0200 */
/*0120*/ FSETP.GEU.AND P0, PT, R4, -126, PT ; /* 0xc2fc00000400780b */
/* 0x000fe40003f0e000 */
/*0130*/ ISETP.GE.U32.AND P2, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fd60003f46070 */
/*0140*/ @!P0 FMUL R4, R4, 0.5 ; /* 0x3f00000004048820 */
/* 0x000fc80000400000 */
/*0150*/ MUFU.EX2 R5, R4 ; /* 0x0000000400057308 */
/* 0x000e240000000800 */
/*0160*/ @!P0 FMUL R5, R5, R5 ; /* 0x0000000505058220 */
/* 0x001fc80000400000 */
/*0170*/ FADD R8, R5, 1 ; /* 0x3f80000005087421 */
/* 0x000fc80000000000 */
/*0180*/ MUFU.RCP R5, R8 ; /* 0x0000000800057308 */
/* 0x000e300000001000 */
/*0190*/ FCHK P0, -R7, R8 ; /* 0x0000000807007302 */
/* 0x000e620000000100 */
/*01a0*/ FFMA R6, -R8, R5, 1 ; /* 0x3f80000008067423 */
/* 0x001fc80000000105 */
/*01b0*/ FFMA R6, R5, R6, R5 ; /* 0x0000000605067223 */
/* 0x000fc80000000005 */
/*01c0*/ FFMA R3, R6, -2, RZ ; /* 0xc000000006037823 */
/* 0x000fc800000000ff */
/*01d0*/ FFMA R4, -R8, R3, -2 ; /* 0xc000000008047423 */
/* 0x000fc80000000103 */
/*01e0*/ FFMA R3, R6, R4, R3 ; /* 0x0000000406037223 */
/* 0x000fe20000000003 */
/*01f0*/ @!P0 BRA 0x230 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*0200*/ MOV R4, 0x220 ; /* 0x0000022000047802 */
/* 0x000fe40000000f00 */
/*0210*/ CALL.REL.NOINC 0x2a0 ; /* 0x0000008000007944 */
/* 0x000fea0003c00000 */
/*0220*/ IMAD.MOV.U32 R3, RZ, RZ, R6 ; /* 0x000000ffff037224 */
/* 0x001fe400078e0006 */
/*0230*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0240*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe400078e00ff */
/*0250*/ FADD R5, R3, 1 ; /* 0x3f80000003057421 */
/* 0x000fe40000000000 */
/*0260*/ IMAD.WIDE.U32 R2, R2, R7, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0007 */
/*0270*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e2000c101906 */
/*0280*/ @!P2 BRA 0x70 ; /* 0xfffffde00000a947 */
/* 0x000fea000383ffff */
/*0290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02a0*/ SHF.R.U32.HI R3, RZ, 0x17, R8.reuse ; /* 0x00000017ff037819 */
/* 0x100fe20000011608 */
/*02b0*/ BSSY B0, 0x890 ; /* 0x000005d000007945 */
/* 0x000fe20003800000 */
/*02c0*/ BSSY B2, 0x480 ; /* 0x000001b000027945 */
/* 0x000fe20003800000 */
/*02d0*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0008 */
/*02e0*/ LOP3.LUT R10, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff030a7812 */
/* 0x000fc800078ec0ff */
/*02f0*/ IADD3 R7, R10, -0x1, RZ ; /* 0xffffffff0a077810 */
/* 0x000fc80007ffe0ff */
/*0300*/ ISETP.GT.U32.AND P0, PT, R7, 0xfd, PT ; /* 0x000000fd0700780c */
/* 0x000fda0003f04070 */
/*0310*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff058224 */
/* 0x000fe200078e00ff */
/*0320*/ @!P0 BRA 0x470 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0330*/ FSETP.GTU.FTZ.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fe20003f1c200 */
/*0340*/ IMAD.MOV.U32 R3, RZ, RZ, R8 ; /* 0x000000ffff037224 */
/* 0x000fd800078e0008 */
/*0350*/ @P0 BREAK B2 ; /* 0x0000000000020942 */
/* 0x000fe20003800000 */
/*0360*/ @P0 BRA 0x870 ; /* 0x0000050000000947 */
/* 0x000fea0003800000 */
/*0370*/ IMAD.MOV.U32 R5, RZ, RZ, -0x40000000 ; /* 0xc0000000ff057424 */
/* 0x000fca00078e00ff */
/*0380*/ LOP3.LUT P0, RZ, R6, 0x7fffffff, R5, 0xc8, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fda000780c805 */
/*0390*/ @!P0 BREAK B2 ; /* 0x0000000000028942 */
/* 0x000fe20003800000 */
/*03a0*/ @!P0 BRA 0x850 ; /* 0x000004a000008947 */
/* 0x000fea0003800000 */
/*03b0*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fe40003f1d200 */
/*03c0*/ LOP3.LUT P1, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fc8000782c0ff */
/*03d0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*03e0*/ @P0 BREAK B2 ; /* 0x0000000000020942 */
/* 0x000fe20003800000 */
/*03f0*/ @P0 BRA 0x830 ; /* 0x0000043000000947 */
/* 0x000fea0003800000 */
/*0400*/ LOP3.LUT P0, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fda000780c0ff */
/*0410*/ @!P0 BREAK B2 ; /* 0x0000000000028942 */
/* 0x000fe20003800000 */
/*0420*/ @!P0 BRA 0x800 ; /* 0x000003d000008947 */
/* 0x000fea0003800000 */
/*0430*/ ISETP.GE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f06270 */
/*0440*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fd800078e00ff */
/*0450*/ @!P0 FFMA R6, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003068823 */
/* 0x000fe200000000ff */
/*0460*/ @!P0 IADD3 R5, R5, 0x40, RZ ; /* 0x0000004005058810 */
/* 0x000fe40007ffe0ff */
/*0470*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0480*/ LEA R3, R10, 0xc0800000, 0x17 ; /* 0xc08000000a037811 */
/* 0x000fe200078eb8ff */
/*0490*/ UMOV UR4, 0xc0000000 ; /* 0xc000000000047882 */
/* 0x000fe20000000000 */
/*04a0*/ IADD3 R5, R5, 0x80, -R10 ; /* 0x0000008005057810 */
/* 0x000fe20007ffe80a */
/*04b0*/ UIADD3 UR4, UR4, -0x800000, URZ ; /* 0xff80000004047890 */
/* 0x000fe2000fffe03f */
/*04c0*/ BSSY B2, 0x7f0 ; /* 0x0000032000027945 */
/* 0x000fe20003800000 */
/*04d0*/ IMAD.IADD R3, R6, 0x1, -R3 ; /* 0x0000000106037824 */
/* 0x000fc800078e0a03 */
/*04e0*/ MUFU.RCP R6, R3 ; /* 0x0000000300067308 */
/* 0x000e220000001000 */
/*04f0*/ FADD.FTZ R7, -R3, -RZ ; /* 0x800000ff03077221 */
/* 0x000fc80000010100 */
/*0500*/ FFMA R9, R6, R7, 1 ; /* 0x3f80000006097423 */
/* 0x001fc80000000007 */
/*0510*/ FFMA R8, R6, R9, R6 ; /* 0x0000000906087223 */
/* 0x000fc80000000006 */
/*0520*/ FFMA R6, R8, UR4, RZ ; /* 0x0000000408067c23 */
/* 0x000fc800080000ff */
/*0530*/ FFMA R9, R7, R6, UR4 ; /* 0x0000000407097e23 */
/* 0x000fc80008000006 */
/*0540*/ FFMA R9, R8, R9, R6 ; /* 0x0000000908097223 */
/* 0x000fc80000000006 */
/*0550*/ FFMA R7, R7, R9, UR4 ; /* 0x0000000407077e23 */
/* 0x000fc80008000009 */
/*0560*/ FFMA R6, R8, R7, R9 ; /* 0x0000000708067223 */
/* 0x000fca0000000009 */
/*0570*/ SHF.R.U32.HI R3, RZ, 0x17, R6 ; /* 0x00000017ff037819 */
/* 0x000fc80000011606 */
/*0580*/ LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03037812 */
/* 0x000fca00078ec0ff */
/*0590*/ IMAD.IADD R11, R3, 0x1, R5 ; /* 0x00000001030b7824 */
/* 0x000fca00078e0205 */
/*05a0*/ IADD3 R3, R11, -0x1, RZ ; /* 0xffffffff0b037810 */
/* 0x000fc80007ffe0ff */
/*05b0*/ ISETP.GE.U32.AND P0, PT, R3, 0xfe, PT ; /* 0x000000fe0300780c */
/* 0x000fda0003f06070 */
/*05c0*/ @!P0 BRA 0x7d0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*05d0*/ ISETP.GT.AND P0, PT, R11, 0xfe, PT ; /* 0x000000fe0b00780c */
/* 0x000fda0003f04270 */
/*05e0*/ @P0 BRA 0x7a0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*05f0*/ ISETP.GE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fda0003f06270 */
/*0600*/ @P0 BRA 0x7e0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0610*/ ISETP.GE.AND P0, PT, R11, -0x18, PT ; /* 0xffffffe80b00780c */
/* 0x000fe40003f06270 */
/*0620*/ LOP3.LUT R6, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000006067812 */
/* 0x000fd600078ec0ff */
/*0630*/ @!P0 BRA 0x7e0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0640*/ FFMA.RZ R3, R8.reuse, R7.reuse, R9.reuse ; /* 0x0000000708037223 */
/* 0x1c0fe2000000c009 */
/*0650*/ IADD3 R10, R11.reuse, 0x20, RZ ; /* 0x000000200b0a7810 */
/* 0x040fe40007ffe0ff */
/*0660*/ ISETP.NE.AND P3, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f65270 */
/*0670*/ LOP3.LUT R5, R3, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff03057812 */
/* 0x000fe200078ec0ff */
/*0680*/ FFMA.RP R3, R8.reuse, R7.reuse, R9.reuse ; /* 0x0000000708037223 */
/* 0x1c0fe20000008009 */
/*0690*/ ISETP.NE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f25270 */
/*06a0*/ FFMA.RM R8, R8, R7, R9 ; /* 0x0000000708087223 */
/* 0x000fe20000004009 */
/*06b0*/ LOP3.LUT R5, R5, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000005057812 */
/* 0x000fe200078efcff */
/*06c0*/ IMAD.MOV R7, RZ, RZ, -R11 ; /* 0x000000ffff077224 */
/* 0x000fc600078e0a0b */
/*06d0*/ SHF.L.U32 R10, R5, R10, RZ ; /* 0x0000000a050a7219 */
/* 0x000fe400000006ff */
/*06e0*/ FSETP.NEU.FTZ.AND P0, PT, R3, R8, PT ; /* 0x000000080300720b */
/* 0x000fe40003f1d000 */
/*06f0*/ SEL R8, R7, RZ, P3 ; /* 0x000000ff07087207 */
/* 0x000fe40001800000 */
/*0700*/ ISETP.NE.AND P1, PT, R10, RZ, P1 ; /* 0x000000ff0a00720c */
/* 0x000fe40000f25270 */
/*0710*/ SHF.R.U32.HI R8, RZ, R8, R5 ; /* 0x00000008ff087219 */
/* 0x000fe40000011605 */
/*0720*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0730*/ SHF.R.U32.HI R10, RZ, 0x1, R8 ; /* 0x00000001ff0a7819 */
/* 0x000fe40000011608 */
/*0740*/ SEL R3, RZ, 0x1, !P0 ; /* 0x00000001ff037807 */
/* 0x000fc80004000000 */
/*0750*/ LOP3.LUT R3, R3, 0x1, R10, 0xf8, !PT ; /* 0x0000000103037812 */
/* 0x000fc800078ef80a */
/*0760*/ LOP3.LUT R3, R3, R8, RZ, 0xc0, !PT ; /* 0x0000000803037212 */
/* 0x000fca00078ec0ff */
/*0770*/ IMAD.IADD R3, R10, 0x1, R3 ; /* 0x000000010a037824 */
/* 0x000fca00078e0203 */
/*0780*/ LOP3.LUT R6, R3, R6, RZ, 0xfc, !PT ; /* 0x0000000603067212 */
/* 0x000fe200078efcff */
/*0790*/ BRA 0x7e0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*07a0*/ LOP3.LUT R6, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000006067812 */
/* 0x000fc800078ec0ff */
/*07b0*/ LOP3.LUT R6, R6, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000006067812 */
/* 0x000fe200078efcff */
/*07c0*/ BRA 0x7e0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*07d0*/ IMAD R6, R5, 0x800000, R6 ; /* 0x0080000005067824 */
/* 0x000fe400078e0206 */
/*07e0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*07f0*/ BRA 0x880 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0800*/ LOP3.LUT R6, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006067812 */
/* 0x000fc800078e4805 */
/*0810*/ LOP3.LUT R6, R6, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000006067812 */
/* 0x000fe200078efcff */
/*0820*/ BRA 0x880 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0830*/ LOP3.LUT R6, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006067812 */
/* 0x000fe200078e4805 */
/*0840*/ BRA 0x880 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0850*/ MUFU.RSQ R6, -QNAN ; /* 0xffc0000000067908 */
/* 0x000e220000001400 */
/*0860*/ BRA 0x880 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0870*/ FADD.FTZ R6, R3, -2 ; /* 0xc000000003067421 */
/* 0x000fe40000010000 */
/*0880*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0890*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*08a0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff75004007950 */
/* 0x000fea0003c3ffff */
/*08b0*/ BRA 0x8b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kApplyTanh(float* mat, float* target, unsigned int len) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
float mat_i, exp2x;
for (unsigned int i = idx; i < len; i += numThreads) {
mat_i = mat[i];
exp2x = __expf(2 * mat_i);
target[i] = 1 - 2 / (exp2x + 1);
}
} | .file "tmpxft_0016b9df_00000000-6_kApplyTanh.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z10kApplyTanhPfS_jPfS_j
.type _Z33__device_stub__Z10kApplyTanhPfS_jPfS_j, @function
_Z33__device_stub__Z10kApplyTanhPfS_jPfS_j:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10kApplyTanhPfS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z10kApplyTanhPfS_jPfS_j, .-_Z33__device_stub__Z10kApplyTanhPfS_jPfS_j
.globl _Z10kApplyTanhPfS_j
.type _Z10kApplyTanhPfS_j, @function
_Z10kApplyTanhPfS_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10kApplyTanhPfS_jPfS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10kApplyTanhPfS_j, .-_Z10kApplyTanhPfS_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10kApplyTanhPfS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10kApplyTanhPfS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kApplyTanh(float* mat, float* target, unsigned int len) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
float mat_i, exp2x;
for (unsigned int i = idx; i < len; i += numThreads) {
mat_i = mat[i];
exp2x = __expf(2 * mat_i);
target[i] = 1 - 2 / (exp2x + 1);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kApplyTanh(float* mat, float* target, unsigned int len) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
float mat_i, exp2x;
for (unsigned int i = idx; i < len; i += numThreads) {
mat_i = mat[i];
exp2x = __expf(2 * mat_i);
target[i] = 1 - 2 / (exp2x + 1);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kApplyTanh(float* mat, float* target, unsigned int len) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
float mat_i, exp2x;
for (unsigned int i = idx; i < len; i += numThreads) {
mat_i = mat[i];
exp2x = __expf(2 * mat_i);
target[i] = 1 - 2 / (exp2x + 1);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10kApplyTanhPfS_j
.globl _Z10kApplyTanhPfS_j
.p2align 8
.type _Z10kApplyTanhPfS_j,@function
_Z10kApplyTanhPfS_j:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s8, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s2, s9
s_mov_b32 s2, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v3, s0, s6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s0, s7, v4, s0
global_load_b32 v0, v[5:6], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v0
v_mul_f32_e32 v0, 0x3fb8aa3b, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_add_f32_e32 v0, 1.0, v0
v_div_scale_f32 v5, null, v0, v0, 2.0
v_div_scale_f32 v8, vcc_lo, 2.0, v0, 2.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v6, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v7, -v5, v6, 1.0
v_fmac_f32_e32 v6, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v8, v6
v_fma_f32 v9, -v5, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v9, v6
v_fma_f32 v5, -v5, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v5, v5, v6, v7
v_cmp_le_u32_e32 vcc_lo, s8, v1
v_div_fixup_f32 v0, v5, v0, 2.0
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1)
v_sub_f32_e32 v0, 1.0, v0
global_store_b32 v[3:4], v0, off
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10kApplyTanhPfS_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10kApplyTanhPfS_j, .Lfunc_end0-_Z10kApplyTanhPfS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10kApplyTanhPfS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10kApplyTanhPfS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kApplyTanh(float* mat, float* target, unsigned int len) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
float mat_i, exp2x;
for (unsigned int i = idx; i < len; i += numThreads) {
mat_i = mat[i];
exp2x = __expf(2 * mat_i);
target[i] = 1 - 2 / (exp2x + 1);
}
} | .text
.file "kApplyTanh.hip"
.globl _Z25__device_stub__kApplyTanhPfS_j # -- Begin function _Z25__device_stub__kApplyTanhPfS_j
.p2align 4, 0x90
.type _Z25__device_stub__kApplyTanhPfS_j,@function
_Z25__device_stub__kApplyTanhPfS_j: # @_Z25__device_stub__kApplyTanhPfS_j
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10kApplyTanhPfS_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__kApplyTanhPfS_j, .Lfunc_end0-_Z25__device_stub__kApplyTanhPfS_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10kApplyTanhPfS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10kApplyTanhPfS_j,@object # @_Z10kApplyTanhPfS_j
.section .rodata,"a",@progbits
.globl _Z10kApplyTanhPfS_j
.p2align 3, 0x0
_Z10kApplyTanhPfS_j:
.quad _Z25__device_stub__kApplyTanhPfS_j
.size _Z10kApplyTanhPfS_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10kApplyTanhPfS_j"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__kApplyTanhPfS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10kApplyTanhPfS_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10kApplyTanhPfS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0070*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x001fc800078e00ff */
/*0080*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0003 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x0000a2000c1e1900 */
/*00a0*/ UMOV UR4, 0x40000000 ; /* 0x4000000000047882 */
/* 0x000fe20000000000 */
/*00b0*/ BSSY B1, 0x240 ; /* 0x0000018000017945 */
/* 0x000fe20003800000 */
/*00c0*/ IMAD.U32 R7, RZ, RZ, UR4 ; /* 0x00000004ff077e24 */
/* 0x000fe4000f8e00ff */
/*00d0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff037624 */
/* 0x001fe400078e00ff */
/*00e0*/ FADD R4, R2, R2 ; /* 0x0000000202047221 */
/* 0x004fe40000000000 */
/*00f0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*0100*/ FMUL R4, R4, 1.4426950216293334961 ; /* 0x3fb8aa3b04047820 */
/* 0x000fc40000400000 */
/*0110*/ IMAD R0, R3, c[0x0][0xc], R0 ; /* 0x0000030003007a24 */
/* 0x000fc600078e0200 */
/*0120*/ FSETP.GEU.AND P0, PT, R4, -126, PT ; /* 0xc2fc00000400780b */
/* 0x000fe40003f0e000 */
/*0130*/ ISETP.GE.U32.AND P2, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fd60003f46070 */
/*0140*/ @!P0 FMUL R4, R4, 0.5 ; /* 0x3f00000004048820 */
/* 0x000fc80000400000 */
/*0150*/ MUFU.EX2 R5, R4 ; /* 0x0000000400057308 */
/* 0x000e240000000800 */
/*0160*/ @!P0 FMUL R5, R5, R5 ; /* 0x0000000505058220 */
/* 0x001fc80000400000 */
/*0170*/ FADD R8, R5, 1 ; /* 0x3f80000005087421 */
/* 0x000fc80000000000 */
/*0180*/ MUFU.RCP R5, R8 ; /* 0x0000000800057308 */
/* 0x000e300000001000 */
/*0190*/ FCHK P0, -R7, R8 ; /* 0x0000000807007302 */
/* 0x000e620000000100 */
/*01a0*/ FFMA R6, -R8, R5, 1 ; /* 0x3f80000008067423 */
/* 0x001fc80000000105 */
/*01b0*/ FFMA R6, R5, R6, R5 ; /* 0x0000000605067223 */
/* 0x000fc80000000005 */
/*01c0*/ FFMA R3, R6, -2, RZ ; /* 0xc000000006037823 */
/* 0x000fc800000000ff */
/*01d0*/ FFMA R4, -R8, R3, -2 ; /* 0xc000000008047423 */
/* 0x000fc80000000103 */
/*01e0*/ FFMA R3, R6, R4, R3 ; /* 0x0000000406037223 */
/* 0x000fe20000000003 */
/*01f0*/ @!P0 BRA 0x230 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*0200*/ MOV R4, 0x220 ; /* 0x0000022000047802 */
/* 0x000fe40000000f00 */
/*0210*/ CALL.REL.NOINC 0x2a0 ; /* 0x0000008000007944 */
/* 0x000fea0003c00000 */
/*0220*/ IMAD.MOV.U32 R3, RZ, RZ, R6 ; /* 0x000000ffff037224 */
/* 0x001fe400078e0006 */
/*0230*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0240*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe400078e00ff */
/*0250*/ FADD R5, R3, 1 ; /* 0x3f80000003057421 */
/* 0x000fe40000000000 */
/*0260*/ IMAD.WIDE.U32 R2, R2, R7, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0007 */
/*0270*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e2000c101906 */
/*0280*/ @!P2 BRA 0x70 ; /* 0xfffffde00000a947 */
/* 0x000fea000383ffff */
/*0290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02a0*/ SHF.R.U32.HI R3, RZ, 0x17, R8.reuse ; /* 0x00000017ff037819 */
/* 0x100fe20000011608 */
/*02b0*/ BSSY B0, 0x890 ; /* 0x000005d000007945 */
/* 0x000fe20003800000 */
/*02c0*/ BSSY B2, 0x480 ; /* 0x000001b000027945 */
/* 0x000fe20003800000 */
/*02d0*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0008 */
/*02e0*/ LOP3.LUT R10, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff030a7812 */
/* 0x000fc800078ec0ff */
/*02f0*/ IADD3 R7, R10, -0x1, RZ ; /* 0xffffffff0a077810 */
/* 0x000fc80007ffe0ff */
/*0300*/ ISETP.GT.U32.AND P0, PT, R7, 0xfd, PT ; /* 0x000000fd0700780c */
/* 0x000fda0003f04070 */
/*0310*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff058224 */
/* 0x000fe200078e00ff */
/*0320*/ @!P0 BRA 0x470 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0330*/ FSETP.GTU.FTZ.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fe20003f1c200 */
/*0340*/ IMAD.MOV.U32 R3, RZ, RZ, R8 ; /* 0x000000ffff037224 */
/* 0x000fd800078e0008 */
/*0350*/ @P0 BREAK B2 ; /* 0x0000000000020942 */
/* 0x000fe20003800000 */
/*0360*/ @P0 BRA 0x870 ; /* 0x0000050000000947 */
/* 0x000fea0003800000 */
/*0370*/ IMAD.MOV.U32 R5, RZ, RZ, -0x40000000 ; /* 0xc0000000ff057424 */
/* 0x000fca00078e00ff */
/*0380*/ LOP3.LUT P0, RZ, R6, 0x7fffffff, R5, 0xc8, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fda000780c805 */
/*0390*/ @!P0 BREAK B2 ; /* 0x0000000000028942 */
/* 0x000fe20003800000 */
/*03a0*/ @!P0 BRA 0x850 ; /* 0x000004a000008947 */
/* 0x000fea0003800000 */
/*03b0*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fe40003f1d200 */
/*03c0*/ LOP3.LUT P1, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fc8000782c0ff */
/*03d0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*03e0*/ @P0 BREAK B2 ; /* 0x0000000000020942 */
/* 0x000fe20003800000 */
/*03f0*/ @P0 BRA 0x830 ; /* 0x0000043000000947 */
/* 0x000fea0003800000 */
/*0400*/ LOP3.LUT P0, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fda000780c0ff */
/*0410*/ @!P0 BREAK B2 ; /* 0x0000000000028942 */
/* 0x000fe20003800000 */
/*0420*/ @!P0 BRA 0x800 ; /* 0x000003d000008947 */
/* 0x000fea0003800000 */
/*0430*/ ISETP.GE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f06270 */
/*0440*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fd800078e00ff */
/*0450*/ @!P0 FFMA R6, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003068823 */
/* 0x000fe200000000ff */
/*0460*/ @!P0 IADD3 R5, R5, 0x40, RZ ; /* 0x0000004005058810 */
/* 0x000fe40007ffe0ff */
/*0470*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0480*/ LEA R3, R10, 0xc0800000, 0x17 ; /* 0xc08000000a037811 */
/* 0x000fe200078eb8ff */
/*0490*/ UMOV UR4, 0xc0000000 ; /* 0xc000000000047882 */
/* 0x000fe20000000000 */
/*04a0*/ IADD3 R5, R5, 0x80, -R10 ; /* 0x0000008005057810 */
/* 0x000fe20007ffe80a */
/*04b0*/ UIADD3 UR4, UR4, -0x800000, URZ ; /* 0xff80000004047890 */
/* 0x000fe2000fffe03f */
/*04c0*/ BSSY B2, 0x7f0 ; /* 0x0000032000027945 */
/* 0x000fe20003800000 */
/*04d0*/ IMAD.IADD R3, R6, 0x1, -R3 ; /* 0x0000000106037824 */
/* 0x000fc800078e0a03 */
/*04e0*/ MUFU.RCP R6, R3 ; /* 0x0000000300067308 */
/* 0x000e220000001000 */
/*04f0*/ FADD.FTZ R7, -R3, -RZ ; /* 0x800000ff03077221 */
/* 0x000fc80000010100 */
/*0500*/ FFMA R9, R6, R7, 1 ; /* 0x3f80000006097423 */
/* 0x001fc80000000007 */
/*0510*/ FFMA R8, R6, R9, R6 ; /* 0x0000000906087223 */
/* 0x000fc80000000006 */
/*0520*/ FFMA R6, R8, UR4, RZ ; /* 0x0000000408067c23 */
/* 0x000fc800080000ff */
/*0530*/ FFMA R9, R7, R6, UR4 ; /* 0x0000000407097e23 */
/* 0x000fc80008000006 */
/*0540*/ FFMA R9, R8, R9, R6 ; /* 0x0000000908097223 */
/* 0x000fc80000000006 */
/*0550*/ FFMA R7, R7, R9, UR4 ; /* 0x0000000407077e23 */
/* 0x000fc80008000009 */
/*0560*/ FFMA R6, R8, R7, R9 ; /* 0x0000000708067223 */
/* 0x000fca0000000009 */
/*0570*/ SHF.R.U32.HI R3, RZ, 0x17, R6 ; /* 0x00000017ff037819 */
/* 0x000fc80000011606 */
/*0580*/ LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03037812 */
/* 0x000fca00078ec0ff */
/*0590*/ IMAD.IADD R11, R3, 0x1, R5 ; /* 0x00000001030b7824 */
/* 0x000fca00078e0205 */
/*05a0*/ IADD3 R3, R11, -0x1, RZ ; /* 0xffffffff0b037810 */
/* 0x000fc80007ffe0ff */
/*05b0*/ ISETP.GE.U32.AND P0, PT, R3, 0xfe, PT ; /* 0x000000fe0300780c */
/* 0x000fda0003f06070 */
/*05c0*/ @!P0 BRA 0x7d0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*05d0*/ ISETP.GT.AND P0, PT, R11, 0xfe, PT ; /* 0x000000fe0b00780c */
/* 0x000fda0003f04270 */
/*05e0*/ @P0 BRA 0x7a0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*05f0*/ ISETP.GE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fda0003f06270 */
/*0600*/ @P0 BRA 0x7e0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0610*/ ISETP.GE.AND P0, PT, R11, -0x18, PT ; /* 0xffffffe80b00780c */
/* 0x000fe40003f06270 */
/*0620*/ LOP3.LUT R6, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000006067812 */
/* 0x000fd600078ec0ff */
/*0630*/ @!P0 BRA 0x7e0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0640*/ FFMA.RZ R3, R8.reuse, R7.reuse, R9.reuse ; /* 0x0000000708037223 */
/* 0x1c0fe2000000c009 */
/*0650*/ IADD3 R10, R11.reuse, 0x20, RZ ; /* 0x000000200b0a7810 */
/* 0x040fe40007ffe0ff */
/*0660*/ ISETP.NE.AND P3, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f65270 */
/*0670*/ LOP3.LUT R5, R3, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff03057812 */
/* 0x000fe200078ec0ff */
/*0680*/ FFMA.RP R3, R8.reuse, R7.reuse, R9.reuse ; /* 0x0000000708037223 */
/* 0x1c0fe20000008009 */
/*0690*/ ISETP.NE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f25270 */
/*06a0*/ FFMA.RM R8, R8, R7, R9 ; /* 0x0000000708087223 */
/* 0x000fe20000004009 */
/*06b0*/ LOP3.LUT R5, R5, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000005057812 */
/* 0x000fe200078efcff */
/*06c0*/ IMAD.MOV R7, RZ, RZ, -R11 ; /* 0x000000ffff077224 */
/* 0x000fc600078e0a0b */
/*06d0*/ SHF.L.U32 R10, R5, R10, RZ ; /* 0x0000000a050a7219 */
/* 0x000fe400000006ff */
/*06e0*/ FSETP.NEU.FTZ.AND P0, PT, R3, R8, PT ; /* 0x000000080300720b */
/* 0x000fe40003f1d000 */
/*06f0*/ SEL R8, R7, RZ, P3 ; /* 0x000000ff07087207 */
/* 0x000fe40001800000 */
/*0700*/ ISETP.NE.AND P1, PT, R10, RZ, P1 ; /* 0x000000ff0a00720c */
/* 0x000fe40000f25270 */
/*0710*/ SHF.R.U32.HI R8, RZ, R8, R5 ; /* 0x00000008ff087219 */
/* 0x000fe40000011605 */
/*0720*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0730*/ SHF.R.U32.HI R10, RZ, 0x1, R8 ; /* 0x00000001ff0a7819 */
/* 0x000fe40000011608 */
/*0740*/ SEL R3, RZ, 0x1, !P0 ; /* 0x00000001ff037807 */
/* 0x000fc80004000000 */
/*0750*/ LOP3.LUT R3, R3, 0x1, R10, 0xf8, !PT ; /* 0x0000000103037812 */
/* 0x000fc800078ef80a */
/*0760*/ LOP3.LUT R3, R3, R8, RZ, 0xc0, !PT ; /* 0x0000000803037212 */
/* 0x000fca00078ec0ff */
/*0770*/ IMAD.IADD R3, R10, 0x1, R3 ; /* 0x000000010a037824 */
/* 0x000fca00078e0203 */
/*0780*/ LOP3.LUT R6, R3, R6, RZ, 0xfc, !PT ; /* 0x0000000603067212 */
/* 0x000fe200078efcff */
/*0790*/ BRA 0x7e0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*07a0*/ LOP3.LUT R6, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000006067812 */
/* 0x000fc800078ec0ff */
/*07b0*/ LOP3.LUT R6, R6, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000006067812 */
/* 0x000fe200078efcff */
/*07c0*/ BRA 0x7e0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*07d0*/ IMAD R6, R5, 0x800000, R6 ; /* 0x0080000005067824 */
/* 0x000fe400078e0206 */
/*07e0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*07f0*/ BRA 0x880 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0800*/ LOP3.LUT R6, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006067812 */
/* 0x000fc800078e4805 */
/*0810*/ LOP3.LUT R6, R6, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000006067812 */
/* 0x000fe200078efcff */
/*0820*/ BRA 0x880 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0830*/ LOP3.LUT R6, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006067812 */
/* 0x000fe200078e4805 */
/*0840*/ BRA 0x880 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0850*/ MUFU.RSQ R6, -QNAN ; /* 0xffc0000000067908 */
/* 0x000e220000001400 */
/*0860*/ BRA 0x880 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0870*/ FADD.FTZ R6, R3, -2 ; /* 0xc000000003067421 */
/* 0x000fe40000010000 */
/*0880*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0890*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*08a0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff75004007950 */
/* 0x000fea0003c3ffff */
/*08b0*/ BRA 0x8b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10kApplyTanhPfS_j
.globl _Z10kApplyTanhPfS_j
.p2align 8
.type _Z10kApplyTanhPfS_j,@function
_Z10kApplyTanhPfS_j:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s8, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s2, s9
s_mov_b32 s2, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v3, s0, s6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s0, s7, v4, s0
global_load_b32 v0, v[5:6], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v0
v_mul_f32_e32 v0, 0x3fb8aa3b, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_add_f32_e32 v0, 1.0, v0
v_div_scale_f32 v5, null, v0, v0, 2.0
v_div_scale_f32 v8, vcc_lo, 2.0, v0, 2.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v6, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v7, -v5, v6, 1.0
v_fmac_f32_e32 v6, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v8, v6
v_fma_f32 v9, -v5, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v9, v6
v_fma_f32 v5, -v5, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v5, v5, v6, v7
v_cmp_le_u32_e32 vcc_lo, s8, v1
v_div_fixup_f32 v0, v5, v0, 2.0
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1)
v_sub_f32_e32 v0, 1.0, v0
global_store_b32 v[3:4], v0, off
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10kApplyTanhPfS_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10kApplyTanhPfS_j, .Lfunc_end0-_Z10kApplyTanhPfS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10kApplyTanhPfS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10kApplyTanhPfS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016b9df_00000000-6_kApplyTanh.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z10kApplyTanhPfS_jPfS_j
.type _Z33__device_stub__Z10kApplyTanhPfS_jPfS_j, @function
_Z33__device_stub__Z10kApplyTanhPfS_jPfS_j:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10kApplyTanhPfS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z10kApplyTanhPfS_jPfS_j, .-_Z33__device_stub__Z10kApplyTanhPfS_jPfS_j
.globl _Z10kApplyTanhPfS_j
.type _Z10kApplyTanhPfS_j, @function
_Z10kApplyTanhPfS_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10kApplyTanhPfS_jPfS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10kApplyTanhPfS_j, .-_Z10kApplyTanhPfS_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10kApplyTanhPfS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10kApplyTanhPfS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kApplyTanh.hip"
.globl _Z25__device_stub__kApplyTanhPfS_j # -- Begin function _Z25__device_stub__kApplyTanhPfS_j
.p2align 4, 0x90
.type _Z25__device_stub__kApplyTanhPfS_j,@function
_Z25__device_stub__kApplyTanhPfS_j: # @_Z25__device_stub__kApplyTanhPfS_j
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10kApplyTanhPfS_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__kApplyTanhPfS_j, .Lfunc_end0-_Z25__device_stub__kApplyTanhPfS_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10kApplyTanhPfS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10kApplyTanhPfS_j,@object # @_Z10kApplyTanhPfS_j
.section .rodata,"a",@progbits
.globl _Z10kApplyTanhPfS_j
.p2align 3, 0x0
_Z10kApplyTanhPfS_j:
.quad _Z25__device_stub__kApplyTanhPfS_j
.size _Z10kApplyTanhPfS_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10kApplyTanhPfS_j"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__kApplyTanhPfS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10kApplyTanhPfS_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
// __global__ keyword specifies a device kernel function
__global__ void cuda_hello() {
printf("Hello World from GPU!\n");
printf("hello form GPU B.x=%d, Thread.x=%d\n", blockIdx.x, threadIdx.x);
}
int main() {
printf("Hello World from CPU!\n");
// Call a device function from the host: a kernel launch Which will print from the device
cuda_hello<<<6,1>>>();
//cuda_hello<<<1,6>>>(); comment and uncomment lines 13-14 for lab step 7 and 8
// This call waits for all of the submitted GPU work to complete
cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z10cuda_hellov
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc600078e00ff */
/*0010*/ MOV R17, 0x0 ; /* 0x0000000000117802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R8, c[0x4][R17] ; /* 0x0100000011087b82 */
/* 0x0000620000000a00 */
/*0060*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0070*/ IADD3 R2, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001027a10 */
/* 0x000fca0007f1e0ff */
/*0080*/ IMAD.X R16, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff107624 */
/* 0x000fe400000e06ff */
/*0090*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x000fcc0000000000 */
/*00a0*/ MOV R3, 0x110 ; /* 0x0000011000037802 */
/* 0x000fe40000000f00 */
/*00b0*/ MOV R20, 0x90 ; /* 0x0000009000147802 */
/* 0x000fe40000000f00 */
/*00c0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00d0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*00e0*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*00f0*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0100*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x003fea0003c00000 */
/*0110*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002100 */
/*0120*/ LDC.64 R8, c[0x4][R17] ; /* 0x0100000011087b82 */
/* 0x0002a20000000a00 */
/*0130*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0002 */
/*0140*/ S2R R10, SR_CTAID.X ; /* 0x00000000000a7919 */
/* 0x000e220000002500 */
/*0150*/ IMAD.MOV.U32 R7, RZ, RZ, R16 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0010 */
/*0160*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe400078e00ff */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe200078e00ff */
/*0180*/ STL.64 [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0013e80000100a00 */
/*0190*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x004fe40000000000 */
/*01a0*/ MOV R11, 0x210 ; /* 0x00000210000b7802 */
/* 0x002fe40000000f00 */
/*01b0*/ MOV R20, 0x190 ; /* 0x0000019000147802 */
/* 0x000fc40000000f00 */
/*01c0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*01d0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*01e0*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*01f0*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0200*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
// __global__ keyword specifies a device kernel function
__global__ void cuda_hello() {
printf("Hello World from GPU!\n");
printf("hello form GPU B.x=%d, Thread.x=%d\n", blockIdx.x, threadIdx.x);
}
int main() {
printf("Hello World from CPU!\n");
// Call a device function from the host: a kernel launch Which will print from the device
cuda_hello<<<6,1>>>();
//cuda_hello<<<1,6>>>(); comment and uncomment lines 13-14 for lab step 7 and 8
// This call waits for all of the submitted GPU work to complete
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_0012f83e_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10cuda_hellovv
.type _Z29__device_stub__Z10cuda_hellovv, @function
_Z29__device_stub__Z10cuda_hellovv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10cuda_hellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10cuda_hellovv, .-_Z29__device_stub__Z10cuda_hellovv
.globl _Z10cuda_hellov
.type _Z10cuda_hellov, @function
_Z10cuda_hellov:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10cuda_hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10cuda_hellov, .-_Z10cuda_hellov
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World from CPU!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $6, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z29__device_stub__Z10cuda_hellovv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z10cuda_hellov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10cuda_hellov(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
// __global__ keyword specifies a device kernel function
__global__ void cuda_hello() {
printf("Hello World from GPU!\n");
printf("hello form GPU B.x=%d, Thread.x=%d\n", blockIdx.x, threadIdx.x);
}
int main() {
printf("Hello World from CPU!\n");
// Call a device function from the host: a kernel launch Which will print from the device
cuda_hello<<<6,1>>>();
//cuda_hello<<<1,6>>>(); comment and uncomment lines 13-14 for lab step 7 and 8
// This call waits for all of the submitted GPU work to complete
cudaDeviceSynchronize();
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
// __global__ keyword specifies a device kernel function
__global__ void cuda_hello() {
printf("Hello World from GPU!\n");
printf("hello form GPU B.x=%d, Thread.x=%d\n", blockIdx.x, threadIdx.x);
}
int main() {
printf("Hello World from CPU!\n");
// Call a device function from the host: a kernel launch Which will print from the device
cuda_hello<<<6,1>>>();
//cuda_hello<<<1,6>>>(); comment and uncomment lines 13-14 for lab step 7 and 8
// This call waits for all of the submitted GPU work to complete
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
// __global__ keyword specifies a device kernel function
__global__ void cuda_hello() {
printf("Hello World from GPU!\n");
printf("hello form GPU B.x=%d, Thread.x=%d\n", blockIdx.x, threadIdx.x);
}
int main() {
printf("Hello World from CPU!\n");
// Call a device function from the host: a kernel launch Which will print from the device
cuda_hello<<<6,1>>>();
//cuda_hello<<<1,6>>>(); comment and uncomment lines 13-14 for lab step 7 and 8
// This call waits for all of the submitted GPU work to complete
hipDeviceSynchronize();
return 0;
} | .text
.file "hello.hip"
.globl _Z25__device_stub__cuda_hellov # -- Begin function _Z25__device_stub__cuda_hellov
.p2align 4, 0x90
.type _Z25__device_stub__cuda_hellov,@function
_Z25__device_stub__cuda_hellov: # @_Z25__device_stub__cuda_hellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10cuda_hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__cuda_hellov, .Lfunc_end0-_Z25__device_stub__cuda_hellov
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 5(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10cuda_hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10cuda_hellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10cuda_hellov,@object # @_Z10cuda_hellov
.section .rodata,"a",@progbits
.globl _Z10cuda_hellov
.p2align 3, 0x0
_Z10cuda_hellov:
.quad _Z25__device_stub__cuda_hellov
.size _Z10cuda_hellov, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10cuda_hellov"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World from CPU!"
.size .Lstr, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__cuda_hellov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10cuda_hellov
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012f83e_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10cuda_hellovv
.type _Z29__device_stub__Z10cuda_hellovv, @function
_Z29__device_stub__Z10cuda_hellovv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10cuda_hellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10cuda_hellovv, .-_Z29__device_stub__Z10cuda_hellovv
.globl _Z10cuda_hellov
.type _Z10cuda_hellov, @function
_Z10cuda_hellov:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10cuda_hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10cuda_hellov, .-_Z10cuda_hellov
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World from CPU!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $6, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z29__device_stub__Z10cuda_hellovv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z10cuda_hellov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10cuda_hellov(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hello.hip"
.globl _Z25__device_stub__cuda_hellov # -- Begin function _Z25__device_stub__cuda_hellov
.p2align 4, 0x90
.type _Z25__device_stub__cuda_hellov,@function
_Z25__device_stub__cuda_hellov: # @_Z25__device_stub__cuda_hellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10cuda_hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__cuda_hellov, .Lfunc_end0-_Z25__device_stub__cuda_hellov
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 5(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10cuda_hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10cuda_hellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10cuda_hellov,@object # @_Z10cuda_hellov
.section .rodata,"a",@progbits
.globl _Z10cuda_hellov
.p2align 3, 0x0
_Z10cuda_hellov:
.quad _Z25__device_stub__cuda_hellov
.size _Z10cuda_hellov, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10cuda_hellov"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World from CPU!"
.size .Lstr, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__cuda_hellov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10cuda_hellov
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/*
* JCuda - Java bindings for NVIDIA CUDA driver and runtime API
* http://www.jcuda.org
*
*
* This code is based on the NVIDIA 'reduction' CUDA sample,
* Copyright 1993-2010 NVIDIA Corporation.
*/
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
__global__ void setTargetIndex(int n, double *w, double *out)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<n)
{
if(w[i] == 1.0) {out[i] -= 1.0;}
}
} | code for sm_80
Function : setTargetIndex
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0203 */
/*0090*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1b00 */
/*00a0*/ DSETP.NEU.AND P0, PT, R2, 1, PT ; /* 0x3ff000000200742a */
/* 0x004e1c0003f0d000 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*00c0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe40000011400 */
/*00d0*/ LEA R2, P0, R0, c[0x0][0x170], 0x3 ; /* 0x00005c0000027a11 */
/* 0x000fc800078018ff */
/*00e0*/ LEA.HI.X R3, R0, c[0x0][0x174], R3, 0x3, P0 ; /* 0x00005d0000037a11 */
/* 0x000fca00000f1c03 */
/*00f0*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1b00 */
/*0100*/ DADD R4, R4, -1 ; /* 0xbff0000004047429 */
/* 0x004e0e0000000000 */
/*0110*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe2000c101b04 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/*
* JCuda - Java bindings for NVIDIA CUDA driver and runtime API
* http://www.jcuda.org
*
*
* This code is based on the NVIDIA 'reduction' CUDA sample,
* Copyright 1993-2010 NVIDIA Corporation.
*/
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
__global__ void setTargetIndex(int n, double *w, double *out)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<n)
{
if(w[i] == 1.0) {out[i] -= 1.0;}
}
} | .file "tmpxft_00092ad9_00000000-6_setTargetIndex.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z14setTargetIndexiPdS_iPdS_
.type _Z37__device_stub__Z14setTargetIndexiPdS_iPdS_, @function
_Z37__device_stub__Z14setTargetIndexiPdS_iPdS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq setTargetIndex(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z14setTargetIndexiPdS_iPdS_, .-_Z37__device_stub__Z14setTargetIndexiPdS_iPdS_
.globl setTargetIndex
.type setTargetIndex, @function
setTargetIndex:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z14setTargetIndexiPdS_iPdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size setTargetIndex, .-setTargetIndex
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "setTargetIndex"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq setTargetIndex(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/*
* JCuda - Java bindings for NVIDIA CUDA driver and runtime API
* http://www.jcuda.org
*
*
* This code is based on the NVIDIA 'reduction' CUDA sample,
* Copyright 1993-2010 NVIDIA Corporation.
*/
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
__global__ void setTargetIndex(int n, double *w, double *out)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<n)
{
if(w[i] == 1.0) {out[i] -= 1.0;}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
/*
* JCuda - Java bindings for NVIDIA CUDA driver and runtime API
* http://www.jcuda.org
*
*
* This code is based on the NVIDIA 'reduction' CUDA sample,
* Copyright 1993-2010 NVIDIA Corporation.
*/
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
__global__ void setTargetIndex(int n, double *w, double *out)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<n)
{
if(w[i] == 1.0) {out[i] -= 1.0;}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/*
* JCuda - Java bindings for NVIDIA CUDA driver and runtime API
* http://www.jcuda.org
*
*
* This code is based on the NVIDIA 'reduction' CUDA sample,
* Copyright 1993-2010 NVIDIA Corporation.
*/
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
__global__ void setTargetIndex(int n, double *w, double *out)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<n)
{
if(w[i] == 1.0) {out[i] -= 1.0;}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected setTargetIndex
.globl setTargetIndex
.p2align 8
.type setTargetIndex,@function
setTargetIndex:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_3
s_load_b64 s[2:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_eq_f64_e32 vcc_lo, 1.0, v[2:3]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], -1.0
global_store_b64 v[0:1], v[2:3], off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel setTargetIndex
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size setTargetIndex, .Lfunc_end0-setTargetIndex
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: setTargetIndex
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: setTargetIndex.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/*
* JCuda - Java bindings for NVIDIA CUDA driver and runtime API
* http://www.jcuda.org
*
*
* This code is based on the NVIDIA 'reduction' CUDA sample,
* Copyright 1993-2010 NVIDIA Corporation.
*/
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
__global__ void setTargetIndex(int n, double *w, double *out)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<n)
{
if(w[i] == 1.0) {out[i] -= 1.0;}
}
} | .text
.file "setTargetIndex.hip"
.globl __device_stub__setTargetIndex # -- Begin function __device_stub__setTargetIndex
.p2align 4, 0x90
.type __device_stub__setTargetIndex,@function
__device_stub__setTargetIndex: # @__device_stub__setTargetIndex
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $setTargetIndex, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size __device_stub__setTargetIndex, .Lfunc_end0-__device_stub__setTargetIndex
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $setTargetIndex, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type setTargetIndex,@object # @setTargetIndex
.section .rodata,"a",@progbits
.globl setTargetIndex
.p2align 3, 0x0
setTargetIndex:
.quad __device_stub__setTargetIndex
.size setTargetIndex, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "setTargetIndex"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__setTargetIndex
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym setTargetIndex
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : setTargetIndex
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0203 */
/*0090*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1b00 */
/*00a0*/ DSETP.NEU.AND P0, PT, R2, 1, PT ; /* 0x3ff000000200742a */
/* 0x004e1c0003f0d000 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*00c0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe40000011400 */
/*00d0*/ LEA R2, P0, R0, c[0x0][0x170], 0x3 ; /* 0x00005c0000027a11 */
/* 0x000fc800078018ff */
/*00e0*/ LEA.HI.X R3, R0, c[0x0][0x174], R3, 0x3, P0 ; /* 0x00005d0000037a11 */
/* 0x000fca00000f1c03 */
/*00f0*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1b00 */
/*0100*/ DADD R4, R4, -1 ; /* 0xbff0000004047429 */
/* 0x004e0e0000000000 */
/*0110*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe2000c101b04 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected setTargetIndex
.globl setTargetIndex
.p2align 8
.type setTargetIndex,@function
setTargetIndex:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_3
s_load_b64 s[2:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_eq_f64_e32 vcc_lo, 1.0, v[2:3]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], -1.0
global_store_b64 v[0:1], v[2:3], off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel setTargetIndex
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size setTargetIndex, .Lfunc_end0-setTargetIndex
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: setTargetIndex
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: setTargetIndex.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00092ad9_00000000-6_setTargetIndex.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z14setTargetIndexiPdS_iPdS_
.type _Z37__device_stub__Z14setTargetIndexiPdS_iPdS_, @function
_Z37__device_stub__Z14setTargetIndexiPdS_iPdS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq setTargetIndex(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z14setTargetIndexiPdS_iPdS_, .-_Z37__device_stub__Z14setTargetIndexiPdS_iPdS_
.globl setTargetIndex
.type setTargetIndex, @function
setTargetIndex:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z14setTargetIndexiPdS_iPdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size setTargetIndex, .-setTargetIndex
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "setTargetIndex"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq setTargetIndex(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "setTargetIndex.hip"
.globl __device_stub__setTargetIndex # -- Begin function __device_stub__setTargetIndex
.p2align 4, 0x90
.type __device_stub__setTargetIndex,@function
__device_stub__setTargetIndex: # @__device_stub__setTargetIndex
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $setTargetIndex, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size __device_stub__setTargetIndex, .Lfunc_end0-__device_stub__setTargetIndex
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $setTargetIndex, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type setTargetIndex,@object # @setTargetIndex
.section .rodata,"a",@progbits
.globl setTargetIndex
.p2align 3, 0x0
setTargetIndex:
.quad __device_stub__setTargetIndex
.size setTargetIndex, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "setTargetIndex"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__setTargetIndex
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym setTargetIndex
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <assert.h>
#include <cuda.h>
#include <sys/time.h>
#define N 10240000
#define ThreadPerBlock 128
#define NSTREAM 4
__global__ void multiply(double * a, double *b , double * output, int length)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < length)
output[tid] = a[tid] + b[tid];
}
int main()
{
cudaSetDevice(1);
int nbytes = N * sizeof (double);
double *a, *b, *c;
double *dev_A, *dev_B, *dev_C;
a = (double *) malloc( N*sizeof(double));
b = (double *) malloc( N*sizeof(double));
c = (double *) malloc( N*sizeof(double));
if(a == NULL){
printf("Error malloc \n");
exit(0);
}
int i;
for (i = 0; i < N ; i++)
{
a[i] = i;
b[i] = i;
}
assert(cudaMalloc((void**) &dev_A, nbytes) == cudaSuccess);
assert(cudaMalloc((void**) &dev_B, nbytes) == cudaSuccess);
assert(cudaMalloc((void**) &dev_C, nbytes) == cudaSuccess);
assert(cudaMemcpy(dev_A, a, nbytes, cudaMemcpyHostToDevice) == cudaSuccess);
assert(cudaMemcpy(dev_B, b, nbytes, cudaMemcpyHostToDevice) == cudaSuccess);
struct timeval begin, end;
gettimeofday(&begin, NULL);
int nblock = N/ThreadPerBlock;
if ( N % ThreadPerBlock) nblock ++;
multiply<<<nblock, ThreadPerBlock>>>(dev_A, dev_B, dev_C,N);
assert( cudaThreadSynchronize() == cudaSuccess ) ;
gettimeofday(&end, NULL);
double time = 1000000*(end.tv_sec - begin.tv_sec) + (end.tv_usec - begin.tv_usec);
printf("One Stream time: %lf ms \n", time);
cudaStream_t stream[NSTREAM];
int n = N/NSTREAM;
printf("%d\n", n);
assert( cudaThreadSynchronize() == cudaSuccess ) ;
gettimeofday(&begin, NULL);
for (i = 0; i < NSTREAM; i++)
{
nblock = n/ThreadPerBlock;
if(n % ThreadPerBlock) nblock++;
assert(cudaStreamCreate(&stream[i])== cudaSuccess);
multiply<<<nblock, ThreadPerBlock, 0, stream[i]>>>(&dev_A[i*n], &dev_B[i*n], &dev_C[i*n], n);
assert(cudaStreamDestroy(stream[i])== cudaSuccess);
}
assert( cudaThreadSynchronize() == cudaSuccess ) ;
gettimeofday(&end, NULL);
time = 1000000*(end.tv_sec - begin.tv_sec) + (end.tv_usec - begin.tv_usec);
printf("%d Stream time: %lf ms \n",NSTREAM, time);
assert(cudaMemcpy(c, dev_C, nbytes, cudaMemcpyDeviceToHost) == cudaSuccess);
for (i = 0; i < N; i++)
{
int d = (int) c[i];
int e = 2*i;
if( d != e)
{
printf("Error, %d, %lf\n", i, c[i]);
exit(0);
}
}
printf("Passed!!\n");
cudaFree(dev_A);
cudaFree(dev_B);
cudaFree(dev_C);
free(a);
free(b);
free(c);
} | code for sm_80
Function : _Z8multiplyPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R8, R9, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R2, R8.reuse, R9.reuse, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0209 */
/*00d0*/ DADD R6, R4, R2 ; /* 0x0000000004067229 */
/* 0x004e0e0000000002 */
/*00e0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <assert.h>
#include <cuda.h>
#include <sys/time.h>
#define N 10240000
#define ThreadPerBlock 128
#define NSTREAM 4
__global__ void multiply(double * a, double *b , double * output, int length)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < length)
output[tid] = a[tid] + b[tid];
}
int main()
{
cudaSetDevice(1);
int nbytes = N * sizeof (double);
double *a, *b, *c;
double *dev_A, *dev_B, *dev_C;
a = (double *) malloc( N*sizeof(double));
b = (double *) malloc( N*sizeof(double));
c = (double *) malloc( N*sizeof(double));
if(a == NULL){
printf("Error malloc \n");
exit(0);
}
int i;
for (i = 0; i < N ; i++)
{
a[i] = i;
b[i] = i;
}
assert(cudaMalloc((void**) &dev_A, nbytes) == cudaSuccess);
assert(cudaMalloc((void**) &dev_B, nbytes) == cudaSuccess);
assert(cudaMalloc((void**) &dev_C, nbytes) == cudaSuccess);
assert(cudaMemcpy(dev_A, a, nbytes, cudaMemcpyHostToDevice) == cudaSuccess);
assert(cudaMemcpy(dev_B, b, nbytes, cudaMemcpyHostToDevice) == cudaSuccess);
struct timeval begin, end;
gettimeofday(&begin, NULL);
int nblock = N/ThreadPerBlock;
if ( N % ThreadPerBlock) nblock ++;
multiply<<<nblock, ThreadPerBlock>>>(dev_A, dev_B, dev_C,N);
assert( cudaThreadSynchronize() == cudaSuccess ) ;
gettimeofday(&end, NULL);
double time = 1000000*(end.tv_sec - begin.tv_sec) + (end.tv_usec - begin.tv_usec);
printf("One Stream time: %lf ms \n", time);
cudaStream_t stream[NSTREAM];
int n = N/NSTREAM;
printf("%d\n", n);
assert( cudaThreadSynchronize() == cudaSuccess ) ;
gettimeofday(&begin, NULL);
for (i = 0; i < NSTREAM; i++)
{
nblock = n/ThreadPerBlock;
if(n % ThreadPerBlock) nblock++;
assert(cudaStreamCreate(&stream[i])== cudaSuccess);
multiply<<<nblock, ThreadPerBlock, 0, stream[i]>>>(&dev_A[i*n], &dev_B[i*n], &dev_C[i*n], n);
assert(cudaStreamDestroy(stream[i])== cudaSuccess);
}
assert( cudaThreadSynchronize() == cudaSuccess ) ;
gettimeofday(&end, NULL);
time = 1000000*(end.tv_sec - begin.tv_sec) + (end.tv_usec - begin.tv_usec);
printf("%d Stream time: %lf ms \n",NSTREAM, time);
assert(cudaMemcpy(c, dev_C, nbytes, cudaMemcpyDeviceToHost) == cudaSuccess);
for (i = 0; i < N; i++)
{
int d = (int) c[i];
int e = 2*i;
if( d != e)
{
printf("Error, %d, %lf\n", i, c[i]);
exit(0);
}
}
printf("Passed!!\n");
cudaFree(dev_A);
cudaFree(dev_B);
cudaFree(dev_C);
free(a);
free(b);
free(c);
} | .file "tmpxft_001bb225_00000000-6_concurrentKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z8multiplyPdS_S_iPdS_S_i
.type _Z32__device_stub__Z8multiplyPdS_S_iPdS_S_i, @function
_Z32__device_stub__Z8multiplyPdS_S_iPdS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8multiplyPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z8multiplyPdS_S_iPdS_S_i, .-_Z32__device_stub__Z8multiplyPdS_S_iPdS_S_i
.globl _Z8multiplyPdS_S_i
.type _Z8multiplyPdS_S_i, @function
_Z8multiplyPdS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8multiplyPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8multiplyPdS_S_i, .-_Z8multiplyPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Error malloc \n"
.LC1:
.string "One Stream time: %lf ms \n"
.LC2:
.string "%d\n"
.LC3:
.string "%d Stream time: %lf ms \n"
.LC4:
.string "Error, %d, %lf\n"
.LC5:
.string "Passed!!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $112, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $1, %edi
call cudaSetDevice@PLT
movl $81920000, %edi
call malloc@PLT
movq %rax, %rbx
movl $81920000, %edi
call malloc@PLT
movq %rax, %rbp
movl $81920000, %edi
call malloc@PLT
testq %rbx, %rbx
je .L24
movq %rax, %r12
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%rbx,%rax,8)
movsd %xmm0, 0(%rbp,%rax,8)
addq $1, %rax
cmpq $10240000, %rax
jne .L12
leaq 32(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $128, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $80000, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L13:
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 48(%rsp), %rax
subq 32(%rsp), %rax
imulq $1000000, %rax, %rax
addq 56(%rsp), %rax
subq 40(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2560000, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
leaq 64(%rsp), %r14
movl $0, %r13d
jmp .L15
.L24:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L25:
movl $10240000, %ecx
movl $0, %edx
movl $0, %esi
movl $0, %edi
call _Z32__device_stub__Z8multiplyPdS_S_iPdS_S_i
jmp .L13
.L14:
addq $8, %r14
addq $20480000, %r13
cmpq $81920000, %r13
je .L26
.L15:
movl $128, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $20000, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movq (%r14), %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L14
movq %r13, %rdx
movq %r13, %rsi
movq %r13, %rdi
movl $2560000, %ecx
call _Z32__device_stub__Z8multiplyPdS_S_iPdS_S_i
jmp .L14
.L26:
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 48(%rsp), %rax
subq 32(%rsp), %rax
imulq $1000000, %rax, %rax
addq 56(%rsp), %rax
subq 40(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
movl $4, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %edx
.L17:
movsd (%r12,%rdx,8), %xmm0
cvttsd2sil %xmm0, %ecx
leal (%rdx,%rdx), %eax
cmpl %eax, %ecx
jne .L27
addq $1, %rdx
cmpq $10240000, %rdx
jne .L17
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call cudaFree@PLT
movl $0, %esi
movq %rsi, %rdi
call cudaFree@PLT
movl $0, %edx
movq %rdx, %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z8multiplyPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z8multiplyPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <assert.h>
#include <cuda.h>
#include <sys/time.h>
#define N 10240000
#define ThreadPerBlock 128
#define NSTREAM 4
__global__ void multiply(double * a, double *b , double * output, int length)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < length)
output[tid] = a[tid] + b[tid];
}
int main()
{
cudaSetDevice(1);
int nbytes = N * sizeof (double);
double *a, *b, *c;
double *dev_A, *dev_B, *dev_C;
a = (double *) malloc( N*sizeof(double));
b = (double *) malloc( N*sizeof(double));
c = (double *) malloc( N*sizeof(double));
if(a == NULL){
printf("Error malloc \n");
exit(0);
}
int i;
for (i = 0; i < N ; i++)
{
a[i] = i;
b[i] = i;
}
assert(cudaMalloc((void**) &dev_A, nbytes) == cudaSuccess);
assert(cudaMalloc((void**) &dev_B, nbytes) == cudaSuccess);
assert(cudaMalloc((void**) &dev_C, nbytes) == cudaSuccess);
assert(cudaMemcpy(dev_A, a, nbytes, cudaMemcpyHostToDevice) == cudaSuccess);
assert(cudaMemcpy(dev_B, b, nbytes, cudaMemcpyHostToDevice) == cudaSuccess);
struct timeval begin, end;
gettimeofday(&begin, NULL);
int nblock = N/ThreadPerBlock;
if ( N % ThreadPerBlock) nblock ++;
multiply<<<nblock, ThreadPerBlock>>>(dev_A, dev_B, dev_C,N);
assert( cudaThreadSynchronize() == cudaSuccess ) ;
gettimeofday(&end, NULL);
double time = 1000000*(end.tv_sec - begin.tv_sec) + (end.tv_usec - begin.tv_usec);
printf("One Stream time: %lf ms \n", time);
cudaStream_t stream[NSTREAM];
int n = N/NSTREAM;
printf("%d\n", n);
assert( cudaThreadSynchronize() == cudaSuccess ) ;
gettimeofday(&begin, NULL);
for (i = 0; i < NSTREAM; i++)
{
nblock = n/ThreadPerBlock;
if(n % ThreadPerBlock) nblock++;
assert(cudaStreamCreate(&stream[i])== cudaSuccess);
multiply<<<nblock, ThreadPerBlock, 0, stream[i]>>>(&dev_A[i*n], &dev_B[i*n], &dev_C[i*n], n);
assert(cudaStreamDestroy(stream[i])== cudaSuccess);
}
assert( cudaThreadSynchronize() == cudaSuccess ) ;
gettimeofday(&end, NULL);
time = 1000000*(end.tv_sec - begin.tv_sec) + (end.tv_usec - begin.tv_usec);
printf("%d Stream time: %lf ms \n",NSTREAM, time);
assert(cudaMemcpy(c, dev_C, nbytes, cudaMemcpyDeviceToHost) == cudaSuccess);
for (i = 0; i < N; i++)
{
int d = (int) c[i];
int e = 2*i;
if( d != e)
{
printf("Error, %d, %lf\n", i, c[i]);
exit(0);
}
}
printf("Passed!!\n");
cudaFree(dev_A);
cudaFree(dev_B);
cudaFree(dev_C);
free(a);
free(b);
free(c);
} | #include <stdio.h>
#include <assert.h>
#include <hip/hip_runtime.h>
#include <sys/time.h>
#define N 10240000
#define ThreadPerBlock 128
#define NSTREAM 4
__global__ void multiply(double * a, double *b , double * output, int length)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < length)
output[tid] = a[tid] + b[tid];
}
int main()
{
hipSetDevice(1);
int nbytes = N * sizeof (double);
double *a, *b, *c;
double *dev_A, *dev_B, *dev_C;
a = (double *) malloc( N*sizeof(double));
b = (double *) malloc( N*sizeof(double));
c = (double *) malloc( N*sizeof(double));
if(a == NULL){
printf("Error malloc \n");
exit(0);
}
int i;
for (i = 0; i < N ; i++)
{
a[i] = i;
b[i] = i;
}
assert(hipMalloc((void**) &dev_A, nbytes) == hipSuccess);
assert(hipMalloc((void**) &dev_B, nbytes) == hipSuccess);
assert(hipMalloc((void**) &dev_C, nbytes) == hipSuccess);
assert(hipMemcpy(dev_A, a, nbytes, hipMemcpyHostToDevice) == hipSuccess);
assert(hipMemcpy(dev_B, b, nbytes, hipMemcpyHostToDevice) == hipSuccess);
struct timeval begin, end;
gettimeofday(&begin, NULL);
int nblock = N/ThreadPerBlock;
if ( N % ThreadPerBlock) nblock ++;
multiply<<<nblock, ThreadPerBlock>>>(dev_A, dev_B, dev_C,N);
assert( hipDeviceSynchronize() == hipSuccess ) ;
gettimeofday(&end, NULL);
double time = 1000000*(end.tv_sec - begin.tv_sec) + (end.tv_usec - begin.tv_usec);
printf("One Stream time: %lf ms \n", time);
hipStream_t stream[NSTREAM];
int n = N/NSTREAM;
printf("%d\n", n);
assert( hipDeviceSynchronize() == hipSuccess ) ;
gettimeofday(&begin, NULL);
for (i = 0; i < NSTREAM; i++)
{
nblock = n/ThreadPerBlock;
if(n % ThreadPerBlock) nblock++;
assert(hipStreamCreate(&stream[i])== hipSuccess);
multiply<<<nblock, ThreadPerBlock, 0, stream[i]>>>(&dev_A[i*n], &dev_B[i*n], &dev_C[i*n], n);
assert(hipStreamDestroy(stream[i])== hipSuccess);
}
assert( hipDeviceSynchronize() == hipSuccess ) ;
gettimeofday(&end, NULL);
time = 1000000*(end.tv_sec - begin.tv_sec) + (end.tv_usec - begin.tv_usec);
printf("%d Stream time: %lf ms \n",NSTREAM, time);
assert(hipMemcpy(c, dev_C, nbytes, hipMemcpyDeviceToHost) == hipSuccess);
for (i = 0; i < N; i++)
{
int d = (int) c[i];
int e = 2*i;
if( d != e)
{
printf("Error, %d, %lf\n", i, c[i]);
exit(0);
}
}
printf("Passed!!\n");
hipFree(dev_A);
hipFree(dev_B);
hipFree(dev_C);
free(a);
free(b);
free(c);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <assert.h>
#include <hip/hip_runtime.h>
#include <sys/time.h>
#define N 10240000
#define ThreadPerBlock 128
#define NSTREAM 4
__global__ void multiply(double * a, double *b , double * output, int length)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < length)
output[tid] = a[tid] + b[tid];
}
int main()
{
hipSetDevice(1);
int nbytes = N * sizeof (double);
double *a, *b, *c;
double *dev_A, *dev_B, *dev_C;
a = (double *) malloc( N*sizeof(double));
b = (double *) malloc( N*sizeof(double));
c = (double *) malloc( N*sizeof(double));
if(a == NULL){
printf("Error malloc \n");
exit(0);
}
int i;
for (i = 0; i < N ; i++)
{
a[i] = i;
b[i] = i;
}
assert(hipMalloc((void**) &dev_A, nbytes) == hipSuccess);
assert(hipMalloc((void**) &dev_B, nbytes) == hipSuccess);
assert(hipMalloc((void**) &dev_C, nbytes) == hipSuccess);
assert(hipMemcpy(dev_A, a, nbytes, hipMemcpyHostToDevice) == hipSuccess);
assert(hipMemcpy(dev_B, b, nbytes, hipMemcpyHostToDevice) == hipSuccess);
struct timeval begin, end;
gettimeofday(&begin, NULL);
int nblock = N/ThreadPerBlock;
if ( N % ThreadPerBlock) nblock ++;
multiply<<<nblock, ThreadPerBlock>>>(dev_A, dev_B, dev_C,N);
assert( hipDeviceSynchronize() == hipSuccess ) ;
gettimeofday(&end, NULL);
double time = 1000000*(end.tv_sec - begin.tv_sec) + (end.tv_usec - begin.tv_usec);
printf("One Stream time: %lf ms \n", time);
hipStream_t stream[NSTREAM];
int n = N/NSTREAM;
printf("%d\n", n);
assert( hipDeviceSynchronize() == hipSuccess ) ;
gettimeofday(&begin, NULL);
for (i = 0; i < NSTREAM; i++)
{
nblock = n/ThreadPerBlock;
if(n % ThreadPerBlock) nblock++;
assert(hipStreamCreate(&stream[i])== hipSuccess);
multiply<<<nblock, ThreadPerBlock, 0, stream[i]>>>(&dev_A[i*n], &dev_B[i*n], &dev_C[i*n], n);
assert(hipStreamDestroy(stream[i])== hipSuccess);
}
assert( hipDeviceSynchronize() == hipSuccess ) ;
gettimeofday(&end, NULL);
time = 1000000*(end.tv_sec - begin.tv_sec) + (end.tv_usec - begin.tv_usec);
printf("%d Stream time: %lf ms \n",NSTREAM, time);
assert(hipMemcpy(c, dev_C, nbytes, hipMemcpyDeviceToHost) == hipSuccess);
for (i = 0; i < N; i++)
{
int d = (int) c[i];
int e = 2*i;
if( d != e)
{
printf("Error, %d, %lf\n", i, c[i]);
exit(0);
}
}
printf("Passed!!\n");
hipFree(dev_A);
hipFree(dev_B);
hipFree(dev_C);
free(a);
free(b);
free(c);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8multiplyPdS_S_i
.globl _Z8multiplyPdS_S_i
.p2align 8
.type _Z8multiplyPdS_S_i,@function
_Z8multiplyPdS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8multiplyPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8multiplyPdS_S_i, .Lfunc_end0-_Z8multiplyPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8multiplyPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8multiplyPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <assert.h>
#include <hip/hip_runtime.h>
#include <sys/time.h>
#define N 10240000
#define ThreadPerBlock 128
#define NSTREAM 4
__global__ void multiply(double * a, double *b , double * output, int length)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < length)
output[tid] = a[tid] + b[tid];
}
int main()
{
hipSetDevice(1);
int nbytes = N * sizeof (double);
double *a, *b, *c;
double *dev_A, *dev_B, *dev_C;
a = (double *) malloc( N*sizeof(double));
b = (double *) malloc( N*sizeof(double));
c = (double *) malloc( N*sizeof(double));
if(a == NULL){
printf("Error malloc \n");
exit(0);
}
int i;
for (i = 0; i < N ; i++)
{
a[i] = i;
b[i] = i;
}
assert(hipMalloc((void**) &dev_A, nbytes) == hipSuccess);
assert(hipMalloc((void**) &dev_B, nbytes) == hipSuccess);
assert(hipMalloc((void**) &dev_C, nbytes) == hipSuccess);
assert(hipMemcpy(dev_A, a, nbytes, hipMemcpyHostToDevice) == hipSuccess);
assert(hipMemcpy(dev_B, b, nbytes, hipMemcpyHostToDevice) == hipSuccess);
struct timeval begin, end;
gettimeofday(&begin, NULL);
int nblock = N/ThreadPerBlock;
if ( N % ThreadPerBlock) nblock ++;
multiply<<<nblock, ThreadPerBlock>>>(dev_A, dev_B, dev_C,N);
assert( hipDeviceSynchronize() == hipSuccess ) ;
gettimeofday(&end, NULL);
double time = 1000000*(end.tv_sec - begin.tv_sec) + (end.tv_usec - begin.tv_usec);
printf("One Stream time: %lf ms \n", time);
hipStream_t stream[NSTREAM];
int n = N/NSTREAM;
printf("%d\n", n);
assert( hipDeviceSynchronize() == hipSuccess ) ;
gettimeofday(&begin, NULL);
for (i = 0; i < NSTREAM; i++)
{
nblock = n/ThreadPerBlock;
if(n % ThreadPerBlock) nblock++;
assert(hipStreamCreate(&stream[i])== hipSuccess);
multiply<<<nblock, ThreadPerBlock, 0, stream[i]>>>(&dev_A[i*n], &dev_B[i*n], &dev_C[i*n], n);
assert(hipStreamDestroy(stream[i])== hipSuccess);
}
assert( hipDeviceSynchronize() == hipSuccess ) ;
gettimeofday(&end, NULL);
time = 1000000*(end.tv_sec - begin.tv_sec) + (end.tv_usec - begin.tv_usec);
printf("%d Stream time: %lf ms \n",NSTREAM, time);
assert(hipMemcpy(c, dev_C, nbytes, hipMemcpyDeviceToHost) == hipSuccess);
for (i = 0; i < N; i++)
{
int d = (int) c[i];
int e = 2*i;
if( d != e)
{
printf("Error, %d, %lf\n", i, c[i]);
exit(0);
}
}
printf("Passed!!\n");
hipFree(dev_A);
hipFree(dev_B);
hipFree(dev_C);
free(a);
free(b);
free(c);
} | .text
.file "concurrentKernel.hip"
.globl _Z23__device_stub__multiplyPdS_S_i # -- Begin function _Z23__device_stub__multiplyPdS_S_i
.p2align 4, 0x90
.type _Z23__device_stub__multiplyPdS_S_i,@function
_Z23__device_stub__multiplyPdS_S_i: # @_Z23__device_stub__multiplyPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8multiplyPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__multiplyPdS_S_i, .Lfunc_end0-_Z23__device_stub__multiplyPdS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967424, %r14 # imm = 0x100000080
movl $1, %edi
callq hipSetDevice
movl $81920000, %edi # imm = 0x4E20000
callq malloc
movq %rax, %rbx
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
leaq 79872(%r14), %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 80(%rsp), %rax
leaq 64(%rsp), %rcx
movl $10240000, 16(%rsp) # imm = 0x9C4000
movq %rax, 96(%rsp)
movq %rcx, 104(%rsp)
leaq 136(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rdi
movq %rsp, %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8multiplyPdS_S_i, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
xorl %ebp, %ebp
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rax
movq 8(%rsp), %rcx
subq 32(%rsp), %rax
subq 40(%rsp), %rcx
imulq $1000000, %rax, %rax # imm = 0xF4240
addq %rax, %rcx
cvtsi2sd %rcx, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movl $.L.str.2, %edi
movl $2560000, %esi # imm = 0x271000
xorl %eax, %eax
callq printf
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
leaq 19872(%r14), %r15
leaq 128(%rsp), %r12
leaq 96(%rsp), %r13
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_3 Depth=1
incq %rbp
cmpq $4, %rbp
je .LBB1_6
.LBB1_3: # =>This Inner Loop Header: Depth=1
movq 144(%rsp,%rbp,8), %r9
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_3 Depth=1
movl $2560000, 28(%rsp) # imm = 0x271000
leaq 136(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rax
movq %rax, 112(%rsp)
leaq 28(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 16(%rsp), %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z8multiplyPdS_S_i, %edi
movq %r13, %r9
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_5
.LBB1_6:
xorl %r14d, %r14d
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rax
movq 8(%rsp), %rcx
subq 32(%rsp), %rax
subq 40(%rsp), %rcx
imulq $1000000, %rax, %rax # imm = 0xF4240
addq %rax, %rcx
xorps %xmm0, %xmm0
cvtsi2sd %rcx, %xmm0
movl $.L.str.3, %edi
movl $4, %esi
movb $1, %al
callq printf
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movsd (%rbx,%rsi,8), %xmm0 # xmm0 = mem[0],zero
cvttsd2si %xmm0, %eax
cmpq %rax, %r14
jne .LBB1_10
# %bb.8: # in Loop: Header=BB1_7 Depth=1
incq %rsi
addq $2, %r14
cmpq $10240000, %rsi # imm = 0x9C4000
jne .LBB1_7
# %bb.9:
movl $.Lstr, %edi
callq puts@PLT
callq hipFree
callq hipFree
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_10:
.cfi_def_cfa_offset 240
movl $.L.str.4, %edi
# kill: def $esi killed $esi killed $rsi
movb $1, %al
callq printf
xorl %edi, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8multiplyPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8multiplyPdS_S_i,@object # @_Z8multiplyPdS_S_i
.section .rodata,"a",@progbits
.globl _Z8multiplyPdS_S_i
.p2align 3, 0x0
_Z8multiplyPdS_S_i:
.quad _Z23__device_stub__multiplyPdS_S_i
.size _Z8multiplyPdS_S_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "One Stream time: %lf ms \n"
.size .L.str.1, 26
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d\n"
.size .L.str.2, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d Stream time: %lf ms \n"
.size .L.str.3, 25
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Error, %d, %lf\n"
.size .L.str.4, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8multiplyPdS_S_i"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Passed!!"
.size .Lstr, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__multiplyPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8multiplyPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8multiplyPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R8, R9, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R2, R8.reuse, R9.reuse, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0209 */
/*00d0*/ DADD R6, R4, R2 ; /* 0x0000000004067229 */
/* 0x004e0e0000000002 */
/*00e0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8multiplyPdS_S_i
.globl _Z8multiplyPdS_S_i
.p2align 8
.type _Z8multiplyPdS_S_i,@function
_Z8multiplyPdS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8multiplyPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8multiplyPdS_S_i, .Lfunc_end0-_Z8multiplyPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8multiplyPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8multiplyPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001bb225_00000000-6_concurrentKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z8multiplyPdS_S_iPdS_S_i
.type _Z32__device_stub__Z8multiplyPdS_S_iPdS_S_i, @function
_Z32__device_stub__Z8multiplyPdS_S_iPdS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8multiplyPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z8multiplyPdS_S_iPdS_S_i, .-_Z32__device_stub__Z8multiplyPdS_S_iPdS_S_i
.globl _Z8multiplyPdS_S_i
.type _Z8multiplyPdS_S_i, @function
_Z8multiplyPdS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8multiplyPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8multiplyPdS_S_i, .-_Z8multiplyPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Error malloc \n"
.LC1:
.string "One Stream time: %lf ms \n"
.LC2:
.string "%d\n"
.LC3:
.string "%d Stream time: %lf ms \n"
.LC4:
.string "Error, %d, %lf\n"
.LC5:
.string "Passed!!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $112, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $1, %edi
call cudaSetDevice@PLT
movl $81920000, %edi
call malloc@PLT
movq %rax, %rbx
movl $81920000, %edi
call malloc@PLT
movq %rax, %rbp
movl $81920000, %edi
call malloc@PLT
testq %rbx, %rbx
je .L24
movq %rax, %r12
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%rbx,%rax,8)
movsd %xmm0, 0(%rbp,%rax,8)
addq $1, %rax
cmpq $10240000, %rax
jne .L12
leaq 32(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $128, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $80000, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L13:
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 48(%rsp), %rax
subq 32(%rsp), %rax
imulq $1000000, %rax, %rax
addq 56(%rsp), %rax
subq 40(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2560000, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
leaq 64(%rsp), %r14
movl $0, %r13d
jmp .L15
.L24:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L25:
movl $10240000, %ecx
movl $0, %edx
movl $0, %esi
movl $0, %edi
call _Z32__device_stub__Z8multiplyPdS_S_iPdS_S_i
jmp .L13
.L14:
addq $8, %r14
addq $20480000, %r13
cmpq $81920000, %r13
je .L26
.L15:
movl $128, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $20000, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movq (%r14), %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L14
movq %r13, %rdx
movq %r13, %rsi
movq %r13, %rdi
movl $2560000, %ecx
call _Z32__device_stub__Z8multiplyPdS_S_iPdS_S_i
jmp .L14
.L26:
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 48(%rsp), %rax
subq 32(%rsp), %rax
imulq $1000000, %rax, %rax
addq 56(%rsp), %rax
subq 40(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
movl $4, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %edx
.L17:
movsd (%r12,%rdx,8), %xmm0
cvttsd2sil %xmm0, %ecx
leal (%rdx,%rdx), %eax
cmpl %eax, %ecx
jne .L27
addq $1, %rdx
cmpq $10240000, %rdx
jne .L17
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call cudaFree@PLT
movl $0, %esi
movq %rsi, %rdi
call cudaFree@PLT
movl $0, %edx
movq %rdx, %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z8multiplyPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z8multiplyPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "concurrentKernel.hip"
.globl _Z23__device_stub__multiplyPdS_S_i # -- Begin function _Z23__device_stub__multiplyPdS_S_i
.p2align 4, 0x90
.type _Z23__device_stub__multiplyPdS_S_i,@function
_Z23__device_stub__multiplyPdS_S_i: # @_Z23__device_stub__multiplyPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8multiplyPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__multiplyPdS_S_i, .Lfunc_end0-_Z23__device_stub__multiplyPdS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967424, %r14 # imm = 0x100000080
movl $1, %edi
callq hipSetDevice
movl $81920000, %edi # imm = 0x4E20000
callq malloc
movq %rax, %rbx
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
leaq 79872(%r14), %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 80(%rsp), %rax
leaq 64(%rsp), %rcx
movl $10240000, 16(%rsp) # imm = 0x9C4000
movq %rax, 96(%rsp)
movq %rcx, 104(%rsp)
leaq 136(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rdi
movq %rsp, %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8multiplyPdS_S_i, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
xorl %ebp, %ebp
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rax
movq 8(%rsp), %rcx
subq 32(%rsp), %rax
subq 40(%rsp), %rcx
imulq $1000000, %rax, %rax # imm = 0xF4240
addq %rax, %rcx
cvtsi2sd %rcx, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movl $.L.str.2, %edi
movl $2560000, %esi # imm = 0x271000
xorl %eax, %eax
callq printf
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
leaq 19872(%r14), %r15
leaq 128(%rsp), %r12
leaq 96(%rsp), %r13
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_3 Depth=1
incq %rbp
cmpq $4, %rbp
je .LBB1_6
.LBB1_3: # =>This Inner Loop Header: Depth=1
movq 144(%rsp,%rbp,8), %r9
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_3 Depth=1
movl $2560000, 28(%rsp) # imm = 0x271000
leaq 136(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rax
movq %rax, 112(%rsp)
leaq 28(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 16(%rsp), %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z8multiplyPdS_S_i, %edi
movq %r13, %r9
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_5
.LBB1_6:
xorl %r14d, %r14d
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rax
movq 8(%rsp), %rcx
subq 32(%rsp), %rax
subq 40(%rsp), %rcx
imulq $1000000, %rax, %rax # imm = 0xF4240
addq %rax, %rcx
xorps %xmm0, %xmm0
cvtsi2sd %rcx, %xmm0
movl $.L.str.3, %edi
movl $4, %esi
movb $1, %al
callq printf
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movsd (%rbx,%rsi,8), %xmm0 # xmm0 = mem[0],zero
cvttsd2si %xmm0, %eax
cmpq %rax, %r14
jne .LBB1_10
# %bb.8: # in Loop: Header=BB1_7 Depth=1
incq %rsi
addq $2, %r14
cmpq $10240000, %rsi # imm = 0x9C4000
jne .LBB1_7
# %bb.9:
movl $.Lstr, %edi
callq puts@PLT
callq hipFree
callq hipFree
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_10:
.cfi_def_cfa_offset 240
movl $.L.str.4, %edi
# kill: def $esi killed $esi killed $rsi
movb $1, %al
callq printf
xorl %edi, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8multiplyPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8multiplyPdS_S_i,@object # @_Z8multiplyPdS_S_i
.section .rodata,"a",@progbits
.globl _Z8multiplyPdS_S_i
.p2align 3, 0x0
_Z8multiplyPdS_S_i:
.quad _Z23__device_stub__multiplyPdS_S_i
.size _Z8multiplyPdS_S_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "One Stream time: %lf ms \n"
.size .L.str.1, 26
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d\n"
.size .L.str.2, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d Stream time: %lf ms \n"
.size .L.str.3, 25
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Error, %d, %lf\n"
.size .L.str.4, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8multiplyPdS_S_i"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Passed!!"
.size .Lstr, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__multiplyPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8multiplyPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kMultiSoftmaxCost(float* probs, float* labels, float* maxProbs, float* labelLogProbs, float* correctProbs, float* top5Probs, const int numCases, const int numOut, const int setSize) {
const int tx = blockIdx.x * LOGREG_ERR_THREADS_X + threadIdx.x;
if (tx < numCases) {
const int label = int(labels[tx]);
const float maxp = maxProbs[tx];
const float labelp = probs[label * numCases + tx];
labelLogProbs[tx] = __logf(labelp);
int numBiggerProbs = 0, numEqualsProbs = 0;
for (int i = 0; i < numOut; ++i) {
numBiggerProbs += probs[i * numCases + tx] > labelp;
numEqualsProbs += probs[i * numCases + tx] == labelp;
}
const int slotsLeft = setSize - numBiggerProbs;
top5Probs[tx] = slotsLeft <= 0.0f ? 0.0f : (numEqualsProbs <= slotsLeft ? 1.0f : float(slotsLeft) / numEqualsProbs);
correctProbs[tx] = labelp != maxp ? 0.0f : 1.0f / float(numEqualsProbs);
}
} | .file "tmpxft_0017432b_00000000-6_kMultiSoftmaxCost.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z17kMultiSoftmaxCostPfS_S_S_S_S_iiiPfS_S_S_S_S_iii
.type _Z50__device_stub__Z17kMultiSoftmaxCostPfS_S_S_S_S_iiiPfS_S_S_S_S_iii, @function
_Z50__device_stub__Z17kMultiSoftmaxCostPfS_S_S_S_S_iiiPfS_S_S_S_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17kMultiSoftmaxCostPfS_S_S_S_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z17kMultiSoftmaxCostPfS_S_S_S_S_iiiPfS_S_S_S_S_iii, .-_Z50__device_stub__Z17kMultiSoftmaxCostPfS_S_S_S_S_iiiPfS_S_S_S_S_iii
.globl _Z17kMultiSoftmaxCostPfS_S_S_S_S_iii
.type _Z17kMultiSoftmaxCostPfS_S_S_S_S_iii, @function
_Z17kMultiSoftmaxCostPfS_S_S_S_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z50__device_stub__Z17kMultiSoftmaxCostPfS_S_S_S_S_iiiPfS_S_S_S_S_iii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17kMultiSoftmaxCostPfS_S_S_S_S_iii, .-_Z17kMultiSoftmaxCostPfS_S_S_S_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17kMultiSoftmaxCostPfS_S_S_S_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17kMultiSoftmaxCostPfS_S_S_S_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kMultiSoftmaxCost(float* probs, float* labels, float* maxProbs, float* labelLogProbs, float* correctProbs, float* top5Probs, const int numCases, const int numOut, const int setSize) {
const int tx = blockIdx.x * LOGREG_ERR_THREADS_X + threadIdx.x;
if (tx < numCases) {
const int label = int(labels[tx]);
const float maxp = maxProbs[tx];
const float labelp = probs[label * numCases + tx];
labelLogProbs[tx] = __logf(labelp);
int numBiggerProbs = 0, numEqualsProbs = 0;
for (int i = 0; i < numOut; ++i) {
numBiggerProbs += probs[i * numCases + tx] > labelp;
numEqualsProbs += probs[i * numCases + tx] == labelp;
}
const int slotsLeft = setSize - numBiggerProbs;
top5Probs[tx] = slotsLeft <= 0.0f ? 0.0f : (numEqualsProbs <= slotsLeft ? 1.0f : float(slotsLeft) / numEqualsProbs);
correctProbs[tx] = labelp != maxp ? 0.0f : 1.0f / float(numEqualsProbs);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kMultiSoftmaxCost(float* probs, float* labels, float* maxProbs, float* labelLogProbs, float* correctProbs, float* top5Probs, const int numCases, const int numOut, const int setSize) {
const int tx = blockIdx.x * LOGREG_ERR_THREADS_X + threadIdx.x;
if (tx < numCases) {
const int label = int(labels[tx]);
const float maxp = maxProbs[tx];
const float labelp = probs[label * numCases + tx];
labelLogProbs[tx] = __logf(labelp);
int numBiggerProbs = 0, numEqualsProbs = 0;
for (int i = 0; i < numOut; ++i) {
numBiggerProbs += probs[i * numCases + tx] > labelp;
numEqualsProbs += probs[i * numCases + tx] == labelp;
}
const int slotsLeft = setSize - numBiggerProbs;
top5Probs[tx] = slotsLeft <= 0.0f ? 0.0f : (numEqualsProbs <= slotsLeft ? 1.0f : float(slotsLeft) / numEqualsProbs);
correctProbs[tx] = labelp != maxp ? 0.0f : 1.0f / float(numEqualsProbs);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kMultiSoftmaxCost(float* probs, float* labels, float* maxProbs, float* labelLogProbs, float* correctProbs, float* top5Probs, const int numCases, const int numOut, const int setSize) {
const int tx = blockIdx.x * LOGREG_ERR_THREADS_X + threadIdx.x;
if (tx < numCases) {
const int label = int(labels[tx]);
const float maxp = maxProbs[tx];
const float labelp = probs[label * numCases + tx];
labelLogProbs[tx] = __logf(labelp);
int numBiggerProbs = 0, numEqualsProbs = 0;
for (int i = 0; i < numOut; ++i) {
numBiggerProbs += probs[i * numCases + tx] > labelp;
numEqualsProbs += probs[i * numCases + tx] == labelp;
}
const int slotsLeft = setSize - numBiggerProbs;
top5Probs[tx] = slotsLeft <= 0.0f ? 0.0f : (numEqualsProbs <= slotsLeft ? 1.0f : float(slotsLeft) / numEqualsProbs);
correctProbs[tx] = labelp != maxp ? 0.0f : 1.0f / float(numEqualsProbs);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17kMultiSoftmaxCostPfS_S_S_S_S_iii
.globl _Z17kMultiSoftmaxCostPfS_S_S_S_S_iii
.p2align 8
.type _Z17kMultiSoftmaxCostPfS_S_S_S_S_iii,@function
_Z17kMultiSoftmaxCostPfS_S_S_S_S_iii:
s_load_b32 s2, s[0:1], 0x30
v_lshl_add_u32 v0, s15, 7, v0
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB0_11
s_load_b256 s[4:11], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_load_b32 s3, s[0:1], 0x34
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
s_cmp_lt_i32 s3, 1
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v6, v4
v_mad_u64_u32 v[4:5], null, v6, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v4, v[4:5], off
v_add_co_u32 v5, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v3, vcc_lo
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(1)
v_cmp_gt_f32_e32 vcc_lo, 0x800000, v4
v_cndmask_b32_e64 v6, 1.0, 0x4f800000, vcc_lo
v_cndmask_b32_e64 v8, 0, 0x41b17218, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v4, v6
v_log_f32_e32 v6, v6
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v7, 0x3f317217, v6
v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v6|
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, v6, 0x3f317217, -v7
v_fmamk_f32 v7, v6, 0x3377d1cf, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, 0x3f317217, v6
v_cndmask_b32_e32 v6, v6, v7, vcc_lo
v_add_co_u32 v2, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_sub_f32_e32 v8, v6, v8
v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v7, 0
global_store_b32 v[2:3], v8, off
s_cbranch_scc1 .LBB0_4
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v2, v0
v_mov_b32_e32 v6, 0
.LBB0_3:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v3, 31, v2
s_add_i32 s3, s3, -1
s_cmp_eq_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[8:9], 2, v[2:3]
v_add_nc_u32_e32 v2, s2, v2
v_add_co_u32 v8, vcc_lo, s4, v8
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
global_load_b32 v3, v[8:9], off
s_waitcnt vmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, v3, v4
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, v3, v4
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_cbranch_scc0 .LBB0_3
.LBB0_4:
s_load_b32 s2, s[0:1], 0x38
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0
s_waitcnt lgkmcnt(0)
v_sub_nc_u32_e32 v7, s2, v7
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e32 0, v7
s_cbranch_execz .LBB0_8
v_mov_b32_e32 v3, 1.0
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 v6, v7
s_cbranch_execz .LBB0_7
v_cvt_f32_i32_e32 v3, v7
v_cvt_f32_i32_e32 v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v8, null, v7, v7, v3
v_rcp_f32_e32 v9, v8
s_waitcnt_depctr 0xfff
v_fma_f32 v10, -v8, v9, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v9, v10, v9
v_div_scale_f32 v10, vcc_lo, v3, v7, v3
v_mul_f32_e32 v11, v10, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v12, -v8, v11, v10
v_fmac_f32_e32 v11, v12, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v8, v11, v10
v_div_fmas_f32 v8, v8, v9, v11
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v3, v8, v7, v3
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s3
.LBB0_8:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[2:3], s[0:1], 0x28
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v1, vcc_lo
s_mov_b32 s2, exec_lo
global_store_b32 v[7:8], v3, off
s_waitcnt vmcnt(0)
v_cmpx_eq_f32_e32 v4, v5
s_cbranch_execz .LBB0_10
v_cvt_f32_i32_e32 v2, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v3, null, v2, v2, 1.0
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v4
v_div_scale_f32 v5, vcc_lo, 1.0, v2, 1.0
v_mul_f32_e32 v6, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v3, v6, v5
v_fmac_f32_e32 v6, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v6, v5
v_div_fmas_f32 v3, v3, v4, v6
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v2, v3, v2, 1.0
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17kMultiSoftmaxCostPfS_S_S_S_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 60
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17kMultiSoftmaxCostPfS_S_S_S_S_iii, .Lfunc_end0-_Z17kMultiSoftmaxCostPfS_S_S_S_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 60
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17kMultiSoftmaxCostPfS_S_S_S_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17kMultiSoftmaxCostPfS_S_S_S_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kMultiSoftmaxCost(float* probs, float* labels, float* maxProbs, float* labelLogProbs, float* correctProbs, float* top5Probs, const int numCases, const int numOut, const int setSize) {
const int tx = blockIdx.x * LOGREG_ERR_THREADS_X + threadIdx.x;
if (tx < numCases) {
const int label = int(labels[tx]);
const float maxp = maxProbs[tx];
const float labelp = probs[label * numCases + tx];
labelLogProbs[tx] = __logf(labelp);
int numBiggerProbs = 0, numEqualsProbs = 0;
for (int i = 0; i < numOut; ++i) {
numBiggerProbs += probs[i * numCases + tx] > labelp;
numEqualsProbs += probs[i * numCases + tx] == labelp;
}
const int slotsLeft = setSize - numBiggerProbs;
top5Probs[tx] = slotsLeft <= 0.0f ? 0.0f : (numEqualsProbs <= slotsLeft ? 1.0f : float(slotsLeft) / numEqualsProbs);
correctProbs[tx] = labelp != maxp ? 0.0f : 1.0f / float(numEqualsProbs);
}
} | .text
.file "kMultiSoftmaxCost.hip"
.globl _Z32__device_stub__kMultiSoftmaxCostPfS_S_S_S_S_iii # -- Begin function _Z32__device_stub__kMultiSoftmaxCostPfS_S_S_S_S_iii
.p2align 4, 0x90
.type _Z32__device_stub__kMultiSoftmaxCostPfS_S_S_S_S_iii,@function
_Z32__device_stub__kMultiSoftmaxCostPfS_S_S_S_S_iii: # @_Z32__device_stub__kMultiSoftmaxCostPfS_S_S_S_S_iii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17kMultiSoftmaxCostPfS_S_S_S_S_iii, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z32__device_stub__kMultiSoftmaxCostPfS_S_S_S_S_iii, .Lfunc_end0-_Z32__device_stub__kMultiSoftmaxCostPfS_S_S_S_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17kMultiSoftmaxCostPfS_S_S_S_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17kMultiSoftmaxCostPfS_S_S_S_S_iii,@object # @_Z17kMultiSoftmaxCostPfS_S_S_S_S_iii
.section .rodata,"a",@progbits
.globl _Z17kMultiSoftmaxCostPfS_S_S_S_S_iii
.p2align 3, 0x0
_Z17kMultiSoftmaxCostPfS_S_S_S_S_iii:
.quad _Z32__device_stub__kMultiSoftmaxCostPfS_S_S_S_S_iii
.size _Z17kMultiSoftmaxCostPfS_S_S_S_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17kMultiSoftmaxCostPfS_S_S_S_S_iii"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__kMultiSoftmaxCostPfS_S_S_S_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17kMultiSoftmaxCostPfS_S_S_S_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017432b_00000000-6_kMultiSoftmaxCost.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z17kMultiSoftmaxCostPfS_S_S_S_S_iiiPfS_S_S_S_S_iii
.type _Z50__device_stub__Z17kMultiSoftmaxCostPfS_S_S_S_S_iiiPfS_S_S_S_S_iii, @function
_Z50__device_stub__Z17kMultiSoftmaxCostPfS_S_S_S_S_iiiPfS_S_S_S_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17kMultiSoftmaxCostPfS_S_S_S_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z17kMultiSoftmaxCostPfS_S_S_S_S_iiiPfS_S_S_S_S_iii, .-_Z50__device_stub__Z17kMultiSoftmaxCostPfS_S_S_S_S_iiiPfS_S_S_S_S_iii
.globl _Z17kMultiSoftmaxCostPfS_S_S_S_S_iii
.type _Z17kMultiSoftmaxCostPfS_S_S_S_S_iii, @function
_Z17kMultiSoftmaxCostPfS_S_S_S_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z50__device_stub__Z17kMultiSoftmaxCostPfS_S_S_S_S_iiiPfS_S_S_S_S_iii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17kMultiSoftmaxCostPfS_S_S_S_S_iii, .-_Z17kMultiSoftmaxCostPfS_S_S_S_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17kMultiSoftmaxCostPfS_S_S_S_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17kMultiSoftmaxCostPfS_S_S_S_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kMultiSoftmaxCost.hip"
.globl _Z32__device_stub__kMultiSoftmaxCostPfS_S_S_S_S_iii # -- Begin function _Z32__device_stub__kMultiSoftmaxCostPfS_S_S_S_S_iii
.p2align 4, 0x90
.type _Z32__device_stub__kMultiSoftmaxCostPfS_S_S_S_S_iii,@function
_Z32__device_stub__kMultiSoftmaxCostPfS_S_S_S_S_iii: # @_Z32__device_stub__kMultiSoftmaxCostPfS_S_S_S_S_iii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17kMultiSoftmaxCostPfS_S_S_S_S_iii, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z32__device_stub__kMultiSoftmaxCostPfS_S_S_S_S_iii, .Lfunc_end0-_Z32__device_stub__kMultiSoftmaxCostPfS_S_S_S_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17kMultiSoftmaxCostPfS_S_S_S_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17kMultiSoftmaxCostPfS_S_S_S_S_iii,@object # @_Z17kMultiSoftmaxCostPfS_S_S_S_S_iii
.section .rodata,"a",@progbits
.globl _Z17kMultiSoftmaxCostPfS_S_S_S_S_iii
.p2align 3, 0x0
_Z17kMultiSoftmaxCostPfS_S_S_S_S_iii:
.quad _Z32__device_stub__kMultiSoftmaxCostPfS_S_S_S_S_iii
.size _Z17kMultiSoftmaxCostPfS_S_S_S_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17kMultiSoftmaxCostPfS_S_S_S_S_iii"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__kMultiSoftmaxCostPfS_S_S_S_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17kMultiSoftmaxCostPfS_S_S_S_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <iomanip>
using namespace std;
void Error(cudaError_t error)
{
if (error != cudaSuccess){
cout << "ERROR:" << cudaGetErrorString(error) << endl;
exit(0);
}
}
__global__ void sqr_items_vectors(double* a, double* result, int n)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
while (tid < n) {
result[tid] = a[tid]*a[tid];
tid += blockDim.x*gridDim.x;
}
}
int main()
{
int n, size;
double *a, *result;
double *gpu_a, *gpu_result;
cin >> n;
size = sizeof(double) * n;
a = (double*)malloc(size);
result = (double*)malloc(size);
for (int i = 0; i < n; ++i) {
cin >> a[i];
}
Error(cudaMalloc(&gpu_a, size));
Error(cudaMalloc(&gpu_result, size));
Error(cudaMemcpy(gpu_a, a, size, cudaMemcpyHostToDevice));
sqr_items_vectors<<<256, 256>>>(gpu_a, gpu_result, n);
Error(cudaMemcpy(result, gpu_result, size, cudaMemcpyDeviceToHost));
for (int i = 0; i < n; ++i) {
cout << scientific << setprecision(10) << result[i] << " ";
}
cout << endl;
Error(cudaFree(gpu_a));
Error(cudaFree(gpu_result));
free(a);
free(result);
return 0;
} | code for sm_80
Function : _Z17sqr_items_vectorsPdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0207 */
/*0090*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x000fe200078e0207 */
/*00b0*/ MOV R9, c[0x0][0x0] ; /* 0x0000000000097a02 */
/* 0x000fca0000000f00 */
/*00c0*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fca00078e0200 */
/*00d0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06270 */
/*00e0*/ DMUL R4, R2, R2 ; /* 0x0000000202047228 */
/* 0x004e0e0000000000 */
/*00f0*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x0011ea000c101b04 */
/*0100*/ @!P0 BRA 0x70 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <iomanip>
using namespace std;
void Error(cudaError_t error)
{
if (error != cudaSuccess){
cout << "ERROR:" << cudaGetErrorString(error) << endl;
exit(0);
}
}
__global__ void sqr_items_vectors(double* a, double* result, int n)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
while (tid < n) {
result[tid] = a[tid]*a[tid];
tid += blockDim.x*gridDim.x;
}
}
int main()
{
int n, size;
double *a, *result;
double *gpu_a, *gpu_result;
cin >> n;
size = sizeof(double) * n;
a = (double*)malloc(size);
result = (double*)malloc(size);
for (int i = 0; i < n; ++i) {
cin >> a[i];
}
Error(cudaMalloc(&gpu_a, size));
Error(cudaMalloc(&gpu_result, size));
Error(cudaMemcpy(gpu_a, a, size, cudaMemcpyHostToDevice));
sqr_items_vectors<<<256, 256>>>(gpu_a, gpu_result, n);
Error(cudaMemcpy(result, gpu_result, size, cudaMemcpyDeviceToHost));
for (int i = 0; i < n; ++i) {
cout << scientific << setprecision(10) << result[i] << " ";
}
cout << endl;
Error(cudaFree(gpu_a));
Error(cudaFree(gpu_result));
free(a);
free(result);
return 0;
} | .file "tmpxft_000c6489_00000000-6_lab1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3953:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3953:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "ERROR:"
.text
.globl _Z5Error9cudaError
.type _Z5Error9cudaError, @function
_Z5Error9cudaError:
.LFB3949:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L13
ret
.L13:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edi, %ebx
movl $6, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rbx
testq %rax, %rax
je .L14
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbx, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L6:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L15
cmpb $0, 56(%rbx)
je .L8
movzbl 67(%rbx), %esi
.L9:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $0, %edi
call exit@PLT
.L14:
leaq _ZSt4cout(%rip), %rdi
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L6
.L15:
call _ZSt16__throw_bad_castv@PLT
.L8:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L9
.cfi_endproc
.LFE3949:
.size _Z5Error9cudaError, .-_Z5Error9cudaError
.globl _Z40__device_stub__Z17sqr_items_vectorsPdS_iPdS_i
.type _Z40__device_stub__Z17sqr_items_vectorsPdS_iPdS_i, @function
_Z40__device_stub__Z17sqr_items_vectorsPdS_iPdS_i:
.LFB3975:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17sqr_items_vectorsPdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3975:
.size _Z40__device_stub__Z17sqr_items_vectorsPdS_iPdS_i, .-_Z40__device_stub__Z17sqr_items_vectorsPdS_iPdS_i
.globl _Z17sqr_items_vectorsPdS_i
.type _Z17sqr_items_vectorsPdS_i, @function
_Z17sqr_items_vectorsPdS_i:
.LFB3976:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z17sqr_items_vectorsPdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3976:
.size _Z17sqr_items_vectorsPdS_i, .-_Z17sqr_items_vectorsPdS_i
.section .rodata.str1.1
.LC1:
.string " "
.text
.globl main
.type main, @function
main:
.LFB3950:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
movl 12(%rsp), %ebx
leal 0(,%rbx,8), %r13d
movslq %r13d, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %r14
movq %r13, %rdi
call malloc@PLT
movq %rax, %r12
testl %ebx, %ebx
jle .L25
movq %r14, %rbp
movl $0, %ebx
leaq _ZSt3cin(%rip), %r15
.L26:
movq %rbp, %rsi
movq %r15, %rdi
call _ZNSi10_M_extractIdEERSiRT_@PLT
addl $1, %ebx
addq $8, %rbp
cmpl %ebx, 12(%rsp)
jg .L26
.L25:
leaq 16(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call _Z5Error9cudaError
leaq 24(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call _Z5Error9cudaError
movl $1, %ecx
movq %r13, %rdx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z5Error9cudaError
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $256, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L27:
movl $2, %ecx
movq %r13, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z5Error9cudaError
cmpl $0, 12(%rsp)
jle .L28
movl $0, %ebp
leaq _ZSt4cout(%rip), %rbx
leaq .LC1(%rip), %r13
.L29:
movq (%rbx), %rdx
movq %rbx, %rcx
addq -24(%rdx), %rcx
movl 24(%rcx), %eax
andl $-261, %eax
orb $1, %ah
movl %eax, 24(%rcx)
movq -24(%rdx), %rax
movq $10, 8(%rbx,%rax)
movsd (%r12,%rbp,8), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbp
cmpl %ebp, 12(%rsp)
jg .L29
.L28:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call _Z5Error9cudaError
movq 24(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call _Z5Error9cudaError
movq %r14, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movl 12(%rsp), %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z40__device_stub__Z17sqr_items_vectorsPdS_iPdS_i
jmp .L27
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3950:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z17sqr_items_vectorsPdS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3978:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z17sqr_items_vectorsPdS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3978:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <iomanip>
using namespace std;
void Error(cudaError_t error)
{
if (error != cudaSuccess){
cout << "ERROR:" << cudaGetErrorString(error) << endl;
exit(0);
}
}
__global__ void sqr_items_vectors(double* a, double* result, int n)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
while (tid < n) {
result[tid] = a[tid]*a[tid];
tid += blockDim.x*gridDim.x;
}
}
int main()
{
int n, size;
double *a, *result;
double *gpu_a, *gpu_result;
cin >> n;
size = sizeof(double) * n;
a = (double*)malloc(size);
result = (double*)malloc(size);
for (int i = 0; i < n; ++i) {
cin >> a[i];
}
Error(cudaMalloc(&gpu_a, size));
Error(cudaMalloc(&gpu_result, size));
Error(cudaMemcpy(gpu_a, a, size, cudaMemcpyHostToDevice));
sqr_items_vectors<<<256, 256>>>(gpu_a, gpu_result, n);
Error(cudaMemcpy(result, gpu_result, size, cudaMemcpyDeviceToHost));
for (int i = 0; i < n; ++i) {
cout << scientific << setprecision(10) << result[i] << " ";
}
cout << endl;
Error(cudaFree(gpu_a));
Error(cudaFree(gpu_result));
free(a);
free(result);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <iomanip>
using namespace std;
void Error(hipError_t error)
{
if (error != hipSuccess){
cout << "ERROR:" << hipGetErrorString(error) << endl;
exit(0);
}
}
__global__ void sqr_items_vectors(double* a, double* result, int n)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
while (tid < n) {
result[tid] = a[tid]*a[tid];
tid += blockDim.x*gridDim.x;
}
}
int main()
{
int n, size;
double *a, *result;
double *gpu_a, *gpu_result;
cin >> n;
size = sizeof(double) * n;
a = (double*)malloc(size);
result = (double*)malloc(size);
for (int i = 0; i < n; ++i) {
cin >> a[i];
}
Error(hipMalloc(&gpu_a, size));
Error(hipMalloc(&gpu_result, size));
Error(hipMemcpy(gpu_a, a, size, hipMemcpyHostToDevice));
sqr_items_vectors<<<256, 256>>>(gpu_a, gpu_result, n);
Error(hipMemcpy(result, gpu_result, size, hipMemcpyDeviceToHost));
for (int i = 0; i < n; ++i) {
cout << scientific << setprecision(10) << result[i] << " ";
}
cout << endl;
Error(hipFree(gpu_a));
Error(hipFree(gpu_result));
free(a);
free(result);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <iomanip>
using namespace std;
void Error(hipError_t error)
{
if (error != hipSuccess){
cout << "ERROR:" << hipGetErrorString(error) << endl;
exit(0);
}
}
__global__ void sqr_items_vectors(double* a, double* result, int n)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
while (tid < n) {
result[tid] = a[tid]*a[tid];
tid += blockDim.x*gridDim.x;
}
}
int main()
{
int n, size;
double *a, *result;
double *gpu_a, *gpu_result;
cin >> n;
size = sizeof(double) * n;
a = (double*)malloc(size);
result = (double*)malloc(size);
for (int i = 0; i < n; ++i) {
cin >> a[i];
}
Error(hipMalloc(&gpu_a, size));
Error(hipMalloc(&gpu_result, size));
Error(hipMemcpy(gpu_a, a, size, hipMemcpyHostToDevice));
sqr_items_vectors<<<256, 256>>>(gpu_a, gpu_result, n);
Error(hipMemcpy(result, gpu_result, size, hipMemcpyDeviceToHost));
for (int i = 0; i < n; ++i) {
cout << scientific << setprecision(10) << result[i] << " ";
}
cout << endl;
Error(hipFree(gpu_a));
Error(hipFree(gpu_result));
free(a);
free(result);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17sqr_items_vectorsPdS_i
.globl _Z17sqr_items_vectorsPdS_i
.p2align 8
.type _Z17sqr_items_vectorsPdS_i,@function
_Z17sqr_items_vectorsPdS_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s2, s9
s_mov_b32 s2, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s8, v1
v_add_co_u32 v2, s0, s6, v2
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e64 v3, s0, s7, v3, s0
s_or_b32 s2, vcc_lo, s2
s_waitcnt vmcnt(0)
v_mul_f64 v[4:5], v[4:5], v[4:5]
global_store_b64 v[2:3], v[4:5], off
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17sqr_items_vectorsPdS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17sqr_items_vectorsPdS_i, .Lfunc_end0-_Z17sqr_items_vectorsPdS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17sqr_items_vectorsPdS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17sqr_items_vectorsPdS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <iomanip>
using namespace std;
void Error(hipError_t error)
{
if (error != hipSuccess){
cout << "ERROR:" << hipGetErrorString(error) << endl;
exit(0);
}
}
__global__ void sqr_items_vectors(double* a, double* result, int n)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
while (tid < n) {
result[tid] = a[tid]*a[tid];
tid += blockDim.x*gridDim.x;
}
}
int main()
{
int n, size;
double *a, *result;
double *gpu_a, *gpu_result;
cin >> n;
size = sizeof(double) * n;
a = (double*)malloc(size);
result = (double*)malloc(size);
for (int i = 0; i < n; ++i) {
cin >> a[i];
}
Error(hipMalloc(&gpu_a, size));
Error(hipMalloc(&gpu_result, size));
Error(hipMemcpy(gpu_a, a, size, hipMemcpyHostToDevice));
sqr_items_vectors<<<256, 256>>>(gpu_a, gpu_result, n);
Error(hipMemcpy(result, gpu_result, size, hipMemcpyDeviceToHost));
for (int i = 0; i < n; ++i) {
cout << scientific << setprecision(10) << result[i] << " ";
}
cout << endl;
Error(hipFree(gpu_a));
Error(hipFree(gpu_result));
free(a);
free(result);
return 0;
} | .text
.file "lab1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z5Error10hipError_t # -- Begin function _Z5Error10hipError_t
.p2align 4, 0x90
.type _Z5Error10hipError_t,@function
_Z5Error10hipError_t: # @_Z5Error10hipError_t
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB0_2
# %bb.1:
retq
.LBB0_2:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edi, %ebx
movl $_ZSt4cout, %edi
movl $.L.str, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
xorl %edi, %edi
callq exit
.Lfunc_end0:
.size _Z5Error10hipError_t, .Lfunc_end0-_Z5Error10hipError_t
.cfi_endproc
# -- End function
.globl _Z32__device_stub__sqr_items_vectorsPdS_i # -- Begin function _Z32__device_stub__sqr_items_vectorsPdS_i
.p2align 4, 0x90
.type _Z32__device_stub__sqr_items_vectorsPdS_i,@function
_Z32__device_stub__sqr_items_vectorsPdS_i: # @_Z32__device_stub__sqr_items_vectorsPdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17sqr_items_vectorsPdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z32__device_stub__sqr_items_vectorsPdS_i, .Lfunc_end1-_Z32__device_stub__sqr_items_vectorsPdS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movl 4(%rsp), %r12d
leal (,%r12,8), %eax
movslq %eax, %r15
movq %r15, %rdi
callq malloc
movq %rax, %rbx
movq %r15, %rdi
callq malloc
movq %rax, %r14
testl %r12d, %r12d
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
xorl %r13d, %r13d
movq %rbx, %r12
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $_ZSt3cin, %edi
movq %r12, %rsi
callq _ZNSi10_M_extractIdEERSiRT_
incq %r13
movslq 4(%rsp), %rax
addq $8, %r12
cmpq %rax, %r13
jl .LBB2_2
.LBB2_3: # %._crit_edge
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_18
# %bb.4: # %_Z5Error10hipError_t.exit
leaq 8(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_18
# %bb.5: # %_Z5Error10hipError_t.exit22
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_18
# %bb.6: # %_Z5Error10hipError_t.exit24
movabsq $4294967552, %rdi # imm = 0x100000100
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl 4(%rsp), %edx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %edx, 28(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17sqr_items_vectorsPdS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_18
# %bb.9: # %_Z5Error10hipError_t.exit26.preheader
cmpl $0, 4(%rsp)
jle .LBB2_12
# %bb.10: # %_Z5Error10hipError_t.exit26.preheader45
xorl %r15d, %r15d
movl $-261, %ebp # imm = 0xFEFB
.p2align 4, 0x90
.LBB2_11: # %_Z5Error10hipError_t.exit26
# =>This Inner Loop Header: Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rcx
movl _ZSt4cout+24(%rcx), %edx
andl %ebp, %edx
orl $256, %edx # imm = 0x100
movl %edx, _ZSt4cout+24(%rcx)
movq -24(%rax), %rax
movq $10, _ZSt4cout+8(%rax)
movsd (%r14,%r15,8), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r15
movslq 4(%rsp), %rax
cmpq %rax, %r15
jl .LBB2_11
.LBB2_12: # %_Z5Error10hipError_t.exit26._crit_edge
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB2_19
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB2_15
# %bb.14:
movzbl 67(%r15), %eax
jmp .LBB2_16
.LBB2_15:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_18
# %bb.17: # %_Z5Error10hipError_t.exit28
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_18
# %bb.20: # %_Z5Error10hipError_t.exit30
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_18:
.cfi_def_cfa_offset 176
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
xorl %edi, %edi
callq exit
.LBB2_19:
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17sqr_items_vectorsPdS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "ERROR:"
.size .L.str, 7
.type _Z17sqr_items_vectorsPdS_i,@object # @_Z17sqr_items_vectorsPdS_i
.section .rodata,"a",@progbits
.globl _Z17sqr_items_vectorsPdS_i
.p2align 3, 0x0
_Z17sqr_items_vectorsPdS_i:
.quad _Z32__device_stub__sqr_items_vectorsPdS_i
.size _Z17sqr_items_vectorsPdS_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz " "
.size .L.str.1, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z17sqr_items_vectorsPdS_i"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__sqr_items_vectorsPdS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _Z17sqr_items_vectorsPdS_i
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17sqr_items_vectorsPdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0207 */
/*0090*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x000fe200078e0207 */
/*00b0*/ MOV R9, c[0x0][0x0] ; /* 0x0000000000097a02 */
/* 0x000fca0000000f00 */
/*00c0*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fca00078e0200 */
/*00d0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06270 */
/*00e0*/ DMUL R4, R2, R2 ; /* 0x0000000202047228 */
/* 0x004e0e0000000000 */
/*00f0*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x0011ea000c101b04 */
/*0100*/ @!P0 BRA 0x70 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17sqr_items_vectorsPdS_i
.globl _Z17sqr_items_vectorsPdS_i
.p2align 8
.type _Z17sqr_items_vectorsPdS_i,@function
_Z17sqr_items_vectorsPdS_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s2, s9
s_mov_b32 s2, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s8, v1
v_add_co_u32 v2, s0, s6, v2
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e64 v3, s0, s7, v3, s0
s_or_b32 s2, vcc_lo, s2
s_waitcnt vmcnt(0)
v_mul_f64 v[4:5], v[4:5], v[4:5]
global_store_b64 v[2:3], v[4:5], off
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17sqr_items_vectorsPdS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17sqr_items_vectorsPdS_i, .Lfunc_end0-_Z17sqr_items_vectorsPdS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17sqr_items_vectorsPdS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17sqr_items_vectorsPdS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c6489_00000000-6_lab1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3953:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3953:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "ERROR:"
.text
.globl _Z5Error9cudaError
.type _Z5Error9cudaError, @function
_Z5Error9cudaError:
.LFB3949:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L13
ret
.L13:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edi, %ebx
movl $6, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rbx
testq %rax, %rax
je .L14
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbx, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L6:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L15
cmpb $0, 56(%rbx)
je .L8
movzbl 67(%rbx), %esi
.L9:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $0, %edi
call exit@PLT
.L14:
leaq _ZSt4cout(%rip), %rdi
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L6
.L15:
call _ZSt16__throw_bad_castv@PLT
.L8:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L9
.cfi_endproc
.LFE3949:
.size _Z5Error9cudaError, .-_Z5Error9cudaError
.globl _Z40__device_stub__Z17sqr_items_vectorsPdS_iPdS_i
.type _Z40__device_stub__Z17sqr_items_vectorsPdS_iPdS_i, @function
_Z40__device_stub__Z17sqr_items_vectorsPdS_iPdS_i:
.LFB3975:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17sqr_items_vectorsPdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3975:
.size _Z40__device_stub__Z17sqr_items_vectorsPdS_iPdS_i, .-_Z40__device_stub__Z17sqr_items_vectorsPdS_iPdS_i
.globl _Z17sqr_items_vectorsPdS_i
.type _Z17sqr_items_vectorsPdS_i, @function
_Z17sqr_items_vectorsPdS_i:
.LFB3976:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z17sqr_items_vectorsPdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3976:
.size _Z17sqr_items_vectorsPdS_i, .-_Z17sqr_items_vectorsPdS_i
.section .rodata.str1.1
.LC1:
.string " "
.text
.globl main
.type main, @function
main:
.LFB3950:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
movl 12(%rsp), %ebx
leal 0(,%rbx,8), %r13d
movslq %r13d, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %r14
movq %r13, %rdi
call malloc@PLT
movq %rax, %r12
testl %ebx, %ebx
jle .L25
movq %r14, %rbp
movl $0, %ebx
leaq _ZSt3cin(%rip), %r15
.L26:
movq %rbp, %rsi
movq %r15, %rdi
call _ZNSi10_M_extractIdEERSiRT_@PLT
addl $1, %ebx
addq $8, %rbp
cmpl %ebx, 12(%rsp)
jg .L26
.L25:
leaq 16(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call _Z5Error9cudaError
leaq 24(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call _Z5Error9cudaError
movl $1, %ecx
movq %r13, %rdx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z5Error9cudaError
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $256, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L27:
movl $2, %ecx
movq %r13, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z5Error9cudaError
cmpl $0, 12(%rsp)
jle .L28
movl $0, %ebp
leaq _ZSt4cout(%rip), %rbx
leaq .LC1(%rip), %r13
.L29:
movq (%rbx), %rdx
movq %rbx, %rcx
addq -24(%rdx), %rcx
movl 24(%rcx), %eax
andl $-261, %eax
orb $1, %ah
movl %eax, 24(%rcx)
movq -24(%rdx), %rax
movq $10, 8(%rbx,%rax)
movsd (%r12,%rbp,8), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbp
cmpl %ebp, 12(%rsp)
jg .L29
.L28:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call _Z5Error9cudaError
movq 24(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call _Z5Error9cudaError
movq %r14, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movl 12(%rsp), %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z40__device_stub__Z17sqr_items_vectorsPdS_iPdS_i
jmp .L27
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3950:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z17sqr_items_vectorsPdS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3978:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z17sqr_items_vectorsPdS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3978:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "lab1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z5Error10hipError_t # -- Begin function _Z5Error10hipError_t
.p2align 4, 0x90
.type _Z5Error10hipError_t,@function
_Z5Error10hipError_t: # @_Z5Error10hipError_t
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB0_2
# %bb.1:
retq
.LBB0_2:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edi, %ebx
movl $_ZSt4cout, %edi
movl $.L.str, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
xorl %edi, %edi
callq exit
.Lfunc_end0:
.size _Z5Error10hipError_t, .Lfunc_end0-_Z5Error10hipError_t
.cfi_endproc
# -- End function
.globl _Z32__device_stub__sqr_items_vectorsPdS_i # -- Begin function _Z32__device_stub__sqr_items_vectorsPdS_i
.p2align 4, 0x90
.type _Z32__device_stub__sqr_items_vectorsPdS_i,@function
_Z32__device_stub__sqr_items_vectorsPdS_i: # @_Z32__device_stub__sqr_items_vectorsPdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17sqr_items_vectorsPdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z32__device_stub__sqr_items_vectorsPdS_i, .Lfunc_end1-_Z32__device_stub__sqr_items_vectorsPdS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movl 4(%rsp), %r12d
leal (,%r12,8), %eax
movslq %eax, %r15
movq %r15, %rdi
callq malloc
movq %rax, %rbx
movq %r15, %rdi
callq malloc
movq %rax, %r14
testl %r12d, %r12d
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
xorl %r13d, %r13d
movq %rbx, %r12
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $_ZSt3cin, %edi
movq %r12, %rsi
callq _ZNSi10_M_extractIdEERSiRT_
incq %r13
movslq 4(%rsp), %rax
addq $8, %r12
cmpq %rax, %r13
jl .LBB2_2
.LBB2_3: # %._crit_edge
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_18
# %bb.4: # %_Z5Error10hipError_t.exit
leaq 8(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_18
# %bb.5: # %_Z5Error10hipError_t.exit22
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_18
# %bb.6: # %_Z5Error10hipError_t.exit24
movabsq $4294967552, %rdi # imm = 0x100000100
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl 4(%rsp), %edx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %edx, 28(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17sqr_items_vectorsPdS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_18
# %bb.9: # %_Z5Error10hipError_t.exit26.preheader
cmpl $0, 4(%rsp)
jle .LBB2_12
# %bb.10: # %_Z5Error10hipError_t.exit26.preheader45
xorl %r15d, %r15d
movl $-261, %ebp # imm = 0xFEFB
.p2align 4, 0x90
.LBB2_11: # %_Z5Error10hipError_t.exit26
# =>This Inner Loop Header: Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rcx
movl _ZSt4cout+24(%rcx), %edx
andl %ebp, %edx
orl $256, %edx # imm = 0x100
movl %edx, _ZSt4cout+24(%rcx)
movq -24(%rax), %rax
movq $10, _ZSt4cout+8(%rax)
movsd (%r14,%r15,8), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r15
movslq 4(%rsp), %rax
cmpq %rax, %r15
jl .LBB2_11
.LBB2_12: # %_Z5Error10hipError_t.exit26._crit_edge
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB2_19
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB2_15
# %bb.14:
movzbl 67(%r15), %eax
jmp .LBB2_16
.LBB2_15:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_18
# %bb.17: # %_Z5Error10hipError_t.exit28
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_18
# %bb.20: # %_Z5Error10hipError_t.exit30
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_18:
.cfi_def_cfa_offset 176
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
xorl %edi, %edi
callq exit
.LBB2_19:
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17sqr_items_vectorsPdS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "ERROR:"
.size .L.str, 7
.type _Z17sqr_items_vectorsPdS_i,@object # @_Z17sqr_items_vectorsPdS_i
.section .rodata,"a",@progbits
.globl _Z17sqr_items_vectorsPdS_i
.p2align 3, 0x0
_Z17sqr_items_vectorsPdS_i:
.quad _Z32__device_stub__sqr_items_vectorsPdS_i
.size _Z17sqr_items_vectorsPdS_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz " "
.size .L.str.1, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z17sqr_items_vectorsPdS_i"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__sqr_items_vectorsPdS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _Z17sqr_items_vectorsPdS_i
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define MAX_BLOCKS 65535
#define MAX_THREADS 512
#include <iostream>
using namespace std;
/*
__global__ void harmonic_sum_kernel(float *d_idata,int gulp_index, int size, int stretch_factor)
{
//float* d_idata_float = (float*)d_idata;
int Index = blockIdx.x * blockDim.x + threadIdx.x;
if(Index<size/stretch_factor)
{
for(int i = 0;i<stretch_factor;i++)
{
d_idata[gulp_index+stretch_factor*Index+i] =
d_idata[gulp_index+stretch_factor*Index+i]
+d_idata[gulp_index+Index];
}
}
return;
}
__global__ void harmonic_sum_kernel_16(float *d_idata, float *d_odata,int gulp_index, int size)
{
//float* d_idata_float = (float*)d_idata;
int Index = blockIdx.x * blockDim.x + threadIdx.x;
if(Index<size)
{
d_odata[gulp_index+Index] =
d_idata[1*(gulp_index+Index)/2]
+d_idata[gulp_index+Index]
+d_idata[1*(gulp_index+Index)/4]
+d_idata[3*(gulp_index+Index)/4]
+d_idata[1*(gulp_index+Index)/8]
+d_idata[3*(gulp_index+Index)/8]
+d_idata[5*(gulp_index+Index)/8]
+d_idata[7*(gulp_index+Index)/8]
+d_idata[(gulp_index+Index)/16]
+d_idata[3*(gulp_index+Index)/16]
+d_idata[5*(gulp_index+Index)/16]
+d_idata[7*(gulp_index+Index)/16]
+d_idata[9*(gulp_index+Index)/16]
+d_idata[11*(gulp_index+Index)/16]
+d_idata[13*(gulp_index+Index)/16]
+d_idata[15*(gulp_index+Index)/16];
}
return;
}
__global__ void harmonic_sum_kernel_8(float *d_idata, float *d_odata,int gulp_index, int size)
{
//float* d_idata_float = (float*)d_idata;
int Index = blockIdx.x * blockDim.x + threadIdx.x;
if(Index<size)
{
d_odata[gulp_index+Index] = d_idata[(gulp_index+Index)/8]
+d_idata[2*(gulp_index+Index)/8]
+d_idata[3*(gulp_index+Index)/8]
+d_idata[4*(gulp_index+Index)/8]
+d_idata[5*(gulp_index+Index)/8]
+d_idata[6*(gulp_index+Index)/8]
+d_idata[7*(gulp_index+Index)/8]
+d_idata[gulp_index+Index];
}
return;
}
__global__ void harmonic_sum_kernel_4(float *d_idata, float *d_odata,int gulp_index, int size)
{
//float* d_idata_float = (float*)d_idata;
int Index = blockIdx.x * blockDim.x + threadIdx.x;
if(Index<size)
{
d_odata[gulp_index+Index] = d_idata[(gulp_index+Index)/4]
+d_idata[2*(gulp_index+Index)/4]
+d_idata[3*(gulp_index+Index)/4]
+d_idata[gulp_index+Index];
}
return;
}
__global__ void harmonic_sum_kernel_2(float *d_idata, float *d_odata,int gulp_index, int size)
{
//float* d_idata_float = (float*)d_idata;
int Index = blockIdx.x * blockDim.x + threadIdx.x;
if(Index<size)
{
d_odata[gulp_index+Index] = d_idata[(gulp_index+Index)/2]
+d_idata[gulp_index+Index];
}
return;
}
void call_harmonic_sum_kernel_generic(float *d_idata, float *d_odata, int gulp_index, int size, int harmonic)
{
harmonic_sum_kernel_generic(d_idata, d_odata, gulp_index, size, harmonic);
}
*/
__global__ void harmonic_sum_kernel_generic(float *d_idata, float *d_odata,int gulp_index, int size,int harmonic)
{
//float* d_idata_float = (float*)d_idata;
int Index = blockIdx.x * blockDim.x + threadIdx.x;
if(Index<size)
{
d_odata[gulp_index+Index] = d_idata[gulp_index+Index];
for(int i = 1; i < harmonic; i++)
{
d_odata[gulp_index+Index] += d_idata[(i*(gulp_index+Index))/harmonic];
}
// NOTE ERROR HERE
d_odata[gulp_index+Index] = d_odata[gulp_index+Index]/sqrt((float)harmonic); // can use *rsqrt to optimise further
}
return;
}
void GPU_harmonic_sum(float* d_input_array, float* d_output_array, int original_size, int harmonic)
{
int gulps;
int gulp_counter;
int gulp_index = 0;
int gulp_size;
gulps = original_size/(MAX_BLOCKS*MAX_THREADS)+1;
for(gulp_counter = 0; gulp_counter<gulps; gulp_counter++)
{
if(gulp_counter<gulps-1)
{
gulp_size = MAX_BLOCKS*MAX_THREADS;
}
else
{
gulp_size = original_size - gulp_counter*MAX_BLOCKS*MAX_THREADS;
}
harmonic_sum_kernel_generic<<<MAX_BLOCKS,MAX_THREADS>>>(d_input_array,d_output_array,gulp_index,gulp_size,harmonic);
gulp_index = gulp_index + MAX_BLOCKS*MAX_THREADS;
}
return;
} | .file "tmpxft_00106d69_00000000-6_harmonic_sum.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z52__device_stub__Z27harmonic_sum_kernel_genericPfS_iiiPfS_iii
.type _Z52__device_stub__Z27harmonic_sum_kernel_genericPfS_iiiPfS_iii, @function
_Z52__device_stub__Z27harmonic_sum_kernel_genericPfS_iiiPfS_iii:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z27harmonic_sum_kernel_genericPfS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z52__device_stub__Z27harmonic_sum_kernel_genericPfS_iiiPfS_iii, .-_Z52__device_stub__Z27harmonic_sum_kernel_genericPfS_iiiPfS_iii
.globl _Z27harmonic_sum_kernel_genericPfS_iii
.type _Z27harmonic_sum_kernel_genericPfS_iii, @function
_Z27harmonic_sum_kernel_genericPfS_iii:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z27harmonic_sum_kernel_genericPfS_iiiPfS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z27harmonic_sum_kernel_genericPfS_iii, .-_Z27harmonic_sum_kernel_genericPfS_iii
.globl _Z16GPU_harmonic_sumPfS_ii
.type _Z16GPU_harmonic_sumPfS_ii, @function
_Z16GPU_harmonic_sumPfS_ii:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movslq %edx, %r12
imulq $-2147450879, %r12, %r12
shrq $32, %r12
addl %edx, %r12d
sarl $24, %r12d
movl %edx, %eax
sarl $31, %eax
subl %eax, %r12d
cmpl $-33553919, %edx
jl .L11
movl %edx, %ebp
movl %ecx, %r15d
movl $0, %ebx
movl $33553920, %r14d
jmp .L15
.L14:
addl $1, %ebx
subl $33553920, %ebp
cmpl %ebx, %r12d
jl .L11
.L15:
cmpl %ebx, %r12d
movl %r14d, %r13d
cmovle %ebp, %r13d
movl $512, 36(%rsp)
movl $1, 40(%rsp)
movl $65535, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L14
imull $33553920, %ebx, %edx
movl %r15d, %r8d
movl %r13d, %ecx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z52__device_stub__Z27harmonic_sum_kernel_genericPfS_iiiPfS_iii
jmp .L14
.L11:
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size _Z16GPU_harmonic_sumPfS_ii, .-_Z16GPU_harmonic_sumPfS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z27harmonic_sum_kernel_genericPfS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z27harmonic_sum_kernel_genericPfS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define MAX_BLOCKS 65535
#define MAX_THREADS 512
#include <iostream>
using namespace std;
/*
__global__ void harmonic_sum_kernel(float *d_idata,int gulp_index, int size, int stretch_factor)
{
//float* d_idata_float = (float*)d_idata;
int Index = blockIdx.x * blockDim.x + threadIdx.x;
if(Index<size/stretch_factor)
{
for(int i = 0;i<stretch_factor;i++)
{
d_idata[gulp_index+stretch_factor*Index+i] =
d_idata[gulp_index+stretch_factor*Index+i]
+d_idata[gulp_index+Index];
}
}
return;
}
__global__ void harmonic_sum_kernel_16(float *d_idata, float *d_odata,int gulp_index, int size)
{
//float* d_idata_float = (float*)d_idata;
int Index = blockIdx.x * blockDim.x + threadIdx.x;
if(Index<size)
{
d_odata[gulp_index+Index] =
d_idata[1*(gulp_index+Index)/2]
+d_idata[gulp_index+Index]
+d_idata[1*(gulp_index+Index)/4]
+d_idata[3*(gulp_index+Index)/4]
+d_idata[1*(gulp_index+Index)/8]
+d_idata[3*(gulp_index+Index)/8]
+d_idata[5*(gulp_index+Index)/8]
+d_idata[7*(gulp_index+Index)/8]
+d_idata[(gulp_index+Index)/16]
+d_idata[3*(gulp_index+Index)/16]
+d_idata[5*(gulp_index+Index)/16]
+d_idata[7*(gulp_index+Index)/16]
+d_idata[9*(gulp_index+Index)/16]
+d_idata[11*(gulp_index+Index)/16]
+d_idata[13*(gulp_index+Index)/16]
+d_idata[15*(gulp_index+Index)/16];
}
return;
}
__global__ void harmonic_sum_kernel_8(float *d_idata, float *d_odata,int gulp_index, int size)
{
//float* d_idata_float = (float*)d_idata;
int Index = blockIdx.x * blockDim.x + threadIdx.x;
if(Index<size)
{
d_odata[gulp_index+Index] = d_idata[(gulp_index+Index)/8]
+d_idata[2*(gulp_index+Index)/8]
+d_idata[3*(gulp_index+Index)/8]
+d_idata[4*(gulp_index+Index)/8]
+d_idata[5*(gulp_index+Index)/8]
+d_idata[6*(gulp_index+Index)/8]
+d_idata[7*(gulp_index+Index)/8]
+d_idata[gulp_index+Index];
}
return;
}
__global__ void harmonic_sum_kernel_4(float *d_idata, float *d_odata,int gulp_index, int size)
{
//float* d_idata_float = (float*)d_idata;
int Index = blockIdx.x * blockDim.x + threadIdx.x;
if(Index<size)
{
d_odata[gulp_index+Index] = d_idata[(gulp_index+Index)/4]
+d_idata[2*(gulp_index+Index)/4]
+d_idata[3*(gulp_index+Index)/4]
+d_idata[gulp_index+Index];
}
return;
}
__global__ void harmonic_sum_kernel_2(float *d_idata, float *d_odata,int gulp_index, int size)
{
//float* d_idata_float = (float*)d_idata;
int Index = blockIdx.x * blockDim.x + threadIdx.x;
if(Index<size)
{
d_odata[gulp_index+Index] = d_idata[(gulp_index+Index)/2]
+d_idata[gulp_index+Index];
}
return;
}
void call_harmonic_sum_kernel_generic(float *d_idata, float *d_odata, int gulp_index, int size, int harmonic)
{
harmonic_sum_kernel_generic(d_idata, d_odata, gulp_index, size, harmonic);
}
*/
__global__ void harmonic_sum_kernel_generic(float *d_idata, float *d_odata,int gulp_index, int size,int harmonic)
{
//float* d_idata_float = (float*)d_idata;
int Index = blockIdx.x * blockDim.x + threadIdx.x;
if(Index<size)
{
d_odata[gulp_index+Index] = d_idata[gulp_index+Index];
for(int i = 1; i < harmonic; i++)
{
d_odata[gulp_index+Index] += d_idata[(i*(gulp_index+Index))/harmonic];
}
// NOTE ERROR HERE
d_odata[gulp_index+Index] = d_odata[gulp_index+Index]/sqrt((float)harmonic); // can use *rsqrt to optimise further
}
return;
}
void GPU_harmonic_sum(float* d_input_array, float* d_output_array, int original_size, int harmonic)
{
int gulps;
int gulp_counter;
int gulp_index = 0;
int gulp_size;
gulps = original_size/(MAX_BLOCKS*MAX_THREADS)+1;
for(gulp_counter = 0; gulp_counter<gulps; gulp_counter++)
{
if(gulp_counter<gulps-1)
{
gulp_size = MAX_BLOCKS*MAX_THREADS;
}
else
{
gulp_size = original_size - gulp_counter*MAX_BLOCKS*MAX_THREADS;
}
harmonic_sum_kernel_generic<<<MAX_BLOCKS,MAX_THREADS>>>(d_input_array,d_output_array,gulp_index,gulp_size,harmonic);
gulp_index = gulp_index + MAX_BLOCKS*MAX_THREADS;
}
return;
} | #define MAX_BLOCKS 65535
#define MAX_THREADS 512
#include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
/*
__global__ void harmonic_sum_kernel(float *d_idata,int gulp_index, int size, int stretch_factor)
{
//float* d_idata_float = (float*)d_idata;
int Index = blockIdx.x * blockDim.x + threadIdx.x;
if(Index<size/stretch_factor)
{
for(int i = 0;i<stretch_factor;i++)
{
d_idata[gulp_index+stretch_factor*Index+i] =
d_idata[gulp_index+stretch_factor*Index+i]
+d_idata[gulp_index+Index];
}
}
return;
}
__global__ void harmonic_sum_kernel_16(float *d_idata, float *d_odata,int gulp_index, int size)
{
//float* d_idata_float = (float*)d_idata;
int Index = blockIdx.x * blockDim.x + threadIdx.x;
if(Index<size)
{
d_odata[gulp_index+Index] =
d_idata[1*(gulp_index+Index)/2]
+d_idata[gulp_index+Index]
+d_idata[1*(gulp_index+Index)/4]
+d_idata[3*(gulp_index+Index)/4]
+d_idata[1*(gulp_index+Index)/8]
+d_idata[3*(gulp_index+Index)/8]
+d_idata[5*(gulp_index+Index)/8]
+d_idata[7*(gulp_index+Index)/8]
+d_idata[(gulp_index+Index)/16]
+d_idata[3*(gulp_index+Index)/16]
+d_idata[5*(gulp_index+Index)/16]
+d_idata[7*(gulp_index+Index)/16]
+d_idata[9*(gulp_index+Index)/16]
+d_idata[11*(gulp_index+Index)/16]
+d_idata[13*(gulp_index+Index)/16]
+d_idata[15*(gulp_index+Index)/16];
}
return;
}
__global__ void harmonic_sum_kernel_8(float *d_idata, float *d_odata,int gulp_index, int size)
{
//float* d_idata_float = (float*)d_idata;
int Index = blockIdx.x * blockDim.x + threadIdx.x;
if(Index<size)
{
d_odata[gulp_index+Index] = d_idata[(gulp_index+Index)/8]
+d_idata[2*(gulp_index+Index)/8]
+d_idata[3*(gulp_index+Index)/8]
+d_idata[4*(gulp_index+Index)/8]
+d_idata[5*(gulp_index+Index)/8]
+d_idata[6*(gulp_index+Index)/8]
+d_idata[7*(gulp_index+Index)/8]
+d_idata[gulp_index+Index];
}
return;
}
__global__ void harmonic_sum_kernel_4(float *d_idata, float *d_odata,int gulp_index, int size)
{
//float* d_idata_float = (float*)d_idata;
int Index = blockIdx.x * blockDim.x + threadIdx.x;
if(Index<size)
{
d_odata[gulp_index+Index] = d_idata[(gulp_index+Index)/4]
+d_idata[2*(gulp_index+Index)/4]
+d_idata[3*(gulp_index+Index)/4]
+d_idata[gulp_index+Index];
}
return;
}
__global__ void harmonic_sum_kernel_2(float *d_idata, float *d_odata,int gulp_index, int size)
{
//float* d_idata_float = (float*)d_idata;
int Index = blockIdx.x * blockDim.x + threadIdx.x;
if(Index<size)
{
d_odata[gulp_index+Index] = d_idata[(gulp_index+Index)/2]
+d_idata[gulp_index+Index];
}
return;
}
void call_harmonic_sum_kernel_generic(float *d_idata, float *d_odata, int gulp_index, int size, int harmonic)
{
harmonic_sum_kernel_generic(d_idata, d_odata, gulp_index, size, harmonic);
}
*/
__global__ void harmonic_sum_kernel_generic(float *d_idata, float *d_odata,int gulp_index, int size,int harmonic)
{
//float* d_idata_float = (float*)d_idata;
int Index = blockIdx.x * blockDim.x + threadIdx.x;
if(Index<size)
{
d_odata[gulp_index+Index] = d_idata[gulp_index+Index];
for(int i = 1; i < harmonic; i++)
{
d_odata[gulp_index+Index] += d_idata[(i*(gulp_index+Index))/harmonic];
}
// NOTE ERROR HERE
d_odata[gulp_index+Index] = d_odata[gulp_index+Index]/sqrt((float)harmonic); // can use *rsqrt to optimise further
}
return;
}
void GPU_harmonic_sum(float* d_input_array, float* d_output_array, int original_size, int harmonic)
{
int gulps;
int gulp_counter;
int gulp_index = 0;
int gulp_size;
gulps = original_size/(MAX_BLOCKS*MAX_THREADS)+1;
for(gulp_counter = 0; gulp_counter<gulps; gulp_counter++)
{
if(gulp_counter<gulps-1)
{
gulp_size = MAX_BLOCKS*MAX_THREADS;
}
else
{
gulp_size = original_size - gulp_counter*MAX_BLOCKS*MAX_THREADS;
}
harmonic_sum_kernel_generic<<<MAX_BLOCKS,MAX_THREADS>>>(d_input_array,d_output_array,gulp_index,gulp_size,harmonic);
gulp_index = gulp_index + MAX_BLOCKS*MAX_THREADS;
}
return;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #define MAX_BLOCKS 65535
#define MAX_THREADS 512
#include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
/*
__global__ void harmonic_sum_kernel(float *d_idata,int gulp_index, int size, int stretch_factor)
{
//float* d_idata_float = (float*)d_idata;
int Index = blockIdx.x * blockDim.x + threadIdx.x;
if(Index<size/stretch_factor)
{
for(int i = 0;i<stretch_factor;i++)
{
d_idata[gulp_index+stretch_factor*Index+i] =
d_idata[gulp_index+stretch_factor*Index+i]
+d_idata[gulp_index+Index];
}
}
return;
}
__global__ void harmonic_sum_kernel_16(float *d_idata, float *d_odata,int gulp_index, int size)
{
//float* d_idata_float = (float*)d_idata;
int Index = blockIdx.x * blockDim.x + threadIdx.x;
if(Index<size)
{
d_odata[gulp_index+Index] =
d_idata[1*(gulp_index+Index)/2]
+d_idata[gulp_index+Index]
+d_idata[1*(gulp_index+Index)/4]
+d_idata[3*(gulp_index+Index)/4]
+d_idata[1*(gulp_index+Index)/8]
+d_idata[3*(gulp_index+Index)/8]
+d_idata[5*(gulp_index+Index)/8]
+d_idata[7*(gulp_index+Index)/8]
+d_idata[(gulp_index+Index)/16]
+d_idata[3*(gulp_index+Index)/16]
+d_idata[5*(gulp_index+Index)/16]
+d_idata[7*(gulp_index+Index)/16]
+d_idata[9*(gulp_index+Index)/16]
+d_idata[11*(gulp_index+Index)/16]
+d_idata[13*(gulp_index+Index)/16]
+d_idata[15*(gulp_index+Index)/16];
}
return;
}
__global__ void harmonic_sum_kernel_8(float *d_idata, float *d_odata,int gulp_index, int size)
{
//float* d_idata_float = (float*)d_idata;
int Index = blockIdx.x * blockDim.x + threadIdx.x;
if(Index<size)
{
d_odata[gulp_index+Index] = d_idata[(gulp_index+Index)/8]
+d_idata[2*(gulp_index+Index)/8]
+d_idata[3*(gulp_index+Index)/8]
+d_idata[4*(gulp_index+Index)/8]
+d_idata[5*(gulp_index+Index)/8]
+d_idata[6*(gulp_index+Index)/8]
+d_idata[7*(gulp_index+Index)/8]
+d_idata[gulp_index+Index];
}
return;
}
__global__ void harmonic_sum_kernel_4(float *d_idata, float *d_odata,int gulp_index, int size)
{
//float* d_idata_float = (float*)d_idata;
int Index = blockIdx.x * blockDim.x + threadIdx.x;
if(Index<size)
{
d_odata[gulp_index+Index] = d_idata[(gulp_index+Index)/4]
+d_idata[2*(gulp_index+Index)/4]
+d_idata[3*(gulp_index+Index)/4]
+d_idata[gulp_index+Index];
}
return;
}
__global__ void harmonic_sum_kernel_2(float *d_idata, float *d_odata,int gulp_index, int size)
{
//float* d_idata_float = (float*)d_idata;
int Index = blockIdx.x * blockDim.x + threadIdx.x;
if(Index<size)
{
d_odata[gulp_index+Index] = d_idata[(gulp_index+Index)/2]
+d_idata[gulp_index+Index];
}
return;
}
void call_harmonic_sum_kernel_generic(float *d_idata, float *d_odata, int gulp_index, int size, int harmonic)
{
harmonic_sum_kernel_generic(d_idata, d_odata, gulp_index, size, harmonic);
}
*/
__global__ void harmonic_sum_kernel_generic(float *d_idata, float *d_odata,int gulp_index, int size,int harmonic)
{
//float* d_idata_float = (float*)d_idata;
int Index = blockIdx.x * blockDim.x + threadIdx.x;
if(Index<size)
{
d_odata[gulp_index+Index] = d_idata[gulp_index+Index];
for(int i = 1; i < harmonic; i++)
{
d_odata[gulp_index+Index] += d_idata[(i*(gulp_index+Index))/harmonic];
}
// NOTE ERROR HERE
d_odata[gulp_index+Index] = d_odata[gulp_index+Index]/sqrt((float)harmonic); // can use *rsqrt to optimise further
}
return;
}
void GPU_harmonic_sum(float* d_input_array, float* d_output_array, int original_size, int harmonic)
{
int gulps;
int gulp_counter;
int gulp_index = 0;
int gulp_size;
gulps = original_size/(MAX_BLOCKS*MAX_THREADS)+1;
for(gulp_counter = 0; gulp_counter<gulps; gulp_counter++)
{
if(gulp_counter<gulps-1)
{
gulp_size = MAX_BLOCKS*MAX_THREADS;
}
else
{
gulp_size = original_size - gulp_counter*MAX_BLOCKS*MAX_THREADS;
}
harmonic_sum_kernel_generic<<<MAX_BLOCKS,MAX_THREADS>>>(d_input_array,d_output_array,gulp_index,gulp_size,harmonic);
gulp_index = gulp_index + MAX_BLOCKS*MAX_THREADS;
}
return;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z27harmonic_sum_kernel_genericPfS_iii
.globl _Z27harmonic_sum_kernel_genericPfS_iii
.p2align 8
.type _Z27harmonic_sum_kernel_genericPfS_iii,@function
_Z27harmonic_sum_kernel_genericPfS_iii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_5
s_clause 0x2
s_load_b32 s2, s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, s2, v1
s_cmp_lt_i32 s0, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v3, off
s_cbranch_scc1 .LBB0_4
global_load_b32 v3, v[0:1], off
s_ashr_i32 s1, s0, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s0, s1
s_xor_b32 s2, s2, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v4, s2
s_sub_i32 s3, 0, s2
v_rcp_iflag_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v4, v4
v_mul_lo_u32 v5, s3, v4
s_mov_b32 s3, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v5, v4, v5
v_dual_mov_b32 v5, v2 :: v_dual_add_nc_u32 v4, v4, v5
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s3, s3, 1
s_cmp_eq_u32 s0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v7, v5, v6
v_add_nc_u32_e32 v5, v5, v2
v_xor_b32_e32 v7, v7, v6
v_xor_b32_e32 v6, s1, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v8, v7, v4
v_mul_lo_u32 v9, v8, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v7, v7, v9
v_subrev_nc_u32_e32 v9, s2, v7
v_cmp_le_u32_e32 vcc_lo, s2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v7, v7, v9 :: v_dual_add_nc_u32 v10, 1, v8
v_cndmask_b32_e32 v8, v8, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s2, v7
v_add_nc_u32_e32 v9, 1, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v7, v8, v9, vcc_lo
v_xor_b32_e32 v7, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v6, v7, v6
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_u32 v6, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b32 v6, v[6:7], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v6, v3
global_store_b32 v[0:1], v3, off
s_cbranch_scc0 .LBB0_3
.LBB0_4:
s_set_inst_prefetch_distance 0x2
global_load_b32 v2, v[0:1], off
v_cvt_f32_i32_e32 v3, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v4, 0x4f800000, v3
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v3
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v5, -1, v4
v_add_nc_u32_e32 v6, 1, v4
v_fma_f32 v7, -v5, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v8, -v6, v4, v3
v_cmp_ge_f32_e64 s0, 0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v4, v4, v5, s0
v_cmp_lt_f32_e64 s0, 0, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v4, v4, v6, s0
v_mul_f32_e32 v5, 0x37800000, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v3, 0x260
v_cndmask_b32_e32 v3, v4, v3, vcc_lo
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v4, null, v3, v3, v2
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v2, v3, v2
v_mul_f32_e32 v7, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v7, v6
v_fmac_f32_e32 v7, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v7, v6
v_div_fmas_f32 v4, v4, v5, v7
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v2, v4, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z27harmonic_sum_kernel_genericPfS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z27harmonic_sum_kernel_genericPfS_iii, .Lfunc_end0-_Z27harmonic_sum_kernel_genericPfS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z27harmonic_sum_kernel_genericPfS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z27harmonic_sum_kernel_genericPfS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #define MAX_BLOCKS 65535
#define MAX_THREADS 512
#include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
/*
__global__ void harmonic_sum_kernel(float *d_idata,int gulp_index, int size, int stretch_factor)
{
//float* d_idata_float = (float*)d_idata;
int Index = blockIdx.x * blockDim.x + threadIdx.x;
if(Index<size/stretch_factor)
{
for(int i = 0;i<stretch_factor;i++)
{
d_idata[gulp_index+stretch_factor*Index+i] =
d_idata[gulp_index+stretch_factor*Index+i]
+d_idata[gulp_index+Index];
}
}
return;
}
__global__ void harmonic_sum_kernel_16(float *d_idata, float *d_odata,int gulp_index, int size)
{
//float* d_idata_float = (float*)d_idata;
int Index = blockIdx.x * blockDim.x + threadIdx.x;
if(Index<size)
{
d_odata[gulp_index+Index] =
d_idata[1*(gulp_index+Index)/2]
+d_idata[gulp_index+Index]
+d_idata[1*(gulp_index+Index)/4]
+d_idata[3*(gulp_index+Index)/4]
+d_idata[1*(gulp_index+Index)/8]
+d_idata[3*(gulp_index+Index)/8]
+d_idata[5*(gulp_index+Index)/8]
+d_idata[7*(gulp_index+Index)/8]
+d_idata[(gulp_index+Index)/16]
+d_idata[3*(gulp_index+Index)/16]
+d_idata[5*(gulp_index+Index)/16]
+d_idata[7*(gulp_index+Index)/16]
+d_idata[9*(gulp_index+Index)/16]
+d_idata[11*(gulp_index+Index)/16]
+d_idata[13*(gulp_index+Index)/16]
+d_idata[15*(gulp_index+Index)/16];
}
return;
}
__global__ void harmonic_sum_kernel_8(float *d_idata, float *d_odata,int gulp_index, int size)
{
//float* d_idata_float = (float*)d_idata;
int Index = blockIdx.x * blockDim.x + threadIdx.x;
if(Index<size)
{
d_odata[gulp_index+Index] = d_idata[(gulp_index+Index)/8]
+d_idata[2*(gulp_index+Index)/8]
+d_idata[3*(gulp_index+Index)/8]
+d_idata[4*(gulp_index+Index)/8]
+d_idata[5*(gulp_index+Index)/8]
+d_idata[6*(gulp_index+Index)/8]
+d_idata[7*(gulp_index+Index)/8]
+d_idata[gulp_index+Index];
}
return;
}
__global__ void harmonic_sum_kernel_4(float *d_idata, float *d_odata,int gulp_index, int size)
{
//float* d_idata_float = (float*)d_idata;
int Index = blockIdx.x * blockDim.x + threadIdx.x;
if(Index<size)
{
d_odata[gulp_index+Index] = d_idata[(gulp_index+Index)/4]
+d_idata[2*(gulp_index+Index)/4]
+d_idata[3*(gulp_index+Index)/4]
+d_idata[gulp_index+Index];
}
return;
}
__global__ void harmonic_sum_kernel_2(float *d_idata, float *d_odata,int gulp_index, int size)
{
//float* d_idata_float = (float*)d_idata;
int Index = blockIdx.x * blockDim.x + threadIdx.x;
if(Index<size)
{
d_odata[gulp_index+Index] = d_idata[(gulp_index+Index)/2]
+d_idata[gulp_index+Index];
}
return;
}
void call_harmonic_sum_kernel_generic(float *d_idata, float *d_odata, int gulp_index, int size, int harmonic)
{
harmonic_sum_kernel_generic(d_idata, d_odata, gulp_index, size, harmonic);
}
*/
__global__ void harmonic_sum_kernel_generic(float *d_idata, float *d_odata,int gulp_index, int size,int harmonic)
{
//float* d_idata_float = (float*)d_idata;
int Index = blockIdx.x * blockDim.x + threadIdx.x;
if(Index<size)
{
d_odata[gulp_index+Index] = d_idata[gulp_index+Index];
for(int i = 1; i < harmonic; i++)
{
d_odata[gulp_index+Index] += d_idata[(i*(gulp_index+Index))/harmonic];
}
// NOTE ERROR HERE
d_odata[gulp_index+Index] = d_odata[gulp_index+Index]/sqrt((float)harmonic); // can use *rsqrt to optimise further
}
return;
}
void GPU_harmonic_sum(float* d_input_array, float* d_output_array, int original_size, int harmonic)
{
int gulps;
int gulp_counter;
int gulp_index = 0;
int gulp_size;
gulps = original_size/(MAX_BLOCKS*MAX_THREADS)+1;
for(gulp_counter = 0; gulp_counter<gulps; gulp_counter++)
{
if(gulp_counter<gulps-1)
{
gulp_size = MAX_BLOCKS*MAX_THREADS;
}
else
{
gulp_size = original_size - gulp_counter*MAX_BLOCKS*MAX_THREADS;
}
harmonic_sum_kernel_generic<<<MAX_BLOCKS,MAX_THREADS>>>(d_input_array,d_output_array,gulp_index,gulp_size,harmonic);
gulp_index = gulp_index + MAX_BLOCKS*MAX_THREADS;
}
return;
} | .text
.file "harmonic_sum.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z42__device_stub__harmonic_sum_kernel_genericPfS_iii # -- Begin function _Z42__device_stub__harmonic_sum_kernel_genericPfS_iii
.p2align 4, 0x90
.type _Z42__device_stub__harmonic_sum_kernel_genericPfS_iii,@function
_Z42__device_stub__harmonic_sum_kernel_genericPfS_iii: # @_Z42__device_stub__harmonic_sum_kernel_genericPfS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z27harmonic_sum_kernel_genericPfS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z42__device_stub__harmonic_sum_kernel_genericPfS_iii, .Lfunc_end0-_Z42__device_stub__harmonic_sum_kernel_genericPfS_iii
.cfi_endproc
# -- End function
.globl _Z16GPU_harmonic_sumPfS_ii # -- Begin function _Z16GPU_harmonic_sumPfS_ii
.p2align 4, 0x90
.type _Z16GPU_harmonic_sumPfS_ii,@function
_Z16GPU_harmonic_sumPfS_ii: # @_Z16GPU_harmonic_sumPfS_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, (%rsp) # 4-byte Spill
movq %rsi, 24(%rsp) # 8-byte Spill
movq %rdi, 16(%rsp) # 8-byte Spill
cmpl $-33553919, %edx # imm = 0xFE000201
jge .LBB1_1
.LBB1_5: # %._crit_edge
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1: # %.lr.ph
.cfi_def_cfa_offset 192
movl %edx, %ebp
movslq %edx, %rax
imulq $-2147450879, %rax, %rbx # imm = 0x80008001
shrq $32, %rbx
addl %edx, %ebx
movl %ebx, %eax
shrl $31, %eax
sarl $24, %ebx
addl %eax, %ebx
movabsq $4294967808, %rax # imm = 0x100000200
leal 1(%rbx), %r14d
xorl %r15d, %r15d
leaq 65023(%rax), %r13
xorl %r12d, %r12d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_4: # in Loop: Header=BB1_2 Depth=1
addl $33553920, %r12d # imm = 0x1FFFE00
incl %r15d
addl $-33553920, %ebp # imm = 0xFE000200
cmpl %r15d, %r14d
je .LBB1_5
.LBB1_2: # =>This Inner Loop Header: Depth=1
movq %r13, %rdi
movl $1, %esi
movabsq $4294967808, %rdx # imm = 0x100000200
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3: # in Loop: Header=BB1_2 Depth=1
cmpl %ebx, %r15d
movl %ebp, %eax
movl $33553920, %ecx # imm = 0x1FFFE00
cmovll %ecx, %eax
movq 16(%rsp), %rcx # 8-byte Reload
movq %rcx, 88(%rsp)
movq 24(%rsp), %rcx # 8-byte Reload
movq %rcx, 80(%rsp)
movl %r12d, 12(%rsp)
movl %eax, 8(%rsp)
movl (%rsp), %eax # 4-byte Reload
movl %eax, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z27harmonic_sum_kernel_genericPfS_iii, %edi
leaq 96(%rsp), %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_4
.Lfunc_end1:
.size _Z16GPU_harmonic_sumPfS_ii, .Lfunc_end1-_Z16GPU_harmonic_sumPfS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27harmonic_sum_kernel_genericPfS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z27harmonic_sum_kernel_genericPfS_iii,@object # @_Z27harmonic_sum_kernel_genericPfS_iii
.section .rodata,"a",@progbits
.globl _Z27harmonic_sum_kernel_genericPfS_iii
.p2align 3, 0x0
_Z27harmonic_sum_kernel_genericPfS_iii:
.quad _Z42__device_stub__harmonic_sum_kernel_genericPfS_iii
.size _Z27harmonic_sum_kernel_genericPfS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z27harmonic_sum_kernel_genericPfS_iii"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__harmonic_sum_kernel_genericPfS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z27harmonic_sum_kernel_genericPfS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00106d69_00000000-6_harmonic_sum.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z52__device_stub__Z27harmonic_sum_kernel_genericPfS_iiiPfS_iii
.type _Z52__device_stub__Z27harmonic_sum_kernel_genericPfS_iiiPfS_iii, @function
_Z52__device_stub__Z27harmonic_sum_kernel_genericPfS_iiiPfS_iii:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z27harmonic_sum_kernel_genericPfS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z52__device_stub__Z27harmonic_sum_kernel_genericPfS_iiiPfS_iii, .-_Z52__device_stub__Z27harmonic_sum_kernel_genericPfS_iiiPfS_iii
.globl _Z27harmonic_sum_kernel_genericPfS_iii
.type _Z27harmonic_sum_kernel_genericPfS_iii, @function
_Z27harmonic_sum_kernel_genericPfS_iii:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z27harmonic_sum_kernel_genericPfS_iiiPfS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z27harmonic_sum_kernel_genericPfS_iii, .-_Z27harmonic_sum_kernel_genericPfS_iii
.globl _Z16GPU_harmonic_sumPfS_ii
.type _Z16GPU_harmonic_sumPfS_ii, @function
_Z16GPU_harmonic_sumPfS_ii:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movslq %edx, %r12
imulq $-2147450879, %r12, %r12
shrq $32, %r12
addl %edx, %r12d
sarl $24, %r12d
movl %edx, %eax
sarl $31, %eax
subl %eax, %r12d
cmpl $-33553919, %edx
jl .L11
movl %edx, %ebp
movl %ecx, %r15d
movl $0, %ebx
movl $33553920, %r14d
jmp .L15
.L14:
addl $1, %ebx
subl $33553920, %ebp
cmpl %ebx, %r12d
jl .L11
.L15:
cmpl %ebx, %r12d
movl %r14d, %r13d
cmovle %ebp, %r13d
movl $512, 36(%rsp)
movl $1, 40(%rsp)
movl $65535, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L14
imull $33553920, %ebx, %edx
movl %r15d, %r8d
movl %r13d, %ecx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z52__device_stub__Z27harmonic_sum_kernel_genericPfS_iiiPfS_iii
jmp .L14
.L11:
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size _Z16GPU_harmonic_sumPfS_ii, .-_Z16GPU_harmonic_sumPfS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z27harmonic_sum_kernel_genericPfS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z27harmonic_sum_kernel_genericPfS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "harmonic_sum.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z42__device_stub__harmonic_sum_kernel_genericPfS_iii # -- Begin function _Z42__device_stub__harmonic_sum_kernel_genericPfS_iii
.p2align 4, 0x90
.type _Z42__device_stub__harmonic_sum_kernel_genericPfS_iii,@function
_Z42__device_stub__harmonic_sum_kernel_genericPfS_iii: # @_Z42__device_stub__harmonic_sum_kernel_genericPfS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z27harmonic_sum_kernel_genericPfS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z42__device_stub__harmonic_sum_kernel_genericPfS_iii, .Lfunc_end0-_Z42__device_stub__harmonic_sum_kernel_genericPfS_iii
.cfi_endproc
# -- End function
.globl _Z16GPU_harmonic_sumPfS_ii # -- Begin function _Z16GPU_harmonic_sumPfS_ii
.p2align 4, 0x90
.type _Z16GPU_harmonic_sumPfS_ii,@function
_Z16GPU_harmonic_sumPfS_ii: # @_Z16GPU_harmonic_sumPfS_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, (%rsp) # 4-byte Spill
movq %rsi, 24(%rsp) # 8-byte Spill
movq %rdi, 16(%rsp) # 8-byte Spill
cmpl $-33553919, %edx # imm = 0xFE000201
jge .LBB1_1
.LBB1_5: # %._crit_edge
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1: # %.lr.ph
.cfi_def_cfa_offset 192
movl %edx, %ebp
movslq %edx, %rax
imulq $-2147450879, %rax, %rbx # imm = 0x80008001
shrq $32, %rbx
addl %edx, %ebx
movl %ebx, %eax
shrl $31, %eax
sarl $24, %ebx
addl %eax, %ebx
movabsq $4294967808, %rax # imm = 0x100000200
leal 1(%rbx), %r14d
xorl %r15d, %r15d
leaq 65023(%rax), %r13
xorl %r12d, %r12d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_4: # in Loop: Header=BB1_2 Depth=1
addl $33553920, %r12d # imm = 0x1FFFE00
incl %r15d
addl $-33553920, %ebp # imm = 0xFE000200
cmpl %r15d, %r14d
je .LBB1_5
.LBB1_2: # =>This Inner Loop Header: Depth=1
movq %r13, %rdi
movl $1, %esi
movabsq $4294967808, %rdx # imm = 0x100000200
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3: # in Loop: Header=BB1_2 Depth=1
cmpl %ebx, %r15d
movl %ebp, %eax
movl $33553920, %ecx # imm = 0x1FFFE00
cmovll %ecx, %eax
movq 16(%rsp), %rcx # 8-byte Reload
movq %rcx, 88(%rsp)
movq 24(%rsp), %rcx # 8-byte Reload
movq %rcx, 80(%rsp)
movl %r12d, 12(%rsp)
movl %eax, 8(%rsp)
movl (%rsp), %eax # 4-byte Reload
movl %eax, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z27harmonic_sum_kernel_genericPfS_iii, %edi
leaq 96(%rsp), %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_4
.Lfunc_end1:
.size _Z16GPU_harmonic_sumPfS_ii, .Lfunc_end1-_Z16GPU_harmonic_sumPfS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27harmonic_sum_kernel_genericPfS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z27harmonic_sum_kernel_genericPfS_iii,@object # @_Z27harmonic_sum_kernel_genericPfS_iii
.section .rodata,"a",@progbits
.globl _Z27harmonic_sum_kernel_genericPfS_iii
.p2align 3, 0x0
_Z27harmonic_sum_kernel_genericPfS_iii:
.quad _Z42__device_stub__harmonic_sum_kernel_genericPfS_iii
.size _Z27harmonic_sum_kernel_genericPfS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z27harmonic_sum_kernel_genericPfS_iii"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__harmonic_sum_kernel_genericPfS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z27harmonic_sum_kernel_genericPfS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void transpose_unroll4_row(int * mat, int * transpose, int nx, int ny)
{
int ix = blockIdx.x * blockDim.x * 4 + threadIdx.x;
int iy = blockIdx.y * blockDim.y + threadIdx.y;
int ti = iy * nx + ix;
int to = ix * ny + iy;
if (ix + 3 * blockDim.x < nx && iy < ny)
{
transpose[to] = mat[ti];
transpose[to + ny*blockDim.x] = mat[ti + blockDim.x];
transpose[to + ny * 2 * blockDim.x] = mat[ti + 2 * blockDim.x];
transpose[to + ny * 3 * blockDim.x] = mat[ti + 3 * blockDim.x];
}
} | code for sm_80
Function : _Z21transpose_unroll4_rowPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.Y ; /* 0x0000000000067919 */
/* 0x000e220000002600 */
/*0020*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e620000002500 */
/*0030*/ MOV R14, c[0x0][0x0] ; /* 0x00000000000e7a02 */
/* 0x000fe40000000f00 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e240000002200 */
/*0050*/ SHF.L.U32 R2, R14.reuse, 0x2, RZ ; /* 0x000000020e027819 */
/* 0x040fe400000006ff */
/*0060*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0070*/ LEA R0, R14, R14, 0x1 ; /* 0x0000000e0e007211 */
/* 0x000fe200078e08ff */
/*0080*/ IMAD R6, R6, c[0x0][0x4], R5 ; /* 0x0000010006067a24 */
/* 0x001fc400078e0205 */
/*0090*/ IMAD R3, R2, UR4, R3 ; /* 0x0000000402037c24 */
/* 0x002fc6000f8e0203 */
/*00a0*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x174], PT ; /* 0x00005d0006007a0c */
/* 0x000fe40003f06270 */
/*00b0*/ IADD3 R2, R3, R0, RZ ; /* 0x0000000003027210 */
/* 0x000fc80007ffe0ff */
/*00c0*/ ISETP.GE.U32.OR P0, PT, R2, c[0x0][0x170], P0 ; /* 0x00005c0002007a0c */
/* 0x000fda0000706470 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*00f0*/ IMAD R7, R6, c[0x0][0x170], R3 ; /* 0x00005c0006077a24 */
/* 0x000fe200078e0203 */
/*0100*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0110*/ IMAD.WIDE R4, R7, R2, c[0x0][0x160] ; /* 0x0000580007047625 */
/* 0x000fcc00078e0202 */
/*0120*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0130*/ IADD3 R11, R7, c[0x0][0x0], RZ ; /* 0x00000000070b7a10 */
/* 0x000fe20007ffe0ff */
/*0140*/ IMAD R3, R3, c[0x0][0x174], R6 ; /* 0x00005d0003037a24 */
/* 0x000fc800078e0206 */
/*0150*/ IMAD.WIDE R6, R3, R2, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0202 */
/*0160*/ IMAD.WIDE.U32 R8, R11.reuse, R2, c[0x0][0x160] ; /* 0x000058000b087625 */
/* 0x040fe200078e0002 */
/*0170*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x0041ea000c101904 */
/*0180*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0190*/ IMAD R13, R14, c[0x0][0x174], R3 ; /* 0x00005d000e0d7a24 */
/* 0x000fe200078e0203 */
/*01a0*/ IADD3 R15, R11, c[0x0][0x0], RZ ; /* 0x000000000b0f7a10 */
/* 0x000fc60007ffe0ff */
/*01b0*/ IMAD.WIDE.U32 R10, R13, R2, c[0x0][0x168] ; /* 0x00005a000d0a7625 */
/* 0x000fc800078e0002 */
/*01c0*/ IMAD.WIDE.U32 R12, R15.reuse, R2, c[0x0][0x160] ; /* 0x000058000f0c7625 */
/* 0x040fe200078e0002 */
/*01d0*/ SHF.L.U32 R4, R14, 0x1, RZ ; /* 0x000000010e047819 */
/* 0x000fe200000006ff */
/*01e0*/ STG.E [R10.64], R9 ; /* 0x000000090a007986 */
/* 0x004fe8000c101904 */
/*01f0*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000ea2000c1e1900 */
/*0200*/ IADD3 R15, R15, c[0x0][0x0], RZ ; /* 0x000000000f0f7a10 */
/* 0x000fe20007ffe0ff */
/*0210*/ IMAD R17, R4, c[0x0][0x174], R3 ; /* 0x00005d0004117a24 */
/* 0x000fc800078e0203 */
/*0220*/ IMAD.WIDE.U32 R4, R17, R2, c[0x0][0x168] ; /* 0x00005a0011047625 */
/* 0x001fc800078e0002 */
/*0230*/ IMAD.WIDE.U32 R6, R15, R2, c[0x0][0x160] ; /* 0x000058000f067625 */
/* 0x000fe200078e0002 */
/*0240*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x004fea000c101904 */
/*0250*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea2000c1e1900 */
/*0260*/ IMAD R3, R0, c[0x0][0x174], R3 ; /* 0x00005d0000037a24 */
/* 0x000fc800078e0203 */
/*0270*/ IMAD.WIDE.U32 R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fca00078e0002 */
/*0280*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x004fe2000c101904 */
/*0290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02a0*/ BRA 0x2a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void transpose_unroll4_row(int * mat, int * transpose, int nx, int ny)
{
int ix = blockIdx.x * blockDim.x * 4 + threadIdx.x;
int iy = blockIdx.y * blockDim.y + threadIdx.y;
int ti = iy * nx + ix;
int to = ix * ny + iy;
if (ix + 3 * blockDim.x < nx && iy < ny)
{
transpose[to] = mat[ti];
transpose[to + ny*blockDim.x] = mat[ti + blockDim.x];
transpose[to + ny * 2 * blockDim.x] = mat[ti + 2 * blockDim.x];
transpose[to + ny * 3 * blockDim.x] = mat[ti + 3 * blockDim.x];
}
} | .file "tmpxft_00123f0f_00000000-6_transpose_unroll4_row.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z21transpose_unroll4_rowPiS_iiPiS_ii
.type _Z45__device_stub__Z21transpose_unroll4_rowPiS_iiPiS_ii, @function
_Z45__device_stub__Z21transpose_unroll4_rowPiS_iiPiS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21transpose_unroll4_rowPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z21transpose_unroll4_rowPiS_iiPiS_ii, .-_Z45__device_stub__Z21transpose_unroll4_rowPiS_iiPiS_ii
.globl _Z21transpose_unroll4_rowPiS_ii
.type _Z21transpose_unroll4_rowPiS_ii, @function
_Z21transpose_unroll4_rowPiS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z21transpose_unroll4_rowPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z21transpose_unroll4_rowPiS_ii, .-_Z21transpose_unroll4_rowPiS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z21transpose_unroll4_rowPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21transpose_unroll4_rowPiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void transpose_unroll4_row(int * mat, int * transpose, int nx, int ny)
{
int ix = blockIdx.x * blockDim.x * 4 + threadIdx.x;
int iy = blockIdx.y * blockDim.y + threadIdx.y;
int ti = iy * nx + ix;
int to = ix * ny + iy;
if (ix + 3 * blockDim.x < nx && iy < ny)
{
transpose[to] = mat[ti];
transpose[to + ny*blockDim.x] = mat[ti + blockDim.x];
transpose[to + ny * 2 * blockDim.x] = mat[ti + 2 * blockDim.x];
transpose[to + ny * 3 * blockDim.x] = mat[ti + 3 * blockDim.x];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void transpose_unroll4_row(int * mat, int * transpose, int nx, int ny)
{
int ix = blockIdx.x * blockDim.x * 4 + threadIdx.x;
int iy = blockIdx.y * blockDim.y + threadIdx.y;
int ti = iy * nx + ix;
int to = ix * ny + iy;
if (ix + 3 * blockDim.x < nx && iy < ny)
{
transpose[to] = mat[ti];
transpose[to + ny*blockDim.x] = mat[ti + blockDim.x];
transpose[to + ny * 2 * blockDim.x] = mat[ti + 2 * blockDim.x];
transpose[to + ny * 3 * blockDim.x] = mat[ti + 3 * blockDim.x];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void transpose_unroll4_row(int * mat, int * transpose, int nx, int ny)
{
int ix = blockIdx.x * blockDim.x * 4 + threadIdx.x;
int iy = blockIdx.y * blockDim.y + threadIdx.y;
int ti = iy * nx + ix;
int to = ix * ny + iy;
if (ix + 3 * blockDim.x < nx && iy < ny)
{
transpose[to] = mat[ti];
transpose[to + ny*blockDim.x] = mat[ti + blockDim.x];
transpose[to + ny * 2 * blockDim.x] = mat[ti + 2 * blockDim.x];
transpose[to + ny * 3 * blockDim.x] = mat[ti + 3 * blockDim.x];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21transpose_unroll4_rowPiS_ii
.globl _Z21transpose_unroll4_rowPiS_ii
.p2align 8
.type _Z21transpose_unroll4_rowPiS_ii,@function
_Z21transpose_unroll4_rowPiS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_mul_i32 s14, s14, s7
s_mul_i32 s6, s7, 3
v_lshl_add_u32 v0, s14, 2, v1
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, s6, v0
v_cmp_gt_i32_e64 s2, s5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_u32_e32 vcc_lo, s4, v2
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_mul_i32 s4, s7, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_load_b32 v8, v[3:4], off
v_mad_u64_u32 v[3:4], null, v0, s5, v[1:2]
v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, s7, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[6:7], 2, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
v_add_nc_u32_e32 v0, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[3:4]
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v8, off
global_load_b32 v8, v[6:7], off
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_lshl_add_u32 v0, s7, 1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[6:7], 2, v[0:1]
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_lshl_add_u32 v0, s4, 1, v3
v_add_co_u32 v6, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v8, off
global_load_b32 v8, v[6:7], off
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_add_nc_u32_e32 v0, s6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[6:7], 2, v[0:1]
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v6
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v8, off
global_load_b32 v2, v[6:7], off
v_mad_u64_u32 v[4:5], null, s4, 3, v[3:4]
v_mov_b32_e32 v5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[4:5]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21transpose_unroll4_rowPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21transpose_unroll4_rowPiS_ii, .Lfunc_end0-_Z21transpose_unroll4_rowPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21transpose_unroll4_rowPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21transpose_unroll4_rowPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void transpose_unroll4_row(int * mat, int * transpose, int nx, int ny)
{
int ix = blockIdx.x * blockDim.x * 4 + threadIdx.x;
int iy = blockIdx.y * blockDim.y + threadIdx.y;
int ti = iy * nx + ix;
int to = ix * ny + iy;
if (ix + 3 * blockDim.x < nx && iy < ny)
{
transpose[to] = mat[ti];
transpose[to + ny*blockDim.x] = mat[ti + blockDim.x];
transpose[to + ny * 2 * blockDim.x] = mat[ti + 2 * blockDim.x];
transpose[to + ny * 3 * blockDim.x] = mat[ti + 3 * blockDim.x];
}
} | .text
.file "transpose_unroll4_row.hip"
.globl _Z36__device_stub__transpose_unroll4_rowPiS_ii # -- Begin function _Z36__device_stub__transpose_unroll4_rowPiS_ii
.p2align 4, 0x90
.type _Z36__device_stub__transpose_unroll4_rowPiS_ii,@function
_Z36__device_stub__transpose_unroll4_rowPiS_ii: # @_Z36__device_stub__transpose_unroll4_rowPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21transpose_unroll4_rowPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z36__device_stub__transpose_unroll4_rowPiS_ii, .Lfunc_end0-_Z36__device_stub__transpose_unroll4_rowPiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21transpose_unroll4_rowPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21transpose_unroll4_rowPiS_ii,@object # @_Z21transpose_unroll4_rowPiS_ii
.section .rodata,"a",@progbits
.globl _Z21transpose_unroll4_rowPiS_ii
.p2align 3, 0x0
_Z21transpose_unroll4_rowPiS_ii:
.quad _Z36__device_stub__transpose_unroll4_rowPiS_ii
.size _Z21transpose_unroll4_rowPiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21transpose_unroll4_rowPiS_ii"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__transpose_unroll4_rowPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21transpose_unroll4_rowPiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z21transpose_unroll4_rowPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.Y ; /* 0x0000000000067919 */
/* 0x000e220000002600 */
/*0020*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e620000002500 */
/*0030*/ MOV R14, c[0x0][0x0] ; /* 0x00000000000e7a02 */
/* 0x000fe40000000f00 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e240000002200 */
/*0050*/ SHF.L.U32 R2, R14.reuse, 0x2, RZ ; /* 0x000000020e027819 */
/* 0x040fe400000006ff */
/*0060*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0070*/ LEA R0, R14, R14, 0x1 ; /* 0x0000000e0e007211 */
/* 0x000fe200078e08ff */
/*0080*/ IMAD R6, R6, c[0x0][0x4], R5 ; /* 0x0000010006067a24 */
/* 0x001fc400078e0205 */
/*0090*/ IMAD R3, R2, UR4, R3 ; /* 0x0000000402037c24 */
/* 0x002fc6000f8e0203 */
/*00a0*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x174], PT ; /* 0x00005d0006007a0c */
/* 0x000fe40003f06270 */
/*00b0*/ IADD3 R2, R3, R0, RZ ; /* 0x0000000003027210 */
/* 0x000fc80007ffe0ff */
/*00c0*/ ISETP.GE.U32.OR P0, PT, R2, c[0x0][0x170], P0 ; /* 0x00005c0002007a0c */
/* 0x000fda0000706470 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*00f0*/ IMAD R7, R6, c[0x0][0x170], R3 ; /* 0x00005c0006077a24 */
/* 0x000fe200078e0203 */
/*0100*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0110*/ IMAD.WIDE R4, R7, R2, c[0x0][0x160] ; /* 0x0000580007047625 */
/* 0x000fcc00078e0202 */
/*0120*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0130*/ IADD3 R11, R7, c[0x0][0x0], RZ ; /* 0x00000000070b7a10 */
/* 0x000fe20007ffe0ff */
/*0140*/ IMAD R3, R3, c[0x0][0x174], R6 ; /* 0x00005d0003037a24 */
/* 0x000fc800078e0206 */
/*0150*/ IMAD.WIDE R6, R3, R2, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0202 */
/*0160*/ IMAD.WIDE.U32 R8, R11.reuse, R2, c[0x0][0x160] ; /* 0x000058000b087625 */
/* 0x040fe200078e0002 */
/*0170*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x0041ea000c101904 */
/*0180*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0190*/ IMAD R13, R14, c[0x0][0x174], R3 ; /* 0x00005d000e0d7a24 */
/* 0x000fe200078e0203 */
/*01a0*/ IADD3 R15, R11, c[0x0][0x0], RZ ; /* 0x000000000b0f7a10 */
/* 0x000fc60007ffe0ff */
/*01b0*/ IMAD.WIDE.U32 R10, R13, R2, c[0x0][0x168] ; /* 0x00005a000d0a7625 */
/* 0x000fc800078e0002 */
/*01c0*/ IMAD.WIDE.U32 R12, R15.reuse, R2, c[0x0][0x160] ; /* 0x000058000f0c7625 */
/* 0x040fe200078e0002 */
/*01d0*/ SHF.L.U32 R4, R14, 0x1, RZ ; /* 0x000000010e047819 */
/* 0x000fe200000006ff */
/*01e0*/ STG.E [R10.64], R9 ; /* 0x000000090a007986 */
/* 0x004fe8000c101904 */
/*01f0*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000ea2000c1e1900 */
/*0200*/ IADD3 R15, R15, c[0x0][0x0], RZ ; /* 0x000000000f0f7a10 */
/* 0x000fe20007ffe0ff */
/*0210*/ IMAD R17, R4, c[0x0][0x174], R3 ; /* 0x00005d0004117a24 */
/* 0x000fc800078e0203 */
/*0220*/ IMAD.WIDE.U32 R4, R17, R2, c[0x0][0x168] ; /* 0x00005a0011047625 */
/* 0x001fc800078e0002 */
/*0230*/ IMAD.WIDE.U32 R6, R15, R2, c[0x0][0x160] ; /* 0x000058000f067625 */
/* 0x000fe200078e0002 */
/*0240*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x004fea000c101904 */
/*0250*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea2000c1e1900 */
/*0260*/ IMAD R3, R0, c[0x0][0x174], R3 ; /* 0x00005d0000037a24 */
/* 0x000fc800078e0203 */
/*0270*/ IMAD.WIDE.U32 R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fca00078e0002 */
/*0280*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x004fe2000c101904 */
/*0290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02a0*/ BRA 0x2a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21transpose_unroll4_rowPiS_ii
.globl _Z21transpose_unroll4_rowPiS_ii
.p2align 8
.type _Z21transpose_unroll4_rowPiS_ii,@function
_Z21transpose_unroll4_rowPiS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_mul_i32 s14, s14, s7
s_mul_i32 s6, s7, 3
v_lshl_add_u32 v0, s14, 2, v1
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, s6, v0
v_cmp_gt_i32_e64 s2, s5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_u32_e32 vcc_lo, s4, v2
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_mul_i32 s4, s7, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_load_b32 v8, v[3:4], off
v_mad_u64_u32 v[3:4], null, v0, s5, v[1:2]
v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, s7, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[6:7], 2, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
v_add_nc_u32_e32 v0, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[3:4]
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v8, off
global_load_b32 v8, v[6:7], off
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_lshl_add_u32 v0, s7, 1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[6:7], 2, v[0:1]
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_lshl_add_u32 v0, s4, 1, v3
v_add_co_u32 v6, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v8, off
global_load_b32 v8, v[6:7], off
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_add_nc_u32_e32 v0, s6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[6:7], 2, v[0:1]
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v6
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v8, off
global_load_b32 v2, v[6:7], off
v_mad_u64_u32 v[4:5], null, s4, 3, v[3:4]
v_mov_b32_e32 v5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[4:5]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21transpose_unroll4_rowPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21transpose_unroll4_rowPiS_ii, .Lfunc_end0-_Z21transpose_unroll4_rowPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21transpose_unroll4_rowPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21transpose_unroll4_rowPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00123f0f_00000000-6_transpose_unroll4_row.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z21transpose_unroll4_rowPiS_iiPiS_ii
.type _Z45__device_stub__Z21transpose_unroll4_rowPiS_iiPiS_ii, @function
_Z45__device_stub__Z21transpose_unroll4_rowPiS_iiPiS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21transpose_unroll4_rowPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z21transpose_unroll4_rowPiS_iiPiS_ii, .-_Z45__device_stub__Z21transpose_unroll4_rowPiS_iiPiS_ii
.globl _Z21transpose_unroll4_rowPiS_ii
.type _Z21transpose_unroll4_rowPiS_ii, @function
_Z21transpose_unroll4_rowPiS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z21transpose_unroll4_rowPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z21transpose_unroll4_rowPiS_ii, .-_Z21transpose_unroll4_rowPiS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z21transpose_unroll4_rowPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21transpose_unroll4_rowPiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "transpose_unroll4_row.hip"
.globl _Z36__device_stub__transpose_unroll4_rowPiS_ii # -- Begin function _Z36__device_stub__transpose_unroll4_rowPiS_ii
.p2align 4, 0x90
.type _Z36__device_stub__transpose_unroll4_rowPiS_ii,@function
_Z36__device_stub__transpose_unroll4_rowPiS_ii: # @_Z36__device_stub__transpose_unroll4_rowPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21transpose_unroll4_rowPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z36__device_stub__transpose_unroll4_rowPiS_ii, .Lfunc_end0-_Z36__device_stub__transpose_unroll4_rowPiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21transpose_unroll4_rowPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21transpose_unroll4_rowPiS_ii,@object # @_Z21transpose_unroll4_rowPiS_ii
.section .rodata,"a",@progbits
.globl _Z21transpose_unroll4_rowPiS_ii
.p2align 3, 0x0
_Z21transpose_unroll4_rowPiS_ii:
.quad _Z36__device_stub__transpose_unroll4_rowPiS_ii
.size _Z21transpose_unroll4_rowPiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21transpose_unroll4_rowPiS_ii"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__transpose_unroll4_rowPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21transpose_unroll4_rowPiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // NAME: Jose Torres
#include <stdio.h>
#include <iostream>
#include <assert.h>
__global__ void matrixMulCUDA(float *A, float *B, float *C, int size){
// Code from HW slide
__shared__ float smem_c[64][64];
__shared__ float smem_a[64][8];
__shared__ float smem_b[8][64];
int c = blockIdx.x * 64;
int r = blockIdx.y * 64;
for(int kk = 0; kk < size; kk += 8){
for(int i = threadIdx.x + blockDim.x * threadIdx.y;
i < 64 * 8;
i += blockDim.x * blockDim.y){
// load into shared memory
int k = kk + i / 64;
int rt = r + i % 64;
int ct = c + i % 64;
smem_a[i%64][i/64] = A[rt*size+k];
smem_b[i/64][i%64] = B[k*size+ct];
}
__syncthreads();
for(int i=0; i < 2; ++i){
for(int j=0; j < 2; ++j){
int rowIdx = threadIdx.y * 2 + j;
int colIdx = threadIdx.x * 2 + i;
for(int k=0; k < 8; ++k){
// Store / Compute results in shared C
smem_c[rowIdx][colIdx] += smem_a[rowIdx][k] * smem_b[k][colIdx];
}
// Store back into global memory
C[(r+rowIdx) * size + (c+colIdx)] = smem_c[rowIdx][colIdx];
}
}
}
}
int main() {
const int N = 8192;
// Declare host memory for Matrices A and B
float *hostA, *hostB, *hostC, *hostSumTemp;
// Declare device memory
float *deviceA, *deviceB, *deviceC;
// Allocate host memory for all Matrices
size_t memSize = sizeof(float) * N * N;
hostA = (float*) malloc(memSize);
hostB = (float*) malloc(memSize);
hostC = (float*) malloc(memSize);
hostSumTemp = (float*) malloc(memSize);
// init host memory
// A = 2, 2, 2, 2 . . .
// B = 3, 3, 3, 3 . . .
// C = 0, 0, 0, 0 . . .
// hostSumTemp = 6, 6, 6, 6, ...
// hostSumTemp is just temp variable to compare to
// values are chosen to be really easy
for(int i=0; i < N; ++i){
for(int j=0; j < N; ++j){
hostA[i*N+j] = 2;
hostB[i*N+j] = 3;
hostC[i*N+j] = 0;
hostSumTemp[i*N+j] = 6;
}
}
// Allocate device memory
cudaMalloc((void**) &deviceA, memSize);
cudaMalloc((void**) &deviceB, memSize);
cudaMalloc((void**) &deviceC, memSize);
// Copy Matrix A and B from host to device
cudaMemcpy(deviceA, hostA, memSize, cudaMemcpyHostToDevice);
cudaMemcpy(deviceB, hostB, memSize, cudaMemcpyHostToDevice);
// Invoke Kernel
dim3 nblocks(N / 64, N / 64);
dim3 nthreads(32, 32);
// Init Kernel
matrixMulCUDA<<<nblocks, nthreads>>> (deviceA, deviceB, deviceC, N);
// Transfer from result matrix from device to host
cudaMemcpy(hostC, deviceC, memSize, cudaMemcpyDeviceToHost);
// Check results
bool isSame = true;
int row, col;
for(row=0; row < N; ++row){
for(col=0; col < N; ++col){
if(hostC[row*N+col] != hostSumTemp[row*N+col]){
isSame = false;
break;
}
}
}
// Print comparasion
if(!isSame){
std::cout << "Did not match at \n\trow = " << row << "\n\tcol = " << col << std::endl;
} else {
std::cout << "Results matched.\n";
}
// free memory
free(hostA);
free(hostB);
free(hostC);
free(hostSumTemp);
cudaFree(deviceA);
cudaFree(deviceB);
cudaFree(deviceC);
return 0;
} | code for sm_80
Function : _Z13matrixMulCUDAPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fc80000000f00 */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2UR UR5, SR_CTAID.Y ; /* 0x00000000000579c3 */
/* 0x000e220000002600 */
/*0050*/ S2R R24, SR_TID.Y ; /* 0x0000000000187919 */
/* 0x000e620000002200 */
/*0060*/ MOV R25, RZ ; /* 0x000000ff00197202 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0080*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000ea60000002100 */
/*0090*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000ee20000002500 */
/*00a0*/ USHF.L.U32 UR5, UR5, 0x6, URZ ; /* 0x0000000605057899 */
/* 0x001fe2000800063f */
/*00b0*/ SHF.L.U32 R23, R0, 0x3, RZ ; /* 0x0000000300177819 */
/* 0x004fe200000006ff */
/*00c0*/ IMAD R22, R24, c[0x0][0x0], R0 ; /* 0x0000000018167a24 */
/* 0x002fc800078e0200 */
/*00d0*/ LEA R3, R24.reuse, UR5, 0x1 ; /* 0x0000000518037c11 */
/* 0x040fe2000f8e08ff */
/*00e0*/ USHF.L.U32 UR4, UR4, 0x6, URZ ; /* 0x0000000604047899 */
/* 0x008fe2000800063f */
/*00f0*/ LEA R23, R24.reuse, R23, 0x9 ; /* 0x0000001718177211 */
/* 0x040fe400078e48ff */
/*0100*/ IADD3 R5, R3, 0x1, RZ ; /* 0x0000000103057810 */
/* 0x000fe40007ffe0ff */
/*0110*/ LEA R24, R24, 0x4000, 0x6 ; /* 0x0000400018187811 */
/* 0x000fe400078e30ff */
/*0120*/ LEA R2, R0, UR4, 0x1 ; /* 0x0000000400027c11 */
/* 0x000fca000f8e08ff */
/*0130*/ IMAD R20, R3, c[0x0][0x178], R2.reuse ; /* 0x00005e0003147a24 */
/* 0x100fe200078e0202 */
/*0140*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0150*/ IMAD R2, R5, c[0x0][0x178], R2 ; /* 0x00005e0005027a24 */
/* 0x000fd200078e0202 */
/*0160*/ IMAD.WIDE R20, R20, R3, c[0x0][0x170] ; /* 0x00005c0014147625 */
/* 0x000fc800078e0203 */
/*0170*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fc800078e0203 */
/*0180*/ ISETP.GT.AND P0, PT, R22, 0x1ff, PT ; /* 0x000001ff1600780c */
/* 0x000fe20003f04270 */
/*0190*/ BSSY B0, 0x360 ; /* 0x000001c000007945 */
/* 0x000fd80003800000 */
/*01a0*/ @P0 BRA 0x350 ; /* 0x000001a000000947 */
/* 0x001fea0003800000 */
/*01b0*/ MOV R8, R22 ; /* 0x0000001600087202 */
/* 0x000fc80000000f00 */
/*01c0*/ SHF.R.S32.HI R5, RZ, 0x1f, R8 ; /* 0x0000001fff057819 */
/* 0x000fe20000011408 */
/*01d0*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x001fc600000001ff */
/*01e0*/ LEA.HI R5, R5, R8, RZ, 0x6 ; /* 0x0000000805057211 */
/* 0x000fc800078f30ff */
/*01f0*/ LOP3.LUT R7, R5, 0xffffffc0, RZ, 0xc0, !PT ; /* 0xffffffc005077812 */
/* 0x000fe400078ec0ff */
/*0200*/ SHF.R.S32.HI R10, RZ, 0x6, R5 ; /* 0x00000006ff0a7819 */
/* 0x000fe40000011405 */
/*0210*/ IADD3 R9, -R7, R8, RZ ; /* 0x0000000807097210 */
/* 0x000fe40007ffe1ff */
/*0220*/ IADD3 R4, R10, R25, RZ ; /* 0x000000190a047210 */
/* 0x000fe40007ffe0ff */
/*0230*/ IADD3 R5, R9.reuse, UR5, RZ ; /* 0x0000000509057c10 */
/* 0x040fe4000fffe0ff */
/*0240*/ IADD3 R7, R9, UR4, RZ ; /* 0x0000000409077c10 */
/* 0x000fc6000fffe0ff */
/*0250*/ IMAD R5, R5, c[0x0][0x178], R4 ; /* 0x00005e0005057a24 */
/* 0x000fe400078e0204 */
/*0260*/ IMAD R7, R4, c[0x0][0x178], R7 ; /* 0x00005e0004077a24 */
/* 0x000fe400078e0207 */
/*0270*/ IMAD.WIDE R4, R5, R6, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fc800078e0206 */
/*0280*/ IMAD.WIDE R6, R7, R6, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x000fe400078e0206 */
/*0290*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea8000c1e1900 */
/*02a0*/ LDG.E R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ee2000c1e1900 */
/*02b0*/ LEA R11, R9, 0x4000, 0x5 ; /* 0x00004000090b7811 */
/* 0x000fe400078e28ff */
/*02c0*/ LEA R12, R10.reuse, 0x4800, 0x8 ; /* 0x000048000a0c7811 */
/* 0x040fe400078e40ff */
/*02d0*/ LEA R11, R10, R11, 0x2 ; /* 0x0000000b0a0b7211 */
/* 0x000fc400078e10ff */
/*02e0*/ LEA R9, R9, R12, 0x2 ; /* 0x0000000c09097211 */
/* 0x000fe400078e10ff */
/*02f0*/ MOV R13, c[0x0][0x0] ; /* 0x00000000000d7a02 */
/* 0x000fca0000000f00 */
/*0300*/ IMAD R8, R13, c[0x0][0x4], R8 ; /* 0x000001000d087a24 */
/* 0x000fca00078e0208 */
/*0310*/ ISETP.GE.AND P0, PT, R8, 0x200, PT ; /* 0x000002000800780c */
/* 0x000fe20003f06270 */
/*0320*/ STS [R11], R4 ; /* 0x000000040b007388 */
/* 0x0041e80000000800 */
/*0330*/ STS [R9], R6 ; /* 0x0000000609007388 */
/* 0x0081f00000000800 */
/*0340*/ @!P0 BRA 0x1c0 ; /* 0xfffffe7000008947 */
/* 0x000fea000383ffff */
/*0350*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0360*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0370*/ IADD3 R25, R25, 0x8, RZ ; /* 0x0000000819197810 */
/* 0x000fc80007ffe0ff */
/*0380*/ ISETP.GE.AND P0, PT, R25, c[0x0][0x178], PT ; /* 0x00005e0019007a0c */
/* 0x000fe20003f06270 */
/*0390*/ LDS R17, [R0.X8+0x4800] ; /* 0x0048000000117984 */
/* 0x000fe80000008800 */
/*03a0*/ LDS R12, [R23] ; /* 0x00000000170c7984 */
/* 0x000fe80000000800 */
/*03b0*/ LDS.128 R4, [R24] ; /* 0x0000000018047984 */
/* 0x001e280000000c00 */
/*03c0*/ LDS R34, [R0.X8+0x4900] ; /* 0x0049000000227984 */
/* 0x000e680000008800 */
/*03d0*/ LDS R29, [R0.X8+0x4a00] ; /* 0x004a0000001d7984 */
/* 0x000ea80000008800 */
/*03e0*/ LDS R30, [R0.X8+0x4b00] ; /* 0x004b0000001e7984 */
/* 0x000ee80000008800 */
/*03f0*/ LDS R31, [R0.X8+0x4c00] ; /* 0x004c0000001f7984 */
/* 0x000fe80000008800 */
/*0400*/ LDS.128 R8, [R24+0x10] ; /* 0x0000100018087984 */
/* 0x000f280000000c00 */
/*0410*/ LDS R32, [R0.X8+0x4d00] ; /* 0x004d000000207984 */
/* 0x000f680000008800 */
/*0420*/ LDS R27, [R0.X8+0x4e00] ; /* 0x004e0000001b7984 */
/* 0x000f680000008800 */
/*0430*/ LDS R28, [R0.X8+0x4f00] ; /* 0x004f0000001c7984 */
/* 0x000f680000008800 */
/*0440*/ LDS R16, [R23+0x100] ; /* 0x0001000017107984 */
/* 0x000fe20000000800 */
/*0450*/ FFMA R12, R17, R4, R12 ; /* 0x00000004110c7223 */
/* 0x001fc8000000000c */
/*0460*/ FFMA R12, R34, R5, R12 ; /* 0x00000005220c7223 */
/* 0x002fc8000000000c */
/*0470*/ FFMA R12, R29, R6, R12 ; /* 0x000000061d0c7223 */
/* 0x004fc8000000000c */
/*0480*/ FFMA R12, R30, R7, R12 ; /* 0x000000071e0c7223 */
/* 0x008fc8000000000c */
/*0490*/ FFMA R12, R31, R8, R12 ; /* 0x000000081f0c7223 */
/* 0x010fc8000000000c */
/*04a0*/ FFMA R12, R32, R9, R12 ; /* 0x00000009200c7223 */
/* 0x020fc8000000000c */
/*04b0*/ FFMA R12, R27, R10, R12 ; /* 0x0000000a1b0c7223 */
/* 0x000fc8000000000c */
/*04c0*/ FFMA R26, R28, R11, R12 ; /* 0x0000000b1c1a7223 */
/* 0x000fca000000000c */
/*04d0*/ STS [R23], R26 ; /* 0x0000001a17007388 */
/* 0x000fe80000000800 */
/*04e0*/ LDS.128 R12, [R24+0x20] ; /* 0x00002000180c7984 */
/* 0x000e280000000c00 */
/*04f0*/ STG.E [R20.64], R26 ; /* 0x0000001a14007986 */
/* 0x000fe2000c101906 */
/*0500*/ FFMA R33, R17, R12, R16 ; /* 0x0000000c11217223 */
/* 0x001fc60000000010 */
/*0510*/ LDS.128 R16, [R24+0x30] ; /* 0x0000300018107984 */
/* 0x000e220000000c00 */
/*0520*/ FFMA R33, R34, R13, R33 ; /* 0x0000000d22217223 */
/* 0x000fc80000000021 */
/*0530*/ FFMA R33, R29, R14, R33 ; /* 0x0000000e1d217223 */
/* 0x000fc80000000021 */
/*0540*/ FFMA R33, R30, R15, R33 ; /* 0x0000000f1e217223 */
/* 0x000fc80000000021 */
/*0550*/ FFMA R33, R31, R16, R33 ; /* 0x000000101f217223 */
/* 0x001fc80000000021 */
/*0560*/ FFMA R33, R32, R17, R33 ; /* 0x0000001120217223 */
/* 0x000fc80000000021 */
/*0570*/ FFMA R33, R27, R18, R33 ; /* 0x000000121b217223 */
/* 0x000fe40000000021 */
/*0580*/ LDS R27, [R23+0x104] ; /* 0x00010400171b7984 */
/* 0x000fe40000000800 */
/*0590*/ FFMA R28, R28, R19, R33 ; /* 0x000000131c1c7223 */
/* 0x000fe40000000021 */
/*05a0*/ LDS R33, [R23+0x4] ; /* 0x0000040017217984 */
/* 0x000fe80000000800 */
/*05b0*/ STS [R23+0x100], R28 ; /* 0x0001001c17007388 */
/* 0x000fe80000000800 */
/*05c0*/ LDS R29, [R0.X8+0x4804] ; /* 0x00480400001d7984 */
/* 0x000e280000008800 */
/*05d0*/ LDS R32, [R0.X8+0x4904] ; /* 0x0049040000207984 */
/* 0x000e680000008800 */
/*05e0*/ LDS R31, [R0.X8+0x4a04] ; /* 0x004a0400001f7984 */
/* 0x000ea80000008800 */
/*05f0*/ LDS R30, [R0.X8+0x4b04] ; /* 0x004b0400001e7984 */
/* 0x000ee80000008800 */
/*0600*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101906 */
/*0610*/ FFMA R4, R4, R29, R33 ; /* 0x0000001d04047223 */
/* 0x001fc60000000021 */
/*0620*/ LDS R33, [R0.X8+0x4c04] ; /* 0x004c040000217984 */
/* 0x000e220000008800 */
/*0630*/ FFMA R27, R12, R29, R27 ; /* 0x0000001d0c1b7223 */
/* 0x000fe4000000001b */
/*0640*/ FFMA R5, R32.reuse, R5, R4 ; /* 0x0000000520057223 */
/* 0x042fe40000000004 */
/*0650*/ LDS R4, [R0.X8+0x4d04] ; /* 0x004d040000047984 */
/* 0x000e620000008800 */
/*0660*/ FFMA R27, R32, R13, R27 ; /* 0x0000000d201b7223 */
/* 0x000fe4000000001b */
/*0670*/ FFMA R34, R31.reuse, R6, R5 ; /* 0x000000061f227223 */
/* 0x044fe40000000005 */
/*0680*/ LDS R5, [R0.X8+0x4e04] ; /* 0x004e040000057984 */
/* 0x000ea20000008800 */
/*0690*/ FFMA R27, R31, R14, R27 ; /* 0x0000000e1f1b7223 */
/* 0x000fc4000000001b */
/*06a0*/ FFMA R34, R30.reuse, R7, R34 ; /* 0x000000071e227223 */
/* 0x048fe20000000022 */
/*06b0*/ LDS R6, [R0.X8+0x4f04] ; /* 0x004f040000067984 */
/* 0x000ee20000008800 */
/*06c0*/ FFMA R27, R30, R15, R27 ; /* 0x0000000f1e1b7223 */
/* 0x000fe4000000001b */
/*06d0*/ FFMA R34, R8, R33.reuse, R34 ; /* 0x0000002108227223 */
/* 0x081fe40000000022 */
/*06e0*/ FFMA R27, R16, R33, R27 ; /* 0x00000021101b7223 */
/* 0x000fe4000000001b */
/*06f0*/ FFMA R34, R4.reuse, R9, R34 ; /* 0x0000000904227223 */
/* 0x042fe40000000022 */
/*0700*/ FFMA R27, R4, R17, R27 ; /* 0x00000011041b7223 */
/* 0x000fc4000000001b */
/*0710*/ FFMA R34, R5.reuse, R10, R34 ; /* 0x0000000a05227223 */
/* 0x044fe40000000022 */
/*0720*/ FFMA R27, R5, R18, R27 ; /* 0x00000012051b7223 */
/* 0x000fe4000000001b */
/*0730*/ FFMA R34, R6.reuse, R11, R34 ; /* 0x0000000b06227223 */
/* 0x048fe40000000022 */
/*0740*/ FFMA R27, R6, R19, R27 ; /* 0x00000013061b7223 */
/* 0x000fc6000000001b */
/*0750*/ STG.E [R20.64+0x4], R34 ; /* 0x0000042214007986 */
/* 0x0001e8000c101906 */
/*0760*/ STS [R23+0x4], R34 ; /* 0x0000042217007388 */
/* 0x0001e80000000800 */
/*0770*/ STS [R23+0x104], R27 ; /* 0x0001041b17007388 */
/* 0x0001e80000000800 */
/*0780*/ STG.E [R2.64+0x4], R27 ; /* 0x0000041b02007986 */
/* 0x0001e2000c101906 */
/*0790*/ @!P0 BRA 0x180 ; /* 0xfffff9e000008947 */
/* 0x000fea000383ffff */
/*07a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07b0*/ BRA 0x7b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // NAME: Jose Torres
#include <stdio.h>
#include <iostream>
#include <assert.h>
__global__ void matrixMulCUDA(float *A, float *B, float *C, int size){
// Code from HW slide
__shared__ float smem_c[64][64];
__shared__ float smem_a[64][8];
__shared__ float smem_b[8][64];
int c = blockIdx.x * 64;
int r = blockIdx.y * 64;
for(int kk = 0; kk < size; kk += 8){
for(int i = threadIdx.x + blockDim.x * threadIdx.y;
i < 64 * 8;
i += blockDim.x * blockDim.y){
// load into shared memory
int k = kk + i / 64;
int rt = r + i % 64;
int ct = c + i % 64;
smem_a[i%64][i/64] = A[rt*size+k];
smem_b[i/64][i%64] = B[k*size+ct];
}
__syncthreads();
for(int i=0; i < 2; ++i){
for(int j=0; j < 2; ++j){
int rowIdx = threadIdx.y * 2 + j;
int colIdx = threadIdx.x * 2 + i;
for(int k=0; k < 8; ++k){
// Store / Compute results in shared C
smem_c[rowIdx][colIdx] += smem_a[rowIdx][k] * smem_b[k][colIdx];
}
// Store back into global memory
C[(r+rowIdx) * size + (c+colIdx)] = smem_c[rowIdx][colIdx];
}
}
}
}
int main() {
const int N = 8192;
// Declare host memory for Matrices A and B
float *hostA, *hostB, *hostC, *hostSumTemp;
// Declare device memory
float *deviceA, *deviceB, *deviceC;
// Allocate host memory for all Matrices
size_t memSize = sizeof(float) * N * N;
hostA = (float*) malloc(memSize);
hostB = (float*) malloc(memSize);
hostC = (float*) malloc(memSize);
hostSumTemp = (float*) malloc(memSize);
// init host memory
// A = 2, 2, 2, 2 . . .
// B = 3, 3, 3, 3 . . .
// C = 0, 0, 0, 0 . . .
// hostSumTemp = 6, 6, 6, 6, ...
// hostSumTemp is just temp variable to compare to
// values are chosen to be really easy
for(int i=0; i < N; ++i){
for(int j=0; j < N; ++j){
hostA[i*N+j] = 2;
hostB[i*N+j] = 3;
hostC[i*N+j] = 0;
hostSumTemp[i*N+j] = 6;
}
}
// Allocate device memory
cudaMalloc((void**) &deviceA, memSize);
cudaMalloc((void**) &deviceB, memSize);
cudaMalloc((void**) &deviceC, memSize);
// Copy Matrix A and B from host to device
cudaMemcpy(deviceA, hostA, memSize, cudaMemcpyHostToDevice);
cudaMemcpy(deviceB, hostB, memSize, cudaMemcpyHostToDevice);
// Invoke Kernel
dim3 nblocks(N / 64, N / 64);
dim3 nthreads(32, 32);
// Init Kernel
matrixMulCUDA<<<nblocks, nthreads>>> (deviceA, deviceB, deviceC, N);
// Transfer from result matrix from device to host
cudaMemcpy(hostC, deviceC, memSize, cudaMemcpyDeviceToHost);
// Check results
bool isSame = true;
int row, col;
for(row=0; row < N; ++row){
for(col=0; col < N; ++col){
if(hostC[row*N+col] != hostSumTemp[row*N+col]){
isSame = false;
break;
}
}
}
// Print comparasion
if(!isSame){
std::cout << "Did not match at \n\trow = " << row << "\n\tcol = " << col << std::endl;
} else {
std::cout << "Results matched.\n";
}
// free memory
free(hostA);
free(hostB);
free(hostC);
free(hostSumTemp);
cudaFree(deviceA);
cudaFree(deviceB);
cudaFree(deviceC);
return 0;
} | .file "tmpxft_0011b3da_00000000-6_matrixMul.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z13matrixMulCUDAPfS_S_iPfS_S_i
.type _Z38__device_stub__Z13matrixMulCUDAPfS_S_iPfS_S_i, @function
_Z38__device_stub__Z13matrixMulCUDAPfS_S_iPfS_S_i:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13matrixMulCUDAPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z38__device_stub__Z13matrixMulCUDAPfS_S_iPfS_S_i, .-_Z38__device_stub__Z13matrixMulCUDAPfS_S_iPfS_S_i
.globl _Z13matrixMulCUDAPfS_S_i
.type _Z13matrixMulCUDAPfS_S_i, @function
_Z13matrixMulCUDAPfS_S_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13matrixMulCUDAPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z13matrixMulCUDAPfS_S_i, .-_Z13matrixMulCUDAPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "Did not match at \n\trow = "
.LC5:
.string "\n\tcol = "
.LC6:
.string "Results matched.\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $268435456, %edi
call malloc@PLT
movq %rax, %r13
movl $268435456, %edi
call malloc@PLT
movq %rax, %r12
movl $268435456, %edi
call malloc@PLT
movq %rax, %rbx
movl $268435456, %edi
call malloc@PLT
movq %rax, %rbp
movl $32768, %edx
movss .LC0(%rip), %xmm2
movss .LC1(%rip), %xmm1
movss .LC3(%rip), %xmm0
.L12:
leaq -32768(%rdx), %rax
.L13:
movss %xmm2, 0(%r13,%rax)
movss %xmm1, (%r12,%rax)
movl $0x00000000, (%rbx,%rax)
movss %xmm0, 0(%rbp,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L13
addq $32768, %rdx
cmpq $268468224, %rdx
jne .L12
leaq 8(%rsp), %rdi
movl $268435456, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $268435456, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $268435456, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $268435456, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $268435456, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 32(%rsp)
movl $128, 36(%rsp)
movl $32, 44(%rsp)
movl $32, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L15:
movl $2, %ecx
movl $268435456, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $0, %edx
movl $1, %ecx
movl $0, %esi
jmp .L16
.L29:
movl $8192, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z38__device_stub__Z13matrixMulCUDAPfS_S_iPfS_S_i
jmp .L15
.L24:
movl %esi, %ecx
.L17:
addq $32768, %rdx
cmpq $268435456, %rdx
je .L20
.L16:
movq %rdx, %rax
movl $0, %r14d
.L19:
movss (%rbx,%rax), %xmm0
ucomiss 0(%rbp,%rax), %xmm0
jp .L24
jne .L24
addl $1, %r14d
addq $4, %rax
cmpl $8192, %r14d
jne .L19
jmp .L17
.L20:
testb %cl, %cl
jne .L21
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $8192, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r14d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L22:
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L22
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z13matrixMulCUDAPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z13matrixMulCUDAPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1073741824
.align 4
.LC1:
.long 1077936128
.align 4
.LC3:
.long 1086324736
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // NAME: Jose Torres
#include <stdio.h>
#include <iostream>
#include <assert.h>
__global__ void matrixMulCUDA(float *A, float *B, float *C, int size){
// Code from HW slide
__shared__ float smem_c[64][64];
__shared__ float smem_a[64][8];
__shared__ float smem_b[8][64];
int c = blockIdx.x * 64;
int r = blockIdx.y * 64;
for(int kk = 0; kk < size; kk += 8){
for(int i = threadIdx.x + blockDim.x * threadIdx.y;
i < 64 * 8;
i += blockDim.x * blockDim.y){
// load into shared memory
int k = kk + i / 64;
int rt = r + i % 64;
int ct = c + i % 64;
smem_a[i%64][i/64] = A[rt*size+k];
smem_b[i/64][i%64] = B[k*size+ct];
}
__syncthreads();
for(int i=0; i < 2; ++i){
for(int j=0; j < 2; ++j){
int rowIdx = threadIdx.y * 2 + j;
int colIdx = threadIdx.x * 2 + i;
for(int k=0; k < 8; ++k){
// Store / Compute results in shared C
smem_c[rowIdx][colIdx] += smem_a[rowIdx][k] * smem_b[k][colIdx];
}
// Store back into global memory
C[(r+rowIdx) * size + (c+colIdx)] = smem_c[rowIdx][colIdx];
}
}
}
}
int main() {
const int N = 8192;
// Declare host memory for Matrices A and B
float *hostA, *hostB, *hostC, *hostSumTemp;
// Declare device memory
float *deviceA, *deviceB, *deviceC;
// Allocate host memory for all Matrices
size_t memSize = sizeof(float) * N * N;
hostA = (float*) malloc(memSize);
hostB = (float*) malloc(memSize);
hostC = (float*) malloc(memSize);
hostSumTemp = (float*) malloc(memSize);
// init host memory
// A = 2, 2, 2, 2 . . .
// B = 3, 3, 3, 3 . . .
// C = 0, 0, 0, 0 . . .
// hostSumTemp = 6, 6, 6, 6, ...
// hostSumTemp is just temp variable to compare to
// values are chosen to be really easy
for(int i=0; i < N; ++i){
for(int j=0; j < N; ++j){
hostA[i*N+j] = 2;
hostB[i*N+j] = 3;
hostC[i*N+j] = 0;
hostSumTemp[i*N+j] = 6;
}
}
// Allocate device memory
cudaMalloc((void**) &deviceA, memSize);
cudaMalloc((void**) &deviceB, memSize);
cudaMalloc((void**) &deviceC, memSize);
// Copy Matrix A and B from host to device
cudaMemcpy(deviceA, hostA, memSize, cudaMemcpyHostToDevice);
cudaMemcpy(deviceB, hostB, memSize, cudaMemcpyHostToDevice);
// Invoke Kernel
dim3 nblocks(N / 64, N / 64);
dim3 nthreads(32, 32);
// Init Kernel
matrixMulCUDA<<<nblocks, nthreads>>> (deviceA, deviceB, deviceC, N);
// Transfer from result matrix from device to host
cudaMemcpy(hostC, deviceC, memSize, cudaMemcpyDeviceToHost);
// Check results
bool isSame = true;
int row, col;
for(row=0; row < N; ++row){
for(col=0; col < N; ++col){
if(hostC[row*N+col] != hostSumTemp[row*N+col]){
isSame = false;
break;
}
}
}
// Print comparasion
if(!isSame){
std::cout << "Did not match at \n\trow = " << row << "\n\tcol = " << col << std::endl;
} else {
std::cout << "Results matched.\n";
}
// free memory
free(hostA);
free(hostB);
free(hostC);
free(hostSumTemp);
cudaFree(deviceA);
cudaFree(deviceB);
cudaFree(deviceC);
return 0;
} | // NAME: Jose Torres
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <assert.h>
__global__ void matrixMulCUDA(float *A, float *B, float *C, int size){
// Code from HW slide
__shared__ float smem_c[64][64];
__shared__ float smem_a[64][8];
__shared__ float smem_b[8][64];
int c = blockIdx.x * 64;
int r = blockIdx.y * 64;
for(int kk = 0; kk < size; kk += 8){
for(int i = threadIdx.x + blockDim.x * threadIdx.y;
i < 64 * 8;
i += blockDim.x * blockDim.y){
// load into shared memory
int k = kk + i / 64;
int rt = r + i % 64;
int ct = c + i % 64;
smem_a[i%64][i/64] = A[rt*size+k];
smem_b[i/64][i%64] = B[k*size+ct];
}
__syncthreads();
for(int i=0; i < 2; ++i){
for(int j=0; j < 2; ++j){
int rowIdx = threadIdx.y * 2 + j;
int colIdx = threadIdx.x * 2 + i;
for(int k=0; k < 8; ++k){
// Store / Compute results in shared C
smem_c[rowIdx][colIdx] += smem_a[rowIdx][k] * smem_b[k][colIdx];
}
// Store back into global memory
C[(r+rowIdx) * size + (c+colIdx)] = smem_c[rowIdx][colIdx];
}
}
}
}
int main() {
const int N = 8192;
// Declare host memory for Matrices A and B
float *hostA, *hostB, *hostC, *hostSumTemp;
// Declare device memory
float *deviceA, *deviceB, *deviceC;
// Allocate host memory for all Matrices
size_t memSize = sizeof(float) * N * N;
hostA = (float*) malloc(memSize);
hostB = (float*) malloc(memSize);
hostC = (float*) malloc(memSize);
hostSumTemp = (float*) malloc(memSize);
// init host memory
// A = 2, 2, 2, 2 . . .
// B = 3, 3, 3, 3 . . .
// C = 0, 0, 0, 0 . . .
// hostSumTemp = 6, 6, 6, 6, ...
// hostSumTemp is just temp variable to compare to
// values are chosen to be really easy
for(int i=0; i < N; ++i){
for(int j=0; j < N; ++j){
hostA[i*N+j] = 2;
hostB[i*N+j] = 3;
hostC[i*N+j] = 0;
hostSumTemp[i*N+j] = 6;
}
}
// Allocate device memory
hipMalloc((void**) &deviceA, memSize);
hipMalloc((void**) &deviceB, memSize);
hipMalloc((void**) &deviceC, memSize);
// Copy Matrix A and B from host to device
hipMemcpy(deviceA, hostA, memSize, hipMemcpyHostToDevice);
hipMemcpy(deviceB, hostB, memSize, hipMemcpyHostToDevice);
// Invoke Kernel
dim3 nblocks(N / 64, N / 64);
dim3 nthreads(32, 32);
// Init Kernel
matrixMulCUDA<<<nblocks, nthreads>>> (deviceA, deviceB, deviceC, N);
// Transfer from result matrix from device to host
hipMemcpy(hostC, deviceC, memSize, hipMemcpyDeviceToHost);
// Check results
bool isSame = true;
int row, col;
for(row=0; row < N; ++row){
for(col=0; col < N; ++col){
if(hostC[row*N+col] != hostSumTemp[row*N+col]){
isSame = false;
break;
}
}
}
// Print comparasion
if(!isSame){
std::cout << "Did not match at \n\trow = " << row << "\n\tcol = " << col << std::endl;
} else {
std::cout << "Results matched.\n";
}
// free memory
free(hostA);
free(hostB);
free(hostC);
free(hostSumTemp);
hipFree(deviceA);
hipFree(deviceB);
hipFree(deviceC);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // NAME: Jose Torres
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <assert.h>
__global__ void matrixMulCUDA(float *A, float *B, float *C, int size){
// Code from HW slide
__shared__ float smem_c[64][64];
__shared__ float smem_a[64][8];
__shared__ float smem_b[8][64];
int c = blockIdx.x * 64;
int r = blockIdx.y * 64;
for(int kk = 0; kk < size; kk += 8){
for(int i = threadIdx.x + blockDim.x * threadIdx.y;
i < 64 * 8;
i += blockDim.x * blockDim.y){
// load into shared memory
int k = kk + i / 64;
int rt = r + i % 64;
int ct = c + i % 64;
smem_a[i%64][i/64] = A[rt*size+k];
smem_b[i/64][i%64] = B[k*size+ct];
}
__syncthreads();
for(int i=0; i < 2; ++i){
for(int j=0; j < 2; ++j){
int rowIdx = threadIdx.y * 2 + j;
int colIdx = threadIdx.x * 2 + i;
for(int k=0; k < 8; ++k){
// Store / Compute results in shared C
smem_c[rowIdx][colIdx] += smem_a[rowIdx][k] * smem_b[k][colIdx];
}
// Store back into global memory
C[(r+rowIdx) * size + (c+colIdx)] = smem_c[rowIdx][colIdx];
}
}
}
}
int main() {
const int N = 8192;
// Declare host memory for Matrices A and B
float *hostA, *hostB, *hostC, *hostSumTemp;
// Declare device memory
float *deviceA, *deviceB, *deviceC;
// Allocate host memory for all Matrices
size_t memSize = sizeof(float) * N * N;
hostA = (float*) malloc(memSize);
hostB = (float*) malloc(memSize);
hostC = (float*) malloc(memSize);
hostSumTemp = (float*) malloc(memSize);
// init host memory
// A = 2, 2, 2, 2 . . .
// B = 3, 3, 3, 3 . . .
// C = 0, 0, 0, 0 . . .
// hostSumTemp = 6, 6, 6, 6, ...
// hostSumTemp is just temp variable to compare to
// values are chosen to be really easy
for(int i=0; i < N; ++i){
for(int j=0; j < N; ++j){
hostA[i*N+j] = 2;
hostB[i*N+j] = 3;
hostC[i*N+j] = 0;
hostSumTemp[i*N+j] = 6;
}
}
// Allocate device memory
hipMalloc((void**) &deviceA, memSize);
hipMalloc((void**) &deviceB, memSize);
hipMalloc((void**) &deviceC, memSize);
// Copy Matrix A and B from host to device
hipMemcpy(deviceA, hostA, memSize, hipMemcpyHostToDevice);
hipMemcpy(deviceB, hostB, memSize, hipMemcpyHostToDevice);
// Invoke Kernel
dim3 nblocks(N / 64, N / 64);
dim3 nthreads(32, 32);
// Init Kernel
matrixMulCUDA<<<nblocks, nthreads>>> (deviceA, deviceB, deviceC, N);
// Transfer from result matrix from device to host
hipMemcpy(hostC, deviceC, memSize, hipMemcpyDeviceToHost);
// Check results
bool isSame = true;
int row, col;
for(row=0; row < N; ++row){
for(col=0; col < N; ++col){
if(hostC[row*N+col] != hostSumTemp[row*N+col]){
isSame = false;
break;
}
}
}
// Print comparasion
if(!isSame){
std::cout << "Did not match at \n\trow = " << row << "\n\tcol = " << col << std::endl;
} else {
std::cout << "Results matched.\n";
}
// free memory
free(hostA);
free(hostB);
free(hostC);
free(hostSumTemp);
hipFree(deviceA);
hipFree(deviceB);
hipFree(deviceC);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13matrixMulCUDAPfS_S_i
.globl _Z13matrixMulCUDAPfS_S_i
.p2align 8
.type _Z13matrixMulCUDAPfS_S_i,@function
_Z13matrixMulCUDAPfS_S_i:
s_load_b32 s10, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s10, 1
s_cbranch_scc1 .LBB0_12
s_clause 0x2
s_load_b32 s13, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_and_b32_e32 v5, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_lshl_b32 s11, s14, 6
s_lshl_b32 s12, s15, 6
s_add_u32 s8, s0, 32
s_addc_u32 s9, s1, 0
v_lshlrev_b32_e32 v2, 1, v0
v_lshlrev_b32_e32 v3, 1, v5
v_lshl_add_u32 v4, v0, 6, 0x4000
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s13, 0xffff
s_mov_b32 s13, 0
v_mad_u32_u24 v1, v0, s1, v5
v_lshl_add_u32 v5, v5, 3, 0x4800
s_delay_alu instid0(VALU_DEP_2)
v_cmp_gt_u32_e32 vcc_lo, 0x200, v1
.LBB0_2:
s_and_saveexec_b32 s14, vcc_lo
s_cbranch_execz .LBB0_5
s_load_b32 s0, s[8:9], 0xc
v_lshl_add_u32 v0, v1, 5, 0x4000
v_lshl_add_u32 v6, v1, 2, 0x4800
v_mov_b32_e32 v7, v1
s_mov_b32 s18, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s15, s0, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s1
s_lshl_b32 s16, s15, 5
s_lshl_b32 s17, s15, 2
.LBB0_4:
v_ashrrev_i32_e32 v8, 31, v7
v_add_nc_u32_e32 v9, s11, v7
v_add_nc_u32_e32 v10, s12, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v8, 26, v8
v_add_nc_u32_e32 v8, v7, v8
v_add_nc_u32_e32 v7, s15, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v14, 6, v8
v_and_b32_e32 v11, 0xffffffc0, v8
v_add_nc_u32_e32 v8, s13, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v9, v9, v11
v_sub_nc_u32_e32 v15, v10, v11
v_mad_u64_u32 v[10:11], null, s10, v8, v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[12:13], null, v15, s10, v[8:9]
v_ashrrev_i32_e32 v11, 31, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[8:9], 2, v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[10:11], 2, v[12:13]
v_add_co_u32 v8, s0, s6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v9, s0, s7, v9, s0
v_add_co_u32 v10, s0, s4, v10
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v11, s0, s5, v11, s0
global_load_b32 v12, v[8:9], off
global_load_b32 v10, v[10:11], off
v_mad_u64_u32 v[8:9], null, v14, 0xfffff804, v[0:1]
v_cmp_lt_i32_e64 s0, 0x1ff, v7
v_add_nc_u32_e32 v0, s16, v0
s_delay_alu instid0(VALU_DEP_2)
s_or_b32 s18, s0, s18
s_waitcnt vmcnt(1)
ds_store_b32 v6, v12
v_add_nc_u32_e32 v6, s17, v6
s_waitcnt vmcnt(0)
ds_store_b32 v8, v10
s_and_not1_b32 exec_lo, exec_lo, s18
s_cbranch_execnz .LBB0_4
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s14
v_mov_b32_e32 v6, v5
s_mov_b32 s14, 0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_6:
v_dual_mov_b32 v8, v4 :: v_dual_add_nc_u32 v7, s14, v3
s_mov_b32 s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v0, s11, v7
v_lshlrev_b32_e32 v7, 2, v7
.p2align 6
.LBB0_7:
v_dual_mov_b32 v12, v6 :: v_dual_add_nc_u32 v11, s15, v2
s_mov_b32 s0, 0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v10, v11, 8, v7
ds_load_b32 v9, v10
.LBB0_8:
v_add_nc_u32_e32 v13, s0, v8
s_add_i32 s0, s0, 4
ds_load_b32 v14, v12
ds_load_b32 v13, v13
v_add_nc_u32_e32 v12, 0x100, v12
s_cmp_eq_u32 s0, 32
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v9, v13, v14
s_cbranch_scc0 .LBB0_8
v_add_nc_u32_e32 v13, s12, v11
ds_store_b32 v10, v9
v_add_nc_u32_e32 v8, 32, v8
v_mad_u64_u32 v[11:12], null, v13, s10, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v10, s0, s2, v11
v_add_co_ci_u32_e64 v11, s0, s3, v12, s0
s_add_i32 s0, s15, 1
s_cmp_lg_u32 s15, 0
s_mov_b32 s15, s0
global_store_b32 v[10:11], v9, off
s_cbranch_scc0 .LBB0_7
v_add_nc_u32_e32 v6, 4, v6
s_add_i32 s0, s14, 1
s_cmp_lg_u32 s14, 0
s_mov_b32 s14, s0
s_cbranch_scc0 .LBB0_6
s_set_inst_prefetch_distance 0x2
s_add_i32 s13, s13, 8
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s13, s10
s_cbranch_scc0 .LBB0_2
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13matrixMulCUDAPfS_S_i
.amdhsa_group_segment_fixed_size 20480
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 19
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13matrixMulCUDAPfS_S_i, .Lfunc_end0-_Z13matrixMulCUDAPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 20480
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13matrixMulCUDAPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 21
.sgpr_spill_count: 0
.symbol: _Z13matrixMulCUDAPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // NAME: Jose Torres
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <assert.h>
__global__ void matrixMulCUDA(float *A, float *B, float *C, int size){
// Code from HW slide
__shared__ float smem_c[64][64];
__shared__ float smem_a[64][8];
__shared__ float smem_b[8][64];
int c = blockIdx.x * 64;
int r = blockIdx.y * 64;
for(int kk = 0; kk < size; kk += 8){
for(int i = threadIdx.x + blockDim.x * threadIdx.y;
i < 64 * 8;
i += blockDim.x * blockDim.y){
// load into shared memory
int k = kk + i / 64;
int rt = r + i % 64;
int ct = c + i % 64;
smem_a[i%64][i/64] = A[rt*size+k];
smem_b[i/64][i%64] = B[k*size+ct];
}
__syncthreads();
for(int i=0; i < 2; ++i){
for(int j=0; j < 2; ++j){
int rowIdx = threadIdx.y * 2 + j;
int colIdx = threadIdx.x * 2 + i;
for(int k=0; k < 8; ++k){
// Store / Compute results in shared C
smem_c[rowIdx][colIdx] += smem_a[rowIdx][k] * smem_b[k][colIdx];
}
// Store back into global memory
C[(r+rowIdx) * size + (c+colIdx)] = smem_c[rowIdx][colIdx];
}
}
}
}
int main() {
const int N = 8192;
// Declare host memory for Matrices A and B
float *hostA, *hostB, *hostC, *hostSumTemp;
// Declare device memory
float *deviceA, *deviceB, *deviceC;
// Allocate host memory for all Matrices
size_t memSize = sizeof(float) * N * N;
hostA = (float*) malloc(memSize);
hostB = (float*) malloc(memSize);
hostC = (float*) malloc(memSize);
hostSumTemp = (float*) malloc(memSize);
// init host memory
// A = 2, 2, 2, 2 . . .
// B = 3, 3, 3, 3 . . .
// C = 0, 0, 0, 0 . . .
// hostSumTemp = 6, 6, 6, 6, ...
// hostSumTemp is just temp variable to compare to
// values are chosen to be really easy
for(int i=0; i < N; ++i){
for(int j=0; j < N; ++j){
hostA[i*N+j] = 2;
hostB[i*N+j] = 3;
hostC[i*N+j] = 0;
hostSumTemp[i*N+j] = 6;
}
}
// Allocate device memory
hipMalloc((void**) &deviceA, memSize);
hipMalloc((void**) &deviceB, memSize);
hipMalloc((void**) &deviceC, memSize);
// Copy Matrix A and B from host to device
hipMemcpy(deviceA, hostA, memSize, hipMemcpyHostToDevice);
hipMemcpy(deviceB, hostB, memSize, hipMemcpyHostToDevice);
// Invoke Kernel
dim3 nblocks(N / 64, N / 64);
dim3 nthreads(32, 32);
// Init Kernel
matrixMulCUDA<<<nblocks, nthreads>>> (deviceA, deviceB, deviceC, N);
// Transfer from result matrix from device to host
hipMemcpy(hostC, deviceC, memSize, hipMemcpyDeviceToHost);
// Check results
bool isSame = true;
int row, col;
for(row=0; row < N; ++row){
for(col=0; col < N; ++col){
if(hostC[row*N+col] != hostSumTemp[row*N+col]){
isSame = false;
break;
}
}
}
// Print comparasion
if(!isSame){
std::cout << "Did not match at \n\trow = " << row << "\n\tcol = " << col << std::endl;
} else {
std::cout << "Results matched.\n";
}
// free memory
free(hostA);
free(hostB);
free(hostC);
free(hostSumTemp);
hipFree(deviceA);
hipFree(deviceB);
hipFree(deviceC);
return 0;
} | .text
.file "matrixMul.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__matrixMulCUDAPfS_S_i # -- Begin function _Z28__device_stub__matrixMulCUDAPfS_S_i
.p2align 4, 0x90
.type _Z28__device_stub__matrixMulCUDAPfS_S_i,@function
_Z28__device_stub__matrixMulCUDAPfS_S_i: # @_Z28__device_stub__matrixMulCUDAPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13matrixMulCUDAPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__matrixMulCUDAPfS_S_i, .Lfunc_end0-_Z28__device_stub__matrixMulCUDAPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $268435456, %edi # imm = 0x10000000
callq malloc
movq %rax, %rbx
movl $268435456, %edi # imm = 0x10000000
callq malloc
movq %rax, %r14
movl $268435456, %edi # imm = 0x10000000
callq malloc
movq %rax, %r15
movl $268435456, %edi # imm = 0x10000000
callq malloc
movq %rax, %r12
xorl %r13d, %r13d
movl $268435456, %edx # imm = 0x10000000
movq %r15, %rdi
xorl %esi, %esi
callq memset@PLT
movq %rbx, %rax
movq %r14, %rcx
movq %r12, %rdx
.p2align 4, 0x90
.LBB1_1: # %.preheader60
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl $1073741824, (%rax,%rsi,4) # imm = 0x40000000
movl $1077936128, (%rcx,%rsi,4) # imm = 0x40400000
movl $1086324736, (%rdx,%rsi,4) # imm = 0x40C00000
incq %rsi
cmpq $8192, %rsi # imm = 0x2000
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %r13
addq $32768, %rdx # imm = 0x8000
addq $32768, %rcx # imm = 0x8000
addq $32768, %rax # imm = 0x8000
cmpq $8192, %r13 # imm = 0x2000
jne .LBB1_1
# %bb.4:
leaq 24(%rsp), %rdi
movl $268435456, %esi # imm = 0x10000000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $268435456, %esi # imm = 0x10000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $268435456, %esi # imm = 0x10000000
callq hipMalloc
movq 24(%rsp), %rdi
movl $268435456, %edx # imm = 0x10000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $268435456, %edx # imm = 0x10000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $549755814016, %rdi # imm = 0x8000000080
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $8192, 36(%rsp) # imm = 0x2000
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z13matrixMulCUDAPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 8(%rsp), %rsi
movl $268435456, %edx # imm = 0x10000000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movb $1, %al
xorl %ecx, %ecx
movq %r15, %rdx
movq %r12, %rsi
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_11: # %.split.loop.exit
# in Loop: Header=BB1_7 Depth=1
xorl %eax, %eax
.LBB1_12: # %.split.loop.exit76
# in Loop: Header=BB1_7 Depth=1
incq %rcx
addq $32768, %rsi # imm = 0x8000
addq $32768, %rdx # imm = 0x8000
cmpq $8192, %rcx # imm = 0x2000
je .LBB1_13
.LBB1_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdx,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss (%rsi,%r13,4), %xmm0
jne .LBB1_11
jp .LBB1_11
# %bb.9: # in Loop: Header=BB1_8 Depth=2
incq %r13
cmpq $8192, %r13 # imm = 0x2000
jne .LBB1_8
# %bb.10: # in Loop: Header=BB1_7 Depth=1
movl $8192, %r13d # imm = 0x2000
jmp .LBB1_12
.LBB1_13:
movl $_ZSt4cout, %edi
testb $1, %al
jne .LBB1_19
# %bb.14:
movl $.L.str, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $8192, %esi # imm = 0x2000
callq _ZNSolsEi
movq %rax, %rbp
movl $.L.str.1, %esi
movl $8, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbp, %rdi
movl %r13d, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r13
testq %r13, %r13
je .LBB1_21
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r13)
je .LBB1_17
# %bb.16:
movzbl 67(%r13), %ecx
jmp .LBB1_18
.LBB1_19:
movl $.L.str.2, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_20
.LBB1_17:
movq %r13, %rdi
movq %rax, %rbp
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbp, %rax
.LBB1_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_20:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_21:
.cfi_def_cfa_offset 208
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13matrixMulCUDAPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13matrixMulCUDAPfS_S_i,@object # @_Z13matrixMulCUDAPfS_S_i
.section .rodata,"a",@progbits
.globl _Z13matrixMulCUDAPfS_S_i
.p2align 3, 0x0
_Z13matrixMulCUDAPfS_S_i:
.quad _Z28__device_stub__matrixMulCUDAPfS_S_i
.size _Z13matrixMulCUDAPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Did not match at \n\trow = "
.size .L.str, 26
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n\tcol = "
.size .L.str.1, 9
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Results matched.\n"
.size .L.str.2, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13matrixMulCUDAPfS_S_i"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__matrixMulCUDAPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13matrixMulCUDAPfS_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13matrixMulCUDAPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fc80000000f00 */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2UR UR5, SR_CTAID.Y ; /* 0x00000000000579c3 */
/* 0x000e220000002600 */
/*0050*/ S2R R24, SR_TID.Y ; /* 0x0000000000187919 */
/* 0x000e620000002200 */
/*0060*/ MOV R25, RZ ; /* 0x000000ff00197202 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0080*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000ea60000002100 */
/*0090*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000ee20000002500 */
/*00a0*/ USHF.L.U32 UR5, UR5, 0x6, URZ ; /* 0x0000000605057899 */
/* 0x001fe2000800063f */
/*00b0*/ SHF.L.U32 R23, R0, 0x3, RZ ; /* 0x0000000300177819 */
/* 0x004fe200000006ff */
/*00c0*/ IMAD R22, R24, c[0x0][0x0], R0 ; /* 0x0000000018167a24 */
/* 0x002fc800078e0200 */
/*00d0*/ LEA R3, R24.reuse, UR5, 0x1 ; /* 0x0000000518037c11 */
/* 0x040fe2000f8e08ff */
/*00e0*/ USHF.L.U32 UR4, UR4, 0x6, URZ ; /* 0x0000000604047899 */
/* 0x008fe2000800063f */
/*00f0*/ LEA R23, R24.reuse, R23, 0x9 ; /* 0x0000001718177211 */
/* 0x040fe400078e48ff */
/*0100*/ IADD3 R5, R3, 0x1, RZ ; /* 0x0000000103057810 */
/* 0x000fe40007ffe0ff */
/*0110*/ LEA R24, R24, 0x4000, 0x6 ; /* 0x0000400018187811 */
/* 0x000fe400078e30ff */
/*0120*/ LEA R2, R0, UR4, 0x1 ; /* 0x0000000400027c11 */
/* 0x000fca000f8e08ff */
/*0130*/ IMAD R20, R3, c[0x0][0x178], R2.reuse ; /* 0x00005e0003147a24 */
/* 0x100fe200078e0202 */
/*0140*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0150*/ IMAD R2, R5, c[0x0][0x178], R2 ; /* 0x00005e0005027a24 */
/* 0x000fd200078e0202 */
/*0160*/ IMAD.WIDE R20, R20, R3, c[0x0][0x170] ; /* 0x00005c0014147625 */
/* 0x000fc800078e0203 */
/*0170*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fc800078e0203 */
/*0180*/ ISETP.GT.AND P0, PT, R22, 0x1ff, PT ; /* 0x000001ff1600780c */
/* 0x000fe20003f04270 */
/*0190*/ BSSY B0, 0x360 ; /* 0x000001c000007945 */
/* 0x000fd80003800000 */
/*01a0*/ @P0 BRA 0x350 ; /* 0x000001a000000947 */
/* 0x001fea0003800000 */
/*01b0*/ MOV R8, R22 ; /* 0x0000001600087202 */
/* 0x000fc80000000f00 */
/*01c0*/ SHF.R.S32.HI R5, RZ, 0x1f, R8 ; /* 0x0000001fff057819 */
/* 0x000fe20000011408 */
/*01d0*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x001fc600000001ff */
/*01e0*/ LEA.HI R5, R5, R8, RZ, 0x6 ; /* 0x0000000805057211 */
/* 0x000fc800078f30ff */
/*01f0*/ LOP3.LUT R7, R5, 0xffffffc0, RZ, 0xc0, !PT ; /* 0xffffffc005077812 */
/* 0x000fe400078ec0ff */
/*0200*/ SHF.R.S32.HI R10, RZ, 0x6, R5 ; /* 0x00000006ff0a7819 */
/* 0x000fe40000011405 */
/*0210*/ IADD3 R9, -R7, R8, RZ ; /* 0x0000000807097210 */
/* 0x000fe40007ffe1ff */
/*0220*/ IADD3 R4, R10, R25, RZ ; /* 0x000000190a047210 */
/* 0x000fe40007ffe0ff */
/*0230*/ IADD3 R5, R9.reuse, UR5, RZ ; /* 0x0000000509057c10 */
/* 0x040fe4000fffe0ff */
/*0240*/ IADD3 R7, R9, UR4, RZ ; /* 0x0000000409077c10 */
/* 0x000fc6000fffe0ff */
/*0250*/ IMAD R5, R5, c[0x0][0x178], R4 ; /* 0x00005e0005057a24 */
/* 0x000fe400078e0204 */
/*0260*/ IMAD R7, R4, c[0x0][0x178], R7 ; /* 0x00005e0004077a24 */
/* 0x000fe400078e0207 */
/*0270*/ IMAD.WIDE R4, R5, R6, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fc800078e0206 */
/*0280*/ IMAD.WIDE R6, R7, R6, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x000fe400078e0206 */
/*0290*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea8000c1e1900 */
/*02a0*/ LDG.E R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ee2000c1e1900 */
/*02b0*/ LEA R11, R9, 0x4000, 0x5 ; /* 0x00004000090b7811 */
/* 0x000fe400078e28ff */
/*02c0*/ LEA R12, R10.reuse, 0x4800, 0x8 ; /* 0x000048000a0c7811 */
/* 0x040fe400078e40ff */
/*02d0*/ LEA R11, R10, R11, 0x2 ; /* 0x0000000b0a0b7211 */
/* 0x000fc400078e10ff */
/*02e0*/ LEA R9, R9, R12, 0x2 ; /* 0x0000000c09097211 */
/* 0x000fe400078e10ff */
/*02f0*/ MOV R13, c[0x0][0x0] ; /* 0x00000000000d7a02 */
/* 0x000fca0000000f00 */
/*0300*/ IMAD R8, R13, c[0x0][0x4], R8 ; /* 0x000001000d087a24 */
/* 0x000fca00078e0208 */
/*0310*/ ISETP.GE.AND P0, PT, R8, 0x200, PT ; /* 0x000002000800780c */
/* 0x000fe20003f06270 */
/*0320*/ STS [R11], R4 ; /* 0x000000040b007388 */
/* 0x0041e80000000800 */
/*0330*/ STS [R9], R6 ; /* 0x0000000609007388 */
/* 0x0081f00000000800 */
/*0340*/ @!P0 BRA 0x1c0 ; /* 0xfffffe7000008947 */
/* 0x000fea000383ffff */
/*0350*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0360*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0370*/ IADD3 R25, R25, 0x8, RZ ; /* 0x0000000819197810 */
/* 0x000fc80007ffe0ff */
/*0380*/ ISETP.GE.AND P0, PT, R25, c[0x0][0x178], PT ; /* 0x00005e0019007a0c */
/* 0x000fe20003f06270 */
/*0390*/ LDS R17, [R0.X8+0x4800] ; /* 0x0048000000117984 */
/* 0x000fe80000008800 */
/*03a0*/ LDS R12, [R23] ; /* 0x00000000170c7984 */
/* 0x000fe80000000800 */
/*03b0*/ LDS.128 R4, [R24] ; /* 0x0000000018047984 */
/* 0x001e280000000c00 */
/*03c0*/ LDS R34, [R0.X8+0x4900] ; /* 0x0049000000227984 */
/* 0x000e680000008800 */
/*03d0*/ LDS R29, [R0.X8+0x4a00] ; /* 0x004a0000001d7984 */
/* 0x000ea80000008800 */
/*03e0*/ LDS R30, [R0.X8+0x4b00] ; /* 0x004b0000001e7984 */
/* 0x000ee80000008800 */
/*03f0*/ LDS R31, [R0.X8+0x4c00] ; /* 0x004c0000001f7984 */
/* 0x000fe80000008800 */
/*0400*/ LDS.128 R8, [R24+0x10] ; /* 0x0000100018087984 */
/* 0x000f280000000c00 */
/*0410*/ LDS R32, [R0.X8+0x4d00] ; /* 0x004d000000207984 */
/* 0x000f680000008800 */
/*0420*/ LDS R27, [R0.X8+0x4e00] ; /* 0x004e0000001b7984 */
/* 0x000f680000008800 */
/*0430*/ LDS R28, [R0.X8+0x4f00] ; /* 0x004f0000001c7984 */
/* 0x000f680000008800 */
/*0440*/ LDS R16, [R23+0x100] ; /* 0x0001000017107984 */
/* 0x000fe20000000800 */
/*0450*/ FFMA R12, R17, R4, R12 ; /* 0x00000004110c7223 */
/* 0x001fc8000000000c */
/*0460*/ FFMA R12, R34, R5, R12 ; /* 0x00000005220c7223 */
/* 0x002fc8000000000c */
/*0470*/ FFMA R12, R29, R6, R12 ; /* 0x000000061d0c7223 */
/* 0x004fc8000000000c */
/*0480*/ FFMA R12, R30, R7, R12 ; /* 0x000000071e0c7223 */
/* 0x008fc8000000000c */
/*0490*/ FFMA R12, R31, R8, R12 ; /* 0x000000081f0c7223 */
/* 0x010fc8000000000c */
/*04a0*/ FFMA R12, R32, R9, R12 ; /* 0x00000009200c7223 */
/* 0x020fc8000000000c */
/*04b0*/ FFMA R12, R27, R10, R12 ; /* 0x0000000a1b0c7223 */
/* 0x000fc8000000000c */
/*04c0*/ FFMA R26, R28, R11, R12 ; /* 0x0000000b1c1a7223 */
/* 0x000fca000000000c */
/*04d0*/ STS [R23], R26 ; /* 0x0000001a17007388 */
/* 0x000fe80000000800 */
/*04e0*/ LDS.128 R12, [R24+0x20] ; /* 0x00002000180c7984 */
/* 0x000e280000000c00 */
/*04f0*/ STG.E [R20.64], R26 ; /* 0x0000001a14007986 */
/* 0x000fe2000c101906 */
/*0500*/ FFMA R33, R17, R12, R16 ; /* 0x0000000c11217223 */
/* 0x001fc60000000010 */
/*0510*/ LDS.128 R16, [R24+0x30] ; /* 0x0000300018107984 */
/* 0x000e220000000c00 */
/*0520*/ FFMA R33, R34, R13, R33 ; /* 0x0000000d22217223 */
/* 0x000fc80000000021 */
/*0530*/ FFMA R33, R29, R14, R33 ; /* 0x0000000e1d217223 */
/* 0x000fc80000000021 */
/*0540*/ FFMA R33, R30, R15, R33 ; /* 0x0000000f1e217223 */
/* 0x000fc80000000021 */
/*0550*/ FFMA R33, R31, R16, R33 ; /* 0x000000101f217223 */
/* 0x001fc80000000021 */
/*0560*/ FFMA R33, R32, R17, R33 ; /* 0x0000001120217223 */
/* 0x000fc80000000021 */
/*0570*/ FFMA R33, R27, R18, R33 ; /* 0x000000121b217223 */
/* 0x000fe40000000021 */
/*0580*/ LDS R27, [R23+0x104] ; /* 0x00010400171b7984 */
/* 0x000fe40000000800 */
/*0590*/ FFMA R28, R28, R19, R33 ; /* 0x000000131c1c7223 */
/* 0x000fe40000000021 */
/*05a0*/ LDS R33, [R23+0x4] ; /* 0x0000040017217984 */
/* 0x000fe80000000800 */
/*05b0*/ STS [R23+0x100], R28 ; /* 0x0001001c17007388 */
/* 0x000fe80000000800 */
/*05c0*/ LDS R29, [R0.X8+0x4804] ; /* 0x00480400001d7984 */
/* 0x000e280000008800 */
/*05d0*/ LDS R32, [R0.X8+0x4904] ; /* 0x0049040000207984 */
/* 0x000e680000008800 */
/*05e0*/ LDS R31, [R0.X8+0x4a04] ; /* 0x004a0400001f7984 */
/* 0x000ea80000008800 */
/*05f0*/ LDS R30, [R0.X8+0x4b04] ; /* 0x004b0400001e7984 */
/* 0x000ee80000008800 */
/*0600*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101906 */
/*0610*/ FFMA R4, R4, R29, R33 ; /* 0x0000001d04047223 */
/* 0x001fc60000000021 */
/*0620*/ LDS R33, [R0.X8+0x4c04] ; /* 0x004c040000217984 */
/* 0x000e220000008800 */
/*0630*/ FFMA R27, R12, R29, R27 ; /* 0x0000001d0c1b7223 */
/* 0x000fe4000000001b */
/*0640*/ FFMA R5, R32.reuse, R5, R4 ; /* 0x0000000520057223 */
/* 0x042fe40000000004 */
/*0650*/ LDS R4, [R0.X8+0x4d04] ; /* 0x004d040000047984 */
/* 0x000e620000008800 */
/*0660*/ FFMA R27, R32, R13, R27 ; /* 0x0000000d201b7223 */
/* 0x000fe4000000001b */
/*0670*/ FFMA R34, R31.reuse, R6, R5 ; /* 0x000000061f227223 */
/* 0x044fe40000000005 */
/*0680*/ LDS R5, [R0.X8+0x4e04] ; /* 0x004e040000057984 */
/* 0x000ea20000008800 */
/*0690*/ FFMA R27, R31, R14, R27 ; /* 0x0000000e1f1b7223 */
/* 0x000fc4000000001b */
/*06a0*/ FFMA R34, R30.reuse, R7, R34 ; /* 0x000000071e227223 */
/* 0x048fe20000000022 */
/*06b0*/ LDS R6, [R0.X8+0x4f04] ; /* 0x004f040000067984 */
/* 0x000ee20000008800 */
/*06c0*/ FFMA R27, R30, R15, R27 ; /* 0x0000000f1e1b7223 */
/* 0x000fe4000000001b */
/*06d0*/ FFMA R34, R8, R33.reuse, R34 ; /* 0x0000002108227223 */
/* 0x081fe40000000022 */
/*06e0*/ FFMA R27, R16, R33, R27 ; /* 0x00000021101b7223 */
/* 0x000fe4000000001b */
/*06f0*/ FFMA R34, R4.reuse, R9, R34 ; /* 0x0000000904227223 */
/* 0x042fe40000000022 */
/*0700*/ FFMA R27, R4, R17, R27 ; /* 0x00000011041b7223 */
/* 0x000fc4000000001b */
/*0710*/ FFMA R34, R5.reuse, R10, R34 ; /* 0x0000000a05227223 */
/* 0x044fe40000000022 */
/*0720*/ FFMA R27, R5, R18, R27 ; /* 0x00000012051b7223 */
/* 0x000fe4000000001b */
/*0730*/ FFMA R34, R6.reuse, R11, R34 ; /* 0x0000000b06227223 */
/* 0x048fe40000000022 */
/*0740*/ FFMA R27, R6, R19, R27 ; /* 0x00000013061b7223 */
/* 0x000fc6000000001b */
/*0750*/ STG.E [R20.64+0x4], R34 ; /* 0x0000042214007986 */
/* 0x0001e8000c101906 */
/*0760*/ STS [R23+0x4], R34 ; /* 0x0000042217007388 */
/* 0x0001e80000000800 */
/*0770*/ STS [R23+0x104], R27 ; /* 0x0001041b17007388 */
/* 0x0001e80000000800 */
/*0780*/ STG.E [R2.64+0x4], R27 ; /* 0x0000041b02007986 */
/* 0x0001e2000c101906 */
/*0790*/ @!P0 BRA 0x180 ; /* 0xfffff9e000008947 */
/* 0x000fea000383ffff */
/*07a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07b0*/ BRA 0x7b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13matrixMulCUDAPfS_S_i
.globl _Z13matrixMulCUDAPfS_S_i
.p2align 8
.type _Z13matrixMulCUDAPfS_S_i,@function
_Z13matrixMulCUDAPfS_S_i:
s_load_b32 s10, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s10, 1
s_cbranch_scc1 .LBB0_12
s_clause 0x2
s_load_b32 s13, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_and_b32_e32 v5, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_lshl_b32 s11, s14, 6
s_lshl_b32 s12, s15, 6
s_add_u32 s8, s0, 32
s_addc_u32 s9, s1, 0
v_lshlrev_b32_e32 v2, 1, v0
v_lshlrev_b32_e32 v3, 1, v5
v_lshl_add_u32 v4, v0, 6, 0x4000
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s13, 0xffff
s_mov_b32 s13, 0
v_mad_u32_u24 v1, v0, s1, v5
v_lshl_add_u32 v5, v5, 3, 0x4800
s_delay_alu instid0(VALU_DEP_2)
v_cmp_gt_u32_e32 vcc_lo, 0x200, v1
.LBB0_2:
s_and_saveexec_b32 s14, vcc_lo
s_cbranch_execz .LBB0_5
s_load_b32 s0, s[8:9], 0xc
v_lshl_add_u32 v0, v1, 5, 0x4000
v_lshl_add_u32 v6, v1, 2, 0x4800
v_mov_b32_e32 v7, v1
s_mov_b32 s18, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s15, s0, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s1
s_lshl_b32 s16, s15, 5
s_lshl_b32 s17, s15, 2
.LBB0_4:
v_ashrrev_i32_e32 v8, 31, v7
v_add_nc_u32_e32 v9, s11, v7
v_add_nc_u32_e32 v10, s12, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v8, 26, v8
v_add_nc_u32_e32 v8, v7, v8
v_add_nc_u32_e32 v7, s15, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v14, 6, v8
v_and_b32_e32 v11, 0xffffffc0, v8
v_add_nc_u32_e32 v8, s13, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v9, v9, v11
v_sub_nc_u32_e32 v15, v10, v11
v_mad_u64_u32 v[10:11], null, s10, v8, v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[12:13], null, v15, s10, v[8:9]
v_ashrrev_i32_e32 v11, 31, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[8:9], 2, v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[10:11], 2, v[12:13]
v_add_co_u32 v8, s0, s6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v9, s0, s7, v9, s0
v_add_co_u32 v10, s0, s4, v10
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v11, s0, s5, v11, s0
global_load_b32 v12, v[8:9], off
global_load_b32 v10, v[10:11], off
v_mad_u64_u32 v[8:9], null, v14, 0xfffff804, v[0:1]
v_cmp_lt_i32_e64 s0, 0x1ff, v7
v_add_nc_u32_e32 v0, s16, v0
s_delay_alu instid0(VALU_DEP_2)
s_or_b32 s18, s0, s18
s_waitcnt vmcnt(1)
ds_store_b32 v6, v12
v_add_nc_u32_e32 v6, s17, v6
s_waitcnt vmcnt(0)
ds_store_b32 v8, v10
s_and_not1_b32 exec_lo, exec_lo, s18
s_cbranch_execnz .LBB0_4
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s14
v_mov_b32_e32 v6, v5
s_mov_b32 s14, 0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_6:
v_dual_mov_b32 v8, v4 :: v_dual_add_nc_u32 v7, s14, v3
s_mov_b32 s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v0, s11, v7
v_lshlrev_b32_e32 v7, 2, v7
.p2align 6
.LBB0_7:
v_dual_mov_b32 v12, v6 :: v_dual_add_nc_u32 v11, s15, v2
s_mov_b32 s0, 0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v10, v11, 8, v7
ds_load_b32 v9, v10
.LBB0_8:
v_add_nc_u32_e32 v13, s0, v8
s_add_i32 s0, s0, 4
ds_load_b32 v14, v12
ds_load_b32 v13, v13
v_add_nc_u32_e32 v12, 0x100, v12
s_cmp_eq_u32 s0, 32
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v9, v13, v14
s_cbranch_scc0 .LBB0_8
v_add_nc_u32_e32 v13, s12, v11
ds_store_b32 v10, v9
v_add_nc_u32_e32 v8, 32, v8
v_mad_u64_u32 v[11:12], null, v13, s10, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v10, s0, s2, v11
v_add_co_ci_u32_e64 v11, s0, s3, v12, s0
s_add_i32 s0, s15, 1
s_cmp_lg_u32 s15, 0
s_mov_b32 s15, s0
global_store_b32 v[10:11], v9, off
s_cbranch_scc0 .LBB0_7
v_add_nc_u32_e32 v6, 4, v6
s_add_i32 s0, s14, 1
s_cmp_lg_u32 s14, 0
s_mov_b32 s14, s0
s_cbranch_scc0 .LBB0_6
s_set_inst_prefetch_distance 0x2
s_add_i32 s13, s13, 8
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s13, s10
s_cbranch_scc0 .LBB0_2
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13matrixMulCUDAPfS_S_i
.amdhsa_group_segment_fixed_size 20480
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 19
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13matrixMulCUDAPfS_S_i, .Lfunc_end0-_Z13matrixMulCUDAPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 20480
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13matrixMulCUDAPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 21
.sgpr_spill_count: 0
.symbol: _Z13matrixMulCUDAPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011b3da_00000000-6_matrixMul.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z13matrixMulCUDAPfS_S_iPfS_S_i
.type _Z38__device_stub__Z13matrixMulCUDAPfS_S_iPfS_S_i, @function
_Z38__device_stub__Z13matrixMulCUDAPfS_S_iPfS_S_i:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13matrixMulCUDAPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z38__device_stub__Z13matrixMulCUDAPfS_S_iPfS_S_i, .-_Z38__device_stub__Z13matrixMulCUDAPfS_S_iPfS_S_i
.globl _Z13matrixMulCUDAPfS_S_i
.type _Z13matrixMulCUDAPfS_S_i, @function
_Z13matrixMulCUDAPfS_S_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13matrixMulCUDAPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z13matrixMulCUDAPfS_S_i, .-_Z13matrixMulCUDAPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "Did not match at \n\trow = "
.LC5:
.string "\n\tcol = "
.LC6:
.string "Results matched.\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $268435456, %edi
call malloc@PLT
movq %rax, %r13
movl $268435456, %edi
call malloc@PLT
movq %rax, %r12
movl $268435456, %edi
call malloc@PLT
movq %rax, %rbx
movl $268435456, %edi
call malloc@PLT
movq %rax, %rbp
movl $32768, %edx
movss .LC0(%rip), %xmm2
movss .LC1(%rip), %xmm1
movss .LC3(%rip), %xmm0
.L12:
leaq -32768(%rdx), %rax
.L13:
movss %xmm2, 0(%r13,%rax)
movss %xmm1, (%r12,%rax)
movl $0x00000000, (%rbx,%rax)
movss %xmm0, 0(%rbp,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L13
addq $32768, %rdx
cmpq $268468224, %rdx
jne .L12
leaq 8(%rsp), %rdi
movl $268435456, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $268435456, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $268435456, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $268435456, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $268435456, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 32(%rsp)
movl $128, 36(%rsp)
movl $32, 44(%rsp)
movl $32, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L15:
movl $2, %ecx
movl $268435456, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $0, %edx
movl $1, %ecx
movl $0, %esi
jmp .L16
.L29:
movl $8192, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z38__device_stub__Z13matrixMulCUDAPfS_S_iPfS_S_i
jmp .L15
.L24:
movl %esi, %ecx
.L17:
addq $32768, %rdx
cmpq $268435456, %rdx
je .L20
.L16:
movq %rdx, %rax
movl $0, %r14d
.L19:
movss (%rbx,%rax), %xmm0
ucomiss 0(%rbp,%rax), %xmm0
jp .L24
jne .L24
addl $1, %r14d
addq $4, %rax
cmpl $8192, %r14d
jne .L19
jmp .L17
.L20:
testb %cl, %cl
jne .L21
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $8192, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r14d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L22:
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L22
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z13matrixMulCUDAPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z13matrixMulCUDAPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1073741824
.align 4
.LC1:
.long 1077936128
.align 4
.LC3:
.long 1086324736
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixMul.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__matrixMulCUDAPfS_S_i # -- Begin function _Z28__device_stub__matrixMulCUDAPfS_S_i
.p2align 4, 0x90
.type _Z28__device_stub__matrixMulCUDAPfS_S_i,@function
_Z28__device_stub__matrixMulCUDAPfS_S_i: # @_Z28__device_stub__matrixMulCUDAPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13matrixMulCUDAPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__matrixMulCUDAPfS_S_i, .Lfunc_end0-_Z28__device_stub__matrixMulCUDAPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $268435456, %edi # imm = 0x10000000
callq malloc
movq %rax, %rbx
movl $268435456, %edi # imm = 0x10000000
callq malloc
movq %rax, %r14
movl $268435456, %edi # imm = 0x10000000
callq malloc
movq %rax, %r15
movl $268435456, %edi # imm = 0x10000000
callq malloc
movq %rax, %r12
xorl %r13d, %r13d
movl $268435456, %edx # imm = 0x10000000
movq %r15, %rdi
xorl %esi, %esi
callq memset@PLT
movq %rbx, %rax
movq %r14, %rcx
movq %r12, %rdx
.p2align 4, 0x90
.LBB1_1: # %.preheader60
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl $1073741824, (%rax,%rsi,4) # imm = 0x40000000
movl $1077936128, (%rcx,%rsi,4) # imm = 0x40400000
movl $1086324736, (%rdx,%rsi,4) # imm = 0x40C00000
incq %rsi
cmpq $8192, %rsi # imm = 0x2000
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %r13
addq $32768, %rdx # imm = 0x8000
addq $32768, %rcx # imm = 0x8000
addq $32768, %rax # imm = 0x8000
cmpq $8192, %r13 # imm = 0x2000
jne .LBB1_1
# %bb.4:
leaq 24(%rsp), %rdi
movl $268435456, %esi # imm = 0x10000000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $268435456, %esi # imm = 0x10000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $268435456, %esi # imm = 0x10000000
callq hipMalloc
movq 24(%rsp), %rdi
movl $268435456, %edx # imm = 0x10000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $268435456, %edx # imm = 0x10000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $549755814016, %rdi # imm = 0x8000000080
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $8192, 36(%rsp) # imm = 0x2000
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z13matrixMulCUDAPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 8(%rsp), %rsi
movl $268435456, %edx # imm = 0x10000000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movb $1, %al
xorl %ecx, %ecx
movq %r15, %rdx
movq %r12, %rsi
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_11: # %.split.loop.exit
# in Loop: Header=BB1_7 Depth=1
xorl %eax, %eax
.LBB1_12: # %.split.loop.exit76
# in Loop: Header=BB1_7 Depth=1
incq %rcx
addq $32768, %rsi # imm = 0x8000
addq $32768, %rdx # imm = 0x8000
cmpq $8192, %rcx # imm = 0x2000
je .LBB1_13
.LBB1_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdx,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss (%rsi,%r13,4), %xmm0
jne .LBB1_11
jp .LBB1_11
# %bb.9: # in Loop: Header=BB1_8 Depth=2
incq %r13
cmpq $8192, %r13 # imm = 0x2000
jne .LBB1_8
# %bb.10: # in Loop: Header=BB1_7 Depth=1
movl $8192, %r13d # imm = 0x2000
jmp .LBB1_12
.LBB1_13:
movl $_ZSt4cout, %edi
testb $1, %al
jne .LBB1_19
# %bb.14:
movl $.L.str, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $8192, %esi # imm = 0x2000
callq _ZNSolsEi
movq %rax, %rbp
movl $.L.str.1, %esi
movl $8, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbp, %rdi
movl %r13d, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r13
testq %r13, %r13
je .LBB1_21
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r13)
je .LBB1_17
# %bb.16:
movzbl 67(%r13), %ecx
jmp .LBB1_18
.LBB1_19:
movl $.L.str.2, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_20
.LBB1_17:
movq %r13, %rdi
movq %rax, %rbp
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbp, %rax
.LBB1_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_20:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_21:
.cfi_def_cfa_offset 208
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13matrixMulCUDAPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13matrixMulCUDAPfS_S_i,@object # @_Z13matrixMulCUDAPfS_S_i
.section .rodata,"a",@progbits
.globl _Z13matrixMulCUDAPfS_S_i
.p2align 3, 0x0
_Z13matrixMulCUDAPfS_S_i:
.quad _Z28__device_stub__matrixMulCUDAPfS_S_i
.size _Z13matrixMulCUDAPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Did not match at \n\trow = "
.size .L.str, 26
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n\tcol = "
.size .L.str.1, 9
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Results matched.\n"
.size .L.str.2, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13matrixMulCUDAPfS_S_i"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__matrixMulCUDAPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13matrixMulCUDAPfS_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<bits/stdc++.h>
using namespace std;
#define pi (2.0*acos(0.0))
#define eps 1e-6
#define ll long long
#define inf (1<<29)
#define vi vector<int>
#define vll vector<ll>
#define sc(x) scanf("%d",&x)
#define scl(x) scanf("%lld",&x)
#define all(v) v.begin() , v.end()
#define me(a,val) memset( a , val ,sizeof(a) )
#define pb(x) push_back(x)
#define pii pair<int,int>
#define mp(a,b) make_pair(a,b)
#define Q(x) (x) * (x)
#define L(x) ((x<<1) + 1)
#define R(x) ((x<<1) + 2)
#define M(x,y) ((x+y)>>1)
#define fi first
#define se second
#define MOD 1000000007
#define ios ios::sync_with_stdio(0)
typedef struct StructA {
int *a;
} CudaMatrix;
#define N 10
__global__ void kernel(CudaMatrix *A){
int x = threadIdx.x;
printf("--> %d\n",x);
for(int i = 0 ; i < 10 ; i++)
printf("%d - ",A->a[i]);
printf("\n");
}
int main() {
CudaMatrix *A;
int *a;
a = (int *)malloc( N * sizeof(int) );
for(int i = 0 ; i < N ; i++)
a[i] = i;
int *a2;
cudaMalloc( &a2 , N * sizeof(int) );
cudaMemcpy( a2 , a , N * sizeof(int) , cudaMemcpyHostToDevice );
int sz = sizeof(CudaMatrix);
cudaMalloc( &A , sz );
cudaMemcpy( &(A->a) , &a2 , sizeof(int *) , cudaMemcpyHostToDevice );
kernel<<<1,1>>>( A );
cudaFree( A );
} | code for sm_80
Function : _Z6kernelP7StructA
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R19, 0x0 ; /* 0x0000000000137802 */
/* 0x000fe20000000f00 */
/*0050*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0060*/ IADD3 R18, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001127a10 */
/* 0x000fe20007f1e0ff */
/*0070*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fe20000000a00 */
/*0080*/ LDC.64 R8, c[0x4][R19] ; /* 0x0100000013087b82 */
/* 0x0002a60000000a00 */
/*0090*/ IMAD.X R2, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff027624 */
/* 0x000fc400000e06ff */
/*00a0*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0012 */
/*00b0*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*00c0*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0013e80000100800 */
/*00d0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x000fe40000000000 */
/*00e0*/ MOV R3, 0x150 ; /* 0x0000015000037802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R20, 0xd0 ; /* 0x000000d000147802 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x002fe40000000f00 */
/*0120*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0130*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0140*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x004fea0003c00000 */
/*0150*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff107624 */
/* 0x000fe400078e00ff */
/*0160*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff117624 */
/* 0x000fca00078e00ff */
/*0170*/ LDG.E.64 R10, [R16.64] ; /* 0x00000024100a7981 */
/* 0x000ea8000c1e1b00 */
/*0180*/ LD.E R10, [R10.64] ; /* 0x000000240a0a7980 */
/* 0x004ea2000c101900 */
/*0190*/ LDC.64 R8, c[0x4][R19] ; /* 0x0100000013087b82 */
/* 0x0000620000000a00 */
/*01a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe400078e00ff */
/*01b0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe400078e00ff */
/*01c0*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fc400078e0012 */
/*01d0*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*01e0*/ STL [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0041e80000100800 */
/*01f0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x003fe40000000000 */
/*0200*/ MOV R3, 0x270 ; /* 0x0000027000037802 */
/* 0x000fe40000000f00 */
/*0210*/ MOV R20, 0x1f0 ; /* 0x000001f000147802 */
/* 0x000fe40000000f00 */
/*0220*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0230*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0240*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0250*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0260*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0270*/ LDG.E.64 R10, [R16.64] ; /* 0x00000024100a7981 */
/* 0x000ea8000c1e1b00 */
/*0280*/ LD.E R10, [R10.64+0x4] ; /* 0x000004240a0a7980 */
/* 0x004ea2000c101900 */
/*0290*/ LDC.64 R8, c[0x4][R19] ; /* 0x0100000013087b82 */
/* 0x0000620000000a00 */
/*02a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe400078e00ff */
/*02b0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe400078e00ff */
/*02c0*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fc400078e0012 */
/*02d0*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*02e0*/ STL [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0041e80000100800 */
/*02f0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x003fe40000000000 */
/*0300*/ MOV R3, 0x370 ; /* 0x0000037000037802 */
/* 0x000fe40000000f00 */
/*0310*/ MOV R20, 0x2f0 ; /* 0x000002f000147802 */
/* 0x000fe40000000f00 */
/*0320*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0330*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0340*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0350*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0360*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0370*/ LDG.E.64 R10, [R16.64] ; /* 0x00000024100a7981 */
/* 0x000ea8000c1e1b00 */
/*0380*/ LD.E R10, [R10.64+0x8] ; /* 0x000008240a0a7980 */
/* 0x004ea2000c101900 */
/*0390*/ LDC.64 R8, c[0x4][R19] ; /* 0x0100000013087b82 */
/* 0x0000620000000a00 */
/*03a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe400078e00ff */
/*03b0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe400078e00ff */
/*03c0*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fc400078e0012 */
/*03d0*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*03e0*/ STL [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0041e80000100800 */
/*03f0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x003fe40000000000 */
/*0400*/ MOV R3, 0x470 ; /* 0x0000047000037802 */
/* 0x000fe40000000f00 */
/*0410*/ MOV R20, 0x3f0 ; /* 0x000003f000147802 */
/* 0x000fe40000000f00 */
/*0420*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0430*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0440*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0450*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0460*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0470*/ LDG.E.64 R10, [R16.64] ; /* 0x00000024100a7981 */
/* 0x000ea8000c1e1b00 */
/*0480*/ LD.E R10, [R10.64+0xc] ; /* 0x00000c240a0a7980 */
/* 0x004ea2000c101900 */
/*0490*/ LDC.64 R8, c[0x4][R19] ; /* 0x0100000013087b82 */
/* 0x0000620000000a00 */
/*04a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe400078e00ff */
/*04b0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe400078e00ff */
/*04c0*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fc400078e0012 */
/*04d0*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*04e0*/ STL [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0041e80000100800 */
/*04f0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x003fe40000000000 */
/*0500*/ MOV R3, 0x570 ; /* 0x0000057000037802 */
/* 0x000fe40000000f00 */
/*0510*/ MOV R20, 0x4f0 ; /* 0x000004f000147802 */
/* 0x000fe40000000f00 */
/*0520*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0530*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0540*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0550*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0560*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0570*/ LDG.E.64 R10, [R16.64] ; /* 0x00000024100a7981 */
/* 0x000ea8000c1e1b00 */
/*0580*/ LD.E R10, [R10.64+0x10] ; /* 0x000010240a0a7980 */
/* 0x004ea2000c101900 */
/*0590*/ LDC.64 R8, c[0x4][R19] ; /* 0x0100000013087b82 */
/* 0x0000620000000a00 */
/*05a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe400078e00ff */
/*05b0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe400078e00ff */
/*05c0*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fc400078e0012 */
/*05d0*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*05e0*/ STL [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0041e80000100800 */
/*05f0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x003fe40000000000 */
/*0600*/ MOV R3, 0x670 ; /* 0x0000067000037802 */
/* 0x000fe40000000f00 */
/*0610*/ MOV R20, 0x5f0 ; /* 0x000005f000147802 */
/* 0x000fe40000000f00 */
/*0620*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0630*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0640*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0650*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0660*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0670*/ LDG.E.64 R10, [R16.64] ; /* 0x00000024100a7981 */
/* 0x000ea8000c1e1b00 */
/*0680*/ LD.E R10, [R10.64+0x14] ; /* 0x000014240a0a7980 */
/* 0x004ea2000c101900 */
/*0690*/ LDC.64 R8, c[0x4][R19] ; /* 0x0100000013087b82 */
/* 0x0000620000000a00 */
/*06a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe400078e00ff */
/*06b0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe400078e00ff */
/*06c0*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fc400078e0012 */
/*06d0*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*06e0*/ STL [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0041e80000100800 */
/*06f0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x003fe40000000000 */
/*0700*/ MOV R3, 0x770 ; /* 0x0000077000037802 */
/* 0x000fe40000000f00 */
/*0710*/ MOV R20, 0x6f0 ; /* 0x000006f000147802 */
/* 0x000fe40000000f00 */
/*0720*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0730*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0740*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0750*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0760*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0770*/ LDG.E.64 R10, [R16.64] ; /* 0x00000024100a7981 */
/* 0x000ea8000c1e1b00 */
/*0780*/ LD.E R10, [R10.64+0x18] ; /* 0x000018240a0a7980 */
/* 0x004ea2000c101900 */
/*0790*/ LDC.64 R8, c[0x4][R19] ; /* 0x0100000013087b82 */
/* 0x0000620000000a00 */
/*07a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe400078e00ff */
/*07b0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe400078e00ff */
/*07c0*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fc400078e0012 */
/*07d0*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*07e0*/ STL [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0041e80000100800 */
/*07f0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x003fe40000000000 */
/*0800*/ MOV R3, 0x870 ; /* 0x0000087000037802 */
/* 0x000fe40000000f00 */
/*0810*/ MOV R20, 0x7f0 ; /* 0x000007f000147802 */
/* 0x000fe40000000f00 */
/*0820*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0830*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0840*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0850*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0860*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0870*/ LDG.E.64 R10, [R16.64] ; /* 0x00000024100a7981 */
/* 0x000ea8000c1e1b00 */
/*0880*/ LD.E R10, [R10.64+0x1c] ; /* 0x00001c240a0a7980 */
/* 0x004ea2000c101900 */
/*0890*/ LDC.64 R8, c[0x4][R19] ; /* 0x0100000013087b82 */
/* 0x0000620000000a00 */
/*08a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe400078e00ff */
/*08b0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe400078e00ff */
/*08c0*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fc400078e0012 */
/*08d0*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*08e0*/ STL [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0041e80000100800 */
/*08f0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x003fe40000000000 */
/*0900*/ MOV R3, 0x970 ; /* 0x0000097000037802 */
/* 0x000fe40000000f00 */
/*0910*/ MOV R20, 0x8f0 ; /* 0x000008f000147802 */
/* 0x000fe40000000f00 */
/*0920*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0930*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0940*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0950*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0960*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0970*/ LDG.E.64 R10, [R16.64] ; /* 0x00000024100a7981 */
/* 0x000ea8000c1e1b00 */
/*0980*/ LD.E R10, [R10.64+0x20] ; /* 0x000020240a0a7980 */
/* 0x004ea2000c101900 */
/*0990*/ LDC.64 R8, c[0x4][R19] ; /* 0x0100000013087b82 */
/* 0x0000620000000a00 */
/*09a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe400078e00ff */
/*09b0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe400078e00ff */
/*09c0*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fc400078e0012 */
/*09d0*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*09e0*/ STL [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0041e80000100800 */
/*09f0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x003fe40000000000 */
/*0a00*/ MOV R3, 0xa70 ; /* 0x00000a7000037802 */
/* 0x000fe40000000f00 */
/*0a10*/ MOV R20, 0x9f0 ; /* 0x000009f000147802 */
/* 0x000fe40000000f00 */
/*0a20*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0a30*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0a40*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0a50*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0a60*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0a70*/ LDG.E.64 R16, [R16.64] ; /* 0x0000002410107981 */
/* 0x000ea8000c1e1b00 */
/*0a80*/ LD.E R0, [R16.64+0x24] ; /* 0x0000242410007980 */
/* 0x004ea2000c101900 */
/*0a90*/ LDC.64 R8, c[0x4][R19] ; /* 0x0100000013087b82 */
/* 0x0000620000000a00 */
/*0aa0*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0012 */
/*0ab0*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0002 */
/*0ac0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fc400078e00ff */
/*0ad0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe200078e00ff */
/*0ae0*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0041e80000100800 */
/*0af0*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x002fe40000000000 */
/*0b00*/ MOV R11, 0xb70 ; /* 0x00000b70000b7802 */
/* 0x000fe40000000f00 */
/*0b10*/ MOV R20, 0xaf0 ; /* 0x00000af000147802 */
/* 0x000fe40000000f00 */
/*0b20*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0b30*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fe40000000f00 */
/*0b40*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*0b50*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0b60*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0b70*/ LDC.64 R2, c[0x4][R19] ; /* 0x0100000013027b82 */
/* 0x0000620000000a00 */
/*0b80*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x18] ; /* 0x01000600ff047624 */
/* 0x000fe200078e00ff */
/*0b90*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0ba0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x1c] ; /* 0x01000700ff057624 */
/* 0x000fca00078e00ff */
/*0bb0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0bc0*/ MOV R11, 0xc30 ; /* 0x00000c30000b7802 */
/* 0x000fe40000000f00 */
/*0bd0*/ MOV R20, 0xbb0 ; /* 0x00000bb000147802 */
/* 0x000fe40000000f00 */
/*0be0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0bf0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0c00*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0c10*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0c20*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x003fea0003c00000 */
/*0c30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c40*/ BRA 0xc40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<bits/stdc++.h>
using namespace std;
#define pi (2.0*acos(0.0))
#define eps 1e-6
#define ll long long
#define inf (1<<29)
#define vi vector<int>
#define vll vector<ll>
#define sc(x) scanf("%d",&x)
#define scl(x) scanf("%lld",&x)
#define all(v) v.begin() , v.end()
#define me(a,val) memset( a , val ,sizeof(a) )
#define pb(x) push_back(x)
#define pii pair<int,int>
#define mp(a,b) make_pair(a,b)
#define Q(x) (x) * (x)
#define L(x) ((x<<1) + 1)
#define R(x) ((x<<1) + 2)
#define M(x,y) ((x+y)>>1)
#define fi first
#define se second
#define MOD 1000000007
#define ios ios::sync_with_stdio(0)
typedef struct StructA {
int *a;
} CudaMatrix;
#define N 10
__global__ void kernel(CudaMatrix *A){
int x = threadIdx.x;
printf("--> %d\n",x);
for(int i = 0 ; i < 10 ; i++)
printf("%d - ",A->a[i]);
printf("\n");
}
int main() {
CudaMatrix *A;
int *a;
a = (int *)malloc( N * sizeof(int) );
for(int i = 0 ; i < N ; i++)
a[i] = i;
int *a2;
cudaMalloc( &a2 , N * sizeof(int) );
cudaMemcpy( a2 , a , N * sizeof(int) , cudaMemcpyHostToDevice );
int sz = sizeof(CudaMatrix);
cudaMalloc( &A , sz );
cudaMemcpy( &(A->a) , &a2 , sizeof(int *) , cudaMemcpyHostToDevice );
kernel<<<1,1>>>( A );
cudaFree( A );
} | .file "tmpxft_00035700_00000000-6_copy.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB10862:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10862:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z6kernelP7StructAP7StructA
.type _Z32__device_stub__Z6kernelP7StructAP7StructA, @function
_Z32__device_stub__Z6kernelP7StructAP7StructA:
.LFB10884:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelP7StructA(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10884:
.size _Z32__device_stub__Z6kernelP7StructAP7StructA, .-_Z32__device_stub__Z6kernelP7StructAP7StructA
.globl _Z6kernelP7StructA
.type _Z6kernelP7StructA, @function
_Z6kernelP7StructA:
.LFB10885:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6kernelP7StructAP7StructA
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10885:
.size _Z6kernelP7StructA, .-_Z6kernelP7StructA
.globl main
.type main, @function
main:
.LFB10859:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $40, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %eax
.L12:
movl %eax, (%rbx,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L12
leaq 8(%rsp), %rbp
movl $40, %esi
movq %rbp, %rdi
call cudaMalloc@PLT
movl $1, %ecx
movl $40, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movq %rsp, %rdi
movl $8, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq (%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq (%rsp), %rdi
call _Z32__device_stub__Z6kernelP7StructAP7StructA
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10859:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelP7StructA"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB10887:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelP7StructA(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10887:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<bits/stdc++.h>
using namespace std;
#define pi (2.0*acos(0.0))
#define eps 1e-6
#define ll long long
#define inf (1<<29)
#define vi vector<int>
#define vll vector<ll>
#define sc(x) scanf("%d",&x)
#define scl(x) scanf("%lld",&x)
#define all(v) v.begin() , v.end()
#define me(a,val) memset( a , val ,sizeof(a) )
#define pb(x) push_back(x)
#define pii pair<int,int>
#define mp(a,b) make_pair(a,b)
#define Q(x) (x) * (x)
#define L(x) ((x<<1) + 1)
#define R(x) ((x<<1) + 2)
#define M(x,y) ((x+y)>>1)
#define fi first
#define se second
#define MOD 1000000007
#define ios ios::sync_with_stdio(0)
typedef struct StructA {
int *a;
} CudaMatrix;
#define N 10
__global__ void kernel(CudaMatrix *A){
int x = threadIdx.x;
printf("--> %d\n",x);
for(int i = 0 ; i < 10 ; i++)
printf("%d - ",A->a[i]);
printf("\n");
}
int main() {
CudaMatrix *A;
int *a;
a = (int *)malloc( N * sizeof(int) );
for(int i = 0 ; i < N ; i++)
a[i] = i;
int *a2;
cudaMalloc( &a2 , N * sizeof(int) );
cudaMemcpy( a2 , a , N * sizeof(int) , cudaMemcpyHostToDevice );
int sz = sizeof(CudaMatrix);
cudaMalloc( &A , sz );
cudaMemcpy( &(A->a) , &a2 , sizeof(int *) , cudaMemcpyHostToDevice );
kernel<<<1,1>>>( A );
cudaFree( A );
} | #include <hip/hip_runtime.h>
#include<bits/stdc++.h>
using namespace std;
#define pi (2.0*acos(0.0))
#define eps 1e-6
#define ll long long
#define inf (1<<29)
#define vi vector<int>
#define vll vector<ll>
#define sc(x) scanf("%d",&x)
#define scl(x) scanf("%lld",&x)
#define all(v) v.begin() , v.end()
#define me(a,val) memset( a , val ,sizeof(a) )
#define pb(x) push_back(x)
#define pii pair<int,int>
#define mp(a,b) make_pair(a,b)
#define Q(x) (x) * (x)
#define L(x) ((x<<1) + 1)
#define R(x) ((x<<1) + 2)
#define M(x,y) ((x+y)>>1)
#define fi first
#define se second
#define MOD 1000000007
#define ios ios::sync_with_stdio(0)
typedef struct StructA {
int *a;
} CudaMatrix;
#define N 10
__global__ void kernel(CudaMatrix *A){
int x = threadIdx.x;
printf("--> %d\n",x);
for(int i = 0 ; i < 10 ; i++)
printf("%d - ",A->a[i]);
printf("\n");
}
int main() {
CudaMatrix *A;
int *a;
a = (int *)malloc( N * sizeof(int) );
for(int i = 0 ; i < N ; i++)
a[i] = i;
int *a2;
hipMalloc( &a2 , N * sizeof(int) );
hipMemcpy( a2 , a , N * sizeof(int) , hipMemcpyHostToDevice );
int sz = sizeof(CudaMatrix);
hipMalloc( &A , sz );
hipMemcpy( &(A->a) , &a2 , sizeof(int *) , hipMemcpyHostToDevice );
kernel<<<1,1>>>( A );
hipFree( A );
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<bits/stdc++.h>
using namespace std;
#define pi (2.0*acos(0.0))
#define eps 1e-6
#define ll long long
#define inf (1<<29)
#define vi vector<int>
#define vll vector<ll>
#define sc(x) scanf("%d",&x)
#define scl(x) scanf("%lld",&x)
#define all(v) v.begin() , v.end()
#define me(a,val) memset( a , val ,sizeof(a) )
#define pb(x) push_back(x)
#define pii pair<int,int>
#define mp(a,b) make_pair(a,b)
#define Q(x) (x) * (x)
#define L(x) ((x<<1) + 1)
#define R(x) ((x<<1) + 2)
#define M(x,y) ((x+y)>>1)
#define fi first
#define se second
#define MOD 1000000007
#define ios ios::sync_with_stdio(0)
typedef struct StructA {
int *a;
} CudaMatrix;
#define N 10
__global__ void kernel(CudaMatrix *A){
int x = threadIdx.x;
printf("--> %d\n",x);
for(int i = 0 ; i < 10 ; i++)
printf("%d - ",A->a[i]);
printf("\n");
}
int main() {
CudaMatrix *A;
int *a;
a = (int *)malloc( N * sizeof(int) );
for(int i = 0 ; i < N ; i++)
a[i] = i;
int *a2;
hipMalloc( &a2 , N * sizeof(int) );
hipMemcpy( a2 , a , N * sizeof(int) , hipMemcpyHostToDevice );
int sz = sizeof(CudaMatrix);
hipMalloc( &A , sz );
hipMemcpy( &(A->a) , &a2 , sizeof(int *) , hipMemcpyHostToDevice );
kernel<<<1,1>>>( A );
hipFree( A );
} | .text
.file "copy.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__kernelP7StructA # -- Begin function _Z21__device_stub__kernelP7StructA
.p2align 4, 0x90
.type _Z21__device_stub__kernelP7StructA,@function
_Z21__device_stub__kernelP7StructA: # @_Z21__device_stub__kernelP7StructA
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z6kernelP7StructA, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelP7StructA, .Lfunc_end0-_Z21__device_stub__kernelP7StructA
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $88, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $40, %edi
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %r14
movl $40, %esi
movq %r14, %rdi
callq hipMalloc
movq 24(%rsp), %rdi
movl $40, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movl $8, %esi
callq hipMalloc
movq 8(%rsp), %rdi
movl $8, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z6kernelP7StructA, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelP7StructA, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelP7StructA,@object # @_Z6kernelP7StructA
.section .rodata,"a",@progbits
.globl _Z6kernelP7StructA
.p2align 3, 0x0
_Z6kernelP7StructA:
.quad _Z21__device_stub__kernelP7StructA
.size _Z6kernelP7StructA, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelP7StructA"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelP7StructA
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelP7StructA
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00035700_00000000-6_copy.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB10862:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10862:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z6kernelP7StructAP7StructA
.type _Z32__device_stub__Z6kernelP7StructAP7StructA, @function
_Z32__device_stub__Z6kernelP7StructAP7StructA:
.LFB10884:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelP7StructA(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10884:
.size _Z32__device_stub__Z6kernelP7StructAP7StructA, .-_Z32__device_stub__Z6kernelP7StructAP7StructA
.globl _Z6kernelP7StructA
.type _Z6kernelP7StructA, @function
_Z6kernelP7StructA:
.LFB10885:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6kernelP7StructAP7StructA
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10885:
.size _Z6kernelP7StructA, .-_Z6kernelP7StructA
.globl main
.type main, @function
main:
.LFB10859:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $40, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %eax
.L12:
movl %eax, (%rbx,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L12
leaq 8(%rsp), %rbp
movl $40, %esi
movq %rbp, %rdi
call cudaMalloc@PLT
movl $1, %ecx
movl $40, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movq %rsp, %rdi
movl $8, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq (%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq (%rsp), %rdi
call _Z32__device_stub__Z6kernelP7StructAP7StructA
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10859:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelP7StructA"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB10887:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelP7StructA(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10887:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "copy.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__kernelP7StructA # -- Begin function _Z21__device_stub__kernelP7StructA
.p2align 4, 0x90
.type _Z21__device_stub__kernelP7StructA,@function
_Z21__device_stub__kernelP7StructA: # @_Z21__device_stub__kernelP7StructA
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z6kernelP7StructA, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelP7StructA, .Lfunc_end0-_Z21__device_stub__kernelP7StructA
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $88, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $40, %edi
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %r14
movl $40, %esi
movq %r14, %rdi
callq hipMalloc
movq 24(%rsp), %rdi
movl $40, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movl $8, %esi
callq hipMalloc
movq 8(%rsp), %rdi
movl $8, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z6kernelP7StructA, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelP7StructA, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelP7StructA,@object # @_Z6kernelP7StructA
.section .rodata,"a",@progbits
.globl _Z6kernelP7StructA
.p2align 3, 0x0
_Z6kernelP7StructA:
.quad _Z21__device_stub__kernelP7StructA
.size _Z6kernelP7StructA, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelP7StructA"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelP7StructA
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelP7StructA
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cc_labelling.cuh"
constexpr int connectivity = 4;
__global__ void initialization_step(const int* nn_list, int* residual_list, int* labels, int height, int width)
{
int x = blockDim.x * blockIdx.x + threadIdx.x;
int y = blockDim.y * blockIdx.y + threadIdx.y;
if (x >= width || y >= height)
return;
int i = x + y * width;
int label = i;
for (int j = i * connectivity; (j - i * connectivity) < connectivity; ++j)
{
int nn = nn_list[j];
if (nn == -1)
continue;
if (nn < label)
label = nn;
}
int pos = i * connectivity;
for (int j = i * connectivity; (j - i * connectivity) < connectivity; ++j)
{
int nn = nn_list[j];
if (nn == -1)
continue;
if (nn < i && nn != label)
residual_list[pos++] = nn;
}
// Assign label
labels[i] = label;
}
__global__ void analysis_step(int* labels, int height, int width)
{
int x = blockDim.x * blockIdx.x + threadIdx.x;
int y = blockDim.y * blockIdx.y + threadIdx.y;
if (x >= width || y >= height)
return;
int i = x + y * width;
int last_label;
do
{
last_label = labels[i];
labels[i] = labels[labels[i]];
} while (labels[i] != last_label);
}
__global__ void reduction_step(const int* residual_list, int* labels, int height, int width)
{
int x = blockDim.x * blockIdx.x + threadIdx.x;
int y = blockDim.y * blockIdx.y + threadIdx.y;
if (x >= width || y >= height)
return;
int i = x + y * width;
for (int j = i * connectivity; (j - i * connectivity) < connectivity && residual_list[j] != -1; ++j)
{
int label_1 = labels[i];
while (label_1 != labels[label_1])
label_1 = labels[label_1];
int residual_element = residual_list[j];
int label_2 = labels[residual_element];
while (label_2 != labels[label_2])
label_2 = labels[label_2];
bool flag = label_1 == label_2;
if (label_1 < label_2)
{
int tmp = label_1;
label_1 = label_2;
label_2 = tmp;
}
while (!flag)
{
int label_3 = atomicMin(&labels[label_1], label_2);
if (label_3 == label_2)
flag = true;
else if (label_3 > label_2)
label_1 = label_3;
else if (label_3 < label_2)
{
label_1 = label_2;
label_2 = label_3;
}
}
}
} | code for sm_80
Function : _Z14reduction_stepPKiPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x170], P0 ; /* 0x00005c0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R5, R3, c[0x0][0x174], R0 ; /* 0x00005d0003057a24 */
/* 0x000fe200078e0200 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fe400078e00ff */
/*00d0*/ IMAD.SHL.U32 R3, R5, 0x4, RZ ; /* 0x0000000405037824 */
/* 0x000fc800078e00ff */
/*00e0*/ IMAD.WIDE R2, R3, R0, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0200 */
/*00f0*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea4000c1e1900 */
/*0100*/ ISETP.NE.AND P0, PT, R8, -0x1, PT ; /* 0xffffffff0800780c */
/* 0x004fda0003f05270 */
/*0110*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0120*/ IMAD.WIDE R4, R5, R0, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0200 */
/*0130*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000162000c1e1900 */
/*0140*/ BSSY B0, 0x1d0 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*0150*/ SHF.R.S32.HI R11, RZ, 0x1f, R8 ; /* 0x0000001fff0b7819 */
/* 0x000fe40000011408 */
/*0160*/ IMAD.WIDE R6, R9, R0, c[0x0][0x168] ; /* 0x00005a0009067625 */
/* 0x020fcc00078e0200 */
/*0170*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*0180*/ IMAD.MOV.U32 R10, RZ, RZ, R9 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0009 */
/*0190*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fe20003f05270 */
/*01a0*/ IMAD.MOV.U32 R9, RZ, RZ, R6 ; /* 0x000000ffff097224 */
/* 0x000fd800078e0006 */
/*01b0*/ @P0 BRA 0x160 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*01c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01d0*/ LEA R6, P0, R8, c[0x0][0x168], 0x2 ; /* 0x00005a0008067a11 */
/* 0x000fc800078010ff */
/*01e0*/ LEA.HI.X R7, R8, c[0x0][0x16c], R11, 0x2, P0 ; /* 0x00005b0008077a11 */
/* 0x000fca00000f140b */
/*01f0*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000362000c1e1900 */
/*0200*/ BSSY B0, 0x280 ; /* 0x0000007000007945 */
/* 0x000fe60003800000 */
/*0210*/ IMAD.WIDE R6, R9, R0, c[0x0][0x168] ; /* 0x00005a0009067625 */
/* 0x022fcc00078e0200 */
/*0220*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*0230*/ IMAD.MOV.U32 R11, RZ, RZ, R9 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0009 */
/*0240*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fe20003f05270 */
/*0250*/ IMAD.MOV.U32 R9, RZ, RZ, R6 ; /* 0x000000ffff097224 */
/* 0x000fd800078e0006 */
/*0260*/ @P0 BRA 0x210 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*0270*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0280*/ ISETP.NE.AND P0, PT, R10, R11, PT ; /* 0x0000000b0a00720c */
/* 0x000fe20003f05270 */
/*0290*/ BSSY B0, 0x390 ; /* 0x000000f000007945 */
/* 0x000fd80003800000 */
/*02a0*/ @!P0 BRA 0x380 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*02b0*/ IMNMX R9, R11.reuse, R10.reuse, PT ; /* 0x0000000a0b097217 */
/* 0x0c0fe20003800200 */
/*02c0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fe200078e00ff */
/*02d0*/ IMNMX R8, R11, R10, !PT ; /* 0x0000000a0b087217 */
/* 0x000fca0007800200 */
/*02e0*/ IMAD.WIDE R6, R8, R0, c[0x0][0x168] ; /* 0x00005a0008067625 */
/* 0x000fe200078e0200 */
/*02f0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fea0003800000 */
/*0300*/ ATOMG.E.MIN.S32.STRONG.GPU PT, R6, [R6.64], R9 ; /* 0x00000009060679a8 */
/* 0x000ea400089ee3c4 */
/*0310*/ ISETP.NE.AND P1, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x004fda0003f25270 */
/*0320*/ @P1 ISETP.GE.AND P2, PT, R6.reuse, R9.reuse, PT ; /* 0x000000090600120c */
/* 0x0c0fe40003f46270 */
/*0330*/ @P1 ISETP.GT.AND P0, PT, R6.reuse, R9, PT ; /* 0x000000090600120c */
/* 0x040fe40003f04270 */
/*0340*/ @P1 SEL R10, R9.reuse, R8, !P2 ; /* 0x00000008090a1207 */
/* 0x040fe40005000000 */
/*0350*/ @P1 IMNMX R9, R9, R6, PT ; /* 0x0000000609091217 */
/* 0x000fe40003800200 */
/*0360*/ @P1 SEL R8, R6, R10, P0 ; /* 0x0000000a06081207 */
/* 0x000fe20000000000 */
/*0370*/ @P1 BRA 0x2e0 ; /* 0xffffff6000001947 */
/* 0x000fea000383ffff */
/*0380*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0390*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040402087981 */
/* 0x000ea4000c1e1900 */
/*03a0*/ ISETP.NE.AND P0, PT, R8, -0x1, PT ; /* 0xffffffff0800780c */
/* 0x004fda0003f05270 */
/*03b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*03c0*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000362000c1e1900 */
/*03d0*/ BSSY B0, 0x460 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*03e0*/ SHF.R.S32.HI R11, RZ, 0x1f, R8 ; /* 0x0000001fff0b7819 */
/* 0x000fe40000011408 */
/*03f0*/ IMAD.WIDE R6, R9, R0, c[0x0][0x168] ; /* 0x00005a0009067625 */
/* 0x020fcc00078e0200 */
/*0400*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*0410*/ IMAD.MOV.U32 R10, RZ, RZ, R9 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0009 */
/*0420*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fe20003f05270 */
/*0430*/ IMAD.MOV.U32 R9, RZ, RZ, R6 ; /* 0x000000ffff097224 */
/* 0x000fd800078e0006 */
/*0440*/ @P0 BRA 0x3f0 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*0450*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0460*/ LEA R6, P0, R8, c[0x0][0x168], 0x2 ; /* 0x00005a0008067a11 */
/* 0x000fc800078010ff */
/*0470*/ LEA.HI.X R7, R8, c[0x0][0x16c], R11, 0x2, P0 ; /* 0x00005b0008077a11 */
/* 0x000fca00000f140b */
/*0480*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000562000c1e1900 */
/*0490*/ BSSY B0, 0x510 ; /* 0x0000007000007945 */
/* 0x000fe60003800000 */
/*04a0*/ IMAD.WIDE R6, R9, R0, c[0x0][0x168] ; /* 0x00005a0009067625 */
/* 0x024fcc00078e0200 */
/*04b0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*04c0*/ IMAD.MOV.U32 R11, RZ, RZ, R9 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0009 */
/*04d0*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fe20003f05270 */
/*04e0*/ IMAD.MOV.U32 R9, RZ, RZ, R6 ; /* 0x000000ffff097224 */
/* 0x000fd800078e0006 */
/*04f0*/ @P0 BRA 0x4a0 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*0500*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0510*/ ISETP.NE.AND P0, PT, R10, R11, PT ; /* 0x0000000b0a00720c */
/* 0x000fe20003f05270 */
/*0520*/ BSSY B0, 0x620 ; /* 0x000000f000007945 */
/* 0x000fd80003800000 */
/*0530*/ @!P0 BRA 0x610 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0540*/ IMNMX R9, R11.reuse, R10.reuse, PT ; /* 0x0000000a0b097217 */
/* 0x0c0fe20003800200 */
/*0550*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fe200078e00ff */
/*0560*/ IMNMX R8, R11, R10, !PT ; /* 0x0000000a0b087217 */
/* 0x000fca0007800200 */
/*0570*/ IMAD.WIDE R6, R8, R0, c[0x0][0x168] ; /* 0x00005a0008067625 */
/* 0x000fe200078e0200 */
/*0580*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fea0003800000 */
/*0590*/ ATOMG.E.MIN.S32.STRONG.GPU PT, R6, [R6.64], R9 ; /* 0x00000009060679a8 */
/* 0x000ea400089ee3c4 */
/*05a0*/ ISETP.NE.AND P1, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x004fda0003f25270 */
/*05b0*/ @P1 ISETP.GE.AND P2, PT, R6.reuse, R9.reuse, PT ; /* 0x000000090600120c */
/* 0x0c0fe40003f46270 */
/*05c0*/ @P1 ISETP.GT.AND P0, PT, R6.reuse, R9, PT ; /* 0x000000090600120c */
/* 0x040fe40003f04270 */
/*05d0*/ @P1 SEL R10, R9.reuse, R8, !P2 ; /* 0x00000008090a1207 */
/* 0x040fe40005000000 */
/*05e0*/ @P1 IMNMX R9, R9, R6, PT ; /* 0x0000000609091217 */
/* 0x000fe40003800200 */
/*05f0*/ @P1 SEL R8, R6, R10, P0 ; /* 0x0000000a06081207 */
/* 0x000fe20000000000 */
/*0600*/ @P1 BRA 0x570 ; /* 0xffffff6000001947 */
/* 0x000fea000383ffff */
/*0610*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0620*/ LDG.E R8, [R2.64+0x8] ; /* 0x0000080402087981 */
/* 0x000ea4000c1e1900 */
/*0630*/ ISETP.NE.AND P0, PT, R8, -0x1, PT ; /* 0xffffffff0800780c */
/* 0x004fda0003f05270 */
/*0640*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0650*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000562000c1e1900 */
/*0660*/ BSSY B0, 0x6f0 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*0670*/ SHF.R.S32.HI R11, RZ, 0x1f, R8 ; /* 0x0000001fff0b7819 */
/* 0x000fe40000011408 */
/*0680*/ IMAD.WIDE R6, R9, R0, c[0x0][0x168] ; /* 0x00005a0009067625 */
/* 0x020fcc00078e0200 */
/*0690*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1900 */
/*06a0*/ IMAD.MOV.U32 R10, RZ, RZ, R9 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0009 */
/*06b0*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x008fe20003f05270 */
/*06c0*/ IMAD.MOV.U32 R9, RZ, RZ, R6 ; /* 0x000000ffff097224 */
/* 0x000fd800078e0006 */
/*06d0*/ @P0 BRA 0x680 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*06e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06f0*/ LEA R6, P0, R8, c[0x0][0x168], 0x2 ; /* 0x00005a0008067a11 */
/* 0x000fc800078010ff */
/*0700*/ LEA.HI.X R7, R8, c[0x0][0x16c], R11, 0x2, P0 ; /* 0x00005b0008077a11 */
/* 0x000fca00000f140b */
/*0710*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000762000c1e1900 */
/*0720*/ BSSY B0, 0x7a0 ; /* 0x0000007000007945 */
/* 0x000fe60003800000 */
/*0730*/ IMAD.WIDE R6, R9, R0, c[0x0][0x168] ; /* 0x00005a0009067625 */
/* 0x028fcc00078e0200 */
/*0740*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1900 */
/*0750*/ IMAD.MOV.U32 R11, RZ, RZ, R9 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0009 */
/*0760*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x008fe20003f05270 */
/*0770*/ IMAD.MOV.U32 R9, RZ, RZ, R6 ; /* 0x000000ffff097224 */
/* 0x000fd800078e0006 */
/*0780*/ @P0 BRA 0x730 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*0790*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07a0*/ ISETP.NE.AND P0, PT, R10, R11, PT ; /* 0x0000000b0a00720c */
/* 0x000fe20003f05270 */
/*07b0*/ BSSY B0, 0x8b0 ; /* 0x000000f000007945 */
/* 0x000fd80003800000 */
/*07c0*/ @!P0 BRA 0x8a0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*07d0*/ IMNMX R9, R11.reuse, R10.reuse, PT ; /* 0x0000000a0b097217 */
/* 0x0c0fe20003800200 */
/*07e0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fe200078e00ff */
/*07f0*/ IMNMX R8, R11, R10, !PT ; /* 0x0000000a0b087217 */
/* 0x000fca0007800200 */
/*0800*/ IMAD.WIDE R6, R8, R0, c[0x0][0x168] ; /* 0x00005a0008067625 */
/* 0x000fe200078e0200 */
/*0810*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fea0003800000 */
/*0820*/ ATOMG.E.MIN.S32.STRONG.GPU PT, R6, [R6.64], R9 ; /* 0x00000009060679a8 */
/* 0x000ee400089ee3c4 */
/*0830*/ ISETP.NE.AND P1, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x008fda0003f25270 */
/*0840*/ @P1 ISETP.GE.AND P2, PT, R6.reuse, R9.reuse, PT ; /* 0x000000090600120c */
/* 0x0c0fe40003f46270 */
/*0850*/ @P1 ISETP.GT.AND P0, PT, R6.reuse, R9, PT ; /* 0x000000090600120c */
/* 0x040fe40003f04270 */
/*0860*/ @P1 SEL R10, R9.reuse, R8, !P2 ; /* 0x00000008090a1207 */
/* 0x040fe40005000000 */
/*0870*/ @P1 IMNMX R9, R9, R6, PT ; /* 0x0000000609091217 */
/* 0x000fe40003800200 */
/*0880*/ @P1 SEL R8, R6, R10, P0 ; /* 0x0000000a06081207 */
/* 0x000fe20000000000 */
/*0890*/ @P1 BRA 0x800 ; /* 0xffffff6000001947 */
/* 0x000fea000383ffff */
/*08a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08b0*/ LDG.E R6, [R2.64+0xc] ; /* 0x00000c0402067981 */
/* 0x000ee4000c1e1900 */
/*08c0*/ ISETP.NE.AND P0, PT, R6, -0x1, PT ; /* 0xffffffff0600780c */
/* 0x008fda0003f05270 */
/*08d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*08e0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x007162000c1e1900 */
/*08f0*/ BSSY B0, 0x980 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*0900*/ SHF.R.S32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */
/* 0x000fe40000011406 */
/*0910*/ IMAD.WIDE R2, R5, R0, c[0x0][0x168] ; /* 0x00005a0005027625 */
/* 0x020fcc00078e0200 */
/*0920*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0930*/ IMAD.MOV.U32 R4, RZ, RZ, R5 ; /* 0x000000ffff047224 */
/* 0x001fe200078e0005 */
/*0940*/ ISETP.NE.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x004fe20003f05270 */
/*0950*/ IMAD.MOV.U32 R5, RZ, RZ, R2 ; /* 0x000000ffff057224 */
/* 0x000fd800078e0002 */
/*0960*/ @P0 BRA 0x910 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*0970*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0980*/ LEA R2, P0, R6, c[0x0][0x168], 0x2 ; /* 0x00005a0006027a11 */
/* 0x000fc800078010ff */
/*0990*/ LEA.HI.X R3, R6, c[0x0][0x16c], R7, 0x2, P0 ; /* 0x00005b0006037a11 */
/* 0x000fca00000f1407 */
/*09a0*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000162000c1e1900 */
/*09b0*/ BSSY B0, 0xa30 ; /* 0x0000007000007945 */
/* 0x000fe60003800000 */
/*09c0*/ IMAD.WIDE R2, R5, R0, c[0x0][0x168] ; /* 0x00005a0005027625 */
/* 0x021fcc00078e0200 */
/*09d0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*09e0*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0005 */
/*09f0*/ ISETP.NE.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x004fe20003f05270 */
/*0a00*/ IMAD.MOV.U32 R5, RZ, RZ, R2 ; /* 0x000000ffff057224 */
/* 0x000fd800078e0002 */
/*0a10*/ @P0 BRA 0x9c0 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*0a20*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a30*/ ISETP.NE.AND P0, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x000fda0003f05270 */
/*0a40*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0a50*/ IMNMX R5, R7.reuse, R4.reuse, PT ; /* 0x0000000407057217 */
/* 0x0c0fe40003800200 */
/*0a60*/ IMNMX R0, R7, R4, !PT ; /* 0x0000000407007217 */
/* 0x000fe20007800200 */
/*0a70*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc800078e00ff */
/*0a80*/ IMAD.WIDE R2, R0, R7, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fe200078e0207 */
/*0a90*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fea0003800000 */
/*0aa0*/ ATOMG.E.MIN.S32.STRONG.GPU PT, R2, [R2.64], R5 ; /* 0x00000005020279a8 */
/* 0x000ea400089ee3c4 */
/*0ab0*/ ISETP.NE.AND P1, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x004fda0003f25270 */
/*0ac0*/ @P1 ISETP.GE.AND P2, PT, R2.reuse, R5.reuse, PT ; /* 0x000000050200120c */
/* 0x0c0fe40003f46270 */
/*0ad0*/ @P1 ISETP.GT.AND P0, PT, R2.reuse, R5, PT ; /* 0x000000050200120c */
/* 0x040fe40003f04270 */
/*0ae0*/ @P1 SEL R4, R5.reuse, R0, !P2 ; /* 0x0000000005041207 */
/* 0x040fe40005000000 */
/*0af0*/ @P1 IMNMX R5, R5, R2, PT ; /* 0x0000000205051217 */
/* 0x000fe40003800200 */
/*0b00*/ @P1 SEL R0, R2, R4, P0 ; /* 0x0000000402001207 */
/* 0x000fe20000000000 */
/*0b10*/ @P1 BRA 0xa80 ; /* 0xffffff6000001947 */
/* 0x000fea000383ffff */
/*0b20*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b30*/ BRA 0xb30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13analysis_stepPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x168], P0 ; /* 0x00005a0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R3, R3, c[0x0][0x16c], R0 ; /* 0x00005b0003037a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R3, R6, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0206 */
/*00e0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000164000c1e1900 */
/*00f0*/ IMAD.WIDE R4, R0, R6, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x020fcc00078e0206 */
/*0100*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0110*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0043e2000c101904 */
/*0120*/ ISETP.NE.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fe40003f05270 */
/*0130*/ MOV R0, R5 ; /* 0x0000000500007202 */
/* 0x000fd60000000f00 */
/*0140*/ @P0 BRA 0xf0 ; /* 0xffffffa000000947 */
/* 0x002fea000383ffff */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z19initialization_stepPKiPiS1_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R0, R3, c[0x0][0x17c], R0 ; /* 0x00005f0003007a24 */
/* 0x000fe200078e0200 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.MOV.U32 R19, RZ, RZ, 0x4 ; /* 0x00000004ff137424 */
/* 0x000fe400078e00ff */
/*00d0*/ IMAD.SHL.U32 R5, R0, 0x4, RZ ; /* 0x0000000400057824 */
/* 0x000fc800078e00ff */
/*00e0*/ IMAD.WIDE R2, R5, R19, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fca00078e0213 */
/*00f0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R13, [R2.64+0x4] ; /* 0x00000404020d7981 */
/* 0x000ee8000c1e1900 */
/*0110*/ LDG.E R9, [R2.64+0x8] ; /* 0x0000080402097981 */
/* 0x000f28000c1e1900 */
/*0120*/ LDG.E R11, [R2.64+0xc] ; /* 0x00000c04020b7981 */
/* 0x000f62000c1e1900 */
/*0130*/ BSSY B0, 0x2c0 ; /* 0x0000018000007945 */
/* 0x000fe20003800000 */
/*0140*/ IMAD.MOV.U32 R6, RZ, RZ, R5 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0005 */
/*0150*/ ISETP.NE.AND P0, PT, R7, -0x1, PT ; /* 0xffffffff0700780c */
/* 0x004fc80003f05270 */
/*0160*/ ISETP.LT.AND P0, PT, R7, R0.reuse, P0 ; /* 0x000000000700720c */
/* 0x080fe40000701270 */
/*0170*/ ISETP.NE.AND P1, PT, R13, -0x1, PT ; /* 0xffffffff0d00780c */
/* 0x008fe40003f25270 */
/*0180*/ SEL R4, R7, R0, P0 ; /* 0x0000000007047207 */
/* 0x000fe40000000000 */
/*0190*/ ISETP.NE.AND P0, PT, R9, -0x1, PT ; /* 0xffffffff0900780c */
/* 0x010fe40003f05270 */
/*01a0*/ ISETP.LT.AND P1, PT, R13, R4, P1 ; /* 0x000000040d00720c */
/* 0x000fc80000f21270 */
/*01b0*/ SEL R4, R13, R4, P1 ; /* 0x000000040d047207 */
/* 0x000fe40000800000 */
/*01c0*/ ISETP.NE.AND P1, PT, R11, -0x1, PT ; /* 0xffffffff0b00780c */
/* 0x020fe40003f25270 */
/*01d0*/ ISETP.LT.AND P0, PT, R9, R4, P0 ; /* 0x000000040900720c */
/* 0x000fc80000701270 */
/*01e0*/ SEL R4, R9, R4, P0 ; /* 0x0000000409047207 */
/* 0x000fe40000000000 */
/*01f0*/ ISETP.GE.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fe40003f06270 */
/*0200*/ ISETP.LT.AND P1, PT, R11, R4, P1 ; /* 0x000000040b00720c */
/* 0x000fc80000f21270 */
/*0210*/ SEL R11, R11, R4, P1 ; /* 0x000000040b0b7207 */
/* 0x000fc80000800000 */
/*0220*/ ISETP.NE.AND P0, PT, R7, R11, !P0 ; /* 0x0000000b0700720c */
/* 0x000fc80004705270 */
/*0230*/ ISETP.NE.AND P0, PT, R7, -0x1, P0 ; /* 0xffffffff0700780c */
/* 0x000fda0000705270 */
/*0240*/ @!P0 BRA 0x2b0 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*0250*/ SHF.R.S32.HI R8, RZ, 0x1f, R5 ; /* 0x0000001fff087819 */
/* 0x000fe40000011405 */
/*0260*/ LEA R4, P0, R5, c[0x0][0x168], 0x2 ; /* 0x00005a0005047a11 */
/* 0x000fc800078010ff */
/*0270*/ LEA.HI.X R5, R5, c[0x0][0x16c], R8, 0x2, P0 ; /* 0x00005b0005057a11 */
/* 0x000fca00000f1408 */
/*0280*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e8000c101904 */
/*0290*/ LDG.E R13, [R2.64+0x4] ; /* 0x00000404020d7981 */
/* 0x000162000c1e1900 */
/*02a0*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fc60007ffe0ff */
/*02b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02c0*/ ISETP.NE.AND P0, PT, R13, R11, PT ; /* 0x0000000b0d00720c */
/* 0x020fc80003f05270 */
/*02d0*/ ISETP.GE.OR P0, PT, R13, R0, !P0 ; /* 0x000000000d00720c */
/* 0x000fc80004706670 */
/*02e0*/ ISETP.EQ.OR P0, PT, R13, -0x1, P0 ; /* 0xffffffff0d00780c */
/* 0x000fda0000702670 */
/*02f0*/ @!P0 IMAD.WIDE R4, R6, R19, c[0x0][0x168] ; /* 0x00005a0006048625 */
/* 0x001fca00078e0213 */
/*0300*/ @!P0 STG.E [R4.64], R13 ; /* 0x0000000d04008986 */
/* 0x0001e8000c101904 */
/*0310*/ LDG.E R15, [R2.64+0x8] ; /* 0x00000804020f7981 */
/* 0x000ea2000c1e1900 */
/*0320*/ @!P0 IADD3 R7, R6, 0x1, RZ ; /* 0x0000000106078810 */
/* 0x000fca0007ffe0ff */
/*0330*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, R7 ; /* 0x000000ffff068224 */
/* 0x000fe200078e0007 */
/*0340*/ ISETP.NE.AND P1, PT, R15, R11, PT ; /* 0x0000000b0f00720c */
/* 0x004fc80003f25270 */
/*0350*/ ISETP.GE.OR P1, PT, R15, R0, !P1 ; /* 0x000000000f00720c */
/* 0x000fc80004f26670 */
/*0360*/ ISETP.EQ.OR P1, PT, R15, -0x1, P1 ; /* 0xffffffff0f00780c */
/* 0x000fda0000f22670 */
/*0370*/ @!P1 IMAD.WIDE R8, R6, R19, c[0x0][0x168] ; /* 0x00005a0006089625 */
/* 0x000fca00078e0213 */
/*0380*/ @!P1 STG.E [R8.64], R15 ; /* 0x0000000f08009986 */
/* 0x000fe8000c101904 */
/*0390*/ LDG.E R17, [R2.64+0xc] ; /* 0x00000c0402117981 */
/* 0x000ea2000c1e1900 */
/*03a0*/ @!P1 IADD3 R4, R6, 0x1, RZ ; /* 0x0000000106049810 */
/* 0x001fca0007ffe0ff */
/*03b0*/ @!P1 IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff069224 */
/* 0x000fe200078e0004 */
/*03c0*/ ISETP.NE.AND P0, PT, R17, R11, PT ; /* 0x0000000b1100720c */
/* 0x004fc80003f05270 */
/*03d0*/ ISETP.GE.OR P0, PT, R17, R0, !P0 ; /* 0x000000001100720c */
/* 0x000fc80004706670 */
/*03e0*/ ISETP.EQ.OR P0, PT, R17, -0x1, P0 ; /* 0xffffffff1100780c */
/* 0x000fda0000702670 */
/*03f0*/ @!P0 IMAD.WIDE R4, R6, R19, c[0x0][0x168] ; /* 0x00005a0006048625 */
/* 0x000fc800078e0213 */
/*0400*/ IMAD.WIDE R6, R0, R19, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0213 */
/*0410*/ @!P0 STG.E [R4.64], R17 ; /* 0x0000001104008986 */
/* 0x000fe8000c101904 */
/*0420*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x000fe2000c101904 */
/*0430*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0440*/ BRA 0x440; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cc_labelling.cuh"
constexpr int connectivity = 4;
__global__ void initialization_step(const int* nn_list, int* residual_list, int* labels, int height, int width)
{
int x = blockDim.x * blockIdx.x + threadIdx.x;
int y = blockDim.y * blockIdx.y + threadIdx.y;
if (x >= width || y >= height)
return;
int i = x + y * width;
int label = i;
for (int j = i * connectivity; (j - i * connectivity) < connectivity; ++j)
{
int nn = nn_list[j];
if (nn == -1)
continue;
if (nn < label)
label = nn;
}
int pos = i * connectivity;
for (int j = i * connectivity; (j - i * connectivity) < connectivity; ++j)
{
int nn = nn_list[j];
if (nn == -1)
continue;
if (nn < i && nn != label)
residual_list[pos++] = nn;
}
// Assign label
labels[i] = label;
}
__global__ void analysis_step(int* labels, int height, int width)
{
int x = blockDim.x * blockIdx.x + threadIdx.x;
int y = blockDim.y * blockIdx.y + threadIdx.y;
if (x >= width || y >= height)
return;
int i = x + y * width;
int last_label;
do
{
last_label = labels[i];
labels[i] = labels[labels[i]];
} while (labels[i] != last_label);
}
__global__ void reduction_step(const int* residual_list, int* labels, int height, int width)
{
int x = blockDim.x * blockIdx.x + threadIdx.x;
int y = blockDim.y * blockIdx.y + threadIdx.y;
if (x >= width || y >= height)
return;
int i = x + y * width;
for (int j = i * connectivity; (j - i * connectivity) < connectivity && residual_list[j] != -1; ++j)
{
int label_1 = labels[i];
while (label_1 != labels[label_1])
label_1 = labels[label_1];
int residual_element = residual_list[j];
int label_2 = labels[residual_element];
while (label_2 != labels[label_2])
label_2 = labels[label_2];
bool flag = label_1 == label_2;
if (label_1 < label_2)
{
int tmp = label_1;
label_1 = label_2;
label_2 = tmp;
}
while (!flag)
{
int label_3 = atomicMin(&labels[label_1], label_2);
if (label_3 == label_2)
flag = true;
else if (label_3 > label_2)
label_1 = label_3;
else if (label_3 < label_2)
{
label_1 = label_2;
label_2 = label_3;
}
}
}
} | .file "tmpxft_0004c851_00000000-6_cc_labelling.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z19initialization_stepPKiPiS1_iiPKiPiS1_ii
.type _Z47__device_stub__Z19initialization_stepPKiPiS1_iiPKiPiS1_ii, @function
_Z47__device_stub__Z19initialization_stepPKiPiS1_iiPKiPiS1_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19initialization_stepPKiPiS1_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z19initialization_stepPKiPiS1_iiPKiPiS1_ii, .-_Z47__device_stub__Z19initialization_stepPKiPiS1_iiPKiPiS1_ii
.globl _Z19initialization_stepPKiPiS1_ii
.type _Z19initialization_stepPKiPiS1_ii, @function
_Z19initialization_stepPKiPiS1_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z19initialization_stepPKiPiS1_iiPKiPiS1_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19initialization_stepPKiPiS1_ii, .-_Z19initialization_stepPKiPiS1_ii
.globl _Z35__device_stub__Z13analysis_stepPiiiPiii
.type _Z35__device_stub__Z13analysis_stepPiiiPiii, @function
_Z35__device_stub__Z13analysis_stepPiiiPiii:
.LFB2053:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13analysis_stepPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z35__device_stub__Z13analysis_stepPiiiPiii, .-_Z35__device_stub__Z13analysis_stepPiiiPiii
.globl _Z13analysis_stepPiii
.type _Z13analysis_stepPiii, @function
_Z13analysis_stepPiii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13analysis_stepPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z13analysis_stepPiii, .-_Z13analysis_stepPiii
.globl _Z39__device_stub__Z14reduction_stepPKiPiiiPKiPiii
.type _Z39__device_stub__Z14reduction_stepPKiPiiiPKiPiii, @function
_Z39__device_stub__Z14reduction_stepPKiPiiiPKiPiii:
.LFB2055:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14reduction_stepPKiPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z39__device_stub__Z14reduction_stepPKiPiiiPKiPiii, .-_Z39__device_stub__Z14reduction_stepPKiPiiiPKiPiii
.globl _Z14reduction_stepPKiPiii
.type _Z14reduction_stepPKiPiii, @function
_Z14reduction_stepPKiPiii:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14reduction_stepPKiPiiiPKiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z14reduction_stepPKiPiii, .-_Z14reduction_stepPKiPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14reduction_stepPKiPiii"
.LC1:
.string "_Z13analysis_stepPiii"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_Z19initialization_stepPKiPiS1_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14reduction_stepPKiPiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13analysis_stepPiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z19initialization_stepPKiPiS1_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
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