system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void transposeOptimized(float *input, float *output, int m, int n){
int colID_input = threadIdx.x + blockDim.x*blockIdx.x;
int rowID_input = threadIdx.y + blockDim.y*blockIdx.y;
__shared__ float sdata[32][33];
// bank ~ 一次传32 words，32次访问 ~ 32次unit time，所以希望存在shared memory里的数据尽可能多地分布在不同bank上
// 希望shared memory中每列数据所在的bank尽可能多
if (rowID_input < m && colID_input < n) {
int index_input = colID_input + rowID_input*n;
sdata[threadIdx.y][threadIdx.x] = input[index_input];
__syncthreads();
int dst_col = threadIdx.x + blockIdx.y * blockDim.y;
int dst_row = threadIdx.y + blockIdx.x * blockDim.x;
output[dst_col + dst_row*m] = sdata[threadIdx.x][threadIdx.y];
}
} | #include <hip/hip_runtime.h>
__global__ void transposeOptimized(float *input, float *output, int m, int n){
int colID_input = threadIdx.x + blockDim.x*blockIdx.x;
int rowID_input = threadIdx.y + blockDim.y*blockIdx.y;
__shared__ float sdata[32][33];
// bank ~ 一次传32 words，32次访问 ~ 32次unit time，所以希望存在shared memory里的数据尽可能多地分布在不同bank上
// 希望shared memory中每列数据所在的bank尽可能多
if (rowID_input < m && colID_input < n) {
int index_input = colID_input + rowID_input*n;
sdata[threadIdx.y][threadIdx.x] = input[index_input];
__syncthreads();
int dst_col = threadIdx.x + blockIdx.y * blockDim.y;
int dst_row = threadIdx.y + blockIdx.x * blockDim.x;
output[dst_col + dst_row*m] = sdata[threadIdx.x][threadIdx.y];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void transposeOptimized(float *input, float *output, int m, int n){
int colID_input = threadIdx.x + blockDim.x*blockIdx.x;
int rowID_input = threadIdx.y + blockDim.y*blockIdx.y;
__shared__ float sdata[32][33];
// bank ~ 一次传32 words，32次访问 ~ 32次unit time，所以希望存在shared memory里的数据尽可能多地分布在不同bank上
// 希望shared memory中每列数据所在的bank尽可能多
if (rowID_input < m && colID_input < n) {
int index_input = colID_input + rowID_input*n;
sdata[threadIdx.y][threadIdx.x] = input[index_input];
__syncthreads();
int dst_col = threadIdx.x + blockIdx.y * blockDim.y;
int dst_row = threadIdx.y + blockIdx.x * blockDim.x;
output[dst_col + dst_row*m] = sdata[threadIdx.x][threadIdx.y];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18transposeOptimizedPfS_ii
.globl _Z18transposeOptimizedPfS_ii
.p2align 8
.type _Z18transposeOptimizedPfS_ii,@function
_Z18transposeOptimizedPfS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v2, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_mul_i32 s15, s15, s3
s_mul_i32 s14, s14, s2
v_add_nc_u32_e32 v3, s15, v2
v_add_nc_u32_e32 v0, s14, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v3
v_cmp_gt_i32_e64 s2, s5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[4:5], null, v3, s5, v[0:1]
v_add_nc_u32_e32 v0, s14, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v0, v0, s4
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[3:4], 2, v[4:5]
v_lshlrev_b32_e32 v5, 2, v2
v_add3_u32 v0, s15, v1, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_load_b32 v3, v[3:4], off
v_lshlrev_b32_e32 v4, 2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u32_u24 v2, v2, 0x84, v4
v_mad_u32_u24 v4, v1, 0x84, v5
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
ds_store_b32 v2, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v2, v4
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18transposeOptimizedPfS_ii
.amdhsa_group_segment_fixed_size 4224
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18transposeOptimizedPfS_ii, .Lfunc_end0-_Z18transposeOptimizedPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4224
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18transposeOptimizedPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18transposeOptimizedPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void transposeOptimized(float *input, float *output, int m, int n){
int colID_input = threadIdx.x + blockDim.x*blockIdx.x;
int rowID_input = threadIdx.y + blockDim.y*blockIdx.y;
__shared__ float sdata[32][33];
// bank ~ 一次传32 words，32次访问 ~ 32次unit time，所以希望存在shared memory里的数据尽可能多地分布在不同bank上
// 希望shared memory中每列数据所在的bank尽可能多
if (rowID_input < m && colID_input < n) {
int index_input = colID_input + rowID_input*n;
sdata[threadIdx.y][threadIdx.x] = input[index_input];
__syncthreads();
int dst_col = threadIdx.x + blockIdx.y * blockDim.y;
int dst_row = threadIdx.y + blockIdx.x * blockDim.x;
output[dst_col + dst_row*m] = sdata[threadIdx.x][threadIdx.y];
}
} | .text
.file "matrix-transposition.hip"
.globl _Z33__device_stub__transposeOptimizedPfS_ii # -- Begin function _Z33__device_stub__transposeOptimizedPfS_ii
.p2align 4, 0x90
.type _Z33__device_stub__transposeOptimizedPfS_ii,@function
_Z33__device_stub__transposeOptimizedPfS_ii: # @_Z33__device_stub__transposeOptimizedPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18transposeOptimizedPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z33__device_stub__transposeOptimizedPfS_ii, .Lfunc_end0-_Z33__device_stub__transposeOptimizedPfS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18transposeOptimizedPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18transposeOptimizedPfS_ii,@object # @_Z18transposeOptimizedPfS_ii
.section .rodata,"a",@progbits
.globl _Z18transposeOptimizedPfS_ii
.p2align 3, 0x0
_Z18transposeOptimizedPfS_ii:
.quad _Z33__device_stub__transposeOptimizedPfS_ii
.size _Z18transposeOptimizedPfS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18transposeOptimizedPfS_ii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__transposeOptimizedPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18transposeOptimizedPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18transposeOptimizedPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0020*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0030*/ S2R R6, SR_CTAID.Y ; /* 0x0000000000067919 */
/* 0x000e680000002600 */
/*0040*/ S2R R8, SR_TID.Y ; /* 0x0000000000087919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R4, c[0x0][0x0], R5 ; /* 0x0000000004007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R6, c[0x0][0x4], R8 ; /* 0x0000010006037a24 */
/* 0x002fca00078e0208 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x170], P0 ; /* 0x00005c0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R10, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0a7435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R3, R3, c[0x0][0x174], R0 ; /* 0x00005d0003037a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R3, R10, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fcc00078e020a */
/*00e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD R9, R8, 0x21, R5.reuse ; /* 0x0000002108097824 */
/* 0x100fe400078e0205 */
/*0100*/ IMAD R7, R5, 0x21, R8.reuse ; /* 0x0000002105077824 */
/* 0x100fe400078e0208 */
/*0110*/ IMAD R0, R4, c[0x0][0x0], R8 ; /* 0x0000000004007a24 */
/* 0x000fe400078e0208 */
/*0120*/ IMAD R5, R6, c[0x0][0x4], R5 ; /* 0x0000010006057a24 */
/* 0x000fc800078e0205 */
/*0130*/ IMAD R5, R0, c[0x0][0x170], R5 ; /* 0x00005c0000057a24 */
/* 0x000fc800078e0205 */
/*0140*/ IMAD.WIDE R4, R5, R10, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fe200078e020a */
/*0150*/ STS [R9.X4], R2 ; /* 0x0000000209007388 */
/* 0x004fe80000004800 */
/*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0170*/ LDS R7, [R7.X4] ; /* 0x0000000007077984 */
/* 0x000e280000004800 */
/*0180*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x001fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18transposeOptimizedPfS_ii
.globl _Z18transposeOptimizedPfS_ii
.p2align 8
.type _Z18transposeOptimizedPfS_ii,@function
_Z18transposeOptimizedPfS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v2, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_mul_i32 s15, s15, s3
s_mul_i32 s14, s14, s2
v_add_nc_u32_e32 v3, s15, v2
v_add_nc_u32_e32 v0, s14, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v3
v_cmp_gt_i32_e64 s2, s5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[4:5], null, v3, s5, v[0:1]
v_add_nc_u32_e32 v0, s14, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v0, v0, s4
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[3:4], 2, v[4:5]
v_lshlrev_b32_e32 v5, 2, v2
v_add3_u32 v0, s15, v1, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_load_b32 v3, v[3:4], off
v_lshlrev_b32_e32 v4, 2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u32_u24 v2, v2, 0x84, v4
v_mad_u32_u24 v4, v1, 0x84, v5
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
ds_store_b32 v2, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v2, v4
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18transposeOptimizedPfS_ii
.amdhsa_group_segment_fixed_size 4224
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18transposeOptimizedPfS_ii, .Lfunc_end0-_Z18transposeOptimizedPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4224
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18transposeOptimizedPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18transposeOptimizedPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f61d2_00000000-6_matrix-transposition.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z18transposeOptimizedPfS_iiPfS_ii
.type _Z42__device_stub__Z18transposeOptimizedPfS_iiPfS_ii, @function
_Z42__device_stub__Z18transposeOptimizedPfS_iiPfS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18transposeOptimizedPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z18transposeOptimizedPfS_iiPfS_ii, .-_Z42__device_stub__Z18transposeOptimizedPfS_iiPfS_ii
.globl _Z18transposeOptimizedPfS_ii
.type _Z18transposeOptimizedPfS_ii, @function
_Z18transposeOptimizedPfS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z18transposeOptimizedPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18transposeOptimizedPfS_ii, .-_Z18transposeOptimizedPfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18transposeOptimizedPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18transposeOptimizedPfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix-transposition.hip"
.globl _Z33__device_stub__transposeOptimizedPfS_ii # -- Begin function _Z33__device_stub__transposeOptimizedPfS_ii
.p2align 4, 0x90
.type _Z33__device_stub__transposeOptimizedPfS_ii,@function
_Z33__device_stub__transposeOptimizedPfS_ii: # @_Z33__device_stub__transposeOptimizedPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18transposeOptimizedPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z33__device_stub__transposeOptimizedPfS_ii, .Lfunc_end0-_Z33__device_stub__transposeOptimizedPfS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18transposeOptimizedPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18transposeOptimizedPfS_ii,@object # @_Z18transposeOptimizedPfS_ii
.section .rodata,"a",@progbits
.globl _Z18transposeOptimizedPfS_ii
.p2align 3, 0x0
_Z18transposeOptimizedPfS_ii:
.quad _Z33__device_stub__transposeOptimizedPfS_ii
.size _Z18transposeOptimizedPfS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18transposeOptimizedPfS_ii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__transposeOptimizedPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18transposeOptimizedPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //////////////////////////////
//MultiDimKernelLaunch.cpp
//This program is an example posted online concerning the
//launch of multiple processes in a 2D format. The hope
//is that this program also contains incormation concerning
//the passing and use of 2D arrays using CUDA. This program
//is probably written in C.
/////////////////////////////
////////////////////////////
//Libraries
#include <stdlib.h>
#include <stdio.h>
#include <cuda.h>
///////////////////////////
//Define Kernel
__global__ void kernel(int *array){
int index_x = blockIdx.x * blockDim.x + threadIdx.x;
int index_y = blockIdx.y * blockDim.y + threadIdx.y;
//map 2d indicies to single liner 1d index
int grid_width = gridDim.x * blockDim.x;
int index = index_y * grid_width + index_x; //every value of y goes to next "row"
//map the 2d block indicies to single linear 1d block index
int result = blockIdx.y * gridDim.x + blockIdx.x;
//write out result
array[index] = result;
}
int main(void){
//define size of grid in box x and y direction
int num_elements_x = 16;
int num_elements_y = 16;
//setup size of memory that we will be requesting
int num_bytes = num_elements_x * num_elements_y * sizeof(int);
int *device_array = 0;
int *host_array = 0;
//allocate memory to host and device
host_array = (int*)malloc(num_bytes);
cudaMalloc((void**)&device_array, num_bytes);
//create 2d 4x4 thread blocks
dim3 block_size;
block_size.x = 4;
block_size.y = 4;
//configure a 2d grid
dim3 grid_size;
grid_size.x = num_elements_x / block_size.x;
grid_size.y = num_elements_y / block_size.y;
//gridsize and block size are passed as arugments to kernel
kernel <<<grid_size, block_size>>> (device_array);
//note how system defines 2d run with grid size as "x" and block_size
//(aka number of threads/block) as "y"
//download results and inspect on host
cudaMemcpy(host_array, device_array, num_bytes, cudaMemcpyDeviceToHost);
//print out result in nested loop
for(int row = 0; row < num_elements_y; row++){
for(int col = 0; col < num_elements_x; col++){
printf("%2d ", host_array[row*num_elements_x + col]);
}
printf("\n");
}
printf("\n");
//free memory to be nice
free(host_array);
cudaFree(device_array);
return 0;
} | code for sm_80
Function : _Z6kernelPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002200 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002100 */
/*0060*/ IMAD R0, R2, c[0x0][0x4], R7 ; /* 0x0000010002007a24 */
/* 0x001fe200078e0207 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fc600000001ff */
/*0080*/ IMAD R0, R0, c[0x0][0xc], R5.reuse ; /* 0x0000030000007a24 */
/* 0x102fe400078e0205 */
/*0090*/ IMAD R5, R2, c[0x0][0xc], R5 ; /* 0x0000030002057a24 */
/* 0x000fe400078e0205 */
/*00a0*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x004fc800078e0203 */
/*00b0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0207 */
/*00c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //////////////////////////////
//MultiDimKernelLaunch.cpp
//This program is an example posted online concerning the
//launch of multiple processes in a 2D format. The hope
//is that this program also contains incormation concerning
//the passing and use of 2D arrays using CUDA. This program
//is probably written in C.
/////////////////////////////
////////////////////////////
//Libraries
#include <stdlib.h>
#include <stdio.h>
#include <cuda.h>
///////////////////////////
//Define Kernel
__global__ void kernel(int *array){
int index_x = blockIdx.x * blockDim.x + threadIdx.x;
int index_y = blockIdx.y * blockDim.y + threadIdx.y;
//map 2d indicies to single liner 1d index
int grid_width = gridDim.x * blockDim.x;
int index = index_y * grid_width + index_x; //every value of y goes to next "row"
//map the 2d block indicies to single linear 1d block index
int result = blockIdx.y * gridDim.x + blockIdx.x;
//write out result
array[index] = result;
}
int main(void){
//define size of grid in box x and y direction
int num_elements_x = 16;
int num_elements_y = 16;
//setup size of memory that we will be requesting
int num_bytes = num_elements_x * num_elements_y * sizeof(int);
int *device_array = 0;
int *host_array = 0;
//allocate memory to host and device
host_array = (int*)malloc(num_bytes);
cudaMalloc((void**)&device_array, num_bytes);
//create 2d 4x4 thread blocks
dim3 block_size;
block_size.x = 4;
block_size.y = 4;
//configure a 2d grid
dim3 grid_size;
grid_size.x = num_elements_x / block_size.x;
grid_size.y = num_elements_y / block_size.y;
//gridsize and block size are passed as arugments to kernel
kernel <<<grid_size, block_size>>> (device_array);
//note how system defines 2d run with grid size as "x" and block_size
//(aka number of threads/block) as "y"
//download results and inspect on host
cudaMemcpy(host_array, device_array, num_bytes, cudaMemcpyDeviceToHost);
//print out result in nested loop
for(int row = 0; row < num_elements_y; row++){
for(int col = 0; col < num_elements_x; col++){
printf("%2d ", host_array[row*num_elements_x + col]);
}
printf("\n");
}
printf("\n");
//free memory to be nice
free(host_array);
cudaFree(device_array);
return 0;
} | .file "tmpxft_00129cb9_00000000-6_MultiDimKernelLaunch.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z6kernelPiPi
.type _Z25__device_stub__Z6kernelPiPi, @function
_Z25__device_stub__Z6kernelPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z25__device_stub__Z6kernelPiPi, .-_Z25__device_stub__Z6kernelPiPi
.globl _Z6kernelPi
.type _Z6kernelPi, @function
_Z6kernelPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z6kernelPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelPi, .-_Z6kernelPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%2d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movl $1024, %edi
call malloc@PLT
movq %rax, %r15
leaq 8(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
movl $4, 28(%rsp)
movl $4, 32(%rsp)
movl $4, 16(%rsp)
movl $4, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L12:
movl $2, %ecx
movl $1024, %edx
movq 8(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
leaq 64(%r15), %rbp
leaq 1088(%r15), %r14
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %r13
.L13:
leaq -64(%rbp), %rbx
.L14:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L14
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $64, %rbp
cmpq %r14, %rbp
jne .L13
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r15, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z25__device_stub__Z6kernelPiPi
jmp .L12
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z6kernelPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //////////////////////////////
//MultiDimKernelLaunch.cpp
//This program is an example posted online concerning the
//launch of multiple processes in a 2D format. The hope
//is that this program also contains incormation concerning
//the passing and use of 2D arrays using CUDA. This program
//is probably written in C.
/////////////////////////////
////////////////////////////
//Libraries
#include <stdlib.h>
#include <stdio.h>
#include <cuda.h>
///////////////////////////
//Define Kernel
__global__ void kernel(int *array){
int index_x = blockIdx.x * blockDim.x + threadIdx.x;
int index_y = blockIdx.y * blockDim.y + threadIdx.y;
//map 2d indicies to single liner 1d index
int grid_width = gridDim.x * blockDim.x;
int index = index_y * grid_width + index_x; //every value of y goes to next "row"
//map the 2d block indicies to single linear 1d block index
int result = blockIdx.y * gridDim.x + blockIdx.x;
//write out result
array[index] = result;
}
int main(void){
//define size of grid in box x and y direction
int num_elements_x = 16;
int num_elements_y = 16;
//setup size of memory that we will be requesting
int num_bytes = num_elements_x * num_elements_y * sizeof(int);
int *device_array = 0;
int *host_array = 0;
//allocate memory to host and device
host_array = (int*)malloc(num_bytes);
cudaMalloc((void**)&device_array, num_bytes);
//create 2d 4x4 thread blocks
dim3 block_size;
block_size.x = 4;
block_size.y = 4;
//configure a 2d grid
dim3 grid_size;
grid_size.x = num_elements_x / block_size.x;
grid_size.y = num_elements_y / block_size.y;
//gridsize and block size are passed as arugments to kernel
kernel <<<grid_size, block_size>>> (device_array);
//note how system defines 2d run with grid size as "x" and block_size
//(aka number of threads/block) as "y"
//download results and inspect on host
cudaMemcpy(host_array, device_array, num_bytes, cudaMemcpyDeviceToHost);
//print out result in nested loop
for(int row = 0; row < num_elements_y; row++){
for(int col = 0; col < num_elements_x; col++){
printf("%2d ", host_array[row*num_elements_x + col]);
}
printf("\n");
}
printf("\n");
//free memory to be nice
free(host_array);
cudaFree(device_array);
return 0;
} | //////////////////////////////
//MultiDimKernelLaunch.cpp
//This program is an example posted online concerning the
//launch of multiple processes in a 2D format. The hope
//is that this program also contains incormation concerning
//the passing and use of 2D arrays using CUDA. This program
//is probably written in C.
/////////////////////////////
////////////////////////////
//Libraries
#include <stdlib.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
///////////////////////////
//Define Kernel
__global__ void kernel(int *array){
int index_x = blockIdx.x * blockDim.x + threadIdx.x;
int index_y = blockIdx.y * blockDim.y + threadIdx.y;
//map 2d indicies to single liner 1d index
int grid_width = gridDim.x * blockDim.x;
int index = index_y * grid_width + index_x; //every value of y goes to next "row"
//map the 2d block indicies to single linear 1d block index
int result = blockIdx.y * gridDim.x + blockIdx.x;
//write out result
array[index] = result;
}
int main(void){
//define size of grid in box x and y direction
int num_elements_x = 16;
int num_elements_y = 16;
//setup size of memory that we will be requesting
int num_bytes = num_elements_x * num_elements_y * sizeof(int);
int *device_array = 0;
int *host_array = 0;
//allocate memory to host and device
host_array = (int*)malloc(num_bytes);
hipMalloc((void**)&device_array, num_bytes);
//create 2d 4x4 thread blocks
dim3 block_size;
block_size.x = 4;
block_size.y = 4;
//configure a 2d grid
dim3 grid_size;
grid_size.x = num_elements_x / block_size.x;
grid_size.y = num_elements_y / block_size.y;
//gridsize and block size are passed as arugments to kernel
kernel <<<grid_size, block_size>>> (device_array);
//note how system defines 2d run with grid size as "x" and block_size
//(aka number of threads/block) as "y"
//download results and inspect on host
hipMemcpy(host_array, device_array, num_bytes, hipMemcpyDeviceToHost);
//print out result in nested loop
for(int row = 0; row < num_elements_y; row++){
for(int col = 0; col < num_elements_x; col++){
printf("%2d ", host_array[row*num_elements_x + col]);
}
printf("\n");
}
printf("\n");
//free memory to be nice
free(host_array);
hipFree(device_array);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //////////////////////////////
//MultiDimKernelLaunch.cpp
//This program is an example posted online concerning the
//launch of multiple processes in a 2D format. The hope
//is that this program also contains incormation concerning
//the passing and use of 2D arrays using CUDA. This program
//is probably written in C.
/////////////////////////////
////////////////////////////
//Libraries
#include <stdlib.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
///////////////////////////
//Define Kernel
__global__ void kernel(int *array){
int index_x = blockIdx.x * blockDim.x + threadIdx.x;
int index_y = blockIdx.y * blockDim.y + threadIdx.y;
//map 2d indicies to single liner 1d index
int grid_width = gridDim.x * blockDim.x;
int index = index_y * grid_width + index_x; //every value of y goes to next "row"
//map the 2d block indicies to single linear 1d block index
int result = blockIdx.y * gridDim.x + blockIdx.x;
//write out result
array[index] = result;
}
int main(void){
//define size of grid in box x and y direction
int num_elements_x = 16;
int num_elements_y = 16;
//setup size of memory that we will be requesting
int num_bytes = num_elements_x * num_elements_y * sizeof(int);
int *device_array = 0;
int *host_array = 0;
//allocate memory to host and device
host_array = (int*)malloc(num_bytes);
hipMalloc((void**)&device_array, num_bytes);
//create 2d 4x4 thread blocks
dim3 block_size;
block_size.x = 4;
block_size.y = 4;
//configure a 2d grid
dim3 grid_size;
grid_size.x = num_elements_x / block_size.x;
grid_size.y = num_elements_y / block_size.y;
//gridsize and block size are passed as arugments to kernel
kernel <<<grid_size, block_size>>> (device_array);
//note how system defines 2d run with grid size as "x" and block_size
//(aka number of threads/block) as "y"
//download results and inspect on host
hipMemcpy(host_array, device_array, num_bytes, hipMemcpyDeviceToHost);
//print out result in nested loop
for(int row = 0; row < num_elements_y; row++){
for(int col = 0; col < num_elements_x; col++){
printf("%2d ", host_array[row*num_elements_x + col]);
}
printf("\n");
}
printf("\n");
//free memory to be nice
free(host_array);
hipFree(device_array);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPi
.globl _Z6kernelPi
.p2align 8
.type _Z6kernelPi,@function
_Z6kernelPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b32 s3, s[0:1], 0x8
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s3, s[14:15]
v_mad_u64_u32 v[1:2], null, v3, s2, v[0:1]
s_mul_i32 s2, s3, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_add_i32 s2, s2, s14
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, s2
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPi, .Lfunc_end0-_Z6kernelPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //////////////////////////////
//MultiDimKernelLaunch.cpp
//This program is an example posted online concerning the
//launch of multiple processes in a 2D format. The hope
//is that this program also contains incormation concerning
//the passing and use of 2D arrays using CUDA. This program
//is probably written in C.
/////////////////////////////
////////////////////////////
//Libraries
#include <stdlib.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
///////////////////////////
//Define Kernel
__global__ void kernel(int *array){
int index_x = blockIdx.x * blockDim.x + threadIdx.x;
int index_y = blockIdx.y * blockDim.y + threadIdx.y;
//map 2d indicies to single liner 1d index
int grid_width = gridDim.x * blockDim.x;
int index = index_y * grid_width + index_x; //every value of y goes to next "row"
//map the 2d block indicies to single linear 1d block index
int result = blockIdx.y * gridDim.x + blockIdx.x;
//write out result
array[index] = result;
}
int main(void){
//define size of grid in box x and y direction
int num_elements_x = 16;
int num_elements_y = 16;
//setup size of memory that we will be requesting
int num_bytes = num_elements_x * num_elements_y * sizeof(int);
int *device_array = 0;
int *host_array = 0;
//allocate memory to host and device
host_array = (int*)malloc(num_bytes);
hipMalloc((void**)&device_array, num_bytes);
//create 2d 4x4 thread blocks
dim3 block_size;
block_size.x = 4;
block_size.y = 4;
//configure a 2d grid
dim3 grid_size;
grid_size.x = num_elements_x / block_size.x;
grid_size.y = num_elements_y / block_size.y;
//gridsize and block size are passed as arugments to kernel
kernel <<<grid_size, block_size>>> (device_array);
//note how system defines 2d run with grid size as "x" and block_size
//(aka number of threads/block) as "y"
//download results and inspect on host
hipMemcpy(host_array, device_array, num_bytes, hipMemcpyDeviceToHost);
//print out result in nested loop
for(int row = 0; row < num_elements_y; row++){
for(int col = 0; col < num_elements_x; col++){
printf("%2d ", host_array[row*num_elements_x + col]);
}
printf("\n");
}
printf("\n");
//free memory to be nice
free(host_array);
hipFree(device_array);
return 0;
} | .text
.file "MultiDimKernelLaunch.hip"
.globl _Z21__device_stub__kernelPi # -- Begin function _Z21__device_stub__kernelPi
.p2align 4, 0x90
.type _Z21__device_stub__kernelPi,@function
_Z21__device_stub__kernelPi: # @_Z21__device_stub__kernelPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z6kernelPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPi, .Lfunc_end0-_Z21__device_stub__kernelPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $88, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq $0, 8(%rsp)
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movabsq $17179869188, %rdi # imm = 0x400000004
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z6kernelPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_3 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $16, %r12
jne .LBB1_4
# %bb.5: # in Loop: Header=BB1_3 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq $64, %r14
cmpq $16, %r15
jne .LBB1_3
# %bb.6:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPi,@object # @_Z6kernelPi
.section .rodata,"a",@progbits
.globl _Z6kernelPi
.p2align 3, 0x0
_Z6kernelPi:
.quad _Z21__device_stub__kernelPi
.size _Z6kernelPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%2d "
.size .L.str, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPi"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002200 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002100 */
/*0060*/ IMAD R0, R2, c[0x0][0x4], R7 ; /* 0x0000010002007a24 */
/* 0x001fe200078e0207 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fc600000001ff */
/*0080*/ IMAD R0, R0, c[0x0][0xc], R5.reuse ; /* 0x0000030000007a24 */
/* 0x102fe400078e0205 */
/*0090*/ IMAD R5, R2, c[0x0][0xc], R5 ; /* 0x0000030002057a24 */
/* 0x000fe400078e0205 */
/*00a0*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x004fc800078e0203 */
/*00b0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0207 */
/*00c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPi
.globl _Z6kernelPi
.p2align 8
.type _Z6kernelPi,@function
_Z6kernelPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b32 s3, s[0:1], 0x8
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s3, s[14:15]
v_mad_u64_u32 v[1:2], null, v3, s2, v[0:1]
s_mul_i32 s2, s3, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_add_i32 s2, s2, s14
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, s2
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPi, .Lfunc_end0-_Z6kernelPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00129cb9_00000000-6_MultiDimKernelLaunch.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z6kernelPiPi
.type _Z25__device_stub__Z6kernelPiPi, @function
_Z25__device_stub__Z6kernelPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z25__device_stub__Z6kernelPiPi, .-_Z25__device_stub__Z6kernelPiPi
.globl _Z6kernelPi
.type _Z6kernelPi, @function
_Z6kernelPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z6kernelPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelPi, .-_Z6kernelPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%2d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movl $1024, %edi
call malloc@PLT
movq %rax, %r15
leaq 8(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
movl $4, 28(%rsp)
movl $4, 32(%rsp)
movl $4, 16(%rsp)
movl $4, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L12:
movl $2, %ecx
movl $1024, %edx
movq 8(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
leaq 64(%r15), %rbp
leaq 1088(%r15), %r14
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %r13
.L13:
leaq -64(%rbp), %rbx
.L14:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L14
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $64, %rbp
cmpq %r14, %rbp
jne .L13
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r15, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z25__device_stub__Z6kernelPiPi
jmp .L12
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z6kernelPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "MultiDimKernelLaunch.hip"
.globl _Z21__device_stub__kernelPi # -- Begin function _Z21__device_stub__kernelPi
.p2align 4, 0x90
.type _Z21__device_stub__kernelPi,@function
_Z21__device_stub__kernelPi: # @_Z21__device_stub__kernelPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z6kernelPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPi, .Lfunc_end0-_Z21__device_stub__kernelPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $88, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq $0, 8(%rsp)
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movabsq $17179869188, %rdi # imm = 0x400000004
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z6kernelPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_3 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $16, %r12
jne .LBB1_4
# %bb.5: # in Loop: Header=BB1_3 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq $64, %r14
cmpq $16, %r15
jne .LBB1_3
# %bb.6:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPi,@object # @_Z6kernelPi
.section .rodata,"a",@progbits
.globl _Z6kernelPi
.p2align 3, 0x0
_Z6kernelPi:
.quad _Z21__device_stub__kernelPi
.size _Z6kernelPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%2d "
.size .L.str, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPi"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void matriMult(int* m, int* n, int* p, int size){
// Calculate Row and Coulmn
int row = blockIdx.y * blockDim.y + threadIdx.y;
int column = blockIdx.x * blockDim.x + threadIdx.x;
int p_sum = 0;
for(int i = 0; i < size; i++){
p_sum += m[row * size + i] * n[i * size + column];
}
p[row * size + column] = p_sum;
} | code for sm_80
Function : _Z9matriMultPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002600 */
/*0020*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0080*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R4, R4, c[0x0][0x4], R3 ; /* 0x0000010004047a24 */
/* 0x001fc800078e0203 */
/*00a0*/ IMAD R4, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a24 */
/* 0x000fe400078e02ff */
/*00b0*/ IMAD R2, R2, c[0x0][0x0], R5 ; /* 0x0000000002027a24 */
/* 0x002fe200078e0205 */
/*00c0*/ @!P0 BRA 0xbe0 ; /* 0x00000b1000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R3, R0.reuse, -0x1, RZ ; /* 0xffffffff00037810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300057812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*0100*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fd20000000f00 */
/*0120*/ @!P0 BRA 0xac0 ; /* 0x0000099000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0150*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0160*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fe40000000f00 */
/*0170*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fcc0003f04270 */
/*0180*/ IMAD.WIDE R24, R2, R25, c[0x0][0x168] ; /* 0x00005a0002187625 */
/* 0x000fce00078e0219 */
/*0190*/ @!P0 BRA 0x930 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01a0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01c0*/ @!P1 BRA 0x670 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01e0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*01f0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0200*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0210*/ IMAD.WIDE R12, R4, 0x4, R12 ; /* 0x00000004040c7825 */
/* 0x000fca00078e020c */
/*0220*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0230*/ IMAD.WIDE R10, R0, 0x4, R24 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0218 */
/*0240*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0250*/ IMAD.WIDE R18, R0.reuse, 0x4, R10 ; /* 0x0000000400127825 */
/* 0x040fe200078e020a */
/*0260*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*0270*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*0280*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*0290*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02a0*/ IMAD.WIDE R20, R0.reuse, 0x4, R14 ; /* 0x0000000400147825 */
/* 0x040fe200078e020e */
/*02b0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*02c0*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*02d0*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*02e0*/ IMAD.WIDE R14, R0, 0x4, R20 ; /* 0x00000004000e7825 */
/* 0x001fc600078e0214 */
/*02f0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0300*/ IMAD.WIDE R22, R0.reuse, 0x4, R14 ; /* 0x0000000400167825 */
/* 0x040fe200078e020e */
/*0310*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0320*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0330*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x000fc600078e0216 */
/*0340*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0350*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0360*/ IMAD R29, R29, R27, R28 ; /* 0x0000001b1d1d7224 */
/* 0x004fc600078e021c */
/*0370*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*0380*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*0390*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0218 */
/*03a0*/ IMAD R29, R16, R17, R29 ; /* 0x00000011101d7224 */
/* 0x008fe400078e021d */
/*03b0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fe400078e020e */
/*03c0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*03d0*/ IMAD R29, R18, R19, R29 ; /* 0x00000013121d7224 */
/* 0x010fe400078e021d */
/*03e0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fe400078e0210 */
/*03f0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0400*/ IMAD R26, R26, R7, R29 ; /* 0x000000071a1a7224 */
/* 0x000fc400078e021d */
/*0410*/ IMAD.WIDE R22, R0.reuse, 0x4, R18 ; /* 0x0000000400167825 */
/* 0x042fe200078e0212 */
/*0420*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0430*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0440*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x001fc600078e0216 */
/*0450*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0460*/ IMAD R9, R20, R9, R26 ; /* 0x0000000914097224 */
/* 0x020fc600078e021a */
/*0470*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*0480*/ IMAD R11, R8, R11, R9 ; /* 0x0000000b080b7224 */
/* 0x000fe400078e0209 */
/*0490*/ IMAD.WIDE R8, R0, 0x4, R24 ; /* 0x0000000400087825 */
/* 0x000fe200078e0218 */
/*04a0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04b0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*04c0*/ IMAD R21, R10, R21, R11 ; /* 0x000000150a157224 */
/* 0x000fc600078e020b */
/*04d0*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*04e0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*04f0*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0500*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0510*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0520*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0530*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0540*/ IMAD R9, R28, R27, R21 ; /* 0x0000001b1c097224 */
/* 0x004fc600078e0215 */
/*0550*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0560*/ IMAD.WIDE R20, R0, 0x4, R10 ; /* 0x0000000400147825 */
/* 0x000fca00078e020a */
/*0570*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*0580*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*0590*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05a0*/ IMAD R7, R14, R7, R9 ; /* 0x000000070e077224 */
/* 0x000fc800078e0209 */
/*05b0*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x000fc800078e0207 */
/*05c0*/ IMAD R7, R18, R26, R7 ; /* 0x0000001a12077224 */
/* 0x020fc800078e0207 */
/*05d0*/ IMAD R7, R22, R17, R7 ; /* 0x0000001116077224 */
/* 0x010fe200078e0207 */
/*05e0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*05f0*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fc60007ffe0ff */
/*0600*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0610*/ IMAD R7, R15, R24, R7 ; /* 0x000000180f077224 */
/* 0x008fc800078e0207 */
/*0620*/ IMAD R28, R19, R28, R7 ; /* 0x0000001c131c7224 */
/* 0x004fc800078e0207 */
/*0630*/ IMAD R28, R23, R25, R28 ; /* 0x00000019171c7224 */
/* 0x000fe400078e021c */
/*0640*/ IMAD.WIDE R24, R0, 0x4, R20 ; /* 0x0000000400187825 */
/* 0x000fc800078e0214 */
/*0650*/ IMAD R28, R27, R8, R28 ; /* 0x000000081b1c7224 */
/* 0x000fe200078e021c */
/*0660*/ @P1 BRA 0x1e0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0670*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0680*/ @!P1 BRA 0x910 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*0690*/ IMAD.WIDE R16, R0, 0x4, R24 ; /* 0x0000000400107825 */
/* 0x000fe200078e0218 */
/*06a0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06b0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*06c0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*06d0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fe200078e0210 */
/*06e0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*06f0*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fe200078e0208 */
/*0700*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0710*/ IMAD.WIDE R14, R0.reuse, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x040fe200078e020c */
/*0720*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0730*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0740*/ IMAD.WIDE R10, R0, 0x4, R14 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020e */
/*0750*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0760*/ IMAD.WIDE R16, R0.reuse, 0x4, R10 ; /* 0x0000000400107825 */
/* 0x042fe200078e020a */
/*0770*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*0780*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*0790*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*07a0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07b0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*07c0*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x010fc600078e0212 */
/*07d0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*07e0*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0800*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0810*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0830*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0840*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0850*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*0860*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0870*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0880*/ IMAD R7, R7, R20, R28 ; /* 0x0000001407077224 */
/* 0x004fc800078e021c */
/*0890*/ IMAD R7, R21, R22, R7 ; /* 0x0000001615077224 */
/* 0x008fc800078e0207 */
/*08a0*/ IMAD R7, R23, R26, R7 ; /* 0x0000001a17077224 */
/* 0x020fc800078e0207 */
/*08b0*/ IMAD R7, R14, R27, R7 ; /* 0x0000001b0e077224 */
/* 0x000fc800078e0207 */
/*08c0*/ IMAD R7, R10, R25, R7 ; /* 0x000000190a077224 */
/* 0x000fc800078e0207 */
/*08d0*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x010fc800078e0207 */
/*08e0*/ IMAD R7, R24, R11, R7 ; /* 0x0000000b18077224 */
/* 0x000fe400078e0207 */
/*08f0*/ IMAD.WIDE R24, R0, 0x4, R12 ; /* 0x0000000400187825 */
/* 0x000fc800078e020c */
/*0900*/ IMAD R28, R15, R18, R7 ; /* 0x000000120f1c7224 */
/* 0x000fe400078e0207 */
/*0910*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0920*/ @!P0 BRA 0xac0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0930*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0940*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fe200078e0218 */
/*0950*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0960*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*0970*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fc800078e0208 */
/*0980*/ IMAD.WIDE R12, R0.reuse, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x040fe200078e020e */
/*0990*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09b0*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020c */
/*09c0*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*09d0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*09e0*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*09f0*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a00*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a10*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a20*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a30*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a40*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc60007ffe0ff */
/*0a50*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a60*/ IMAD R7, R25, R7, R28 ; /* 0x0000000719077224 */
/* 0x004fc800078e021c */
/*0a70*/ IMAD R7, R14, R16, R7 ; /* 0x000000100e077224 */
/* 0x008fe400078e0207 */
/*0a80*/ IMAD.WIDE R24, R0, 0x4, R10 ; /* 0x0000000400187825 */
/* 0x000fc800078e020a */
/*0a90*/ IMAD R7, R18, R17, R7 ; /* 0x0000001112077224 */
/* 0x010fc800078e0207 */
/*0aa0*/ IMAD R28, R20, R19, R7 ; /* 0x00000013141c7224 */
/* 0x020fe200078e0207 */
/*0ab0*/ @P0 BRA 0x930 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0ac0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0ad0*/ @!P0 BRA 0xbe0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0ae0*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0af0*/ IADD3 R6, R4, R3, RZ ; /* 0x0000000304067210 */
/* 0x000fe20007ffe0ff */
/*0b00*/ IMAD R3, R3, c[0x0][0x178], R2 ; /* 0x00005e0003037a24 */
/* 0x000fd000078e0202 */
/*0b10*/ IMAD.WIDE R6, R6, R8, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0208 */
/*0b20*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fe200078e0208 */
/*0b30*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fc80000000f00 */
/*0b40*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x000fe20000000f00 */
/*0b50*/ LDG.E R3, [R8.64] ; /* 0x0000000408037981 */
/* 0x0000aa000c1e1900 */
/*0b60*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x0002a2000c1e1900 */
/*0b70*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*0b80*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc40007f3e0ff */
/*0b90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0ba0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fe200078e0208 */
/*0bb0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x002fc60000ffe4ff */
/*0bc0*/ IMAD R28, R3, R6, R28 ; /* 0x00000006031c7224 */
/* 0x004fd000078e021c */
/*0bd0*/ @P0 BRA 0xb40 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0be0*/ IADD3 R2, R2, R4, RZ ; /* 0x0000000402027210 */
/* 0x000fe40007ffe0ff */
/*0bf0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0c00*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0c10*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c20*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c30*/ BRA 0xc30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void matriMult(int* m, int* n, int* p, int size){
// Calculate Row and Coulmn
int row = blockIdx.y * blockDim.y + threadIdx.y;
int column = blockIdx.x * blockDim.x + threadIdx.x;
int p_sum = 0;
for(int i = 0; i < size; i++){
p_sum += m[row * size + i] * n[i * size + column];
}
p[row * size + column] = p_sum;
} | .file "tmpxft_00027d96_00000000-6_matriMult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9matriMultPiS_S_iPiS_S_i
.type _Z33__device_stub__Z9matriMultPiS_S_iPiS_S_i, @function
_Z33__device_stub__Z9matriMultPiS_S_iPiS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9matriMultPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z9matriMultPiS_S_iPiS_S_i, .-_Z33__device_stub__Z9matriMultPiS_S_iPiS_S_i
.globl _Z9matriMultPiS_S_i
.type _Z9matriMultPiS_S_i, @function
_Z9matriMultPiS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9matriMultPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9matriMultPiS_S_i, .-_Z9matriMultPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9matriMultPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9matriMultPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void matriMult(int* m, int* n, int* p, int size){
// Calculate Row and Coulmn
int row = blockIdx.y * blockDim.y + threadIdx.y;
int column = blockIdx.x * blockDim.x + threadIdx.x;
int p_sum = 0;
for(int i = 0; i < size; i++){
p_sum += m[row * size + i] * n[i * size + column];
}
p[row * size + column] = p_sum;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matriMult(int* m, int* n, int* p, int size){
// Calculate Row and Coulmn
int row = blockIdx.y * blockDim.y + threadIdx.y;
int column = blockIdx.x * blockDim.x + threadIdx.x;
int p_sum = 0;
for(int i = 0; i < size; i++){
p_sum += m[row * size + i] * n[i * size + column];
}
p[row * size + column] = p_sum;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matriMult(int* m, int* n, int* p, int size){
// Calculate Row and Coulmn
int row = blockIdx.y * blockDim.y + threadIdx.y;
int column = blockIdx.x * blockDim.x + threadIdx.x;
int p_sum = 0;
for(int i = 0; i < size; i++){
p_sum += m[row * size + i] * n[i * size + column];
}
p[row * size + column] = p_sum;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9matriMultPiS_S_i
.globl _Z9matriMultPiS_S_i
.p2align 8
.type _Z9matriMultPiS_S_i,@function
_Z9matriMultPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v0, s2
s_mov_b32 s3, s2
v_mov_b32_e32 v5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s3, s3, -1
s_cmp_eq_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v8, v[3:4], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s2, v5
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v2, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9matriMultPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9matriMultPiS_S_i, .Lfunc_end0-_Z9matriMultPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9matriMultPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9matriMultPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matriMult(int* m, int* n, int* p, int size){
// Calculate Row and Coulmn
int row = blockIdx.y * blockDim.y + threadIdx.y;
int column = blockIdx.x * blockDim.x + threadIdx.x;
int p_sum = 0;
for(int i = 0; i < size; i++){
p_sum += m[row * size + i] * n[i * size + column];
}
p[row * size + column] = p_sum;
} | .text
.file "matriMult.hip"
.globl _Z24__device_stub__matriMultPiS_S_i # -- Begin function _Z24__device_stub__matriMultPiS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__matriMultPiS_S_i,@function
_Z24__device_stub__matriMultPiS_S_i: # @_Z24__device_stub__matriMultPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9matriMultPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__matriMultPiS_S_i, .Lfunc_end0-_Z24__device_stub__matriMultPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9matriMultPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9matriMultPiS_S_i,@object # @_Z9matriMultPiS_S_i
.section .rodata,"a",@progbits
.globl _Z9matriMultPiS_S_i
.p2align 3, 0x0
_Z9matriMultPiS_S_i:
.quad _Z24__device_stub__matriMultPiS_S_i
.size _Z9matriMultPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9matriMultPiS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__matriMultPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9matriMultPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9matriMultPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002600 */
/*0020*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0080*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R4, R4, c[0x0][0x4], R3 ; /* 0x0000010004047a24 */
/* 0x001fc800078e0203 */
/*00a0*/ IMAD R4, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a24 */
/* 0x000fe400078e02ff */
/*00b0*/ IMAD R2, R2, c[0x0][0x0], R5 ; /* 0x0000000002027a24 */
/* 0x002fe200078e0205 */
/*00c0*/ @!P0 BRA 0xbe0 ; /* 0x00000b1000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R3, R0.reuse, -0x1, RZ ; /* 0xffffffff00037810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300057812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*0100*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fd20000000f00 */
/*0120*/ @!P0 BRA 0xac0 ; /* 0x0000099000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0150*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0160*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fe40000000f00 */
/*0170*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fcc0003f04270 */
/*0180*/ IMAD.WIDE R24, R2, R25, c[0x0][0x168] ; /* 0x00005a0002187625 */
/* 0x000fce00078e0219 */
/*0190*/ @!P0 BRA 0x930 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01a0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01c0*/ @!P1 BRA 0x670 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01e0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*01f0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0200*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0210*/ IMAD.WIDE R12, R4, 0x4, R12 ; /* 0x00000004040c7825 */
/* 0x000fca00078e020c */
/*0220*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0230*/ IMAD.WIDE R10, R0, 0x4, R24 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0218 */
/*0240*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0250*/ IMAD.WIDE R18, R0.reuse, 0x4, R10 ; /* 0x0000000400127825 */
/* 0x040fe200078e020a */
/*0260*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*0270*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*0280*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*0290*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02a0*/ IMAD.WIDE R20, R0.reuse, 0x4, R14 ; /* 0x0000000400147825 */
/* 0x040fe200078e020e */
/*02b0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*02c0*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*02d0*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*02e0*/ IMAD.WIDE R14, R0, 0x4, R20 ; /* 0x00000004000e7825 */
/* 0x001fc600078e0214 */
/*02f0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0300*/ IMAD.WIDE R22, R0.reuse, 0x4, R14 ; /* 0x0000000400167825 */
/* 0x040fe200078e020e */
/*0310*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0320*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0330*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x000fc600078e0216 */
/*0340*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0350*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0360*/ IMAD R29, R29, R27, R28 ; /* 0x0000001b1d1d7224 */
/* 0x004fc600078e021c */
/*0370*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*0380*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*0390*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0218 */
/*03a0*/ IMAD R29, R16, R17, R29 ; /* 0x00000011101d7224 */
/* 0x008fe400078e021d */
/*03b0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fe400078e020e */
/*03c0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*03d0*/ IMAD R29, R18, R19, R29 ; /* 0x00000013121d7224 */
/* 0x010fe400078e021d */
/*03e0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fe400078e0210 */
/*03f0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0400*/ IMAD R26, R26, R7, R29 ; /* 0x000000071a1a7224 */
/* 0x000fc400078e021d */
/*0410*/ IMAD.WIDE R22, R0.reuse, 0x4, R18 ; /* 0x0000000400167825 */
/* 0x042fe200078e0212 */
/*0420*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0430*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0440*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x001fc600078e0216 */
/*0450*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0460*/ IMAD R9, R20, R9, R26 ; /* 0x0000000914097224 */
/* 0x020fc600078e021a */
/*0470*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*0480*/ IMAD R11, R8, R11, R9 ; /* 0x0000000b080b7224 */
/* 0x000fe400078e0209 */
/*0490*/ IMAD.WIDE R8, R0, 0x4, R24 ; /* 0x0000000400087825 */
/* 0x000fe200078e0218 */
/*04a0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04b0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*04c0*/ IMAD R21, R10, R21, R11 ; /* 0x000000150a157224 */
/* 0x000fc600078e020b */
/*04d0*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*04e0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*04f0*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0500*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0510*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0520*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0530*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0540*/ IMAD R9, R28, R27, R21 ; /* 0x0000001b1c097224 */
/* 0x004fc600078e0215 */
/*0550*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0560*/ IMAD.WIDE R20, R0, 0x4, R10 ; /* 0x0000000400147825 */
/* 0x000fca00078e020a */
/*0570*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*0580*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*0590*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05a0*/ IMAD R7, R14, R7, R9 ; /* 0x000000070e077224 */
/* 0x000fc800078e0209 */
/*05b0*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x000fc800078e0207 */
/*05c0*/ IMAD R7, R18, R26, R7 ; /* 0x0000001a12077224 */
/* 0x020fc800078e0207 */
/*05d0*/ IMAD R7, R22, R17, R7 ; /* 0x0000001116077224 */
/* 0x010fe200078e0207 */
/*05e0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*05f0*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fc60007ffe0ff */
/*0600*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0610*/ IMAD R7, R15, R24, R7 ; /* 0x000000180f077224 */
/* 0x008fc800078e0207 */
/*0620*/ IMAD R28, R19, R28, R7 ; /* 0x0000001c131c7224 */
/* 0x004fc800078e0207 */
/*0630*/ IMAD R28, R23, R25, R28 ; /* 0x00000019171c7224 */
/* 0x000fe400078e021c */
/*0640*/ IMAD.WIDE R24, R0, 0x4, R20 ; /* 0x0000000400187825 */
/* 0x000fc800078e0214 */
/*0650*/ IMAD R28, R27, R8, R28 ; /* 0x000000081b1c7224 */
/* 0x000fe200078e021c */
/*0660*/ @P1 BRA 0x1e0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0670*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0680*/ @!P1 BRA 0x910 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*0690*/ IMAD.WIDE R16, R0, 0x4, R24 ; /* 0x0000000400107825 */
/* 0x000fe200078e0218 */
/*06a0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06b0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*06c0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*06d0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fe200078e0210 */
/*06e0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*06f0*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fe200078e0208 */
/*0700*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0710*/ IMAD.WIDE R14, R0.reuse, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x040fe200078e020c */
/*0720*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0730*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0740*/ IMAD.WIDE R10, R0, 0x4, R14 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020e */
/*0750*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0760*/ IMAD.WIDE R16, R0.reuse, 0x4, R10 ; /* 0x0000000400107825 */
/* 0x042fe200078e020a */
/*0770*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*0780*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*0790*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*07a0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07b0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*07c0*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x010fc600078e0212 */
/*07d0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*07e0*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0800*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0810*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0830*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0840*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0850*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*0860*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0870*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0880*/ IMAD R7, R7, R20, R28 ; /* 0x0000001407077224 */
/* 0x004fc800078e021c */
/*0890*/ IMAD R7, R21, R22, R7 ; /* 0x0000001615077224 */
/* 0x008fc800078e0207 */
/*08a0*/ IMAD R7, R23, R26, R7 ; /* 0x0000001a17077224 */
/* 0x020fc800078e0207 */
/*08b0*/ IMAD R7, R14, R27, R7 ; /* 0x0000001b0e077224 */
/* 0x000fc800078e0207 */
/*08c0*/ IMAD R7, R10, R25, R7 ; /* 0x000000190a077224 */
/* 0x000fc800078e0207 */
/*08d0*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x010fc800078e0207 */
/*08e0*/ IMAD R7, R24, R11, R7 ; /* 0x0000000b18077224 */
/* 0x000fe400078e0207 */
/*08f0*/ IMAD.WIDE R24, R0, 0x4, R12 ; /* 0x0000000400187825 */
/* 0x000fc800078e020c */
/*0900*/ IMAD R28, R15, R18, R7 ; /* 0x000000120f1c7224 */
/* 0x000fe400078e0207 */
/*0910*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0920*/ @!P0 BRA 0xac0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0930*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0940*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fe200078e0218 */
/*0950*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0960*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*0970*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fc800078e0208 */
/*0980*/ IMAD.WIDE R12, R0.reuse, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x040fe200078e020e */
/*0990*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09b0*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020c */
/*09c0*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*09d0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*09e0*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*09f0*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a00*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a10*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a20*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a30*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a40*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc60007ffe0ff */
/*0a50*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a60*/ IMAD R7, R25, R7, R28 ; /* 0x0000000719077224 */
/* 0x004fc800078e021c */
/*0a70*/ IMAD R7, R14, R16, R7 ; /* 0x000000100e077224 */
/* 0x008fe400078e0207 */
/*0a80*/ IMAD.WIDE R24, R0, 0x4, R10 ; /* 0x0000000400187825 */
/* 0x000fc800078e020a */
/*0a90*/ IMAD R7, R18, R17, R7 ; /* 0x0000001112077224 */
/* 0x010fc800078e0207 */
/*0aa0*/ IMAD R28, R20, R19, R7 ; /* 0x00000013141c7224 */
/* 0x020fe200078e0207 */
/*0ab0*/ @P0 BRA 0x930 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0ac0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0ad0*/ @!P0 BRA 0xbe0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0ae0*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0af0*/ IADD3 R6, R4, R3, RZ ; /* 0x0000000304067210 */
/* 0x000fe20007ffe0ff */
/*0b00*/ IMAD R3, R3, c[0x0][0x178], R2 ; /* 0x00005e0003037a24 */
/* 0x000fd000078e0202 */
/*0b10*/ IMAD.WIDE R6, R6, R8, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0208 */
/*0b20*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fe200078e0208 */
/*0b30*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fc80000000f00 */
/*0b40*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x000fe20000000f00 */
/*0b50*/ LDG.E R3, [R8.64] ; /* 0x0000000408037981 */
/* 0x0000aa000c1e1900 */
/*0b60*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x0002a2000c1e1900 */
/*0b70*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*0b80*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc40007f3e0ff */
/*0b90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0ba0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fe200078e0208 */
/*0bb0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x002fc60000ffe4ff */
/*0bc0*/ IMAD R28, R3, R6, R28 ; /* 0x00000006031c7224 */
/* 0x004fd000078e021c */
/*0bd0*/ @P0 BRA 0xb40 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0be0*/ IADD3 R2, R2, R4, RZ ; /* 0x0000000402027210 */
/* 0x000fe40007ffe0ff */
/*0bf0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0c00*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0c10*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c20*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c30*/ BRA 0xc30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9matriMultPiS_S_i
.globl _Z9matriMultPiS_S_i
.p2align 8
.type _Z9matriMultPiS_S_i,@function
_Z9matriMultPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v0, s2
s_mov_b32 s3, s2
v_mov_b32_e32 v5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s3, s3, -1
s_cmp_eq_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v8, v[3:4], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s2, v5
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v2, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9matriMultPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9matriMultPiS_S_i, .Lfunc_end0-_Z9matriMultPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9matriMultPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9matriMultPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00027d96_00000000-6_matriMult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9matriMultPiS_S_iPiS_S_i
.type _Z33__device_stub__Z9matriMultPiS_S_iPiS_S_i, @function
_Z33__device_stub__Z9matriMultPiS_S_iPiS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9matriMultPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z9matriMultPiS_S_iPiS_S_i, .-_Z33__device_stub__Z9matriMultPiS_S_iPiS_S_i
.globl _Z9matriMultPiS_S_i
.type _Z9matriMultPiS_S_i, @function
_Z9matriMultPiS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9matriMultPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9matriMultPiS_S_i, .-_Z9matriMultPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9matriMultPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9matriMultPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matriMult.hip"
.globl _Z24__device_stub__matriMultPiS_S_i # -- Begin function _Z24__device_stub__matriMultPiS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__matriMultPiS_S_i,@function
_Z24__device_stub__matriMultPiS_S_i: # @_Z24__device_stub__matriMultPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9matriMultPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__matriMultPiS_S_i, .Lfunc_end0-_Z24__device_stub__matriMultPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9matriMultPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9matriMultPiS_S_i,@object # @_Z9matriMultPiS_S_i
.section .rodata,"a",@progbits
.globl _Z9matriMultPiS_S_i
.p2align 3, 0x0
_Z9matriMultPiS_S_i:
.quad _Z24__device_stub__matriMultPiS_S_i
.size _Z9matriMultPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9matriMultPiS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__matriMultPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9matriMultPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#define N (1024 * 1024)
#define FULL_DATA_SIZE (N * 20)
using namespace std;
#define CUDA_CHECK_RETURN(value) {\
cudaError_t _m_cudaStat = value;\
if (_m_cudaStat != cudaSuccess) {\
fprintf(stderr, "Error %s at line %d in file %s\n", cudaGetErrorString(_m_cudaStat), __LINE__, __FILE__);\
exit(1);\
}}
__global__ void kernel(int *a, int *b, int *c)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < N) {
int idx1 = (idx + 1) % 256;
int idx2 = (idx + 2) % 256;
float as = (a[idx] + a[idx1] + a[idx2]) / 3.0f;
float bs = (b[idx] + b[idx1] + b[idx2]) / 3.0f;
c[idx] = (as + bs) / 2;
}
}
int main()
{
cudaDeviceProp prop;
int whichDevice;
cudaGetDevice(&whichDevice);
cudaGetDeviceProperties(&prop, whichDevice);
if (!prop.deviceOverlap) {
cout << "Device does not support overlapping" << endl;
return 0;
}
int *host_a, *host_b, *host_c;
int *dev_a, *dev_b, *dev_c;
cudaHostAlloc((void**)&dev_a, FULL_DATA_SIZE * sizeof(int), cudaHostAllocDefault);
cudaHostAlloc((void**)&dev_b, FULL_DATA_SIZE * sizeof(int), cudaHostAllocDefault);
cudaHostAlloc((void**)&dev_c, FULL_DATA_SIZE * sizeof(int), cudaHostAllocDefault);
cudaHostAlloc((void**)&host_a, FULL_DATA_SIZE * sizeof(int), cudaHostAllocDefault);
cudaHostAlloc((void**)&host_b, FULL_DATA_SIZE * sizeof(int), cudaHostAllocDefault);
cudaHostAlloc((void**)&host_c, FULL_DATA_SIZE * sizeof(int), cudaHostAllocDefault);
cudaStream_t stream;
cudaStreamCreate(&stream);
float elapsedTime;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
for (int i = 0; i < FULL_DATA_SIZE; i += N) {
cudaMemcpyAsync(dev_a, host_a + i, N * sizeof(int), cudaMemcpyHostToDevice, stream);
cudaMemcpyAsync(dev_b, host_b + i, N * sizeof(int), cudaMemcpyHostToDevice, stream);
kernel <<< N / 256, 256, 0, stream >>> (dev_a, dev_b, dev_c);
cudaMemcpyAsync(host_c + i, dev_c, N * sizeof(int), cudaMemcpyDeviceToHost, stream);
}
cudaStreamSynchronize(stream);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
CUDA_CHECK_RETURN(cudaDeviceSynchronize());
CUDA_CHECK_RETURN(cudaGetLastError());
cudaEventElapsedTime(&elapsedTime, start, stop);
cout << "time: " << elapsedTime << " ms" << endl;
} | code for sm_80
Function : _Z6kernelPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, 0xfffff, PT ; /* 0x000fffff0000780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R3, R0.reuse, 0x1, RZ ; /* 0x0000000100037810 */
/* 0x040fe20007ffe0ff */
/*0070*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0080*/ IADD3 R4, R0, 0x2, RZ ; /* 0x0000000200047810 */
/* 0x000fe20007ffe0ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ SHF.R.S32.HI R2, RZ, 0x1f, R3 ; /* 0x0000001fff027819 */
/* 0x000fe40000011403 */
/*00b0*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fe40000011404 */
/*00c0*/ LEA.HI R2, R2, R3, RZ, 0x8 ; /* 0x0000000302027211 */
/* 0x000fe400078f40ff */
/*00d0*/ LEA.HI R5, R5, R4, RZ, 0x8 ; /* 0x0000000405057211 */
/* 0x000fc400078f40ff */
/*00e0*/ LOP3.LUT R2, R2, 0xffffff00, RZ, 0xc0, !PT ; /* 0xffffff0002027812 */
/* 0x000fe400078ec0ff */
/*00f0*/ LOP3.LUT R5, R5, 0xffffff00, RZ, 0xc0, !PT ; /* 0xffffff0005057812 */
/* 0x000fc600078ec0ff */
/*0100*/ IMAD.IADD R3, R3, 0x1, -R2 ; /* 0x0000000103037824 */
/* 0x000fe400078e0a02 */
/*0110*/ IMAD.IADD R2, R4, 0x1, -R5 ; /* 0x0000000104027824 */
/* 0x000fe400078e0a05 */
/*0120*/ IMAD.WIDE R4, R0, R9, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e0209 */
/*0130*/ IMAD.WIDE R6, R3, R9.reuse, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x080fe400078e0209 */
/*0140*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*0150*/ IMAD.WIDE R8, R2, R9, c[0x0][0x160] ; /* 0x0000580002087625 */
/* 0x000fe400078e0209 */
/*0160*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*0170*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1900 */
/*0180*/ IMAD.MOV.U32 R12, RZ, RZ, 0x3eaaaaab ; /* 0x3eaaaaabff0c7424 */
/* 0x000fc400078e00ff */
/*0190*/ IMAD.MOV.U32 R13, RZ, RZ, 0x40400000 ; /* 0x40400000ff0d7424 */
/* 0x000fc800078e00ff */
/*01a0*/ FFMA R11, R12, -R13, 1 ; /* 0x3f8000000c0b7423 */
/* 0x000fc8000000080d */
/*01b0*/ FFMA R11, R11, R12, 0.3333333432674407959 ; /* 0x3eaaaaab0b0b7423 */
/* 0x000fe2000000000c */
/*01c0*/ BSSY B0, 0x280 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*01d0*/ IADD3 R10, R8, R6, R5 ; /* 0x00000006080a7210 */
/* 0x004fcc0007ffe005 */
/*01e0*/ I2F R10, R10 ; /* 0x0000000a000a7306 */
/* 0x000e300000201400 */
/*01f0*/ FCHK P0, R10, 3 ; /* 0x404000000a007902 */
/* 0x001e220000000000 */
/*0200*/ FFMA R12, R10, R11, RZ ; /* 0x0000000b0a0c7223 */
/* 0x000fc800000000ff */
/*0210*/ FFMA R4, R12, -3, R10 ; /* 0xc04000000c047823 */
/* 0x000fc8000000000a */
/*0220*/ FFMA R4, R11, R4, R12 ; /* 0x000000040b047223 */
/* 0x000fe2000000000c */
/*0230*/ @!P0 BRA 0x270 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*0240*/ MOV R6, 0x260 ; /* 0x0000026000067802 */
/* 0x000fe40000000f00 */
/*0250*/ CALL.REL.NOINC 0x470 ; /* 0x0000021000007944 */
/* 0x000fea0003c00000 */
/*0260*/ IMAD.MOV.U32 R4, RZ, RZ, R5 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0005 */
/*0270*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0280*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0290*/ IMAD.WIDE R8, R3, R5, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fc800078e0205 */
/*02a0*/ IMAD.WIDE R6, R0, R5.reuse, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x080fe400078e0205 */
/*02b0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea4000c1e1900 */
/*02c0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fe400078e0205 */
/*02d0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea8000c1e1900 */
/*02e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*02f0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x3eaaaaab ; /* 0x3eaaaaabff0a7424 */
/* 0x000fc400078e00ff */
/*0300*/ IMAD.MOV.U32 R13, RZ, RZ, 0x40400000 ; /* 0x40400000ff0d7424 */
/* 0x000fc800078e00ff */
/*0310*/ FFMA R11, R10, -R13, 1 ; /* 0x3f8000000a0b7423 */
/* 0x000fc8000000080d */
/*0320*/ FFMA R12, R11, R10, 0.3333333432674407959 ; /* 0x3eaaaaab0b0c7423 */
/* 0x000fe2000000000a */
/*0330*/ BSSY B0, 0x400 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*0340*/ IADD3 R5, R2, R8, R7 ; /* 0x0000000802057210 */
/* 0x004fcc0007ffe007 */
/*0350*/ I2F R5, R5 ; /* 0x0000000500057306 */
/* 0x000e300000201400 */
/*0360*/ FCHK P0, R5, 3 ; /* 0x4040000005007902 */
/* 0x001e220000000000 */
/*0370*/ FFMA R10, R12, R5, RZ ; /* 0x000000050c0a7223 */
/* 0x000fc800000000ff */
/*0380*/ FFMA R9, R10, -3, R5 ; /* 0xc04000000a097823 */
/* 0x000fc80000000005 */
/*0390*/ FFMA R9, R12, R9, R10 ; /* 0x000000090c097223 */
/* 0x000fe2000000000a */
/*03a0*/ @!P0 BRA 0x3f0 ; /* 0x0000004000008947 */
/* 0x001fea0003800000 */
/*03b0*/ IMAD.MOV.U32 R10, RZ, RZ, R5 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0005 */
/*03c0*/ MOV R6, 0x3e0 ; /* 0x000003e000067802 */
/* 0x000fe40000000f00 */
/*03d0*/ CALL.REL.NOINC 0x470 ; /* 0x0000009000007944 */
/* 0x000fea0003c00000 */
/*03e0*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x001fe400078e0005 */
/*03f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0400*/ FADD R4, R9, R4 ; /* 0x0000000409047221 */
/* 0x000fe40000000000 */
/*0410*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*0420*/ FMUL R4, R4, 0.5 ; /* 0x3f00000004047820 */
/* 0x000fe40000400000 */
/*0430*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fe400078e0203 */
/*0440*/ F2I.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000e26000020f100 */
/*0450*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0460*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0470*/ SHF.R.U32.HI R7, RZ, 0x17, R13.reuse ; /* 0x00000017ff077819 */
/* 0x100fe2000001160d */
/*0480*/ BSSY B1, 0xad0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0490*/ SHF.R.U32.HI R5, RZ, 0x17, R10 ; /* 0x00000017ff057819 */
/* 0x000fe2000001160a */
/*04a0*/ IMAD.MOV.U32 R8, RZ, RZ, R13 ; /* 0x000000ffff087224 */
/* 0x000fe200078e000d */
/*04b0*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fc400078ec0ff */
/*04c0*/ LOP3.LUT R14, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff050e7812 */
/* 0x000fe200078ec0ff */
/*04d0*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000a */
/*04e0*/ IADD3 R11, R7, -0x1, RZ ; /* 0xffffffff070b7810 */
/* 0x000fe40007ffe0ff */
/*04f0*/ IADD3 R12, R14, -0x1, RZ ; /* 0xffffffff0e0c7810 */
/* 0x000fe40007ffe0ff */
/*0500*/ ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ; /* 0x000000fd0b00780c */
/* 0x000fc80003f04070 */
/*0510*/ ISETP.GT.U32.OR P0, PT, R12, 0xfd, P0 ; /* 0x000000fd0c00780c */
/* 0x000fda0000704470 */
/*0520*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*0530*/ @!P0 BRA 0x6b0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0540*/ FSETP.GTU.FTZ.AND P0, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fe40003f1c200 */
/*0550*/ FSETP.GTU.FTZ.AND P1, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fc80003f3c200 */
/*0560*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0570*/ @P0 BRA 0xab0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0580*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R5, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c805 */
/*0590*/ @!P0 BRA 0xa90 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*05a0*/ FSETP.NEU.FTZ.AND P2, PT, |R10|.reuse, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x040fe40003f5d200 */
/*05b0*/ FSETP.NEU.FTZ.AND P1, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fe40003f3d200 */
/*05c0*/ FSETP.NEU.FTZ.AND P0, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fd60003f1d200 */
/*05d0*/ @!P1 BRA !P2, 0xa90 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*05e0*/ LOP3.LUT P2, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fc8000784c0ff */
/*05f0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0600*/ @P1 BRA 0xa70 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0610*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*0620*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0630*/ @P0 BRA 0xa40 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0640*/ ISETP.GE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f06270 */
/*0650*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f26270 */
/*0660*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*0670*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*0680*/ @!P0 FFMA R5, R10, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000a058823 */
/* 0x000fe400000000ff */
/*0690*/ @!P1 FFMA R8, R13, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000d089823 */
/* 0x000fe200000000ff */
/*06a0*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*06b0*/ LEA R11, R7, 0xc0800000, 0x17 ; /* 0xc0800000070b7811 */
/* 0x000fe200078eb8ff */
/*06c0*/ BSSY B2, 0xa30 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*06d0*/ IMAD.IADD R11, R8, 0x1, -R11 ; /* 0x00000001080b7824 */
/* 0x000fe200078e0a0b */
/*06e0*/ IADD3 R8, R14, -0x7f, RZ ; /* 0xffffff810e087810 */
/* 0x000fc60007ffe0ff */
/*06f0*/ MUFU.RCP R10, R11 ; /* 0x0000000b000a7308 */
/* 0x000e220000001000 */
/*0700*/ FADD.FTZ R12, -R11, -RZ ; /* 0x800000ff0b0c7221 */
/* 0x000fe40000010100 */
/*0710*/ IMAD R5, R8.reuse, -0x800000, R5 ; /* 0xff80000008057824 */
/* 0x040fe200078e0205 */
/*0720*/ IADD3 R8, R8, 0x7f, -R7 ; /* 0x0000007f08087810 */
/* 0x000fca0007ffe807 */
/*0730*/ IMAD.IADD R8, R8, 0x1, R9 ; /* 0x0000000108087824 */
/* 0x000fe400078e0209 */
/*0740*/ FFMA R13, R10, R12, 1 ; /* 0x3f8000000a0d7423 */
/* 0x001fc8000000000c */
/*0750*/ FFMA R14, R10, R13, R10 ; /* 0x0000000d0a0e7223 */
/* 0x000fc8000000000a */
/*0760*/ FFMA R10, R5, R14, RZ ; /* 0x0000000e050a7223 */
/* 0x000fc800000000ff */
/*0770*/ FFMA R13, R12, R10, R5 ; /* 0x0000000a0c0d7223 */
/* 0x000fc80000000005 */
/*0780*/ FFMA R13, R14, R13, R10 ; /* 0x0000000d0e0d7223 */
/* 0x000fc8000000000a */
/*0790*/ FFMA R12, R12, R13, R5 ; /* 0x0000000d0c0c7223 */
/* 0x000fc80000000005 */
/*07a0*/ FFMA R5, R14, R12, R13 ; /* 0x0000000c0e057223 */
/* 0x000fca000000000d */
/*07b0*/ SHF.R.U32.HI R7, RZ, 0x17, R5 ; /* 0x00000017ff077819 */
/* 0x000fc80000011605 */
/*07c0*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fca00078ec0ff */
/*07d0*/ IMAD.IADD R11, R7, 0x1, R8 ; /* 0x00000001070b7824 */
/* 0x000fca00078e0208 */
/*07e0*/ IADD3 R7, R11, -0x1, RZ ; /* 0xffffffff0b077810 */
/* 0x000fc80007ffe0ff */
/*07f0*/ ISETP.GE.U32.AND P0, PT, R7, 0xfe, PT ; /* 0x000000fe0700780c */
/* 0x000fda0003f06070 */
/*0800*/ @!P0 BRA 0xa10 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0810*/ ISETP.GT.AND P0, PT, R11, 0xfe, PT ; /* 0x000000fe0b00780c */
/* 0x000fda0003f04270 */
/*0820*/ @P0 BRA 0x9e0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0830*/ ISETP.GE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fda0003f06270 */
/*0840*/ @P0 BRA 0xa20 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0850*/ ISETP.GE.AND P0, PT, R11, -0x18, PT ; /* 0xffffffe80b00780c */
/* 0x000fe40003f06270 */
/*0860*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fd600078ec0ff */
/*0870*/ @!P0 BRA 0xa20 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0880*/ FFMA.RZ R7, R14.reuse, R12.reuse, R13.reuse ; /* 0x0000000c0e077223 */
/* 0x1c0fe2000000c00d */
/*0890*/ IADD3 R10, R11.reuse, 0x20, RZ ; /* 0x000000200b0a7810 */
/* 0x040fe20007ffe0ff */
/*08a0*/ FFMA.RM R8, R14.reuse, R12.reuse, R13.reuse ; /* 0x0000000c0e087223 */
/* 0x1c0fe2000000400d */
/*08b0*/ ISETP.NE.AND P2, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f45270 */
/*08c0*/ LOP3.LUT R9, R7, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff07097812 */
/* 0x000fe200078ec0ff */
/*08d0*/ FFMA.RP R7, R14, R12, R13 ; /* 0x0000000c0e077223 */
/* 0x000fe2000000800d */
/*08e0*/ ISETP.NE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f25270 */
/*08f0*/ IMAD.MOV R11, RZ, RZ, -R11 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0a0b */
/*0900*/ LOP3.LUT R9, R9, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000009097812 */
/* 0x000fe400078efcff */
/*0910*/ FSETP.NEU.FTZ.AND P0, PT, R7, R8, PT ; /* 0x000000080700720b */
/* 0x000fc40003f1d000 */
/*0920*/ SHF.L.U32 R10, R9, R10, RZ ; /* 0x0000000a090a7219 */
/* 0x000fe400000006ff */
/*0930*/ SEL R8, R11, RZ, P2 ; /* 0x000000ff0b087207 */
/* 0x000fe40001000000 */
/*0940*/ ISETP.NE.AND P1, PT, R10, RZ, P1 ; /* 0x000000ff0a00720c */
/* 0x000fe40000f25270 */
/*0950*/ SHF.R.U32.HI R8, RZ, R8, R9 ; /* 0x00000008ff087219 */
/* 0x000fe40000011609 */
/*0960*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0970*/ SHF.R.U32.HI R10, RZ, 0x1, R8 ; /* 0x00000001ff0a7819 */
/* 0x000fc40000011608 */
/*0980*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fc80004000000 */
/*0990*/ LOP3.LUT R7, R7, 0x1, R10, 0xf8, !PT ; /* 0x0000000107077812 */
/* 0x000fc800078ef80a */
/*09a0*/ LOP3.LUT R7, R7, R8, RZ, 0xc0, !PT ; /* 0x0000000807077212 */
/* 0x000fca00078ec0ff */
/*09b0*/ IMAD.IADD R10, R10, 0x1, R7 ; /* 0x000000010a0a7824 */
/* 0x000fca00078e0207 */
/*09c0*/ LOP3.LUT R5, R10, R5, RZ, 0xfc, !PT ; /* 0x000000050a057212 */
/* 0x000fe200078efcff */
/*09d0*/ BRA 0xa20 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*09e0*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fc800078ec0ff */
/*09f0*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*0a00*/ BRA 0xa20 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0a10*/ IMAD R5, R8, 0x800000, R5 ; /* 0x0080000008057824 */
/* 0x000fe400078e0205 */
/*0a20*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0a30*/ BRA 0xac0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0a40*/ LOP3.LUT R5, R8, 0x80000000, R5, 0x48, !PT ; /* 0x8000000008057812 */
/* 0x000fc800078e4805 */
/*0a50*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*0a60*/ BRA 0xac0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0a70*/ LOP3.LUT R5, R8, 0x80000000, R5, 0x48, !PT ; /* 0x8000000008057812 */
/* 0x000fe200078e4805 */
/*0a80*/ BRA 0xac0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0a90*/ MUFU.RSQ R5, -QNAN ; /* 0xffc0000000057908 */
/* 0x000e220000001400 */
/*0aa0*/ BRA 0xac0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0ab0*/ FADD.FTZ R5, R10, R13 ; /* 0x0000000d0a057221 */
/* 0x000fe40000010000 */
/*0ac0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0ad0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc800078e00ff */
/*0ae0*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff51006007950 */
/* 0x000fea0003c3ffff */
/*0af0*/ BRA 0xaf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#define N (1024 * 1024)
#define FULL_DATA_SIZE (N * 20)
using namespace std;
#define CUDA_CHECK_RETURN(value) {\
cudaError_t _m_cudaStat = value;\
if (_m_cudaStat != cudaSuccess) {\
fprintf(stderr, "Error %s at line %d in file %s\n", cudaGetErrorString(_m_cudaStat), __LINE__, __FILE__);\
exit(1);\
}}
__global__ void kernel(int *a, int *b, int *c)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < N) {
int idx1 = (idx + 1) % 256;
int idx2 = (idx + 2) % 256;
float as = (a[idx] + a[idx1] + a[idx2]) / 3.0f;
float bs = (b[idx] + b[idx1] + b[idx2]) / 3.0f;
c[idx] = (as + bs) / 2;
}
}
int main()
{
cudaDeviceProp prop;
int whichDevice;
cudaGetDevice(&whichDevice);
cudaGetDeviceProperties(&prop, whichDevice);
if (!prop.deviceOverlap) {
cout << "Device does not support overlapping" << endl;
return 0;
}
int *host_a, *host_b, *host_c;
int *dev_a, *dev_b, *dev_c;
cudaHostAlloc((void**)&dev_a, FULL_DATA_SIZE * sizeof(int), cudaHostAllocDefault);
cudaHostAlloc((void**)&dev_b, FULL_DATA_SIZE * sizeof(int), cudaHostAllocDefault);
cudaHostAlloc((void**)&dev_c, FULL_DATA_SIZE * sizeof(int), cudaHostAllocDefault);
cudaHostAlloc((void**)&host_a, FULL_DATA_SIZE * sizeof(int), cudaHostAllocDefault);
cudaHostAlloc((void**)&host_b, FULL_DATA_SIZE * sizeof(int), cudaHostAllocDefault);
cudaHostAlloc((void**)&host_c, FULL_DATA_SIZE * sizeof(int), cudaHostAllocDefault);
cudaStream_t stream;
cudaStreamCreate(&stream);
float elapsedTime;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
for (int i = 0; i < FULL_DATA_SIZE; i += N) {
cudaMemcpyAsync(dev_a, host_a + i, N * sizeof(int), cudaMemcpyHostToDevice, stream);
cudaMemcpyAsync(dev_b, host_b + i, N * sizeof(int), cudaMemcpyHostToDevice, stream);
kernel <<< N / 256, 256, 0, stream >>> (dev_a, dev_b, dev_c);
cudaMemcpyAsync(host_c + i, dev_c, N * sizeof(int), cudaMemcpyDeviceToHost, stream);
}
cudaStreamSynchronize(stream);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
CUDA_CHECK_RETURN(cudaDeviceSynchronize());
CUDA_CHECK_RETURN(cudaGetLastError());
cudaEventElapsedTime(&elapsedTime, start, stop);
cout << "time: " << elapsedTime << " ms" << endl;
} | .file "tmpxft_0012a151_00000000-6_memcpyPageLocked.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6kernelPiS_S_PiS_S_
.type _Z29__device_stub__Z6kernelPiS_S_PiS_S_, @function
_Z29__device_stub__Z6kernelPiS_S_PiS_S_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernelPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z29__device_stub__Z6kernelPiS_S_PiS_S_, .-_Z29__device_stub__Z6kernelPiS_S_PiS_S_
.globl _Z6kernelPiS_S_
.type _Z6kernelPiS_S_, @function
_Z6kernelPiS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6kernelPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z6kernelPiS_S_, .-_Z6kernelPiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Device does not support overlapping"
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/VladislavMamonov/cuda/main/lab6/memcpyPageLocked.cu"
.align 8
.LC2:
.string "Error %s at line %d in file %s\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "time: "
.LC4:
.string " ms"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1152, %rsp
.cfi_def_cfa_offset 1168
movq %fs:40, %rax
movq %rax, 1144(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDevice@PLT
leaq 112(%rsp), %rdi
movl 12(%rsp), %esi
call cudaGetDeviceProperties_v2@PLT
cmpl $0, 496(%rsp)
je .L21
leaq 40(%rsp), %rdi
movl $0, %edx
movl $83886080, %esi
call cudaHostAlloc@PLT
leaq 48(%rsp), %rdi
movl $0, %edx
movl $83886080, %esi
call cudaHostAlloc@PLT
leaq 56(%rsp), %rdi
movl $0, %edx
movl $83886080, %esi
call cudaHostAlloc@PLT
leaq 16(%rsp), %rdi
movl $0, %edx
movl $83886080, %esi
call cudaHostAlloc@PLT
leaq 24(%rsp), %rdi
movl $0, %edx
movl $83886080, %esi
call cudaHostAlloc@PLT
leaq 32(%rsp), %rdi
movl $0, %edx
movl $83886080, %esi
call cudaHostAlloc@PLT
leaq 64(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
leaq 80(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %ebx
jmp .L15
.L21:
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L13
.L14:
movq %rbx, %rdi
addq 32(%rsp), %rdi
movq 64(%rsp), %r8
movl $2, %ecx
movl $4194304, %edx
movq 56(%rsp), %rsi
call cudaMemcpyAsync@PLT
addq $4194304, %rbx
cmpq $83886080, %rbx
je .L22
.L15:
movq %rbx, %rsi
addq 16(%rsp), %rsi
movq 64(%rsp), %r8
movl $1, %ecx
movl $4194304, %edx
movq 40(%rsp), %rdi
call cudaMemcpyAsync@PLT
movq %rbx, %rsi
addq 24(%rsp), %rsi
movq 64(%rsp), %r8
movl $1, %ecx
movl $4194304, %edx
movq 48(%rsp), %rdi
call cudaMemcpyAsync@PLT
movl $256, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $4096, 88(%rsp)
movl $1, 92(%rsp)
movq 64(%rsp), %r9
movl $0, %r8d
movq 100(%rsp), %rdx
movl $1, %ecx
movq 88(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L14
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z29__device_stub__Z6kernelPiS_S_PiS_S_
jmp .L14
.L22:
movq 64(%rsp), %rdi
call cudaStreamSynchronize@PLT
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
movq 80(%rsp), %rdi
call cudaEventSynchronize@PLT
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L23
call cudaGetLastError@PLT
testl %eax, %eax
jne .L24
leaq 100(%rsp), %rdi
movq 80(%rsp), %rdx
movq 72(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 100(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L13:
movq 1144(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $1152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %r9
movl $76, %r8d
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L24:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %r9
movl $77, %r8d
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z6kernelPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#define N (1024 * 1024)
#define FULL_DATA_SIZE (N * 20)
using namespace std;
#define CUDA_CHECK_RETURN(value) {\
cudaError_t _m_cudaStat = value;\
if (_m_cudaStat != cudaSuccess) {\
fprintf(stderr, "Error %s at line %d in file %s\n", cudaGetErrorString(_m_cudaStat), __LINE__, __FILE__);\
exit(1);\
}}
__global__ void kernel(int *a, int *b, int *c)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < N) {
int idx1 = (idx + 1) % 256;
int idx2 = (idx + 2) % 256;
float as = (a[idx] + a[idx1] + a[idx2]) / 3.0f;
float bs = (b[idx] + b[idx1] + b[idx2]) / 3.0f;
c[idx] = (as + bs) / 2;
}
}
int main()
{
cudaDeviceProp prop;
int whichDevice;
cudaGetDevice(&whichDevice);
cudaGetDeviceProperties(&prop, whichDevice);
if (!prop.deviceOverlap) {
cout << "Device does not support overlapping" << endl;
return 0;
}
int *host_a, *host_b, *host_c;
int *dev_a, *dev_b, *dev_c;
cudaHostAlloc((void**)&dev_a, FULL_DATA_SIZE * sizeof(int), cudaHostAllocDefault);
cudaHostAlloc((void**)&dev_b, FULL_DATA_SIZE * sizeof(int), cudaHostAllocDefault);
cudaHostAlloc((void**)&dev_c, FULL_DATA_SIZE * sizeof(int), cudaHostAllocDefault);
cudaHostAlloc((void**)&host_a, FULL_DATA_SIZE * sizeof(int), cudaHostAllocDefault);
cudaHostAlloc((void**)&host_b, FULL_DATA_SIZE * sizeof(int), cudaHostAllocDefault);
cudaHostAlloc((void**)&host_c, FULL_DATA_SIZE * sizeof(int), cudaHostAllocDefault);
cudaStream_t stream;
cudaStreamCreate(&stream);
float elapsedTime;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
for (int i = 0; i < FULL_DATA_SIZE; i += N) {
cudaMemcpyAsync(dev_a, host_a + i, N * sizeof(int), cudaMemcpyHostToDevice, stream);
cudaMemcpyAsync(dev_b, host_b + i, N * sizeof(int), cudaMemcpyHostToDevice, stream);
kernel <<< N / 256, 256, 0, stream >>> (dev_a, dev_b, dev_c);
cudaMemcpyAsync(host_c + i, dev_c, N * sizeof(int), cudaMemcpyDeviceToHost, stream);
}
cudaStreamSynchronize(stream);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
CUDA_CHECK_RETURN(cudaDeviceSynchronize());
CUDA_CHECK_RETURN(cudaGetLastError());
cudaEventElapsedTime(&elapsedTime, start, stop);
cout << "time: " << elapsedTime << " ms" << endl;
} | #include <hip/hip_runtime.h>
#include <iostream>
#define N (1024 * 1024)
#define FULL_DATA_SIZE (N * 20)
using namespace std;
#define CUDA_CHECK_RETURN(value) {\
hipError_t _m_cudaStat = value;\
if (_m_cudaStat != hipSuccess) {\
fprintf(stderr, "Error %s at line %d in file %s\n", hipGetErrorString(_m_cudaStat), __LINE__, __FILE__);\
exit(1);\
}}
__global__ void kernel(int *a, int *b, int *c)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < N) {
int idx1 = (idx + 1) % 256;
int idx2 = (idx + 2) % 256;
float as = (a[idx] + a[idx1] + a[idx2]) / 3.0f;
float bs = (b[idx] + b[idx1] + b[idx2]) / 3.0f;
c[idx] = (as + bs) / 2;
}
}
int main()
{
hipDeviceProp_t prop;
int whichDevice;
hipGetDevice(&whichDevice);
hipGetDeviceProperties(&prop, whichDevice);
if (!prop.deviceOverlap) {
cout << "Device does not support overlapping" << endl;
return 0;
}
int *host_a, *host_b, *host_c;
int *dev_a, *dev_b, *dev_c;
hipHostAlloc((void**)&dev_a, FULL_DATA_SIZE * sizeof(int), hipHostMallocDefault);
hipHostAlloc((void**)&dev_b, FULL_DATA_SIZE * sizeof(int), hipHostMallocDefault);
hipHostAlloc((void**)&dev_c, FULL_DATA_SIZE * sizeof(int), hipHostMallocDefault);
hipHostAlloc((void**)&host_a, FULL_DATA_SIZE * sizeof(int), hipHostMallocDefault);
hipHostAlloc((void**)&host_b, FULL_DATA_SIZE * sizeof(int), hipHostMallocDefault);
hipHostAlloc((void**)&host_c, FULL_DATA_SIZE * sizeof(int), hipHostMallocDefault);
hipStream_t stream;
hipStreamCreate(&stream);
float elapsedTime;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
for (int i = 0; i < FULL_DATA_SIZE; i += N) {
hipMemcpyAsync(dev_a, host_a + i, N * sizeof(int), hipMemcpyHostToDevice, stream);
hipMemcpyAsync(dev_b, host_b + i, N * sizeof(int), hipMemcpyHostToDevice, stream);
kernel <<< N / 256, 256, 0, stream >>> (dev_a, dev_b, dev_c);
hipMemcpyAsync(host_c + i, dev_c, N * sizeof(int), hipMemcpyDeviceToHost, stream);
}
hipStreamSynchronize(stream);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
CUDA_CHECK_RETURN(hipDeviceSynchronize());
CUDA_CHECK_RETURN(hipGetLastError());
hipEventElapsedTime(&elapsedTime, start, stop);
cout << "time: " << elapsedTime << " ms" << endl;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#define N (1024 * 1024)
#define FULL_DATA_SIZE (N * 20)
using namespace std;
#define CUDA_CHECK_RETURN(value) {\
hipError_t _m_cudaStat = value;\
if (_m_cudaStat != hipSuccess) {\
fprintf(stderr, "Error %s at line %d in file %s\n", hipGetErrorString(_m_cudaStat), __LINE__, __FILE__);\
exit(1);\
}}
__global__ void kernel(int *a, int *b, int *c)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < N) {
int idx1 = (idx + 1) % 256;
int idx2 = (idx + 2) % 256;
float as = (a[idx] + a[idx1] + a[idx2]) / 3.0f;
float bs = (b[idx] + b[idx1] + b[idx2]) / 3.0f;
c[idx] = (as + bs) / 2;
}
}
int main()
{
hipDeviceProp_t prop;
int whichDevice;
hipGetDevice(&whichDevice);
hipGetDeviceProperties(&prop, whichDevice);
if (!prop.deviceOverlap) {
cout << "Device does not support overlapping" << endl;
return 0;
}
int *host_a, *host_b, *host_c;
int *dev_a, *dev_b, *dev_c;
hipHostAlloc((void**)&dev_a, FULL_DATA_SIZE * sizeof(int), hipHostMallocDefault);
hipHostAlloc((void**)&dev_b, FULL_DATA_SIZE * sizeof(int), hipHostMallocDefault);
hipHostAlloc((void**)&dev_c, FULL_DATA_SIZE * sizeof(int), hipHostMallocDefault);
hipHostAlloc((void**)&host_a, FULL_DATA_SIZE * sizeof(int), hipHostMallocDefault);
hipHostAlloc((void**)&host_b, FULL_DATA_SIZE * sizeof(int), hipHostMallocDefault);
hipHostAlloc((void**)&host_c, FULL_DATA_SIZE * sizeof(int), hipHostMallocDefault);
hipStream_t stream;
hipStreamCreate(&stream);
float elapsedTime;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
for (int i = 0; i < FULL_DATA_SIZE; i += N) {
hipMemcpyAsync(dev_a, host_a + i, N * sizeof(int), hipMemcpyHostToDevice, stream);
hipMemcpyAsync(dev_b, host_b + i, N * sizeof(int), hipMemcpyHostToDevice, stream);
kernel <<< N / 256, 256, 0, stream >>> (dev_a, dev_b, dev_c);
hipMemcpyAsync(host_c + i, dev_c, N * sizeof(int), hipMemcpyDeviceToHost, stream);
}
hipStreamSynchronize(stream);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
CUDA_CHECK_RETURN(hipDeviceSynchronize());
CUDA_CHECK_RETURN(hipGetLastError());
hipEventElapsedTime(&elapsedTime, start, stop);
cout << "time: " << elapsedTime << " ms" << endl;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPiS_S_
.globl _Z6kernelPiS_S_
.p2align 8
.type _Z6kernelPiS_S_,@function
_Z6kernelPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x100000, v1
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v0, 1, v1
v_add_nc_u32_e32 v4, 2, v1
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v0
v_ashrrev_i32_e32 v3, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshrrev_b32_e32 v2, 24, v2
v_lshrrev_b32_e32 v3, 24, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v0, v2
v_add_nc_u32_e32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v5, 0xffffff00, v2
v_and_b32_e32 v6, 0xffffff00, v3
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v0, v0, v5
v_sub_nc_u32_e32 v4, v4, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v5, 31, v4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v2
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v10, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v12, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
s_clause 0x2
global_load_b32 v6, v[6:7], off
global_load_b32 v7, v[10:11], off
global_load_b32 v10, v[12:13], off
s_clause 0x2
global_load_b32 v8, v[8:9], off
global_load_b32 v0, v[0:1], off
global_load_b32 v1, v[4:5], off
s_waitcnt vmcnt(3)
v_add3_u32 v4, v7, v6, v10
s_waitcnt vmcnt(0)
v_add3_u32 v0, v0, v8, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v1, v4
v_cvt_f32_i32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_scale_f32 v4, null, 0x40400000, 0x40400000, v1
v_div_scale_f32 v10, vcc_lo, v1, 0x40400000, v1
v_div_scale_f32 v5, null, 0x40400000, 0x40400000, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v6, v4
v_rcp_f32_e32 v7, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v4, v6, 1.0
v_fma_f32 v9, -v5, v7, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v6, v8, v6
v_div_scale_f32 v8, s0, v0, 0x40400000, v0
v_fmac_f32_e32 v7, v9, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v9, v10, v6
v_mul_f32_e32 v11, v8, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v12, -v4, v9, v10
v_fma_f32 v13, -v5, v11, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v9, v12, v6
v_fmac_f32_e32 v11, v13, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v4, -v4, v9, v10
v_fma_f32 v5, -v5, v11, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v4, v4, v6, v9
s_mov_b32 vcc_lo, s0
v_div_fmas_f32 v5, v5, v7, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f32 v1, v4, 0x40400000, v1
v_div_fixup_f32 v0, v5, 0x40400000, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, v1, v0
v_mul_f32_e32 v0, 0.5, v0
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v4, v0
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPiS_S_, .Lfunc_end0-_Z6kernelPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#define N (1024 * 1024)
#define FULL_DATA_SIZE (N * 20)
using namespace std;
#define CUDA_CHECK_RETURN(value) {\
hipError_t _m_cudaStat = value;\
if (_m_cudaStat != hipSuccess) {\
fprintf(stderr, "Error %s at line %d in file %s\n", hipGetErrorString(_m_cudaStat), __LINE__, __FILE__);\
exit(1);\
}}
__global__ void kernel(int *a, int *b, int *c)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < N) {
int idx1 = (idx + 1) % 256;
int idx2 = (idx + 2) % 256;
float as = (a[idx] + a[idx1] + a[idx2]) / 3.0f;
float bs = (b[idx] + b[idx1] + b[idx2]) / 3.0f;
c[idx] = (as + bs) / 2;
}
}
int main()
{
hipDeviceProp_t prop;
int whichDevice;
hipGetDevice(&whichDevice);
hipGetDeviceProperties(&prop, whichDevice);
if (!prop.deviceOverlap) {
cout << "Device does not support overlapping" << endl;
return 0;
}
int *host_a, *host_b, *host_c;
int *dev_a, *dev_b, *dev_c;
hipHostAlloc((void**)&dev_a, FULL_DATA_SIZE * sizeof(int), hipHostMallocDefault);
hipHostAlloc((void**)&dev_b, FULL_DATA_SIZE * sizeof(int), hipHostMallocDefault);
hipHostAlloc((void**)&dev_c, FULL_DATA_SIZE * sizeof(int), hipHostMallocDefault);
hipHostAlloc((void**)&host_a, FULL_DATA_SIZE * sizeof(int), hipHostMallocDefault);
hipHostAlloc((void**)&host_b, FULL_DATA_SIZE * sizeof(int), hipHostMallocDefault);
hipHostAlloc((void**)&host_c, FULL_DATA_SIZE * sizeof(int), hipHostMallocDefault);
hipStream_t stream;
hipStreamCreate(&stream);
float elapsedTime;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
for (int i = 0; i < FULL_DATA_SIZE; i += N) {
hipMemcpyAsync(dev_a, host_a + i, N * sizeof(int), hipMemcpyHostToDevice, stream);
hipMemcpyAsync(dev_b, host_b + i, N * sizeof(int), hipMemcpyHostToDevice, stream);
kernel <<< N / 256, 256, 0, stream >>> (dev_a, dev_b, dev_c);
hipMemcpyAsync(host_c + i, dev_c, N * sizeof(int), hipMemcpyDeviceToHost, stream);
}
hipStreamSynchronize(stream);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
CUDA_CHECK_RETURN(hipDeviceSynchronize());
CUDA_CHECK_RETURN(hipGetLastError());
hipEventElapsedTime(&elapsedTime, start, stop);
cout << "time: " << elapsedTime << " ms" << endl;
} | .text
.file "memcpyPageLocked.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__kernelPiS_S_ # -- Begin function _Z21__device_stub__kernelPiS_S_
.p2align 4, 0x90
.type _Z21__device_stub__kernelPiS_S_,@function
_Z21__device_stub__kernelPiS_S_: # @_Z21__device_stub__kernelPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPiS_S_, .Lfunc_end0-_Z21__device_stub__kernelPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1656, %rsp # imm = 0x678
.cfi_def_cfa_offset 1712
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 28(%rsp), %rdi
callq hipGetDevice
movl 28(%rsp), %esi
leaq 184(%rsp), %rdi
callq hipGetDevicePropertiesR0600
cmpl $0, 568(%rsp)
je .LBB1_1
# %bb.6:
movabsq $4294967552, %rbx # imm = 0x100000100
leaq 56(%rsp), %rdi
xorl %r12d, %r12d
movl $83886080, %esi # imm = 0x5000000
xorl %edx, %edx
callq hipHostAlloc
leaq 48(%rsp), %rdi
movl $83886080, %esi # imm = 0x5000000
xorl %edx, %edx
callq hipHostAlloc
leaq 40(%rsp), %rdi
movl $83886080, %esi # imm = 0x5000000
xorl %edx, %edx
callq hipHostAlloc
leaq 104(%rsp), %rdi
movl $83886080, %esi # imm = 0x5000000
xorl %edx, %edx
callq hipHostAlloc
leaq 96(%rsp), %rdi
movl $83886080, %esi # imm = 0x5000000
xorl %edx, %edx
callq hipHostAlloc
leaq 88(%rsp), %rdi
movl $83886080, %esi # imm = 0x5000000
xorl %edx, %edx
callq hipHostAlloc
leaq 8(%rsp), %rdi
callq hipStreamCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq $-1048576, %r13 # imm = 0xFFF00000
leaq 3840(%rbx), %r14
leaq 112(%rsp), %rbp
leaq 64(%rsp), %r15
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_9: # in Loop: Header=BB1_7 Depth=1
movq 88(%rsp), %rdi
addq %r12, %rdi
movq 40(%rsp), %rsi
movq 8(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $2, %ecx
callq hipMemcpyAsync
addq $1048576, %r13 # imm = 0x100000
addq $4194304, %r12 # imm = 0x400000
cmpq $19922944, %r13 # imm = 0x1300000
jae .LBB1_10
.LBB1_7: # =>This Inner Loop Header: Depth=1
movq 56(%rsp), %rdi
movq 104(%rsp), %rsi
addq %r12, %rsi
movq 8(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpyAsync
movq 48(%rsp), %rdi
movq 96(%rsp), %rsi
addq %r12, %rsi
movq 8(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpyAsync
movq 8(%rsp), %r9
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_9
# %bb.8: # in Loop: Header=BB1_7 Depth=1
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq %rax, 176(%rsp)
movq %rcx, 168(%rsp)
movq %rdx, 160(%rsp)
leaq 176(%rsp), %rax
movq %rax, 64(%rsp)
leaq 168(%rsp), %rax
movq %rax, 72(%rsp)
leaq 160(%rsp), %rax
movq %rax, 80(%rsp)
leaq 144(%rsp), %rdi
leaq 128(%rsp), %rsi
leaq 120(%rsp), %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
movq 128(%rsp), %rcx
movl 136(%rsp), %r8d
movl $_Z6kernelPiS_S_, %edi
movq %r15, %r9
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_9
.LBB1_10:
movq 8(%rsp), %rdi
callq hipStreamSynchronize
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_11
# %bb.13:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_14
# %bb.15:
movq 32(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 64(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.4, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB1_21
# %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i18
cmpb $0, 56(%r14)
je .LBB1_18
# %bb.17:
movzbl 67(%r14), %eax
jmp .LBB1_19
.LBB1_1:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $35, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_21
# %bb.2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_4
# %bb.3:
movzbl 67(%rbx), %eax
jmp .LBB1_5
.LBB1_18:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_19: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit21
movsbl %al, %esi
movq %rbx, %rdi
jmp .LBB1_20
.LBB1_4:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_5: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
.LBB1_20:
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $1656, %rsp # imm = 0x678
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_21:
.cfi_def_cfa_offset 1712
callq _ZSt16__throw_bad_castv
.LBB1_11:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $78, %ecx
jmp .LBB1_12
.LBB1_14:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $79, %ecx
.LBB1_12:
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPiS_S_,@object # @_Z6kernelPiS_S_
.section .rodata,"a",@progbits
.globl _Z6kernelPiS_S_
.p2align 3, 0x0
_Z6kernelPiS_S_:
.quad _Z21__device_stub__kernelPiS_S_
.size _Z6kernelPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Device does not support overlapping"
.size .L.str, 36
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error %s at line %d in file %s\n"
.size .L.str.1, 32
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/VladislavMamonov/cuda/main/lab6/memcpyPageLocked.hip"
.size .L.str.2, 110
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "time: "
.size .L.str.3, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " ms"
.size .L.str.4, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPiS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, 0xfffff, PT ; /* 0x000fffff0000780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R3, R0.reuse, 0x1, RZ ; /* 0x0000000100037810 */
/* 0x040fe20007ffe0ff */
/*0070*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0080*/ IADD3 R4, R0, 0x2, RZ ; /* 0x0000000200047810 */
/* 0x000fe20007ffe0ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ SHF.R.S32.HI R2, RZ, 0x1f, R3 ; /* 0x0000001fff027819 */
/* 0x000fe40000011403 */
/*00b0*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fe40000011404 */
/*00c0*/ LEA.HI R2, R2, R3, RZ, 0x8 ; /* 0x0000000302027211 */
/* 0x000fe400078f40ff */
/*00d0*/ LEA.HI R5, R5, R4, RZ, 0x8 ; /* 0x0000000405057211 */
/* 0x000fc400078f40ff */
/*00e0*/ LOP3.LUT R2, R2, 0xffffff00, RZ, 0xc0, !PT ; /* 0xffffff0002027812 */
/* 0x000fe400078ec0ff */
/*00f0*/ LOP3.LUT R5, R5, 0xffffff00, RZ, 0xc0, !PT ; /* 0xffffff0005057812 */
/* 0x000fc600078ec0ff */
/*0100*/ IMAD.IADD R3, R3, 0x1, -R2 ; /* 0x0000000103037824 */
/* 0x000fe400078e0a02 */
/*0110*/ IMAD.IADD R2, R4, 0x1, -R5 ; /* 0x0000000104027824 */
/* 0x000fe400078e0a05 */
/*0120*/ IMAD.WIDE R4, R0, R9, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e0209 */
/*0130*/ IMAD.WIDE R6, R3, R9.reuse, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x080fe400078e0209 */
/*0140*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*0150*/ IMAD.WIDE R8, R2, R9, c[0x0][0x160] ; /* 0x0000580002087625 */
/* 0x000fe400078e0209 */
/*0160*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*0170*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1900 */
/*0180*/ IMAD.MOV.U32 R12, RZ, RZ, 0x3eaaaaab ; /* 0x3eaaaaabff0c7424 */
/* 0x000fc400078e00ff */
/*0190*/ IMAD.MOV.U32 R13, RZ, RZ, 0x40400000 ; /* 0x40400000ff0d7424 */
/* 0x000fc800078e00ff */
/*01a0*/ FFMA R11, R12, -R13, 1 ; /* 0x3f8000000c0b7423 */
/* 0x000fc8000000080d */
/*01b0*/ FFMA R11, R11, R12, 0.3333333432674407959 ; /* 0x3eaaaaab0b0b7423 */
/* 0x000fe2000000000c */
/*01c0*/ BSSY B0, 0x280 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*01d0*/ IADD3 R10, R8, R6, R5 ; /* 0x00000006080a7210 */
/* 0x004fcc0007ffe005 */
/*01e0*/ I2F R10, R10 ; /* 0x0000000a000a7306 */
/* 0x000e300000201400 */
/*01f0*/ FCHK P0, R10, 3 ; /* 0x404000000a007902 */
/* 0x001e220000000000 */
/*0200*/ FFMA R12, R10, R11, RZ ; /* 0x0000000b0a0c7223 */
/* 0x000fc800000000ff */
/*0210*/ FFMA R4, R12, -3, R10 ; /* 0xc04000000c047823 */
/* 0x000fc8000000000a */
/*0220*/ FFMA R4, R11, R4, R12 ; /* 0x000000040b047223 */
/* 0x000fe2000000000c */
/*0230*/ @!P0 BRA 0x270 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*0240*/ MOV R6, 0x260 ; /* 0x0000026000067802 */
/* 0x000fe40000000f00 */
/*0250*/ CALL.REL.NOINC 0x470 ; /* 0x0000021000007944 */
/* 0x000fea0003c00000 */
/*0260*/ IMAD.MOV.U32 R4, RZ, RZ, R5 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0005 */
/*0270*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0280*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0290*/ IMAD.WIDE R8, R3, R5, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fc800078e0205 */
/*02a0*/ IMAD.WIDE R6, R0, R5.reuse, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x080fe400078e0205 */
/*02b0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea4000c1e1900 */
/*02c0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fe400078e0205 */
/*02d0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea8000c1e1900 */
/*02e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*02f0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x3eaaaaab ; /* 0x3eaaaaabff0a7424 */
/* 0x000fc400078e00ff */
/*0300*/ IMAD.MOV.U32 R13, RZ, RZ, 0x40400000 ; /* 0x40400000ff0d7424 */
/* 0x000fc800078e00ff */
/*0310*/ FFMA R11, R10, -R13, 1 ; /* 0x3f8000000a0b7423 */
/* 0x000fc8000000080d */
/*0320*/ FFMA R12, R11, R10, 0.3333333432674407959 ; /* 0x3eaaaaab0b0c7423 */
/* 0x000fe2000000000a */
/*0330*/ BSSY B0, 0x400 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*0340*/ IADD3 R5, R2, R8, R7 ; /* 0x0000000802057210 */
/* 0x004fcc0007ffe007 */
/*0350*/ I2F R5, R5 ; /* 0x0000000500057306 */
/* 0x000e300000201400 */
/*0360*/ FCHK P0, R5, 3 ; /* 0x4040000005007902 */
/* 0x001e220000000000 */
/*0370*/ FFMA R10, R12, R5, RZ ; /* 0x000000050c0a7223 */
/* 0x000fc800000000ff */
/*0380*/ FFMA R9, R10, -3, R5 ; /* 0xc04000000a097823 */
/* 0x000fc80000000005 */
/*0390*/ FFMA R9, R12, R9, R10 ; /* 0x000000090c097223 */
/* 0x000fe2000000000a */
/*03a0*/ @!P0 BRA 0x3f0 ; /* 0x0000004000008947 */
/* 0x001fea0003800000 */
/*03b0*/ IMAD.MOV.U32 R10, RZ, RZ, R5 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0005 */
/*03c0*/ MOV R6, 0x3e0 ; /* 0x000003e000067802 */
/* 0x000fe40000000f00 */
/*03d0*/ CALL.REL.NOINC 0x470 ; /* 0x0000009000007944 */
/* 0x000fea0003c00000 */
/*03e0*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x001fe400078e0005 */
/*03f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0400*/ FADD R4, R9, R4 ; /* 0x0000000409047221 */
/* 0x000fe40000000000 */
/*0410*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*0420*/ FMUL R4, R4, 0.5 ; /* 0x3f00000004047820 */
/* 0x000fe40000400000 */
/*0430*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fe400078e0203 */
/*0440*/ F2I.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000e26000020f100 */
/*0450*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0460*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0470*/ SHF.R.U32.HI R7, RZ, 0x17, R13.reuse ; /* 0x00000017ff077819 */
/* 0x100fe2000001160d */
/*0480*/ BSSY B1, 0xad0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0490*/ SHF.R.U32.HI R5, RZ, 0x17, R10 ; /* 0x00000017ff057819 */
/* 0x000fe2000001160a */
/*04a0*/ IMAD.MOV.U32 R8, RZ, RZ, R13 ; /* 0x000000ffff087224 */
/* 0x000fe200078e000d */
/*04b0*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fc400078ec0ff */
/*04c0*/ LOP3.LUT R14, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff050e7812 */
/* 0x000fe200078ec0ff */
/*04d0*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000a */
/*04e0*/ IADD3 R11, R7, -0x1, RZ ; /* 0xffffffff070b7810 */
/* 0x000fe40007ffe0ff */
/*04f0*/ IADD3 R12, R14, -0x1, RZ ; /* 0xffffffff0e0c7810 */
/* 0x000fe40007ffe0ff */
/*0500*/ ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ; /* 0x000000fd0b00780c */
/* 0x000fc80003f04070 */
/*0510*/ ISETP.GT.U32.OR P0, PT, R12, 0xfd, P0 ; /* 0x000000fd0c00780c */
/* 0x000fda0000704470 */
/*0520*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*0530*/ @!P0 BRA 0x6b0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0540*/ FSETP.GTU.FTZ.AND P0, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fe40003f1c200 */
/*0550*/ FSETP.GTU.FTZ.AND P1, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fc80003f3c200 */
/*0560*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0570*/ @P0 BRA 0xab0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0580*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R5, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c805 */
/*0590*/ @!P0 BRA 0xa90 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*05a0*/ FSETP.NEU.FTZ.AND P2, PT, |R10|.reuse, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x040fe40003f5d200 */
/*05b0*/ FSETP.NEU.FTZ.AND P1, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fe40003f3d200 */
/*05c0*/ FSETP.NEU.FTZ.AND P0, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fd60003f1d200 */
/*05d0*/ @!P1 BRA !P2, 0xa90 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*05e0*/ LOP3.LUT P2, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fc8000784c0ff */
/*05f0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0600*/ @P1 BRA 0xa70 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0610*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*0620*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0630*/ @P0 BRA 0xa40 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0640*/ ISETP.GE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f06270 */
/*0650*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f26270 */
/*0660*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*0670*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*0680*/ @!P0 FFMA R5, R10, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000a058823 */
/* 0x000fe400000000ff */
/*0690*/ @!P1 FFMA R8, R13, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000d089823 */
/* 0x000fe200000000ff */
/*06a0*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*06b0*/ LEA R11, R7, 0xc0800000, 0x17 ; /* 0xc0800000070b7811 */
/* 0x000fe200078eb8ff */
/*06c0*/ BSSY B2, 0xa30 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*06d0*/ IMAD.IADD R11, R8, 0x1, -R11 ; /* 0x00000001080b7824 */
/* 0x000fe200078e0a0b */
/*06e0*/ IADD3 R8, R14, -0x7f, RZ ; /* 0xffffff810e087810 */
/* 0x000fc60007ffe0ff */
/*06f0*/ MUFU.RCP R10, R11 ; /* 0x0000000b000a7308 */
/* 0x000e220000001000 */
/*0700*/ FADD.FTZ R12, -R11, -RZ ; /* 0x800000ff0b0c7221 */
/* 0x000fe40000010100 */
/*0710*/ IMAD R5, R8.reuse, -0x800000, R5 ; /* 0xff80000008057824 */
/* 0x040fe200078e0205 */
/*0720*/ IADD3 R8, R8, 0x7f, -R7 ; /* 0x0000007f08087810 */
/* 0x000fca0007ffe807 */
/*0730*/ IMAD.IADD R8, R8, 0x1, R9 ; /* 0x0000000108087824 */
/* 0x000fe400078e0209 */
/*0740*/ FFMA R13, R10, R12, 1 ; /* 0x3f8000000a0d7423 */
/* 0x001fc8000000000c */
/*0750*/ FFMA R14, R10, R13, R10 ; /* 0x0000000d0a0e7223 */
/* 0x000fc8000000000a */
/*0760*/ FFMA R10, R5, R14, RZ ; /* 0x0000000e050a7223 */
/* 0x000fc800000000ff */
/*0770*/ FFMA R13, R12, R10, R5 ; /* 0x0000000a0c0d7223 */
/* 0x000fc80000000005 */
/*0780*/ FFMA R13, R14, R13, R10 ; /* 0x0000000d0e0d7223 */
/* 0x000fc8000000000a */
/*0790*/ FFMA R12, R12, R13, R5 ; /* 0x0000000d0c0c7223 */
/* 0x000fc80000000005 */
/*07a0*/ FFMA R5, R14, R12, R13 ; /* 0x0000000c0e057223 */
/* 0x000fca000000000d */
/*07b0*/ SHF.R.U32.HI R7, RZ, 0x17, R5 ; /* 0x00000017ff077819 */
/* 0x000fc80000011605 */
/*07c0*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fca00078ec0ff */
/*07d0*/ IMAD.IADD R11, R7, 0x1, R8 ; /* 0x00000001070b7824 */
/* 0x000fca00078e0208 */
/*07e0*/ IADD3 R7, R11, -0x1, RZ ; /* 0xffffffff0b077810 */
/* 0x000fc80007ffe0ff */
/*07f0*/ ISETP.GE.U32.AND P0, PT, R7, 0xfe, PT ; /* 0x000000fe0700780c */
/* 0x000fda0003f06070 */
/*0800*/ @!P0 BRA 0xa10 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0810*/ ISETP.GT.AND P0, PT, R11, 0xfe, PT ; /* 0x000000fe0b00780c */
/* 0x000fda0003f04270 */
/*0820*/ @P0 BRA 0x9e0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0830*/ ISETP.GE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fda0003f06270 */
/*0840*/ @P0 BRA 0xa20 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0850*/ ISETP.GE.AND P0, PT, R11, -0x18, PT ; /* 0xffffffe80b00780c */
/* 0x000fe40003f06270 */
/*0860*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fd600078ec0ff */
/*0870*/ @!P0 BRA 0xa20 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0880*/ FFMA.RZ R7, R14.reuse, R12.reuse, R13.reuse ; /* 0x0000000c0e077223 */
/* 0x1c0fe2000000c00d */
/*0890*/ IADD3 R10, R11.reuse, 0x20, RZ ; /* 0x000000200b0a7810 */
/* 0x040fe20007ffe0ff */
/*08a0*/ FFMA.RM R8, R14.reuse, R12.reuse, R13.reuse ; /* 0x0000000c0e087223 */
/* 0x1c0fe2000000400d */
/*08b0*/ ISETP.NE.AND P2, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f45270 */
/*08c0*/ LOP3.LUT R9, R7, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff07097812 */
/* 0x000fe200078ec0ff */
/*08d0*/ FFMA.RP R7, R14, R12, R13 ; /* 0x0000000c0e077223 */
/* 0x000fe2000000800d */
/*08e0*/ ISETP.NE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f25270 */
/*08f0*/ IMAD.MOV R11, RZ, RZ, -R11 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0a0b */
/*0900*/ LOP3.LUT R9, R9, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000009097812 */
/* 0x000fe400078efcff */
/*0910*/ FSETP.NEU.FTZ.AND P0, PT, R7, R8, PT ; /* 0x000000080700720b */
/* 0x000fc40003f1d000 */
/*0920*/ SHF.L.U32 R10, R9, R10, RZ ; /* 0x0000000a090a7219 */
/* 0x000fe400000006ff */
/*0930*/ SEL R8, R11, RZ, P2 ; /* 0x000000ff0b087207 */
/* 0x000fe40001000000 */
/*0940*/ ISETP.NE.AND P1, PT, R10, RZ, P1 ; /* 0x000000ff0a00720c */
/* 0x000fe40000f25270 */
/*0950*/ SHF.R.U32.HI R8, RZ, R8, R9 ; /* 0x00000008ff087219 */
/* 0x000fe40000011609 */
/*0960*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0970*/ SHF.R.U32.HI R10, RZ, 0x1, R8 ; /* 0x00000001ff0a7819 */
/* 0x000fc40000011608 */
/*0980*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fc80004000000 */
/*0990*/ LOP3.LUT R7, R7, 0x1, R10, 0xf8, !PT ; /* 0x0000000107077812 */
/* 0x000fc800078ef80a */
/*09a0*/ LOP3.LUT R7, R7, R8, RZ, 0xc0, !PT ; /* 0x0000000807077212 */
/* 0x000fca00078ec0ff */
/*09b0*/ IMAD.IADD R10, R10, 0x1, R7 ; /* 0x000000010a0a7824 */
/* 0x000fca00078e0207 */
/*09c0*/ LOP3.LUT R5, R10, R5, RZ, 0xfc, !PT ; /* 0x000000050a057212 */
/* 0x000fe200078efcff */
/*09d0*/ BRA 0xa20 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*09e0*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fc800078ec0ff */
/*09f0*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*0a00*/ BRA 0xa20 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0a10*/ IMAD R5, R8, 0x800000, R5 ; /* 0x0080000008057824 */
/* 0x000fe400078e0205 */
/*0a20*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0a30*/ BRA 0xac0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0a40*/ LOP3.LUT R5, R8, 0x80000000, R5, 0x48, !PT ; /* 0x8000000008057812 */
/* 0x000fc800078e4805 */
/*0a50*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*0a60*/ BRA 0xac0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0a70*/ LOP3.LUT R5, R8, 0x80000000, R5, 0x48, !PT ; /* 0x8000000008057812 */
/* 0x000fe200078e4805 */
/*0a80*/ BRA 0xac0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0a90*/ MUFU.RSQ R5, -QNAN ; /* 0xffc0000000057908 */
/* 0x000e220000001400 */
/*0aa0*/ BRA 0xac0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0ab0*/ FADD.FTZ R5, R10, R13 ; /* 0x0000000d0a057221 */
/* 0x000fe40000010000 */
/*0ac0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0ad0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc800078e00ff */
/*0ae0*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff51006007950 */
/* 0x000fea0003c3ffff */
/*0af0*/ BRA 0xaf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPiS_S_
.globl _Z6kernelPiS_S_
.p2align 8
.type _Z6kernelPiS_S_,@function
_Z6kernelPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x100000, v1
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v0, 1, v1
v_add_nc_u32_e32 v4, 2, v1
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v0
v_ashrrev_i32_e32 v3, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshrrev_b32_e32 v2, 24, v2
v_lshrrev_b32_e32 v3, 24, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v0, v2
v_add_nc_u32_e32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v5, 0xffffff00, v2
v_and_b32_e32 v6, 0xffffff00, v3
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v0, v0, v5
v_sub_nc_u32_e32 v4, v4, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v5, 31, v4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v2
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v10, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v12, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
s_clause 0x2
global_load_b32 v6, v[6:7], off
global_load_b32 v7, v[10:11], off
global_load_b32 v10, v[12:13], off
s_clause 0x2
global_load_b32 v8, v[8:9], off
global_load_b32 v0, v[0:1], off
global_load_b32 v1, v[4:5], off
s_waitcnt vmcnt(3)
v_add3_u32 v4, v7, v6, v10
s_waitcnt vmcnt(0)
v_add3_u32 v0, v0, v8, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v1, v4
v_cvt_f32_i32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_scale_f32 v4, null, 0x40400000, 0x40400000, v1
v_div_scale_f32 v10, vcc_lo, v1, 0x40400000, v1
v_div_scale_f32 v5, null, 0x40400000, 0x40400000, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v6, v4
v_rcp_f32_e32 v7, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v4, v6, 1.0
v_fma_f32 v9, -v5, v7, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v6, v8, v6
v_div_scale_f32 v8, s0, v0, 0x40400000, v0
v_fmac_f32_e32 v7, v9, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v9, v10, v6
v_mul_f32_e32 v11, v8, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v12, -v4, v9, v10
v_fma_f32 v13, -v5, v11, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v9, v12, v6
v_fmac_f32_e32 v11, v13, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v4, -v4, v9, v10
v_fma_f32 v5, -v5, v11, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v4, v4, v6, v9
s_mov_b32 vcc_lo, s0
v_div_fmas_f32 v5, v5, v7, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f32 v1, v4, 0x40400000, v1
v_div_fixup_f32 v0, v5, 0x40400000, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, v1, v0
v_mul_f32_e32 v0, 0.5, v0
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v4, v0
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPiS_S_, .Lfunc_end0-_Z6kernelPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012a151_00000000-6_memcpyPageLocked.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6kernelPiS_S_PiS_S_
.type _Z29__device_stub__Z6kernelPiS_S_PiS_S_, @function
_Z29__device_stub__Z6kernelPiS_S_PiS_S_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernelPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z29__device_stub__Z6kernelPiS_S_PiS_S_, .-_Z29__device_stub__Z6kernelPiS_S_PiS_S_
.globl _Z6kernelPiS_S_
.type _Z6kernelPiS_S_, @function
_Z6kernelPiS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6kernelPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z6kernelPiS_S_, .-_Z6kernelPiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Device does not support overlapping"
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/VladislavMamonov/cuda/main/lab6/memcpyPageLocked.cu"
.align 8
.LC2:
.string "Error %s at line %d in file %s\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "time: "
.LC4:
.string " ms"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1152, %rsp
.cfi_def_cfa_offset 1168
movq %fs:40, %rax
movq %rax, 1144(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDevice@PLT
leaq 112(%rsp), %rdi
movl 12(%rsp), %esi
call cudaGetDeviceProperties_v2@PLT
cmpl $0, 496(%rsp)
je .L21
leaq 40(%rsp), %rdi
movl $0, %edx
movl $83886080, %esi
call cudaHostAlloc@PLT
leaq 48(%rsp), %rdi
movl $0, %edx
movl $83886080, %esi
call cudaHostAlloc@PLT
leaq 56(%rsp), %rdi
movl $0, %edx
movl $83886080, %esi
call cudaHostAlloc@PLT
leaq 16(%rsp), %rdi
movl $0, %edx
movl $83886080, %esi
call cudaHostAlloc@PLT
leaq 24(%rsp), %rdi
movl $0, %edx
movl $83886080, %esi
call cudaHostAlloc@PLT
leaq 32(%rsp), %rdi
movl $0, %edx
movl $83886080, %esi
call cudaHostAlloc@PLT
leaq 64(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
leaq 80(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %ebx
jmp .L15
.L21:
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L13
.L14:
movq %rbx, %rdi
addq 32(%rsp), %rdi
movq 64(%rsp), %r8
movl $2, %ecx
movl $4194304, %edx
movq 56(%rsp), %rsi
call cudaMemcpyAsync@PLT
addq $4194304, %rbx
cmpq $83886080, %rbx
je .L22
.L15:
movq %rbx, %rsi
addq 16(%rsp), %rsi
movq 64(%rsp), %r8
movl $1, %ecx
movl $4194304, %edx
movq 40(%rsp), %rdi
call cudaMemcpyAsync@PLT
movq %rbx, %rsi
addq 24(%rsp), %rsi
movq 64(%rsp), %r8
movl $1, %ecx
movl $4194304, %edx
movq 48(%rsp), %rdi
call cudaMemcpyAsync@PLT
movl $256, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $4096, 88(%rsp)
movl $1, 92(%rsp)
movq 64(%rsp), %r9
movl $0, %r8d
movq 100(%rsp), %rdx
movl $1, %ecx
movq 88(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L14
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z29__device_stub__Z6kernelPiS_S_PiS_S_
jmp .L14
.L22:
movq 64(%rsp), %rdi
call cudaStreamSynchronize@PLT
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
movq 80(%rsp), %rdi
call cudaEventSynchronize@PLT
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L23
call cudaGetLastError@PLT
testl %eax, %eax
jne .L24
leaq 100(%rsp), %rdi
movq 80(%rsp), %rdx
movq 72(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 100(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L13:
movq 1144(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $1152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %r9
movl $76, %r8d
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L24:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %r9
movl $77, %r8d
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z6kernelPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "memcpyPageLocked.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__kernelPiS_S_ # -- Begin function _Z21__device_stub__kernelPiS_S_
.p2align 4, 0x90
.type _Z21__device_stub__kernelPiS_S_,@function
_Z21__device_stub__kernelPiS_S_: # @_Z21__device_stub__kernelPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPiS_S_, .Lfunc_end0-_Z21__device_stub__kernelPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1656, %rsp # imm = 0x678
.cfi_def_cfa_offset 1712
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 28(%rsp), %rdi
callq hipGetDevice
movl 28(%rsp), %esi
leaq 184(%rsp), %rdi
callq hipGetDevicePropertiesR0600
cmpl $0, 568(%rsp)
je .LBB1_1
# %bb.6:
movabsq $4294967552, %rbx # imm = 0x100000100
leaq 56(%rsp), %rdi
xorl %r12d, %r12d
movl $83886080, %esi # imm = 0x5000000
xorl %edx, %edx
callq hipHostAlloc
leaq 48(%rsp), %rdi
movl $83886080, %esi # imm = 0x5000000
xorl %edx, %edx
callq hipHostAlloc
leaq 40(%rsp), %rdi
movl $83886080, %esi # imm = 0x5000000
xorl %edx, %edx
callq hipHostAlloc
leaq 104(%rsp), %rdi
movl $83886080, %esi # imm = 0x5000000
xorl %edx, %edx
callq hipHostAlloc
leaq 96(%rsp), %rdi
movl $83886080, %esi # imm = 0x5000000
xorl %edx, %edx
callq hipHostAlloc
leaq 88(%rsp), %rdi
movl $83886080, %esi # imm = 0x5000000
xorl %edx, %edx
callq hipHostAlloc
leaq 8(%rsp), %rdi
callq hipStreamCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq $-1048576, %r13 # imm = 0xFFF00000
leaq 3840(%rbx), %r14
leaq 112(%rsp), %rbp
leaq 64(%rsp), %r15
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_9: # in Loop: Header=BB1_7 Depth=1
movq 88(%rsp), %rdi
addq %r12, %rdi
movq 40(%rsp), %rsi
movq 8(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $2, %ecx
callq hipMemcpyAsync
addq $1048576, %r13 # imm = 0x100000
addq $4194304, %r12 # imm = 0x400000
cmpq $19922944, %r13 # imm = 0x1300000
jae .LBB1_10
.LBB1_7: # =>This Inner Loop Header: Depth=1
movq 56(%rsp), %rdi
movq 104(%rsp), %rsi
addq %r12, %rsi
movq 8(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpyAsync
movq 48(%rsp), %rdi
movq 96(%rsp), %rsi
addq %r12, %rsi
movq 8(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpyAsync
movq 8(%rsp), %r9
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_9
# %bb.8: # in Loop: Header=BB1_7 Depth=1
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq %rax, 176(%rsp)
movq %rcx, 168(%rsp)
movq %rdx, 160(%rsp)
leaq 176(%rsp), %rax
movq %rax, 64(%rsp)
leaq 168(%rsp), %rax
movq %rax, 72(%rsp)
leaq 160(%rsp), %rax
movq %rax, 80(%rsp)
leaq 144(%rsp), %rdi
leaq 128(%rsp), %rsi
leaq 120(%rsp), %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
movq 128(%rsp), %rcx
movl 136(%rsp), %r8d
movl $_Z6kernelPiS_S_, %edi
movq %r15, %r9
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_9
.LBB1_10:
movq 8(%rsp), %rdi
callq hipStreamSynchronize
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_11
# %bb.13:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_14
# %bb.15:
movq 32(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 64(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.4, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB1_21
# %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i18
cmpb $0, 56(%r14)
je .LBB1_18
# %bb.17:
movzbl 67(%r14), %eax
jmp .LBB1_19
.LBB1_1:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $35, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_21
# %bb.2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_4
# %bb.3:
movzbl 67(%rbx), %eax
jmp .LBB1_5
.LBB1_18:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_19: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit21
movsbl %al, %esi
movq %rbx, %rdi
jmp .LBB1_20
.LBB1_4:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_5: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
.LBB1_20:
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $1656, %rsp # imm = 0x678
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_21:
.cfi_def_cfa_offset 1712
callq _ZSt16__throw_bad_castv
.LBB1_11:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $78, %ecx
jmp .LBB1_12
.LBB1_14:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $79, %ecx
.LBB1_12:
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPiS_S_,@object # @_Z6kernelPiS_S_
.section .rodata,"a",@progbits
.globl _Z6kernelPiS_S_
.p2align 3, 0x0
_Z6kernelPiS_S_:
.quad _Z21__device_stub__kernelPiS_S_
.size _Z6kernelPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Device does not support overlapping"
.size .L.str, 36
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error %s at line %d in file %s\n"
.size .L.str.1, 32
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/VladislavMamonov/cuda/main/lab6/memcpyPageLocked.hip"
.size .L.str.2, 110
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "time: "
.size .L.str.3, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " ms"
.size .L.str.4, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPiS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "TFcore.cuh"
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
__global__ void _computeGradient(double* p, double* pshift, double* dp, int XRES) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
dp[i] = (p[i] - pshift[i]) * (double)XRES;
}
__global__ void _computeWeightedSum(double* p, double* ddp, double alpha) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
//p[i] += alpha * ddp[i] + beta * ((1 / (double)XRES) - p[i]);
p[i] = p[i] + alpha * ddp[i];
}
//__global__ void normalizeProb(double* pdist) {
// // <<< M, numChannels >>>
// int numChannels = blockDim.x;
// int m = blockIdx.x;
// int n = threadIdx.x;
//
// double psum = 0;
// for (int k = 0; k < XRES; k++) psum += pdist[k + n * XRES + m * numChannels * XRES];
// for (int k = 0; k < XRES; k++) pdist[k + n * XRES + m * numChannels * XRES] /= psum;
//}
__global__ void _computeProduct(double* pdist_prior, double* pdist_lik, double* pdist_post) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
pdist_post[i] = pdist_prior[i] * pdist_lik[i];
}
TFcore::TFcore() {
}
TFcore::TFcore(string filename) {
outputFile.open(filename, ios::out);
}
TFcore::TFcore(fs::path filename) {
outputFile.open(filename, ios::out);
}
//TFcore::TFcore(CTFcoreMFCDlg& dlg) : dlg_(dlg) {
// TFcore();
//}
TFcore::~TFcore() {
free(mu_init);
free(sig2_init);
free(sig2_reg);
free(sig2_update);
free(xbin);
free(xnew);
free(idnew);
free(emgMAV);
free(emgStack);
free(pdist_prior);
free(pdist_post);
free(pdist_lik);
inputFile.close();
outputFile.close();
}
void TFcore::initModel(int n) {
M = 1;
reglast = 0;
samples = 0;
bCollect = false;
bCompute = false;
bRegister = false;
bGPU_product = false;
bGPU_diffusion = false;
bFuncRegistration = true;
bFuncAdaptation = true;
XRES = 128;
WIN_MAV = 1024;
M_MAX = 2048;
// set channel
setNumChannels(n);
// memory allocation
mu_init = (double*)calloc(numChannels, sizeof(double));
sig2_init = (double*)calloc(numChannels, sizeof(double));
sig2_reg = (double*)calloc(numChannels, sizeof(double));
sig2_update = (double*)calloc(numChannels, sizeof(double));
emgMAV = (double*)calloc(numChannels, sizeof(double));
xnew = (double*)calloc(numChannels, sizeof(double));
idnew = (int*)calloc(numChannels, sizeof(int));
xbin = (double*)calloc(XRES, sizeof(double));
for (int k = 0; k < XRES; k++) xbin[k] = ((k + 1) / (double)(XRES));
emgStack = (double*)calloc(WIN_MAV * numChannels, sizeof(double));
// lookup table for normal distribution
tableSize = 10000;
discretizeStep = 1000;
normalTable = (double*)calloc(tableSize, sizeof(double));
constructLookup();
// distribution = max number of patterns
pdist_prior = (double*)calloc(XRES * numChannels * M_MAX, sizeof(double));
pdist_post = (double*)calloc(XRES * numChannels * M_MAX, sizeof(double));
pdist_lik = (double*)calloc(XRES * numChannels * M_MAX, sizeof(double));
dp = (double*)calloc(XRES * numChannels * M_MAX, sizeof(double));
ddp = (double*)calloc(XRES * numChannels * M_MAX, sizeof(double));
p_shift = (double*)calloc(XRES * numChannels * M_MAX, sizeof(double));
dp_shift = (double*)calloc(XRES * numChannels * M_MAX, sizeof(double));
p_lik = (double*)calloc(M_MAX, sizeof(double));
for (int m = 0; m < M_MAX; m++) {
p_lik[m] = NAN;
for (int n = 0; n < numChannels; n++) {
for (int k = 0; k < XRES; k++) {
pdist_prior[k + n * XRES + m * XRES * numChannels] = NAN;
pdist_post[k + n * XRES + m * XRES * numChannels] = NAN;
pdist_lik[k + n * XRES + m * XRES * numChannels] = NAN;
dp[k + n * XRES + m * XRES * numChannels] = 0;
ddp[k + n * XRES + m * XRES * numChannels] = 0;
p_shift[k + n * XRES + m * XRES * numChannels] = (1 / (double)XRES);
dp_shift[k + n * XRES + m * XRES * numChannels] = 0;
}
}
}
// model parameter
xmax = 5.00e-5;
alpha = 1.00e-10;
beta = 1.00e-50;
p_star = -20;
reghold = 512;
setVal(mu_init, 3.00e-2);
setVal(sig2_init, 1.00e-1);
setVal(sig2_reg, 1.00e-2);
setVal(sig2_update, 1.00e+2);
setZero(emgMAV);
// initialize first pattern
for (int n = 0; n < numChannels; n++) {
for (int k = 0; k < XRES; k++) {
// assign uniform distribution
pdist_prior[k + n * XRES] = (1 / (double)XRES);
pdist_post[k + n * XRES] = (1 / (double)XRES);
pdist_lik[k + n * XRES] = (1 / (double)XRES);
dp[k + n * XRES] = 0;
ddp[k + n * XRES] = 0;
p_shift[k + n * XRES] = (1 / (double)XRES);
dp_shift[k + n * XRES] = (1 / (double)XRES);
}
}
_pdist_prior = nullptr;
_pdist_lik = nullptr;
_pdist_post = nullptr;
_p_shift = nullptr;
_dp_shift = nullptr;
_dp = nullptr;
_ddp = nullptr;
if (!outputFile.is_open()) outputFile.open("output.csv", ios::out);
}
void TFcore::getSample() {
samples++;
// a vertical stack of row samples to compute MAV
// the first row = the latest sample
string data;
string line;
stringstream parse;
//for (int n = 0; n < numChannels; n++) {
//memcpy(&emgStack[1 + n * WIN_MAV], &emgStack[0 + n * WIN_MAV], (WIN_MAV - 1) * sizeof(double));
//emgStack[n * WIN_MAV] = dataStack.front();
//dataStack.erase(dataStack.begin());
//}
getline(inputFile, line, '\n');
parse.str(line);
for (int n = 0; n < numChannels; n++) {
memcpy(&emgStack[1 + n * WIN_MAV], &emgStack[0 + n * WIN_MAV], (WIN_MAV - 1) * sizeof(double));
getline(parse, data, ',');
emgStack[n * WIN_MAV] = stod(data);
}
// compute MAV = a single row vector
for (int n = 0; n < numChannels; n++) {
emgMAV[n] = 0;
for (int m = 0; m < WIN_MAV; m++) {
emgMAV[n] += abs(emgStack[m + n * WIN_MAV]) / (double)(WIN_MAV);
}
}
bCollect = true;
bCompute = false;
}
void TFcore::proceedIteration() {
if (isCollect() && (samples > 2 * WIN_MAV)) {
bRegister = false;
reglast += 1;
p_max = -999;
mpred = 0;
for (int n = 0; n < numChannels; n++) {
xnew[n] = (1 / xmax) * emgMAV[n];
xnew[n] = min((double)1, xnew[n]);
idnew[n] = floor(xnew[n] * (double)(XRES));
if (idnew[n] > (XRES - 1)) idnew[n] = XRES - 1;
}
if (bFuncAdaptation) {
if (bGPU_diffusion) {
cudaMalloc(&_pdist_prior, M * XRES * numChannels * sizeof(double));
cudaMalloc(&_p_shift, M * XRES * numChannels * sizeof(double));
cudaMalloc(&_dp_shift, M * XRES * numChannels * sizeof(double));
cudaMalloc(&_dp, M * XRES * numChannels * sizeof(double));
cudaMalloc(&_ddp, M * XRES * numChannels * sizeof(double));
// memcpy pdist_prior => pshift(dist_prior)
for (int m = 0; m < M; m++) {
for (int n = 0; n < numChannels; n++) {
memcpy(&p_shift[1 + n * XRES + m * (XRES * numChannels)],
&pdist_prior[0 + n * XRES + m * (XRES * numChannels)],
(XRES - 1) * sizeof(double));
p_shift[0 + n * XRES + m * (XRES * numChannels)] = p_shift[1 + n * XRES + m * (XRES * numChannels)];
}
}
cudaMemcpy(_pdist_prior, pdist_prior, M * XRES * numChannels * sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(_p_shift, p_shift, M * XRES * numChannels * sizeof(double), cudaMemcpyHostToDevice);
_computeGradient << < 1, M* XRES* numChannels >> > (_pdist_prior, _p_shift, _dp, XRES);
cudaMemcpy(dp, _dp, M * XRES * numChannels * sizeof(double), cudaMemcpyDeviceToHost);
// memcpy dp(dist_prior) => dpshift(dist_prior)
for (int m = 0; m < M; m++) {
for (int n = 0; n < numChannels; n++) {
memcpy(&dp_shift[1 + n * XRES + m * (XRES * numChannels)],
&dp[0 + n * XRES + m * (XRES * numChannels)],
(XRES - 1) * sizeof(double));
dp_shift[0 + n * XRES + m * (XRES * numChannels)] = dp_shift[1 + n * XRES + m * (XRES * numChannels)];
}
}
//cudaMemcpy(_dp, dp, M * XRES * numChannels * sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(_dp_shift, dp_shift, M * XRES * numChannels * sizeof(double), cudaMemcpyHostToDevice);
_computeGradient << < 1, M* XRES* numChannels >> > (_dp, _dp_shift, _ddp, XRES);
cudaMemcpy(ddp, _ddp, M * XRES * numChannels * sizeof(double), cudaMemcpyDeviceToHost);
_computeWeightedSum << < 1, M* XRES* numChannels >> > (_pdist_prior, _ddp, alpha);
cudaMemcpy(pdist_prior, _pdist_prior, M * XRES * numChannels * sizeof(double), cudaMemcpyDeviceToHost);
cudaFree(_pdist_prior);
cudaFree(_p_shift);
cudaFree(_dp_shift);
cudaFree(_dp);
cudaFree(_ddp);
}
else {
computeDiffusion();
}
normalizePrior();
computeLikelihood(xnew, sig2_update);
//normalizeLikelihood();
if (bGPU_product) {
cudaMalloc(&_pdist_prior, M * XRES * numChannels * sizeof(double));
cudaMalloc(&_pdist_lik, M * XRES * numChannels * sizeof(double));
cudaMalloc(&_pdist_post, M * XRES * numChannels * sizeof(double));
cudaMemcpy(_pdist_prior, pdist_prior, M * XRES * numChannels * sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(_pdist_lik, pdist_lik, M * XRES * numChannels * sizeof(double), cudaMemcpyHostToDevice);
_computeProduct << < M * XRES * numChannels, 1 >> > (_pdist_prior, _pdist_lik, _pdist_post);
cudaMemcpy(pdist_post, _pdist_post, M * XRES * numChannels * sizeof(double), cudaMemcpyDeviceToHost);
cudaFree(_pdist_prior);
cudaFree(_pdist_lik);
cudaFree(_pdist_post);
}
else {
computeProduct();
}
normalizePost();
// get maximum likelihood probability
for (int m = 0; m < M; m++) {
p_lik[m] = 0;
for (int n = 0; n < numChannels; n++) {
p_lik[m] += log10(pdist_post[idnew[n] + n * XRES + m * numChannels * XRES]);
}
//if (p_lik[m] < 1e-200) p_lik[m] = 1e-200;
// MLE prediction
if (p_lik[m] > p_max) {
p_max = p_lik[m];
mpred = m;
}
}
}
// registration
if (bFuncRegistration) {
if ((p_max < p_star) && (reglast > reghold) && (samples > 2 * WIN_MAV)) {
registerPattern(xnew, sig2_reg);
p_lik[M] = 0;
for (int n = 0; n < numChannels; n++) {
p_lik[M] += log10(pdist_post[idnew[n] + n * XRES + M * numChannels * XRES]);
}
p_max = p_lik[M];
mpred = M;
M += 1;
reglast = 0;
bRegister = true;
}
memcpy(&pdist_prior[mpred * XRES * numChannels], &pdist_post[mpred * XRES * numChannels], XRES * numChannels * sizeof(double));
}
bCollect = false;
bCompute = true;
}
else {
return;
}
}
void TFcore::writeResult() {
outputFile << p_max << ',' << mpred << ',';
for (int n = 0; n < numChannels; n++) outputFile << xnew[n] << ',';
outputFile << endl;
}
void TFcore::exportModel(fs::path filename) {
fstream file;
file.open(filename, ios::out | ios::binary);
file.write(reinterpret_cast<char*>(&numChannels), sizeof(int));
file.write(reinterpret_cast<char*>(&M_MAX), sizeof(int));
file.write(reinterpret_cast<char*>(&xmax), sizeof(double));
file.write(reinterpret_cast<char*>(&XRES), sizeof(int));
file.write(reinterpret_cast<char*>(&WIN_MAV), sizeof(int));
file.write(reinterpret_cast<char*>(&alpha), sizeof(double));
file.write(reinterpret_cast<char*>(&beta), sizeof(double));
file.write(reinterpret_cast<char*>(&p_star), sizeof(double));
file.write(reinterpret_cast<char*>(&M), sizeof(int));
file.write(reinterpret_cast<char*>(®hold), sizeof(int));
file.write(reinterpret_cast<char*>(&tableSize), sizeof(int));
file.write(reinterpret_cast<char*>(&discretizeStep), sizeof(int));
for (int k = 0; k < tableSize; k++) {
file.write(reinterpret_cast<char*>(&normalTable[k]), sizeof(double));
}
for (int n = 0; n < numChannels; n++) {
file.write(reinterpret_cast<char*>(&sig2_reg[n]), sizeof(double));
file.write(reinterpret_cast<char*>(&sig2_update[n]), sizeof(double));
}
for (int m = 0; m < M; m++) {
for (int n = 0; n < numChannels; n++) {
for (int k = 0; k < XRES; k++) {
file.write(reinterpret_cast<char*>(&pdist_prior[k + n * XRES + m * XRES * numChannels]), sizeof(double));
file.write(reinterpret_cast<char*>(&pdist_post[k + n * XRES + m * XRES * numChannels]), sizeof(double));
}
}
}
file.close();
}
void TFcore::importModel(fs::path filename) {
fstream file;
file.open(filename, ios::in | ios::binary);
file.read(reinterpret_cast<char*>(&numChannels), sizeof(int));
file.read(reinterpret_cast<char*>(&M_MAX), sizeof(int));
file.read(reinterpret_cast<char*>(&xmax), sizeof(double));
file.read(reinterpret_cast<char*>(&XRES), sizeof(int));
file.read(reinterpret_cast<char*>(&WIN_MAV), sizeof(int));
cout << "numChannels: " << numChannels << endl;
cout << "M_MAX: " << M_MAX << endl;
cout << "xmax: " << xmax << endl;
cout << "XRES: " << XRES << endl;
cout << "WIN_MAV: " << WIN_MAV << endl;
file.read(reinterpret_cast<char*>(&alpha), sizeof(double));
file.read(reinterpret_cast<char*>(&beta), sizeof(double));
file.read(reinterpret_cast<char*>(&p_star), sizeof(double));
cout << "alpha: " << alpha << endl;
cout << "beta: " << beta << endl;
cout << "p_star: " << p_star << endl;
file.read(reinterpret_cast<char*>(&M), sizeof(int));
file.read(reinterpret_cast<char*>(®hold), sizeof(int));
cout << "M: " << M << endl;
cout << "reghold: " << reghold << endl;
file.read(reinterpret_cast<char*>(&tableSize), sizeof(int));
file.read(reinterpret_cast<char*>(&discretizeStep), sizeof(int));
cout << "tableSize: " << tableSize << endl;
cout << "discretizeStep: " << discretizeStep << endl;
for (int k = 0; k < tableSize; k++) {
file.read(reinterpret_cast<char*>(&normalTable[k]), sizeof(double));
}
cout << "normalTable" << endl;
for (int n = 0; n < numChannels; n++) {
file.read(reinterpret_cast<char*>(&sig2_reg[n]), sizeof(double));
file.read(reinterpret_cast<char*>(&sig2_update[n]), sizeof(double));
}
cout << "sig2" << endl;
for (int m = 0; m < M; m++) {
for (int n = 0; n < numChannels; n++) {
for (int k = 0; k < XRES; k++) {
file.read(reinterpret_cast<char*>(&pdist_prior[k + n * XRES + m * XRES * numChannels]), sizeof(double));
file.read(reinterpret_cast<char*>(&pdist_post[k + n * XRES + m * XRES * numChannels]), sizeof(double));
}
}
}
cout << "pdist" << endl;
file.close();
}
void TFcore::computeDiffusion() {
// pdist_prior => pshift(dist_prior)
for (int m = 0; m < M; m++) {
for (int n = 0; n < numChannels; n++) {
memcpy(&p_shift[1 + n * XRES + m * (XRES * numChannels)],
&pdist_prior[0 + n * XRES + m * (XRES * numChannels)],
(XRES - 1) * sizeof(double));
p_shift[0 + n * XRES + m * (XRES * numChannels)] = p_shift[1 + n * XRES + m * (XRES * numChannels)];
}
}
// compute (p, pshift) => dp
for (int m = 0; m < M; m++) {
for (int n = 0; n < numChannels; n++) {
for (int k = 0; k < XRES; k++) {
dp[k + n * XRES + m * XRES * numChannels]
= (double)XRES * (pdist_prior[k + n * XRES + m * XRES * numChannels] - p_shift[k + n * XRES + m * XRES * numChannels]);
}
}
}
// memcpy dp(dist_prior) => dpshift(dist_prior)
for (int m = 0; m < M; m++) {
for (int n = 0; n < numChannels; n++) {
memcpy(&dp_shift[1 + n * XRES + m * (XRES * numChannels)],
&dp[0 + n * XRES + m * (XRES * numChannels)],
(XRES - 1) * sizeof(double));
dp_shift[0 + n * XRES + m * (XRES * numChannels)] = dp_shift[1 + n * XRES + m * (XRES * numChannels)];
}
}
// compute (dp, dpshift) => ddp
for (int m = 0; m < M; m++) {
for (int n = 0; n < numChannels; n++) {
for (int k = 0; k < XRES; k++) {
ddp[k + n * XRES + m * XRES * numChannels]
= (double)XRES * (dp[k + n * XRES + m * XRES * numChannels] - dp_shift[k + n * XRES + m * XRES * numChannels]);
}
}
}
// weighted summation
for (int m = 0; m < M; m++) {
for (int n = 0; n < numChannels; n++) {
for (int k = 0; k < XRES; k++) {
pdist_prior[k + n * XRES + m * XRES * numChannels]
= pdist_prior[k + n * XRES + m * XRES * numChannels] + alpha * ddp[k + n * XRES + m * XRES * numChannels];
}
}
}
}
void TFcore::computeProduct() {
for (int m = 0; m < M; m++) {
for (int n = 0; n < numChannels; n++) {
for (int k = 0; k < XRES; k++) {
pdist_post[k + n * XRES + m * XRES * numChannels]
= pdist_prior[k + n * XRES + m * XRES * numChannels]
* pdist_lik[k + n * XRES + m * XRES * numChannels];
}
}
}
}
void TFcore::loadData(string filename) {
string extension = filename.substr(filename.find_last_of(".") + 1);
//if (!strcmp(extension.c_str(), "mat")) {
// MATFile* pmat = matOpen(filename.c_str(), "r");
// if (pmat == NULL) {
// return;
// }
// mxArray* mxdata = matGetVariable(pmat, "emg");
// int m, n;
// m = mxGetM(mxdata);
// n = mxGetN(mxdata);
// double* data = mxGetPr(mxdata);
// for (int i = 0; i < m * n; i++) {
// dataStack.push_back(data[i]);
// }
// initModel(n);
// setNumSamples(m);
// mxDestroyArray(mxdata);
// matClose(pmat);
//}
if (!strcmp(extension.c_str(), "csv")) {
// comma separated file (samples x channels)
inputFile.open(filename.c_str(), ios::in);
int m = 0;
int n = 0;
string data;
string line;
stringstream parse;
getline(inputFile, line, '\n'); m++;
parse.str(line);
while (getline(parse, data, ',')) n++;
while (getline(inputFile, line, '\n')) m++;
inputFile.clear();
inputFile.seekg(0, ios::beg);
initModel(n);
setNumSamples(m);
}
}
void TFcore::loadData(fs::path filename) {
if (filename.extension() == ".csv") {
// comma separated file (samples x channels)
inputFile.open(filename, ios::in);
int m = 0;
int n = 0;
string data;
string line;
stringstream parse;
getline(inputFile, line, '\n'); m++;
parse.str(line);
while (getline(parse, data, ',')) n++;
while (getline(inputFile, line, '\n')) m++;
inputFile.clear();
inputFile.seekg(0, ios::beg);
initModel(n);
setNumSamples(m);
}
}
void TFcore::loadData(vector<double> data, int ch) {
initModel(ch);
setNumSamples(data.size() / ch);
for (int k = 0; k < data.size(); k++) dataStack.push_back(data[k]);
}
void TFcore::computeLikelihood(double* mu, double* sig2) {
double* Z = (double*)calloc(XRES * numChannels, sizeof(double));
int id = 0;
for (int k = 0; k < XRES; k++) {
for (int n = 0; n < numChannels; n++) {
Z[k + n * XRES] = abs(((k + 1) / (double)XRES) - mu[n]);
Z[k + n * XRES] *= discretizeStep / sqrt(sig2[n]);
id = floor(abs(Z[k + n * XRES]));
if (id < tableSize) {
pdist_lik[k + n * XRES] = normalTable[id];
}
else {
pdist_lik[k + n * XRES] = EPSILON;
}
}
}
// memcpy ÀÌÀü¿¡ normalize Çعö¸²
double psum;
for (int n = 0; n < numChannels; n++) {
psum = 0;
for (int k = 0; k < XRES; k++) psum += pdist_lik[k + n * XRES];
for (int k = 0; k < XRES; k++) pdist_lik[k + n * XRES] /= psum;
}
if (M > 1) {
for (int m = 1; m < M; m++) memcpy(&pdist_lik[m * XRES * numChannels], &pdist_lik[0], XRES * numChannels * sizeof(double));
}
free(Z);
}
void TFcore::registerPattern(double* mu, double* sig2) {
double* Z = (double*)calloc(XRES * numChannels, sizeof(double));
int id = 0;
for (int n = 0; n < numChannels; n++) {
for (int k = 0; k < XRES; k++) {
Z[k + n * XRES] = abs(((k + 1) / (double)XRES) - mu[n]);
Z[k + n * XRES] *= discretizeStep / sqrt(sig2[n]);
id = floor(abs(Z[k + n * XRES]));
if (id < tableSize) {
pdist_post[k + n * XRES + M * XRES * numChannels] = normalTable[id];
}
else {
pdist_post[k + n * XRES + M * XRES * numChannels] = EPSILON;
}
}
}
double psum;
for (int n = 0; n < numChannels; n++) {
psum = 0;
for (int k = 0; k < XRES; k++) psum += pdist_post[k + n * XRES + M * XRES * numChannels];
for (int k = 0; k < XRES; k++) pdist_post[k + n * XRES + M * XRES * numChannels] /= psum;
}
free(Z);
}
void TFcore::normalizeLikelihood() {
double psum;
for (int m = 0; m < M; m++) {
for (int n = 0; n < numChannels; n++) {
psum = 0;
for (int k = 0; k < XRES; k++) psum += pdist_lik[k + n * XRES + m * XRES * numChannels];
for (int k = 0; k < XRES; k++) pdist_lik[k + n * XRES + m * XRES * numChannels] /= psum;
}
}
}
void TFcore::normalizePrior() {
double psum;
for (int m = 0; m < M; m++) {
for (int n = 0; n < numChannels; n++) {
psum = 0;
for (int k = 0; k < XRES; k++) psum += pdist_prior[k + n * XRES + m * XRES * numChannels];
for (int k = 0; k < XRES; k++) pdist_prior[k + n * XRES + m * XRES * numChannels] /= psum;
}
}
}
void TFcore::normalizePost() {
double psum;
for (int m = 0; m < M; m++) {
for (int n = 0; n < numChannels; n++) {
psum = 0;
for (int k = 0; k < XRES; k++) psum += pdist_post[k + n * XRES + m * XRES * numChannels];
for (int k = 0; k < XRES; k++) pdist_post[k + n * XRES + m * XRES * numChannels] /= psum;
}
}
}
void TFcore::constructLookup() {
for (int i = 0; i < tableSize; i++) {
normalTable[i] = (1 / sqrt(2 * M_PI)) * exp(-0.5 * ((double)i / discretizeStep) * ((double)i / discretizeStep));
}
}
void TFcore::setVal(double* vector, double val) {
for (int k = 0; k < numChannels; k++) {
vector[k] = val;
}
}
void TFcore::setZero(double* vector) {
setVal(vector, (double)0);
}
void TFcore::setOnes(double* vector) {
setVal(vector, (double)1);
} | code for sm_80
Function : _Z15_computeProductPdS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R8, R9, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x000fc800078e0209 */
/*0070*/ IMAD.WIDE R4, R8.reuse, R9.reuse, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x0c0fe400078e0209 */
/*0080*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*0090*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0209 */
/*00b0*/ DMUL R6, R2, R4 ; /* 0x0000000402067228 */
/* 0x004e0e0000000000 */
/*00c0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z19_computeWeightedSumPdS_d
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R6, R2, R5, c[0x0][0x168] ; /* 0x00005a0002067625 */
/* 0x000fc800078e0205 */
/*0070*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe400078e0205 */
/*0080*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1b00 */
/*0090*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1b00 */
/*00a0*/ DFMA R4, R6, c[0x0][0x170], R4 ; /* 0x00005c0006047a2b */
/* 0x004e0e0000000004 */
/*00b0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe2000c101b04 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z16_computeGradientPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R11, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0b7435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R0, R11, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e020b */
/*0070*/ IMAD.WIDE R4, R0, R11, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe400078e020b */
/*0080*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*0090*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ I2F.F64 R8, c[0x0][0x178] ; /* 0x00005e0000087b12 */
/* 0x000e220000201c00 */
/*00b0*/ DADD R6, R2, -R4 ; /* 0x0000000002067229 */
/* 0x004e0c0000000804 */
/*00c0*/ DMUL R6, R6, R8 ; /* 0x0000000806067228 */
/* 0x0010640000000000 */
/*00d0*/ IMAD.WIDE R8, R0, R11, c[0x0][0x170] ; /* 0x00005c0000087625 */
/* 0x001fca00078e020b */
/*00e0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x002fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "TFcore.cuh"
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
__global__ void _computeGradient(double* p, double* pshift, double* dp, int XRES) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
dp[i] = (p[i] - pshift[i]) * (double)XRES;
}
__global__ void _computeWeightedSum(double* p, double* ddp, double alpha) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
//p[i] += alpha * ddp[i] + beta * ((1 / (double)XRES) - p[i]);
p[i] = p[i] + alpha * ddp[i];
}
//__global__ void normalizeProb(double* pdist) {
// // <<< M, numChannels >>>
// int numChannels = blockDim.x;
// int m = blockIdx.x;
// int n = threadIdx.x;
//
// double psum = 0;
// for (int k = 0; k < XRES; k++) psum += pdist[k + n * XRES + m * numChannels * XRES];
// for (int k = 0; k < XRES; k++) pdist[k + n * XRES + m * numChannels * XRES] /= psum;
//}
__global__ void _computeProduct(double* pdist_prior, double* pdist_lik, double* pdist_post) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
pdist_post[i] = pdist_prior[i] * pdist_lik[i];
}
TFcore::TFcore() {
}
TFcore::TFcore(string filename) {
outputFile.open(filename, ios::out);
}
TFcore::TFcore(fs::path filename) {
outputFile.open(filename, ios::out);
}
//TFcore::TFcore(CTFcoreMFCDlg& dlg) : dlg_(dlg) {
// TFcore();
//}
TFcore::~TFcore() {
free(mu_init);
free(sig2_init);
free(sig2_reg);
free(sig2_update);
free(xbin);
free(xnew);
free(idnew);
free(emgMAV);
free(emgStack);
free(pdist_prior);
free(pdist_post);
free(pdist_lik);
inputFile.close();
outputFile.close();
}
void TFcore::initModel(int n) {
M = 1;
reglast = 0;
samples = 0;
bCollect = false;
bCompute = false;
bRegister = false;
bGPU_product = false;
bGPU_diffusion = false;
bFuncRegistration = true;
bFuncAdaptation = true;
XRES = 128;
WIN_MAV = 1024;
M_MAX = 2048;
// set channel
setNumChannels(n);
// memory allocation
mu_init = (double*)calloc(numChannels, sizeof(double));
sig2_init = (double*)calloc(numChannels, sizeof(double));
sig2_reg = (double*)calloc(numChannels, sizeof(double));
sig2_update = (double*)calloc(numChannels, sizeof(double));
emgMAV = (double*)calloc(numChannels, sizeof(double));
xnew = (double*)calloc(numChannels, sizeof(double));
idnew = (int*)calloc(numChannels, sizeof(int));
xbin = (double*)calloc(XRES, sizeof(double));
for (int k = 0; k < XRES; k++) xbin[k] = ((k + 1) / (double)(XRES));
emgStack = (double*)calloc(WIN_MAV * numChannels, sizeof(double));
// lookup table for normal distribution
tableSize = 10000;
discretizeStep = 1000;
normalTable = (double*)calloc(tableSize, sizeof(double));
constructLookup();
// distribution = max number of patterns
pdist_prior = (double*)calloc(XRES * numChannels * M_MAX, sizeof(double));
pdist_post = (double*)calloc(XRES * numChannels * M_MAX, sizeof(double));
pdist_lik = (double*)calloc(XRES * numChannels * M_MAX, sizeof(double));
dp = (double*)calloc(XRES * numChannels * M_MAX, sizeof(double));
ddp = (double*)calloc(XRES * numChannels * M_MAX, sizeof(double));
p_shift = (double*)calloc(XRES * numChannels * M_MAX, sizeof(double));
dp_shift = (double*)calloc(XRES * numChannels * M_MAX, sizeof(double));
p_lik = (double*)calloc(M_MAX, sizeof(double));
for (int m = 0; m < M_MAX; m++) {
p_lik[m] = NAN;
for (int n = 0; n < numChannels; n++) {
for (int k = 0; k < XRES; k++) {
pdist_prior[k + n * XRES + m * XRES * numChannels] = NAN;
pdist_post[k + n * XRES + m * XRES * numChannels] = NAN;
pdist_lik[k + n * XRES + m * XRES * numChannels] = NAN;
dp[k + n * XRES + m * XRES * numChannels] = 0;
ddp[k + n * XRES + m * XRES * numChannels] = 0;
p_shift[k + n * XRES + m * XRES * numChannels] = (1 / (double)XRES);
dp_shift[k + n * XRES + m * XRES * numChannels] = 0;
}
}
}
// model parameter
xmax = 5.00e-5;
alpha = 1.00e-10;
beta = 1.00e-50;
p_star = -20;
reghold = 512;
setVal(mu_init, 3.00e-2);
setVal(sig2_init, 1.00e-1);
setVal(sig2_reg, 1.00e-2);
setVal(sig2_update, 1.00e+2);
setZero(emgMAV);
// initialize first pattern
for (int n = 0; n < numChannels; n++) {
for (int k = 0; k < XRES; k++) {
// assign uniform distribution
pdist_prior[k + n * XRES] = (1 / (double)XRES);
pdist_post[k + n * XRES] = (1 / (double)XRES);
pdist_lik[k + n * XRES] = (1 / (double)XRES);
dp[k + n * XRES] = 0;
ddp[k + n * XRES] = 0;
p_shift[k + n * XRES] = (1 / (double)XRES);
dp_shift[k + n * XRES] = (1 / (double)XRES);
}
}
_pdist_prior = nullptr;
_pdist_lik = nullptr;
_pdist_post = nullptr;
_p_shift = nullptr;
_dp_shift = nullptr;
_dp = nullptr;
_ddp = nullptr;
if (!outputFile.is_open()) outputFile.open("output.csv", ios::out);
}
void TFcore::getSample() {
samples++;
// a vertical stack of row samples to compute MAV
// the first row = the latest sample
string data;
string line;
stringstream parse;
//for (int n = 0; n < numChannels; n++) {
//memcpy(&emgStack[1 + n * WIN_MAV], &emgStack[0 + n * WIN_MAV], (WIN_MAV - 1) * sizeof(double));
//emgStack[n * WIN_MAV] = dataStack.front();
//dataStack.erase(dataStack.begin());
//}
getline(inputFile, line, '\n');
parse.str(line);
for (int n = 0; n < numChannels; n++) {
memcpy(&emgStack[1 + n * WIN_MAV], &emgStack[0 + n * WIN_MAV], (WIN_MAV - 1) * sizeof(double));
getline(parse, data, ',');
emgStack[n * WIN_MAV] = stod(data);
}
// compute MAV = a single row vector
for (int n = 0; n < numChannels; n++) {
emgMAV[n] = 0;
for (int m = 0; m < WIN_MAV; m++) {
emgMAV[n] += abs(emgStack[m + n * WIN_MAV]) / (double)(WIN_MAV);
}
}
bCollect = true;
bCompute = false;
}
void TFcore::proceedIteration() {
if (isCollect() && (samples > 2 * WIN_MAV)) {
bRegister = false;
reglast += 1;
p_max = -999;
mpred = 0;
for (int n = 0; n < numChannels; n++) {
xnew[n] = (1 / xmax) * emgMAV[n];
xnew[n] = min((double)1, xnew[n]);
idnew[n] = floor(xnew[n] * (double)(XRES));
if (idnew[n] > (XRES - 1)) idnew[n] = XRES - 1;
}
if (bFuncAdaptation) {
if (bGPU_diffusion) {
cudaMalloc(&_pdist_prior, M * XRES * numChannels * sizeof(double));
cudaMalloc(&_p_shift, M * XRES * numChannels * sizeof(double));
cudaMalloc(&_dp_shift, M * XRES * numChannels * sizeof(double));
cudaMalloc(&_dp, M * XRES * numChannels * sizeof(double));
cudaMalloc(&_ddp, M * XRES * numChannels * sizeof(double));
// memcpy pdist_prior => pshift(dist_prior)
for (int m = 0; m < M; m++) {
for (int n = 0; n < numChannels; n++) {
memcpy(&p_shift[1 + n * XRES + m * (XRES * numChannels)],
&pdist_prior[0 + n * XRES + m * (XRES * numChannels)],
(XRES - 1) * sizeof(double));
p_shift[0 + n * XRES + m * (XRES * numChannels)] = p_shift[1 + n * XRES + m * (XRES * numChannels)];
}
}
cudaMemcpy(_pdist_prior, pdist_prior, M * XRES * numChannels * sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(_p_shift, p_shift, M * XRES * numChannels * sizeof(double), cudaMemcpyHostToDevice);
_computeGradient << < 1, M* XRES* numChannels >> > (_pdist_prior, _p_shift, _dp, XRES);
cudaMemcpy(dp, _dp, M * XRES * numChannels * sizeof(double), cudaMemcpyDeviceToHost);
// memcpy dp(dist_prior) => dpshift(dist_prior)
for (int m = 0; m < M; m++) {
for (int n = 0; n < numChannels; n++) {
memcpy(&dp_shift[1 + n * XRES + m * (XRES * numChannels)],
&dp[0 + n * XRES + m * (XRES * numChannels)],
(XRES - 1) * sizeof(double));
dp_shift[0 + n * XRES + m * (XRES * numChannels)] = dp_shift[1 + n * XRES + m * (XRES * numChannels)];
}
}
//cudaMemcpy(_dp, dp, M * XRES * numChannels * sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(_dp_shift, dp_shift, M * XRES * numChannels * sizeof(double), cudaMemcpyHostToDevice);
_computeGradient << < 1, M* XRES* numChannels >> > (_dp, _dp_shift, _ddp, XRES);
cudaMemcpy(ddp, _ddp, M * XRES * numChannels * sizeof(double), cudaMemcpyDeviceToHost);
_computeWeightedSum << < 1, M* XRES* numChannels >> > (_pdist_prior, _ddp, alpha);
cudaMemcpy(pdist_prior, _pdist_prior, M * XRES * numChannels * sizeof(double), cudaMemcpyDeviceToHost);
cudaFree(_pdist_prior);
cudaFree(_p_shift);
cudaFree(_dp_shift);
cudaFree(_dp);
cudaFree(_ddp);
}
else {
computeDiffusion();
}
normalizePrior();
computeLikelihood(xnew, sig2_update);
//normalizeLikelihood();
if (bGPU_product) {
cudaMalloc(&_pdist_prior, M * XRES * numChannels * sizeof(double));
cudaMalloc(&_pdist_lik, M * XRES * numChannels * sizeof(double));
cudaMalloc(&_pdist_post, M * XRES * numChannels * sizeof(double));
cudaMemcpy(_pdist_prior, pdist_prior, M * XRES * numChannels * sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(_pdist_lik, pdist_lik, M * XRES * numChannels * sizeof(double), cudaMemcpyHostToDevice);
_computeProduct << < M * XRES * numChannels, 1 >> > (_pdist_prior, _pdist_lik, _pdist_post);
cudaMemcpy(pdist_post, _pdist_post, M * XRES * numChannels * sizeof(double), cudaMemcpyDeviceToHost);
cudaFree(_pdist_prior);
cudaFree(_pdist_lik);
cudaFree(_pdist_post);
}
else {
computeProduct();
}
normalizePost();
// get maximum likelihood probability
for (int m = 0; m < M; m++) {
p_lik[m] = 0;
for (int n = 0; n < numChannels; n++) {
p_lik[m] += log10(pdist_post[idnew[n] + n * XRES + m * numChannels * XRES]);
}
//if (p_lik[m] < 1e-200) p_lik[m] = 1e-200;
// MLE prediction
if (p_lik[m] > p_max) {
p_max = p_lik[m];
mpred = m;
}
}
}
// registration
if (bFuncRegistration) {
if ((p_max < p_star) && (reglast > reghold) && (samples > 2 * WIN_MAV)) {
registerPattern(xnew, sig2_reg);
p_lik[M] = 0;
for (int n = 0; n < numChannels; n++) {
p_lik[M] += log10(pdist_post[idnew[n] + n * XRES + M * numChannels * XRES]);
}
p_max = p_lik[M];
mpred = M;
M += 1;
reglast = 0;
bRegister = true;
}
memcpy(&pdist_prior[mpred * XRES * numChannels], &pdist_post[mpred * XRES * numChannels], XRES * numChannels * sizeof(double));
}
bCollect = false;
bCompute = true;
}
else {
return;
}
}
void TFcore::writeResult() {
outputFile << p_max << ',' << mpred << ',';
for (int n = 0; n < numChannels; n++) outputFile << xnew[n] << ',';
outputFile << endl;
}
void TFcore::exportModel(fs::path filename) {
fstream file;
file.open(filename, ios::out | ios::binary);
file.write(reinterpret_cast<char*>(&numChannels), sizeof(int));
file.write(reinterpret_cast<char*>(&M_MAX), sizeof(int));
file.write(reinterpret_cast<char*>(&xmax), sizeof(double));
file.write(reinterpret_cast<char*>(&XRES), sizeof(int));
file.write(reinterpret_cast<char*>(&WIN_MAV), sizeof(int));
file.write(reinterpret_cast<char*>(&alpha), sizeof(double));
file.write(reinterpret_cast<char*>(&beta), sizeof(double));
file.write(reinterpret_cast<char*>(&p_star), sizeof(double));
file.write(reinterpret_cast<char*>(&M), sizeof(int));
file.write(reinterpret_cast<char*>(®hold), sizeof(int));
file.write(reinterpret_cast<char*>(&tableSize), sizeof(int));
file.write(reinterpret_cast<char*>(&discretizeStep), sizeof(int));
for (int k = 0; k < tableSize; k++) {
file.write(reinterpret_cast<char*>(&normalTable[k]), sizeof(double));
}
for (int n = 0; n < numChannels; n++) {
file.write(reinterpret_cast<char*>(&sig2_reg[n]), sizeof(double));
file.write(reinterpret_cast<char*>(&sig2_update[n]), sizeof(double));
}
for (int m = 0; m < M; m++) {
for (int n = 0; n < numChannels; n++) {
for (int k = 0; k < XRES; k++) {
file.write(reinterpret_cast<char*>(&pdist_prior[k + n * XRES + m * XRES * numChannels]), sizeof(double));
file.write(reinterpret_cast<char*>(&pdist_post[k + n * XRES + m * XRES * numChannels]), sizeof(double));
}
}
}
file.close();
}
void TFcore::importModel(fs::path filename) {
fstream file;
file.open(filename, ios::in | ios::binary);
file.read(reinterpret_cast<char*>(&numChannels), sizeof(int));
file.read(reinterpret_cast<char*>(&M_MAX), sizeof(int));
file.read(reinterpret_cast<char*>(&xmax), sizeof(double));
file.read(reinterpret_cast<char*>(&XRES), sizeof(int));
file.read(reinterpret_cast<char*>(&WIN_MAV), sizeof(int));
cout << "numChannels: " << numChannels << endl;
cout << "M_MAX: " << M_MAX << endl;
cout << "xmax: " << xmax << endl;
cout << "XRES: " << XRES << endl;
cout << "WIN_MAV: " << WIN_MAV << endl;
file.read(reinterpret_cast<char*>(&alpha), sizeof(double));
file.read(reinterpret_cast<char*>(&beta), sizeof(double));
file.read(reinterpret_cast<char*>(&p_star), sizeof(double));
cout << "alpha: " << alpha << endl;
cout << "beta: " << beta << endl;
cout << "p_star: " << p_star << endl;
file.read(reinterpret_cast<char*>(&M), sizeof(int));
file.read(reinterpret_cast<char*>(®hold), sizeof(int));
cout << "M: " << M << endl;
cout << "reghold: " << reghold << endl;
file.read(reinterpret_cast<char*>(&tableSize), sizeof(int));
file.read(reinterpret_cast<char*>(&discretizeStep), sizeof(int));
cout << "tableSize: " << tableSize << endl;
cout << "discretizeStep: " << discretizeStep << endl;
for (int k = 0; k < tableSize; k++) {
file.read(reinterpret_cast<char*>(&normalTable[k]), sizeof(double));
}
cout << "normalTable" << endl;
for (int n = 0; n < numChannels; n++) {
file.read(reinterpret_cast<char*>(&sig2_reg[n]), sizeof(double));
file.read(reinterpret_cast<char*>(&sig2_update[n]), sizeof(double));
}
cout << "sig2" << endl;
for (int m = 0; m < M; m++) {
for (int n = 0; n < numChannels; n++) {
for (int k = 0; k < XRES; k++) {
file.read(reinterpret_cast<char*>(&pdist_prior[k + n * XRES + m * XRES * numChannels]), sizeof(double));
file.read(reinterpret_cast<char*>(&pdist_post[k + n * XRES + m * XRES * numChannels]), sizeof(double));
}
}
}
cout << "pdist" << endl;
file.close();
}
void TFcore::computeDiffusion() {
// pdist_prior => pshift(dist_prior)
for (int m = 0; m < M; m++) {
for (int n = 0; n < numChannels; n++) {
memcpy(&p_shift[1 + n * XRES + m * (XRES * numChannels)],
&pdist_prior[0 + n * XRES + m * (XRES * numChannels)],
(XRES - 1) * sizeof(double));
p_shift[0 + n * XRES + m * (XRES * numChannels)] = p_shift[1 + n * XRES + m * (XRES * numChannels)];
}
}
// compute (p, pshift) => dp
for (int m = 0; m < M; m++) {
for (int n = 0; n < numChannels; n++) {
for (int k = 0; k < XRES; k++) {
dp[k + n * XRES + m * XRES * numChannels]
= (double)XRES * (pdist_prior[k + n * XRES + m * XRES * numChannels] - p_shift[k + n * XRES + m * XRES * numChannels]);
}
}
}
// memcpy dp(dist_prior) => dpshift(dist_prior)
for (int m = 0; m < M; m++) {
for (int n = 0; n < numChannels; n++) {
memcpy(&dp_shift[1 + n * XRES + m * (XRES * numChannels)],
&dp[0 + n * XRES + m * (XRES * numChannels)],
(XRES - 1) * sizeof(double));
dp_shift[0 + n * XRES + m * (XRES * numChannels)] = dp_shift[1 + n * XRES + m * (XRES * numChannels)];
}
}
// compute (dp, dpshift) => ddp
for (int m = 0; m < M; m++) {
for (int n = 0; n < numChannels; n++) {
for (int k = 0; k < XRES; k++) {
ddp[k + n * XRES + m * XRES * numChannels]
= (double)XRES * (dp[k + n * XRES + m * XRES * numChannels] - dp_shift[k + n * XRES + m * XRES * numChannels]);
}
}
}
// weighted summation
for (int m = 0; m < M; m++) {
for (int n = 0; n < numChannels; n++) {
for (int k = 0; k < XRES; k++) {
pdist_prior[k + n * XRES + m * XRES * numChannels]
= pdist_prior[k + n * XRES + m * XRES * numChannels] + alpha * ddp[k + n * XRES + m * XRES * numChannels];
}
}
}
}
void TFcore::computeProduct() {
for (int m = 0; m < M; m++) {
for (int n = 0; n < numChannels; n++) {
for (int k = 0; k < XRES; k++) {
pdist_post[k + n * XRES + m * XRES * numChannels]
= pdist_prior[k + n * XRES + m * XRES * numChannels]
* pdist_lik[k + n * XRES + m * XRES * numChannels];
}
}
}
}
void TFcore::loadData(string filename) {
string extension = filename.substr(filename.find_last_of(".") + 1);
//if (!strcmp(extension.c_str(), "mat")) {
// MATFile* pmat = matOpen(filename.c_str(), "r");
// if (pmat == NULL) {
// return;
// }
// mxArray* mxdata = matGetVariable(pmat, "emg");
// int m, n;
// m = mxGetM(mxdata);
// n = mxGetN(mxdata);
// double* data = mxGetPr(mxdata);
// for (int i = 0; i < m * n; i++) {
// dataStack.push_back(data[i]);
// }
// initModel(n);
// setNumSamples(m);
// mxDestroyArray(mxdata);
// matClose(pmat);
//}
if (!strcmp(extension.c_str(), "csv")) {
// comma separated file (samples x channels)
inputFile.open(filename.c_str(), ios::in);
int m = 0;
int n = 0;
string data;
string line;
stringstream parse;
getline(inputFile, line, '\n'); m++;
parse.str(line);
while (getline(parse, data, ',')) n++;
while (getline(inputFile, line, '\n')) m++;
inputFile.clear();
inputFile.seekg(0, ios::beg);
initModel(n);
setNumSamples(m);
}
}
void TFcore::loadData(fs::path filename) {
if (filename.extension() == ".csv") {
// comma separated file (samples x channels)
inputFile.open(filename, ios::in);
int m = 0;
int n = 0;
string data;
string line;
stringstream parse;
getline(inputFile, line, '\n'); m++;
parse.str(line);
while (getline(parse, data, ',')) n++;
while (getline(inputFile, line, '\n')) m++;
inputFile.clear();
inputFile.seekg(0, ios::beg);
initModel(n);
setNumSamples(m);
}
}
void TFcore::loadData(vector<double> data, int ch) {
initModel(ch);
setNumSamples(data.size() / ch);
for (int k = 0; k < data.size(); k++) dataStack.push_back(data[k]);
}
void TFcore::computeLikelihood(double* mu, double* sig2) {
double* Z = (double*)calloc(XRES * numChannels, sizeof(double));
int id = 0;
for (int k = 0; k < XRES; k++) {
for (int n = 0; n < numChannels; n++) {
Z[k + n * XRES] = abs(((k + 1) / (double)XRES) - mu[n]);
Z[k + n * XRES] *= discretizeStep / sqrt(sig2[n]);
id = floor(abs(Z[k + n * XRES]));
if (id < tableSize) {
pdist_lik[k + n * XRES] = normalTable[id];
}
else {
pdist_lik[k + n * XRES] = EPSILON;
}
}
}
// memcpy ÀÌÀü¿¡ normalize Çعö¸²
double psum;
for (int n = 0; n < numChannels; n++) {
psum = 0;
for (int k = 0; k < XRES; k++) psum += pdist_lik[k + n * XRES];
for (int k = 0; k < XRES; k++) pdist_lik[k + n * XRES] /= psum;
}
if (M > 1) {
for (int m = 1; m < M; m++) memcpy(&pdist_lik[m * XRES * numChannels], &pdist_lik[0], XRES * numChannels * sizeof(double));
}
free(Z);
}
void TFcore::registerPattern(double* mu, double* sig2) {
double* Z = (double*)calloc(XRES * numChannels, sizeof(double));
int id = 0;
for (int n = 0; n < numChannels; n++) {
for (int k = 0; k < XRES; k++) {
Z[k + n * XRES] = abs(((k + 1) / (double)XRES) - mu[n]);
Z[k + n * XRES] *= discretizeStep / sqrt(sig2[n]);
id = floor(abs(Z[k + n * XRES]));
if (id < tableSize) {
pdist_post[k + n * XRES + M * XRES * numChannels] = normalTable[id];
}
else {
pdist_post[k + n * XRES + M * XRES * numChannels] = EPSILON;
}
}
}
double psum;
for (int n = 0; n < numChannels; n++) {
psum = 0;
for (int k = 0; k < XRES; k++) psum += pdist_post[k + n * XRES + M * XRES * numChannels];
for (int k = 0; k < XRES; k++) pdist_post[k + n * XRES + M * XRES * numChannels] /= psum;
}
free(Z);
}
void TFcore::normalizeLikelihood() {
double psum;
for (int m = 0; m < M; m++) {
for (int n = 0; n < numChannels; n++) {
psum = 0;
for (int k = 0; k < XRES; k++) psum += pdist_lik[k + n * XRES + m * XRES * numChannels];
for (int k = 0; k < XRES; k++) pdist_lik[k + n * XRES + m * XRES * numChannels] /= psum;
}
}
}
void TFcore::normalizePrior() {
double psum;
for (int m = 0; m < M; m++) {
for (int n = 0; n < numChannels; n++) {
psum = 0;
for (int k = 0; k < XRES; k++) psum += pdist_prior[k + n * XRES + m * XRES * numChannels];
for (int k = 0; k < XRES; k++) pdist_prior[k + n * XRES + m * XRES * numChannels] /= psum;
}
}
}
void TFcore::normalizePost() {
double psum;
for (int m = 0; m < M; m++) {
for (int n = 0; n < numChannels; n++) {
psum = 0;
for (int k = 0; k < XRES; k++) psum += pdist_post[k + n * XRES + m * XRES * numChannels];
for (int k = 0; k < XRES; k++) pdist_post[k + n * XRES + m * XRES * numChannels] /= psum;
}
}
}
void TFcore::constructLookup() {
for (int i = 0; i < tableSize; i++) {
normalTable[i] = (1 / sqrt(2 * M_PI)) * exp(-0.5 * ((double)i / discretizeStep) * ((double)i / discretizeStep));
}
}
void TFcore::setVal(double* vector, double val) {
for (int k = 0; k < numChannels; k++) {
vector[k] = val;
}
}
void TFcore::setZero(double* vector) {
setVal(vector, (double)0);
}
void TFcore::setOnes(double* vector) {
setVal(vector, (double)1);
} | #ifndef TFcore_H_
#include <hip/hip_runtime.h>
#define TFcore_H_
#pragma once
#include <array>
#define _SILENCE_EXPERIMENTAL_FILESYSTEM_DEPRECATION_WARNING
#include <experimental/filesystem>
#include <iostream>
#include <fstream>
#include <istream>
#include <sstream>
#define _USE_MATH_DEFINES
#include <math.h>
#include <iomanip>
#include <vector>
#include <string>
#define EPSILON 1.00e-10 // minimum value for probability distribution
using namespace std;
namespace fs = std::experimental::filesystem;
class CTFcoreMFCDlg;
class TFcore {
public:
TFcore();
TFcore(string filename);
TFcore(fs::path filename);
//TFcore(CTFcoreMFCDlg& dlg);
~TFcore();
private:
//CTFcoreMFCDlg& dlg_;
public:
void loadData(string filename);
void loadData(fs::path filename);
void loadData(vector<double> data, int ch);
public:
int getNumSamples() { return numSamples; }
int getNumChannels() { return numChannels; }
int getPredict() { return mpred; }
int getNumPatterns() { return M; }
//int getNumRemaining() { return ((int)dataStack.size() / numChannels); }
int getNumRemaining() { return (numSamples - samples); }
double getProbMax() { return p_max; }
double getProbThresh() { return p_star; }
public:
void resetModel() { initModel(numChannels); }
void initModel(int n);
void setNumSamples(int numsamples) { numSamples = numsamples; }
void setNumChannels(int numchannels) { numChannels = numchannels; }
public:
bool isCollect() { return bCollect; }
bool isCompute() { return bCompute; }
bool isRegister() { return bRegister; }
bool isRemaining() { return !inputFile.eof(); }
bool isGPU_Product() { return bGPU_product; }
bool isGPU_Diffusion() { return bGPU_diffusion; }
void enableGPU_Product() { bGPU_product = true; }
void disableGPU_Product() { bGPU_product = false; }
void enableGPU_Diffusion() { bGPU_diffusion = true; }
void disableGPU_Diffusion() { bGPU_diffusion = false; }
void enableRegistration() { bFuncRegistration = true; }
void disableRegistration() { bFuncRegistration = false; }
void enableAdaptation() { bFuncAdaptation = true; }
void disableAdaptation() { bFuncAdaptation = false; }
public:
void getSample();
void proceedIteration();
void writeResult();
public:
void exportModel(fs::path filename);
void importModel(fs::path filename);
private:
int numChannels;
int numSamples;
int samples;
int M_MAX;
double xmax;
int XRES;
int WIN_MAV;
double alpha;
double beta;
double p_star;
double* p_lik;
double* mu_init;
double* sig2_init;
double* sig2_reg;
double* sig2_update;
private:
bool bCollect;
bool bCompute;
bool bRegister;
private:
bool bGPU_product;
bool bGPU_diffusion;
bool bFuncRegistration;
bool bFuncAdaptation;
public:
double* pdist_prior;
double* pdist_post;
double* pdist_lik;
double* dp;
double* ddp;
double* p_shift;
double* dp_shift;
private:
int mpred;
int M;
int reglast;
int reghold;
double p_max;
double* xbin;
double* xnew;
int* idnew;
double* emgMAV;
double* emgStack;
private:
vector<double> dataStack;
private:
int tableSize;
int discretizeStep;
void registerPattern(double* mu, double* sig2);
void computeLikelihood(double* mu, double* sig2);
void computeProduct();
void computeDiffusion();
void normalizeLikelihood();
void normalizePrior();
void normalizePost();
double* normalTable;
void constructLookup();
private:
void setVal(double* vector, double val);
void setZero(double* vector);
void setOnes(double* vector);
private:
double* _pdist_prior;
double* _pdist_lik;
double* _pdist_post;
double* _p_shift;
double* _dp_shift;
double* _dp;
double* _ddp;
private:
fstream inputFile;
fstream outputFile;
};
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifndef TFcore_H_
#include <hip/hip_runtime.h>
#define TFcore_H_
#pragma once
#include <array>
#define _SILENCE_EXPERIMENTAL_FILESYSTEM_DEPRECATION_WARNING
#include <experimental/filesystem>
#include <iostream>
#include <fstream>
#include <istream>
#include <sstream>
#define _USE_MATH_DEFINES
#include <math.h>
#include <iomanip>
#include <vector>
#include <string>
#define EPSILON 1.00e-10 // minimum value for probability distribution
using namespace std;
namespace fs = std::experimental::filesystem;
class CTFcoreMFCDlg;
class TFcore {
public:
TFcore();
TFcore(string filename);
TFcore(fs::path filename);
//TFcore(CTFcoreMFCDlg& dlg);
~TFcore();
private:
//CTFcoreMFCDlg& dlg_;
public:
void loadData(string filename);
void loadData(fs::path filename);
void loadData(vector<double> data, int ch);
public:
int getNumSamples() { return numSamples; }
int getNumChannels() { return numChannels; }
int getPredict() { return mpred; }
int getNumPatterns() { return M; }
//int getNumRemaining() { return ((int)dataStack.size() / numChannels); }
int getNumRemaining() { return (numSamples - samples); }
double getProbMax() { return p_max; }
double getProbThresh() { return p_star; }
public:
void resetModel() { initModel(numChannels); }
void initModel(int n);
void setNumSamples(int numsamples) { numSamples = numsamples; }
void setNumChannels(int numchannels) { numChannels = numchannels; }
public:
bool isCollect() { return bCollect; }
bool isCompute() { return bCompute; }
bool isRegister() { return bRegister; }
bool isRemaining() { return !inputFile.eof(); }
bool isGPU_Product() { return bGPU_product; }
bool isGPU_Diffusion() { return bGPU_diffusion; }
void enableGPU_Product() { bGPU_product = true; }
void disableGPU_Product() { bGPU_product = false; }
void enableGPU_Diffusion() { bGPU_diffusion = true; }
void disableGPU_Diffusion() { bGPU_diffusion = false; }
void enableRegistration() { bFuncRegistration = true; }
void disableRegistration() { bFuncRegistration = false; }
void enableAdaptation() { bFuncAdaptation = true; }
void disableAdaptation() { bFuncAdaptation = false; }
public:
void getSample();
void proceedIteration();
void writeResult();
public:
void exportModel(fs::path filename);
void importModel(fs::path filename);
private:
int numChannels;
int numSamples;
int samples;
int M_MAX;
double xmax;
int XRES;
int WIN_MAV;
double alpha;
double beta;
double p_star;
double* p_lik;
double* mu_init;
double* sig2_init;
double* sig2_reg;
double* sig2_update;
private:
bool bCollect;
bool bCompute;
bool bRegister;
private:
bool bGPU_product;
bool bGPU_diffusion;
bool bFuncRegistration;
bool bFuncAdaptation;
public:
double* pdist_prior;
double* pdist_post;
double* pdist_lik;
double* dp;
double* ddp;
double* p_shift;
double* dp_shift;
private:
int mpred;
int M;
int reglast;
int reghold;
double p_max;
double* xbin;
double* xnew;
int* idnew;
double* emgMAV;
double* emgStack;
private:
vector<double> dataStack;
private:
int tableSize;
int discretizeStep;
void registerPattern(double* mu, double* sig2);
void computeLikelihood(double* mu, double* sig2);
void computeProduct();
void computeDiffusion();
void normalizeLikelihood();
void normalizePrior();
void normalizePost();
double* normalTable;
void constructLookup();
private:
void setVal(double* vector, double val);
void setZero(double* vector);
void setOnes(double* vector);
private:
double* _pdist_prior;
double* _pdist_lik;
double* _pdist_post;
double* _p_shift;
double* _dp_shift;
double* _dp;
double* _ddp;
private:
fstream inputFile;
fstream outputFile;
};
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef TFcore_H_
#include <hip/hip_runtime.h>
#define TFcore_H_
#pragma once
#include <array>
#define _SILENCE_EXPERIMENTAL_FILESYSTEM_DEPRECATION_WARNING
#include <experimental/filesystem>
#include <iostream>
#include <fstream>
#include <istream>
#include <sstream>
#define _USE_MATH_DEFINES
#include <math.h>
#include <iomanip>
#include <vector>
#include <string>
#define EPSILON 1.00e-10 // minimum value for probability distribution
using namespace std;
namespace fs = std::experimental::filesystem;
class CTFcoreMFCDlg;
class TFcore {
public:
TFcore();
TFcore(string filename);
TFcore(fs::path filename);
//TFcore(CTFcoreMFCDlg& dlg);
~TFcore();
private:
//CTFcoreMFCDlg& dlg_;
public:
void loadData(string filename);
void loadData(fs::path filename);
void loadData(vector<double> data, int ch);
public:
int getNumSamples() { return numSamples; }
int getNumChannels() { return numChannels; }
int getPredict() { return mpred; }
int getNumPatterns() { return M; }
//int getNumRemaining() { return ((int)dataStack.size() / numChannels); }
int getNumRemaining() { return (numSamples - samples); }
double getProbMax() { return p_max; }
double getProbThresh() { return p_star; }
public:
void resetModel() { initModel(numChannels); }
void initModel(int n);
void setNumSamples(int numsamples) { numSamples = numsamples; }
void setNumChannels(int numchannels) { numChannels = numchannels; }
public:
bool isCollect() { return bCollect; }
bool isCompute() { return bCompute; }
bool isRegister() { return bRegister; }
bool isRemaining() { return !inputFile.eof(); }
bool isGPU_Product() { return bGPU_product; }
bool isGPU_Diffusion() { return bGPU_diffusion; }
void enableGPU_Product() { bGPU_product = true; }
void disableGPU_Product() { bGPU_product = false; }
void enableGPU_Diffusion() { bGPU_diffusion = true; }
void disableGPU_Diffusion() { bGPU_diffusion = false; }
void enableRegistration() { bFuncRegistration = true; }
void disableRegistration() { bFuncRegistration = false; }
void enableAdaptation() { bFuncAdaptation = true; }
void disableAdaptation() { bFuncAdaptation = false; }
public:
void getSample();
void proceedIteration();
void writeResult();
public:
void exportModel(fs::path filename);
void importModel(fs::path filename);
private:
int numChannels;
int numSamples;
int samples;
int M_MAX;
double xmax;
int XRES;
int WIN_MAV;
double alpha;
double beta;
double p_star;
double* p_lik;
double* mu_init;
double* sig2_init;
double* sig2_reg;
double* sig2_update;
private:
bool bCollect;
bool bCompute;
bool bRegister;
private:
bool bGPU_product;
bool bGPU_diffusion;
bool bFuncRegistration;
bool bFuncAdaptation;
public:
double* pdist_prior;
double* pdist_post;
double* pdist_lik;
double* dp;
double* ddp;
double* p_shift;
double* dp_shift;
private:
int mpred;
int M;
int reglast;
int reghold;
double p_max;
double* xbin;
double* xnew;
int* idnew;
double* emgMAV;
double* emgStack;
private:
vector<double> dataStack;
private:
int tableSize;
int discretizeStep;
void registerPattern(double* mu, double* sig2);
void computeLikelihood(double* mu, double* sig2);
void computeProduct();
void computeDiffusion();
void normalizeLikelihood();
void normalizePrior();
void normalizePost();
double* normalTable;
void constructLookup();
private:
void setVal(double* vector, double val);
void setZero(double* vector);
void setOnes(double* vector);
private:
double* _pdist_prior;
double* _pdist_lik;
double* _pdist_post;
double* _p_shift;
double* _dp_shift;
double* _dp;
double* _ddp;
private:
fstream inputFile;
fstream outputFile;
};
#endif | .text
.file "TFcore.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15_computeProductPdS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R8, R9, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x000fc800078e0209 */
/*0070*/ IMAD.WIDE R4, R8.reuse, R9.reuse, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x0c0fe400078e0209 */
/*0080*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*0090*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0209 */
/*00b0*/ DMUL R6, R2, R4 ; /* 0x0000000402067228 */
/* 0x004e0e0000000000 */
/*00c0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z19_computeWeightedSumPdS_d
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R6, R2, R5, c[0x0][0x168] ; /* 0x00005a0002067625 */
/* 0x000fc800078e0205 */
/*0070*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe400078e0205 */
/*0080*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1b00 */
/*0090*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1b00 */
/*00a0*/ DFMA R4, R6, c[0x0][0x170], R4 ; /* 0x00005c0006047a2b */
/* 0x004e0e0000000004 */
/*00b0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe2000c101b04 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z16_computeGradientPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R11, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0b7435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R0, R11, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e020b */
/*0070*/ IMAD.WIDE R4, R0, R11, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe400078e020b */
/*0080*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*0090*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ I2F.F64 R8, c[0x0][0x178] ; /* 0x00005e0000087b12 */
/* 0x000e220000201c00 */
/*00b0*/ DADD R6, R2, -R4 ; /* 0x0000000002067229 */
/* 0x004e0c0000000804 */
/*00c0*/ DMUL R6, R6, R8 ; /* 0x0000000806067228 */
/* 0x0010640000000000 */
/*00d0*/ IMAD.WIDE R8, R0, R11, c[0x0][0x170] ; /* 0x00005c0000087625 */
/* 0x001fca00078e020b */
/*00e0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x002fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kEltwiseLogregCost(float* predmap, float* indmap, float*indlogpred, float* correctprobs, int numCases, int numTasks, int per_thread_case) {
const int task_id = blockIdx.x;
const int start_tx = threadIdx.x * per_thread_case;
const int end_tx = min(start_tx + per_thread_case, numCases);
const float EPSILON=1e-20; // Minimum value allowed, avoid log( 0 )
if (task_id >= numTasks) {
return;
}
for (int c_id = start_tx; c_id < end_tx; ++c_id) {
int pos = task_id * numCases + c_id;
float t = __fdividef(1.0f, 1.0f + __expf(-predmap[ pos ]));
if (indmap[pos] == 1) {
t = fmaxf(t, EPSILON);
indlogpred[pos] = __logf(t);
correctprobs[pos] = t;
} else {
t = 1-t;
t = fmaxf(t, EPSILON);
indlogpred[pos] = __logf(t);
correctprobs[pos] = t;
}
}
} | code for sm_80
Function : _Z18kEltwiseLogregCostPfS_S_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0020*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e620000002500 */
/*0030*/ IMAD R3, R3, c[0x0][0x188], RZ ; /* 0x0000620003037a24 */
/* 0x001fca00078e02ff */
/*0040*/ IADD3 R2, R3, c[0x0][0x188], RZ ; /* 0x0000620003027a10 */
/* 0x000fc80007ffe0ff */
/*0050*/ IMNMX R2, R2, c[0x0][0x180], PT ; /* 0x0000600002027a17 */
/* 0x000fc80003800200 */
/*0060*/ ISETP.GE.AND P0, PT, R3, R2, PT ; /* 0x000000020300720c */
/* 0x000fc80003f06270 */
/*0070*/ ISETP.GE.OR P0, PT, R8, c[0x0][0x184], P0 ; /* 0x0000610008007a0c */
/* 0x002fda0000706670 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ IMAD.IADD R0, R2, 0x1, -R3.reuse ; /* 0x0000000102007824 */
/* 0x100fe200078e0a03 */
/*00a0*/ LOP3.LUT R4, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff047212 */
/* 0x000fe200078e33ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ BSSY B0, 0x430 ; /* 0x0000036000007945 */
/* 0x000fe40003800000 */
/*00d0*/ LOP3.LUT P1, R15, R0, 0x3, RZ, 0xc0, !PT ; /* 0x00000003000f7812 */
/* 0x000fe4000782c0ff */
/*00e0*/ IADD3 R4, -R4, -0x2, -R3 ; /* 0xfffffffe04047810 */
/* 0x000fe40007ffe903 */
/*00f0*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fe40000000f00 */
/*0100*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fce0003f06070 */
/*0110*/ @!P1 BRA 0x420 ; /* 0x0000030000009947 */
/* 0x000fea0003800000 */
/*0120*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe400078e00ff */
/*0130*/ IMAD R4, R8, c[0x0][0x180], R3 ; /* 0x0000600008047a24 */
/* 0x000fc800078e0203 */
/*0140*/ IMAD.WIDE R10, R4, R5, c[0x0][0x178] ; /* 0x00005e00040a7625 */
/* 0x000fc800078e0205 */
/*0150*/ IMAD.WIDE R12, R4, R5, c[0x0][0x170] ; /* 0x00005c00040c7625 */
/* 0x000fc800078e0205 */
/*0160*/ IMAD.WIDE R6, R4, R5, c[0x0][0x168] ; /* 0x00005a0004067625 */
/* 0x000fc800078e0205 */
/*0170*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e0205 */
/*0180*/ MOV R9, R6 ; /* 0x0000000600097202 */
/* 0x000fc60000000f00 */
/*0190*/ IMAD.MOV.U32 R14, RZ, RZ, R7 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0007 */
/*01a0*/ MOV R16, R4 ; /* 0x0000000400107202 */
/* 0x000fe20000000f00 */
/*01b0*/ IMAD.MOV.U32 R17, RZ, RZ, R5 ; /* 0x000000ffff117224 */
/* 0x000fca00078e0005 */
/*01c0*/ LDG.E R6, [R16.64] ; /* 0x0000000410067981 */
/* 0x0010a2000c1e1900 */
/*01d0*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x000fe20000000f00 */
/*01e0*/ IMAD.MOV.U32 R5, RZ, RZ, R14 ; /* 0x000000ffff057224 */
/* 0x000fca00078e000e */
/*01f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee2000c1e1900 */
/*0200*/ IADD3 R15, R15, -0x1, RZ ; /* 0xffffffff0f0f7810 */
/* 0x000fe40007ffe0ff */
/*0210*/ IADD3 R16, P5, R16, 0x4, RZ ; /* 0x0000000410107810 */
/* 0x001fe40007fbe0ff */
/*0220*/ IADD3 R9, P4, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe40007f9e0ff */
/*0230*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fe20007ffe0ff */
/*0240*/ IMAD.X R17, RZ, RZ, R17, P5 ; /* 0x000000ffff117224 */
/* 0x000fe200028e0611 */
/*0250*/ IADD3.X R14, RZ, R14, RZ, P4, !PT ; /* 0x0000000eff0e7210 */
/* 0x000fe200027fe4ff */
/*0260*/ FMUL R6, R6, -1.4426950216293334961 ; /* 0xbfb8aa3b06067820 */
/* 0x004fca0000400000 */
/*0270*/ FSETP.GEU.AND P1, PT, R6, -126, PT ; /* 0xc2fc00000600780b */
/* 0x000fda0003f2e000 */
/*0280*/ @!P1 FMUL R6, R6, 0.5 ; /* 0x3f00000006069820 */
/* 0x000fc80000400000 */
/*0290*/ MUFU.EX2 R7, R6 ; /* 0x0000000600077308 */
/* 0x0000640000000800 */
/*02a0*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x001fe40000000f00 */
/*02b0*/ IADD3 R10, P2, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fe20007f5e0ff */
/*02c0*/ @!P1 FMUL R7, R7, R7 ; /* 0x0000000707079220 */
/* 0x002fe20000400000 */
/*02d0*/ FSETP.NEU.AND P1, PT, R4, 1, PT ; /* 0x3f8000000400780b */
/* 0x008fc60003f2d000 */
/*02e0*/ FADD R7, R7, 1 ; /* 0x3f80000007077421 */
/* 0x000fc80000000000 */
/*02f0*/ MUFU.RCP R18, R7 ; /* 0x0000000700127308 */
/* 0x0000640000001000 */
/*0300*/ IMAD.MOV.U32 R7, RZ, RZ, R11 ; /* 0x000000ffff077224 */
/* 0x001fe200078e000b */
/*0310*/ IADD3.X R11, RZ, R11, RZ, P2, !PT ; /* 0x0000000bff0b7210 */
/* 0x000fc600017fe4ff */
/*0320*/ @P1 FADD R18, -R18, 1 ; /* 0x3f80000012121421 */
/* 0x002fca0000000100 */
/*0330*/ FMNMX R19, R18, 9.999999682655225389e-21, !PT ; /* 0x1e3ce50812137809 */
/* 0x000fc80007800000 */
/*0340*/ FSETP.GEU.AND P1, PT, |R19|.reuse, 1.175494350822287508e-38, PT ; /* 0x008000001300780b */
/* 0x040fe20003f2e200 */
/*0350*/ FMUL R4, R19, 16777216 ; /* 0x4b80000013047820 */
/* 0x000fca0000400000 */
/*0360*/ FSEL R4, R4, R19, !P1 ; /* 0x0000001304047208 */
/* 0x000fc80004800000 */
/*0370*/ MUFU.LG2 R5, R4 ; /* 0x0000000400057308 */
/* 0x0000640000000c00 */
/*0380*/ MOV R4, R12 ; /* 0x0000000c00047202 */
/* 0x001fe40000000f00 */
/*0390*/ IADD3 R12, P3, R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x000fe20007f7e0ff */
/*03a0*/ @!P1 FADD R5, R5, -24 ; /* 0xc1c0000005059421 */
/* 0x002fe20000000000 */
/*03b0*/ ISETP.NE.AND P1, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fc60003f25270 */
/*03c0*/ FMUL R21, R5, 0.69314718246459960938 ; /* 0x3f31721805157820 */
/* 0x000fe40000400000 */
/*03d0*/ IMAD.MOV.U32 R5, RZ, RZ, R13.reuse ; /* 0x000000ffff057224 */
/* 0x100fe400078e000d */
/*03e0*/ IMAD.X R13, RZ, RZ, R13, P3 ; /* 0x000000ffff0d7224 */
/* 0x000fc600018e060d */
/*03f0*/ STG.E [R4.64], R21 ; /* 0x0000001504007986 */
/* 0x0001e8000c101904 */
/*0400*/ STG.E [R6.64], R19 ; /* 0x0000001306007986 */
/* 0x0001e2000c101904 */
/*0410*/ @P1 BRA 0x1c0 ; /* 0xfffffda000001947 */
/* 0x000fea000383ffff */
/*0420*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0430*/ MOV R19, c[0x0][0x17c] ; /* 0x00005f0000137a02 */
/* 0x001fe20000000f00 */
/*0440*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0c7624 */
/* 0x000fe200078e00ff */
/*0450*/ MOV R13, c[0x0][0x174] ; /* 0x00005d00000d7a02 */
/* 0x000fe20000000f00 */
/*0460*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff0e7624 */
/* 0x000fe200078e00ff */
/*0470*/ MOV R15, c[0x0][0x16c] ; /* 0x00005b00000f7a02 */
/* 0x000fe40000000f00 */
/*0480*/ MOV R16, c[0x0][0x160] ; /* 0x0000580000107a02 */
/* 0x000fe20000000f00 */
/*0490*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fec0003800000 */
/*04a0*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff117624 */
/* 0x000fe400078e00ff */
/*04b0*/ IMAD R21, R8, c[0x0][0x180], R3 ; /* 0x0000600008157a24 */
/* 0x000fc800078e0203 */
/*04c0*/ IMAD.WIDE R4, R21, 0x4, R16 ; /* 0x0000000415047825 */
/* 0x001fca00078e0210 */
/*04d0*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea2000c1e1900 */
/*04e0*/ IMAD.WIDE R6, R21, 0x4, R14 ; /* 0x0000000415067825 */
/* 0x000fca00078e020e */
/*04f0*/ LDG.E R11, [R6.64] ; /* 0x00000004060b7981 */
/* 0x000ee2000c1e1900 */
/*0500*/ FMUL R8, R8, -1.4426950216293334961 ; /* 0xbfb8aa3b08087820 */
/* 0x004fca0000400000 */
/*0510*/ FSETP.GEU.AND P0, PT, R8, -126, PT ; /* 0xc2fc00000800780b */
/* 0x000fda0003f0e000 */
/*0520*/ @!P0 FMUL R8, R8, 0.5 ; /* 0x3f00000008088820 */
/* 0x000fc80000400000 */
/*0530*/ MUFU.EX2 R9, R8 ; /* 0x0000000800097308 */
/* 0x0000640000000800 */
/*0540*/ IMAD.MOV.U32 R8, RZ, RZ, R0 ; /* 0x000000ffff087224 */
/* 0x001fe400078e0000 */
/*0550*/ @!P0 FMUL R9, R9, R9 ; /* 0x0000000909098220 */
/* 0x002fe20000400000 */
/*0560*/ FSETP.NEU.AND P0, PT, R11, 1, PT ; /* 0x3f8000000b00780b */
/* 0x008fe40003f0d000 */
/*0570*/ MOV R11, R13 ; /* 0x0000000d000b7202 */
/* 0x000fe20000000f00 */
/*0580*/ FADD R9, R9, 1 ; /* 0x3f80000009097421 */
/* 0x000fc80000000000 */
/*0590*/ MUFU.RCP R10, R9 ; /* 0x00000009000a7308 */
/* 0x0000640000001000 */
/*05a0*/ MOV R9, R19 ; /* 0x0000001300097202 */
/* 0x001fca0000000f00 */
/*05b0*/ IMAD.WIDE R8, R21, 0x4, R8 ; /* 0x0000000415087825 */
/* 0x000fc800078e0208 */
/*05c0*/ @P0 FADD R10, -R10, 1 ; /* 0x3f8000000a0a0421 */
/* 0x002fca0000000100 */
/*05d0*/ FMNMX R23, R10, 9.999999682655225389e-21, !PT ; /* 0x1e3ce5080a177809 */
/* 0x000fc80007800000 */
/*05e0*/ FSETP.GEU.AND P0, PT, |R23|.reuse, 1.175494350822287508e-38, PT ; /* 0x008000001700780b */
/* 0x040fe20003f0e200 */
/*05f0*/ FMUL R10, R23, 16777216 ; /* 0x4b800000170a7820 */
/* 0x000fca0000400000 */
/*0600*/ FSEL R18, R10, R23, !P0 ; /* 0x000000170a127208 */
/* 0x000fe40004000000 */
/*0610*/ MOV R10, R12 ; /* 0x0000000c000a7202 */
/* 0x000fe40000000f00 */
/*0620*/ MUFU.LG2 R20, R18 ; /* 0x0000001200147308 */
/* 0x000e260000000c00 */
/*0630*/ IMAD.WIDE R10, R21, 0x4, R10 ; /* 0x00000004150a7825 */
/* 0x000fc800078e020a */
/*0640*/ @!P0 FADD R20, R20, -24 ; /* 0xc1c0000014148421 */
/* 0x001fc80000000000 */
/*0650*/ FMUL R25, R20, 0.69314718246459960938 ; /* 0x3f31721814197820 */
/* 0x000fca0000400000 */
/*0660*/ STG.E [R10.64], R25 ; /* 0x000000190a007986 */
/* 0x000fe8000c101904 */
/*0670*/ STG.E [R8.64], R23 ; /* 0x0000001708007986 */
/* 0x0001e8000c101904 */
/*0680*/ LDG.E R20, [R4.64+0x4] ; /* 0x0000040404147981 */
/* 0x000ea8000c1e1900 */
/*0690*/ LDG.E R24, [R6.64+0x4] ; /* 0x0000040406187981 */
/* 0x000ee2000c1e1900 */
/*06a0*/ FMUL R20, R20, -1.4426950216293334961 ; /* 0xbfb8aa3b14147820 */
/* 0x004fca0000400000 */
/*06b0*/ FSETP.GEU.AND P0, PT, R20, -126, PT ; /* 0xc2fc00001400780b */
/* 0x000fda0003f0e000 */
/*06c0*/ @!P0 FMUL R20, R20, 0.5 ; /* 0x3f00000014148820 */
/* 0x000fc80000400000 */
/*06d0*/ MUFU.EX2 R18, R20 ; /* 0x0000001400127308 */
/* 0x000e640000000800 */
/*06e0*/ @!P0 FMUL R18, R18, R18 ; /* 0x0000001212128220 */
/* 0x002fe20000400000 */
/*06f0*/ FSETP.NEU.AND P0, PT, R24, 1, PT ; /* 0x3f8000001800780b */
/* 0x008fc60003f0d000 */
/*0700*/ FADD R18, R18, 1 ; /* 0x3f80000012127421 */
/* 0x000fc80000000000 */
/*0710*/ MUFU.RCP R22, R18 ; /* 0x0000001200167308 */
/* 0x000e6c0000001000 */
/*0720*/ @P0 FADD R22, -R22, 1 ; /* 0x3f80000016160421 */
/* 0x002fca0000000100 */
/*0730*/ FMNMX R23, R22, 9.999999682655225389e-21, !PT ; /* 0x1e3ce50816177809 */
/* 0x001fc80007800000 */
/*0740*/ FSETP.GEU.AND P0, PT, |R23|.reuse, 1.175494350822287508e-38, PT ; /* 0x008000001700780b */
/* 0x040fe20003f0e200 */
/*0750*/ FMUL R22, R23, 16777216 ; /* 0x4b80000017167820 */
/* 0x000fca0000400000 */
/*0760*/ FSEL R22, R22, R23, !P0 ; /* 0x0000001716167208 */
/* 0x000fc80004000000 */
/*0770*/ MUFU.LG2 R24, R22 ; /* 0x0000001600187308 */
/* 0x000e260000000c00 */
/*0780*/ @!P0 FADD R24, R24, -24 ; /* 0xc1c0000018188421 */
/* 0x001fc80000000000 */
/*0790*/ FMUL R25, R24, 0.69314718246459960938 ; /* 0x3f31721818197820 */
/* 0x000fca0000400000 */
/*07a0*/ STG.E [R10.64+0x4], R25 ; /* 0x000004190a007986 */
/* 0x000fe8000c101904 */
/*07b0*/ STG.E [R8.64+0x4], R23 ; /* 0x0000041708007986 */
/* 0x0001e8000c101904 */
/*07c0*/ LDG.E R18, [R4.64+0x8] ; /* 0x0000080404127981 */
/* 0x000ea8000c1e1900 */
/*07d0*/ LDG.E R24, [R6.64+0x8] ; /* 0x0000080406187981 */
/* 0x000ee2000c1e1900 */
/*07e0*/ FMUL R18, R18, -1.4426950216293334961 ; /* 0xbfb8aa3b12127820 */
/* 0x004fca0000400000 */
/*07f0*/ FSETP.GEU.AND P0, PT, R18, -126, PT ; /* 0xc2fc00001200780b */
/* 0x000fda0003f0e000 */
/*0800*/ @!P0 FMUL R18, R18, 0.5 ; /* 0x3f00000012128820 */
/* 0x000fc80000400000 */
/*0810*/ MUFU.EX2 R20, R18 ; /* 0x0000001200147308 */
/* 0x000e640000000800 */
/*0820*/ @!P0 FMUL R20, R20, R20 ; /* 0x0000001414148220 */
/* 0x002fe20000400000 */
/*0830*/ FSETP.NEU.AND P0, PT, R24, 1, PT ; /* 0x3f8000001800780b */
/* 0x008fc60003f0d000 */
/*0840*/ FADD R20, R20, 1 ; /* 0x3f80000014147421 */
/* 0x000fc80000000000 */
/*0850*/ MUFU.RCP R22, R20 ; /* 0x0000001400167308 */
/* 0x000e6c0000001000 */
/*0860*/ @P0 FADD R22, -R22, 1 ; /* 0x3f80000016160421 */
/* 0x002fca0000000100 */
/*0870*/ FMNMX R23, R22, 9.999999682655225389e-21, !PT ; /* 0x1e3ce50816177809 */
/* 0x001fc80007800000 */
/*0880*/ FSETP.GEU.AND P0, PT, |R23|.reuse, 1.175494350822287508e-38, PT ; /* 0x008000001700780b */
/* 0x040fe20003f0e200 */
/*0890*/ FMUL R22, R23, 16777216 ; /* 0x4b80000017167820 */
/* 0x000fca0000400000 */
/*08a0*/ FSEL R22, R22, R23, !P0 ; /* 0x0000001716167208 */
/* 0x000fc80004000000 */
/*08b0*/ MUFU.LG2 R24, R22 ; /* 0x0000001600187308 */
/* 0x000e260000000c00 */
/*08c0*/ @!P0 FADD R24, R24, -24 ; /* 0xc1c0000018188421 */
/* 0x001fc80000000000 */
/*08d0*/ FMUL R25, R24, 0.69314718246459960938 ; /* 0x3f31721818197820 */
/* 0x000fca0000400000 */
/*08e0*/ STG.E [R10.64+0x8], R25 ; /* 0x000008190a007986 */
/* 0x0001e8000c101904 */
/*08f0*/ STG.E [R8.64+0x8], R23 ; /* 0x0000081708007986 */
/* 0x0001e8000c101904 */
/*0900*/ LDG.E R4, [R4.64+0xc] ; /* 0x00000c0404047981 */
/* 0x000ea8000c1e1900 */
/*0910*/ LDG.E R6, [R6.64+0xc] ; /* 0x00000c0406067981 */
/* 0x000ee2000c1e1900 */
/*0920*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc40007ffe0ff */
/*0930*/ IADD3 R12, P2, R12, 0x10, RZ ; /* 0x000000100c0c7810 */
/* 0x000fe40007f5e0ff */
/*0940*/ IADD3 R0, P1, R0, 0x10, RZ ; /* 0x0000001000007810 */
/* 0x000fe40007f3e0ff */
/*0950*/ IADD3 R14, P3, R14, 0x10, RZ ; /* 0x000000100e0e7810 */
/* 0x000fe20007f7e0ff */
/*0960*/ IMAD.X R13, RZ, RZ, R13, P2 ; /* 0x000000ffff0d7224 */
/* 0x000fe200010e060d */
/*0970*/ IADD3 R16, P4, R16, 0x10, RZ ; /* 0x0000001010107810 */
/* 0x000fe40007f9e0ff */
/*0980*/ IADD3.X R19, RZ, R19, RZ, P1, !PT ; /* 0x00000013ff137210 */
/* 0x000fe40000ffe4ff */
/*0990*/ IADD3.X R15, RZ, R15, RZ, P3, !PT ; /* 0x0000000fff0f7210 */
/* 0x000fc40001ffe4ff */
/*09a0*/ IADD3.X R17, RZ, R17, RZ, P4, !PT ; /* 0x00000011ff117210 */
/* 0x000fe200027fe4ff */
/*09b0*/ FMUL R18, R4, -1.4426950216293334961 ; /* 0xbfb8aa3b04127820 */
/* 0x004fca0000400000 */
/*09c0*/ FSETP.GEU.AND P0, PT, R18, -126, PT ; /* 0xc2fc00001200780b */
/* 0x000fda0003f0e000 */
/*09d0*/ @!P0 FMUL R18, R18, 0.5 ; /* 0x3f00000012128820 */
/* 0x000fc80000400000 */
/*09e0*/ MUFU.EX2 R20, R18 ; /* 0x0000001200147308 */
/* 0x000e640000000800 */
/*09f0*/ @!P0 FMUL R20, R20, R20 ; /* 0x0000001414148220 */
/* 0x002fe20000400000 */
/*0a00*/ FSETP.NEU.AND P0, PT, R6, 1, PT ; /* 0x3f8000000600780b */
/* 0x008fc60003f0d000 */
/*0a10*/ FADD R20, R20, 1 ; /* 0x3f80000014147421 */
/* 0x000fc80000000000 */
/*0a20*/ MUFU.RCP R22, R20 ; /* 0x0000001400167308 */
/* 0x000e6c0000001000 */
/*0a30*/ @P0 FADD R22, -R22, 1 ; /* 0x3f80000016160421 */
/* 0x002fca0000000100 */
/*0a40*/ FMNMX R5, R22, 9.999999682655225389e-21, !PT ; /* 0x1e3ce50816057809 */
/* 0x000fc80007800000 */
/*0a50*/ FSETP.GEU.AND P0, PT, |R5|.reuse, 1.175494350822287508e-38, PT ; /* 0x008000000500780b */
/* 0x040fe20003f0e200 */
/*0a60*/ FMUL R4, R5, 16777216 ; /* 0x4b80000005047820 */
/* 0x000fca0000400000 */
/*0a70*/ FSEL R4, R4, R5, !P0 ; /* 0x0000000504047208 */
/* 0x000fc80004000000 */
/*0a80*/ MUFU.LG2 R6, R4 ; /* 0x0000000400067308 */
/* 0x000e660000000c00 */
/*0a90*/ @!P0 FADD R6, R6, -24 ; /* 0xc1c0000006068421 */
/* 0x002fe20000000000 */
/*0aa0*/ ISETP.GE.AND P0, PT, R3, R2, PT ; /* 0x000000020300720c */
/* 0x000fc60003f06270 */
/*0ab0*/ FMUL R7, R6, 0.69314718246459960938 ; /* 0x3f31721806077820 */
/* 0x000fca0000400000 */
/*0ac0*/ STG.E [R10.64+0xc], R7 ; /* 0x00000c070a007986 */
/* 0x0001e8000c101904 */
/*0ad0*/ STG.E [R8.64+0xc], R5 ; /* 0x00000c0508007986 */
/* 0x0001e2000c101904 */
/*0ae0*/ @!P0 BRA 0x4c0 ; /* 0xfffff9d000008947 */
/* 0x000fea000383ffff */
/*0af0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b00*/ BRA 0xb00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kEltwiseLogregCost(float* predmap, float* indmap, float*indlogpred, float* correctprobs, int numCases, int numTasks, int per_thread_case) {
const int task_id = blockIdx.x;
const int start_tx = threadIdx.x * per_thread_case;
const int end_tx = min(start_tx + per_thread_case, numCases);
const float EPSILON=1e-20; // Minimum value allowed, avoid log( 0 )
if (task_id >= numTasks) {
return;
}
for (int c_id = start_tx; c_id < end_tx; ++c_id) {
int pos = task_id * numCases + c_id;
float t = __fdividef(1.0f, 1.0f + __expf(-predmap[ pos ]));
if (indmap[pos] == 1) {
t = fmaxf(t, EPSILON);
indlogpred[pos] = __logf(t);
correctprobs[pos] = t;
} else {
t = 1-t;
t = fmaxf(t, EPSILON);
indlogpred[pos] = __logf(t);
correctprobs[pos] = t;
}
}
} | .file "tmpxft_00029cad_00000000-6_kEltwiseLogregCost.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z18kEltwiseLogregCostPfS_S_S_iiiPfS_S_S_iii
.type _Z47__device_stub__Z18kEltwiseLogregCostPfS_S_S_iiiPfS_S_S_iii, @function
_Z47__device_stub__Z18kEltwiseLogregCostPfS_S_S_iiiPfS_S_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18kEltwiseLogregCostPfS_S_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z18kEltwiseLogregCostPfS_S_S_iiiPfS_S_S_iii, .-_Z47__device_stub__Z18kEltwiseLogregCostPfS_S_S_iiiPfS_S_S_iii
.globl _Z18kEltwiseLogregCostPfS_S_S_iii
.type _Z18kEltwiseLogregCostPfS_S_S_iii, @function
_Z18kEltwiseLogregCostPfS_S_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z47__device_stub__Z18kEltwiseLogregCostPfS_S_S_iiiPfS_S_S_iii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18kEltwiseLogregCostPfS_S_S_iii, .-_Z18kEltwiseLogregCostPfS_S_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18kEltwiseLogregCostPfS_S_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18kEltwiseLogregCostPfS_S_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kEltwiseLogregCost(float* predmap, float* indmap, float*indlogpred, float* correctprobs, int numCases, int numTasks, int per_thread_case) {
const int task_id = blockIdx.x;
const int start_tx = threadIdx.x * per_thread_case;
const int end_tx = min(start_tx + per_thread_case, numCases);
const float EPSILON=1e-20; // Minimum value allowed, avoid log( 0 )
if (task_id >= numTasks) {
return;
}
for (int c_id = start_tx; c_id < end_tx; ++c_id) {
int pos = task_id * numCases + c_id;
float t = __fdividef(1.0f, 1.0f + __expf(-predmap[ pos ]));
if (indmap[pos] == 1) {
t = fmaxf(t, EPSILON);
indlogpred[pos] = __logf(t);
correctprobs[pos] = t;
} else {
t = 1-t;
t = fmaxf(t, EPSILON);
indlogpred[pos] = __logf(t);
correctprobs[pos] = t;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kEltwiseLogregCost(float* predmap, float* indmap, float*indlogpred, float* correctprobs, int numCases, int numTasks, int per_thread_case) {
const int task_id = blockIdx.x;
const int start_tx = threadIdx.x * per_thread_case;
const int end_tx = min(start_tx + per_thread_case, numCases);
const float EPSILON=1e-20; // Minimum value allowed, avoid log( 0 )
if (task_id >= numTasks) {
return;
}
for (int c_id = start_tx; c_id < end_tx; ++c_id) {
int pos = task_id * numCases + c_id;
float t = __fdividef(1.0f, 1.0f + __expf(-predmap[ pos ]));
if (indmap[pos] == 1) {
t = fmaxf(t, EPSILON);
indlogpred[pos] = __logf(t);
correctprobs[pos] = t;
} else {
t = 1-t;
t = fmaxf(t, EPSILON);
indlogpred[pos] = __logf(t);
correctprobs[pos] = t;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kEltwiseLogregCost(float* predmap, float* indmap, float*indlogpred, float* correctprobs, int numCases, int numTasks, int per_thread_case) {
const int task_id = blockIdx.x;
const int start_tx = threadIdx.x * per_thread_case;
const int end_tx = min(start_tx + per_thread_case, numCases);
const float EPSILON=1e-20; // Minimum value allowed, avoid log( 0 )
if (task_id >= numTasks) {
return;
}
for (int c_id = start_tx; c_id < end_tx; ++c_id) {
int pos = task_id * numCases + c_id;
float t = __fdividef(1.0f, 1.0f + __expf(-predmap[ pos ]));
if (indmap[pos] == 1) {
t = fmaxf(t, EPSILON);
indlogpred[pos] = __logf(t);
correctprobs[pos] = t;
} else {
t = 1-t;
t = fmaxf(t, EPSILON);
indlogpred[pos] = __logf(t);
correctprobs[pos] = t;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18kEltwiseLogregCostPfS_S_S_iii
.globl _Z18kEltwiseLogregCostPfS_S_S_iii
.p2align 8
.type _Z18kEltwiseLogregCostPfS_S_S_iii,@function
_Z18kEltwiseLogregCostPfS_S_S_iii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x28
s_load_b64 s[2:3], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v0, v0, s4
s_cmp_lt_i32 s15, s3
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, s4, v0
v_min_i32_e32 v9, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_lt_i32_e32 vcc_lo, v0, v9
s_and_b32 s3, s3, vcc_lo
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB0_3
s_load_b256 s[4:11], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[7:8], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s8, v7
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v8, vcc_lo
v_add_co_u32 v3, vcc_lo, s10, v7
v_add_co_ci_u32_e32 v4, vcc_lo, s11, v8, vcc_lo
v_add_co_u32 v5, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v8, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
.LBB0_2:
global_load_b32 v10, v[5:6], off
global_load_b32 v11, v[7:8], off
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, v7, 4
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
s_waitcnt vmcnt(1)
v_mul_f32_e32 v10, 0xbfb8aa3b, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v10, v10
s_waitcnt_depctr 0xfff
v_add_f32_e32 v10, 1.0, v10
v_div_scale_f32 v12, null, v10, v10, 1.0
v_div_scale_f32 v13, vcc_lo, 1.0, v10, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v14, v12
s_waitcnt_depctr 0xfff
v_fma_f32 v15, -v12, v14, 1.0
v_fmac_f32_e32 v14, v15, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v15, v13, v14 :: v_dual_add_nc_u32 v0, 1, v0
v_cmp_ge_i32_e64 s0, v0, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v16, -v12, v15, v13
s_or_b32 s1, s0, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v15, v16, v14
v_fma_f32 v12, -v12, v15, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_fmas_f32 v12, v12, v14, v15
s_waitcnt vmcnt(0)
v_cmp_eq_f32_e32 vcc_lo, 1.0, v11
v_div_fixup_f32 v10, v12, v10, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v12, 1.0, v10
v_cndmask_b32_e32 v10, v12, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_f32_e32 v10, 0x1e3ce508, v10
v_cmp_gt_f32_e32 vcc_lo, 0x800000, v10
v_cndmask_b32_e64 v11, 1.0, 0x4f800000, vcc_lo
v_cndmask_b32_e64 v12, 0, 0x41b17218, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v11, v10, v11
v_log_f32_e32 v11, v11
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v13, 0x3f317217, v11
v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v11|
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v13, v11, 0x3f317217, -v13
v_fmac_f32_e32 v13, 0x3377d1cf, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v13, 0x3f317217, v11
v_cndmask_b32_e32 v11, v11, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_sub_f32_e32 v11, v11, v12
global_store_b32 v[1:2], v11, off
global_store_b32 v[3:4], v10, off
v_add_co_u32 v1, vcc_lo, v1, 4
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18kEltwiseLogregCostPfS_S_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 44
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18kEltwiseLogregCostPfS_S_S_iii, .Lfunc_end0-_Z18kEltwiseLogregCostPfS_S_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 44
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18kEltwiseLogregCostPfS_S_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18kEltwiseLogregCostPfS_S_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kEltwiseLogregCost(float* predmap, float* indmap, float*indlogpred, float* correctprobs, int numCases, int numTasks, int per_thread_case) {
const int task_id = blockIdx.x;
const int start_tx = threadIdx.x * per_thread_case;
const int end_tx = min(start_tx + per_thread_case, numCases);
const float EPSILON=1e-20; // Minimum value allowed, avoid log( 0 )
if (task_id >= numTasks) {
return;
}
for (int c_id = start_tx; c_id < end_tx; ++c_id) {
int pos = task_id * numCases + c_id;
float t = __fdividef(1.0f, 1.0f + __expf(-predmap[ pos ]));
if (indmap[pos] == 1) {
t = fmaxf(t, EPSILON);
indlogpred[pos] = __logf(t);
correctprobs[pos] = t;
} else {
t = 1-t;
t = fmaxf(t, EPSILON);
indlogpred[pos] = __logf(t);
correctprobs[pos] = t;
}
}
} | .text
.file "kEltwiseLogregCost.hip"
.globl _Z33__device_stub__kEltwiseLogregCostPfS_S_S_iii # -- Begin function _Z33__device_stub__kEltwiseLogregCostPfS_S_S_iii
.p2align 4, 0x90
.type _Z33__device_stub__kEltwiseLogregCostPfS_S_S_iii,@function
_Z33__device_stub__kEltwiseLogregCostPfS_S_S_iii: # @_Z33__device_stub__kEltwiseLogregCostPfS_S_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18kEltwiseLogregCostPfS_S_S_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z33__device_stub__kEltwiseLogregCostPfS_S_S_iii, .Lfunc_end0-_Z33__device_stub__kEltwiseLogregCostPfS_S_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18kEltwiseLogregCostPfS_S_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18kEltwiseLogregCostPfS_S_S_iii,@object # @_Z18kEltwiseLogregCostPfS_S_S_iii
.section .rodata,"a",@progbits
.globl _Z18kEltwiseLogregCostPfS_S_S_iii
.p2align 3, 0x0
_Z18kEltwiseLogregCostPfS_S_S_iii:
.quad _Z33__device_stub__kEltwiseLogregCostPfS_S_S_iii
.size _Z18kEltwiseLogregCostPfS_S_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18kEltwiseLogregCostPfS_S_S_iii"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__kEltwiseLogregCostPfS_S_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18kEltwiseLogregCostPfS_S_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18kEltwiseLogregCostPfS_S_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0020*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e620000002500 */
/*0030*/ IMAD R3, R3, c[0x0][0x188], RZ ; /* 0x0000620003037a24 */
/* 0x001fca00078e02ff */
/*0040*/ IADD3 R2, R3, c[0x0][0x188], RZ ; /* 0x0000620003027a10 */
/* 0x000fc80007ffe0ff */
/*0050*/ IMNMX R2, R2, c[0x0][0x180], PT ; /* 0x0000600002027a17 */
/* 0x000fc80003800200 */
/*0060*/ ISETP.GE.AND P0, PT, R3, R2, PT ; /* 0x000000020300720c */
/* 0x000fc80003f06270 */
/*0070*/ ISETP.GE.OR P0, PT, R8, c[0x0][0x184], P0 ; /* 0x0000610008007a0c */
/* 0x002fda0000706670 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ IMAD.IADD R0, R2, 0x1, -R3.reuse ; /* 0x0000000102007824 */
/* 0x100fe200078e0a03 */
/*00a0*/ LOP3.LUT R4, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff047212 */
/* 0x000fe200078e33ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ BSSY B0, 0x430 ; /* 0x0000036000007945 */
/* 0x000fe40003800000 */
/*00d0*/ LOP3.LUT P1, R15, R0, 0x3, RZ, 0xc0, !PT ; /* 0x00000003000f7812 */
/* 0x000fe4000782c0ff */
/*00e0*/ IADD3 R4, -R4, -0x2, -R3 ; /* 0xfffffffe04047810 */
/* 0x000fe40007ffe903 */
/*00f0*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fe40000000f00 */
/*0100*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fce0003f06070 */
/*0110*/ @!P1 BRA 0x420 ; /* 0x0000030000009947 */
/* 0x000fea0003800000 */
/*0120*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe400078e00ff */
/*0130*/ IMAD R4, R8, c[0x0][0x180], R3 ; /* 0x0000600008047a24 */
/* 0x000fc800078e0203 */
/*0140*/ IMAD.WIDE R10, R4, R5, c[0x0][0x178] ; /* 0x00005e00040a7625 */
/* 0x000fc800078e0205 */
/*0150*/ IMAD.WIDE R12, R4, R5, c[0x0][0x170] ; /* 0x00005c00040c7625 */
/* 0x000fc800078e0205 */
/*0160*/ IMAD.WIDE R6, R4, R5, c[0x0][0x168] ; /* 0x00005a0004067625 */
/* 0x000fc800078e0205 */
/*0170*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e0205 */
/*0180*/ MOV R9, R6 ; /* 0x0000000600097202 */
/* 0x000fc60000000f00 */
/*0190*/ IMAD.MOV.U32 R14, RZ, RZ, R7 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0007 */
/*01a0*/ MOV R16, R4 ; /* 0x0000000400107202 */
/* 0x000fe20000000f00 */
/*01b0*/ IMAD.MOV.U32 R17, RZ, RZ, R5 ; /* 0x000000ffff117224 */
/* 0x000fca00078e0005 */
/*01c0*/ LDG.E R6, [R16.64] ; /* 0x0000000410067981 */
/* 0x0010a2000c1e1900 */
/*01d0*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x000fe20000000f00 */
/*01e0*/ IMAD.MOV.U32 R5, RZ, RZ, R14 ; /* 0x000000ffff057224 */
/* 0x000fca00078e000e */
/*01f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee2000c1e1900 */
/*0200*/ IADD3 R15, R15, -0x1, RZ ; /* 0xffffffff0f0f7810 */
/* 0x000fe40007ffe0ff */
/*0210*/ IADD3 R16, P5, R16, 0x4, RZ ; /* 0x0000000410107810 */
/* 0x001fe40007fbe0ff */
/*0220*/ IADD3 R9, P4, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe40007f9e0ff */
/*0230*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fe20007ffe0ff */
/*0240*/ IMAD.X R17, RZ, RZ, R17, P5 ; /* 0x000000ffff117224 */
/* 0x000fe200028e0611 */
/*0250*/ IADD3.X R14, RZ, R14, RZ, P4, !PT ; /* 0x0000000eff0e7210 */
/* 0x000fe200027fe4ff */
/*0260*/ FMUL R6, R6, -1.4426950216293334961 ; /* 0xbfb8aa3b06067820 */
/* 0x004fca0000400000 */
/*0270*/ FSETP.GEU.AND P1, PT, R6, -126, PT ; /* 0xc2fc00000600780b */
/* 0x000fda0003f2e000 */
/*0280*/ @!P1 FMUL R6, R6, 0.5 ; /* 0x3f00000006069820 */
/* 0x000fc80000400000 */
/*0290*/ MUFU.EX2 R7, R6 ; /* 0x0000000600077308 */
/* 0x0000640000000800 */
/*02a0*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x001fe40000000f00 */
/*02b0*/ IADD3 R10, P2, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fe20007f5e0ff */
/*02c0*/ @!P1 FMUL R7, R7, R7 ; /* 0x0000000707079220 */
/* 0x002fe20000400000 */
/*02d0*/ FSETP.NEU.AND P1, PT, R4, 1, PT ; /* 0x3f8000000400780b */
/* 0x008fc60003f2d000 */
/*02e0*/ FADD R7, R7, 1 ; /* 0x3f80000007077421 */
/* 0x000fc80000000000 */
/*02f0*/ MUFU.RCP R18, R7 ; /* 0x0000000700127308 */
/* 0x0000640000001000 */
/*0300*/ IMAD.MOV.U32 R7, RZ, RZ, R11 ; /* 0x000000ffff077224 */
/* 0x001fe200078e000b */
/*0310*/ IADD3.X R11, RZ, R11, RZ, P2, !PT ; /* 0x0000000bff0b7210 */
/* 0x000fc600017fe4ff */
/*0320*/ @P1 FADD R18, -R18, 1 ; /* 0x3f80000012121421 */
/* 0x002fca0000000100 */
/*0330*/ FMNMX R19, R18, 9.999999682655225389e-21, !PT ; /* 0x1e3ce50812137809 */
/* 0x000fc80007800000 */
/*0340*/ FSETP.GEU.AND P1, PT, |R19|.reuse, 1.175494350822287508e-38, PT ; /* 0x008000001300780b */
/* 0x040fe20003f2e200 */
/*0350*/ FMUL R4, R19, 16777216 ; /* 0x4b80000013047820 */
/* 0x000fca0000400000 */
/*0360*/ FSEL R4, R4, R19, !P1 ; /* 0x0000001304047208 */
/* 0x000fc80004800000 */
/*0370*/ MUFU.LG2 R5, R4 ; /* 0x0000000400057308 */
/* 0x0000640000000c00 */
/*0380*/ MOV R4, R12 ; /* 0x0000000c00047202 */
/* 0x001fe40000000f00 */
/*0390*/ IADD3 R12, P3, R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x000fe20007f7e0ff */
/*03a0*/ @!P1 FADD R5, R5, -24 ; /* 0xc1c0000005059421 */
/* 0x002fe20000000000 */
/*03b0*/ ISETP.NE.AND P1, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fc60003f25270 */
/*03c0*/ FMUL R21, R5, 0.69314718246459960938 ; /* 0x3f31721805157820 */
/* 0x000fe40000400000 */
/*03d0*/ IMAD.MOV.U32 R5, RZ, RZ, R13.reuse ; /* 0x000000ffff057224 */
/* 0x100fe400078e000d */
/*03e0*/ IMAD.X R13, RZ, RZ, R13, P3 ; /* 0x000000ffff0d7224 */
/* 0x000fc600018e060d */
/*03f0*/ STG.E [R4.64], R21 ; /* 0x0000001504007986 */
/* 0x0001e8000c101904 */
/*0400*/ STG.E [R6.64], R19 ; /* 0x0000001306007986 */
/* 0x0001e2000c101904 */
/*0410*/ @P1 BRA 0x1c0 ; /* 0xfffffda000001947 */
/* 0x000fea000383ffff */
/*0420*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0430*/ MOV R19, c[0x0][0x17c] ; /* 0x00005f0000137a02 */
/* 0x001fe20000000f00 */
/*0440*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0c7624 */
/* 0x000fe200078e00ff */
/*0450*/ MOV R13, c[0x0][0x174] ; /* 0x00005d00000d7a02 */
/* 0x000fe20000000f00 */
/*0460*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff0e7624 */
/* 0x000fe200078e00ff */
/*0470*/ MOV R15, c[0x0][0x16c] ; /* 0x00005b00000f7a02 */
/* 0x000fe40000000f00 */
/*0480*/ MOV R16, c[0x0][0x160] ; /* 0x0000580000107a02 */
/* 0x000fe20000000f00 */
/*0490*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fec0003800000 */
/*04a0*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff117624 */
/* 0x000fe400078e00ff */
/*04b0*/ IMAD R21, R8, c[0x0][0x180], R3 ; /* 0x0000600008157a24 */
/* 0x000fc800078e0203 */
/*04c0*/ IMAD.WIDE R4, R21, 0x4, R16 ; /* 0x0000000415047825 */
/* 0x001fca00078e0210 */
/*04d0*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea2000c1e1900 */
/*04e0*/ IMAD.WIDE R6, R21, 0x4, R14 ; /* 0x0000000415067825 */
/* 0x000fca00078e020e */
/*04f0*/ LDG.E R11, [R6.64] ; /* 0x00000004060b7981 */
/* 0x000ee2000c1e1900 */
/*0500*/ FMUL R8, R8, -1.4426950216293334961 ; /* 0xbfb8aa3b08087820 */
/* 0x004fca0000400000 */
/*0510*/ FSETP.GEU.AND P0, PT, R8, -126, PT ; /* 0xc2fc00000800780b */
/* 0x000fda0003f0e000 */
/*0520*/ @!P0 FMUL R8, R8, 0.5 ; /* 0x3f00000008088820 */
/* 0x000fc80000400000 */
/*0530*/ MUFU.EX2 R9, R8 ; /* 0x0000000800097308 */
/* 0x0000640000000800 */
/*0540*/ IMAD.MOV.U32 R8, RZ, RZ, R0 ; /* 0x000000ffff087224 */
/* 0x001fe400078e0000 */
/*0550*/ @!P0 FMUL R9, R9, R9 ; /* 0x0000000909098220 */
/* 0x002fe20000400000 */
/*0560*/ FSETP.NEU.AND P0, PT, R11, 1, PT ; /* 0x3f8000000b00780b */
/* 0x008fe40003f0d000 */
/*0570*/ MOV R11, R13 ; /* 0x0000000d000b7202 */
/* 0x000fe20000000f00 */
/*0580*/ FADD R9, R9, 1 ; /* 0x3f80000009097421 */
/* 0x000fc80000000000 */
/*0590*/ MUFU.RCP R10, R9 ; /* 0x00000009000a7308 */
/* 0x0000640000001000 */
/*05a0*/ MOV R9, R19 ; /* 0x0000001300097202 */
/* 0x001fca0000000f00 */
/*05b0*/ IMAD.WIDE R8, R21, 0x4, R8 ; /* 0x0000000415087825 */
/* 0x000fc800078e0208 */
/*05c0*/ @P0 FADD R10, -R10, 1 ; /* 0x3f8000000a0a0421 */
/* 0x002fca0000000100 */
/*05d0*/ FMNMX R23, R10, 9.999999682655225389e-21, !PT ; /* 0x1e3ce5080a177809 */
/* 0x000fc80007800000 */
/*05e0*/ FSETP.GEU.AND P0, PT, |R23|.reuse, 1.175494350822287508e-38, PT ; /* 0x008000001700780b */
/* 0x040fe20003f0e200 */
/*05f0*/ FMUL R10, R23, 16777216 ; /* 0x4b800000170a7820 */
/* 0x000fca0000400000 */
/*0600*/ FSEL R18, R10, R23, !P0 ; /* 0x000000170a127208 */
/* 0x000fe40004000000 */
/*0610*/ MOV R10, R12 ; /* 0x0000000c000a7202 */
/* 0x000fe40000000f00 */
/*0620*/ MUFU.LG2 R20, R18 ; /* 0x0000001200147308 */
/* 0x000e260000000c00 */
/*0630*/ IMAD.WIDE R10, R21, 0x4, R10 ; /* 0x00000004150a7825 */
/* 0x000fc800078e020a */
/*0640*/ @!P0 FADD R20, R20, -24 ; /* 0xc1c0000014148421 */
/* 0x001fc80000000000 */
/*0650*/ FMUL R25, R20, 0.69314718246459960938 ; /* 0x3f31721814197820 */
/* 0x000fca0000400000 */
/*0660*/ STG.E [R10.64], R25 ; /* 0x000000190a007986 */
/* 0x000fe8000c101904 */
/*0670*/ STG.E [R8.64], R23 ; /* 0x0000001708007986 */
/* 0x0001e8000c101904 */
/*0680*/ LDG.E R20, [R4.64+0x4] ; /* 0x0000040404147981 */
/* 0x000ea8000c1e1900 */
/*0690*/ LDG.E R24, [R6.64+0x4] ; /* 0x0000040406187981 */
/* 0x000ee2000c1e1900 */
/*06a0*/ FMUL R20, R20, -1.4426950216293334961 ; /* 0xbfb8aa3b14147820 */
/* 0x004fca0000400000 */
/*06b0*/ FSETP.GEU.AND P0, PT, R20, -126, PT ; /* 0xc2fc00001400780b */
/* 0x000fda0003f0e000 */
/*06c0*/ @!P0 FMUL R20, R20, 0.5 ; /* 0x3f00000014148820 */
/* 0x000fc80000400000 */
/*06d0*/ MUFU.EX2 R18, R20 ; /* 0x0000001400127308 */
/* 0x000e640000000800 */
/*06e0*/ @!P0 FMUL R18, R18, R18 ; /* 0x0000001212128220 */
/* 0x002fe20000400000 */
/*06f0*/ FSETP.NEU.AND P0, PT, R24, 1, PT ; /* 0x3f8000001800780b */
/* 0x008fc60003f0d000 */
/*0700*/ FADD R18, R18, 1 ; /* 0x3f80000012127421 */
/* 0x000fc80000000000 */
/*0710*/ MUFU.RCP R22, R18 ; /* 0x0000001200167308 */
/* 0x000e6c0000001000 */
/*0720*/ @P0 FADD R22, -R22, 1 ; /* 0x3f80000016160421 */
/* 0x002fca0000000100 */
/*0730*/ FMNMX R23, R22, 9.999999682655225389e-21, !PT ; /* 0x1e3ce50816177809 */
/* 0x001fc80007800000 */
/*0740*/ FSETP.GEU.AND P0, PT, |R23|.reuse, 1.175494350822287508e-38, PT ; /* 0x008000001700780b */
/* 0x040fe20003f0e200 */
/*0750*/ FMUL R22, R23, 16777216 ; /* 0x4b80000017167820 */
/* 0x000fca0000400000 */
/*0760*/ FSEL R22, R22, R23, !P0 ; /* 0x0000001716167208 */
/* 0x000fc80004000000 */
/*0770*/ MUFU.LG2 R24, R22 ; /* 0x0000001600187308 */
/* 0x000e260000000c00 */
/*0780*/ @!P0 FADD R24, R24, -24 ; /* 0xc1c0000018188421 */
/* 0x001fc80000000000 */
/*0790*/ FMUL R25, R24, 0.69314718246459960938 ; /* 0x3f31721818197820 */
/* 0x000fca0000400000 */
/*07a0*/ STG.E [R10.64+0x4], R25 ; /* 0x000004190a007986 */
/* 0x000fe8000c101904 */
/*07b0*/ STG.E [R8.64+0x4], R23 ; /* 0x0000041708007986 */
/* 0x0001e8000c101904 */
/*07c0*/ LDG.E R18, [R4.64+0x8] ; /* 0x0000080404127981 */
/* 0x000ea8000c1e1900 */
/*07d0*/ LDG.E R24, [R6.64+0x8] ; /* 0x0000080406187981 */
/* 0x000ee2000c1e1900 */
/*07e0*/ FMUL R18, R18, -1.4426950216293334961 ; /* 0xbfb8aa3b12127820 */
/* 0x004fca0000400000 */
/*07f0*/ FSETP.GEU.AND P0, PT, R18, -126, PT ; /* 0xc2fc00001200780b */
/* 0x000fda0003f0e000 */
/*0800*/ @!P0 FMUL R18, R18, 0.5 ; /* 0x3f00000012128820 */
/* 0x000fc80000400000 */
/*0810*/ MUFU.EX2 R20, R18 ; /* 0x0000001200147308 */
/* 0x000e640000000800 */
/*0820*/ @!P0 FMUL R20, R20, R20 ; /* 0x0000001414148220 */
/* 0x002fe20000400000 */
/*0830*/ FSETP.NEU.AND P0, PT, R24, 1, PT ; /* 0x3f8000001800780b */
/* 0x008fc60003f0d000 */
/*0840*/ FADD R20, R20, 1 ; /* 0x3f80000014147421 */
/* 0x000fc80000000000 */
/*0850*/ MUFU.RCP R22, R20 ; /* 0x0000001400167308 */
/* 0x000e6c0000001000 */
/*0860*/ @P0 FADD R22, -R22, 1 ; /* 0x3f80000016160421 */
/* 0x002fca0000000100 */
/*0870*/ FMNMX R23, R22, 9.999999682655225389e-21, !PT ; /* 0x1e3ce50816177809 */
/* 0x001fc80007800000 */
/*0880*/ FSETP.GEU.AND P0, PT, |R23|.reuse, 1.175494350822287508e-38, PT ; /* 0x008000001700780b */
/* 0x040fe20003f0e200 */
/*0890*/ FMUL R22, R23, 16777216 ; /* 0x4b80000017167820 */
/* 0x000fca0000400000 */
/*08a0*/ FSEL R22, R22, R23, !P0 ; /* 0x0000001716167208 */
/* 0x000fc80004000000 */
/*08b0*/ MUFU.LG2 R24, R22 ; /* 0x0000001600187308 */
/* 0x000e260000000c00 */
/*08c0*/ @!P0 FADD R24, R24, -24 ; /* 0xc1c0000018188421 */
/* 0x001fc80000000000 */
/*08d0*/ FMUL R25, R24, 0.69314718246459960938 ; /* 0x3f31721818197820 */
/* 0x000fca0000400000 */
/*08e0*/ STG.E [R10.64+0x8], R25 ; /* 0x000008190a007986 */
/* 0x0001e8000c101904 */
/*08f0*/ STG.E [R8.64+0x8], R23 ; /* 0x0000081708007986 */
/* 0x0001e8000c101904 */
/*0900*/ LDG.E R4, [R4.64+0xc] ; /* 0x00000c0404047981 */
/* 0x000ea8000c1e1900 */
/*0910*/ LDG.E R6, [R6.64+0xc] ; /* 0x00000c0406067981 */
/* 0x000ee2000c1e1900 */
/*0920*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc40007ffe0ff */
/*0930*/ IADD3 R12, P2, R12, 0x10, RZ ; /* 0x000000100c0c7810 */
/* 0x000fe40007f5e0ff */
/*0940*/ IADD3 R0, P1, R0, 0x10, RZ ; /* 0x0000001000007810 */
/* 0x000fe40007f3e0ff */
/*0950*/ IADD3 R14, P3, R14, 0x10, RZ ; /* 0x000000100e0e7810 */
/* 0x000fe20007f7e0ff */
/*0960*/ IMAD.X R13, RZ, RZ, R13, P2 ; /* 0x000000ffff0d7224 */
/* 0x000fe200010e060d */
/*0970*/ IADD3 R16, P4, R16, 0x10, RZ ; /* 0x0000001010107810 */
/* 0x000fe40007f9e0ff */
/*0980*/ IADD3.X R19, RZ, R19, RZ, P1, !PT ; /* 0x00000013ff137210 */
/* 0x000fe40000ffe4ff */
/*0990*/ IADD3.X R15, RZ, R15, RZ, P3, !PT ; /* 0x0000000fff0f7210 */
/* 0x000fc40001ffe4ff */
/*09a0*/ IADD3.X R17, RZ, R17, RZ, P4, !PT ; /* 0x00000011ff117210 */
/* 0x000fe200027fe4ff */
/*09b0*/ FMUL R18, R4, -1.4426950216293334961 ; /* 0xbfb8aa3b04127820 */
/* 0x004fca0000400000 */
/*09c0*/ FSETP.GEU.AND P0, PT, R18, -126, PT ; /* 0xc2fc00001200780b */
/* 0x000fda0003f0e000 */
/*09d0*/ @!P0 FMUL R18, R18, 0.5 ; /* 0x3f00000012128820 */
/* 0x000fc80000400000 */
/*09e0*/ MUFU.EX2 R20, R18 ; /* 0x0000001200147308 */
/* 0x000e640000000800 */
/*09f0*/ @!P0 FMUL R20, R20, R20 ; /* 0x0000001414148220 */
/* 0x002fe20000400000 */
/*0a00*/ FSETP.NEU.AND P0, PT, R6, 1, PT ; /* 0x3f8000000600780b */
/* 0x008fc60003f0d000 */
/*0a10*/ FADD R20, R20, 1 ; /* 0x3f80000014147421 */
/* 0x000fc80000000000 */
/*0a20*/ MUFU.RCP R22, R20 ; /* 0x0000001400167308 */
/* 0x000e6c0000001000 */
/*0a30*/ @P0 FADD R22, -R22, 1 ; /* 0x3f80000016160421 */
/* 0x002fca0000000100 */
/*0a40*/ FMNMX R5, R22, 9.999999682655225389e-21, !PT ; /* 0x1e3ce50816057809 */
/* 0x000fc80007800000 */
/*0a50*/ FSETP.GEU.AND P0, PT, |R5|.reuse, 1.175494350822287508e-38, PT ; /* 0x008000000500780b */
/* 0x040fe20003f0e200 */
/*0a60*/ FMUL R4, R5, 16777216 ; /* 0x4b80000005047820 */
/* 0x000fca0000400000 */
/*0a70*/ FSEL R4, R4, R5, !P0 ; /* 0x0000000504047208 */
/* 0x000fc80004000000 */
/*0a80*/ MUFU.LG2 R6, R4 ; /* 0x0000000400067308 */
/* 0x000e660000000c00 */
/*0a90*/ @!P0 FADD R6, R6, -24 ; /* 0xc1c0000006068421 */
/* 0x002fe20000000000 */
/*0aa0*/ ISETP.GE.AND P0, PT, R3, R2, PT ; /* 0x000000020300720c */
/* 0x000fc60003f06270 */
/*0ab0*/ FMUL R7, R6, 0.69314718246459960938 ; /* 0x3f31721806077820 */
/* 0x000fca0000400000 */
/*0ac0*/ STG.E [R10.64+0xc], R7 ; /* 0x00000c070a007986 */
/* 0x0001e8000c101904 */
/*0ad0*/ STG.E [R8.64+0xc], R5 ; /* 0x00000c0508007986 */
/* 0x0001e2000c101904 */
/*0ae0*/ @!P0 BRA 0x4c0 ; /* 0xfffff9d000008947 */
/* 0x000fea000383ffff */
/*0af0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b00*/ BRA 0xb00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18kEltwiseLogregCostPfS_S_S_iii
.globl _Z18kEltwiseLogregCostPfS_S_S_iii
.p2align 8
.type _Z18kEltwiseLogregCostPfS_S_S_iii,@function
_Z18kEltwiseLogregCostPfS_S_S_iii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x28
s_load_b64 s[2:3], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v0, v0, s4
s_cmp_lt_i32 s15, s3
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, s4, v0
v_min_i32_e32 v9, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_lt_i32_e32 vcc_lo, v0, v9
s_and_b32 s3, s3, vcc_lo
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB0_3
s_load_b256 s[4:11], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[7:8], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s8, v7
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v8, vcc_lo
v_add_co_u32 v3, vcc_lo, s10, v7
v_add_co_ci_u32_e32 v4, vcc_lo, s11, v8, vcc_lo
v_add_co_u32 v5, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v8, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
.LBB0_2:
global_load_b32 v10, v[5:6], off
global_load_b32 v11, v[7:8], off
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, v7, 4
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
s_waitcnt vmcnt(1)
v_mul_f32_e32 v10, 0xbfb8aa3b, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v10, v10
s_waitcnt_depctr 0xfff
v_add_f32_e32 v10, 1.0, v10
v_div_scale_f32 v12, null, v10, v10, 1.0
v_div_scale_f32 v13, vcc_lo, 1.0, v10, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v14, v12
s_waitcnt_depctr 0xfff
v_fma_f32 v15, -v12, v14, 1.0
v_fmac_f32_e32 v14, v15, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v15, v13, v14 :: v_dual_add_nc_u32 v0, 1, v0
v_cmp_ge_i32_e64 s0, v0, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v16, -v12, v15, v13
s_or_b32 s1, s0, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v15, v16, v14
v_fma_f32 v12, -v12, v15, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_fmas_f32 v12, v12, v14, v15
s_waitcnt vmcnt(0)
v_cmp_eq_f32_e32 vcc_lo, 1.0, v11
v_div_fixup_f32 v10, v12, v10, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v12, 1.0, v10
v_cndmask_b32_e32 v10, v12, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_f32_e32 v10, 0x1e3ce508, v10
v_cmp_gt_f32_e32 vcc_lo, 0x800000, v10
v_cndmask_b32_e64 v11, 1.0, 0x4f800000, vcc_lo
v_cndmask_b32_e64 v12, 0, 0x41b17218, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v11, v10, v11
v_log_f32_e32 v11, v11
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v13, 0x3f317217, v11
v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v11|
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v13, v11, 0x3f317217, -v13
v_fmac_f32_e32 v13, 0x3377d1cf, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v13, 0x3f317217, v11
v_cndmask_b32_e32 v11, v11, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_sub_f32_e32 v11, v11, v12
global_store_b32 v[1:2], v11, off
global_store_b32 v[3:4], v10, off
v_add_co_u32 v1, vcc_lo, v1, 4
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18kEltwiseLogregCostPfS_S_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 44
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18kEltwiseLogregCostPfS_S_S_iii, .Lfunc_end0-_Z18kEltwiseLogregCostPfS_S_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 44
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18kEltwiseLogregCostPfS_S_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18kEltwiseLogregCostPfS_S_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00029cad_00000000-6_kEltwiseLogregCost.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z18kEltwiseLogregCostPfS_S_S_iiiPfS_S_S_iii
.type _Z47__device_stub__Z18kEltwiseLogregCostPfS_S_S_iiiPfS_S_S_iii, @function
_Z47__device_stub__Z18kEltwiseLogregCostPfS_S_S_iiiPfS_S_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18kEltwiseLogregCostPfS_S_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z18kEltwiseLogregCostPfS_S_S_iiiPfS_S_S_iii, .-_Z47__device_stub__Z18kEltwiseLogregCostPfS_S_S_iiiPfS_S_S_iii
.globl _Z18kEltwiseLogregCostPfS_S_S_iii
.type _Z18kEltwiseLogregCostPfS_S_S_iii, @function
_Z18kEltwiseLogregCostPfS_S_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z47__device_stub__Z18kEltwiseLogregCostPfS_S_S_iiiPfS_S_S_iii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18kEltwiseLogregCostPfS_S_S_iii, .-_Z18kEltwiseLogregCostPfS_S_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18kEltwiseLogregCostPfS_S_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18kEltwiseLogregCostPfS_S_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kEltwiseLogregCost.hip"
.globl _Z33__device_stub__kEltwiseLogregCostPfS_S_S_iii # -- Begin function _Z33__device_stub__kEltwiseLogregCostPfS_S_S_iii
.p2align 4, 0x90
.type _Z33__device_stub__kEltwiseLogregCostPfS_S_S_iii,@function
_Z33__device_stub__kEltwiseLogregCostPfS_S_S_iii: # @_Z33__device_stub__kEltwiseLogregCostPfS_S_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18kEltwiseLogregCostPfS_S_S_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z33__device_stub__kEltwiseLogregCostPfS_S_S_iii, .Lfunc_end0-_Z33__device_stub__kEltwiseLogregCostPfS_S_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18kEltwiseLogregCostPfS_S_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18kEltwiseLogregCostPfS_S_S_iii,@object # @_Z18kEltwiseLogregCostPfS_S_S_iii
.section .rodata,"a",@progbits
.globl _Z18kEltwiseLogregCostPfS_S_S_iii
.p2align 3, 0x0
_Z18kEltwiseLogregCostPfS_S_S_iii:
.quad _Z33__device_stub__kEltwiseLogregCostPfS_S_S_iii
.size _Z18kEltwiseLogregCostPfS_S_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18kEltwiseLogregCostPfS_S_S_iii"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__kEltwiseLogregCostPfS_S_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18kEltwiseLogregCostPfS_S_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<iostream>
#include<fstream>
#include<time.h>
using namespace std;
typedef struct{
int *x;
int *y;
int nr_vertice;
int mbr[4];
int *boxes;
}polygon;
__device__ int PtInPolygon(int x,int y, int *poly_x, int *poly_y, int nCount){
int nCross=0,i;
int x1,x2,y1,y2;
double ix;
for(i=0;i<nCount-1;i++){
x1=poly_x[i];
y1=poly_y[i];
x2=poly_x[i+1];
y2=poly_y[i+1];
if(y1==y2)continue;
if(y<min(y1,y2))continue;
if(y>=max(y1,y2))continue;
ix=(double)(y-y1)*(double)(x2-x1)/(double)(y2-y1)+x1;
if(ix>x)nCross++;
}
return(nCross%2==1);
}
__global__ void kernel(int nr_v1, int *poly1_x, int *poly1_y, int nr_v2, int *poly2_x, int *poly2_y, int left, int top, int *result){
int tid = threadIdx.x+blockIdx.x*blockDim.x+blockIdx.y*gridDim.x*blockDim.x;
int x = blockIdx.x + left,y = blockIdx.y + top;
int *poly_x, *poly_y, nr_v;
poly_x = (tid%2 == 0) ? poly1_x:poly2_x;
poly_y = (tid%2 == 0) ? poly1_y:poly2_y;
nr_v = (tid%2 == 0) ? nr_v1:nr_v2;
if(PtInPolygon(x, y, poly_x, poly_y, nr_v) == 1)
result[tid] = 1;
else result[tid] = 0;
}
void parsePoly(char *line,polygon *poly){
int i, offset = 0;
sscanf(line, "%d, %d %d %d %d", &poly->nr_vertice, &poly->mbr[0], &poly->mbr[1], &poly->mbr[2], &poly->mbr[3]);
//printf("%d, %d %d %d %d\n", poly->nr_vertice, poly->mbr[0], poly->mbr[1], poly->mbr[2], poly->mbr[3]);
while(line[offset++] != ',');
while(line[offset++] != ',');
poly->x = (int *)malloc(poly->nr_vertice*sizeof(int));
poly->y = (int *)malloc(poly->nr_vertice*sizeof(int));
for(i=0;i<poly->nr_vertice;i++){
sscanf(line+offset, "%d %d", &poly->x[i], &poly->y[i]);
while(line[offset++] != ',');
}
}
int filter(polygon *poly1, polygon *poly2){
/* Check whether the mbr of poly1 contains in poly2 */
if(poly2->mbr[0]<=poly1->mbr[0] && poly2->mbr[1]>=poly1->mbr[1] && poly2->mbr[2]<=poly1->mbr[2] && poly2->mbr[3]>=poly1->mbr[3])
return 0;
else return 1;
}
int main()
{
static const int read_bufsize=65536;
char polygon1[read_bufsize], polygon2[read_bufsize];
const char *filename = "polygon";
fstream polyfile;
polyfile.open(filename,fstream::in | fstream::binary);
polyfile.getline(polygon1,read_bufsize);
polyfile.getline(polygon2,read_bufsize);
polygon *poly1,*poly2;
poly1 = (polygon *)malloc(sizeof(polygon));
poly2 = (polygon *)malloc(sizeof(polygon));
parsePoly(polygon1, poly1);
parsePoly(polygon2, poly2);
if(filter(poly1,poly2)){
cout<<"NO!"<<endl;
return 1;
}
int *dev_poly1_x, *dev_poly1_y, *dev_poly2_x, *dev_poly2_y;
int *host_result, *dev_result;
int boxsize = (poly1->mbr[1]-poly1->mbr[0]+1)*(poly1->mbr[3]-poly1->mbr[2]+1);
cudaMalloc((void **)&dev_poly1_x, poly1->nr_vertice*sizeof(int));
cudaMalloc((void **)&dev_poly1_y, poly1->nr_vertice*sizeof(int));
cudaMalloc((void **)&dev_poly2_x, poly2->nr_vertice*sizeof(int));
cudaMalloc((void **)&dev_poly2_y, poly2->nr_vertice*sizeof(int));
cudaMalloc((void **)&dev_result, 2*boxsize*sizeof(int));
cudaMemcpy(dev_poly1_x, poly1->x, poly1->nr_vertice*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_poly1_y, poly1->y, poly1->nr_vertice*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_poly2_x, poly2->x, poly2->nr_vertice*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_poly2_y, poly2->y, poly2->nr_vertice*sizeof(int), cudaMemcpyHostToDevice);
clock_t start, end;
start = clock();
dim3 grids(poly1->mbr[1]-poly1->mbr[0],poly1->mbr[3]-poly1->mbr[2]);
kernel<<<grids, 2>>>(poly1->nr_vertice, dev_poly1_x, dev_poly1_y, poly2->nr_vertice, dev_poly2_x, dev_poly2_y, poly1->mbr[0], poly1->mbr[2], dev_result);
host_result = (int *)malloc(2*boxsize*sizeof(int));
cudaMemcpy(host_result, dev_result, 2*boxsize*sizeof(int), cudaMemcpyDeviceToHost);
for(int i=0;i<boxsize;i++){
// cout<<i % (poly1->mbr[1]-poly1->mbr[0])+poly1->mbr[0]<<" "<<i/(poly1->mbr[1]-poly1->mbr[0])+poly1->mbr[2]<<endl;
if(host_result[2*i] == 1 && host_result[2*i+1] == 0){
end = clock();
cout<<"NO! Time used: "<<end-start<<endl;
return 1;
}
}
end = clock();
cout<<"YES! Time used: "<<end-start<<endl;
return 0;
} | .file "tmpxft_0013f06d_00000000-6_contain_gpu.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3806:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3806:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11PtInPolygoniiPiS_i
.type _Z11PtInPolygoniiPiS_i, @function
_Z11PtInPolygoniiPiS_i:
.LFB3800:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3800:
.size _Z11PtInPolygoniiPiS_i, .-_Z11PtInPolygoniiPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d, %d %d %d %d"
.LC1:
.string "%d %d"
.text
.globl _Z9parsePolyPcP7polygon
.type _Z9parsePolyPcP7polygon, @function
_Z9parsePolyPcP7polygon:
.LFB3801:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %rbx
movq %rsi, %rbp
leaq 20(%rsi), %rcx
leaq 16(%rsi), %rdx
subq $8, %rsp
.cfi_def_cfa_offset 56
leaq 32(%rsi), %rax
pushq %rax
.cfi_def_cfa_offset 64
leaq 28(%rsi), %r9
leaq 24(%rsi), %r8
leaq .LC0(%rip), %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
addq $16, %rsp
.cfi_def_cfa_offset 48
movl $1, %edx
.L6:
movq %rdx, %rax
addq $1, %rdx
cmpb $44, -2(%rbx,%rdx)
jne .L6
addl $1, %eax
cltq
.L7:
movq %rax, %r14
addq $1, %rax
cmpb $44, -2(%rbx,%rax)
jne .L7
movl 16(%rbp), %r13d
movslq %r13d, %r12
salq $2, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, 0(%rbp)
movq %r12, %rdi
call malloc@PLT
movq %rax, 8(%rbp)
testl %r13d, %r13d
jle .L5
movl $0, %r12d
leaq .LC1(%rip), %r13
.L10:
leaq 0(,%r12,4), %rdx
movq %rdx, %rcx
addq 8(%rbp), %rcx
addq 0(%rbp), %rdx
movslq %r14d, %rdi
addq %rbx, %rdi
movq %r13, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
leal 1(%r14), %eax
cltq
.L9:
movq %rax, %rdx
addq $1, %rax
cmpb $44, -2(%rbx,%rax)
jne .L9
addq $1, %r12
cmpl %r12d, 16(%rbp)
jle .L5
movl %edx, %r14d
jmp .L10
.L5:
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3801:
.size _Z9parsePolyPcP7polygon, .-_Z9parsePolyPcP7polygon
.globl _Z6filterP7polygonS0_
.type _Z6filterP7polygonS0_, @function
_Z6filterP7polygonS0_:
.LFB3802:
.cfi_startproc
endbr64
movl $1, %eax
movl 20(%rdi), %edx
cmpl %edx, 20(%rsi)
jg .L15
movl 24(%rdi), %ecx
cmpl %ecx, 24(%rsi)
jl .L15
movl 28(%rdi), %ecx
cmpl %ecx, 28(%rsi)
jg .L15
movl 32(%rdi), %eax
cmpl %eax, 32(%rsi)
setl %al
movzbl %al, %eax
.L15:
ret
.cfi_endproc
.LFE3802:
.size _Z6filterP7polygonS0_, .-_Z6filterP7polygonS0_
.globl _Z37__device_stub__Z6kerneliPiS_iS_S_iiS_iPiS_iS_S_iiS_
.type _Z37__device_stub__Z6kerneliPiS_iS_S_iiS_iPiS_iS_S_iiS_, @function
_Z37__device_stub__Z6kerneliPiS_iS_S_iiS_iPiS_iS_S_iiS_:
.LFB3828:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 40(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq 224(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movq %rsp, %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6kerneliPiS_iS_S_iiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3828:
.size _Z37__device_stub__Z6kerneliPiS_iS_S_iiS_iPiS_iS_S_iiS_, .-_Z37__device_stub__Z6kerneliPiS_iS_S_iiS_iPiS_iS_S_iiS_
.globl _Z6kerneliPiS_iS_S_iiS_
.type _Z6kerneliPiS_iS_S_iiS_, @function
_Z6kerneliPiS_iS_S_iiS_:
.LFB3829:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z37__device_stub__Z6kerneliPiS_iS_S_iiS_iPiS_iS_S_iiS_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3829:
.size _Z6kerneliPiS_iS_S_iiS_, .-_Z6kerneliPiS_iS_S_iiS_
.section .rodata.str1.1
.LC2:
.string "_Z6kerneliPiS_iS_S_iiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3831:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kerneliPiS_iS_S_iiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3831:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.1
.LC3:
.string "polygon"
.LC4:
.string "NO!"
.LC5:
.string "NO! Time used: "
.LC6:
.string "YES! Time used: "
.text
.globl main
.type main, @function
main:
.LFB3803:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3803
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
leaq -131072(%rsp), %r11
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
subq $632, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
leaq -131664(%rbp), %rbx
movq %rbx, %rdi
.LEHB0:
call _ZNSt13basic_fstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE0:
movl $12, %edx
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
.LEHB1:
call _ZNSt13basic_fstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
leaq -131136(%rbp), %rsi
movq %rbx, %rdi
movl $65536, %edx
call _ZNSi7getlineEPcl@PLT
leaq -65600(%rbp), %rsi
movq %rbx, %rdi
movl $65536, %edx
call _ZNSi7getlineEPcl@PLT
movl $48, %edi
call malloc@PLT
movq %rax, %rbx
movl $48, %edi
call malloc@PLT
movq %rax, %r15
movq %rax, -131736(%rbp)
leaq -131136(%rbp), %rdi
movq %rbx, %rsi
call _Z9parsePolyPcP7polygon
leaq -65600(%rbp), %rdi
movq %r15, %rsi
call _Z9parsePolyPcP7polygon
movq %r15, %rsi
movq %rbx, %rdi
call _Z6filterP7polygonS0_
movl %eax, %r12d
testl %eax, %eax
jne .L46
movl 24(%rbx), %r14d
subl 20(%rbx), %r14d
addl $1, %r14d
movl 32(%rbx), %eax
subl 28(%rbx), %eax
addl $1, %eax
imull %eax, %r14d
movslq 16(%rbx), %rsi
salq $2, %rsi
leaq -131728(%rbp), %rdi
call cudaMalloc@PLT
jmp .L47
.L46:
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L48
.L47:
movslq 16(%rbx), %rsi
salq $2, %rsi
leaq -131720(%rbp), %rdi
call cudaMalloc@PLT
movq -131736(%rbp), %r13
movslq 16(%r13), %rsi
salq $2, %rsi
leaq -131712(%rbp), %rdi
call cudaMalloc@PLT
movslq 16(%r13), %rsi
salq $2, %rsi
leaq -131704(%rbp), %rdi
call cudaMalloc@PLT
leal (%r14,%r14), %r15d
movslq %r15d, %r15
salq $2, %r15
leaq -131696(%rbp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movslq 16(%rbx), %rdx
salq $2, %rdx
movl $1, %ecx
movq (%rbx), %rsi
movq -131728(%rbp), %rdi
call cudaMemcpy@PLT
movslq 16(%rbx), %rdx
salq $2, %rdx
movq 8(%rbx), %rsi
movl $1, %ecx
movq -131720(%rbp), %rdi
call cudaMemcpy@PLT
movslq 16(%r13), %rdx
salq $2, %rdx
movl $1, %ecx
movq 0(%r13), %rsi
movq -131712(%rbp), %rdi
call cudaMemcpy@PLT
movslq 16(%r13), %rdx
salq $2, %rdx
movq %r13, -131736(%rbp)
movq 8(%r13), %rsi
movl $1, %ecx
movq -131704(%rbp), %rdi
call cudaMemcpy@PLT
call clock@PLT
movq %rax, %r13
movl 32(%rbx), %eax
subl 28(%rbx), %eax
movl 24(%rbx), %edx
subl 20(%rbx), %edx
movl %edx, -131688(%rbp)
movl %eax, -131684(%rbp)
movl $1, -131680(%rbp)
movl $2, -131676(%rbp)
movl $1, -131672(%rbp)
movl $1, -131668(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -131676(%rbp), %rdx
movl $1, %ecx
movq -131688(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L33
movq -131736(%rbp), %rax
movl 16(%rax), %ecx
movl 16(%rbx), %edi
subq $8, %rsp
pushq -131696(%rbp)
movl 28(%rbx), %eax
pushq %rax
movl 20(%rbx), %eax
pushq %rax
movq -131704(%rbp), %r9
movq -131712(%rbp), %r8
movq -131720(%rbp), %rdx
movq -131728(%rbp), %rsi
.cfi_escape 0x2e,0x20
call _Z37__device_stub__Z6kerneliPiS_iS_S_iiS_iPiS_iS_S_iiS_
addq $32, %rsp
.L33:
movq %r15, %rdi
call malloc@PLT
movq %rax, %rbx
movl $2, %ecx
movq %r15, %rdx
movq -131696(%rbp), %rsi
movq %rax, %rdi
.cfi_escape 0x2e,0
call cudaMemcpy@PLT
testl %r14d, %r14d
jle .L34
movq %rbx, %rax
movslq %r14d, %r14
leaq (%rbx,%r14,8), %rdx
jmp .L36
.L49:
movq %rax, %rdi
movq %r14, %rsi
subq %r13, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L32
.L35:
addq $8, %rax
cmpq %rdx, %rax
je .L34
.L36:
movl (%rax), %ebx
cmpl $1, %ebx
jne .L35
cmpl $0, 4(%rax)
jne .L35
call clock@PLT
movq %rax, %r14
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L49
.L34:
call clock@PLT
movq %rax, %rbx
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %rsi
subq %r13, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE1:
movl %r12d, %ebx
.L32:
leaq -131664(%rbp), %rdi
call _ZNSt13basic_fstreamIcSt11char_traitsIcEED1Ev@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L50
movl %ebx, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L48:
.cfi_restore_state
movl $1, %ebx
jmp .L32
.L41:
endbr64
movq %rax, %rbx
leaq -131664(%rbp), %rdi
call _ZNSt13basic_fstreamIcSt11char_traitsIcEED1Ev@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L38
call __stack_chk_fail@PLT
.L38:
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3803:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3803:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3803-.LLSDACSB3803
.LLSDACSB3803:
.uleb128 .LEHB0-.LFB3803
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3803
.uleb128 .LEHE1-.LEHB1
.uleb128 .L41-.LFB3803
.uleb128 0
.uleb128 .LEHB2-.LFB3803
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE3803:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<iostream>
#include<fstream>
#include<time.h>
using namespace std;
typedef struct{
int *x;
int *y;
int nr_vertice;
int mbr[4];
int *boxes;
}polygon;
__device__ int PtInPolygon(int x,int y, int *poly_x, int *poly_y, int nCount){
int nCross=0,i;
int x1,x2,y1,y2;
double ix;
for(i=0;i<nCount-1;i++){
x1=poly_x[i];
y1=poly_y[i];
x2=poly_x[i+1];
y2=poly_y[i+1];
if(y1==y2)continue;
if(y<min(y1,y2))continue;
if(y>=max(y1,y2))continue;
ix=(double)(y-y1)*(double)(x2-x1)/(double)(y2-y1)+x1;
if(ix>x)nCross++;
}
return(nCross%2==1);
}
__global__ void kernel(int nr_v1, int *poly1_x, int *poly1_y, int nr_v2, int *poly2_x, int *poly2_y, int left, int top, int *result){
int tid = threadIdx.x+blockIdx.x*blockDim.x+blockIdx.y*gridDim.x*blockDim.x;
int x = blockIdx.x + left,y = blockIdx.y + top;
int *poly_x, *poly_y, nr_v;
poly_x = (tid%2 == 0) ? poly1_x:poly2_x;
poly_y = (tid%2 == 0) ? poly1_y:poly2_y;
nr_v = (tid%2 == 0) ? nr_v1:nr_v2;
if(PtInPolygon(x, y, poly_x, poly_y, nr_v) == 1)
result[tid] = 1;
else result[tid] = 0;
}
void parsePoly(char *line,polygon *poly){
int i, offset = 0;
sscanf(line, "%d, %d %d %d %d", &poly->nr_vertice, &poly->mbr[0], &poly->mbr[1], &poly->mbr[2], &poly->mbr[3]);
//printf("%d, %d %d %d %d\n", poly->nr_vertice, poly->mbr[0], poly->mbr[1], poly->mbr[2], poly->mbr[3]);
while(line[offset++] != ',');
while(line[offset++] != ',');
poly->x = (int *)malloc(poly->nr_vertice*sizeof(int));
poly->y = (int *)malloc(poly->nr_vertice*sizeof(int));
for(i=0;i<poly->nr_vertice;i++){
sscanf(line+offset, "%d %d", &poly->x[i], &poly->y[i]);
while(line[offset++] != ',');
}
}
int filter(polygon *poly1, polygon *poly2){
/* Check whether the mbr of poly1 contains in poly2 */
if(poly2->mbr[0]<=poly1->mbr[0] && poly2->mbr[1]>=poly1->mbr[1] && poly2->mbr[2]<=poly1->mbr[2] && poly2->mbr[3]>=poly1->mbr[3])
return 0;
else return 1;
}
int main()
{
static const int read_bufsize=65536;
char polygon1[read_bufsize], polygon2[read_bufsize];
const char *filename = "polygon";
fstream polyfile;
polyfile.open(filename,fstream::in | fstream::binary);
polyfile.getline(polygon1,read_bufsize);
polyfile.getline(polygon2,read_bufsize);
polygon *poly1,*poly2;
poly1 = (polygon *)malloc(sizeof(polygon));
poly2 = (polygon *)malloc(sizeof(polygon));
parsePoly(polygon1, poly1);
parsePoly(polygon2, poly2);
if(filter(poly1,poly2)){
cout<<"NO!"<<endl;
return 1;
}
int *dev_poly1_x, *dev_poly1_y, *dev_poly2_x, *dev_poly2_y;
int *host_result, *dev_result;
int boxsize = (poly1->mbr[1]-poly1->mbr[0]+1)*(poly1->mbr[3]-poly1->mbr[2]+1);
cudaMalloc((void **)&dev_poly1_x, poly1->nr_vertice*sizeof(int));
cudaMalloc((void **)&dev_poly1_y, poly1->nr_vertice*sizeof(int));
cudaMalloc((void **)&dev_poly2_x, poly2->nr_vertice*sizeof(int));
cudaMalloc((void **)&dev_poly2_y, poly2->nr_vertice*sizeof(int));
cudaMalloc((void **)&dev_result, 2*boxsize*sizeof(int));
cudaMemcpy(dev_poly1_x, poly1->x, poly1->nr_vertice*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_poly1_y, poly1->y, poly1->nr_vertice*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_poly2_x, poly2->x, poly2->nr_vertice*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_poly2_y, poly2->y, poly2->nr_vertice*sizeof(int), cudaMemcpyHostToDevice);
clock_t start, end;
start = clock();
dim3 grids(poly1->mbr[1]-poly1->mbr[0],poly1->mbr[3]-poly1->mbr[2]);
kernel<<<grids, 2>>>(poly1->nr_vertice, dev_poly1_x, dev_poly1_y, poly2->nr_vertice, dev_poly2_x, dev_poly2_y, poly1->mbr[0], poly1->mbr[2], dev_result);
host_result = (int *)malloc(2*boxsize*sizeof(int));
cudaMemcpy(host_result, dev_result, 2*boxsize*sizeof(int), cudaMemcpyDeviceToHost);
for(int i=0;i<boxsize;i++){
// cout<<i % (poly1->mbr[1]-poly1->mbr[0])+poly1->mbr[0]<<" "<<i/(poly1->mbr[1]-poly1->mbr[0])+poly1->mbr[2]<<endl;
if(host_result[2*i] == 1 && host_result[2*i+1] == 0){
end = clock();
cout<<"NO! Time used: "<<end-start<<endl;
return 1;
}
}
end = clock();
cout<<"YES! Time used: "<<end-start<<endl;
return 0;
} | #include <hip/hip_runtime.h>
#include<iostream>
#include<fstream>
#include<time.h>
using namespace std;
typedef struct{
int *x;
int *y;
int nr_vertice;
int mbr[4];
int *boxes;
}polygon;
__device__ int PtInPolygon(int x,int y, int *poly_x, int *poly_y, int nCount){
int nCross=0,i;
int x1,x2,y1,y2;
double ix;
for(i=0;i<nCount-1;i++){
x1=poly_x[i];
y1=poly_y[i];
x2=poly_x[i+1];
y2=poly_y[i+1];
if(y1==y2)continue;
if(y<min(y1,y2))continue;
if(y>=max(y1,y2))continue;
ix=(double)(y-y1)*(double)(x2-x1)/(double)(y2-y1)+x1;
if(ix>x)nCross++;
}
return(nCross%2==1);
}
__global__ void kernel(int nr_v1, int *poly1_x, int *poly1_y, int nr_v2, int *poly2_x, int *poly2_y, int left, int top, int *result){
int tid = threadIdx.x+blockIdx.x*blockDim.x+blockIdx.y*gridDim.x*blockDim.x;
int x = blockIdx.x + left,y = blockIdx.y + top;
int *poly_x, *poly_y, nr_v;
poly_x = (tid%2 == 0) ? poly1_x:poly2_x;
poly_y = (tid%2 == 0) ? poly1_y:poly2_y;
nr_v = (tid%2 == 0) ? nr_v1:nr_v2;
if(PtInPolygon(x, y, poly_x, poly_y, nr_v) == 1)
result[tid] = 1;
else result[tid] = 0;
}
void parsePoly(char *line,polygon *poly){
int i, offset = 0;
sscanf(line, "%d, %d %d %d %d", &poly->nr_vertice, &poly->mbr[0], &poly->mbr[1], &poly->mbr[2], &poly->mbr[3]);
//printf("%d, %d %d %d %d\n", poly->nr_vertice, poly->mbr[0], poly->mbr[1], poly->mbr[2], poly->mbr[3]);
while(line[offset++] != ',');
while(line[offset++] != ',');
poly->x = (int *)malloc(poly->nr_vertice*sizeof(int));
poly->y = (int *)malloc(poly->nr_vertice*sizeof(int));
for(i=0;i<poly->nr_vertice;i++){
sscanf(line+offset, "%d %d", &poly->x[i], &poly->y[i]);
while(line[offset++] != ',');
}
}
int filter(polygon *poly1, polygon *poly2){
/* Check whether the mbr of poly1 contains in poly2 */
if(poly2->mbr[0]<=poly1->mbr[0] && poly2->mbr[1]>=poly1->mbr[1] && poly2->mbr[2]<=poly1->mbr[2] && poly2->mbr[3]>=poly1->mbr[3])
return 0;
else return 1;
}
int main()
{
static const int read_bufsize=65536;
char polygon1[read_bufsize], polygon2[read_bufsize];
const char *filename = "polygon";
fstream polyfile;
polyfile.open(filename,fstream::in | fstream::binary);
polyfile.getline(polygon1,read_bufsize);
polyfile.getline(polygon2,read_bufsize);
polygon *poly1,*poly2;
poly1 = (polygon *)malloc(sizeof(polygon));
poly2 = (polygon *)malloc(sizeof(polygon));
parsePoly(polygon1, poly1);
parsePoly(polygon2, poly2);
if(filter(poly1,poly2)){
cout<<"NO!"<<endl;
return 1;
}
int *dev_poly1_x, *dev_poly1_y, *dev_poly2_x, *dev_poly2_y;
int *host_result, *dev_result;
int boxsize = (poly1->mbr[1]-poly1->mbr[0]+1)*(poly1->mbr[3]-poly1->mbr[2]+1);
hipMalloc((void **)&dev_poly1_x, poly1->nr_vertice*sizeof(int));
hipMalloc((void **)&dev_poly1_y, poly1->nr_vertice*sizeof(int));
hipMalloc((void **)&dev_poly2_x, poly2->nr_vertice*sizeof(int));
hipMalloc((void **)&dev_poly2_y, poly2->nr_vertice*sizeof(int));
hipMalloc((void **)&dev_result, 2*boxsize*sizeof(int));
hipMemcpy(dev_poly1_x, poly1->x, poly1->nr_vertice*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(dev_poly1_y, poly1->y, poly1->nr_vertice*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(dev_poly2_x, poly2->x, poly2->nr_vertice*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(dev_poly2_y, poly2->y, poly2->nr_vertice*sizeof(int), hipMemcpyHostToDevice);
clock_t start, end;
start = clock();
dim3 grids(poly1->mbr[1]-poly1->mbr[0],poly1->mbr[3]-poly1->mbr[2]);
kernel<<<grids, 2>>>(poly1->nr_vertice, dev_poly1_x, dev_poly1_y, poly2->nr_vertice, dev_poly2_x, dev_poly2_y, poly1->mbr[0], poly1->mbr[2], dev_result);
host_result = (int *)malloc(2*boxsize*sizeof(int));
hipMemcpy(host_result, dev_result, 2*boxsize*sizeof(int), hipMemcpyDeviceToHost);
for(int i=0;i<boxsize;i++){
// cout<<i % (poly1->mbr[1]-poly1->mbr[0])+poly1->mbr[0]<<" "<<i/(poly1->mbr[1]-poly1->mbr[0])+poly1->mbr[2]<<endl;
if(host_result[2*i] == 1 && host_result[2*i+1] == 0){
end = clock();
cout<<"NO! Time used: "<<end-start<<endl;
return 1;
}
}
end = clock();
cout<<"YES! Time used: "<<end-start<<endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<iostream>
#include<fstream>
#include<time.h>
using namespace std;
typedef struct{
int *x;
int *y;
int nr_vertice;
int mbr[4];
int *boxes;
}polygon;
__device__ int PtInPolygon(int x,int y, int *poly_x, int *poly_y, int nCount){
int nCross=0,i;
int x1,x2,y1,y2;
double ix;
for(i=0;i<nCount-1;i++){
x1=poly_x[i];
y1=poly_y[i];
x2=poly_x[i+1];
y2=poly_y[i+1];
if(y1==y2)continue;
if(y<min(y1,y2))continue;
if(y>=max(y1,y2))continue;
ix=(double)(y-y1)*(double)(x2-x1)/(double)(y2-y1)+x1;
if(ix>x)nCross++;
}
return(nCross%2==1);
}
__global__ void kernel(int nr_v1, int *poly1_x, int *poly1_y, int nr_v2, int *poly2_x, int *poly2_y, int left, int top, int *result){
int tid = threadIdx.x+blockIdx.x*blockDim.x+blockIdx.y*gridDim.x*blockDim.x;
int x = blockIdx.x + left,y = blockIdx.y + top;
int *poly_x, *poly_y, nr_v;
poly_x = (tid%2 == 0) ? poly1_x:poly2_x;
poly_y = (tid%2 == 0) ? poly1_y:poly2_y;
nr_v = (tid%2 == 0) ? nr_v1:nr_v2;
if(PtInPolygon(x, y, poly_x, poly_y, nr_v) == 1)
result[tid] = 1;
else result[tid] = 0;
}
void parsePoly(char *line,polygon *poly){
int i, offset = 0;
sscanf(line, "%d, %d %d %d %d", &poly->nr_vertice, &poly->mbr[0], &poly->mbr[1], &poly->mbr[2], &poly->mbr[3]);
//printf("%d, %d %d %d %d\n", poly->nr_vertice, poly->mbr[0], poly->mbr[1], poly->mbr[2], poly->mbr[3]);
while(line[offset++] != ',');
while(line[offset++] != ',');
poly->x = (int *)malloc(poly->nr_vertice*sizeof(int));
poly->y = (int *)malloc(poly->nr_vertice*sizeof(int));
for(i=0;i<poly->nr_vertice;i++){
sscanf(line+offset, "%d %d", &poly->x[i], &poly->y[i]);
while(line[offset++] != ',');
}
}
int filter(polygon *poly1, polygon *poly2){
/* Check whether the mbr of poly1 contains in poly2 */
if(poly2->mbr[0]<=poly1->mbr[0] && poly2->mbr[1]>=poly1->mbr[1] && poly2->mbr[2]<=poly1->mbr[2] && poly2->mbr[3]>=poly1->mbr[3])
return 0;
else return 1;
}
int main()
{
static const int read_bufsize=65536;
char polygon1[read_bufsize], polygon2[read_bufsize];
const char *filename = "polygon";
fstream polyfile;
polyfile.open(filename,fstream::in | fstream::binary);
polyfile.getline(polygon1,read_bufsize);
polyfile.getline(polygon2,read_bufsize);
polygon *poly1,*poly2;
poly1 = (polygon *)malloc(sizeof(polygon));
poly2 = (polygon *)malloc(sizeof(polygon));
parsePoly(polygon1, poly1);
parsePoly(polygon2, poly2);
if(filter(poly1,poly2)){
cout<<"NO!"<<endl;
return 1;
}
int *dev_poly1_x, *dev_poly1_y, *dev_poly2_x, *dev_poly2_y;
int *host_result, *dev_result;
int boxsize = (poly1->mbr[1]-poly1->mbr[0]+1)*(poly1->mbr[3]-poly1->mbr[2]+1);
hipMalloc((void **)&dev_poly1_x, poly1->nr_vertice*sizeof(int));
hipMalloc((void **)&dev_poly1_y, poly1->nr_vertice*sizeof(int));
hipMalloc((void **)&dev_poly2_x, poly2->nr_vertice*sizeof(int));
hipMalloc((void **)&dev_poly2_y, poly2->nr_vertice*sizeof(int));
hipMalloc((void **)&dev_result, 2*boxsize*sizeof(int));
hipMemcpy(dev_poly1_x, poly1->x, poly1->nr_vertice*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(dev_poly1_y, poly1->y, poly1->nr_vertice*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(dev_poly2_x, poly2->x, poly2->nr_vertice*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(dev_poly2_y, poly2->y, poly2->nr_vertice*sizeof(int), hipMemcpyHostToDevice);
clock_t start, end;
start = clock();
dim3 grids(poly1->mbr[1]-poly1->mbr[0],poly1->mbr[3]-poly1->mbr[2]);
kernel<<<grids, 2>>>(poly1->nr_vertice, dev_poly1_x, dev_poly1_y, poly2->nr_vertice, dev_poly2_x, dev_poly2_y, poly1->mbr[0], poly1->mbr[2], dev_result);
host_result = (int *)malloc(2*boxsize*sizeof(int));
hipMemcpy(host_result, dev_result, 2*boxsize*sizeof(int), hipMemcpyDeviceToHost);
for(int i=0;i<boxsize;i++){
// cout<<i % (poly1->mbr[1]-poly1->mbr[0])+poly1->mbr[0]<<" "<<i/(poly1->mbr[1]-poly1->mbr[0])+poly1->mbr[2]<<endl;
if(host_result[2*i] == 1 && host_result[2*i+1] == 0){
end = clock();
cout<<"NO! Time used: "<<end-start<<endl;
return 1;
}
}
end = clock();
cout<<"YES! Time used: "<<end-start<<endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kerneliPiS_iS_S_iiS_
.globl _Z6kerneliPiS_iS_S_iiS_
.p2align 8
.type _Z6kerneliPiS_iS_S_iiS_,@function
_Z6kerneliPiS_iS_S_iiS_:
s_clause 0x3
s_load_b32 s2, s[0:1], 0x40
s_load_b32 s3, s[0:1], 0x4c
s_load_b32 s4, s[0:1], 0x0
s_load_b32 s5, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_mov_b32_e32 v2, s4
s_mov_b32 s3, -1
s_mov_b32 s4, exec_lo
v_and_b32_e32 v0, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, 0, v0
v_cndmask_b32_e32 v0, s5, v2, vcc_lo
s_mov_b32 s5, 0
v_cmpx_lt_i32_e32 1, v0
s_cbranch_execz .LBB0_8
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x30
s_load_b128 s[8:11], s[0:1], 0x8
s_load_b128 s[16:19], s[0:1], 0x20
v_add_nc_u32_e32 v0, -1, v0
s_waitcnt lgkmcnt(0)
s_add_i32 s14, s14, s2
v_dual_mov_b32 v4, s9 :: v_dual_mov_b32 v5, s10
v_cvt_f64_i32_e32 v[2:3], s14
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, s11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v8, s17, v4, vcc_lo
v_cndmask_b32_e32 v4, s18, v5, vcc_lo
s_add_i32 s15, s15, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v6, s16, v6, vcc_lo
v_cndmask_b32_e32 v5, s19, v7, vcc_lo
v_add_co_u32 v4, vcc_lo, v4, 4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, v6, 4
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
v_mov_b32_e32 v8, 0
s_branch .LBB0_4
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v0, -1, v0
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v0
v_add_co_u32 v6, s2, v6, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v7, s2, 0, v7, s2
s_or_b32 s5, vcc_lo, s5
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execz .LBB0_7
.LBB0_4:
s_clause 0x1
global_load_b32 v9, v[4:5], off offset:-4
global_load_b32 v10, v[4:5], off
s_waitcnt vmcnt(0)
v_min_i32_e32 v11, v9, v10
v_max_i32_e32 v12, v9, v10
v_cmp_ne_u32_e32 vcc_lo, v10, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_ge_i32_e64 s2, s15, v11
v_cmp_lt_i32_e64 s3, s15, v12
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_3
s_clause 0x1
global_load_b32 v11, v[6:7], off
global_load_b32 v21, v[6:7], off offset:-4
v_sub_nc_u32_e32 v12, s15, v9
v_sub_nc_u32_e32 v9, v10, v9
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_cvt_f64_i32_e32 v[9:10], v9
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v13, v11, v21
v_cvt_f64_i32_e32 v[11:12], v12
v_cvt_f64_i32_e32 v[13:14], v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[11:12], v[11:12], v[13:14]
v_div_scale_f64 v[13:14], null, v[9:10], v[9:10], v[11:12]
v_div_scale_f64 v[19:20], vcc_lo, v[11:12], v[9:10], v[11:12]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[15:16], v[13:14]
s_waitcnt_depctr 0xfff
v_fma_f64 v[17:18], -v[13:14], v[15:16], 1.0
v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], -v[13:14], v[15:16], 1.0
v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[17:18], v[19:20], v[15:16]
v_fma_f64 v[13:14], -v[13:14], v[17:18], v[19:20]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[13:14], v[13:14], v[15:16], v[17:18]
v_div_fixup_f64 v[9:10], v[13:14], v[9:10], v[11:12]
v_cvt_f64_i32_e32 v[11:12], v21
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[9:10], v[9:10], v[11:12]
v_cmpx_gt_f64_e32 v[9:10], v[2:3]
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v8, 1, v8
s_branch .LBB0_2
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s5
v_and_b32_e32 v0, 0x80000001, v8
s_mov_b32 s6, 1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, 1, v0
s_or_not1_b32 s3, vcc_lo, exec_lo
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s4
v_mov_b32_e32 v0, s6
s_and_saveexec_b32 s2, s3
v_mov_b32_e32 v0, 0
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x38
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kerneliPiS_iS_S_iiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 22
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kerneliPiS_iS_S_iiS_, .Lfunc_end0-_Z6kerneliPiS_iS_S_iiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kerneliPiS_iS_S_iiS_
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z6kerneliPiS_iS_S_iiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 22
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<iostream>
#include<fstream>
#include<time.h>
using namespace std;
typedef struct{
int *x;
int *y;
int nr_vertice;
int mbr[4];
int *boxes;
}polygon;
__device__ int PtInPolygon(int x,int y, int *poly_x, int *poly_y, int nCount){
int nCross=0,i;
int x1,x2,y1,y2;
double ix;
for(i=0;i<nCount-1;i++){
x1=poly_x[i];
y1=poly_y[i];
x2=poly_x[i+1];
y2=poly_y[i+1];
if(y1==y2)continue;
if(y<min(y1,y2))continue;
if(y>=max(y1,y2))continue;
ix=(double)(y-y1)*(double)(x2-x1)/(double)(y2-y1)+x1;
if(ix>x)nCross++;
}
return(nCross%2==1);
}
__global__ void kernel(int nr_v1, int *poly1_x, int *poly1_y, int nr_v2, int *poly2_x, int *poly2_y, int left, int top, int *result){
int tid = threadIdx.x+blockIdx.x*blockDim.x+blockIdx.y*gridDim.x*blockDim.x;
int x = blockIdx.x + left,y = blockIdx.y + top;
int *poly_x, *poly_y, nr_v;
poly_x = (tid%2 == 0) ? poly1_x:poly2_x;
poly_y = (tid%2 == 0) ? poly1_y:poly2_y;
nr_v = (tid%2 == 0) ? nr_v1:nr_v2;
if(PtInPolygon(x, y, poly_x, poly_y, nr_v) == 1)
result[tid] = 1;
else result[tid] = 0;
}
void parsePoly(char *line,polygon *poly){
int i, offset = 0;
sscanf(line, "%d, %d %d %d %d", &poly->nr_vertice, &poly->mbr[0], &poly->mbr[1], &poly->mbr[2], &poly->mbr[3]);
//printf("%d, %d %d %d %d\n", poly->nr_vertice, poly->mbr[0], poly->mbr[1], poly->mbr[2], poly->mbr[3]);
while(line[offset++] != ',');
while(line[offset++] != ',');
poly->x = (int *)malloc(poly->nr_vertice*sizeof(int));
poly->y = (int *)malloc(poly->nr_vertice*sizeof(int));
for(i=0;i<poly->nr_vertice;i++){
sscanf(line+offset, "%d %d", &poly->x[i], &poly->y[i]);
while(line[offset++] != ',');
}
}
int filter(polygon *poly1, polygon *poly2){
/* Check whether the mbr of poly1 contains in poly2 */
if(poly2->mbr[0]<=poly1->mbr[0] && poly2->mbr[1]>=poly1->mbr[1] && poly2->mbr[2]<=poly1->mbr[2] && poly2->mbr[3]>=poly1->mbr[3])
return 0;
else return 1;
}
int main()
{
static const int read_bufsize=65536;
char polygon1[read_bufsize], polygon2[read_bufsize];
const char *filename = "polygon";
fstream polyfile;
polyfile.open(filename,fstream::in | fstream::binary);
polyfile.getline(polygon1,read_bufsize);
polyfile.getline(polygon2,read_bufsize);
polygon *poly1,*poly2;
poly1 = (polygon *)malloc(sizeof(polygon));
poly2 = (polygon *)malloc(sizeof(polygon));
parsePoly(polygon1, poly1);
parsePoly(polygon2, poly2);
if(filter(poly1,poly2)){
cout<<"NO!"<<endl;
return 1;
}
int *dev_poly1_x, *dev_poly1_y, *dev_poly2_x, *dev_poly2_y;
int *host_result, *dev_result;
int boxsize = (poly1->mbr[1]-poly1->mbr[0]+1)*(poly1->mbr[3]-poly1->mbr[2]+1);
hipMalloc((void **)&dev_poly1_x, poly1->nr_vertice*sizeof(int));
hipMalloc((void **)&dev_poly1_y, poly1->nr_vertice*sizeof(int));
hipMalloc((void **)&dev_poly2_x, poly2->nr_vertice*sizeof(int));
hipMalloc((void **)&dev_poly2_y, poly2->nr_vertice*sizeof(int));
hipMalloc((void **)&dev_result, 2*boxsize*sizeof(int));
hipMemcpy(dev_poly1_x, poly1->x, poly1->nr_vertice*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(dev_poly1_y, poly1->y, poly1->nr_vertice*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(dev_poly2_x, poly2->x, poly2->nr_vertice*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(dev_poly2_y, poly2->y, poly2->nr_vertice*sizeof(int), hipMemcpyHostToDevice);
clock_t start, end;
start = clock();
dim3 grids(poly1->mbr[1]-poly1->mbr[0],poly1->mbr[3]-poly1->mbr[2]);
kernel<<<grids, 2>>>(poly1->nr_vertice, dev_poly1_x, dev_poly1_y, poly2->nr_vertice, dev_poly2_x, dev_poly2_y, poly1->mbr[0], poly1->mbr[2], dev_result);
host_result = (int *)malloc(2*boxsize*sizeof(int));
hipMemcpy(host_result, dev_result, 2*boxsize*sizeof(int), hipMemcpyDeviceToHost);
for(int i=0;i<boxsize;i++){
// cout<<i % (poly1->mbr[1]-poly1->mbr[0])+poly1->mbr[0]<<" "<<i/(poly1->mbr[1]-poly1->mbr[0])+poly1->mbr[2]<<endl;
if(host_result[2*i] == 1 && host_result[2*i+1] == 0){
end = clock();
cout<<"NO! Time used: "<<end-start<<endl;
return 1;
}
}
end = clock();
cout<<"YES! Time used: "<<end-start<<endl;
return 0;
} | .text
.file "contain_gpu.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__kerneliPiS_iS_S_iiS_ # -- Begin function _Z21__device_stub__kerneliPiS_iS_S_iiS_
.p2align 4, 0x90
.type _Z21__device_stub__kerneliPiS_iS_S_iiS_,@function
_Z21__device_stub__kerneliPiS_iS_S_iiS_: # @_Z21__device_stub__kerneliPiS_iS_S_iiS_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 12(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movl %ecx, 8(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6kerneliPiS_iS_S_iiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z21__device_stub__kerneliPiS_iS_S_iiS_, .Lfunc_end0-_Z21__device_stub__kerneliPiS_iS_S_iiS_
.cfi_endproc
# -- End function
.globl _Z9parsePolyPcP7polygon # -- Begin function _Z9parsePolyPcP7polygon
.p2align 4, 0x90
.type _Z9parsePolyPcP7polygon,@function
_Z9parsePolyPcP7polygon: # @_Z9parsePolyPcP7polygon
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
leaq 16(%rsi), %r15
leaq 20(%rsi), %rcx
leaq 24(%rsi), %r8
leaq 28(%rsi), %r9
leaq 32(%rsi), %rax
movq %rax, (%rsp)
xorl %r13d, %r13d
movl $.L.str, %esi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_sscanf
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
cmpb $44, (%r14,%r13)
leaq 1(%r13), %r13
jne .LBB1_1
.p2align 4, 0x90
.LBB1_2: # %.preheader
# =>This Inner Loop Header: Depth=1
cmpb $44, (%r14,%r13)
leaq 1(%r13), %r13
jne .LBB1_2
# %bb.3:
movslq 16(%rbx), %r12
shlq $2, %r12
movq %r12, %rdi
callq malloc
movq %rax, (%rbx)
movq %r12, %rdi
callq malloc
movq %rax, 8(%rbx)
cmpl $0, 16(%rbx)
jle .LBB1_8
# %bb.4: # %.lr.ph.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_5: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
movslq %r13d, %r13
leaq (%r14,%r13), %rdi
leaq (,%r12,4), %rcx
movq (%rbx), %rdx
addq %rcx, %rdx
addq 8(%rbx), %rcx
movl $.L.str.1, %esi
xorl %eax, %eax
callq __isoc23_sscanf
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
cmpb $44, (%r14,%r13)
leaq 1(%r13), %r13
jne .LBB1_6
# %bb.7: # in Loop: Header=BB1_5 Depth=1
incq %r12
movslq (%r15), %rax
cmpq %rax, %r12
jl .LBB1_5
.LBB1_8: # %._crit_edge
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z9parsePolyPcP7polygon, .Lfunc_end1-_Z9parsePolyPcP7polygon
.cfi_endproc
# -- End function
.globl _Z6filterP7polygonS0_ # -- Begin function _Z6filterP7polygonS0_
.p2align 4, 0x90
.type _Z6filterP7polygonS0_,@function
_Z6filterP7polygonS0_: # @_Z6filterP7polygonS0_
.cfi_startproc
# %bb.0:
movl 20(%rsi), %eax
cmpl 20(%rdi), %eax
jg .LBB2_4
# %bb.1:
movl 24(%rsi), %eax
cmpl 24(%rdi), %eax
jl .LBB2_4
# %bb.2:
movl 28(%rsi), %eax
cmpl 28(%rdi), %eax
jg .LBB2_4
# %bb.3:
movl 32(%rsi), %ecx
xorl %eax, %eax
cmpl 32(%rdi), %ecx
jge .LBB2_5
.LBB2_4:
movl $1, %eax
.LBB2_5:
retq
.Lfunc_end2:
.size _Z6filterP7polygonS0_, .Lfunc_end2-_Z6filterP7polygonS0_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $131832, %rsp # imm = 0x202F8
.cfi_def_cfa_offset 131888
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
.cfi_escape 0x2e, 0x00
leaq 224(%rsp), %rbx
movq %rbx, %rdi
callq _ZNSt13basic_fstreamIcSt11char_traitsIcEEC1Ev
leaq 248(%rsp), %rdi
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %esi
movl $12, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp1:
# %bb.1: # %.noexc
movq 224(%rsp), %rcx
addq -24(%rcx), %rbx
xorl %esi, %esi
testq %rax, %rax
jne .LBB3_3
# %bb.2:
movl 32(%rbx), %esi
orl $4, %esi
.LBB3_3: # %.invoke140
.Ltmp2:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp3:
# %bb.4: # %_ZNSt13basic_fstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit
movq 224(%rsp), %rax
movq -24(%rax), %rax
movq 464(%rsp,%rax), %rbx
testq %rbx, %rbx
je .LBB3_11
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB3_7
# %bb.6:
movzbl 67(%rbx), %eax
jmp .LBB3_9
.LBB3_7:
.Ltmp4:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp5:
# %bb.8: # %.noexc70
movq (%rbx), %rax
.Ltmp6:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp7:
.LBB3_9: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp8:
.cfi_escape 0x2e, 0x00
movsbl %al, %ecx
leaq 224(%rsp), %rdi
leaq 66288(%rsp), %rsi
movl $65536, %edx # imm = 0x10000
callq _ZNSi7getlineEPclc
.Ltmp9:
# %bb.10: # %_ZNSi7getlineEPcl.exit
movq 224(%rsp), %rax
movq -24(%rax), %rax
movq 464(%rsp,%rax), %rbx
testq %rbx, %rbx
je .LBB3_11
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i74
cmpb $0, 56(%rbx)
je .LBB3_15
# %bb.14:
movzbl 67(%rbx), %eax
jmp .LBB3_17
.LBB3_15:
.Ltmp10:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp11:
# %bb.16: # %.noexc79
movq (%rbx), %rax
.Ltmp12:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp13:
.LBB3_17: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i76
.Ltmp14:
.cfi_escape 0x2e, 0x00
movsbl %al, %ecx
leaq 224(%rsp), %rdi
leaq 752(%rsp), %rsi
movl $65536, %edx # imm = 0x10000
callq _ZNSi7getlineEPclc
.Ltmp15:
# %bb.18: # %_ZNSi7getlineEPcl.exit82
.cfi_escape 0x2e, 0x00
movl $48, %edi
callq malloc
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $48, %edi
callq malloc
movq %rax, %r15
.cfi_escape 0x2e, 0x00
leaq 66288(%rsp), %rdi
movq %r14, %rsi
callq _Z9parsePolyPcP7polygon
.cfi_escape 0x2e, 0x00
leaq 752(%rsp), %rdi
movq %r15, %rsi
callq _Z9parsePolyPcP7polygon
movl 20(%r14), %ebx
cmpl %ebx, 20(%r15)
jg .LBB3_22
# %bb.19:
movl 24(%r15), %eax
cmpl 24(%r14), %eax
jl .LBB3_22
# %bb.20:
movl 28(%r15), %eax
cmpl 28(%r14), %eax
jg .LBB3_22
# %bb.21:
movl 32(%r15), %eax
cmpl 32(%r14), %eax
jge .LBB3_33
.LBB3_22: # %.critedge
.Ltmp73:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp74:
# %bb.23: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB3_24
# %bb.26: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i100
cmpb $0, 56(%rbx)
je .LBB3_28
# %bb.27:
movzbl 67(%rbx), %eax
jmp .LBB3_30
.LBB3_28:
.Ltmp75:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp76:
# %bb.29: # %.noexc105
movq (%rbx), %rax
.Ltmp77:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp78:
.LBB3_30: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i102
.Ltmp79:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp80:
# %bb.31: # %.noexc107
movl $1, %ebp
.Ltmp81:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp82:
.LBB3_78: # %_ZNSolsEPFRSoS_E.exit
.cfi_escape 0x2e, 0x00
leaq 224(%rsp), %rdi
movl $_ZTTSt13basic_fstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt13basic_fstreamIcSt11char_traitsIcEED2Ev
leaq 488(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNSt8ios_baseD2Ev
movl %ebp, %eax
addq $131832, %rsp # imm = 0x202F8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_33: # %_Z6filterP7polygonS0_.exit
.cfi_def_cfa_offset 131888
movl 24(%r14), %ebp
movl 32(%r14), %r13d
subl 28(%r14), %r13d
movslq 16(%r14), %rsi
shlq $2, %rsi
.Ltmp16:
.cfi_escape 0x2e, 0x00
leaq 48(%rsp), %rdi
callq hipMalloc
.Ltmp17:
# %bb.34:
movslq 16(%r14), %rsi
shlq $2, %rsi
.Ltmp18:
.cfi_escape 0x2e, 0x00
leaq 40(%rsp), %rdi
callq hipMalloc
.Ltmp19:
# %bb.35:
movslq 16(%r15), %rsi
shlq $2, %rsi
.Ltmp20:
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rdi
callq hipMalloc
.Ltmp21:
# %bb.36:
movslq 16(%r15), %rsi
shlq $2, %rsi
.Ltmp22:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
callq hipMalloc
.Ltmp23:
# %bb.37:
subl %ebx, %ebp
incl %ebp
incl %r13d
imull %ebp, %r13d
leal (,%r13,2), %eax
movslq %eax, %r12
shlq $2, %r12
.Ltmp24:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
.Ltmp25:
# %bb.38:
movq 48(%rsp), %rdi
movq (%r14), %rsi
movslq 16(%r14), %rdx
shlq $2, %rdx
.Ltmp26:
.cfi_escape 0x2e, 0x00
movl $1, %ecx
callq hipMemcpy
.Ltmp27:
# %bb.39:
movq 40(%rsp), %rdi
movq 8(%r14), %rsi
movslq 16(%r14), %rdx
shlq $2, %rdx
.Ltmp28:
.cfi_escape 0x2e, 0x00
movl $1, %ecx
callq hipMemcpy
.Ltmp29:
# %bb.40:
movq 32(%rsp), %rdi
movq (%r15), %rsi
movslq 16(%r15), %rdx
shlq $2, %rdx
.Ltmp30:
.cfi_escape 0x2e, 0x00
movl $1, %ecx
callq hipMemcpy
.Ltmp31:
# %bb.41:
movq 24(%rsp), %rdi
movq 8(%r15), %rsi
movslq 16(%r15), %rdx
shlq $2, %rdx
.Ltmp32:
.cfi_escape 0x2e, 0x00
movl $1, %ecx
callq hipMemcpy
.Ltmp33:
# %bb.42:
.cfi_escape 0x2e, 0x00
callq clock
movq %rax, %rbx
movl 24(%r14), %eax
movl 32(%r14), %edi
subl 20(%r14), %eax
subl 28(%r14), %edi
shlq $32, %rdi
orq %rax, %rdi
.Ltmp35:
.cfi_escape 0x2e, 0x00
movabsq $4294967298, %rdx # imm = 0x100000002
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp36:
# %bb.43:
testl %eax, %eax
jne .LBB3_46
# %bb.44:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movl 16(%r15), %edx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
movl 16(%r14), %r8d
movl 20(%r14), %r9d
movl 28(%r14), %r10d
movq 16(%rsp), %r11
movl %r8d, 12(%rsp)
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movl %edx, 8(%rsp)
movq %rsi, 120(%rsp)
movq %rdi, 112(%rsp)
movl %r9d, 4(%rsp)
movl %r10d, (%rsp)
movq %r11, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 136(%rsp), %rax
movq %rax, 152(%rsp)
leaq 128(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
leaq 120(%rsp), %rax
movq %rax, 176(%rsp)
leaq 112(%rsp), %rax
movq %rax, 184(%rsp)
leaq 4(%rsp), %rax
movq %rax, 192(%rsp)
movq %rsp, %rax
movq %rax, 200(%rsp)
leaq 104(%rsp), %rax
movq %rax, 208(%rsp)
.Ltmp37:
.cfi_escape 0x2e, 0x00
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp38:
# %bb.45: # %.noexc86
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
.Ltmp39:
.cfi_escape 0x2e, 0x10
leaq 144(%rsp), %r9
movl $_Z6kerneliPiS_iS_S_iiS_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp40:
.LBB3_46:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq 16(%rsp), %rsi
.Ltmp41:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
.Ltmp42:
# %bb.47: # %.preheader
xorl %ebp, %ebp
testl %r13d, %r13d
setg %r12b
jle .LBB3_66
# %bb.48: # %.lr.ph.preheader
movl %r13d, %eax
movq %rax, %rcx
negq %rcx
movl $1, %edx
jmp .LBB3_49
.p2align 4, 0x90
.LBB3_65: # in Loop: Header=BB3_49 Depth=1
cmpq %rax, %rdx
setb %r12b
leaq (%rcx,%rdx), %rsi
incq %rsi
incq %rdx
cmpq $1, %rsi
je .LBB3_66
.LBB3_49: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cmpl $1, -8(%r14,%rdx,8)
jne .LBB3_65
# %bb.50: # in Loop: Header=BB3_49 Depth=1
cmpl $0, -4(%r14,%rdx,8)
jne .LBB3_65
# %bb.51:
.cfi_escape 0x2e, 0x00
callq clock
movq %rax, %r14
.Ltmp43:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp44:
# %bb.52: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit89
subq %rbx, %r14
.Ltmp45:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movq %r14, %rsi
callq _ZNSo9_M_insertIlEERSoT_
.Ltmp46:
# %bb.53: # %_ZNSolsEl.exit
movq %rax, %r14
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB3_54
# %bb.58: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i110
cmpb $0, 56(%r15)
je .LBB3_60
# %bb.59:
movzbl 67(%r15), %eax
jmp .LBB3_62
.LBB3_60:
.Ltmp47:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp48:
# %bb.61: # %.noexc115
movq (%r15), %rax
.Ltmp49:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp50:
.LBB3_62: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i112
.Ltmp51:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.Ltmp52:
# %bb.63: # %.noexc117
movl $1, %ebp
.Ltmp53:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp54:
.LBB3_66: # %_ZNSolsEPFRSoS_E.exit92
testb $1, %r12b
jne .LBB3_78
# %bb.67:
.cfi_escape 0x2e, 0x00
callq clock
movq %rax, %r14
.Ltmp55:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp56:
# %bb.68: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit94
subq %rbx, %r14
.Ltmp57:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movq %r14, %rsi
callq _ZNSo9_M_insertIlEERSoT_
.Ltmp58:
# %bb.69: # %_ZNSolsEl.exit96
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB3_70
# %bb.72: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i121
cmpb $0, 56(%r14)
je .LBB3_74
# %bb.73:
movzbl 67(%r14), %eax
jmp .LBB3_76
.LBB3_74:
.Ltmp59:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp60:
# %bb.75: # %.noexc126
movq (%r14), %rax
.Ltmp61:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp62:
.LBB3_76: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i123
.Ltmp63:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp64:
# %bb.77: # %.noexc128
xorl %ebp, %ebp
.Ltmp65:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp66:
jmp .LBB3_78
.LBB3_11: # %.invoke
.Ltmp86:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp87:
# %bb.12: # %.cont
.LBB3_24:
.Ltmp83:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp84:
# %bb.25: # %.noexc104
.LBB3_70:
.Ltmp67:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp68:
# %bb.71: # %.noexc125
.LBB3_54:
.Ltmp70:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp71:
# %bb.57: # %.noexc114
.LBB3_64:
.Ltmp72:
jmp .LBB3_80
.LBB3_56:
.Ltmp69:
jmp .LBB3_80
.LBB3_55:
.Ltmp34:
jmp .LBB3_80
.LBB3_32:
.Ltmp85:
jmp .LBB3_80
.LBB3_79:
.Ltmp88:
.LBB3_80:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
leaq 224(%rsp), %rdi
movl $_ZTTSt13basic_fstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt13basic_fstreamIcSt11char_traitsIcEED2Ev
leaq 488(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNSt8ios_baseD2Ev
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table3:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp15-.Ltmp0 # Call between .Ltmp0 and .Ltmp15
.uleb128 .Ltmp88-.Lfunc_begin0 # jumps to .Ltmp88
.byte 0 # On action: cleanup
.uleb128 .Ltmp73-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp82-.Ltmp73 # Call between .Ltmp73 and .Ltmp82
.uleb128 .Ltmp85-.Lfunc_begin0 # jumps to .Ltmp85
.byte 0 # On action: cleanup
.uleb128 .Ltmp16-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp33-.Ltmp16 # Call between .Ltmp16 and .Ltmp33
.uleb128 .Ltmp34-.Lfunc_begin0 # jumps to .Ltmp34
.byte 0 # On action: cleanup
.uleb128 .Ltmp35-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp42-.Ltmp35 # Call between .Ltmp35 and .Ltmp42
.uleb128 .Ltmp69-.Lfunc_begin0 # jumps to .Ltmp69
.byte 0 # On action: cleanup
.uleb128 .Ltmp43-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp54-.Ltmp43 # Call between .Ltmp43 and .Ltmp54
.uleb128 .Ltmp72-.Lfunc_begin0 # jumps to .Ltmp72
.byte 0 # On action: cleanup
.uleb128 .Ltmp55-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp66-.Ltmp55 # Call between .Ltmp55 and .Ltmp66
.uleb128 .Ltmp69-.Lfunc_begin0 # jumps to .Ltmp69
.byte 0 # On action: cleanup
.uleb128 .Ltmp86-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp87-.Ltmp86 # Call between .Ltmp86 and .Ltmp87
.uleb128 .Ltmp88-.Lfunc_begin0 # jumps to .Ltmp88
.byte 0 # On action: cleanup
.uleb128 .Ltmp83-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp84-.Ltmp83 # Call between .Ltmp83 and .Ltmp84
.uleb128 .Ltmp85-.Lfunc_begin0 # jumps to .Ltmp85
.byte 0 # On action: cleanup
.uleb128 .Ltmp67-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp68-.Ltmp67 # Call between .Ltmp67 and .Ltmp68
.uleb128 .Ltmp69-.Lfunc_begin0 # jumps to .Ltmp69
.byte 0 # On action: cleanup
.uleb128 .Ltmp70-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp71-.Ltmp70 # Call between .Ltmp70 and .Ltmp71
.uleb128 .Ltmp72-.Lfunc_begin0 # jumps to .Ltmp72
.byte 0 # On action: cleanup
.uleb128 .Ltmp71-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Lfunc_end3-.Ltmp71 # Call between .Ltmp71 and .Lfunc_end3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kerneliPiS_iS_S_iiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kerneliPiS_iS_S_iiS_,@object # @_Z6kerneliPiS_iS_S_iiS_
.section .rodata,"a",@progbits
.globl _Z6kerneliPiS_iS_S_iiS_
.p2align 3, 0x0
_Z6kerneliPiS_iS_S_iiS_:
.quad _Z21__device_stub__kerneliPiS_iS_S_iiS_
.size _Z6kerneliPiS_iS_S_iiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d, %d %d %d %d"
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d %d"
.size .L.str.1, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "polygon"
.size .L.str.2, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "NO!"
.size .L.str.3, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "NO! Time used: "
.size .L.str.4, 16
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "YES! Time used: "
.size .L.str.5, 17
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kerneliPiS_iS_S_iiS_"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kerneliPiS_iS_S_iiS_
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z6kerneliPiS_iS_S_iiS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013f06d_00000000-6_contain_gpu.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3806:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3806:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11PtInPolygoniiPiS_i
.type _Z11PtInPolygoniiPiS_i, @function
_Z11PtInPolygoniiPiS_i:
.LFB3800:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3800:
.size _Z11PtInPolygoniiPiS_i, .-_Z11PtInPolygoniiPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d, %d %d %d %d"
.LC1:
.string "%d %d"
.text
.globl _Z9parsePolyPcP7polygon
.type _Z9parsePolyPcP7polygon, @function
_Z9parsePolyPcP7polygon:
.LFB3801:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %rbx
movq %rsi, %rbp
leaq 20(%rsi), %rcx
leaq 16(%rsi), %rdx
subq $8, %rsp
.cfi_def_cfa_offset 56
leaq 32(%rsi), %rax
pushq %rax
.cfi_def_cfa_offset 64
leaq 28(%rsi), %r9
leaq 24(%rsi), %r8
leaq .LC0(%rip), %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
addq $16, %rsp
.cfi_def_cfa_offset 48
movl $1, %edx
.L6:
movq %rdx, %rax
addq $1, %rdx
cmpb $44, -2(%rbx,%rdx)
jne .L6
addl $1, %eax
cltq
.L7:
movq %rax, %r14
addq $1, %rax
cmpb $44, -2(%rbx,%rax)
jne .L7
movl 16(%rbp), %r13d
movslq %r13d, %r12
salq $2, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, 0(%rbp)
movq %r12, %rdi
call malloc@PLT
movq %rax, 8(%rbp)
testl %r13d, %r13d
jle .L5
movl $0, %r12d
leaq .LC1(%rip), %r13
.L10:
leaq 0(,%r12,4), %rdx
movq %rdx, %rcx
addq 8(%rbp), %rcx
addq 0(%rbp), %rdx
movslq %r14d, %rdi
addq %rbx, %rdi
movq %r13, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
leal 1(%r14), %eax
cltq
.L9:
movq %rax, %rdx
addq $1, %rax
cmpb $44, -2(%rbx,%rax)
jne .L9
addq $1, %r12
cmpl %r12d, 16(%rbp)
jle .L5
movl %edx, %r14d
jmp .L10
.L5:
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3801:
.size _Z9parsePolyPcP7polygon, .-_Z9parsePolyPcP7polygon
.globl _Z6filterP7polygonS0_
.type _Z6filterP7polygonS0_, @function
_Z6filterP7polygonS0_:
.LFB3802:
.cfi_startproc
endbr64
movl $1, %eax
movl 20(%rdi), %edx
cmpl %edx, 20(%rsi)
jg .L15
movl 24(%rdi), %ecx
cmpl %ecx, 24(%rsi)
jl .L15
movl 28(%rdi), %ecx
cmpl %ecx, 28(%rsi)
jg .L15
movl 32(%rdi), %eax
cmpl %eax, 32(%rsi)
setl %al
movzbl %al, %eax
.L15:
ret
.cfi_endproc
.LFE3802:
.size _Z6filterP7polygonS0_, .-_Z6filterP7polygonS0_
.globl _Z37__device_stub__Z6kerneliPiS_iS_S_iiS_iPiS_iS_S_iiS_
.type _Z37__device_stub__Z6kerneliPiS_iS_S_iiS_iPiS_iS_S_iiS_, @function
_Z37__device_stub__Z6kerneliPiS_iS_S_iiS_iPiS_iS_S_iiS_:
.LFB3828:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 40(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq 224(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movq %rsp, %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6kerneliPiS_iS_S_iiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3828:
.size _Z37__device_stub__Z6kerneliPiS_iS_S_iiS_iPiS_iS_S_iiS_, .-_Z37__device_stub__Z6kerneliPiS_iS_S_iiS_iPiS_iS_S_iiS_
.globl _Z6kerneliPiS_iS_S_iiS_
.type _Z6kerneliPiS_iS_S_iiS_, @function
_Z6kerneliPiS_iS_S_iiS_:
.LFB3829:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z37__device_stub__Z6kerneliPiS_iS_S_iiS_iPiS_iS_S_iiS_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3829:
.size _Z6kerneliPiS_iS_S_iiS_, .-_Z6kerneliPiS_iS_S_iiS_
.section .rodata.str1.1
.LC2:
.string "_Z6kerneliPiS_iS_S_iiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3831:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kerneliPiS_iS_S_iiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3831:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.1
.LC3:
.string "polygon"
.LC4:
.string "NO!"
.LC5:
.string "NO! Time used: "
.LC6:
.string "YES! Time used: "
.text
.globl main
.type main, @function
main:
.LFB3803:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3803
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
leaq -131072(%rsp), %r11
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
subq $632, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
leaq -131664(%rbp), %rbx
movq %rbx, %rdi
.LEHB0:
call _ZNSt13basic_fstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE0:
movl $12, %edx
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
.LEHB1:
call _ZNSt13basic_fstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
leaq -131136(%rbp), %rsi
movq %rbx, %rdi
movl $65536, %edx
call _ZNSi7getlineEPcl@PLT
leaq -65600(%rbp), %rsi
movq %rbx, %rdi
movl $65536, %edx
call _ZNSi7getlineEPcl@PLT
movl $48, %edi
call malloc@PLT
movq %rax, %rbx
movl $48, %edi
call malloc@PLT
movq %rax, %r15
movq %rax, -131736(%rbp)
leaq -131136(%rbp), %rdi
movq %rbx, %rsi
call _Z9parsePolyPcP7polygon
leaq -65600(%rbp), %rdi
movq %r15, %rsi
call _Z9parsePolyPcP7polygon
movq %r15, %rsi
movq %rbx, %rdi
call _Z6filterP7polygonS0_
movl %eax, %r12d
testl %eax, %eax
jne .L46
movl 24(%rbx), %r14d
subl 20(%rbx), %r14d
addl $1, %r14d
movl 32(%rbx), %eax
subl 28(%rbx), %eax
addl $1, %eax
imull %eax, %r14d
movslq 16(%rbx), %rsi
salq $2, %rsi
leaq -131728(%rbp), %rdi
call cudaMalloc@PLT
jmp .L47
.L46:
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L48
.L47:
movslq 16(%rbx), %rsi
salq $2, %rsi
leaq -131720(%rbp), %rdi
call cudaMalloc@PLT
movq -131736(%rbp), %r13
movslq 16(%r13), %rsi
salq $2, %rsi
leaq -131712(%rbp), %rdi
call cudaMalloc@PLT
movslq 16(%r13), %rsi
salq $2, %rsi
leaq -131704(%rbp), %rdi
call cudaMalloc@PLT
leal (%r14,%r14), %r15d
movslq %r15d, %r15
salq $2, %r15
leaq -131696(%rbp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movslq 16(%rbx), %rdx
salq $2, %rdx
movl $1, %ecx
movq (%rbx), %rsi
movq -131728(%rbp), %rdi
call cudaMemcpy@PLT
movslq 16(%rbx), %rdx
salq $2, %rdx
movq 8(%rbx), %rsi
movl $1, %ecx
movq -131720(%rbp), %rdi
call cudaMemcpy@PLT
movslq 16(%r13), %rdx
salq $2, %rdx
movl $1, %ecx
movq 0(%r13), %rsi
movq -131712(%rbp), %rdi
call cudaMemcpy@PLT
movslq 16(%r13), %rdx
salq $2, %rdx
movq %r13, -131736(%rbp)
movq 8(%r13), %rsi
movl $1, %ecx
movq -131704(%rbp), %rdi
call cudaMemcpy@PLT
call clock@PLT
movq %rax, %r13
movl 32(%rbx), %eax
subl 28(%rbx), %eax
movl 24(%rbx), %edx
subl 20(%rbx), %edx
movl %edx, -131688(%rbp)
movl %eax, -131684(%rbp)
movl $1, -131680(%rbp)
movl $2, -131676(%rbp)
movl $1, -131672(%rbp)
movl $1, -131668(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -131676(%rbp), %rdx
movl $1, %ecx
movq -131688(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L33
movq -131736(%rbp), %rax
movl 16(%rax), %ecx
movl 16(%rbx), %edi
subq $8, %rsp
pushq -131696(%rbp)
movl 28(%rbx), %eax
pushq %rax
movl 20(%rbx), %eax
pushq %rax
movq -131704(%rbp), %r9
movq -131712(%rbp), %r8
movq -131720(%rbp), %rdx
movq -131728(%rbp), %rsi
.cfi_escape 0x2e,0x20
call _Z37__device_stub__Z6kerneliPiS_iS_S_iiS_iPiS_iS_S_iiS_
addq $32, %rsp
.L33:
movq %r15, %rdi
call malloc@PLT
movq %rax, %rbx
movl $2, %ecx
movq %r15, %rdx
movq -131696(%rbp), %rsi
movq %rax, %rdi
.cfi_escape 0x2e,0
call cudaMemcpy@PLT
testl %r14d, %r14d
jle .L34
movq %rbx, %rax
movslq %r14d, %r14
leaq (%rbx,%r14,8), %rdx
jmp .L36
.L49:
movq %rax, %rdi
movq %r14, %rsi
subq %r13, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L32
.L35:
addq $8, %rax
cmpq %rdx, %rax
je .L34
.L36:
movl (%rax), %ebx
cmpl $1, %ebx
jne .L35
cmpl $0, 4(%rax)
jne .L35
call clock@PLT
movq %rax, %r14
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L49
.L34:
call clock@PLT
movq %rax, %rbx
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %rsi
subq %r13, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE1:
movl %r12d, %ebx
.L32:
leaq -131664(%rbp), %rdi
call _ZNSt13basic_fstreamIcSt11char_traitsIcEED1Ev@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L50
movl %ebx, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L48:
.cfi_restore_state
movl $1, %ebx
jmp .L32
.L41:
endbr64
movq %rax, %rbx
leaq -131664(%rbp), %rdi
call _ZNSt13basic_fstreamIcSt11char_traitsIcEED1Ev@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L38
call __stack_chk_fail@PLT
.L38:
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3803:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3803:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3803-.LLSDACSB3803
.LLSDACSB3803:
.uleb128 .LEHB0-.LFB3803
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3803
.uleb128 .LEHE1-.LEHB1
.uleb128 .L41-.LFB3803
.uleb128 0
.uleb128 .LEHB2-.LFB3803
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE3803:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "contain_gpu.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__kerneliPiS_iS_S_iiS_ # -- Begin function _Z21__device_stub__kerneliPiS_iS_S_iiS_
.p2align 4, 0x90
.type _Z21__device_stub__kerneliPiS_iS_S_iiS_,@function
_Z21__device_stub__kerneliPiS_iS_S_iiS_: # @_Z21__device_stub__kerneliPiS_iS_S_iiS_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 12(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movl %ecx, 8(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6kerneliPiS_iS_S_iiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z21__device_stub__kerneliPiS_iS_S_iiS_, .Lfunc_end0-_Z21__device_stub__kerneliPiS_iS_S_iiS_
.cfi_endproc
# -- End function
.globl _Z9parsePolyPcP7polygon # -- Begin function _Z9parsePolyPcP7polygon
.p2align 4, 0x90
.type _Z9parsePolyPcP7polygon,@function
_Z9parsePolyPcP7polygon: # @_Z9parsePolyPcP7polygon
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
leaq 16(%rsi), %r15
leaq 20(%rsi), %rcx
leaq 24(%rsi), %r8
leaq 28(%rsi), %r9
leaq 32(%rsi), %rax
movq %rax, (%rsp)
xorl %r13d, %r13d
movl $.L.str, %esi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_sscanf
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
cmpb $44, (%r14,%r13)
leaq 1(%r13), %r13
jne .LBB1_1
.p2align 4, 0x90
.LBB1_2: # %.preheader
# =>This Inner Loop Header: Depth=1
cmpb $44, (%r14,%r13)
leaq 1(%r13), %r13
jne .LBB1_2
# %bb.3:
movslq 16(%rbx), %r12
shlq $2, %r12
movq %r12, %rdi
callq malloc
movq %rax, (%rbx)
movq %r12, %rdi
callq malloc
movq %rax, 8(%rbx)
cmpl $0, 16(%rbx)
jle .LBB1_8
# %bb.4: # %.lr.ph.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_5: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
movslq %r13d, %r13
leaq (%r14,%r13), %rdi
leaq (,%r12,4), %rcx
movq (%rbx), %rdx
addq %rcx, %rdx
addq 8(%rbx), %rcx
movl $.L.str.1, %esi
xorl %eax, %eax
callq __isoc23_sscanf
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
cmpb $44, (%r14,%r13)
leaq 1(%r13), %r13
jne .LBB1_6
# %bb.7: # in Loop: Header=BB1_5 Depth=1
incq %r12
movslq (%r15), %rax
cmpq %rax, %r12
jl .LBB1_5
.LBB1_8: # %._crit_edge
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z9parsePolyPcP7polygon, .Lfunc_end1-_Z9parsePolyPcP7polygon
.cfi_endproc
# -- End function
.globl _Z6filterP7polygonS0_ # -- Begin function _Z6filterP7polygonS0_
.p2align 4, 0x90
.type _Z6filterP7polygonS0_,@function
_Z6filterP7polygonS0_: # @_Z6filterP7polygonS0_
.cfi_startproc
# %bb.0:
movl 20(%rsi), %eax
cmpl 20(%rdi), %eax
jg .LBB2_4
# %bb.1:
movl 24(%rsi), %eax
cmpl 24(%rdi), %eax
jl .LBB2_4
# %bb.2:
movl 28(%rsi), %eax
cmpl 28(%rdi), %eax
jg .LBB2_4
# %bb.3:
movl 32(%rsi), %ecx
xorl %eax, %eax
cmpl 32(%rdi), %ecx
jge .LBB2_5
.LBB2_4:
movl $1, %eax
.LBB2_5:
retq
.Lfunc_end2:
.size _Z6filterP7polygonS0_, .Lfunc_end2-_Z6filterP7polygonS0_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $131832, %rsp # imm = 0x202F8
.cfi_def_cfa_offset 131888
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
.cfi_escape 0x2e, 0x00
leaq 224(%rsp), %rbx
movq %rbx, %rdi
callq _ZNSt13basic_fstreamIcSt11char_traitsIcEEC1Ev
leaq 248(%rsp), %rdi
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %esi
movl $12, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp1:
# %bb.1: # %.noexc
movq 224(%rsp), %rcx
addq -24(%rcx), %rbx
xorl %esi, %esi
testq %rax, %rax
jne .LBB3_3
# %bb.2:
movl 32(%rbx), %esi
orl $4, %esi
.LBB3_3: # %.invoke140
.Ltmp2:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp3:
# %bb.4: # %_ZNSt13basic_fstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit
movq 224(%rsp), %rax
movq -24(%rax), %rax
movq 464(%rsp,%rax), %rbx
testq %rbx, %rbx
je .LBB3_11
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB3_7
# %bb.6:
movzbl 67(%rbx), %eax
jmp .LBB3_9
.LBB3_7:
.Ltmp4:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp5:
# %bb.8: # %.noexc70
movq (%rbx), %rax
.Ltmp6:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp7:
.LBB3_9: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp8:
.cfi_escape 0x2e, 0x00
movsbl %al, %ecx
leaq 224(%rsp), %rdi
leaq 66288(%rsp), %rsi
movl $65536, %edx # imm = 0x10000
callq _ZNSi7getlineEPclc
.Ltmp9:
# %bb.10: # %_ZNSi7getlineEPcl.exit
movq 224(%rsp), %rax
movq -24(%rax), %rax
movq 464(%rsp,%rax), %rbx
testq %rbx, %rbx
je .LBB3_11
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i74
cmpb $0, 56(%rbx)
je .LBB3_15
# %bb.14:
movzbl 67(%rbx), %eax
jmp .LBB3_17
.LBB3_15:
.Ltmp10:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp11:
# %bb.16: # %.noexc79
movq (%rbx), %rax
.Ltmp12:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp13:
.LBB3_17: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i76
.Ltmp14:
.cfi_escape 0x2e, 0x00
movsbl %al, %ecx
leaq 224(%rsp), %rdi
leaq 752(%rsp), %rsi
movl $65536, %edx # imm = 0x10000
callq _ZNSi7getlineEPclc
.Ltmp15:
# %bb.18: # %_ZNSi7getlineEPcl.exit82
.cfi_escape 0x2e, 0x00
movl $48, %edi
callq malloc
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $48, %edi
callq malloc
movq %rax, %r15
.cfi_escape 0x2e, 0x00
leaq 66288(%rsp), %rdi
movq %r14, %rsi
callq _Z9parsePolyPcP7polygon
.cfi_escape 0x2e, 0x00
leaq 752(%rsp), %rdi
movq %r15, %rsi
callq _Z9parsePolyPcP7polygon
movl 20(%r14), %ebx
cmpl %ebx, 20(%r15)
jg .LBB3_22
# %bb.19:
movl 24(%r15), %eax
cmpl 24(%r14), %eax
jl .LBB3_22
# %bb.20:
movl 28(%r15), %eax
cmpl 28(%r14), %eax
jg .LBB3_22
# %bb.21:
movl 32(%r15), %eax
cmpl 32(%r14), %eax
jge .LBB3_33
.LBB3_22: # %.critedge
.Ltmp73:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp74:
# %bb.23: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB3_24
# %bb.26: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i100
cmpb $0, 56(%rbx)
je .LBB3_28
# %bb.27:
movzbl 67(%rbx), %eax
jmp .LBB3_30
.LBB3_28:
.Ltmp75:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp76:
# %bb.29: # %.noexc105
movq (%rbx), %rax
.Ltmp77:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp78:
.LBB3_30: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i102
.Ltmp79:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp80:
# %bb.31: # %.noexc107
movl $1, %ebp
.Ltmp81:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp82:
.LBB3_78: # %_ZNSolsEPFRSoS_E.exit
.cfi_escape 0x2e, 0x00
leaq 224(%rsp), %rdi
movl $_ZTTSt13basic_fstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt13basic_fstreamIcSt11char_traitsIcEED2Ev
leaq 488(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNSt8ios_baseD2Ev
movl %ebp, %eax
addq $131832, %rsp # imm = 0x202F8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_33: # %_Z6filterP7polygonS0_.exit
.cfi_def_cfa_offset 131888
movl 24(%r14), %ebp
movl 32(%r14), %r13d
subl 28(%r14), %r13d
movslq 16(%r14), %rsi
shlq $2, %rsi
.Ltmp16:
.cfi_escape 0x2e, 0x00
leaq 48(%rsp), %rdi
callq hipMalloc
.Ltmp17:
# %bb.34:
movslq 16(%r14), %rsi
shlq $2, %rsi
.Ltmp18:
.cfi_escape 0x2e, 0x00
leaq 40(%rsp), %rdi
callq hipMalloc
.Ltmp19:
# %bb.35:
movslq 16(%r15), %rsi
shlq $2, %rsi
.Ltmp20:
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rdi
callq hipMalloc
.Ltmp21:
# %bb.36:
movslq 16(%r15), %rsi
shlq $2, %rsi
.Ltmp22:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
callq hipMalloc
.Ltmp23:
# %bb.37:
subl %ebx, %ebp
incl %ebp
incl %r13d
imull %ebp, %r13d
leal (,%r13,2), %eax
movslq %eax, %r12
shlq $2, %r12
.Ltmp24:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
.Ltmp25:
# %bb.38:
movq 48(%rsp), %rdi
movq (%r14), %rsi
movslq 16(%r14), %rdx
shlq $2, %rdx
.Ltmp26:
.cfi_escape 0x2e, 0x00
movl $1, %ecx
callq hipMemcpy
.Ltmp27:
# %bb.39:
movq 40(%rsp), %rdi
movq 8(%r14), %rsi
movslq 16(%r14), %rdx
shlq $2, %rdx
.Ltmp28:
.cfi_escape 0x2e, 0x00
movl $1, %ecx
callq hipMemcpy
.Ltmp29:
# %bb.40:
movq 32(%rsp), %rdi
movq (%r15), %rsi
movslq 16(%r15), %rdx
shlq $2, %rdx
.Ltmp30:
.cfi_escape 0x2e, 0x00
movl $1, %ecx
callq hipMemcpy
.Ltmp31:
# %bb.41:
movq 24(%rsp), %rdi
movq 8(%r15), %rsi
movslq 16(%r15), %rdx
shlq $2, %rdx
.Ltmp32:
.cfi_escape 0x2e, 0x00
movl $1, %ecx
callq hipMemcpy
.Ltmp33:
# %bb.42:
.cfi_escape 0x2e, 0x00
callq clock
movq %rax, %rbx
movl 24(%r14), %eax
movl 32(%r14), %edi
subl 20(%r14), %eax
subl 28(%r14), %edi
shlq $32, %rdi
orq %rax, %rdi
.Ltmp35:
.cfi_escape 0x2e, 0x00
movabsq $4294967298, %rdx # imm = 0x100000002
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp36:
# %bb.43:
testl %eax, %eax
jne .LBB3_46
# %bb.44:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movl 16(%r15), %edx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
movl 16(%r14), %r8d
movl 20(%r14), %r9d
movl 28(%r14), %r10d
movq 16(%rsp), %r11
movl %r8d, 12(%rsp)
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movl %edx, 8(%rsp)
movq %rsi, 120(%rsp)
movq %rdi, 112(%rsp)
movl %r9d, 4(%rsp)
movl %r10d, (%rsp)
movq %r11, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 136(%rsp), %rax
movq %rax, 152(%rsp)
leaq 128(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
leaq 120(%rsp), %rax
movq %rax, 176(%rsp)
leaq 112(%rsp), %rax
movq %rax, 184(%rsp)
leaq 4(%rsp), %rax
movq %rax, 192(%rsp)
movq %rsp, %rax
movq %rax, 200(%rsp)
leaq 104(%rsp), %rax
movq %rax, 208(%rsp)
.Ltmp37:
.cfi_escape 0x2e, 0x00
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp38:
# %bb.45: # %.noexc86
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
.Ltmp39:
.cfi_escape 0x2e, 0x10
leaq 144(%rsp), %r9
movl $_Z6kerneliPiS_iS_S_iiS_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp40:
.LBB3_46:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq 16(%rsp), %rsi
.Ltmp41:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
.Ltmp42:
# %bb.47: # %.preheader
xorl %ebp, %ebp
testl %r13d, %r13d
setg %r12b
jle .LBB3_66
# %bb.48: # %.lr.ph.preheader
movl %r13d, %eax
movq %rax, %rcx
negq %rcx
movl $1, %edx
jmp .LBB3_49
.p2align 4, 0x90
.LBB3_65: # in Loop: Header=BB3_49 Depth=1
cmpq %rax, %rdx
setb %r12b
leaq (%rcx,%rdx), %rsi
incq %rsi
incq %rdx
cmpq $1, %rsi
je .LBB3_66
.LBB3_49: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cmpl $1, -8(%r14,%rdx,8)
jne .LBB3_65
# %bb.50: # in Loop: Header=BB3_49 Depth=1
cmpl $0, -4(%r14,%rdx,8)
jne .LBB3_65
# %bb.51:
.cfi_escape 0x2e, 0x00
callq clock
movq %rax, %r14
.Ltmp43:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp44:
# %bb.52: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit89
subq %rbx, %r14
.Ltmp45:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movq %r14, %rsi
callq _ZNSo9_M_insertIlEERSoT_
.Ltmp46:
# %bb.53: # %_ZNSolsEl.exit
movq %rax, %r14
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB3_54
# %bb.58: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i110
cmpb $0, 56(%r15)
je .LBB3_60
# %bb.59:
movzbl 67(%r15), %eax
jmp .LBB3_62
.LBB3_60:
.Ltmp47:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp48:
# %bb.61: # %.noexc115
movq (%r15), %rax
.Ltmp49:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp50:
.LBB3_62: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i112
.Ltmp51:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.Ltmp52:
# %bb.63: # %.noexc117
movl $1, %ebp
.Ltmp53:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp54:
.LBB3_66: # %_ZNSolsEPFRSoS_E.exit92
testb $1, %r12b
jne .LBB3_78
# %bb.67:
.cfi_escape 0x2e, 0x00
callq clock
movq %rax, %r14
.Ltmp55:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp56:
# %bb.68: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit94
subq %rbx, %r14
.Ltmp57:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movq %r14, %rsi
callq _ZNSo9_M_insertIlEERSoT_
.Ltmp58:
# %bb.69: # %_ZNSolsEl.exit96
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB3_70
# %bb.72: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i121
cmpb $0, 56(%r14)
je .LBB3_74
# %bb.73:
movzbl 67(%r14), %eax
jmp .LBB3_76
.LBB3_74:
.Ltmp59:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp60:
# %bb.75: # %.noexc126
movq (%r14), %rax
.Ltmp61:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp62:
.LBB3_76: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i123
.Ltmp63:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp64:
# %bb.77: # %.noexc128
xorl %ebp, %ebp
.Ltmp65:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp66:
jmp .LBB3_78
.LBB3_11: # %.invoke
.Ltmp86:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp87:
# %bb.12: # %.cont
.LBB3_24:
.Ltmp83:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp84:
# %bb.25: # %.noexc104
.LBB3_70:
.Ltmp67:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp68:
# %bb.71: # %.noexc125
.LBB3_54:
.Ltmp70:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp71:
# %bb.57: # %.noexc114
.LBB3_64:
.Ltmp72:
jmp .LBB3_80
.LBB3_56:
.Ltmp69:
jmp .LBB3_80
.LBB3_55:
.Ltmp34:
jmp .LBB3_80
.LBB3_32:
.Ltmp85:
jmp .LBB3_80
.LBB3_79:
.Ltmp88:
.LBB3_80:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
leaq 224(%rsp), %rdi
movl $_ZTTSt13basic_fstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt13basic_fstreamIcSt11char_traitsIcEED2Ev
leaq 488(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNSt8ios_baseD2Ev
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table3:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp15-.Ltmp0 # Call between .Ltmp0 and .Ltmp15
.uleb128 .Ltmp88-.Lfunc_begin0 # jumps to .Ltmp88
.byte 0 # On action: cleanup
.uleb128 .Ltmp73-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp82-.Ltmp73 # Call between .Ltmp73 and .Ltmp82
.uleb128 .Ltmp85-.Lfunc_begin0 # jumps to .Ltmp85
.byte 0 # On action: cleanup
.uleb128 .Ltmp16-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp33-.Ltmp16 # Call between .Ltmp16 and .Ltmp33
.uleb128 .Ltmp34-.Lfunc_begin0 # jumps to .Ltmp34
.byte 0 # On action: cleanup
.uleb128 .Ltmp35-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp42-.Ltmp35 # Call between .Ltmp35 and .Ltmp42
.uleb128 .Ltmp69-.Lfunc_begin0 # jumps to .Ltmp69
.byte 0 # On action: cleanup
.uleb128 .Ltmp43-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp54-.Ltmp43 # Call between .Ltmp43 and .Ltmp54
.uleb128 .Ltmp72-.Lfunc_begin0 # jumps to .Ltmp72
.byte 0 # On action: cleanup
.uleb128 .Ltmp55-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp66-.Ltmp55 # Call between .Ltmp55 and .Ltmp66
.uleb128 .Ltmp69-.Lfunc_begin0 # jumps to .Ltmp69
.byte 0 # On action: cleanup
.uleb128 .Ltmp86-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp87-.Ltmp86 # Call between .Ltmp86 and .Ltmp87
.uleb128 .Ltmp88-.Lfunc_begin0 # jumps to .Ltmp88
.byte 0 # On action: cleanup
.uleb128 .Ltmp83-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp84-.Ltmp83 # Call between .Ltmp83 and .Ltmp84
.uleb128 .Ltmp85-.Lfunc_begin0 # jumps to .Ltmp85
.byte 0 # On action: cleanup
.uleb128 .Ltmp67-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp68-.Ltmp67 # Call between .Ltmp67 and .Ltmp68
.uleb128 .Ltmp69-.Lfunc_begin0 # jumps to .Ltmp69
.byte 0 # On action: cleanup
.uleb128 .Ltmp70-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp71-.Ltmp70 # Call between .Ltmp70 and .Ltmp71
.uleb128 .Ltmp72-.Lfunc_begin0 # jumps to .Ltmp72
.byte 0 # On action: cleanup
.uleb128 .Ltmp71-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Lfunc_end3-.Ltmp71 # Call between .Ltmp71 and .Lfunc_end3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kerneliPiS_iS_S_iiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kerneliPiS_iS_S_iiS_,@object # @_Z6kerneliPiS_iS_S_iiS_
.section .rodata,"a",@progbits
.globl _Z6kerneliPiS_iS_S_iiS_
.p2align 3, 0x0
_Z6kerneliPiS_iS_S_iiS_:
.quad _Z21__device_stub__kerneliPiS_iS_S_iiS_
.size _Z6kerneliPiS_iS_S_iiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d, %d %d %d %d"
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d %d"
.size .L.str.1, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "polygon"
.size .L.str.2, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "NO!"
.size .L.str.3, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "NO! Time used: "
.size .L.str.4, 16
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "YES! Time used: "
.size .L.str.5, 17
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kerneliPiS_iS_S_iiS_"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kerneliPiS_iS_S_iiS_
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z6kerneliPiS_iS_S_iiS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <string.h>
#include <cuda.h>
/*********************************/
/** constants/define statements **/
/*********************************/
#define THREADS_PER_BLOCK 1024
#define MAX_BLOCKS 65535
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
#define BUFFER_CHAR 'A'
#define PAD_AMT 5
/**********************/
/** function headers **/
/**********************/
void usage(void);
int init_data(char** data, unsigned int num_chars);
int init_data_pad(char** data, unsigned int num_chars);
int read_data(char* data, char* file, unsigned int num_genomes,
unsigned int genome_len, unsigned int buffer_len,
unsigned int buffed_len, unsigned int vicinity);
void free_data(char* data, unsigned int num_genomes);
__global__ void readcmp(char* a, char* b, /*char* result,*/
unsigned long nthreads, unsigned int str_len,
unsigned int vicinity, unsigned int tstride,
char *reduce, unsigned int pop_thresh, unsigned int threads_per_block);
__global__ void reduce(char *g_idata, char *g_odata, unsigned long nthreads,
unsigned int str_len, unsigned int pop_thresh,
unsigned int tstride);
void print_device_info(void);
unsigned int next_power_2(unsigned int v);
unsigned int log_2(unsigned int v);
/***************/
/** functions **/
/***************/
/*
* Function - gpuAssert
*
* Inputs:
* code - gpu error code
* file - current source file
* line - line within this file
* abort - if true, the prgram aborts
*
* Description:
* This function checks the cuda error code, and aborts if it is not a
* success.
*/
inline void gpuAssert(cudaError_t code, char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n",cudaGetErrorString(code),file,line);
if (abort) exit(code);
}
}
/*
* Kernel - readcmp
*
* Arguments:
* a - a pointer to one base
* b - a pointer to the other base
*
* Description:
* TODO...
*/
__global__ void readcmp(char *a, char *b, /*char *result,*/ unsigned long nthreads, unsigned int str_len, unsigned int vicinity, unsigned int tstride, char *reduce, unsigned int pop_thresh, unsigned int threads_per_block) {
extern __shared__ char shared_data[];
char* sdata = (char *)shared_data;
char* result = (char *)&shared_data[threads_per_block];
// Find index of this thread
unsigned long x = threadIdx.x + blockIdx.x * blockDim.x;
unsigned long y = threadIdx.y + blockIdx.y * blockDim.y;
unsigned long tid = x + y * blockDim.x * gridDim.x;
unsigned long i = threadIdx.x; //local block tid
int j, k;
while(tid < nthreads) {
result[i] = a[tid+PAD_AMT] ^ b[tid+PAD_AMT];
__syncthreads();
if (result[i]!=0) {
for (j=1; j<vicinity; j++) {
if(result[i+j]!=0)
break;
}
if (result[i+j]!=0) {
for (k=1; k<j; k++) {
result[i+k]=0xff;
}
}
}
sdata[i] = a[tid+PAD_AMT] ^ b[tid+PAD_AMT-1];
__syncthreads();
if (sdata[i] != 0) {
for (j=1; j<vicinity; j++) {
if(sdata[i+j]!=0)
break;
}
if (sdata[i+j]!=0) {
for (k=1; k<j; k++) {
sdata[i+k]=0xff;
}
}
}
__syncthreads();
result[i] = result[i] && sdata[i];
sdata[i] = b[tid+PAD_AMT] ^ a[tid+PAD_AMT-1];
__syncthreads();
if (sdata[i]!=0) {
for (j=1; j<vicinity; j++) {
if(sdata[i+j]!=0)
break;
}
if (sdata[i+j]!=0) {
for (k=1; k<j; k++) {
sdata[i+k]=0xff;
}
}
}
__syncthreads();
result[i] = result[i] && sdata[i];
__syncthreads();
/////////////////////////////////////////////////////////////////////
//sdata[tid] = g_idata[i];
sdata[i] = result[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s=str_len/2; s>0; s >>= 1){
//if (tid<s) {
if(i < s) {
//sdata[tid] += sdata[tid + s];
sdata[i] += sdata[i + s];
}
__syncthreads();
}
__syncthreads();
// write result for this block to global mem
//if (tid%str_len == 0) {
if(i%str_len == 0) {
//g_odata[i/str_len] = (sdata[tid]<=pop_thresh)?1:0;
reduce[tid/str_len] = (sdata[i]<=pop_thresh)?0:1;
//reduce[tid/str_len] = sdata[i];
}
///////////////////////////////////////////////////////////////////////
__syncthreads();
tid += tstride;
}
}
__global__ void reduce(char *g_idata, char *g_odata, unsigned long nthreads, unsigned int str_len, unsigned int pop_thresh, unsigned int tstride) {
extern __shared__ char sdata[];
// each thread loads one element from global to shared mem
unsigned long x = threadIdx.x + blockIdx.x * blockDim.x;
unsigned long y = threadIdx.y + blockIdx.y * blockDim.y;
unsigned long i = x + y * blockDim.x * gridDim.x; //global tid
unsigned int tid = threadIdx.x; //local block tid
while(i < nthreads) {
sdata[tid] = g_idata[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s=str_len/2; s>0; s >>= 1){
if (tid<s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
// write result for this block to global mem
if (tid%str_len == 0) {
//g_odata[i/str_len] = (sdata[tid]<=pop_thresh)?1:0;
g_odata[i/str_len] = sdata[tid];
}
i += tstride;
}
}
/*
* Function - main
*
* Arguments:
* argc - the number of command line arguments
* argv - an array of the command line arguments
*
* Outputs:
* int - 0 if success, 1 if failure
*
* Description:
* TODO...
*/
int main(int argc, char *argv[]) {
/* check the number of command line arguments */
if(argc != 7) {
usage();
return 1;
}
print_device_info();
/* get arguments */
char* file_1;
char* file_2;
unsigned int num_genomes, genome_len, buffed_len,
buffer_len, vicinity, errors, pop_thresh;
FILE *pop_count_file;
file_1 = argv[1];
file_2 = argv[2];
num_genomes = atoi(argv[3]);
genome_len = atoi(argv[4]);
errors = atoi(argv[5]);
vicinity = atoi(argv[6]);
/* calculate important values */
pop_thresh = (vicinity-1)*(errors-1) + errors; //popcount threshold
buffed_len = next_power_2(genome_len); //genome length + buffer space
buffer_len = buffed_len - genome_len; //difference bw genome len and buf len
unsigned long num_chars = num_genomes*buffed_len;
/* initialize and allocate strings to compare */
char* genome_1_data; //first genome data
char* genome_2_data; //second genome data
//char* result_data; //xor result data
char* reduce_data; //sum of "errors" in each string
if(init_data_pad(&genome_1_data, num_chars)) return 1;
if(init_data_pad(&genome_2_data, num_chars)) return 1;
//if(init_data(&result_data, num_chars)) return 1;
if(init_data(&reduce_data, num_genomes)) return 1;
/* read in the data */
if(read_data(genome_1_data, file_1, num_genomes, genome_len, buffer_len, buffed_len, vicinity+1)) return 1;
if(read_data(genome_2_data, file_2, num_genomes, genome_len, buffer_len, buffed_len, vicinity+1)) return 1;
/* create timing events */
//clock_t start_c, end_c;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
/* initialize and allocate memoer for GPU input and output arrays */
char *dev_genome_1_data;
char *dev_genome_2_data;
//char *dev_result_data;
char *dev_reduce_data;
gpuErrchk( cudaMalloc((void**)&dev_genome_1_data, (num_chars+PAD_AMT)*sizeof(char)));
gpuErrchk( cudaMalloc((void**)&dev_genome_2_data, (num_chars+PAD_AMT)*sizeof(char)));
//gpuErrchk( cudaMalloc((void**)&dev_result_data, num_chars*sizeof(char) ));
gpuErrchk( cudaMalloc((void**)&dev_reduce_data, num_genomes*sizeof(char) ));
/* set start time */
cudaEventRecord(start, 0);
//start_c = clock(); //begin timing computation
/* copy data to GPU */
gpuErrchk(cudaMemcpy( dev_genome_1_data, genome_1_data,
(num_chars+PAD_AMT)*sizeof(char), cudaMemcpyHostToDevice ));
gpuErrchk(cudaMemcpy( dev_genome_2_data, genome_2_data,
(num_chars+PAD_AMT)*sizeof(char), cudaMemcpyHostToDevice ));
/* figure out thread count and dimensions for GPU */
unsigned int num_blocks_x = 128;
unsigned int num_blocks_y = 128;
unsigned int threads_per_block = buffed_len;
unsigned int tstride = threads_per_block*num_blocks_x*num_blocks_y;
dim3 grid_size(num_blocks_x, num_blocks_y, 1);
unsigned int log_len = log_2(buffed_len); //TODO: do we need this??
/*printf("Number of threads per block: %d\n", threads_per_block);
printf("Grid Dim X: %d\n", num_blocks_x);
printf("Grid Dim Y:: %d\n", num_blocks_y);
printf("num_chars: %lu\n", num_chars);*/
/* set start time */
//cudaEventRecord(start,0);
//start_c = clock(); //begin timing computation
/******************/
/** START TIMING **/
/******************/
/*========================================================================*/
/* create and run GPU threads */
readcmp<<<grid_size,threads_per_block,2*threads_per_block>>>(dev_genome_1_data,
dev_genome_2_data,/* dev_result_data,*/ num_chars, buffed_len, vicinity,
tstride, dev_reduce_data, pop_thresh, threads_per_block);
gpuErrchk(cudaThreadSynchronize());
//reduce<<<grid_size,threads_per_block,threads_per_block>>>(dev_result_data, dev_reduce_data, num_chars, buffed_len, pop_thresh, tstride);
//gpuErrchk(cudaThreadSynchronize());
/*========================================================================*/
/****************/
/** END TIMING **/
/****************/
/* set stop time */
//cudaEventRecord(stop,0);
//cudaEventSynchronize( stop );
//end_c = clock(); //end timing computation
gpuErrchk(cudaMemcpy( reduce_data, dev_reduce_data,
num_genomes*sizeof(char), cudaMemcpyDeviceToHost ));
//gpuErrchk(cudaMemcpy( result_data, dev_result_data,
// num_chars*sizeof(char), cudaMemcpyDeviceToHost ));
//printf("\n---------------------------------------------------------------\n");
/*for(unsigned int i = 0; i < num_chars; i ++) {
if (result_data[i]!=0)
printf("%d: %c %c %d\n", i, genome_1_data[i+5], genome_2_data[i+5], (result_data[i] != 0)?1:0);
}*/
//for(unsigned int i = 128000000-128; i < 128000000; i ++) {
// if(i % 128 == 0) {
// printf("pop count:\t%d\n", reduce_data[i/128]);
// }
// printf("%d:\t%c %c --- %d %d %d\n",
// i, genome_1_data[i+5], genome_2_data[i+5],
// ((genome_1_data[i+5] ^ genome_2_data[i+5]) == 0) ? 0:1,
// ((genome_1_data[i+5] ^ genome_2_data[i+5-1]) == 0) ? 0:1,
// ((genome_1_data[i+5-1] ^ genome_2_data[i+5]) == 0) ? 0:1/*,
// result_data[i]*/);
//}
cudaEventRecord(stop,0);
cudaEventSynchronize( stop );
//end_c = clock(); //end timing computation
/* calculate elapsed time for GPU computation */
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
printf("Time to complete comparison %1.4f ms\n", elapsedTime);
//printf("Total time of computation: %f\n", (end_c-start_c)/(double)CLOCKS_PER_SEC);
/* print out result_data to check */
/*for (int i = 0; i < num_chars; i++) {
printf("%d",*(result_data+i));
printf("\n");
}
printf("\n");*/
/* print out reduce_data to check */
/*for (int i = 0; i < 2100; i++) {
printf("%d",*(reduce_data+i));
printf("\n");
}*/
// Writing output pop count to file
// for data collection purposes
unsigned int matches=0;
for (unsigned int q=0; q<num_genomes; q++) {
if (reduce_data[q]==0)
matches++;
}
pop_count_file = fopen("pop_output.txt","w");
fprintf(pop_count_file, "%d %d\n", matches, num_genomes-matches);
/* free and destroy all allocated information */
cudaFree(dev_genome_1_data);
cudaFree(dev_genome_2_data);
//cudaFree(dev_result_data);
cudaFree(dev_reduce_data);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaFreeHost(genome_1_data);
cudaFreeHost(genome_2_data);
//cudaFreeHost(result_data);
cudaFreeHost(reduce_data);
//free(genome_1_data);
//free(genome_2_data);
//free(result_data);
//free(reduce_data);
}
/*
* Function - usage
*
* Description:
* Just prints the usage invariant for this program.
*/
void usage(void) {
printf("\nUsage:\n");
printf("\t./a.out <file_1> <file_2> <num_genomes> <genome_len> <errors> <vicinity>\n\n");
}
/*
* Function - init_data
*
* Arguments:
* data - the array in which to place data
* num_chars - the number of chars to allocate
*
* Outputs:
* int - 0 if success, 1 if failure
*
* Description:
* This function initializes a data array. Pretty simple to follow.
*/
int init_data(char** data, unsigned int num_chars) {
/* allocate pointers for the genome strings */
//*data = (char*)malloc(num_chars * sizeof(char));
cudaHostAlloc((void**)data,num_chars*sizeof(char),cudaHostAllocDefault);
if(NULL == *data) {
printf("init_data - malloc failed\n");
return 1;
}
return 0; //SUCCESS
}
/*
* Function - init_data_pad TODO
*
* Arguments:
* data - the array in which to place data
* num_chars - the number of chars to allocate
*
* Outputs:
* int - 0 if success, 1 if failure
*
* Description:
* This function initializes a data array. Pretty simple to follow.
*/
int init_data_pad(char** data, unsigned int num_chars) {
/* allocate pointers for the genome strings */
//*data = (char*)malloc((num_chars + PAD_AMT) * sizeof(char));
cudaHostAlloc((void**)data,(num_chars+PAD_AMT)*sizeof(char),cudaHostAllocDefault);
if(NULL == *data) {
printf("init_data - malloc failed\n");
return 1;
}
return 0; //SUCCESS
}
/*
* Function - read_data
*
* Arguments:
* data - the char* to which the data will be written
* file - the filae that contains the genomes we care about
* num_genomes - the numebr of genomed to read
* genome_len - the length of the genomes
* buffer_len - the length of the buffer at the end of each genome
* buffed_len - length of genome + buffer
*
* Outputs:
* int - 0 if success, 1 if failure
*
* Description:
* This function reads in all of the genome data from the given genome
* file. Each line contains a genome read, and this is read into each
* string.
*/
int read_data(char* data, char* file, unsigned int num_genomes,
unsigned int genome_len, unsigned int buffer_len,
unsigned int buffed_len,unsigned int vicinity) {
/* basic info and variables */
FILE* ifp; //ifp: "in file pointer"
char* mode = "r";
/* open the file */
ifp = fopen(file, mode);
if(NULL == ifp) {
printf("Can't open input file %s!\n", file);
return 1;
}
/* create read in buffer */
char* buf = (char*)malloc((genome_len+2)*sizeof(char));
/* initialize the padding at beginning of array */
for(int i = 0; i < PAD_AMT; i++) {
*(data + i) = BUFFER_CHAR;
}
int limit_len;
/* calculate the limit to which we will read data */
if (buffer_len < vicinity)
limit_len = buffed_len - vicinity;
else
limit_len = genome_len;
/* read in the file */
for(int i = 0; i < num_genomes; i++) {
//printf("%d\n",i);
if(NULL != fgets(buf, genome_len + 2, ifp)) {
for(int j = 0; j < limit_len; j++) {
*(data + PAD_AMT + i*buffed_len + j) = buf[j];
}
for(int j = 0; j < buffed_len-limit_len; j++) {
*(data + PAD_AMT + i*buffed_len + limit_len + j) = BUFFER_CHAR;
}
//buf[genome_len] = '\0';
//printf("%s\n", buf);
}
else {
printf("Failed to read from the file\n");
return 1;
}
}
/* close the file */
fclose(ifp);
free(buf);
return 0; //SUCCESS
}
/*
* Function - print_device_info
*
* Description:
* Prints valuable information out regarding the CUDA-capable devices
* in this system.
*/
void print_device_info(void) {
cudaDeviceProp prop;
int count;
cudaGetDeviceCount( &count );
for (int i=0; i< count; i++) {
cudaGetDeviceProperties( &prop, i );
printf( " --- General Information for device %d ---\n", i );
printf( "Name: %s\n", prop.name );
printf( "Compute capability: %d.%d\n", prop.major, prop.minor );
printf( "Clock rate: %d\n", prop.clockRate );
printf( "Device copy overlap: " );
if (prop.deviceOverlap)
printf( "Enabled\n" );
else
printf( "Disabled\n" );
printf( "Kernel execition timeout : " );
if (prop.kernelExecTimeoutEnabled)
printf( "Enabled\n" );
else
printf( "Disabled\n" );
printf( " --- Memory Information for device %d ---\n", i );
printf( "Total global mem: %ld\n", prop.totalGlobalMem );
printf( "Total constant Mem: %ld\n", prop.totalConstMem );
printf( "Max mem pitch: %ld\n", prop.memPitch );
printf( "Texture Alignment: %ld\n", prop.textureAlignment );
printf( " --- MP Information for device %d ---\n", i );
printf( "Multiprocessor count: %d\n", prop.multiProcessorCount );
printf( "Shared mem per mp: %ld\n", prop.sharedMemPerBlock );
printf( "Registers per mp: %d\n", prop.regsPerBlock );
printf( "Threads in warp: %d\n", prop.warpSize );
printf( "Max threads per block: %d\n", prop.maxThreadsPerBlock );
printf( "Max thread dimensions: (%d, %d, %d)\n",
prop.maxThreadsDim[0], prop.maxThreadsDim[1],
prop.maxThreadsDim[2] );
printf( "Max grid dimensions: (%d, %d, %d)\n",
prop.maxGridSize[0], prop.maxGridSize[1],
prop.maxGridSize[2] );
printf( "\n" );
}
}
/*
* Function - next_power_2
*
* Arguments:
* v - the value for which we want to find the next power of 2
*
* Outputs:
* unsigned int - the next power of 2 greater than v
*
* Description:
* This code basically rounds v up to the next highest power of 2. So if
* v was 2, this function would return 2. If v was 15, this function would
* return 16. Etcetera.
*
* Source:
* http://graphics.stanford.edu/~seander/bithacks.html
*/
unsigned int next_power_2(unsigned int v) {
v--;
v |= v >> 1;
v |= v >> 2;
v |= v >> 4;
v |= v >> 8;
v |= v >> 16;
v++;
return v;
}
unsigned int log_2(unsigned int v) {
unsigned int r=0;
while (v >>= 1) // unroll for more speed...
{
r++;
}
return r;
} | .file "tmpxft_00048f32_00000000-6_introCUDA_injection_taylor.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2068:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPcib,comdat
.weak _Z9gpuAssert9cudaErrorPcib
.type _Z9gpuAssert9cudaErrorPcib, @function
_Z9gpuAssert9cudaErrorPcib:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z9gpuAssert9cudaErrorPcib, .-_Z9gpuAssert9cudaErrorPcib
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\nUsage:\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "\t./a.out <file_1> <file_2> <num_genomes> <genome_len> <errors> <vicinity>\n\n"
.text
.globl _Z5usagev
.type _Z5usagev, @function
_Z5usagev:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z5usagev, .-_Z5usagev
.section .rodata.str1.1
.LC3:
.string "init_data - malloc failed\n"
.text
.globl _Z9init_dataPPcj
.type _Z9init_dataPPcj, @function
_Z9init_dataPPcj:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movl %esi, %esi
movl $0, %edx
call cudaHostAlloc@PLT
movl $0, %eax
cmpq $0, (%rbx)
je .L17
.L13:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %eax
jmp .L13
.cfi_endproc
.LFE2060:
.size _Z9init_dataPPcj, .-_Z9init_dataPPcj
.globl _Z13init_data_padPPcj
.type _Z13init_data_padPPcj, @function
_Z13init_data_padPPcj:
.LFB2061:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leal 5(%rsi), %esi
movl $0, %edx
call cudaHostAlloc@PLT
movl $0, %eax
cmpq $0, (%rbx)
je .L22
.L18:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %eax
jmp .L18
.cfi_endproc
.LFE2061:
.size _Z13init_data_padPPcj, .-_Z13init_data_padPPcj
.section .rodata.str1.1
.LC4:
.string "r"
.LC5:
.string "Can't open input file %s!\n"
.LC6:
.string "Failed to read from the file\n"
.text
.globl _Z9read_dataPcS_jjjjj
.type _Z9read_dataPcS_jjjjj, @function
_Z9read_dataPcS_jjjjj:
.LFB2062:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r15
movq %rsi, %rbx
movl %edx, 16(%rsp)
movl %ecx, %ebp
movl %r8d, %r14d
movl %r9d, %r12d
movl 96(%rsp), %r13d
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call fopen@PLT
movq %rax, 8(%rsp)
testq %rax, %rax
je .L39
leal 2(%rbp), %eax
movl %eax, 20(%rsp)
movl %eax, %eax
movq %rax, 24(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %rbx
movb $65, (%r15)
movb $65, 1(%r15)
movb $65, 2(%r15)
movb $65, 3(%r15)
movb $65, 4(%r15)
movl %r12d, %eax
subl %r13d, %eax
cmpl %r13d, %r14d
cmovb %eax, %ebp
movl %ebp, %r13d
cmpl $0, 16(%rsp)
je .L28
movl $0, 4(%rsp)
movl $0, %r14d
movslq %ebp, %rbp
jmp .L34
.L39:
movq %rbx, %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %eax
jmp .L23
.L29:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L23
.L32:
addl $1, %r14d
addl %r12d, 4(%rsp)
movl 16(%rsp), %eax
cmpl %eax, %r14d
je .L28
.L34:
movq 8(%rsp), %rcx
movl 20(%rsp), %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call __fgets_chk@PLT
testq %rax, %rax
je .L29
testl %r13d, %r13d
jle .L30
movl 4(%rsp), %ecx
movl $0, %eax
addq %r15, %rcx
.L31:
movzbl (%rbx,%rax), %edx
movb %dl, 5(%rcx,%rax)
addq $1, %rax
cmpq %rax, %rbp
jne .L31
.L30:
movl %r12d, %ecx
subl %r13d, %ecx
cmpl %r13d, %r12d
je .L32
movl 4(%rsp), %eax
leaq 5(%rax,%rbp), %rdx
movl $0, %eax
addq %r15, %rdx
.L33:
movb $65, (%rdx,%rax)
addq $1, %rax
cmpl %ecx, %eax
jb .L33
jmp .L32
.L28:
movq 8(%rsp), %rdi
call fclose@PLT
movq %rbx, %rdi
call free@PLT
movl $0, %eax
.L23:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z9read_dataPcS_jjjjj, .-_Z9read_dataPcS_jjjjj
.section .rodata.str1.8
.align 8
.LC7:
.string " --- General Information for device %d ---\n"
.section .rodata.str1.1
.LC8:
.string "Name: %s\n"
.LC9:
.string "Compute capability: %d.%d\n"
.LC10:
.string "Clock rate: %d\n"
.LC11:
.string "Device copy overlap: "
.LC12:
.string "Enabled\n"
.LC13:
.string "Disabled\n"
.LC14:
.string "Kernel execition timeout : "
.section .rodata.str1.8
.align 8
.LC15:
.string " --- Memory Information for device %d ---\n"
.section .rodata.str1.1
.LC16:
.string "Total global mem: %ld\n"
.LC17:
.string "Total constant Mem: %ld\n"
.LC18:
.string "Max mem pitch: %ld\n"
.LC19:
.string "Texture Alignment: %ld\n"
.section .rodata.str1.8
.align 8
.LC20:
.string " --- MP Information for device %d ---\n"
.section .rodata.str1.1
.LC21:
.string "Multiprocessor count: %d\n"
.LC22:
.string "Shared mem per mp: %ld\n"
.LC23:
.string "Registers per mp: %d\n"
.LC24:
.string "Threads in warp: %d\n"
.LC25:
.string "Max threads per block: %d\n"
.section .rodata.str1.8
.align 8
.LC26:
.string "Max thread dimensions: (%d, %d, %d)\n"
.align 8
.LC27:
.string "Max grid dimensions: (%d, %d, %d)\n"
.section .rodata.str1.1
.LC28:
.string "\n"
.text
.globl _Z17print_device_infov
.type _Z17print_device_infov, @function
_Z17print_device_infov:
.LFB2063:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
jle .L40
movl $0, %ebx
leaq .LC7(%rip), %r15
leaq .LC8(%rip), %r14
leaq .LC9(%rip), %r13
leaq .LC10(%rip), %r12
jmp .L46
.L42:
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L43
.L44:
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L45:
movl %ebx, %edx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rdx
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 368(%rsp), %rdx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 328(%rsp), %rdx
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 384(%rsp), %rdx
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 404(%rsp), %edx
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 312(%rsp), %rdx
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 320(%rsp), %edx
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 324(%rsp), %edx
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
leaq .LC27(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC28(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jle .L40
.L46:
leaq 16(%rsp), %rbp
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movl %ebx, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 380(%rsp), %ecx
movl 376(%rsp), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 364(%rsp), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 400(%rsp)
je .L42
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L43:
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 408(%rsp)
je .L44
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L45
.L40:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L50
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size _Z17print_device_infov, .-_Z17print_device_infov
.globl _Z12next_power_2j
.type _Z12next_power_2j, @function
_Z12next_power_2j:
.LFB2064:
.cfi_startproc
endbr64
subl $1, %edi
movl %edi, %eax
shrl %eax
orl %edi, %eax
movl %eax, %edi
shrl $2, %edi
orl %eax, %edi
movl %edi, %eax
shrl $4, %eax
orl %edi, %eax
movl %eax, %edx
shrl $8, %edx
orl %eax, %edx
movl %edx, %eax
shrl $16, %eax
orl %edx, %eax
addl $1, %eax
ret
.cfi_endproc
.LFE2064:
.size _Z12next_power_2j, .-_Z12next_power_2j
.globl _Z5log_2j
.type _Z5log_2j, @function
_Z5log_2j:
.LFB2065:
.cfi_startproc
endbr64
movl %edi, %eax
shrl %eax
je .L52
movl %eax, %edx
.L54:
shrl %edx
jne .L54
bsrl %eax, %edx
xorl $31, %edx
movl $32, %eax
subl %edx, %eax
.L52:
ret
.cfi_endproc
.LFE2065:
.size _Z5log_2j, .-_Z5log_2j
.globl _Z36__device_stub__Z7readcmpPcS_mjjjS_jjPcS_mjjjS_jj
.type _Z36__device_stub__Z7readcmpPcS_mjjjS_jjPcS_mjjjS_jj, @function
_Z36__device_stub__Z7readcmpPcS_mjjjS_jjPcS_mjjjS_jj:
.LFB2090:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq 208(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L60
.L56:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L61
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7readcmpPcS_mjjjS_jj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L56
.L61:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z36__device_stub__Z7readcmpPcS_mjjjS_jjPcS_mjjjS_jj, .-_Z36__device_stub__Z7readcmpPcS_mjjjS_jjPcS_mjjjS_jj
.globl _Z7readcmpPcS_mjjjS_jj
.type _Z7readcmpPcS_mjjjS_jj, @function
_Z7readcmpPcS_mjjjS_jj:
.LFB2091:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z36__device_stub__Z7readcmpPcS_mjjjS_jjPcS_mjjjS_jj
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z7readcmpPcS_mjjjS_jj, .-_Z7readcmpPcS_mjjjS_jj
.section .rodata.str1.8
.align 8
.LC29:
.string "/home/ubuntu/Datasets/stackv2/train-structured/xhongyi/toybrick/master/cuda/introCUDA_injection_taylor.cu"
.align 8
.LC30:
.string "Time to complete comparison %1.4f ms\n"
.section .rodata.str1.1
.LC31:
.string "w"
.LC32:
.string "pop_output.txt"
.LC33:
.string "%d %d\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
cmpl $7, %edi
je .L65
call _Z5usagev
movl $1, %ebx
.L64:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L78
movl %ebx, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L65:
.cfi_restore_state
movq %rsi, %rbx
call _Z17print_device_infov
movq 8(%rbx), %r15
movq 16(%rbx), %rax
movq %rax, 24(%rsp)
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movl %eax, 40(%rsp)
movq 32(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movq 40(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 32(%rsp)
movq 48(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 16(%rsp)
movl %r13d, 8(%rsp)
movl %r13d, %edi
call _Z12next_power_2j
movl %eax, %r12d
movl %eax, %r14d
imull %ebp, %r14d
leaq 48(%rsp), %rdi
movl %r14d, %esi
call _Z13init_data_padPPcj
movl $1, %ebx
testl %eax, %eax
jne .L64
leaq 56(%rsp), %rdi
movl %r14d, %esi
call _Z13init_data_padPPcj
testl %eax, %eax
jne .L64
leaq 64(%rsp), %rdi
movl 40(%rsp), %esi
call _Z9init_dataPPcj
testl %eax, %eax
jne .L64
movl %r12d, %ecx
subl %r13d, %ecx
movl 16(%rsp), %edx
leal 1(%rdx), %r13d
subq $8, %rsp
.cfi_def_cfa_offset 216
pushq %r13
.cfi_def_cfa_offset 224
movl %r12d, %r9d
movl %ecx, 60(%rsp)
movl %ecx, %r8d
movl 24(%rsp), %ecx
movl 56(%rsp), %edx
movq %r15, %rsi
movq 64(%rsp), %rdi
call _Z9read_dataPcS_jjjjj
addq $16, %rsp
.cfi_def_cfa_offset 208
testl %eax, %eax
jne .L64
subq $8, %rsp
.cfi_def_cfa_offset 216
pushq %r13
.cfi_def_cfa_offset 224
movl %r12d, %r9d
movl 60(%rsp), %r8d
movl 24(%rsp), %ecx
movl 56(%rsp), %edx
movq 40(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z9read_dataPcS_jjjjj
movl %eax, %ebx
addq $16, %rsp
.cfi_def_cfa_offset 208
testl %eax, %eax
je .L79
movl $1, %ebx
jmp .L64
.L79:
movl %r14d, %r15d
movq %r15, 8(%rsp)
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
leaq 80(%rsp), %rdi
call cudaEventCreate@PLT
leaq 5(%r15), %r14
leaq 88(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $277, %edx
leaq .LC29(%rip), %r13
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPcib
leaq 96(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $278, %edx
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPcib
movl %ebp, %r15d
leaq 104(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $280, %edx
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPcib
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %r14, %rdx
movq 48(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $287, %edx
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPcib
movl $1, %ecx
movq %r14, %rdx
movq 56(%rsp), %rsi
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $289, %edx
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPcib
movl $128, 112(%rsp)
movl $128, 116(%rsp)
movl $1, 120(%rsp)
movl %r12d, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
leal (%r12,%r12), %r8d
movl $0, %r9d
movl %r8d, %r8d
movq 124(%rsp), %rdx
movl $1, %ecx
movq 112(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L80
.L67:
call cudaThreadSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $321, %edx
leaq .LC29(%rip), %r12
movq %r12, %rsi
call _Z9gpuAssert9cudaErrorPcib
movl $2, %ecx
movq %r15, %rdx
movq 104(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $337, %edx
movq %r12, %rsi
call _Z9gpuAssert9cudaErrorPcib
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
movq 80(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 124(%rsp), %rdi
movq 80(%rsp), %rdx
movq 72(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 124(%rsp), %xmm0
leaq .LC30(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 64(%rsp), %rdx
movl $0, %eax
movl $0, %r12d
movl 40(%rsp), %ecx
jmp .L68
.L80:
subq $8, %rsp
.cfi_def_cfa_offset 216
pushq %r12
.cfi_def_cfa_offset 224
movq 32(%rsp), %rsi
movl %esi, %eax
subl $1, %eax
movq 48(%rsp), %rcx
movl %ecx, %edx
subl $1, %edx
imull %edx, %eax
addl %ecx, %eax
pushq %rax
.cfi_def_cfa_offset 232
pushq 128(%rsp)
.cfi_def_cfa_offset 240
movl %r12d, %r9d
sall $14, %r9d
movl %esi, %r8d
movl %r12d, %ecx
movq 40(%rsp), %rdx
movq 128(%rsp), %rsi
movq 120(%rsp), %rdi
call _Z36__device_stub__Z7readcmpPcS_mjjjS_jjPcS_mjjjS_jj
addq $32, %rsp
.cfi_def_cfa_offset 208
jmp .L67
.L69:
addq $1, %rax
.L68:
cmpl %ecx, %eax
jnb .L81
cmpb $0, (%rdx,%rax)
jne .L69
addl $1, %r12d
jmp .L69
.L81:
leaq .LC31(%rip), %rsi
leaq .LC32(%rip), %rdi
call fopen@PLT
movq %rax, %rdi
movl %ebp, %r8d
subl %r12d, %r8d
movl %r12d, %ecx
leaq .LC33(%rip), %rdx
movl $2, %esi
movl $0, %eax
call __fprintf_chk@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaEventDestroy@PLT
movq 80(%rsp), %rdi
call cudaEventDestroy@PLT
movq 48(%rsp), %rdi
call cudaFreeHost@PLT
movq 56(%rsp), %rdi
call cudaFreeHost@PLT
movq 64(%rsp), %rdi
call cudaFreeHost@PLT
jmp .L64
.L78:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.globl _Z31__device_stub__Z6reducePcS_mjjjPcS_mjjj
.type _Z31__device_stub__Z6reducePcS_mjjjPcS_mjjj, @function
_Z31__device_stub__Z6reducePcS_mjjjPcS_mjjj:
.LFB2092:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L86
.L82:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L87
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L86:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6reducePcS_mjjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L82
.L87:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2092:
.size _Z31__device_stub__Z6reducePcS_mjjjPcS_mjjj, .-_Z31__device_stub__Z6reducePcS_mjjjPcS_mjjj
.globl _Z6reducePcS_mjjj
.type _Z6reducePcS_mjjj, @function
_Z6reducePcS_mjjj:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z6reducePcS_mjjjPcS_mjjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _Z6reducePcS_mjjj, .-_Z6reducePcS_mjjj
.section .rodata.str1.1
.LC34:
.string "_Z6reducePcS_mjjj"
.LC35:
.string "_Z7readcmpPcS_mjjjS_jj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2095:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC34(%rip), %rdx
movq %rdx, %rcx
leaq _Z6reducePcS_mjjj(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC35(%rip), %rdx
movq %rdx, %rcx
leaq _Z7readcmpPcS_mjjjS_jj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <string.h>
#include <cuda.h>
/*********************************/
/** constants/define statements **/
/*********************************/
#define THREADS_PER_BLOCK 1024
#define MAX_BLOCKS 65535
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
#define BUFFER_CHAR 'A'
#define PAD_AMT 5
/**********************/
/** function headers **/
/**********************/
void usage(void);
int init_data(char** data, unsigned int num_chars);
int init_data_pad(char** data, unsigned int num_chars);
int read_data(char* data, char* file, unsigned int num_genomes,
unsigned int genome_len, unsigned int buffer_len,
unsigned int buffed_len, unsigned int vicinity);
void free_data(char* data, unsigned int num_genomes);
__global__ void readcmp(char* a, char* b, /*char* result,*/
unsigned long nthreads, unsigned int str_len,
unsigned int vicinity, unsigned int tstride,
char *reduce, unsigned int pop_thresh, unsigned int threads_per_block);
__global__ void reduce(char *g_idata, char *g_odata, unsigned long nthreads,
unsigned int str_len, unsigned int pop_thresh,
unsigned int tstride);
void print_device_info(void);
unsigned int next_power_2(unsigned int v);
unsigned int log_2(unsigned int v);
/***************/
/** functions **/
/***************/
/*
* Function - gpuAssert
*
* Inputs:
* code - gpu error code
* file - current source file
* line - line within this file
* abort - if true, the prgram aborts
*
* Description:
* This function checks the cuda error code, and aborts if it is not a
* success.
*/
inline void gpuAssert(cudaError_t code, char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n",cudaGetErrorString(code),file,line);
if (abort) exit(code);
}
}
/*
* Kernel - readcmp
*
* Arguments:
* a - a pointer to one base
* b - a pointer to the other base
*
* Description:
* TODO...
*/
__global__ void readcmp(char *a, char *b, /*char *result,*/ unsigned long nthreads, unsigned int str_len, unsigned int vicinity, unsigned int tstride, char *reduce, unsigned int pop_thresh, unsigned int threads_per_block) {
extern __shared__ char shared_data[];
char* sdata = (char *)shared_data;
char* result = (char *)&shared_data[threads_per_block];
// Find index of this thread
unsigned long x = threadIdx.x + blockIdx.x * blockDim.x;
unsigned long y = threadIdx.y + blockIdx.y * blockDim.y;
unsigned long tid = x + y * blockDim.x * gridDim.x;
unsigned long i = threadIdx.x; //local block tid
int j, k;
while(tid < nthreads) {
result[i] = a[tid+PAD_AMT] ^ b[tid+PAD_AMT];
__syncthreads();
if (result[i]!=0) {
for (j=1; j<vicinity; j++) {
if(result[i+j]!=0)
break;
}
if (result[i+j]!=0) {
for (k=1; k<j; k++) {
result[i+k]=0xff;
}
}
}
sdata[i] = a[tid+PAD_AMT] ^ b[tid+PAD_AMT-1];
__syncthreads();
if (sdata[i] != 0) {
for (j=1; j<vicinity; j++) {
if(sdata[i+j]!=0)
break;
}
if (sdata[i+j]!=0) {
for (k=1; k<j; k++) {
sdata[i+k]=0xff;
}
}
}
__syncthreads();
result[i] = result[i] && sdata[i];
sdata[i] = b[tid+PAD_AMT] ^ a[tid+PAD_AMT-1];
__syncthreads();
if (sdata[i]!=0) {
for (j=1; j<vicinity; j++) {
if(sdata[i+j]!=0)
break;
}
if (sdata[i+j]!=0) {
for (k=1; k<j; k++) {
sdata[i+k]=0xff;
}
}
}
__syncthreads();
result[i] = result[i] && sdata[i];
__syncthreads();
/////////////////////////////////////////////////////////////////////
//sdata[tid] = g_idata[i];
sdata[i] = result[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s=str_len/2; s>0; s >>= 1){
//if (tid<s) {
if(i < s) {
//sdata[tid] += sdata[tid + s];
sdata[i] += sdata[i + s];
}
__syncthreads();
}
__syncthreads();
// write result for this block to global mem
//if (tid%str_len == 0) {
if(i%str_len == 0) {
//g_odata[i/str_len] = (sdata[tid]<=pop_thresh)?1:0;
reduce[tid/str_len] = (sdata[i]<=pop_thresh)?0:1;
//reduce[tid/str_len] = sdata[i];
}
///////////////////////////////////////////////////////////////////////
__syncthreads();
tid += tstride;
}
}
__global__ void reduce(char *g_idata, char *g_odata, unsigned long nthreads, unsigned int str_len, unsigned int pop_thresh, unsigned int tstride) {
extern __shared__ char sdata[];
// each thread loads one element from global to shared mem
unsigned long x = threadIdx.x + blockIdx.x * blockDim.x;
unsigned long y = threadIdx.y + blockIdx.y * blockDim.y;
unsigned long i = x + y * blockDim.x * gridDim.x; //global tid
unsigned int tid = threadIdx.x; //local block tid
while(i < nthreads) {
sdata[tid] = g_idata[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s=str_len/2; s>0; s >>= 1){
if (tid<s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
// write result for this block to global mem
if (tid%str_len == 0) {
//g_odata[i/str_len] = (sdata[tid]<=pop_thresh)?1:0;
g_odata[i/str_len] = sdata[tid];
}
i += tstride;
}
}
/*
* Function - main
*
* Arguments:
* argc - the number of command line arguments
* argv - an array of the command line arguments
*
* Outputs:
* int - 0 if success, 1 if failure
*
* Description:
* TODO...
*/
int main(int argc, char *argv[]) {
/* check the number of command line arguments */
if(argc != 7) {
usage();
return 1;
}
print_device_info();
/* get arguments */
char* file_1;
char* file_2;
unsigned int num_genomes, genome_len, buffed_len,
buffer_len, vicinity, errors, pop_thresh;
FILE *pop_count_file;
file_1 = argv[1];
file_2 = argv[2];
num_genomes = atoi(argv[3]);
genome_len = atoi(argv[4]);
errors = atoi(argv[5]);
vicinity = atoi(argv[6]);
/* calculate important values */
pop_thresh = (vicinity-1)*(errors-1) + errors; //popcount threshold
buffed_len = next_power_2(genome_len); //genome length + buffer space
buffer_len = buffed_len - genome_len; //difference bw genome len and buf len
unsigned long num_chars = num_genomes*buffed_len;
/* initialize and allocate strings to compare */
char* genome_1_data; //first genome data
char* genome_2_data; //second genome data
//char* result_data; //xor result data
char* reduce_data; //sum of "errors" in each string
if(init_data_pad(&genome_1_data, num_chars)) return 1;
if(init_data_pad(&genome_2_data, num_chars)) return 1;
//if(init_data(&result_data, num_chars)) return 1;
if(init_data(&reduce_data, num_genomes)) return 1;
/* read in the data */
if(read_data(genome_1_data, file_1, num_genomes, genome_len, buffer_len, buffed_len, vicinity+1)) return 1;
if(read_data(genome_2_data, file_2, num_genomes, genome_len, buffer_len, buffed_len, vicinity+1)) return 1;
/* create timing events */
//clock_t start_c, end_c;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
/* initialize and allocate memoer for GPU input and output arrays */
char *dev_genome_1_data;
char *dev_genome_2_data;
//char *dev_result_data;
char *dev_reduce_data;
gpuErrchk( cudaMalloc((void**)&dev_genome_1_data, (num_chars+PAD_AMT)*sizeof(char)));
gpuErrchk( cudaMalloc((void**)&dev_genome_2_data, (num_chars+PAD_AMT)*sizeof(char)));
//gpuErrchk( cudaMalloc((void**)&dev_result_data, num_chars*sizeof(char) ));
gpuErrchk( cudaMalloc((void**)&dev_reduce_data, num_genomes*sizeof(char) ));
/* set start time */
cudaEventRecord(start, 0);
//start_c = clock(); //begin timing computation
/* copy data to GPU */
gpuErrchk(cudaMemcpy( dev_genome_1_data, genome_1_data,
(num_chars+PAD_AMT)*sizeof(char), cudaMemcpyHostToDevice ));
gpuErrchk(cudaMemcpy( dev_genome_2_data, genome_2_data,
(num_chars+PAD_AMT)*sizeof(char), cudaMemcpyHostToDevice ));
/* figure out thread count and dimensions for GPU */
unsigned int num_blocks_x = 128;
unsigned int num_blocks_y = 128;
unsigned int threads_per_block = buffed_len;
unsigned int tstride = threads_per_block*num_blocks_x*num_blocks_y;
dim3 grid_size(num_blocks_x, num_blocks_y, 1);
unsigned int log_len = log_2(buffed_len); //TODO: do we need this??
/*printf("Number of threads per block: %d\n", threads_per_block);
printf("Grid Dim X: %d\n", num_blocks_x);
printf("Grid Dim Y:: %d\n", num_blocks_y);
printf("num_chars: %lu\n", num_chars);*/
/* set start time */
//cudaEventRecord(start,0);
//start_c = clock(); //begin timing computation
/******************/
/** START TIMING **/
/******************/
/*========================================================================*/
/* create and run GPU threads */
readcmp<<<grid_size,threads_per_block,2*threads_per_block>>>(dev_genome_1_data,
dev_genome_2_data,/* dev_result_data,*/ num_chars, buffed_len, vicinity,
tstride, dev_reduce_data, pop_thresh, threads_per_block);
gpuErrchk(cudaThreadSynchronize());
//reduce<<<grid_size,threads_per_block,threads_per_block>>>(dev_result_data, dev_reduce_data, num_chars, buffed_len, pop_thresh, tstride);
//gpuErrchk(cudaThreadSynchronize());
/*========================================================================*/
/****************/
/** END TIMING **/
/****************/
/* set stop time */
//cudaEventRecord(stop,0);
//cudaEventSynchronize( stop );
//end_c = clock(); //end timing computation
gpuErrchk(cudaMemcpy( reduce_data, dev_reduce_data,
num_genomes*sizeof(char), cudaMemcpyDeviceToHost ));
//gpuErrchk(cudaMemcpy( result_data, dev_result_data,
// num_chars*sizeof(char), cudaMemcpyDeviceToHost ));
//printf("\n---------------------------------------------------------------\n");
/*for(unsigned int i = 0; i < num_chars; i ++) {
if (result_data[i]!=0)
printf("%d: %c %c %d\n", i, genome_1_data[i+5], genome_2_data[i+5], (result_data[i] != 0)?1:0);
}*/
//for(unsigned int i = 128000000-128; i < 128000000; i ++) {
// if(i % 128 == 0) {
// printf("pop count:\t%d\n", reduce_data[i/128]);
// }
// printf("%d:\t%c %c --- %d %d %d\n",
// i, genome_1_data[i+5], genome_2_data[i+5],
// ((genome_1_data[i+5] ^ genome_2_data[i+5]) == 0) ? 0:1,
// ((genome_1_data[i+5] ^ genome_2_data[i+5-1]) == 0) ? 0:1,
// ((genome_1_data[i+5-1] ^ genome_2_data[i+5]) == 0) ? 0:1/*,
// result_data[i]*/);
//}
cudaEventRecord(stop,0);
cudaEventSynchronize( stop );
//end_c = clock(); //end timing computation
/* calculate elapsed time for GPU computation */
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
printf("Time to complete comparison %1.4f ms\n", elapsedTime);
//printf("Total time of computation: %f\n", (end_c-start_c)/(double)CLOCKS_PER_SEC);
/* print out result_data to check */
/*for (int i = 0; i < num_chars; i++) {
printf("%d",*(result_data+i));
printf("\n");
}
printf("\n");*/
/* print out reduce_data to check */
/*for (int i = 0; i < 2100; i++) {
printf("%d",*(reduce_data+i));
printf("\n");
}*/
// Writing output pop count to file
// for data collection purposes
unsigned int matches=0;
for (unsigned int q=0; q<num_genomes; q++) {
if (reduce_data[q]==0)
matches++;
}
pop_count_file = fopen("pop_output.txt","w");
fprintf(pop_count_file, "%d %d\n", matches, num_genomes-matches);
/* free and destroy all allocated information */
cudaFree(dev_genome_1_data);
cudaFree(dev_genome_2_data);
//cudaFree(dev_result_data);
cudaFree(dev_reduce_data);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaFreeHost(genome_1_data);
cudaFreeHost(genome_2_data);
//cudaFreeHost(result_data);
cudaFreeHost(reduce_data);
//free(genome_1_data);
//free(genome_2_data);
//free(result_data);
//free(reduce_data);
}
/*
* Function - usage
*
* Description:
* Just prints the usage invariant for this program.
*/
void usage(void) {
printf("\nUsage:\n");
printf("\t./a.out <file_1> <file_2> <num_genomes> <genome_len> <errors> <vicinity>\n\n");
}
/*
* Function - init_data
*
* Arguments:
* data - the array in which to place data
* num_chars - the number of chars to allocate
*
* Outputs:
* int - 0 if success, 1 if failure
*
* Description:
* This function initializes a data array. Pretty simple to follow.
*/
int init_data(char** data, unsigned int num_chars) {
/* allocate pointers for the genome strings */
//*data = (char*)malloc(num_chars * sizeof(char));
cudaHostAlloc((void**)data,num_chars*sizeof(char),cudaHostAllocDefault);
if(NULL == *data) {
printf("init_data - malloc failed\n");
return 1;
}
return 0; //SUCCESS
}
/*
* Function - init_data_pad TODO
*
* Arguments:
* data - the array in which to place data
* num_chars - the number of chars to allocate
*
* Outputs:
* int - 0 if success, 1 if failure
*
* Description:
* This function initializes a data array. Pretty simple to follow.
*/
int init_data_pad(char** data, unsigned int num_chars) {
/* allocate pointers for the genome strings */
//*data = (char*)malloc((num_chars + PAD_AMT) * sizeof(char));
cudaHostAlloc((void**)data,(num_chars+PAD_AMT)*sizeof(char),cudaHostAllocDefault);
if(NULL == *data) {
printf("init_data - malloc failed\n");
return 1;
}
return 0; //SUCCESS
}
/*
* Function - read_data
*
* Arguments:
* data - the char* to which the data will be written
* file - the filae that contains the genomes we care about
* num_genomes - the numebr of genomed to read
* genome_len - the length of the genomes
* buffer_len - the length of the buffer at the end of each genome
* buffed_len - length of genome + buffer
*
* Outputs:
* int - 0 if success, 1 if failure
*
* Description:
* This function reads in all of the genome data from the given genome
* file. Each line contains a genome read, and this is read into each
* string.
*/
int read_data(char* data, char* file, unsigned int num_genomes,
unsigned int genome_len, unsigned int buffer_len,
unsigned int buffed_len,unsigned int vicinity) {
/* basic info and variables */
FILE* ifp; //ifp: "in file pointer"
char* mode = "r";
/* open the file */
ifp = fopen(file, mode);
if(NULL == ifp) {
printf("Can't open input file %s!\n", file);
return 1;
}
/* create read in buffer */
char* buf = (char*)malloc((genome_len+2)*sizeof(char));
/* initialize the padding at beginning of array */
for(int i = 0; i < PAD_AMT; i++) {
*(data + i) = BUFFER_CHAR;
}
int limit_len;
/* calculate the limit to which we will read data */
if (buffer_len < vicinity)
limit_len = buffed_len - vicinity;
else
limit_len = genome_len;
/* read in the file */
for(int i = 0; i < num_genomes; i++) {
//printf("%d\n",i);
if(NULL != fgets(buf, genome_len + 2, ifp)) {
for(int j = 0; j < limit_len; j++) {
*(data + PAD_AMT + i*buffed_len + j) = buf[j];
}
for(int j = 0; j < buffed_len-limit_len; j++) {
*(data + PAD_AMT + i*buffed_len + limit_len + j) = BUFFER_CHAR;
}
//buf[genome_len] = '\0';
//printf("%s\n", buf);
}
else {
printf("Failed to read from the file\n");
return 1;
}
}
/* close the file */
fclose(ifp);
free(buf);
return 0; //SUCCESS
}
/*
* Function - print_device_info
*
* Description:
* Prints valuable information out regarding the CUDA-capable devices
* in this system.
*/
void print_device_info(void) {
cudaDeviceProp prop;
int count;
cudaGetDeviceCount( &count );
for (int i=0; i< count; i++) {
cudaGetDeviceProperties( &prop, i );
printf( " --- General Information for device %d ---\n", i );
printf( "Name: %s\n", prop.name );
printf( "Compute capability: %d.%d\n", prop.major, prop.minor );
printf( "Clock rate: %d\n", prop.clockRate );
printf( "Device copy overlap: " );
if (prop.deviceOverlap)
printf( "Enabled\n" );
else
printf( "Disabled\n" );
printf( "Kernel execition timeout : " );
if (prop.kernelExecTimeoutEnabled)
printf( "Enabled\n" );
else
printf( "Disabled\n" );
printf( " --- Memory Information for device %d ---\n", i );
printf( "Total global mem: %ld\n", prop.totalGlobalMem );
printf( "Total constant Mem: %ld\n", prop.totalConstMem );
printf( "Max mem pitch: %ld\n", prop.memPitch );
printf( "Texture Alignment: %ld\n", prop.textureAlignment );
printf( " --- MP Information for device %d ---\n", i );
printf( "Multiprocessor count: %d\n", prop.multiProcessorCount );
printf( "Shared mem per mp: %ld\n", prop.sharedMemPerBlock );
printf( "Registers per mp: %d\n", prop.regsPerBlock );
printf( "Threads in warp: %d\n", prop.warpSize );
printf( "Max threads per block: %d\n", prop.maxThreadsPerBlock );
printf( "Max thread dimensions: (%d, %d, %d)\n",
prop.maxThreadsDim[0], prop.maxThreadsDim[1],
prop.maxThreadsDim[2] );
printf( "Max grid dimensions: (%d, %d, %d)\n",
prop.maxGridSize[0], prop.maxGridSize[1],
prop.maxGridSize[2] );
printf( "\n" );
}
}
/*
* Function - next_power_2
*
* Arguments:
* v - the value for which we want to find the next power of 2
*
* Outputs:
* unsigned int - the next power of 2 greater than v
*
* Description:
* This code basically rounds v up to the next highest power of 2. So if
* v was 2, this function would return 2. If v was 15, this function would
* return 16. Etcetera.
*
* Source:
* http://graphics.stanford.edu/~seander/bithacks.html
*/
unsigned int next_power_2(unsigned int v) {
v--;
v |= v >> 1;
v |= v >> 2;
v |= v >> 4;
v |= v >> 8;
v |= v >> 16;
v++;
return v;
}
unsigned int log_2(unsigned int v) {
unsigned int r=0;
while (v >>= 1) // unroll for more speed...
{
r++;
}
return r;
} | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <string.h>
#include <hip/hip_runtime.h>
/*********************************/
/** constants/define statements **/
/*********************************/
#define THREADS_PER_BLOCK 1024
#define MAX_BLOCKS 65535
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
#define BUFFER_CHAR 'A'
#define PAD_AMT 5
/**********************/
/** function headers **/
/**********************/
void usage(void);
int init_data(char** data, unsigned int num_chars);
int init_data_pad(char** data, unsigned int num_chars);
int read_data(char* data, char* file, unsigned int num_genomes,
unsigned int genome_len, unsigned int buffer_len,
unsigned int buffed_len, unsigned int vicinity);
void free_data(char* data, unsigned int num_genomes);
__global__ void readcmp(char* a, char* b, /*char* result,*/
unsigned long nthreads, unsigned int str_len,
unsigned int vicinity, unsigned int tstride,
char *reduce, unsigned int pop_thresh, unsigned int threads_per_block);
__global__ void reduce(char *g_idata, char *g_odata, unsigned long nthreads,
unsigned int str_len, unsigned int pop_thresh,
unsigned int tstride);
void print_device_info(void);
unsigned int next_power_2(unsigned int v);
unsigned int log_2(unsigned int v);
/***************/
/** functions **/
/***************/
/*
* Function - gpuAssert
*
* Inputs:
* code - gpu error code
* file - current source file
* line - line within this file
* abort - if true, the prgram aborts
*
* Description:
* This function checks the cuda error code, and aborts if it is not a
* success.
*/
inline void gpuAssert(hipError_t code, char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n",hipGetErrorString(code),file,line);
if (abort) exit(code);
}
}
/*
* Kernel - readcmp
*
* Arguments:
* a - a pointer to one base
* b - a pointer to the other base
*
* Description:
* TODO...
*/
__global__ void readcmp(char *a, char *b, /*char *result,*/ unsigned long nthreads, unsigned int str_len, unsigned int vicinity, unsigned int tstride, char *reduce, unsigned int pop_thresh, unsigned int threads_per_block) {
extern __shared__ char shared_data[];
char* sdata = (char *)shared_data;
char* result = (char *)&shared_data[threads_per_block];
// Find index of this thread
unsigned long x = threadIdx.x + blockIdx.x * blockDim.x;
unsigned long y = threadIdx.y + blockIdx.y * blockDim.y;
unsigned long tid = x + y * blockDim.x * gridDim.x;
unsigned long i = threadIdx.x; //local block tid
int j, k;
while(tid < nthreads) {
result[i] = a[tid+PAD_AMT] ^ b[tid+PAD_AMT];
__syncthreads();
if (result[i]!=0) {
for (j=1; j<vicinity; j++) {
if(result[i+j]!=0)
break;
}
if (result[i+j]!=0) {
for (k=1; k<j; k++) {
result[i+k]=0xff;
}
}
}
sdata[i] = a[tid+PAD_AMT] ^ b[tid+PAD_AMT-1];
__syncthreads();
if (sdata[i] != 0) {
for (j=1; j<vicinity; j++) {
if(sdata[i+j]!=0)
break;
}
if (sdata[i+j]!=0) {
for (k=1; k<j; k++) {
sdata[i+k]=0xff;
}
}
}
__syncthreads();
result[i] = result[i] && sdata[i];
sdata[i] = b[tid+PAD_AMT] ^ a[tid+PAD_AMT-1];
__syncthreads();
if (sdata[i]!=0) {
for (j=1; j<vicinity; j++) {
if(sdata[i+j]!=0)
break;
}
if (sdata[i+j]!=0) {
for (k=1; k<j; k++) {
sdata[i+k]=0xff;
}
}
}
__syncthreads();
result[i] = result[i] && sdata[i];
__syncthreads();
/////////////////////////////////////////////////////////////////////
//sdata[tid] = g_idata[i];
sdata[i] = result[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s=str_len/2; s>0; s >>= 1){
//if (tid<s) {
if(i < s) {
//sdata[tid] += sdata[tid + s];
sdata[i] += sdata[i + s];
}
__syncthreads();
}
__syncthreads();
// write result for this block to global mem
//if (tid%str_len == 0) {
if(i%str_len == 0) {
//g_odata[i/str_len] = (sdata[tid]<=pop_thresh)?1:0;
reduce[tid/str_len] = (sdata[i]<=pop_thresh)?0:1;
//reduce[tid/str_len] = sdata[i];
}
///////////////////////////////////////////////////////////////////////
__syncthreads();
tid += tstride;
}
}
__global__ void reduce(char *g_idata, char *g_odata, unsigned long nthreads, unsigned int str_len, unsigned int pop_thresh, unsigned int tstride) {
extern __shared__ char sdata[];
// each thread loads one element from global to shared mem
unsigned long x = threadIdx.x + blockIdx.x * blockDim.x;
unsigned long y = threadIdx.y + blockIdx.y * blockDim.y;
unsigned long i = x + y * blockDim.x * gridDim.x; //global tid
unsigned int tid = threadIdx.x; //local block tid
while(i < nthreads) {
sdata[tid] = g_idata[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s=str_len/2; s>0; s >>= 1){
if (tid<s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
// write result for this block to global mem
if (tid%str_len == 0) {
//g_odata[i/str_len] = (sdata[tid]<=pop_thresh)?1:0;
g_odata[i/str_len] = sdata[tid];
}
i += tstride;
}
}
/*
* Function - main
*
* Arguments:
* argc - the number of command line arguments
* argv - an array of the command line arguments
*
* Outputs:
* int - 0 if success, 1 if failure
*
* Description:
* TODO...
*/
int main(int argc, char *argv[]) {
/* check the number of command line arguments */
if(argc != 7) {
usage();
return 1;
}
print_device_info();
/* get arguments */
char* file_1;
char* file_2;
unsigned int num_genomes, genome_len, buffed_len,
buffer_len, vicinity, errors, pop_thresh;
FILE *pop_count_file;
file_1 = argv[1];
file_2 = argv[2];
num_genomes = atoi(argv[3]);
genome_len = atoi(argv[4]);
errors = atoi(argv[5]);
vicinity = atoi(argv[6]);
/* calculate important values */
pop_thresh = (vicinity-1)*(errors-1) + errors; //popcount threshold
buffed_len = next_power_2(genome_len); //genome length + buffer space
buffer_len = buffed_len - genome_len; //difference bw genome len and buf len
unsigned long num_chars = num_genomes*buffed_len;
/* initialize and allocate strings to compare */
char* genome_1_data; //first genome data
char* genome_2_data; //second genome data
//char* result_data; //xor result data
char* reduce_data; //sum of "errors" in each string
if(init_data_pad(&genome_1_data, num_chars)) return 1;
if(init_data_pad(&genome_2_data, num_chars)) return 1;
//if(init_data(&result_data, num_chars)) return 1;
if(init_data(&reduce_data, num_genomes)) return 1;
/* read in the data */
if(read_data(genome_1_data, file_1, num_genomes, genome_len, buffer_len, buffed_len, vicinity+1)) return 1;
if(read_data(genome_2_data, file_2, num_genomes, genome_len, buffer_len, buffed_len, vicinity+1)) return 1;
/* create timing events */
//clock_t start_c, end_c;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
/* initialize and allocate memoer for GPU input and output arrays */
char *dev_genome_1_data;
char *dev_genome_2_data;
//char *dev_result_data;
char *dev_reduce_data;
gpuErrchk( hipMalloc((void**)&dev_genome_1_data, (num_chars+PAD_AMT)*sizeof(char)));
gpuErrchk( hipMalloc((void**)&dev_genome_2_data, (num_chars+PAD_AMT)*sizeof(char)));
//gpuErrchk( cudaMalloc((void**)&dev_result_data, num_chars*sizeof(char) ));
gpuErrchk( hipMalloc((void**)&dev_reduce_data, num_genomes*sizeof(char) ));
/* set start time */
hipEventRecord(start, 0);
//start_c = clock(); //begin timing computation
/* copy data to GPU */
gpuErrchk(hipMemcpy( dev_genome_1_data, genome_1_data,
(num_chars+PAD_AMT)*sizeof(char), hipMemcpyHostToDevice ));
gpuErrchk(hipMemcpy( dev_genome_2_data, genome_2_data,
(num_chars+PAD_AMT)*sizeof(char), hipMemcpyHostToDevice ));
/* figure out thread count and dimensions for GPU */
unsigned int num_blocks_x = 128;
unsigned int num_blocks_y = 128;
unsigned int threads_per_block = buffed_len;
unsigned int tstride = threads_per_block*num_blocks_x*num_blocks_y;
dim3 grid_size(num_blocks_x, num_blocks_y, 1);
unsigned int log_len = log_2(buffed_len); //TODO: do we need this??
/*printf("Number of threads per block: %d\n", threads_per_block);
printf("Grid Dim X: %d\n", num_blocks_x);
printf("Grid Dim Y:: %d\n", num_blocks_y);
printf("num_chars: %lu\n", num_chars);*/
/* set start time */
//cudaEventRecord(start,0);
//start_c = clock(); //begin timing computation
/******************/
/** START TIMING **/
/******************/
/*========================================================================*/
/* create and run GPU threads */
readcmp<<<grid_size,threads_per_block,2*threads_per_block>>>(dev_genome_1_data,
dev_genome_2_data,/* dev_result_data,*/ num_chars, buffed_len, vicinity,
tstride, dev_reduce_data, pop_thresh, threads_per_block);
gpuErrchk(hipDeviceSynchronize());
//reduce<<<grid_size,threads_per_block,threads_per_block>>>(dev_result_data, dev_reduce_data, num_chars, buffed_len, pop_thresh, tstride);
//gpuErrchk(cudaThreadSynchronize());
/*========================================================================*/
/****************/
/** END TIMING **/
/****************/
/* set stop time */
//cudaEventRecord(stop,0);
//cudaEventSynchronize( stop );
//end_c = clock(); //end timing computation
gpuErrchk(hipMemcpy( reduce_data, dev_reduce_data,
num_genomes*sizeof(char), hipMemcpyDeviceToHost ));
//gpuErrchk(cudaMemcpy( result_data, dev_result_data,
// num_chars*sizeof(char), cudaMemcpyDeviceToHost ));
//printf("\n---------------------------------------------------------------\n");
/*for(unsigned int i = 0; i < num_chars; i ++) {
if (result_data[i]!=0)
printf("%d: %c %c %d\n", i, genome_1_data[i+5], genome_2_data[i+5], (result_data[i] != 0)?1:0);
}*/
//for(unsigned int i = 128000000-128; i < 128000000; i ++) {
// if(i % 128 == 0) {
// printf("pop count:\t%d\n", reduce_data[i/128]);
// }
// printf("%d:\t%c %c --- %d %d %d\n",
// i, genome_1_data[i+5], genome_2_data[i+5],
// ((genome_1_data[i+5] ^ genome_2_data[i+5]) == 0) ? 0:1,
// ((genome_1_data[i+5] ^ genome_2_data[i+5-1]) == 0) ? 0:1,
// ((genome_1_data[i+5-1] ^ genome_2_data[i+5]) == 0) ? 0:1/*,
// result_data[i]*/);
//}
hipEventRecord(stop,0);
hipEventSynchronize( stop );
//end_c = clock(); //end timing computation
/* calculate elapsed time for GPU computation */
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
printf("Time to complete comparison %1.4f ms\n", elapsedTime);
//printf("Total time of computation: %f\n", (end_c-start_c)/(double)CLOCKS_PER_SEC);
/* print out result_data to check */
/*for (int i = 0; i < num_chars; i++) {
printf("%d",*(result_data+i));
printf("\n");
}
printf("\n");*/
/* print out reduce_data to check */
/*for (int i = 0; i < 2100; i++) {
printf("%d",*(reduce_data+i));
printf("\n");
}*/
// Writing output pop count to file
// for data collection purposes
unsigned int matches=0;
for (unsigned int q=0; q<num_genomes; q++) {
if (reduce_data[q]==0)
matches++;
}
pop_count_file = fopen("pop_output.txt","w");
fprintf(pop_count_file, "%d %d\n", matches, num_genomes-matches);
/* free and destroy all allocated information */
hipFree(dev_genome_1_data);
hipFree(dev_genome_2_data);
//cudaFree(dev_result_data);
hipFree(dev_reduce_data);
hipEventDestroy(start);
hipEventDestroy(stop);
hipHostFree(genome_1_data);
hipHostFree(genome_2_data);
//cudaFreeHost(result_data);
hipHostFree(reduce_data);
//free(genome_1_data);
//free(genome_2_data);
//free(result_data);
//free(reduce_data);
}
/*
* Function - usage
*
* Description:
* Just prints the usage invariant for this program.
*/
void usage(void) {
printf("\nUsage:\n");
printf("\t./a.out <file_1> <file_2> <num_genomes> <genome_len> <errors> <vicinity>\n\n");
}
/*
* Function - init_data
*
* Arguments:
* data - the array in which to place data
* num_chars - the number of chars to allocate
*
* Outputs:
* int - 0 if success, 1 if failure
*
* Description:
* This function initializes a data array. Pretty simple to follow.
*/
int init_data(char** data, unsigned int num_chars) {
/* allocate pointers for the genome strings */
//*data = (char*)malloc(num_chars * sizeof(char));
hipHostAlloc((void**)data,num_chars*sizeof(char),hipHostMallocDefault);
if(NULL == *data) {
printf("init_data - malloc failed\n");
return 1;
}
return 0; //SUCCESS
}
/*
* Function - init_data_pad TODO
*
* Arguments:
* data - the array in which to place data
* num_chars - the number of chars to allocate
*
* Outputs:
* int - 0 if success, 1 if failure
*
* Description:
* This function initializes a data array. Pretty simple to follow.
*/
int init_data_pad(char** data, unsigned int num_chars) {
/* allocate pointers for the genome strings */
//*data = (char*)malloc((num_chars + PAD_AMT) * sizeof(char));
hipHostAlloc((void**)data,(num_chars+PAD_AMT)*sizeof(char),hipHostMallocDefault);
if(NULL == *data) {
printf("init_data - malloc failed\n");
return 1;
}
return 0; //SUCCESS
}
/*
* Function - read_data
*
* Arguments:
* data - the char* to which the data will be written
* file - the filae that contains the genomes we care about
* num_genomes - the numebr of genomed to read
* genome_len - the length of the genomes
* buffer_len - the length of the buffer at the end of each genome
* buffed_len - length of genome + buffer
*
* Outputs:
* int - 0 if success, 1 if failure
*
* Description:
* This function reads in all of the genome data from the given genome
* file. Each line contains a genome read, and this is read into each
* string.
*/
int read_data(char* data, char* file, unsigned int num_genomes,
unsigned int genome_len, unsigned int buffer_len,
unsigned int buffed_len,unsigned int vicinity) {
/* basic info and variables */
FILE* ifp; //ifp: "in file pointer"
char* mode = "r";
/* open the file */
ifp = fopen(file, mode);
if(NULL == ifp) {
printf("Can't open input file %s!\n", file);
return 1;
}
/* create read in buffer */
char* buf = (char*)malloc((genome_len+2)*sizeof(char));
/* initialize the padding at beginning of array */
for(int i = 0; i < PAD_AMT; i++) {
*(data + i) = BUFFER_CHAR;
}
int limit_len;
/* calculate the limit to which we will read data */
if (buffer_len < vicinity)
limit_len = buffed_len - vicinity;
else
limit_len = genome_len;
/* read in the file */
for(int i = 0; i < num_genomes; i++) {
//printf("%d\n",i);
if(NULL != fgets(buf, genome_len + 2, ifp)) {
for(int j = 0; j < limit_len; j++) {
*(data + PAD_AMT + i*buffed_len + j) = buf[j];
}
for(int j = 0; j < buffed_len-limit_len; j++) {
*(data + PAD_AMT + i*buffed_len + limit_len + j) = BUFFER_CHAR;
}
//buf[genome_len] = '\0';
//printf("%s\n", buf);
}
else {
printf("Failed to read from the file\n");
return 1;
}
}
/* close the file */
fclose(ifp);
free(buf);
return 0; //SUCCESS
}
/*
* Function - print_device_info
*
* Description:
* Prints valuable information out regarding the CUDA-capable devices
* in this system.
*/
void print_device_info(void) {
hipDeviceProp_t prop;
int count;
hipGetDeviceCount( &count );
for (int i=0; i< count; i++) {
hipGetDeviceProperties( &prop, i );
printf( " --- General Information for device %d ---\n", i );
printf( "Name: %s\n", prop.name );
printf( "Compute capability: %d.%d\n", prop.major, prop.minor );
printf( "Clock rate: %d\n", prop.clockRate );
printf( "Device copy overlap: " );
if (prop.deviceOverlap)
printf( "Enabled\n" );
else
printf( "Disabled\n" );
printf( "Kernel execition timeout : " );
if (prop.kernelExecTimeoutEnabled)
printf( "Enabled\n" );
else
printf( "Disabled\n" );
printf( " --- Memory Information for device %d ---\n", i );
printf( "Total global mem: %ld\n", prop.totalGlobalMem );
printf( "Total constant Mem: %ld\n", prop.totalConstMem );
printf( "Max mem pitch: %ld\n", prop.memPitch );
printf( "Texture Alignment: %ld\n", prop.textureAlignment );
printf( " --- MP Information for device %d ---\n", i );
printf( "Multiprocessor count: %d\n", prop.multiProcessorCount );
printf( "Shared mem per mp: %ld\n", prop.sharedMemPerBlock );
printf( "Registers per mp: %d\n", prop.regsPerBlock );
printf( "Threads in warp: %d\n", prop.warpSize );
printf( "Max threads per block: %d\n", prop.maxThreadsPerBlock );
printf( "Max thread dimensions: (%d, %d, %d)\n",
prop.maxThreadsDim[0], prop.maxThreadsDim[1],
prop.maxThreadsDim[2] );
printf( "Max grid dimensions: (%d, %d, %d)\n",
prop.maxGridSize[0], prop.maxGridSize[1],
prop.maxGridSize[2] );
printf( "\n" );
}
}
/*
* Function - next_power_2
*
* Arguments:
* v - the value for which we want to find the next power of 2
*
* Outputs:
* unsigned int - the next power of 2 greater than v
*
* Description:
* This code basically rounds v up to the next highest power of 2. So if
* v was 2, this function would return 2. If v was 15, this function would
* return 16. Etcetera.
*
* Source:
* http://graphics.stanford.edu/~seander/bithacks.html
*/
unsigned int next_power_2(unsigned int v) {
v--;
v |= v >> 1;
v |= v >> 2;
v |= v >> 4;
v |= v >> 8;
v |= v >> 16;
v++;
return v;
}
unsigned int log_2(unsigned int v) {
unsigned int r=0;
while (v >>= 1) // unroll for more speed...
{
r++;
}
return r;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <string.h>
#include <hip/hip_runtime.h>
/*********************************/
/** constants/define statements **/
/*********************************/
#define THREADS_PER_BLOCK 1024
#define MAX_BLOCKS 65535
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
#define BUFFER_CHAR 'A'
#define PAD_AMT 5
/**********************/
/** function headers **/
/**********************/
void usage(void);
int init_data(char** data, unsigned int num_chars);
int init_data_pad(char** data, unsigned int num_chars);
int read_data(char* data, char* file, unsigned int num_genomes,
unsigned int genome_len, unsigned int buffer_len,
unsigned int buffed_len, unsigned int vicinity);
void free_data(char* data, unsigned int num_genomes);
__global__ void readcmp(char* a, char* b, /*char* result,*/
unsigned long nthreads, unsigned int str_len,
unsigned int vicinity, unsigned int tstride,
char *reduce, unsigned int pop_thresh, unsigned int threads_per_block);
__global__ void reduce(char *g_idata, char *g_odata, unsigned long nthreads,
unsigned int str_len, unsigned int pop_thresh,
unsigned int tstride);
void print_device_info(void);
unsigned int next_power_2(unsigned int v);
unsigned int log_2(unsigned int v);
/***************/
/** functions **/
/***************/
/*
* Function - gpuAssert
*
* Inputs:
* code - gpu error code
* file - current source file
* line - line within this file
* abort - if true, the prgram aborts
*
* Description:
* This function checks the cuda error code, and aborts if it is not a
* success.
*/
inline void gpuAssert(hipError_t code, char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n",hipGetErrorString(code),file,line);
if (abort) exit(code);
}
}
/*
* Kernel - readcmp
*
* Arguments:
* a - a pointer to one base
* b - a pointer to the other base
*
* Description:
* TODO...
*/
__global__ void readcmp(char *a, char *b, /*char *result,*/ unsigned long nthreads, unsigned int str_len, unsigned int vicinity, unsigned int tstride, char *reduce, unsigned int pop_thresh, unsigned int threads_per_block) {
extern __shared__ char shared_data[];
char* sdata = (char *)shared_data;
char* result = (char *)&shared_data[threads_per_block];
// Find index of this thread
unsigned long x = threadIdx.x + blockIdx.x * blockDim.x;
unsigned long y = threadIdx.y + blockIdx.y * blockDim.y;
unsigned long tid = x + y * blockDim.x * gridDim.x;
unsigned long i = threadIdx.x; //local block tid
int j, k;
while(tid < nthreads) {
result[i] = a[tid+PAD_AMT] ^ b[tid+PAD_AMT];
__syncthreads();
if (result[i]!=0) {
for (j=1; j<vicinity; j++) {
if(result[i+j]!=0)
break;
}
if (result[i+j]!=0) {
for (k=1; k<j; k++) {
result[i+k]=0xff;
}
}
}
sdata[i] = a[tid+PAD_AMT] ^ b[tid+PAD_AMT-1];
__syncthreads();
if (sdata[i] != 0) {
for (j=1; j<vicinity; j++) {
if(sdata[i+j]!=0)
break;
}
if (sdata[i+j]!=0) {
for (k=1; k<j; k++) {
sdata[i+k]=0xff;
}
}
}
__syncthreads();
result[i] = result[i] && sdata[i];
sdata[i] = b[tid+PAD_AMT] ^ a[tid+PAD_AMT-1];
__syncthreads();
if (sdata[i]!=0) {
for (j=1; j<vicinity; j++) {
if(sdata[i+j]!=0)
break;
}
if (sdata[i+j]!=0) {
for (k=1; k<j; k++) {
sdata[i+k]=0xff;
}
}
}
__syncthreads();
result[i] = result[i] && sdata[i];
__syncthreads();
/////////////////////////////////////////////////////////////////////
//sdata[tid] = g_idata[i];
sdata[i] = result[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s=str_len/2; s>0; s >>= 1){
//if (tid<s) {
if(i < s) {
//sdata[tid] += sdata[tid + s];
sdata[i] += sdata[i + s];
}
__syncthreads();
}
__syncthreads();
// write result for this block to global mem
//if (tid%str_len == 0) {
if(i%str_len == 0) {
//g_odata[i/str_len] = (sdata[tid]<=pop_thresh)?1:0;
reduce[tid/str_len] = (sdata[i]<=pop_thresh)?0:1;
//reduce[tid/str_len] = sdata[i];
}
///////////////////////////////////////////////////////////////////////
__syncthreads();
tid += tstride;
}
}
__global__ void reduce(char *g_idata, char *g_odata, unsigned long nthreads, unsigned int str_len, unsigned int pop_thresh, unsigned int tstride) {
extern __shared__ char sdata[];
// each thread loads one element from global to shared mem
unsigned long x = threadIdx.x + blockIdx.x * blockDim.x;
unsigned long y = threadIdx.y + blockIdx.y * blockDim.y;
unsigned long i = x + y * blockDim.x * gridDim.x; //global tid
unsigned int tid = threadIdx.x; //local block tid
while(i < nthreads) {
sdata[tid] = g_idata[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s=str_len/2; s>0; s >>= 1){
if (tid<s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
// write result for this block to global mem
if (tid%str_len == 0) {
//g_odata[i/str_len] = (sdata[tid]<=pop_thresh)?1:0;
g_odata[i/str_len] = sdata[tid];
}
i += tstride;
}
}
/*
* Function - main
*
* Arguments:
* argc - the number of command line arguments
* argv - an array of the command line arguments
*
* Outputs:
* int - 0 if success, 1 if failure
*
* Description:
* TODO...
*/
int main(int argc, char *argv[]) {
/* check the number of command line arguments */
if(argc != 7) {
usage();
return 1;
}
print_device_info();
/* get arguments */
char* file_1;
char* file_2;
unsigned int num_genomes, genome_len, buffed_len,
buffer_len, vicinity, errors, pop_thresh;
FILE *pop_count_file;
file_1 = argv[1];
file_2 = argv[2];
num_genomes = atoi(argv[3]);
genome_len = atoi(argv[4]);
errors = atoi(argv[5]);
vicinity = atoi(argv[6]);
/* calculate important values */
pop_thresh = (vicinity-1)*(errors-1) + errors; //popcount threshold
buffed_len = next_power_2(genome_len); //genome length + buffer space
buffer_len = buffed_len - genome_len; //difference bw genome len and buf len
unsigned long num_chars = num_genomes*buffed_len;
/* initialize and allocate strings to compare */
char* genome_1_data; //first genome data
char* genome_2_data; //second genome data
//char* result_data; //xor result data
char* reduce_data; //sum of "errors" in each string
if(init_data_pad(&genome_1_data, num_chars)) return 1;
if(init_data_pad(&genome_2_data, num_chars)) return 1;
//if(init_data(&result_data, num_chars)) return 1;
if(init_data(&reduce_data, num_genomes)) return 1;
/* read in the data */
if(read_data(genome_1_data, file_1, num_genomes, genome_len, buffer_len, buffed_len, vicinity+1)) return 1;
if(read_data(genome_2_data, file_2, num_genomes, genome_len, buffer_len, buffed_len, vicinity+1)) return 1;
/* create timing events */
//clock_t start_c, end_c;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
/* initialize and allocate memoer for GPU input and output arrays */
char *dev_genome_1_data;
char *dev_genome_2_data;
//char *dev_result_data;
char *dev_reduce_data;
gpuErrchk( hipMalloc((void**)&dev_genome_1_data, (num_chars+PAD_AMT)*sizeof(char)));
gpuErrchk( hipMalloc((void**)&dev_genome_2_data, (num_chars+PAD_AMT)*sizeof(char)));
//gpuErrchk( cudaMalloc((void**)&dev_result_data, num_chars*sizeof(char) ));
gpuErrchk( hipMalloc((void**)&dev_reduce_data, num_genomes*sizeof(char) ));
/* set start time */
hipEventRecord(start, 0);
//start_c = clock(); //begin timing computation
/* copy data to GPU */
gpuErrchk(hipMemcpy( dev_genome_1_data, genome_1_data,
(num_chars+PAD_AMT)*sizeof(char), hipMemcpyHostToDevice ));
gpuErrchk(hipMemcpy( dev_genome_2_data, genome_2_data,
(num_chars+PAD_AMT)*sizeof(char), hipMemcpyHostToDevice ));
/* figure out thread count and dimensions for GPU */
unsigned int num_blocks_x = 128;
unsigned int num_blocks_y = 128;
unsigned int threads_per_block = buffed_len;
unsigned int tstride = threads_per_block*num_blocks_x*num_blocks_y;
dim3 grid_size(num_blocks_x, num_blocks_y, 1);
unsigned int log_len = log_2(buffed_len); //TODO: do we need this??
/*printf("Number of threads per block: %d\n", threads_per_block);
printf("Grid Dim X: %d\n", num_blocks_x);
printf("Grid Dim Y:: %d\n", num_blocks_y);
printf("num_chars: %lu\n", num_chars);*/
/* set start time */
//cudaEventRecord(start,0);
//start_c = clock(); //begin timing computation
/******************/
/** START TIMING **/
/******************/
/*========================================================================*/
/* create and run GPU threads */
readcmp<<<grid_size,threads_per_block,2*threads_per_block>>>(dev_genome_1_data,
dev_genome_2_data,/* dev_result_data,*/ num_chars, buffed_len, vicinity,
tstride, dev_reduce_data, pop_thresh, threads_per_block);
gpuErrchk(hipDeviceSynchronize());
//reduce<<<grid_size,threads_per_block,threads_per_block>>>(dev_result_data, dev_reduce_data, num_chars, buffed_len, pop_thresh, tstride);
//gpuErrchk(cudaThreadSynchronize());
/*========================================================================*/
/****************/
/** END TIMING **/
/****************/
/* set stop time */
//cudaEventRecord(stop,0);
//cudaEventSynchronize( stop );
//end_c = clock(); //end timing computation
gpuErrchk(hipMemcpy( reduce_data, dev_reduce_data,
num_genomes*sizeof(char), hipMemcpyDeviceToHost ));
//gpuErrchk(cudaMemcpy( result_data, dev_result_data,
// num_chars*sizeof(char), cudaMemcpyDeviceToHost ));
//printf("\n---------------------------------------------------------------\n");
/*for(unsigned int i = 0; i < num_chars; i ++) {
if (result_data[i]!=0)
printf("%d: %c %c %d\n", i, genome_1_data[i+5], genome_2_data[i+5], (result_data[i] != 0)?1:0);
}*/
//for(unsigned int i = 128000000-128; i < 128000000; i ++) {
// if(i % 128 == 0) {
// printf("pop count:\t%d\n", reduce_data[i/128]);
// }
// printf("%d:\t%c %c --- %d %d %d\n",
// i, genome_1_data[i+5], genome_2_data[i+5],
// ((genome_1_data[i+5] ^ genome_2_data[i+5]) == 0) ? 0:1,
// ((genome_1_data[i+5] ^ genome_2_data[i+5-1]) == 0) ? 0:1,
// ((genome_1_data[i+5-1] ^ genome_2_data[i+5]) == 0) ? 0:1/*,
// result_data[i]*/);
//}
hipEventRecord(stop,0);
hipEventSynchronize( stop );
//end_c = clock(); //end timing computation
/* calculate elapsed time for GPU computation */
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
printf("Time to complete comparison %1.4f ms\n", elapsedTime);
//printf("Total time of computation: %f\n", (end_c-start_c)/(double)CLOCKS_PER_SEC);
/* print out result_data to check */
/*for (int i = 0; i < num_chars; i++) {
printf("%d",*(result_data+i));
printf("\n");
}
printf("\n");*/
/* print out reduce_data to check */
/*for (int i = 0; i < 2100; i++) {
printf("%d",*(reduce_data+i));
printf("\n");
}*/
// Writing output pop count to file
// for data collection purposes
unsigned int matches=0;
for (unsigned int q=0; q<num_genomes; q++) {
if (reduce_data[q]==0)
matches++;
}
pop_count_file = fopen("pop_output.txt","w");
fprintf(pop_count_file, "%d %d\n", matches, num_genomes-matches);
/* free and destroy all allocated information */
hipFree(dev_genome_1_data);
hipFree(dev_genome_2_data);
//cudaFree(dev_result_data);
hipFree(dev_reduce_data);
hipEventDestroy(start);
hipEventDestroy(stop);
hipHostFree(genome_1_data);
hipHostFree(genome_2_data);
//cudaFreeHost(result_data);
hipHostFree(reduce_data);
//free(genome_1_data);
//free(genome_2_data);
//free(result_data);
//free(reduce_data);
}
/*
* Function - usage
*
* Description:
* Just prints the usage invariant for this program.
*/
void usage(void) {
printf("\nUsage:\n");
printf("\t./a.out <file_1> <file_2> <num_genomes> <genome_len> <errors> <vicinity>\n\n");
}
/*
* Function - init_data
*
* Arguments:
* data - the array in which to place data
* num_chars - the number of chars to allocate
*
* Outputs:
* int - 0 if success, 1 if failure
*
* Description:
* This function initializes a data array. Pretty simple to follow.
*/
int init_data(char** data, unsigned int num_chars) {
/* allocate pointers for the genome strings */
//*data = (char*)malloc(num_chars * sizeof(char));
hipHostAlloc((void**)data,num_chars*sizeof(char),hipHostMallocDefault);
if(NULL == *data) {
printf("init_data - malloc failed\n");
return 1;
}
return 0; //SUCCESS
}
/*
* Function - init_data_pad TODO
*
* Arguments:
* data - the array in which to place data
* num_chars - the number of chars to allocate
*
* Outputs:
* int - 0 if success, 1 if failure
*
* Description:
* This function initializes a data array. Pretty simple to follow.
*/
int init_data_pad(char** data, unsigned int num_chars) {
/* allocate pointers for the genome strings */
//*data = (char*)malloc((num_chars + PAD_AMT) * sizeof(char));
hipHostAlloc((void**)data,(num_chars+PAD_AMT)*sizeof(char),hipHostMallocDefault);
if(NULL == *data) {
printf("init_data - malloc failed\n");
return 1;
}
return 0; //SUCCESS
}
/*
* Function - read_data
*
* Arguments:
* data - the char* to which the data will be written
* file - the filae that contains the genomes we care about
* num_genomes - the numebr of genomed to read
* genome_len - the length of the genomes
* buffer_len - the length of the buffer at the end of each genome
* buffed_len - length of genome + buffer
*
* Outputs:
* int - 0 if success, 1 if failure
*
* Description:
* This function reads in all of the genome data from the given genome
* file. Each line contains a genome read, and this is read into each
* string.
*/
int read_data(char* data, char* file, unsigned int num_genomes,
unsigned int genome_len, unsigned int buffer_len,
unsigned int buffed_len,unsigned int vicinity) {
/* basic info and variables */
FILE* ifp; //ifp: "in file pointer"
char* mode = "r";
/* open the file */
ifp = fopen(file, mode);
if(NULL == ifp) {
printf("Can't open input file %s!\n", file);
return 1;
}
/* create read in buffer */
char* buf = (char*)malloc((genome_len+2)*sizeof(char));
/* initialize the padding at beginning of array */
for(int i = 0; i < PAD_AMT; i++) {
*(data + i) = BUFFER_CHAR;
}
int limit_len;
/* calculate the limit to which we will read data */
if (buffer_len < vicinity)
limit_len = buffed_len - vicinity;
else
limit_len = genome_len;
/* read in the file */
for(int i = 0; i < num_genomes; i++) {
//printf("%d\n",i);
if(NULL != fgets(buf, genome_len + 2, ifp)) {
for(int j = 0; j < limit_len; j++) {
*(data + PAD_AMT + i*buffed_len + j) = buf[j];
}
for(int j = 0; j < buffed_len-limit_len; j++) {
*(data + PAD_AMT + i*buffed_len + limit_len + j) = BUFFER_CHAR;
}
//buf[genome_len] = '\0';
//printf("%s\n", buf);
}
else {
printf("Failed to read from the file\n");
return 1;
}
}
/* close the file */
fclose(ifp);
free(buf);
return 0; //SUCCESS
}
/*
* Function - print_device_info
*
* Description:
* Prints valuable information out regarding the CUDA-capable devices
* in this system.
*/
void print_device_info(void) {
hipDeviceProp_t prop;
int count;
hipGetDeviceCount( &count );
for (int i=0; i< count; i++) {
hipGetDeviceProperties( &prop, i );
printf( " --- General Information for device %d ---\n", i );
printf( "Name: %s\n", prop.name );
printf( "Compute capability: %d.%d\n", prop.major, prop.minor );
printf( "Clock rate: %d\n", prop.clockRate );
printf( "Device copy overlap: " );
if (prop.deviceOverlap)
printf( "Enabled\n" );
else
printf( "Disabled\n" );
printf( "Kernel execition timeout : " );
if (prop.kernelExecTimeoutEnabled)
printf( "Enabled\n" );
else
printf( "Disabled\n" );
printf( " --- Memory Information for device %d ---\n", i );
printf( "Total global mem: %ld\n", prop.totalGlobalMem );
printf( "Total constant Mem: %ld\n", prop.totalConstMem );
printf( "Max mem pitch: %ld\n", prop.memPitch );
printf( "Texture Alignment: %ld\n", prop.textureAlignment );
printf( " --- MP Information for device %d ---\n", i );
printf( "Multiprocessor count: %d\n", prop.multiProcessorCount );
printf( "Shared mem per mp: %ld\n", prop.sharedMemPerBlock );
printf( "Registers per mp: %d\n", prop.regsPerBlock );
printf( "Threads in warp: %d\n", prop.warpSize );
printf( "Max threads per block: %d\n", prop.maxThreadsPerBlock );
printf( "Max thread dimensions: (%d, %d, %d)\n",
prop.maxThreadsDim[0], prop.maxThreadsDim[1],
prop.maxThreadsDim[2] );
printf( "Max grid dimensions: (%d, %d, %d)\n",
prop.maxGridSize[0], prop.maxGridSize[1],
prop.maxGridSize[2] );
printf( "\n" );
}
}
/*
* Function - next_power_2
*
* Arguments:
* v - the value for which we want to find the next power of 2
*
* Outputs:
* unsigned int - the next power of 2 greater than v
*
* Description:
* This code basically rounds v up to the next highest power of 2. So if
* v was 2, this function would return 2. If v was 15, this function would
* return 16. Etcetera.
*
* Source:
* http://graphics.stanford.edu/~seander/bithacks.html
*/
unsigned int next_power_2(unsigned int v) {
v--;
v |= v >> 1;
v |= v >> 2;
v |= v >> 4;
v |= v >> 8;
v |= v >> 16;
v++;
return v;
}
unsigned int log_2(unsigned int v) {
unsigned int r=0;
while (v >>= 1) // unroll for more speed...
{
r++;
}
return r;
} | .text
.file "introCUDA_injection_taylor.hip"
.globl _Z22__device_stub__readcmpPcS_mjjjS_jj # -- Begin function _Z22__device_stub__readcmpPcS_mjjjS_jj
.p2align 4, 0x90
.type _Z22__device_stub__readcmpPcS_mjjjS_jj,@function
_Z22__device_stub__readcmpPcS_mjjjS_jj: # @_Z22__device_stub__readcmpPcS_mjjjS_jj
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7readcmpPcS_mjjjS_jj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z22__device_stub__readcmpPcS_mjjjS_jj, .Lfunc_end0-_Z22__device_stub__readcmpPcS_mjjjS_jj
.cfi_endproc
# -- End function
.globl _Z21__device_stub__reducePcS_mjjj # -- Begin function _Z21__device_stub__reducePcS_mjjj
.p2align 4, 0x90
.type _Z21__device_stub__reducePcS_mjjj,@function
_Z21__device_stub__reducePcS_mjjj: # @_Z21__device_stub__reducePcS_mjjj
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6reducePcS_mjjj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z21__device_stub__reducePcS_mjjj, .Lfunc_end1-_Z21__device_stub__reducePcS_mjjj
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $7, %edi
jne .LBB2_1
# %bb.2:
movq %rsi, %r12
callq _Z17print_device_infov
movq 8(%r12), %rax
movq %rax, 56(%rsp) # 8-byte Spill
movq 16(%r12), %rax
movq %rax, 128(%rsp) # 8-byte Spill
movq 24(%r12), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbp
movq 32(%r12), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 40(%r12), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 120(%rsp) # 8-byte Spill
movq 48(%r12), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
leal -1(%r14), %eax
movl %eax, %ecx
shrl %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $2, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $4, %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $8, %eax
orl %ecx, %eax
movl %eax, %r12d
shrl $16, %r12d
orl %eax, %r12d
incl %r12d
movl %r12d, %r13d
imull %ebp, %r13d
leal 5(%r13), %ebx
leaq 48(%rsp), %rdi
movq %rbx, %rsi
xorl %edx, %edx
callq hipHostAlloc
cmpq $0, 48(%rsp)
je .LBB2_3
# %bb.5: # %.critedge
leaq 40(%rsp), %rdi
movq %rbx, %rsi
xorl %edx, %edx
callq hipHostAlloc
cmpq $0, 40(%rsp)
je .LBB2_3
# %bb.6: # %.critedge84
movl %ebp, %ebx
leaq 32(%rsp), %rdi
movq %rbx, %rsi
xorl %edx, %edx
callq hipHostAlloc
cmpq $0, 32(%rsp)
je .LBB2_3
# %bb.7: # %.critedge85
movq %rbx, 112(%rsp) # 8-byte Spill
movl %r12d, %ebx
subl %r14d, %ebx
movq 48(%rsp), %rdi
movq %rbp, %rdx
leal 1(%r15), %ebp
movl %ebp, (%rsp)
movq 56(%rsp), %rsi # 8-byte Reload
movq %rdx, 56(%rsp) # 8-byte Spill
# kill: def $edx killed $edx killed $rdx
movl %r14d, %ecx
movl %ebx, %r8d
movl %r12d, %r9d
callq _Z9read_dataPcS_jjjjj
movl %eax, %ecx
movl $1, %eax
testl %ecx, %ecx
jne .LBB2_15
# %bb.8:
movq %r15, 104(%rsp) # 8-byte Spill
movq 40(%rsp), %rdi
movl %ebp, (%rsp)
movq 128(%rsp), %rsi # 8-byte Reload
movq 56(%rsp), %r15 # 8-byte Reload
movl %r15d, %edx
movl %r14d, %ecx
movl %ebx, %r8d
movl %r12d, %r9d
callq _Z9read_dataPcS_jjjjj
movl %eax, %ecx
movl $1, %eax
testl %ecx, %ecx
jne .LBB2_15
# %bb.9: # %_Z5log_2j.exit
movq %r15, %rbx
leaq 88(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 5(%r13), %r14
leaq 80(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movl $.L.str, %esi
movl %eax, %edi
movl $277, %edx # imm = 0x115
movl $1, %ecx
callq _Z9gpuAssert10hipError_tPcib
leaq 72(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movl $.L.str, %esi
movl %eax, %edi
movl $278, %edx # imm = 0x116
movl $1, %ecx
callq _Z9gpuAssert10hipError_tPcib
leaq 64(%rsp), %rdi
movq 112(%rsp), %r15 # 8-byte Reload
movq %r15, %rsi
callq hipMalloc
movl $.L.str, %esi
movl %eax, %edi
movl $280, %edx # imm = 0x118
movl $1, %ecx
callq _Z9gpuAssert10hipError_tPcib
movq 88(%rsp), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
callq hipEventRecord
movq 80(%rsp), %rdi
movq 48(%rsp), %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl $.L.str, %esi
movl %eax, %edi
movl $288, %edx # imm = 0x120
movl $1, %ecx
callq _Z9gpuAssert10hipError_tPcib
movq 72(%rsp), %rdi
movq 40(%rsp), %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl $.L.str, %esi
movl %eax, %edi
movl $290, %edx # imm = 0x122
movl $1, %ecx
callq _Z9gpuAssert10hipError_tPcib
leal (%r12,%r12), %r8d
movl %r12d, %eax
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rax, %rdx
movabsq $549755814016, %rdi # imm = 0x8000000080
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_11
# %bb.10:
movq 104(%rsp), %r8 # 8-byte Reload
leal -1(%r8), %eax
movq 120(%rsp), %rdx # 8-byte Reload
leal -1(%rdx), %ecx
imull %eax, %ecx
addl %edx, %ecx
movl %r12d, %r9d
shll $14, %r9d
movq 80(%rsp), %rdi
movq 72(%rsp), %rsi
movq 64(%rsp), %rax
movl %r12d, 16(%rsp)
movl %ecx, 8(%rsp)
movq %rax, (%rsp)
movq %r13, %rdx
movl %r12d, %ecx
# kill: def $r8d killed $r8d killed $r8
callq _Z22__device_stub__readcmpPcS_mjjjS_jj
.LBB2_11:
callq hipDeviceSynchronize
movl $.L.str, %esi
movl %eax, %edi
movl $321, %edx # imm = 0x141
movl $1, %ecx
callq _Z9gpuAssert10hipError_tPcib
movq 32(%rsp), %rdi
movq 64(%rsp), %rsi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.L.str, %esi
movl %eax, %edi
movl $338, %edx # imm = 0x152
movl $1, %ecx
callq _Z9gpuAssert10hipError_tPcib
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 88(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 100(%rsp), %rdi
callq hipEventElapsedTime
movss 100(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
testl %ebx, %ebx
je .LBB2_14
# %bb.12: # %.lr.ph
movq 32(%rsp), %rax
movl %ebx, %ecx
xorl %edx, %edx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_13: # =>This Inner Loop Header: Depth=1
cmpb $1, (%rax,%rdx)
adcl $0, %ebp
incq %rdx
cmpq %rdx, %rcx
jne .LBB2_13
.LBB2_14: # %._crit_edge
movl $.L.str.2, %edi
movl $.L.str.3, %esi
callq fopen
movq %rbx, %rcx
subl %ebp, %ecx
movl $.L.str.4, %esi
movq %rax, %rdi
movl %ebp, %edx
# kill: def $ecx killed $ecx killed $rcx
xorl %eax, %eax
callq fprintf
movq 80(%rsp), %rdi
callq hipFree
movq 72(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
movq 88(%rsp), %rdi
callq hipEventDestroy
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 48(%rsp), %rdi
callq hipHostFree
movq 40(%rsp), %rdi
callq hipHostFree
movq 32(%rsp), %rdi
callq hipHostFree
xorl %eax, %eax
jmp .LBB2_15
.LBB2_1:
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.1, %edi
jmp .LBB2_4
.LBB2_3: # %_Z13init_data_padPPcj.exit
movl $.Lstr.7, %edi
.LBB2_4:
callq puts@PLT
movl $1, %eax
.LBB2_15:
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.globl _Z5usagev # -- Begin function _Z5usagev
.p2align 4, 0x90
.type _Z5usagev,@function
_Z5usagev: # @_Z5usagev
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.1, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end3:
.size _Z5usagev, .Lfunc_end3-_Z5usagev
.cfi_endproc
# -- End function
.globl _Z17print_device_infov # -- Begin function _Z17print_device_infov
.p2align 4, 0x90
.type _Z17print_device_infov,@function
_Z17print_device_infov: # @_Z17print_device_infov
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 12(%rsp)
jle .LBB4_3
# %bb.1: # %.lr.ph
leaq 16(%rsp), %rbx
movl $.Lstr.4, %r14d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB4_2: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.11, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl $.L.str.12, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 376(%rsp), %esi
movl 380(%rsp), %edx
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
movl 364(%rsp), %esi
movl $.L.str.14, %edi
xorl %eax, %eax
callq printf
movl $.L.str.15, %edi
xorl %eax, %eax
callq printf
cmpl $0, 400(%rsp)
movl $.Lstr.5, %edi
cmoveq %r14, %rdi
callq puts@PLT
movl $.L.str.18, %edi
xorl %eax, %eax
callq printf
cmpl $0, 408(%rsp)
movl $.Lstr.5, %edi
cmoveq %r14, %rdi
callq puts@PLT
movl $.L.str.19, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movq 304(%rsp), %rsi
movl $.L.str.20, %edi
xorl %eax, %eax
callq printf
movq 368(%rsp), %rsi
movl $.L.str.21, %edi
xorl %eax, %eax
callq printf
movq 328(%rsp), %rsi
movl $.L.str.22, %edi
xorl %eax, %eax
callq printf
movq 384(%rsp), %rsi
movl $.L.str.23, %edi
xorl %eax, %eax
callq printf
movl $.L.str.24, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl 404(%rsp), %esi
movl $.L.str.25, %edi
xorl %eax, %eax
callq printf
movq 312(%rsp), %rsi
movl $.L.str.26, %edi
xorl %eax, %eax
callq printf
movl 320(%rsp), %esi
movl $.L.str.27, %edi
xorl %eax, %eax
callq printf
movl 324(%rsp), %esi
movl $.L.str.28, %edi
xorl %eax, %eax
callq printf
movl 336(%rsp), %esi
movl $.L.str.29, %edi
xorl %eax, %eax
callq printf
movl 340(%rsp), %esi
movl 344(%rsp), %edx
movl 348(%rsp), %ecx
movl $.L.str.30, %edi
xorl %eax, %eax
callq printf
movl 352(%rsp), %esi
movl 356(%rsp), %edx
movl 360(%rsp), %ecx
movl $.L.str.31, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl 12(%rsp), %ebp
jl .LBB4_2
.LBB4_3: # %._crit_edge
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z17print_device_infov, .Lfunc_end4-_Z17print_device_infov
.cfi_endproc
# -- End function
.globl _Z12next_power_2j # -- Begin function _Z12next_power_2j
.p2align 4, 0x90
.type _Z12next_power_2j,@function
_Z12next_power_2j: # @_Z12next_power_2j
.cfi_startproc
# %bb.0:
# kill: def $edi killed $edi def $rdi
leal -1(%rdi), %eax
movl %eax, %ecx
shrl %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $2, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $4, %ecx
orl %eax, %ecx
movl %ecx, %edx
shrl $8, %edx
orl %ecx, %edx
movl %edx, %eax
shrl $16, %eax
orl %edx, %eax
incl %eax
retq
.Lfunc_end5:
.size _Z12next_power_2j, .Lfunc_end5-_Z12next_power_2j
.cfi_endproc
# -- End function
.globl _Z13init_data_padPPcj # -- Begin function _Z13init_data_padPPcj
.p2align 4, 0x90
.type _Z13init_data_padPPcj,@function
_Z13init_data_padPPcj: # @_Z13init_data_padPPcj
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
# kill: def $esi killed $esi def $rsi
movq %rdi, %r14
addl $5, %esi
xorl %ebx, %ebx
xorl %edx, %edx
callq hipHostAlloc
cmpq $0, (%r14)
jne .LBB6_2
# %bb.1:
movl $.Lstr.7, %edi
callq puts@PLT
movl $1, %ebx
.LBB6_2:
movl %ebx, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z13init_data_padPPcj, .Lfunc_end6-_Z13init_data_padPPcj
.cfi_endproc
# -- End function
.globl _Z9init_dataPPcj # -- Begin function _Z9init_dataPPcj
.p2align 4, 0x90
.type _Z9init_dataPPcj,@function
_Z9init_dataPPcj: # @_Z9init_dataPPcj
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %r14
movl %esi, %esi
xorl %ebx, %ebx
xorl %edx, %edx
callq hipHostAlloc
cmpq $0, (%r14)
jne .LBB7_2
# %bb.1:
movl $.Lstr.7, %edi
callq puts@PLT
movl $1, %ebx
.LBB7_2:
movl %ebx, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _Z9init_dataPPcj, .Lfunc_end7-_Z9init_dataPPcj
.cfi_endproc
# -- End function
.globl _Z9read_dataPcS_jjjjj # -- Begin function _Z9read_dataPcS_jjjjj
.p2align 4, 0x90
.type _Z9read_dataPcS_jjjjj,@function
_Z9read_dataPcS_jjjjj: # @_Z9read_dataPcS_jjjjj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %ebx
movl %r8d, %r15d
movl %ecx, %r14d
movl %edx, %ebp
movq %rsi, %r13
movq %rdi, %r12
movl $.L.str.8, %esi
movq %r13, %rdi
callq fopen
movq %rax, (%rsp) # 8-byte Spill
testq %rax, %rax
je .LBB8_10
# %bb.1:
leal 2(%r14), %edi
movq %rdi, 32(%rsp) # 8-byte Spill
callq malloc
movq %rax, %r13
movl $1094795585, (%r12) # imm = 0x41414141
movb $65, 4(%r12)
testl %ebp, %ebp
je .LBB8_9
# %bb.2: # %.lr.ph58
movq %r12, %rdx
movl 96(%rsp), %eax
movl %ebx, %ecx
subl %eax, %ecx
cmpl %eax, %r15d
cmovbl %ecx, %r14d
movslq %r14d, %rax
leaq (%r12,%rax), %rcx
addq $5, %rcx
movq %rcx, 8(%rsp) # 8-byte Spill
addq $5, %rdx
movq %rdx, 24(%rsp) # 8-byte Spill
notl %eax
addl %ebx, %eax
incq %rax
movq %rax, 16(%rsp) # 8-byte Spill
movl %ebp, %ebp
xorl %r12d, %r12d
jmp .LBB8_4
.p2align 4, 0x90
.LBB8_3: # %._crit_edge
# in Loop: Header=BB8_4 Depth=1
addl %ebx, %r12d
decq %rbp
je .LBB8_9
.LBB8_4: # =>This Inner Loop Header: Depth=1
movq %r13, %rdi
movq 32(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
movq (%rsp), %rdx # 8-byte Reload
callq fgets
testq %rax, %rax
je .LBB8_11
# %bb.5: # %.preheader50
# in Loop: Header=BB8_4 Depth=1
movl %r12d, %r15d
testl %r14d, %r14d
jle .LBB8_7
# %bb.6: # %.lr.ph
# in Loop: Header=BB8_4 Depth=1
movq 24(%rsp), %rax # 8-byte Reload
leaq (%rax,%r15), %rdi
movq %r13, %rsi
movq %r14, %rdx
callq memcpy@PLT
.LBB8_7: # %.preheader
# in Loop: Header=BB8_4 Depth=1
cmpl %ebx, %r14d
je .LBB8_3
# %bb.8: # %.lr.ph54
# in Loop: Header=BB8_4 Depth=1
addq 8(%rsp), %r15 # 8-byte Folded Reload
movq %r15, %rdi
movl $65, %esi
movq 16(%rsp), %rdx # 8-byte Reload
callq memset@PLT
jmp .LBB8_3
.LBB8_9: # %.critedge
movq (%rsp), %rdi # 8-byte Reload
callq fclose
movq %r13, %rdi
callq free
xorl %eax, %eax
jmp .LBB8_13
.LBB8_10:
movl $.L.str.9, %edi
movq %r13, %rsi
xorl %eax, %eax
callq printf
jmp .LBB8_12
.LBB8_11:
movl $.Lstr.8, %edi
callq puts@PLT
.LBB8_12:
movl $1, %eax
.LBB8_13:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size _Z9read_dataPcS_jjjjj, .Lfunc_end8-_Z9read_dataPcS_jjjjj
.cfi_endproc
# -- End function
.section .text._Z9gpuAssert10hipError_tPcib,"axG",@progbits,_Z9gpuAssert10hipError_tPcib,comdat
.weak _Z9gpuAssert10hipError_tPcib # -- Begin function _Z9gpuAssert10hipError_tPcib
.p2align 4, 0x90
.type _Z9gpuAssert10hipError_tPcib,@function
_Z9gpuAssert10hipError_tPcib: # @_Z9gpuAssert10hipError_tPcib
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
testl %edi, %edi
jne .LBB9_1
.LBB9_2:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB9_1:
.cfi_def_cfa_offset 48
movq stderr(%rip), %r14
movl %edi, %ebx
movl %ecx, %r12d
movl %edx, %ebp
movq %rsi, %r15
callq hipGetErrorString
movl $.L.str.33, %esi
movq %r14, %rdi
movq %rax, %rdx
movq %r15, %rcx
movl %ebp, %r8d
xorl %eax, %eax
callq fprintf
testb %r12b, %r12b
je .LBB9_2
# %bb.3:
movl %ebx, %edi
callq exit
.Lfunc_end9:
.size _Z9gpuAssert10hipError_tPcib, .Lfunc_end9-_Z9gpuAssert10hipError_tPcib
.cfi_endproc
# -- End function
.text
.globl _Z5log_2j # -- Begin function _Z5log_2j
.p2align 4, 0x90
.type _Z5log_2j,@function
_Z5log_2j: # @_Z5log_2j
.cfi_startproc
# %bb.0:
xorl %eax, %eax
cmpl $2, %edi
jb .LBB10_3
# %bb.1: # %.lr.ph.preheader
xorl %eax, %eax
movl %edi, %ecx
.p2align 4, 0x90
.LBB10_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
shrl %ecx
incl %eax
cmpl $3, %edi
movl %ecx, %edi
ja .LBB10_2
.LBB10_3: # %._crit_edge
retq
.Lfunc_end10:
.size _Z5log_2j, .Lfunc_end10-_Z5log_2j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB11_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB11_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7readcmpPcS_mjjjS_jj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6reducePcS_mjjj, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end11:
.size __hip_module_ctor, .Lfunc_end11-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB12_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB12_2:
retq
.Lfunc_end12:
.size __hip_module_dtor, .Lfunc_end12-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7readcmpPcS_mjjjS_jj,@object # @_Z7readcmpPcS_mjjjS_jj
.section .rodata,"a",@progbits
.globl _Z7readcmpPcS_mjjjS_jj
.p2align 3, 0x0
_Z7readcmpPcS_mjjjS_jj:
.quad _Z22__device_stub__readcmpPcS_mjjjS_jj
.size _Z7readcmpPcS_mjjjS_jj, 8
.type _Z6reducePcS_mjjj,@object # @_Z6reducePcS_mjjj
.globl _Z6reducePcS_mjjj
.p2align 3, 0x0
_Z6reducePcS_mjjj:
.quad _Z21__device_stub__reducePcS_mjjj
.size _Z6reducePcS_mjjj, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/xhongyi/toybrick/master/cuda/introCUDA_injection_taylor.hip"
.size .L.str, 117
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Time to complete comparison %1.4f ms\n"
.size .L.str.1, 38
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "pop_output.txt"
.size .L.str.2, 15
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "w"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d %d\n"
.size .L.str.4, 7
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "r"
.size .L.str.8, 2
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Can't open input file %s!\n"
.size .L.str.9, 27
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz " --- General Information for device %d ---\n"
.size .L.str.11, 44
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Name: %s\n"
.size .L.str.12, 10
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Compute capability: %d.%d\n"
.size .L.str.13, 27
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Clock rate: %d\n"
.size .L.str.14, 16
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Device copy overlap: "
.size .L.str.15, 22
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "Kernel execition timeout : "
.size .L.str.18, 28
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz " --- Memory Information for device %d ---\n"
.size .L.str.19, 45
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "Total global mem: %ld\n"
.size .L.str.20, 24
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "Total constant Mem: %ld\n"
.size .L.str.21, 26
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "Max mem pitch: %ld\n"
.size .L.str.22, 21
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz "Texture Alignment: %ld\n"
.size .L.str.23, 25
.type .L.str.24,@object # @.str.24
.L.str.24:
.asciz " --- MP Information for device %d ---\n"
.size .L.str.24, 41
.type .L.str.25,@object # @.str.25
.L.str.25:
.asciz "Multiprocessor count: %d\n"
.size .L.str.25, 27
.type .L.str.26,@object # @.str.26
.L.str.26:
.asciz "Shared mem per mp: %ld\n"
.size .L.str.26, 25
.type .L.str.27,@object # @.str.27
.L.str.27:
.asciz "Registers per mp: %d\n"
.size .L.str.27, 23
.type .L.str.28,@object # @.str.28
.L.str.28:
.asciz "Threads in warp: %d\n"
.size .L.str.28, 22
.type .L.str.29,@object # @.str.29
.L.str.29:
.asciz "Max threads per block: %d\n"
.size .L.str.29, 28
.type .L.str.30,@object # @.str.30
.L.str.30:
.asciz "Max thread dimensions: (%d, %d, %d)\n"
.size .L.str.30, 38
.type .L.str.31,@object # @.str.31
.L.str.31:
.asciz "Max grid dimensions: (%d, %d, %d)\n"
.size .L.str.31, 36
.type .L.str.33,@object # @.str.33
.L.str.33:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.33, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7readcmpPcS_mjjjS_jj"
.size .L__unnamed_1, 23
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z6reducePcS_mjjj"
.size .L__unnamed_2, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nUsage:"
.size .Lstr, 8
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\t./a.out <file_1> <file_2> <num_genomes> <genome_len> <errors> <vicinity>\n"
.size .Lstr.1, 75
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Disabled"
.size .Lstr.4, 9
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "Enabled"
.size .Lstr.5, 8
.type .Lstr.7,@object # @str.7
.Lstr.7:
.asciz "init_data - malloc failed"
.size .Lstr.7, 26
.type .Lstr.8,@object # @str.8
.Lstr.8:
.asciz "Failed to read from the file"
.size .Lstr.8, 29
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__readcmpPcS_mjjjS_jj
.addrsig_sym _Z21__device_stub__reducePcS_mjjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7readcmpPcS_mjjjS_jj
.addrsig_sym _Z6reducePcS_mjjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void splitNodes(int* octree, int* numNodes, int poolSize, int startNode) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
//Don't do anything if its out of bounds
if (index < poolSize) {
int node = octree[2 * (index+startNode)];
//Split the node if its flagged
if (node & 0x40000000) {
//Get a new node tile
int newNode = atomicAdd(numNodes, 8);
//Point this node at the new tile
octree[2 * (index+startNode)] = (octree[2 * (index+startNode)] & 0xC0000000) | (newNode & 0x3FFFFFFF);
//Initialize new child nodes to 0's
for (int off = 0; off < 8; off++) {
octree[2 * (newNode + off)] = 0;
octree[2 * (newNode + off) + 1] = 0;
}
}
}
} | code for sm_80
Function : _Z10splitNodesPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R0, R0, c[0x0][0x174], RZ ; /* 0x00005d0000007a10 */
/* 0x000fe20007ffe0ff */
/*0070*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0090*/ SHF.L.U32 R0, R0, 0x1, RZ ; /* 0x0000000100007819 */
/* 0x000fca00000006ff */
/*00a0*/ IMAD.WIDE R2, R0, R13, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e020d */
/*00b0*/ LDG.E.U8 R0, [R2.64+0x3] ; /* 0x0000030402007981 */
/* 0x000ea4000c1e1100 */
/*00c0*/ LOP3.LUT P0, RZ, R0, 0x40, RZ, 0xc0, !PT ; /* 0x0000004000ff7812 */
/* 0x004fda000780c0ff */
/*00d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00e0*/ S2R R5, SR_LANEID ; /* 0x0000000000057919 */
/* 0x000e220000000000 */
/*00f0*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe200038e0100 */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0110*/ FLO.U32 R8, UR6 ; /* 0x0000000600087d00 */
/* 0x000e3000080e0000 */
/*0120*/ POPC R0, UR6 ; /* 0x0000000600007d09 */
/* 0x000e620008000000 */
/*0130*/ ISETP.EQ.U32.AND P0, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x001fe20003f02070 */
/*0140*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*0150*/ SHF.L.U32 R11, R0, 0x3, RZ ; /* 0x00000003000b7819 */
/* 0x002fd600000006ff */
/*0160*/ @P0 ATOMG.E.ADD.STRONG.GPU PT, R5, [R4.64], R11 ; /* 0x0000000b040509a8 */
/* 0x000ea800081ee1c4 */
/*0170*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ee8000c1e1900 */
/*0180*/ S2R R7, SR_LTMASK ; /* 0x0000000000077919 */
/* 0x000e240000003900 */
/*0190*/ LOP3.LUT R10, R7, UR6, RZ, 0xc0, !PT ; /* 0x00000006070a7c12 */
/* 0x001fc8000f8ec0ff */
/*01a0*/ POPC R7, R10 ; /* 0x0000000a00077309 */
/* 0x000e220000000000 */
/*01b0*/ SHFL.IDX PT, R0, R5, R8, 0x1f ; /* 0x00001f0805007589 */
/* 0x004e2400000e0000 */
/*01c0*/ IMAD R0, R7, 0x8, R0 ; /* 0x0000000807007824 */
/* 0x001fe200078e0200 */
/*01d0*/ LOP3.LUT R7, R6, 0xc0000000, RZ, 0xc0, !PT ; /* 0xc000000006077812 */
/* 0x008fc800078ec0ff */
/*01e0*/ SHF.L.U32 R6, R0, 0x1, RZ ; /* 0x0000000100067819 */
/* 0x000fe400000006ff */
/*01f0*/ LOP3.LUT R9, R7, 0x3fffffff, R0, 0xf8, !PT ; /* 0x3fffffff07097812 */
/* 0x000fc600078ef800 */
/*0200*/ IMAD.WIDE R6, R6, R13, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe400078e020d */
/*0210*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*0220*/ STG.E [R6.64], RZ ; /* 0x000000ff06007986 */
/* 0x000fe8000c101904 */
/*0230*/ STG.E [R6.64+0x4], RZ ; /* 0x000004ff06007986 */
/* 0x000fe8000c101904 */
/*0240*/ STG.E [R6.64+0x8], RZ ; /* 0x000008ff06007986 */
/* 0x000fe8000c101904 */
/*0250*/ STG.E [R6.64+0xc], RZ ; /* 0x00000cff06007986 */
/* 0x000fe8000c101904 */
/*0260*/ STG.E [R6.64+0x10], RZ ; /* 0x000010ff06007986 */
/* 0x000fe8000c101904 */
/*0270*/ STG.E [R6.64+0x14], RZ ; /* 0x000014ff06007986 */
/* 0x000fe8000c101904 */
/*0280*/ STG.E [R6.64+0x18], RZ ; /* 0x000018ff06007986 */
/* 0x000fe8000c101904 */
/*0290*/ STG.E [R6.64+0x1c], RZ ; /* 0x00001cff06007986 */
/* 0x000fe8000c101904 */
/*02a0*/ STG.E [R6.64+0x20], RZ ; /* 0x000020ff06007986 */
/* 0x000fe8000c101904 */
/*02b0*/ STG.E [R6.64+0x24], RZ ; /* 0x000024ff06007986 */
/* 0x000fe8000c101904 */
/*02c0*/ STG.E [R6.64+0x28], RZ ; /* 0x000028ff06007986 */
/* 0x000fe8000c101904 */
/*02d0*/ STG.E [R6.64+0x2c], RZ ; /* 0x00002cff06007986 */
/* 0x000fe8000c101904 */
/*02e0*/ STG.E [R6.64+0x30], RZ ; /* 0x000030ff06007986 */
/* 0x000fe8000c101904 */
/*02f0*/ STG.E [R6.64+0x34], RZ ; /* 0x000034ff06007986 */
/* 0x000fe8000c101904 */
/*0300*/ STG.E [R6.64+0x38], RZ ; /* 0x000038ff06007986 */
/* 0x000fe8000c101904 */
/*0310*/ STG.E [R6.64+0x3c], RZ ; /* 0x00003cff06007986 */
/* 0x000fe2000c101904 */
/*0320*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0330*/ BRA 0x330; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void splitNodes(int* octree, int* numNodes, int poolSize, int startNode) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
//Don't do anything if its out of bounds
if (index < poolSize) {
int node = octree[2 * (index+startNode)];
//Split the node if its flagged
if (node & 0x40000000) {
//Get a new node tile
int newNode = atomicAdd(numNodes, 8);
//Point this node at the new tile
octree[2 * (index+startNode)] = (octree[2 * (index+startNode)] & 0xC0000000) | (newNode & 0x3FFFFFFF);
//Initialize new child nodes to 0's
for (int off = 0; off < 8; off++) {
octree[2 * (newNode + off)] = 0;
octree[2 * (newNode + off) + 1] = 0;
}
}
}
} | .file "tmpxft_0010969f_00000000-6_splitNodes.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z10splitNodesPiS_iiPiS_ii
.type _Z34__device_stub__Z10splitNodesPiS_iiPiS_ii, @function
_Z34__device_stub__Z10splitNodesPiS_iiPiS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10splitNodesPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z10splitNodesPiS_iiPiS_ii, .-_Z34__device_stub__Z10splitNodesPiS_iiPiS_ii
.globl _Z10splitNodesPiS_ii
.type _Z10splitNodesPiS_ii, @function
_Z10splitNodesPiS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10splitNodesPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10splitNodesPiS_ii, .-_Z10splitNodesPiS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10splitNodesPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10splitNodesPiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void splitNodes(int* octree, int* numNodes, int poolSize, int startNode) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
//Don't do anything if its out of bounds
if (index < poolSize) {
int node = octree[2 * (index+startNode)];
//Split the node if its flagged
if (node & 0x40000000) {
//Get a new node tile
int newNode = atomicAdd(numNodes, 8);
//Point this node at the new tile
octree[2 * (index+startNode)] = (octree[2 * (index+startNode)] & 0xC0000000) | (newNode & 0x3FFFFFFF);
//Initialize new child nodes to 0's
for (int off = 0; off < 8; off++) {
octree[2 * (newNode + off)] = 0;
octree[2 * (newNode + off) + 1] = 0;
}
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void splitNodes(int* octree, int* numNodes, int poolSize, int startNode) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
//Don't do anything if its out of bounds
if (index < poolSize) {
int node = octree[2 * (index+startNode)];
//Split the node if its flagged
if (node & 0x40000000) {
//Get a new node tile
int newNode = atomicAdd(numNodes, 8);
//Point this node at the new tile
octree[2 * (index+startNode)] = (octree[2 * (index+startNode)] & 0xC0000000) | (newNode & 0x3FFFFFFF);
//Initialize new child nodes to 0's
for (int off = 0; off < 8; off++) {
octree[2 * (newNode + off)] = 0;
octree[2 * (newNode + off) + 1] = 0;
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void splitNodes(int* octree, int* numNodes, int poolSize, int startNode) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
//Don't do anything if its out of bounds
if (index < poolSize) {
int node = octree[2 * (index+startNode)];
//Split the node if its flagged
if (node & 0x40000000) {
//Get a new node tile
int newNode = atomicAdd(numNodes, 8);
//Point this node at the new tile
octree[2 * (index+startNode)] = (octree[2 * (index+startNode)] & 0xC0000000) | (newNode & 0x3FFFFFFF);
//Initialize new child nodes to 0's
for (int off = 0; off < 8; off++) {
octree[2 * (newNode + off)] = 0;
octree[2 * (newNode + off) + 1] = 0;
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10splitNodesPiS_ii
.globl _Z10splitNodesPiS_ii
.p2align 8
.type _Z10splitNodesPiS_ii,@function
_Z10splitNodesPiS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b32 s4, s[0:1], 0x14
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_lshl_u32 v0, v1, s4, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v2, 2.0, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, 0, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_6
s_mov_b32 s6, exec_lo
s_mov_b32 s4, 0
v_mbcnt_lo_u32_b32 v2, s6, 0
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_4
s_load_b64 s[0:1], s[0:1], 0x8
s_bcnt1_i32_b32 s6, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b32 s6, s6, 3
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, s6
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v3, v3, v4, s[0:1] glc
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s5
global_load_b32 v4, v[0:1], off
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_lshl_add_u32 v3, v2, 3, s0
s_lshl_b32 s0, s0, 1
v_lshl_add_u32 v2, v2, 4, s0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2)
v_bfi_b32 v4, -2.0, v4, v3
v_mov_b32_e32 v3, 0
global_store_b32 v[0:1], v4, off
.p2align 6
.LBB0_5:
v_add_nc_u32_e32 v0, s4, v2
s_add_i32 s4, s4, 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s4, 16
v_add_nc_u32_e32 v4, 1, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_clause 0x1
global_store_b32 v[0:1], v3, off
global_store_b32 v[4:5], v3, off
s_cbranch_scc1 .LBB0_5
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10splitNodesPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10splitNodesPiS_ii, .Lfunc_end0-_Z10splitNodesPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10splitNodesPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10splitNodesPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void splitNodes(int* octree, int* numNodes, int poolSize, int startNode) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
//Don't do anything if its out of bounds
if (index < poolSize) {
int node = octree[2 * (index+startNode)];
//Split the node if its flagged
if (node & 0x40000000) {
//Get a new node tile
int newNode = atomicAdd(numNodes, 8);
//Point this node at the new tile
octree[2 * (index+startNode)] = (octree[2 * (index+startNode)] & 0xC0000000) | (newNode & 0x3FFFFFFF);
//Initialize new child nodes to 0's
for (int off = 0; off < 8; off++) {
octree[2 * (newNode + off)] = 0;
octree[2 * (newNode + off) + 1] = 0;
}
}
}
} | .text
.file "splitNodes.hip"
.globl _Z25__device_stub__splitNodesPiS_ii # -- Begin function _Z25__device_stub__splitNodesPiS_ii
.p2align 4, 0x90
.type _Z25__device_stub__splitNodesPiS_ii,@function
_Z25__device_stub__splitNodesPiS_ii: # @_Z25__device_stub__splitNodesPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10splitNodesPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__splitNodesPiS_ii, .Lfunc_end0-_Z25__device_stub__splitNodesPiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10splitNodesPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10splitNodesPiS_ii,@object # @_Z10splitNodesPiS_ii
.section .rodata,"a",@progbits
.globl _Z10splitNodesPiS_ii
.p2align 3, 0x0
_Z10splitNodesPiS_ii:
.quad _Z25__device_stub__splitNodesPiS_ii
.size _Z10splitNodesPiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10splitNodesPiS_ii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__splitNodesPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10splitNodesPiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10splitNodesPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R0, R0, c[0x0][0x174], RZ ; /* 0x00005d0000007a10 */
/* 0x000fe20007ffe0ff */
/*0070*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0090*/ SHF.L.U32 R0, R0, 0x1, RZ ; /* 0x0000000100007819 */
/* 0x000fca00000006ff */
/*00a0*/ IMAD.WIDE R2, R0, R13, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e020d */
/*00b0*/ LDG.E.U8 R0, [R2.64+0x3] ; /* 0x0000030402007981 */
/* 0x000ea4000c1e1100 */
/*00c0*/ LOP3.LUT P0, RZ, R0, 0x40, RZ, 0xc0, !PT ; /* 0x0000004000ff7812 */
/* 0x004fda000780c0ff */
/*00d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00e0*/ S2R R5, SR_LANEID ; /* 0x0000000000057919 */
/* 0x000e220000000000 */
/*00f0*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe200038e0100 */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0110*/ FLO.U32 R8, UR6 ; /* 0x0000000600087d00 */
/* 0x000e3000080e0000 */
/*0120*/ POPC R0, UR6 ; /* 0x0000000600007d09 */
/* 0x000e620008000000 */
/*0130*/ ISETP.EQ.U32.AND P0, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x001fe20003f02070 */
/*0140*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*0150*/ SHF.L.U32 R11, R0, 0x3, RZ ; /* 0x00000003000b7819 */
/* 0x002fd600000006ff */
/*0160*/ @P0 ATOMG.E.ADD.STRONG.GPU PT, R5, [R4.64], R11 ; /* 0x0000000b040509a8 */
/* 0x000ea800081ee1c4 */
/*0170*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ee8000c1e1900 */
/*0180*/ S2R R7, SR_LTMASK ; /* 0x0000000000077919 */
/* 0x000e240000003900 */
/*0190*/ LOP3.LUT R10, R7, UR6, RZ, 0xc0, !PT ; /* 0x00000006070a7c12 */
/* 0x001fc8000f8ec0ff */
/*01a0*/ POPC R7, R10 ; /* 0x0000000a00077309 */
/* 0x000e220000000000 */
/*01b0*/ SHFL.IDX PT, R0, R5, R8, 0x1f ; /* 0x00001f0805007589 */
/* 0x004e2400000e0000 */
/*01c0*/ IMAD R0, R7, 0x8, R0 ; /* 0x0000000807007824 */
/* 0x001fe200078e0200 */
/*01d0*/ LOP3.LUT R7, R6, 0xc0000000, RZ, 0xc0, !PT ; /* 0xc000000006077812 */
/* 0x008fc800078ec0ff */
/*01e0*/ SHF.L.U32 R6, R0, 0x1, RZ ; /* 0x0000000100067819 */
/* 0x000fe400000006ff */
/*01f0*/ LOP3.LUT R9, R7, 0x3fffffff, R0, 0xf8, !PT ; /* 0x3fffffff07097812 */
/* 0x000fc600078ef800 */
/*0200*/ IMAD.WIDE R6, R6, R13, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe400078e020d */
/*0210*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*0220*/ STG.E [R6.64], RZ ; /* 0x000000ff06007986 */
/* 0x000fe8000c101904 */
/*0230*/ STG.E [R6.64+0x4], RZ ; /* 0x000004ff06007986 */
/* 0x000fe8000c101904 */
/*0240*/ STG.E [R6.64+0x8], RZ ; /* 0x000008ff06007986 */
/* 0x000fe8000c101904 */
/*0250*/ STG.E [R6.64+0xc], RZ ; /* 0x00000cff06007986 */
/* 0x000fe8000c101904 */
/*0260*/ STG.E [R6.64+0x10], RZ ; /* 0x000010ff06007986 */
/* 0x000fe8000c101904 */
/*0270*/ STG.E [R6.64+0x14], RZ ; /* 0x000014ff06007986 */
/* 0x000fe8000c101904 */
/*0280*/ STG.E [R6.64+0x18], RZ ; /* 0x000018ff06007986 */
/* 0x000fe8000c101904 */
/*0290*/ STG.E [R6.64+0x1c], RZ ; /* 0x00001cff06007986 */
/* 0x000fe8000c101904 */
/*02a0*/ STG.E [R6.64+0x20], RZ ; /* 0x000020ff06007986 */
/* 0x000fe8000c101904 */
/*02b0*/ STG.E [R6.64+0x24], RZ ; /* 0x000024ff06007986 */
/* 0x000fe8000c101904 */
/*02c0*/ STG.E [R6.64+0x28], RZ ; /* 0x000028ff06007986 */
/* 0x000fe8000c101904 */
/*02d0*/ STG.E [R6.64+0x2c], RZ ; /* 0x00002cff06007986 */
/* 0x000fe8000c101904 */
/*02e0*/ STG.E [R6.64+0x30], RZ ; /* 0x000030ff06007986 */
/* 0x000fe8000c101904 */
/*02f0*/ STG.E [R6.64+0x34], RZ ; /* 0x000034ff06007986 */
/* 0x000fe8000c101904 */
/*0300*/ STG.E [R6.64+0x38], RZ ; /* 0x000038ff06007986 */
/* 0x000fe8000c101904 */
/*0310*/ STG.E [R6.64+0x3c], RZ ; /* 0x00003cff06007986 */
/* 0x000fe2000c101904 */
/*0320*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0330*/ BRA 0x330; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10splitNodesPiS_ii
.globl _Z10splitNodesPiS_ii
.p2align 8
.type _Z10splitNodesPiS_ii,@function
_Z10splitNodesPiS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b32 s4, s[0:1], 0x14
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_lshl_u32 v0, v1, s4, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v2, 2.0, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, 0, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_6
s_mov_b32 s6, exec_lo
s_mov_b32 s4, 0
v_mbcnt_lo_u32_b32 v2, s6, 0
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_4
s_load_b64 s[0:1], s[0:1], 0x8
s_bcnt1_i32_b32 s6, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b32 s6, s6, 3
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, s6
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v3, v3, v4, s[0:1] glc
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s5
global_load_b32 v4, v[0:1], off
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_lshl_add_u32 v3, v2, 3, s0
s_lshl_b32 s0, s0, 1
v_lshl_add_u32 v2, v2, 4, s0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2)
v_bfi_b32 v4, -2.0, v4, v3
v_mov_b32_e32 v3, 0
global_store_b32 v[0:1], v4, off
.p2align 6
.LBB0_5:
v_add_nc_u32_e32 v0, s4, v2
s_add_i32 s4, s4, 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s4, 16
v_add_nc_u32_e32 v4, 1, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_clause 0x1
global_store_b32 v[0:1], v3, off
global_store_b32 v[4:5], v3, off
s_cbranch_scc1 .LBB0_5
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10splitNodesPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10splitNodesPiS_ii, .Lfunc_end0-_Z10splitNodesPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10splitNodesPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10splitNodesPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010969f_00000000-6_splitNodes.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z10splitNodesPiS_iiPiS_ii
.type _Z34__device_stub__Z10splitNodesPiS_iiPiS_ii, @function
_Z34__device_stub__Z10splitNodesPiS_iiPiS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10splitNodesPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z10splitNodesPiS_iiPiS_ii, .-_Z34__device_stub__Z10splitNodesPiS_iiPiS_ii
.globl _Z10splitNodesPiS_ii
.type _Z10splitNodesPiS_ii, @function
_Z10splitNodesPiS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10splitNodesPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10splitNodesPiS_ii, .-_Z10splitNodesPiS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10splitNodesPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10splitNodesPiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "splitNodes.hip"
.globl _Z25__device_stub__splitNodesPiS_ii # -- Begin function _Z25__device_stub__splitNodesPiS_ii
.p2align 4, 0x90
.type _Z25__device_stub__splitNodesPiS_ii,@function
_Z25__device_stub__splitNodesPiS_ii: # @_Z25__device_stub__splitNodesPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10splitNodesPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__splitNodesPiS_ii, .Lfunc_end0-_Z25__device_stub__splitNodesPiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10splitNodesPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10splitNodesPiS_ii,@object # @_Z10splitNodesPiS_ii
.section .rodata,"a",@progbits
.globl _Z10splitNodesPiS_ii
.p2align 3, 0x0
_Z10splitNodesPiS_ii:
.quad _Z25__device_stub__splitNodesPiS_ii
.size _Z10splitNodesPiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10splitNodesPiS_ii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__splitNodesPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10splitNodesPiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define N 1024*1024
#define THREADS_PER_BLOCK 512
__global__ void multiply(float *a, float *b, int n);
void random_floats(float *x, int Num);
float* CPU_big_dot(float *a, float *b, int Num);
float* GPU_big_dot(float *A, float *B, int Num);
long long start_timer();
long long stop_timer(long long start_time, char *name);
int main(void) {
float *a, *b; // host copies of a, b, c
int size = N * sizeof(float);
// Alloc space for host copies of a, b, c and setup input values
a = (float *) malloc(size);
random_floats(a, N);
b = (float *) malloc(size);
random_floats(b, N);
float *result_cpu, *result_gpu;
long long cpu_start, cpu_time, gpu_start, gpu_time;
char cpu_task_name[] = "CPU time usage";
char gpu_task_name[] = "GPU time usage";
cpu_start = start_timer();
result_cpu = CPU_big_dot(a, b, N);
cpu_time = stop_timer(cpu_start, cpu_task_name);
gpu_start = start_timer();
result_gpu = GPU_big_dot(a, b, N);
gpu_time = stop_timer(gpu_start, gpu_task_name);
printf("\ncpu result: %f\n", *result_cpu);
printf("gpu result: %f\n", *result_gpu);
float diff = *result_cpu - *result_gpu;
if (diff <= 1.0e-6)
printf("difference between 2 results is: %f < 1.0e-6 ===> correct.\n", diff);
else{
printf("difference between 2 results is: %f > 1.0e-6 ===> incorrect.\nExit Now!\n", diff);
exit(-1);
}
printf("\nCPU/GPU speedup: %f\n", 1.0 * cpu_time / gpu_time);
free(a);
free(b);
free(result_cpu);
free(result_gpu);
return 0;
}
__global__ void multiply(float *a, float *b, int n)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
if (index < n)
a[index] = a[index] * b[index];
}
void random_floats(float *x, int Num)
{
for (int i = 0; i < Num; i++)
{
x[i] = (float)rand() / RAND_MAX;
}
}
float* CPU_big_dot(float *a, float *b, int Num)
{
float *sum;
sum = (float *) malloc(sizeof(float));
(*sum) = 0;
for (int i = 0; i < Num; i++)
{
(*sum) += a[i] * b[i];
}
return sum;
}
float* GPU_big_dot(float *A, float *B, int Num)
{
float *sum;
sum = (float *) malloc(sizeof(float));
(*sum) = 0;
float *d_A, *d_B; // device copies of A, B
int size = Num * sizeof(float);
// Allocate space for device copies of a, b, c
cudaMalloc((void **) &d_A, size);
cudaMalloc((void **) &d_B, size);
// Copy inputs to device
cudaMemcpy(d_A, A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, B, size, cudaMemcpyHostToDevice);
// Launch add() kernel on GPU with N threads
multiply<<<(Num + THREADS_PER_BLOCK - 1)/THREADS_PER_BLOCK, THREADS_PER_BLOCK>>>(d_A, d_B, Num);
// Copy result back to host
cudaMemcpy(A, d_A, size, cudaMemcpyDeviceToHost);
for (int i = 0; i < Num; i++)
(*sum) += A[i];
// Cleanup
cudaFree(d_A);
cudaFree(d_B);
return sum;
}
long long start_timer() {
struct timeval tv;
gettimeofday(&tv, NULL);
return tv.tv_sec * 1000000 + tv.tv_usec;
}
long long stop_timer(long long start_time, char *name) {
struct timeval tv;
gettimeofday(&tv, NULL);
long long end_time = tv.tv_sec * 1000000 + tv.tv_usec;
printf("%s: %.5f sec\n", name, ((float)(end_time-start_time))/(1000*1000));
return end_time - start_time;
} | code for sm_80
Function : _Z8multiplyPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R2, R3, c[0x0][0x168] ; /* 0x00005a0002047625 */
/* 0x000fc800078e0203 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe400078e0203 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FMUL R7, R4, R7 ; /* 0x0000000704077220 */
/* 0x004fca0000400000 */
/*00d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define N 1024*1024
#define THREADS_PER_BLOCK 512
__global__ void multiply(float *a, float *b, int n);
void random_floats(float *x, int Num);
float* CPU_big_dot(float *a, float *b, int Num);
float* GPU_big_dot(float *A, float *B, int Num);
long long start_timer();
long long stop_timer(long long start_time, char *name);
int main(void) {
float *a, *b; // host copies of a, b, c
int size = N * sizeof(float);
// Alloc space for host copies of a, b, c and setup input values
a = (float *) malloc(size);
random_floats(a, N);
b = (float *) malloc(size);
random_floats(b, N);
float *result_cpu, *result_gpu;
long long cpu_start, cpu_time, gpu_start, gpu_time;
char cpu_task_name[] = "CPU time usage";
char gpu_task_name[] = "GPU time usage";
cpu_start = start_timer();
result_cpu = CPU_big_dot(a, b, N);
cpu_time = stop_timer(cpu_start, cpu_task_name);
gpu_start = start_timer();
result_gpu = GPU_big_dot(a, b, N);
gpu_time = stop_timer(gpu_start, gpu_task_name);
printf("\ncpu result: %f\n", *result_cpu);
printf("gpu result: %f\n", *result_gpu);
float diff = *result_cpu - *result_gpu;
if (diff <= 1.0e-6)
printf("difference between 2 results is: %f < 1.0e-6 ===> correct.\n", diff);
else{
printf("difference between 2 results is: %f > 1.0e-6 ===> incorrect.\nExit Now!\n", diff);
exit(-1);
}
printf("\nCPU/GPU speedup: %f\n", 1.0 * cpu_time / gpu_time);
free(a);
free(b);
free(result_cpu);
free(result_gpu);
return 0;
}
__global__ void multiply(float *a, float *b, int n)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
if (index < n)
a[index] = a[index] * b[index];
}
void random_floats(float *x, int Num)
{
for (int i = 0; i < Num; i++)
{
x[i] = (float)rand() / RAND_MAX;
}
}
float* CPU_big_dot(float *a, float *b, int Num)
{
float *sum;
sum = (float *) malloc(sizeof(float));
(*sum) = 0;
for (int i = 0; i < Num; i++)
{
(*sum) += a[i] * b[i];
}
return sum;
}
float* GPU_big_dot(float *A, float *B, int Num)
{
float *sum;
sum = (float *) malloc(sizeof(float));
(*sum) = 0;
float *d_A, *d_B; // device copies of A, B
int size = Num * sizeof(float);
// Allocate space for device copies of a, b, c
cudaMalloc((void **) &d_A, size);
cudaMalloc((void **) &d_B, size);
// Copy inputs to device
cudaMemcpy(d_A, A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, B, size, cudaMemcpyHostToDevice);
// Launch add() kernel on GPU with N threads
multiply<<<(Num + THREADS_PER_BLOCK - 1)/THREADS_PER_BLOCK, THREADS_PER_BLOCK>>>(d_A, d_B, Num);
// Copy result back to host
cudaMemcpy(A, d_A, size, cudaMemcpyDeviceToHost);
for (int i = 0; i < Num; i++)
(*sum) += A[i];
// Cleanup
cudaFree(d_A);
cudaFree(d_B);
return sum;
}
long long start_timer() {
struct timeval tv;
gettimeofday(&tv, NULL);
return tv.tv_sec * 1000000 + tv.tv_usec;
}
long long stop_timer(long long start_time, char *name) {
struct timeval tv;
gettimeofday(&tv, NULL);
long long end_time = tv.tv_sec * 1000000 + tv.tv_usec;
printf("%s: %.5f sec\n", name, ((float)(end_time-start_time))/(1000*1000));
return end_time - start_time;
} | .file "tmpxft_0012b7c8_00000000-6_assign1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13random_floatsPfi
.type _Z13random_floatsPfi, @function
_Z13random_floatsPfi:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2058:
.size _Z13random_floatsPfi, .-_Z13random_floatsPfi
.globl _Z11CPU_big_dotPfS_i
.type _Z11CPU_big_dotPfS_i, @function
_Z11CPU_big_dotPfS_i:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbp
movq %rsi, %r12
movl %edx, %ebx
movl $4, %edi
call malloc@PLT
movl $0x00000000, (%rax)
testl %ebx, %ebx
jle .L11
movslq %ebx, %rcx
salq $2, %rcx
movl $0, %edx
pxor %xmm1, %xmm1
.L13:
movss 0(%rbp,%rdx), %xmm0
mulss (%r12,%rdx), %xmm0
addss %xmm0, %xmm1
addq $4, %rdx
cmpq %rcx, %rdx
jne .L13
movss %xmm1, (%rax)
.L11:
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z11CPU_big_dotPfS_i, .-_Z11CPU_big_dotPfS_i
.globl _Z11start_timerv
.type _Z11start_timerv, @function
_Z11start_timerv:
.LFB2061:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
imulq $1000000, (%rsp), %rax
addq 8(%rsp), %rax
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L19
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z11start_timerv, .-_Z11start_timerv
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "%s: %.5f sec\n"
.text
.globl _Z10stop_timerxPc
.type _Z10stop_timerxPc, @function
_Z10stop_timerxPc:
.LFB2062:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r12
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
imulq $1000000, (%rsp), %rbx
addq 8(%rsp), %rbx
subq %r12, %rbx
pxor %xmm0, %xmm0
cvtsi2ssq %rbx, %xmm0
divss .LC2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %rbp, %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L23
movq %rbx, %rax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size _Z10stop_timerxPc, .-_Z10stop_timerxPc
.globl _Z30__device_stub__Z8multiplyPfS_iPfS_i
.type _Z30__device_stub__Z8multiplyPfS_iPfS_i, @function
_Z30__device_stub__Z8multiplyPfS_iPfS_i:
.LFB2087:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8multiplyPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z30__device_stub__Z8multiplyPfS_iPfS_i, .-_Z30__device_stub__Z8multiplyPfS_iPfS_i
.globl _Z8multiplyPfS_i
.type _Z8multiplyPfS_i, @function
_Z8multiplyPfS_i:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z8multiplyPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z8multiplyPfS_i, .-_Z8multiplyPfS_i
.globl _Z11GPU_big_dotPfS_i
.type _Z11GPU_big_dotPfS_i, @function
_Z11GPU_big_dotPfS_i:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r12
movq %rsi, %r15
movl %edx, %ebx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $4, %edi
call malloc@PLT
movq %rax, %rbp
movl $0x00000000, (%rax)
movslq %ebx, %r13
leal 0(,%rbx,4), %r14d
movslq %r14d, %r14
movq %rsp, %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r12, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r15, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 28(%rsp)
movl $1, 32(%rsp)
leal 1022(%rbx), %eax
movl %ebx, %edx
addl $511, %edx
cmovns %edx, %eax
sarl $9, %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L33:
movl $2, %ecx
movq %r14, %rdx
movq (%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %ebx, %ebx
jle .L34
movss 0(%rbp), %xmm0
movq %r12, %rax
leaq (%r12,%r13,4), %rdx
.L35:
addss (%rax), %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L35
movss %xmm0, 0(%rbp)
.L34:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L40
movq %rbp, %rax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movl %ebx, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z30__device_stub__Z8multiplyPfS_iPfS_i
jmp .L33
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z11GPU_big_dotPfS_i, .-_Z11GPU_big_dotPfS_i
.section .rodata.str1.1
.LC4:
.string "\ncpu result: %f\n"
.LC5:
.string "gpu result: %f\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "difference between 2 results is: %f < 1.0e-6 ===> correct.\n"
.section .rodata.str1.1
.LC8:
.string "\nCPU/GPU speedup: %f\n"
.section .rodata.str1.8
.align 8
.LC9:
.string "difference between 2 results is: %f > 1.0e-6 ===> incorrect.\nExit Now!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $1048576, %esi
movq %rax, %rdi
call _Z13random_floatsPfi
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movl $1048576, %esi
movq %rax, %rdi
call _Z13random_floatsPfi
movabsq $7308613717771767875, %rax
movq %rax, 10(%rsp)
movabsq $28542640894320741, %rax
movq %rax, 17(%rsp)
movabsq $7308613717771767879, %rcx
movq %rcx, 25(%rsp)
movq %rax, 32(%rsp)
call _Z11start_timerv
movq %rax, %r12
movl $1048576, %edx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z11CPU_big_dotPfS_i
movq %rax, %r13
leaq 10(%rsp), %rsi
movq %r12, %rdi
call _Z10stop_timerxPc
movq %rax, %r15
call _Z11start_timerv
movq %rax, %r14
movl $1048576, %edx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z11GPU_big_dotPfS_i
movq %rax, %r12
leaq 25(%rsp), %rsi
movq %r14, %rdi
call _Z10stop_timerxPc
movq %rax, %r14
pxor %xmm0, %xmm0
cvtss2sd 0(%r13), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 0(%r13), %xmm0
subss (%r12), %xmm0
cvtss2sd %xmm0, %xmm0
movsd .LC6(%rip), %xmm1
comisd %xmm0, %xmm1
jb .L46
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %r15, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq %r14, %xmm1
divsd %xmm1, %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L49
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L49:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z8multiplyPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z8multiplyPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.align 4
.LC2:
.long 1232348160
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC6:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define N 1024*1024
#define THREADS_PER_BLOCK 512
__global__ void multiply(float *a, float *b, int n);
void random_floats(float *x, int Num);
float* CPU_big_dot(float *a, float *b, int Num);
float* GPU_big_dot(float *A, float *B, int Num);
long long start_timer();
long long stop_timer(long long start_time, char *name);
int main(void) {
float *a, *b; // host copies of a, b, c
int size = N * sizeof(float);
// Alloc space for host copies of a, b, c and setup input values
a = (float *) malloc(size);
random_floats(a, N);
b = (float *) malloc(size);
random_floats(b, N);
float *result_cpu, *result_gpu;
long long cpu_start, cpu_time, gpu_start, gpu_time;
char cpu_task_name[] = "CPU time usage";
char gpu_task_name[] = "GPU time usage";
cpu_start = start_timer();
result_cpu = CPU_big_dot(a, b, N);
cpu_time = stop_timer(cpu_start, cpu_task_name);
gpu_start = start_timer();
result_gpu = GPU_big_dot(a, b, N);
gpu_time = stop_timer(gpu_start, gpu_task_name);
printf("\ncpu result: %f\n", *result_cpu);
printf("gpu result: %f\n", *result_gpu);
float diff = *result_cpu - *result_gpu;
if (diff <= 1.0e-6)
printf("difference between 2 results is: %f < 1.0e-6 ===> correct.\n", diff);
else{
printf("difference between 2 results is: %f > 1.0e-6 ===> incorrect.\nExit Now!\n", diff);
exit(-1);
}
printf("\nCPU/GPU speedup: %f\n", 1.0 * cpu_time / gpu_time);
free(a);
free(b);
free(result_cpu);
free(result_gpu);
return 0;
}
__global__ void multiply(float *a, float *b, int n)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
if (index < n)
a[index] = a[index] * b[index];
}
void random_floats(float *x, int Num)
{
for (int i = 0; i < Num; i++)
{
x[i] = (float)rand() / RAND_MAX;
}
}
float* CPU_big_dot(float *a, float *b, int Num)
{
float *sum;
sum = (float *) malloc(sizeof(float));
(*sum) = 0;
for (int i = 0; i < Num; i++)
{
(*sum) += a[i] * b[i];
}
return sum;
}
float* GPU_big_dot(float *A, float *B, int Num)
{
float *sum;
sum = (float *) malloc(sizeof(float));
(*sum) = 0;
float *d_A, *d_B; // device copies of A, B
int size = Num * sizeof(float);
// Allocate space for device copies of a, b, c
cudaMalloc((void **) &d_A, size);
cudaMalloc((void **) &d_B, size);
// Copy inputs to device
cudaMemcpy(d_A, A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, B, size, cudaMemcpyHostToDevice);
// Launch add() kernel on GPU with N threads
multiply<<<(Num + THREADS_PER_BLOCK - 1)/THREADS_PER_BLOCK, THREADS_PER_BLOCK>>>(d_A, d_B, Num);
// Copy result back to host
cudaMemcpy(A, d_A, size, cudaMemcpyDeviceToHost);
for (int i = 0; i < Num; i++)
(*sum) += A[i];
// Cleanup
cudaFree(d_A);
cudaFree(d_B);
return sum;
}
long long start_timer() {
struct timeval tv;
gettimeofday(&tv, NULL);
return tv.tv_sec * 1000000 + tv.tv_usec;
}
long long stop_timer(long long start_time, char *name) {
struct timeval tv;
gettimeofday(&tv, NULL);
long long end_time = tv.tv_sec * 1000000 + tv.tv_usec;
printf("%s: %.5f sec\n", name, ((float)(end_time-start_time))/(1000*1000));
return end_time - start_time;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define N 1024*1024
#define THREADS_PER_BLOCK 512
__global__ void multiply(float *a, float *b, int n);
void random_floats(float *x, int Num);
float* CPU_big_dot(float *a, float *b, int Num);
float* GPU_big_dot(float *A, float *B, int Num);
long long start_timer();
long long stop_timer(long long start_time, char *name);
int main(void) {
float *a, *b; // host copies of a, b, c
int size = N * sizeof(float);
// Alloc space for host copies of a, b, c and setup input values
a = (float *) malloc(size);
random_floats(a, N);
b = (float *) malloc(size);
random_floats(b, N);
float *result_cpu, *result_gpu;
long long cpu_start, cpu_time, gpu_start, gpu_time;
char cpu_task_name[] = "CPU time usage";
char gpu_task_name[] = "GPU time usage";
cpu_start = start_timer();
result_cpu = CPU_big_dot(a, b, N);
cpu_time = stop_timer(cpu_start, cpu_task_name);
gpu_start = start_timer();
result_gpu = GPU_big_dot(a, b, N);
gpu_time = stop_timer(gpu_start, gpu_task_name);
printf("\ncpu result: %f\n", *result_cpu);
printf("gpu result: %f\n", *result_gpu);
float diff = *result_cpu - *result_gpu;
if (diff <= 1.0e-6)
printf("difference between 2 results is: %f < 1.0e-6 ===> correct.\n", diff);
else{
printf("difference between 2 results is: %f > 1.0e-6 ===> incorrect.\nExit Now!\n", diff);
exit(-1);
}
printf("\nCPU/GPU speedup: %f\n", 1.0 * cpu_time / gpu_time);
free(a);
free(b);
free(result_cpu);
free(result_gpu);
return 0;
}
__global__ void multiply(float *a, float *b, int n)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
if (index < n)
a[index] = a[index] * b[index];
}
void random_floats(float *x, int Num)
{
for (int i = 0; i < Num; i++)
{
x[i] = (float)rand() / RAND_MAX;
}
}
float* CPU_big_dot(float *a, float *b, int Num)
{
float *sum;
sum = (float *) malloc(sizeof(float));
(*sum) = 0;
for (int i = 0; i < Num; i++)
{
(*sum) += a[i] * b[i];
}
return sum;
}
float* GPU_big_dot(float *A, float *B, int Num)
{
float *sum;
sum = (float *) malloc(sizeof(float));
(*sum) = 0;
float *d_A, *d_B; // device copies of A, B
int size = Num * sizeof(float);
// Allocate space for device copies of a, b, c
hipMalloc((void **) &d_A, size);
hipMalloc((void **) &d_B, size);
// Copy inputs to device
hipMemcpy(d_A, A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, B, size, hipMemcpyHostToDevice);
// Launch add() kernel on GPU with N threads
multiply<<<(Num + THREADS_PER_BLOCK - 1)/THREADS_PER_BLOCK, THREADS_PER_BLOCK>>>(d_A, d_B, Num);
// Copy result back to host
hipMemcpy(A, d_A, size, hipMemcpyDeviceToHost);
for (int i = 0; i < Num; i++)
(*sum) += A[i];
// Cleanup
hipFree(d_A);
hipFree(d_B);
return sum;
}
long long start_timer() {
struct timeval tv;
gettimeofday(&tv, NULL);
return tv.tv_sec * 1000000 + tv.tv_usec;
}
long long stop_timer(long long start_time, char *name) {
struct timeval tv;
gettimeofday(&tv, NULL);
long long end_time = tv.tv_sec * 1000000 + tv.tv_usec;
printf("%s: %.5f sec\n", name, ((float)(end_time-start_time))/(1000*1000));
return end_time - start_time;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define N 1024*1024
#define THREADS_PER_BLOCK 512
__global__ void multiply(float *a, float *b, int n);
void random_floats(float *x, int Num);
float* CPU_big_dot(float *a, float *b, int Num);
float* GPU_big_dot(float *A, float *B, int Num);
long long start_timer();
long long stop_timer(long long start_time, char *name);
int main(void) {
float *a, *b; // host copies of a, b, c
int size = N * sizeof(float);
// Alloc space for host copies of a, b, c and setup input values
a = (float *) malloc(size);
random_floats(a, N);
b = (float *) malloc(size);
random_floats(b, N);
float *result_cpu, *result_gpu;
long long cpu_start, cpu_time, gpu_start, gpu_time;
char cpu_task_name[] = "CPU time usage";
char gpu_task_name[] = "GPU time usage";
cpu_start = start_timer();
result_cpu = CPU_big_dot(a, b, N);
cpu_time = stop_timer(cpu_start, cpu_task_name);
gpu_start = start_timer();
result_gpu = GPU_big_dot(a, b, N);
gpu_time = stop_timer(gpu_start, gpu_task_name);
printf("\ncpu result: %f\n", *result_cpu);
printf("gpu result: %f\n", *result_gpu);
float diff = *result_cpu - *result_gpu;
if (diff <= 1.0e-6)
printf("difference between 2 results is: %f < 1.0e-6 ===> correct.\n", diff);
else{
printf("difference between 2 results is: %f > 1.0e-6 ===> incorrect.\nExit Now!\n", diff);
exit(-1);
}
printf("\nCPU/GPU speedup: %f\n", 1.0 * cpu_time / gpu_time);
free(a);
free(b);
free(result_cpu);
free(result_gpu);
return 0;
}
__global__ void multiply(float *a, float *b, int n)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
if (index < n)
a[index] = a[index] * b[index];
}
void random_floats(float *x, int Num)
{
for (int i = 0; i < Num; i++)
{
x[i] = (float)rand() / RAND_MAX;
}
}
float* CPU_big_dot(float *a, float *b, int Num)
{
float *sum;
sum = (float *) malloc(sizeof(float));
(*sum) = 0;
for (int i = 0; i < Num; i++)
{
(*sum) += a[i] * b[i];
}
return sum;
}
float* GPU_big_dot(float *A, float *B, int Num)
{
float *sum;
sum = (float *) malloc(sizeof(float));
(*sum) = 0;
float *d_A, *d_B; // device copies of A, B
int size = Num * sizeof(float);
// Allocate space for device copies of a, b, c
hipMalloc((void **) &d_A, size);
hipMalloc((void **) &d_B, size);
// Copy inputs to device
hipMemcpy(d_A, A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, B, size, hipMemcpyHostToDevice);
// Launch add() kernel on GPU with N threads
multiply<<<(Num + THREADS_PER_BLOCK - 1)/THREADS_PER_BLOCK, THREADS_PER_BLOCK>>>(d_A, d_B, Num);
// Copy result back to host
hipMemcpy(A, d_A, size, hipMemcpyDeviceToHost);
for (int i = 0; i < Num; i++)
(*sum) += A[i];
// Cleanup
hipFree(d_A);
hipFree(d_B);
return sum;
}
long long start_timer() {
struct timeval tv;
gettimeofday(&tv, NULL);
return tv.tv_sec * 1000000 + tv.tv_usec;
}
long long stop_timer(long long start_time, char *name) {
struct timeval tv;
gettimeofday(&tv, NULL);
long long end_time = tv.tv_sec * 1000000 + tv.tv_usec;
printf("%s: %.5f sec\n", name, ((float)(end_time-start_time))/(1000*1000));
return end_time - start_time;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8multiplyPfS_i
.globl _Z8multiplyPfS_i
.p2align 8
.type _Z8multiplyPfS_i,@function
_Z8multiplyPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v4, v[2:3], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v0, v4, v0
global_store_b32 v[2:3], v0, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8multiplyPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8multiplyPfS_i, .Lfunc_end0-_Z8multiplyPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8multiplyPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8multiplyPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define N 1024*1024
#define THREADS_PER_BLOCK 512
__global__ void multiply(float *a, float *b, int n);
void random_floats(float *x, int Num);
float* CPU_big_dot(float *a, float *b, int Num);
float* GPU_big_dot(float *A, float *B, int Num);
long long start_timer();
long long stop_timer(long long start_time, char *name);
int main(void) {
float *a, *b; // host copies of a, b, c
int size = N * sizeof(float);
// Alloc space for host copies of a, b, c and setup input values
a = (float *) malloc(size);
random_floats(a, N);
b = (float *) malloc(size);
random_floats(b, N);
float *result_cpu, *result_gpu;
long long cpu_start, cpu_time, gpu_start, gpu_time;
char cpu_task_name[] = "CPU time usage";
char gpu_task_name[] = "GPU time usage";
cpu_start = start_timer();
result_cpu = CPU_big_dot(a, b, N);
cpu_time = stop_timer(cpu_start, cpu_task_name);
gpu_start = start_timer();
result_gpu = GPU_big_dot(a, b, N);
gpu_time = stop_timer(gpu_start, gpu_task_name);
printf("\ncpu result: %f\n", *result_cpu);
printf("gpu result: %f\n", *result_gpu);
float diff = *result_cpu - *result_gpu;
if (diff <= 1.0e-6)
printf("difference between 2 results is: %f < 1.0e-6 ===> correct.\n", diff);
else{
printf("difference between 2 results is: %f > 1.0e-6 ===> incorrect.\nExit Now!\n", diff);
exit(-1);
}
printf("\nCPU/GPU speedup: %f\n", 1.0 * cpu_time / gpu_time);
free(a);
free(b);
free(result_cpu);
free(result_gpu);
return 0;
}
__global__ void multiply(float *a, float *b, int n)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
if (index < n)
a[index] = a[index] * b[index];
}
void random_floats(float *x, int Num)
{
for (int i = 0; i < Num; i++)
{
x[i] = (float)rand() / RAND_MAX;
}
}
float* CPU_big_dot(float *a, float *b, int Num)
{
float *sum;
sum = (float *) malloc(sizeof(float));
(*sum) = 0;
for (int i = 0; i < Num; i++)
{
(*sum) += a[i] * b[i];
}
return sum;
}
float* GPU_big_dot(float *A, float *B, int Num)
{
float *sum;
sum = (float *) malloc(sizeof(float));
(*sum) = 0;
float *d_A, *d_B; // device copies of A, B
int size = Num * sizeof(float);
// Allocate space for device copies of a, b, c
hipMalloc((void **) &d_A, size);
hipMalloc((void **) &d_B, size);
// Copy inputs to device
hipMemcpy(d_A, A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, B, size, hipMemcpyHostToDevice);
// Launch add() kernel on GPU with N threads
multiply<<<(Num + THREADS_PER_BLOCK - 1)/THREADS_PER_BLOCK, THREADS_PER_BLOCK>>>(d_A, d_B, Num);
// Copy result back to host
hipMemcpy(A, d_A, size, hipMemcpyDeviceToHost);
for (int i = 0; i < Num; i++)
(*sum) += A[i];
// Cleanup
hipFree(d_A);
hipFree(d_B);
return sum;
}
long long start_timer() {
struct timeval tv;
gettimeofday(&tv, NULL);
return tv.tv_sec * 1000000 + tv.tv_usec;
}
long long stop_timer(long long start_time, char *name) {
struct timeval tv;
gettimeofday(&tv, NULL);
long long end_time = tv.tv_sec * 1000000 + tv.tv_usec;
printf("%s: %.5f sec\n", name, ((float)(end_time-start_time))/(1000*1000));
return end_time - start_time;
} | .text
.file "assign1.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI0_1:
.long 0x49742400 # float 1.0E+6
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI0_2:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI0_0(%rip), %xmm0
movss %xmm0, (%rbx,%r14,4)
incq %r14
cmpq $1048576, %r14 # imm = 0x100000
jne .LBB0_1
# %bb.2: # %_Z13random_floatsPfi.exit
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_3: # %.lr.ph.i22
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI0_0(%rip), %xmm0
movss %xmm0, (%r14,%r15,4)
incq %r15
cmpq $1048576, %r15 # imm = 0x100000
jne .LBB0_3
# %bb.4: # %_Z13random_floatsPfi.exit26
movabsq $7308613717771767875, %rax # imm = 0x656D697420555043
movq %rax, 41(%rsp)
movl $1634956576, 49(%rsp) # imm = 0x61737520
movw $25959, 53(%rsp) # imm = 0x6567
movb $0, 55(%rsp)
movabsq $7308613717771767879, %rax # imm = 0x656D697420555047
movq %rax, 26(%rsp)
movl $1634956576, 34(%rsp) # imm = 0x61737520
movw $25959, 38(%rsp) # imm = 0x6567
movb $0, 40(%rsp)
xorl %r13d, %r13d
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %r12
movq 8(%rsp), %r15
xorps %xmm1, %xmm1
.p2align 4, 0x90
.LBB0_5: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%r14,%r13,4), %xmm0
addss %xmm0, %xmm1
incq %r13
cmpq $1048576, %r13 # imm = 0x100000
jne .LBB0_5
# %bb.6: # %_Z11CPU_big_dotPfS_i.exit
movq %rsp, %rdi
xorl %esi, %esi
movss %xmm1, 16(%rsp) # 4-byte Spill
callq gettimeofday
movq (%rsp), %rax
subq %r12, %rax
movq 8(%rsp), %rcx
subq %r15, %rcx
imulq $1000000, %rax, %r12 # imm = 0xF4240
addq %rcx, %r12
xorps %xmm0, %xmm0
cvtsi2ss %r12, %xmm0
divss .LCPI0_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq 41(%rsp), %rsi
movl $.L.str.5, %edi
movb $1, %al
callq printf
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %r13
movq 8(%rsp), %rbp
movq %rbx, %rdi
movq %r14, %rsi
movl $1048576, %edx # imm = 0x100000
callq _Z11GPU_big_dotPfS_i
movq %rax, %r15
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rax
subq %r13, %rax
movq 8(%rsp), %rcx
subq %rbp, %rcx
imulq $1000000, %rax, %r13 # imm = 0xF4240
addq %rcx, %r13
xorps %xmm0, %xmm0
cvtsi2ss %r13, %xmm0
divss .LCPI0_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq 26(%rsp), %rsi
movl $.L.str.5, %edi
movb $1, %al
callq printf
movss 16(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movss (%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, 20(%rsp) # 4-byte Spill
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movss 16(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
subss 20(%rsp), %xmm0 # 4-byte Folded Reload
cvtss2sd %xmm0, %xmm0
movsd .LCPI0_2(%rip), %xmm1 # xmm1 = mem[0],zero
ucomisd %xmm0, %xmm1
jb .LBB0_8
# %bb.7:
movl $.L.str.2, %edi
movb $1, %al
callq printf
xorps %xmm0, %xmm0
cvtsi2sd %r12, %xmm0
xorps %xmm1, %xmm1
cvtsi2sd %r13, %xmm1
divsd %xmm1, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_8:
.cfi_def_cfa_offset 112
movl $.L.str.3, %edi
movb $1, %al
callq printf
movl $-1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z13random_floatsPfi
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z13random_floatsPfi
.p2align 4, 0x90
.type _Z13random_floatsPfi,@function
_Z13random_floatsPfi: # @_Z13random_floatsPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z13random_floatsPfi, .Lfunc_end1-_Z13random_floatsPfi
.cfi_endproc
# -- End function
.globl _Z11start_timerv # -- Begin function _Z11start_timerv
.p2align 4, 0x90
.type _Z11start_timerv,@function
_Z11start_timerv: # @_Z11start_timerv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, 8(%rsp), %rax # imm = 0xF4240
addq 16(%rsp), %rax
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z11start_timerv, .Lfunc_end2-_Z11start_timerv
.cfi_endproc
# -- End function
.globl _Z11CPU_big_dotPfS_i # -- Begin function _Z11CPU_big_dotPfS_i
.p2align 4, 0x90
.type _Z11CPU_big_dotPfS_i,@function
_Z11CPU_big_dotPfS_i: # @_Z11CPU_big_dotPfS_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movq %rsi, %rbx
movq %rdi, %r14
movl $4, %edi
callq malloc
movl $0, (%rax)
testl %ebp, %ebp
jle .LBB3_4
# %bb.1: # %.lr.ph
movss (%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
movl %ebp, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_2: # =>This Inner Loop Header: Depth=1
movss (%r14,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rbx,%rdx,4), %xmm1
addss %xmm1, %xmm0
incq %rdx
cmpq %rdx, %rcx
jne .LBB3_2
# %bb.3: # %._crit_edge
movss %xmm0, (%rax)
.LBB3_4:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z11CPU_big_dotPfS_i, .Lfunc_end3-_Z11CPU_big_dotPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z10stop_timerxPc
.LCPI4_0:
.long 0x49742400 # float 1.0E+6
.text
.globl _Z10stop_timerxPc
.p2align 4, 0x90
.type _Z10stop_timerxPc,@function
_Z10stop_timerxPc: # @_Z10stop_timerxPc
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, (%rsp), %rax # imm = 0xF4240
movq 8(%rsp), %r15
subq %r14, %r15
addq %rax, %r15
cvtsi2ss %r15, %xmm0
divss .LCPI4_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movq %rbx, %rsi
movb $1, %al
callq printf
movq %r15, %rax
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z10stop_timerxPc, .Lfunc_end4-_Z10stop_timerxPc
.cfi_endproc
# -- End function
.globl _Z11GPU_big_dotPfS_i # -- Begin function _Z11GPU_big_dotPfS_i
.p2align 4, 0x90
.type _Z11GPU_big_dotPfS_i,@function
_Z11GPU_big_dotPfS_i: # @_Z11GPU_big_dotPfS_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %edx, %r15d
movq %rsi, %r13
movq %rdi, %r14
movl $4, %edi
callq malloc
movq %rax, %rbx
movl $0, (%rax)
leal (,%r15,4), %eax
movslq %eax, %r12
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r13, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
leal 511(%r15), %eax
leal 1022(%r15), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r15d, 28(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8multiplyPfS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
testl %r15d, %r15d
jle .LBB5_6
# %bb.3: # %.lr.ph
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
movl %r15d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB5_4: # =>This Inner Loop Header: Depth=1
addss (%r14,%rcx,4), %xmm0
incq %rcx
cmpq %rcx, %rax
jne .LBB5_4
# %bb.5: # %._crit_edge
movss %xmm0, (%rbx)
.LBB5_6:
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z11GPU_big_dotPfS_i, .Lfunc_end5-_Z11GPU_big_dotPfS_i
.cfi_endproc
# -- End function
.globl _Z23__device_stub__multiplyPfS_i # -- Begin function _Z23__device_stub__multiplyPfS_i
.p2align 4, 0x90
.type _Z23__device_stub__multiplyPfS_i,@function
_Z23__device_stub__multiplyPfS_i: # @_Z23__device_stub__multiplyPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8multiplyPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end6:
.size _Z23__device_stub__multiplyPfS_i, .Lfunc_end6-_Z23__device_stub__multiplyPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8multiplyPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\ncpu result: %f\n"
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "gpu result: %f\n"
.size .L.str.1, 16
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "difference between 2 results is: %f < 1.0e-6 ===> correct.\n"
.size .L.str.2, 60
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "difference between 2 results is: %f > 1.0e-6 ===> incorrect.\nExit Now!\n"
.size .L.str.3, 72
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\nCPU/GPU speedup: %f\n"
.size .L.str.4, 22
.type _Z8multiplyPfS_i,@object # @_Z8multiplyPfS_i
.section .rodata,"a",@progbits
.globl _Z8multiplyPfS_i
.p2align 3, 0x0
_Z8multiplyPfS_i:
.quad _Z23__device_stub__multiplyPfS_i
.size _Z8multiplyPfS_i, 8
.type .L.str.5,@object # @.str.5
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.5:
.asciz "%s: %.5f sec\n"
.size .L.str.5, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8multiplyPfS_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__multiplyPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8multiplyPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8multiplyPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R2, R3, c[0x0][0x168] ; /* 0x00005a0002047625 */
/* 0x000fc800078e0203 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe400078e0203 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FMUL R7, R4, R7 ; /* 0x0000000704077220 */
/* 0x004fca0000400000 */
/*00d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8multiplyPfS_i
.globl _Z8multiplyPfS_i
.p2align 8
.type _Z8multiplyPfS_i,@function
_Z8multiplyPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v4, v[2:3], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v0, v4, v0
global_store_b32 v[2:3], v0, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8multiplyPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8multiplyPfS_i, .Lfunc_end0-_Z8multiplyPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8multiplyPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8multiplyPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012b7c8_00000000-6_assign1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13random_floatsPfi
.type _Z13random_floatsPfi, @function
_Z13random_floatsPfi:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2058:
.size _Z13random_floatsPfi, .-_Z13random_floatsPfi
.globl _Z11CPU_big_dotPfS_i
.type _Z11CPU_big_dotPfS_i, @function
_Z11CPU_big_dotPfS_i:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbp
movq %rsi, %r12
movl %edx, %ebx
movl $4, %edi
call malloc@PLT
movl $0x00000000, (%rax)
testl %ebx, %ebx
jle .L11
movslq %ebx, %rcx
salq $2, %rcx
movl $0, %edx
pxor %xmm1, %xmm1
.L13:
movss 0(%rbp,%rdx), %xmm0
mulss (%r12,%rdx), %xmm0
addss %xmm0, %xmm1
addq $4, %rdx
cmpq %rcx, %rdx
jne .L13
movss %xmm1, (%rax)
.L11:
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z11CPU_big_dotPfS_i, .-_Z11CPU_big_dotPfS_i
.globl _Z11start_timerv
.type _Z11start_timerv, @function
_Z11start_timerv:
.LFB2061:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
imulq $1000000, (%rsp), %rax
addq 8(%rsp), %rax
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L19
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z11start_timerv, .-_Z11start_timerv
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "%s: %.5f sec\n"
.text
.globl _Z10stop_timerxPc
.type _Z10stop_timerxPc, @function
_Z10stop_timerxPc:
.LFB2062:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r12
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
imulq $1000000, (%rsp), %rbx
addq 8(%rsp), %rbx
subq %r12, %rbx
pxor %xmm0, %xmm0
cvtsi2ssq %rbx, %xmm0
divss .LC2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %rbp, %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L23
movq %rbx, %rax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size _Z10stop_timerxPc, .-_Z10stop_timerxPc
.globl _Z30__device_stub__Z8multiplyPfS_iPfS_i
.type _Z30__device_stub__Z8multiplyPfS_iPfS_i, @function
_Z30__device_stub__Z8multiplyPfS_iPfS_i:
.LFB2087:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8multiplyPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z30__device_stub__Z8multiplyPfS_iPfS_i, .-_Z30__device_stub__Z8multiplyPfS_iPfS_i
.globl _Z8multiplyPfS_i
.type _Z8multiplyPfS_i, @function
_Z8multiplyPfS_i:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z8multiplyPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z8multiplyPfS_i, .-_Z8multiplyPfS_i
.globl _Z11GPU_big_dotPfS_i
.type _Z11GPU_big_dotPfS_i, @function
_Z11GPU_big_dotPfS_i:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r12
movq %rsi, %r15
movl %edx, %ebx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $4, %edi
call malloc@PLT
movq %rax, %rbp
movl $0x00000000, (%rax)
movslq %ebx, %r13
leal 0(,%rbx,4), %r14d
movslq %r14d, %r14
movq %rsp, %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r12, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r15, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 28(%rsp)
movl $1, 32(%rsp)
leal 1022(%rbx), %eax
movl %ebx, %edx
addl $511, %edx
cmovns %edx, %eax
sarl $9, %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L33:
movl $2, %ecx
movq %r14, %rdx
movq (%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %ebx, %ebx
jle .L34
movss 0(%rbp), %xmm0
movq %r12, %rax
leaq (%r12,%r13,4), %rdx
.L35:
addss (%rax), %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L35
movss %xmm0, 0(%rbp)
.L34:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L40
movq %rbp, %rax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movl %ebx, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z30__device_stub__Z8multiplyPfS_iPfS_i
jmp .L33
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z11GPU_big_dotPfS_i, .-_Z11GPU_big_dotPfS_i
.section .rodata.str1.1
.LC4:
.string "\ncpu result: %f\n"
.LC5:
.string "gpu result: %f\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "difference between 2 results is: %f < 1.0e-6 ===> correct.\n"
.section .rodata.str1.1
.LC8:
.string "\nCPU/GPU speedup: %f\n"
.section .rodata.str1.8
.align 8
.LC9:
.string "difference between 2 results is: %f > 1.0e-6 ===> incorrect.\nExit Now!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $1048576, %esi
movq %rax, %rdi
call _Z13random_floatsPfi
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movl $1048576, %esi
movq %rax, %rdi
call _Z13random_floatsPfi
movabsq $7308613717771767875, %rax
movq %rax, 10(%rsp)
movabsq $28542640894320741, %rax
movq %rax, 17(%rsp)
movabsq $7308613717771767879, %rcx
movq %rcx, 25(%rsp)
movq %rax, 32(%rsp)
call _Z11start_timerv
movq %rax, %r12
movl $1048576, %edx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z11CPU_big_dotPfS_i
movq %rax, %r13
leaq 10(%rsp), %rsi
movq %r12, %rdi
call _Z10stop_timerxPc
movq %rax, %r15
call _Z11start_timerv
movq %rax, %r14
movl $1048576, %edx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z11GPU_big_dotPfS_i
movq %rax, %r12
leaq 25(%rsp), %rsi
movq %r14, %rdi
call _Z10stop_timerxPc
movq %rax, %r14
pxor %xmm0, %xmm0
cvtss2sd 0(%r13), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 0(%r13), %xmm0
subss (%r12), %xmm0
cvtss2sd %xmm0, %xmm0
movsd .LC6(%rip), %xmm1
comisd %xmm0, %xmm1
jb .L46
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %r15, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq %r14, %xmm1
divsd %xmm1, %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L49
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L49:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z8multiplyPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z8multiplyPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.align 4
.LC2:
.long 1232348160
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC6:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "assign1.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI0_1:
.long 0x49742400 # float 1.0E+6
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI0_2:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI0_0(%rip), %xmm0
movss %xmm0, (%rbx,%r14,4)
incq %r14
cmpq $1048576, %r14 # imm = 0x100000
jne .LBB0_1
# %bb.2: # %_Z13random_floatsPfi.exit
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_3: # %.lr.ph.i22
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI0_0(%rip), %xmm0
movss %xmm0, (%r14,%r15,4)
incq %r15
cmpq $1048576, %r15 # imm = 0x100000
jne .LBB0_3
# %bb.4: # %_Z13random_floatsPfi.exit26
movabsq $7308613717771767875, %rax # imm = 0x656D697420555043
movq %rax, 41(%rsp)
movl $1634956576, 49(%rsp) # imm = 0x61737520
movw $25959, 53(%rsp) # imm = 0x6567
movb $0, 55(%rsp)
movabsq $7308613717771767879, %rax # imm = 0x656D697420555047
movq %rax, 26(%rsp)
movl $1634956576, 34(%rsp) # imm = 0x61737520
movw $25959, 38(%rsp) # imm = 0x6567
movb $0, 40(%rsp)
xorl %r13d, %r13d
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %r12
movq 8(%rsp), %r15
xorps %xmm1, %xmm1
.p2align 4, 0x90
.LBB0_5: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%r14,%r13,4), %xmm0
addss %xmm0, %xmm1
incq %r13
cmpq $1048576, %r13 # imm = 0x100000
jne .LBB0_5
# %bb.6: # %_Z11CPU_big_dotPfS_i.exit
movq %rsp, %rdi
xorl %esi, %esi
movss %xmm1, 16(%rsp) # 4-byte Spill
callq gettimeofday
movq (%rsp), %rax
subq %r12, %rax
movq 8(%rsp), %rcx
subq %r15, %rcx
imulq $1000000, %rax, %r12 # imm = 0xF4240
addq %rcx, %r12
xorps %xmm0, %xmm0
cvtsi2ss %r12, %xmm0
divss .LCPI0_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq 41(%rsp), %rsi
movl $.L.str.5, %edi
movb $1, %al
callq printf
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %r13
movq 8(%rsp), %rbp
movq %rbx, %rdi
movq %r14, %rsi
movl $1048576, %edx # imm = 0x100000
callq _Z11GPU_big_dotPfS_i
movq %rax, %r15
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rax
subq %r13, %rax
movq 8(%rsp), %rcx
subq %rbp, %rcx
imulq $1000000, %rax, %r13 # imm = 0xF4240
addq %rcx, %r13
xorps %xmm0, %xmm0
cvtsi2ss %r13, %xmm0
divss .LCPI0_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq 26(%rsp), %rsi
movl $.L.str.5, %edi
movb $1, %al
callq printf
movss 16(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movss (%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, 20(%rsp) # 4-byte Spill
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movss 16(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
subss 20(%rsp), %xmm0 # 4-byte Folded Reload
cvtss2sd %xmm0, %xmm0
movsd .LCPI0_2(%rip), %xmm1 # xmm1 = mem[0],zero
ucomisd %xmm0, %xmm1
jb .LBB0_8
# %bb.7:
movl $.L.str.2, %edi
movb $1, %al
callq printf
xorps %xmm0, %xmm0
cvtsi2sd %r12, %xmm0
xorps %xmm1, %xmm1
cvtsi2sd %r13, %xmm1
divsd %xmm1, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_8:
.cfi_def_cfa_offset 112
movl $.L.str.3, %edi
movb $1, %al
callq printf
movl $-1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z13random_floatsPfi
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z13random_floatsPfi
.p2align 4, 0x90
.type _Z13random_floatsPfi,@function
_Z13random_floatsPfi: # @_Z13random_floatsPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z13random_floatsPfi, .Lfunc_end1-_Z13random_floatsPfi
.cfi_endproc
# -- End function
.globl _Z11start_timerv # -- Begin function _Z11start_timerv
.p2align 4, 0x90
.type _Z11start_timerv,@function
_Z11start_timerv: # @_Z11start_timerv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, 8(%rsp), %rax # imm = 0xF4240
addq 16(%rsp), %rax
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z11start_timerv, .Lfunc_end2-_Z11start_timerv
.cfi_endproc
# -- End function
.globl _Z11CPU_big_dotPfS_i # -- Begin function _Z11CPU_big_dotPfS_i
.p2align 4, 0x90
.type _Z11CPU_big_dotPfS_i,@function
_Z11CPU_big_dotPfS_i: # @_Z11CPU_big_dotPfS_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movq %rsi, %rbx
movq %rdi, %r14
movl $4, %edi
callq malloc
movl $0, (%rax)
testl %ebp, %ebp
jle .LBB3_4
# %bb.1: # %.lr.ph
movss (%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
movl %ebp, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_2: # =>This Inner Loop Header: Depth=1
movss (%r14,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rbx,%rdx,4), %xmm1
addss %xmm1, %xmm0
incq %rdx
cmpq %rdx, %rcx
jne .LBB3_2
# %bb.3: # %._crit_edge
movss %xmm0, (%rax)
.LBB3_4:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z11CPU_big_dotPfS_i, .Lfunc_end3-_Z11CPU_big_dotPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z10stop_timerxPc
.LCPI4_0:
.long 0x49742400 # float 1.0E+6
.text
.globl _Z10stop_timerxPc
.p2align 4, 0x90
.type _Z10stop_timerxPc,@function
_Z10stop_timerxPc: # @_Z10stop_timerxPc
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, (%rsp), %rax # imm = 0xF4240
movq 8(%rsp), %r15
subq %r14, %r15
addq %rax, %r15
cvtsi2ss %r15, %xmm0
divss .LCPI4_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movq %rbx, %rsi
movb $1, %al
callq printf
movq %r15, %rax
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z10stop_timerxPc, .Lfunc_end4-_Z10stop_timerxPc
.cfi_endproc
# -- End function
.globl _Z11GPU_big_dotPfS_i # -- Begin function _Z11GPU_big_dotPfS_i
.p2align 4, 0x90
.type _Z11GPU_big_dotPfS_i,@function
_Z11GPU_big_dotPfS_i: # @_Z11GPU_big_dotPfS_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %edx, %r15d
movq %rsi, %r13
movq %rdi, %r14
movl $4, %edi
callq malloc
movq %rax, %rbx
movl $0, (%rax)
leal (,%r15,4), %eax
movslq %eax, %r12
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r13, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
leal 511(%r15), %eax
leal 1022(%r15), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r15d, 28(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8multiplyPfS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
testl %r15d, %r15d
jle .LBB5_6
# %bb.3: # %.lr.ph
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
movl %r15d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB5_4: # =>This Inner Loop Header: Depth=1
addss (%r14,%rcx,4), %xmm0
incq %rcx
cmpq %rcx, %rax
jne .LBB5_4
# %bb.5: # %._crit_edge
movss %xmm0, (%rbx)
.LBB5_6:
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z11GPU_big_dotPfS_i, .Lfunc_end5-_Z11GPU_big_dotPfS_i
.cfi_endproc
# -- End function
.globl _Z23__device_stub__multiplyPfS_i # -- Begin function _Z23__device_stub__multiplyPfS_i
.p2align 4, 0x90
.type _Z23__device_stub__multiplyPfS_i,@function
_Z23__device_stub__multiplyPfS_i: # @_Z23__device_stub__multiplyPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8multiplyPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end6:
.size _Z23__device_stub__multiplyPfS_i, .Lfunc_end6-_Z23__device_stub__multiplyPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8multiplyPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\ncpu result: %f\n"
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "gpu result: %f\n"
.size .L.str.1, 16
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "difference between 2 results is: %f < 1.0e-6 ===> correct.\n"
.size .L.str.2, 60
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "difference between 2 results is: %f > 1.0e-6 ===> incorrect.\nExit Now!\n"
.size .L.str.3, 72
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\nCPU/GPU speedup: %f\n"
.size .L.str.4, 22
.type _Z8multiplyPfS_i,@object # @_Z8multiplyPfS_i
.section .rodata,"a",@progbits
.globl _Z8multiplyPfS_i
.p2align 3, 0x0
_Z8multiplyPfS_i:
.quad _Z23__device_stub__multiplyPfS_i
.size _Z8multiplyPfS_i, 8
.type .L.str.5,@object # @.str.5
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.5:
.asciz "%s: %.5f sec\n"
.size .L.str.5, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8multiplyPfS_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__multiplyPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8multiplyPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdint.h>
#define BDIM 32
#define ITERTOT 1024
extern "C" __global__ void
__launch_bounds__(32, 1)
arr_kernel(int *inptr, int *outptr) {
int x = threadIdx.x;
int a = inptr[x];
uint32_t start = 0;
uint32_t stop = 0;
int b;
asm volatile ("mov.u32 %0, %%clock;" : "=r"(start) :: "memory");
#pragma unroll 8
for (uint32_t i = 0; i < ITERTOT; ++i) {
asm volatile ("{\n"
".reg .u32 t1;\n"
"shfl.sync.down.b32 t1, %1, 4, 31, -1;\n"
"add.s32 %0, t1, 1;\n"
"}\n"
: "=r"(b) : "r"(a) : "memory");
a = b;
// outptr[x] = __shfl_down_sync(0xFFFFFFFF, a, 4, 32) + 1;
}
asm volatile ("mov.u32 %0, %%clock;" : "=r"(stop) :: "memory");
outptr[x] = b;
if (threadIdx.x == 0)
outptr[x] = stop - start;
} | code for sm_80
Function : arr_kernel
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE R2, R9, R2, c[0x0][0x160] ; /* 0x0000580009027625 */
/* 0x001fca00078e0202 */
/*0050*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000162000c1e1900 */
/*0060*/ SHF.R.S32.HI R10, RZ, 0x1f, R9 ; /* 0x0000001fff0a7819 */
/* 0x000fca0000011409 */
/*0070*/ S2UR UR6, SR_CLOCKLO ; /* 0x00000000000679c3 */
/* 0x000e640000005000 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fc800078e00ff */
/*0090*/ SHFL.DOWN PT, R5, R5, 0x4, 0x1f ; /* 0x08801f0005057f89 */
/* 0x020ea200000e0000 */
/*00a0*/ IADD3 R0, R0, 0x8, RZ ; /* 0x0000000800007810 */
/* 0x000fc80007ffe0ff */
/*00b0*/ ISETP.NE.AND P0, PT, R0, 0x400, PT ; /* 0x000004000000780c */
/* 0x000fe40003f05270 */
/*00c0*/ IADD3 R2, R5, 0x1, RZ ; /* 0x0000000105027810 */
/* 0x005fcc0007ffe0ff */
/*00d0*/ SHFL.DOWN PT, R2, R2, 0x4, 0x1f ; /* 0x08801f0002027f89 */
/* 0x000e2400000e0000 */
/*00e0*/ IADD3 R3, R2, 0x1, RZ ; /* 0x0000000102037810 */
/* 0x001fcc0007ffe0ff */
/*00f0*/ SHFL.DOWN PT, R3, R3, 0x4, 0x1f ; /* 0x08801f0003037f89 */
/* 0x000e2400000e0000 */
/*0100*/ IADD3 R4, R3, 0x1, RZ ; /* 0x0000000103047810 */
/* 0x001fcc0007ffe0ff */
/*0110*/ SHFL.DOWN PT, R4, R4, 0x4, 0x1f ; /* 0x08801f0004047f89 */
/* 0x000e2400000e0000 */
/*0120*/ IADD3 R6, R4, 0x1, RZ ; /* 0x0000000104067810 */
/* 0x001fcc0007ffe0ff */
/*0130*/ SHFL.DOWN PT, R6, R6, 0x4, 0x1f ; /* 0x08801f0006067f89 */
/* 0x000e2400000e0000 */
/*0140*/ IADD3 R7, R6, 0x1, RZ ; /* 0x0000000106077810 */
/* 0x001fcc0007ffe0ff */
/*0150*/ SHFL.DOWN PT, R7, R7, 0x4, 0x1f ; /* 0x08801f0007077f89 */
/* 0x000e2400000e0000 */
/*0160*/ IADD3 R8, R7, 0x1, RZ ; /* 0x0000000107087810 */
/* 0x001fcc0007ffe0ff */
/*0170*/ SHFL.DOWN PT, R8, R8, 0x4, 0x1f ; /* 0x08801f0008087f89 */
/* 0x000e2400000e0000 */
/*0180*/ IADD3 R2, R8, 0x1, RZ ; /* 0x0000000108027810 */
/* 0x001fcc0007ffe0ff */
/*0190*/ SHFL.DOWN PT, R2, R2, 0x4, 0x1f ; /* 0x08801f0002027f89 */
/* 0x000e2400000e0000 */
/*01a0*/ IADD3 R5, R2, 0x1, RZ ; /* 0x0000000102057810 */
/* 0x001fe20007ffe0ff */
/*01b0*/ @P0 BRA 0x90 ; /* 0xfffffed000000947 */
/* 0x000fea000383ffff */
/*01c0*/ CS2R.32 R0, SR_CLOCKLO ; /* 0x0000000000007805 */
/* 0x000fe40000005000 */
/*01d0*/ ISETP.NE.AND P0, PT, R9.reuse, RZ, PT ; /* 0x000000ff0900720c */
/* 0x040fe40003f05270 */
/*01e0*/ LEA R2, P1, R9, c[0x0][0x168], 0x2 ; /* 0x00005a0009027a11 */
/* 0x000fc800078210ff */
/*01f0*/ LEA.HI.X R3, R9, c[0x0][0x16c], R10, 0x2, P1 ; /* 0x00005b0009037a11 */
/* 0x000fca00008f140a */
/*0200*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c101904 */
/*0210*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0220*/ IADD3 R5, R0, -UR6, RZ ; /* 0x8000000600057c10 */
/* 0x003fe2000fffe0ff */
/*0230*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe400078e00ff */
/*0240*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fca00078e00ff */
/*0250*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ BRA 0x270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdint.h>
#define BDIM 32
#define ITERTOT 1024
extern "C" __global__ void
__launch_bounds__(32, 1)
arr_kernel(int *inptr, int *outptr) {
int x = threadIdx.x;
int a = inptr[x];
uint32_t start = 0;
uint32_t stop = 0;
int b;
asm volatile ("mov.u32 %0, %%clock;" : "=r"(start) :: "memory");
#pragma unroll 8
for (uint32_t i = 0; i < ITERTOT; ++i) {
asm volatile ("{\n"
".reg .u32 t1;\n"
"shfl.sync.down.b32 t1, %1, 4, 31, -1;\n"
"add.s32 %0, t1, 1;\n"
"}\n"
: "=r"(b) : "r"(a) : "memory");
a = b;
// outptr[x] = __shfl_down_sync(0xFFFFFFFF, a, 4, 32) + 1;
}
asm volatile ("mov.u32 %0, %%clock;" : "=r"(stop) :: "memory");
outptr[x] = b;
if (threadIdx.x == 0)
outptr[x] = stop - start;
} | .file "tmpxft_001748d0_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z10arr_kernelPiS_PiS_
.type _Z32__device_stub__Z10arr_kernelPiS_PiS_, @function
_Z32__device_stub__Z10arr_kernelPiS_PiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq arr_kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z10arr_kernelPiS_PiS_, .-_Z32__device_stub__Z10arr_kernelPiS_PiS_
.globl arr_kernel
.type arr_kernel, @function
arr_kernel:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10arr_kernelPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size arr_kernel, .-arr_kernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "arr_kernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq arr_kernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdint.h>
#define BDIM 32
#define ITERTOT 1024
extern "C" __global__ void
__launch_bounds__(32, 1)
arr_kernel(int *inptr, int *outptr) {
int x = threadIdx.x;
int a = inptr[x];
uint32_t start = 0;
uint32_t stop = 0;
int b;
asm volatile ("mov.u32 %0, %%clock;" : "=r"(start) :: "memory");
#pragma unroll 8
for (uint32_t i = 0; i < ITERTOT; ++i) {
asm volatile ("{\n"
".reg .u32 t1;\n"
"shfl.sync.down.b32 t1, %1, 4, 31, -1;\n"
"add.s32 %0, t1, 1;\n"
"}\n"
: "=r"(b) : "r"(a) : "memory");
a = b;
// outptr[x] = __shfl_down_sync(0xFFFFFFFF, a, 4, 32) + 1;
}
asm volatile ("mov.u32 %0, %%clock;" : "=r"(stop) :: "memory");
outptr[x] = b;
if (threadIdx.x == 0)
outptr[x] = stop - start;
} | #include <hip/hip_runtime.h>
#include <stdint.h>
#define BDIM 32
#define ITERTOT 1024
extern "C" __global__ void
__launch_bounds__(32, 1)
arr_kernel(int *inptr, int *outptr) {
int x = threadIdx.x;
int a = inptr[x];
uint32_t start = 0;
uint32_t stop = 0;
int b;
asm volatile ("mov.u32 %0, %%clock;" : "=r"(start) :: "memory");
#pragma unroll 8
for (uint32_t i = 0; i < ITERTOT; ++i) {
asm volatile ("{\n"
".reg .u32 t1;\n"
"shfl.sync.down.b32 t1, %1, 4, 31, -1;\n"
"add.s32 %0, t1, 1;\n"
"}\n"
: "=r"(b) : "r"(a) : "memory");
a = b;
// outptr[x] = __shfl_down_sync(0xFFFFFFFF, a, 4, 32) + 1;
}
asm volatile ("mov.u32 %0, %%clock;" : "=r"(stop) :: "memory");
outptr[x] = b;
if (threadIdx.x == 0)
outptr[x] = stop - start;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdint.h>
#define BDIM 32
#define ITERTOT 1024
extern "C" __global__ void
__launch_bounds__(32, 1)
arr_kernel(int *inptr, int *outptr) {
int x = threadIdx.x;
int a = inptr[x];
uint32_t start = 0;
uint32_t stop = 0;
int b;
asm volatile ("mov.u32 %0, %%clock;" : "=r"(start) :: "memory");
#pragma unroll 8
for (uint32_t i = 0; i < ITERTOT; ++i) {
asm volatile ("{\n"
".reg .u32 t1;\n"
"shfl.sync.down.b32 t1, %1, 4, 31, -1;\n"
"add.s32 %0, t1, 1;\n"
"}\n"
: "=r"(b) : "r"(a) : "memory");
a = b;
// outptr[x] = __shfl_down_sync(0xFFFFFFFF, a, 4, 32) + 1;
}
asm volatile ("mov.u32 %0, %%clock;" : "=r"(stop) :: "memory");
outptr[x] = b;
if (threadIdx.x == 0)
outptr[x] = stop - start;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected arr_kernel
.globl arr_kernel
.p2align 8
.type arr_kernel,@function
arr_kernel:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v1, s[2:3]
mov.u32 s2, %clock
s_movk_i32 s3, 0x400
.LBB0_1:
s_waitcnt vmcnt(0)
.reg .u32 t1
shfl.sync.down.b32 t1, v1, 4, 31, -1
add.s32 s4, t1, 1
.reg .u32 t1
shfl.sync.down.b32 t1, s4, 4, 31, -1
add.s32 s4, t1, 1
.reg .u32 t1
shfl.sync.down.b32 t1, s4, 4, 31, -1
add.s32 s4, t1, 1
.reg .u32 t1
shfl.sync.down.b32 t1, s4, 4, 31, -1
add.s32 s4, t1, 1
.reg .u32 t1
shfl.sync.down.b32 t1, s4, 4, 31, -1
add.s32 s4, t1, 1
.reg .u32 t1
shfl.sync.down.b32 t1, s4, 4, 31, -1
add.s32 s4, t1, 1
.reg .u32 t1
shfl.sync.down.b32 t1, s4, 4, 31, -1
add.s32 s4, t1, 1
.reg .u32 t1
shfl.sync.down.b32 t1, s4, 4, 31, -1
add.s32 s4, t1, 1
v_mov_b32_e32 v1, s4
s_add_i32 s3, s3, -8
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s3, 0
s_cbranch_scc0 .LBB0_1
s_load_b64 s[0:1], s[0:1], 0x8
mov.u32 s3, %clock
s_sub_i32 s2, s3, s2
v_cmp_eq_u32_e32 vcc_lo, 0, v0
v_dual_mov_b32 v1, s2 :: v_dual_lshlrev_b32 v0, 2, v0
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e32 v1, s4, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel arr_kernel
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size arr_kernel, .Lfunc_end0-arr_kernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 32
.name: arr_kernel
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: arr_kernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdint.h>
#define BDIM 32
#define ITERTOT 1024
extern "C" __global__ void
__launch_bounds__(32, 1)
arr_kernel(int *inptr, int *outptr) {
int x = threadIdx.x;
int a = inptr[x];
uint32_t start = 0;
uint32_t stop = 0;
int b;
asm volatile ("mov.u32 %0, %%clock;" : "=r"(start) :: "memory");
#pragma unroll 8
for (uint32_t i = 0; i < ITERTOT; ++i) {
asm volatile ("{\n"
".reg .u32 t1;\n"
"shfl.sync.down.b32 t1, %1, 4, 31, -1;\n"
"add.s32 %0, t1, 1;\n"
"}\n"
: "=r"(b) : "r"(a) : "memory");
a = b;
// outptr[x] = __shfl_down_sync(0xFFFFFFFF, a, 4, 32) + 1;
}
asm volatile ("mov.u32 %0, %%clock;" : "=r"(stop) :: "memory");
outptr[x] = b;
if (threadIdx.x == 0)
outptr[x] = stop - start;
} | .text
.file "kernel.hip"
.globl __device_stub__arr_kernel # -- Begin function __device_stub__arr_kernel
.p2align 4, 0x90
.type __device_stub__arr_kernel,@function
__device_stub__arr_kernel: # @__device_stub__arr_kernel
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $arr_kernel, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size __device_stub__arr_kernel, .Lfunc_end0-__device_stub__arr_kernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $arr_kernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type arr_kernel,@object # @arr_kernel
.section .rodata,"a",@progbits
.globl arr_kernel
.p2align 3, 0x0
arr_kernel:
.quad __device_stub__arr_kernel
.size arr_kernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "arr_kernel"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__arr_kernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym arr_kernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : arr_kernel
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE R2, R9, R2, c[0x0][0x160] ; /* 0x0000580009027625 */
/* 0x001fca00078e0202 */
/*0050*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000162000c1e1900 */
/*0060*/ SHF.R.S32.HI R10, RZ, 0x1f, R9 ; /* 0x0000001fff0a7819 */
/* 0x000fca0000011409 */
/*0070*/ S2UR UR6, SR_CLOCKLO ; /* 0x00000000000679c3 */
/* 0x000e640000005000 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fc800078e00ff */
/*0090*/ SHFL.DOWN PT, R5, R5, 0x4, 0x1f ; /* 0x08801f0005057f89 */
/* 0x020ea200000e0000 */
/*00a0*/ IADD3 R0, R0, 0x8, RZ ; /* 0x0000000800007810 */
/* 0x000fc80007ffe0ff */
/*00b0*/ ISETP.NE.AND P0, PT, R0, 0x400, PT ; /* 0x000004000000780c */
/* 0x000fe40003f05270 */
/*00c0*/ IADD3 R2, R5, 0x1, RZ ; /* 0x0000000105027810 */
/* 0x005fcc0007ffe0ff */
/*00d0*/ SHFL.DOWN PT, R2, R2, 0x4, 0x1f ; /* 0x08801f0002027f89 */
/* 0x000e2400000e0000 */
/*00e0*/ IADD3 R3, R2, 0x1, RZ ; /* 0x0000000102037810 */
/* 0x001fcc0007ffe0ff */
/*00f0*/ SHFL.DOWN PT, R3, R3, 0x4, 0x1f ; /* 0x08801f0003037f89 */
/* 0x000e2400000e0000 */
/*0100*/ IADD3 R4, R3, 0x1, RZ ; /* 0x0000000103047810 */
/* 0x001fcc0007ffe0ff */
/*0110*/ SHFL.DOWN PT, R4, R4, 0x4, 0x1f ; /* 0x08801f0004047f89 */
/* 0x000e2400000e0000 */
/*0120*/ IADD3 R6, R4, 0x1, RZ ; /* 0x0000000104067810 */
/* 0x001fcc0007ffe0ff */
/*0130*/ SHFL.DOWN PT, R6, R6, 0x4, 0x1f ; /* 0x08801f0006067f89 */
/* 0x000e2400000e0000 */
/*0140*/ IADD3 R7, R6, 0x1, RZ ; /* 0x0000000106077810 */
/* 0x001fcc0007ffe0ff */
/*0150*/ SHFL.DOWN PT, R7, R7, 0x4, 0x1f ; /* 0x08801f0007077f89 */
/* 0x000e2400000e0000 */
/*0160*/ IADD3 R8, R7, 0x1, RZ ; /* 0x0000000107087810 */
/* 0x001fcc0007ffe0ff */
/*0170*/ SHFL.DOWN PT, R8, R8, 0x4, 0x1f ; /* 0x08801f0008087f89 */
/* 0x000e2400000e0000 */
/*0180*/ IADD3 R2, R8, 0x1, RZ ; /* 0x0000000108027810 */
/* 0x001fcc0007ffe0ff */
/*0190*/ SHFL.DOWN PT, R2, R2, 0x4, 0x1f ; /* 0x08801f0002027f89 */
/* 0x000e2400000e0000 */
/*01a0*/ IADD3 R5, R2, 0x1, RZ ; /* 0x0000000102057810 */
/* 0x001fe20007ffe0ff */
/*01b0*/ @P0 BRA 0x90 ; /* 0xfffffed000000947 */
/* 0x000fea000383ffff */
/*01c0*/ CS2R.32 R0, SR_CLOCKLO ; /* 0x0000000000007805 */
/* 0x000fe40000005000 */
/*01d0*/ ISETP.NE.AND P0, PT, R9.reuse, RZ, PT ; /* 0x000000ff0900720c */
/* 0x040fe40003f05270 */
/*01e0*/ LEA R2, P1, R9, c[0x0][0x168], 0x2 ; /* 0x00005a0009027a11 */
/* 0x000fc800078210ff */
/*01f0*/ LEA.HI.X R3, R9, c[0x0][0x16c], R10, 0x2, P1 ; /* 0x00005b0009037a11 */
/* 0x000fca00008f140a */
/*0200*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c101904 */
/*0210*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0220*/ IADD3 R5, R0, -UR6, RZ ; /* 0x8000000600057c10 */
/* 0x003fe2000fffe0ff */
/*0230*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe400078e00ff */
/*0240*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fca00078e00ff */
/*0250*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ BRA 0x270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected arr_kernel
.globl arr_kernel
.p2align 8
.type arr_kernel,@function
arr_kernel:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v1, s[2:3]
mov.u32 s2, %clock
s_movk_i32 s3, 0x400
.LBB0_1:
s_waitcnt vmcnt(0)
.reg .u32 t1
shfl.sync.down.b32 t1, v1, 4, 31, -1
add.s32 s4, t1, 1
.reg .u32 t1
shfl.sync.down.b32 t1, s4, 4, 31, -1
add.s32 s4, t1, 1
.reg .u32 t1
shfl.sync.down.b32 t1, s4, 4, 31, -1
add.s32 s4, t1, 1
.reg .u32 t1
shfl.sync.down.b32 t1, s4, 4, 31, -1
add.s32 s4, t1, 1
.reg .u32 t1
shfl.sync.down.b32 t1, s4, 4, 31, -1
add.s32 s4, t1, 1
.reg .u32 t1
shfl.sync.down.b32 t1, s4, 4, 31, -1
add.s32 s4, t1, 1
.reg .u32 t1
shfl.sync.down.b32 t1, s4, 4, 31, -1
add.s32 s4, t1, 1
.reg .u32 t1
shfl.sync.down.b32 t1, s4, 4, 31, -1
add.s32 s4, t1, 1
v_mov_b32_e32 v1, s4
s_add_i32 s3, s3, -8
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s3, 0
s_cbranch_scc0 .LBB0_1
s_load_b64 s[0:1], s[0:1], 0x8
mov.u32 s3, %clock
s_sub_i32 s2, s3, s2
v_cmp_eq_u32_e32 vcc_lo, 0, v0
v_dual_mov_b32 v1, s2 :: v_dual_lshlrev_b32 v0, 2, v0
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e32 v1, s4, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel arr_kernel
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size arr_kernel, .Lfunc_end0-arr_kernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 32
.name: arr_kernel
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: arr_kernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001748d0_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z10arr_kernelPiS_PiS_
.type _Z32__device_stub__Z10arr_kernelPiS_PiS_, @function
_Z32__device_stub__Z10arr_kernelPiS_PiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq arr_kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z10arr_kernelPiS_PiS_, .-_Z32__device_stub__Z10arr_kernelPiS_PiS_
.globl arr_kernel
.type arr_kernel, @function
arr_kernel:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10arr_kernelPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size arr_kernel, .-arr_kernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "arr_kernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq arr_kernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl __device_stub__arr_kernel # -- Begin function __device_stub__arr_kernel
.p2align 4, 0x90
.type __device_stub__arr_kernel,@function
__device_stub__arr_kernel: # @__device_stub__arr_kernel
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $arr_kernel, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size __device_stub__arr_kernel, .Lfunc_end0-__device_stub__arr_kernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $arr_kernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type arr_kernel,@object # @arr_kernel
.section .rodata,"a",@progbits
.globl arr_kernel
.p2align 3, 0x0
arr_kernel:
.quad __device_stub__arr_kernel
.size arr_kernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "arr_kernel"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__arr_kernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym arr_kernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
__global__ void GPU_Matrix_Multiply_Kernel(double *A, double *B, double *C, int N) {
//2D Thread ID
int tx = threadIdx.x;
int ty = threadIdx.y;
//Cvalue stores the C element that is computed by the thread
float Cvalue = 0;
//Looping through to compute entries of C
for(int k = 0; k < N ; ++k) {
float Mdelement = A[ty*N + k];
float Ndelement = B[k*N + tx];
Cvalue += (Mdelement*Ndelement);
}
//Storing the value into C
C[ty*N + tx] = Cvalue;
} | code for sm_80
Function : _Z26GPU_Matrix_Multiply_KernelPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x000fe2000001ff00 */
/*0050*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*0070*/ @!P0 BRA 0xf80 ; /* 0x00000f0000008947 */
/* 0x000fea0003800000 */
/*0080*/ IADD3 R4, R2, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x000fe20007ffe0ff */
/*0090*/ HFMA2.MMA R27, -RZ, RZ, 0, 0 ; /* 0x00000000ff1b7435 */
/* 0x000fe200000001ff */
/*00a0*/ MOV R5, RZ ; /* 0x000000ff00057202 */
/* 0x000fe40000000f00 */
/*00b0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*00c0*/ LOP3.LUT R4, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302047812 */
/* 0x000fd600078ec0ff */
/*00d0*/ @!P0 BRA 0xe10 ; /* 0x00000d3000008947 */
/* 0x000fea0003800000 */
/*00e0*/ IADD3 R6, -R4, c[0x0][0x178], RZ ; /* 0x00005e0004067a10 */
/* 0x000fe20007ffe1ff */
/*00f0*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0100*/ MOV R19, 0x8 ; /* 0x0000000800137802 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD R8, R3, c[0x0][0x178], RZ ; /* 0x00005e0003087a24 */
/* 0x002fe200078e02ff */
/*0120*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*0130*/ MOV R27, RZ ; /* 0x000000ff001b7202 */
/* 0x000fe20000000f00 */
/*0140*/ IMAD.WIDE R18, R0, R19, c[0x0][0x168] ; /* 0x00005a0000127625 */
/* 0x001fe200078e0213 */
/*0150*/ MOV R5, RZ ; /* 0x000000ff00057202 */
/* 0x000fd20000000f00 */
/*0160*/ @!P0 BRA 0xc00 ; /* 0x00000a9000008947 */
/* 0x000fea0003800000 */
/*0170*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0180*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0190*/ @!P1 BRA 0x840 ; /* 0x000006a000009947 */
/* 0x000fea0003800000 */
/*01a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01b0*/ IMAD.WIDE R14, R2, 0x8, R18 ; /* 0x00000008020e7825 */
/* 0x000fe200078e0212 */
/*01c0*/ MOV R16, UR6 ; /* 0x0000000600107c02 */
/* 0x000fe20008000f00 */
/*01d0*/ LDG.E.64 R36, [R18.64] ; /* 0x0000000412247981 */
/* 0x0000a2000c1e1b00 */
/*01e0*/ MOV R17, UR7 ; /* 0x0000000700117c02 */
/* 0x000fc60008000f00 */
/*01f0*/ IMAD.WIDE R30, R2, 0x8, R14 ; /* 0x00000008021e7825 */
/* 0x000fe200078e020e */
/*0200*/ LDG.E.64 R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x0002e6000c1e1b00 */
/*0210*/ IMAD.WIDE R16, R8, 0x8, R16 ; /* 0x0000000808107825 */
/* 0x000fc800078e0210 */
/*0220*/ IMAD.WIDE R28, R2.reuse, 0x8, R30 ; /* 0x00000008021c7825 */
/* 0x040fe200078e021e */
/*0230*/ LDG.E.64 R32, [R16.64+0x10] ; /* 0x0000100410207981 */
/* 0x000e68000c1e1b00 */
/*0240*/ LDG.E.64 R24, [R28.64] ; /* 0x000000041c187981 */
/* 0x000e28000c1e1b00 */
/*0250*/ LDG.E.64 R34, [R16.64] ; /* 0x0000000410227981 */
/* 0x000f28000c1e1b00 */
/*0260*/ LDG.E.64 R12, [R16.64+0x8] ; /* 0x00000804100c7981 */
/* 0x000f68000c1e1b00 */
/*0270*/ LDG.E.64 R30, [R30.64] ; /* 0x000000041e1e7981 */
/* 0x000ea8000c1e1b00 */
/*0280*/ LDG.E.64 R20, [R16.64+0x18] ; /* 0x0000180410147981 */
/* 0x000ea8000c1e1b00 */
/*0290*/ LDG.E.64 R22, [R16.64+0x20] ; /* 0x0000200410167981 */
/* 0x000ee2000c1e1b00 */
/*02a0*/ F2F.F32.F64 R14, R32 ; /* 0x00000020000e7310 */
/* 0x0023e40000301000 */
/*02b0*/ IMAD.WIDE R32, R2, 0x8, R28 ; /* 0x0000000802207825 */
/* 0x002fcc00078e021c */
/*02c0*/ F2F.F32.F64 R19, R24 ; /* 0x0000001800137310 */
/* 0x0011e40000301000 */
/*02d0*/ IMAD.WIDE R24, R2, 0x8, R32 ; /* 0x0000000802187825 */
/* 0x001fcc00078e0220 */
/*02e0*/ F2F.F32.F64 R18, R36 ; /* 0x0000002400127310 */
/* 0x0041e20000301000 */
/*02f0*/ LDG.E.64 R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0002a8000c1e1b00 */
/*0300*/ LDG.E.64 R36, [R32.64] ; /* 0x0000000420247981 */
/* 0x0010a6000c1e1b00 */
/*0310*/ F2F.F32.F64 R9, R34 ; /* 0x0000002200097310 */
/* 0x0108620000301000 */
/*0320*/ LDG.E.64 R32, [R16.64+0x30] ; /* 0x0000300410207981 */
/* 0x001ea8000c1e1b00 */
/*0330*/ LDG.E.64 R34, [R16.64+0x28] ; /* 0x0000280410227981 */
/* 0x010f26000c1e1b00 */
/*0340*/ F2F.F32.F64 R15, R10 ; /* 0x0000000a000f7310 */
/* 0x008ff00000301000 */
/*0350*/ F2F.F32.F64 R12, R12 ; /* 0x0000000c000c7310 */
/* 0x020e220000301000 */
/*0360*/ FFMA R9, R9, R18, R27 ; /* 0x0000001209097223 */
/* 0x002fce000000001b */
/*0370*/ F2F.F32.F64 R11, R30 ; /* 0x0000001e000b7310 */
/* 0x0002e40000301000 */
/*0380*/ IMAD.WIDE R30, R2, 0x8, R24 ; /* 0x00000008021e7825 */
/* 0x002fcc00078e0218 */
/*0390*/ F2F.F32.F64 R10, R20 ; /* 0x00000014000a7310 */
/* 0x000e620000301000 */
/*03a0*/ LDG.E.64 R24, [R16.64+0x38] ; /* 0x0000380410187981 */
/* 0x000f62000c1e1b00 */
/*03b0*/ FFMA R15, R12, R15, R9 ; /* 0x0000000f0c0f7223 */
/* 0x001fe40000000009 */
/*03c0*/ IMAD.WIDE R12, R2, 0x8, R30 ; /* 0x00000008020c7825 */
/* 0x000fe400078e021e */
/*03d0*/ LDG.E.64 R30, [R30.64] ; /* 0x000000041e1e7981 */
/* 0x000f64000c1e1b00 */
/*03e0*/ F2F.F32.F64 R22, R22 ; /* 0x0000001600167310 */
/* 0x000fe40000301000 */
/*03f0*/ LDG.E.64 R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000162000c1e1b00 */
/*0400*/ FFMA R11, R14, R11, R15 ; /* 0x0000000b0e0b7223 */
/* 0x008fc6000000000f */
/*0410*/ LDG.E.64 R14, [R16.64+0x40] ; /* 0x00004004100e7981 */
/* 0x000f62000c1e1b00 */
/*0420*/ FFMA R19, R10, R19, R11 ; /* 0x000000130a137223 */
/* 0x002fe2000000000b */
/*0430*/ F2F.F32.F64 R21, R28 ; /* 0x0000001c00157310 */
/* 0x0043f00000301000 */
/*0440*/ F2F.F32.F64 R7, R36 ; /* 0x0000002400077310 */
/* 0x0004a20000301000 */
/*0450*/ IMAD.WIDE R28, R2, 0x8, R12 ; /* 0x00000008021c7825 */
/* 0x002fca00078e020c */
/*0460*/ LDG.E.64 R10, [R28.64] ; /* 0x000000041c0a7981 */
/* 0x0002e2000c1e1b00 */
/*0470*/ IMAD.WIDE R12, R2, 0x8, R28 ; /* 0x00000008020c7825 */
/* 0x001fe200078e021c */
/*0480*/ F2F.F32.F64 R18, R34 ; /* 0x0000002200127310 */
/* 0x0101240000301000 */
/*0490*/ LDG.E.64 R36, [R16.64+0x48] ; /* 0x0000480410247981 */
/* 0x0044ac000c1e1b00 */
/*04a0*/ F2F.F32.F64 R9, R32 ; /* 0x0000002000097310 */
/* 0x0003e20000301000 */
/*04b0*/ FFMA R7, R22, R7, R19 ; /* 0x0000000716077223 */
/* 0x000fe20000000013 */
/*04c0*/ LDG.E.64 R34, [R12.64] ; /* 0x000000040c227981 */
/* 0x0010a2000c1e1b00 */
/*04d0*/ IMAD.WIDE R32, R2, 0x8, R12 ; /* 0x0000000802207825 */
/* 0x002fc600078e020c */
/*04e0*/ LDG.E.64 R12, [R16.64+0x58] ; /* 0x00005804100c7981 */
/* 0x001ea6000c1e1b00 */
/*04f0*/ IMAD.WIDE R28, R2, 0x8, R32 ; /* 0x00000008021c7825 */
/* 0x000fe200078e0220 */
/*0500*/ LDG.E.64 R22, [R32.64] ; /* 0x0000000420167981 */
/* 0x000ea6000c1e1b00 */
/*0510*/ FFMA R21, R18, R21, R7 ; /* 0x0000001512157223 */
/* 0x010fe40000000007 */
/*0520*/ LDG.E.64 R18, [R28.64] ; /* 0x000000041c127981 */
/* 0x000f22000c1e1b00 */
/*0530*/ F2F.F32.F64 R20, R30 ; /* 0x0000001e00147310 */
/* 0x0200700000301000 */
/*0540*/ F2F.F32.F64 R27, R26 ; /* 0x0000001a001b7310 */
/* 0x000fe20000301000 */
/*0550*/ LDG.E.64 R30, [R16.64+0x50] ; /* 0x00005004101e7981 */
/* 0x00116e000c1e1b00 */
/*0560*/ F2F.F32.F64 R24, R24 ; /* 0x0000001800187310 */
/* 0x000e220000301000 */
/*0570*/ FFMA R9, R9, R20, R21 ; /* 0x0000001409097223 */
/* 0x002fc40000000015 */
/*0580*/ IMAD.WIDE R20, R2, 0x8, R28 ; /* 0x0000000802147825 */
/* 0x000fca00078e021c */
/*0590*/ F2F.F32.F64 R14, R14 ; /* 0x0000000e000e7310 */
/* 0x000fe20000301000 */
/*05a0*/ FFMA R27, R24, R27, R9 ; /* 0x0000001b181b7223 */
/* 0x001fce0000000009 */
/*05b0*/ F2F.F32.F64 R15, R10 ; /* 0x0000000a000f7310 */
/* 0x008e300000301000 */
/*05c0*/ F2F.F32.F64 R11, R22 ; /* 0x00000016000b7310 */
/* 0x0043f00000301000 */
/*05d0*/ F2F.F32.F64 R25, R18 ; /* 0x0000001200197310 */
/* 0x0105e20000301000 */
/*05e0*/ LDG.E.64 R22, [R16.64+0x60] ; /* 0x0000600410167981 */
/* 0x002ee8000c1e1b00 */
/*05f0*/ LDG.E.64 R18, [R20.64] ; /* 0x0000000414127981 */
/* 0x0042a6000c1e1b00 */
/*0600*/ F2F.F32.F64 R24, R12 ; /* 0x0000000c00187310 */
/* 0x0009e40000301000 */
/*0610*/ LDG.E.64 R12, [R16.64+0x68] ; /* 0x00006804100c7981 */
/* 0x010f22000c1e1b00 */
/*0620*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x002fc800078e0214 */
/*0630*/ FFMA R27, R14, R15, R27 ; /* 0x0000000f0e1b7223 */
/* 0x001fe2000000001b */
/*0640*/ LDG.E.64 R28, [R20.64] ; /* 0x00000004141c7981 */
/* 0x000162000c1e1b00 */
/*0650*/ F2F.F32.F64 R22, R22 ; /* 0x0000001600167310 */
/* 0x008ff00000301000 */
/*0660*/ F2F.F32.F64 R23, R18 ; /* 0x0000001200177310 */
/* 0x0043e40000301000 */
/*0670*/ IMAD.WIDE R18, R2, 0x8, R20 ; /* 0x0000000802127825 */
/* 0x002fcc00078e0214 */
/*0680*/ F2F.F32.F64 R9, R12 ; /* 0x0000000c00097310 */
/* 0x0103e20000301000 */
/*0690*/ LDG.E.64 R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x0004e8000c1e1b00 */
/*06a0*/ LDG.E.64 R12, [R16.64+0x70] ; /* 0x00007004100c7981 */
/* 0x002322000c1e1b00 */
/*06b0*/ IMAD.WIDE R18, R2, 0x8, R18 ; /* 0x0000000802127825 */
/* 0x004fca00078e0212 */
/*06c0*/ LDG.E.64 R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x0010a8000c1e1b00 */
/*06d0*/ LDG.E.64 R16, [R16.64+0x78] ; /* 0x0000780410107981 */
/* 0x002ea2000c1e1b00 */
/*06e0*/ F2F.F32.F64 R10, R36 ; /* 0x00000024000a7310 */
/* 0x000ff00000301000 */
/*06f0*/ F2F.F32.F64 R7, R34 ; /* 0x0000002200077310 */
/* 0x000e700000301000 */
/*0700*/ F2F.F32.F64 R26, R30 ; /* 0x0000001e001a7310 */
/* 0x020f620000301000 */
/*0710*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fce0007ffe0ff */
/*0720*/ F2F.F32.F64 R28, R28 ; /* 0x0000001c001c7310 */
/* 0x000e220000301000 */
/*0730*/ FFMA R7, R10, R7, R27 ; /* 0x000000070a077223 */
/* 0x002fe2000000001b */
/*0740*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fc60003f24270 */
/*0750*/ FFMA R7, R26, R11, R7 ; /* 0x0000000b1a077223 */
/* 0x020fc80000000007 */
/*0760*/ FFMA R7, R24, R25, R7 ; /* 0x0000001918077223 */
/* 0x000fc80000000007 */
/*0770*/ FFMA R7, R22, R23, R7 ; /* 0x0000001716077223 */
/* 0x000fe20000000007 */
/*0780*/ UIADD3 UR6, UP0, UR6, 0x80, URZ ; /* 0x0000008006067890 */
/* 0x000fc6000ff1e03f */
/*0790*/ FFMA R7, R9, R28, R7 ; /* 0x0000001c09077223 */
/* 0x001fe20000000007 */
/*07a0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*07b0*/ IADD3 R5, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x000fe20007ffe0ff */
/*07c0*/ IMAD.WIDE R18, R2, 0x8, R18 ; /* 0x0000000802127825 */
/* 0x000fe200078e0212 */
/*07d0*/ F2F.F32.F64 R15, R14 ; /* 0x0000000e000f7310 */
/* 0x008ff00000301000 */
/*07e0*/ F2F.F32.F64 R30, R12 ; /* 0x0000000c001e7310 */
/* 0x010e300000301000 */
/*07f0*/ F2F.F32.F64 R20, R20 ; /* 0x0000001400147310 */
/* 0x004ff00000301000 */
/*0800*/ F2F.F32.F64 R10, R16 ; /* 0x00000010000a7310 */
/* 0x000e620000301000 */
/*0810*/ FFMA R7, R30, R15, R7 ; /* 0x0000000f1e077223 */
/* 0x001fc80000000007 */
/*0820*/ FFMA R27, R10, R20, R7 ; /* 0x000000140a1b7223 */
/* 0x002fe20000000007 */
/*0830*/ @P1 BRA 0x1b0 ; /* 0xfffff97000001947 */
/* 0x000fea000383ffff */
/*0840*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0850*/ @!P1 BRA 0xbe0 ; /* 0x0000038000009947 */
/* 0x000fea0003800000 */
/*0860*/ MOV R16, UR6 ; /* 0x0000000600107c02 */
/* 0x000fe20008000f00 */
/*0870*/ LDG.E.64 R22, [R18.64] ; /* 0x0000000412167981 */
/* 0x0000a2000c1e1b00 */
/*0880*/ MOV R17, UR7 ; /* 0x0000000700117c02 */
/* 0x000fe20008000f00 */
/*0890*/ IMAD.WIDE R24, R2, 0x8, R18 ; /* 0x0000000802187825 */
/* 0x000fc800078e0212 */
/*08a0*/ IMAD.WIDE R16, R8, 0x8, R16 ; /* 0x0000000808107825 */
/* 0x000fe200078e0210 */
/*08b0*/ LDG.E.64 R20, [R24.64] ; /* 0x0000000418147981 */
/* 0x000ee6000c1e1b00 */
/*08c0*/ IMAD.WIDE R36, R2.reuse, 0x8, R24 ; /* 0x0000000802247825 */
/* 0x040fe200078e0218 */
/*08d0*/ LDG.E.64 R18, [R16.64+0x10] ; /* 0x0000100410127981 */
/* 0x001f28000c1e1b00 */
/*08e0*/ LDG.E.64 R28, [R16.64] ; /* 0x00000004101c7981 */
/* 0x000f62000c1e1b00 */
/*08f0*/ IMAD.WIDE R12, R2, 0x8, R36 ; /* 0x00000008020c7825 */
/* 0x000fc600078e0224 */
/*0900*/ LDG.E.64 R10, [R16.64+0x8] ; /* 0x00000804100a7981 */
/* 0x0000e6000c1e1b00 */
/*0910*/ IMAD.WIDE R30, R2.reuse, 0x8, R12 ; /* 0x00000008021e7825 */
/* 0x040fe200078e020c */
/*0920*/ LDG.E.64 R34, [R12.64] ; /* 0x000000040c227981 */
/* 0x0002e8000c1e1b00 */
/*0930*/ LDG.E.64 R36, [R36.64] ; /* 0x0000000424247981 */
/* 0x000ee8000c1e1b00 */
/*0940*/ LDG.E.64 R32, [R16.64+0x18] ; /* 0x0000180410207981 */
/* 0x0000e8000c1e1b00 */
/*0950*/ LDG.E.64 R12, [R16.64+0x28] ; /* 0x00002804100c7981 */
/* 0x002ee2000c1e1b00 */
/*0960*/ F2F.F32.F64 R15, R22 ; /* 0x00000016000f7310 */
/* 0x0043e60000301000 */
/*0970*/ LDG.E.64 R22, [R16.64+0x20] ; /* 0x0000200410167981 */
/* 0x0020aa000c1e1b00 */
/*0980*/ F2F.F32.F64 R26, R18 ; /* 0x00000012001a7310 */
/* 0x0103e40000301000 */
/*0990*/ LDG.E.64 R18, [R30.64] ; /* 0x000000041e127981 */
/* 0x002f2c000c1e1b00 */
/*09a0*/ F2F.F32.F64 R14, R28 ; /* 0x0000001c000e7310 */
/* 0x020e700000301000 */
/*09b0*/ F2F.F32.F64 R7, R20 ; /* 0x0000001400077310 */
/* 0x0087e40000301000 */
/*09c0*/ IMAD.WIDE R20, R2, 0x8, R30 ; /* 0x0000000802147825 */
/* 0x008fcc00078e021e */
/*09d0*/ F2F.F32.F64 R9, R12 ; /* 0x0000000c00097310 */
/* 0x0007e20000301000 */
/*09e0*/ FFMA R27, R14, R15, R27 ; /* 0x0000000f0e1b7223 */
/* 0x002fe2000000001b */
/*09f0*/ LDG.E.64 R28, [R20.64] ; /* 0x00000004141c7981 */
/* 0x000368000c1e1b00 */
/*0a00*/ LDG.E.64 R12, [R16.64+0x30] ; /* 0x00003004100c7981 */
/* 0x0080e8000c1e1b00 */
/*0a10*/ LDG.E.64 R16, [R16.64+0x38] ; /* 0x0000380410107981 */
/* 0x001ee2000c1e1b00 */
/*0a20*/ F2F.F32.F64 R22, R22 ; /* 0x0000001600167310 */
/* 0x004ff00000301000 */
/*0a30*/ F2F.F32.F64 R23, R18 ; /* 0x0000001200177310 */
/* 0x0101e40000301000 */
/*0a40*/ IMAD.WIDE R18, R2, 0x8, R20 ; /* 0x0000000802127825 */
/* 0x001fca00078e0214 */
/*0a50*/ LDG.E.64 R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x0000a4000c1e1b00 */
/*0a60*/ IMAD.WIDE R18, R2, 0x8, R18 ; /* 0x0000000802127825 */
/* 0x001fca00078e0212 */
/*0a70*/ LDG.E.64 R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x002122000c1e1b00 */
/*0a80*/ F2F.F32.F64 R10, R10 ; /* 0x0000000a000a7310 */
/* 0x000e700000301000 */
/*0a90*/ F2F.F32.F64 R11, R36 ; /* 0x00000024000b7310 */
/* 0x000e300000301000 */
/*0aa0*/ F2F.F32.F64 R25, R34 ; /* 0x0000002200197310 */
/* 0x000ff00000301000 */
/*0ab0*/ F2F.F32.F64 R24, R32 ; /* 0x0000002000187310 */
/* 0x000ee20000301000 */
/*0ac0*/ FFMA R7, R10, R7, R27 ; /* 0x000000070a077223 */
/* 0x002fce000000001b */
/*0ad0*/ F2F.F32.F64 R28, R28 ; /* 0x0000001c001c7310 */
/* 0x020e620000301000 */
/*0ae0*/ FFMA R7, R26, R11, R7 ; /* 0x0000000b1a077223 */
/* 0x001fce0000000007 */
/*0af0*/ F2F.F32.F64 R30, R12 ; /* 0x0000000c001e7310 */
/* 0x008fe20000301000 */
/*0b00*/ FFMA R7, R24, R25, R7 ; /* 0x0000001918077223 */
/* 0x000fce0000000007 */
/*0b10*/ F2F.F32.F64 R10, R16 ; /* 0x00000010000a7310 */
/* 0x000fe20000301000 */
/*0b20*/ FFMA R7, R22, R23, R7 ; /* 0x0000001716077223 */
/* 0x000fc80000000007 */
/*0b30*/ FFMA R7, R9, R28, R7 ; /* 0x0000001c09077223 */
/* 0x002fe20000000007 */
/*0b40*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0b50*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0b60*/ IMAD.WIDE R18, R2, 0x8, R18 ; /* 0x0000000802127825 */
/* 0x000fe200078e0212 */
/*0b70*/ IADD3 R5, R5, 0x8, RZ ; /* 0x0000000805057810 */
/* 0x000fe40007ffe0ff */
/*0b80*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0b90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ba0*/ F2F.F32.F64 R15, R14 ; /* 0x0000000e000f7310 */
/* 0x004e300000301000 */
/*0bb0*/ F2F.F32.F64 R20, R20 ; /* 0x0000001400147310 */
/* 0x010e620000301000 */
/*0bc0*/ FFMA R7, R30, R15, R7 ; /* 0x0000000f1e077223 */
/* 0x001fc80000000007 */
/*0bd0*/ FFMA R27, R10, R20, R7 ; /* 0x000000140a1b7223 */
/* 0x002fc60000000007 */
/*0be0*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0bf0*/ @!P0 BRA 0xe10 ; /* 0x0000021000008947 */
/* 0x000fea0003800000 */
/*0c00*/ MOV R30, UR6 ; /* 0x00000006001e7c02 */
/* 0x000fe20008000f00 */
/*0c10*/ IMAD.WIDE R10, R2, 0x8, R18 ; /* 0x00000008020a7825 */
/* 0x000fe200078e0212 */
/*0c20*/ MOV R31, UR7 ; /* 0x00000007001f7c02 */
/* 0x000fe20008000f00 */
/*0c30*/ LDG.E.64 R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x0000a8000c1e1b00 */
/*0c40*/ IMAD.WIDE R30, R8, 0x8, R30 ; /* 0x00000008081e7825 */
/* 0x000fc800078e021e */
/*0c50*/ IMAD.WIDE R32, R2.reuse, 0x8, R10 ; /* 0x0000000802207825 */
/* 0x040fe200078e020a */
/*0c60*/ LDG.E.64 R28, [R30.64] ; /* 0x000000041e1c7981 */
/* 0x000ee8000c1e1b00 */
/*0c70*/ LDG.E.64 R22, [R30.64+0x8] ; /* 0x000008041e167981 */
/* 0x000f22000c1e1b00 */
/*0c80*/ IMAD.WIDE R16, R2, 0x8, R32 ; /* 0x0000000802107825 */
/* 0x000fc600078e0220 */
/*0c90*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f68000c1e1b00 */
/*0ca0*/ LDG.E.64 R12, [R32.64] ; /* 0x00000004200c7981 */
/* 0x000f68000c1e1b00 */
/*0cb0*/ LDG.E.64 R14, [R30.64+0x10] ; /* 0x000010041e0e7981 */
/* 0x000f68000c1e1b00 */
/*0cc0*/ LDG.E.64 R18, [R30.64+0x18] ; /* 0x000018041e127981 */
/* 0x001f68000c1e1b00 */
/*0cd0*/ LDG.E.64 R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000f62000c1e1b00 */
/*0ce0*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0cf0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0d00*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0d10*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fc60007ffe0ff */
/*0d20*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0d30*/ F2F.F32.F64 R24, R24 ; /* 0x0000001800187310 */
/* 0x004ff00000301000 */
/*0d40*/ F2F.F32.F64 R28, R28 ; /* 0x0000001c001c7310 */
/* 0x008e300000301000 */
/*0d50*/ F2F.F32.F64 R22, R22 ; /* 0x0000001600167310 */
/* 0x010ff00000301000 */
/*0d60*/ F2F.F32.F64 R7, R10 ; /* 0x0000000a00077310 */
/* 0x020e700000301000 */
/*0d70*/ F2F.F32.F64 R14, R14 ; /* 0x0000000e000e7310 */
/* 0x000ff00000301000 */
/*0d80*/ F2F.F32.F64 R12, R12 ; /* 0x0000000c000c7310 */
/* 0x000ea20000301000 */
/*0d90*/ FFMA R27, R28, R24, R27 ; /* 0x000000181c1b7223 */
/* 0x001fce000000001b */
/*0da0*/ F2F.F32.F64 R18, R18 ; /* 0x0000001200127310 */
/* 0x000ff00000301000 */
/*0db0*/ F2F.F32.F64 R20, R20 ; /* 0x0000001400147310 */
/* 0x000e220000301000 */
/*0dc0*/ FFMA R7, R22, R7, R27 ; /* 0x0000000716077223 */
/* 0x002fc8000000001b */
/*0dd0*/ FFMA R7, R14, R12, R7 ; /* 0x0000000c0e077223 */
/* 0x004fc80000000007 */
/*0de0*/ FFMA R27, R18, R20, R7 ; /* 0x00000014121b7223 */
/* 0x001fe40000000007 */
/*0df0*/ IMAD.WIDE R18, R2, 0x8, R16 ; /* 0x0000000802127825 */
/* 0x000fe200078e0210 */
/*0e00*/ @P0 BRA 0xc00 ; /* 0xfffffdf000000947 */
/* 0x000fea000383ffff */
/*0e10*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0e20*/ @!P0 BRA 0xf70 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0e30*/ HFMA2.MMA R8, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff087435 */
/* 0x000fe200000001ff */
/*0e40*/ IMAD R6, R3, c[0x0][0x178], R5 ; /* 0x00005e0003067a24 */
/* 0x002fe400078e0205 */
/*0e50*/ IMAD R5, R5, c[0x0][0x178], R0 ; /* 0x00005e0005057a24 */
/* 0x001fce00078e0200 */
/*0e60*/ IMAD.WIDE R6, R6, R8, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0208 */
/*0e70*/ IMAD.WIDE R8, R5, R8, c[0x0][0x168] ; /* 0x00005a0005087625 */
/* 0x000fe200078e0208 */
/*0e80*/ MOV R5, R6 ; /* 0x0000000600057202 */
/* 0x000fe40000000f00 */
/*0e90*/ MOV R14, R7 ; /* 0x00000007000e7202 */
/* 0x000fe40000000f00 */
/*0ea0*/ MOV R6, R5 ; /* 0x0000000500067202 */
/* 0x000fe20000000f00 */
/*0eb0*/ LDG.E.64 R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x0000a2000c1e1b00 */
/*0ec0*/ MOV R7, R14 ; /* 0x0000000e00077202 */
/* 0x000fcc0000000f00 */
/*0ed0*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1b00 */
/*0ee0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fc80007ffe0ff */
/*0ef0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*0f00*/ IADD3 R5, P1, R5, 0x8, RZ ; /* 0x0000000805057810 */
/* 0x000fe20007f3e0ff */
/*0f10*/ IMAD.WIDE R8, R2, 0x8, R8 ; /* 0x0000000802087825 */
/* 0x001fc600078e0208 */
/*0f20*/ IADD3.X R14, RZ, R14, RZ, P1, !PT ; /* 0x0000000eff0e7210 */
/* 0x000fe20000ffe4ff */
/*0f30*/ F2F.F32.F64 R10, R10 ; /* 0x0000000a000a7310 */
/* 0x004ff00000301000 */
/*0f40*/ F2F.F32.F64 R12, R6 ; /* 0x00000006000c7310 */
/* 0x008e240000301000 */
/*0f50*/ FFMA R27, R12, R10, R27 ; /* 0x0000000a0c1b7223 */
/* 0x001fe2000000001b */
/*0f60*/ @P0 BRA 0xea0 ; /* 0xffffff3000000947 */
/* 0x000fea000383ffff */
/*0f70*/ F2F.F64.F32 R4, R27 ; /* 0x0000001b00047310 */
/* 0x0004e40000201800 */
/*0f80*/ HFMA2.MMA R2, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff027435 */
/* 0x000fe200000001ff */
/*0f90*/ IMAD R3, R3, c[0x0][0x178], R0 ; /* 0x00005e0003037a24 */
/* 0x003fd200078e0200 */
/*0fa0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0fb0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x008fe2000c101b04 */
/*0fc0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0fd0*/ BRA 0xfd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1000*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
__global__ void GPU_Matrix_Multiply_Kernel(double *A, double *B, double *C, int N) {
//2D Thread ID
int tx = threadIdx.x;
int ty = threadIdx.y;
//Cvalue stores the C element that is computed by the thread
float Cvalue = 0;
//Looping through to compute entries of C
for(int k = 0; k < N ; ++k) {
float Mdelement = A[ty*N + k];
float Ndelement = B[k*N + tx];
Cvalue += (Mdelement*Ndelement);
}
//Storing the value into C
C[ty*N + tx] = Cvalue;
} | .file "tmpxft_000fedd3_00000000-6_gpu_matrix_multiply.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z26GPU_Matrix_Multiply_KernelPdS_S_iPdS_S_i
.type _Z51__device_stub__Z26GPU_Matrix_Multiply_KernelPdS_S_iPdS_S_i, @function
_Z51__device_stub__Z26GPU_Matrix_Multiply_KernelPdS_S_iPdS_S_i:
.LFB2081:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26GPU_Matrix_Multiply_KernelPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z51__device_stub__Z26GPU_Matrix_Multiply_KernelPdS_S_iPdS_S_i, .-_Z51__device_stub__Z26GPU_Matrix_Multiply_KernelPdS_S_iPdS_S_i
.globl _Z26GPU_Matrix_Multiply_KernelPdS_S_i
.type _Z26GPU_Matrix_Multiply_KernelPdS_S_i, @function
_Z26GPU_Matrix_Multiply_KernelPdS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z26GPU_Matrix_Multiply_KernelPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z26GPU_Matrix_Multiply_KernelPdS_S_i, .-_Z26GPU_Matrix_Multiply_KernelPdS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26GPU_Matrix_Multiply_KernelPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26GPU_Matrix_Multiply_KernelPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
__global__ void GPU_Matrix_Multiply_Kernel(double *A, double *B, double *C, int N) {
//2D Thread ID
int tx = threadIdx.x;
int ty = threadIdx.y;
//Cvalue stores the C element that is computed by the thread
float Cvalue = 0;
//Looping through to compute entries of C
for(int k = 0; k < N ; ++k) {
float Mdelement = A[ty*N + k];
float Ndelement = B[k*N + tx];
Cvalue += (Mdelement*Ndelement);
}
//Storing the value into C
C[ty*N + tx] = Cvalue;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void GPU_Matrix_Multiply_Kernel(double *A, double *B, double *C, int N) {
//2D Thread ID
int tx = threadIdx.x;
int ty = threadIdx.y;
//Cvalue stores the C element that is computed by the thread
float Cvalue = 0;
//Looping through to compute entries of C
for(int k = 0; k < N ; ++k) {
float Mdelement = A[ty*N + k];
float Ndelement = B[k*N + tx];
Cvalue += (Mdelement*Ndelement);
}
//Storing the value into C
C[ty*N + tx] = Cvalue;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void GPU_Matrix_Multiply_Kernel(double *A, double *B, double *C, int N) {
//2D Thread ID
int tx = threadIdx.x;
int ty = threadIdx.y;
//Cvalue stores the C element that is computed by the thread
float Cvalue = 0;
//Looping through to compute entries of C
for(int k = 0; k < N ; ++k) {
float Mdelement = A[ty*N + k];
float Ndelement = B[k*N + tx];
Cvalue += (Mdelement*Ndelement);
}
//Storing the value into C
C[ty*N + tx] = Cvalue;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26GPU_Matrix_Multiply_KernelPdS_S_i
.globl _Z26GPU_Matrix_Multiply_KernelPdS_S_i
.p2align 8
.type _Z26GPU_Matrix_Multiply_KernelPdS_S_i,@function
_Z26GPU_Matrix_Multiply_KernelPdS_S_i:
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v3, 0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 3, v[2:3]
v_mov_b32_e32 v2, v1
v_mov_b32_e32 v6, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.p2align 6
.LBB0_2:
v_lshlrev_b64 v[7:8], 3, v[2:3]
v_add_nc_u32_e32 v2, s2, v2
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s3, 0
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b64 v[9:10], v[4:5], off
global_load_b64 v[7:8], v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 8
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(1)
v_cvt_f32_f64_e32 v9, v[9:10]
s_waitcnt vmcnt(0)
v_cvt_f32_f64_e32 v7, v[7:8]
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v6, v9, v7
s_cbranch_scc0 .LBB0_2
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f64_f32_e32 v[2:3], v6
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26GPU_Matrix_Multiply_KernelPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26GPU_Matrix_Multiply_KernelPdS_S_i, .Lfunc_end0-_Z26GPU_Matrix_Multiply_KernelPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26GPU_Matrix_Multiply_KernelPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z26GPU_Matrix_Multiply_KernelPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void GPU_Matrix_Multiply_Kernel(double *A, double *B, double *C, int N) {
//2D Thread ID
int tx = threadIdx.x;
int ty = threadIdx.y;
//Cvalue stores the C element that is computed by the thread
float Cvalue = 0;
//Looping through to compute entries of C
for(int k = 0; k < N ; ++k) {
float Mdelement = A[ty*N + k];
float Ndelement = B[k*N + tx];
Cvalue += (Mdelement*Ndelement);
}
//Storing the value into C
C[ty*N + tx] = Cvalue;
} | .text
.file "gpu_matrix_multiply.hip"
.globl _Z41__device_stub__GPU_Matrix_Multiply_KernelPdS_S_i # -- Begin function _Z41__device_stub__GPU_Matrix_Multiply_KernelPdS_S_i
.p2align 4, 0x90
.type _Z41__device_stub__GPU_Matrix_Multiply_KernelPdS_S_i,@function
_Z41__device_stub__GPU_Matrix_Multiply_KernelPdS_S_i: # @_Z41__device_stub__GPU_Matrix_Multiply_KernelPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26GPU_Matrix_Multiply_KernelPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z41__device_stub__GPU_Matrix_Multiply_KernelPdS_S_i, .Lfunc_end0-_Z41__device_stub__GPU_Matrix_Multiply_KernelPdS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26GPU_Matrix_Multiply_KernelPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26GPU_Matrix_Multiply_KernelPdS_S_i,@object # @_Z26GPU_Matrix_Multiply_KernelPdS_S_i
.section .rodata,"a",@progbits
.globl _Z26GPU_Matrix_Multiply_KernelPdS_S_i
.p2align 3, 0x0
_Z26GPU_Matrix_Multiply_KernelPdS_S_i:
.quad _Z41__device_stub__GPU_Matrix_Multiply_KernelPdS_S_i
.size _Z26GPU_Matrix_Multiply_KernelPdS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26GPU_Matrix_Multiply_KernelPdS_S_i"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__GPU_Matrix_Multiply_KernelPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26GPU_Matrix_Multiply_KernelPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z26GPU_Matrix_Multiply_KernelPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x000fe2000001ff00 */
/*0050*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*0070*/ @!P0 BRA 0xf80 ; /* 0x00000f0000008947 */
/* 0x000fea0003800000 */
/*0080*/ IADD3 R4, R2, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x000fe20007ffe0ff */
/*0090*/ HFMA2.MMA R27, -RZ, RZ, 0, 0 ; /* 0x00000000ff1b7435 */
/* 0x000fe200000001ff */
/*00a0*/ MOV R5, RZ ; /* 0x000000ff00057202 */
/* 0x000fe40000000f00 */
/*00b0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*00c0*/ LOP3.LUT R4, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302047812 */
/* 0x000fd600078ec0ff */
/*00d0*/ @!P0 BRA 0xe10 ; /* 0x00000d3000008947 */
/* 0x000fea0003800000 */
/*00e0*/ IADD3 R6, -R4, c[0x0][0x178], RZ ; /* 0x00005e0004067a10 */
/* 0x000fe20007ffe1ff */
/*00f0*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0100*/ MOV R19, 0x8 ; /* 0x0000000800137802 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD R8, R3, c[0x0][0x178], RZ ; /* 0x00005e0003087a24 */
/* 0x002fe200078e02ff */
/*0120*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*0130*/ MOV R27, RZ ; /* 0x000000ff001b7202 */
/* 0x000fe20000000f00 */
/*0140*/ IMAD.WIDE R18, R0, R19, c[0x0][0x168] ; /* 0x00005a0000127625 */
/* 0x001fe200078e0213 */
/*0150*/ MOV R5, RZ ; /* 0x000000ff00057202 */
/* 0x000fd20000000f00 */
/*0160*/ @!P0 BRA 0xc00 ; /* 0x00000a9000008947 */
/* 0x000fea0003800000 */
/*0170*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0180*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0190*/ @!P1 BRA 0x840 ; /* 0x000006a000009947 */
/* 0x000fea0003800000 */
/*01a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01b0*/ IMAD.WIDE R14, R2, 0x8, R18 ; /* 0x00000008020e7825 */
/* 0x000fe200078e0212 */
/*01c0*/ MOV R16, UR6 ; /* 0x0000000600107c02 */
/* 0x000fe20008000f00 */
/*01d0*/ LDG.E.64 R36, [R18.64] ; /* 0x0000000412247981 */
/* 0x0000a2000c1e1b00 */
/*01e0*/ MOV R17, UR7 ; /* 0x0000000700117c02 */
/* 0x000fc60008000f00 */
/*01f0*/ IMAD.WIDE R30, R2, 0x8, R14 ; /* 0x00000008021e7825 */
/* 0x000fe200078e020e */
/*0200*/ LDG.E.64 R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x0002e6000c1e1b00 */
/*0210*/ IMAD.WIDE R16, R8, 0x8, R16 ; /* 0x0000000808107825 */
/* 0x000fc800078e0210 */
/*0220*/ IMAD.WIDE R28, R2.reuse, 0x8, R30 ; /* 0x00000008021c7825 */
/* 0x040fe200078e021e */
/*0230*/ LDG.E.64 R32, [R16.64+0x10] ; /* 0x0000100410207981 */
/* 0x000e68000c1e1b00 */
/*0240*/ LDG.E.64 R24, [R28.64] ; /* 0x000000041c187981 */
/* 0x000e28000c1e1b00 */
/*0250*/ LDG.E.64 R34, [R16.64] ; /* 0x0000000410227981 */
/* 0x000f28000c1e1b00 */
/*0260*/ LDG.E.64 R12, [R16.64+0x8] ; /* 0x00000804100c7981 */
/* 0x000f68000c1e1b00 */
/*0270*/ LDG.E.64 R30, [R30.64] ; /* 0x000000041e1e7981 */
/* 0x000ea8000c1e1b00 */
/*0280*/ LDG.E.64 R20, [R16.64+0x18] ; /* 0x0000180410147981 */
/* 0x000ea8000c1e1b00 */
/*0290*/ LDG.E.64 R22, [R16.64+0x20] ; /* 0x0000200410167981 */
/* 0x000ee2000c1e1b00 */
/*02a0*/ F2F.F32.F64 R14, R32 ; /* 0x00000020000e7310 */
/* 0x0023e40000301000 */
/*02b0*/ IMAD.WIDE R32, R2, 0x8, R28 ; /* 0x0000000802207825 */
/* 0x002fcc00078e021c */
/*02c0*/ F2F.F32.F64 R19, R24 ; /* 0x0000001800137310 */
/* 0x0011e40000301000 */
/*02d0*/ IMAD.WIDE R24, R2, 0x8, R32 ; /* 0x0000000802187825 */
/* 0x001fcc00078e0220 */
/*02e0*/ F2F.F32.F64 R18, R36 ; /* 0x0000002400127310 */
/* 0x0041e20000301000 */
/*02f0*/ LDG.E.64 R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0002a8000c1e1b00 */
/*0300*/ LDG.E.64 R36, [R32.64] ; /* 0x0000000420247981 */
/* 0x0010a6000c1e1b00 */
/*0310*/ F2F.F32.F64 R9, R34 ; /* 0x0000002200097310 */
/* 0x0108620000301000 */
/*0320*/ LDG.E.64 R32, [R16.64+0x30] ; /* 0x0000300410207981 */
/* 0x001ea8000c1e1b00 */
/*0330*/ LDG.E.64 R34, [R16.64+0x28] ; /* 0x0000280410227981 */
/* 0x010f26000c1e1b00 */
/*0340*/ F2F.F32.F64 R15, R10 ; /* 0x0000000a000f7310 */
/* 0x008ff00000301000 */
/*0350*/ F2F.F32.F64 R12, R12 ; /* 0x0000000c000c7310 */
/* 0x020e220000301000 */
/*0360*/ FFMA R9, R9, R18, R27 ; /* 0x0000001209097223 */
/* 0x002fce000000001b */
/*0370*/ F2F.F32.F64 R11, R30 ; /* 0x0000001e000b7310 */
/* 0x0002e40000301000 */
/*0380*/ IMAD.WIDE R30, R2, 0x8, R24 ; /* 0x00000008021e7825 */
/* 0x002fcc00078e0218 */
/*0390*/ F2F.F32.F64 R10, R20 ; /* 0x00000014000a7310 */
/* 0x000e620000301000 */
/*03a0*/ LDG.E.64 R24, [R16.64+0x38] ; /* 0x0000380410187981 */
/* 0x000f62000c1e1b00 */
/*03b0*/ FFMA R15, R12, R15, R9 ; /* 0x0000000f0c0f7223 */
/* 0x001fe40000000009 */
/*03c0*/ IMAD.WIDE R12, R2, 0x8, R30 ; /* 0x00000008020c7825 */
/* 0x000fe400078e021e */
/*03d0*/ LDG.E.64 R30, [R30.64] ; /* 0x000000041e1e7981 */
/* 0x000f64000c1e1b00 */
/*03e0*/ F2F.F32.F64 R22, R22 ; /* 0x0000001600167310 */
/* 0x000fe40000301000 */
/*03f0*/ LDG.E.64 R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000162000c1e1b00 */
/*0400*/ FFMA R11, R14, R11, R15 ; /* 0x0000000b0e0b7223 */
/* 0x008fc6000000000f */
/*0410*/ LDG.E.64 R14, [R16.64+0x40] ; /* 0x00004004100e7981 */
/* 0x000f62000c1e1b00 */
/*0420*/ FFMA R19, R10, R19, R11 ; /* 0x000000130a137223 */
/* 0x002fe2000000000b */
/*0430*/ F2F.F32.F64 R21, R28 ; /* 0x0000001c00157310 */
/* 0x0043f00000301000 */
/*0440*/ F2F.F32.F64 R7, R36 ; /* 0x0000002400077310 */
/* 0x0004a20000301000 */
/*0450*/ IMAD.WIDE R28, R2, 0x8, R12 ; /* 0x00000008021c7825 */
/* 0x002fca00078e020c */
/*0460*/ LDG.E.64 R10, [R28.64] ; /* 0x000000041c0a7981 */
/* 0x0002e2000c1e1b00 */
/*0470*/ IMAD.WIDE R12, R2, 0x8, R28 ; /* 0x00000008020c7825 */
/* 0x001fe200078e021c */
/*0480*/ F2F.F32.F64 R18, R34 ; /* 0x0000002200127310 */
/* 0x0101240000301000 */
/*0490*/ LDG.E.64 R36, [R16.64+0x48] ; /* 0x0000480410247981 */
/* 0x0044ac000c1e1b00 */
/*04a0*/ F2F.F32.F64 R9, R32 ; /* 0x0000002000097310 */
/* 0x0003e20000301000 */
/*04b0*/ FFMA R7, R22, R7, R19 ; /* 0x0000000716077223 */
/* 0x000fe20000000013 */
/*04c0*/ LDG.E.64 R34, [R12.64] ; /* 0x000000040c227981 */
/* 0x0010a2000c1e1b00 */
/*04d0*/ IMAD.WIDE R32, R2, 0x8, R12 ; /* 0x0000000802207825 */
/* 0x002fc600078e020c */
/*04e0*/ LDG.E.64 R12, [R16.64+0x58] ; /* 0x00005804100c7981 */
/* 0x001ea6000c1e1b00 */
/*04f0*/ IMAD.WIDE R28, R2, 0x8, R32 ; /* 0x00000008021c7825 */
/* 0x000fe200078e0220 */
/*0500*/ LDG.E.64 R22, [R32.64] ; /* 0x0000000420167981 */
/* 0x000ea6000c1e1b00 */
/*0510*/ FFMA R21, R18, R21, R7 ; /* 0x0000001512157223 */
/* 0x010fe40000000007 */
/*0520*/ LDG.E.64 R18, [R28.64] ; /* 0x000000041c127981 */
/* 0x000f22000c1e1b00 */
/*0530*/ F2F.F32.F64 R20, R30 ; /* 0x0000001e00147310 */
/* 0x0200700000301000 */
/*0540*/ F2F.F32.F64 R27, R26 ; /* 0x0000001a001b7310 */
/* 0x000fe20000301000 */
/*0550*/ LDG.E.64 R30, [R16.64+0x50] ; /* 0x00005004101e7981 */
/* 0x00116e000c1e1b00 */
/*0560*/ F2F.F32.F64 R24, R24 ; /* 0x0000001800187310 */
/* 0x000e220000301000 */
/*0570*/ FFMA R9, R9, R20, R21 ; /* 0x0000001409097223 */
/* 0x002fc40000000015 */
/*0580*/ IMAD.WIDE R20, R2, 0x8, R28 ; /* 0x0000000802147825 */
/* 0x000fca00078e021c */
/*0590*/ F2F.F32.F64 R14, R14 ; /* 0x0000000e000e7310 */
/* 0x000fe20000301000 */
/*05a0*/ FFMA R27, R24, R27, R9 ; /* 0x0000001b181b7223 */
/* 0x001fce0000000009 */
/*05b0*/ F2F.F32.F64 R15, R10 ; /* 0x0000000a000f7310 */
/* 0x008e300000301000 */
/*05c0*/ F2F.F32.F64 R11, R22 ; /* 0x00000016000b7310 */
/* 0x0043f00000301000 */
/*05d0*/ F2F.F32.F64 R25, R18 ; /* 0x0000001200197310 */
/* 0x0105e20000301000 */
/*05e0*/ LDG.E.64 R22, [R16.64+0x60] ; /* 0x0000600410167981 */
/* 0x002ee8000c1e1b00 */
/*05f0*/ LDG.E.64 R18, [R20.64] ; /* 0x0000000414127981 */
/* 0x0042a6000c1e1b00 */
/*0600*/ F2F.F32.F64 R24, R12 ; /* 0x0000000c00187310 */
/* 0x0009e40000301000 */
/*0610*/ LDG.E.64 R12, [R16.64+0x68] ; /* 0x00006804100c7981 */
/* 0x010f22000c1e1b00 */
/*0620*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x002fc800078e0214 */
/*0630*/ FFMA R27, R14, R15, R27 ; /* 0x0000000f0e1b7223 */
/* 0x001fe2000000001b */
/*0640*/ LDG.E.64 R28, [R20.64] ; /* 0x00000004141c7981 */
/* 0x000162000c1e1b00 */
/*0650*/ F2F.F32.F64 R22, R22 ; /* 0x0000001600167310 */
/* 0x008ff00000301000 */
/*0660*/ F2F.F32.F64 R23, R18 ; /* 0x0000001200177310 */
/* 0x0043e40000301000 */
/*0670*/ IMAD.WIDE R18, R2, 0x8, R20 ; /* 0x0000000802127825 */
/* 0x002fcc00078e0214 */
/*0680*/ F2F.F32.F64 R9, R12 ; /* 0x0000000c00097310 */
/* 0x0103e20000301000 */
/*0690*/ LDG.E.64 R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x0004e8000c1e1b00 */
/*06a0*/ LDG.E.64 R12, [R16.64+0x70] ; /* 0x00007004100c7981 */
/* 0x002322000c1e1b00 */
/*06b0*/ IMAD.WIDE R18, R2, 0x8, R18 ; /* 0x0000000802127825 */
/* 0x004fca00078e0212 */
/*06c0*/ LDG.E.64 R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x0010a8000c1e1b00 */
/*06d0*/ LDG.E.64 R16, [R16.64+0x78] ; /* 0x0000780410107981 */
/* 0x002ea2000c1e1b00 */
/*06e0*/ F2F.F32.F64 R10, R36 ; /* 0x00000024000a7310 */
/* 0x000ff00000301000 */
/*06f0*/ F2F.F32.F64 R7, R34 ; /* 0x0000002200077310 */
/* 0x000e700000301000 */
/*0700*/ F2F.F32.F64 R26, R30 ; /* 0x0000001e001a7310 */
/* 0x020f620000301000 */
/*0710*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fce0007ffe0ff */
/*0720*/ F2F.F32.F64 R28, R28 ; /* 0x0000001c001c7310 */
/* 0x000e220000301000 */
/*0730*/ FFMA R7, R10, R7, R27 ; /* 0x000000070a077223 */
/* 0x002fe2000000001b */
/*0740*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fc60003f24270 */
/*0750*/ FFMA R7, R26, R11, R7 ; /* 0x0000000b1a077223 */
/* 0x020fc80000000007 */
/*0760*/ FFMA R7, R24, R25, R7 ; /* 0x0000001918077223 */
/* 0x000fc80000000007 */
/*0770*/ FFMA R7, R22, R23, R7 ; /* 0x0000001716077223 */
/* 0x000fe20000000007 */
/*0780*/ UIADD3 UR6, UP0, UR6, 0x80, URZ ; /* 0x0000008006067890 */
/* 0x000fc6000ff1e03f */
/*0790*/ FFMA R7, R9, R28, R7 ; /* 0x0000001c09077223 */
/* 0x001fe20000000007 */
/*07a0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*07b0*/ IADD3 R5, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x000fe20007ffe0ff */
/*07c0*/ IMAD.WIDE R18, R2, 0x8, R18 ; /* 0x0000000802127825 */
/* 0x000fe200078e0212 */
/*07d0*/ F2F.F32.F64 R15, R14 ; /* 0x0000000e000f7310 */
/* 0x008ff00000301000 */
/*07e0*/ F2F.F32.F64 R30, R12 ; /* 0x0000000c001e7310 */
/* 0x010e300000301000 */
/*07f0*/ F2F.F32.F64 R20, R20 ; /* 0x0000001400147310 */
/* 0x004ff00000301000 */
/*0800*/ F2F.F32.F64 R10, R16 ; /* 0x00000010000a7310 */
/* 0x000e620000301000 */
/*0810*/ FFMA R7, R30, R15, R7 ; /* 0x0000000f1e077223 */
/* 0x001fc80000000007 */
/*0820*/ FFMA R27, R10, R20, R7 ; /* 0x000000140a1b7223 */
/* 0x002fe20000000007 */
/*0830*/ @P1 BRA 0x1b0 ; /* 0xfffff97000001947 */
/* 0x000fea000383ffff */
/*0840*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0850*/ @!P1 BRA 0xbe0 ; /* 0x0000038000009947 */
/* 0x000fea0003800000 */
/*0860*/ MOV R16, UR6 ; /* 0x0000000600107c02 */
/* 0x000fe20008000f00 */
/*0870*/ LDG.E.64 R22, [R18.64] ; /* 0x0000000412167981 */
/* 0x0000a2000c1e1b00 */
/*0880*/ MOV R17, UR7 ; /* 0x0000000700117c02 */
/* 0x000fe20008000f00 */
/*0890*/ IMAD.WIDE R24, R2, 0x8, R18 ; /* 0x0000000802187825 */
/* 0x000fc800078e0212 */
/*08a0*/ IMAD.WIDE R16, R8, 0x8, R16 ; /* 0x0000000808107825 */
/* 0x000fe200078e0210 */
/*08b0*/ LDG.E.64 R20, [R24.64] ; /* 0x0000000418147981 */
/* 0x000ee6000c1e1b00 */
/*08c0*/ IMAD.WIDE R36, R2.reuse, 0x8, R24 ; /* 0x0000000802247825 */
/* 0x040fe200078e0218 */
/*08d0*/ LDG.E.64 R18, [R16.64+0x10] ; /* 0x0000100410127981 */
/* 0x001f28000c1e1b00 */
/*08e0*/ LDG.E.64 R28, [R16.64] ; /* 0x00000004101c7981 */
/* 0x000f62000c1e1b00 */
/*08f0*/ IMAD.WIDE R12, R2, 0x8, R36 ; /* 0x00000008020c7825 */
/* 0x000fc600078e0224 */
/*0900*/ LDG.E.64 R10, [R16.64+0x8] ; /* 0x00000804100a7981 */
/* 0x0000e6000c1e1b00 */
/*0910*/ IMAD.WIDE R30, R2.reuse, 0x8, R12 ; /* 0x00000008021e7825 */
/* 0x040fe200078e020c */
/*0920*/ LDG.E.64 R34, [R12.64] ; /* 0x000000040c227981 */
/* 0x0002e8000c1e1b00 */
/*0930*/ LDG.E.64 R36, [R36.64] ; /* 0x0000000424247981 */
/* 0x000ee8000c1e1b00 */
/*0940*/ LDG.E.64 R32, [R16.64+0x18] ; /* 0x0000180410207981 */
/* 0x0000e8000c1e1b00 */
/*0950*/ LDG.E.64 R12, [R16.64+0x28] ; /* 0x00002804100c7981 */
/* 0x002ee2000c1e1b00 */
/*0960*/ F2F.F32.F64 R15, R22 ; /* 0x00000016000f7310 */
/* 0x0043e60000301000 */
/*0970*/ LDG.E.64 R22, [R16.64+0x20] ; /* 0x0000200410167981 */
/* 0x0020aa000c1e1b00 */
/*0980*/ F2F.F32.F64 R26, R18 ; /* 0x00000012001a7310 */
/* 0x0103e40000301000 */
/*0990*/ LDG.E.64 R18, [R30.64] ; /* 0x000000041e127981 */
/* 0x002f2c000c1e1b00 */
/*09a0*/ F2F.F32.F64 R14, R28 ; /* 0x0000001c000e7310 */
/* 0x020e700000301000 */
/*09b0*/ F2F.F32.F64 R7, R20 ; /* 0x0000001400077310 */
/* 0x0087e40000301000 */
/*09c0*/ IMAD.WIDE R20, R2, 0x8, R30 ; /* 0x0000000802147825 */
/* 0x008fcc00078e021e */
/*09d0*/ F2F.F32.F64 R9, R12 ; /* 0x0000000c00097310 */
/* 0x0007e20000301000 */
/*09e0*/ FFMA R27, R14, R15, R27 ; /* 0x0000000f0e1b7223 */
/* 0x002fe2000000001b */
/*09f0*/ LDG.E.64 R28, [R20.64] ; /* 0x00000004141c7981 */
/* 0x000368000c1e1b00 */
/*0a00*/ LDG.E.64 R12, [R16.64+0x30] ; /* 0x00003004100c7981 */
/* 0x0080e8000c1e1b00 */
/*0a10*/ LDG.E.64 R16, [R16.64+0x38] ; /* 0x0000380410107981 */
/* 0x001ee2000c1e1b00 */
/*0a20*/ F2F.F32.F64 R22, R22 ; /* 0x0000001600167310 */
/* 0x004ff00000301000 */
/*0a30*/ F2F.F32.F64 R23, R18 ; /* 0x0000001200177310 */
/* 0x0101e40000301000 */
/*0a40*/ IMAD.WIDE R18, R2, 0x8, R20 ; /* 0x0000000802127825 */
/* 0x001fca00078e0214 */
/*0a50*/ LDG.E.64 R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x0000a4000c1e1b00 */
/*0a60*/ IMAD.WIDE R18, R2, 0x8, R18 ; /* 0x0000000802127825 */
/* 0x001fca00078e0212 */
/*0a70*/ LDG.E.64 R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x002122000c1e1b00 */
/*0a80*/ F2F.F32.F64 R10, R10 ; /* 0x0000000a000a7310 */
/* 0x000e700000301000 */
/*0a90*/ F2F.F32.F64 R11, R36 ; /* 0x00000024000b7310 */
/* 0x000e300000301000 */
/*0aa0*/ F2F.F32.F64 R25, R34 ; /* 0x0000002200197310 */
/* 0x000ff00000301000 */
/*0ab0*/ F2F.F32.F64 R24, R32 ; /* 0x0000002000187310 */
/* 0x000ee20000301000 */
/*0ac0*/ FFMA R7, R10, R7, R27 ; /* 0x000000070a077223 */
/* 0x002fce000000001b */
/*0ad0*/ F2F.F32.F64 R28, R28 ; /* 0x0000001c001c7310 */
/* 0x020e620000301000 */
/*0ae0*/ FFMA R7, R26, R11, R7 ; /* 0x0000000b1a077223 */
/* 0x001fce0000000007 */
/*0af0*/ F2F.F32.F64 R30, R12 ; /* 0x0000000c001e7310 */
/* 0x008fe20000301000 */
/*0b00*/ FFMA R7, R24, R25, R7 ; /* 0x0000001918077223 */
/* 0x000fce0000000007 */
/*0b10*/ F2F.F32.F64 R10, R16 ; /* 0x00000010000a7310 */
/* 0x000fe20000301000 */
/*0b20*/ FFMA R7, R22, R23, R7 ; /* 0x0000001716077223 */
/* 0x000fc80000000007 */
/*0b30*/ FFMA R7, R9, R28, R7 ; /* 0x0000001c09077223 */
/* 0x002fe20000000007 */
/*0b40*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0b50*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0b60*/ IMAD.WIDE R18, R2, 0x8, R18 ; /* 0x0000000802127825 */
/* 0x000fe200078e0212 */
/*0b70*/ IADD3 R5, R5, 0x8, RZ ; /* 0x0000000805057810 */
/* 0x000fe40007ffe0ff */
/*0b80*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0b90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ba0*/ F2F.F32.F64 R15, R14 ; /* 0x0000000e000f7310 */
/* 0x004e300000301000 */
/*0bb0*/ F2F.F32.F64 R20, R20 ; /* 0x0000001400147310 */
/* 0x010e620000301000 */
/*0bc0*/ FFMA R7, R30, R15, R7 ; /* 0x0000000f1e077223 */
/* 0x001fc80000000007 */
/*0bd0*/ FFMA R27, R10, R20, R7 ; /* 0x000000140a1b7223 */
/* 0x002fc60000000007 */
/*0be0*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0bf0*/ @!P0 BRA 0xe10 ; /* 0x0000021000008947 */
/* 0x000fea0003800000 */
/*0c00*/ MOV R30, UR6 ; /* 0x00000006001e7c02 */
/* 0x000fe20008000f00 */
/*0c10*/ IMAD.WIDE R10, R2, 0x8, R18 ; /* 0x00000008020a7825 */
/* 0x000fe200078e0212 */
/*0c20*/ MOV R31, UR7 ; /* 0x00000007001f7c02 */
/* 0x000fe20008000f00 */
/*0c30*/ LDG.E.64 R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x0000a8000c1e1b00 */
/*0c40*/ IMAD.WIDE R30, R8, 0x8, R30 ; /* 0x00000008081e7825 */
/* 0x000fc800078e021e */
/*0c50*/ IMAD.WIDE R32, R2.reuse, 0x8, R10 ; /* 0x0000000802207825 */
/* 0x040fe200078e020a */
/*0c60*/ LDG.E.64 R28, [R30.64] ; /* 0x000000041e1c7981 */
/* 0x000ee8000c1e1b00 */
/*0c70*/ LDG.E.64 R22, [R30.64+0x8] ; /* 0x000008041e167981 */
/* 0x000f22000c1e1b00 */
/*0c80*/ IMAD.WIDE R16, R2, 0x8, R32 ; /* 0x0000000802107825 */
/* 0x000fc600078e0220 */
/*0c90*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f68000c1e1b00 */
/*0ca0*/ LDG.E.64 R12, [R32.64] ; /* 0x00000004200c7981 */
/* 0x000f68000c1e1b00 */
/*0cb0*/ LDG.E.64 R14, [R30.64+0x10] ; /* 0x000010041e0e7981 */
/* 0x000f68000c1e1b00 */
/*0cc0*/ LDG.E.64 R18, [R30.64+0x18] ; /* 0x000018041e127981 */
/* 0x001f68000c1e1b00 */
/*0cd0*/ LDG.E.64 R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000f62000c1e1b00 */
/*0ce0*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0cf0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0d00*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0d10*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fc60007ffe0ff */
/*0d20*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0d30*/ F2F.F32.F64 R24, R24 ; /* 0x0000001800187310 */
/* 0x004ff00000301000 */
/*0d40*/ F2F.F32.F64 R28, R28 ; /* 0x0000001c001c7310 */
/* 0x008e300000301000 */
/*0d50*/ F2F.F32.F64 R22, R22 ; /* 0x0000001600167310 */
/* 0x010ff00000301000 */
/*0d60*/ F2F.F32.F64 R7, R10 ; /* 0x0000000a00077310 */
/* 0x020e700000301000 */
/*0d70*/ F2F.F32.F64 R14, R14 ; /* 0x0000000e000e7310 */
/* 0x000ff00000301000 */
/*0d80*/ F2F.F32.F64 R12, R12 ; /* 0x0000000c000c7310 */
/* 0x000ea20000301000 */
/*0d90*/ FFMA R27, R28, R24, R27 ; /* 0x000000181c1b7223 */
/* 0x001fce000000001b */
/*0da0*/ F2F.F32.F64 R18, R18 ; /* 0x0000001200127310 */
/* 0x000ff00000301000 */
/*0db0*/ F2F.F32.F64 R20, R20 ; /* 0x0000001400147310 */
/* 0x000e220000301000 */
/*0dc0*/ FFMA R7, R22, R7, R27 ; /* 0x0000000716077223 */
/* 0x002fc8000000001b */
/*0dd0*/ FFMA R7, R14, R12, R7 ; /* 0x0000000c0e077223 */
/* 0x004fc80000000007 */
/*0de0*/ FFMA R27, R18, R20, R7 ; /* 0x00000014121b7223 */
/* 0x001fe40000000007 */
/*0df0*/ IMAD.WIDE R18, R2, 0x8, R16 ; /* 0x0000000802127825 */
/* 0x000fe200078e0210 */
/*0e00*/ @P0 BRA 0xc00 ; /* 0xfffffdf000000947 */
/* 0x000fea000383ffff */
/*0e10*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0e20*/ @!P0 BRA 0xf70 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0e30*/ HFMA2.MMA R8, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff087435 */
/* 0x000fe200000001ff */
/*0e40*/ IMAD R6, R3, c[0x0][0x178], R5 ; /* 0x00005e0003067a24 */
/* 0x002fe400078e0205 */
/*0e50*/ IMAD R5, R5, c[0x0][0x178], R0 ; /* 0x00005e0005057a24 */
/* 0x001fce00078e0200 */
/*0e60*/ IMAD.WIDE R6, R6, R8, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0208 */
/*0e70*/ IMAD.WIDE R8, R5, R8, c[0x0][0x168] ; /* 0x00005a0005087625 */
/* 0x000fe200078e0208 */
/*0e80*/ MOV R5, R6 ; /* 0x0000000600057202 */
/* 0x000fe40000000f00 */
/*0e90*/ MOV R14, R7 ; /* 0x00000007000e7202 */
/* 0x000fe40000000f00 */
/*0ea0*/ MOV R6, R5 ; /* 0x0000000500067202 */
/* 0x000fe20000000f00 */
/*0eb0*/ LDG.E.64 R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x0000a2000c1e1b00 */
/*0ec0*/ MOV R7, R14 ; /* 0x0000000e00077202 */
/* 0x000fcc0000000f00 */
/*0ed0*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1b00 */
/*0ee0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fc80007ffe0ff */
/*0ef0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*0f00*/ IADD3 R5, P1, R5, 0x8, RZ ; /* 0x0000000805057810 */
/* 0x000fe20007f3e0ff */
/*0f10*/ IMAD.WIDE R8, R2, 0x8, R8 ; /* 0x0000000802087825 */
/* 0x001fc600078e0208 */
/*0f20*/ IADD3.X R14, RZ, R14, RZ, P1, !PT ; /* 0x0000000eff0e7210 */
/* 0x000fe20000ffe4ff */
/*0f30*/ F2F.F32.F64 R10, R10 ; /* 0x0000000a000a7310 */
/* 0x004ff00000301000 */
/*0f40*/ F2F.F32.F64 R12, R6 ; /* 0x00000006000c7310 */
/* 0x008e240000301000 */
/*0f50*/ FFMA R27, R12, R10, R27 ; /* 0x0000000a0c1b7223 */
/* 0x001fe2000000001b */
/*0f60*/ @P0 BRA 0xea0 ; /* 0xffffff3000000947 */
/* 0x000fea000383ffff */
/*0f70*/ F2F.F64.F32 R4, R27 ; /* 0x0000001b00047310 */
/* 0x0004e40000201800 */
/*0f80*/ HFMA2.MMA R2, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff027435 */
/* 0x000fe200000001ff */
/*0f90*/ IMAD R3, R3, c[0x0][0x178], R0 ; /* 0x00005e0003037a24 */
/* 0x003fd200078e0200 */
/*0fa0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0fb0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x008fe2000c101b04 */
/*0fc0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0fd0*/ BRA 0xfd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1000*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26GPU_Matrix_Multiply_KernelPdS_S_i
.globl _Z26GPU_Matrix_Multiply_KernelPdS_S_i
.p2align 8
.type _Z26GPU_Matrix_Multiply_KernelPdS_S_i,@function
_Z26GPU_Matrix_Multiply_KernelPdS_S_i:
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v3, 0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 3, v[2:3]
v_mov_b32_e32 v2, v1
v_mov_b32_e32 v6, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.p2align 6
.LBB0_2:
v_lshlrev_b64 v[7:8], 3, v[2:3]
v_add_nc_u32_e32 v2, s2, v2
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s3, 0
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b64 v[9:10], v[4:5], off
global_load_b64 v[7:8], v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 8
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(1)
v_cvt_f32_f64_e32 v9, v[9:10]
s_waitcnt vmcnt(0)
v_cvt_f32_f64_e32 v7, v[7:8]
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v6, v9, v7
s_cbranch_scc0 .LBB0_2
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f64_f32_e32 v[2:3], v6
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26GPU_Matrix_Multiply_KernelPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26GPU_Matrix_Multiply_KernelPdS_S_i, .Lfunc_end0-_Z26GPU_Matrix_Multiply_KernelPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26GPU_Matrix_Multiply_KernelPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z26GPU_Matrix_Multiply_KernelPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000fedd3_00000000-6_gpu_matrix_multiply.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z26GPU_Matrix_Multiply_KernelPdS_S_iPdS_S_i
.type _Z51__device_stub__Z26GPU_Matrix_Multiply_KernelPdS_S_iPdS_S_i, @function
_Z51__device_stub__Z26GPU_Matrix_Multiply_KernelPdS_S_iPdS_S_i:
.LFB2081:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26GPU_Matrix_Multiply_KernelPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z51__device_stub__Z26GPU_Matrix_Multiply_KernelPdS_S_iPdS_S_i, .-_Z51__device_stub__Z26GPU_Matrix_Multiply_KernelPdS_S_iPdS_S_i
.globl _Z26GPU_Matrix_Multiply_KernelPdS_S_i
.type _Z26GPU_Matrix_Multiply_KernelPdS_S_i, @function
_Z26GPU_Matrix_Multiply_KernelPdS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z26GPU_Matrix_Multiply_KernelPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z26GPU_Matrix_Multiply_KernelPdS_S_i, .-_Z26GPU_Matrix_Multiply_KernelPdS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26GPU_Matrix_Multiply_KernelPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26GPU_Matrix_Multiply_KernelPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpu_matrix_multiply.hip"
.globl _Z41__device_stub__GPU_Matrix_Multiply_KernelPdS_S_i # -- Begin function _Z41__device_stub__GPU_Matrix_Multiply_KernelPdS_S_i
.p2align 4, 0x90
.type _Z41__device_stub__GPU_Matrix_Multiply_KernelPdS_S_i,@function
_Z41__device_stub__GPU_Matrix_Multiply_KernelPdS_S_i: # @_Z41__device_stub__GPU_Matrix_Multiply_KernelPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26GPU_Matrix_Multiply_KernelPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z41__device_stub__GPU_Matrix_Multiply_KernelPdS_S_i, .Lfunc_end0-_Z41__device_stub__GPU_Matrix_Multiply_KernelPdS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26GPU_Matrix_Multiply_KernelPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26GPU_Matrix_Multiply_KernelPdS_S_i,@object # @_Z26GPU_Matrix_Multiply_KernelPdS_S_i
.section .rodata,"a",@progbits
.globl _Z26GPU_Matrix_Multiply_KernelPdS_S_i
.p2align 3, 0x0
_Z26GPU_Matrix_Multiply_KernelPdS_S_i:
.quad _Z41__device_stub__GPU_Matrix_Multiply_KernelPdS_S_i
.size _Z26GPU_Matrix_Multiply_KernelPdS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26GPU_Matrix_Multiply_KernelPdS_S_i"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__GPU_Matrix_Multiply_KernelPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26GPU_Matrix_Multiply_KernelPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
__global__ void revArray(int N, float *a, float *b) {
int n = threadIdx.x + blockIdx.x*blockDim.x;
if(n<N) {
b[N-1-n] = a[n];
}
}
int main(int argc, char **argv) {
int N = 100;
//Host memory allocation
float *h_a = (float*) malloc(N*sizeof(float));
float *h_b = (float*) malloc(N*sizeof(float));
int n;
for(n=0;n<N;n++) {
h_a[n] = 1+n;
}
// Device memory allocation
float *d_a, *d_b;
cudaMalloc(&d_a, N*sizeof(float));
cudaMalloc(&d_b, N*sizeof(float));
// Copy data from host to device
cudaMemcpy(d_a, h_a, N*sizeof(float), cudaMemcpyHostToDevice);
//save this for later
int NthreadsPerBlock = 10;
int NthreadBlocks = (N+NthreadsPerBlock-1)/NthreadsPerBlock ;
revArray<<<NthreadBlocks, NthreadsPerBlock>>>(N,d_a,d_b);
//copy result from device to host
cudaMemcpy(h_b, d_b, N*sizeof(float), cudaMemcpyDeviceToHost);
for(n=0;n<N;++n) {
printf("h_b[%d] = %g\n",n,h_b[n]);
}
free(h_a);
free(h_b);
cudaFree(d_a);
cudaFree(d_b);
return 0;
} | code for sm_80
Function : _Z8revArrayiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ LOP3.LUT R0, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff007212 */
/* 0x000fc800078e33ff */
/*00b0*/ IADD3 R0, R0, c[0x0][0x160], RZ ; /* 0x0000580000007a10 */
/* 0x000fca0007ffe0ff */
/*00c0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fca00078e0205 */
/*00d0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
__global__ void revArray(int N, float *a, float *b) {
int n = threadIdx.x + blockIdx.x*blockDim.x;
if(n<N) {
b[N-1-n] = a[n];
}
}
int main(int argc, char **argv) {
int N = 100;
//Host memory allocation
float *h_a = (float*) malloc(N*sizeof(float));
float *h_b = (float*) malloc(N*sizeof(float));
int n;
for(n=0;n<N;n++) {
h_a[n] = 1+n;
}
// Device memory allocation
float *d_a, *d_b;
cudaMalloc(&d_a, N*sizeof(float));
cudaMalloc(&d_b, N*sizeof(float));
// Copy data from host to device
cudaMemcpy(d_a, h_a, N*sizeof(float), cudaMemcpyHostToDevice);
//save this for later
int NthreadsPerBlock = 10;
int NthreadBlocks = (N+NthreadsPerBlock-1)/NthreadsPerBlock ;
revArray<<<NthreadBlocks, NthreadsPerBlock>>>(N,d_a,d_b);
//copy result from device to host
cudaMemcpy(h_b, d_b, N*sizeof(float), cudaMemcpyDeviceToHost);
for(n=0;n<N;++n) {
printf("h_b[%d] = %g\n",n,h_b[n]);
}
free(h_a);
free(h_b);
cudaFree(d_a);
cudaFree(d_b);
return 0;
} | .file "tmpxft_00042b41_00000000-6_rev-array.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z8revArrayiPfS_iPfS_
.type _Z30__device_stub__Z8revArrayiPfS_iPfS_, @function
_Z30__device_stub__Z8revArrayiPfS_iPfS_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8revArrayiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z8revArrayiPfS_iPfS_, .-_Z30__device_stub__Z8revArrayiPfS_iPfS_
.globl _Z8revArrayiPfS_
.type _Z8revArrayiPfS_, @function
_Z8revArrayiPfS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z8revArrayiPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8revArrayiPfS_, .-_Z8revArrayiPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "h_b[%d] = %g\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $400, %edi
call malloc@PLT
movq %rax, %r12
movl $400, %edi
call malloc@PLT
movq %rax, %rbp
movl $1, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, -4(%r12,%rax,4)
addq $1, %rax
cmpq $101, %rax
jne .L12
movq %rsp, %rdi
movl $400, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $400, %edx
movq %r12, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $10, 28(%rsp)
movl $1, 32(%rsp)
movl $10, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $400, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %r13
.L14:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $100, %rbx
jne .L14
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movl $100, %edi
call _Z30__device_stub__Z8revArrayiPfS_iPfS_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z8revArrayiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8revArrayiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
__global__ void revArray(int N, float *a, float *b) {
int n = threadIdx.x + blockIdx.x*blockDim.x;
if(n<N) {
b[N-1-n] = a[n];
}
}
int main(int argc, char **argv) {
int N = 100;
//Host memory allocation
float *h_a = (float*) malloc(N*sizeof(float));
float *h_b = (float*) malloc(N*sizeof(float));
int n;
for(n=0;n<N;n++) {
h_a[n] = 1+n;
}
// Device memory allocation
float *d_a, *d_b;
cudaMalloc(&d_a, N*sizeof(float));
cudaMalloc(&d_b, N*sizeof(float));
// Copy data from host to device
cudaMemcpy(d_a, h_a, N*sizeof(float), cudaMemcpyHostToDevice);
//save this for later
int NthreadsPerBlock = 10;
int NthreadBlocks = (N+NthreadsPerBlock-1)/NthreadsPerBlock ;
revArray<<<NthreadBlocks, NthreadsPerBlock>>>(N,d_a,d_b);
//copy result from device to host
cudaMemcpy(h_b, d_b, N*sizeof(float), cudaMemcpyDeviceToHost);
for(n=0;n<N;++n) {
printf("h_b[%d] = %g\n",n,h_b[n]);
}
free(h_a);
free(h_b);
cudaFree(d_a);
cudaFree(d_b);
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
__global__ void revArray(int N, float *a, float *b) {
int n = threadIdx.x + blockIdx.x*blockDim.x;
if(n<N) {
b[N-1-n] = a[n];
}
}
int main(int argc, char **argv) {
int N = 100;
//Host memory allocation
float *h_a = (float*) malloc(N*sizeof(float));
float *h_b = (float*) malloc(N*sizeof(float));
int n;
for(n=0;n<N;n++) {
h_a[n] = 1+n;
}
// Device memory allocation
float *d_a, *d_b;
hipMalloc(&d_a, N*sizeof(float));
hipMalloc(&d_b, N*sizeof(float));
// Copy data from host to device
hipMemcpy(d_a, h_a, N*sizeof(float), hipMemcpyHostToDevice);
//save this for later
int NthreadsPerBlock = 10;
int NthreadBlocks = (N+NthreadsPerBlock-1)/NthreadsPerBlock ;
revArray<<<NthreadBlocks, NthreadsPerBlock>>>(N,d_a,d_b);
//copy result from device to host
hipMemcpy(h_b, d_b, N*sizeof(float), hipMemcpyDeviceToHost);
for(n=0;n<N;++n) {
printf("h_b[%d] = %g\n",n,h_b[n]);
}
free(h_a);
free(h_b);
hipFree(d_a);
hipFree(d_b);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
__global__ void revArray(int N, float *a, float *b) {
int n = threadIdx.x + blockIdx.x*blockDim.x;
if(n<N) {
b[N-1-n] = a[n];
}
}
int main(int argc, char **argv) {
int N = 100;
//Host memory allocation
float *h_a = (float*) malloc(N*sizeof(float));
float *h_b = (float*) malloc(N*sizeof(float));
int n;
for(n=0;n<N;n++) {
h_a[n] = 1+n;
}
// Device memory allocation
float *d_a, *d_b;
hipMalloc(&d_a, N*sizeof(float));
hipMalloc(&d_b, N*sizeof(float));
// Copy data from host to device
hipMemcpy(d_a, h_a, N*sizeof(float), hipMemcpyHostToDevice);
//save this for later
int NthreadsPerBlock = 10;
int NthreadBlocks = (N+NthreadsPerBlock-1)/NthreadsPerBlock ;
revArray<<<NthreadBlocks, NthreadsPerBlock>>>(N,d_a,d_b);
//copy result from device to host
hipMemcpy(h_b, d_b, N*sizeof(float), hipMemcpyDeviceToHost);
for(n=0;n<N;++n) {
printf("h_b[%d] = %g\n",n,h_b[n]);
}
free(h_a);
free(h_b);
hipFree(d_a);
hipFree(d_b);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8revArrayiPfS_
.globl _Z8revArrayiPfS_
.p2align 8
.type _Z8revArrayiPfS_,@function
_Z8revArrayiPfS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
v_xad_u32 v0, v1, -1, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8revArrayiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8revArrayiPfS_, .Lfunc_end0-_Z8revArrayiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8revArrayiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8revArrayiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
__global__ void revArray(int N, float *a, float *b) {
int n = threadIdx.x + blockIdx.x*blockDim.x;
if(n<N) {
b[N-1-n] = a[n];
}
}
int main(int argc, char **argv) {
int N = 100;
//Host memory allocation
float *h_a = (float*) malloc(N*sizeof(float));
float *h_b = (float*) malloc(N*sizeof(float));
int n;
for(n=0;n<N;n++) {
h_a[n] = 1+n;
}
// Device memory allocation
float *d_a, *d_b;
hipMalloc(&d_a, N*sizeof(float));
hipMalloc(&d_b, N*sizeof(float));
// Copy data from host to device
hipMemcpy(d_a, h_a, N*sizeof(float), hipMemcpyHostToDevice);
//save this for later
int NthreadsPerBlock = 10;
int NthreadBlocks = (N+NthreadsPerBlock-1)/NthreadsPerBlock ;
revArray<<<NthreadBlocks, NthreadsPerBlock>>>(N,d_a,d_b);
//copy result from device to host
hipMemcpy(h_b, d_b, N*sizeof(float), hipMemcpyDeviceToHost);
for(n=0;n<N;++n) {
printf("h_b[%d] = %g\n",n,h_b[n]);
}
free(h_a);
free(h_b);
hipFree(d_a);
hipFree(d_b);
return 0;
} | .text
.file "rev-array.hip"
.globl _Z23__device_stub__revArrayiPfS_ # -- Begin function _Z23__device_stub__revArrayiPfS_
.p2align 4, 0x90
.type _Z23__device_stub__revArrayiPfS_,@function
_Z23__device_stub__revArrayiPfS_: # @_Z23__device_stub__revArrayiPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8revArrayiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__revArrayiPfS_, .Lfunc_end0-_Z23__device_stub__revArrayiPfS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %rbx
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq 1(%rax), %rcx
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rbx,%rax,4)
movq %rcx, %rax
cmpq $100, %rcx
jne .LBB1_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
leaq 8(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
movq 16(%rsp), %rdi
movl $400, %edx # imm = 0x190
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967306, %rdi # imm = 0x10000000A
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl $100, 28(%rsp)
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8revArrayiPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $400, %edx # imm = 0x190
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movl %r15d, %esi
movb $1, %al
callq printf
incq %r15
cmpq $100, %r15
jne .LBB1_5
# %bb.6:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8revArrayiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8revArrayiPfS_,@object # @_Z8revArrayiPfS_
.section .rodata,"a",@progbits
.globl _Z8revArrayiPfS_
.p2align 3, 0x0
_Z8revArrayiPfS_:
.quad _Z23__device_stub__revArrayiPfS_
.size _Z8revArrayiPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "h_b[%d] = %g\n"
.size .L.str, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8revArrayiPfS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__revArrayiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8revArrayiPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8revArrayiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ LOP3.LUT R0, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff007212 */
/* 0x000fc800078e33ff */
/*00b0*/ IADD3 R0, R0, c[0x0][0x160], RZ ; /* 0x0000580000007a10 */
/* 0x000fca0007ffe0ff */
/*00c0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fca00078e0205 */
/*00d0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8revArrayiPfS_
.globl _Z8revArrayiPfS_
.p2align 8
.type _Z8revArrayiPfS_,@function
_Z8revArrayiPfS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
v_xad_u32 v0, v1, -1, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8revArrayiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8revArrayiPfS_, .Lfunc_end0-_Z8revArrayiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8revArrayiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8revArrayiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00042b41_00000000-6_rev-array.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z8revArrayiPfS_iPfS_
.type _Z30__device_stub__Z8revArrayiPfS_iPfS_, @function
_Z30__device_stub__Z8revArrayiPfS_iPfS_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8revArrayiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z8revArrayiPfS_iPfS_, .-_Z30__device_stub__Z8revArrayiPfS_iPfS_
.globl _Z8revArrayiPfS_
.type _Z8revArrayiPfS_, @function
_Z8revArrayiPfS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z8revArrayiPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8revArrayiPfS_, .-_Z8revArrayiPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "h_b[%d] = %g\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $400, %edi
call malloc@PLT
movq %rax, %r12
movl $400, %edi
call malloc@PLT
movq %rax, %rbp
movl $1, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, -4(%r12,%rax,4)
addq $1, %rax
cmpq $101, %rax
jne .L12
movq %rsp, %rdi
movl $400, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $400, %edx
movq %r12, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $10, 28(%rsp)
movl $1, 32(%rsp)
movl $10, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $400, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %r13
.L14:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $100, %rbx
jne .L14
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movl $100, %edi
call _Z30__device_stub__Z8revArrayiPfS_iPfS_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z8revArrayiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8revArrayiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "rev-array.hip"
.globl _Z23__device_stub__revArrayiPfS_ # -- Begin function _Z23__device_stub__revArrayiPfS_
.p2align 4, 0x90
.type _Z23__device_stub__revArrayiPfS_,@function
_Z23__device_stub__revArrayiPfS_: # @_Z23__device_stub__revArrayiPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8revArrayiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__revArrayiPfS_, .Lfunc_end0-_Z23__device_stub__revArrayiPfS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %rbx
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq 1(%rax), %rcx
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rbx,%rax,4)
movq %rcx, %rax
cmpq $100, %rcx
jne .LBB1_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
leaq 8(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
movq 16(%rsp), %rdi
movl $400, %edx # imm = 0x190
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967306, %rdi # imm = 0x10000000A
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl $100, 28(%rsp)
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8revArrayiPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $400, %edx # imm = 0x190
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movl %r15d, %esi
movb $1, %al
callq printf
incq %r15
cmpq $100, %r15
jne .LBB1_5
# %bb.6:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8revArrayiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8revArrayiPfS_,@object # @_Z8revArrayiPfS_
.section .rodata,"a",@progbits
.globl _Z8revArrayiPfS_
.p2align 3, 0x0
_Z8revArrayiPfS_:
.quad _Z23__device_stub__revArrayiPfS_
.size _Z8revArrayiPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "h_b[%d] = %g\n"
.size .L.str, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8revArrayiPfS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__revArrayiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8revArrayiPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define N 256
#define THREADS_PER_BLOCK 256
//Test
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void add(double *price,int n) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ double returns[256];
//Calculate Log Returns
double logRt = 0.0;
if(index == 0) {
returns[0] = 0.0;
}else if(index < n) {
logRt = log(price[index]) - log(price[index-1]);
returns[index] = logRt;
}
__syncthreads();
//find average of returns
int idx = 2;
int back = 1;
while(idx <= (n+1)) {
if((index+1) % idx == 0) {
returns[index] = returns[index] + returns[index-back];
}
idx = idx * 2;
back = back * 2;
__syncthreads();
}
__syncthreads();
float ravg = returns[n-1]/n;
float rdiffSq = (logRt - ravg) * (logRt - ravg);
__syncthreads();
returns[index] = rdiffSq;
__syncthreads();
idx = 2;
back = 1;
while(idx <= (n + 1)) {
if((index+1) % idx == 0) {
returns[index] = returns[index] + returns[index-back];
}
idx = idx * 2;
back = back * 2;
__syncthreads();
}
__syncthreads();
if(index == 0) {
float vol = returns[n-1]/(n-2);
float sd = sqrt(vol);
printf("SD %f Volatility %f\n",sd,vol);
}
}
int main(void) {
double *price;
double *d_price;
int size = N * sizeof(double);
cudaMalloc((void **)&d_price,size);
price = (double *)malloc(size);
for(int i = 0; i < N;i++) {
price[i] = i+1;
}
cudaMemcpy(d_price,price,size,cudaMemcpyHostToDevice);
add<<<(N + THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(d_price,N);
gpuErrchk( cudaPeekAtLastError() );
gpuErrchk( cudaDeviceSynchronize() );
free(price);
cudaFree(d_price);
return 0;
} | .file "tmpxft_001a70b2_00000000-6_bschole.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z23__device_stub__Z3addPdiPdi
.type _Z23__device_stub__Z3addPdiPdi, @function
_Z23__device_stub__Z3addPdiPdi:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addPdi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z23__device_stub__Z3addPdiPdi, .-_Z23__device_stub__Z3addPdiPdi
.globl _Z3addPdi
.type _Z3addPdi, @function
_Z3addPdi:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z3addPdiPdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z3addPdi, .-_Z3addPdi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/accnttodrop/cudapg/master/bschole.cu"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
movl $2048, %edi
call malloc@PLT
movq %rax, %rbx
movl $1, %eax
.L20:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, -8(%rbx,%rax,8)
addq $1, %rax
cmpq $257, %rax
jne .L20
movl $1, %ecx
movl $2048, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
call cudaPeekAtLastError@PLT
movl %eax, %edi
movl $1, %ecx
movl $81, %edx
leaq .LC1(%rip), %rbp
movq %rbp, %rsi
call _Z9gpuAssert9cudaErrorPKcib
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $82, %edx
movq %rbp, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movl $256, %esi
movq 8(%rsp), %rdi
call _Z23__device_stub__Z3addPdiPdi
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z3addPdi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPdi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define N 256
#define THREADS_PER_BLOCK 256
//Test
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void add(double *price,int n) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ double returns[256];
//Calculate Log Returns
double logRt = 0.0;
if(index == 0) {
returns[0] = 0.0;
}else if(index < n) {
logRt = log(price[index]) - log(price[index-1]);
returns[index] = logRt;
}
__syncthreads();
//find average of returns
int idx = 2;
int back = 1;
while(idx <= (n+1)) {
if((index+1) % idx == 0) {
returns[index] = returns[index] + returns[index-back];
}
idx = idx * 2;
back = back * 2;
__syncthreads();
}
__syncthreads();
float ravg = returns[n-1]/n;
float rdiffSq = (logRt - ravg) * (logRt - ravg);
__syncthreads();
returns[index] = rdiffSq;
__syncthreads();
idx = 2;
back = 1;
while(idx <= (n + 1)) {
if((index+1) % idx == 0) {
returns[index] = returns[index] + returns[index-back];
}
idx = idx * 2;
back = back * 2;
__syncthreads();
}
__syncthreads();
if(index == 0) {
float vol = returns[n-1]/(n-2);
float sd = sqrt(vol);
printf("SD %f Volatility %f\n",sd,vol);
}
}
int main(void) {
double *price;
double *d_price;
int size = N * sizeof(double);
cudaMalloc((void **)&d_price,size);
price = (double *)malloc(size);
for(int i = 0; i < N;i++) {
price[i] = i+1;
}
cudaMemcpy(d_price,price,size,cudaMemcpyHostToDevice);
add<<<(N + THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(d_price,N);
gpuErrchk( cudaPeekAtLastError() );
gpuErrchk( cudaDeviceSynchronize() );
free(price);
cudaFree(d_price);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define N 256
#define THREADS_PER_BLOCK 256
//Test
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void add(double *price,int n) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ double returns[256];
//Calculate Log Returns
double logRt = 0.0;
if(index == 0) {
returns[0] = 0.0;
}else if(index < n) {
logRt = log(price[index]) - log(price[index-1]);
returns[index] = logRt;
}
__syncthreads();
//find average of returns
int idx = 2;
int back = 1;
while(idx <= (n+1)) {
if((index+1) % idx == 0) {
returns[index] = returns[index] + returns[index-back];
}
idx = idx * 2;
back = back * 2;
__syncthreads();
}
__syncthreads();
float ravg = returns[n-1]/n;
float rdiffSq = (logRt - ravg) * (logRt - ravg);
__syncthreads();
returns[index] = rdiffSq;
__syncthreads();
idx = 2;
back = 1;
while(idx <= (n + 1)) {
if((index+1) % idx == 0) {
returns[index] = returns[index] + returns[index-back];
}
idx = idx * 2;
back = back * 2;
__syncthreads();
}
__syncthreads();
if(index == 0) {
float vol = returns[n-1]/(n-2);
float sd = sqrt(vol);
printf("SD %f Volatility %f\n",sd,vol);
}
}
int main(void) {
double *price;
double *d_price;
int size = N * sizeof(double);
hipMalloc((void **)&d_price,size);
price = (double *)malloc(size);
for(int i = 0; i < N;i++) {
price[i] = i+1;
}
hipMemcpy(d_price,price,size,hipMemcpyHostToDevice);
add<<<(N + THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(d_price,N);
gpuErrchk( hipPeekAtLastError() );
gpuErrchk( hipDeviceSynchronize() );
free(price);
hipFree(d_price);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define N 256
#define THREADS_PER_BLOCK 256
//Test
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void add(double *price,int n) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ double returns[256];
//Calculate Log Returns
double logRt = 0.0;
if(index == 0) {
returns[0] = 0.0;
}else if(index < n) {
logRt = log(price[index]) - log(price[index-1]);
returns[index] = logRt;
}
__syncthreads();
//find average of returns
int idx = 2;
int back = 1;
while(idx <= (n+1)) {
if((index+1) % idx == 0) {
returns[index] = returns[index] + returns[index-back];
}
idx = idx * 2;
back = back * 2;
__syncthreads();
}
__syncthreads();
float ravg = returns[n-1]/n;
float rdiffSq = (logRt - ravg) * (logRt - ravg);
__syncthreads();
returns[index] = rdiffSq;
__syncthreads();
idx = 2;
back = 1;
while(idx <= (n + 1)) {
if((index+1) % idx == 0) {
returns[index] = returns[index] + returns[index-back];
}
idx = idx * 2;
back = back * 2;
__syncthreads();
}
__syncthreads();
if(index == 0) {
float vol = returns[n-1]/(n-2);
float sd = sqrt(vol);
printf("SD %f Volatility %f\n",sd,vol);
}
}
int main(void) {
double *price;
double *d_price;
int size = N * sizeof(double);
hipMalloc((void **)&d_price,size);
price = (double *)malloc(size);
for(int i = 0; i < N;i++) {
price[i] = i+1;
}
hipMemcpy(d_price,price,size,hipMemcpyHostToDevice);
add<<<(N + THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(d_price,N);
gpuErrchk( hipPeekAtLastError() );
gpuErrchk( hipDeviceSynchronize() );
free(price);
hipFree(d_price);
return 0;
} | .text
.file "bschole.hip"
.globl _Z18__device_stub__addPdi # -- Begin function _Z18__device_stub__addPdi
.p2align 4, 0x90
.type _Z18__device_stub__addPdi,@function
_Z18__device_stub__addPdi: # @_Z18__device_stub__addPdi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3addPdi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__addPdi, .Lfunc_end0-_Z18__device_stub__addPdi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 8(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq 1(%rax), %rcx
xorps %xmm0, %xmm0
cvtsi2sd %ecx, %xmm0
movsd %xmm0, (%rbx,%rax,8)
movq %rcx, %rax
cmpq $256, %rcx # imm = 0x100
jne .LBB1_1
# %bb.2:
movq 8(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $256, 20(%rsp) # imm = 0x100
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPdi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB1_5
# %bb.7: # %_Z9gpuAssert10hipError_tPKcib.exit
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_8
# %bb.9: # %_Z9gpuAssert10hipError_tPKcib.exit12
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_5:
.cfi_def_cfa_offset 128
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $83, %r8d
jmp .LBB1_6
.LBB1_8:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $84, %r8d
.LBB1_6:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPdi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPdi,@object # @_Z3addPdi
.section .rodata,"a",@progbits
.globl _Z3addPdi
.p2align 3, 0x0
_Z3addPdi:
.quad _Z18__device_stub__addPdi
.size _Z3addPdi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/accnttodrop/cudapg/master/bschole.hip"
.size .L.str, 95
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.1, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPdi"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPdi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPdi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a70b2_00000000-6_bschole.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z23__device_stub__Z3addPdiPdi
.type _Z23__device_stub__Z3addPdiPdi, @function
_Z23__device_stub__Z3addPdiPdi:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addPdi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z23__device_stub__Z3addPdiPdi, .-_Z23__device_stub__Z3addPdiPdi
.globl _Z3addPdi
.type _Z3addPdi, @function
_Z3addPdi:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z3addPdiPdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z3addPdi, .-_Z3addPdi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/accnttodrop/cudapg/master/bschole.cu"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
movl $2048, %edi
call malloc@PLT
movq %rax, %rbx
movl $1, %eax
.L20:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, -8(%rbx,%rax,8)
addq $1, %rax
cmpq $257, %rax
jne .L20
movl $1, %ecx
movl $2048, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
call cudaPeekAtLastError@PLT
movl %eax, %edi
movl $1, %ecx
movl $81, %edx
leaq .LC1(%rip), %rbp
movq %rbp, %rsi
call _Z9gpuAssert9cudaErrorPKcib
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $82, %edx
movq %rbp, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movl $256, %esi
movq 8(%rsp), %rdi
call _Z23__device_stub__Z3addPdiPdi
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z3addPdi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPdi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "bschole.hip"
.globl _Z18__device_stub__addPdi # -- Begin function _Z18__device_stub__addPdi
.p2align 4, 0x90
.type _Z18__device_stub__addPdi,@function
_Z18__device_stub__addPdi: # @_Z18__device_stub__addPdi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3addPdi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__addPdi, .Lfunc_end0-_Z18__device_stub__addPdi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 8(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq 1(%rax), %rcx
xorps %xmm0, %xmm0
cvtsi2sd %ecx, %xmm0
movsd %xmm0, (%rbx,%rax,8)
movq %rcx, %rax
cmpq $256, %rcx # imm = 0x100
jne .LBB1_1
# %bb.2:
movq 8(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $256, 20(%rsp) # imm = 0x100
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPdi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB1_5
# %bb.7: # %_Z9gpuAssert10hipError_tPKcib.exit
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_8
# %bb.9: # %_Z9gpuAssert10hipError_tPKcib.exit12
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_5:
.cfi_def_cfa_offset 128
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $83, %r8d
jmp .LBB1_6
.LBB1_8:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $84, %r8d
.LBB1_6:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPdi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPdi,@object # @_Z3addPdi
.section .rodata,"a",@progbits
.globl _Z3addPdi
.p2align 3, 0x0
_Z3addPdi:
.quad _Z18__device_stub__addPdi
.size _Z3addPdi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/accnttodrop/cudapg/master/bschole.hip"
.size .L.str, 95
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.1, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPdi"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPdi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPdi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define Columnas 10
#define Filas 10
cudaError_t addWithCuda(int* c, const int* a, unsigned int size);
__device__ unsigned int computeOutputEdge(int mask[][3], int vecinos[][3], int rows, int cols) {
float result = 1;
int sum = 0;
for (int i = 0; i < rows; i++) {
for (int j = 0; j < cols; j++) {
float mul = mask[i][j] * vecinos[i][j];
sum = sum + mul;
}
}
result = abs(sum);
return (int)result;
}
__global__ void bordes(int* val2, int* val1, int m, int n)
{
int column = threadIdx.x + blockDim.x * blockIdx.x;
int row = threadIdx.y + blockDim.y * blockIdx.y;
int myEdge[3][3] = { {0,1,0},{1,-4,1},{0,1,0} };
//int filas = (sizeof(myMask)/sizeof(myMask[0]));
if (row < m && column < n) {
int thread_id1 = (row - 1) * n + (column - 1);
int thread_id2 = (row - 1) * n + (column);
int thread_id3 = (row - 1) * n + (column + 1);
int thread_id4 = (row)* n + (column - 1);
int thread_id5 = (row)* n + (column);
int thread_id6 = (row)* n + (column + 1);
int thread_id7 = (row + 1) * n + (column - 1);
int thread_id8 = (row + 1) * n + (column);
int thread_id9 = (row + 1) * n + (column + 1);
//int my_val = val1[thread_id5];
//printf("row: %d, \tcol: %d, \tvalor: %d\n", row, column, my_val);
val2[thread_id5] = val1[thread_id5];
if ((row > 0 && row < (m - 1)) && (column > 0 && column < (n - 1)))
{
int my_val0 = val1[thread_id1];
int my_val2 = val1[thread_id2];
int my_val3 = val1[thread_id3];
int my_val4 = val1[thread_id4];
int my_val5 = val1[thread_id5]; //doubly-subscripted access
int my_val6 = val1[thread_id6];
int my_val7 = val1[thread_id7];
int my_val8 = val1[thread_id8];
int my_val9 = val1[thread_id9];
//printf("row: %d, col: %d, value: %d\n", row, column, my_val);
int myMask2[3][3] = { {(my_val0),(my_val2),(my_val3)},
{(my_val4),(my_val5),(my_val6)},
{(my_val7),(my_val8),(my_val9)} };
unsigned int output = computeOutputEdge(myEdge, myMask2, 3, 3);
//printf("row: %d,\t col: %d,\t Valor Original: %d,\t Nuevo Valor: %d\n", row, column, my_val5,output);
//printf("Salida: %d \n", output);
//printf("Entro\n");
val2[thread_id5] = output;
}
}
} | code for sm_80
Function : _Z6bordesPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x170], P0 ; /* 0x00005c0005007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R4, R5, c[0x0][0x174], R0 ; /* 0x00005d0005047a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe40000000a00 */
/*00d0*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe40000000000 */
/*00e0*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fc80000000a00 */
/*00f0*/ IMAD.WIDE R2, R4, R9, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fca00078e0209 */
/*0100*/ LDG.E R7, [R2.64] ; /* 0x0000000802077981 */
/* 0x0000a2000c1e1900 */
/*0110*/ UIADD3 UR4, -UR5, UR6, URZ ; /* 0x0000000605047290 */
/* 0x000fe4000fffe13f */
/*0120*/ UIADD3 UR5, -UR5, UR7, URZ ; /* 0x0000000705057290 */
/* 0x000fc8000fffe13f */
/*0130*/ ISETP.GE.AND P0, PT, R5.reuse, UR4, PT ; /* 0x0000000405007c0c */
/* 0x040fe4000bf06270 */
/*0140*/ ISETP.GE.AND P1, PT, R0, UR5, PT ; /* 0x0000000500007c0c */
/* 0x000fe2000bf26270 */
/*0150*/ IMAD.WIDE R2, R4, R9, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x001fe200078e0209 */
/*0160*/ ISETP.GT.AND P0, PT, R5.reuse, RZ, !P0 ; /* 0x000000ff0500720c */
/* 0x040fe40004704270 */
/*0170*/ ISETP.GT.AND P1, PT, R0, RZ, !P1 ; /* 0x000000ff0000720c */
/* 0x000fe40004f24270 */
/*0180*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*0190*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fc60000703070 */
/*01a0*/ IMAD R5, R5, c[0x0][0x174], R0 ; /* 0x00005d0005057a24 */
/* 0x000fe200078e0200 */
/*01b0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0041f2000c101908 */
/*01c0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*01d0*/ IMAD.WIDE R4, R5, R9, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0209 */
/*01e0*/ LDG.E R0, [R4.64] ; /* 0x0000000804007981 */
/* 0x000ea2000c1e1900 */
/*01f0*/ IMAD.WIDE R6, R9, c[0x0][0x174], R4 ; /* 0x00005d0009067a25 */
/* 0x001fca00078e0204 */
/*0200*/ LDG.E R12, [R6.64+-0x4] ; /* 0xfffffc08060c7981 */
/* 0x000ee8000c1e1900 */
/*0210*/ LDG.E R13, [R6.64] ; /* 0x00000008060d7981 */
/* 0x000f28000c1e1900 */
/*0220*/ LDG.E R14, [R6.64+0x4] ; /* 0x00000408060e7981 */
/* 0x000f62000c1e1900 */
/*0230*/ IMAD.WIDE R8, R9, c[0x0][0x174], R6 ; /* 0x00005d0009087a25 */
/* 0x000fcc00078e0206 */
/*0240*/ LDG.E R8, [R8.64] ; /* 0x0000000808087981 */
/* 0x000f62000c1e1900 */
/*0250*/ I2F R0, R0 ; /* 0x0000000000007306 */
/* 0x004e300000201400 */
/*0260*/ I2F R12, R12 ; /* 0x0000000c000c7306 */
/* 0x008fe20000201400 */
/*0270*/ LEA R13, -R13, RZ, 0x2 ; /* 0x000000ff0d0d7211 */
/* 0x010fe200078e11ff */
/*0280*/ FADD R10, RZ, R0 ; /* 0x00000000ff0a7221 */
/* 0x001fcc0000000000 */
/*0290*/ I2F R4, R13 ; /* 0x0000000d00047306 */
/* 0x000ff00000201400 */
/*02a0*/ F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a7305 */
/* 0x000e30000020f100 */
/*02b0*/ I2F R14, R14 ; /* 0x0000000e000e7306 */
/* 0x020ff00000201400 */
/*02c0*/ I2F R11, R10 ; /* 0x0000000a000b7306 */
/* 0x001e300000201400 */
/*02d0*/ I2F R8, R8 ; /* 0x0000000800087306 */
/* 0x000ff00000201400 */
/*02e0*/ F2I.TRUNC.NTZ R11, R11 ; /* 0x0000000b000b7305 */
/* 0x001e30000020f100 */
/*02f0*/ I2F R5, R11 ; /* 0x0000000b00057306 */
/* 0x001e240000201400 */
/*0300*/ FADD R5, R12, R5 ; /* 0x000000050c057221 */
/* 0x001fcc0000000000 */
/*0310*/ F2I.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000e30000020f100 */
/*0320*/ I2F R7, R5 ; /* 0x0000000500077306 */
/* 0x001e240000201400 */
/*0330*/ FADD R4, R4, R7 ; /* 0x0000000704047221 */
/* 0x001fcc0000000000 */
/*0340*/ F2I.TRUNC.NTZ R4, R4 ; /* 0x0000000400047305 */
/* 0x000e30000020f100 */
/*0350*/ I2F R7, R4 ; /* 0x0000000400077306 */
/* 0x001e240000201400 */
/*0360*/ FADD R7, R14, R7 ; /* 0x000000070e077221 */
/* 0x001fcc0000000000 */
/*0370*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e30000020f100 */
/*0380*/ I2F R0, R7 ; /* 0x0000000700007306 */
/* 0x001e300000201400 */
/*0390*/ F2I.TRUNC.NTZ R0, R0 ; /* 0x0000000000007305 */
/* 0x001e30000020f100 */
/*03a0*/ I2F R9, R0 ; /* 0x0000000000097306 */
/* 0x001e240000201400 */
/*03b0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x001fcc0000000000 */
/*03c0*/ F2I.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e30000020f100 */
/*03d0*/ I2F R5, R9 ; /* 0x0000000900057306 */
/* 0x001e300000201400 */
/*03e0*/ F2I.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x001e24000020f100 */
/*03f0*/ IABS R4, R5 ; /* 0x0000000500047213 */
/* 0x001fcc0000000000 */
/*0400*/ I2F R4, R4 ; /* 0x0000000400047306 */
/* 0x000e300000201400 */
/*0410*/ F2I.TRUNC.NTZ R7, R4 ; /* 0x0000000400077305 */
/* 0x001e24000020f100 */
/*0420*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe2000c101908 */
/*0430*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0440*/ BRA 0x440; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define Columnas 10
#define Filas 10
cudaError_t addWithCuda(int* c, const int* a, unsigned int size);
__device__ unsigned int computeOutputEdge(int mask[][3], int vecinos[][3], int rows, int cols) {
float result = 1;
int sum = 0;
for (int i = 0; i < rows; i++) {
for (int j = 0; j < cols; j++) {
float mul = mask[i][j] * vecinos[i][j];
sum = sum + mul;
}
}
result = abs(sum);
return (int)result;
}
__global__ void bordes(int* val2, int* val1, int m, int n)
{
int column = threadIdx.x + blockDim.x * blockIdx.x;
int row = threadIdx.y + blockDim.y * blockIdx.y;
int myEdge[3][3] = { {0,1,0},{1,-4,1},{0,1,0} };
//int filas = (sizeof(myMask)/sizeof(myMask[0]));
if (row < m && column < n) {
int thread_id1 = (row - 1) * n + (column - 1);
int thread_id2 = (row - 1) * n + (column);
int thread_id3 = (row - 1) * n + (column + 1);
int thread_id4 = (row)* n + (column - 1);
int thread_id5 = (row)* n + (column);
int thread_id6 = (row)* n + (column + 1);
int thread_id7 = (row + 1) * n + (column - 1);
int thread_id8 = (row + 1) * n + (column);
int thread_id9 = (row + 1) * n + (column + 1);
//int my_val = val1[thread_id5];
//printf("row: %d, \tcol: %d, \tvalor: %d\n", row, column, my_val);
val2[thread_id5] = val1[thread_id5];
if ((row > 0 && row < (m - 1)) && (column > 0 && column < (n - 1)))
{
int my_val0 = val1[thread_id1];
int my_val2 = val1[thread_id2];
int my_val3 = val1[thread_id3];
int my_val4 = val1[thread_id4];
int my_val5 = val1[thread_id5]; //doubly-subscripted access
int my_val6 = val1[thread_id6];
int my_val7 = val1[thread_id7];
int my_val8 = val1[thread_id8];
int my_val9 = val1[thread_id9];
//printf("row: %d, col: %d, value: %d\n", row, column, my_val);
int myMask2[3][3] = { {(my_val0),(my_val2),(my_val3)},
{(my_val4),(my_val5),(my_val6)},
{(my_val7),(my_val8),(my_val9)} };
unsigned int output = computeOutputEdge(myEdge, myMask2, 3, 3);
//printf("row: %d,\t col: %d,\t Valor Original: %d,\t Nuevo Valor: %d\n", row, column, my_val5,output);
//printf("Salida: %d \n", output);
//printf("Entro\n");
val2[thread_id5] = output;
}
}
} | .file "tmpxft_000aa661_00000000-6_bordes.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z17computeOutputEdgePA3_iS0_ii
.type _Z17computeOutputEdgePA3_iS0_ii, @function
_Z17computeOutputEdgePA3_iS0_ii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z17computeOutputEdgePA3_iS0_ii, .-_Z17computeOutputEdgePA3_iS0_ii
.globl _Z29__device_stub__Z6bordesPiS_iiPiS_ii
.type _Z29__device_stub__Z6bordesPiS_iiPiS_ii, @function
_Z29__device_stub__Z6bordesPiS_iiPiS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6bordesPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z29__device_stub__Z6bordesPiS_iiPiS_ii, .-_Z29__device_stub__Z6bordesPiS_iiPiS_ii
.globl _Z6bordesPiS_ii
.type _Z6bordesPiS_ii, @function
_Z6bordesPiS_ii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6bordesPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z6bordesPiS_ii, .-_Z6bordesPiS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6bordesPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6bordesPiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define Columnas 10
#define Filas 10
cudaError_t addWithCuda(int* c, const int* a, unsigned int size);
__device__ unsigned int computeOutputEdge(int mask[][3], int vecinos[][3], int rows, int cols) {
float result = 1;
int sum = 0;
for (int i = 0; i < rows; i++) {
for (int j = 0; j < cols; j++) {
float mul = mask[i][j] * vecinos[i][j];
sum = sum + mul;
}
}
result = abs(sum);
return (int)result;
}
__global__ void bordes(int* val2, int* val1, int m, int n)
{
int column = threadIdx.x + blockDim.x * blockIdx.x;
int row = threadIdx.y + blockDim.y * blockIdx.y;
int myEdge[3][3] = { {0,1,0},{1,-4,1},{0,1,0} };
//int filas = (sizeof(myMask)/sizeof(myMask[0]));
if (row < m && column < n) {
int thread_id1 = (row - 1) * n + (column - 1);
int thread_id2 = (row - 1) * n + (column);
int thread_id3 = (row - 1) * n + (column + 1);
int thread_id4 = (row)* n + (column - 1);
int thread_id5 = (row)* n + (column);
int thread_id6 = (row)* n + (column + 1);
int thread_id7 = (row + 1) * n + (column - 1);
int thread_id8 = (row + 1) * n + (column);
int thread_id9 = (row + 1) * n + (column + 1);
//int my_val = val1[thread_id5];
//printf("row: %d, \tcol: %d, \tvalor: %d\n", row, column, my_val);
val2[thread_id5] = val1[thread_id5];
if ((row > 0 && row < (m - 1)) && (column > 0 && column < (n - 1)))
{
int my_val0 = val1[thread_id1];
int my_val2 = val1[thread_id2];
int my_val3 = val1[thread_id3];
int my_val4 = val1[thread_id4];
int my_val5 = val1[thread_id5]; //doubly-subscripted access
int my_val6 = val1[thread_id6];
int my_val7 = val1[thread_id7];
int my_val8 = val1[thread_id8];
int my_val9 = val1[thread_id9];
//printf("row: %d, col: %d, value: %d\n", row, column, my_val);
int myMask2[3][3] = { {(my_val0),(my_val2),(my_val3)},
{(my_val4),(my_val5),(my_val6)},
{(my_val7),(my_val8),(my_val9)} };
unsigned int output = computeOutputEdge(myEdge, myMask2, 3, 3);
//printf("row: %d,\t col: %d,\t Valor Original: %d,\t Nuevo Valor: %d\n", row, column, my_val5,output);
//printf("Salida: %d \n", output);
//printf("Entro\n");
val2[thread_id5] = output;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define Columnas 10
#define Filas 10
hipError_t addWithCuda(int* c, const int* a, unsigned int size);
__device__ unsigned int computeOutputEdge(int mask[][3], int vecinos[][3], int rows, int cols) {
float result = 1;
int sum = 0;
for (int i = 0; i < rows; i++) {
for (int j = 0; j < cols; j++) {
float mul = mask[i][j] * vecinos[i][j];
sum = sum + mul;
}
}
result = abs(sum);
return (int)result;
}
__global__ void bordes(int* val2, int* val1, int m, int n)
{
int column = threadIdx.x + blockDim.x * blockIdx.x;
int row = threadIdx.y + blockDim.y * blockIdx.y;
int myEdge[3][3] = { {0,1,0},{1,-4,1},{0,1,0} };
//int filas = (sizeof(myMask)/sizeof(myMask[0]));
if (row < m && column < n) {
int thread_id1 = (row - 1) * n + (column - 1);
int thread_id2 = (row - 1) * n + (column);
int thread_id3 = (row - 1) * n + (column + 1);
int thread_id4 = (row)* n + (column - 1);
int thread_id5 = (row)* n + (column);
int thread_id6 = (row)* n + (column + 1);
int thread_id7 = (row + 1) * n + (column - 1);
int thread_id8 = (row + 1) * n + (column);
int thread_id9 = (row + 1) * n + (column + 1);
//int my_val = val1[thread_id5];
//printf("row: %d, \tcol: %d, \tvalor: %d\n", row, column, my_val);
val2[thread_id5] = val1[thread_id5];
if ((row > 0 && row < (m - 1)) && (column > 0 && column < (n - 1)))
{
int my_val0 = val1[thread_id1];
int my_val2 = val1[thread_id2];
int my_val3 = val1[thread_id3];
int my_val4 = val1[thread_id4];
int my_val5 = val1[thread_id5]; //doubly-subscripted access
int my_val6 = val1[thread_id6];
int my_val7 = val1[thread_id7];
int my_val8 = val1[thread_id8];
int my_val9 = val1[thread_id9];
//printf("row: %d, col: %d, value: %d\n", row, column, my_val);
int myMask2[3][3] = { {(my_val0),(my_val2),(my_val3)},
{(my_val4),(my_val5),(my_val6)},
{(my_val7),(my_val8),(my_val9)} };
unsigned int output = computeOutputEdge(myEdge, myMask2, 3, 3);
//printf("row: %d,\t col: %d,\t Valor Original: %d,\t Nuevo Valor: %d\n", row, column, my_val5,output);
//printf("Salida: %d \n", output);
//printf("Entro\n");
val2[thread_id5] = output;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define Columnas 10
#define Filas 10
hipError_t addWithCuda(int* c, const int* a, unsigned int size);
__device__ unsigned int computeOutputEdge(int mask[][3], int vecinos[][3], int rows, int cols) {
float result = 1;
int sum = 0;
for (int i = 0; i < rows; i++) {
for (int j = 0; j < cols; j++) {
float mul = mask[i][j] * vecinos[i][j];
sum = sum + mul;
}
}
result = abs(sum);
return (int)result;
}
__global__ void bordes(int* val2, int* val1, int m, int n)
{
int column = threadIdx.x + blockDim.x * blockIdx.x;
int row = threadIdx.y + blockDim.y * blockIdx.y;
int myEdge[3][3] = { {0,1,0},{1,-4,1},{0,1,0} };
//int filas = (sizeof(myMask)/sizeof(myMask[0]));
if (row < m && column < n) {
int thread_id1 = (row - 1) * n + (column - 1);
int thread_id2 = (row - 1) * n + (column);
int thread_id3 = (row - 1) * n + (column + 1);
int thread_id4 = (row)* n + (column - 1);
int thread_id5 = (row)* n + (column);
int thread_id6 = (row)* n + (column + 1);
int thread_id7 = (row + 1) * n + (column - 1);
int thread_id8 = (row + 1) * n + (column);
int thread_id9 = (row + 1) * n + (column + 1);
//int my_val = val1[thread_id5];
//printf("row: %d, \tcol: %d, \tvalor: %d\n", row, column, my_val);
val2[thread_id5] = val1[thread_id5];
if ((row > 0 && row < (m - 1)) && (column > 0 && column < (n - 1)))
{
int my_val0 = val1[thread_id1];
int my_val2 = val1[thread_id2];
int my_val3 = val1[thread_id3];
int my_val4 = val1[thread_id4];
int my_val5 = val1[thread_id5]; //doubly-subscripted access
int my_val6 = val1[thread_id6];
int my_val7 = val1[thread_id7];
int my_val8 = val1[thread_id8];
int my_val9 = val1[thread_id9];
//printf("row: %d, col: %d, value: %d\n", row, column, my_val);
int myMask2[3][3] = { {(my_val0),(my_val2),(my_val3)},
{(my_val4),(my_val5),(my_val6)},
{(my_val7),(my_val8),(my_val9)} };
unsigned int output = computeOutputEdge(myEdge, myMask2, 3, 3);
//printf("row: %d,\t col: %d,\t Valor Original: %d,\t Nuevo Valor: %d\n", row, column, my_val5,output);
//printf("Salida: %d \n", output);
//printf("Entro\n");
val2[thread_id5] = output;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6bordesPiS_ii
.globl _Z6bordesPiS_ii
.p2align 8
.type _Z6bordesPiS_ii,@function
_Z6bordesPiS_ii:
s_load_b64 s[4:5], s[0:1], 0x4
s_clause 0x1
s_load_b32 s0, s[2:3], 0x24
s_load_b64 s[6:7], s[2:3], 0x10
s_mov_b32 s8, 0
v_bfe_u32 v2, v0, 10, 10
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 20, 10
v_dual_mov_b32 v11, -4 :: v_dual_mov_b32 v12, 1
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s4, 16
v_mul_u32_u24_e32 v10, s5, v2
s_mul_i32 s1, s4, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, s1, v1
s_and_b32 s1, s0, 0xffff
s_lshr_b32 s0, s0, 16
v_mad_u64_u32 v[6:7], null, s14, s1, v[1:2]
v_mad_u64_u32 v[8:9], null, s15, s0, v[2:3]
v_add3_u32 v2, v3, v10, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e64 s0, s7, v6
v_mov_b32_e32 v9, 0
v_mul_lo_u32 v7, v2, 36
v_mov_b32_e32 v2, s8
v_cmp_gt_i32_e32 vcc_lo, s6, v8
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
v_mov_b32_e32 v5, s11
ds_store_b128 v7, v[2:5]
ds_store_b128 v7, v[2:5] offset:16
ds_store_b64 v7, v[11:12] offset:16
ds_store_b32 v7, v9 offset:32
ds_store_2addr_b32 v7, v12, v12 offset0:1 offset1:3
ds_store_b32 v7, v12 offset:28
s_and_b32 s0, s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_mul_lo_u32 v7, v8, s7
s_load_b128 s[0:3], s[2:3], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v7, v6
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v9, v[4:5], off
v_cmp_lt_i32_e32 vcc_lo, 0, v8
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v9, off
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_8
s_add_i32 s0, s6, -1
s_add_i32 s1, s7, -1
v_cmp_gt_i32_e32 vcc_lo, s0, v8
v_cmp_gt_i32_e64 s0, s1, v6
v_cmp_lt_i32_e64 s1, 0, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_and_b32 s6, vcc_lo, s0
s_mov_b32 s0, 0
s_and_b32 s1, s6, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v9, -1, v8
v_add_nc_u32_e32 v13, -1, v6
s_mov_b32 s6, s7
v_add_nc_u32_e32 v19, 1, v6
v_mad_u64_u32 v[11:12], null, s7, v8, s[6:7]
v_mul_lo_u32 v9, v9, s7
v_add_nc_u32_e32 v12, v7, v13
s_delay_alu instid0(VALU_DEP_4)
v_add_nc_u32_e32 v7, v7, v19
v_mul_lo_u32 v1, v1, s5
v_add_nc_u32_e32 v18, v11, v13
v_add_nc_u32_e32 v8, v9, v13
v_add_nc_u32_e32 v14, v9, v6
v_add_nc_u32_e32 v16, v9, v19
v_ashrrev_i32_e32 v13, 31, v12
v_add_nc_u32_e32 v6, v11, v6
v_ashrrev_i32_e32 v9, 31, v8
v_ashrrev_i32_e32 v15, 31, v14
v_ashrrev_i32_e32 v17, 31, v16
v_lshlrev_b64 v[12:13], 2, v[12:13]
v_add_nc_u32_e32 v11, v11, v19
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_lshlrev_b64 v[14:15], 2, v[14:15]
v_lshlrev_b64 v[16:17], 2, v[16:17]
v_ashrrev_i32_e32 v19, 31, v18
v_mul_lo_u32 v1, v1, s4
v_add_co_u32 v20, vcc_lo, s2, v8
v_add_co_ci_u32_e32 v21, vcc_lo, s3, v9, vcc_lo
v_add_co_u32 v14, vcc_lo, s2, v14
v_ashrrev_i32_e32 v8, 31, v7
v_add_co_ci_u32_e32 v15, vcc_lo, s3, v15, vcc_lo
v_add_co_u32 v16, vcc_lo, s2, v16
v_add_co_ci_u32_e32 v17, vcc_lo, s3, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_lshlrev_b64 v[8:9], 2, v[7:8]
v_add_co_u32 v22, vcc_lo, s2, v12
v_add_co_ci_u32_e32 v23, vcc_lo, s3, v13, vcc_lo
v_lshlrev_b64 v[12:13], 2, v[18:19]
v_ashrrev_i32_e32 v7, 31, v6
v_add_co_u32 v8, vcc_lo, s2, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_add_co_u32 v18, vcc_lo, s2, v12
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_ci_u32_e32 v19, vcc_lo, s3, v13, vcc_lo
v_mul_lo_u32 v1, v1, 36
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_clause 0x6
global_load_b32 v13, v[20:21], off
global_load_b32 v14, v[14:15], off
global_load_b32 v15, v[16:17], off
global_load_b32 v16, v[22:23], off
global_load_b32 v8, v[8:9], off
global_load_b32 v9, v[18:19], off
global_load_b32 v17, v[6:7], off
v_add_co_u32 v6, vcc_lo, s2, v11
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v12, vcc_lo
s_clause 0x1
global_load_b32 v5, v[4:5], off
global_load_b32 v6, v[6:7], off
v_mov_b32_e32 v4, 0
v_mul_lo_u32 v7, v10, 36
v_mul_u32_u24_e32 v10, 36, v0
v_mov_b32_e32 v0, 16
s_waitcnt vmcnt(8)
scratch_store_b32 off, v13, off offset:16
s_waitcnt vmcnt(7)
scratch_store_b32 off, v14, off offset:20
s_waitcnt vmcnt(6)
scratch_store_b32 off, v15, off offset:24
s_waitcnt vmcnt(5)
scratch_store_b32 off, v16, off offset:28
s_waitcnt vmcnt(1)
s_clause 0x3
scratch_store_b32 off, v5, off offset:32
scratch_store_b32 off, v8, off offset:36
scratch_store_b32 off, v9, off offset:40
scratch_store_b32 off, v17, off offset:44
s_waitcnt vmcnt(0)
scratch_store_b32 off, v6, off offset:48
v_add3_u32 v1, v1, v7, v10
.p2align 6
.LBB0_4:
s_mov_b32 s1, 0
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, s1, v0
v_add_nc_u32_e32 v6, s1, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cvt_f32_i32_e32 v4, v4
s_add_i32 s1, s1, 4
s_cmp_eq_u32 s1, 12
scratch_load_b32 v5, v5, off
ds_load_b32 v6, v6
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mul_lo_u32 v5, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v5, v5
v_add_f32_e32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v4, v4
s_cbranch_scc0 .LBB0_5
v_add_nc_u32_e32 v0, 12, v0
v_add_nc_u32_e32 v1, 12, v1
s_add_i32 s0, s0, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s0, 3
s_cbranch_scc0 .LBB0_4
v_sub_nc_u32_e32 v0, 0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v0, v4, v0
v_cvt_f32_i32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v0, v0
global_store_b32 v[2:3], v0, off
.LBB0_8:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6bordesPiS_ii
.amdhsa_group_segment_fixed_size 36864
.amdhsa_private_segment_fixed_size 64
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 1
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 24
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6bordesPiS_ii, .Lfunc_end0-_Z6bordesPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 36864
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6bordesPiS_ii
.private_segment_fixed_size: 64
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6bordesPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 24
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define Columnas 10
#define Filas 10
hipError_t addWithCuda(int* c, const int* a, unsigned int size);
__device__ unsigned int computeOutputEdge(int mask[][3], int vecinos[][3], int rows, int cols) {
float result = 1;
int sum = 0;
for (int i = 0; i < rows; i++) {
for (int j = 0; j < cols; j++) {
float mul = mask[i][j] * vecinos[i][j];
sum = sum + mul;
}
}
result = abs(sum);
return (int)result;
}
__global__ void bordes(int* val2, int* val1, int m, int n)
{
int column = threadIdx.x + blockDim.x * blockIdx.x;
int row = threadIdx.y + blockDim.y * blockIdx.y;
int myEdge[3][3] = { {0,1,0},{1,-4,1},{0,1,0} };
//int filas = (sizeof(myMask)/sizeof(myMask[0]));
if (row < m && column < n) {
int thread_id1 = (row - 1) * n + (column - 1);
int thread_id2 = (row - 1) * n + (column);
int thread_id3 = (row - 1) * n + (column + 1);
int thread_id4 = (row)* n + (column - 1);
int thread_id5 = (row)* n + (column);
int thread_id6 = (row)* n + (column + 1);
int thread_id7 = (row + 1) * n + (column - 1);
int thread_id8 = (row + 1) * n + (column);
int thread_id9 = (row + 1) * n + (column + 1);
//int my_val = val1[thread_id5];
//printf("row: %d, \tcol: %d, \tvalor: %d\n", row, column, my_val);
val2[thread_id5] = val1[thread_id5];
if ((row > 0 && row < (m - 1)) && (column > 0 && column < (n - 1)))
{
int my_val0 = val1[thread_id1];
int my_val2 = val1[thread_id2];
int my_val3 = val1[thread_id3];
int my_val4 = val1[thread_id4];
int my_val5 = val1[thread_id5]; //doubly-subscripted access
int my_val6 = val1[thread_id6];
int my_val7 = val1[thread_id7];
int my_val8 = val1[thread_id8];
int my_val9 = val1[thread_id9];
//printf("row: %d, col: %d, value: %d\n", row, column, my_val);
int myMask2[3][3] = { {(my_val0),(my_val2),(my_val3)},
{(my_val4),(my_val5),(my_val6)},
{(my_val7),(my_val8),(my_val9)} };
unsigned int output = computeOutputEdge(myEdge, myMask2, 3, 3);
//printf("row: %d,\t col: %d,\t Valor Original: %d,\t Nuevo Valor: %d\n", row, column, my_val5,output);
//printf("Salida: %d \n", output);
//printf("Entro\n");
val2[thread_id5] = output;
}
}
} | .text
.file "bordes.hip"
.globl _Z21__device_stub__bordesPiS_ii # -- Begin function _Z21__device_stub__bordesPiS_ii
.p2align 4, 0x90
.type _Z21__device_stub__bordesPiS_ii,@function
_Z21__device_stub__bordesPiS_ii: # @_Z21__device_stub__bordesPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6bordesPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__bordesPiS_ii, .Lfunc_end0-_Z21__device_stub__bordesPiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6bordesPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6bordesPiS_ii,@object # @_Z6bordesPiS_ii
.section .rodata,"a",@progbits
.globl _Z6bordesPiS_ii
.p2align 3, 0x0
_Z6bordesPiS_ii:
.quad _Z21__device_stub__bordesPiS_ii
.size _Z6bordesPiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6bordesPiS_ii"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__bordesPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6bordesPiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6bordesPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x170], P0 ; /* 0x00005c0005007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R4, R5, c[0x0][0x174], R0 ; /* 0x00005d0005047a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe40000000a00 */
/*00d0*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe40000000000 */
/*00e0*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fc80000000a00 */
/*00f0*/ IMAD.WIDE R2, R4, R9, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fca00078e0209 */
/*0100*/ LDG.E R7, [R2.64] ; /* 0x0000000802077981 */
/* 0x0000a2000c1e1900 */
/*0110*/ UIADD3 UR4, -UR5, UR6, URZ ; /* 0x0000000605047290 */
/* 0x000fe4000fffe13f */
/*0120*/ UIADD3 UR5, -UR5, UR7, URZ ; /* 0x0000000705057290 */
/* 0x000fc8000fffe13f */
/*0130*/ ISETP.GE.AND P0, PT, R5.reuse, UR4, PT ; /* 0x0000000405007c0c */
/* 0x040fe4000bf06270 */
/*0140*/ ISETP.GE.AND P1, PT, R0, UR5, PT ; /* 0x0000000500007c0c */
/* 0x000fe2000bf26270 */
/*0150*/ IMAD.WIDE R2, R4, R9, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x001fe200078e0209 */
/*0160*/ ISETP.GT.AND P0, PT, R5.reuse, RZ, !P0 ; /* 0x000000ff0500720c */
/* 0x040fe40004704270 */
/*0170*/ ISETP.GT.AND P1, PT, R0, RZ, !P1 ; /* 0x000000ff0000720c */
/* 0x000fe40004f24270 */
/*0180*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*0190*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fc60000703070 */
/*01a0*/ IMAD R5, R5, c[0x0][0x174], R0 ; /* 0x00005d0005057a24 */
/* 0x000fe200078e0200 */
/*01b0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0041f2000c101908 */
/*01c0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*01d0*/ IMAD.WIDE R4, R5, R9, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0209 */
/*01e0*/ LDG.E R0, [R4.64] ; /* 0x0000000804007981 */
/* 0x000ea2000c1e1900 */
/*01f0*/ IMAD.WIDE R6, R9, c[0x0][0x174], R4 ; /* 0x00005d0009067a25 */
/* 0x001fca00078e0204 */
/*0200*/ LDG.E R12, [R6.64+-0x4] ; /* 0xfffffc08060c7981 */
/* 0x000ee8000c1e1900 */
/*0210*/ LDG.E R13, [R6.64] ; /* 0x00000008060d7981 */
/* 0x000f28000c1e1900 */
/*0220*/ LDG.E R14, [R6.64+0x4] ; /* 0x00000408060e7981 */
/* 0x000f62000c1e1900 */
/*0230*/ IMAD.WIDE R8, R9, c[0x0][0x174], R6 ; /* 0x00005d0009087a25 */
/* 0x000fcc00078e0206 */
/*0240*/ LDG.E R8, [R8.64] ; /* 0x0000000808087981 */
/* 0x000f62000c1e1900 */
/*0250*/ I2F R0, R0 ; /* 0x0000000000007306 */
/* 0x004e300000201400 */
/*0260*/ I2F R12, R12 ; /* 0x0000000c000c7306 */
/* 0x008fe20000201400 */
/*0270*/ LEA R13, -R13, RZ, 0x2 ; /* 0x000000ff0d0d7211 */
/* 0x010fe200078e11ff */
/*0280*/ FADD R10, RZ, R0 ; /* 0x00000000ff0a7221 */
/* 0x001fcc0000000000 */
/*0290*/ I2F R4, R13 ; /* 0x0000000d00047306 */
/* 0x000ff00000201400 */
/*02a0*/ F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a7305 */
/* 0x000e30000020f100 */
/*02b0*/ I2F R14, R14 ; /* 0x0000000e000e7306 */
/* 0x020ff00000201400 */
/*02c0*/ I2F R11, R10 ; /* 0x0000000a000b7306 */
/* 0x001e300000201400 */
/*02d0*/ I2F R8, R8 ; /* 0x0000000800087306 */
/* 0x000ff00000201400 */
/*02e0*/ F2I.TRUNC.NTZ R11, R11 ; /* 0x0000000b000b7305 */
/* 0x001e30000020f100 */
/*02f0*/ I2F R5, R11 ; /* 0x0000000b00057306 */
/* 0x001e240000201400 */
/*0300*/ FADD R5, R12, R5 ; /* 0x000000050c057221 */
/* 0x001fcc0000000000 */
/*0310*/ F2I.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000e30000020f100 */
/*0320*/ I2F R7, R5 ; /* 0x0000000500077306 */
/* 0x001e240000201400 */
/*0330*/ FADD R4, R4, R7 ; /* 0x0000000704047221 */
/* 0x001fcc0000000000 */
/*0340*/ F2I.TRUNC.NTZ R4, R4 ; /* 0x0000000400047305 */
/* 0x000e30000020f100 */
/*0350*/ I2F R7, R4 ; /* 0x0000000400077306 */
/* 0x001e240000201400 */
/*0360*/ FADD R7, R14, R7 ; /* 0x000000070e077221 */
/* 0x001fcc0000000000 */
/*0370*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e30000020f100 */
/*0380*/ I2F R0, R7 ; /* 0x0000000700007306 */
/* 0x001e300000201400 */
/*0390*/ F2I.TRUNC.NTZ R0, R0 ; /* 0x0000000000007305 */
/* 0x001e30000020f100 */
/*03a0*/ I2F R9, R0 ; /* 0x0000000000097306 */
/* 0x001e240000201400 */
/*03b0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x001fcc0000000000 */
/*03c0*/ F2I.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e30000020f100 */
/*03d0*/ I2F R5, R9 ; /* 0x0000000900057306 */
/* 0x001e300000201400 */
/*03e0*/ F2I.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x001e24000020f100 */
/*03f0*/ IABS R4, R5 ; /* 0x0000000500047213 */
/* 0x001fcc0000000000 */
/*0400*/ I2F R4, R4 ; /* 0x0000000400047306 */
/* 0x000e300000201400 */
/*0410*/ F2I.TRUNC.NTZ R7, R4 ; /* 0x0000000400077305 */
/* 0x001e24000020f100 */
/*0420*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe2000c101908 */
/*0430*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0440*/ BRA 0x440; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6bordesPiS_ii
.globl _Z6bordesPiS_ii
.p2align 8
.type _Z6bordesPiS_ii,@function
_Z6bordesPiS_ii:
s_load_b64 s[4:5], s[0:1], 0x4
s_clause 0x1
s_load_b32 s0, s[2:3], 0x24
s_load_b64 s[6:7], s[2:3], 0x10
s_mov_b32 s8, 0
v_bfe_u32 v2, v0, 10, 10
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 20, 10
v_dual_mov_b32 v11, -4 :: v_dual_mov_b32 v12, 1
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s4, 16
v_mul_u32_u24_e32 v10, s5, v2
s_mul_i32 s1, s4, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, s1, v1
s_and_b32 s1, s0, 0xffff
s_lshr_b32 s0, s0, 16
v_mad_u64_u32 v[6:7], null, s14, s1, v[1:2]
v_mad_u64_u32 v[8:9], null, s15, s0, v[2:3]
v_add3_u32 v2, v3, v10, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e64 s0, s7, v6
v_mov_b32_e32 v9, 0
v_mul_lo_u32 v7, v2, 36
v_mov_b32_e32 v2, s8
v_cmp_gt_i32_e32 vcc_lo, s6, v8
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
v_mov_b32_e32 v5, s11
ds_store_b128 v7, v[2:5]
ds_store_b128 v7, v[2:5] offset:16
ds_store_b64 v7, v[11:12] offset:16
ds_store_b32 v7, v9 offset:32
ds_store_2addr_b32 v7, v12, v12 offset0:1 offset1:3
ds_store_b32 v7, v12 offset:28
s_and_b32 s0, s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_mul_lo_u32 v7, v8, s7
s_load_b128 s[0:3], s[2:3], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v7, v6
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v9, v[4:5], off
v_cmp_lt_i32_e32 vcc_lo, 0, v8
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v9, off
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_8
s_add_i32 s0, s6, -1
s_add_i32 s1, s7, -1
v_cmp_gt_i32_e32 vcc_lo, s0, v8
v_cmp_gt_i32_e64 s0, s1, v6
v_cmp_lt_i32_e64 s1, 0, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_and_b32 s6, vcc_lo, s0
s_mov_b32 s0, 0
s_and_b32 s1, s6, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v9, -1, v8
v_add_nc_u32_e32 v13, -1, v6
s_mov_b32 s6, s7
v_add_nc_u32_e32 v19, 1, v6
v_mad_u64_u32 v[11:12], null, s7, v8, s[6:7]
v_mul_lo_u32 v9, v9, s7
v_add_nc_u32_e32 v12, v7, v13
s_delay_alu instid0(VALU_DEP_4)
v_add_nc_u32_e32 v7, v7, v19
v_mul_lo_u32 v1, v1, s5
v_add_nc_u32_e32 v18, v11, v13
v_add_nc_u32_e32 v8, v9, v13
v_add_nc_u32_e32 v14, v9, v6
v_add_nc_u32_e32 v16, v9, v19
v_ashrrev_i32_e32 v13, 31, v12
v_add_nc_u32_e32 v6, v11, v6
v_ashrrev_i32_e32 v9, 31, v8
v_ashrrev_i32_e32 v15, 31, v14
v_ashrrev_i32_e32 v17, 31, v16
v_lshlrev_b64 v[12:13], 2, v[12:13]
v_add_nc_u32_e32 v11, v11, v19
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_lshlrev_b64 v[14:15], 2, v[14:15]
v_lshlrev_b64 v[16:17], 2, v[16:17]
v_ashrrev_i32_e32 v19, 31, v18
v_mul_lo_u32 v1, v1, s4
v_add_co_u32 v20, vcc_lo, s2, v8
v_add_co_ci_u32_e32 v21, vcc_lo, s3, v9, vcc_lo
v_add_co_u32 v14, vcc_lo, s2, v14
v_ashrrev_i32_e32 v8, 31, v7
v_add_co_ci_u32_e32 v15, vcc_lo, s3, v15, vcc_lo
v_add_co_u32 v16, vcc_lo, s2, v16
v_add_co_ci_u32_e32 v17, vcc_lo, s3, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_lshlrev_b64 v[8:9], 2, v[7:8]
v_add_co_u32 v22, vcc_lo, s2, v12
v_add_co_ci_u32_e32 v23, vcc_lo, s3, v13, vcc_lo
v_lshlrev_b64 v[12:13], 2, v[18:19]
v_ashrrev_i32_e32 v7, 31, v6
v_add_co_u32 v8, vcc_lo, s2, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_add_co_u32 v18, vcc_lo, s2, v12
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_ci_u32_e32 v19, vcc_lo, s3, v13, vcc_lo
v_mul_lo_u32 v1, v1, 36
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_clause 0x6
global_load_b32 v13, v[20:21], off
global_load_b32 v14, v[14:15], off
global_load_b32 v15, v[16:17], off
global_load_b32 v16, v[22:23], off
global_load_b32 v8, v[8:9], off
global_load_b32 v9, v[18:19], off
global_load_b32 v17, v[6:7], off
v_add_co_u32 v6, vcc_lo, s2, v11
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v12, vcc_lo
s_clause 0x1
global_load_b32 v5, v[4:5], off
global_load_b32 v6, v[6:7], off
v_mov_b32_e32 v4, 0
v_mul_lo_u32 v7, v10, 36
v_mul_u32_u24_e32 v10, 36, v0
v_mov_b32_e32 v0, 16
s_waitcnt vmcnt(8)
scratch_store_b32 off, v13, off offset:16
s_waitcnt vmcnt(7)
scratch_store_b32 off, v14, off offset:20
s_waitcnt vmcnt(6)
scratch_store_b32 off, v15, off offset:24
s_waitcnt vmcnt(5)
scratch_store_b32 off, v16, off offset:28
s_waitcnt vmcnt(1)
s_clause 0x3
scratch_store_b32 off, v5, off offset:32
scratch_store_b32 off, v8, off offset:36
scratch_store_b32 off, v9, off offset:40
scratch_store_b32 off, v17, off offset:44
s_waitcnt vmcnt(0)
scratch_store_b32 off, v6, off offset:48
v_add3_u32 v1, v1, v7, v10
.p2align 6
.LBB0_4:
s_mov_b32 s1, 0
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, s1, v0
v_add_nc_u32_e32 v6, s1, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cvt_f32_i32_e32 v4, v4
s_add_i32 s1, s1, 4
s_cmp_eq_u32 s1, 12
scratch_load_b32 v5, v5, off
ds_load_b32 v6, v6
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mul_lo_u32 v5, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v5, v5
v_add_f32_e32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v4, v4
s_cbranch_scc0 .LBB0_5
v_add_nc_u32_e32 v0, 12, v0
v_add_nc_u32_e32 v1, 12, v1
s_add_i32 s0, s0, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s0, 3
s_cbranch_scc0 .LBB0_4
v_sub_nc_u32_e32 v0, 0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v0, v4, v0
v_cvt_f32_i32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v0, v0
global_store_b32 v[2:3], v0, off
.LBB0_8:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6bordesPiS_ii
.amdhsa_group_segment_fixed_size 36864
.amdhsa_private_segment_fixed_size 64
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 1
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 24
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6bordesPiS_ii, .Lfunc_end0-_Z6bordesPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 36864
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6bordesPiS_ii
.private_segment_fixed_size: 64
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6bordesPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 24
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000aa661_00000000-6_bordes.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z17computeOutputEdgePA3_iS0_ii
.type _Z17computeOutputEdgePA3_iS0_ii, @function
_Z17computeOutputEdgePA3_iS0_ii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z17computeOutputEdgePA3_iS0_ii, .-_Z17computeOutputEdgePA3_iS0_ii
.globl _Z29__device_stub__Z6bordesPiS_iiPiS_ii
.type _Z29__device_stub__Z6bordesPiS_iiPiS_ii, @function
_Z29__device_stub__Z6bordesPiS_iiPiS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6bordesPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z29__device_stub__Z6bordesPiS_iiPiS_ii, .-_Z29__device_stub__Z6bordesPiS_iiPiS_ii
.globl _Z6bordesPiS_ii
.type _Z6bordesPiS_ii, @function
_Z6bordesPiS_ii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6bordesPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z6bordesPiS_ii, .-_Z6bordesPiS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6bordesPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6bordesPiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "bordes.hip"
.globl _Z21__device_stub__bordesPiS_ii # -- Begin function _Z21__device_stub__bordesPiS_ii
.p2align 4, 0x90
.type _Z21__device_stub__bordesPiS_ii,@function
_Z21__device_stub__bordesPiS_ii: # @_Z21__device_stub__bordesPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6bordesPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__bordesPiS_ii, .Lfunc_end0-_Z21__device_stub__bordesPiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6bordesPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6bordesPiS_ii,@object # @_Z6bordesPiS_ii
.section .rodata,"a",@progbits
.globl _Z6bordesPiS_ii
.p2align 3, 0x0
_Z6bordesPiS_ii:
.quad _Z21__device_stub__bordesPiS_ii
.size _Z6bordesPiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6bordesPiS_ii"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__bordesPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6bordesPiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*****************************************************
* This file tests cuda memory management APIs.
*****************************************************/
#include <cuda_runtime.h>
#include <stdio.h>
__global__ void vecAdd(float* A, float* B, float* C) {
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
C[i] = A[i] + B[i];
//printf("From GPU %f.\n", C[i]);
}
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*
* See cuda.h for error code descriptions.
*/
#define CHECK_CUDA_RESULT(N) { \
cudaError_t result = N; \
if (result != 0) { \
printf("CUDA call on line %d returned error %d\n", __LINE__, \
result); \
printf("Error: %s.\n", cudaGetErrorString(result)); \
exit(1); \
} }
void initialData(float *h, long long n, float data) {
long long i;
for (i = 0; i < n; i++) {
h[i] = data;
}
}
void test_cudaDeviceGetAttribute(int* value, cudaDeviceAttr attr, int device) {
cudaDeviceGetAttribute(value, attr, device);
}
void test_cudaMallocManaged(int dev, int ipower) {
int val;
// Check if supports managed memory
CHECK_CUDA_RESULT(cudaDeviceGetAttribute(&val, cudaDevAttrManagedMemory, dev));
// Check concurrent managed access, for cuda 8.0
cudaDeviceGetAttribute(&val, cudaDevAttrConcurrentManagedAccess, dev);
if (!val) {
printf("*** Warn: Concurrent managed access is not supported!\n");
}
// Calculate number of elements and bytes
long long nElem = ((long long) 1) << ipower;
long long nBytes = nElem * sizeof(float);
// allocate memory
float *g_A[64*1024], *g_B[64*1024], *g_C[64*1024];
int totalLoop = 1024*2;
//int totalLoop = 10;
for (int loop=0; loop<totalLoop; loop++) {
printf("==== ==== ==== ==== Loop: %d.\n", loop);
if (ipower < 18) {
printf("Vector size is %lld, nbytes is %f KB\n", nElem,
(float) nBytes / (1024.0f));
} else {
printf("Vector size is %lld, nbytes is %f MB\n", nElem,
(float) nBytes / (1024.0f * 1024.0f));
}
// unsigned int flags = cudaMemAttachHost;
unsigned int flags = cudaMemAttachGlobal;
CHECK_CUDA_RESULT(cudaMallocManaged(&g_A[loop], nBytes, flags));
CHECK_CUDA_RESULT(cudaMallocManaged(&g_B[loop], nBytes, flags));
CHECK_CUDA_RESULT(cudaMallocManaged(&g_C[loop], nBytes, flags));
printf("===== inital data begins...\n");
initialData(g_A[loop], nElem, 2.0f);
initialData(g_B[loop], nElem, 2.0f);
printf("===== synchronize begins...\n");
cudaDeviceSynchronize();
printf("===== add data begins...\n");
dim3 threadsPerBlock(1024);
dim3 numBlocks((nElem+threadsPerBlock.x-1) / threadsPerBlock.x);
printf("===== numBlocks is %d, threadsPerBlock is %d\n", numBlocks.x, threadsPerBlock.x);
// Kernel invocation with N threads
vecAdd<<<numBlocks, threadsPerBlock>>>(g_A[loop], g_B[loop], g_C[loop]);
//cudaMemcpy(g_C[loop], g_A[loop], nElem, cudaMemcpyDeviceToDevice);
cudaDeviceSynchronize();
}
printf("===== Check the results...\n");
float ans = 4.0f;
printf("===== ans is %f\n", ans);
for (int i = 0; i < totalLoop; i++) {
printf("\n======================================================\n");
for (int j = 0; j < 8; j++) {
//if ((g_C[i])[j] != ans)
{
printf("%3.0f ", (g_C[i])[j]);
}
}
}
printf("\n");
cudaFree(g_A);
cudaFree(g_B);
cudaFree(g_C);
cudaDeviceReset();
}
int main(int argc, char* argv[]) {
// set up device
int dev = 0;
cudaSetDevice(dev);
// get device properties
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, dev);
// check uva supporting
if (deviceProp.unifiedAddressing) {
printf("Device %d supports uva memory!\n", dev);
} else {
printf("Device %d does not support uva memory!\n", dev);
exit(EXIT_SUCCESS);
}
// set up date size of vectors
int ipower = 20+4;
if (argc > 1)
ipower = atoi(argv[1]);
test_cudaMallocManaged(dev, ipower);
} | code for sm_80
Function : _Z6vecAddPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0007 */
/*0070*/ IMAD.WIDE.U32 R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0007 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0007 */
/*00b0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*****************************************************
* This file tests cuda memory management APIs.
*****************************************************/
#include <cuda_runtime.h>
#include <stdio.h>
__global__ void vecAdd(float* A, float* B, float* C) {
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
C[i] = A[i] + B[i];
//printf("From GPU %f.\n", C[i]);
}
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*
* See cuda.h for error code descriptions.
*/
#define CHECK_CUDA_RESULT(N) { \
cudaError_t result = N; \
if (result != 0) { \
printf("CUDA call on line %d returned error %d\n", __LINE__, \
result); \
printf("Error: %s.\n", cudaGetErrorString(result)); \
exit(1); \
} }
void initialData(float *h, long long n, float data) {
long long i;
for (i = 0; i < n; i++) {
h[i] = data;
}
}
void test_cudaDeviceGetAttribute(int* value, cudaDeviceAttr attr, int device) {
cudaDeviceGetAttribute(value, attr, device);
}
void test_cudaMallocManaged(int dev, int ipower) {
int val;
// Check if supports managed memory
CHECK_CUDA_RESULT(cudaDeviceGetAttribute(&val, cudaDevAttrManagedMemory, dev));
// Check concurrent managed access, for cuda 8.0
cudaDeviceGetAttribute(&val, cudaDevAttrConcurrentManagedAccess, dev);
if (!val) {
printf("*** Warn: Concurrent managed access is not supported!\n");
}
// Calculate number of elements and bytes
long long nElem = ((long long) 1) << ipower;
long long nBytes = nElem * sizeof(float);
// allocate memory
float *g_A[64*1024], *g_B[64*1024], *g_C[64*1024];
int totalLoop = 1024*2;
//int totalLoop = 10;
for (int loop=0; loop<totalLoop; loop++) {
printf("==== ==== ==== ==== Loop: %d.\n", loop);
if (ipower < 18) {
printf("Vector size is %lld, nbytes is %f KB\n", nElem,
(float) nBytes / (1024.0f));
} else {
printf("Vector size is %lld, nbytes is %f MB\n", nElem,
(float) nBytes / (1024.0f * 1024.0f));
}
// unsigned int flags = cudaMemAttachHost;
unsigned int flags = cudaMemAttachGlobal;
CHECK_CUDA_RESULT(cudaMallocManaged(&g_A[loop], nBytes, flags));
CHECK_CUDA_RESULT(cudaMallocManaged(&g_B[loop], nBytes, flags));
CHECK_CUDA_RESULT(cudaMallocManaged(&g_C[loop], nBytes, flags));
printf("===== inital data begins...\n");
initialData(g_A[loop], nElem, 2.0f);
initialData(g_B[loop], nElem, 2.0f);
printf("===== synchronize begins...\n");
cudaDeviceSynchronize();
printf("===== add data begins...\n");
dim3 threadsPerBlock(1024);
dim3 numBlocks((nElem+threadsPerBlock.x-1) / threadsPerBlock.x);
printf("===== numBlocks is %d, threadsPerBlock is %d\n", numBlocks.x, threadsPerBlock.x);
// Kernel invocation with N threads
vecAdd<<<numBlocks, threadsPerBlock>>>(g_A[loop], g_B[loop], g_C[loop]);
//cudaMemcpy(g_C[loop], g_A[loop], nElem, cudaMemcpyDeviceToDevice);
cudaDeviceSynchronize();
}
printf("===== Check the results...\n");
float ans = 4.0f;
printf("===== ans is %f\n", ans);
for (int i = 0; i < totalLoop; i++) {
printf("\n======================================================\n");
for (int j = 0; j < 8; j++) {
//if ((g_C[i])[j] != ans)
{
printf("%3.0f ", (g_C[i])[j]);
}
}
}
printf("\n");
cudaFree(g_A);
cudaFree(g_B);
cudaFree(g_C);
cudaDeviceReset();
}
int main(int argc, char* argv[]) {
// set up device
int dev = 0;
cudaSetDevice(dev);
// get device properties
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, dev);
// check uva supporting
if (deviceProp.unifiedAddressing) {
printf("Device %d supports uva memory!\n", dev);
} else {
printf("Device %d does not support uva memory!\n", dev);
exit(EXIT_SUCCESS);
}
// set up date size of vectors
int ipower = 20+4;
if (argc > 1)
ipower = atoi(argv[1]);
test_cudaMallocManaged(dev, ipower);
} | .file "tmpxft_0006e891_00000000-6_uma.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initialDataPfxf
.type _Z11initialDataPfxf, @function
_Z11initialDataPfxf:
.LFB2057:
.cfi_startproc
endbr64
testq %rsi, %rsi
jle .L3
movq %rdi, %rax
leaq (%rdi,%rsi,4), %rdx
.L5:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z11initialDataPfxf, .-_Z11initialDataPfxf
.globl _Z27test_cudaDeviceGetAttributePi14cudaDeviceAttri
.type _Z27test_cudaDeviceGetAttributePi14cudaDeviceAttri, @function
_Z27test_cudaDeviceGetAttributePi14cudaDeviceAttri:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaDeviceGetAttribute@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z27test_cudaDeviceGetAttributePi14cudaDeviceAttri, .-_Z27test_cudaDeviceGetAttributePi14cudaDeviceAttri
.globl _Z29__device_stub__Z6vecAddPfS_S_PfS_S_
.type _Z29__device_stub__Z6vecAddPfS_S_PfS_S_, @function
_Z29__device_stub__Z6vecAddPfS_S_PfS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecAddPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z29__device_stub__Z6vecAddPfS_S_PfS_S_, .-_Z29__device_stub__Z6vecAddPfS_S_PfS_S_
.globl _Z6vecAddPfS_S_
.type _Z6vecAddPfS_S_, @function
_Z6vecAddPfS_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6vecAddPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z6vecAddPfS_S_, .-_Z6vecAddPfS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "CUDA call on line %d returned error %d\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Error: %s.\n"
.section .rodata.str1.8
.align 8
.LC2:
.string "*** Warn: Concurrent managed access is not supported!\n"
.align 8
.LC3:
.string "==== ==== ==== ==== Loop: %d.\n"
.align 8
.LC5:
.string "Vector size is %lld, nbytes is %f KB\n"
.align 8
.LC7:
.string "Vector size is %lld, nbytes is %f MB\n"
.section .rodata.str1.1
.LC8:
.string "===== inital data begins...\n"
.LC10:
.string "===== synchronize begins...\n"
.LC11:
.string "===== add data begins...\n"
.section .rodata.str1.8
.align 8
.LC12:
.string "===== numBlocks is %d, threadsPerBlock is %d\n"
.section .rodata.str1.1
.LC13:
.string "===== Check the results...\n"
.LC15:
.string "===== ans is %f\n"
.section .rodata.str1.8
.align 8
.LC16:
.string "\n======================================================\n"
.section .rodata.str1.1
.LC17:
.string "%3.0f "
.LC18:
.string "\n"
.text
.globl _Z22test_cudaMallocManagedii
.type _Z22test_cudaMallocManagedii, @function
_Z22test_cudaMallocManagedii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
leaq -1572864(%rsp), %r11
.cfi_def_cfa 11, 1572920
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $88, %rsp
.cfi_def_cfa_offset 1573008
movl %edi, %ebp
movl %esi, 20(%rsp)
movq %fs:40, %rax
movq %rax, 1572936(%rsp)
xorl %eax, %eax
leaq 36(%rsp), %rdi
movl %ebp, %edx
movl $83, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L34
leaq 36(%rsp), %rdi
movl %ebp, %edx
movl $89, %esi
call cudaDeviceGetAttribute@PLT
cmpl $0, 36(%rsp)
je .L35
.L19:
movl $1, %eax
movl 20(%rsp), %ebx
movl %ebx, %ecx
salq %cl, %rax
movl $4, %edx
salq %cl, %rdx
movq %rdx, %r12
leaq 2046(%rax), %rdx
movq %rax, %rcx
addq $1023, %rcx
cmovns %rcx, %rdx
sarq $10, %rdx
movl %edx, 16(%rsp)
leaq 524352(%rsp), %r13
leaq 64(%rsp), %r14
movl $0, %ebp
movq %rax, 8(%rsp)
jmp .L26
.L34:
movl %eax, %ebx
movl %eax, %ecx
movl $43, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L35:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L19
.L20:
pxor %xmm0, %xmm0
cvtsi2ssq %r12, %xmm0
mulss .LC6(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq 8(%rsp), %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.L21:
movl $1, %edx
movq %r12, %rsi
movq %r14, %rdi
call cudaMallocManaged@PLT
testl %eax, %eax
jne .L36
movl $1, %edx
movq %r12, %rsi
movq %r13, %rdi
call cudaMallocManaged@PLT
testl %eax, %eax
jne .L37
leaq 1048640(%rsp), %rax
movq %rax, 24(%rsp)
leaq (%rax,%rbp,8), %rdi
movl $1, %edx
movq %r12, %rsi
call cudaMallocManaged@PLT
testl %eax, %eax
jne .L38
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%r14), %rdi
movss .LC9(%rip), %xmm0
movq 8(%rsp), %rsi
call _Z11initialDataPfxf
movq 0(%r13), %rdi
movss .LC9(%rip), %xmm0
movq 8(%rsp), %rsi
call _Z11initialDataPfxf
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceSynchronize@PLT
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1024, %ecx
movl 16(%rsp), %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 16(%rsp), %eax
movl %eax, 52(%rsp)
movl $1024, 40(%rsp)
movl 48(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movq 52(%rsp), %rdi
movl 60(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L25:
call cudaDeviceSynchronize@PLT
addq $1, %rbp
addq $8, %r13
addq $8, %r14
cmpq $2048, %rbp
je .L40
.L26:
movl %ebp, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $17, 20(%rsp)
jg .L20
pxor %xmm0, %xmm0
cvtsi2ssq %r12, %xmm0
mulss .LC4(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq 8(%rsp), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L21
.L36:
movl %eax, %ebx
movl %eax, %ecx
movl $72, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L37:
movl %eax, %ebx
movl %eax, %ecx
movl $73, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
movl %eax, %ebx
movl %eax, %ecx
movl $74, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L39:
movq 1048640(%rsp,%rbp,8), %rdx
movq 0(%r13), %rsi
movq (%r14), %rdi
call _Z29__device_stub__Z6vecAddPfS_S_PfS_S_
jmp .L25
.L40:
movq 24(%rsp), %rbx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movsd .LC14(%rip), %xmm0
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 16384(%rbx), %r14
leaq .LC16(%rip), %r13
leaq .LC17(%rip), %r12
jmp .L28
.L42:
addq $8, %rbx
cmpq %r14, %rbx
je .L41
.L28:
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebp
.L27:
movq (%rbx), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbp), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbp
cmpq $32, %rbp
jne .L27
jmp .L42
.L41:
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 64(%rsp), %rdi
call cudaFree@PLT
leaq 524352(%rsp), %rdi
call cudaFree@PLT
leaq 1048640(%rsp), %rdi
call cudaFree@PLT
call cudaDeviceReset@PLT
movq 1572936(%rsp), %rax
subq %fs:40, %rax
jne .L43
addq $1572952, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z22test_cudaMallocManagedii, .-_Z22test_cudaMallocManagedii
.section .rodata.str1.8
.align 8
.LC19:
.string "Device %d supports uva memory!\n"
.align 8
.LC20:
.string "Device %d does not support uva memory!\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1048, %rsp
.cfi_def_cfa_offset 1072
movl %edi, %ebx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 1032(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
movq %rsp, %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
cmpl $0, 604(%rsp)
je .L45
movl $0, %edx
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $24, %esi
cmpl $1, %ebx
jg .L50
.L47:
movl $0, %edi
call _Z22test_cudaMallocManagedii
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L51
movl $0, %eax
addq $1048, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
movl $0, %edx
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L50:
movq 8(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %esi
jmp .L47
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC21:
.string "_Z6vecAddPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecAddPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 981467136
.align 4
.LC6:
.long 897581056
.align 4
.LC9:
.long 1073741824
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC14:
.long 0
.long 1074790400
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*****************************************************
* This file tests cuda memory management APIs.
*****************************************************/
#include <cuda_runtime.h>
#include <stdio.h>
__global__ void vecAdd(float* A, float* B, float* C) {
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
C[i] = A[i] + B[i];
//printf("From GPU %f.\n", C[i]);
}
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*
* See cuda.h for error code descriptions.
*/
#define CHECK_CUDA_RESULT(N) { \
cudaError_t result = N; \
if (result != 0) { \
printf("CUDA call on line %d returned error %d\n", __LINE__, \
result); \
printf("Error: %s.\n", cudaGetErrorString(result)); \
exit(1); \
} }
void initialData(float *h, long long n, float data) {
long long i;
for (i = 0; i < n; i++) {
h[i] = data;
}
}
void test_cudaDeviceGetAttribute(int* value, cudaDeviceAttr attr, int device) {
cudaDeviceGetAttribute(value, attr, device);
}
void test_cudaMallocManaged(int dev, int ipower) {
int val;
// Check if supports managed memory
CHECK_CUDA_RESULT(cudaDeviceGetAttribute(&val, cudaDevAttrManagedMemory, dev));
// Check concurrent managed access, for cuda 8.0
cudaDeviceGetAttribute(&val, cudaDevAttrConcurrentManagedAccess, dev);
if (!val) {
printf("*** Warn: Concurrent managed access is not supported!\n");
}
// Calculate number of elements and bytes
long long nElem = ((long long) 1) << ipower;
long long nBytes = nElem * sizeof(float);
// allocate memory
float *g_A[64*1024], *g_B[64*1024], *g_C[64*1024];
int totalLoop = 1024*2;
//int totalLoop = 10;
for (int loop=0; loop<totalLoop; loop++) {
printf("==== ==== ==== ==== Loop: %d.\n", loop);
if (ipower < 18) {
printf("Vector size is %lld, nbytes is %f KB\n", nElem,
(float) nBytes / (1024.0f));
} else {
printf("Vector size is %lld, nbytes is %f MB\n", nElem,
(float) nBytes / (1024.0f * 1024.0f));
}
// unsigned int flags = cudaMemAttachHost;
unsigned int flags = cudaMemAttachGlobal;
CHECK_CUDA_RESULT(cudaMallocManaged(&g_A[loop], nBytes, flags));
CHECK_CUDA_RESULT(cudaMallocManaged(&g_B[loop], nBytes, flags));
CHECK_CUDA_RESULT(cudaMallocManaged(&g_C[loop], nBytes, flags));
printf("===== inital data begins...\n");
initialData(g_A[loop], nElem, 2.0f);
initialData(g_B[loop], nElem, 2.0f);
printf("===== synchronize begins...\n");
cudaDeviceSynchronize();
printf("===== add data begins...\n");
dim3 threadsPerBlock(1024);
dim3 numBlocks((nElem+threadsPerBlock.x-1) / threadsPerBlock.x);
printf("===== numBlocks is %d, threadsPerBlock is %d\n", numBlocks.x, threadsPerBlock.x);
// Kernel invocation with N threads
vecAdd<<<numBlocks, threadsPerBlock>>>(g_A[loop], g_B[loop], g_C[loop]);
//cudaMemcpy(g_C[loop], g_A[loop], nElem, cudaMemcpyDeviceToDevice);
cudaDeviceSynchronize();
}
printf("===== Check the results...\n");
float ans = 4.0f;
printf("===== ans is %f\n", ans);
for (int i = 0; i < totalLoop; i++) {
printf("\n======================================================\n");
for (int j = 0; j < 8; j++) {
//if ((g_C[i])[j] != ans)
{
printf("%3.0f ", (g_C[i])[j]);
}
}
}
printf("\n");
cudaFree(g_A);
cudaFree(g_B);
cudaFree(g_C);
cudaDeviceReset();
}
int main(int argc, char* argv[]) {
// set up device
int dev = 0;
cudaSetDevice(dev);
// get device properties
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, dev);
// check uva supporting
if (deviceProp.unifiedAddressing) {
printf("Device %d supports uva memory!\n", dev);
} else {
printf("Device %d does not support uva memory!\n", dev);
exit(EXIT_SUCCESS);
}
// set up date size of vectors
int ipower = 20+4;
if (argc > 1)
ipower = atoi(argv[1]);
test_cudaMallocManaged(dev, ipower);
} | /*****************************************************
* This file tests cuda memory management APIs.
*****************************************************/
#include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void vecAdd(float* A, float* B, float* C) {
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
C[i] = A[i] + B[i];
//printf("From GPU %f.\n", C[i]);
}
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*
* See cuda.h for error code descriptions.
*/
#define CHECK_CUDA_RESULT(N) { \
hipError_t result = N; \
if (result != 0) { \
printf("CUDA call on line %d returned error %d\n", __LINE__, \
result); \
printf("Error: %s.\n", hipGetErrorString(result)); \
exit(1); \
} }
void initialData(float *h, long long n, float data) {
long long i;
for (i = 0; i < n; i++) {
h[i] = data;
}
}
void test_cudaDeviceGetAttribute(int* value, hipDeviceAttribute_t attr, int device) {
hipDeviceGetAttribute(value, attr, device);
}
void test_cudaMallocManaged(int dev, int ipower) {
int val;
// Check if supports managed memory
CHECK_CUDA_RESULT(hipDeviceGetAttribute(&val, hipDeviceAttributeManagedMemory, dev));
// Check concurrent managed access, for cuda 8.0
hipDeviceGetAttribute(&val, hipDeviceAttributeConcurrentManagedAccess, dev);
if (!val) {
printf("*** Warn: Concurrent managed access is not supported!\n");
}
// Calculate number of elements and bytes
long long nElem = ((long long) 1) << ipower;
long long nBytes = nElem * sizeof(float);
// allocate memory
float *g_A[64*1024], *g_B[64*1024], *g_C[64*1024];
int totalLoop = 1024*2;
//int totalLoop = 10;
for (int loop=0; loop<totalLoop; loop++) {
printf("==== ==== ==== ==== Loop: %d.\n", loop);
if (ipower < 18) {
printf("Vector size is %lld, nbytes is %f KB\n", nElem,
(float) nBytes / (1024.0f));
} else {
printf("Vector size is %lld, nbytes is %f MB\n", nElem,
(float) nBytes / (1024.0f * 1024.0f));
}
// unsigned int flags = cudaMemAttachHost;
unsigned int flags = hipMemAttachGlobal;
CHECK_CUDA_RESULT(hipMallocManaged(&g_A[loop], nBytes, flags));
CHECK_CUDA_RESULT(hipMallocManaged(&g_B[loop], nBytes, flags));
CHECK_CUDA_RESULT(hipMallocManaged(&g_C[loop], nBytes, flags));
printf("===== inital data begins...\n");
initialData(g_A[loop], nElem, 2.0f);
initialData(g_B[loop], nElem, 2.0f);
printf("===== synchronize begins...\n");
hipDeviceSynchronize();
printf("===== add data begins...\n");
dim3 threadsPerBlock(1024);
dim3 numBlocks((nElem+threadsPerBlock.x-1) / threadsPerBlock.x);
printf("===== numBlocks is %d, threadsPerBlock is %d\n", numBlocks.x, threadsPerBlock.x);
// Kernel invocation with N threads
vecAdd<<<numBlocks, threadsPerBlock>>>(g_A[loop], g_B[loop], g_C[loop]);
//cudaMemcpy(g_C[loop], g_A[loop], nElem, cudaMemcpyDeviceToDevice);
hipDeviceSynchronize();
}
printf("===== Check the results...\n");
float ans = 4.0f;
printf("===== ans is %f\n", ans);
for (int i = 0; i < totalLoop; i++) {
printf("\n======================================================\n");
for (int j = 0; j < 8; j++) {
//if ((g_C[i])[j] != ans)
{
printf("%3.0f ", (g_C[i])[j]);
}
}
}
printf("\n");
hipFree(g_A);
hipFree(g_B);
hipFree(g_C);
hipDeviceReset();
}
int main(int argc, char* argv[]) {
// set up device
int dev = 0;
hipSetDevice(dev);
// get device properties
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, dev);
// check uva supporting
if (deviceProp.unifiedAddressing) {
printf("Device %d supports uva memory!\n", dev);
} else {
printf("Device %d does not support uva memory!\n", dev);
exit(EXIT_SUCCESS);
}
// set up date size of vectors
int ipower = 20+4;
if (argc > 1)
ipower = atoi(argv[1]);
test_cudaMallocManaged(dev, ipower);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*****************************************************
* This file tests cuda memory management APIs.
*****************************************************/
#include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void vecAdd(float* A, float* B, float* C) {
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
C[i] = A[i] + B[i];
//printf("From GPU %f.\n", C[i]);
}
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*
* See cuda.h for error code descriptions.
*/
#define CHECK_CUDA_RESULT(N) { \
hipError_t result = N; \
if (result != 0) { \
printf("CUDA call on line %d returned error %d\n", __LINE__, \
result); \
printf("Error: %s.\n", hipGetErrorString(result)); \
exit(1); \
} }
void initialData(float *h, long long n, float data) {
long long i;
for (i = 0; i < n; i++) {
h[i] = data;
}
}
void test_cudaDeviceGetAttribute(int* value, hipDeviceAttribute_t attr, int device) {
hipDeviceGetAttribute(value, attr, device);
}
void test_cudaMallocManaged(int dev, int ipower) {
int val;
// Check if supports managed memory
CHECK_CUDA_RESULT(hipDeviceGetAttribute(&val, hipDeviceAttributeManagedMemory, dev));
// Check concurrent managed access, for cuda 8.0
hipDeviceGetAttribute(&val, hipDeviceAttributeConcurrentManagedAccess, dev);
if (!val) {
printf("*** Warn: Concurrent managed access is not supported!\n");
}
// Calculate number of elements and bytes
long long nElem = ((long long) 1) << ipower;
long long nBytes = nElem * sizeof(float);
// allocate memory
float *g_A[64*1024], *g_B[64*1024], *g_C[64*1024];
int totalLoop = 1024*2;
//int totalLoop = 10;
for (int loop=0; loop<totalLoop; loop++) {
printf("==== ==== ==== ==== Loop: %d.\n", loop);
if (ipower < 18) {
printf("Vector size is %lld, nbytes is %f KB\n", nElem,
(float) nBytes / (1024.0f));
} else {
printf("Vector size is %lld, nbytes is %f MB\n", nElem,
(float) nBytes / (1024.0f * 1024.0f));
}
// unsigned int flags = cudaMemAttachHost;
unsigned int flags = hipMemAttachGlobal;
CHECK_CUDA_RESULT(hipMallocManaged(&g_A[loop], nBytes, flags));
CHECK_CUDA_RESULT(hipMallocManaged(&g_B[loop], nBytes, flags));
CHECK_CUDA_RESULT(hipMallocManaged(&g_C[loop], nBytes, flags));
printf("===== inital data begins...\n");
initialData(g_A[loop], nElem, 2.0f);
initialData(g_B[loop], nElem, 2.0f);
printf("===== synchronize begins...\n");
hipDeviceSynchronize();
printf("===== add data begins...\n");
dim3 threadsPerBlock(1024);
dim3 numBlocks((nElem+threadsPerBlock.x-1) / threadsPerBlock.x);
printf("===== numBlocks is %d, threadsPerBlock is %d\n", numBlocks.x, threadsPerBlock.x);
// Kernel invocation with N threads
vecAdd<<<numBlocks, threadsPerBlock>>>(g_A[loop], g_B[loop], g_C[loop]);
//cudaMemcpy(g_C[loop], g_A[loop], nElem, cudaMemcpyDeviceToDevice);
hipDeviceSynchronize();
}
printf("===== Check the results...\n");
float ans = 4.0f;
printf("===== ans is %f\n", ans);
for (int i = 0; i < totalLoop; i++) {
printf("\n======================================================\n");
for (int j = 0; j < 8; j++) {
//if ((g_C[i])[j] != ans)
{
printf("%3.0f ", (g_C[i])[j]);
}
}
}
printf("\n");
hipFree(g_A);
hipFree(g_B);
hipFree(g_C);
hipDeviceReset();
}
int main(int argc, char* argv[]) {
// set up device
int dev = 0;
hipSetDevice(dev);
// get device properties
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, dev);
// check uva supporting
if (deviceProp.unifiedAddressing) {
printf("Device %d supports uva memory!\n", dev);
} else {
printf("Device %d does not support uva memory!\n", dev);
exit(EXIT_SUCCESS);
}
// set up date size of vectors
int ipower = 20+4;
if (argc > 1)
ipower = atoi(argv[1]);
test_cudaMallocManaged(dev, ipower);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecAddPfS_S_
.globl _Z6vecAddPfS_S_
.p2align 8
.type _Z6vecAddPfS_S_,@function
_Z6vecAddPfS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecAddPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecAddPfS_S_, .Lfunc_end0-_Z6vecAddPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecAddPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecAddPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*****************************************************
* This file tests cuda memory management APIs.
*****************************************************/
#include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void vecAdd(float* A, float* B, float* C) {
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
C[i] = A[i] + B[i];
//printf("From GPU %f.\n", C[i]);
}
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*
* See cuda.h for error code descriptions.
*/
#define CHECK_CUDA_RESULT(N) { \
hipError_t result = N; \
if (result != 0) { \
printf("CUDA call on line %d returned error %d\n", __LINE__, \
result); \
printf("Error: %s.\n", hipGetErrorString(result)); \
exit(1); \
} }
void initialData(float *h, long long n, float data) {
long long i;
for (i = 0; i < n; i++) {
h[i] = data;
}
}
void test_cudaDeviceGetAttribute(int* value, hipDeviceAttribute_t attr, int device) {
hipDeviceGetAttribute(value, attr, device);
}
void test_cudaMallocManaged(int dev, int ipower) {
int val;
// Check if supports managed memory
CHECK_CUDA_RESULT(hipDeviceGetAttribute(&val, hipDeviceAttributeManagedMemory, dev));
// Check concurrent managed access, for cuda 8.0
hipDeviceGetAttribute(&val, hipDeviceAttributeConcurrentManagedAccess, dev);
if (!val) {
printf("*** Warn: Concurrent managed access is not supported!\n");
}
// Calculate number of elements and bytes
long long nElem = ((long long) 1) << ipower;
long long nBytes = nElem * sizeof(float);
// allocate memory
float *g_A[64*1024], *g_B[64*1024], *g_C[64*1024];
int totalLoop = 1024*2;
//int totalLoop = 10;
for (int loop=0; loop<totalLoop; loop++) {
printf("==== ==== ==== ==== Loop: %d.\n", loop);
if (ipower < 18) {
printf("Vector size is %lld, nbytes is %f KB\n", nElem,
(float) nBytes / (1024.0f));
} else {
printf("Vector size is %lld, nbytes is %f MB\n", nElem,
(float) nBytes / (1024.0f * 1024.0f));
}
// unsigned int flags = cudaMemAttachHost;
unsigned int flags = hipMemAttachGlobal;
CHECK_CUDA_RESULT(hipMallocManaged(&g_A[loop], nBytes, flags));
CHECK_CUDA_RESULT(hipMallocManaged(&g_B[loop], nBytes, flags));
CHECK_CUDA_RESULT(hipMallocManaged(&g_C[loop], nBytes, flags));
printf("===== inital data begins...\n");
initialData(g_A[loop], nElem, 2.0f);
initialData(g_B[loop], nElem, 2.0f);
printf("===== synchronize begins...\n");
hipDeviceSynchronize();
printf("===== add data begins...\n");
dim3 threadsPerBlock(1024);
dim3 numBlocks((nElem+threadsPerBlock.x-1) / threadsPerBlock.x);
printf("===== numBlocks is %d, threadsPerBlock is %d\n", numBlocks.x, threadsPerBlock.x);
// Kernel invocation with N threads
vecAdd<<<numBlocks, threadsPerBlock>>>(g_A[loop], g_B[loop], g_C[loop]);
//cudaMemcpy(g_C[loop], g_A[loop], nElem, cudaMemcpyDeviceToDevice);
hipDeviceSynchronize();
}
printf("===== Check the results...\n");
float ans = 4.0f;
printf("===== ans is %f\n", ans);
for (int i = 0; i < totalLoop; i++) {
printf("\n======================================================\n");
for (int j = 0; j < 8; j++) {
//if ((g_C[i])[j] != ans)
{
printf("%3.0f ", (g_C[i])[j]);
}
}
}
printf("\n");
hipFree(g_A);
hipFree(g_B);
hipFree(g_C);
hipDeviceReset();
}
int main(int argc, char* argv[]) {
// set up device
int dev = 0;
hipSetDevice(dev);
// get device properties
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, dev);
// check uva supporting
if (deviceProp.unifiedAddressing) {
printf("Device %d supports uva memory!\n", dev);
} else {
printf("Device %d does not support uva memory!\n", dev);
exit(EXIT_SUCCESS);
}
// set up date size of vectors
int ipower = 20+4;
if (argc > 1)
ipower = atoi(argv[1]);
test_cudaMallocManaged(dev, ipower);
} | .text
.file "uma.hip"
.globl _Z21__device_stub__vecAddPfS_S_ # -- Begin function _Z21__device_stub__vecAddPfS_S_
.p2align 4, 0x90
.type _Z21__device_stub__vecAddPfS_S_,@function
_Z21__device_stub__vecAddPfS_S_: # @_Z21__device_stub__vecAddPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecAddPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__vecAddPfS_S_, .Lfunc_end0-_Z21__device_stub__vecAddPfS_S_
.cfi_endproc
# -- End function
.globl _Z11initialDataPfxf # -- Begin function _Z11initialDataPfxf
.p2align 4, 0x90
.type _Z11initialDataPfxf,@function
_Z11initialDataPfxf: # @_Z11initialDataPfxf
.cfi_startproc
# %bb.0:
testq %rsi, %rsi
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss %xmm0, (%rdi,%rax,4)
incq %rax
cmpq %rax, %rsi
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z11initialDataPfxf, .Lfunc_end1-_Z11initialDataPfxf
.cfi_endproc
# -- End function
.globl _Z27test_cudaDeviceGetAttributePi20hipDeviceAttribute_ti # -- Begin function _Z27test_cudaDeviceGetAttributePi20hipDeviceAttribute_ti
.p2align 4, 0x90
.type _Z27test_cudaDeviceGetAttributePi20hipDeviceAttribute_ti,@function
_Z27test_cudaDeviceGetAttributePi20hipDeviceAttribute_ti: # @_Z27test_cudaDeviceGetAttributePi20hipDeviceAttribute_ti
.cfi_startproc
# %bb.0:
jmp hipDeviceGetAttribute # TAILCALL
.Lfunc_end2:
.size _Z27test_cudaDeviceGetAttributePi20hipDeviceAttribute_ti, .Lfunc_end2-_Z27test_cudaDeviceGetAttributePi20hipDeviceAttribute_ti
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z22test_cudaMallocManagedii
.LCPI3_0:
.long 0x35800000 # float 9.53674316E-7
.LCPI3_1:
.long 0x3a800000 # float 9.765625E-4
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI3_2:
.quad 0x4010000000000000 # double 4
.text
.globl _Z22test_cudaMallocManagedii
.p2align 4, 0x90
.type _Z22test_cudaMallocManagedii,@function
_Z22test_cudaMallocManagedii: # @_Z22test_cudaMallocManagedii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1573048, %rsp # imm = 0x1800B8
.cfi_def_cfa_offset 1573104
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movl %edi, %ebx
leaq 12(%rsp), %rdi
movl $24, %esi
movl %ebx, %edx
callq hipDeviceGetAttribute
testl %eax, %eax
jne .LBB3_1
# %bb.4:
leaq 12(%rsp), %rdi
movl $9, %esi
movl %ebx, %edx
callq hipDeviceGetAttribute
cmpl $0, 12(%rsp)
jne .LBB3_6
# %bb.5:
movl $.Lstr, %edi
callq puts@PLT
.LBB3_6:
movl $1, %r14d
movl %ebp, %ecx
shlq %cl, %r14
movl $4, %ebx
shlq %cl, %rbx
movabsq $4294967296, %rcx # imm = 0x100000000
cvtsi2ss %rbx, %xmm0
movss .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm0, %xmm1
mulss .LCPI3_1(%rip), %xmm0
cvtss2sd %xmm1, %xmm1
movsd %xmm1, 32(%rsp) # 8-byte Spill
cvtss2sd %xmm0, %xmm0
movsd %xmm0, 24(%rsp) # 8-byte Spill
leaq 1023(%r14), %rax
leaq 2046(%r14), %rdx
testq %rax, %rax
cmovnsq %rax, %rdx
sarq $10, %rdx
movq %rdx, 48(%rsp) # 8-byte Spill
movl %edx, %eax
orq %rcx, %rax
movq %rax, 40(%rsp) # 8-byte Spill
addq $1024, %rcx # imm = 0x400
movq %rcx, 56(%rsp) # 8-byte Spill
xorl %r12d, %r12d
movq %rbx, 64(%rsp) # 8-byte Spill
jmp .LBB3_7
.p2align 4, 0x90
.LBB3_22: # %_Z11initialDataPfxf.exit74
# in Loop: Header=BB3_7 Depth=1
movl $.Lstr.4, %edi
callq puts@PLT
callq hipDeviceSynchronize
movl $.Lstr.5, %edi
callq puts@PLT
movl $.L.str.9, %edi
movq 48(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
movl $1024, %edx # imm = 0x400
xorl %eax, %eax
callq printf
movq 40(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movq 56(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB3_23
.LBB3_24: # in Loop: Header=BB3_7 Depth=1
callq hipDeviceSynchronize
incq %r12
cmpq $2048, %r12 # imm = 0x800
movq 64(%rsp), %rbx # 8-byte Reload
je .LBB3_25
.LBB3_7: # =>This Loop Header: Depth=1
# Child Loop BB3_18 Depth 2
# Child Loop BB3_21 Depth 2
movl $.L.str.3, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
cmpl $17, %ebp
jg .LBB3_9
# %bb.8: # in Loop: Header=BB3_7 Depth=1
movl $.L.str.4, %edi
movq %r14, %rsi
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
jmp .LBB3_10
.p2align 4, 0x90
.LBB3_9: # in Loop: Header=BB3_7 Depth=1
movl $.L.str.5, %edi
movq %r14, %rsi
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
.LBB3_10: # in Loop: Header=BB3_7 Depth=1
movb $1, %al
callq printf
leaq (%rsp,%r12,8), %rdi
addq $1048752, %rdi # imm = 0x1000B0
movq %rdi, 16(%rsp) # 8-byte Spill
movq %rbx, %rsi
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB3_11
# %bb.12: # in Loop: Header=BB3_7 Depth=1
leaq (%rsp,%r12,8), %r13
addq $524464, %r13 # imm = 0x800B0
movq %r13, %rdi
movq %rbx, %rsi
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB3_13
# %bb.14: # in Loop: Header=BB3_7 Depth=1
movq %rbx, %rsi
leaq (%rsp,%r12,8), %rbx
addq $176, %rbx
movq %rbx, %rdi
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB3_15
# %bb.16: # in Loop: Header=BB3_7 Depth=1
movl $.Lstr.3, %edi
callq puts@PLT
cmpl $63, %ebp
je .LBB3_19
# %bb.17: # %.lr.ph.i.preheader
# in Loop: Header=BB3_7 Depth=1
movq 16(%rsp), %rax # 8-byte Reload
movq (%rax), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_18: # %.lr.ph.i
# Parent Loop BB3_7 Depth=1
# => This Inner Loop Header: Depth=2
movl $1073741824, (%rax,%rcx,4) # imm = 0x40000000
incq %rcx
cmpq %rcx, %r14
jne .LBB3_18
.LBB3_19: # %_Z11initialDataPfxf.exit
# in Loop: Header=BB3_7 Depth=1
cmpl $63, %ebp
je .LBB3_22
# %bb.20: # %.lr.ph.i71.preheader
# in Loop: Header=BB3_7 Depth=1
movq (%r13), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_21: # %.lr.ph.i71
# Parent Loop BB3_7 Depth=1
# => This Inner Loop Header: Depth=2
movl $1073741824, (%rax,%rcx,4) # imm = 0x40000000
incq %rcx
cmpq %rcx, %r14
jne .LBB3_21
jmp .LBB3_22
.p2align 4, 0x90
.LBB3_23: # in Loop: Header=BB3_7 Depth=1
movq 16(%rsp), %rax # 8-byte Reload
movq (%rax), %rax
movq (%r13), %rcx
movq (%rbx), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
movl $_Z6vecAddPfS_S_, %edi
leaq 144(%rsp), %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_24
.LBB3_25:
movl $.Lstr.1, %edi
callq puts@PLT
movsd .LCPI3_2(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.11, %edi
movb $1, %al
callq printf
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_26: # =>This Loop Header: Depth=1
# Child Loop BB3_27 Depth 2
movl $.Lstr.2, %edi
callq puts@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_27: # Parent Loop BB3_26 Depth=1
# => This Inner Loop Header: Depth=2
movq 176(%rsp,%rbx,8), %rax
movss (%rax,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.13, %edi
movb $1, %al
callq printf
incq %r14
cmpq $8, %r14
jne .LBB3_27
# %bb.28: # in Loop: Header=BB3_26 Depth=1
incq %rbx
cmpq $2048, %rbx # imm = 0x800
jne .LBB3_26
# %bb.29:
movl $10, %edi
callq putchar@PLT
leaq 1048752(%rsp), %rdi
callq hipFree
leaq 524464(%rsp), %rdi
callq hipFree
leaq 176(%rsp), %rdi
callq hipFree
callq hipDeviceReset
addq $1573048, %rsp # imm = 0x1800B8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_15:
.cfi_def_cfa_offset 1573104
movl %eax, %r15d
movl $.L.str, %edi
movl $74, %esi
movl %eax, %edx
xorl %eax, %eax
callq printf
movl %r15d, %edi
jmp .LBB3_3
.LBB3_13:
movl $.L.str, %edi
movl $73, %esi
jmp .LBB3_2
.LBB3_11:
movl $.L.str, %edi
movl $72, %esi
.LBB3_2:
movl %eax, %edx
movl %eax, %ebx
xorl %eax, %eax
callq printf
movl %ebx, %edi
.LBB3_3:
callq hipGetErrorString
movl $.L.str.1, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB3_1:
movl $.L.str, %edi
movl $43, %esi
jmp .LBB3_2
.Lfunc_end3:
.size _Z22test_cudaMallocManagedii, .Lfunc_end3-_Z22test_cudaMallocManagedii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
xorl %edi, %edi
callq hipSetDevice
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
cmpl $0, 612(%rsp)
je .LBB4_4
# %bb.1:
movl $.L.str.15, %edi
xorl %esi, %esi
xorl %eax, %eax
callq printf
movl $24, %esi
cmpl $1, %ebp
jle .LBB4_3
# %bb.2:
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rsi
.LBB4_3:
xorl %edi, %edi
# kill: def $esi killed $esi killed $rsi
callq _Z22test_cudaMallocManagedii
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_4:
.cfi_def_cfa_offset 1504
movl $.L.str.16, %edi
xorl %esi, %esi
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecAddPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecAddPfS_S_,@object # @_Z6vecAddPfS_S_
.section .rodata,"a",@progbits
.globl _Z6vecAddPfS_S_
.p2align 3, 0x0
_Z6vecAddPfS_S_:
.quad _Z21__device_stub__vecAddPfS_S_
.size _Z6vecAddPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA call on line %d returned error %d\n"
.size .L.str, 40
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error: %s.\n"
.size .L.str.1, 12
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "==== ==== ==== ==== Loop: %d.\n"
.size .L.str.3, 31
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Vector size is %lld, nbytes is %f KB\n"
.size .L.str.4, 38
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Vector size is %lld, nbytes is %f MB\n"
.size .L.str.5, 38
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "===== numBlocks is %d, threadsPerBlock is %d\n"
.size .L.str.9, 46
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "===== ans is %f\n"
.size .L.str.11, 17
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "%3.0f "
.size .L.str.13, 7
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Device %d supports uva memory!\n"
.size .L.str.15, 32
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "Device %d does not support uva memory!\n"
.size .L.str.16, 40
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6vecAddPfS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "*** Warn: Concurrent managed access is not supported!"
.size .Lstr, 54
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "===== Check the results..."
.size .Lstr.1, 27
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\n======================================================"
.size .Lstr.2, 56
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "===== inital data begins..."
.size .Lstr.3, 28
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "===== synchronize begins..."
.size .Lstr.4, 28
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "===== add data begins..."
.size .Lstr.5, 25
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecAddPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecAddPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6vecAddPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0007 */
/*0070*/ IMAD.WIDE.U32 R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0007 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0007 */
/*00b0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecAddPfS_S_
.globl _Z6vecAddPfS_S_
.p2align 8
.type _Z6vecAddPfS_S_,@function
_Z6vecAddPfS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecAddPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecAddPfS_S_, .Lfunc_end0-_Z6vecAddPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecAddPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecAddPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006e891_00000000-6_uma.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initialDataPfxf
.type _Z11initialDataPfxf, @function
_Z11initialDataPfxf:
.LFB2057:
.cfi_startproc
endbr64
testq %rsi, %rsi
jle .L3
movq %rdi, %rax
leaq (%rdi,%rsi,4), %rdx
.L5:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z11initialDataPfxf, .-_Z11initialDataPfxf
.globl _Z27test_cudaDeviceGetAttributePi14cudaDeviceAttri
.type _Z27test_cudaDeviceGetAttributePi14cudaDeviceAttri, @function
_Z27test_cudaDeviceGetAttributePi14cudaDeviceAttri:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaDeviceGetAttribute@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z27test_cudaDeviceGetAttributePi14cudaDeviceAttri, .-_Z27test_cudaDeviceGetAttributePi14cudaDeviceAttri
.globl _Z29__device_stub__Z6vecAddPfS_S_PfS_S_
.type _Z29__device_stub__Z6vecAddPfS_S_PfS_S_, @function
_Z29__device_stub__Z6vecAddPfS_S_PfS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecAddPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z29__device_stub__Z6vecAddPfS_S_PfS_S_, .-_Z29__device_stub__Z6vecAddPfS_S_PfS_S_
.globl _Z6vecAddPfS_S_
.type _Z6vecAddPfS_S_, @function
_Z6vecAddPfS_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6vecAddPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z6vecAddPfS_S_, .-_Z6vecAddPfS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "CUDA call on line %d returned error %d\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Error: %s.\n"
.section .rodata.str1.8
.align 8
.LC2:
.string "*** Warn: Concurrent managed access is not supported!\n"
.align 8
.LC3:
.string "==== ==== ==== ==== Loop: %d.\n"
.align 8
.LC5:
.string "Vector size is %lld, nbytes is %f KB\n"
.align 8
.LC7:
.string "Vector size is %lld, nbytes is %f MB\n"
.section .rodata.str1.1
.LC8:
.string "===== inital data begins...\n"
.LC10:
.string "===== synchronize begins...\n"
.LC11:
.string "===== add data begins...\n"
.section .rodata.str1.8
.align 8
.LC12:
.string "===== numBlocks is %d, threadsPerBlock is %d\n"
.section .rodata.str1.1
.LC13:
.string "===== Check the results...\n"
.LC15:
.string "===== ans is %f\n"
.section .rodata.str1.8
.align 8
.LC16:
.string "\n======================================================\n"
.section .rodata.str1.1
.LC17:
.string "%3.0f "
.LC18:
.string "\n"
.text
.globl _Z22test_cudaMallocManagedii
.type _Z22test_cudaMallocManagedii, @function
_Z22test_cudaMallocManagedii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
leaq -1572864(%rsp), %r11
.cfi_def_cfa 11, 1572920
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $88, %rsp
.cfi_def_cfa_offset 1573008
movl %edi, %ebp
movl %esi, 20(%rsp)
movq %fs:40, %rax
movq %rax, 1572936(%rsp)
xorl %eax, %eax
leaq 36(%rsp), %rdi
movl %ebp, %edx
movl $83, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L34
leaq 36(%rsp), %rdi
movl %ebp, %edx
movl $89, %esi
call cudaDeviceGetAttribute@PLT
cmpl $0, 36(%rsp)
je .L35
.L19:
movl $1, %eax
movl 20(%rsp), %ebx
movl %ebx, %ecx
salq %cl, %rax
movl $4, %edx
salq %cl, %rdx
movq %rdx, %r12
leaq 2046(%rax), %rdx
movq %rax, %rcx
addq $1023, %rcx
cmovns %rcx, %rdx
sarq $10, %rdx
movl %edx, 16(%rsp)
leaq 524352(%rsp), %r13
leaq 64(%rsp), %r14
movl $0, %ebp
movq %rax, 8(%rsp)
jmp .L26
.L34:
movl %eax, %ebx
movl %eax, %ecx
movl $43, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L35:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L19
.L20:
pxor %xmm0, %xmm0
cvtsi2ssq %r12, %xmm0
mulss .LC6(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq 8(%rsp), %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.L21:
movl $1, %edx
movq %r12, %rsi
movq %r14, %rdi
call cudaMallocManaged@PLT
testl %eax, %eax
jne .L36
movl $1, %edx
movq %r12, %rsi
movq %r13, %rdi
call cudaMallocManaged@PLT
testl %eax, %eax
jne .L37
leaq 1048640(%rsp), %rax
movq %rax, 24(%rsp)
leaq (%rax,%rbp,8), %rdi
movl $1, %edx
movq %r12, %rsi
call cudaMallocManaged@PLT
testl %eax, %eax
jne .L38
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%r14), %rdi
movss .LC9(%rip), %xmm0
movq 8(%rsp), %rsi
call _Z11initialDataPfxf
movq 0(%r13), %rdi
movss .LC9(%rip), %xmm0
movq 8(%rsp), %rsi
call _Z11initialDataPfxf
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceSynchronize@PLT
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1024, %ecx
movl 16(%rsp), %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 16(%rsp), %eax
movl %eax, 52(%rsp)
movl $1024, 40(%rsp)
movl 48(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movq 52(%rsp), %rdi
movl 60(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L25:
call cudaDeviceSynchronize@PLT
addq $1, %rbp
addq $8, %r13
addq $8, %r14
cmpq $2048, %rbp
je .L40
.L26:
movl %ebp, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $17, 20(%rsp)
jg .L20
pxor %xmm0, %xmm0
cvtsi2ssq %r12, %xmm0
mulss .LC4(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq 8(%rsp), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L21
.L36:
movl %eax, %ebx
movl %eax, %ecx
movl $72, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L37:
movl %eax, %ebx
movl %eax, %ecx
movl $73, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
movl %eax, %ebx
movl %eax, %ecx
movl $74, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L39:
movq 1048640(%rsp,%rbp,8), %rdx
movq 0(%r13), %rsi
movq (%r14), %rdi
call _Z29__device_stub__Z6vecAddPfS_S_PfS_S_
jmp .L25
.L40:
movq 24(%rsp), %rbx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movsd .LC14(%rip), %xmm0
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 16384(%rbx), %r14
leaq .LC16(%rip), %r13
leaq .LC17(%rip), %r12
jmp .L28
.L42:
addq $8, %rbx
cmpq %r14, %rbx
je .L41
.L28:
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebp
.L27:
movq (%rbx), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbp), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbp
cmpq $32, %rbp
jne .L27
jmp .L42
.L41:
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 64(%rsp), %rdi
call cudaFree@PLT
leaq 524352(%rsp), %rdi
call cudaFree@PLT
leaq 1048640(%rsp), %rdi
call cudaFree@PLT
call cudaDeviceReset@PLT
movq 1572936(%rsp), %rax
subq %fs:40, %rax
jne .L43
addq $1572952, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z22test_cudaMallocManagedii, .-_Z22test_cudaMallocManagedii
.section .rodata.str1.8
.align 8
.LC19:
.string "Device %d supports uva memory!\n"
.align 8
.LC20:
.string "Device %d does not support uva memory!\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1048, %rsp
.cfi_def_cfa_offset 1072
movl %edi, %ebx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 1032(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
movq %rsp, %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
cmpl $0, 604(%rsp)
je .L45
movl $0, %edx
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $24, %esi
cmpl $1, %ebx
jg .L50
.L47:
movl $0, %edi
call _Z22test_cudaMallocManagedii
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L51
movl $0, %eax
addq $1048, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
movl $0, %edx
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L50:
movq 8(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %esi
jmp .L47
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC21:
.string "_Z6vecAddPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecAddPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 981467136
.align 4
.LC6:
.long 897581056
.align 4
.LC9:
.long 1073741824
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC14:
.long 0
.long 1074790400
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "uma.hip"
.globl _Z21__device_stub__vecAddPfS_S_ # -- Begin function _Z21__device_stub__vecAddPfS_S_
.p2align 4, 0x90
.type _Z21__device_stub__vecAddPfS_S_,@function
_Z21__device_stub__vecAddPfS_S_: # @_Z21__device_stub__vecAddPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecAddPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__vecAddPfS_S_, .Lfunc_end0-_Z21__device_stub__vecAddPfS_S_
.cfi_endproc
# -- End function
.globl _Z11initialDataPfxf # -- Begin function _Z11initialDataPfxf
.p2align 4, 0x90
.type _Z11initialDataPfxf,@function
_Z11initialDataPfxf: # @_Z11initialDataPfxf
.cfi_startproc
# %bb.0:
testq %rsi, %rsi
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss %xmm0, (%rdi,%rax,4)
incq %rax
cmpq %rax, %rsi
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z11initialDataPfxf, .Lfunc_end1-_Z11initialDataPfxf
.cfi_endproc
# -- End function
.globl _Z27test_cudaDeviceGetAttributePi20hipDeviceAttribute_ti # -- Begin function _Z27test_cudaDeviceGetAttributePi20hipDeviceAttribute_ti
.p2align 4, 0x90
.type _Z27test_cudaDeviceGetAttributePi20hipDeviceAttribute_ti,@function
_Z27test_cudaDeviceGetAttributePi20hipDeviceAttribute_ti: # @_Z27test_cudaDeviceGetAttributePi20hipDeviceAttribute_ti
.cfi_startproc
# %bb.0:
jmp hipDeviceGetAttribute # TAILCALL
.Lfunc_end2:
.size _Z27test_cudaDeviceGetAttributePi20hipDeviceAttribute_ti, .Lfunc_end2-_Z27test_cudaDeviceGetAttributePi20hipDeviceAttribute_ti
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z22test_cudaMallocManagedii
.LCPI3_0:
.long 0x35800000 # float 9.53674316E-7
.LCPI3_1:
.long 0x3a800000 # float 9.765625E-4
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI3_2:
.quad 0x4010000000000000 # double 4
.text
.globl _Z22test_cudaMallocManagedii
.p2align 4, 0x90
.type _Z22test_cudaMallocManagedii,@function
_Z22test_cudaMallocManagedii: # @_Z22test_cudaMallocManagedii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1573048, %rsp # imm = 0x1800B8
.cfi_def_cfa_offset 1573104
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movl %edi, %ebx
leaq 12(%rsp), %rdi
movl $24, %esi
movl %ebx, %edx
callq hipDeviceGetAttribute
testl %eax, %eax
jne .LBB3_1
# %bb.4:
leaq 12(%rsp), %rdi
movl $9, %esi
movl %ebx, %edx
callq hipDeviceGetAttribute
cmpl $0, 12(%rsp)
jne .LBB3_6
# %bb.5:
movl $.Lstr, %edi
callq puts@PLT
.LBB3_6:
movl $1, %r14d
movl %ebp, %ecx
shlq %cl, %r14
movl $4, %ebx
shlq %cl, %rbx
movabsq $4294967296, %rcx # imm = 0x100000000
cvtsi2ss %rbx, %xmm0
movss .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm0, %xmm1
mulss .LCPI3_1(%rip), %xmm0
cvtss2sd %xmm1, %xmm1
movsd %xmm1, 32(%rsp) # 8-byte Spill
cvtss2sd %xmm0, %xmm0
movsd %xmm0, 24(%rsp) # 8-byte Spill
leaq 1023(%r14), %rax
leaq 2046(%r14), %rdx
testq %rax, %rax
cmovnsq %rax, %rdx
sarq $10, %rdx
movq %rdx, 48(%rsp) # 8-byte Spill
movl %edx, %eax
orq %rcx, %rax
movq %rax, 40(%rsp) # 8-byte Spill
addq $1024, %rcx # imm = 0x400
movq %rcx, 56(%rsp) # 8-byte Spill
xorl %r12d, %r12d
movq %rbx, 64(%rsp) # 8-byte Spill
jmp .LBB3_7
.p2align 4, 0x90
.LBB3_22: # %_Z11initialDataPfxf.exit74
# in Loop: Header=BB3_7 Depth=1
movl $.Lstr.4, %edi
callq puts@PLT
callq hipDeviceSynchronize
movl $.Lstr.5, %edi
callq puts@PLT
movl $.L.str.9, %edi
movq 48(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
movl $1024, %edx # imm = 0x400
xorl %eax, %eax
callq printf
movq 40(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movq 56(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB3_23
.LBB3_24: # in Loop: Header=BB3_7 Depth=1
callq hipDeviceSynchronize
incq %r12
cmpq $2048, %r12 # imm = 0x800
movq 64(%rsp), %rbx # 8-byte Reload
je .LBB3_25
.LBB3_7: # =>This Loop Header: Depth=1
# Child Loop BB3_18 Depth 2
# Child Loop BB3_21 Depth 2
movl $.L.str.3, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
cmpl $17, %ebp
jg .LBB3_9
# %bb.8: # in Loop: Header=BB3_7 Depth=1
movl $.L.str.4, %edi
movq %r14, %rsi
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
jmp .LBB3_10
.p2align 4, 0x90
.LBB3_9: # in Loop: Header=BB3_7 Depth=1
movl $.L.str.5, %edi
movq %r14, %rsi
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
.LBB3_10: # in Loop: Header=BB3_7 Depth=1
movb $1, %al
callq printf
leaq (%rsp,%r12,8), %rdi
addq $1048752, %rdi # imm = 0x1000B0
movq %rdi, 16(%rsp) # 8-byte Spill
movq %rbx, %rsi
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB3_11
# %bb.12: # in Loop: Header=BB3_7 Depth=1
leaq (%rsp,%r12,8), %r13
addq $524464, %r13 # imm = 0x800B0
movq %r13, %rdi
movq %rbx, %rsi
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB3_13
# %bb.14: # in Loop: Header=BB3_7 Depth=1
movq %rbx, %rsi
leaq (%rsp,%r12,8), %rbx
addq $176, %rbx
movq %rbx, %rdi
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB3_15
# %bb.16: # in Loop: Header=BB3_7 Depth=1
movl $.Lstr.3, %edi
callq puts@PLT
cmpl $63, %ebp
je .LBB3_19
# %bb.17: # %.lr.ph.i.preheader
# in Loop: Header=BB3_7 Depth=1
movq 16(%rsp), %rax # 8-byte Reload
movq (%rax), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_18: # %.lr.ph.i
# Parent Loop BB3_7 Depth=1
# => This Inner Loop Header: Depth=2
movl $1073741824, (%rax,%rcx,4) # imm = 0x40000000
incq %rcx
cmpq %rcx, %r14
jne .LBB3_18
.LBB3_19: # %_Z11initialDataPfxf.exit
# in Loop: Header=BB3_7 Depth=1
cmpl $63, %ebp
je .LBB3_22
# %bb.20: # %.lr.ph.i71.preheader
# in Loop: Header=BB3_7 Depth=1
movq (%r13), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_21: # %.lr.ph.i71
# Parent Loop BB3_7 Depth=1
# => This Inner Loop Header: Depth=2
movl $1073741824, (%rax,%rcx,4) # imm = 0x40000000
incq %rcx
cmpq %rcx, %r14
jne .LBB3_21
jmp .LBB3_22
.p2align 4, 0x90
.LBB3_23: # in Loop: Header=BB3_7 Depth=1
movq 16(%rsp), %rax # 8-byte Reload
movq (%rax), %rax
movq (%r13), %rcx
movq (%rbx), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
movl $_Z6vecAddPfS_S_, %edi
leaq 144(%rsp), %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_24
.LBB3_25:
movl $.Lstr.1, %edi
callq puts@PLT
movsd .LCPI3_2(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.11, %edi
movb $1, %al
callq printf
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_26: # =>This Loop Header: Depth=1
# Child Loop BB3_27 Depth 2
movl $.Lstr.2, %edi
callq puts@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_27: # Parent Loop BB3_26 Depth=1
# => This Inner Loop Header: Depth=2
movq 176(%rsp,%rbx,8), %rax
movss (%rax,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.13, %edi
movb $1, %al
callq printf
incq %r14
cmpq $8, %r14
jne .LBB3_27
# %bb.28: # in Loop: Header=BB3_26 Depth=1
incq %rbx
cmpq $2048, %rbx # imm = 0x800
jne .LBB3_26
# %bb.29:
movl $10, %edi
callq putchar@PLT
leaq 1048752(%rsp), %rdi
callq hipFree
leaq 524464(%rsp), %rdi
callq hipFree
leaq 176(%rsp), %rdi
callq hipFree
callq hipDeviceReset
addq $1573048, %rsp # imm = 0x1800B8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_15:
.cfi_def_cfa_offset 1573104
movl %eax, %r15d
movl $.L.str, %edi
movl $74, %esi
movl %eax, %edx
xorl %eax, %eax
callq printf
movl %r15d, %edi
jmp .LBB3_3
.LBB3_13:
movl $.L.str, %edi
movl $73, %esi
jmp .LBB3_2
.LBB3_11:
movl $.L.str, %edi
movl $72, %esi
.LBB3_2:
movl %eax, %edx
movl %eax, %ebx
xorl %eax, %eax
callq printf
movl %ebx, %edi
.LBB3_3:
callq hipGetErrorString
movl $.L.str.1, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB3_1:
movl $.L.str, %edi
movl $43, %esi
jmp .LBB3_2
.Lfunc_end3:
.size _Z22test_cudaMallocManagedii, .Lfunc_end3-_Z22test_cudaMallocManagedii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
xorl %edi, %edi
callq hipSetDevice
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
cmpl $0, 612(%rsp)
je .LBB4_4
# %bb.1:
movl $.L.str.15, %edi
xorl %esi, %esi
xorl %eax, %eax
callq printf
movl $24, %esi
cmpl $1, %ebp
jle .LBB4_3
# %bb.2:
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rsi
.LBB4_3:
xorl %edi, %edi
# kill: def $esi killed $esi killed $rsi
callq _Z22test_cudaMallocManagedii
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_4:
.cfi_def_cfa_offset 1504
movl $.L.str.16, %edi
xorl %esi, %esi
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecAddPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecAddPfS_S_,@object # @_Z6vecAddPfS_S_
.section .rodata,"a",@progbits
.globl _Z6vecAddPfS_S_
.p2align 3, 0x0
_Z6vecAddPfS_S_:
.quad _Z21__device_stub__vecAddPfS_S_
.size _Z6vecAddPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA call on line %d returned error %d\n"
.size .L.str, 40
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error: %s.\n"
.size .L.str.1, 12
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "==== ==== ==== ==== Loop: %d.\n"
.size .L.str.3, 31
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Vector size is %lld, nbytes is %f KB\n"
.size .L.str.4, 38
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Vector size is %lld, nbytes is %f MB\n"
.size .L.str.5, 38
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "===== numBlocks is %d, threadsPerBlock is %d\n"
.size .L.str.9, 46
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "===== ans is %f\n"
.size .L.str.11, 17
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "%3.0f "
.size .L.str.13, 7
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Device %d supports uva memory!\n"
.size .L.str.15, 32
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "Device %d does not support uva memory!\n"
.size .L.str.16, 40
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6vecAddPfS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "*** Warn: Concurrent managed access is not supported!"
.size .Lstr, 54
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "===== Check the results..."
.size .Lstr.1, 27
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\n======================================================"
.size .Lstr.2, 56
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "===== inital data begins..."
.size .Lstr.3, 28
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "===== synchronize begins..."
.size .Lstr.4, 28
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "===== add data begins..."
.size .Lstr.5, 25
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecAddPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecAddPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
__device__ int smallerDst (int a, int b){
if(a < b){
return a;
}
else {
return b;
}
} /*ending of device funtion */
__global__ void strongestNeighborScan_gpu(int * src, int * oldDst, int * newDst, int * oldWeight, int * newWeight, int * madeChanges, int distance, int numEdges) {
/*YOUR CODE HERE*/
int i;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int total_threads = blockDim.x * gridDim.x;
for(i = tid; i < numEdges; i += total_threads){
if(tid >= numEdges){
return;
}
if (src[i] == src[i-distance]){ /* if the element is in the same segment */
if(oldWeight[i] == oldWeight[i-distance]){ /*if the two weights are equal */
newDst[i] = smallerDst (oldDst[i], oldDst[i-distance]);
newWeight[i] = oldWeight[i];
} /*second if statement */
else {
newWeight[i] = max (oldWeight[i], oldWeight[i-distance]);
if (newWeight[i] == oldWeight[i])
newDst[i] = oldDst[i];
if (newWeight[i] == oldWeight[i-distance])
newDst[i] = oldDst[i-distance];
}
} /*first if statement */
else {
newWeight[i] = oldWeight[i]; /* when the element is in a different segment, it takes its old weight as the new weight */
newDst[i] = oldDst[i];
}
if(oldDst[i] != newDst[i]){
* madeChanges = 1;
}
} /*ending of for loop */
} /*ending of main */ | code for sm_80
Function : _Z25strongestNeighborScan_gpuPiS_S_S_S_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x194], PT ; /* 0x0000650000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R10, -R0.reuse, c[0x0][0x190], RZ ; /* 0x00006400000a7a10 */
/* 0x040fe20007ffe1ff */
/*0070*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff077624 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD.WIDE R2, R0, 0x4, RZ ; /* 0x0000000400027825 */
/* 0x000fc800078e02ff */
/*00a0*/ IMAD.WIDE R10, R10, 0x4, RZ ; /* 0x000000040a0a7825 */
/* 0x000fc800078e02ff */
/*00b0*/ IMAD R7, R7, c[0x0][0xc], RZ ; /* 0x0000030007077a24 */
/* 0x000fe200078e02ff */
/*00c0*/ IADD3 R9, P0, RZ, -R10, RZ ; /* 0x8000000aff097210 */
/* 0x000fc60007f1e0ff */
/*00d0*/ IMAD.MOV R4, RZ, RZ, -R7 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0a07 */
/*00e0*/ IMAD.X R11, RZ, RZ, ~R11, P0 ; /* 0x000000ffff0b7224 */
/* 0x000fe400000e0e0b */
/*00f0*/ IMAD.WIDE R4, R4, 0x4, RZ ; /* 0x0000000404047825 */
/* 0x000fc800078e02ff */
/*0100*/ IADD3 R16, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002107a10 */
/* 0x000fe40007f1e0ff */
/*0110*/ IADD3 R14, P1, R9, c[0x0][0x160], RZ ; /* 0x00005800090e7a10 */
/* 0x000fe40007f3e0ff */
/*0120*/ IADD3.X R17, R3, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590003117a10 */
/* 0x000fe400007fe4ff */
/*0130*/ IADD3.X R15, R11, c[0x0][0x164], RZ, P1, !PT ; /* 0x000059000b0f7a10 */
/* 0x000fc80000ffe4ff */
/*0140*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ea8000c1e1900 */
/*0150*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea2000c1e1900 */
/*0160*/ IADD3 R22, P0, R2, c[0x0][0x178], RZ ; /* 0x00005e0002167a10 */
/* 0x000fc80007f1e0ff */
/*0170*/ IADD3.X R23, R3, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f0003177a10 */
/* 0x000fca00007fe4ff */
/*0180*/ LDG.E R25, [R22.64] ; /* 0x0000000416197981 */
/* 0x000ee2000c1e1900 */
/*0190*/ IADD3 R20, P1, R2.reuse, c[0x0][0x180], RZ ; /* 0x0000600002147a10 */
/* 0x040fe40007f3e0ff */
/*01a0*/ IADD3 R12, P2, R2, c[0x0][0x168], RZ ; /* 0x00005a00020c7a10 */
/* 0x000fe40007f5e0ff */
/*01b0*/ IADD3.X R21, R3.reuse, c[0x0][0x184], RZ, P1, !PT ; /* 0x0000610003157a10 */
/* 0x040fe40000ffe4ff */
/*01c0*/ IADD3.X R13, R3, c[0x0][0x16c], RZ, P2, !PT ; /* 0x00005b00030d7a10 */
/* 0x000fe400017fe4ff */
/*01d0*/ ISETP.NE.AND P0, PT, R17, R14, PT ; /* 0x0000000e1100720c */
/* 0x004fda0003f05270 */
/*01e0*/ @P0 STG.E [R20.64], R25 ; /* 0x0000001914000986 */
/* 0x0081e8000c101904 */
/*01f0*/ @P0 LDG.E R19, [R12.64] ; /* 0x000000040c130981 */
/* 0x000ea2000c1e1900 */
/*0200*/ IADD3 R14, P1, R2, c[0x0][0x170], RZ ; /* 0x00005c00020e7a10 */
/* 0x000fc80007f3e0ff */
/*0210*/ IADD3.X R15, R3, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d00030f7a10 */
/* 0x000fe20000ffe4ff */
/*0220*/ BSSY B0, 0x400 ; /* 0x000001d000007945 */
/* 0x000fe80003800000 */
/*0230*/ @P0 STG.E [R14.64], R19 ; /* 0x000000130e000986 */
/* 0x0041e2000c101904 */
/*0240*/ @P0 BRA 0x3f0 ; /* 0x000001a000000947 */
/* 0x000fea0003800000 */
/*0250*/ IADD3 R18, P0, R9, c[0x0][0x178], RZ ; /* 0x00005e0009127a10 */
/* 0x000fc80007f1e0ff */
/*0260*/ IADD3.X R19, R11, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f000b137a10 */
/* 0x001fca00007fe4ff */
/*0270*/ LDG.E R6, [R18.64] ; /* 0x0000000412067981 */
/* 0x000ea2000c1e1900 */
/*0280*/ IADD3 R16, P1, R9, c[0x0][0x168], RZ ; /* 0x00005a0009107a10 */
/* 0x000fc80007f3e0ff */
/*0290*/ IADD3.X R17, R11, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b000b117a10 */
/* 0x000fe40000ffe4ff */
/*02a0*/ ISETP.NE.AND P0, PT, R25, R6, PT ; /* 0x000000061900720c */
/* 0x004fda0003f05270 */
/*02b0*/ @!P0 BRA 0x390 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*02c0*/ IMNMX R25, R25, R6, !PT ; /* 0x0000000619197217 */
/* 0x000fca0007800200 */
/*02d0*/ STG.E [R20.64], R25 ; /* 0x0000001914007986 */
/* 0x0001e8000c101904 */
/*02e0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000ea4000c1e1900 */
/*02f0*/ ISETP.NE.AND P0, PT, R25, R22, PT ; /* 0x000000161900720c */
/* 0x004fda0003f05270 */
/*0300*/ @!P0 LDG.E R27, [R12.64] ; /* 0x000000040c1b8981 */
/* 0x000ea8000c1e1900 */
/*0310*/ @!P0 STG.E [R14.64], R27 ; /* 0x0000001b0e008986 */
/* 0x0043e8000c101904 */
/*0320*/ @!P0 LDG.E R25, [R20.64] ; /* 0x0000000414198981 */
/* 0x001ea8000c1e1900 */
/*0330*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea4000c1e1900 */
/*0340*/ ISETP.NE.AND P0, PT, R25, R18, PT ; /* 0x000000121900720c */
/* 0x004fda0003f05270 */
/*0350*/ @P0 BRA 0x3f0 ; /* 0x0000009000000947 */
/* 0x000fea0003800000 */
/*0360*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x002ea8000c1e1900 */
/*0370*/ STG.E [R14.64], R17 ; /* 0x000000110e007986 */
/* 0x0041e2000c101904 */
/*0380*/ BRA 0x3f0 ; /* 0x0000006000007947 */
/* 0x000fea0003800000 */
/*0390*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ea8000c1e1900 */
/*03a0*/ LDG.E R6, [R12.64] ; /* 0x000000040c067981 */
/* 0x000ea4000c1e1900 */
/*03b0*/ IMNMX R19, R6, R17, PT ; /* 0x0000001106137217 */
/* 0x004fca0003800200 */
/*03c0*/ STG.E [R14.64], R19 ; /* 0x000000130e007986 */
/* 0x0001e8000c101904 */
/*03d0*/ LDG.E R23, [R22.64] ; /* 0x0000000416177981 */
/* 0x000ea8000c1e1900 */
/*03e0*/ STG.E [R20.64], R23 ; /* 0x0000001714007986 */
/* 0x0041e4000c101904 */
/*03f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0400*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea8000c1e1900 */
/*0410*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x001ea2000c1e1900 */
/*0420*/ IMAD.IADD R0, R7.reuse, 0x1, R0 ; /* 0x0000000107007824 */
/* 0x040fe200078e0200 */
/*0430*/ IADD3 R9, P1, -R4, R9, RZ ; /* 0x0000000904097210 */
/* 0x000fe20007f3e1ff */
/*0440*/ IMAD.WIDE R2, R7, 0x4, R2 ; /* 0x0000000407027825 */
/* 0x000fc800078e0202 */
/*0450*/ IMAD.X R11, R11, 0x1, ~R5, P1 ; /* 0x000000010b0b7824 */
/* 0x000fe200008e0e05 */
/*0460*/ ISETP.NE.AND P0, PT, R12, R15, PT ; /* 0x0000000f0c00720c */
/* 0x004fda0003f05270 */
/*0470*/ @P0 IMAD.MOV.U32 R19, RZ, RZ, 0x1 ; /* 0x00000001ff130424 */
/* 0x000fe400078e00ff */
/*0480*/ @P0 IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff100624 */
/* 0x000fe400078e00ff */
/*0490*/ @P0 IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff110624 */
/* 0x000fca00078e00ff */
/*04a0*/ @P0 STG.E [R16.64], R19 ; /* 0x0000001310000986 */
/* 0x0001e2000c101904 */
/*04b0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x194], PT ; /* 0x0000650000007a0c */
/* 0x000fda0003f06270 */
/*04c0*/ @!P0 BRA 0x100 ; /* 0xfffffc3000008947 */
/* 0x001fea000383ffff */
/*04d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04e0*/ BRA 0x4e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
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