system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
Copyright 2015 Thomas Luu
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
File: plog.cu
Computation of the Lambert W-function by Halley's Method.
Single and double precision implementations.
Initial guesses based on:
D.A. Barry, J.-Y. Parlange, L. Li, H. Prommer, C.J. Cunningham, and
F. Stagnitti. Analytical approximations for real values of the Lambert
W-function. Mathematics and Computers in Simulation, 53(1):95-103, 2000.
D.A. Barry, J.-Y. Parlange, L. Li, H. Prommer, C.J. Cunningham, and
F. Stagnitti. Erratum to analytical approximations for real values of the
Lambert W-function. Mathematics and computers in simulation, 59(6):543-543,
2002.
*/
#ifndef PLOG
#define PLOG
__host__ __device__ double plog(double x)
{
if (x == 0.0) {
return 0.0;
}
double w0, w1;
if (x > 0.0) {
w0 = log(1.2 * x / log(2.4 * x / log1p(2.4 * x)));
} else {
double v = 1.4142135623730950488 * sqrt(1 + 2.7182818284590452354 * x);
double N2 = 10.242640687119285146 + 1.9797586132081854940 * v;
double N1 = 0.29289321881345247560 * (1.4142135623730950488 + N2);
w0 = -1.0 + v * (N2 + v) / (N2 + v + N1 * v);
}
while (true) {
double e = exp(w0);
double f = w0 * e - x;
w1 = w0 + ((f+f) * (1.0 + w0)) / (f * (2.0 + w0) - (e+e) * (1.0 + w0) * (1.0 + w0));
if (fabs(w0 / w1 - 1.0) < 1.4901161193847656e-8) {
break;
}
w0 = w1;
}
return w1;
}
__host__ __device__ float plog(float x)
{
if (x == 0.0f) {
return 0.0f;
}
float w0, w1;
if (x > 0.0f) {
w0 = log(1.2f * x / log(2.4f * x / log1p(2.4f * x)));
} else {
float v = 1.4142135623730950488f * sqrt(1 + 2.7182818284590452354f * x);
float N2 = 10.242640687119285146f + 1.9797586132081854940f * v;
float N1 = 0.29289321881345247560f * (1.4142135623730950488f + N2);
w0 = -1.0f + v * (N2 + v) / (N2 + v + N1 * v);
}
while (true) {
float e = exp(w0);
float f = w0 * e - x;
w1 = w0 + ((f+f) * (1.0f + w0)) / (f * (2.0f + w0) - (e+e) * (1.0f + w0) * (1.0f + w0));
if (fabs(w0 / w1 - 1.0f) < 0.00034526698300124390840f) {
break;
}
w0 = w1;
}
return w1;
}
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
Copyright 2015 Thomas Luu
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
File: plog.cu
Computation of the Lambert W-function by Halley's Method.
Single and double precision implementations.
Initial guesses based on:
D.A. Barry, J.-Y. Parlange, L. Li, H. Prommer, C.J. Cunningham, and
F. Stagnitti. Analytical approximations for real values of the Lambert
W-function. Mathematics and Computers in Simulation, 53(1):95-103, 2000.
D.A. Barry, J.-Y. Parlange, L. Li, H. Prommer, C.J. Cunningham, and
F. Stagnitti. Erratum to analytical approximations for real values of the
Lambert W-function. Mathematics and computers in simulation, 59(6):543-543,
2002.
*/
#ifndef PLOG
#define PLOG
__host__ __device__ double plog(double x)
{
if (x == 0.0) {
return 0.0;
}
double w0, w1;
if (x > 0.0) {
w0 = log(1.2 * x / log(2.4 * x / log1p(2.4 * x)));
} else {
double v = 1.4142135623730950488 * sqrt(1 + 2.7182818284590452354 * x);
double N2 = 10.242640687119285146 + 1.9797586132081854940 * v;
double N1 = 0.29289321881345247560 * (1.4142135623730950488 + N2);
w0 = -1.0 + v * (N2 + v) / (N2 + v + N1 * v);
}
while (true) {
double e = exp(w0);
double f = w0 * e - x;
w1 = w0 + ((f+f) * (1.0 + w0)) / (f * (2.0 + w0) - (e+e) * (1.0 + w0) * (1.0 + w0));
if (fabs(w0 / w1 - 1.0) < 1.4901161193847656e-8) {
break;
}
w0 = w1;
}
return w1;
}
__host__ __device__ float plog(float x)
{
if (x == 0.0f) {
return 0.0f;
}
float w0, w1;
if (x > 0.0f) {
w0 = log(1.2f * x / log(2.4f * x / log1p(2.4f * x)));
} else {
float v = 1.4142135623730950488f * sqrt(1 + 2.7182818284590452354f * x);
float N2 = 10.242640687119285146f + 1.9797586132081854940f * v;
float N1 = 0.29289321881345247560f * (1.4142135623730950488f + N2);
w0 = -1.0f + v * (N2 + v) / (N2 + v + N1 * v);
}
while (true) {
float e = exp(w0);
float f = w0 * e - x;
w1 = w0 + ((f+f) * (1.0f + w0)) / (f * (2.0f + w0) - (e+e) * (1.0f + w0) * (1.0f + w0));
if (fabs(w0 / w1 - 1.0f) < 0.00034526698300124390840f) {
break;
}
w0 = w1;
}
return w1;
}
#endif | .text
.file "plog.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z4plogd
.LCPI0_0:
.quad 0x4005bf0a8b145769 # double 2.7182818284590451
.LCPI0_1:
.quad 0x3ff0000000000000 # double 1
.LCPI0_2:
.quad 0x3ff6a09e667f3bcd # double 1.4142135623730951
.LCPI0_3:
.quad 0x3fffad175e1b416a # double 1.9797586132081855
.LCPI0_4:
.quad 0x40247c3b666fb66d # double 10.242640687119286
.LCPI0_5:
.quad 0x3fd2bec333018867 # double 0.29289321881345248
.LCPI0_6:
.quad 0xbff0000000000000 # double -1
.LCPI0_7:
.quad 0x3ff3333333333333 # double 1.2
.LCPI0_8:
.quad 0x4003333333333333 # double 2.3999999999999999
.LCPI0_9:
.quad 0x4000000000000000 # double 2
.LCPI0_11:
.quad 0x3e50000000000000 # double 1.4901161193847656E-8
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI0_10:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl _Z4plogd
.p2align 4, 0x90
.type _Z4plogd,@function
_Z4plogd: # @_Z4plogd
.cfi_startproc
# %bb.0:
movapd %xmm0, %xmm2
xorpd %xmm0, %xmm0
ucomisd %xmm0, %xmm2
jne .LBB0_1
jp .LBB0_1
# %bb.10: # %.loopexit
retq
.LBB0_1:
subq $40, %rsp
.cfi_def_cfa_offset 48
xorpd %xmm1, %xmm1
ucomisd %xmm1, %xmm2
movsd %xmm2, 32(%rsp) # 8-byte Spill
jbe .LBB0_3
# %bb.2:
movsd .LCPI0_7(%rip), %xmm0 # xmm0 = mem[0],zero
mulsd %xmm2, %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
movsd .LCPI0_8(%rip), %xmm0 # xmm0 = mem[0],zero
mulsd %xmm2, %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
callq log1p
movsd (%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movapd %xmm1, %xmm0
callq log
movsd 16(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movapd %xmm1, %xmm0
callq log
movapd %xmm0, %xmm3
jmp .LBB0_7
.LBB0_3:
movsd .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero
mulsd %xmm2, %xmm0
addsd .LCPI0_1(%rip), %xmm0
ucomisd %xmm1, %xmm0
jb .LBB0_5
# %bb.4:
sqrtsd %xmm0, %xmm0
jmp .LBB0_6
.LBB0_5: # %call.sqrt
callq sqrt
.LBB0_6: # %.split
movsd .LCPI0_2(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
movsd .LCPI0_3(%rip), %xmm2 # xmm2 = mem[0],zero
mulsd %xmm0, %xmm2
addsd .LCPI0_4(%rip), %xmm2
addsd %xmm2, %xmm1
mulsd .LCPI0_5(%rip), %xmm1
addsd %xmm0, %xmm2
movapd %xmm0, %xmm3
mulsd %xmm2, %xmm3
mulsd %xmm0, %xmm1
addsd %xmm2, %xmm1
divsd %xmm1, %xmm3
addsd .LCPI0_6(%rip), %xmm3
.LBB0_7: # %.preheader
movapd %xmm3, %xmm2
.p2align 4, 0x90
.LBB0_8: # =>This Inner Loop Header: Depth=1
movapd %xmm3, (%rsp) # 16-byte Spill
movapd %xmm2, 16(%rsp) # 16-byte Spill
movapd %xmm3, %xmm0
callq exp
movapd %xmm0, %xmm1
movapd (%rsp), %xmm4 # 16-byte Reload
movapd %xmm4, %xmm0
mulsd %xmm1, %xmm0
subsd 32(%rsp), %xmm0 # 8-byte Folded Reload
movapd %xmm4, %xmm2
addsd .LCPI0_9(%rip), %xmm2
mulsd %xmm0, %xmm2
addsd %xmm0, %xmm0
movapd %xmm4, %xmm3
addsd .LCPI0_1(%rip), %xmm3
mulsd %xmm3, %xmm0
addsd %xmm1, %xmm1
mulsd %xmm3, %xmm1
mulsd %xmm3, %xmm1
subsd %xmm1, %xmm2
divsd %xmm2, %xmm0
movapd 16(%rsp), %xmm2 # 16-byte Reload
addsd %xmm4, %xmm0
divsd %xmm0, %xmm2
addsd .LCPI0_6(%rip), %xmm2
andpd .LCPI0_10(%rip), %xmm2
movsd .LCPI0_11(%rip), %xmm1 # xmm1 = mem[0],zero
ucomisd %xmm2, %xmm1
cmpltsd %xmm1, %xmm2
movapd %xmm2, %xmm1
andnpd %xmm0, %xmm1
andpd %xmm4, %xmm2
orpd %xmm1, %xmm2
movapd %xmm2, %xmm3
jbe .LBB0_8
# %bb.9:
addq $40, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z4plogd, .Lfunc_end0-_Z4plogd
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z4plogf
.LCPI1_0:
.long 0x402df854 # float 2.71828175
.LCPI1_1:
.long 0x3f800000 # float 1
.LCPI1_3:
.long 0x3ffd68bb # float 1.97975862
.LCPI1_4:
.long 0x4123e1db # float 10.2426405
.LCPI1_5:
.long 0x3fb504f3 # float 1.41421354
.LCPI1_6:
.long 0x3e95f61a # float 0.292893231
.LCPI1_7:
.long 0xbf800000 # float -1
.LCPI1_8:
.long 0x3f99999a # float 1.20000005
.LCPI1_9:
.long 0x4019999a # float 2.4000001
.LCPI1_10:
.long 0x40000000 # float 2
.LCPI1_12:
.long 0x39b504f3 # float 3.45266977E-4
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_2:
.quad 0x3ff6a09e60000000 # double 1.4142135381698608
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_11:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl _Z4plogf
.p2align 4, 0x90
.type _Z4plogf,@function
_Z4plogf: # @_Z4plogf
.cfi_startproc
# %bb.0:
movaps %xmm0, %xmm1
xorps %xmm0, %xmm0
ucomiss %xmm0, %xmm1
jne .LBB1_1
jp .LBB1_1
# %bb.10: # %.loopexit
retq
.LBB1_1:
subq $56, %rsp
.cfi_def_cfa_offset 64
xorps %xmm0, %xmm0
ucomiss %xmm0, %xmm1
movss %xmm1, 12(%rsp) # 4-byte Spill
jbe .LBB1_3
# %bb.2:
movss .LCPI1_8(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movsd %xmm0, 32(%rsp) # 8-byte Spill
movss .LCPI1_9(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
callq log1p
movsd 16(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movapd %xmm1, %xmm0
callq log
movsd 32(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movapd %xmm1, %xmm0
callq log
xorps %xmm1, %xmm1
cvtsd2ss %xmm0, %xmm1
jmp .LBB1_7
.LBB1_3:
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
addss .LCPI1_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
xorps %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jb .LBB1_5
# %bb.4:
sqrtsd %xmm0, %xmm0
jmp .LBB1_6
.LBB1_5: # %call.sqrt
callq sqrt
.LBB1_6: # %.split
mulsd .LCPI1_2(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss .LCPI1_3(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm0, %xmm1
addss .LCPI1_4(%rip), %xmm1
movss .LCPI1_5(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss %xmm1, %xmm2
mulss .LCPI1_6(%rip), %xmm2
addss %xmm0, %xmm1
mulss %xmm0, %xmm2
addss %xmm1, %xmm2
mulss %xmm0, %xmm1
divss %xmm2, %xmm1
addss .LCPI1_7(%rip), %xmm1
.LBB1_7: # %.preheader
movaps %xmm1, %xmm2
.p2align 4, 0x90
.LBB1_8: # =>This Inner Loop Header: Depth=1
movaps %xmm1, 16(%rsp) # 16-byte Spill
movaps %xmm2, 32(%rsp) # 16-byte Spill
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
callq exp
xorps %xmm1, %xmm1
cvtsd2ss %xmm0, %xmm1
movaps 16(%rsp), %xmm4 # 16-byte Reload
movaps %xmm4, %xmm0
mulss %xmm1, %xmm0
subss 12(%rsp), %xmm0 # 4-byte Folded Reload
movaps %xmm4, %xmm2
addss .LCPI1_10(%rip), %xmm2
mulss %xmm0, %xmm2
addss %xmm0, %xmm0
movaps %xmm4, %xmm3
addss .LCPI1_1(%rip), %xmm3
mulss %xmm3, %xmm0
addss %xmm1, %xmm1
mulss %xmm3, %xmm1
mulss %xmm3, %xmm1
subss %xmm1, %xmm2
divss %xmm2, %xmm0
movaps 32(%rsp), %xmm2 # 16-byte Reload
addss %xmm4, %xmm0
divss %xmm0, %xmm2
addss .LCPI1_7(%rip), %xmm2
andps .LCPI1_11(%rip), %xmm2
movss .LCPI1_12(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm2, %xmm1
cmpltss %xmm1, %xmm2
movaps %xmm2, %xmm1
andnps %xmm0, %xmm1
andps %xmm4, %xmm2
orps %xmm1, %xmm2
movaps %xmm2, %xmm1
jbe .LBB1_8
# %bb.9:
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z4plogf, .Lfunc_end1-_Z4plogf
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008ebf7_00000000-6_plog.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4plogd
.type _Z4plogd, @function
_Z4plogd:
.LFB2027:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movapd %xmm0, %xmm7
movsd %xmm0, 8(%rsp)
pxor %xmm0, %xmm0
ucomisd %xmm0, %xmm7
jp .L15
movsd %xmm0, (%rsp)
je .L3
.L15:
pxor %xmm0, %xmm0
movsd 8(%rsp), %xmm7
comisd %xmm0, %xmm7
jbe .L18
movapd %xmm7, %xmm5
mulsd .LC1(%rip), %xmm5
movapd %xmm5, %xmm0
movq %xmm5, %rbx
call log1p@PLT
movapd %xmm0, %xmm1
movq %rbx, %xmm0
divsd %xmm1, %xmm0
call log@PLT
movapd %xmm0, %xmm1
movsd 8(%rsp), %xmm0
mulsd .LC2(%rip), %xmm0
divsd %xmm1, %xmm0
call log@PLT
movsd %xmm0, (%rsp)
.L12:
movsd (%rsp), %xmm0
call exp@PLT
movsd (%rsp), %xmm6
movapd %xmm6, %xmm4
mulsd %xmm0, %xmm4
subsd 8(%rsp), %xmm4
movsd .LC4(%rip), %xmm5
addsd %xmm6, %xmm5
movapd %xmm6, %xmm1
movapd %xmm4, %xmm2
addsd %xmm4, %xmm2
mulsd %xmm5, %xmm2
movsd .LC9(%rip), %xmm3
addsd %xmm6, %xmm3
mulsd %xmm4, %xmm3
addsd %xmm0, %xmm0
mulsd %xmm5, %xmm0
mulsd %xmm5, %xmm0
subsd %xmm0, %xmm3
divsd %xmm3, %xmm2
movapd %xmm2, %xmm0
addsd %xmm6, %xmm0
movsd %xmm0, (%rsp)
divsd %xmm0, %xmm1
subsd .LC4(%rip), %xmm1
andpd .LC10(%rip), %xmm1
movsd .LC11(%rip), %xmm7
comisd %xmm1, %xmm7
jbe .L12
.L3:
movsd (%rsp), %xmm0
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movsd 8(%rsp), %xmm0
mulsd .LC3(%rip), %xmm0
addsd .LC4(%rip), %xmm0
pxor %xmm1, %xmm1
ucomisd %xmm0, %xmm1
ja .L19
sqrtsd %xmm0, %xmm0
.L11:
movsd .LC5(%rip), %xmm4
mulsd %xmm4, %xmm0
movapd %xmm0, %xmm1
mulsd .LC6(%rip), %xmm1
addsd .LC7(%rip), %xmm1
movapd %xmm0, %xmm3
addsd %xmm1, %xmm3
movapd %xmm3, %xmm2
mulsd %xmm0, %xmm2
addsd %xmm4, %xmm1
mulsd .LC8(%rip), %xmm1
mulsd %xmm0, %xmm1
addsd %xmm3, %xmm1
divsd %xmm1, %xmm2
subsd .LC4(%rip), %xmm2
movsd %xmm2, (%rsp)
jmp .L12
.L19:
call sqrt@PLT
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z4plogd, .-_Z4plogd
.globl _Z4plogf
.type _Z4plogf, @function
_Z4plogf:
.LFB2028:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movaps %xmm0, %xmm7
movss %xmm0, 12(%rsp)
pxor %xmm0, %xmm0
ucomiss %xmm0, %xmm7
jp .L33
movss %xmm0, 8(%rsp)
je .L21
.L33:
pxor %xmm0, %xmm0
movss 12(%rsp), %xmm7
comiss %xmm0, %xmm7
jbe .L36
movaps %xmm7, %xmm5
mulss .LC13(%rip), %xmm5
movaps %xmm5, %xmm0
movd %xmm5, %ebx
call log1pf@PLT
movaps %xmm0, %xmm1
movd %ebx, %xmm0
divss %xmm1, %xmm0
call logf@PLT
movaps %xmm0, %xmm1
movss 12(%rsp), %xmm0
mulss .LC14(%rip), %xmm0
divss %xmm1, %xmm0
call logf@PLT
movss %xmm0, 8(%rsp)
.L30:
movss 8(%rsp), %xmm0
call expf@PLT
movss 8(%rsp), %xmm6
movaps %xmm6, %xmm4
mulss %xmm0, %xmm4
subss 12(%rsp), %xmm4
movss .LC16(%rip), %xmm5
addss %xmm6, %xmm5
movaps %xmm6, %xmm1
movaps %xmm4, %xmm2
addss %xmm4, %xmm2
mulss %xmm5, %xmm2
movss .LC21(%rip), %xmm3
addss %xmm6, %xmm3
mulss %xmm4, %xmm3
addss %xmm0, %xmm0
mulss %xmm5, %xmm0
mulss %xmm5, %xmm0
subss %xmm0, %xmm3
divss %xmm3, %xmm2
movaps %xmm2, %xmm0
addss %xmm6, %xmm0
movss %xmm0, 8(%rsp)
divss %xmm0, %xmm1
subss .LC16(%rip), %xmm1
andps .LC22(%rip), %xmm1
movss .LC23(%rip), %xmm7
comiss %xmm1, %xmm7
jbe .L30
.L21:
movss 8(%rsp), %xmm0
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
movss 12(%rsp), %xmm0
mulss .LC15(%rip), %xmm0
addss .LC16(%rip), %xmm0
pxor %xmm1, %xmm1
ucomiss %xmm0, %xmm1
ja .L37
sqrtss %xmm0, %xmm0
.L29:
movss .LC17(%rip), %xmm4
mulss %xmm4, %xmm0
movaps %xmm0, %xmm1
mulss .LC18(%rip), %xmm1
addss .LC19(%rip), %xmm1
movaps %xmm0, %xmm3
addss %xmm1, %xmm3
movaps %xmm3, %xmm2
mulss %xmm0, %xmm2
addss %xmm4, %xmm1
mulss .LC20(%rip), %xmm1
mulss %xmm0, %xmm1
addss %xmm3, %xmm1
divss %xmm1, %xmm2
subss .LC16(%rip), %xmm2
movss %xmm2, 8(%rsp)
jmp .L30
.L37:
call sqrtf@PLT
jmp .L29
.cfi_endproc
.LFE2028:
.size _Z4plogf, .-_Z4plogf
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 858993459
.long 1073951539
.align 8
.LC2:
.long 858993459
.long 1072902963
.align 8
.LC3:
.long -1961601175
.long 1074118410
.align 8
.LC4:
.long 0
.long 1072693248
.align 8
.LC5:
.long 1719614413
.long 1073127582
.align 8
.LC6:
.long 1578844522
.long 1073720599
.align 8
.LC7:
.long 1718597229
.long 1076132923
.align 8
.LC8:
.long 855738471
.long 1070776003
.align 8
.LC9:
.long 0
.long 1073741824
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC10:
.long -1
.long 2147483647
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC11:
.long 0
.long 1045430272
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC13:
.long 1075419546
.align 4
.LC14:
.long 1067030938
.align 4
.LC15:
.long 1076754516
.align 4
.LC16:
.long 1065353216
.align 4
.LC17:
.long 1068827891
.align 4
.LC18:
.long 1073572027
.align 4
.LC19:
.long 1092870619
.align 4
.LC20:
.long 1050015258
.set .LC21,.LC9+4
.section .rodata.cst16
.align 16
.LC22:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4
.align 4
.LC23:
.long 968164595
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "plog.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z4plogd
.LCPI0_0:
.quad 0x4005bf0a8b145769 # double 2.7182818284590451
.LCPI0_1:
.quad 0x3ff0000000000000 # double 1
.LCPI0_2:
.quad 0x3ff6a09e667f3bcd # double 1.4142135623730951
.LCPI0_3:
.quad 0x3fffad175e1b416a # double 1.9797586132081855
.LCPI0_4:
.quad 0x40247c3b666fb66d # double 10.242640687119286
.LCPI0_5:
.quad 0x3fd2bec333018867 # double 0.29289321881345248
.LCPI0_6:
.quad 0xbff0000000000000 # double -1
.LCPI0_7:
.quad 0x3ff3333333333333 # double 1.2
.LCPI0_8:
.quad 0x4003333333333333 # double 2.3999999999999999
.LCPI0_9:
.quad 0x4000000000000000 # double 2
.LCPI0_11:
.quad 0x3e50000000000000 # double 1.4901161193847656E-8
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI0_10:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl _Z4plogd
.p2align 4, 0x90
.type _Z4plogd,@function
_Z4plogd: # @_Z4plogd
.cfi_startproc
# %bb.0:
movapd %xmm0, %xmm2
xorpd %xmm0, %xmm0
ucomisd %xmm0, %xmm2
jne .LBB0_1
jp .LBB0_1
# %bb.10: # %.loopexit
retq
.LBB0_1:
subq $40, %rsp
.cfi_def_cfa_offset 48
xorpd %xmm1, %xmm1
ucomisd %xmm1, %xmm2
movsd %xmm2, 32(%rsp) # 8-byte Spill
jbe .LBB0_3
# %bb.2:
movsd .LCPI0_7(%rip), %xmm0 # xmm0 = mem[0],zero
mulsd %xmm2, %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
movsd .LCPI0_8(%rip), %xmm0 # xmm0 = mem[0],zero
mulsd %xmm2, %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
callq log1p
movsd (%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movapd %xmm1, %xmm0
callq log
movsd 16(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movapd %xmm1, %xmm0
callq log
movapd %xmm0, %xmm3
jmp .LBB0_7
.LBB0_3:
movsd .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero
mulsd %xmm2, %xmm0
addsd .LCPI0_1(%rip), %xmm0
ucomisd %xmm1, %xmm0
jb .LBB0_5
# %bb.4:
sqrtsd %xmm0, %xmm0
jmp .LBB0_6
.LBB0_5: # %call.sqrt
callq sqrt
.LBB0_6: # %.split
movsd .LCPI0_2(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
movsd .LCPI0_3(%rip), %xmm2 # xmm2 = mem[0],zero
mulsd %xmm0, %xmm2
addsd .LCPI0_4(%rip), %xmm2
addsd %xmm2, %xmm1
mulsd .LCPI0_5(%rip), %xmm1
addsd %xmm0, %xmm2
movapd %xmm0, %xmm3
mulsd %xmm2, %xmm3
mulsd %xmm0, %xmm1
addsd %xmm2, %xmm1
divsd %xmm1, %xmm3
addsd .LCPI0_6(%rip), %xmm3
.LBB0_7: # %.preheader
movapd %xmm3, %xmm2
.p2align 4, 0x90
.LBB0_8: # =>This Inner Loop Header: Depth=1
movapd %xmm3, (%rsp) # 16-byte Spill
movapd %xmm2, 16(%rsp) # 16-byte Spill
movapd %xmm3, %xmm0
callq exp
movapd %xmm0, %xmm1
movapd (%rsp), %xmm4 # 16-byte Reload
movapd %xmm4, %xmm0
mulsd %xmm1, %xmm0
subsd 32(%rsp), %xmm0 # 8-byte Folded Reload
movapd %xmm4, %xmm2
addsd .LCPI0_9(%rip), %xmm2
mulsd %xmm0, %xmm2
addsd %xmm0, %xmm0
movapd %xmm4, %xmm3
addsd .LCPI0_1(%rip), %xmm3
mulsd %xmm3, %xmm0
addsd %xmm1, %xmm1
mulsd %xmm3, %xmm1
mulsd %xmm3, %xmm1
subsd %xmm1, %xmm2
divsd %xmm2, %xmm0
movapd 16(%rsp), %xmm2 # 16-byte Reload
addsd %xmm4, %xmm0
divsd %xmm0, %xmm2
addsd .LCPI0_6(%rip), %xmm2
andpd .LCPI0_10(%rip), %xmm2
movsd .LCPI0_11(%rip), %xmm1 # xmm1 = mem[0],zero
ucomisd %xmm2, %xmm1
cmpltsd %xmm1, %xmm2
movapd %xmm2, %xmm1
andnpd %xmm0, %xmm1
andpd %xmm4, %xmm2
orpd %xmm1, %xmm2
movapd %xmm2, %xmm3
jbe .LBB0_8
# %bb.9:
addq $40, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z4plogd, .Lfunc_end0-_Z4plogd
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z4plogf
.LCPI1_0:
.long 0x402df854 # float 2.71828175
.LCPI1_1:
.long 0x3f800000 # float 1
.LCPI1_3:
.long 0x3ffd68bb # float 1.97975862
.LCPI1_4:
.long 0x4123e1db # float 10.2426405
.LCPI1_5:
.long 0x3fb504f3 # float 1.41421354
.LCPI1_6:
.long 0x3e95f61a # float 0.292893231
.LCPI1_7:
.long 0xbf800000 # float -1
.LCPI1_8:
.long 0x3f99999a # float 1.20000005
.LCPI1_9:
.long 0x4019999a # float 2.4000001
.LCPI1_10:
.long 0x40000000 # float 2
.LCPI1_12:
.long 0x39b504f3 # float 3.45266977E-4
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_2:
.quad 0x3ff6a09e60000000 # double 1.4142135381698608
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_11:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl _Z4plogf
.p2align 4, 0x90
.type _Z4plogf,@function
_Z4plogf: # @_Z4plogf
.cfi_startproc
# %bb.0:
movaps %xmm0, %xmm1
xorps %xmm0, %xmm0
ucomiss %xmm0, %xmm1
jne .LBB1_1
jp .LBB1_1
# %bb.10: # %.loopexit
retq
.LBB1_1:
subq $56, %rsp
.cfi_def_cfa_offset 64
xorps %xmm0, %xmm0
ucomiss %xmm0, %xmm1
movss %xmm1, 12(%rsp) # 4-byte Spill
jbe .LBB1_3
# %bb.2:
movss .LCPI1_8(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movsd %xmm0, 32(%rsp) # 8-byte Spill
movss .LCPI1_9(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
callq log1p
movsd 16(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movapd %xmm1, %xmm0
callq log
movsd 32(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movapd %xmm1, %xmm0
callq log
xorps %xmm1, %xmm1
cvtsd2ss %xmm0, %xmm1
jmp .LBB1_7
.LBB1_3:
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
addss .LCPI1_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
xorps %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jb .LBB1_5
# %bb.4:
sqrtsd %xmm0, %xmm0
jmp .LBB1_6
.LBB1_5: # %call.sqrt
callq sqrt
.LBB1_6: # %.split
mulsd .LCPI1_2(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss .LCPI1_3(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm0, %xmm1
addss .LCPI1_4(%rip), %xmm1
movss .LCPI1_5(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss %xmm1, %xmm2
mulss .LCPI1_6(%rip), %xmm2
addss %xmm0, %xmm1
mulss %xmm0, %xmm2
addss %xmm1, %xmm2
mulss %xmm0, %xmm1
divss %xmm2, %xmm1
addss .LCPI1_7(%rip), %xmm1
.LBB1_7: # %.preheader
movaps %xmm1, %xmm2
.p2align 4, 0x90
.LBB1_8: # =>This Inner Loop Header: Depth=1
movaps %xmm1, 16(%rsp) # 16-byte Spill
movaps %xmm2, 32(%rsp) # 16-byte Spill
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
callq exp
xorps %xmm1, %xmm1
cvtsd2ss %xmm0, %xmm1
movaps 16(%rsp), %xmm4 # 16-byte Reload
movaps %xmm4, %xmm0
mulss %xmm1, %xmm0
subss 12(%rsp), %xmm0 # 4-byte Folded Reload
movaps %xmm4, %xmm2
addss .LCPI1_10(%rip), %xmm2
mulss %xmm0, %xmm2
addss %xmm0, %xmm0
movaps %xmm4, %xmm3
addss .LCPI1_1(%rip), %xmm3
mulss %xmm3, %xmm0
addss %xmm1, %xmm1
mulss %xmm3, %xmm1
mulss %xmm3, %xmm1
subss %xmm1, %xmm2
divss %xmm2, %xmm0
movaps 32(%rsp), %xmm2 # 16-byte Reload
addss %xmm4, %xmm0
divss %xmm0, %xmm2
addss .LCPI1_7(%rip), %xmm2
andps .LCPI1_11(%rip), %xmm2
movss .LCPI1_12(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm2, %xmm1
cmpltss %xmm1, %xmm2
movaps %xmm2, %xmm1
andnps %xmm0, %xmm1
andps %xmm4, %xmm2
orps %xmm1, %xmm2
movaps %xmm2, %xmm1
jbe .LBB1_8
# %bb.9:
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z4plogf, .Lfunc_end1-_Z4plogf
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void Initialize_Kernel(int size, unsigned int *randoms, int *bestSeen, int *origin, int *mis, int *incomplete)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < size)
{
// Taustep is performed with S1=13, S2=19, S3=12, and M=UINT_MAX coded into kernel
unsigned int z = randoms[idx];
unsigned int b = (((z << 13) ^ z) >> 19);
z = (((z & UINT_MAX) << 12) ^ b);
// Set the origin to be self
origin[idx] = idx;
// Set the bestSeen value to be either random from 0-1000000 or 1000001 if in MIS
int status = mis[idx];
int value = 0;
if (status == 1)
value = 1000001;
bestSeen[idx] = (mis[idx] == -1) ? (z % 1000000) : value;
// Write out new random value for seeding
randoms[idx] = z;
}
// Reset incomplete value
if (idx == 0)
incomplete[0] = 0;
} | code for sm_80
Function : _Z17Initialize_KerneliPjPiS0_S0_S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x210 ; /* 0x000001d000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R11, R11, c[0x0][0x0], R0 ; /* 0x000000000b0b7a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P1, PT, R11.reuse, c[0x0][0x160], PT ; /* 0x000058000b007a0c */
/* 0x040fe40003f26270 */
/*0070*/ ISETP.NE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f05270 */
/*0080*/ @P1 BRA 0x200 ; /* 0x0000017000001947 */
/* 0x000fea0003800000 */
/*0090*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fc800078e00ff */
/*00a0*/ IMAD.WIDE R2, R11, R6, c[0x0][0x168] ; /* 0x00005a000b027625 */
/* 0x000fc800078e0206 */
/*00b0*/ IMAD.WIDE R4, R11.reuse, R6.reuse, c[0x0][0x178] ; /* 0x00005e000b047625 */
/* 0x0c0fe200078e0206 */
/*00c0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea6000c1e1900 */
/*00d0*/ IMAD.WIDE R6, R11.reuse, R6, c[0x0][0x180] ; /* 0x000060000b067625 */
/* 0x040fe200078e0206 */
/*00e0*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0001ea000c101904 */
/*00f0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1900 */
/*0100*/ LEA R4, P3, R11, c[0x0][0x170], 0x2 ; /* 0x00005c000b047a11 */
/* 0x001fe200078610ff */
/*0110*/ IMAD.SHL.U32 R9, R0, 0x2000, RZ ; /* 0x0000200000097824 */
/* 0x004fca00078e00ff */
/*0120*/ LOP3.LUT R9, R9, R0, RZ, 0x3c, !PT ; /* 0x0000000009097212 */
/* 0x000fe200078e3cff */
/*0130*/ IMAD.SHL.U32 R0, R0, 0x1000, RZ ; /* 0x0000100000007824 */
/* 0x000fe200078e00ff */
/*0140*/ ISETP.NE.AND P2, PT, R6, -0x1, PT ; /* 0xffffffff0600780c */
/* 0x008fe40003f45270 */
/*0150*/ SHF.R.U32.HI R9, RZ, 0x13, R9 ; /* 0x00000013ff097819 */
/* 0x000fc80000011609 */
/*0160*/ LOP3.LUT R13, R9, R0, RZ, 0x3c, !PT ; /* 0x00000000090d7212 */
/* 0x000fe400078e3cff */
/*0170*/ ISETP.NE.AND P1, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fca0003f25270 */
/*0180*/ @!P2 IMAD.WIDE.U32 R8, R13, 0x431bde83, RZ ; /* 0x431bde830d08a825 */
/* 0x000fe200078e00ff */
/*0190*/ SHF.R.S32.HI R0, RZ, 0x1f, R11 ; /* 0x0000001fff007819 */
/* 0x000fc8000001140b */
/*01a0*/ @!P2 SHF.R.U32.HI R8, RZ, 0x12, R9 ; /* 0x00000012ff08a819 */
/* 0x000fe40000011609 */
/*01b0*/ SEL R7, RZ, 0xf4241, P1 ; /* 0x000f4241ff077807 */
/* 0x000fe40000800000 */
/*01c0*/ LEA.HI.X R5, R11, c[0x0][0x174], R0, 0x2, P3 ; /* 0x00005d000b057a11 */
/* 0x000fe200018f1400 */
/*01d0*/ @!P2 IMAD R7, R8, -0xf4240, R13 ; /* 0xfff0bdc00807a824 */
/* 0x000fca00078e020d */
/*01e0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e8000c101904 */
/*01f0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e4000c101904 */
/*0200*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0210*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0220*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff027624 */
/* 0x001fe400078e00ff */
/*0230*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff037624 */
/* 0x000fca00078e00ff */
/*0240*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*0250*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0260*/ BRA 0x260; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void Initialize_Kernel(int size, unsigned int *randoms, int *bestSeen, int *origin, int *mis, int *incomplete)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < size)
{
// Taustep is performed with S1=13, S2=19, S3=12, and M=UINT_MAX coded into kernel
unsigned int z = randoms[idx];
unsigned int b = (((z << 13) ^ z) >> 19);
z = (((z & UINT_MAX) << 12) ^ b);
// Set the origin to be self
origin[idx] = idx;
// Set the bestSeen value to be either random from 0-1000000 or 1000001 if in MIS
int status = mis[idx];
int value = 0;
if (status == 1)
value = 1000001;
bestSeen[idx] = (mis[idx] == -1) ? (z % 1000000) : value;
// Write out new random value for seeding
randoms[idx] = z;
}
// Reset incomplete value
if (idx == 0)
incomplete[0] = 0;
} | .file "tmpxft_00058a2b_00000000-6_Initialize_Kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z17Initialize_KerneliPjPiS0_S0_S0_iPjPiS0_S0_S0_
.type _Z49__device_stub__Z17Initialize_KerneliPjPiS0_S0_S0_iPjPiS0_S0_S0_, @function
_Z49__device_stub__Z17Initialize_KerneliPjPiS0_S0_S0_iPjPiS0_S0_S0_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17Initialize_KerneliPjPiS0_S0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z17Initialize_KerneliPjPiS0_S0_S0_iPjPiS0_S0_S0_, .-_Z49__device_stub__Z17Initialize_KerneliPjPiS0_S0_S0_iPjPiS0_S0_S0_
.globl _Z17Initialize_KerneliPjPiS0_S0_S0_
.type _Z17Initialize_KerneliPjPiS0_S0_S0_, @function
_Z17Initialize_KerneliPjPiS0_S0_S0_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z17Initialize_KerneliPjPiS0_S0_S0_iPjPiS0_S0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17Initialize_KerneliPjPiS0_S0_S0_, .-_Z17Initialize_KerneliPjPiS0_S0_S0_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17Initialize_KerneliPjPiS0_S0_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17Initialize_KerneliPjPiS0_S0_S0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void Initialize_Kernel(int size, unsigned int *randoms, int *bestSeen, int *origin, int *mis, int *incomplete)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < size)
{
// Taustep is performed with S1=13, S2=19, S3=12, and M=UINT_MAX coded into kernel
unsigned int z = randoms[idx];
unsigned int b = (((z << 13) ^ z) >> 19);
z = (((z & UINT_MAX) << 12) ^ b);
// Set the origin to be self
origin[idx] = idx;
// Set the bestSeen value to be either random from 0-1000000 or 1000001 if in MIS
int status = mis[idx];
int value = 0;
if (status == 1)
value = 1000001;
bestSeen[idx] = (mis[idx] == -1) ? (z % 1000000) : value;
// Write out new random value for seeding
randoms[idx] = z;
}
// Reset incomplete value
if (idx == 0)
incomplete[0] = 0;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Initialize_Kernel(int size, unsigned int *randoms, int *bestSeen, int *origin, int *mis, int *incomplete)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < size)
{
// Taustep is performed with S1=13, S2=19, S3=12, and M=UINT_MAX coded into kernel
unsigned int z = randoms[idx];
unsigned int b = (((z << 13) ^ z) >> 19);
z = (((z & UINT_MAX) << 12) ^ b);
// Set the origin to be self
origin[idx] = idx;
// Set the bestSeen value to be either random from 0-1000000 or 1000001 if in MIS
int status = mis[idx];
int value = 0;
if (status == 1)
value = 1000001;
bestSeen[idx] = (mis[idx] == -1) ? (z % 1000000) : value;
// Write out new random value for seeding
randoms[idx] = z;
}
// Reset incomplete value
if (idx == 0)
incomplete[0] = 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Initialize_Kernel(int size, unsigned int *randoms, int *bestSeen, int *origin, int *mis, int *incomplete)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < size)
{
// Taustep is performed with S1=13, S2=19, S3=12, and M=UINT_MAX coded into kernel
unsigned int z = randoms[idx];
unsigned int b = (((z << 13) ^ z) >> 19);
z = (((z & UINT_MAX) << 12) ^ b);
// Set the origin to be self
origin[idx] = idx;
// Set the bestSeen value to be either random from 0-1000000 or 1000001 if in MIS
int status = mis[idx];
int value = 0;
if (status == 1)
value = 1000001;
bestSeen[idx] = (mis[idx] == -1) ? (z % 1000000) : value;
// Write out new random value for seeding
randoms[idx] = z;
}
// Reset incomplete value
if (idx == 0)
incomplete[0] = 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17Initialize_KerneliPjPiS0_S0_S0_
.globl _Z17Initialize_KerneliPjPiS0_S0_S0_
.p2align 8
.type _Z17Initialize_KerneliPjPiS0_S0_S0_,@function
_Z17Initialize_KerneliPjPiS0_S0_S0_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x8
s_load_b128 s[4:7], s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s8, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v6, vcc_lo
global_load_b32 v0, v[3:4], off
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
global_store_b32 v[7:8], v1, off
global_load_b32 v7, v[5:6], off
s_waitcnt vmcnt(1)
v_lshlrev_b32_e32 v5, 13, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor_b32_e32 v6, v5, v0
v_lshlrev_b32_e32 v5, 12, v0
v_lshrrev_b32_e32 v6, 19, v6
s_waitcnt vmcnt(0)
v_cmpx_ne_u32_e32 -1, v7
s_xor_b32 s3, exec_lo, s3
v_cmp_eq_u32_e32 vcc_lo, 1, v7
v_cndmask_b32_e64 v0, 0, 0xf4241, vcc_lo
s_or_saveexec_b32 s3, s3
v_xor_b32_e32 v5, v6, v5
s_xor_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v5, 0x431bde83
v_lshrrev_b32_e32 v0, 18, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_u32_u24_e32 v0, 0xf4240, v0
v_sub_nc_u32_e32 v0, v5, v0
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[4:5], s[0:1], 0x10
v_lshlrev_b64 v[6:7], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_store_b32 v[6:7], v0, off
global_store_b32 v[3:4], v5, off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v1
s_cbranch_execz .LBB0_8
s_load_b64 s[0:1], s[0:1], 0x28
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v0, s[0:1]
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17Initialize_KerneliPjPiS0_S0_S0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17Initialize_KerneliPjPiS0_S0_S0_, .Lfunc_end0-_Z17Initialize_KerneliPjPiS0_S0_S0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17Initialize_KerneliPjPiS0_S0_S0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17Initialize_KerneliPjPiS0_S0_S0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Initialize_Kernel(int size, unsigned int *randoms, int *bestSeen, int *origin, int *mis, int *incomplete)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < size)
{
// Taustep is performed with S1=13, S2=19, S3=12, and M=UINT_MAX coded into kernel
unsigned int z = randoms[idx];
unsigned int b = (((z << 13) ^ z) >> 19);
z = (((z & UINT_MAX) << 12) ^ b);
// Set the origin to be self
origin[idx] = idx;
// Set the bestSeen value to be either random from 0-1000000 or 1000001 if in MIS
int status = mis[idx];
int value = 0;
if (status == 1)
value = 1000001;
bestSeen[idx] = (mis[idx] == -1) ? (z % 1000000) : value;
// Write out new random value for seeding
randoms[idx] = z;
}
// Reset incomplete value
if (idx == 0)
incomplete[0] = 0;
} | .text
.file "Initialize_Kernel.hip"
.globl _Z32__device_stub__Initialize_KerneliPjPiS0_S0_S0_ # -- Begin function _Z32__device_stub__Initialize_KerneliPjPiS0_S0_S0_
.p2align 4, 0x90
.type _Z32__device_stub__Initialize_KerneliPjPiS0_S0_S0_,@function
_Z32__device_stub__Initialize_KerneliPjPiS0_S0_S0_: # @_Z32__device_stub__Initialize_KerneliPjPiS0_S0_S0_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 4(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17Initialize_KerneliPjPiS0_S0_S0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z32__device_stub__Initialize_KerneliPjPiS0_S0_S0_, .Lfunc_end0-_Z32__device_stub__Initialize_KerneliPjPiS0_S0_S0_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17Initialize_KerneliPjPiS0_S0_S0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17Initialize_KerneliPjPiS0_S0_S0_,@object # @_Z17Initialize_KerneliPjPiS0_S0_S0_
.section .rodata,"a",@progbits
.globl _Z17Initialize_KerneliPjPiS0_S0_S0_
.p2align 3, 0x0
_Z17Initialize_KerneliPjPiS0_S0_S0_:
.quad _Z32__device_stub__Initialize_KerneliPjPiS0_S0_S0_
.size _Z17Initialize_KerneliPjPiS0_S0_S0_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17Initialize_KerneliPjPiS0_S0_S0_"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__Initialize_KerneliPjPiS0_S0_S0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17Initialize_KerneliPjPiS0_S0_S0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17Initialize_KerneliPjPiS0_S0_S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x210 ; /* 0x000001d000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R11, R11, c[0x0][0x0], R0 ; /* 0x000000000b0b7a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P1, PT, R11.reuse, c[0x0][0x160], PT ; /* 0x000058000b007a0c */
/* 0x040fe40003f26270 */
/*0070*/ ISETP.NE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f05270 */
/*0080*/ @P1 BRA 0x200 ; /* 0x0000017000001947 */
/* 0x000fea0003800000 */
/*0090*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fc800078e00ff */
/*00a0*/ IMAD.WIDE R2, R11, R6, c[0x0][0x168] ; /* 0x00005a000b027625 */
/* 0x000fc800078e0206 */
/*00b0*/ IMAD.WIDE R4, R11.reuse, R6.reuse, c[0x0][0x178] ; /* 0x00005e000b047625 */
/* 0x0c0fe200078e0206 */
/*00c0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea6000c1e1900 */
/*00d0*/ IMAD.WIDE R6, R11.reuse, R6, c[0x0][0x180] ; /* 0x000060000b067625 */
/* 0x040fe200078e0206 */
/*00e0*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0001ea000c101904 */
/*00f0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1900 */
/*0100*/ LEA R4, P3, R11, c[0x0][0x170], 0x2 ; /* 0x00005c000b047a11 */
/* 0x001fe200078610ff */
/*0110*/ IMAD.SHL.U32 R9, R0, 0x2000, RZ ; /* 0x0000200000097824 */
/* 0x004fca00078e00ff */
/*0120*/ LOP3.LUT R9, R9, R0, RZ, 0x3c, !PT ; /* 0x0000000009097212 */
/* 0x000fe200078e3cff */
/*0130*/ IMAD.SHL.U32 R0, R0, 0x1000, RZ ; /* 0x0000100000007824 */
/* 0x000fe200078e00ff */
/*0140*/ ISETP.NE.AND P2, PT, R6, -0x1, PT ; /* 0xffffffff0600780c */
/* 0x008fe40003f45270 */
/*0150*/ SHF.R.U32.HI R9, RZ, 0x13, R9 ; /* 0x00000013ff097819 */
/* 0x000fc80000011609 */
/*0160*/ LOP3.LUT R13, R9, R0, RZ, 0x3c, !PT ; /* 0x00000000090d7212 */
/* 0x000fe400078e3cff */
/*0170*/ ISETP.NE.AND P1, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fca0003f25270 */
/*0180*/ @!P2 IMAD.WIDE.U32 R8, R13, 0x431bde83, RZ ; /* 0x431bde830d08a825 */
/* 0x000fe200078e00ff */
/*0190*/ SHF.R.S32.HI R0, RZ, 0x1f, R11 ; /* 0x0000001fff007819 */
/* 0x000fc8000001140b */
/*01a0*/ @!P2 SHF.R.U32.HI R8, RZ, 0x12, R9 ; /* 0x00000012ff08a819 */
/* 0x000fe40000011609 */
/*01b0*/ SEL R7, RZ, 0xf4241, P1 ; /* 0x000f4241ff077807 */
/* 0x000fe40000800000 */
/*01c0*/ LEA.HI.X R5, R11, c[0x0][0x174], R0, 0x2, P3 ; /* 0x00005d000b057a11 */
/* 0x000fe200018f1400 */
/*01d0*/ @!P2 IMAD R7, R8, -0xf4240, R13 ; /* 0xfff0bdc00807a824 */
/* 0x000fca00078e020d */
/*01e0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e8000c101904 */
/*01f0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e4000c101904 */
/*0200*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0210*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0220*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff027624 */
/* 0x001fe400078e00ff */
/*0230*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff037624 */
/* 0x000fca00078e00ff */
/*0240*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*0250*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0260*/ BRA 0x260; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17Initialize_KerneliPjPiS0_S0_S0_
.globl _Z17Initialize_KerneliPjPiS0_S0_S0_
.p2align 8
.type _Z17Initialize_KerneliPjPiS0_S0_S0_,@function
_Z17Initialize_KerneliPjPiS0_S0_S0_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x8
s_load_b128 s[4:7], s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s8, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v6, vcc_lo
global_load_b32 v0, v[3:4], off
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
global_store_b32 v[7:8], v1, off
global_load_b32 v7, v[5:6], off
s_waitcnt vmcnt(1)
v_lshlrev_b32_e32 v5, 13, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor_b32_e32 v6, v5, v0
v_lshlrev_b32_e32 v5, 12, v0
v_lshrrev_b32_e32 v6, 19, v6
s_waitcnt vmcnt(0)
v_cmpx_ne_u32_e32 -1, v7
s_xor_b32 s3, exec_lo, s3
v_cmp_eq_u32_e32 vcc_lo, 1, v7
v_cndmask_b32_e64 v0, 0, 0xf4241, vcc_lo
s_or_saveexec_b32 s3, s3
v_xor_b32_e32 v5, v6, v5
s_xor_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v5, 0x431bde83
v_lshrrev_b32_e32 v0, 18, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_u32_u24_e32 v0, 0xf4240, v0
v_sub_nc_u32_e32 v0, v5, v0
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[4:5], s[0:1], 0x10
v_lshlrev_b64 v[6:7], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_store_b32 v[6:7], v0, off
global_store_b32 v[3:4], v5, off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v1
s_cbranch_execz .LBB0_8
s_load_b64 s[0:1], s[0:1], 0x28
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v0, s[0:1]
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17Initialize_KerneliPjPiS0_S0_S0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17Initialize_KerneliPjPiS0_S0_S0_, .Lfunc_end0-_Z17Initialize_KerneliPjPiS0_S0_S0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17Initialize_KerneliPjPiS0_S0_S0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17Initialize_KerneliPjPiS0_S0_S0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00058a2b_00000000-6_Initialize_Kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z17Initialize_KerneliPjPiS0_S0_S0_iPjPiS0_S0_S0_
.type _Z49__device_stub__Z17Initialize_KerneliPjPiS0_S0_S0_iPjPiS0_S0_S0_, @function
_Z49__device_stub__Z17Initialize_KerneliPjPiS0_S0_S0_iPjPiS0_S0_S0_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17Initialize_KerneliPjPiS0_S0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z17Initialize_KerneliPjPiS0_S0_S0_iPjPiS0_S0_S0_, .-_Z49__device_stub__Z17Initialize_KerneliPjPiS0_S0_S0_iPjPiS0_S0_S0_
.globl _Z17Initialize_KerneliPjPiS0_S0_S0_
.type _Z17Initialize_KerneliPjPiS0_S0_S0_, @function
_Z17Initialize_KerneliPjPiS0_S0_S0_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z17Initialize_KerneliPjPiS0_S0_S0_iPjPiS0_S0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17Initialize_KerneliPjPiS0_S0_S0_, .-_Z17Initialize_KerneliPjPiS0_S0_S0_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17Initialize_KerneliPjPiS0_S0_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17Initialize_KerneliPjPiS0_S0_S0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Initialize_Kernel.hip"
.globl _Z32__device_stub__Initialize_KerneliPjPiS0_S0_S0_ # -- Begin function _Z32__device_stub__Initialize_KerneliPjPiS0_S0_S0_
.p2align 4, 0x90
.type _Z32__device_stub__Initialize_KerneliPjPiS0_S0_S0_,@function
_Z32__device_stub__Initialize_KerneliPjPiS0_S0_S0_: # @_Z32__device_stub__Initialize_KerneliPjPiS0_S0_S0_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 4(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17Initialize_KerneliPjPiS0_S0_S0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z32__device_stub__Initialize_KerneliPjPiS0_S0_S0_, .Lfunc_end0-_Z32__device_stub__Initialize_KerneliPjPiS0_S0_S0_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17Initialize_KerneliPjPiS0_S0_S0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17Initialize_KerneliPjPiS0_S0_S0_,@object # @_Z17Initialize_KerneliPjPiS0_S0_S0_
.section .rodata,"a",@progbits
.globl _Z17Initialize_KerneliPjPiS0_S0_S0_
.p2align 3, 0x0
_Z17Initialize_KerneliPjPiS0_S0_S0_:
.quad _Z32__device_stub__Initialize_KerneliPjPiS0_S0_S0_
.size _Z17Initialize_KerneliPjPiS0_S0_S0_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17Initialize_KerneliPjPiS0_S0_S0_"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__Initialize_KerneliPjPiS0_S0_S0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17Initialize_KerneliPjPiS0_S0_S0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //
// Created by root on 2020/11/20.
//
#include "stdio.h"
#include "cuda_runtime.h"
#define BDIM 32
#define RADIUS 4
#define a0 0.00000f
#define a1 0.80000f
#define a2 -0.20000f
#define a3 0.03809f
#define a4 -0.00357f
__constant__ float coef[RADIUS + 1];
// constant memory is 64KB for each processor, which is good at uniform read
__global__ void stencil_ld(float *in, float *out) {
__shared__ float smem[BDIM + 2 * RADIUS];
int idx = threadIdx.x + blockIdx.x * blockDim.x; // index in global memory
int sidx = threadIdx.x + RADIUS; // index in shared memory
smem[sidx] = in[idx]; // thread index + R is the medium data
if (threadIdx.x < RADIUS) {
// First four threads get data from thread index(left) and thread index + R + dim(right) into shared memory
smem[sidx - RADIUS] = in[idx - RADIUS];
smem[sidx + BDIM] = in[idx + BDIM];
}
__syncthreads();
// calculate stencil
float tmp = 0.0f;
#pragma unroll
for (int i = 0; i <= RADIUS; i++) {
tmp += coef[i] * (smem[sidx + i] - smem[sidx - i]);
}
out[idx] = tmp;
}
// restrict memory is 48KB for each processor, which is only suitable for scatter read
__global__ void stencil_ld_readonly(float *in, float *out, float *__restrict__ dcoef) {
__shared__ float smem[BDIM + 2 * RADIUS];
int idx = threadIdx.x + blockIdx.x * blockDim.x; // index in global memory
int sidx = threadIdx.x + RADIUS; // index in shared memory
smem[sidx] = in[idx]; // thread index + R is the medium data
if (threadIdx.x < RADIUS) {
// First four threads get data from thread index(left) and thread index + R + dim(right) into shared memory
smem[sidx - RADIUS] = in[idx - RADIUS];
smem[sidx + BDIM] = in[idx + BDIM];
}
__syncthreads();
// calculate stencil
float tmp = 0.0f;
#pragma unroll
for (int i = 0; i <= RADIUS; i++) {
tmp += dcoef[i] * (smem[sidx + i] - smem[sidx - i]);
}
out[idx] = tmp;
}
void setup_coef() {
const float h_coef[] = {a0, a1, a2, a3, a4};
cudaMemcpyToSymbol(coef, h_coef, (RADIUS + 1) * sizeof(float));
}
int main() {
int isize = 16;
size_t nBytes = (isize + 2 * RADIUS) * sizeof(float);
// allocate host memory
float *h_in = (float *) malloc(nBytes);
float *hostRef = (float *) malloc(nBytes);
float *gpuRef = (float *) malloc(nBytes);
float *d_in, *d_out, *d_coef;
cudaMalloc((float **) &d_in, nBytes);
cudaMalloc((float **) &d_out, nBytes);
cudaMalloc((float **) &d_coef, (RADIUS + 1) * sizeof(float ));
for (int i = 0; i < isize + 2 * RADIUS; i++) {
h_in[i] = (float) i;
}
cudaMemcpy(d_in, h_in, nBytes, cudaMemcpyHostToDevice);
setup_coef();
dim3 block(BDIM, 1);
dim3 grid((isize + block.x - 1) / block.x, 1);
stencil_ld<<<grid, block>>>(d_in + RADIUS, d_out + RADIUS);
cudaDeviceSynchronize();
// Copy result back to host
cudaMemcpy(gpuRef, d_out, nBytes, cudaMemcpyDeviceToHost);
for (int i = 0; i < isize + 2 * RADIUS; i++) {
printf("%f->", gpuRef[i]);
}
printf("\n========\n");
cudaMemset(d_out, 0, nBytes);
memset(gpuRef, 0, nBytes);
const float h_coef[] = {a0, a1, a2, a3, a4};
cudaMemcpy(d_coef, h_coef, (RADIUS + 1) * sizeof(float ), cudaMemcpyHostToDevice);
stencil_ld_readonly<<<grid, block>>>(d_in + RADIUS, d_out + RADIUS, d_coef);
cudaDeviceSynchronize();
cudaMemcpy(gpuRef, d_out, nBytes, cudaMemcpyDeviceToHost);
for (int i = 0; i < isize + 2 * RADIUS; i++) {
printf("%f->", gpuRef[i]);
}
return 0;
} | code for sm_80
Function : _Z19stencil_ld_readonlyPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R18, SR_TID.X ; /* 0x0000000000127919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e620000002500 */
/*0050*/ ISETP.GE.U32.AND P0, PT, R18, 0x4, PT ; /* 0x000000041200780c */
/* 0x001fe20003f06070 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R18 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0212 */
/*0070*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fca00078e0205 */
/*0080*/ LDG.E R3, [R4.64] ; /* 0x0000000404037981 */
/* 0x000ea8000c1e1900 */
/*0090*/ @!P0 LDG.E R8, [R4.64+-0x10] ; /* 0xfffff00404088981 */
/* 0x000ee8000c1e1900 */
/*00a0*/ @!P0 LDG.E R9, [R4.64+0x80] ; /* 0x0000800404098981 */
/* 0x000f22000c1e1900 */
/*00b0*/ MOV R6, c[0x0][0x170] ; /* 0x00005c0000067a02 */
/* 0x000fe40000000f00 */
/*00c0*/ MOV R7, c[0x0][0x174] ; /* 0x00005d0000077a02 */
/* 0x000fca0000000f00 */
/*00d0*/ LDG.E.CONSTANT R11, [R6.64] ; /* 0x00000004060b7981 */
/* 0x000168000c1e9900 */
/*00e0*/ LDG.E.CONSTANT R12, [R6.64+0x4] ; /* 0x00000404060c7981 */
/* 0x000168000c1e9900 */
/*00f0*/ LDG.E.CONSTANT R15, [R6.64+0x8] ; /* 0x00000804060f7981 */
/* 0x000168000c1e9900 */
/*0100*/ LDG.E.CONSTANT R17, [R6.64+0xc] ; /* 0x00000c0406117981 */
/* 0x000168000c1e9900 */
/*0110*/ LDG.E.CONSTANT R2, [R6.64+0x10] ; /* 0x0000100406027981 */
/* 0x000168000c1e9900 */
/*0120*/ STS [R18.X4+0x10], R3 ; /* 0x0000100312007388 */
/* 0x004fe80000004800 */
/*0130*/ @!P0 STS [R18.X4], R8 ; /* 0x0000000812008388 */
/* 0x008fe80000004800 */
/*0140*/ @!P0 STS [R18.X4+0x90], R9 ; /* 0x0000900912008388 */
/* 0x010fe80000004800 */
/*0150*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0160*/ LDS R4, [R18.X4+0x10] ; /* 0x0000100012047984 */
/* 0x000e680000004800 */
/*0170*/ LDS R5, [R18.X4+0xc] ; /* 0x00000c0012057984 */
/* 0x000fe80000004800 */
/*0180*/ LDS R10, [R18.X4+0x14] ; /* 0x00001400120a7984 */
/* 0x000ea80000004800 */
/*0190*/ LDS R13, [R18.X4+0x8] ; /* 0x00000800120d7984 */
/* 0x000fe80000004800 */
/*01a0*/ LDS R14, [R18.X4+0x18] ; /* 0x00001800120e7984 */
/* 0x000ee80000004800 */
/*01b0*/ LDS R16, [R18.X4+0x4] ; /* 0x0000040012107984 */
/* 0x000fe80000004800 */
/*01c0*/ LDS R7, [R18.X4+0x1c] ; /* 0x00001c0012077984 */
/* 0x001e280000004800 */
/*01d0*/ LDS R3, [R18.X4] ; /* 0x0000000012037984 */
/* 0x000fe80000004800 */
/*01e0*/ LDS R6, [R18.X4+0x20] ; /* 0x0000200012067984 */
/* 0x000f220000004800 */
/*01f0*/ FADD R4, R4, -R4 ; /* 0x8000000404047221 */
/* 0x002fc80000000000 */
/*0200*/ FFMA R4, R4, R11, RZ ; /* 0x0000000b04047223 */
/* 0x020fe400000000ff */
/*0210*/ FADD R5, -R5, R10 ; /* 0x0000000a05057221 */
/* 0x004fc80000000100 */
/*0220*/ FFMA R4, R5, R12, R4 ; /* 0x0000000c05047223 */
/* 0x000fe20000000004 */
/*0230*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fe20000011400 */
/*0240*/ FADD R13, -R13, R14 ; /* 0x0000000e0d0d7221 */
/* 0x008fc80000000100 */
/*0250*/ FFMA R4, R13, R15, R4 ; /* 0x0000000f0d047223 */
/* 0x000fe40000000004 */
/*0260*/ FADD R7, -R16, R7 ; /* 0x0000000710077221 */
/* 0x001fc80000000100 */
/*0270*/ FFMA R7, R7, R17, R4 ; /* 0x0000001107077223 */
/* 0x000fe20000000004 */
/*0280*/ LEA R4, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000047a11 */
/* 0x000fe200078010ff */
/*0290*/ FADD R3, -R3, R6 ; /* 0x0000000603037221 */
/* 0x010fc60000000100 */
/*02a0*/ LEA.HI.X R5, R0, c[0x0][0x16c], R5, 0x2, P0 ; /* 0x00005b0000057a11 */
/* 0x000fe200000f1405 */
/*02b0*/ FFMA R3, R3, R2, R7 ; /* 0x0000000203037223 */
/* 0x000fca0000000007 */
/*02c0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x000fe2000c101904 */
/*02d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02e0*/ BRA 0x2e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10stencil_ldPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R13, SR_TID.X ; /* 0x00000000000d7919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e620000002500 */
/*0050*/ ISETP.GE.U32.AND P0, PT, R13, 0x4, PT ; /* 0x000000040d00780c */
/* 0x001fe20003f06070 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R13 ; /* 0x0000000000007a24 */
/* 0x002fca00078e020d */
/*0070*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0080*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ @!P0 LDG.E R5, [R2.64+-0x10] ; /* 0xfffff00402058981 */
/* 0x000ee8000c1e1900 */
/*00a0*/ @!P0 LDG.E R6, [R2.64+0x80] ; /* 0x0000800402068981 */
/* 0x000f28000c1e1900 */
/*00b0*/ STS [R13.X4+0x10], R4 ; /* 0x000010040d007388 */
/* 0x004fe80000004800 */
/*00c0*/ @!P0 STS [R13.X4], R5 ; /* 0x000000050d008388 */
/* 0x008fe80000004800 */
/*00d0*/ @!P0 STS [R13.X4+0x90], R6 ; /* 0x000090060d008388 */
/* 0x010fe80000004800 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*00f0*/ LEA R2, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fca00078010ff */
/*0100*/ LDS R7, [R13.X4+0x10] ; /* 0x000010000d077984 */
/* 0x000e280000004800 */
/*0110*/ LDS R8, [R13.X4+0xc] ; /* 0x00000c000d087984 */
/* 0x000fe80000004800 */
/*0120*/ LDS R9, [R13.X4+0x14] ; /* 0x000014000d097984 */
/* 0x000e680000004800 */
/*0130*/ LDS R10, [R13.X4+0x8] ; /* 0x000008000d0a7984 */
/* 0x000fe80000004800 */
/*0140*/ LDS R11, [R13.X4+0x18] ; /* 0x000018000d0b7984 */
/* 0x000ea80000004800 */
/*0150*/ LDS R12, [R13.X4+0x4] ; /* 0x000004000d0c7984 */
/* 0x000fe80000004800 */
/*0160*/ LDS R3, [R13.X4+0x1c] ; /* 0x00001c000d037984 */
/* 0x000ee80000004800 */
/*0170*/ LDS R4, [R13.X4] ; /* 0x000000000d047984 */
/* 0x000fe80000004800 */
/*0180*/ LDS R5, [R13.X4+0x20] ; /* 0x000020000d057984 */
/* 0x000f220000004800 */
/*0190*/ FADD R7, R7, -R7 ; /* 0x8000000707077221 */
/* 0x001fc80000000000 */
/*01a0*/ FFMA R7, R7, c[0x3][0x0], RZ ; /* 0x00c0000007077a23 */
/* 0x000fe400000000ff */
/*01b0*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x002fc80000000100 */
/*01c0*/ FFMA R7, R8, c[0x3][0x4], R7 ; /* 0x00c0010008077a23 */
/* 0x000fe40000000007 */
/*01d0*/ FADD R10, -R10, R11 ; /* 0x0000000b0a0a7221 */
/* 0x004fc80000000100 */
/*01e0*/ FFMA R7, R10, c[0x3][0x8], R7 ; /* 0x00c002000a077a23 */
/* 0x000fe40000000007 */
/*01f0*/ FADD R12, -R12, R3 ; /* 0x000000030c0c7221 */
/* 0x008fe20000000100 */
/*0200*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc60000011400 */
/*0210*/ FFMA R7, R12, c[0x3][0xc], R7 ; /* 0x00c003000c077a23 */
/* 0x000fe20000000007 */
/*0220*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b0000037a11 */
/* 0x000fe200000f1403 */
/*0230*/ FADD R4, -R4, R5 ; /* 0x0000000504047221 */
/* 0x010fc80000000100 */
/*0240*/ FFMA R7, R4, c[0x3][0x10], R7 ; /* 0x00c0040004077a23 */
/* 0x000fca0000000007 */
/*0250*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ BRA 0x270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //
// Created by root on 2020/11/20.
//
#include "stdio.h"
#include "cuda_runtime.h"
#define BDIM 32
#define RADIUS 4
#define a0 0.00000f
#define a1 0.80000f
#define a2 -0.20000f
#define a3 0.03809f
#define a4 -0.00357f
__constant__ float coef[RADIUS + 1];
// constant memory is 64KB for each processor, which is good at uniform read
__global__ void stencil_ld(float *in, float *out) {
__shared__ float smem[BDIM + 2 * RADIUS];
int idx = threadIdx.x + blockIdx.x * blockDim.x; // index in global memory
int sidx = threadIdx.x + RADIUS; // index in shared memory
smem[sidx] = in[idx]; // thread index + R is the medium data
if (threadIdx.x < RADIUS) {
// First four threads get data from thread index(left) and thread index + R + dim(right) into shared memory
smem[sidx - RADIUS] = in[idx - RADIUS];
smem[sidx + BDIM] = in[idx + BDIM];
}
__syncthreads();
// calculate stencil
float tmp = 0.0f;
#pragma unroll
for (int i = 0; i <= RADIUS; i++) {
tmp += coef[i] * (smem[sidx + i] - smem[sidx - i]);
}
out[idx] = tmp;
}
// restrict memory is 48KB for each processor, which is only suitable for scatter read
__global__ void stencil_ld_readonly(float *in, float *out, float *__restrict__ dcoef) {
__shared__ float smem[BDIM + 2 * RADIUS];
int idx = threadIdx.x + blockIdx.x * blockDim.x; // index in global memory
int sidx = threadIdx.x + RADIUS; // index in shared memory
smem[sidx] = in[idx]; // thread index + R is the medium data
if (threadIdx.x < RADIUS) {
// First four threads get data from thread index(left) and thread index + R + dim(right) into shared memory
smem[sidx - RADIUS] = in[idx - RADIUS];
smem[sidx + BDIM] = in[idx + BDIM];
}
__syncthreads();
// calculate stencil
float tmp = 0.0f;
#pragma unroll
for (int i = 0; i <= RADIUS; i++) {
tmp += dcoef[i] * (smem[sidx + i] - smem[sidx - i]);
}
out[idx] = tmp;
}
void setup_coef() {
const float h_coef[] = {a0, a1, a2, a3, a4};
cudaMemcpyToSymbol(coef, h_coef, (RADIUS + 1) * sizeof(float));
}
int main() {
int isize = 16;
size_t nBytes = (isize + 2 * RADIUS) * sizeof(float);
// allocate host memory
float *h_in = (float *) malloc(nBytes);
float *hostRef = (float *) malloc(nBytes);
float *gpuRef = (float *) malloc(nBytes);
float *d_in, *d_out, *d_coef;
cudaMalloc((float **) &d_in, nBytes);
cudaMalloc((float **) &d_out, nBytes);
cudaMalloc((float **) &d_coef, (RADIUS + 1) * sizeof(float ));
for (int i = 0; i < isize + 2 * RADIUS; i++) {
h_in[i] = (float) i;
}
cudaMemcpy(d_in, h_in, nBytes, cudaMemcpyHostToDevice);
setup_coef();
dim3 block(BDIM, 1);
dim3 grid((isize + block.x - 1) / block.x, 1);
stencil_ld<<<grid, block>>>(d_in + RADIUS, d_out + RADIUS);
cudaDeviceSynchronize();
// Copy result back to host
cudaMemcpy(gpuRef, d_out, nBytes, cudaMemcpyDeviceToHost);
for (int i = 0; i < isize + 2 * RADIUS; i++) {
printf("%f->", gpuRef[i]);
}
printf("\n========\n");
cudaMemset(d_out, 0, nBytes);
memset(gpuRef, 0, nBytes);
const float h_coef[] = {a0, a1, a2, a3, a4};
cudaMemcpy(d_coef, h_coef, (RADIUS + 1) * sizeof(float ), cudaMemcpyHostToDevice);
stencil_ld_readonly<<<grid, block>>>(d_in + RADIUS, d_out + RADIUS, d_coef);
cudaDeviceSynchronize();
cudaMemcpy(gpuRef, d_out, nBytes, cudaMemcpyDeviceToHost);
for (int i = 0; i < isize + 2 * RADIUS; i++) {
printf("%f->", gpuRef[i]);
}
return 0;
} | .file "tmpxft_00177148_00000000-6_ConstantMemoryTest.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10setup_coefv
.type _Z10setup_coefv, @function
_Z10setup_coefv:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $0x00000000, (%rsp)
movl $0x3f4ccccd, 4(%rsp)
movl $0xbe4ccccd, 8(%rsp)
movl $0x3d1c0443, 12(%rsp)
movl $0xbb69f6a9, 16(%rsp)
movq %rsp, %rsi
movl $1, %r8d
movl $0, %ecx
movl $20, %edx
leaq _ZL4coef(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z10setup_coefv, .-_Z10setup_coefv
.globl _Z32__device_stub__Z10stencil_ldPfS_PfS_
.type _Z32__device_stub__Z10stencil_ldPfS_PfS_, @function
_Z32__device_stub__Z10stencil_ldPfS_PfS_:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10stencil_ldPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z32__device_stub__Z10stencil_ldPfS_PfS_, .-_Z32__device_stub__Z10stencil_ldPfS_PfS_
.globl _Z10stencil_ldPfS_
.type _Z10stencil_ldPfS_, @function
_Z10stencil_ldPfS_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10stencil_ldPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z10stencil_ldPfS_, .-_Z10stencil_ldPfS_
.globl _Z43__device_stub__Z19stencil_ld_readonlyPfS_S_PfS_S_
.type _Z43__device_stub__Z19stencil_ld_readonlyPfS_S_PfS_S_, @function
_Z43__device_stub__Z19stencil_ld_readonlyPfS_S_PfS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
movq %rdx, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19stencil_ld_readonlyPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z43__device_stub__Z19stencil_ld_readonlyPfS_S_PfS_S_, .-_Z43__device_stub__Z19stencil_ld_readonlyPfS_S_PfS_S_
.globl _Z19stencil_ld_readonlyPfS_S_
.type _Z19stencil_ld_readonlyPfS_S_, @function
_Z19stencil_ld_readonlyPfS_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z19stencil_ld_readonlyPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z19stencil_ld_readonlyPfS_S_, .-_Z19stencil_ld_readonlyPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "%f->"
.LC6:
.string "\n========\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $96, %edi
call malloc@PLT
movq %rax, %rbx
movl $96, %edi
call malloc@PLT
movq %rax, %r13
movq %rsp, %rdi
movl $96, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $96, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
movl $0, %eax
.L24:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq $24, %rax
jne .L24
movl $1, %ecx
movl $96, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
call _Z10setup_coefv
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $32, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L25:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $96, %edx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq %r13, %rbx
leaq 96(%r13), %r12
movq %r13, %rbp
leaq .LC5(%rip), %r14
.L26:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbp
cmpq %r12, %rbp
jne .L26
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $96, %edx
movl $0, %esi
movq 8(%rsp), %rdi
call cudaMemset@PLT
movl $12, %ecx
movl $0, %eax
movq %r13, %rdi
rep stosq
movl $0x00000000, 48(%rsp)
movl $0x3f4ccccd, 52(%rsp)
movl $0xbe4ccccd, 56(%rsp)
movl $0x3d1c0443, 60(%rsp)
movl $0xbb69f6a9, 64(%rsp)
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $20, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L27:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $96, %edx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
leaq .LC5(%rip), %rbp
.L28:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L28
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movq 8(%rsp), %rax
leaq 16(%rax), %rsi
movq (%rsp), %rax
leaq 16(%rax), %rdi
call _Z32__device_stub__Z10stencil_ldPfS_PfS_
jmp .L25
.L35:
movq 8(%rsp), %rax
leaq 16(%rax), %rsi
movq (%rsp), %rax
leaq 16(%rax), %rdi
movq 16(%rsp), %rdx
call _Z43__device_stub__Z19stencil_ld_readonlyPfS_S_PfS_S_
jmp .L27
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z19stencil_ld_readonlyPfS_S_"
.LC8:
.string "_Z10stencil_ldPfS_"
.LC9:
.string "coef"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z19stencil_ld_readonlyPfS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z10stencil_ldPfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $20, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4coef(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL4coef
.comm _ZL4coef,20,16
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //
// Created by root on 2020/11/20.
//
#include "stdio.h"
#include "cuda_runtime.h"
#define BDIM 32
#define RADIUS 4
#define a0 0.00000f
#define a1 0.80000f
#define a2 -0.20000f
#define a3 0.03809f
#define a4 -0.00357f
__constant__ float coef[RADIUS + 1];
// constant memory is 64KB for each processor, which is good at uniform read
__global__ void stencil_ld(float *in, float *out) {
__shared__ float smem[BDIM + 2 * RADIUS];
int idx = threadIdx.x + blockIdx.x * blockDim.x; // index in global memory
int sidx = threadIdx.x + RADIUS; // index in shared memory
smem[sidx] = in[idx]; // thread index + R is the medium data
if (threadIdx.x < RADIUS) {
// First four threads get data from thread index(left) and thread index + R + dim(right) into shared memory
smem[sidx - RADIUS] = in[idx - RADIUS];
smem[sidx + BDIM] = in[idx + BDIM];
}
__syncthreads();
// calculate stencil
float tmp = 0.0f;
#pragma unroll
for (int i = 0; i <= RADIUS; i++) {
tmp += coef[i] * (smem[sidx + i] - smem[sidx - i]);
}
out[idx] = tmp;
}
// restrict memory is 48KB for each processor, which is only suitable for scatter read
__global__ void stencil_ld_readonly(float *in, float *out, float *__restrict__ dcoef) {
__shared__ float smem[BDIM + 2 * RADIUS];
int idx = threadIdx.x + blockIdx.x * blockDim.x; // index in global memory
int sidx = threadIdx.x + RADIUS; // index in shared memory
smem[sidx] = in[idx]; // thread index + R is the medium data
if (threadIdx.x < RADIUS) {
// First four threads get data from thread index(left) and thread index + R + dim(right) into shared memory
smem[sidx - RADIUS] = in[idx - RADIUS];
smem[sidx + BDIM] = in[idx + BDIM];
}
__syncthreads();
// calculate stencil
float tmp = 0.0f;
#pragma unroll
for (int i = 0; i <= RADIUS; i++) {
tmp += dcoef[i] * (smem[sidx + i] - smem[sidx - i]);
}
out[idx] = tmp;
}
void setup_coef() {
const float h_coef[] = {a0, a1, a2, a3, a4};
cudaMemcpyToSymbol(coef, h_coef, (RADIUS + 1) * sizeof(float));
}
int main() {
int isize = 16;
size_t nBytes = (isize + 2 * RADIUS) * sizeof(float);
// allocate host memory
float *h_in = (float *) malloc(nBytes);
float *hostRef = (float *) malloc(nBytes);
float *gpuRef = (float *) malloc(nBytes);
float *d_in, *d_out, *d_coef;
cudaMalloc((float **) &d_in, nBytes);
cudaMalloc((float **) &d_out, nBytes);
cudaMalloc((float **) &d_coef, (RADIUS + 1) * sizeof(float ));
for (int i = 0; i < isize + 2 * RADIUS; i++) {
h_in[i] = (float) i;
}
cudaMemcpy(d_in, h_in, nBytes, cudaMemcpyHostToDevice);
setup_coef();
dim3 block(BDIM, 1);
dim3 grid((isize + block.x - 1) / block.x, 1);
stencil_ld<<<grid, block>>>(d_in + RADIUS, d_out + RADIUS);
cudaDeviceSynchronize();
// Copy result back to host
cudaMemcpy(gpuRef, d_out, nBytes, cudaMemcpyDeviceToHost);
for (int i = 0; i < isize + 2 * RADIUS; i++) {
printf("%f->", gpuRef[i]);
}
printf("\n========\n");
cudaMemset(d_out, 0, nBytes);
memset(gpuRef, 0, nBytes);
const float h_coef[] = {a0, a1, a2, a3, a4};
cudaMemcpy(d_coef, h_coef, (RADIUS + 1) * sizeof(float ), cudaMemcpyHostToDevice);
stencil_ld_readonly<<<grid, block>>>(d_in + RADIUS, d_out + RADIUS, d_coef);
cudaDeviceSynchronize();
cudaMemcpy(gpuRef, d_out, nBytes, cudaMemcpyDeviceToHost);
for (int i = 0; i < isize + 2 * RADIUS; i++) {
printf("%f->", gpuRef[i]);
}
return 0;
} | //
// Created by root on 2020/11/20.
//
#include "stdio.h"
#include "hip/hip_runtime.h"
#define BDIM 32
#define RADIUS 4
#define a0 0.00000f
#define a1 0.80000f
#define a2 -0.20000f
#define a3 0.03809f
#define a4 -0.00357f
__constant__ float coef[RADIUS + 1];
// constant memory is 64KB for each processor, which is good at uniform read
__global__ void stencil_ld(float *in, float *out) {
__shared__ float smem[BDIM + 2 * RADIUS];
int idx = threadIdx.x + blockIdx.x * blockDim.x; // index in global memory
int sidx = threadIdx.x + RADIUS; // index in shared memory
smem[sidx] = in[idx]; // thread index + R is the medium data
if (threadIdx.x < RADIUS) {
// First four threads get data from thread index(left) and thread index + R + dim(right) into shared memory
smem[sidx - RADIUS] = in[idx - RADIUS];
smem[sidx + BDIM] = in[idx + BDIM];
}
__syncthreads();
// calculate stencil
float tmp = 0.0f;
#pragma unroll
for (int i = 0; i <= RADIUS; i++) {
tmp += coef[i] * (smem[sidx + i] - smem[sidx - i]);
}
out[idx] = tmp;
}
// restrict memory is 48KB for each processor, which is only suitable for scatter read
__global__ void stencil_ld_readonly(float *in, float *out, float *__restrict__ dcoef) {
__shared__ float smem[BDIM + 2 * RADIUS];
int idx = threadIdx.x + blockIdx.x * blockDim.x; // index in global memory
int sidx = threadIdx.x + RADIUS; // index in shared memory
smem[sidx] = in[idx]; // thread index + R is the medium data
if (threadIdx.x < RADIUS) {
// First four threads get data from thread index(left) and thread index + R + dim(right) into shared memory
smem[sidx - RADIUS] = in[idx - RADIUS];
smem[sidx + BDIM] = in[idx + BDIM];
}
__syncthreads();
// calculate stencil
float tmp = 0.0f;
#pragma unroll
for (int i = 0; i <= RADIUS; i++) {
tmp += dcoef[i] * (smem[sidx + i] - smem[sidx - i]);
}
out[idx] = tmp;
}
void setup_coef() {
const float h_coef[] = {a0, a1, a2, a3, a4};
hipMemcpyToSymbol(HIP_SYMBOL(coef), h_coef, (RADIUS + 1) * sizeof(float));
}
int main() {
int isize = 16;
size_t nBytes = (isize + 2 * RADIUS) * sizeof(float);
// allocate host memory
float *h_in = (float *) malloc(nBytes);
float *hostRef = (float *) malloc(nBytes);
float *gpuRef = (float *) malloc(nBytes);
float *d_in, *d_out, *d_coef;
hipMalloc((float **) &d_in, nBytes);
hipMalloc((float **) &d_out, nBytes);
hipMalloc((float **) &d_coef, (RADIUS + 1) * sizeof(float ));
for (int i = 0; i < isize + 2 * RADIUS; i++) {
h_in[i] = (float) i;
}
hipMemcpy(d_in, h_in, nBytes, hipMemcpyHostToDevice);
setup_coef();
dim3 block(BDIM, 1);
dim3 grid((isize + block.x - 1) / block.x, 1);
stencil_ld<<<grid, block>>>(d_in + RADIUS, d_out + RADIUS);
hipDeviceSynchronize();
// Copy result back to host
hipMemcpy(gpuRef, d_out, nBytes, hipMemcpyDeviceToHost);
for (int i = 0; i < isize + 2 * RADIUS; i++) {
printf("%f->", gpuRef[i]);
}
printf("\n========\n");
hipMemset(d_out, 0, nBytes);
memset(gpuRef, 0, nBytes);
const float h_coef[] = {a0, a1, a2, a3, a4};
hipMemcpy(d_coef, h_coef, (RADIUS + 1) * sizeof(float ), hipMemcpyHostToDevice);
stencil_ld_readonly<<<grid, block>>>(d_in + RADIUS, d_out + RADIUS, d_coef);
hipDeviceSynchronize();
hipMemcpy(gpuRef, d_out, nBytes, hipMemcpyDeviceToHost);
for (int i = 0; i < isize + 2 * RADIUS; i++) {
printf("%f->", gpuRef[i]);
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //
// Created by root on 2020/11/20.
//
#include "stdio.h"
#include "hip/hip_runtime.h"
#define BDIM 32
#define RADIUS 4
#define a0 0.00000f
#define a1 0.80000f
#define a2 -0.20000f
#define a3 0.03809f
#define a4 -0.00357f
__constant__ float coef[RADIUS + 1];
// constant memory is 64KB for each processor, which is good at uniform read
__global__ void stencil_ld(float *in, float *out) {
__shared__ float smem[BDIM + 2 * RADIUS];
int idx = threadIdx.x + blockIdx.x * blockDim.x; // index in global memory
int sidx = threadIdx.x + RADIUS; // index in shared memory
smem[sidx] = in[idx]; // thread index + R is the medium data
if (threadIdx.x < RADIUS) {
// First four threads get data from thread index(left) and thread index + R + dim(right) into shared memory
smem[sidx - RADIUS] = in[idx - RADIUS];
smem[sidx + BDIM] = in[idx + BDIM];
}
__syncthreads();
// calculate stencil
float tmp = 0.0f;
#pragma unroll
for (int i = 0; i <= RADIUS; i++) {
tmp += coef[i] * (smem[sidx + i] - smem[sidx - i]);
}
out[idx] = tmp;
}
// restrict memory is 48KB for each processor, which is only suitable for scatter read
__global__ void stencil_ld_readonly(float *in, float *out, float *__restrict__ dcoef) {
__shared__ float smem[BDIM + 2 * RADIUS];
int idx = threadIdx.x + blockIdx.x * blockDim.x; // index in global memory
int sidx = threadIdx.x + RADIUS; // index in shared memory
smem[sidx] = in[idx]; // thread index + R is the medium data
if (threadIdx.x < RADIUS) {
// First four threads get data from thread index(left) and thread index + R + dim(right) into shared memory
smem[sidx - RADIUS] = in[idx - RADIUS];
smem[sidx + BDIM] = in[idx + BDIM];
}
__syncthreads();
// calculate stencil
float tmp = 0.0f;
#pragma unroll
for (int i = 0; i <= RADIUS; i++) {
tmp += dcoef[i] * (smem[sidx + i] - smem[sidx - i]);
}
out[idx] = tmp;
}
void setup_coef() {
const float h_coef[] = {a0, a1, a2, a3, a4};
hipMemcpyToSymbol(HIP_SYMBOL(coef), h_coef, (RADIUS + 1) * sizeof(float));
}
int main() {
int isize = 16;
size_t nBytes = (isize + 2 * RADIUS) * sizeof(float);
// allocate host memory
float *h_in = (float *) malloc(nBytes);
float *hostRef = (float *) malloc(nBytes);
float *gpuRef = (float *) malloc(nBytes);
float *d_in, *d_out, *d_coef;
hipMalloc((float **) &d_in, nBytes);
hipMalloc((float **) &d_out, nBytes);
hipMalloc((float **) &d_coef, (RADIUS + 1) * sizeof(float ));
for (int i = 0; i < isize + 2 * RADIUS; i++) {
h_in[i] = (float) i;
}
hipMemcpy(d_in, h_in, nBytes, hipMemcpyHostToDevice);
setup_coef();
dim3 block(BDIM, 1);
dim3 grid((isize + block.x - 1) / block.x, 1);
stencil_ld<<<grid, block>>>(d_in + RADIUS, d_out + RADIUS);
hipDeviceSynchronize();
// Copy result back to host
hipMemcpy(gpuRef, d_out, nBytes, hipMemcpyDeviceToHost);
for (int i = 0; i < isize + 2 * RADIUS; i++) {
printf("%f->", gpuRef[i]);
}
printf("\n========\n");
hipMemset(d_out, 0, nBytes);
memset(gpuRef, 0, nBytes);
const float h_coef[] = {a0, a1, a2, a3, a4};
hipMemcpy(d_coef, h_coef, (RADIUS + 1) * sizeof(float ), hipMemcpyHostToDevice);
stencil_ld_readonly<<<grid, block>>>(d_in + RADIUS, d_out + RADIUS, d_coef);
hipDeviceSynchronize();
hipMemcpy(gpuRef, d_out, nBytes, hipMemcpyDeviceToHost);
for (int i = 0; i < isize + 2 * RADIUS; i++) {
printf("%f->", gpuRef[i]);
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10stencil_ldPfS_
.globl _Z10stencil_ldPfS_
.p2align 8
.type _Z10stencil_ldPfS_,@function
_Z10stencil_ldPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x0
v_add_nc_u32_e32 v6, 4, v0
v_lshlrev_b32_e32 v5, 2, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
s_mov_b32 s2, exec_lo
global_load_b32 v7, v[3:4], off
s_waitcnt vmcnt(0)
ds_store_b32 v5, v7 offset:16
v_cmpx_gt_u32_e32 4, v0
s_cbranch_execz .LBB0_2
s_clause 0x1
global_load_b32 v0, v[3:4], off offset:-16
global_load_b32 v3, v[3:4], off offset:128
s_waitcnt vmcnt(0)
ds_store_2addr_b32 v5, v0, v3 offset1:36
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, coef@rel32@lo+4
s_addc_u32 s3, s3, coef@rel32@hi+12
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, coef@rel32@lo+8
s_addc_u32 s5, s5, coef@rel32@hi+16
s_clause 0x1
s_load_b32 s6, s[2:3], 0x0
s_load_b32 s7, s[4:5], 0x0
v_lshlrev_b32_e32 v0, 2, v6
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, coef@rel32@lo+12
s_addc_u32 s3, s3, coef@rel32@hi+20
ds_load_b32 v0, v0
ds_load_2addr_b32 v[3:4], v5 offset0:2 offset1:3
ds_load_2addr_b32 v[6:7], v5 offset0:5 offset1:6
ds_load_2addr_b32 v[8:9], v5 offset1:1
ds_load_2addr_b32 v[10:11], v5 offset0:7 offset1:8
s_load_b32 s8, s[2:3], 0x0
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, coef@rel32@lo+16
s_addc_u32 s5, s5, coef@rel32@hi+24
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, coef@rel32@lo+20
s_addc_u32 s3, s3, coef@rel32@hi+28
s_clause 0x1
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s2, s[2:3], 0x0
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_sub_f32_e32 v0, v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_fma_f32 v5, s6, v0, 0
v_dual_sub_f32 v0, v7, v3 :: v_dual_sub_f32 v3, v10, v9
v_sub_f32_e32 v4, v6, v4
v_fmac_f32_e32 v5, s7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, s8, v0
v_dual_sub_f32 v0, v11, v8 :: v_dual_fmac_f32 v5, s4, v3
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v5, s2, v0
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[0:1], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10stencil_ldPfS_
.amdhsa_group_segment_fixed_size 160
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10stencil_ldPfS_, .Lfunc_end0-_Z10stencil_ldPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z19stencil_ld_readonlyPfS_S_
.globl _Z19stencil_ld_readonlyPfS_S_
.p2align 8
.type _Z19stencil_ld_readonlyPfS_S_,@function
_Z19stencil_ld_readonlyPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x0
v_add_nc_u32_e32 v6, 4, v0
v_lshlrev_b32_e32 v5, 2, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
s_mov_b32 s4, exec_lo
global_load_b32 v7, v[3:4], off
s_waitcnt vmcnt(0)
ds_store_b32 v5, v7 offset:16
v_cmpx_gt_u32_e32 4, v0
s_cbranch_execz .LBB1_2
s_clause 0x1
global_load_b32 v0, v[3:4], off offset:-16
global_load_b32 v3, v[3:4], off offset:128
s_waitcnt vmcnt(0)
ds_store_2addr_b32 v5, v0, v3 offset1:36
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s4
v_lshlrev_b32_e32 v0, 2, v6
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_load_b64 s[0:1], s[0:1], 0x8
ds_load_b32 v0, v0
ds_load_2addr_b32 v[3:4], v5 offset0:2 offset1:3
ds_load_2addr_b32 v[6:7], v5 offset0:5 offset1:6
s_load_b128 s[4:7], s[2:3], 0x0
ds_load_2addr_b32 v[8:9], v5 offset1:1
ds_load_2addr_b32 v[10:11], v5 offset0:7 offset1:8
s_load_b32 s2, s[2:3], 0x10
s_waitcnt lgkmcnt(0)
v_sub_f32_e32 v0, v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_fma_f32 v5, s4, v0, 0
v_dual_sub_f32 v0, v7, v3 :: v_dual_sub_f32 v3, v10, v9
v_sub_f32_e32 v4, v6, v4
v_fmac_f32_e32 v5, s5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, s6, v0
v_dual_sub_f32 v0, v11, v8 :: v_dual_fmac_f32 v5, s7, v3
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v5, s2, v0
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[0:1], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19stencil_ld_readonlyPfS_S_
.amdhsa_group_segment_fixed_size 160
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z19stencil_ld_readonlyPfS_S_, .Lfunc_end1-_Z19stencil_ld_readonlyPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected coef
.type coef,@object
.section .bss,"aw",@nobits
.globl coef
.p2align 4, 0x0
coef:
.zero 20
.size coef, 20
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym coef
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 160
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10stencil_ldPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10stencil_ldPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 160
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19stencil_ld_readonlyPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19stencil_ld_readonlyPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //
// Created by root on 2020/11/20.
//
#include "stdio.h"
#include "hip/hip_runtime.h"
#define BDIM 32
#define RADIUS 4
#define a0 0.00000f
#define a1 0.80000f
#define a2 -0.20000f
#define a3 0.03809f
#define a4 -0.00357f
__constant__ float coef[RADIUS + 1];
// constant memory is 64KB for each processor, which is good at uniform read
__global__ void stencil_ld(float *in, float *out) {
__shared__ float smem[BDIM + 2 * RADIUS];
int idx = threadIdx.x + blockIdx.x * blockDim.x; // index in global memory
int sidx = threadIdx.x + RADIUS; // index in shared memory
smem[sidx] = in[idx]; // thread index + R is the medium data
if (threadIdx.x < RADIUS) {
// First four threads get data from thread index(left) and thread index + R + dim(right) into shared memory
smem[sidx - RADIUS] = in[idx - RADIUS];
smem[sidx + BDIM] = in[idx + BDIM];
}
__syncthreads();
// calculate stencil
float tmp = 0.0f;
#pragma unroll
for (int i = 0; i <= RADIUS; i++) {
tmp += coef[i] * (smem[sidx + i] - smem[sidx - i]);
}
out[idx] = tmp;
}
// restrict memory is 48KB for each processor, which is only suitable for scatter read
__global__ void stencil_ld_readonly(float *in, float *out, float *__restrict__ dcoef) {
__shared__ float smem[BDIM + 2 * RADIUS];
int idx = threadIdx.x + blockIdx.x * blockDim.x; // index in global memory
int sidx = threadIdx.x + RADIUS; // index in shared memory
smem[sidx] = in[idx]; // thread index + R is the medium data
if (threadIdx.x < RADIUS) {
// First four threads get data from thread index(left) and thread index + R + dim(right) into shared memory
smem[sidx - RADIUS] = in[idx - RADIUS];
smem[sidx + BDIM] = in[idx + BDIM];
}
__syncthreads();
// calculate stencil
float tmp = 0.0f;
#pragma unroll
for (int i = 0; i <= RADIUS; i++) {
tmp += dcoef[i] * (smem[sidx + i] - smem[sidx - i]);
}
out[idx] = tmp;
}
void setup_coef() {
const float h_coef[] = {a0, a1, a2, a3, a4};
hipMemcpyToSymbol(HIP_SYMBOL(coef), h_coef, (RADIUS + 1) * sizeof(float));
}
int main() {
int isize = 16;
size_t nBytes = (isize + 2 * RADIUS) * sizeof(float);
// allocate host memory
float *h_in = (float *) malloc(nBytes);
float *hostRef = (float *) malloc(nBytes);
float *gpuRef = (float *) malloc(nBytes);
float *d_in, *d_out, *d_coef;
hipMalloc((float **) &d_in, nBytes);
hipMalloc((float **) &d_out, nBytes);
hipMalloc((float **) &d_coef, (RADIUS + 1) * sizeof(float ));
for (int i = 0; i < isize + 2 * RADIUS; i++) {
h_in[i] = (float) i;
}
hipMemcpy(d_in, h_in, nBytes, hipMemcpyHostToDevice);
setup_coef();
dim3 block(BDIM, 1);
dim3 grid((isize + block.x - 1) / block.x, 1);
stencil_ld<<<grid, block>>>(d_in + RADIUS, d_out + RADIUS);
hipDeviceSynchronize();
// Copy result back to host
hipMemcpy(gpuRef, d_out, nBytes, hipMemcpyDeviceToHost);
for (int i = 0; i < isize + 2 * RADIUS; i++) {
printf("%f->", gpuRef[i]);
}
printf("\n========\n");
hipMemset(d_out, 0, nBytes);
memset(gpuRef, 0, nBytes);
const float h_coef[] = {a0, a1, a2, a3, a4};
hipMemcpy(d_coef, h_coef, (RADIUS + 1) * sizeof(float ), hipMemcpyHostToDevice);
stencil_ld_readonly<<<grid, block>>>(d_in + RADIUS, d_out + RADIUS, d_coef);
hipDeviceSynchronize();
hipMemcpy(gpuRef, d_out, nBytes, hipMemcpyDeviceToHost);
for (int i = 0; i < isize + 2 * RADIUS; i++) {
printf("%f->", gpuRef[i]);
}
return 0;
} | .text
.file "ConstantMemoryTest.hip"
.globl _Z25__device_stub__stencil_ldPfS_ # -- Begin function _Z25__device_stub__stencil_ldPfS_
.p2align 4, 0x90
.type _Z25__device_stub__stencil_ldPfS_,@function
_Z25__device_stub__stencil_ldPfS_: # @_Z25__device_stub__stencil_ldPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10stencil_ldPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__stencil_ldPfS_, .Lfunc_end0-_Z25__device_stub__stencil_ldPfS_
.cfi_endproc
# -- End function
.globl _Z34__device_stub__stencil_ld_readonlyPfS_S_ # -- Begin function _Z34__device_stub__stencil_ld_readonlyPfS_S_
.p2align 4, 0x90
.type _Z34__device_stub__stencil_ld_readonlyPfS_S_,@function
_Z34__device_stub__stencil_ld_readonlyPfS_S_: # @_Z34__device_stub__stencil_ld_readonlyPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19stencil_ld_readonlyPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z34__device_stub__stencil_ld_readonlyPfS_S_, .Lfunc_end1-_Z34__device_stub__stencil_ld_readonlyPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z10setup_coefv
.LCPI2_0:
.long 0x00000000 # float 0
.long 0x3f4ccccd # float 0.800000011
.long 0xbe4ccccd # float -0.200000003
.long 0x3d1c0443 # float 0.0380900018
.text
.globl _Z10setup_coefv
.p2align 4, 0x90
.type _Z10setup_coefv,@function
_Z10setup_coefv: # @_Z10setup_coefv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movaps .LCPI2_0(%rip), %xmm0 # xmm0 = [0.0E+0,8.00000011E-1,-2.00000003E-1,3.80900018E-2]
movaps %xmm0, (%rsp)
movl $-1150683479, 16(%rsp) # imm = 0xBB69F6A9
movq %rsp, %rsi
movl $coef, %edi
movl $20, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z10setup_coefv, .Lfunc_end2-_Z10setup_coefv
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x00000000 # float 0
.long 0x3f4ccccd # float 0.800000011
.long 0xbe4ccccd # float -0.200000003
.long 0x3d1c0443 # float 0.0380900018
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $96, %edi
callq malloc
movq %rax, %r15
movl $96, %edi
callq malloc
movq %rax, %rbx
leaq 16(%rsp), %rdi
movl $96, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $96, %esi
callq hipMalloc
leaq 104(%rsp), %rdi
movl $20, %esi
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r15,%rax,4)
incq %rax
cmpq $24, %rax
jne .LBB3_1
# %bb.2:
movabsq $4294967297, %r14 # imm = 0x100000001
movq 16(%rsp), %rdi
movl $96, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movaps .LCPI3_0(%rip), %xmm0 # xmm0 = [0.0E+0,8.00000011E-1,-2.00000003E-1,3.80900018E-2]
movaps %xmm0, 64(%rsp)
movl $-1150683479, 80(%rsp) # imm = 0xBB69F6A9
leaq 64(%rsp), %rsi
movl $coef, %edi
movl $20, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 31(%r14), %r15
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movq 16(%rsp), %rax
addq $16, %rax
movq 8(%rsp), %rcx
addq $16, %rcx
movq %rax, 88(%rsp)
movq %rcx, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 112(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10stencil_ldPfS_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $96, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_5: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r12
cmpq $24, %r12
jne .LBB3_5
# %bb.6:
movl $.Lstr, %edi
callq puts@PLT
movq 8(%rsp), %rdi
movl $96, %edx
xorl %esi, %esi
callq hipMemset
xorps %xmm0, %xmm0
movups %xmm0, (%rbx)
movups %xmm0, 16(%rbx)
movups %xmm0, 32(%rbx)
movups %xmm0, 48(%rbx)
movups %xmm0, 64(%rbx)
movups %xmm0, 80(%rbx)
movaps .LCPI3_0(%rip), %xmm0 # xmm0 = [0.0E+0,8.00000011E-1,-2.00000003E-1,3.80900018E-2]
movaps %xmm0, 112(%rsp)
movl $-1150683479, 128(%rsp) # imm = 0xBB69F6A9
movq 104(%rsp), %rdi
leaq 112(%rsp), %rsi
movl $20, %edx
movl $1, %ecx
callq hipMemcpy
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_8
# %bb.7:
movq 16(%rsp), %rax
addq $16, %rax
movq 8(%rsp), %rcx
addq $16, %rcx
movq 104(%rsp), %rdx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
movq %rdx, 40(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 144(%rsp), %rdx
leaq 136(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z19stencil_ld_readonlyPfS_S_, %edi
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_8:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $96, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_9: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r14
cmpq $24, %r14
jne .LBB3_9
# %bb.10:
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10stencil_ldPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19stencil_ld_readonlyPfS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $coef, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $20, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type coef,@object # @coef
.local coef
.comm coef,20,16
.type _Z10stencil_ldPfS_,@object # @_Z10stencil_ldPfS_
.section .rodata,"a",@progbits
.globl _Z10stencil_ldPfS_
.p2align 3, 0x0
_Z10stencil_ldPfS_:
.quad _Z25__device_stub__stencil_ldPfS_
.size _Z10stencil_ldPfS_, 8
.type _Z19stencil_ld_readonlyPfS_S_,@object # @_Z19stencil_ld_readonlyPfS_S_
.globl _Z19stencil_ld_readonlyPfS_S_
.p2align 3, 0x0
_Z19stencil_ld_readonlyPfS_S_:
.quad _Z34__device_stub__stencil_ld_readonlyPfS_S_
.size _Z19stencil_ld_readonlyPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f->"
.size .L.str, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10stencil_ldPfS_"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z19stencil_ld_readonlyPfS_S_"
.size .L__unnamed_2, 30
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "coef"
.size .L__unnamed_3, 5
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n========"
.size .Lstr, 10
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__stencil_ldPfS_
.addrsig_sym _Z34__device_stub__stencil_ld_readonlyPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym coef
.addrsig_sym _Z10stencil_ldPfS_
.addrsig_sym _Z19stencil_ld_readonlyPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19stencil_ld_readonlyPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R18, SR_TID.X ; /* 0x0000000000127919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e620000002500 */
/*0050*/ ISETP.GE.U32.AND P0, PT, R18, 0x4, PT ; /* 0x000000041200780c */
/* 0x001fe20003f06070 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R18 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0212 */
/*0070*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fca00078e0205 */
/*0080*/ LDG.E R3, [R4.64] ; /* 0x0000000404037981 */
/* 0x000ea8000c1e1900 */
/*0090*/ @!P0 LDG.E R8, [R4.64+-0x10] ; /* 0xfffff00404088981 */
/* 0x000ee8000c1e1900 */
/*00a0*/ @!P0 LDG.E R9, [R4.64+0x80] ; /* 0x0000800404098981 */
/* 0x000f22000c1e1900 */
/*00b0*/ MOV R6, c[0x0][0x170] ; /* 0x00005c0000067a02 */
/* 0x000fe40000000f00 */
/*00c0*/ MOV R7, c[0x0][0x174] ; /* 0x00005d0000077a02 */
/* 0x000fca0000000f00 */
/*00d0*/ LDG.E.CONSTANT R11, [R6.64] ; /* 0x00000004060b7981 */
/* 0x000168000c1e9900 */
/*00e0*/ LDG.E.CONSTANT R12, [R6.64+0x4] ; /* 0x00000404060c7981 */
/* 0x000168000c1e9900 */
/*00f0*/ LDG.E.CONSTANT R15, [R6.64+0x8] ; /* 0x00000804060f7981 */
/* 0x000168000c1e9900 */
/*0100*/ LDG.E.CONSTANT R17, [R6.64+0xc] ; /* 0x00000c0406117981 */
/* 0x000168000c1e9900 */
/*0110*/ LDG.E.CONSTANT R2, [R6.64+0x10] ; /* 0x0000100406027981 */
/* 0x000168000c1e9900 */
/*0120*/ STS [R18.X4+0x10], R3 ; /* 0x0000100312007388 */
/* 0x004fe80000004800 */
/*0130*/ @!P0 STS [R18.X4], R8 ; /* 0x0000000812008388 */
/* 0x008fe80000004800 */
/*0140*/ @!P0 STS [R18.X4+0x90], R9 ; /* 0x0000900912008388 */
/* 0x010fe80000004800 */
/*0150*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0160*/ LDS R4, [R18.X4+0x10] ; /* 0x0000100012047984 */
/* 0x000e680000004800 */
/*0170*/ LDS R5, [R18.X4+0xc] ; /* 0x00000c0012057984 */
/* 0x000fe80000004800 */
/*0180*/ LDS R10, [R18.X4+0x14] ; /* 0x00001400120a7984 */
/* 0x000ea80000004800 */
/*0190*/ LDS R13, [R18.X4+0x8] ; /* 0x00000800120d7984 */
/* 0x000fe80000004800 */
/*01a0*/ LDS R14, [R18.X4+0x18] ; /* 0x00001800120e7984 */
/* 0x000ee80000004800 */
/*01b0*/ LDS R16, [R18.X4+0x4] ; /* 0x0000040012107984 */
/* 0x000fe80000004800 */
/*01c0*/ LDS R7, [R18.X4+0x1c] ; /* 0x00001c0012077984 */
/* 0x001e280000004800 */
/*01d0*/ LDS R3, [R18.X4] ; /* 0x0000000012037984 */
/* 0x000fe80000004800 */
/*01e0*/ LDS R6, [R18.X4+0x20] ; /* 0x0000200012067984 */
/* 0x000f220000004800 */
/*01f0*/ FADD R4, R4, -R4 ; /* 0x8000000404047221 */
/* 0x002fc80000000000 */
/*0200*/ FFMA R4, R4, R11, RZ ; /* 0x0000000b04047223 */
/* 0x020fe400000000ff */
/*0210*/ FADD R5, -R5, R10 ; /* 0x0000000a05057221 */
/* 0x004fc80000000100 */
/*0220*/ FFMA R4, R5, R12, R4 ; /* 0x0000000c05047223 */
/* 0x000fe20000000004 */
/*0230*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fe20000011400 */
/*0240*/ FADD R13, -R13, R14 ; /* 0x0000000e0d0d7221 */
/* 0x008fc80000000100 */
/*0250*/ FFMA R4, R13, R15, R4 ; /* 0x0000000f0d047223 */
/* 0x000fe40000000004 */
/*0260*/ FADD R7, -R16, R7 ; /* 0x0000000710077221 */
/* 0x001fc80000000100 */
/*0270*/ FFMA R7, R7, R17, R4 ; /* 0x0000001107077223 */
/* 0x000fe20000000004 */
/*0280*/ LEA R4, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000047a11 */
/* 0x000fe200078010ff */
/*0290*/ FADD R3, -R3, R6 ; /* 0x0000000603037221 */
/* 0x010fc60000000100 */
/*02a0*/ LEA.HI.X R5, R0, c[0x0][0x16c], R5, 0x2, P0 ; /* 0x00005b0000057a11 */
/* 0x000fe200000f1405 */
/*02b0*/ FFMA R3, R3, R2, R7 ; /* 0x0000000203037223 */
/* 0x000fca0000000007 */
/*02c0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x000fe2000c101904 */
/*02d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02e0*/ BRA 0x2e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10stencil_ldPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R13, SR_TID.X ; /* 0x00000000000d7919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e620000002500 */
/*0050*/ ISETP.GE.U32.AND P0, PT, R13, 0x4, PT ; /* 0x000000040d00780c */
/* 0x001fe20003f06070 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R13 ; /* 0x0000000000007a24 */
/* 0x002fca00078e020d */
/*0070*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0080*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ @!P0 LDG.E R5, [R2.64+-0x10] ; /* 0xfffff00402058981 */
/* 0x000ee8000c1e1900 */
/*00a0*/ @!P0 LDG.E R6, [R2.64+0x80] ; /* 0x0000800402068981 */
/* 0x000f28000c1e1900 */
/*00b0*/ STS [R13.X4+0x10], R4 ; /* 0x000010040d007388 */
/* 0x004fe80000004800 */
/*00c0*/ @!P0 STS [R13.X4], R5 ; /* 0x000000050d008388 */
/* 0x008fe80000004800 */
/*00d0*/ @!P0 STS [R13.X4+0x90], R6 ; /* 0x000090060d008388 */
/* 0x010fe80000004800 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*00f0*/ LEA R2, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fca00078010ff */
/*0100*/ LDS R7, [R13.X4+0x10] ; /* 0x000010000d077984 */
/* 0x000e280000004800 */
/*0110*/ LDS R8, [R13.X4+0xc] ; /* 0x00000c000d087984 */
/* 0x000fe80000004800 */
/*0120*/ LDS R9, [R13.X4+0x14] ; /* 0x000014000d097984 */
/* 0x000e680000004800 */
/*0130*/ LDS R10, [R13.X4+0x8] ; /* 0x000008000d0a7984 */
/* 0x000fe80000004800 */
/*0140*/ LDS R11, [R13.X4+0x18] ; /* 0x000018000d0b7984 */
/* 0x000ea80000004800 */
/*0150*/ LDS R12, [R13.X4+0x4] ; /* 0x000004000d0c7984 */
/* 0x000fe80000004800 */
/*0160*/ LDS R3, [R13.X4+0x1c] ; /* 0x00001c000d037984 */
/* 0x000ee80000004800 */
/*0170*/ LDS R4, [R13.X4] ; /* 0x000000000d047984 */
/* 0x000fe80000004800 */
/*0180*/ LDS R5, [R13.X4+0x20] ; /* 0x000020000d057984 */
/* 0x000f220000004800 */
/*0190*/ FADD R7, R7, -R7 ; /* 0x8000000707077221 */
/* 0x001fc80000000000 */
/*01a0*/ FFMA R7, R7, c[0x3][0x0], RZ ; /* 0x00c0000007077a23 */
/* 0x000fe400000000ff */
/*01b0*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x002fc80000000100 */
/*01c0*/ FFMA R7, R8, c[0x3][0x4], R7 ; /* 0x00c0010008077a23 */
/* 0x000fe40000000007 */
/*01d0*/ FADD R10, -R10, R11 ; /* 0x0000000b0a0a7221 */
/* 0x004fc80000000100 */
/*01e0*/ FFMA R7, R10, c[0x3][0x8], R7 ; /* 0x00c002000a077a23 */
/* 0x000fe40000000007 */
/*01f0*/ FADD R12, -R12, R3 ; /* 0x000000030c0c7221 */
/* 0x008fe20000000100 */
/*0200*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc60000011400 */
/*0210*/ FFMA R7, R12, c[0x3][0xc], R7 ; /* 0x00c003000c077a23 */
/* 0x000fe20000000007 */
/*0220*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b0000037a11 */
/* 0x000fe200000f1403 */
/*0230*/ FADD R4, -R4, R5 ; /* 0x0000000504047221 */
/* 0x010fc80000000100 */
/*0240*/ FFMA R7, R4, c[0x3][0x10], R7 ; /* 0x00c0040004077a23 */
/* 0x000fca0000000007 */
/*0250*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ BRA 0x270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10stencil_ldPfS_
.globl _Z10stencil_ldPfS_
.p2align 8
.type _Z10stencil_ldPfS_,@function
_Z10stencil_ldPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x0
v_add_nc_u32_e32 v6, 4, v0
v_lshlrev_b32_e32 v5, 2, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
s_mov_b32 s2, exec_lo
global_load_b32 v7, v[3:4], off
s_waitcnt vmcnt(0)
ds_store_b32 v5, v7 offset:16
v_cmpx_gt_u32_e32 4, v0
s_cbranch_execz .LBB0_2
s_clause 0x1
global_load_b32 v0, v[3:4], off offset:-16
global_load_b32 v3, v[3:4], off offset:128
s_waitcnt vmcnt(0)
ds_store_2addr_b32 v5, v0, v3 offset1:36
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, coef@rel32@lo+4
s_addc_u32 s3, s3, coef@rel32@hi+12
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, coef@rel32@lo+8
s_addc_u32 s5, s5, coef@rel32@hi+16
s_clause 0x1
s_load_b32 s6, s[2:3], 0x0
s_load_b32 s7, s[4:5], 0x0
v_lshlrev_b32_e32 v0, 2, v6
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, coef@rel32@lo+12
s_addc_u32 s3, s3, coef@rel32@hi+20
ds_load_b32 v0, v0
ds_load_2addr_b32 v[3:4], v5 offset0:2 offset1:3
ds_load_2addr_b32 v[6:7], v5 offset0:5 offset1:6
ds_load_2addr_b32 v[8:9], v5 offset1:1
ds_load_2addr_b32 v[10:11], v5 offset0:7 offset1:8
s_load_b32 s8, s[2:3], 0x0
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, coef@rel32@lo+16
s_addc_u32 s5, s5, coef@rel32@hi+24
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, coef@rel32@lo+20
s_addc_u32 s3, s3, coef@rel32@hi+28
s_clause 0x1
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s2, s[2:3], 0x0
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_sub_f32_e32 v0, v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_fma_f32 v5, s6, v0, 0
v_dual_sub_f32 v0, v7, v3 :: v_dual_sub_f32 v3, v10, v9
v_sub_f32_e32 v4, v6, v4
v_fmac_f32_e32 v5, s7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, s8, v0
v_dual_sub_f32 v0, v11, v8 :: v_dual_fmac_f32 v5, s4, v3
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v5, s2, v0
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[0:1], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10stencil_ldPfS_
.amdhsa_group_segment_fixed_size 160
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10stencil_ldPfS_, .Lfunc_end0-_Z10stencil_ldPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z19stencil_ld_readonlyPfS_S_
.globl _Z19stencil_ld_readonlyPfS_S_
.p2align 8
.type _Z19stencil_ld_readonlyPfS_S_,@function
_Z19stencil_ld_readonlyPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x0
v_add_nc_u32_e32 v6, 4, v0
v_lshlrev_b32_e32 v5, 2, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
s_mov_b32 s4, exec_lo
global_load_b32 v7, v[3:4], off
s_waitcnt vmcnt(0)
ds_store_b32 v5, v7 offset:16
v_cmpx_gt_u32_e32 4, v0
s_cbranch_execz .LBB1_2
s_clause 0x1
global_load_b32 v0, v[3:4], off offset:-16
global_load_b32 v3, v[3:4], off offset:128
s_waitcnt vmcnt(0)
ds_store_2addr_b32 v5, v0, v3 offset1:36
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s4
v_lshlrev_b32_e32 v0, 2, v6
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_load_b64 s[0:1], s[0:1], 0x8
ds_load_b32 v0, v0
ds_load_2addr_b32 v[3:4], v5 offset0:2 offset1:3
ds_load_2addr_b32 v[6:7], v5 offset0:5 offset1:6
s_load_b128 s[4:7], s[2:3], 0x0
ds_load_2addr_b32 v[8:9], v5 offset1:1
ds_load_2addr_b32 v[10:11], v5 offset0:7 offset1:8
s_load_b32 s2, s[2:3], 0x10
s_waitcnt lgkmcnt(0)
v_sub_f32_e32 v0, v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_fma_f32 v5, s4, v0, 0
v_dual_sub_f32 v0, v7, v3 :: v_dual_sub_f32 v3, v10, v9
v_sub_f32_e32 v4, v6, v4
v_fmac_f32_e32 v5, s5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, s6, v0
v_dual_sub_f32 v0, v11, v8 :: v_dual_fmac_f32 v5, s7, v3
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v5, s2, v0
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[0:1], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19stencil_ld_readonlyPfS_S_
.amdhsa_group_segment_fixed_size 160
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z19stencil_ld_readonlyPfS_S_, .Lfunc_end1-_Z19stencil_ld_readonlyPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected coef
.type coef,@object
.section .bss,"aw",@nobits
.globl coef
.p2align 4, 0x0
coef:
.zero 20
.size coef, 20
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym coef
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 160
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10stencil_ldPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10stencil_ldPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 160
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19stencil_ld_readonlyPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19stencil_ld_readonlyPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00177148_00000000-6_ConstantMemoryTest.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10setup_coefv
.type _Z10setup_coefv, @function
_Z10setup_coefv:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $0x00000000, (%rsp)
movl $0x3f4ccccd, 4(%rsp)
movl $0xbe4ccccd, 8(%rsp)
movl $0x3d1c0443, 12(%rsp)
movl $0xbb69f6a9, 16(%rsp)
movq %rsp, %rsi
movl $1, %r8d
movl $0, %ecx
movl $20, %edx
leaq _ZL4coef(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z10setup_coefv, .-_Z10setup_coefv
.globl _Z32__device_stub__Z10stencil_ldPfS_PfS_
.type _Z32__device_stub__Z10stencil_ldPfS_PfS_, @function
_Z32__device_stub__Z10stencil_ldPfS_PfS_:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10stencil_ldPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z32__device_stub__Z10stencil_ldPfS_PfS_, .-_Z32__device_stub__Z10stencil_ldPfS_PfS_
.globl _Z10stencil_ldPfS_
.type _Z10stencil_ldPfS_, @function
_Z10stencil_ldPfS_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10stencil_ldPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z10stencil_ldPfS_, .-_Z10stencil_ldPfS_
.globl _Z43__device_stub__Z19stencil_ld_readonlyPfS_S_PfS_S_
.type _Z43__device_stub__Z19stencil_ld_readonlyPfS_S_PfS_S_, @function
_Z43__device_stub__Z19stencil_ld_readonlyPfS_S_PfS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
movq %rdx, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19stencil_ld_readonlyPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z43__device_stub__Z19stencil_ld_readonlyPfS_S_PfS_S_, .-_Z43__device_stub__Z19stencil_ld_readonlyPfS_S_PfS_S_
.globl _Z19stencil_ld_readonlyPfS_S_
.type _Z19stencil_ld_readonlyPfS_S_, @function
_Z19stencil_ld_readonlyPfS_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z19stencil_ld_readonlyPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z19stencil_ld_readonlyPfS_S_, .-_Z19stencil_ld_readonlyPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "%f->"
.LC6:
.string "\n========\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $96, %edi
call malloc@PLT
movq %rax, %rbx
movl $96, %edi
call malloc@PLT
movq %rax, %r13
movq %rsp, %rdi
movl $96, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $96, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
movl $0, %eax
.L24:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq $24, %rax
jne .L24
movl $1, %ecx
movl $96, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
call _Z10setup_coefv
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $32, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L25:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $96, %edx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq %r13, %rbx
leaq 96(%r13), %r12
movq %r13, %rbp
leaq .LC5(%rip), %r14
.L26:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbp
cmpq %r12, %rbp
jne .L26
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $96, %edx
movl $0, %esi
movq 8(%rsp), %rdi
call cudaMemset@PLT
movl $12, %ecx
movl $0, %eax
movq %r13, %rdi
rep stosq
movl $0x00000000, 48(%rsp)
movl $0x3f4ccccd, 52(%rsp)
movl $0xbe4ccccd, 56(%rsp)
movl $0x3d1c0443, 60(%rsp)
movl $0xbb69f6a9, 64(%rsp)
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $20, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L27:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $96, %edx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
leaq .LC5(%rip), %rbp
.L28:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L28
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movq 8(%rsp), %rax
leaq 16(%rax), %rsi
movq (%rsp), %rax
leaq 16(%rax), %rdi
call _Z32__device_stub__Z10stencil_ldPfS_PfS_
jmp .L25
.L35:
movq 8(%rsp), %rax
leaq 16(%rax), %rsi
movq (%rsp), %rax
leaq 16(%rax), %rdi
movq 16(%rsp), %rdx
call _Z43__device_stub__Z19stencil_ld_readonlyPfS_S_PfS_S_
jmp .L27
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z19stencil_ld_readonlyPfS_S_"
.LC8:
.string "_Z10stencil_ldPfS_"
.LC9:
.string "coef"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z19stencil_ld_readonlyPfS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z10stencil_ldPfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $20, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4coef(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL4coef
.comm _ZL4coef,20,16
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ConstantMemoryTest.hip"
.globl _Z25__device_stub__stencil_ldPfS_ # -- Begin function _Z25__device_stub__stencil_ldPfS_
.p2align 4, 0x90
.type _Z25__device_stub__stencil_ldPfS_,@function
_Z25__device_stub__stencil_ldPfS_: # @_Z25__device_stub__stencil_ldPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10stencil_ldPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__stencil_ldPfS_, .Lfunc_end0-_Z25__device_stub__stencil_ldPfS_
.cfi_endproc
# -- End function
.globl _Z34__device_stub__stencil_ld_readonlyPfS_S_ # -- Begin function _Z34__device_stub__stencil_ld_readonlyPfS_S_
.p2align 4, 0x90
.type _Z34__device_stub__stencil_ld_readonlyPfS_S_,@function
_Z34__device_stub__stencil_ld_readonlyPfS_S_: # @_Z34__device_stub__stencil_ld_readonlyPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19stencil_ld_readonlyPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z34__device_stub__stencil_ld_readonlyPfS_S_, .Lfunc_end1-_Z34__device_stub__stencil_ld_readonlyPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z10setup_coefv
.LCPI2_0:
.long 0x00000000 # float 0
.long 0x3f4ccccd # float 0.800000011
.long 0xbe4ccccd # float -0.200000003
.long 0x3d1c0443 # float 0.0380900018
.text
.globl _Z10setup_coefv
.p2align 4, 0x90
.type _Z10setup_coefv,@function
_Z10setup_coefv: # @_Z10setup_coefv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movaps .LCPI2_0(%rip), %xmm0 # xmm0 = [0.0E+0,8.00000011E-1,-2.00000003E-1,3.80900018E-2]
movaps %xmm0, (%rsp)
movl $-1150683479, 16(%rsp) # imm = 0xBB69F6A9
movq %rsp, %rsi
movl $coef, %edi
movl $20, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z10setup_coefv, .Lfunc_end2-_Z10setup_coefv
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x00000000 # float 0
.long 0x3f4ccccd # float 0.800000011
.long 0xbe4ccccd # float -0.200000003
.long 0x3d1c0443 # float 0.0380900018
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $96, %edi
callq malloc
movq %rax, %r15
movl $96, %edi
callq malloc
movq %rax, %rbx
leaq 16(%rsp), %rdi
movl $96, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $96, %esi
callq hipMalloc
leaq 104(%rsp), %rdi
movl $20, %esi
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r15,%rax,4)
incq %rax
cmpq $24, %rax
jne .LBB3_1
# %bb.2:
movabsq $4294967297, %r14 # imm = 0x100000001
movq 16(%rsp), %rdi
movl $96, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movaps .LCPI3_0(%rip), %xmm0 # xmm0 = [0.0E+0,8.00000011E-1,-2.00000003E-1,3.80900018E-2]
movaps %xmm0, 64(%rsp)
movl $-1150683479, 80(%rsp) # imm = 0xBB69F6A9
leaq 64(%rsp), %rsi
movl $coef, %edi
movl $20, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 31(%r14), %r15
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movq 16(%rsp), %rax
addq $16, %rax
movq 8(%rsp), %rcx
addq $16, %rcx
movq %rax, 88(%rsp)
movq %rcx, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 112(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10stencil_ldPfS_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $96, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_5: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r12
cmpq $24, %r12
jne .LBB3_5
# %bb.6:
movl $.Lstr, %edi
callq puts@PLT
movq 8(%rsp), %rdi
movl $96, %edx
xorl %esi, %esi
callq hipMemset
xorps %xmm0, %xmm0
movups %xmm0, (%rbx)
movups %xmm0, 16(%rbx)
movups %xmm0, 32(%rbx)
movups %xmm0, 48(%rbx)
movups %xmm0, 64(%rbx)
movups %xmm0, 80(%rbx)
movaps .LCPI3_0(%rip), %xmm0 # xmm0 = [0.0E+0,8.00000011E-1,-2.00000003E-1,3.80900018E-2]
movaps %xmm0, 112(%rsp)
movl $-1150683479, 128(%rsp) # imm = 0xBB69F6A9
movq 104(%rsp), %rdi
leaq 112(%rsp), %rsi
movl $20, %edx
movl $1, %ecx
callq hipMemcpy
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_8
# %bb.7:
movq 16(%rsp), %rax
addq $16, %rax
movq 8(%rsp), %rcx
addq $16, %rcx
movq 104(%rsp), %rdx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
movq %rdx, 40(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 144(%rsp), %rdx
leaq 136(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z19stencil_ld_readonlyPfS_S_, %edi
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_8:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $96, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_9: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r14
cmpq $24, %r14
jne .LBB3_9
# %bb.10:
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10stencil_ldPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19stencil_ld_readonlyPfS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $coef, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $20, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type coef,@object # @coef
.local coef
.comm coef,20,16
.type _Z10stencil_ldPfS_,@object # @_Z10stencil_ldPfS_
.section .rodata,"a",@progbits
.globl _Z10stencil_ldPfS_
.p2align 3, 0x0
_Z10stencil_ldPfS_:
.quad _Z25__device_stub__stencil_ldPfS_
.size _Z10stencil_ldPfS_, 8
.type _Z19stencil_ld_readonlyPfS_S_,@object # @_Z19stencil_ld_readonlyPfS_S_
.globl _Z19stencil_ld_readonlyPfS_S_
.p2align 3, 0x0
_Z19stencil_ld_readonlyPfS_S_:
.quad _Z34__device_stub__stencil_ld_readonlyPfS_S_
.size _Z19stencil_ld_readonlyPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f->"
.size .L.str, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10stencil_ldPfS_"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z19stencil_ld_readonlyPfS_S_"
.size .L__unnamed_2, 30
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "coef"
.size .L__unnamed_3, 5
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n========"
.size .Lstr, 10
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__stencil_ldPfS_
.addrsig_sym _Z34__device_stub__stencil_ld_readonlyPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym coef
.addrsig_sym _Z10stencil_ldPfS_
.addrsig_sym _Z19stencil_ld_readonlyPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // cuda_example3.cu : Defines the entry point for the console application.
//
#include <stdio.h>
#include <cuda.h>
#include <string.h>
#define A(x,y) A[M*x+y]
#define a_h(x,y) a_h[M*x+y]
typedef struct cudaDeviceProp cudaDevProp_t;
// Kernel that executes on the CUDA device
__global__ void bar(float *A, int N, int M){
int i = blockIdx.x * blockDim.x + threadIdx.x; //blockIdx*blockDim e blockIdx*blockDim garante que toda a matriz seja coberda por //threads
int j = blockIdx.y * blockDim.y + threadIdx.y;
if(i<N && j<M){
A(i,j) = M*i+j;}
}
void checkCUDAError(const char *msg)
{
cudaError_t err = cudaGetLastError();
if( cudaSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg,
cudaGetErrorString( err) );
exit(EXIT_FAILURE);
}
}
// main routine that executes on the host
int main( void )
{
float *a_h, *a_d;
const int N = 1000;
const int M = 10000;
int ct, dev;
cudaDevProp_t prop;
cudaGetDeviceCount(&ct);
if(ct == 0){
printf("\nNo CUDA device found.\n");
exit(0);
}
cudaGetDevice(&dev);
cudaGetDeviceProperties(&prop,dev);
dim3 bDim(16,16); //threads por bloco. Nao podem ultrapassar a capacidade da VGA
//se o Z nao for definido, fica Z=1
dim3 gDim((N/bDim.x)+( N % bDim.x == 0 ? 0 : 1 ),M/bDim.y+( M % bDim.y == 0 ? 0 : 1 )); //~numBlocks
size_t size = N * M *sizeof( float );
a_h = (float *)malloc( size ); //Tudo sera alocado da mesma forma, pois temos matriz A[N*M] mas estamos visualizando A[N][M]
cudaMalloc( (void **)&a_d, size );
cudaMemcpy( a_d, a_h, size, cudaMemcpyHostToDevice );
//checkCUDAError("memcpy");
bar<<<gDim, bDim>>>(a_d, N,M);
//cudaThreadSynchronize(); // bloqueia o device ate que a execucao do kernel tenha sido concluida. Retorna erro ou sucesso.
//checkCUDAError("kernel invocation");
cudaMemcpy( a_h, a_d, sizeof( float ) * N * M, cudaMemcpyDeviceToHost ); //recuperando resultados
//checkCUDAError("memcpy"); //checa erro ao recuperar os resultados
/*for ( int i = 0; i < N; i++ ){
printf("%d[ ", i);
for(int j = 0; j<M; ++j){
printf( "%d ",(int)a_h(i,j) );
}
puts(" ]");
puts("\n");
}*/
printf("\n\n%d\n\n", (int)a_h((N-1),(M-1)));
/*if((int)a_h((N-1),(M-1))!=(N*N-1)){
printf("\n\nKernel com erros de programacao");
exit(1);
}*/
free( a_h );
cudaFree( a_d );
//printf("\n\tPrograma sem erros CUDA...\n\n"); //se o programa chegou aqui, ele nao apresenta erros.
return 0;
} | code for sm_80
Function : _Z3barPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x16c], PT ; /* 0x00005b0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x168], P0 ; /* 0x00005a0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R0, R0, c[0x0][0x16c], R3 ; /* 0x00005b0000007a24 */
/* 0x000fe200078e0203 */
/*00b0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00d0*/ I2F R5, R0 ; /* 0x0000000000057306 */
/* 0x000e2e0000201400 */
/*00e0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // cuda_example3.cu : Defines the entry point for the console application.
//
#include <stdio.h>
#include <cuda.h>
#include <string.h>
#define A(x,y) A[M*x+y]
#define a_h(x,y) a_h[M*x+y]
typedef struct cudaDeviceProp cudaDevProp_t;
// Kernel that executes on the CUDA device
__global__ void bar(float *A, int N, int M){
int i = blockIdx.x * blockDim.x + threadIdx.x; //blockIdx*blockDim e blockIdx*blockDim garante que toda a matriz seja coberda por //threads
int j = blockIdx.y * blockDim.y + threadIdx.y;
if(i<N && j<M){
A(i,j) = M*i+j;}
}
void checkCUDAError(const char *msg)
{
cudaError_t err = cudaGetLastError();
if( cudaSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg,
cudaGetErrorString( err) );
exit(EXIT_FAILURE);
}
}
// main routine that executes on the host
int main( void )
{
float *a_h, *a_d;
const int N = 1000;
const int M = 10000;
int ct, dev;
cudaDevProp_t prop;
cudaGetDeviceCount(&ct);
if(ct == 0){
printf("\nNo CUDA device found.\n");
exit(0);
}
cudaGetDevice(&dev);
cudaGetDeviceProperties(&prop,dev);
dim3 bDim(16,16); //threads por bloco. Nao podem ultrapassar a capacidade da VGA
//se o Z nao for definido, fica Z=1
dim3 gDim((N/bDim.x)+( N % bDim.x == 0 ? 0 : 1 ),M/bDim.y+( M % bDim.y == 0 ? 0 : 1 )); //~numBlocks
size_t size = N * M *sizeof( float );
a_h = (float *)malloc( size ); //Tudo sera alocado da mesma forma, pois temos matriz A[N*M] mas estamos visualizando A[N][M]
cudaMalloc( (void **)&a_d, size );
cudaMemcpy( a_d, a_h, size, cudaMemcpyHostToDevice );
//checkCUDAError("memcpy");
bar<<<gDim, bDim>>>(a_d, N,M);
//cudaThreadSynchronize(); // bloqueia o device ate que a execucao do kernel tenha sido concluida. Retorna erro ou sucesso.
//checkCUDAError("kernel invocation");
cudaMemcpy( a_h, a_d, sizeof( float ) * N * M, cudaMemcpyDeviceToHost ); //recuperando resultados
//checkCUDAError("memcpy"); //checa erro ao recuperar os resultados
/*for ( int i = 0; i < N; i++ ){
printf("%d[ ", i);
for(int j = 0; j<M; ++j){
printf( "%d ",(int)a_h(i,j) );
}
puts(" ]");
puts("\n");
}*/
printf("\n\n%d\n\n", (int)a_h((N-1),(M-1)));
/*if((int)a_h((N-1),(M-1))!=(N*N-1)){
printf("\n\nKernel com erros de programacao");
exit(1);
}*/
free( a_h );
cudaFree( a_d );
//printf("\n\tPrograma sem erros CUDA...\n\n"); //se o programa chegou aqui, ele nao apresenta erros.
return 0;
} | .file "tmpxft_001aa6d8_00000000-6_second_sample_2d.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Cuda error: %s: %s.\n"
.text
.globl _Z14checkCUDAErrorPKc
.type _Z14checkCUDAErrorPKc, @function
_Z14checkCUDAErrorPKc:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movq %rbx, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z14checkCUDAErrorPKc, .-_Z14checkCUDAErrorPKc
.globl _Z24__device_stub__Z3barPfiiPfii
.type _Z24__device_stub__Z3barPfiiPfii, @function
_Z24__device_stub__Z3barPfiiPfii:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3barPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z24__device_stub__Z3barPfiiPfii, .-_Z24__device_stub__Z3barPfiiPfii
.globl _Z3barPfii
.type _Z3barPfii, @function
_Z3barPfii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3barPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z3barPfii, .-_Z3barPfii
.section .rodata.str1.1
.LC1:
.string "\nNo CUDA device found.\n"
.LC2:
.string "\n\n%d\n\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1088, %rsp
.cfi_def_cfa_offset 1104
movq %fs:40, %rax
movq %rax, 1080(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 8(%rsp)
jne .L16
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L16:
leaq 12(%rsp), %rdi
call cudaGetDevice@PLT
leaq 48(%rsp), %rdi
movl 12(%rsp), %esi
call cudaGetDeviceProperties_v2@PLT
movl $1, 32(%rsp)
movl $63, 36(%rsp)
movl $625, 40(%rsp)
movl $1, 44(%rsp)
movl $40000000, %edi
call malloc@PLT
movq %rax, %rbx
leaq 16(%rsp), %rdi
movl $40000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40000000, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 24(%rsp)
movl $16, 28(%rsp)
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L17:
movl $2, %ecx
movl $40000000, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
cvttss2sil 39999996(%rbx), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 1080(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $1088, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movl $10000, %edx
movl $1000, %esi
movq 16(%rsp), %rdi
call _Z24__device_stub__Z3barPfiiPfii
jmp .L17
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z3barPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z3barPfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // cuda_example3.cu : Defines the entry point for the console application.
//
#include <stdio.h>
#include <cuda.h>
#include <string.h>
#define A(x,y) A[M*x+y]
#define a_h(x,y) a_h[M*x+y]
typedef struct cudaDeviceProp cudaDevProp_t;
// Kernel that executes on the CUDA device
__global__ void bar(float *A, int N, int M){
int i = blockIdx.x * blockDim.x + threadIdx.x; //blockIdx*blockDim e blockIdx*blockDim garante que toda a matriz seja coberda por //threads
int j = blockIdx.y * blockDim.y + threadIdx.y;
if(i<N && j<M){
A(i,j) = M*i+j;}
}
void checkCUDAError(const char *msg)
{
cudaError_t err = cudaGetLastError();
if( cudaSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg,
cudaGetErrorString( err) );
exit(EXIT_FAILURE);
}
}
// main routine that executes on the host
int main( void )
{
float *a_h, *a_d;
const int N = 1000;
const int M = 10000;
int ct, dev;
cudaDevProp_t prop;
cudaGetDeviceCount(&ct);
if(ct == 0){
printf("\nNo CUDA device found.\n");
exit(0);
}
cudaGetDevice(&dev);
cudaGetDeviceProperties(&prop,dev);
dim3 bDim(16,16); //threads por bloco. Nao podem ultrapassar a capacidade da VGA
//se o Z nao for definido, fica Z=1
dim3 gDim((N/bDim.x)+( N % bDim.x == 0 ? 0 : 1 ),M/bDim.y+( M % bDim.y == 0 ? 0 : 1 )); //~numBlocks
size_t size = N * M *sizeof( float );
a_h = (float *)malloc( size ); //Tudo sera alocado da mesma forma, pois temos matriz A[N*M] mas estamos visualizando A[N][M]
cudaMalloc( (void **)&a_d, size );
cudaMemcpy( a_d, a_h, size, cudaMemcpyHostToDevice );
//checkCUDAError("memcpy");
bar<<<gDim, bDim>>>(a_d, N,M);
//cudaThreadSynchronize(); // bloqueia o device ate que a execucao do kernel tenha sido concluida. Retorna erro ou sucesso.
//checkCUDAError("kernel invocation");
cudaMemcpy( a_h, a_d, sizeof( float ) * N * M, cudaMemcpyDeviceToHost ); //recuperando resultados
//checkCUDAError("memcpy"); //checa erro ao recuperar os resultados
/*for ( int i = 0; i < N; i++ ){
printf("%d[ ", i);
for(int j = 0; j<M; ++j){
printf( "%d ",(int)a_h(i,j) );
}
puts(" ]");
puts("\n");
}*/
printf("\n\n%d\n\n", (int)a_h((N-1),(M-1)));
/*if((int)a_h((N-1),(M-1))!=(N*N-1)){
printf("\n\nKernel com erros de programacao");
exit(1);
}*/
free( a_h );
cudaFree( a_d );
//printf("\n\tPrograma sem erros CUDA...\n\n"); //se o programa chegou aqui, ele nao apresenta erros.
return 0;
} | // cuda_example3.cu : Defines the entry point for the console application.
//
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <string.h>
#define A(x,y) A[M*x+y]
#define a_h(x,y) a_h[M*x+y]
typedef struct hipDeviceProp_t cudaDevProp_t;
// Kernel that executes on the CUDA device
__global__ void bar(float *A, int N, int M){
int i = blockIdx.x * blockDim.x + threadIdx.x; //blockIdx*blockDim e blockIdx*blockDim garante que toda a matriz seja coberda por //threads
int j = blockIdx.y * blockDim.y + threadIdx.y;
if(i<N && j<M){
A(i,j) = M*i+j;}
}
void checkCUDAError(const char *msg)
{
hipError_t err = hipGetLastError();
if( hipSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg,
hipGetErrorString( err) );
exit(EXIT_FAILURE);
}
}
// main routine that executes on the host
int main( void )
{
float *a_h, *a_d;
const int N = 1000;
const int M = 10000;
int ct, dev;
cudaDevProp_t prop;
hipGetDeviceCount(&ct);
if(ct == 0){
printf("\nNo CUDA device found.\n");
exit(0);
}
hipGetDevice(&dev);
hipGetDeviceProperties(&prop,dev);
dim3 bDim(16,16); //threads por bloco. Nao podem ultrapassar a capacidade da VGA
//se o Z nao for definido, fica Z=1
dim3 gDim((N/bDim.x)+( N % bDim.x == 0 ? 0 : 1 ),M/bDim.y+( M % bDim.y == 0 ? 0 : 1 )); //~numBlocks
size_t size = N * M *sizeof( float );
a_h = (float *)malloc( size ); //Tudo sera alocado da mesma forma, pois temos matriz A[N*M] mas estamos visualizando A[N][M]
hipMalloc( (void **)&a_d, size );
hipMemcpy( a_d, a_h, size, hipMemcpyHostToDevice );
//checkCUDAError("memcpy");
bar<<<gDim, bDim>>>(a_d, N,M);
//cudaThreadSynchronize(); // bloqueia o device ate que a execucao do kernel tenha sido concluida. Retorna erro ou sucesso.
//checkCUDAError("kernel invocation");
hipMemcpy( a_h, a_d, sizeof( float ) * N * M, hipMemcpyDeviceToHost ); //recuperando resultados
//checkCUDAError("memcpy"); //checa erro ao recuperar os resultados
/*for ( int i = 0; i < N; i++ ){
printf("%d[ ", i);
for(int j = 0; j<M; ++j){
printf( "%d ",(int)a_h(i,j) );
}
puts(" ]");
puts("\n");
}*/
printf("\n\n%d\n\n", (int)a_h((N-1),(M-1)));
/*if((int)a_h((N-1),(M-1))!=(N*N-1)){
printf("\n\nKernel com erros de programacao");
exit(1);
}*/
free( a_h );
hipFree( a_d );
//printf("\n\tPrograma sem erros CUDA...\n\n"); //se o programa chegou aqui, ele nao apresenta erros.
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // cuda_example3.cu : Defines the entry point for the console application.
//
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <string.h>
#define A(x,y) A[M*x+y]
#define a_h(x,y) a_h[M*x+y]
typedef struct hipDeviceProp_t cudaDevProp_t;
// Kernel that executes on the CUDA device
__global__ void bar(float *A, int N, int M){
int i = blockIdx.x * blockDim.x + threadIdx.x; //blockIdx*blockDim e blockIdx*blockDim garante que toda a matriz seja coberda por //threads
int j = blockIdx.y * blockDim.y + threadIdx.y;
if(i<N && j<M){
A(i,j) = M*i+j;}
}
void checkCUDAError(const char *msg)
{
hipError_t err = hipGetLastError();
if( hipSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg,
hipGetErrorString( err) );
exit(EXIT_FAILURE);
}
}
// main routine that executes on the host
int main( void )
{
float *a_h, *a_d;
const int N = 1000;
const int M = 10000;
int ct, dev;
cudaDevProp_t prop;
hipGetDeviceCount(&ct);
if(ct == 0){
printf("\nNo CUDA device found.\n");
exit(0);
}
hipGetDevice(&dev);
hipGetDeviceProperties(&prop,dev);
dim3 bDim(16,16); //threads por bloco. Nao podem ultrapassar a capacidade da VGA
//se o Z nao for definido, fica Z=1
dim3 gDim((N/bDim.x)+( N % bDim.x == 0 ? 0 : 1 ),M/bDim.y+( M % bDim.y == 0 ? 0 : 1 )); //~numBlocks
size_t size = N * M *sizeof( float );
a_h = (float *)malloc( size ); //Tudo sera alocado da mesma forma, pois temos matriz A[N*M] mas estamos visualizando A[N][M]
hipMalloc( (void **)&a_d, size );
hipMemcpy( a_d, a_h, size, hipMemcpyHostToDevice );
//checkCUDAError("memcpy");
bar<<<gDim, bDim>>>(a_d, N,M);
//cudaThreadSynchronize(); // bloqueia o device ate que a execucao do kernel tenha sido concluida. Retorna erro ou sucesso.
//checkCUDAError("kernel invocation");
hipMemcpy( a_h, a_d, sizeof( float ) * N * M, hipMemcpyDeviceToHost ); //recuperando resultados
//checkCUDAError("memcpy"); //checa erro ao recuperar os resultados
/*for ( int i = 0; i < N; i++ ){
printf("%d[ ", i);
for(int j = 0; j<M; ++j){
printf( "%d ",(int)a_h(i,j) );
}
puts(" ]");
puts("\n");
}*/
printf("\n\n%d\n\n", (int)a_h((N-1),(M-1)));
/*if((int)a_h((N-1),(M-1))!=(N*N-1)){
printf("\n\nKernel com erros de programacao");
exit(1);
}*/
free( a_h );
hipFree( a_d );
//printf("\n\tPrograma sem erros CUDA...\n\n"); //se o programa chegou aqui, ele nao apresenta erros.
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3barPfii
.globl _Z3barPfii
.p2align 8
.type _Z3barPfii,@function
_Z3barPfii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_cvt_f32_i32_e32 v2, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3barPfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3barPfii, .Lfunc_end0-_Z3barPfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3barPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3barPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // cuda_example3.cu : Defines the entry point for the console application.
//
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <string.h>
#define A(x,y) A[M*x+y]
#define a_h(x,y) a_h[M*x+y]
typedef struct hipDeviceProp_t cudaDevProp_t;
// Kernel that executes on the CUDA device
__global__ void bar(float *A, int N, int M){
int i = blockIdx.x * blockDim.x + threadIdx.x; //blockIdx*blockDim e blockIdx*blockDim garante que toda a matriz seja coberda por //threads
int j = blockIdx.y * blockDim.y + threadIdx.y;
if(i<N && j<M){
A(i,j) = M*i+j;}
}
void checkCUDAError(const char *msg)
{
hipError_t err = hipGetLastError();
if( hipSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg,
hipGetErrorString( err) );
exit(EXIT_FAILURE);
}
}
// main routine that executes on the host
int main( void )
{
float *a_h, *a_d;
const int N = 1000;
const int M = 10000;
int ct, dev;
cudaDevProp_t prop;
hipGetDeviceCount(&ct);
if(ct == 0){
printf("\nNo CUDA device found.\n");
exit(0);
}
hipGetDevice(&dev);
hipGetDeviceProperties(&prop,dev);
dim3 bDim(16,16); //threads por bloco. Nao podem ultrapassar a capacidade da VGA
//se o Z nao for definido, fica Z=1
dim3 gDim((N/bDim.x)+( N % bDim.x == 0 ? 0 : 1 ),M/bDim.y+( M % bDim.y == 0 ? 0 : 1 )); //~numBlocks
size_t size = N * M *sizeof( float );
a_h = (float *)malloc( size ); //Tudo sera alocado da mesma forma, pois temos matriz A[N*M] mas estamos visualizando A[N][M]
hipMalloc( (void **)&a_d, size );
hipMemcpy( a_d, a_h, size, hipMemcpyHostToDevice );
//checkCUDAError("memcpy");
bar<<<gDim, bDim>>>(a_d, N,M);
//cudaThreadSynchronize(); // bloqueia o device ate que a execucao do kernel tenha sido concluida. Retorna erro ou sucesso.
//checkCUDAError("kernel invocation");
hipMemcpy( a_h, a_d, sizeof( float ) * N * M, hipMemcpyDeviceToHost ); //recuperando resultados
//checkCUDAError("memcpy"); //checa erro ao recuperar os resultados
/*for ( int i = 0; i < N; i++ ){
printf("%d[ ", i);
for(int j = 0; j<M; ++j){
printf( "%d ",(int)a_h(i,j) );
}
puts(" ]");
puts("\n");
}*/
printf("\n\n%d\n\n", (int)a_h((N-1),(M-1)));
/*if((int)a_h((N-1),(M-1))!=(N*N-1)){
printf("\n\nKernel com erros de programacao");
exit(1);
}*/
free( a_h );
hipFree( a_d );
//printf("\n\tPrograma sem erros CUDA...\n\n"); //se o programa chegou aqui, ele nao apresenta erros.
return 0;
} | .text
.file "second_sample_2d.hip"
.globl _Z18__device_stub__barPfii # -- Begin function _Z18__device_stub__barPfii
.p2align 4, 0x90
.type _Z18__device_stub__barPfii,@function
_Z18__device_stub__barPfii: # @_Z18__device_stub__barPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3barPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__barPfii, .Lfunc_end0-_Z18__device_stub__barPfii
.cfi_endproc
# -- End function
.globl _Z14checkCUDAErrorPKc # -- Begin function _Z14checkCUDAErrorPKc
.p2align 4, 0x90
.type _Z14checkCUDAErrorPKc,@function
_Z14checkCUDAErrorPKc: # @_Z14checkCUDAErrorPKc
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB1_2
# %bb.1:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_2:
.cfi_def_cfa_offset 32
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movq %r14, %rdi
movq %rbx, %rdx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z14checkCUDAErrorPKc, .Lfunc_end1-_Z14checkCUDAErrorPKc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1584, %rsp # imm = 0x630
.cfi_def_cfa_offset 1600
.cfi_offset %rbx, -16
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 12(%rsp)
je .LBB2_4
# %bb.1:
leaq 8(%rsp), %rdi
callq hipGetDevice
movl 8(%rsp), %esi
leaq 112(%rsp), %rdi
callq hipGetDevicePropertiesR0600
movl $40000000, %edi # imm = 0x2625A00
callq malloc
movq %rax, %rbx
movq %rsp, %rdi
movl $40000000, %esi # imm = 0x2625A00
callq hipMalloc
movq (%rsp), %rdi
movl $40000000, %edx # imm = 0x2625A00
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $2684354560063, %rdi # imm = 0x2710000003F
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_3
# %bb.2:
movq (%rsp), %rax
movq %rax, 72(%rsp)
movl $1000, 20(%rsp) # imm = 0x3E8
movl $10000, 16(%rsp) # imm = 0x2710
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3barPfii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_3:
movq (%rsp), %rsi
movl $40000000, %edx # imm = 0x2625A00
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
cvttss2si 39999996(%rbx), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $1584, %rsp # imm = 0x630
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB2_4:
.cfi_def_cfa_offset 1600
movl $.Lstr, %edi
callq puts@PLT
xorl %edi, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3barPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3barPfii,@object # @_Z3barPfii
.section .rodata,"a",@progbits
.globl _Z3barPfii
.p2align 3, 0x0
_Z3barPfii:
.quad _Z18__device_stub__barPfii
.size _Z3barPfii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Cuda error: %s: %s.\n"
.size .L.str, 21
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n\n%d\n\n"
.size .L.str.2, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3barPfii"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nNo CUDA device found."
.size .Lstr, 23
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__barPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3barPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3barPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x16c], PT ; /* 0x00005b0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x168], P0 ; /* 0x00005a0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R0, R0, c[0x0][0x16c], R3 ; /* 0x00005b0000007a24 */
/* 0x000fe200078e0203 */
/*00b0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00d0*/ I2F R5, R0 ; /* 0x0000000000057306 */
/* 0x000e2e0000201400 */
/*00e0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3barPfii
.globl _Z3barPfii
.p2align 8
.type _Z3barPfii,@function
_Z3barPfii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_cvt_f32_i32_e32 v2, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3barPfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3barPfii, .Lfunc_end0-_Z3barPfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3barPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3barPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001aa6d8_00000000-6_second_sample_2d.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Cuda error: %s: %s.\n"
.text
.globl _Z14checkCUDAErrorPKc
.type _Z14checkCUDAErrorPKc, @function
_Z14checkCUDAErrorPKc:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movq %rbx, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z14checkCUDAErrorPKc, .-_Z14checkCUDAErrorPKc
.globl _Z24__device_stub__Z3barPfiiPfii
.type _Z24__device_stub__Z3barPfiiPfii, @function
_Z24__device_stub__Z3barPfiiPfii:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3barPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z24__device_stub__Z3barPfiiPfii, .-_Z24__device_stub__Z3barPfiiPfii
.globl _Z3barPfii
.type _Z3barPfii, @function
_Z3barPfii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3barPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z3barPfii, .-_Z3barPfii
.section .rodata.str1.1
.LC1:
.string "\nNo CUDA device found.\n"
.LC2:
.string "\n\n%d\n\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1088, %rsp
.cfi_def_cfa_offset 1104
movq %fs:40, %rax
movq %rax, 1080(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 8(%rsp)
jne .L16
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L16:
leaq 12(%rsp), %rdi
call cudaGetDevice@PLT
leaq 48(%rsp), %rdi
movl 12(%rsp), %esi
call cudaGetDeviceProperties_v2@PLT
movl $1, 32(%rsp)
movl $63, 36(%rsp)
movl $625, 40(%rsp)
movl $1, 44(%rsp)
movl $40000000, %edi
call malloc@PLT
movq %rax, %rbx
leaq 16(%rsp), %rdi
movl $40000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40000000, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 24(%rsp)
movl $16, 28(%rsp)
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L17:
movl $2, %ecx
movl $40000000, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
cvttss2sil 39999996(%rbx), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 1080(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $1088, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movl $10000, %edx
movl $1000, %esi
movq 16(%rsp), %rdi
call _Z24__device_stub__Z3barPfiiPfii
jmp .L17
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z3barPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z3barPfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "second_sample_2d.hip"
.globl _Z18__device_stub__barPfii # -- Begin function _Z18__device_stub__barPfii
.p2align 4, 0x90
.type _Z18__device_stub__barPfii,@function
_Z18__device_stub__barPfii: # @_Z18__device_stub__barPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3barPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__barPfii, .Lfunc_end0-_Z18__device_stub__barPfii
.cfi_endproc
# -- End function
.globl _Z14checkCUDAErrorPKc # -- Begin function _Z14checkCUDAErrorPKc
.p2align 4, 0x90
.type _Z14checkCUDAErrorPKc,@function
_Z14checkCUDAErrorPKc: # @_Z14checkCUDAErrorPKc
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB1_2
# %bb.1:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_2:
.cfi_def_cfa_offset 32
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movq %r14, %rdi
movq %rbx, %rdx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z14checkCUDAErrorPKc, .Lfunc_end1-_Z14checkCUDAErrorPKc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1584, %rsp # imm = 0x630
.cfi_def_cfa_offset 1600
.cfi_offset %rbx, -16
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 12(%rsp)
je .LBB2_4
# %bb.1:
leaq 8(%rsp), %rdi
callq hipGetDevice
movl 8(%rsp), %esi
leaq 112(%rsp), %rdi
callq hipGetDevicePropertiesR0600
movl $40000000, %edi # imm = 0x2625A00
callq malloc
movq %rax, %rbx
movq %rsp, %rdi
movl $40000000, %esi # imm = 0x2625A00
callq hipMalloc
movq (%rsp), %rdi
movl $40000000, %edx # imm = 0x2625A00
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $2684354560063, %rdi # imm = 0x2710000003F
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_3
# %bb.2:
movq (%rsp), %rax
movq %rax, 72(%rsp)
movl $1000, 20(%rsp) # imm = 0x3E8
movl $10000, 16(%rsp) # imm = 0x2710
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3barPfii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_3:
movq (%rsp), %rsi
movl $40000000, %edx # imm = 0x2625A00
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
cvttss2si 39999996(%rbx), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $1584, %rsp # imm = 0x630
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB2_4:
.cfi_def_cfa_offset 1600
movl $.Lstr, %edi
callq puts@PLT
xorl %edi, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3barPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3barPfii,@object # @_Z3barPfii
.section .rodata,"a",@progbits
.globl _Z3barPfii
.p2align 3, 0x0
_Z3barPfii:
.quad _Z18__device_stub__barPfii
.size _Z3barPfii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Cuda error: %s: %s.\n"
.size .L.str, 21
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n\n%d\n\n"
.size .L.str.2, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3barPfii"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nNo CUDA device found."
.size .Lstr, 23
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__barPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3barPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
__global__ void average_snips(const double *Params, const int *iC, const int *call, const int *id, const float *uproj, const float *cmax, float *WU){
int my_chan, this_chan, tidx, tidy, bid, ind, Nspikes, NrankPC, NchanNear, Nchan;
float xsum = 0.0f;
Nspikes = (int) Params[0];
NrankPC = (int) Params[1];
Nchan = (int) Params[7];
NchanNear = (int) Params[6];
tidx = threadIdx.x;
tidy = threadIdx.y;
bid = blockIdx.x;
for(ind=0; ind<Nspikes;ind++)
if (id[ind]==bid){
my_chan = call[ind];
this_chan = iC[tidy + NchanNear * my_chan];
xsum = uproj[tidx + NrankPC*tidy + NrankPC*NchanNear * ind];
WU[tidx + NrankPC*this_chan + NrankPC*Nchan * bid] += xsum;
}
} | code for sm_80
Function : _Z13average_snipsPKdPKiS2_S2_PKfS4_Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R6, c[0x0][0x160] ; /* 0x0000580000067a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R7, c[0x0][0x164] ; /* 0x0000590000077a02 */
/* 0x000fca0000000f00 */
/*0040*/ LDG.E.64 R2, [R6.64] ; /* 0x0000000a06027981 */
/* 0x000ea4000c1e1b00 */
/*0050*/ F2I.F64.TRUNC R15, R2 ; /* 0x00000002000f7311 */
/* 0x004e24000030d100 */
/*0060*/ ISETP.GE.AND P0, PT, R15, 0x1, PT ; /* 0x000000010f00780c */
/* 0x001fda0003f06270 */
/*0070*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0080*/ LDG.E.64 R12, [R6.64+0x38] ; /* 0x0000380a060c7981 */
/* 0x000ea8000c1e1b00 */
/*0090*/ LDG.E.64 R8, [R6.64+0x8] ; /* 0x0000080a06087981 */
/* 0x000ee8000c1e1b00 */
/*00a0*/ LDG.E.64 R10, [R6.64+0x30] ; /* 0x0000300a060a7981 */
/* 0x000f22000c1e1b00 */
/*00b0*/ S2UR UR12, SR_CTAID.X ; /* 0x00000000000c79c3 */
/* 0x000e220000002500 */
/*00c0*/ IADD3 R3, R15.reuse, -0x1, RZ ; /* 0xffffffff0f037810 */
/* 0x040fe20007ffe0ff */
/*00d0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00e0*/ S2R R4, SR_TID.Y ; /* 0x0000000000047919 */
/* 0x000e620000002200 */
/*00f0*/ LOP3.LUT R2, R15, 0x3, RZ, 0xc0, !PT ; /* 0x000000030f027812 */
/* 0x000fc400078ec0ff */
/*0100*/ ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe20003f26070 */
/*0110*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0120*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0130*/ F2I.F64.TRUNC R12, R12 ; /* 0x0000000c000c7311 */
/* 0x004e30000030d100 */
/*0140*/ F2I.F64.TRUNC R0, R8 ; /* 0x0000000800007311 */
/* 0x0084f0000030d100 */
/*0150*/ F2I.F64.TRUNC R3, R10 ; /* 0x0000000a00037311 */
/* 0x010522000030d100 */
/*0160*/ IMAD R6, R12, UR12, RZ ; /* 0x0000000c0c067c24 */
/* 0x001fe2000f8e02ff */
/*0170*/ @!P1 BRA 0x6e0 ; /* 0x0000056000009947 */
/* 0x000fec0003800000 */
/*0180*/ LEA R23, R3.reuse, R4.reuse, 0x1 ; /* 0x0000000403177211 */
/* 0x0d2fe200078e08ff */
/*0190*/ IMAD R11, R3.reuse, 0x3, R4 ; /* 0x00000003030b7824 */
/* 0x044fe200078e0204 */
/*01a0*/ IADD3 R9, R3, R4, RZ ; /* 0x0000000403097210 */
/* 0x000fe20007ffe0ff */
/*01b0*/ IMAD R8, R0.reuse, R3, RZ ; /* 0x0000000300087224 */
/* 0x048fe200078e02ff */
/*01c0*/ IADD3 R7, -R15, R2, RZ ; /* 0x000000020f077210 */
/* 0x000fe20007ffe1ff */
/*01d0*/ IMAD R21, R0.reuse, R4, R5.reuse ; /* 0x0000000400157224 */
/* 0x140fe200078e0205 */
/*01e0*/ MOV R14, c[0x0][0x170] ; /* 0x00005c00000e7a02 */
/* 0x000fe20000000f00 */
/*01f0*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff0d7624 */
/* 0x000fe200078e00ff */
/*0200*/ MOV R15, c[0x0][0x174] ; /* 0x00005d00000f7a02 */
/* 0x000fe20000000f00 */
/*0210*/ IMAD R11, R0.reuse, R11, R5.reuse ; /* 0x0000000b000b7224 */
/* 0x140fe200078e0205 */
/*0220*/ MOV R12, c[0x0][0x178] ; /* 0x00005e00000c7a02 */
/* 0x000fe20000000f00 */
/*0230*/ IMAD R23, R0.reuse, R23, R5.reuse ; /* 0x0000001700177224 */
/* 0x140fe200078e0205 */
/*0240*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0250*/ IMAD R9, R0, R9, R5 ; /* 0x0000000900097224 */
/* 0x000fc400078e0205 */
/*0260*/ LDG.E R10, [R12.64] ; /* 0x0000000a0c0a7981 */
/* 0x000ea4000c1e1900 */
/*0270*/ ISETP.NE.AND P1, PT, R10, UR12, PT ; /* 0x0000000c0a007c0c */
/* 0x004fda000bf25270 */
/*0280*/ @!P1 LDG.E R10, [R14.64] ; /* 0x0000000a0e0a9981 */
/* 0x000ea2000c1e1900 */
/*0290*/ @!P1 MOV R19, 0x4 ; /* 0x0000000400139802 */
/* 0x000fe20000000f00 */
/*02a0*/ @!P1 IMAD R10, R3, R10, R4 ; /* 0x0000000a030a9224 */
/* 0x004fc800078e0204 */
/*02b0*/ @!P1 IMAD.WIDE R24, R10, R19, c[0x0][0x168] ; /* 0x00005a000a189625 */
/* 0x000fcc00078e0213 */
/*02c0*/ @!P1 LDG.E R25, [R24.64] ; /* 0x0000000a18199981 */
/* 0x000ea2000c1e1900 */
/*02d0*/ @!P1 IMAD.WIDE R16, R21, R19, c[0x0][0x180] ; /* 0x0000600015109625 */
/* 0x000fcc00078e0213 */
/*02e0*/ @!P1 LDG.E R17, [R16.64] ; /* 0x0000000a10119981 */
/* 0x000ee2000c1e1900 */
/*02f0*/ @!P1 IADD3 R10, R6, R25, RZ ; /* 0x00000019060a9210 */
/* 0x004fca0007ffe0ff */
/*0300*/ @!P1 IMAD R10, R0, R10, R5 ; /* 0x0000000a000a9224 */
/* 0x000fc800078e0205 */
/*0310*/ @!P1 IMAD.WIDE R18, R10, R19, c[0x0][0x190] ; /* 0x000064000a129625 */
/* 0x000fca00078e0213 */
/*0320*/ @!P1 LDG.E R10, [R18.64] ; /* 0x0000000a120a9981 */
/* 0x000ee4000c1e1900 */
/*0330*/ @!P1 FADD R27, R10, R17 ; /* 0x000000110a1b9221 */
/* 0x008fca0000000000 */
/*0340*/ @!P1 STG.E [R18.64], R27 ; /* 0x0000001b12009986 */
/* 0x0001e8000c10190a */
/*0350*/ LDG.E R10, [R12.64+0x4] ; /* 0x0000040a0c0a7981 */
/* 0x000ea4000c1e1900 */
/*0360*/ ISETP.NE.AND P1, PT, R10, UR12, PT ; /* 0x0000000c0a007c0c */
/* 0x004fda000bf25270 */
/*0370*/ @!P1 LDG.E R10, [R14.64+0x4] ; /* 0x0000040a0e0a9981 */
/* 0x000ea2000c1e1900 */
/*0380*/ @!P1 MOV R29, 0x4 ; /* 0x00000004001d9802 */
/* 0x000fe20000000f00 */
/*0390*/ @!P1 IMAD R10, R3, R10, R4 ; /* 0x0000000a030a9224 */
/* 0x004fc800078e0204 */
/*03a0*/ @!P1 IMAD.WIDE R24, R10, R29, c[0x0][0x168] ; /* 0x00005a000a189625 */
/* 0x000fcc00078e021d */
/*03b0*/ @!P1 LDG.E R25, [R24.64] ; /* 0x0000000a18199981 */
/* 0x000ea2000c1e1900 */
/*03c0*/ @!P1 IMAD.WIDE R16, R9, R29, c[0x0][0x180] ; /* 0x0000600009109625 */
/* 0x000fcc00078e021d */
/*03d0*/ @!P1 LDG.E R17, [R16.64] ; /* 0x0000000a10119981 */
/* 0x000ee2000c1e1900 */
/*03e0*/ @!P1 IADD3 R10, R6, R25, RZ ; /* 0x00000019060a9210 */
/* 0x004fca0007ffe0ff */
/*03f0*/ @!P1 IMAD R10, R0, R10, R5 ; /* 0x0000000a000a9224 */
/* 0x000fc800078e0205 */
/*0400*/ @!P1 IMAD.WIDE R18, R10, R29, c[0x0][0x190] ; /* 0x000064000a129625 */
/* 0x001fca00078e021d */
/*0410*/ @!P1 LDG.E R10, [R18.64] ; /* 0x0000000a120a9981 */
/* 0x000ee4000c1e1900 */
/*0420*/ @!P1 FADD R27, R10, R17 ; /* 0x000000110a1b9221 */
/* 0x008fca0000000000 */
/*0430*/ @!P1 STG.E [R18.64], R27 ; /* 0x0000001b12009986 */
/* 0x0001e8000c10190a */
/*0440*/ LDG.E R10, [R12.64+0x8] ; /* 0x0000080a0c0a7981 */
/* 0x000ea4000c1e1900 */
/*0450*/ ISETP.NE.AND P1, PT, R10, UR12, PT ; /* 0x0000000c0a007c0c */
/* 0x004fda000bf25270 */
/*0460*/ @!P1 LDG.E R10, [R14.64+0x8] ; /* 0x0000080a0e0a9981 */
/* 0x000ea2000c1e1900 */
/*0470*/ @!P1 MOV R29, 0x4 ; /* 0x00000004001d9802 */
/* 0x000fe20000000f00 */
/*0480*/ @!P1 IMAD R10, R3, R10, R4 ; /* 0x0000000a030a9224 */
/* 0x004fc800078e0204 */
/*0490*/ @!P1 IMAD.WIDE R24, R10, R29, c[0x0][0x168] ; /* 0x00005a000a189625 */
/* 0x000fcc00078e021d */
/*04a0*/ @!P1 LDG.E R25, [R24.64] ; /* 0x0000000a18199981 */
/* 0x000ea2000c1e1900 */
/*04b0*/ @!P1 IMAD.WIDE R16, R23, R29, c[0x0][0x180] ; /* 0x0000600017109625 */
/* 0x000fcc00078e021d */
/*04c0*/ @!P1 LDG.E R17, [R16.64] ; /* 0x0000000a10119981 */
/* 0x000ee2000c1e1900 */
/*04d0*/ @!P1 IADD3 R10, R6, R25, RZ ; /* 0x00000019060a9210 */
/* 0x004fca0007ffe0ff */
/*04e0*/ @!P1 IMAD R10, R0, R10, R5 ; /* 0x0000000a000a9224 */
/* 0x000fc800078e0205 */
/*04f0*/ @!P1 IMAD.WIDE R18, R10, R29, c[0x0][0x190] ; /* 0x000064000a129625 */
/* 0x001fca00078e021d */
/*0500*/ @!P1 LDG.E R10, [R18.64] ; /* 0x0000000a120a9981 */
/* 0x000ee4000c1e1900 */
/*0510*/ @!P1 FADD R27, R10, R17 ; /* 0x000000110a1b9221 */
/* 0x008fca0000000000 */
/*0520*/ @!P1 STG.E [R18.64], R27 ; /* 0x0000001b12009986 */
/* 0x0001e8000c10190a */
/*0530*/ LDG.E R10, [R12.64+0xc] ; /* 0x00000c0a0c0a7981 */
/* 0x000ea4000c1e1900 */
/*0540*/ ISETP.NE.AND P1, PT, R10, UR12, PT ; /* 0x0000000c0a007c0c */
/* 0x004fda000bf25270 */
/*0550*/ @!P1 LDG.E R10, [R14.64+0xc] ; /* 0x00000c0a0e0a9981 */
/* 0x000ea2000c1e1900 */
/*0560*/ @!P1 IMAD.MOV.U32 R29, RZ, RZ, 0x4 ; /* 0x00000004ff1d9424 */
/* 0x000fe400078e00ff */
/*0570*/ @!P1 IMAD R10, R3, R10, R4 ; /* 0x0000000a030a9224 */
/* 0x004fc800078e0204 */
/*0580*/ @!P1 IMAD.WIDE R24, R10, R29, c[0x0][0x168] ; /* 0x00005a000a189625 */
/* 0x000fcc00078e021d */
/*0590*/ @!P1 LDG.E R25, [R24.64] ; /* 0x0000000a18199981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ @!P1 IMAD.WIDE R16, R11, R29, c[0x0][0x180] ; /* 0x000060000b109625 */
/* 0x000fcc00078e021d */
/*05b0*/ @!P1 LDG.E R17, [R16.64] ; /* 0x0000000a10119981 */
/* 0x000ee2000c1e1900 */
/*05c0*/ @!P1 IADD3 R10, R6, R25, RZ ; /* 0x00000019060a9210 */
/* 0x004fca0007ffe0ff */
/*05d0*/ @!P1 IMAD R10, R0, R10, R5 ; /* 0x0000000a000a9224 */
/* 0x000fc800078e0205 */
/*05e0*/ @!P1 IMAD.WIDE R18, R10, R29, c[0x0][0x190] ; /* 0x000064000a129625 */
/* 0x001fca00078e021d */
/*05f0*/ @!P1 LDG.E R10, [R18.64] ; /* 0x0000000a120a9981 */
/* 0x000ee2000c1e1900 */
/*0600*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0610*/ IADD3 R12, P2, R12, 0x10, RZ ; /* 0x000000100c0c7810 */
/* 0x000fe40007f5e0ff */
/*0620*/ IADD3 R14, P3, R14, 0x10, RZ ; /* 0x000000100e0e7810 */
/* 0x000fe20007f7e0ff */
/*0630*/ IMAD R11, R8.reuse, 0x4, R11 ; /* 0x00000004080b7824 */
/* 0x040fe200078e020b */
/*0640*/ IADD3.X R13, RZ, R13, RZ, P2, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe400017fe4ff */
/*0650*/ IADD3.X R15, RZ, R15, RZ, P3, !PT ; /* 0x0000000fff0f7210 */
/* 0x000fe40001ffe4ff */
/*0660*/ LEA R21, R8, R21, 0x2 ; /* 0x0000001508157211 */
/* 0x000fc400078e10ff */
/*0670*/ LEA R9, R8.reuse, R9, 0x2 ; /* 0x0000000908097211 */
/* 0x040fe400078e10ff */
/*0680*/ LEA R23, R8, R23, 0x2 ; /* 0x0000001708177211 */
/* 0x000fe200078e10ff */
/*0690*/ @!P1 FADD R27, R10, R17 ; /* 0x000000110a1b9221 */
/* 0x008fe20000000000 */
/*06a0*/ IADD3 R10, R7, UR4, RZ ; /* 0x00000004070a7c10 */
/* 0x000fc8000fffe0ff */
/*06b0*/ @!P1 STG.E [R18.64], R27 ; /* 0x0000001b12009986 */
/* 0x0001e2000c10190a */
/*06c0*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f25270 */
/*06d0*/ @P1 BRA 0x260 ; /* 0xfffffb8000001947 */
/* 0x001fea000383ffff */
/*06e0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x002fea0003800000 */
/*06f0*/ IMAD R7, R3, UR4, R4 ; /* 0x0000000403077c24 */
/* 0x010fe2000f8e0204 */
/*0700*/ UMOV UR5, 0x4 ; /* 0x0000000400057882 */
/* 0x000fe20000000000 */
/*0710*/ IMAD R18, R0.reuse, R3, RZ ; /* 0x0000000300127224 */
/* 0x048fe200078e02ff */
/*0720*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe20000000a00 */
/*0730*/ IMAD R7, R0, R7, R5 ; /* 0x0000000700077224 */
/* 0x000fe200078e0205 */
/*0740*/ ULDC.64 UR8, c[0x0][0x178] ; /* 0x00005e0000087ab9 */
/* 0x000fe40000000a00 */
/*0750*/ UIMAD.WIDE UR6, UR4, UR5, UR6 ; /* 0x00000005040672a5 */
/* 0x000fe4000f8e0206 */
/*0760*/ UIMAD.WIDE UR8, UR4, UR5, UR8 ; /* 0x00000005040872a5 */
/* 0x000fcc000f8e0208 */
/*0770*/ MOV R10, UR8 ; /* 0x00000008000a7c02 */
/* 0x004fe40008000f00 */
/*0780*/ MOV R11, UR9 ; /* 0x00000009000b7c02 */
/* 0x000fca0008000f00 */
/*0790*/ LDG.E R10, [R10.64] ; /* 0x0000000a0a0a7981 */
/* 0x000ea2000c1e1900 */
/*07a0*/ MOV R14, UR6 ; /* 0x00000006000e7c02 */
/* 0x000fe40008000f00 */
/*07b0*/ MOV R15, UR7 ; /* 0x00000007000f7c02 */
/* 0x000fe40008000f00 */
/*07c0*/ ISETP.NE.AND P0, PT, R10, UR12, PT ; /* 0x0000000c0a007c0c */
/* 0x004fda000bf05270 */
/*07d0*/ @!P0 LDG.E R14, [R14.64] ; /* 0x0000000a0e0e8981 */
/* 0x000ea2000c1e1900 */
/*07e0*/ @!P0 MOV R13, 0x4 ; /* 0x00000004000d8802 */
/* 0x000fe20000000f00 */
/*07f0*/ @!P0 IMAD R8, R3, R14, R4 ; /* 0x0000000e03088224 */
/* 0x004fc800078e0204 */
/*0800*/ @!P0 IMAD.WIDE R8, R8, R13, c[0x0][0x168] ; /* 0x00005a0008088625 */
/* 0x000fcc00078e020d */
/*0810*/ @!P0 LDG.E R9, [R8.64] ; /* 0x0000000a08098981 */
/* 0x000ea2000c1e1900 */
/*0820*/ @!P0 IMAD.WIDE R10, R7, R13, c[0x0][0x180] ; /* 0x00006000070a8625 */
/* 0x000fcc00078e020d */
/*0830*/ @!P0 LDG.E R11, [R10.64] ; /* 0x0000000a0a0b8981 */
/* 0x000ee2000c1e1900 */
/*0840*/ @!P0 IADD3 R12, R6, R9, RZ ; /* 0x00000009060c8210 */
/* 0x004fca0007ffe0ff */
/*0850*/ @!P0 IMAD R12, R0, R12, R5 ; /* 0x0000000c000c8224 */
/* 0x000fc800078e0205 */
/*0860*/ @!P0 IMAD.WIDE R12, R12, R13, c[0x0][0x190] ; /* 0x000064000c0c8625 */
/* 0x000fca00078e020d */
/*0870*/ @!P0 LDG.E R16, [R12.64] ; /* 0x0000000a0c108981 */
/* 0x000ee2000c1e1900 */
/*0880*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe20007ffe0ff */
/*0890*/ UIADD3 UR8, UP1, UR8, 0x4, URZ ; /* 0x0000000408087890 */
/* 0x000fe4000ff3e03f */
/*08a0*/ UIADD3 UR6, UP0, UR6, 0x4, URZ ; /* 0x0000000406067890 */
/* 0x000fe4000ff1e03f */
/*08b0*/ UIADD3.X UR9, URZ, UR9, URZ, UP1, !UPT ; /* 0x000000093f097290 */
/* 0x000fe40008ffe43f */
/*08c0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08d0*/ IADD3 R7, R18, R7, RZ ; /* 0x0000000712077210 */
/* 0x000fe20007ffe0ff */
/*08e0*/ @!P0 FADD R15, R16, R11 ; /* 0x0000000b100f8221 */
/* 0x008fca0000000000 */
/*08f0*/ @!P0 STG.E [R12.64], R15 ; /* 0x0000000f0c008986 */
/* 0x0001e2000c10190a */
/*0900*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*0910*/ @P0 BRA 0x770 ; /* 0xfffffe5000000947 */
/* 0x001fea000383ffff */
/*0920*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0930*/ BRA 0x930; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
__global__ void average_snips(const double *Params, const int *iC, const int *call, const int *id, const float *uproj, const float *cmax, float *WU){
int my_chan, this_chan, tidx, tidy, bid, ind, Nspikes, NrankPC, NchanNear, Nchan;
float xsum = 0.0f;
Nspikes = (int) Params[0];
NrankPC = (int) Params[1];
Nchan = (int) Params[7];
NchanNear = (int) Params[6];
tidx = threadIdx.x;
tidy = threadIdx.y;
bid = blockIdx.x;
for(ind=0; ind<Nspikes;ind++)
if (id[ind]==bid){
my_chan = call[ind];
this_chan = iC[tidy + NchanNear * my_chan];
xsum = uproj[tidx + NrankPC*tidy + NrankPC*NchanNear * ind];
WU[tidx + NrankPC*this_chan + NrankPC*Nchan * bid] += xsum;
}
} | .file "tmpxft_0007cdee_00000000-6_average_snips.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z13average_snipsPKdPKiS2_S2_PKfS4_PfPKdPKiS2_S2_PKfS4_Pf
.type _Z51__device_stub__Z13average_snipsPKdPKiS2_S2_PKfS4_PfPKdPKiS2_S2_PKfS4_Pf, @function
_Z51__device_stub__Z13average_snipsPKdPKiS2_S2_PKfS4_PfPKdPKiS2_S2_PKfS4_Pf:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z13average_snipsPKdPKiS2_S2_PKfS4_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z51__device_stub__Z13average_snipsPKdPKiS2_S2_PKfS4_PfPKdPKiS2_S2_PKfS4_Pf, .-_Z51__device_stub__Z13average_snipsPKdPKiS2_S2_PKfS4_PfPKdPKiS2_S2_PKfS4_Pf
.globl _Z13average_snipsPKdPKiS2_S2_PKfS4_Pf
.type _Z13average_snipsPKdPKiS2_S2_PKfS4_Pf, @function
_Z13average_snipsPKdPKiS2_S2_PKfS4_Pf:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z51__device_stub__Z13average_snipsPKdPKiS2_S2_PKfS4_PfPKdPKiS2_S2_PKfS4_Pf
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13average_snipsPKdPKiS2_S2_PKfS4_Pf, .-_Z13average_snipsPKdPKiS2_S2_PKfS4_Pf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z13average_snipsPKdPKiS2_S2_PKfS4_Pf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13average_snipsPKdPKiS2_S2_PKfS4_Pf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
__global__ void average_snips(const double *Params, const int *iC, const int *call, const int *id, const float *uproj, const float *cmax, float *WU){
int my_chan, this_chan, tidx, tidy, bid, ind, Nspikes, NrankPC, NchanNear, Nchan;
float xsum = 0.0f;
Nspikes = (int) Params[0];
NrankPC = (int) Params[1];
Nchan = (int) Params[7];
NchanNear = (int) Params[6];
tidx = threadIdx.x;
tidy = threadIdx.y;
bid = blockIdx.x;
for(ind=0; ind<Nspikes;ind++)
if (id[ind]==bid){
my_chan = call[ind];
this_chan = iC[tidy + NchanNear * my_chan];
xsum = uproj[tidx + NrankPC*tidy + NrankPC*NchanNear * ind];
WU[tidx + NrankPC*this_chan + NrankPC*Nchan * bid] += xsum;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
__global__ void average_snips(const double *Params, const int *iC, const int *call, const int *id, const float *uproj, const float *cmax, float *WU){
int my_chan, this_chan, tidx, tidy, bid, ind, Nspikes, NrankPC, NchanNear, Nchan;
float xsum = 0.0f;
Nspikes = (int) Params[0];
NrankPC = (int) Params[1];
Nchan = (int) Params[7];
NchanNear = (int) Params[6];
tidx = threadIdx.x;
tidy = threadIdx.y;
bid = blockIdx.x;
for(ind=0; ind<Nspikes;ind++)
if (id[ind]==bid){
my_chan = call[ind];
this_chan = iC[tidy + NchanNear * my_chan];
xsum = uproj[tidx + NrankPC*tidy + NrankPC*NchanNear * ind];
WU[tidx + NrankPC*this_chan + NrankPC*Nchan * bid] += xsum;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
__global__ void average_snips(const double *Params, const int *iC, const int *call, const int *id, const float *uproj, const float *cmax, float *WU){
int my_chan, this_chan, tidx, tidy, bid, ind, Nspikes, NrankPC, NchanNear, Nchan;
float xsum = 0.0f;
Nspikes = (int) Params[0];
NrankPC = (int) Params[1];
Nchan = (int) Params[7];
NchanNear = (int) Params[6];
tidx = threadIdx.x;
tidy = threadIdx.y;
bid = blockIdx.x;
for(ind=0; ind<Nspikes;ind++)
if (id[ind]==bid){
my_chan = call[ind];
this_chan = iC[tidy + NchanNear * my_chan];
xsum = uproj[tidx + NrankPC*tidy + NrankPC*NchanNear * ind];
WU[tidx + NrankPC*this_chan + NrankPC*Nchan * bid] += xsum;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13average_snipsPKdPKiS2_S2_PKfS4_Pf
.globl _Z13average_snipsPKdPKiS2_S2_PKfS4_Pf
.p2align 8
.type _Z13average_snipsPKdPKiS2_S2_PKfS4_Pf,@function
_Z13average_snipsPKdPKiS2_S2_PKfS4_Pf:
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b64 s[4:5], s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_cvt_i32_f64_e32 v4, s[4:5]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, 1, v4
s_cbranch_vccnz .LBB0_5
s_clause 0x1
s_load_b128 s[4:7], s[2:3], 0x30
s_load_b64 s[2:3], s[2:3], 0x8
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
v_cvt_i32_f64_e32 v2, s[6:7]
v_cvt_i32_f64_e32 v5, s[2:3]
v_cvt_i32_f64_e32 v6, s[4:5]
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v7, s15, v2
v_mad_u64_u32 v[2:3], null, v0, v5, v[1:2]
s_delay_alu instid0(VALU_DEP_3)
v_mul_lo_u32 v8, v6, v5
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v4, -1, v4
s_add_u32 s8, s8, 4
v_add_nc_u32_e32 v2, v2, v8
s_addc_u32 s9, s9, 0
s_add_u32 s6, s6, 4
v_cmp_ne_u32_e32 vcc_lo, 0, v4
s_addc_u32 s7, s7, 0
s_cbranch_vccz .LBB0_5
.LBB0_3:
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[8:9], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s2, s15
s_cbranch_scc1 .LBB0_2
s_load_b32 s2, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[9:10], null, s2, v6, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
global_load_b32 v3, v[9:10], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v3, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[9:10], null, v3, v5, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[11:12], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v10, 31, v9
v_add_co_u32 v11, vcc_lo, s10, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_add_co_ci_u32_e32 v12, vcc_lo, s11, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v9, vcc_lo, s0, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v10, vcc_lo
global_load_b32 v3, v[11:12], off
global_load_b32 v11, v[9:10], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v3, v11
global_store_b32 v[9:10], v3, off
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13average_snipsPKdPKiS2_S2_PKfS4_Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 56
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13average_snipsPKdPKiS2_S2_PKfS4_Pf, .Lfunc_end0-_Z13average_snipsPKdPKiS2_S2_PKfS4_Pf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 56
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13average_snipsPKdPKiS2_S2_PKfS4_Pf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13average_snipsPKdPKiS2_S2_PKfS4_Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
__global__ void average_snips(const double *Params, const int *iC, const int *call, const int *id, const float *uproj, const float *cmax, float *WU){
int my_chan, this_chan, tidx, tidy, bid, ind, Nspikes, NrankPC, NchanNear, Nchan;
float xsum = 0.0f;
Nspikes = (int) Params[0];
NrankPC = (int) Params[1];
Nchan = (int) Params[7];
NchanNear = (int) Params[6];
tidx = threadIdx.x;
tidy = threadIdx.y;
bid = blockIdx.x;
for(ind=0; ind<Nspikes;ind++)
if (id[ind]==bid){
my_chan = call[ind];
this_chan = iC[tidy + NchanNear * my_chan];
xsum = uproj[tidx + NrankPC*tidy + NrankPC*NchanNear * ind];
WU[tidx + NrankPC*this_chan + NrankPC*Nchan * bid] += xsum;
}
} | .text
.file "average_snips.hip"
.globl _Z28__device_stub__average_snipsPKdPKiS2_S2_PKfS4_Pf # -- Begin function _Z28__device_stub__average_snipsPKdPKiS2_S2_PKfS4_Pf
.p2align 4, 0x90
.type _Z28__device_stub__average_snipsPKdPKiS2_S2_PKfS4_Pf,@function
_Z28__device_stub__average_snipsPKdPKiS2_S2_PKfS4_Pf: # @_Z28__device_stub__average_snipsPKdPKiS2_S2_PKfS4_Pf
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13average_snipsPKdPKiS2_S2_PKfS4_Pf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z28__device_stub__average_snipsPKdPKiS2_S2_PKfS4_Pf, .Lfunc_end0-_Z28__device_stub__average_snipsPKdPKiS2_S2_PKfS4_Pf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13average_snipsPKdPKiS2_S2_PKfS4_Pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13average_snipsPKdPKiS2_S2_PKfS4_Pf,@object # @_Z13average_snipsPKdPKiS2_S2_PKfS4_Pf
.section .rodata,"a",@progbits
.globl _Z13average_snipsPKdPKiS2_S2_PKfS4_Pf
.p2align 3, 0x0
_Z13average_snipsPKdPKiS2_S2_PKfS4_Pf:
.quad _Z28__device_stub__average_snipsPKdPKiS2_S2_PKfS4_Pf
.size _Z13average_snipsPKdPKiS2_S2_PKfS4_Pf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13average_snipsPKdPKiS2_S2_PKfS4_Pf"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__average_snipsPKdPKiS2_S2_PKfS4_Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13average_snipsPKdPKiS2_S2_PKfS4_Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13average_snipsPKdPKiS2_S2_PKfS4_Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R6, c[0x0][0x160] ; /* 0x0000580000067a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R7, c[0x0][0x164] ; /* 0x0000590000077a02 */
/* 0x000fca0000000f00 */
/*0040*/ LDG.E.64 R2, [R6.64] ; /* 0x0000000a06027981 */
/* 0x000ea4000c1e1b00 */
/*0050*/ F2I.F64.TRUNC R15, R2 ; /* 0x00000002000f7311 */
/* 0x004e24000030d100 */
/*0060*/ ISETP.GE.AND P0, PT, R15, 0x1, PT ; /* 0x000000010f00780c */
/* 0x001fda0003f06270 */
/*0070*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0080*/ LDG.E.64 R12, [R6.64+0x38] ; /* 0x0000380a060c7981 */
/* 0x000ea8000c1e1b00 */
/*0090*/ LDG.E.64 R8, [R6.64+0x8] ; /* 0x0000080a06087981 */
/* 0x000ee8000c1e1b00 */
/*00a0*/ LDG.E.64 R10, [R6.64+0x30] ; /* 0x0000300a060a7981 */
/* 0x000f22000c1e1b00 */
/*00b0*/ S2UR UR12, SR_CTAID.X ; /* 0x00000000000c79c3 */
/* 0x000e220000002500 */
/*00c0*/ IADD3 R3, R15.reuse, -0x1, RZ ; /* 0xffffffff0f037810 */
/* 0x040fe20007ffe0ff */
/*00d0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00e0*/ S2R R4, SR_TID.Y ; /* 0x0000000000047919 */
/* 0x000e620000002200 */
/*00f0*/ LOP3.LUT R2, R15, 0x3, RZ, 0xc0, !PT ; /* 0x000000030f027812 */
/* 0x000fc400078ec0ff */
/*0100*/ ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe20003f26070 */
/*0110*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0120*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0130*/ F2I.F64.TRUNC R12, R12 ; /* 0x0000000c000c7311 */
/* 0x004e30000030d100 */
/*0140*/ F2I.F64.TRUNC R0, R8 ; /* 0x0000000800007311 */
/* 0x0084f0000030d100 */
/*0150*/ F2I.F64.TRUNC R3, R10 ; /* 0x0000000a00037311 */
/* 0x010522000030d100 */
/*0160*/ IMAD R6, R12, UR12, RZ ; /* 0x0000000c0c067c24 */
/* 0x001fe2000f8e02ff */
/*0170*/ @!P1 BRA 0x6e0 ; /* 0x0000056000009947 */
/* 0x000fec0003800000 */
/*0180*/ LEA R23, R3.reuse, R4.reuse, 0x1 ; /* 0x0000000403177211 */
/* 0x0d2fe200078e08ff */
/*0190*/ IMAD R11, R3.reuse, 0x3, R4 ; /* 0x00000003030b7824 */
/* 0x044fe200078e0204 */
/*01a0*/ IADD3 R9, R3, R4, RZ ; /* 0x0000000403097210 */
/* 0x000fe20007ffe0ff */
/*01b0*/ IMAD R8, R0.reuse, R3, RZ ; /* 0x0000000300087224 */
/* 0x048fe200078e02ff */
/*01c0*/ IADD3 R7, -R15, R2, RZ ; /* 0x000000020f077210 */
/* 0x000fe20007ffe1ff */
/*01d0*/ IMAD R21, R0.reuse, R4, R5.reuse ; /* 0x0000000400157224 */
/* 0x140fe200078e0205 */
/*01e0*/ MOV R14, c[0x0][0x170] ; /* 0x00005c00000e7a02 */
/* 0x000fe20000000f00 */
/*01f0*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff0d7624 */
/* 0x000fe200078e00ff */
/*0200*/ MOV R15, c[0x0][0x174] ; /* 0x00005d00000f7a02 */
/* 0x000fe20000000f00 */
/*0210*/ IMAD R11, R0.reuse, R11, R5.reuse ; /* 0x0000000b000b7224 */
/* 0x140fe200078e0205 */
/*0220*/ MOV R12, c[0x0][0x178] ; /* 0x00005e00000c7a02 */
/* 0x000fe20000000f00 */
/*0230*/ IMAD R23, R0.reuse, R23, R5.reuse ; /* 0x0000001700177224 */
/* 0x140fe200078e0205 */
/*0240*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0250*/ IMAD R9, R0, R9, R5 ; /* 0x0000000900097224 */
/* 0x000fc400078e0205 */
/*0260*/ LDG.E R10, [R12.64] ; /* 0x0000000a0c0a7981 */
/* 0x000ea4000c1e1900 */
/*0270*/ ISETP.NE.AND P1, PT, R10, UR12, PT ; /* 0x0000000c0a007c0c */
/* 0x004fda000bf25270 */
/*0280*/ @!P1 LDG.E R10, [R14.64] ; /* 0x0000000a0e0a9981 */
/* 0x000ea2000c1e1900 */
/*0290*/ @!P1 MOV R19, 0x4 ; /* 0x0000000400139802 */
/* 0x000fe20000000f00 */
/*02a0*/ @!P1 IMAD R10, R3, R10, R4 ; /* 0x0000000a030a9224 */
/* 0x004fc800078e0204 */
/*02b0*/ @!P1 IMAD.WIDE R24, R10, R19, c[0x0][0x168] ; /* 0x00005a000a189625 */
/* 0x000fcc00078e0213 */
/*02c0*/ @!P1 LDG.E R25, [R24.64] ; /* 0x0000000a18199981 */
/* 0x000ea2000c1e1900 */
/*02d0*/ @!P1 IMAD.WIDE R16, R21, R19, c[0x0][0x180] ; /* 0x0000600015109625 */
/* 0x000fcc00078e0213 */
/*02e0*/ @!P1 LDG.E R17, [R16.64] ; /* 0x0000000a10119981 */
/* 0x000ee2000c1e1900 */
/*02f0*/ @!P1 IADD3 R10, R6, R25, RZ ; /* 0x00000019060a9210 */
/* 0x004fca0007ffe0ff */
/*0300*/ @!P1 IMAD R10, R0, R10, R5 ; /* 0x0000000a000a9224 */
/* 0x000fc800078e0205 */
/*0310*/ @!P1 IMAD.WIDE R18, R10, R19, c[0x0][0x190] ; /* 0x000064000a129625 */
/* 0x000fca00078e0213 */
/*0320*/ @!P1 LDG.E R10, [R18.64] ; /* 0x0000000a120a9981 */
/* 0x000ee4000c1e1900 */
/*0330*/ @!P1 FADD R27, R10, R17 ; /* 0x000000110a1b9221 */
/* 0x008fca0000000000 */
/*0340*/ @!P1 STG.E [R18.64], R27 ; /* 0x0000001b12009986 */
/* 0x0001e8000c10190a */
/*0350*/ LDG.E R10, [R12.64+0x4] ; /* 0x0000040a0c0a7981 */
/* 0x000ea4000c1e1900 */
/*0360*/ ISETP.NE.AND P1, PT, R10, UR12, PT ; /* 0x0000000c0a007c0c */
/* 0x004fda000bf25270 */
/*0370*/ @!P1 LDG.E R10, [R14.64+0x4] ; /* 0x0000040a0e0a9981 */
/* 0x000ea2000c1e1900 */
/*0380*/ @!P1 MOV R29, 0x4 ; /* 0x00000004001d9802 */
/* 0x000fe20000000f00 */
/*0390*/ @!P1 IMAD R10, R3, R10, R4 ; /* 0x0000000a030a9224 */
/* 0x004fc800078e0204 */
/*03a0*/ @!P1 IMAD.WIDE R24, R10, R29, c[0x0][0x168] ; /* 0x00005a000a189625 */
/* 0x000fcc00078e021d */
/*03b0*/ @!P1 LDG.E R25, [R24.64] ; /* 0x0000000a18199981 */
/* 0x000ea2000c1e1900 */
/*03c0*/ @!P1 IMAD.WIDE R16, R9, R29, c[0x0][0x180] ; /* 0x0000600009109625 */
/* 0x000fcc00078e021d */
/*03d0*/ @!P1 LDG.E R17, [R16.64] ; /* 0x0000000a10119981 */
/* 0x000ee2000c1e1900 */
/*03e0*/ @!P1 IADD3 R10, R6, R25, RZ ; /* 0x00000019060a9210 */
/* 0x004fca0007ffe0ff */
/*03f0*/ @!P1 IMAD R10, R0, R10, R5 ; /* 0x0000000a000a9224 */
/* 0x000fc800078e0205 */
/*0400*/ @!P1 IMAD.WIDE R18, R10, R29, c[0x0][0x190] ; /* 0x000064000a129625 */
/* 0x001fca00078e021d */
/*0410*/ @!P1 LDG.E R10, [R18.64] ; /* 0x0000000a120a9981 */
/* 0x000ee4000c1e1900 */
/*0420*/ @!P1 FADD R27, R10, R17 ; /* 0x000000110a1b9221 */
/* 0x008fca0000000000 */
/*0430*/ @!P1 STG.E [R18.64], R27 ; /* 0x0000001b12009986 */
/* 0x0001e8000c10190a */
/*0440*/ LDG.E R10, [R12.64+0x8] ; /* 0x0000080a0c0a7981 */
/* 0x000ea4000c1e1900 */
/*0450*/ ISETP.NE.AND P1, PT, R10, UR12, PT ; /* 0x0000000c0a007c0c */
/* 0x004fda000bf25270 */
/*0460*/ @!P1 LDG.E R10, [R14.64+0x8] ; /* 0x0000080a0e0a9981 */
/* 0x000ea2000c1e1900 */
/*0470*/ @!P1 MOV R29, 0x4 ; /* 0x00000004001d9802 */
/* 0x000fe20000000f00 */
/*0480*/ @!P1 IMAD R10, R3, R10, R4 ; /* 0x0000000a030a9224 */
/* 0x004fc800078e0204 */
/*0490*/ @!P1 IMAD.WIDE R24, R10, R29, c[0x0][0x168] ; /* 0x00005a000a189625 */
/* 0x000fcc00078e021d */
/*04a0*/ @!P1 LDG.E R25, [R24.64] ; /* 0x0000000a18199981 */
/* 0x000ea2000c1e1900 */
/*04b0*/ @!P1 IMAD.WIDE R16, R23, R29, c[0x0][0x180] ; /* 0x0000600017109625 */
/* 0x000fcc00078e021d */
/*04c0*/ @!P1 LDG.E R17, [R16.64] ; /* 0x0000000a10119981 */
/* 0x000ee2000c1e1900 */
/*04d0*/ @!P1 IADD3 R10, R6, R25, RZ ; /* 0x00000019060a9210 */
/* 0x004fca0007ffe0ff */
/*04e0*/ @!P1 IMAD R10, R0, R10, R5 ; /* 0x0000000a000a9224 */
/* 0x000fc800078e0205 */
/*04f0*/ @!P1 IMAD.WIDE R18, R10, R29, c[0x0][0x190] ; /* 0x000064000a129625 */
/* 0x001fca00078e021d */
/*0500*/ @!P1 LDG.E R10, [R18.64] ; /* 0x0000000a120a9981 */
/* 0x000ee4000c1e1900 */
/*0510*/ @!P1 FADD R27, R10, R17 ; /* 0x000000110a1b9221 */
/* 0x008fca0000000000 */
/*0520*/ @!P1 STG.E [R18.64], R27 ; /* 0x0000001b12009986 */
/* 0x0001e8000c10190a */
/*0530*/ LDG.E R10, [R12.64+0xc] ; /* 0x00000c0a0c0a7981 */
/* 0x000ea4000c1e1900 */
/*0540*/ ISETP.NE.AND P1, PT, R10, UR12, PT ; /* 0x0000000c0a007c0c */
/* 0x004fda000bf25270 */
/*0550*/ @!P1 LDG.E R10, [R14.64+0xc] ; /* 0x00000c0a0e0a9981 */
/* 0x000ea2000c1e1900 */
/*0560*/ @!P1 IMAD.MOV.U32 R29, RZ, RZ, 0x4 ; /* 0x00000004ff1d9424 */
/* 0x000fe400078e00ff */
/*0570*/ @!P1 IMAD R10, R3, R10, R4 ; /* 0x0000000a030a9224 */
/* 0x004fc800078e0204 */
/*0580*/ @!P1 IMAD.WIDE R24, R10, R29, c[0x0][0x168] ; /* 0x00005a000a189625 */
/* 0x000fcc00078e021d */
/*0590*/ @!P1 LDG.E R25, [R24.64] ; /* 0x0000000a18199981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ @!P1 IMAD.WIDE R16, R11, R29, c[0x0][0x180] ; /* 0x000060000b109625 */
/* 0x000fcc00078e021d */
/*05b0*/ @!P1 LDG.E R17, [R16.64] ; /* 0x0000000a10119981 */
/* 0x000ee2000c1e1900 */
/*05c0*/ @!P1 IADD3 R10, R6, R25, RZ ; /* 0x00000019060a9210 */
/* 0x004fca0007ffe0ff */
/*05d0*/ @!P1 IMAD R10, R0, R10, R5 ; /* 0x0000000a000a9224 */
/* 0x000fc800078e0205 */
/*05e0*/ @!P1 IMAD.WIDE R18, R10, R29, c[0x0][0x190] ; /* 0x000064000a129625 */
/* 0x001fca00078e021d */
/*05f0*/ @!P1 LDG.E R10, [R18.64] ; /* 0x0000000a120a9981 */
/* 0x000ee2000c1e1900 */
/*0600*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0610*/ IADD3 R12, P2, R12, 0x10, RZ ; /* 0x000000100c0c7810 */
/* 0x000fe40007f5e0ff */
/*0620*/ IADD3 R14, P3, R14, 0x10, RZ ; /* 0x000000100e0e7810 */
/* 0x000fe20007f7e0ff */
/*0630*/ IMAD R11, R8.reuse, 0x4, R11 ; /* 0x00000004080b7824 */
/* 0x040fe200078e020b */
/*0640*/ IADD3.X R13, RZ, R13, RZ, P2, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe400017fe4ff */
/*0650*/ IADD3.X R15, RZ, R15, RZ, P3, !PT ; /* 0x0000000fff0f7210 */
/* 0x000fe40001ffe4ff */
/*0660*/ LEA R21, R8, R21, 0x2 ; /* 0x0000001508157211 */
/* 0x000fc400078e10ff */
/*0670*/ LEA R9, R8.reuse, R9, 0x2 ; /* 0x0000000908097211 */
/* 0x040fe400078e10ff */
/*0680*/ LEA R23, R8, R23, 0x2 ; /* 0x0000001708177211 */
/* 0x000fe200078e10ff */
/*0690*/ @!P1 FADD R27, R10, R17 ; /* 0x000000110a1b9221 */
/* 0x008fe20000000000 */
/*06a0*/ IADD3 R10, R7, UR4, RZ ; /* 0x00000004070a7c10 */
/* 0x000fc8000fffe0ff */
/*06b0*/ @!P1 STG.E [R18.64], R27 ; /* 0x0000001b12009986 */
/* 0x0001e2000c10190a */
/*06c0*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f25270 */
/*06d0*/ @P1 BRA 0x260 ; /* 0xfffffb8000001947 */
/* 0x001fea000383ffff */
/*06e0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x002fea0003800000 */
/*06f0*/ IMAD R7, R3, UR4, R4 ; /* 0x0000000403077c24 */
/* 0x010fe2000f8e0204 */
/*0700*/ UMOV UR5, 0x4 ; /* 0x0000000400057882 */
/* 0x000fe20000000000 */
/*0710*/ IMAD R18, R0.reuse, R3, RZ ; /* 0x0000000300127224 */
/* 0x048fe200078e02ff */
/*0720*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe20000000a00 */
/*0730*/ IMAD R7, R0, R7, R5 ; /* 0x0000000700077224 */
/* 0x000fe200078e0205 */
/*0740*/ ULDC.64 UR8, c[0x0][0x178] ; /* 0x00005e0000087ab9 */
/* 0x000fe40000000a00 */
/*0750*/ UIMAD.WIDE UR6, UR4, UR5, UR6 ; /* 0x00000005040672a5 */
/* 0x000fe4000f8e0206 */
/*0760*/ UIMAD.WIDE UR8, UR4, UR5, UR8 ; /* 0x00000005040872a5 */
/* 0x000fcc000f8e0208 */
/*0770*/ MOV R10, UR8 ; /* 0x00000008000a7c02 */
/* 0x004fe40008000f00 */
/*0780*/ MOV R11, UR9 ; /* 0x00000009000b7c02 */
/* 0x000fca0008000f00 */
/*0790*/ LDG.E R10, [R10.64] ; /* 0x0000000a0a0a7981 */
/* 0x000ea2000c1e1900 */
/*07a0*/ MOV R14, UR6 ; /* 0x00000006000e7c02 */
/* 0x000fe40008000f00 */
/*07b0*/ MOV R15, UR7 ; /* 0x00000007000f7c02 */
/* 0x000fe40008000f00 */
/*07c0*/ ISETP.NE.AND P0, PT, R10, UR12, PT ; /* 0x0000000c0a007c0c */
/* 0x004fda000bf05270 */
/*07d0*/ @!P0 LDG.E R14, [R14.64] ; /* 0x0000000a0e0e8981 */
/* 0x000ea2000c1e1900 */
/*07e0*/ @!P0 MOV R13, 0x4 ; /* 0x00000004000d8802 */
/* 0x000fe20000000f00 */
/*07f0*/ @!P0 IMAD R8, R3, R14, R4 ; /* 0x0000000e03088224 */
/* 0x004fc800078e0204 */
/*0800*/ @!P0 IMAD.WIDE R8, R8, R13, c[0x0][0x168] ; /* 0x00005a0008088625 */
/* 0x000fcc00078e020d */
/*0810*/ @!P0 LDG.E R9, [R8.64] ; /* 0x0000000a08098981 */
/* 0x000ea2000c1e1900 */
/*0820*/ @!P0 IMAD.WIDE R10, R7, R13, c[0x0][0x180] ; /* 0x00006000070a8625 */
/* 0x000fcc00078e020d */
/*0830*/ @!P0 LDG.E R11, [R10.64] ; /* 0x0000000a0a0b8981 */
/* 0x000ee2000c1e1900 */
/*0840*/ @!P0 IADD3 R12, R6, R9, RZ ; /* 0x00000009060c8210 */
/* 0x004fca0007ffe0ff */
/*0850*/ @!P0 IMAD R12, R0, R12, R5 ; /* 0x0000000c000c8224 */
/* 0x000fc800078e0205 */
/*0860*/ @!P0 IMAD.WIDE R12, R12, R13, c[0x0][0x190] ; /* 0x000064000c0c8625 */
/* 0x000fca00078e020d */
/*0870*/ @!P0 LDG.E R16, [R12.64] ; /* 0x0000000a0c108981 */
/* 0x000ee2000c1e1900 */
/*0880*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe20007ffe0ff */
/*0890*/ UIADD3 UR8, UP1, UR8, 0x4, URZ ; /* 0x0000000408087890 */
/* 0x000fe4000ff3e03f */
/*08a0*/ UIADD3 UR6, UP0, UR6, 0x4, URZ ; /* 0x0000000406067890 */
/* 0x000fe4000ff1e03f */
/*08b0*/ UIADD3.X UR9, URZ, UR9, URZ, UP1, !UPT ; /* 0x000000093f097290 */
/* 0x000fe40008ffe43f */
/*08c0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08d0*/ IADD3 R7, R18, R7, RZ ; /* 0x0000000712077210 */
/* 0x000fe20007ffe0ff */
/*08e0*/ @!P0 FADD R15, R16, R11 ; /* 0x0000000b100f8221 */
/* 0x008fca0000000000 */
/*08f0*/ @!P0 STG.E [R12.64], R15 ; /* 0x0000000f0c008986 */
/* 0x0001e2000c10190a */
/*0900*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*0910*/ @P0 BRA 0x770 ; /* 0xfffffe5000000947 */
/* 0x001fea000383ffff */
/*0920*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0930*/ BRA 0x930; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13average_snipsPKdPKiS2_S2_PKfS4_Pf
.globl _Z13average_snipsPKdPKiS2_S2_PKfS4_Pf
.p2align 8
.type _Z13average_snipsPKdPKiS2_S2_PKfS4_Pf,@function
_Z13average_snipsPKdPKiS2_S2_PKfS4_Pf:
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b64 s[4:5], s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_cvt_i32_f64_e32 v4, s[4:5]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, 1, v4
s_cbranch_vccnz .LBB0_5
s_clause 0x1
s_load_b128 s[4:7], s[2:3], 0x30
s_load_b64 s[2:3], s[2:3], 0x8
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
v_cvt_i32_f64_e32 v2, s[6:7]
v_cvt_i32_f64_e32 v5, s[2:3]
v_cvt_i32_f64_e32 v6, s[4:5]
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v7, s15, v2
v_mad_u64_u32 v[2:3], null, v0, v5, v[1:2]
s_delay_alu instid0(VALU_DEP_3)
v_mul_lo_u32 v8, v6, v5
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v4, -1, v4
s_add_u32 s8, s8, 4
v_add_nc_u32_e32 v2, v2, v8
s_addc_u32 s9, s9, 0
s_add_u32 s6, s6, 4
v_cmp_ne_u32_e32 vcc_lo, 0, v4
s_addc_u32 s7, s7, 0
s_cbranch_vccz .LBB0_5
.LBB0_3:
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[8:9], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s2, s15
s_cbranch_scc1 .LBB0_2
s_load_b32 s2, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[9:10], null, s2, v6, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
global_load_b32 v3, v[9:10], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v3, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[9:10], null, v3, v5, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[11:12], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v10, 31, v9
v_add_co_u32 v11, vcc_lo, s10, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_add_co_ci_u32_e32 v12, vcc_lo, s11, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v9, vcc_lo, s0, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v10, vcc_lo
global_load_b32 v3, v[11:12], off
global_load_b32 v11, v[9:10], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v3, v11
global_store_b32 v[9:10], v3, off
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13average_snipsPKdPKiS2_S2_PKfS4_Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 56
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13average_snipsPKdPKiS2_S2_PKfS4_Pf, .Lfunc_end0-_Z13average_snipsPKdPKiS2_S2_PKfS4_Pf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 56
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13average_snipsPKdPKiS2_S2_PKfS4_Pf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13average_snipsPKdPKiS2_S2_PKfS4_Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007cdee_00000000-6_average_snips.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z13average_snipsPKdPKiS2_S2_PKfS4_PfPKdPKiS2_S2_PKfS4_Pf
.type _Z51__device_stub__Z13average_snipsPKdPKiS2_S2_PKfS4_PfPKdPKiS2_S2_PKfS4_Pf, @function
_Z51__device_stub__Z13average_snipsPKdPKiS2_S2_PKfS4_PfPKdPKiS2_S2_PKfS4_Pf:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z13average_snipsPKdPKiS2_S2_PKfS4_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z51__device_stub__Z13average_snipsPKdPKiS2_S2_PKfS4_PfPKdPKiS2_S2_PKfS4_Pf, .-_Z51__device_stub__Z13average_snipsPKdPKiS2_S2_PKfS4_PfPKdPKiS2_S2_PKfS4_Pf
.globl _Z13average_snipsPKdPKiS2_S2_PKfS4_Pf
.type _Z13average_snipsPKdPKiS2_S2_PKfS4_Pf, @function
_Z13average_snipsPKdPKiS2_S2_PKfS4_Pf:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z51__device_stub__Z13average_snipsPKdPKiS2_S2_PKfS4_PfPKdPKiS2_S2_PKfS4_Pf
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13average_snipsPKdPKiS2_S2_PKfS4_Pf, .-_Z13average_snipsPKdPKiS2_S2_PKfS4_Pf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z13average_snipsPKdPKiS2_S2_PKfS4_Pf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13average_snipsPKdPKiS2_S2_PKfS4_Pf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "average_snips.hip"
.globl _Z28__device_stub__average_snipsPKdPKiS2_S2_PKfS4_Pf # -- Begin function _Z28__device_stub__average_snipsPKdPKiS2_S2_PKfS4_Pf
.p2align 4, 0x90
.type _Z28__device_stub__average_snipsPKdPKiS2_S2_PKfS4_Pf,@function
_Z28__device_stub__average_snipsPKdPKiS2_S2_PKfS4_Pf: # @_Z28__device_stub__average_snipsPKdPKiS2_S2_PKfS4_Pf
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13average_snipsPKdPKiS2_S2_PKfS4_Pf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z28__device_stub__average_snipsPKdPKiS2_S2_PKfS4_Pf, .Lfunc_end0-_Z28__device_stub__average_snipsPKdPKiS2_S2_PKfS4_Pf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13average_snipsPKdPKiS2_S2_PKfS4_Pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13average_snipsPKdPKiS2_S2_PKfS4_Pf,@object # @_Z13average_snipsPKdPKiS2_S2_PKfS4_Pf
.section .rodata,"a",@progbits
.globl _Z13average_snipsPKdPKiS2_S2_PKfS4_Pf
.p2align 3, 0x0
_Z13average_snipsPKdPKiS2_S2_PKfS4_Pf:
.quad _Z28__device_stub__average_snipsPKdPKiS2_S2_PKfS4_Pf
.size _Z13average_snipsPKdPKiS2_S2_PKfS4_Pf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13average_snipsPKdPKiS2_S2_PKfS4_Pf"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__average_snipsPKdPKiS2_S2_PKfS4_Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13average_snipsPKdPKiS2_S2_PKfS4_Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void gpu_square_matrix_mult(int *d_a, int *d_b, int *d_result, int n)
{
__shared__ int tile_a[BLOCK_SIZE][BLOCK_SIZE];
__shared__ int tile_b[BLOCK_SIZE][BLOCK_SIZE];
int row = blockIdx.y * BLOCK_SIZE + threadIdx.y;
int col = blockIdx.x * BLOCK_SIZE + threadIdx.x;
int tmp = 0;
int idx;
for (int sub = 0; sub < gridDim.x; ++sub)
{
idx = row * n + sub * BLOCK_SIZE + threadIdx.x;
if (idx >= n*n)
{
// n may not divisible by BLOCK_SIZE
tile_a[threadIdx.y][threadIdx.x] = 0;
}
else
{
tile_a[threadIdx.y][threadIdx.x] = d_a[idx];
}
idx = (sub * BLOCK_SIZE + threadIdx.y) * n + col;
if (idx >= n * n)
{
tile_b[threadIdx.y][threadIdx.x] = 0;
}
else
{
tile_b[threadIdx.y][threadIdx.x] = d_b[idx];
}
__syncthreads();
for (int k = 0; k < BLOCK_SIZE; ++k)
{
tmp += tile_a[threadIdx.y][k] * tile_b[k][threadIdx.x];
}
__syncthreads();
}
if (row < n && col < n)
{
d_result[row * n + col] = tmp;
}
} | code for sm_80
Function : _Z22gpu_square_matrix_multPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0xc], PT ; /* 0x00000300ff007a0c */
/* 0x000fe20003f25270 */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R17, SR_TID.X ; /* 0x0000000000117919 */
/* 0x000e280000002100 */
/*0060*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0070*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0080*/ LEA R3, R4, R17, 0x4 ; /* 0x0000001104037211 */
/* 0x001fc800078e20ff */
/*0090*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe40003f06270 */
/*00a0*/ LEA R0, R0, R2, 0x4 ; /* 0x0000000200007211 */
/* 0x002fc800078e20ff */
/*00b0*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fe20000706670 */
/*00c0*/ @!P1 BRA 0x4e0 ; /* 0x0000041000009947 */
/* 0x000fd80003800000 */
/*00d0*/ IMAD R16, R2.reuse, c[0x0][0x178], R17.reuse ; /* 0x00005e0002107a24 */
/* 0x140fe200078e0211 */
/*00e0*/ SHF.L.U32 R2, R2, 0x6, RZ ; /* 0x0000000602027819 */
/* 0x000fe200000006ff */
/*00f0*/ IMAD R18, R0, c[0x0][0x178], R17 ; /* 0x00005e0000127a24 */
/* 0x000fe200078e0211 */
/*0100*/ MOV R19, RZ ; /* 0x000000ff00137202 */
/* 0x000fe20000000f00 */
/*0110*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000800 */
/*0120*/ LEA R16, R4, R16, 0x4 ; /* 0x0000001004107211 */
/* 0x000fe200078e20ff */
/*0130*/ UIMAD UR4, UR4, UR4, URZ ; /* 0x00000004040472a4 */
/* 0x000fe2000f8e023f */
/*0140*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fe40000000f00 */
/*0150*/ LEA R20, R17, R2, 0x2 ; /* 0x0000000211147211 */
/* 0x000fc600078e10ff */
/*0160*/ ISETP.GE.AND P1, PT, R18, UR4, PT ; /* 0x0000000412007c0c */
/* 0x000fe2000bf26270 */
/*0170*/ HFMA2.MMA R21, -RZ, RZ, 0, 0 ; /* 0x00000000ff157435 */
/* 0x000fe200000001ff */
/*0180*/ ISETP.GE.AND P2, PT, R16, UR4, PT ; /* 0x0000000410007c0c */
/* 0x000fc4000bf46270 */
/*0190*/ MOV R27, RZ ; /* 0x000000ff001b7202 */
/* 0x000fd20000000f00 */
/*01a0*/ @!P1 MOV R5, 0x4 ; /* 0x0000000400059802 */
/* 0x000fe40000000f00 */
/*01b0*/ @!P2 MOV R11, 0x4 ; /* 0x00000004000ba802 */
/* 0x000fc60000000f00 */
/*01c0*/ @!P1 IMAD.WIDE R4, R18, R5, c[0x0][0x160] ; /* 0x0000580012049625 */
/* 0x000fc800078e0205 */
/*01d0*/ @!P2 IMAD.WIDE R10, R16, R11, c[0x0][0x168] ; /* 0x00005a00100aa625 */
/* 0x000fe200078e020b */
/*01e0*/ @!P1 LDG.E R21, [R4.64] ; /* 0x0000000604159981 */
/* 0x000ea8000c1e1900 */
/*01f0*/ @!P2 LDG.E R27, [R10.64] ; /* 0x000000060a1ba981 */
/* 0x000ee2000c1e1900 */
/*0200*/ IADD3 R19, R19, 0x1, RZ ; /* 0x0000000113137810 */
/* 0x000fe40007ffe0ff */
/*0210*/ IADD3 R18, R18, 0x10, RZ ; /* 0x0000001012127810 */
/* 0x000fe40007ffe0ff */
/*0220*/ ISETP.GE.U32.AND P1, PT, R19, c[0x0][0xc], PT ; /* 0x0000030013007a0c */
/* 0x000fe20003f26070 */
/*0230*/ STS [R20], R21 ; /* 0x0000001514007388 */
/* 0x004fe80000000800 */
/*0240*/ STS [R20+0x400], R27 ; /* 0x0004001b14007388 */
/* 0x008fe80000000800 */
/*0250*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0260*/ LDS R8, [R17.X4+0x400] ; /* 0x0004000011087984 */
/* 0x000fe80000004800 */
/*0270*/ LDS.128 R12, [R2] ; /* 0x00000000020c7984 */
/* 0x000e280000000c00 */
/*0280*/ LDS R28, [R17.X4+0x440] ; /* 0x00044000111c7984 */
/* 0x000e680000004800 */
/*0290*/ LDS R29, [R17.X4+0x480] ; /* 0x00048000111d7984 */
/* 0x000ea80000004800 */
/*02a0*/ LDS R24, [R17.X4+0x4c0] ; /* 0x0004c00011187984 */
/* 0x000ee80000004800 */
/*02b0*/ LDS R25, [R17.X4+0x500] ; /* 0x0005000011197984 */
/* 0x000fe80000004800 */
/*02c0*/ LDS.128 R4, [R2+0x10] ; /* 0x0000100002047984 */
/* 0x000f280000000c00 */
/*02d0*/ LDS R26, [R17.X4+0x540] ; /* 0x00054000111a7984 */
/* 0x000f680000004800 */
/*02e0*/ LDS R23, [R17.X4+0x580] ; /* 0x0005800011177984 */
/* 0x000f680000004800 */
/*02f0*/ LDS R22, [R17.X4+0x5c0] ; /* 0x0005c00011167984 */
/* 0x000f680000004800 */
/*0300*/ LDS R21, [R17.X4+0x600] ; /* 0x0006000011157984 */
/* 0x000fe20000004800 */
/*0310*/ IMAD R8, R8, R12, R9 ; /* 0x0000000c08087224 */
/* 0x001fc800078e0209 */
/*0320*/ IMAD R13, R28, R13, R8 ; /* 0x0000000d1c0d7224 */
/* 0x002fe400078e0208 */
/*0330*/ LDS.128 R8, [R2+0x20] ; /* 0x0000200002087984 */
/* 0x000e240000000c00 */
/*0340*/ IMAD R13, R29, R14, R13 ; /* 0x0000000e1d0d7224 */
/* 0x004fc800078e020d */
/*0350*/ IMAD R13, R24, R15, R13 ; /* 0x0000000f180d7224 */
/* 0x008fe400078e020d */
/*0360*/ LDS R24, [R17.X4+0x640] ; /* 0x0006400011187984 */
/* 0x000e640000004800 */
/*0370*/ IMAD R4, R25, R4, R13 ; /* 0x0000000419047224 */
/* 0x010fe400078e020d */
/*0380*/ LDS R25, [R17.X4+0x680] ; /* 0x0006800011197984 */
/* 0x000ea40000004800 */
/*0390*/ IMAD R5, R26, R5, R4 ; /* 0x000000051a057224 */
/* 0x020fe400078e0204 */
/*03a0*/ LDS R4, [R17.X4+0x6c0] ; /* 0x0006c00011047984 */
/* 0x000ee40000004800 */
/*03b0*/ IMAD R23, R23, R6, R5 ; /* 0x0000000617177224 */
/* 0x000fc400078e0205 */
/*03c0*/ LDS R5, [R17.X4+0x700] ; /* 0x0007000011057984 */
/* 0x000fe40000004800 */
/*03d0*/ IMAD R23, R22, R7, R23 ; /* 0x0000000716177224 */
/* 0x000fe400078e0217 */
/*03e0*/ LDS.128 R12, [R2+0x30] ; /* 0x00003000020c7984 */
/* 0x000f280000000c00 */
/*03f0*/ LDS R6, [R17.X4+0x740] ; /* 0x0007400011067984 */
/* 0x000f680000004800 */
/*0400*/ LDS R7, [R17.X4+0x780] ; /* 0x0007800011077984 */
/* 0x000f680000004800 */
/*0410*/ LDS R22, [R17.X4+0x7c0] ; /* 0x0007c00011167984 */
/* 0x000f620000004800 */
/*0420*/ IMAD R8, R21, R8, R23 ; /* 0x0000000815087224 */
/* 0x001fc800078e0217 */
/*0430*/ IMAD R8, R24, R9, R8 ; /* 0x0000000918087224 */
/* 0x002fc800078e0208 */
/*0440*/ IMAD R8, R25, R10, R8 ; /* 0x0000000a19087224 */
/* 0x004fc800078e0208 */
/*0450*/ IMAD R4, R4, R11, R8 ; /* 0x0000000b04047224 */
/* 0x008fc800078e0208 */
/*0460*/ IMAD R4, R5, R12, R4 ; /* 0x0000000c05047224 */
/* 0x010fe200078e0204 */
/*0470*/ MOV R5, c[0x0][0x178] ; /* 0x00005e0000057a02 */
/* 0x000fc60000000f00 */
/*0480*/ IMAD R4, R6, R13, R4 ; /* 0x0000000d06047224 */
/* 0x020fe200078e0204 */
/*0490*/ LEA R16, R5, R16, 0x4 ; /* 0x0000001005107211 */
/* 0x000fc600078e20ff */
/*04a0*/ IMAD R4, R7, R14, R4 ; /* 0x0000000e07047224 */
/* 0x000fc800078e0204 */
/*04b0*/ IMAD R9, R22, R15, R4 ; /* 0x0000000f16097224 */
/* 0x000fe200078e0204 */
/*04c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04d0*/ @!P1 BRA 0x160 ; /* 0xfffffc8000009947 */
/* 0x000fea000383ffff */
/*04e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*04f0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0500*/ IMAD R3, R0, c[0x0][0x178], R3 ; /* 0x00005e0000037a24 */
/* 0x000fd200078e0203 */
/*0510*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0520*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101906 */
/*0530*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0540*/ BRA 0x540; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void gpu_square_matrix_mult(int *d_a, int *d_b, int *d_result, int n)
{
__shared__ int tile_a[BLOCK_SIZE][BLOCK_SIZE];
__shared__ int tile_b[BLOCK_SIZE][BLOCK_SIZE];
int row = blockIdx.y * BLOCK_SIZE + threadIdx.y;
int col = blockIdx.x * BLOCK_SIZE + threadIdx.x;
int tmp = 0;
int idx;
for (int sub = 0; sub < gridDim.x; ++sub)
{
idx = row * n + sub * BLOCK_SIZE + threadIdx.x;
if (idx >= n*n)
{
// n may not divisible by BLOCK_SIZE
tile_a[threadIdx.y][threadIdx.x] = 0;
}
else
{
tile_a[threadIdx.y][threadIdx.x] = d_a[idx];
}
idx = (sub * BLOCK_SIZE + threadIdx.y) * n + col;
if (idx >= n * n)
{
tile_b[threadIdx.y][threadIdx.x] = 0;
}
else
{
tile_b[threadIdx.y][threadIdx.x] = d_b[idx];
}
__syncthreads();
for (int k = 0; k < BLOCK_SIZE; ++k)
{
tmp += tile_a[threadIdx.y][k] * tile_b[k][threadIdx.x];
}
__syncthreads();
}
if (row < n && col < n)
{
d_result[row * n + col] = tmp;
}
} | .file "tmpxft_0008641b_00000000-6_gpu_square_matrix_mult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z22gpu_square_matrix_multPiS_S_iPiS_S_i
.type _Z47__device_stub__Z22gpu_square_matrix_multPiS_S_iPiS_S_i, @function
_Z47__device_stub__Z22gpu_square_matrix_multPiS_S_iPiS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22gpu_square_matrix_multPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z22gpu_square_matrix_multPiS_S_iPiS_S_i, .-_Z47__device_stub__Z22gpu_square_matrix_multPiS_S_iPiS_S_i
.globl _Z22gpu_square_matrix_multPiS_S_i
.type _Z22gpu_square_matrix_multPiS_S_i, @function
_Z22gpu_square_matrix_multPiS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z22gpu_square_matrix_multPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z22gpu_square_matrix_multPiS_S_i, .-_Z22gpu_square_matrix_multPiS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z22gpu_square_matrix_multPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z22gpu_square_matrix_multPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void gpu_square_matrix_mult(int *d_a, int *d_b, int *d_result, int n)
{
__shared__ int tile_a[BLOCK_SIZE][BLOCK_SIZE];
__shared__ int tile_b[BLOCK_SIZE][BLOCK_SIZE];
int row = blockIdx.y * BLOCK_SIZE + threadIdx.y;
int col = blockIdx.x * BLOCK_SIZE + threadIdx.x;
int tmp = 0;
int idx;
for (int sub = 0; sub < gridDim.x; ++sub)
{
idx = row * n + sub * BLOCK_SIZE + threadIdx.x;
if (idx >= n*n)
{
// n may not divisible by BLOCK_SIZE
tile_a[threadIdx.y][threadIdx.x] = 0;
}
else
{
tile_a[threadIdx.y][threadIdx.x] = d_a[idx];
}
idx = (sub * BLOCK_SIZE + threadIdx.y) * n + col;
if (idx >= n * n)
{
tile_b[threadIdx.y][threadIdx.x] = 0;
}
else
{
tile_b[threadIdx.y][threadIdx.x] = d_b[idx];
}
__syncthreads();
for (int k = 0; k < BLOCK_SIZE; ++k)
{
tmp += tile_a[threadIdx.y][k] * tile_b[k][threadIdx.x];
}
__syncthreads();
}
if (row < n && col < n)
{
d_result[row * n + col] = tmp;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gpu_square_matrix_mult(int *d_a, int *d_b, int *d_result, int n)
{
__shared__ int tile_a[BLOCK_SIZE][BLOCK_SIZE];
__shared__ int tile_b[BLOCK_SIZE][BLOCK_SIZE];
int row = blockIdx.y * BLOCK_SIZE + threadIdx.y;
int col = blockIdx.x * BLOCK_SIZE + threadIdx.x;
int tmp = 0;
int idx;
for (int sub = 0; sub < gridDim.x; ++sub)
{
idx = row * n + sub * BLOCK_SIZE + threadIdx.x;
if (idx >= n*n)
{
// n may not divisible by BLOCK_SIZE
tile_a[threadIdx.y][threadIdx.x] = 0;
}
else
{
tile_a[threadIdx.y][threadIdx.x] = d_a[idx];
}
idx = (sub * BLOCK_SIZE + threadIdx.y) * n + col;
if (idx >= n * n)
{
tile_b[threadIdx.y][threadIdx.x] = 0;
}
else
{
tile_b[threadIdx.y][threadIdx.x] = d_b[idx];
}
__syncthreads();
for (int k = 0; k < BLOCK_SIZE; ++k)
{
tmp += tile_a[threadIdx.y][k] * tile_b[k][threadIdx.x];
}
__syncthreads();
}
if (row < n && col < n)
{
d_result[row * n + col] = tmp;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gpu_square_matrix_mult(int *d_a, int *d_b, int *d_result, int n)
{
__shared__ int tile_a[BLOCK_SIZE][BLOCK_SIZE];
__shared__ int tile_b[BLOCK_SIZE][BLOCK_SIZE];
int row = blockIdx.y * BLOCK_SIZE + threadIdx.y;
int col = blockIdx.x * BLOCK_SIZE + threadIdx.x;
int tmp = 0;
int idx;
for (int sub = 0; sub < gridDim.x; ++sub)
{
idx = row * n + sub * BLOCK_SIZE + threadIdx.x;
if (idx >= n*n)
{
// n may not divisible by BLOCK_SIZE
tile_a[threadIdx.y][threadIdx.x] = 0;
}
else
{
tile_a[threadIdx.y][threadIdx.x] = d_a[idx];
}
idx = (sub * BLOCK_SIZE + threadIdx.y) * n + col;
if (idx >= n * n)
{
tile_b[threadIdx.y][threadIdx.x] = 0;
}
else
{
tile_b[threadIdx.y][threadIdx.x] = d_b[idx];
}
__syncthreads();
for (int k = 0; k < BLOCK_SIZE; ++k)
{
tmp += tile_a[threadIdx.y][k] * tile_b[k][threadIdx.x];
}
__syncthreads();
}
if (row < n && col < n)
{
d_result[row * n + col] = tmp;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22gpu_square_matrix_multPiS_S_i
.globl _Z22gpu_square_matrix_multPiS_S_i
.p2align 8
.type _Z22gpu_square_matrix_multPiS_S_i,@function
_Z22gpu_square_matrix_multPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x20
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v6, v0, 10, 10
v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v4, 0x3ff, v0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v5, s15, 4, v6
v_lshl_add_u32 v0, s14, 4, v4
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s3, 0
s_cbranch_scc1 .LBB0_13
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v4
v_lshlrev_b32_e32 v7, 6, v6
v_mad_u64_u32 v[2:3], null, v5, s2, v[4:5]
s_mul_i32 s9, s2, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v8, 0x400, v1
v_add_nc_u32_e32 v9, v7, v1
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v11, 0 :: v_dual_add_nc_u32 v10, v8, v7
.LBB0_2:
s_lshl_b32 s10, s8, 4
s_mov_b32 s11, exec_lo
v_add_nc_u32_e32 v3, s10, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_le_i32_e64 s9, v3
s_xor_b32 s11, exec_lo, s11
s_cbranch_execz .LBB0_4
ds_store_b32 v9, v11
.LBB0_4:
s_and_not1_saveexec_b32 s11, s11
s_cbranch_execz .LBB0_6
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
ds_store_b32 v9, v3
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s11
v_add_nc_u32_e32 v12, s10, v6
s_mov_b32 s10, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v12, s2, v[0:1]
v_cmpx_le_i32_e64 s9, v3
s_xor_b32 s10, exec_lo, s10
s_cbranch_execz .LBB0_8
ds_store_b32 v10, v11
.LBB0_8:
s_and_not1_saveexec_b32 s10, s10
s_cbranch_execz .LBB0_10
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
ds_store_b32 v10, v3
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s10
v_mov_b32_e32 v3, v8
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_11:
v_add_nc_u32_e32 v4, s10, v7
s_add_i32 s10, s10, 4
ds_load_b32 v14, v3
ds_load_b32 v4, v4
v_add_nc_u32_e32 v3, 64, v3
s_cmp_eq_u32 s10, 64
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[12:13], null, v14, v4, v[1:2]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v1, v12
s_cbranch_scc0 .LBB0_11
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, s3
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_13:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_max_i32_e32 v2, v5, v0
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_15
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v5, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
.LBB0_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22gpu_square_matrix_multPiS_S_i
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22gpu_square_matrix_multPiS_S_i, .Lfunc_end0-_Z22gpu_square_matrix_multPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22gpu_square_matrix_multPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22gpu_square_matrix_multPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gpu_square_matrix_mult(int *d_a, int *d_b, int *d_result, int n)
{
__shared__ int tile_a[BLOCK_SIZE][BLOCK_SIZE];
__shared__ int tile_b[BLOCK_SIZE][BLOCK_SIZE];
int row = blockIdx.y * BLOCK_SIZE + threadIdx.y;
int col = blockIdx.x * BLOCK_SIZE + threadIdx.x;
int tmp = 0;
int idx;
for (int sub = 0; sub < gridDim.x; ++sub)
{
idx = row * n + sub * BLOCK_SIZE + threadIdx.x;
if (idx >= n*n)
{
// n may not divisible by BLOCK_SIZE
tile_a[threadIdx.y][threadIdx.x] = 0;
}
else
{
tile_a[threadIdx.y][threadIdx.x] = d_a[idx];
}
idx = (sub * BLOCK_SIZE + threadIdx.y) * n + col;
if (idx >= n * n)
{
tile_b[threadIdx.y][threadIdx.x] = 0;
}
else
{
tile_b[threadIdx.y][threadIdx.x] = d_b[idx];
}
__syncthreads();
for (int k = 0; k < BLOCK_SIZE; ++k)
{
tmp += tile_a[threadIdx.y][k] * tile_b[k][threadIdx.x];
}
__syncthreads();
}
if (row < n && col < n)
{
d_result[row * n + col] = tmp;
}
} | .text
.file "gpu_square_matrix_mult.hip"
.globl _Z37__device_stub__gpu_square_matrix_multPiS_S_i # -- Begin function _Z37__device_stub__gpu_square_matrix_multPiS_S_i
.p2align 4, 0x90
.type _Z37__device_stub__gpu_square_matrix_multPiS_S_i,@function
_Z37__device_stub__gpu_square_matrix_multPiS_S_i: # @_Z37__device_stub__gpu_square_matrix_multPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22gpu_square_matrix_multPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z37__device_stub__gpu_square_matrix_multPiS_S_i, .Lfunc_end0-_Z37__device_stub__gpu_square_matrix_multPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22gpu_square_matrix_multPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22gpu_square_matrix_multPiS_S_i,@object # @_Z22gpu_square_matrix_multPiS_S_i
.section .rodata,"a",@progbits
.globl _Z22gpu_square_matrix_multPiS_S_i
.p2align 3, 0x0
_Z22gpu_square_matrix_multPiS_S_i:
.quad _Z37__device_stub__gpu_square_matrix_multPiS_S_i
.size _Z22gpu_square_matrix_multPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z22gpu_square_matrix_multPiS_S_i"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__gpu_square_matrix_multPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22gpu_square_matrix_multPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z22gpu_square_matrix_multPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0xc], PT ; /* 0x00000300ff007a0c */
/* 0x000fe20003f25270 */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R17, SR_TID.X ; /* 0x0000000000117919 */
/* 0x000e280000002100 */
/*0060*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0070*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0080*/ LEA R3, R4, R17, 0x4 ; /* 0x0000001104037211 */
/* 0x001fc800078e20ff */
/*0090*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe40003f06270 */
/*00a0*/ LEA R0, R0, R2, 0x4 ; /* 0x0000000200007211 */
/* 0x002fc800078e20ff */
/*00b0*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fe20000706670 */
/*00c0*/ @!P1 BRA 0x4e0 ; /* 0x0000041000009947 */
/* 0x000fd80003800000 */
/*00d0*/ IMAD R16, R2.reuse, c[0x0][0x178], R17.reuse ; /* 0x00005e0002107a24 */
/* 0x140fe200078e0211 */
/*00e0*/ SHF.L.U32 R2, R2, 0x6, RZ ; /* 0x0000000602027819 */
/* 0x000fe200000006ff */
/*00f0*/ IMAD R18, R0, c[0x0][0x178], R17 ; /* 0x00005e0000127a24 */
/* 0x000fe200078e0211 */
/*0100*/ MOV R19, RZ ; /* 0x000000ff00137202 */
/* 0x000fe20000000f00 */
/*0110*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000800 */
/*0120*/ LEA R16, R4, R16, 0x4 ; /* 0x0000001004107211 */
/* 0x000fe200078e20ff */
/*0130*/ UIMAD UR4, UR4, UR4, URZ ; /* 0x00000004040472a4 */
/* 0x000fe2000f8e023f */
/*0140*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fe40000000f00 */
/*0150*/ LEA R20, R17, R2, 0x2 ; /* 0x0000000211147211 */
/* 0x000fc600078e10ff */
/*0160*/ ISETP.GE.AND P1, PT, R18, UR4, PT ; /* 0x0000000412007c0c */
/* 0x000fe2000bf26270 */
/*0170*/ HFMA2.MMA R21, -RZ, RZ, 0, 0 ; /* 0x00000000ff157435 */
/* 0x000fe200000001ff */
/*0180*/ ISETP.GE.AND P2, PT, R16, UR4, PT ; /* 0x0000000410007c0c */
/* 0x000fc4000bf46270 */
/*0190*/ MOV R27, RZ ; /* 0x000000ff001b7202 */
/* 0x000fd20000000f00 */
/*01a0*/ @!P1 MOV R5, 0x4 ; /* 0x0000000400059802 */
/* 0x000fe40000000f00 */
/*01b0*/ @!P2 MOV R11, 0x4 ; /* 0x00000004000ba802 */
/* 0x000fc60000000f00 */
/*01c0*/ @!P1 IMAD.WIDE R4, R18, R5, c[0x0][0x160] ; /* 0x0000580012049625 */
/* 0x000fc800078e0205 */
/*01d0*/ @!P2 IMAD.WIDE R10, R16, R11, c[0x0][0x168] ; /* 0x00005a00100aa625 */
/* 0x000fe200078e020b */
/*01e0*/ @!P1 LDG.E R21, [R4.64] ; /* 0x0000000604159981 */
/* 0x000ea8000c1e1900 */
/*01f0*/ @!P2 LDG.E R27, [R10.64] ; /* 0x000000060a1ba981 */
/* 0x000ee2000c1e1900 */
/*0200*/ IADD3 R19, R19, 0x1, RZ ; /* 0x0000000113137810 */
/* 0x000fe40007ffe0ff */
/*0210*/ IADD3 R18, R18, 0x10, RZ ; /* 0x0000001012127810 */
/* 0x000fe40007ffe0ff */
/*0220*/ ISETP.GE.U32.AND P1, PT, R19, c[0x0][0xc], PT ; /* 0x0000030013007a0c */
/* 0x000fe20003f26070 */
/*0230*/ STS [R20], R21 ; /* 0x0000001514007388 */
/* 0x004fe80000000800 */
/*0240*/ STS [R20+0x400], R27 ; /* 0x0004001b14007388 */
/* 0x008fe80000000800 */
/*0250*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0260*/ LDS R8, [R17.X4+0x400] ; /* 0x0004000011087984 */
/* 0x000fe80000004800 */
/*0270*/ LDS.128 R12, [R2] ; /* 0x00000000020c7984 */
/* 0x000e280000000c00 */
/*0280*/ LDS R28, [R17.X4+0x440] ; /* 0x00044000111c7984 */
/* 0x000e680000004800 */
/*0290*/ LDS R29, [R17.X4+0x480] ; /* 0x00048000111d7984 */
/* 0x000ea80000004800 */
/*02a0*/ LDS R24, [R17.X4+0x4c0] ; /* 0x0004c00011187984 */
/* 0x000ee80000004800 */
/*02b0*/ LDS R25, [R17.X4+0x500] ; /* 0x0005000011197984 */
/* 0x000fe80000004800 */
/*02c0*/ LDS.128 R4, [R2+0x10] ; /* 0x0000100002047984 */
/* 0x000f280000000c00 */
/*02d0*/ LDS R26, [R17.X4+0x540] ; /* 0x00054000111a7984 */
/* 0x000f680000004800 */
/*02e0*/ LDS R23, [R17.X4+0x580] ; /* 0x0005800011177984 */
/* 0x000f680000004800 */
/*02f0*/ LDS R22, [R17.X4+0x5c0] ; /* 0x0005c00011167984 */
/* 0x000f680000004800 */
/*0300*/ LDS R21, [R17.X4+0x600] ; /* 0x0006000011157984 */
/* 0x000fe20000004800 */
/*0310*/ IMAD R8, R8, R12, R9 ; /* 0x0000000c08087224 */
/* 0x001fc800078e0209 */
/*0320*/ IMAD R13, R28, R13, R8 ; /* 0x0000000d1c0d7224 */
/* 0x002fe400078e0208 */
/*0330*/ LDS.128 R8, [R2+0x20] ; /* 0x0000200002087984 */
/* 0x000e240000000c00 */
/*0340*/ IMAD R13, R29, R14, R13 ; /* 0x0000000e1d0d7224 */
/* 0x004fc800078e020d */
/*0350*/ IMAD R13, R24, R15, R13 ; /* 0x0000000f180d7224 */
/* 0x008fe400078e020d */
/*0360*/ LDS R24, [R17.X4+0x640] ; /* 0x0006400011187984 */
/* 0x000e640000004800 */
/*0370*/ IMAD R4, R25, R4, R13 ; /* 0x0000000419047224 */
/* 0x010fe400078e020d */
/*0380*/ LDS R25, [R17.X4+0x680] ; /* 0x0006800011197984 */
/* 0x000ea40000004800 */
/*0390*/ IMAD R5, R26, R5, R4 ; /* 0x000000051a057224 */
/* 0x020fe400078e0204 */
/*03a0*/ LDS R4, [R17.X4+0x6c0] ; /* 0x0006c00011047984 */
/* 0x000ee40000004800 */
/*03b0*/ IMAD R23, R23, R6, R5 ; /* 0x0000000617177224 */
/* 0x000fc400078e0205 */
/*03c0*/ LDS R5, [R17.X4+0x700] ; /* 0x0007000011057984 */
/* 0x000fe40000004800 */
/*03d0*/ IMAD R23, R22, R7, R23 ; /* 0x0000000716177224 */
/* 0x000fe400078e0217 */
/*03e0*/ LDS.128 R12, [R2+0x30] ; /* 0x00003000020c7984 */
/* 0x000f280000000c00 */
/*03f0*/ LDS R6, [R17.X4+0x740] ; /* 0x0007400011067984 */
/* 0x000f680000004800 */
/*0400*/ LDS R7, [R17.X4+0x780] ; /* 0x0007800011077984 */
/* 0x000f680000004800 */
/*0410*/ LDS R22, [R17.X4+0x7c0] ; /* 0x0007c00011167984 */
/* 0x000f620000004800 */
/*0420*/ IMAD R8, R21, R8, R23 ; /* 0x0000000815087224 */
/* 0x001fc800078e0217 */
/*0430*/ IMAD R8, R24, R9, R8 ; /* 0x0000000918087224 */
/* 0x002fc800078e0208 */
/*0440*/ IMAD R8, R25, R10, R8 ; /* 0x0000000a19087224 */
/* 0x004fc800078e0208 */
/*0450*/ IMAD R4, R4, R11, R8 ; /* 0x0000000b04047224 */
/* 0x008fc800078e0208 */
/*0460*/ IMAD R4, R5, R12, R4 ; /* 0x0000000c05047224 */
/* 0x010fe200078e0204 */
/*0470*/ MOV R5, c[0x0][0x178] ; /* 0x00005e0000057a02 */
/* 0x000fc60000000f00 */
/*0480*/ IMAD R4, R6, R13, R4 ; /* 0x0000000d06047224 */
/* 0x020fe200078e0204 */
/*0490*/ LEA R16, R5, R16, 0x4 ; /* 0x0000001005107211 */
/* 0x000fc600078e20ff */
/*04a0*/ IMAD R4, R7, R14, R4 ; /* 0x0000000e07047224 */
/* 0x000fc800078e0204 */
/*04b0*/ IMAD R9, R22, R15, R4 ; /* 0x0000000f16097224 */
/* 0x000fe200078e0204 */
/*04c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04d0*/ @!P1 BRA 0x160 ; /* 0xfffffc8000009947 */
/* 0x000fea000383ffff */
/*04e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*04f0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0500*/ IMAD R3, R0, c[0x0][0x178], R3 ; /* 0x00005e0000037a24 */
/* 0x000fd200078e0203 */
/*0510*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0520*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101906 */
/*0530*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0540*/ BRA 0x540; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22gpu_square_matrix_multPiS_S_i
.globl _Z22gpu_square_matrix_multPiS_S_i
.p2align 8
.type _Z22gpu_square_matrix_multPiS_S_i,@function
_Z22gpu_square_matrix_multPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x20
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v6, v0, 10, 10
v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v4, 0x3ff, v0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v5, s15, 4, v6
v_lshl_add_u32 v0, s14, 4, v4
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s3, 0
s_cbranch_scc1 .LBB0_13
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v4
v_lshlrev_b32_e32 v7, 6, v6
v_mad_u64_u32 v[2:3], null, v5, s2, v[4:5]
s_mul_i32 s9, s2, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v8, 0x400, v1
v_add_nc_u32_e32 v9, v7, v1
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v11, 0 :: v_dual_add_nc_u32 v10, v8, v7
.LBB0_2:
s_lshl_b32 s10, s8, 4
s_mov_b32 s11, exec_lo
v_add_nc_u32_e32 v3, s10, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_le_i32_e64 s9, v3
s_xor_b32 s11, exec_lo, s11
s_cbranch_execz .LBB0_4
ds_store_b32 v9, v11
.LBB0_4:
s_and_not1_saveexec_b32 s11, s11
s_cbranch_execz .LBB0_6
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
ds_store_b32 v9, v3
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s11
v_add_nc_u32_e32 v12, s10, v6
s_mov_b32 s10, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v12, s2, v[0:1]
v_cmpx_le_i32_e64 s9, v3
s_xor_b32 s10, exec_lo, s10
s_cbranch_execz .LBB0_8
ds_store_b32 v10, v11
.LBB0_8:
s_and_not1_saveexec_b32 s10, s10
s_cbranch_execz .LBB0_10
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
ds_store_b32 v10, v3
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s10
v_mov_b32_e32 v3, v8
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_11:
v_add_nc_u32_e32 v4, s10, v7
s_add_i32 s10, s10, 4
ds_load_b32 v14, v3
ds_load_b32 v4, v4
v_add_nc_u32_e32 v3, 64, v3
s_cmp_eq_u32 s10, 64
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[12:13], null, v14, v4, v[1:2]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v1, v12
s_cbranch_scc0 .LBB0_11
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, s3
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_13:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_max_i32_e32 v2, v5, v0
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_15
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v5, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
.LBB0_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22gpu_square_matrix_multPiS_S_i
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22gpu_square_matrix_multPiS_S_i, .Lfunc_end0-_Z22gpu_square_matrix_multPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22gpu_square_matrix_multPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22gpu_square_matrix_multPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008641b_00000000-6_gpu_square_matrix_mult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z22gpu_square_matrix_multPiS_S_iPiS_S_i
.type _Z47__device_stub__Z22gpu_square_matrix_multPiS_S_iPiS_S_i, @function
_Z47__device_stub__Z22gpu_square_matrix_multPiS_S_iPiS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22gpu_square_matrix_multPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z22gpu_square_matrix_multPiS_S_iPiS_S_i, .-_Z47__device_stub__Z22gpu_square_matrix_multPiS_S_iPiS_S_i
.globl _Z22gpu_square_matrix_multPiS_S_i
.type _Z22gpu_square_matrix_multPiS_S_i, @function
_Z22gpu_square_matrix_multPiS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z22gpu_square_matrix_multPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z22gpu_square_matrix_multPiS_S_i, .-_Z22gpu_square_matrix_multPiS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z22gpu_square_matrix_multPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z22gpu_square_matrix_multPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpu_square_matrix_mult.hip"
.globl _Z37__device_stub__gpu_square_matrix_multPiS_S_i # -- Begin function _Z37__device_stub__gpu_square_matrix_multPiS_S_i
.p2align 4, 0x90
.type _Z37__device_stub__gpu_square_matrix_multPiS_S_i,@function
_Z37__device_stub__gpu_square_matrix_multPiS_S_i: # @_Z37__device_stub__gpu_square_matrix_multPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22gpu_square_matrix_multPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z37__device_stub__gpu_square_matrix_multPiS_S_i, .Lfunc_end0-_Z37__device_stub__gpu_square_matrix_multPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22gpu_square_matrix_multPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22gpu_square_matrix_multPiS_S_i,@object # @_Z22gpu_square_matrix_multPiS_S_i
.section .rodata,"a",@progbits
.globl _Z22gpu_square_matrix_multPiS_S_i
.p2align 3, 0x0
_Z22gpu_square_matrix_multPiS_S_i:
.quad _Z37__device_stub__gpu_square_matrix_multPiS_S_i
.size _Z22gpu_square_matrix_multPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z22gpu_square_matrix_multPiS_S_i"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__gpu_square_matrix_multPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22gpu_square_matrix_multPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void matrixMultiply1(float *A, float *C, int size) {
int Col = blockDim.y * blockIdx.y + threadIdx.y;
int Row = blockDim.x * blockIdx.x + threadIdx.x;
for(int k = 0; k < size; k++)
C[Row * size + Col] += A[k * size + Row] * A[k * size + Col];
} | code for sm_80
Function : _Z15matrixMultiply1PfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ MOV R6, c[0x0][0x170] ; /* 0x00005c0000067a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0040*/ ISETP.GE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fc60003f06270 */
/*0050*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000ea80000002500 */
/*0060*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000eec0000002100 */
/*0070*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0080*/ IADD3 R4, R6, -0x1, RZ ; /* 0xffffffff06047810 */
/* 0x000fe20007ffe0ff */
/*0090*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x003fe200078e0203 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ IMAD R5, R5, c[0x0][0x0], R2 ; /* 0x0000000005057a24 */
/* 0x00cfe200078e0202 */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f06070 */
/*00d0*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*00e0*/ LOP3.LUT R6, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306067812 */
/* 0x000fe200078ec0ff */
/*00f0*/ IMAD R3, R5, c[0x0][0x170], R0 ; /* 0x00005c0005037a24 */
/* 0x000fe200078e0200 */
/*0100*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fce0000000f00 */
/*0110*/ IMAD.WIDE R2, R3, R4, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fe400078e0204 */
/*0120*/ @!P0 BRA 0xd50 ; /* 0x00000c2000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R7, -R6, c[0x0][0x170], RZ ; /* 0x00005c0006077a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000162000c1e1900 */
/*0150*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fe20000000f00 */
/*0160*/ IMAD.WIDE R10, R5, R4, c[0x0][0x160] ; /* 0x00005800050a7625 */
/* 0x000fe200078e0204 */
/*0170*/ ISETP.GT.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc60003f04270 */
/*0180*/ IMAD.WIDE R12, R0, R4, c[0x0][0x160] ; /* 0x00005800000c7625 */
/* 0x000fd400078e0204 */
/*0190*/ @!P0 BRA 0xb90 ; /* 0x000009f000008947 */
/* 0x001fea0003800000 */
/*01a0*/ ISETP.GT.AND P1, PT, R7, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x000fe40003f24270 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01c0*/ @!P1 BRA 0x820 ; /* 0x0000065000009947 */
/* 0x000fea0003800000 */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01e0*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea8000c1e1900 */
/*01f0*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x000ea2000c1e1900 */
/*0200*/ IMAD.WIDE R18, R4, c[0x0][0x170], R12 ; /* 0x00005c0004127a25 */
/* 0x000fc800078e020c */
/*0210*/ IMAD.WIDE R16, R4, c[0x0][0x170], R10 ; /* 0x00005c0004107a25 */
/* 0x000fc800078e020a */
/*0220*/ FFMA R9, R14, R15, R9 ; /* 0x0000000f0e097223 */
/* 0x026fca0000000009 */
/*0230*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*0240*/ LDG.E R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000ea8000c1e1900 */
/*0250*/ LDG.E R15, [R16.64] ; /* 0x00000004100f7981 */
/* 0x000ea2000c1e1900 */
/*0260*/ IMAD.WIDE R20, R4, c[0x0][0x170], R16 ; /* 0x00005c0004147a25 */
/* 0x000fc800078e0210 */
/*0270*/ FFMA R25, R14, R15, R9 ; /* 0x0000000f0e197223 */
/* 0x004fe40000000009 */
/*0280*/ IMAD.WIDE R14, R4, c[0x0][0x170], R18 ; /* 0x00005c00040e7a25 */
/* 0x000fc600078e0212 */
/*0290*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*02a0*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x000ea8000c1e1900 */
/*02b0*/ LDG.E R11, [R20.64] ; /* 0x00000004140b7981 */
/* 0x000ea2000c1e1900 */
/*02c0*/ IMAD.WIDE R22, R4, c[0x0][0x170], R14 ; /* 0x00005c0004167a25 */
/* 0x000fc800078e020e */
/*02d0*/ FFMA R27, R10, R11, R25 ; /* 0x0000000b0a1b7223 */
/* 0x004fe40000000019 */
/*02e0*/ IMAD.WIDE R10, R4, c[0x0][0x170], R20 ; /* 0x00005c00040a7a25 */
/* 0x000fc600078e0214 */
/*02f0*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x000fe8000c101904 */
/*0300*/ LDG.E R9, [R10.64] ; /* 0x000000040a097981 */
/* 0x001ea8000c1e1900 */
/*0310*/ LDG.E R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000ea2000c1e1900 */
/*0320*/ IMAD.WIDE R16, R4, c[0x0][0x170], R22 ; /* 0x00005c0004107a25 */
/* 0x000fc800078e0216 */
/*0330*/ FFMA R9, R12, R9, R27 ; /* 0x000000090c097223 */
/* 0x004fe4000000001b */
/*0340*/ IMAD.WIDE R12, R4, c[0x0][0x170], R10 ; /* 0x00005c00040c7a25 */
/* 0x000fc600078e020a */
/*0350*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*0360*/ LDG.E R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000e68000c1e1900 */
/*0370*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000e62000c1e1900 */
/*0380*/ IMAD.WIDE R18, R4, c[0x0][0x170], R16 ; /* 0x00005c0004127a25 */
/* 0x000fc800078e0210 */
/*0390*/ FFMA R25, R14, R15, R9 ; /* 0x0000000f0e197223 */
/* 0x002fe40000000009 */
/*03a0*/ IMAD.WIDE R14, R4, c[0x0][0x170], R12 ; /* 0x00005c00040e7a25 */
/* 0x000fc600078e020c */
/*03b0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*03c0*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x000ea8000c1e1900 */
/*03d0*/ LDG.E R11, [R14.64] ; /* 0x000000040e0b7981 */
/* 0x000ea2000c1e1900 */
/*03e0*/ IMAD.WIDE R20, R4, c[0x0][0x170], R14 ; /* 0x00005c0004147a25 */
/* 0x000fc800078e020e */
/*03f0*/ FFMA R23, R10, R11, R25 ; /* 0x0000000b0a177223 */
/* 0x004fe40000000019 */
/*0400*/ IMAD.WIDE R10, R4, c[0x0][0x170], R18 ; /* 0x00005c00040a7a25 */
/* 0x000fc600078e0212 */
/*0410*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0420*/ LDG.E R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000ee8000c1e1900 */
/*0430*/ LDG.E R9, [R20.64] ; /* 0x0000000414097981 */
/* 0x001ee2000c1e1900 */
/*0440*/ IMAD.WIDE R16, R4, c[0x0][0x170], R10 ; /* 0x00005c0004107a25 */
/* 0x000fc800078e020a */
/*0450*/ FFMA R9, R12, R9, R23 ; /* 0x000000090c097223 */
/* 0x008fe40000000017 */
/*0460*/ IMAD.WIDE R12, R4, c[0x0][0x170], R20 ; /* 0x00005c00040c7a25 */
/* 0x000fc600078e0214 */
/*0470*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*0480*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000e68000c1e1900 */
/*0490*/ LDG.E R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000e62000c1e1900 */
/*04a0*/ IMAD.WIDE R18, R4, c[0x0][0x170], R16 ; /* 0x00005c0004127a25 */
/* 0x000fc800078e0210 */
/*04b0*/ FFMA R25, R14, R15, R9 ; /* 0x0000000f0e197223 */
/* 0x002fe40000000009 */
/*04c0*/ IMAD.WIDE R14, R4, c[0x0][0x170], R12 ; /* 0x00005c00040e7a25 */
/* 0x000fc600078e020c */
/*04d0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*04e0*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x000ee8000c1e1900 */
/*04f0*/ LDG.E R11, [R14.64] ; /* 0x000000040e0b7981 */
/* 0x000ee2000c1e1900 */
/*0500*/ IMAD.WIDE R22, R4, c[0x0][0x170], R18 ; /* 0x00005c0004167a25 */
/* 0x004fc800078e0212 */
/*0510*/ IMAD.WIDE R20, R4, c[0x0][0x170], R14 ; /* 0x00005c0004147a25 */
/* 0x000fc800078e020e */
/*0520*/ FFMA R27, R10, R11, R25 ; /* 0x0000000b0a1b7223 */
/* 0x008fca0000000019 */
/*0530*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0005e8000c101904 */
/*0540*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000ee8000c1e1900 */
/*0550*/ LDG.E R9, [R20.64] ; /* 0x0000000414097981 */
/* 0x001ee2000c1e1900 */
/*0560*/ IMAD.WIDE R16, R4, c[0x0][0x170], R20 ; /* 0x00005c0004107a25 */
/* 0x000fc800078e0214 */
/*0570*/ FFMA R9, R10, R9, R27 ; /* 0x000000090a097223 */
/* 0x008fe4000000001b */
/*0580*/ IMAD.WIDE R10, R4, c[0x0][0x170], R22 ; /* 0x00005c00040a7a25 */
/* 0x000fc600078e0216 */
/*0590*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*05a0*/ LDG.E R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000e68000c1e1900 */
/*05b0*/ LDG.E R13, [R16.64] ; /* 0x00000004100d7981 */
/* 0x000e62000c1e1900 */
/*05c0*/ IMAD.WIDE R18, R4, c[0x0][0x170], R10 ; /* 0x00005c0004127a25 */
/* 0x000fc800078e020a */
/*05d0*/ FFMA R25, R12, R13, R9 ; /* 0x0000000d0c197223 */
/* 0x002fe40000000009 */
/*05e0*/ IMAD.WIDE R12, R4, c[0x0][0x170], R16 ; /* 0x00005c00040c7a25 */
/* 0x000fc600078e0210 */
/*05f0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*0600*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000ea8000c1e1900 */
/*0610*/ LDG.E R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000ea2000c1e1900 */
/*0620*/ IMAD.WIDE R20, R4, c[0x0][0x170], R18 ; /* 0x00005c0004147a25 */
/* 0x000fc800078e0212 */
/*0630*/ FFMA R27, R14, R15, R25 ; /* 0x0000000f0e1b7223 */
/* 0x004fe40000000019 */
/*0640*/ IMAD.WIDE R14, R4, c[0x0][0x170], R12 ; /* 0x00005c00040e7a25 */
/* 0x000fc600078e020c */
/*0650*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x000fe8000c101904 */
/*0660*/ LDG.E R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000ea8000c1e1900 */
/*0670*/ LDG.E R9, [R14.64] ; /* 0x000000040e097981 */
/* 0x001ea2000c1e1900 */
/*0680*/ IMAD.WIDE R22, R4, c[0x0][0x170], R20 ; /* 0x00005c0004167a25 */
/* 0x000fc800078e0214 */
/*0690*/ IMAD.WIDE R16, R4, c[0x0][0x170], R14 ; /* 0x00005c0004107a25 */
/* 0x000fc800078e020e */
/*06a0*/ FFMA R9, R10, R9, R27 ; /* 0x000000090a097223 */
/* 0x004fca000000001b */
/*06b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*06c0*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000e68000c1e1900 */
/*06d0*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000e62000c1e1900 */
/*06e0*/ IMAD.WIDE R12, R4, c[0x0][0x170], R16 ; /* 0x00005c00040c7a25 */
/* 0x000fc800078e0210 */
/*06f0*/ FFMA R25, R10, R11, R9 ; /* 0x0000000b0a197223 */
/* 0x002fe40000000009 */
/*0700*/ IMAD.WIDE R10, R4, c[0x0][0x170], R22 ; /* 0x00005c00040a7a25 */
/* 0x000fc600078e0216 */
/*0710*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*0720*/ LDG.E R14, [R10.64] ; /* 0x000000040a0e7981 */
/* 0x000ea8000c1e1900 */
/*0730*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000ea2000c1e1900 */
/*0740*/ IMAD.WIDE R18, R4, c[0x0][0x170], R10 ; /* 0x00005c0004127a25 */
/* 0x000fe200078e020a */
/*0750*/ IADD3 R7, R7, -0x10, RZ ; /* 0xfffffff007077810 */
/* 0x000fc60007ffe0ff */
/*0760*/ FFMA R21, R14, R15, R25 ; /* 0x0000000f0e157223 */
/* 0x004fe40000000019 */
/*0770*/ IMAD.WIDE R14, R4, c[0x0][0x170], R12 ; /* 0x00005c00040e7a25 */
/* 0x000fc600078e020c */
/*0780*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0790*/ LDG.E R9, [R14.64] ; /* 0x000000040e097981 */
/* 0x001ea8000c1e1900 */
/*07a0*/ LDG.E R16, [R18.64] ; /* 0x0000000412107981 */
/* 0x000ea2000c1e1900 */
/*07b0*/ ISETP.GT.AND P1, PT, R7, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x000fe20003f24270 */
/*07c0*/ IMAD.WIDE R12, R4, c[0x0][0x170], R18 ; /* 0x00005c00040c7a25 */
/* 0x000fe200078e0212 */
/*07d0*/ IADD3 R8, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x000fc60007ffe0ff */
/*07e0*/ IMAD.WIDE R10, R4, c[0x0][0x170], R14 ; /* 0x00005c00040a7a25 */
/* 0x000fc800078e020e */
/*07f0*/ FFMA R9, R16, R9, R21 ; /* 0x0000000910097223 */
/* 0x004fca0000000015 */
/*0800*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e2000c101904 */
/*0810*/ @P1 BRA 0x1e0 ; /* 0xfffff9c000001947 */
/* 0x000fea000383ffff */
/*0820*/ ISETP.GT.AND P1, PT, R7, 0x4, PT ; /* 0x000000040700780c */
/* 0x000fda0003f24270 */
/*0830*/ @!P1 BRA 0xb70 ; /* 0x0000033000009947 */
/* 0x000fea0003800000 */
/*0840*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea8000c1e1900 */
/*0850*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x000ea2000c1e1900 */
/*0860*/ IMAD.WIDE R18, R4, c[0x0][0x170], R12 ; /* 0x00005c0004127a25 */
/* 0x000fc800078e020c */
/*0870*/ IMAD.WIDE R16, R4, c[0x0][0x170], R10 ; /* 0x00005c0004107a25 */
/* 0x000fc800078e020a */
/*0880*/ FFMA R9, R14, R15, R9 ; /* 0x0000000f0e097223 */
/* 0x026fca0000000009 */
/*0890*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*08a0*/ LDG.E R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000ea8000c1e1900 */
/*08b0*/ LDG.E R15, [R16.64] ; /* 0x00000004100f7981 */
/* 0x000ea2000c1e1900 */
/*08c0*/ IMAD.WIDE R20, R4, c[0x0][0x170], R16 ; /* 0x00005c0004147a25 */
/* 0x000fc800078e0210 */
/*08d0*/ FFMA R25, R14, R15, R9 ; /* 0x0000000f0e197223 */
/* 0x004fe40000000009 */
/*08e0*/ IMAD.WIDE R14, R4, c[0x0][0x170], R18 ; /* 0x00005c00040e7a25 */
/* 0x000fc600078e0212 */
/*08f0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*0900*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x000ea8000c1e1900 */
/*0910*/ LDG.E R11, [R20.64] ; /* 0x00000004140b7981 */
/* 0x000ea2000c1e1900 */
/*0920*/ IMAD.WIDE R22, R4, c[0x0][0x170], R14 ; /* 0x00005c0004167a25 */
/* 0x000fc800078e020e */
/*0930*/ FFMA R27, R10, R11, R25 ; /* 0x0000000b0a1b7223 */
/* 0x004fe40000000019 */
/*0940*/ IMAD.WIDE R10, R4, c[0x0][0x170], R20 ; /* 0x00005c00040a7a25 */
/* 0x000fc600078e0214 */
/*0950*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0005e8000c101904 */
/*0960*/ LDG.E R9, [R10.64] ; /* 0x000000040a097981 */
/* 0x001ee8000c1e1900 */
/*0970*/ LDG.E R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000ee2000c1e1900 */
/*0980*/ IMAD.WIDE R16, R4, c[0x0][0x170], R22 ; /* 0x00005c0004107a25 */
/* 0x000fc800078e0216 */
/*0990*/ FFMA R9, R12, R9, R27 ; /* 0x000000090c097223 */
/* 0x008fe4000000001b */
/*09a0*/ IMAD.WIDE R12, R4, c[0x0][0x170], R10 ; /* 0x00005c00040c7a25 */
/* 0x000fc600078e020a */
/*09b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*09c0*/ LDG.E R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000e68000c1e1900 */
/*09d0*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000e62000c1e1900 */
/*09e0*/ IMAD.WIDE R20, R4, c[0x0][0x170], R16 ; /* 0x00005c0004147a25 */
/* 0x000fc800078e0210 */
/*09f0*/ IMAD.WIDE R18, R4, c[0x0][0x170], R12 ; /* 0x00005c0004127a25 */
/* 0x000fc800078e020c */
/*0a00*/ FFMA R25, R14, R15, R9 ; /* 0x0000000f0e197223 */
/* 0x002fca0000000009 */
/*0a10*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*0a20*/ LDG.E R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000ea8000c1e1900 */
/*0a30*/ LDG.E R11, [R18.64] ; /* 0x00000004120b7981 */
/* 0x000ea2000c1e1900 */
/*0a40*/ IMAD.WIDE R22, R4, c[0x0][0x170], R18 ; /* 0x00005c0004167a25 */
/* 0x000fc800078e0212 */
/*0a50*/ FFMA R27, R10, R11, R25 ; /* 0x0000000b0a1b7223 */
/* 0x004fe40000000019 */
/*0a60*/ IMAD.WIDE R10, R4, c[0x0][0x170], R20 ; /* 0x00005c00040a7a25 */
/* 0x000fc600078e0214 */
/*0a70*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0003e8000c101904 */
/*0a80*/ LDG.E R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000ea8000c1e1900 */
/*0a90*/ LDG.E R9, [R22.64] ; /* 0x0000000416097981 */
/* 0x001ea2000c1e1900 */
/*0aa0*/ IMAD.WIDE R14, R4, c[0x0][0x170], R22 ; /* 0x00005c00040e7a25 */
/* 0x000fc800078e0216 */
/*0ab0*/ IMAD.WIDE R16, R4, c[0x0][0x170], R10 ; /* 0x00005c0004107a25 */
/* 0x000fc800078e020a */
/*0ac0*/ FFMA R29, R12, R9, R27 ; /* 0x000000090c1d7223 */
/* 0x004fca000000001b */
/*0ad0*/ STG.E [R2.64], R29 ; /* 0x0000001d02007986 */
/* 0x0003e8000c101904 */
/*0ae0*/ LDG.E R9, [R14.64] ; /* 0x000000040e097981 */
/* 0x000ea8000c1e1900 */
/*0af0*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ea2000c1e1900 */
/*0b00*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0b10*/ IMAD.WIDE R10, R4, c[0x0][0x170], R14 ; /* 0x00005c00040a7a25 */
/* 0x000fe200078e020e */
/*0b20*/ IADD3 R8, R8, 0x8, RZ ; /* 0x0000000808087810 */
/* 0x000fc40007ffe0ff */
/*0b30*/ IADD3 R7, R7, -0x8, RZ ; /* 0xfffffff807077810 */
/* 0x000fe20007ffe0ff */
/*0b40*/ FFMA R9, R12, R9, R29 ; /* 0x000000090c097223 */
/* 0x004fe4000000001d */
/*0b50*/ IMAD.WIDE R12, R4, c[0x0][0x170], R16 ; /* 0x00005c00040c7a25 */
/* 0x000fc600078e0210 */
/*0b60*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*0b70*/ ISETP.NE.OR P0, PT, R7, RZ, P0 ; /* 0x000000ff0700720c */
/* 0x000fda0000705670 */
/*0b80*/ @!P0 BRA 0xd50 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0b90*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea8000c1e1900 */
/*0ba0*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x000ea2000c1e1900 */
/*0bb0*/ IMAD.WIDE R20, R4, c[0x0][0x170], R12 ; /* 0x00005c0004147a25 */
/* 0x002fc800078e020c */
/*0bc0*/ IMAD.WIDE R18, R4, c[0x0][0x170], R10 ; /* 0x00005c0004127a25 */
/* 0x000fc800078e020a */
/*0bd0*/ FFMA R9, R14, R15, R9 ; /* 0x0000000f0e097223 */
/* 0x024fca0000000009 */
/*0be0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*0bf0*/ LDG.E R14, [R20.64] ; /* 0x00000004140e7981 */
/* 0x000ea8000c1e1900 */
/*0c00*/ LDG.E R15, [R18.64] ; /* 0x00000004120f7981 */
/* 0x000ea2000c1e1900 */
/*0c10*/ IMAD.WIDE R22, R4, c[0x0][0x170], R18 ; /* 0x00005c0004167a25 */
/* 0x000fc800078e0212 */
/*0c20*/ FFMA R27, R14, R15, R9 ; /* 0x0000000f0e1b7223 */
/* 0x004fe40000000009 */
/*0c30*/ IMAD.WIDE R14, R4, c[0x0][0x170], R20 ; /* 0x00005c00040e7a25 */
/* 0x000fc600078e0214 */
/*0c40*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0003e8000c101904 */
/*0c50*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x000ea8000c1e1900 */
/*0c60*/ LDG.E R11, [R22.64] ; /* 0x00000004160b7981 */
/* 0x000ea2000c1e1900 */
/*0c70*/ IMAD.WIDE R16, R4, c[0x0][0x170], R22 ; /* 0x00005c0004107a25 */
/* 0x000fc800078e0216 */
/*0c80*/ IMAD.WIDE R24, R4, c[0x0][0x170], R14 ; /* 0x00005c0004187a25 */
/* 0x000fc800078e020e */
/*0c90*/ FFMA R29, R10, R11, R27 ; /* 0x0000000b0a1d7223 */
/* 0x004fca000000001b */
/*0ca0*/ STG.E [R2.64], R29 ; /* 0x0000001d02007986 */
/* 0x0003e8000c101904 */
/*0cb0*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x001ea8000c1e1900 */
/*0cc0*/ LDG.E R10, [R24.64] ; /* 0x00000004180a7981 */
/* 0x000ea2000c1e1900 */
/*0cd0*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fe20007ffe0ff */
/*0ce0*/ IMAD.WIDE R12, R4, c[0x0][0x170], R24 ; /* 0x00005c00040c7a25 */
/* 0x000fe200078e0218 */
/*0cf0*/ IADD3 R8, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fc40007ffe0ff */
/*0d00*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*0d10*/ FFMA R9, R10, R9, R29 ; /* 0x000000090a097223 */
/* 0x004fe4000000001d */
/*0d20*/ IMAD.WIDE R10, R4, c[0x0][0x170], R16 ; /* 0x00005c00040a7a25 */
/* 0x000fc600078e0210 */
/*0d30*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003ee000c101904 */
/*0d40*/ @P0 BRA 0xb90 ; /* 0xfffffe4000000947 */
/* 0x002fea000383ffff */
/*0d50*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*0d60*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0d70*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000164000c1e1900 */
/*0d80*/ IMAD R9, R8.reuse, c[0x0][0x170], R0 ; /* 0x00005c0008097a24 */
/* 0x062fe400078e0200 */
/*0d90*/ IMAD R5, R8, c[0x0][0x170], R5 ; /* 0x00005c0008057a24 */
/* 0x000fe400078e0205 */
/*0da0*/ IMAD.WIDE R8, R9, R4, c[0x0][0x160] ; /* 0x0000580009087625 */
/* 0x000fc800078e0204 */
/*0db0*/ IMAD.WIDE R10, R5, R4, c[0x0][0x160] ; /* 0x00005800050a7625 */
/* 0x000fc800078e0204 */
/*0dc0*/ LDG.E R0, [R8.64] ; /* 0x0000000408007981 */
/* 0x0022a8000c1e1900 */
/*0dd0*/ LDG.E R5, [R10.64] ; /* 0x000000040a057981 */
/* 0x0006a2000c1e1900 */
/*0de0*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fc80007ffe0ff */
/*0df0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0e00*/ IMAD.WIDE R8, R4, c[0x0][0x170], R8 ; /* 0x00005c0004087a25 */
/* 0x002fc800078e0208 */
/*0e10*/ IMAD.WIDE R10, R4, c[0x0][0x170], R10 ; /* 0x00005c00040a7a25 */
/* 0x008fc800078e020a */
/*0e20*/ FFMA R7, R0, R5, R7 ; /* 0x0000000500077223 */
/* 0x004fca0000000007 */
/*0e30*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0003e2000c101904 */
/*0e40*/ @P0 BRA 0xdc0 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0e50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e60*/ BRA 0xe60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void matrixMultiply1(float *A, float *C, int size) {
int Col = blockDim.y * blockIdx.y + threadIdx.y;
int Row = blockDim.x * blockIdx.x + threadIdx.x;
for(int k = 0; k < size; k++)
C[Row * size + Col] += A[k * size + Row] * A[k * size + Col];
} | .file "tmpxft_0005f1c5_00000000-6_matrixMultiply1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z15matrixMultiply1PfS_iPfS_i
.type _Z38__device_stub__Z15matrixMultiply1PfS_iPfS_i, @function
_Z38__device_stub__Z15matrixMultiply1PfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15matrixMultiply1PfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z15matrixMultiply1PfS_iPfS_i, .-_Z38__device_stub__Z15matrixMultiply1PfS_iPfS_i
.globl _Z15matrixMultiply1PfS_i
.type _Z15matrixMultiply1PfS_i, @function
_Z15matrixMultiply1PfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15matrixMultiply1PfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15matrixMultiply1PfS_i, .-_Z15matrixMultiply1PfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15matrixMultiply1PfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matrixMultiply1PfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void matrixMultiply1(float *A, float *C, int size) {
int Col = blockDim.y * blockIdx.y + threadIdx.y;
int Row = blockDim.x * blockIdx.x + threadIdx.x;
for(int k = 0; k < size; k++)
C[Row * size + Col] += A[k * size + Row] * A[k * size + Col];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixMultiply1(float *A, float *C, int size) {
int Col = blockDim.y * blockIdx.y + threadIdx.y;
int Row = blockDim.x * blockIdx.x + threadIdx.x;
for(int k = 0; k < size; k++)
C[Row * size + Col] += A[k * size + Row] * A[k * size + Col];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixMultiply1(float *A, float *C, int size) {
int Col = blockDim.y * blockIdx.y + threadIdx.y;
int Row = blockDim.x * blockIdx.x + threadIdx.x;
for(int k = 0; k < size; k++)
C[Row * size + Col] += A[k * size + Row] * A[k * size + Col];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15matrixMultiply1PfS_i
.globl _Z15matrixMultiply1PfS_i
.p2align 8
.type _Z15matrixMultiply1PfS_i,@function
_Z15matrixMultiply1PfS_i:
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_3
s_load_b32 s2, s[0:1], 0x24
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_mov_b32 s2, 0
s_mov_b32 s3, s4
global_load_b32 v4, v[2:3], off
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v5, s2, v1
v_add_nc_u32_e32 v7, s2, v0
s_add_i32 s3, s3, -1
s_add_i32 s2, s2, s4
s_cmp_eq_u32 s3, 0
v_ashrrev_i32_e32 v6, 31, v5
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
s_clause 0x1
global_load_b32 v5, v[5:6], off
global_load_b32 v6, v[7:8], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v4, v5, v6
global_store_b32 v[2:3], v4, off
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15matrixMultiply1PfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15matrixMultiply1PfS_i, .Lfunc_end0-_Z15matrixMultiply1PfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15matrixMultiply1PfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15matrixMultiply1PfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixMultiply1(float *A, float *C, int size) {
int Col = blockDim.y * blockIdx.y + threadIdx.y;
int Row = blockDim.x * blockIdx.x + threadIdx.x;
for(int k = 0; k < size; k++)
C[Row * size + Col] += A[k * size + Row] * A[k * size + Col];
} | .text
.file "matrixMultiply1.hip"
.globl _Z30__device_stub__matrixMultiply1PfS_i # -- Begin function _Z30__device_stub__matrixMultiply1PfS_i
.p2align 4, 0x90
.type _Z30__device_stub__matrixMultiply1PfS_i,@function
_Z30__device_stub__matrixMultiply1PfS_i: # @_Z30__device_stub__matrixMultiply1PfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15matrixMultiply1PfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__matrixMultiply1PfS_i, .Lfunc_end0-_Z30__device_stub__matrixMultiply1PfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matrixMultiply1PfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15matrixMultiply1PfS_i,@object # @_Z15matrixMultiply1PfS_i
.section .rodata,"a",@progbits
.globl _Z15matrixMultiply1PfS_i
.p2align 3, 0x0
_Z15matrixMultiply1PfS_i:
.quad _Z30__device_stub__matrixMultiply1PfS_i
.size _Z15matrixMultiply1PfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15matrixMultiply1PfS_i"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__matrixMultiply1PfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15matrixMultiply1PfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15matrixMultiply1PfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ MOV R6, c[0x0][0x170] ; /* 0x00005c0000067a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0040*/ ISETP.GE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fc60003f06270 */
/*0050*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000ea80000002500 */
/*0060*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000eec0000002100 */
/*0070*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0080*/ IADD3 R4, R6, -0x1, RZ ; /* 0xffffffff06047810 */
/* 0x000fe20007ffe0ff */
/*0090*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x003fe200078e0203 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ IMAD R5, R5, c[0x0][0x0], R2 ; /* 0x0000000005057a24 */
/* 0x00cfe200078e0202 */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f06070 */
/*00d0*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*00e0*/ LOP3.LUT R6, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306067812 */
/* 0x000fe200078ec0ff */
/*00f0*/ IMAD R3, R5, c[0x0][0x170], R0 ; /* 0x00005c0005037a24 */
/* 0x000fe200078e0200 */
/*0100*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fce0000000f00 */
/*0110*/ IMAD.WIDE R2, R3, R4, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fe400078e0204 */
/*0120*/ @!P0 BRA 0xd50 ; /* 0x00000c2000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R7, -R6, c[0x0][0x170], RZ ; /* 0x00005c0006077a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000162000c1e1900 */
/*0150*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fe20000000f00 */
/*0160*/ IMAD.WIDE R10, R5, R4, c[0x0][0x160] ; /* 0x00005800050a7625 */
/* 0x000fe200078e0204 */
/*0170*/ ISETP.GT.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc60003f04270 */
/*0180*/ IMAD.WIDE R12, R0, R4, c[0x0][0x160] ; /* 0x00005800000c7625 */
/* 0x000fd400078e0204 */
/*0190*/ @!P0 BRA 0xb90 ; /* 0x000009f000008947 */
/* 0x001fea0003800000 */
/*01a0*/ ISETP.GT.AND P1, PT, R7, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x000fe40003f24270 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01c0*/ @!P1 BRA 0x820 ; /* 0x0000065000009947 */
/* 0x000fea0003800000 */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01e0*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea8000c1e1900 */
/*01f0*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x000ea2000c1e1900 */
/*0200*/ IMAD.WIDE R18, R4, c[0x0][0x170], R12 ; /* 0x00005c0004127a25 */
/* 0x000fc800078e020c */
/*0210*/ IMAD.WIDE R16, R4, c[0x0][0x170], R10 ; /* 0x00005c0004107a25 */
/* 0x000fc800078e020a */
/*0220*/ FFMA R9, R14, R15, R9 ; /* 0x0000000f0e097223 */
/* 0x026fca0000000009 */
/*0230*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*0240*/ LDG.E R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000ea8000c1e1900 */
/*0250*/ LDG.E R15, [R16.64] ; /* 0x00000004100f7981 */
/* 0x000ea2000c1e1900 */
/*0260*/ IMAD.WIDE R20, R4, c[0x0][0x170], R16 ; /* 0x00005c0004147a25 */
/* 0x000fc800078e0210 */
/*0270*/ FFMA R25, R14, R15, R9 ; /* 0x0000000f0e197223 */
/* 0x004fe40000000009 */
/*0280*/ IMAD.WIDE R14, R4, c[0x0][0x170], R18 ; /* 0x00005c00040e7a25 */
/* 0x000fc600078e0212 */
/*0290*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*02a0*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x000ea8000c1e1900 */
/*02b0*/ LDG.E R11, [R20.64] ; /* 0x00000004140b7981 */
/* 0x000ea2000c1e1900 */
/*02c0*/ IMAD.WIDE R22, R4, c[0x0][0x170], R14 ; /* 0x00005c0004167a25 */
/* 0x000fc800078e020e */
/*02d0*/ FFMA R27, R10, R11, R25 ; /* 0x0000000b0a1b7223 */
/* 0x004fe40000000019 */
/*02e0*/ IMAD.WIDE R10, R4, c[0x0][0x170], R20 ; /* 0x00005c00040a7a25 */
/* 0x000fc600078e0214 */
/*02f0*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x000fe8000c101904 */
/*0300*/ LDG.E R9, [R10.64] ; /* 0x000000040a097981 */
/* 0x001ea8000c1e1900 */
/*0310*/ LDG.E R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000ea2000c1e1900 */
/*0320*/ IMAD.WIDE R16, R4, c[0x0][0x170], R22 ; /* 0x00005c0004107a25 */
/* 0x000fc800078e0216 */
/*0330*/ FFMA R9, R12, R9, R27 ; /* 0x000000090c097223 */
/* 0x004fe4000000001b */
/*0340*/ IMAD.WIDE R12, R4, c[0x0][0x170], R10 ; /* 0x00005c00040c7a25 */
/* 0x000fc600078e020a */
/*0350*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*0360*/ LDG.E R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000e68000c1e1900 */
/*0370*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000e62000c1e1900 */
/*0380*/ IMAD.WIDE R18, R4, c[0x0][0x170], R16 ; /* 0x00005c0004127a25 */
/* 0x000fc800078e0210 */
/*0390*/ FFMA R25, R14, R15, R9 ; /* 0x0000000f0e197223 */
/* 0x002fe40000000009 */
/*03a0*/ IMAD.WIDE R14, R4, c[0x0][0x170], R12 ; /* 0x00005c00040e7a25 */
/* 0x000fc600078e020c */
/*03b0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*03c0*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x000ea8000c1e1900 */
/*03d0*/ LDG.E R11, [R14.64] ; /* 0x000000040e0b7981 */
/* 0x000ea2000c1e1900 */
/*03e0*/ IMAD.WIDE R20, R4, c[0x0][0x170], R14 ; /* 0x00005c0004147a25 */
/* 0x000fc800078e020e */
/*03f0*/ FFMA R23, R10, R11, R25 ; /* 0x0000000b0a177223 */
/* 0x004fe40000000019 */
/*0400*/ IMAD.WIDE R10, R4, c[0x0][0x170], R18 ; /* 0x00005c00040a7a25 */
/* 0x000fc600078e0212 */
/*0410*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0420*/ LDG.E R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000ee8000c1e1900 */
/*0430*/ LDG.E R9, [R20.64] ; /* 0x0000000414097981 */
/* 0x001ee2000c1e1900 */
/*0440*/ IMAD.WIDE R16, R4, c[0x0][0x170], R10 ; /* 0x00005c0004107a25 */
/* 0x000fc800078e020a */
/*0450*/ FFMA R9, R12, R9, R23 ; /* 0x000000090c097223 */
/* 0x008fe40000000017 */
/*0460*/ IMAD.WIDE R12, R4, c[0x0][0x170], R20 ; /* 0x00005c00040c7a25 */
/* 0x000fc600078e0214 */
/*0470*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*0480*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000e68000c1e1900 */
/*0490*/ LDG.E R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000e62000c1e1900 */
/*04a0*/ IMAD.WIDE R18, R4, c[0x0][0x170], R16 ; /* 0x00005c0004127a25 */
/* 0x000fc800078e0210 */
/*04b0*/ FFMA R25, R14, R15, R9 ; /* 0x0000000f0e197223 */
/* 0x002fe40000000009 */
/*04c0*/ IMAD.WIDE R14, R4, c[0x0][0x170], R12 ; /* 0x00005c00040e7a25 */
/* 0x000fc600078e020c */
/*04d0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*04e0*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x000ee8000c1e1900 */
/*04f0*/ LDG.E R11, [R14.64] ; /* 0x000000040e0b7981 */
/* 0x000ee2000c1e1900 */
/*0500*/ IMAD.WIDE R22, R4, c[0x0][0x170], R18 ; /* 0x00005c0004167a25 */
/* 0x004fc800078e0212 */
/*0510*/ IMAD.WIDE R20, R4, c[0x0][0x170], R14 ; /* 0x00005c0004147a25 */
/* 0x000fc800078e020e */
/*0520*/ FFMA R27, R10, R11, R25 ; /* 0x0000000b0a1b7223 */
/* 0x008fca0000000019 */
/*0530*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0005e8000c101904 */
/*0540*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000ee8000c1e1900 */
/*0550*/ LDG.E R9, [R20.64] ; /* 0x0000000414097981 */
/* 0x001ee2000c1e1900 */
/*0560*/ IMAD.WIDE R16, R4, c[0x0][0x170], R20 ; /* 0x00005c0004107a25 */
/* 0x000fc800078e0214 */
/*0570*/ FFMA R9, R10, R9, R27 ; /* 0x000000090a097223 */
/* 0x008fe4000000001b */
/*0580*/ IMAD.WIDE R10, R4, c[0x0][0x170], R22 ; /* 0x00005c00040a7a25 */
/* 0x000fc600078e0216 */
/*0590*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*05a0*/ LDG.E R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000e68000c1e1900 */
/*05b0*/ LDG.E R13, [R16.64] ; /* 0x00000004100d7981 */
/* 0x000e62000c1e1900 */
/*05c0*/ IMAD.WIDE R18, R4, c[0x0][0x170], R10 ; /* 0x00005c0004127a25 */
/* 0x000fc800078e020a */
/*05d0*/ FFMA R25, R12, R13, R9 ; /* 0x0000000d0c197223 */
/* 0x002fe40000000009 */
/*05e0*/ IMAD.WIDE R12, R4, c[0x0][0x170], R16 ; /* 0x00005c00040c7a25 */
/* 0x000fc600078e0210 */
/*05f0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*0600*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000ea8000c1e1900 */
/*0610*/ LDG.E R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000ea2000c1e1900 */
/*0620*/ IMAD.WIDE R20, R4, c[0x0][0x170], R18 ; /* 0x00005c0004147a25 */
/* 0x000fc800078e0212 */
/*0630*/ FFMA R27, R14, R15, R25 ; /* 0x0000000f0e1b7223 */
/* 0x004fe40000000019 */
/*0640*/ IMAD.WIDE R14, R4, c[0x0][0x170], R12 ; /* 0x00005c00040e7a25 */
/* 0x000fc600078e020c */
/*0650*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x000fe8000c101904 */
/*0660*/ LDG.E R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000ea8000c1e1900 */
/*0670*/ LDG.E R9, [R14.64] ; /* 0x000000040e097981 */
/* 0x001ea2000c1e1900 */
/*0680*/ IMAD.WIDE R22, R4, c[0x0][0x170], R20 ; /* 0x00005c0004167a25 */
/* 0x000fc800078e0214 */
/*0690*/ IMAD.WIDE R16, R4, c[0x0][0x170], R14 ; /* 0x00005c0004107a25 */
/* 0x000fc800078e020e */
/*06a0*/ FFMA R9, R10, R9, R27 ; /* 0x000000090a097223 */
/* 0x004fca000000001b */
/*06b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*06c0*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000e68000c1e1900 */
/*06d0*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000e62000c1e1900 */
/*06e0*/ IMAD.WIDE R12, R4, c[0x0][0x170], R16 ; /* 0x00005c00040c7a25 */
/* 0x000fc800078e0210 */
/*06f0*/ FFMA R25, R10, R11, R9 ; /* 0x0000000b0a197223 */
/* 0x002fe40000000009 */
/*0700*/ IMAD.WIDE R10, R4, c[0x0][0x170], R22 ; /* 0x00005c00040a7a25 */
/* 0x000fc600078e0216 */
/*0710*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*0720*/ LDG.E R14, [R10.64] ; /* 0x000000040a0e7981 */
/* 0x000ea8000c1e1900 */
/*0730*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000ea2000c1e1900 */
/*0740*/ IMAD.WIDE R18, R4, c[0x0][0x170], R10 ; /* 0x00005c0004127a25 */
/* 0x000fe200078e020a */
/*0750*/ IADD3 R7, R7, -0x10, RZ ; /* 0xfffffff007077810 */
/* 0x000fc60007ffe0ff */
/*0760*/ FFMA R21, R14, R15, R25 ; /* 0x0000000f0e157223 */
/* 0x004fe40000000019 */
/*0770*/ IMAD.WIDE R14, R4, c[0x0][0x170], R12 ; /* 0x00005c00040e7a25 */
/* 0x000fc600078e020c */
/*0780*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0790*/ LDG.E R9, [R14.64] ; /* 0x000000040e097981 */
/* 0x001ea8000c1e1900 */
/*07a0*/ LDG.E R16, [R18.64] ; /* 0x0000000412107981 */
/* 0x000ea2000c1e1900 */
/*07b0*/ ISETP.GT.AND P1, PT, R7, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x000fe20003f24270 */
/*07c0*/ IMAD.WIDE R12, R4, c[0x0][0x170], R18 ; /* 0x00005c00040c7a25 */
/* 0x000fe200078e0212 */
/*07d0*/ IADD3 R8, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x000fc60007ffe0ff */
/*07e0*/ IMAD.WIDE R10, R4, c[0x0][0x170], R14 ; /* 0x00005c00040a7a25 */
/* 0x000fc800078e020e */
/*07f0*/ FFMA R9, R16, R9, R21 ; /* 0x0000000910097223 */
/* 0x004fca0000000015 */
/*0800*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e2000c101904 */
/*0810*/ @P1 BRA 0x1e0 ; /* 0xfffff9c000001947 */
/* 0x000fea000383ffff */
/*0820*/ ISETP.GT.AND P1, PT, R7, 0x4, PT ; /* 0x000000040700780c */
/* 0x000fda0003f24270 */
/*0830*/ @!P1 BRA 0xb70 ; /* 0x0000033000009947 */
/* 0x000fea0003800000 */
/*0840*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea8000c1e1900 */
/*0850*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x000ea2000c1e1900 */
/*0860*/ IMAD.WIDE R18, R4, c[0x0][0x170], R12 ; /* 0x00005c0004127a25 */
/* 0x000fc800078e020c */
/*0870*/ IMAD.WIDE R16, R4, c[0x0][0x170], R10 ; /* 0x00005c0004107a25 */
/* 0x000fc800078e020a */
/*0880*/ FFMA R9, R14, R15, R9 ; /* 0x0000000f0e097223 */
/* 0x026fca0000000009 */
/*0890*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*08a0*/ LDG.E R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000ea8000c1e1900 */
/*08b0*/ LDG.E R15, [R16.64] ; /* 0x00000004100f7981 */
/* 0x000ea2000c1e1900 */
/*08c0*/ IMAD.WIDE R20, R4, c[0x0][0x170], R16 ; /* 0x00005c0004147a25 */
/* 0x000fc800078e0210 */
/*08d0*/ FFMA R25, R14, R15, R9 ; /* 0x0000000f0e197223 */
/* 0x004fe40000000009 */
/*08e0*/ IMAD.WIDE R14, R4, c[0x0][0x170], R18 ; /* 0x00005c00040e7a25 */
/* 0x000fc600078e0212 */
/*08f0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*0900*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x000ea8000c1e1900 */
/*0910*/ LDG.E R11, [R20.64] ; /* 0x00000004140b7981 */
/* 0x000ea2000c1e1900 */
/*0920*/ IMAD.WIDE R22, R4, c[0x0][0x170], R14 ; /* 0x00005c0004167a25 */
/* 0x000fc800078e020e */
/*0930*/ FFMA R27, R10, R11, R25 ; /* 0x0000000b0a1b7223 */
/* 0x004fe40000000019 */
/*0940*/ IMAD.WIDE R10, R4, c[0x0][0x170], R20 ; /* 0x00005c00040a7a25 */
/* 0x000fc600078e0214 */
/*0950*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0005e8000c101904 */
/*0960*/ LDG.E R9, [R10.64] ; /* 0x000000040a097981 */
/* 0x001ee8000c1e1900 */
/*0970*/ LDG.E R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000ee2000c1e1900 */
/*0980*/ IMAD.WIDE R16, R4, c[0x0][0x170], R22 ; /* 0x00005c0004107a25 */
/* 0x000fc800078e0216 */
/*0990*/ FFMA R9, R12, R9, R27 ; /* 0x000000090c097223 */
/* 0x008fe4000000001b */
/*09a0*/ IMAD.WIDE R12, R4, c[0x0][0x170], R10 ; /* 0x00005c00040c7a25 */
/* 0x000fc600078e020a */
/*09b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*09c0*/ LDG.E R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000e68000c1e1900 */
/*09d0*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000e62000c1e1900 */
/*09e0*/ IMAD.WIDE R20, R4, c[0x0][0x170], R16 ; /* 0x00005c0004147a25 */
/* 0x000fc800078e0210 */
/*09f0*/ IMAD.WIDE R18, R4, c[0x0][0x170], R12 ; /* 0x00005c0004127a25 */
/* 0x000fc800078e020c */
/*0a00*/ FFMA R25, R14, R15, R9 ; /* 0x0000000f0e197223 */
/* 0x002fca0000000009 */
/*0a10*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*0a20*/ LDG.E R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000ea8000c1e1900 */
/*0a30*/ LDG.E R11, [R18.64] ; /* 0x00000004120b7981 */
/* 0x000ea2000c1e1900 */
/*0a40*/ IMAD.WIDE R22, R4, c[0x0][0x170], R18 ; /* 0x00005c0004167a25 */
/* 0x000fc800078e0212 */
/*0a50*/ FFMA R27, R10, R11, R25 ; /* 0x0000000b0a1b7223 */
/* 0x004fe40000000019 */
/*0a60*/ IMAD.WIDE R10, R4, c[0x0][0x170], R20 ; /* 0x00005c00040a7a25 */
/* 0x000fc600078e0214 */
/*0a70*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0003e8000c101904 */
/*0a80*/ LDG.E R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000ea8000c1e1900 */
/*0a90*/ LDG.E R9, [R22.64] ; /* 0x0000000416097981 */
/* 0x001ea2000c1e1900 */
/*0aa0*/ IMAD.WIDE R14, R4, c[0x0][0x170], R22 ; /* 0x00005c00040e7a25 */
/* 0x000fc800078e0216 */
/*0ab0*/ IMAD.WIDE R16, R4, c[0x0][0x170], R10 ; /* 0x00005c0004107a25 */
/* 0x000fc800078e020a */
/*0ac0*/ FFMA R29, R12, R9, R27 ; /* 0x000000090c1d7223 */
/* 0x004fca000000001b */
/*0ad0*/ STG.E [R2.64], R29 ; /* 0x0000001d02007986 */
/* 0x0003e8000c101904 */
/*0ae0*/ LDG.E R9, [R14.64] ; /* 0x000000040e097981 */
/* 0x000ea8000c1e1900 */
/*0af0*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ea2000c1e1900 */
/*0b00*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0b10*/ IMAD.WIDE R10, R4, c[0x0][0x170], R14 ; /* 0x00005c00040a7a25 */
/* 0x000fe200078e020e */
/*0b20*/ IADD3 R8, R8, 0x8, RZ ; /* 0x0000000808087810 */
/* 0x000fc40007ffe0ff */
/*0b30*/ IADD3 R7, R7, -0x8, RZ ; /* 0xfffffff807077810 */
/* 0x000fe20007ffe0ff */
/*0b40*/ FFMA R9, R12, R9, R29 ; /* 0x000000090c097223 */
/* 0x004fe4000000001d */
/*0b50*/ IMAD.WIDE R12, R4, c[0x0][0x170], R16 ; /* 0x00005c00040c7a25 */
/* 0x000fc600078e0210 */
/*0b60*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*0b70*/ ISETP.NE.OR P0, PT, R7, RZ, P0 ; /* 0x000000ff0700720c */
/* 0x000fda0000705670 */
/*0b80*/ @!P0 BRA 0xd50 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0b90*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea8000c1e1900 */
/*0ba0*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x000ea2000c1e1900 */
/*0bb0*/ IMAD.WIDE R20, R4, c[0x0][0x170], R12 ; /* 0x00005c0004147a25 */
/* 0x002fc800078e020c */
/*0bc0*/ IMAD.WIDE R18, R4, c[0x0][0x170], R10 ; /* 0x00005c0004127a25 */
/* 0x000fc800078e020a */
/*0bd0*/ FFMA R9, R14, R15, R9 ; /* 0x0000000f0e097223 */
/* 0x024fca0000000009 */
/*0be0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*0bf0*/ LDG.E R14, [R20.64] ; /* 0x00000004140e7981 */
/* 0x000ea8000c1e1900 */
/*0c00*/ LDG.E R15, [R18.64] ; /* 0x00000004120f7981 */
/* 0x000ea2000c1e1900 */
/*0c10*/ IMAD.WIDE R22, R4, c[0x0][0x170], R18 ; /* 0x00005c0004167a25 */
/* 0x000fc800078e0212 */
/*0c20*/ FFMA R27, R14, R15, R9 ; /* 0x0000000f0e1b7223 */
/* 0x004fe40000000009 */
/*0c30*/ IMAD.WIDE R14, R4, c[0x0][0x170], R20 ; /* 0x00005c00040e7a25 */
/* 0x000fc600078e0214 */
/*0c40*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0003e8000c101904 */
/*0c50*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x000ea8000c1e1900 */
/*0c60*/ LDG.E R11, [R22.64] ; /* 0x00000004160b7981 */
/* 0x000ea2000c1e1900 */
/*0c70*/ IMAD.WIDE R16, R4, c[0x0][0x170], R22 ; /* 0x00005c0004107a25 */
/* 0x000fc800078e0216 */
/*0c80*/ IMAD.WIDE R24, R4, c[0x0][0x170], R14 ; /* 0x00005c0004187a25 */
/* 0x000fc800078e020e */
/*0c90*/ FFMA R29, R10, R11, R27 ; /* 0x0000000b0a1d7223 */
/* 0x004fca000000001b */
/*0ca0*/ STG.E [R2.64], R29 ; /* 0x0000001d02007986 */
/* 0x0003e8000c101904 */
/*0cb0*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x001ea8000c1e1900 */
/*0cc0*/ LDG.E R10, [R24.64] ; /* 0x00000004180a7981 */
/* 0x000ea2000c1e1900 */
/*0cd0*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fe20007ffe0ff */
/*0ce0*/ IMAD.WIDE R12, R4, c[0x0][0x170], R24 ; /* 0x00005c00040c7a25 */
/* 0x000fe200078e0218 */
/*0cf0*/ IADD3 R8, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fc40007ffe0ff */
/*0d00*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*0d10*/ FFMA R9, R10, R9, R29 ; /* 0x000000090a097223 */
/* 0x004fe4000000001d */
/*0d20*/ IMAD.WIDE R10, R4, c[0x0][0x170], R16 ; /* 0x00005c00040a7a25 */
/* 0x000fc600078e0210 */
/*0d30*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003ee000c101904 */
/*0d40*/ @P0 BRA 0xb90 ; /* 0xfffffe4000000947 */
/* 0x002fea000383ffff */
/*0d50*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*0d60*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0d70*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000164000c1e1900 */
/*0d80*/ IMAD R9, R8.reuse, c[0x0][0x170], R0 ; /* 0x00005c0008097a24 */
/* 0x062fe400078e0200 */
/*0d90*/ IMAD R5, R8, c[0x0][0x170], R5 ; /* 0x00005c0008057a24 */
/* 0x000fe400078e0205 */
/*0da0*/ IMAD.WIDE R8, R9, R4, c[0x0][0x160] ; /* 0x0000580009087625 */
/* 0x000fc800078e0204 */
/*0db0*/ IMAD.WIDE R10, R5, R4, c[0x0][0x160] ; /* 0x00005800050a7625 */
/* 0x000fc800078e0204 */
/*0dc0*/ LDG.E R0, [R8.64] ; /* 0x0000000408007981 */
/* 0x0022a8000c1e1900 */
/*0dd0*/ LDG.E R5, [R10.64] ; /* 0x000000040a057981 */
/* 0x0006a2000c1e1900 */
/*0de0*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fc80007ffe0ff */
/*0df0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0e00*/ IMAD.WIDE R8, R4, c[0x0][0x170], R8 ; /* 0x00005c0004087a25 */
/* 0x002fc800078e0208 */
/*0e10*/ IMAD.WIDE R10, R4, c[0x0][0x170], R10 ; /* 0x00005c00040a7a25 */
/* 0x008fc800078e020a */
/*0e20*/ FFMA R7, R0, R5, R7 ; /* 0x0000000500077223 */
/* 0x004fca0000000007 */
/*0e30*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0003e2000c101904 */
/*0e40*/ @P0 BRA 0xdc0 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0e50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e60*/ BRA 0xe60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15matrixMultiply1PfS_i
.globl _Z15matrixMultiply1PfS_i
.p2align 8
.type _Z15matrixMultiply1PfS_i,@function
_Z15matrixMultiply1PfS_i:
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_3
s_load_b32 s2, s[0:1], 0x24
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_mov_b32 s2, 0
s_mov_b32 s3, s4
global_load_b32 v4, v[2:3], off
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v5, s2, v1
v_add_nc_u32_e32 v7, s2, v0
s_add_i32 s3, s3, -1
s_add_i32 s2, s2, s4
s_cmp_eq_u32 s3, 0
v_ashrrev_i32_e32 v6, 31, v5
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
s_clause 0x1
global_load_b32 v5, v[5:6], off
global_load_b32 v6, v[7:8], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v4, v5, v6
global_store_b32 v[2:3], v4, off
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15matrixMultiply1PfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15matrixMultiply1PfS_i, .Lfunc_end0-_Z15matrixMultiply1PfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15matrixMultiply1PfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15matrixMultiply1PfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005f1c5_00000000-6_matrixMultiply1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z15matrixMultiply1PfS_iPfS_i
.type _Z38__device_stub__Z15matrixMultiply1PfS_iPfS_i, @function
_Z38__device_stub__Z15matrixMultiply1PfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15matrixMultiply1PfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z15matrixMultiply1PfS_iPfS_i, .-_Z38__device_stub__Z15matrixMultiply1PfS_iPfS_i
.globl _Z15matrixMultiply1PfS_i
.type _Z15matrixMultiply1PfS_i, @function
_Z15matrixMultiply1PfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15matrixMultiply1PfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15matrixMultiply1PfS_i, .-_Z15matrixMultiply1PfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15matrixMultiply1PfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matrixMultiply1PfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixMultiply1.hip"
.globl _Z30__device_stub__matrixMultiply1PfS_i # -- Begin function _Z30__device_stub__matrixMultiply1PfS_i
.p2align 4, 0x90
.type _Z30__device_stub__matrixMultiply1PfS_i,@function
_Z30__device_stub__matrixMultiply1PfS_i: # @_Z30__device_stub__matrixMultiply1PfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15matrixMultiply1PfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__matrixMultiply1PfS_i, .Lfunc_end0-_Z30__device_stub__matrixMultiply1PfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matrixMultiply1PfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15matrixMultiply1PfS_i,@object # @_Z15matrixMultiply1PfS_i
.section .rodata,"a",@progbits
.globl _Z15matrixMultiply1PfS_i
.p2align 3, 0x0
_Z15matrixMultiply1PfS_i:
.quad _Z30__device_stub__matrixMultiply1PfS_i
.size _Z15matrixMultiply1PfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15matrixMultiply1PfS_i"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__matrixMultiply1PfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15matrixMultiply1PfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //============================================================================
// Name : cudaProg.cpp
// Author : Pratil
// Version :
// Copyright : Your copyright notice
// Description : Hello World in C++, Ansi-style
//============================================================================
#include <iostream>
#include <stdio.h>
using namespace std;
__global__ void squareFunc(unsigned int *d_in, unsigned int *d_out)
{
int idx = threadIdx.x;
unsigned int val = d_in[idx];
d_out[idx] = val * val;
//printf("%d square value %d \n ", idx, d_out[idx]);
}
int main()
{
const unsigned int arr_len = 64;
const unsigned int arr_size = 64 * sizeof(unsigned int);
unsigned int arr_in[arr_len];
unsigned int arr_out[arr_len];
for (unsigned int i = 0; i < 64; i++)
{
arr_in[i] = i;
cout << i << " : " << arr_in[i] << endl;
}
unsigned int *d_in;
unsigned int *d_out;
cudaMalloc((void**) &d_in, arr_size);
cudaMalloc((void**) &d_out, arr_size);
cudaMemcpy(d_in, arr_in, arr_size, cudaMemcpyHostToDevice);
squareFunc<<<1,64>>>(d_in, d_out);
cudaMemcpy(arr_out, d_out, arr_size, cudaMemcpyDeviceToHost);
for (unsigned int i = 0; i < 64; i++)
{
cout << i <<" : " << arr_out[i] << endl;
}
cudaDeviceSynchronize();
cudaFree(d_out);
cudaFree(d_in);
return 0;
} | code for sm_80
Function : _Z10squareFuncPjS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x001fcc00078e0205 */
/*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0205 */
/*0070*/ IMAD R7, R2, R2, RZ ; /* 0x0000000202077224 */
/* 0x004fca00078e02ff */
/*0080*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //============================================================================
// Name : cudaProg.cpp
// Author : Pratil
// Version :
// Copyright : Your copyright notice
// Description : Hello World in C++, Ansi-style
//============================================================================
#include <iostream>
#include <stdio.h>
using namespace std;
__global__ void squareFunc(unsigned int *d_in, unsigned int *d_out)
{
int idx = threadIdx.x;
unsigned int val = d_in[idx];
d_out[idx] = val * val;
//printf("%d square value %d \n ", idx, d_out[idx]);
}
int main()
{
const unsigned int arr_len = 64;
const unsigned int arr_size = 64 * sizeof(unsigned int);
unsigned int arr_in[arr_len];
unsigned int arr_out[arr_len];
for (unsigned int i = 0; i < 64; i++)
{
arr_in[i] = i;
cout << i << " : " << arr_in[i] << endl;
}
unsigned int *d_in;
unsigned int *d_out;
cudaMalloc((void**) &d_in, arr_size);
cudaMalloc((void**) &d_out, arr_size);
cudaMemcpy(d_in, arr_in, arr_size, cudaMemcpyHostToDevice);
squareFunc<<<1,64>>>(d_in, d_out);
cudaMemcpy(arr_out, d_out, arr_size, cudaMemcpyDeviceToHost);
for (unsigned int i = 0; i < 64; i++)
{
cout << i <<" : " << arr_out[i] << endl;
}
cudaDeviceSynchronize();
cudaFree(d_out);
cudaFree(d_in);
return 0;
} | .file "tmpxft_000a22d2_00000000-6_squareOfNumbers.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z10squareFuncPjS_PjS_
.type _Z32__device_stub__Z10squareFuncPjS_PjS_, @function
_Z32__device_stub__Z10squareFuncPjS_PjS_:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10squareFuncPjS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z32__device_stub__Z10squareFuncPjS_PjS_, .-_Z32__device_stub__Z10squareFuncPjS_PjS_
.globl _Z10squareFuncPjS_
.type _Z10squareFuncPjS_, @function
_Z10squareFuncPjS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10squareFuncPjS_PjS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z10squareFuncPjS_, .-_Z10squareFuncPjS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " : "
.LC1:
.string " : "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $584, %rsp
.cfi_def_cfa_offset 640
movq %fs:40, %rax
movq %rax, 568(%rsp)
xorl %eax, %eax
movl $0, %ebx
leaq 48(%rsp), %r12
leaq _ZSt4cout(%rip), %r14
leaq .LC0(%rip), %r13
jmp .L16
.L29:
movq 568(%rsp), %rax
subq %fs:40, %rax
jne .L27
call _ZSt16__throw_bad_castv@PLT
.L27:
call __stack_chk_fail@PLT
.L30:
movzbl 67(%r15), %esi
.L15:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbx
cmpq $64, %rbx
je .L28
.L16:
movl %ebx, (%r12,%rbx,4)
movq %rbx, %rsi
movq %r14, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbp
movl $8, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl (%r12,%rbx,4), %esi
movq %rbp, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L29
cmpb $0, 56(%r15)
jne .L30
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L15
.L28:
leaq 8(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $256, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $64, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L17:
leaq 304(%rsp), %rdi
movl $2, %ecx
movl $256, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebp
leaq _ZSt4cout(%rip), %r14
leaq .LC1(%rip), %r13
leaq 304(%rsp), %r12
jmp .L22
.L31:
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z10squareFuncPjS_PjS_
jmp .L17
.L34:
movq 568(%rsp), %rax
subq %fs:40, %rax
jne .L32
call _ZSt16__throw_bad_castv@PLT
.L32:
call __stack_chk_fail@PLT
.L20:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
.L21:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbp
cmpq $64, %rbp
je .L33
.L22:
movq %rbp, %rsi
movq %r14, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbx
movl $8, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl (%r12,%rbp,4), %esi
movq %rbx, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r15
testq %r15, %r15
je .L34
cmpb $0, 56(%r15)
je .L20
movzbl 67(%r15), %esi
jmp .L21
.L33:
call cudaDeviceSynchronize@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 568(%rsp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
addq $584, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z10squareFuncPjS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10squareFuncPjS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //============================================================================
// Name : cudaProg.cpp
// Author : Pratil
// Version :
// Copyright : Your copyright notice
// Description : Hello World in C++, Ansi-style
//============================================================================
#include <iostream>
#include <stdio.h>
using namespace std;
__global__ void squareFunc(unsigned int *d_in, unsigned int *d_out)
{
int idx = threadIdx.x;
unsigned int val = d_in[idx];
d_out[idx] = val * val;
//printf("%d square value %d \n ", idx, d_out[idx]);
}
int main()
{
const unsigned int arr_len = 64;
const unsigned int arr_size = 64 * sizeof(unsigned int);
unsigned int arr_in[arr_len];
unsigned int arr_out[arr_len];
for (unsigned int i = 0; i < 64; i++)
{
arr_in[i] = i;
cout << i << " : " << arr_in[i] << endl;
}
unsigned int *d_in;
unsigned int *d_out;
cudaMalloc((void**) &d_in, arr_size);
cudaMalloc((void**) &d_out, arr_size);
cudaMemcpy(d_in, arr_in, arr_size, cudaMemcpyHostToDevice);
squareFunc<<<1,64>>>(d_in, d_out);
cudaMemcpy(arr_out, d_out, arr_size, cudaMemcpyDeviceToHost);
for (unsigned int i = 0; i < 64; i++)
{
cout << i <<" : " << arr_out[i] << endl;
}
cudaDeviceSynchronize();
cudaFree(d_out);
cudaFree(d_in);
return 0;
} | //============================================================================
// Name : cudaProg.cpp
// Author : Pratil
// Version :
// Copyright : Your copyright notice
// Description : Hello World in C++, Ansi-style
//============================================================================
#include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
using namespace std;
__global__ void squareFunc(unsigned int *d_in, unsigned int *d_out)
{
int idx = threadIdx.x;
unsigned int val = d_in[idx];
d_out[idx] = val * val;
//printf("%d square value %d \n ", idx, d_out[idx]);
}
int main()
{
const unsigned int arr_len = 64;
const unsigned int arr_size = 64 * sizeof(unsigned int);
unsigned int arr_in[arr_len];
unsigned int arr_out[arr_len];
for (unsigned int i = 0; i < 64; i++)
{
arr_in[i] = i;
cout << i << " : " << arr_in[i] << endl;
}
unsigned int *d_in;
unsigned int *d_out;
hipMalloc((void**) &d_in, arr_size);
hipMalloc((void**) &d_out, arr_size);
hipMemcpy(d_in, arr_in, arr_size, hipMemcpyHostToDevice);
squareFunc<<<1,64>>>(d_in, d_out);
hipMemcpy(arr_out, d_out, arr_size, hipMemcpyDeviceToHost);
for (unsigned int i = 0; i < 64; i++)
{
cout << i <<" : " << arr_out[i] << endl;
}
hipDeviceSynchronize();
hipFree(d_out);
hipFree(d_in);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //============================================================================
// Name : cudaProg.cpp
// Author : Pratil
// Version :
// Copyright : Your copyright notice
// Description : Hello World in C++, Ansi-style
//============================================================================
#include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
using namespace std;
__global__ void squareFunc(unsigned int *d_in, unsigned int *d_out)
{
int idx = threadIdx.x;
unsigned int val = d_in[idx];
d_out[idx] = val * val;
//printf("%d square value %d \n ", idx, d_out[idx]);
}
int main()
{
const unsigned int arr_len = 64;
const unsigned int arr_size = 64 * sizeof(unsigned int);
unsigned int arr_in[arr_len];
unsigned int arr_out[arr_len];
for (unsigned int i = 0; i < 64; i++)
{
arr_in[i] = i;
cout << i << " : " << arr_in[i] << endl;
}
unsigned int *d_in;
unsigned int *d_out;
hipMalloc((void**) &d_in, arr_size);
hipMalloc((void**) &d_out, arr_size);
hipMemcpy(d_in, arr_in, arr_size, hipMemcpyHostToDevice);
squareFunc<<<1,64>>>(d_in, d_out);
hipMemcpy(arr_out, d_out, arr_size, hipMemcpyDeviceToHost);
for (unsigned int i = 0; i < 64; i++)
{
cout << i <<" : " << arr_out[i] << endl;
}
hipDeviceSynchronize();
hipFree(d_out);
hipFree(d_in);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10squareFuncPjS_
.globl _Z10squareFuncPjS_
.p2align 8
.type _Z10squareFuncPjS_,@function
_Z10squareFuncPjS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_mul_lo_u32 v1, v1, v1
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10squareFuncPjS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10squareFuncPjS_, .Lfunc_end0-_Z10squareFuncPjS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10squareFuncPjS_
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z10squareFuncPjS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //============================================================================
// Name : cudaProg.cpp
// Author : Pratil
// Version :
// Copyright : Your copyright notice
// Description : Hello World in C++, Ansi-style
//============================================================================
#include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
using namespace std;
__global__ void squareFunc(unsigned int *d_in, unsigned int *d_out)
{
int idx = threadIdx.x;
unsigned int val = d_in[idx];
d_out[idx] = val * val;
//printf("%d square value %d \n ", idx, d_out[idx]);
}
int main()
{
const unsigned int arr_len = 64;
const unsigned int arr_size = 64 * sizeof(unsigned int);
unsigned int arr_in[arr_len];
unsigned int arr_out[arr_len];
for (unsigned int i = 0; i < 64; i++)
{
arr_in[i] = i;
cout << i << " : " << arr_in[i] << endl;
}
unsigned int *d_in;
unsigned int *d_out;
hipMalloc((void**) &d_in, arr_size);
hipMalloc((void**) &d_out, arr_size);
hipMemcpy(d_in, arr_in, arr_size, hipMemcpyHostToDevice);
squareFunc<<<1,64>>>(d_in, d_out);
hipMemcpy(arr_out, d_out, arr_size, hipMemcpyDeviceToHost);
for (unsigned int i = 0; i < 64; i++)
{
cout << i <<" : " << arr_out[i] << endl;
}
hipDeviceSynchronize();
hipFree(d_out);
hipFree(d_in);
return 0;
} | .text
.file "squareOfNumbers.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z25__device_stub__squareFuncPjS_ # -- Begin function _Z25__device_stub__squareFuncPjS_
.p2align 4, 0x90
.type _Z25__device_stub__squareFuncPjS_,@function
_Z25__device_stub__squareFuncPjS_: # @_Z25__device_stub__squareFuncPjS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10squareFuncPjS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__squareFuncPjS_, .Lfunc_end0-_Z25__device_stub__squareFuncPjS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $592, %rsp # imm = 0x250
.cfi_def_cfa_offset 624
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %ebx, %ebx
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_4: # in Loop: Header=BB1_1 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_5: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_1 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %rbx
cmpq $64, %rbx
je .LBB1_6
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %ebx, 336(%rsp,%rbx,4)
movl $_ZSt4cout, %edi
movq %rbx, %rsi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %r14
movl $.L.str, %esi
movl $8, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 336(%rsp,%rbx,4), %esi
movq %r14, %rdi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_15
# %bb.2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_1 Depth=1
cmpb $0, 56(%r14)
je .LBB1_4
# %bb.3: # in Loop: Header=BB1_1 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB1_5
.LBB1_6:
leaq 8(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movq %rsp, %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movq 8(%rsp), %rdi
leaq 336(%rsp), %rsi
movl $256, %edx # imm = 0x100
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 63(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10squareFuncPjS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq (%rsp), %rsi
leaq 80(%rsp), %rdi
movl $256, %edx # imm = 0x100
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_12: # in Loop: Header=BB1_9 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_13: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit17
# in Loop: Header=BB1_9 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %rbx
cmpq $64, %rbx
je .LBB1_14
.LBB1_9: # =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movq %rbx, %rsi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %r14
movl $.L.str.1, %esi
movl $8, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 80(%rsp,%rbx,4), %esi
movq %r14, %rdi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_15
# %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i14
# in Loop: Header=BB1_9 Depth=1
cmpb $0, 56(%r14)
je .LBB1_12
# %bb.11: # in Loop: Header=BB1_9 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB1_13
.LBB1_14:
callq hipDeviceSynchronize
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $592, %rsp # imm = 0x250
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_15:
.cfi_def_cfa_offset 624
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10squareFuncPjS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10squareFuncPjS_,@object # @_Z10squareFuncPjS_
.section .rodata,"a",@progbits
.globl _Z10squareFuncPjS_
.p2align 3, 0x0
_Z10squareFuncPjS_:
.quad _Z25__device_stub__squareFuncPjS_
.size _Z10squareFuncPjS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " : "
.size .L.str, 9
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " : "
.size .L.str.1, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10squareFuncPjS_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__squareFuncPjS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10squareFuncPjS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10squareFuncPjS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x001fcc00078e0205 */
/*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0205 */
/*0070*/ IMAD R7, R2, R2, RZ ; /* 0x0000000202077224 */
/* 0x004fca00078e02ff */
/*0080*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10squareFuncPjS_
.globl _Z10squareFuncPjS_
.p2align 8
.type _Z10squareFuncPjS_,@function
_Z10squareFuncPjS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_mul_lo_u32 v1, v1, v1
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10squareFuncPjS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10squareFuncPjS_, .Lfunc_end0-_Z10squareFuncPjS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10squareFuncPjS_
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z10squareFuncPjS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a22d2_00000000-6_squareOfNumbers.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z10squareFuncPjS_PjS_
.type _Z32__device_stub__Z10squareFuncPjS_PjS_, @function
_Z32__device_stub__Z10squareFuncPjS_PjS_:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10squareFuncPjS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z32__device_stub__Z10squareFuncPjS_PjS_, .-_Z32__device_stub__Z10squareFuncPjS_PjS_
.globl _Z10squareFuncPjS_
.type _Z10squareFuncPjS_, @function
_Z10squareFuncPjS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10squareFuncPjS_PjS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z10squareFuncPjS_, .-_Z10squareFuncPjS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " : "
.LC1:
.string " : "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $584, %rsp
.cfi_def_cfa_offset 640
movq %fs:40, %rax
movq %rax, 568(%rsp)
xorl %eax, %eax
movl $0, %ebx
leaq 48(%rsp), %r12
leaq _ZSt4cout(%rip), %r14
leaq .LC0(%rip), %r13
jmp .L16
.L29:
movq 568(%rsp), %rax
subq %fs:40, %rax
jne .L27
call _ZSt16__throw_bad_castv@PLT
.L27:
call __stack_chk_fail@PLT
.L30:
movzbl 67(%r15), %esi
.L15:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbx
cmpq $64, %rbx
je .L28
.L16:
movl %ebx, (%r12,%rbx,4)
movq %rbx, %rsi
movq %r14, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbp
movl $8, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl (%r12,%rbx,4), %esi
movq %rbp, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L29
cmpb $0, 56(%r15)
jne .L30
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L15
.L28:
leaq 8(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $256, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $64, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L17:
leaq 304(%rsp), %rdi
movl $2, %ecx
movl $256, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebp
leaq _ZSt4cout(%rip), %r14
leaq .LC1(%rip), %r13
leaq 304(%rsp), %r12
jmp .L22
.L31:
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z10squareFuncPjS_PjS_
jmp .L17
.L34:
movq 568(%rsp), %rax
subq %fs:40, %rax
jne .L32
call _ZSt16__throw_bad_castv@PLT
.L32:
call __stack_chk_fail@PLT
.L20:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
.L21:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbp
cmpq $64, %rbp
je .L33
.L22:
movq %rbp, %rsi
movq %r14, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbx
movl $8, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl (%r12,%rbp,4), %esi
movq %rbx, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r15
testq %r15, %r15
je .L34
cmpb $0, 56(%r15)
je .L20
movzbl 67(%r15), %esi
jmp .L21
.L33:
call cudaDeviceSynchronize@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 568(%rsp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
addq $584, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z10squareFuncPjS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10squareFuncPjS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "squareOfNumbers.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z25__device_stub__squareFuncPjS_ # -- Begin function _Z25__device_stub__squareFuncPjS_
.p2align 4, 0x90
.type _Z25__device_stub__squareFuncPjS_,@function
_Z25__device_stub__squareFuncPjS_: # @_Z25__device_stub__squareFuncPjS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10squareFuncPjS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__squareFuncPjS_, .Lfunc_end0-_Z25__device_stub__squareFuncPjS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $592, %rsp # imm = 0x250
.cfi_def_cfa_offset 624
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %ebx, %ebx
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_4: # in Loop: Header=BB1_1 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_5: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_1 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %rbx
cmpq $64, %rbx
je .LBB1_6
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %ebx, 336(%rsp,%rbx,4)
movl $_ZSt4cout, %edi
movq %rbx, %rsi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %r14
movl $.L.str, %esi
movl $8, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 336(%rsp,%rbx,4), %esi
movq %r14, %rdi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_15
# %bb.2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_1 Depth=1
cmpb $0, 56(%r14)
je .LBB1_4
# %bb.3: # in Loop: Header=BB1_1 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB1_5
.LBB1_6:
leaq 8(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movq %rsp, %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movq 8(%rsp), %rdi
leaq 336(%rsp), %rsi
movl $256, %edx # imm = 0x100
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 63(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10squareFuncPjS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq (%rsp), %rsi
leaq 80(%rsp), %rdi
movl $256, %edx # imm = 0x100
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_12: # in Loop: Header=BB1_9 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_13: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit17
# in Loop: Header=BB1_9 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %rbx
cmpq $64, %rbx
je .LBB1_14
.LBB1_9: # =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movq %rbx, %rsi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %r14
movl $.L.str.1, %esi
movl $8, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 80(%rsp,%rbx,4), %esi
movq %r14, %rdi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_15
# %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i14
# in Loop: Header=BB1_9 Depth=1
cmpb $0, 56(%r14)
je .LBB1_12
# %bb.11: # in Loop: Header=BB1_9 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB1_13
.LBB1_14:
callq hipDeviceSynchronize
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $592, %rsp # imm = 0x250
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_15:
.cfi_def_cfa_offset 624
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10squareFuncPjS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10squareFuncPjS_,@object # @_Z10squareFuncPjS_
.section .rodata,"a",@progbits
.globl _Z10squareFuncPjS_
.p2align 3, 0x0
_Z10squareFuncPjS_:
.quad _Z25__device_stub__squareFuncPjS_
.size _Z10squareFuncPjS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " : "
.size .L.str, 9
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " : "
.size .L.str.1, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10squareFuncPjS_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__squareFuncPjS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10squareFuncPjS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <math.h>
#define DEG2RAD 0.0174532925
#define RAD2DEG 57.2957795
#define FT_PER_MIN_TO_M_PER_SEC 0.00508
// nvcc -Xcompiler -fPIC -shared propagator_cuda.cu -o propagator_cuda.so
__device__
inline size_t idx(size_t i, size_t y, size_t vec_len=3){
/* The numpy vectors are flattened for some reason. This fcn gives the correct index. */
return i*vec_len + y;
}
__global__
void propagate(int n, float *position, float *velocity, float dt,
float *turn_rate, float *climb_rate, float *heading){
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride){
float horizontal_speed = sqrt(velocity[idx(i,0)]*velocity[idx(i,0)] +
velocity[idx(i,1)]*velocity[idx(i,1)]);
heading[i] = atan2(velocity[idx(i,1)], velocity[idx(i,0)])
+ turn_rate[i] * dt * DEG2RAD;
velocity[idx(i, 0)] = cos(heading[i]) * horizontal_speed;
velocity[idx(i, 1)] = sin(heading[i]) * horizontal_speed;
velocity[idx(i, 2)] = climb_rate[i] * FT_PER_MIN_TO_M_PER_SEC;
position[idx(i, 0)] += velocity[idx(i, 0)] * dt;
position[idx(i, 1)] += velocity[idx(i, 1)] * dt;
position[idx(i, 2)] += velocity[idx(i, 2)] * dt;
}
}
extern "C" void propagate_cuda(float *position,
float *velocity,
float dt,
float *turn_rate,
float *climb_rate,
float *heading,
int fleet_size){
float *d_position, *d_velocity, *d_turn_rate, *d_climb_rate, *d_heading;
cudaMalloc(&d_position, fleet_size*3*sizeof(float));
cudaMalloc(&d_velocity, fleet_size*3*sizeof(float));
cudaMalloc(&d_turn_rate, fleet_size*sizeof(float));
cudaMalloc(&d_climb_rate, fleet_size*sizeof(float));
cudaMalloc(&d_heading, fleet_size*sizeof(float));
cudaMemcpy(d_position, position, fleet_size*3*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_velocity, velocity, fleet_size*3*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_turn_rate, turn_rate, fleet_size*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_climb_rate, climb_rate, fleet_size*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_heading, heading, fleet_size*sizeof(float), cudaMemcpyHostToDevice);
propagate<<<1, 1>>>(fleet_size, d_position, d_velocity, dt, d_turn_rate,
d_climb_rate, d_heading);
cudaDeviceSynchronize();
cudaMemcpy(position, d_position, fleet_size*3*sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(velocity, d_velocity, fleet_size*3*sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(turn_rate, d_turn_rate, fleet_size*sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(climb_rate, d_climb_rate, fleet_size*sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(heading, d_heading, fleet_size*sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(position);
cudaFree(velocity);
cudaFree(turn_rate);
cudaFree(climb_rate);
cudaFree(heading);
return;
} | .file "tmpxft_00139b0b_00000000-6_propagator_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z9propagateiPfS_fS_S_S_iPfS_fS_S_S_
.type _Z38__device_stub__Z9propagateiPfS_fS_S_S_iPfS_fS_S_S_, @function
_Z38__device_stub__Z9propagateiPfS_fS_S_S_iPfS_fS_S_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movss %xmm0, 40(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9propagateiPfS_fS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z38__device_stub__Z9propagateiPfS_fS_S_S_iPfS_fS_S_S_, .-_Z38__device_stub__Z9propagateiPfS_fS_S_S_iPfS_fS_S_S_
.globl _Z9propagateiPfS_fS_S_S_
.type _Z9propagateiPfS_fS_S_S_, @function
_Z9propagateiPfS_fS_S_S_:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z9propagateiPfS_fS_S_S_iPfS_fS_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z9propagateiPfS_fS_S_S_, .-_Z9propagateiPfS_fS_S_S_
.globl propagate_cuda
.type propagate_cuda, @function
propagate_cuda:
.LFB2028:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rdi, %r15
movq %rsi, %r14
movss %xmm0, 28(%rsp)
movq %rdx, %r13
movq %rcx, 8(%rsp)
movq %r8, 16(%rsp)
movl %r9d, %r12d
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leal (%r9,%r9,2), %ebp
movslq %ebp, %rbp
salq $2, %rbp
leaq 40(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movslq %r12d, %rbx
salq $2, %rbx
leaq 56(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r15, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r14, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 40(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 48(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 56(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 64(%rsp), %rsi
movq 8(%rsp), %rbp
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 72(%rsp), %rsi
movq 16(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %r15, %rdi
call cudaFree@PLT
movq %r14, %rdi
call cudaFree@PLT
movq %r13, %rdi
call cudaFree@PLT
movq %rbp, %rdi
call cudaFree@PLT
movq %rbx, %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 72(%rsp), %r9
movq 64(%rsp), %r8
movq 56(%rsp), %rcx
movss 28(%rsp), %xmm0
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movl %r12d, %edi
call _Z38__device_stub__Z9propagateiPfS_fS_S_S_iPfS_fS_S_S_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2028:
.size propagate_cuda, .-propagate_cuda
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9propagateiPfS_fS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9propagateiPfS_fS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <math.h>
#define DEG2RAD 0.0174532925
#define RAD2DEG 57.2957795
#define FT_PER_MIN_TO_M_PER_SEC 0.00508
// nvcc -Xcompiler -fPIC -shared propagator_cuda.cu -o propagator_cuda.so
__device__
inline size_t idx(size_t i, size_t y, size_t vec_len=3){
/* The numpy vectors are flattened for some reason. This fcn gives the correct index. */
return i*vec_len + y;
}
__global__
void propagate(int n, float *position, float *velocity, float dt,
float *turn_rate, float *climb_rate, float *heading){
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride){
float horizontal_speed = sqrt(velocity[idx(i,0)]*velocity[idx(i,0)] +
velocity[idx(i,1)]*velocity[idx(i,1)]);
heading[i] = atan2(velocity[idx(i,1)], velocity[idx(i,0)])
+ turn_rate[i] * dt * DEG2RAD;
velocity[idx(i, 0)] = cos(heading[i]) * horizontal_speed;
velocity[idx(i, 1)] = sin(heading[i]) * horizontal_speed;
velocity[idx(i, 2)] = climb_rate[i] * FT_PER_MIN_TO_M_PER_SEC;
position[idx(i, 0)] += velocity[idx(i, 0)] * dt;
position[idx(i, 1)] += velocity[idx(i, 1)] * dt;
position[idx(i, 2)] += velocity[idx(i, 2)] * dt;
}
}
extern "C" void propagate_cuda(float *position,
float *velocity,
float dt,
float *turn_rate,
float *climb_rate,
float *heading,
int fleet_size){
float *d_position, *d_velocity, *d_turn_rate, *d_climb_rate, *d_heading;
cudaMalloc(&d_position, fleet_size*3*sizeof(float));
cudaMalloc(&d_velocity, fleet_size*3*sizeof(float));
cudaMalloc(&d_turn_rate, fleet_size*sizeof(float));
cudaMalloc(&d_climb_rate, fleet_size*sizeof(float));
cudaMalloc(&d_heading, fleet_size*sizeof(float));
cudaMemcpy(d_position, position, fleet_size*3*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_velocity, velocity, fleet_size*3*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_turn_rate, turn_rate, fleet_size*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_climb_rate, climb_rate, fleet_size*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_heading, heading, fleet_size*sizeof(float), cudaMemcpyHostToDevice);
propagate<<<1, 1>>>(fleet_size, d_position, d_velocity, dt, d_turn_rate,
d_climb_rate, d_heading);
cudaDeviceSynchronize();
cudaMemcpy(position, d_position, fleet_size*3*sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(velocity, d_velocity, fleet_size*3*sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(turn_rate, d_turn_rate, fleet_size*sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(climb_rate, d_climb_rate, fleet_size*sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(heading, d_heading, fleet_size*sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(position);
cudaFree(velocity);
cudaFree(turn_rate);
cudaFree(climb_rate);
cudaFree(heading);
return;
} | #include <hip/hip_runtime.h>
#include <math.h>
#define DEG2RAD 0.0174532925
#define RAD2DEG 57.2957795
#define FT_PER_MIN_TO_M_PER_SEC 0.00508
// nvcc -Xcompiler -fPIC -shared propagator_cuda.cu -o propagator_cuda.so
__device__
inline size_t idx(size_t i, size_t y, size_t vec_len=3){
/* The numpy vectors are flattened for some reason. This fcn gives the correct index. */
return i*vec_len + y;
}
__global__
void propagate(int n, float *position, float *velocity, float dt,
float *turn_rate, float *climb_rate, float *heading){
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride){
float horizontal_speed = sqrt(velocity[idx(i,0)]*velocity[idx(i,0)] +
velocity[idx(i,1)]*velocity[idx(i,1)]);
heading[i] = atan2(velocity[idx(i,1)], velocity[idx(i,0)])
+ turn_rate[i] * dt * DEG2RAD;
velocity[idx(i, 0)] = cos(heading[i]) * horizontal_speed;
velocity[idx(i, 1)] = sin(heading[i]) * horizontal_speed;
velocity[idx(i, 2)] = climb_rate[i] * FT_PER_MIN_TO_M_PER_SEC;
position[idx(i, 0)] += velocity[idx(i, 0)] * dt;
position[idx(i, 1)] += velocity[idx(i, 1)] * dt;
position[idx(i, 2)] += velocity[idx(i, 2)] * dt;
}
}
extern "C" void propagate_cuda(float *position,
float *velocity,
float dt,
float *turn_rate,
float *climb_rate,
float *heading,
int fleet_size){
float *d_position, *d_velocity, *d_turn_rate, *d_climb_rate, *d_heading;
hipMalloc(&d_position, fleet_size*3*sizeof(float));
hipMalloc(&d_velocity, fleet_size*3*sizeof(float));
hipMalloc(&d_turn_rate, fleet_size*sizeof(float));
hipMalloc(&d_climb_rate, fleet_size*sizeof(float));
hipMalloc(&d_heading, fleet_size*sizeof(float));
hipMemcpy(d_position, position, fleet_size*3*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_velocity, velocity, fleet_size*3*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_turn_rate, turn_rate, fleet_size*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_climb_rate, climb_rate, fleet_size*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_heading, heading, fleet_size*sizeof(float), hipMemcpyHostToDevice);
propagate<<<1, 1>>>(fleet_size, d_position, d_velocity, dt, d_turn_rate,
d_climb_rate, d_heading);
hipDeviceSynchronize();
hipMemcpy(position, d_position, fleet_size*3*sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(velocity, d_velocity, fleet_size*3*sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(turn_rate, d_turn_rate, fleet_size*sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(climb_rate, d_climb_rate, fleet_size*sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(heading, d_heading, fleet_size*sizeof(float), hipMemcpyDeviceToHost);
hipFree(position);
hipFree(velocity);
hipFree(turn_rate);
hipFree(climb_rate);
hipFree(heading);
return;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <math.h>
#define DEG2RAD 0.0174532925
#define RAD2DEG 57.2957795
#define FT_PER_MIN_TO_M_PER_SEC 0.00508
// nvcc -Xcompiler -fPIC -shared propagator_cuda.cu -o propagator_cuda.so
__device__
inline size_t idx(size_t i, size_t y, size_t vec_len=3){
/* The numpy vectors are flattened for some reason. This fcn gives the correct index. */
return i*vec_len + y;
}
__global__
void propagate(int n, float *position, float *velocity, float dt,
float *turn_rate, float *climb_rate, float *heading){
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride){
float horizontal_speed = sqrt(velocity[idx(i,0)]*velocity[idx(i,0)] +
velocity[idx(i,1)]*velocity[idx(i,1)]);
heading[i] = atan2(velocity[idx(i,1)], velocity[idx(i,0)])
+ turn_rate[i] * dt * DEG2RAD;
velocity[idx(i, 0)] = cos(heading[i]) * horizontal_speed;
velocity[idx(i, 1)] = sin(heading[i]) * horizontal_speed;
velocity[idx(i, 2)] = climb_rate[i] * FT_PER_MIN_TO_M_PER_SEC;
position[idx(i, 0)] += velocity[idx(i, 0)] * dt;
position[idx(i, 1)] += velocity[idx(i, 1)] * dt;
position[idx(i, 2)] += velocity[idx(i, 2)] * dt;
}
}
extern "C" void propagate_cuda(float *position,
float *velocity,
float dt,
float *turn_rate,
float *climb_rate,
float *heading,
int fleet_size){
float *d_position, *d_velocity, *d_turn_rate, *d_climb_rate, *d_heading;
hipMalloc(&d_position, fleet_size*3*sizeof(float));
hipMalloc(&d_velocity, fleet_size*3*sizeof(float));
hipMalloc(&d_turn_rate, fleet_size*sizeof(float));
hipMalloc(&d_climb_rate, fleet_size*sizeof(float));
hipMalloc(&d_heading, fleet_size*sizeof(float));
hipMemcpy(d_position, position, fleet_size*3*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_velocity, velocity, fleet_size*3*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_turn_rate, turn_rate, fleet_size*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_climb_rate, climb_rate, fleet_size*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_heading, heading, fleet_size*sizeof(float), hipMemcpyHostToDevice);
propagate<<<1, 1>>>(fleet_size, d_position, d_velocity, dt, d_turn_rate,
d_climb_rate, d_heading);
hipDeviceSynchronize();
hipMemcpy(position, d_position, fleet_size*3*sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(velocity, d_velocity, fleet_size*3*sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(turn_rate, d_turn_rate, fleet_size*sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(climb_rate, d_climb_rate, fleet_size*sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(heading, d_heading, fleet_size*sizeof(float), hipMemcpyDeviceToHost);
hipFree(position);
hipFree(velocity);
hipFree(turn_rate);
hipFree(climb_rate);
hipFree(heading);
return;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9propagateiPfS_fS_S_S_
.globl _Z9propagateiPfS_fS_S_S_
.p2align 8
.type _Z9propagateiPfS_fS_S_S_,@function
_Z9propagateiPfS_fS_S_S_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x44
s_load_b32 s20, s[0:1], 0x0
s_add_u32 s2, s0, 56
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s14, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s14, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s20, v1
s_cbranch_execz .LBB0_11
s_load_b32 s16, s[2:3], 0x0
s_clause 0x3
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b32 s21, s[0:1], 0x18
s_load_b128 s[8:11], s[0:1], 0x20
s_load_b64 s[2:3], s[0:1], 0x30
v_ashrrev_i32_e32 v2, 31, v1
v_mad_i64_i32 v[3:4], null, v1, 12, 0
v_mov_b32_e32 v0, 0x4016cbe4
s_mov_b32 s22, 0
s_delay_alu instid0(VALU_DEP_3)
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_mov_b32 s23, 0x3b2d2a58
s_mov_b32 s13, 0x3f91df46
s_mov_b32 s12, 0xa1fae711
s_mov_b32 s24, 0x7fffff
s_mov_b32 s25, 0xb94c1982
s_mov_b32 s26, 0x37d75334
s_mov_b32 s15, 0x3f74cec4
s_waitcnt lgkmcnt(0)
s_mul_i32 s16, s16, s14
s_mov_b32 s14, 0x1dd1a21f
s_ashr_i32 s17, s16, 31
s_mul_hi_i32 s27, s16, 12
s_mul_i32 s28, s16, 12
s_lshl_b64 s[18:19], s[16:17], 2
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_dual_mul_f32 v14, v12, v12 :: v_dual_and_b32 v17, 1, v13
v_xor_b32_e32 v11, v11, v10
v_lshlrev_b32_e32 v13, 30, v13
v_add_nc_u32_e32 v1, s16, v1
v_fmaak_f32 v15, s25, v14, 0x3c0881c4
v_cmp_eq_u32_e32 vcc_lo, 0, v17
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_and_b32_e32 v13, 0x80000000, v13
v_fmaak_f32 v15, v14, v15, 0xbe2aaa9d
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmaak_f32 v16, s26, v14, 0xbab64f3b :: v_dual_mul_f32 v15, v14, v15
v_fmaak_f32 v16, v14, v16, 0x3d2aabf7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v12, v12, v15
v_fmaak_f32 v16, v14, v16, 0xbf000004
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v14, v14, v16, 1.0
v_cndmask_b32_e32 v12, v14, v12, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v10, 0x1f8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor3_b32 v11, v11, v13, v12
v_cndmask_b32_e32 v10, 0x7fc00000, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v11, v9, v10
v_add_co_u32 v9, vcc_lo, s10, v5
v_add_co_ci_u32_e32 v10, vcc_lo, s11, v6, vcc_lo
global_store_b32 v[7:8], v11, off offset:4
v_add_co_u32 v12, vcc_lo, s6, v3
global_load_b32 v9, v[9:10], off
v_add_co_ci_u32_e32 v13, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v14, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v15, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, v5, s18
v_add_co_ci_u32_e32 v6, vcc_lo, s19, v6, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s20, v1
s_add_u32 s6, s6, s28
s_addc_u32 s7, s7, s27
s_add_u32 s4, s4, s28
s_addc_u32 s5, s5, s27
s_or_b32 s22, vcc_lo, s22
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[9:10], v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[9:10], v[9:10], s[14:15]
v_cvt_f32_f64_e32 v9, v[9:10]
global_store_b32 v[12:13], v9, off offset:8
global_load_b96 v[9:11], v[14:15], off
s_waitcnt vmcnt(0)
v_fma_f32 v2, s21, v2, v9
global_store_b32 v[14:15], v2, off
global_load_b32 v2, v[7:8], off offset:4
s_waitcnt vmcnt(0)
v_fma_f32 v2, s21, v2, v10
global_store_b32 v[14:15], v2, off offset:4
global_load_b32 v2, v[12:13], off offset:8
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v11, s21, v2
global_store_b32 v[14:15], v11, off offset:8
s_and_not1_b32 exec_lo, exec_lo, s22
s_cbranch_execz .LBB0_11
.LBB0_3:
v_add_co_u32 v7, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v11, vcc_lo, s8, v5
v_add_co_ci_u32_e32 v12, vcc_lo, s9, v6, vcc_lo
global_load_b64 v[9:10], v[7:8], off
global_load_b32 v2, v[11:12], off
s_waitcnt vmcnt(1)
v_max_f32_e64 v11, |v10|, |v10|
v_max_f32_e64 v12, |v9|, |v9|
v_cmp_gt_i32_e64 s0, 0, v9
v_cmp_gt_f32_e64 vcc_lo, |v10|, |v9|
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s21, v2
v_cmp_class_f32_e64 s1, v10, 0x204
v_max_f32_e32 v13, v12, v11
v_min_f32_e32 v11, v12, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_frexp_mant_f32_e32 v14, v13
v_frexp_exp_i32_f32_e32 v13, v13
v_rcp_f32_e32 v12, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_frexp_exp_i32_f32_e32 v14, v11
v_frexp_mant_f32_e32 v11, v11
v_sub_nc_u32_e32 v13, v14, v13
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v11, v11, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f32 v11, v11, v13
v_mul_f32_e32 v12, v11, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v13, s23, v12, 0xbc7a590c
v_fmaak_f32 v13, v12, v13, 0x3d29fb3f
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v13, v12, v13, 0xbd97d4d7
v_fmaak_f32 v13, v12, v13, 0x3dd931b2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v13, v12, v13, 0xbe1160e6
v_fmaak_f32 v13, v12, v13, 0x3e4cb8bf
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v13, v12, v13, 0xbeaaaa62
v_mul_f32_e32 v12, v12, v13
v_cndmask_b32_e64 v13, 0, 0x40490fdb, s0
v_cmp_class_f32_e64 s0, v9, 0x204
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v11, v11, v12
v_sub_f32_e32 v12, 0x3fc90fdb, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v11, v11, v12, vcc_lo
v_cmp_gt_f32_e32 vcc_lo, 0, v9
v_sub_f32_e32 v12, 0x40490fdb, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v11, v11, v12, vcc_lo
v_cndmask_b32_e32 v12, 0x3f490fdb, v0, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, 0, v10
v_cndmask_b32_e32 v11, v11, v13, vcc_lo
s_and_b32 vcc_lo, s0, s1
v_cvt_f64_f32_e32 v[13:14], v2
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v11, v11, v12, vcc_lo
v_cmp_o_f32_e32 vcc_lo, v9, v10
v_cndmask_b32_e32 v11, 0x7fc00000, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_bfi_b32 v11, 0x7fffffff, v11, v10
v_cvt_f64_f32_e32 v[11:12], v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], v[13:14], s[12:13], v[11:12]
v_cvt_f32_f64_e32 v2, v[11:12]
v_add_co_u32 v11, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v6, vcc_lo
global_store_b32 v[11:12], v2, off
v_cmpx_ngt_f32_e64 0x48000000, |v2|
s_xor_b32 s17, exec_lo, s1
s_cbranch_execz .LBB0_5
v_dual_mov_b32 v15, 0 :: v_dual_and_b32 v20, 0x7fffffff, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_and_or_b32 v23, v20, s24, 0x800000
v_lshrrev_b32_e32 v20, 23, v20
v_mad_u64_u32 v[13:14], null, v23, 0xfe5163ab, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v21, 0xffffff88, v20
v_cmp_lt_u32_e32 vcc_lo, 63, v21
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[16:17], null, v23, 0x3c439041, v[14:15]
v_cndmask_b32_e64 v22, 0, 0xffffffc0, vcc_lo
v_mov_b32_e32 v14, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v22, v22, v21
v_mad_u64_u32 v[17:18], null, v23, 0xdb629599, v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_u32_e64 s0, 31, v22
v_cndmask_b32_e64 v24, 0, 0xffffffe0, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v14, v18 :: v_dual_cndmask_b32 v13, v17, v13
v_add_nc_u32_e32 v24, v24, v22
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[18:19], null, v23, 0xf534ddc0, v[14:15]
v_cmp_lt_u32_e64 s1, 31, v24
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mov_b32_e32 v14, v19
v_cndmask_b32_e32 v16, v18, v16, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[19:20], null, v23, 0xfc2757d1, v[14:15]
v_cndmask_b32_e64 v13, v16, v13, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v14, v20
v_mad_u64_u32 v[20:21], null, v23, 0x4e441529, v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v14, v21
v_mad_u64_u32 v[21:22], null, v23, 0xa2f9836e, v[14:15]
v_cndmask_b32_e64 v14, 0, 0xffffffe0, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v15, v20, v18 :: v_dual_add_nc_u32 v14, v14, v24
v_dual_cndmask_b32 v21, v21, v19 :: v_dual_cndmask_b32 v20, v22, v20
v_cndmask_b32_e32 v19, v19, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u32_e32 vcc_lo, 0, v14
v_cndmask_b32_e64 v18, v21, v15, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v20, v20, v21, s0
v_cndmask_b32_e64 v15, v15, v19, s0
v_sub_nc_u32_e32 v21, 32, v14
v_cndmask_b32_e64 v19, v19, v16, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v20, v20, v18, s1
v_cndmask_b32_e64 v18, v18, v15, s1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v15, v15, v19, s1
v_cndmask_b32_e64 v13, v19, v13, s1
v_alignbit_b32 v22, v20, v18, v21
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_alignbit_b32 v17, v18, v15, v21
v_cndmask_b32_e32 v14, v22, v20, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v20, v15, v13, v21
v_cndmask_b32_e32 v16, v17, v18, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_bfe_u32 v17, v14, 29, 1
v_cndmask_b32_e32 v15, v20, v15, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v18, v14, v16, 30
v_sub_nc_u32_e32 v19, 0, v17
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_alignbit_b32 v16, v16, v15, 30
v_alignbit_b32 v13, v15, v13, 30
v_xor_b32_e32 v18, v18, v19
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v15, v16, v19
v_xor_b32_e32 v13, v13, v19
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_clz_i32_u32_e32 v20, v18
v_min_u32_e32 v20, 32, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v16, 31, v20
v_lshlrev_b32_e32 v22, 23, v20
v_alignbit_b32 v18, v18, v15, v16
v_alignbit_b32 v13, v15, v13, v16
v_lshrrev_b32_e32 v16, 29, v14
v_lshrrev_b32_e32 v14, 30, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v15, v18, v13, 9
v_lshlrev_b32_e32 v16, 31, v16
v_lshrrev_b32_e32 v18, 9, v18
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v14, v17, v14
v_clz_i32_u32_e32 v19, v15
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v21, 0.5, v16
v_min_u32_e32 v19, 32, v19
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v21, v21, v22
v_sub_nc_u32_e32 v23, 31, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v13, v15, v13, v23
v_or_b32_e32 v15, v18, v21
v_add_lshl_u32 v18, v19, v20, 23
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v13, 9, v13
v_mul_f32_e32 v19, 0x3fc90fda, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v13, v13, v18
v_fma_f32 v18, v15, 0x3fc90fda, -v19
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v13, 0x33000000, v13
v_fmac_f32_e32 v18, 0x33a22168, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v13, v13, v16
v_fmac_f32_e32 v18, 0x3fc90fda, v13
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v13, v19, v18
.LBB0_5:
s_and_not1_saveexec_b32 s0, s17
v_mul_f32_e64 v13, 0x3f22f983, |v2|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v14, v13
v_fma_f32 v13, v14, 0xbfc90fda, |v2|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v13, 0xb3a22168, v14
v_fmac_f32_e32 v13, 0xa7c234c4, v14
v_cvt_i32_f32_e32 v14, v14
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_mul_f32 v10, v10, v10 :: v_dual_mul_f32 v15, v13, v13
s_mov_b32 s1, exec_lo
v_and_b32_e32 v21, 1, v14
v_lshlrev_b32_e32 v14, 30, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_fmac_f32 v10, v9, v9 :: v_dual_fmaak_f32 v17, s26, v15, 0xbab64f3b
v_fmaak_f32 v16, s25, v15, 0x3c0881c4
v_and_b32_e32 v14, 0x80000000, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v10
v_fmaak_f32 v17, v15, v17, 0x3d2aabf7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v16, v15, v16, 0xbe2aaa9d
v_dual_mul_f32 v9, 0x4f800000, v10 :: v_dual_mul_f32 v16, v15, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v9, v10, v9, vcc_lo
v_fmac_f32_e32 v13, v13, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v10, v9
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v18, -1, v10
v_add_nc_u32_e32 v19, 1, v10
v_fma_f32 v20, -v18, v10, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v22, -v19, v10, v9
v_cmp_ge_f32_e64 s0, 0, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v10, v10, v18, s0
v_cmp_lt_f32_e64 s0, 0, v22
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v10, v10, v19, s0
v_fmaak_f32 v17, v15, v17, 0xbf000004
v_cmp_eq_u32_e64 s0, 0, v21
v_fma_f32 v15, v15, v17, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v13, -v13, v15, s0
v_mul_f32_e32 v15, 0x37800000, v10
v_xor_b32_e32 v13, v14, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v10, v10, v15, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v2, 0x1f8
v_cndmask_b32_e32 v2, 0x7fc00000, v13, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v9, 0x260
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v9, v10, v9, vcc_lo
v_mul_f32_e32 v2, v9, v2
global_store_b32 v[7:8], v2, off
global_load_b32 v10, v[11:12], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v11, 0x7fffffff, v10
v_cmpx_ngt_f32_e64 0x48000000, |v10|
s_xor_b32 s17, exec_lo, s1
s_cbranch_execz .LBB0_9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_and_or_b32 v22, v11, s24, 0x800000
v_mov_b32_e32 v14, 0
v_lshrrev_b32_e32 v19, 23, v11
v_mad_u64_u32 v[12:13], null, v22, 0xfe5163ab, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v20, 0xffffff88, v19
v_cmp_lt_u32_e32 vcc_lo, 63, v20
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[15:16], null, v22, 0x3c439041, v[13:14]
v_cndmask_b32_e64 v21, 0, 0xffffffc0, vcc_lo
v_mov_b32_e32 v13, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v21, v21, v20
v_mad_u64_u32 v[16:17], null, v22, 0xdb629599, v[13:14]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_u32_e64 s0, 31, v21
v_cndmask_b32_e64 v23, 0, 0xffffffe0, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v13, v17 :: v_dual_cndmask_b32 v12, v16, v12
v_add_nc_u32_e32 v23, v23, v21
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[17:18], null, v22, 0xf534ddc0, v[13:14]
v_cmp_lt_u32_e64 s1, 31, v23
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mov_b32_e32 v13, v18
v_cndmask_b32_e32 v15, v17, v15, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[18:19], null, v22, 0xfc2757d1, v[13:14]
v_cndmask_b32_e64 v12, v15, v12, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v13, v19
v_mad_u64_u32 v[19:20], null, v22, 0x4e441529, v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v13, v20
v_mad_u64_u32 v[20:21], null, v22, 0xa2f9836e, v[13:14]
v_cndmask_b32_e64 v13, 0, 0xffffffe0, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v14, v19, v17 :: v_dual_add_nc_u32 v13, v13, v23
v_dual_cndmask_b32 v20, v20, v18 :: v_dual_cndmask_b32 v19, v21, v19
v_cndmask_b32_e32 v18, v18, v16, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u32_e32 vcc_lo, 0, v13
v_cndmask_b32_e64 v17, v20, v14, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v19, v19, v20, s0
v_cndmask_b32_e64 v14, v14, v18, s0
v_sub_nc_u32_e32 v20, 32, v13
v_cndmask_b32_e64 v18, v18, v15, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v19, v19, v17, s1
v_cndmask_b32_e64 v17, v17, v14, s1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v14, v14, v18, s1
v_cndmask_b32_e64 v12, v18, v12, s1
v_alignbit_b32 v21, v19, v17, v20
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_alignbit_b32 v16, v17, v14, v20
v_cndmask_b32_e32 v13, v21, v19, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v19, v14, v12, v20
v_cndmask_b32_e32 v15, v16, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_bfe_u32 v16, v13, 29, 1
v_cndmask_b32_e32 v14, v19, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v17, v13, v15, 30
v_sub_nc_u32_e32 v18, 0, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_alignbit_b32 v15, v15, v14, 30
v_alignbit_b32 v12, v14, v12, 30
v_xor_b32_e32 v17, v17, v18
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v14, v15, v18
v_xor_b32_e32 v12, v12, v18
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_clz_i32_u32_e32 v19, v17
v_min_u32_e32 v19, 32, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v15, 31, v19
v_lshlrev_b32_e32 v21, 23, v19
v_alignbit_b32 v17, v17, v14, v15
v_alignbit_b32 v12, v14, v12, v15
v_lshrrev_b32_e32 v15, 29, v13
v_lshrrev_b32_e32 v13, 30, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v14, v17, v12, 9
v_lshlrev_b32_e32 v15, 31, v15
v_lshrrev_b32_e32 v17, 9, v17
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v13, v16, v13
v_clz_i32_u32_e32 v18, v14
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v20, 0.5, v15
v_min_u32_e32 v18, 32, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v20, v20, v21
v_sub_nc_u32_e32 v22, 31, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v12, v14, v12, v22
v_or_b32_e32 v14, v17, v20
v_add_lshl_u32 v17, v18, v19, 23
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v12, 9, v12
v_mul_f32_e32 v18, 0x3fc90fda, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v12, v12, v17
v_fma_f32 v17, v14, 0x3fc90fda, -v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v12, 0x33000000, v12
v_fmac_f32_e32 v17, 0x33a22168, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v12, v12, v15
v_fmac_f32_e32 v17, 0x3fc90fda, v12
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v12, v18, v17
.LBB0_9:
s_and_not1_saveexec_b32 s0, s17
s_cbranch_execz .LBB0_2
v_mul_f32_e64 v12, 0x3f22f983, |v10|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v13, v12
v_fma_f32 v12, v13, 0xbfc90fda, |v10|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v12, 0xb3a22168, v13
v_fmac_f32_e32 v12, 0xa7c234c4, v13
v_cvt_i32_f32_e32 v13, v13
s_branch .LBB0_2
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9propagateiPfS_fS_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 25
.amdhsa_next_free_sgpr 29
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9propagateiPfS_fS_S_S_, .Lfunc_end0-_Z9propagateiPfS_fS_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9propagateiPfS_fS_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 31
.sgpr_spill_count: 0
.symbol: _Z9propagateiPfS_fS_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 25
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <math.h>
#define DEG2RAD 0.0174532925
#define RAD2DEG 57.2957795
#define FT_PER_MIN_TO_M_PER_SEC 0.00508
// nvcc -Xcompiler -fPIC -shared propagator_cuda.cu -o propagator_cuda.so
__device__
inline size_t idx(size_t i, size_t y, size_t vec_len=3){
/* The numpy vectors are flattened for some reason. This fcn gives the correct index. */
return i*vec_len + y;
}
__global__
void propagate(int n, float *position, float *velocity, float dt,
float *turn_rate, float *climb_rate, float *heading){
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride){
float horizontal_speed = sqrt(velocity[idx(i,0)]*velocity[idx(i,0)] +
velocity[idx(i,1)]*velocity[idx(i,1)]);
heading[i] = atan2(velocity[idx(i,1)], velocity[idx(i,0)])
+ turn_rate[i] * dt * DEG2RAD;
velocity[idx(i, 0)] = cos(heading[i]) * horizontal_speed;
velocity[idx(i, 1)] = sin(heading[i]) * horizontal_speed;
velocity[idx(i, 2)] = climb_rate[i] * FT_PER_MIN_TO_M_PER_SEC;
position[idx(i, 0)] += velocity[idx(i, 0)] * dt;
position[idx(i, 1)] += velocity[idx(i, 1)] * dt;
position[idx(i, 2)] += velocity[idx(i, 2)] * dt;
}
}
extern "C" void propagate_cuda(float *position,
float *velocity,
float dt,
float *turn_rate,
float *climb_rate,
float *heading,
int fleet_size){
float *d_position, *d_velocity, *d_turn_rate, *d_climb_rate, *d_heading;
hipMalloc(&d_position, fleet_size*3*sizeof(float));
hipMalloc(&d_velocity, fleet_size*3*sizeof(float));
hipMalloc(&d_turn_rate, fleet_size*sizeof(float));
hipMalloc(&d_climb_rate, fleet_size*sizeof(float));
hipMalloc(&d_heading, fleet_size*sizeof(float));
hipMemcpy(d_position, position, fleet_size*3*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_velocity, velocity, fleet_size*3*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_turn_rate, turn_rate, fleet_size*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_climb_rate, climb_rate, fleet_size*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_heading, heading, fleet_size*sizeof(float), hipMemcpyHostToDevice);
propagate<<<1, 1>>>(fleet_size, d_position, d_velocity, dt, d_turn_rate,
d_climb_rate, d_heading);
hipDeviceSynchronize();
hipMemcpy(position, d_position, fleet_size*3*sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(velocity, d_velocity, fleet_size*3*sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(turn_rate, d_turn_rate, fleet_size*sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(climb_rate, d_climb_rate, fleet_size*sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(heading, d_heading, fleet_size*sizeof(float), hipMemcpyDeviceToHost);
hipFree(position);
hipFree(velocity);
hipFree(turn_rate);
hipFree(climb_rate);
hipFree(heading);
return;
} | .text
.file "propagator_cuda.hip"
.globl _Z24__device_stub__propagateiPfS_fS_S_S_ # -- Begin function _Z24__device_stub__propagateiPfS_fS_S_S_
.p2align 4, 0x90
.type _Z24__device_stub__propagateiPfS_fS_S_S_,@function
_Z24__device_stub__propagateiPfS_fS_S_S_: # @_Z24__device_stub__propagateiPfS_fS_S_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 4(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movss %xmm0, (%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9propagateiPfS_fS_S_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z24__device_stub__propagateiPfS_fS_S_S_, .Lfunc_end0-_Z24__device_stub__propagateiPfS_fS_S_S_
.cfi_endproc
# -- End function
.globl propagate_cuda # -- Begin function propagate_cuda
.p2align 4, 0x90
.type propagate_cuda,@function
propagate_cuda: # @propagate_cuda
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %ebp
movq %r8, 56(%rsp) # 8-byte Spill
movq %rcx, %r12
movq %rdx, %r13
movss %xmm0, 44(%rsp) # 4-byte Spill
movq %rsi, %r14
movq %rdi, %r15
leal (%rbp,%rbp,2), %eax
movslq %eax, %rbx
shlq $2, %rbx
leaq 32(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq %rbp, 64(%rsp) # 8-byte Spill
movslq %ebp, %rbp
shlq $2, %rbp
leaq 16(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %rbp, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq %r15, 72(%rsp) # 8-byte Spill
movq %r15, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %r14, 80(%rsp) # 8-byte Spill
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r13, 88(%rsp) # 8-byte Spill
movq %r13, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %r12, 96(%rsp) # 8-byte Spill
movq %r12, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movq 56(%rsp), %rsi # 8-byte Reload
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
movq 64(%rsp), %r8 # 8-byte Reload
movl %r8d, 52(%rsp)
movq %rax, 184(%rsp)
movq %rcx, 176(%rsp)
movss 44(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 48(%rsp)
movq %rdx, 168(%rsp)
movq %rsi, 160(%rsp)
movq %rdi, 152(%rsp)
leaq 52(%rsp), %rax
movq %rax, 192(%rsp)
leaq 184(%rsp), %rax
movq %rax, 200(%rsp)
leaq 176(%rsp), %rax
movq %rax, 208(%rsp)
leaq 48(%rsp), %rax
movq %rax, 216(%rsp)
leaq 168(%rsp), %rax
movq %rax, 224(%rsp)
leaq 160(%rsp), %rax
movq %rax, 232(%rsp)
leaq 152(%rsp), %rax
movq %rax, 240(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 192(%rsp), %r9
movl $_Z9propagateiPfS_fS_S_S_, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movq 32(%rsp), %rsi
movq 72(%rsp), %r13 # 8-byte Reload
movq %r13, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rsi
movq 80(%rsp), %r12 # 8-byte Reload
movq %r12, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rsi
movq 88(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
movq 96(%rsp), %r14 # 8-byte Reload
movq %r14, %rdi
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rsi
movq 56(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
movq %r13, %rdi
callq hipFree
movq %r12, %rdi
callq hipFree
movq %r15, %rdi
callq hipFree
movq %r14, %rdi
callq hipFree
movq %rbx, %rdi
callq hipFree
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size propagate_cuda, .Lfunc_end1-propagate_cuda
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9propagateiPfS_fS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9propagateiPfS_fS_S_S_,@object # @_Z9propagateiPfS_fS_S_S_
.section .rodata,"a",@progbits
.globl _Z9propagateiPfS_fS_S_S_
.p2align 3, 0x0
_Z9propagateiPfS_fS_S_S_:
.quad _Z24__device_stub__propagateiPfS_fS_S_S_
.size _Z9propagateiPfS_fS_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9propagateiPfS_fS_S_S_"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__propagateiPfS_fS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9propagateiPfS_fS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00139b0b_00000000-6_propagator_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z9propagateiPfS_fS_S_S_iPfS_fS_S_S_
.type _Z38__device_stub__Z9propagateiPfS_fS_S_S_iPfS_fS_S_S_, @function
_Z38__device_stub__Z9propagateiPfS_fS_S_S_iPfS_fS_S_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movss %xmm0, 40(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9propagateiPfS_fS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z38__device_stub__Z9propagateiPfS_fS_S_S_iPfS_fS_S_S_, .-_Z38__device_stub__Z9propagateiPfS_fS_S_S_iPfS_fS_S_S_
.globl _Z9propagateiPfS_fS_S_S_
.type _Z9propagateiPfS_fS_S_S_, @function
_Z9propagateiPfS_fS_S_S_:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z9propagateiPfS_fS_S_S_iPfS_fS_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z9propagateiPfS_fS_S_S_, .-_Z9propagateiPfS_fS_S_S_
.globl propagate_cuda
.type propagate_cuda, @function
propagate_cuda:
.LFB2028:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rdi, %r15
movq %rsi, %r14
movss %xmm0, 28(%rsp)
movq %rdx, %r13
movq %rcx, 8(%rsp)
movq %r8, 16(%rsp)
movl %r9d, %r12d
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leal (%r9,%r9,2), %ebp
movslq %ebp, %rbp
salq $2, %rbp
leaq 40(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movslq %r12d, %rbx
salq $2, %rbx
leaq 56(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r15, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r14, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 40(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 48(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 56(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 64(%rsp), %rsi
movq 8(%rsp), %rbp
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 72(%rsp), %rsi
movq 16(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %r15, %rdi
call cudaFree@PLT
movq %r14, %rdi
call cudaFree@PLT
movq %r13, %rdi
call cudaFree@PLT
movq %rbp, %rdi
call cudaFree@PLT
movq %rbx, %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 72(%rsp), %r9
movq 64(%rsp), %r8
movq 56(%rsp), %rcx
movss 28(%rsp), %xmm0
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movl %r12d, %edi
call _Z38__device_stub__Z9propagateiPfS_fS_S_S_iPfS_fS_S_S_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2028:
.size propagate_cuda, .-propagate_cuda
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9propagateiPfS_fS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9propagateiPfS_fS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "propagator_cuda.hip"
.globl _Z24__device_stub__propagateiPfS_fS_S_S_ # -- Begin function _Z24__device_stub__propagateiPfS_fS_S_S_
.p2align 4, 0x90
.type _Z24__device_stub__propagateiPfS_fS_S_S_,@function
_Z24__device_stub__propagateiPfS_fS_S_S_: # @_Z24__device_stub__propagateiPfS_fS_S_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 4(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movss %xmm0, (%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9propagateiPfS_fS_S_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z24__device_stub__propagateiPfS_fS_S_S_, .Lfunc_end0-_Z24__device_stub__propagateiPfS_fS_S_S_
.cfi_endproc
# -- End function
.globl propagate_cuda # -- Begin function propagate_cuda
.p2align 4, 0x90
.type propagate_cuda,@function
propagate_cuda: # @propagate_cuda
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %ebp
movq %r8, 56(%rsp) # 8-byte Spill
movq %rcx, %r12
movq %rdx, %r13
movss %xmm0, 44(%rsp) # 4-byte Spill
movq %rsi, %r14
movq %rdi, %r15
leal (%rbp,%rbp,2), %eax
movslq %eax, %rbx
shlq $2, %rbx
leaq 32(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq %rbp, 64(%rsp) # 8-byte Spill
movslq %ebp, %rbp
shlq $2, %rbp
leaq 16(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %rbp, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq %r15, 72(%rsp) # 8-byte Spill
movq %r15, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %r14, 80(%rsp) # 8-byte Spill
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r13, 88(%rsp) # 8-byte Spill
movq %r13, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %r12, 96(%rsp) # 8-byte Spill
movq %r12, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movq 56(%rsp), %rsi # 8-byte Reload
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
movq 64(%rsp), %r8 # 8-byte Reload
movl %r8d, 52(%rsp)
movq %rax, 184(%rsp)
movq %rcx, 176(%rsp)
movss 44(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 48(%rsp)
movq %rdx, 168(%rsp)
movq %rsi, 160(%rsp)
movq %rdi, 152(%rsp)
leaq 52(%rsp), %rax
movq %rax, 192(%rsp)
leaq 184(%rsp), %rax
movq %rax, 200(%rsp)
leaq 176(%rsp), %rax
movq %rax, 208(%rsp)
leaq 48(%rsp), %rax
movq %rax, 216(%rsp)
leaq 168(%rsp), %rax
movq %rax, 224(%rsp)
leaq 160(%rsp), %rax
movq %rax, 232(%rsp)
leaq 152(%rsp), %rax
movq %rax, 240(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 192(%rsp), %r9
movl $_Z9propagateiPfS_fS_S_S_, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movq 32(%rsp), %rsi
movq 72(%rsp), %r13 # 8-byte Reload
movq %r13, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rsi
movq 80(%rsp), %r12 # 8-byte Reload
movq %r12, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rsi
movq 88(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
movq 96(%rsp), %r14 # 8-byte Reload
movq %r14, %rdi
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rsi
movq 56(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
movq %r13, %rdi
callq hipFree
movq %r12, %rdi
callq hipFree
movq %r15, %rdi
callq hipFree
movq %r14, %rdi
callq hipFree
movq %rbx, %rdi
callq hipFree
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size propagate_cuda, .Lfunc_end1-propagate_cuda
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9propagateiPfS_fS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9propagateiPfS_fS_S_S_,@object # @_Z9propagateiPfS_fS_S_S_
.section .rodata,"a",@progbits
.globl _Z9propagateiPfS_fS_S_S_
.p2align 3, 0x0
_Z9propagateiPfS_fS_S_S_:
.quad _Z24__device_stub__propagateiPfS_fS_S_S_
.size _Z9propagateiPfS_fS_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9propagateiPfS_fS_S_S_"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__propagateiPfS_fS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9propagateiPfS_fS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* Please write your name and net ID below
*
* Last name: Li
* First name: Yuqiong
* Net ID: yl5090
*
*/
/*
* This file contains the code for doing the heat distribution problem.
* You do not need to modify anything except starting gpu_heat_dist() at the bottom
* of this file.
* In gpu_heat_dist() you can organize your data structure and the call to your
* kernel(s) that you need to write too.
*
* You compile with:
* nvcc -o heatdist -arch=sm_60 heatdist.cu
*/
#include <cuda.h>
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
/* To index element (i,j) of a 2D array stored as 1D */
#define index(i, j, N) ((i)*(N)) + (j)
/*****************************************************************/
// Function declarations: Feel free to add any functions you want.
void seq_heat_dist(float *, unsigned int, unsigned int);
void gpu_heat_dist(float *, unsigned int, unsigned int);
__global__ void heatKernel(float *, float *, unsigned int);
/*****************************************************************/
/**** Do NOT CHANGE ANYTHING in main() function ******/
int main(int argc, char * argv[])
{
unsigned int N; /* Dimention of NxN matrix */
int type_of_device = 0; // CPU or GPU
int iterations = 0;
int i;
/* The 2D array of points will be treated as 1D array of NxN elements */
float * playground;
// to measure time taken by a specific part of the code
double time_taken;
clock_t start, end;
if(argc != 4)
{
fprintf(stderr, "usage: heatdist num iterations who\n");
fprintf(stderr, "num = dimension of the square matrix (50 and up)\n");
fprintf(stderr, "iterations = number of iterations till stopping (1 and up)\n");
fprintf(stderr, "who = 0: sequential code on CPU, 1: GPU execution\n");
exit(1);
}
type_of_device = atoi(argv[3]);
N = (unsigned int) atoi(argv[1]);
iterations = (unsigned int) atoi(argv[2]);
/* Dynamically allocate NxN array of floats */
playground = (float *)calloc(N*N, sizeof(float));
if( !playground )
{
fprintf(stderr, " Cannot allocate the %u x %u array\n", N, N);
exit(1);
}
/* Initialize it: calloc already initalized everything to 0 */
// Edge elements to 70F
for(i = 0; i < N; i++)
playground[index(0,i,N)] = 70;
for(i = 0; i < N; i++)
playground[index(i,0,N)] = 70;
for(i = 0; i < N; i++)
playground[index(i,N-1, N)] = 70;
for(i = 0; i < N; i++)
playground[index(N-1,i,N)] = 70;
// from (0,10) to (0,30) inclusive are 100F
for(i = 10; i <= 30; i++)
playground[index(0,i,N)] = 100;
// from (n-1,10) to (n-1,30) inclusive are 150F
for(i = 10; i <= 30; i++)
playground[index(N-1,i,N)] = 150;
if( !type_of_device ) // The CPU sequential version
{
start = clock();
seq_heat_dist(playground, N, iterations);
end = clock();
}
else // The GPU version
{
start = clock();
gpu_heat_dist(playground, N, iterations);
end = clock();
}
time_taken = ((double)(end - start))/ CLOCKS_PER_SEC;
printf("Time taken for %s is %lf\n", type_of_device == 0? "CPU" : "GPU", time_taken);
free(playground);
return 0;
}
/***************** The CPU sequential version (DO NOT CHANGE THAT) **************/
void seq_heat_dist(float * playground, unsigned int N, unsigned int iterations)
{
// Loop indices
int i, j, k;
int upper = N-1;
// number of bytes to be copied between array temp and array playground
unsigned int num_bytes = 0;
float * temp;
/* Dynamically allocate another array for temp values */
/* Dynamically allocate NxN array of floats */
temp = (float *)calloc(N*N, sizeof(float));
if( !temp )
{
fprintf(stderr, " Cannot allocate temp %u x %u array\n", N, N);
exit(1);
}
num_bytes = N*N*sizeof(float);
/* Copy initial array in temp */
memcpy((void *)temp, (void *) playground, num_bytes);
for( k = 0; k < iterations; k++)
{
/* Calculate new values and store them in temp */
for(i = 1; i < upper; i++)
for(j = 1; j < upper; j++)
temp[index(i,j,N)] = (playground[index(i-1,j,N)] +
playground[index(i+1,j,N)] +
playground[index(i,j-1,N)] +
playground[index(i,j+1,N)])/4.0;
/* Move new values into old values */
memcpy((void *)playground, (void *) temp, num_bytes);
}
}
/***************** The GPU version: Write your code here *********************/
/* This function can call one or more kernels if you want ********************/
void gpu_heat_dist(float * playground, unsigned int N, unsigned int iterations)
{
int k;
// number of bytes to be copied between playground and temp
unsigned int num_bytes = N * N * sizeof(float);
// to store results
float * d_temp1, * d_temp2; // define two chunks of memory to swap results
float * swap_ptr;
// 1. allocate device memory for playground and temp
cudaMalloc((void **) &d_temp1, num_bytes);
cudaMalloc((void **) &d_temp2, num_bytes);
cudaMemcpy(d_temp1, playground, num_bytes, cudaMemcpyHostToDevice);
// 2. kernel launch code : let the device perform the operation
dim3 blocksPerGrid(ceil(N/16.0), ceil(N/16.0), 1);
dim3 threadsPerBlock(16, 16, 1);
for (k = 0; k < iterations; k++){
heatKernel<<<blocksPerGrid, threadsPerBlock>>> (d_temp1, d_temp2, N);
// swap and did the whole precess again
swap_ptr = d_temp1;
d_temp1 = d_temp2;
d_temp2 = swap_ptr;
}
// 3. copy result from the device memory
cudaMemcpy(playground, d_temp2, num_bytes, cudaMemcpyDeviceToHost);
cudaFree(d_temp1); // free memory
cudaFree(d_temp2); // free memory
}
__global__ void heatKernel(float * d_temp1, float * d_temp2, unsigned int N){
// a kernel to take average of four neighbors of point[i][j] in temp1 and store results in temp2
unsigned int col = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int row = blockIdx.y * blockDim.y + threadIdx.y;
if ((row >= 1) && (row < N)){
if ((col >= 1) && (col < N))
d_temp2[index(row, col, N)] = (d_temp1[index(row-1, col, N)] +
d_temp1[index(row+1, col, N)] +
d_temp1[index(row, col-1, N)] +
d_temp1[index(row, col+1, N)])/4.0;
}
} | code for sm_80
Function : _Z10heatKernelPfS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fc600078e0205 */
/*0080*/ ISETP.EQ.OR P0, PT, R3, RZ, P0 ; /* 0x000000ff0300720c */
/* 0x000fda0000702670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fc80003f06070 */
/*00b0*/ ISETP.EQ.OR P0, PT, R0, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0000702670 */
/*00c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R5, R3.reuse, -0x1, RZ ; /* 0xffffffff03057810 */
/* 0x040fe20007ffe0ff */
/*00e0*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*00f0*/ MOV R4, c[0x0][0x170] ; /* 0x00005c0000047a02 */
/* 0x000fe20000000f00 */
/*0100*/ IMAD R10, R3, c[0x0][0x170], R0.reuse ; /* 0x00005c00030a7a24 */
/* 0x100fe200078e0200 */
/*0110*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0120*/ IMAD R5, R5, c[0x0][0x170], R0 ; /* 0x00005c0005057a24 */
/* 0x000fc600078e0200 */
/*0130*/ IADD3 R6, R10, -0x1, RZ ; /* 0xffffffff0a067810 */
/* 0x000fe40007ffe0ff */
/*0140*/ LEA R4, R4, R5, 0x1 ; /* 0x0000000504047211 */
/* 0x000fe200078e08ff */
/*0150*/ IMAD.WIDE.U32 R2, R5, R11, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fe200078e000b */
/*0160*/ IADD3 R8, R10, 0x1, RZ ; /* 0x000000010a087810 */
/* 0x000fc60007ffe0ff */
/*0170*/ IMAD.WIDE.U32 R4, R4, R11.reuse, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x080fe400078e000b */
/*0180*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea4000c1e1900 */
/*0190*/ IMAD.WIDE.U32 R6, R6, R11.reuse, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x080fe400078e000b */
/*01a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*01b0*/ IMAD.WIDE.U32 R8, R8, R11.reuse, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x080fe400078e000b */
/*01c0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ee8000c1e1900 */
/*01d0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000f22000c1e1900 */
/*01e0*/ IMAD.WIDE.U32 R10, R10, R11, c[0x0][0x168] ; /* 0x00005a000a0a7625 */
/* 0x000fc800078e000b */
/*01f0*/ FADD R0, R4, R3 ; /* 0x0000000304007221 */
/* 0x004fc80000000000 */
/*0200*/ FADD R0, R0, R7 ; /* 0x0000000700007221 */
/* 0x008fc80000000000 */
/*0210*/ FADD R0, R0, R9 ; /* 0x0000000900007221 */
/* 0x010fc80000000000 */
/*0220*/ FMUL R3, R0, 0.25 ; /* 0x3e80000000037820 */
/* 0x000fca0000400000 */
/*0230*/ STG.E [R10.64], R3 ; /* 0x000000030a007986 */
/* 0x000fe2000c101904 */
/*0240*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0250*/ BRA 0x250; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Please write your name and net ID below
*
* Last name: Li
* First name: Yuqiong
* Net ID: yl5090
*
*/
/*
* This file contains the code for doing the heat distribution problem.
* You do not need to modify anything except starting gpu_heat_dist() at the bottom
* of this file.
* In gpu_heat_dist() you can organize your data structure and the call to your
* kernel(s) that you need to write too.
*
* You compile with:
* nvcc -o heatdist -arch=sm_60 heatdist.cu
*/
#include <cuda.h>
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
/* To index element (i,j) of a 2D array stored as 1D */
#define index(i, j, N) ((i)*(N)) + (j)
/*****************************************************************/
// Function declarations: Feel free to add any functions you want.
void seq_heat_dist(float *, unsigned int, unsigned int);
void gpu_heat_dist(float *, unsigned int, unsigned int);
__global__ void heatKernel(float *, float *, unsigned int);
/*****************************************************************/
/**** Do NOT CHANGE ANYTHING in main() function ******/
int main(int argc, char * argv[])
{
unsigned int N; /* Dimention of NxN matrix */
int type_of_device = 0; // CPU or GPU
int iterations = 0;
int i;
/* The 2D array of points will be treated as 1D array of NxN elements */
float * playground;
// to measure time taken by a specific part of the code
double time_taken;
clock_t start, end;
if(argc != 4)
{
fprintf(stderr, "usage: heatdist num iterations who\n");
fprintf(stderr, "num = dimension of the square matrix (50 and up)\n");
fprintf(stderr, "iterations = number of iterations till stopping (1 and up)\n");
fprintf(stderr, "who = 0: sequential code on CPU, 1: GPU execution\n");
exit(1);
}
type_of_device = atoi(argv[3]);
N = (unsigned int) atoi(argv[1]);
iterations = (unsigned int) atoi(argv[2]);
/* Dynamically allocate NxN array of floats */
playground = (float *)calloc(N*N, sizeof(float));
if( !playground )
{
fprintf(stderr, " Cannot allocate the %u x %u array\n", N, N);
exit(1);
}
/* Initialize it: calloc already initalized everything to 0 */
// Edge elements to 70F
for(i = 0; i < N; i++)
playground[index(0,i,N)] = 70;
for(i = 0; i < N; i++)
playground[index(i,0,N)] = 70;
for(i = 0; i < N; i++)
playground[index(i,N-1, N)] = 70;
for(i = 0; i < N; i++)
playground[index(N-1,i,N)] = 70;
// from (0,10) to (0,30) inclusive are 100F
for(i = 10; i <= 30; i++)
playground[index(0,i,N)] = 100;
// from (n-1,10) to (n-1,30) inclusive are 150F
for(i = 10; i <= 30; i++)
playground[index(N-1,i,N)] = 150;
if( !type_of_device ) // The CPU sequential version
{
start = clock();
seq_heat_dist(playground, N, iterations);
end = clock();
}
else // The GPU version
{
start = clock();
gpu_heat_dist(playground, N, iterations);
end = clock();
}
time_taken = ((double)(end - start))/ CLOCKS_PER_SEC;
printf("Time taken for %s is %lf\n", type_of_device == 0? "CPU" : "GPU", time_taken);
free(playground);
return 0;
}
/***************** The CPU sequential version (DO NOT CHANGE THAT) **************/
void seq_heat_dist(float * playground, unsigned int N, unsigned int iterations)
{
// Loop indices
int i, j, k;
int upper = N-1;
// number of bytes to be copied between array temp and array playground
unsigned int num_bytes = 0;
float * temp;
/* Dynamically allocate another array for temp values */
/* Dynamically allocate NxN array of floats */
temp = (float *)calloc(N*N, sizeof(float));
if( !temp )
{
fprintf(stderr, " Cannot allocate temp %u x %u array\n", N, N);
exit(1);
}
num_bytes = N*N*sizeof(float);
/* Copy initial array in temp */
memcpy((void *)temp, (void *) playground, num_bytes);
for( k = 0; k < iterations; k++)
{
/* Calculate new values and store them in temp */
for(i = 1; i < upper; i++)
for(j = 1; j < upper; j++)
temp[index(i,j,N)] = (playground[index(i-1,j,N)] +
playground[index(i+1,j,N)] +
playground[index(i,j-1,N)] +
playground[index(i,j+1,N)])/4.0;
/* Move new values into old values */
memcpy((void *)playground, (void *) temp, num_bytes);
}
}
/***************** The GPU version: Write your code here *********************/
/* This function can call one or more kernels if you want ********************/
void gpu_heat_dist(float * playground, unsigned int N, unsigned int iterations)
{
int k;
// number of bytes to be copied between playground and temp
unsigned int num_bytes = N * N * sizeof(float);
// to store results
float * d_temp1, * d_temp2; // define two chunks of memory to swap results
float * swap_ptr;
// 1. allocate device memory for playground and temp
cudaMalloc((void **) &d_temp1, num_bytes);
cudaMalloc((void **) &d_temp2, num_bytes);
cudaMemcpy(d_temp1, playground, num_bytes, cudaMemcpyHostToDevice);
// 2. kernel launch code : let the device perform the operation
dim3 blocksPerGrid(ceil(N/16.0), ceil(N/16.0), 1);
dim3 threadsPerBlock(16, 16, 1);
for (k = 0; k < iterations; k++){
heatKernel<<<blocksPerGrid, threadsPerBlock>>> (d_temp1, d_temp2, N);
// swap and did the whole precess again
swap_ptr = d_temp1;
d_temp1 = d_temp2;
d_temp2 = swap_ptr;
}
// 3. copy result from the device memory
cudaMemcpy(playground, d_temp2, num_bytes, cudaMemcpyDeviceToHost);
cudaFree(d_temp1); // free memory
cudaFree(d_temp2); // free memory
}
__global__ void heatKernel(float * d_temp1, float * d_temp2, unsigned int N){
// a kernel to take average of four neighbors of point[i][j] in temp1 and store results in temp2
unsigned int col = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int row = blockIdx.y * blockDim.y + threadIdx.y;
if ((row >= 1) && (row < N)){
if ((col >= 1) && (col < N))
d_temp2[index(row, col, N)] = (d_temp1[index(row-1, col, N)] +
d_temp1[index(row+1, col, N)] +
d_temp1[index(row, col-1, N)] +
d_temp1[index(row, col+1, N)])/4.0;
}
} | .file "tmpxft_00173133_00000000-6_heatdist.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string " Cannot allocate temp %u x %u array\n"
.text
.globl _Z13seq_heat_distPfjj
.type _Z13seq_heat_distPfjj, @function
_Z13seq_heat_distPfjj:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbx
movl %esi, %r12d
movl %edx, 16(%rsp)
leal -1(%rsi), %r13d
movl %esi, %edi
imull %esi, %edi
leaq 0(,%rdi,4), %r14
movl $4, %esi
call calloc@PLT
testq %rax, %rax
je .L16
movq %rax, %rbp
movl %r14d, %eax
movq %rax, 24(%rsp)
movq %r14, %rcx
movq %rax, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call __memcpy_chk@PLT
cmpl $0, 16(%rsp)
je .L3
leal -2(%r12,%r12), %eax
movl %eax, 20(%rsp)
movl %r12d, %eax
negl %eax
movl $0, 12(%rsp)
leal 2(%rax,%rax), %r15d
movl $2, %r14d
subl %r12d, %r14d
jmp .L6
.L16:
movl %r12d, %r8d
movl %r12d, %ecx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L9:
leal (%r14,%rcx), %edx
movl %edx, %eax
leal 1(%rcx,%r15), %esi
subl %edx, %esi
.L7:
leal (%rsi,%rax), %r9d
leal (%rdi,%rax), %edx
movss (%rbx,%r9,4), %xmm0
addss (%rbx,%rdx,4), %xmm0
movl %eax, %r9d
addl $1, %eax
movl %eax, %edx
movl %r9d, %r10d
addss (%rbx,%r10,4), %xmm0
leal 2(%r9), %r9d
addss (%rbx,%r9,4), %xmm0
mulss .LC1(%rip), %xmm0
movss %xmm0, 0(%rbp,%rdx,4)
cmpl %eax, %ecx
jne .L7
addl $1, %r8d
addl %r12d, %ecx
cmpl %r8d, %r13d
jne .L9
.L8:
movq 24(%rsp), %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call memcpy@PLT
addl $1, 12(%rsp)
movl 12(%rsp), %eax
movl 16(%rsp), %edi
cmpl %edi, %eax
je .L3
.L6:
movl 20(%rsp), %ecx
movl $1, %r8d
leal 1(%r12), %edi
cmpl $1, %r13d
jg .L9
jmp .L8
.L3:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z13seq_heat_distPfjj, .-_Z13seq_heat_distPfjj
.globl _Z33__device_stub__Z10heatKernelPfS_jPfS_j
.type _Z33__device_stub__Z10heatKernelPfS_jPfS_j, @function
_Z33__device_stub__Z10heatKernelPfS_jPfS_j:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10heatKernelPfS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z33__device_stub__Z10heatKernelPfS_jPfS_j, .-_Z33__device_stub__Z10heatKernelPfS_jPfS_j
.globl _Z10heatKernelPfS_j
.type _Z10heatKernelPfS_j, @function
_Z10heatKernelPfS_j:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10heatKernelPfS_jPfS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10heatKernelPfS_j, .-_Z10heatKernelPfS_j
.globl _Z13gpu_heat_distPfjj
.type _Z13gpu_heat_distPfjj, @function
_Z13gpu_heat_distPfjj:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r13
movl %esi, %r12d
movl %edx, %ebp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl %esi, %eax
imull %esi, %eax
leal 0(,%rax,4), %r14d
movq %rsp, %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r13, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl %r12d, %eax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC2(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC6(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC3(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L28
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC5(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L28:
cvttsd2siq %xmm3, %rax
movl %eax, 16(%rsp)
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $16, 28(%rsp)
movl $16, 32(%rsp)
movl $1, 36(%rsp)
testl %ebp, %ebp
je .L29
movl $0, %ebx
jmp .L31
.L30:
movq (%rsp), %rax
movq 8(%rsp), %rdx
movq %rdx, (%rsp)
movq %rax, 8(%rsp)
addl $1, %ebx
cmpl %ebx, %ebp
je .L29
.L31:
movl 36(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movq 16(%rsp), %rdi
movl 24(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L30
movl %r12d, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z33__device_stub__Z10heatKernelPfS_jPfS_j
jmp .L30
.L29:
movl $2, %ecx
movq %r14, %rdx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z13gpu_heat_distPfjj, .-_Z13gpu_heat_distPfjj
.section .rodata.str1.1,"aMS",@progbits,1
.LC7:
.string "CPU"
.LC8:
.string "GPU"
.section .rodata.str1.8
.align 8
.LC9:
.string "usage: heatdist num iterations who\n"
.align 8
.LC10:
.string "num = dimension of the square matrix (50 and up)\n"
.align 8
.LC11:
.string "iterations = number of iterations till stopping (1 and up)\n"
.align 8
.LC12:
.string "who = 0: sequential code on CPU, 1: GPU execution\n"
.align 8
.LC13:
.string " Cannot allocate the %u x %u array\n"
.section .rodata.str1.1
.LC18:
.string "Time taken for %s is %lf\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
cmpl $4, %edi
jne .L56
movq %rsi, %rbx
movq 24(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movl %eax, %ebp
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl %r14d, %edi
imull %r14d, %edi
movl $4, %esi
call calloc@PLT
movq %rax, %rbx
testq %rax, %rax
je .L38
testl %r14d, %r14d
je .L40
movq %rax, %rdx
leal -1(%r14), %eax
movl %eax, %ecx
leaq 4(%rbx,%rcx,4), %rcx
movss .LC14(%rip), %xmm0
.L41:
movss %xmm0, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L41
movl %r14d, %edi
movl $0, %ecx
movl $0, %edx
movss .LC14(%rip), %xmm0
.L42:
movl %ecx, %esi
movss %xmm0, (%rbx,%rsi,4)
movl %edx, %esi
addl $1, %edx
addl %ebp, %ecx
cmpl %edi, %edx
jne .L42
movl %eax, %ecx
movl $0, %edx
movss .LC14(%rip), %xmm0
.L43:
movl %ecx, %edi
movss %xmm0, (%rbx,%rdi,4)
movl %edx, %edi
addl $1, %edx
addl %ebp, %ecx
cmpl %edi, %esi
jne .L43
imull %r14d, %eax
leal (%rax,%r14), %ecx
movss .LC14(%rip), %xmm0
.L44:
movl %eax, %edx
movss %xmm0, (%rbx,%rdx,4)
addl $1, %eax
cmpl %eax, %ecx
jne .L44
.L40:
leaq 40(%rbx), %rax
leaq 124(%rbx), %rdx
movss .LC15(%rip), %xmm0
.L45:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L45
leal -1(%r14), %ecx
imull %r14d, %ecx
leal 10(%rcx), %eax
addl $31, %ecx
movss .LC16(%rip), %xmm0
.L46:
movl %eax, %edx
movss %xmm0, (%rbx,%rdx,4)
addl $1, %eax
cmpl %eax, %ecx
jne .L46
testl %r13d, %r13d
jne .L47
call clock@PLT
movq %rax, %r13
movl %r12d, %edx
movl %ebp, %esi
movq %rbx, %rdi
call _Z13seq_heat_distPfjj
call clock@PLT
subq %r13, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC17(%rip), %xmm0
leaq .LC7(%rip), %rdx
.L48:
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movl $0, %eax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L56:
.cfi_restore_state
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
movl %r14d, %r8d
movl %r14d, %ecx
leaq .LC13(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L47:
call clock@PLT
movq %rax, %r13
movl %r12d, %edx
movl %ebp, %esi
movq %rbx, %rdi
call _Z13gpu_heat_distPfjj
call clock@PLT
subq %r13, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC17(%rip), %xmm0
leaq .LC8(%rip), %rdx
jmp .L48
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC19:
.string "_Z10heatKernelPfS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z10heatKernelPfS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1048576000
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1068498944
.align 8
.LC3:
.long 0
.long 1127219200
.align 8
.LC5:
.long 0
.long 1072693248
.align 8
.LC6:
.long -1
.long 2147483647
.section .rodata.cst4
.align 4
.LC14:
.long 1116471296
.align 4
.LC15:
.long 1120403456
.align 4
.LC16:
.long 1125515264
.section .rodata.cst8
.align 8
.LC17:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Please write your name and net ID below
*
* Last name: Li
* First name: Yuqiong
* Net ID: yl5090
*
*/
/*
* This file contains the code for doing the heat distribution problem.
* You do not need to modify anything except starting gpu_heat_dist() at the bottom
* of this file.
* In gpu_heat_dist() you can organize your data structure and the call to your
* kernel(s) that you need to write too.
*
* You compile with:
* nvcc -o heatdist -arch=sm_60 heatdist.cu
*/
#include <cuda.h>
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
/* To index element (i,j) of a 2D array stored as 1D */
#define index(i, j, N) ((i)*(N)) + (j)
/*****************************************************************/
// Function declarations: Feel free to add any functions you want.
void seq_heat_dist(float *, unsigned int, unsigned int);
void gpu_heat_dist(float *, unsigned int, unsigned int);
__global__ void heatKernel(float *, float *, unsigned int);
/*****************************************************************/
/**** Do NOT CHANGE ANYTHING in main() function ******/
int main(int argc, char * argv[])
{
unsigned int N; /* Dimention of NxN matrix */
int type_of_device = 0; // CPU or GPU
int iterations = 0;
int i;
/* The 2D array of points will be treated as 1D array of NxN elements */
float * playground;
// to measure time taken by a specific part of the code
double time_taken;
clock_t start, end;
if(argc != 4)
{
fprintf(stderr, "usage: heatdist num iterations who\n");
fprintf(stderr, "num = dimension of the square matrix (50 and up)\n");
fprintf(stderr, "iterations = number of iterations till stopping (1 and up)\n");
fprintf(stderr, "who = 0: sequential code on CPU, 1: GPU execution\n");
exit(1);
}
type_of_device = atoi(argv[3]);
N = (unsigned int) atoi(argv[1]);
iterations = (unsigned int) atoi(argv[2]);
/* Dynamically allocate NxN array of floats */
playground = (float *)calloc(N*N, sizeof(float));
if( !playground )
{
fprintf(stderr, " Cannot allocate the %u x %u array\n", N, N);
exit(1);
}
/* Initialize it: calloc already initalized everything to 0 */
// Edge elements to 70F
for(i = 0; i < N; i++)
playground[index(0,i,N)] = 70;
for(i = 0; i < N; i++)
playground[index(i,0,N)] = 70;
for(i = 0; i < N; i++)
playground[index(i,N-1, N)] = 70;
for(i = 0; i < N; i++)
playground[index(N-1,i,N)] = 70;
// from (0,10) to (0,30) inclusive are 100F
for(i = 10; i <= 30; i++)
playground[index(0,i,N)] = 100;
// from (n-1,10) to (n-1,30) inclusive are 150F
for(i = 10; i <= 30; i++)
playground[index(N-1,i,N)] = 150;
if( !type_of_device ) // The CPU sequential version
{
start = clock();
seq_heat_dist(playground, N, iterations);
end = clock();
}
else // The GPU version
{
start = clock();
gpu_heat_dist(playground, N, iterations);
end = clock();
}
time_taken = ((double)(end - start))/ CLOCKS_PER_SEC;
printf("Time taken for %s is %lf\n", type_of_device == 0? "CPU" : "GPU", time_taken);
free(playground);
return 0;
}
/***************** The CPU sequential version (DO NOT CHANGE THAT) **************/
void seq_heat_dist(float * playground, unsigned int N, unsigned int iterations)
{
// Loop indices
int i, j, k;
int upper = N-1;
// number of bytes to be copied between array temp and array playground
unsigned int num_bytes = 0;
float * temp;
/* Dynamically allocate another array for temp values */
/* Dynamically allocate NxN array of floats */
temp = (float *)calloc(N*N, sizeof(float));
if( !temp )
{
fprintf(stderr, " Cannot allocate temp %u x %u array\n", N, N);
exit(1);
}
num_bytes = N*N*sizeof(float);
/* Copy initial array in temp */
memcpy((void *)temp, (void *) playground, num_bytes);
for( k = 0; k < iterations; k++)
{
/* Calculate new values and store them in temp */
for(i = 1; i < upper; i++)
for(j = 1; j < upper; j++)
temp[index(i,j,N)] = (playground[index(i-1,j,N)] +
playground[index(i+1,j,N)] +
playground[index(i,j-1,N)] +
playground[index(i,j+1,N)])/4.0;
/* Move new values into old values */
memcpy((void *)playground, (void *) temp, num_bytes);
}
}
/***************** The GPU version: Write your code here *********************/
/* This function can call one or more kernels if you want ********************/
void gpu_heat_dist(float * playground, unsigned int N, unsigned int iterations)
{
int k;
// number of bytes to be copied between playground and temp
unsigned int num_bytes = N * N * sizeof(float);
// to store results
float * d_temp1, * d_temp2; // define two chunks of memory to swap results
float * swap_ptr;
// 1. allocate device memory for playground and temp
cudaMalloc((void **) &d_temp1, num_bytes);
cudaMalloc((void **) &d_temp2, num_bytes);
cudaMemcpy(d_temp1, playground, num_bytes, cudaMemcpyHostToDevice);
// 2. kernel launch code : let the device perform the operation
dim3 blocksPerGrid(ceil(N/16.0), ceil(N/16.0), 1);
dim3 threadsPerBlock(16, 16, 1);
for (k = 0; k < iterations; k++){
heatKernel<<<blocksPerGrid, threadsPerBlock>>> (d_temp1, d_temp2, N);
// swap and did the whole precess again
swap_ptr = d_temp1;
d_temp1 = d_temp2;
d_temp2 = swap_ptr;
}
// 3. copy result from the device memory
cudaMemcpy(playground, d_temp2, num_bytes, cudaMemcpyDeviceToHost);
cudaFree(d_temp1); // free memory
cudaFree(d_temp2); // free memory
}
__global__ void heatKernel(float * d_temp1, float * d_temp2, unsigned int N){
// a kernel to take average of four neighbors of point[i][j] in temp1 and store results in temp2
unsigned int col = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int row = blockIdx.y * blockDim.y + threadIdx.y;
if ((row >= 1) && (row < N)){
if ((col >= 1) && (col < N))
d_temp2[index(row, col, N)] = (d_temp1[index(row-1, col, N)] +
d_temp1[index(row+1, col, N)] +
d_temp1[index(row, col-1, N)] +
d_temp1[index(row, col+1, N)])/4.0;
}
} | /*
* Please write your name and net ID below
*
* Last name: Li
* First name: Yuqiong
* Net ID: yl5090
*
*/
/*
* This file contains the code for doing the heat distribution problem.
* You do not need to modify anything except starting gpu_heat_dist() at the bottom
* of this file.
* In gpu_heat_dist() you can organize your data structure and the call to your
* kernel(s) that you need to write too.
*
* You compile with:
* nvcc -o heatdist -arch=sm_60 heatdist.cu
*/
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
/* To index element (i,j) of a 2D array stored as 1D */
#define index(i, j, N) ((i)*(N)) + (j)
/*****************************************************************/
// Function declarations: Feel free to add any functions you want.
void seq_heat_dist(float *, unsigned int, unsigned int);
void gpu_heat_dist(float *, unsigned int, unsigned int);
__global__ void heatKernel(float *, float *, unsigned int);
/*****************************************************************/
/**** Do NOT CHANGE ANYTHING in main() function ******/
int main(int argc, char * argv[])
{
unsigned int N; /* Dimention of NxN matrix */
int type_of_device = 0; // CPU or GPU
int iterations = 0;
int i;
/* The 2D array of points will be treated as 1D array of NxN elements */
float * playground;
// to measure time taken by a specific part of the code
double time_taken;
clock_t start, end;
if(argc != 4)
{
fprintf(stderr, "usage: heatdist num iterations who\n");
fprintf(stderr, "num = dimension of the square matrix (50 and up)\n");
fprintf(stderr, "iterations = number of iterations till stopping (1 and up)\n");
fprintf(stderr, "who = 0: sequential code on CPU, 1: GPU execution\n");
exit(1);
}
type_of_device = atoi(argv[3]);
N = (unsigned int) atoi(argv[1]);
iterations = (unsigned int) atoi(argv[2]);
/* Dynamically allocate NxN array of floats */
playground = (float *)calloc(N*N, sizeof(float));
if( !playground )
{
fprintf(stderr, " Cannot allocate the %u x %u array\n", N, N);
exit(1);
}
/* Initialize it: calloc already initalized everything to 0 */
// Edge elements to 70F
for(i = 0; i < N; i++)
playground[index(0,i,N)] = 70;
for(i = 0; i < N; i++)
playground[index(i,0,N)] = 70;
for(i = 0; i < N; i++)
playground[index(i,N-1, N)] = 70;
for(i = 0; i < N; i++)
playground[index(N-1,i,N)] = 70;
// from (0,10) to (0,30) inclusive are 100F
for(i = 10; i <= 30; i++)
playground[index(0,i,N)] = 100;
// from (n-1,10) to (n-1,30) inclusive are 150F
for(i = 10; i <= 30; i++)
playground[index(N-1,i,N)] = 150;
if( !type_of_device ) // The CPU sequential version
{
start = clock();
seq_heat_dist(playground, N, iterations);
end = clock();
}
else // The GPU version
{
start = clock();
gpu_heat_dist(playground, N, iterations);
end = clock();
}
time_taken = ((double)(end - start))/ CLOCKS_PER_SEC;
printf("Time taken for %s is %lf\n", type_of_device == 0? "CPU" : "GPU", time_taken);
free(playground);
return 0;
}
/***************** The CPU sequential version (DO NOT CHANGE THAT) **************/
void seq_heat_dist(float * playground, unsigned int N, unsigned int iterations)
{
// Loop indices
int i, j, k;
int upper = N-1;
// number of bytes to be copied between array temp and array playground
unsigned int num_bytes = 0;
float * temp;
/* Dynamically allocate another array for temp values */
/* Dynamically allocate NxN array of floats */
temp = (float *)calloc(N*N, sizeof(float));
if( !temp )
{
fprintf(stderr, " Cannot allocate temp %u x %u array\n", N, N);
exit(1);
}
num_bytes = N*N*sizeof(float);
/* Copy initial array in temp */
memcpy((void *)temp, (void *) playground, num_bytes);
for( k = 0; k < iterations; k++)
{
/* Calculate new values and store them in temp */
for(i = 1; i < upper; i++)
for(j = 1; j < upper; j++)
temp[index(i,j,N)] = (playground[index(i-1,j,N)] +
playground[index(i+1,j,N)] +
playground[index(i,j-1,N)] +
playground[index(i,j+1,N)])/4.0;
/* Move new values into old values */
memcpy((void *)playground, (void *) temp, num_bytes);
}
}
/***************** The GPU version: Write your code here *********************/
/* This function can call one or more kernels if you want ********************/
void gpu_heat_dist(float * playground, unsigned int N, unsigned int iterations)
{
int k;
// number of bytes to be copied between playground and temp
unsigned int num_bytes = N * N * sizeof(float);
// to store results
float * d_temp1, * d_temp2; // define two chunks of memory to swap results
float * swap_ptr;
// 1. allocate device memory for playground and temp
hipMalloc((void **) &d_temp1, num_bytes);
hipMalloc((void **) &d_temp2, num_bytes);
hipMemcpy(d_temp1, playground, num_bytes, hipMemcpyHostToDevice);
// 2. kernel launch code : let the device perform the operation
dim3 blocksPerGrid(ceil(N/16.0), ceil(N/16.0), 1);
dim3 threadsPerBlock(16, 16, 1);
for (k = 0; k < iterations; k++){
heatKernel<<<blocksPerGrid, threadsPerBlock>>> (d_temp1, d_temp2, N);
// swap and did the whole precess again
swap_ptr = d_temp1;
d_temp1 = d_temp2;
d_temp2 = swap_ptr;
}
// 3. copy result from the device memory
hipMemcpy(playground, d_temp2, num_bytes, hipMemcpyDeviceToHost);
hipFree(d_temp1); // free memory
hipFree(d_temp2); // free memory
}
__global__ void heatKernel(float * d_temp1, float * d_temp2, unsigned int N){
// a kernel to take average of four neighbors of point[i][j] in temp1 and store results in temp2
unsigned int col = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int row = blockIdx.y * blockDim.y + threadIdx.y;
if ((row >= 1) && (row < N)){
if ((col >= 1) && (col < N))
d_temp2[index(row, col, N)] = (d_temp1[index(row-1, col, N)] +
d_temp1[index(row+1, col, N)] +
d_temp1[index(row, col-1, N)] +
d_temp1[index(row, col+1, N)])/4.0;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* Please write your name and net ID below
*
* Last name: Li
* First name: Yuqiong
* Net ID: yl5090
*
*/
/*
* This file contains the code for doing the heat distribution problem.
* You do not need to modify anything except starting gpu_heat_dist() at the bottom
* of this file.
* In gpu_heat_dist() you can organize your data structure and the call to your
* kernel(s) that you need to write too.
*
* You compile with:
* nvcc -o heatdist -arch=sm_60 heatdist.cu
*/
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
/* To index element (i,j) of a 2D array stored as 1D */
#define index(i, j, N) ((i)*(N)) + (j)
/*****************************************************************/
// Function declarations: Feel free to add any functions you want.
void seq_heat_dist(float *, unsigned int, unsigned int);
void gpu_heat_dist(float *, unsigned int, unsigned int);
__global__ void heatKernel(float *, float *, unsigned int);
/*****************************************************************/
/**** Do NOT CHANGE ANYTHING in main() function ******/
int main(int argc, char * argv[])
{
unsigned int N; /* Dimention of NxN matrix */
int type_of_device = 0; // CPU or GPU
int iterations = 0;
int i;
/* The 2D array of points will be treated as 1D array of NxN elements */
float * playground;
// to measure time taken by a specific part of the code
double time_taken;
clock_t start, end;
if(argc != 4)
{
fprintf(stderr, "usage: heatdist num iterations who\n");
fprintf(stderr, "num = dimension of the square matrix (50 and up)\n");
fprintf(stderr, "iterations = number of iterations till stopping (1 and up)\n");
fprintf(stderr, "who = 0: sequential code on CPU, 1: GPU execution\n");
exit(1);
}
type_of_device = atoi(argv[3]);
N = (unsigned int) atoi(argv[1]);
iterations = (unsigned int) atoi(argv[2]);
/* Dynamically allocate NxN array of floats */
playground = (float *)calloc(N*N, sizeof(float));
if( !playground )
{
fprintf(stderr, " Cannot allocate the %u x %u array\n", N, N);
exit(1);
}
/* Initialize it: calloc already initalized everything to 0 */
// Edge elements to 70F
for(i = 0; i < N; i++)
playground[index(0,i,N)] = 70;
for(i = 0; i < N; i++)
playground[index(i,0,N)] = 70;
for(i = 0; i < N; i++)
playground[index(i,N-1, N)] = 70;
for(i = 0; i < N; i++)
playground[index(N-1,i,N)] = 70;
// from (0,10) to (0,30) inclusive are 100F
for(i = 10; i <= 30; i++)
playground[index(0,i,N)] = 100;
// from (n-1,10) to (n-1,30) inclusive are 150F
for(i = 10; i <= 30; i++)
playground[index(N-1,i,N)] = 150;
if( !type_of_device ) // The CPU sequential version
{
start = clock();
seq_heat_dist(playground, N, iterations);
end = clock();
}
else // The GPU version
{
start = clock();
gpu_heat_dist(playground, N, iterations);
end = clock();
}
time_taken = ((double)(end - start))/ CLOCKS_PER_SEC;
printf("Time taken for %s is %lf\n", type_of_device == 0? "CPU" : "GPU", time_taken);
free(playground);
return 0;
}
/***************** The CPU sequential version (DO NOT CHANGE THAT) **************/
void seq_heat_dist(float * playground, unsigned int N, unsigned int iterations)
{
// Loop indices
int i, j, k;
int upper = N-1;
// number of bytes to be copied between array temp and array playground
unsigned int num_bytes = 0;
float * temp;
/* Dynamically allocate another array for temp values */
/* Dynamically allocate NxN array of floats */
temp = (float *)calloc(N*N, sizeof(float));
if( !temp )
{
fprintf(stderr, " Cannot allocate temp %u x %u array\n", N, N);
exit(1);
}
num_bytes = N*N*sizeof(float);
/* Copy initial array in temp */
memcpy((void *)temp, (void *) playground, num_bytes);
for( k = 0; k < iterations; k++)
{
/* Calculate new values and store them in temp */
for(i = 1; i < upper; i++)
for(j = 1; j < upper; j++)
temp[index(i,j,N)] = (playground[index(i-1,j,N)] +
playground[index(i+1,j,N)] +
playground[index(i,j-1,N)] +
playground[index(i,j+1,N)])/4.0;
/* Move new values into old values */
memcpy((void *)playground, (void *) temp, num_bytes);
}
}
/***************** The GPU version: Write your code here *********************/
/* This function can call one or more kernels if you want ********************/
void gpu_heat_dist(float * playground, unsigned int N, unsigned int iterations)
{
int k;
// number of bytes to be copied between playground and temp
unsigned int num_bytes = N * N * sizeof(float);
// to store results
float * d_temp1, * d_temp2; // define two chunks of memory to swap results
float * swap_ptr;
// 1. allocate device memory for playground and temp
hipMalloc((void **) &d_temp1, num_bytes);
hipMalloc((void **) &d_temp2, num_bytes);
hipMemcpy(d_temp1, playground, num_bytes, hipMemcpyHostToDevice);
// 2. kernel launch code : let the device perform the operation
dim3 blocksPerGrid(ceil(N/16.0), ceil(N/16.0), 1);
dim3 threadsPerBlock(16, 16, 1);
for (k = 0; k < iterations; k++){
heatKernel<<<blocksPerGrid, threadsPerBlock>>> (d_temp1, d_temp2, N);
// swap and did the whole precess again
swap_ptr = d_temp1;
d_temp1 = d_temp2;
d_temp2 = swap_ptr;
}
// 3. copy result from the device memory
hipMemcpy(playground, d_temp2, num_bytes, hipMemcpyDeviceToHost);
hipFree(d_temp1); // free memory
hipFree(d_temp2); // free memory
}
__global__ void heatKernel(float * d_temp1, float * d_temp2, unsigned int N){
// a kernel to take average of four neighbors of point[i][j] in temp1 and store results in temp2
unsigned int col = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int row = blockIdx.y * blockDim.y + threadIdx.y;
if ((row >= 1) && (row < N)){
if ((col >= 1) && (col < N))
d_temp2[index(row, col, N)] = (d_temp1[index(row-1, col, N)] +
d_temp1[index(row+1, col, N)] +
d_temp1[index(row, col-1, N)] +
d_temp1[index(row, col+1, N)])/4.0;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10heatKernelPfS_j
.globl _Z10heatKernelPfS_j
.p2align 8
.type _Z10heatKernelPfS_j,@function
_Z10heatKernelPfS_j:
s_load_b32 s4, s[0:1], 0x24
v_bfe_u32 v3, v0, 10, 10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
s_mov_b32 s4, exec_lo
v_cmpx_ne_u32_e32 0, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0xc
s_load_b32 s4, s[0:1], 0x10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s14, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_max_u32_e32 v0, v1, v2
v_cmp_ne_u32_e32 vcc_lo, 0, v2
v_cmp_gt_u32_e64 s2, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_3
v_add_nc_u32_e32 v0, -1, v1
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s4, v[2:3]
v_mad_u64_u32 v[5:6], null, v1, s4, v[2:3]
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[3:4]
v_add_nc_u32_e32 v3, s4, v5
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_lshlrev_b64 v[6:7], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
s_clause 0x1
global_load_b32 v10, v[0:1], off
global_load_b32 v6, v[6:7], off
v_add_nc_u32_e32 v3, -1, v5
v_lshlrev_b64 v[8:9], 2, v[3:4]
v_add_nc_u32_e32 v3, 1, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 2, v[3:4]
v_add_co_u32 v0, vcc_lo, s0, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v9, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_load_b32 v0, v[0:1], off
global_load_b32 v1, v[2:3], off
s_waitcnt vmcnt(2)
v_add_f32_e32 v2, v10, v6
v_mov_b32_e32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, v2, v0
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v0, v1
v_lshlrev_b64 v[0:1], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v2, 0x3e800000, v2
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10heatKernelPfS_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10heatKernelPfS_j, .Lfunc_end0-_Z10heatKernelPfS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10heatKernelPfS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10heatKernelPfS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* Please write your name and net ID below
*
* Last name: Li
* First name: Yuqiong
* Net ID: yl5090
*
*/
/*
* This file contains the code for doing the heat distribution problem.
* You do not need to modify anything except starting gpu_heat_dist() at the bottom
* of this file.
* In gpu_heat_dist() you can organize your data structure and the call to your
* kernel(s) that you need to write too.
*
* You compile with:
* nvcc -o heatdist -arch=sm_60 heatdist.cu
*/
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
/* To index element (i,j) of a 2D array stored as 1D */
#define index(i, j, N) ((i)*(N)) + (j)
/*****************************************************************/
// Function declarations: Feel free to add any functions you want.
void seq_heat_dist(float *, unsigned int, unsigned int);
void gpu_heat_dist(float *, unsigned int, unsigned int);
__global__ void heatKernel(float *, float *, unsigned int);
/*****************************************************************/
/**** Do NOT CHANGE ANYTHING in main() function ******/
int main(int argc, char * argv[])
{
unsigned int N; /* Dimention of NxN matrix */
int type_of_device = 0; // CPU or GPU
int iterations = 0;
int i;
/* The 2D array of points will be treated as 1D array of NxN elements */
float * playground;
// to measure time taken by a specific part of the code
double time_taken;
clock_t start, end;
if(argc != 4)
{
fprintf(stderr, "usage: heatdist num iterations who\n");
fprintf(stderr, "num = dimension of the square matrix (50 and up)\n");
fprintf(stderr, "iterations = number of iterations till stopping (1 and up)\n");
fprintf(stderr, "who = 0: sequential code on CPU, 1: GPU execution\n");
exit(1);
}
type_of_device = atoi(argv[3]);
N = (unsigned int) atoi(argv[1]);
iterations = (unsigned int) atoi(argv[2]);
/* Dynamically allocate NxN array of floats */
playground = (float *)calloc(N*N, sizeof(float));
if( !playground )
{
fprintf(stderr, " Cannot allocate the %u x %u array\n", N, N);
exit(1);
}
/* Initialize it: calloc already initalized everything to 0 */
// Edge elements to 70F
for(i = 0; i < N; i++)
playground[index(0,i,N)] = 70;
for(i = 0; i < N; i++)
playground[index(i,0,N)] = 70;
for(i = 0; i < N; i++)
playground[index(i,N-1, N)] = 70;
for(i = 0; i < N; i++)
playground[index(N-1,i,N)] = 70;
// from (0,10) to (0,30) inclusive are 100F
for(i = 10; i <= 30; i++)
playground[index(0,i,N)] = 100;
// from (n-1,10) to (n-1,30) inclusive are 150F
for(i = 10; i <= 30; i++)
playground[index(N-1,i,N)] = 150;
if( !type_of_device ) // The CPU sequential version
{
start = clock();
seq_heat_dist(playground, N, iterations);
end = clock();
}
else // The GPU version
{
start = clock();
gpu_heat_dist(playground, N, iterations);
end = clock();
}
time_taken = ((double)(end - start))/ CLOCKS_PER_SEC;
printf("Time taken for %s is %lf\n", type_of_device == 0? "CPU" : "GPU", time_taken);
free(playground);
return 0;
}
/***************** The CPU sequential version (DO NOT CHANGE THAT) **************/
void seq_heat_dist(float * playground, unsigned int N, unsigned int iterations)
{
// Loop indices
int i, j, k;
int upper = N-1;
// number of bytes to be copied between array temp and array playground
unsigned int num_bytes = 0;
float * temp;
/* Dynamically allocate another array for temp values */
/* Dynamically allocate NxN array of floats */
temp = (float *)calloc(N*N, sizeof(float));
if( !temp )
{
fprintf(stderr, " Cannot allocate temp %u x %u array\n", N, N);
exit(1);
}
num_bytes = N*N*sizeof(float);
/* Copy initial array in temp */
memcpy((void *)temp, (void *) playground, num_bytes);
for( k = 0; k < iterations; k++)
{
/* Calculate new values and store them in temp */
for(i = 1; i < upper; i++)
for(j = 1; j < upper; j++)
temp[index(i,j,N)] = (playground[index(i-1,j,N)] +
playground[index(i+1,j,N)] +
playground[index(i,j-1,N)] +
playground[index(i,j+1,N)])/4.0;
/* Move new values into old values */
memcpy((void *)playground, (void *) temp, num_bytes);
}
}
/***************** The GPU version: Write your code here *********************/
/* This function can call one or more kernels if you want ********************/
void gpu_heat_dist(float * playground, unsigned int N, unsigned int iterations)
{
int k;
// number of bytes to be copied between playground and temp
unsigned int num_bytes = N * N * sizeof(float);
// to store results
float * d_temp1, * d_temp2; // define two chunks of memory to swap results
float * swap_ptr;
// 1. allocate device memory for playground and temp
hipMalloc((void **) &d_temp1, num_bytes);
hipMalloc((void **) &d_temp2, num_bytes);
hipMemcpy(d_temp1, playground, num_bytes, hipMemcpyHostToDevice);
// 2. kernel launch code : let the device perform the operation
dim3 blocksPerGrid(ceil(N/16.0), ceil(N/16.0), 1);
dim3 threadsPerBlock(16, 16, 1);
for (k = 0; k < iterations; k++){
heatKernel<<<blocksPerGrid, threadsPerBlock>>> (d_temp1, d_temp2, N);
// swap and did the whole precess again
swap_ptr = d_temp1;
d_temp1 = d_temp2;
d_temp2 = swap_ptr;
}
// 3. copy result from the device memory
hipMemcpy(playground, d_temp2, num_bytes, hipMemcpyDeviceToHost);
hipFree(d_temp1); // free memory
hipFree(d_temp2); // free memory
}
__global__ void heatKernel(float * d_temp1, float * d_temp2, unsigned int N){
// a kernel to take average of four neighbors of point[i][j] in temp1 and store results in temp2
unsigned int col = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int row = blockIdx.y * blockDim.y + threadIdx.y;
if ((row >= 1) && (row < N)){
if ((col >= 1) && (col < N))
d_temp2[index(row, col, N)] = (d_temp1[index(row-1, col, N)] +
d_temp1[index(row+1, col, N)] +
d_temp1[index(row, col-1, N)] +
d_temp1[index(row, col+1, N)])/4.0;
}
} | .text
.file "heatdist.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
cmpl $4, %edi
jne .LBB0_20
# %bb.1:
movq %rsi, %rbx
movq 24(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movl %r14d, %edi
imull %edi, %edi
movl $4, %esi
callq calloc
testq %rax, %rax
je .LBB0_9
# %bb.2: # %.preheader67
movq %rax, %rbx
movl $4294967295, %eax # imm = 0xFFFFFFFF
testl %r14d, %r14d
je .LBB0_3
# %bb.10: # %.lr.ph.preheader
movl %r14d, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB0_11: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1116471296, (%rbx,%rdx,4) # imm = 0x428C0000
incq %rdx
cmpq %rdx, %rcx
jne .LBB0_11
# %bb.12: # %.lr.ph70.preheader
xorl %edx, %edx
movq %rcx, %rsi
.p2align 4, 0x90
.LBB0_13: # %.lr.ph70
# =>This Inner Loop Header: Depth=1
movl %edx, %edi
movl $1116471296, (%rbx,%rdi,4) # imm = 0x428C0000
addq %r14, %rdx
decq %rsi
jne .LBB0_13
# %bb.14: # %.lr.ph72
leaq (%r14,%rax), %rdx
.p2align 4, 0x90
.LBB0_15: # =>This Inner Loop Header: Depth=1
movl %edx, %esi
movl $1116471296, (%rbx,%rsi,4) # imm = 0x428C0000
addq %r14, %rdx
decq %rcx
jne .LBB0_15
# %bb.16: # %.lr.ph74
leaq (%r14,%rax), %rcx
imulq %r14, %rcx
movl %r14d, %edx
.p2align 4, 0x90
.LBB0_17: # =>This Inner Loop Header: Depth=1
movl %ecx, %esi
movl $1116471296, (%rbx,%rsi,4) # imm = 0x428C0000
incq %rcx
decq %rdx
jne .LBB0_17
.LBB0_3: # %.preheader63.preheader
movl $10, %ecx
.p2align 4, 0x90
.LBB0_4: # %.preheader63
# =>This Inner Loop Header: Depth=1
movl $1120403456, (%rbx,%rcx,4) # imm = 0x42C80000
incq %rcx
cmpq $31, %rcx
jne .LBB0_4
# %bb.5: # %.preheader
addq %r14, %rax
imulq %r14, %rax
movl $10, %ecx
.p2align 4, 0x90
.LBB0_6: # =>This Inner Loop Header: Depth=1
leal (%rax,%rcx), %edx
movl $1125515264, (%rbx,%rdx,4) # imm = 0x43160000
incq %rcx
cmpq $31, %rcx
jne .LBB0_6
# %bb.7:
callq clock
movq %rax, %r13
movq %rbx, %rdi
movl %r14d, %esi
movl %r12d, %edx
testl %r15d, %r15d
je .LBB0_8
# %bb.18:
callq _Z13gpu_heat_distPfjj
movl $.L.str.7, %r14d
jmp .LBB0_19
.LBB0_8:
callq _Z13seq_heat_distPfjj
movl $.L.str.6, %r14d
.LBB0_19:
callq clock
subq %r13, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI0_0(%rip), %xmm0
movl $.L.str.5, %edi
movq %r14, %rsi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_20:
.cfi_def_cfa_offset 48
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $37, %esi
movl $1, %edx
callq fwrite@PLT
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $49, %esi
movl $1, %edx
callq fwrite@PLT
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $59, %esi
movl $1, %edx
callq fwrite@PLT
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $50, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.LBB0_9:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl %r14d, %edx
movl %r14d, %ecx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z13seq_heat_distPfjj
.LCPI1_0:
.long 0x3e800000 # float 0.25
.text
.globl _Z13seq_heat_distPfjj
.p2align 4, 0x90
.type _Z13seq_heat_distPfjj,@function
_Z13seq_heat_distPfjj: # @_Z13seq_heat_distPfjj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
# kill: def $esi killed $esi def $rsi
movq %rdi, %r14
movq %rsi, %rbx
movl %esi, %r15d
imull %r15d, %r15d
movl $4, %esi
movq %r15, %rdi
callq calloc
testq %rax, %rax
je .LBB1_10
# %bb.1:
movq %rax, %r12
shll $2, %r15d
movq %rax, %rdi
movq %r14, %rsi
movq %r15, 16(%rsp) # 8-byte Spill
movq %r15, %rdx
callq memcpy@PLT
movl %ebp, 4(%rsp) # 4-byte Spill
testl %ebp, %ebp
je .LBB1_9
# %bb.2: # %.preheader46.lr.ph
movq %rbx, %rax
leal -1(%rbx), %r13d
movl %r13d, %ebx
movl %eax, %ebp
addl %eax, %eax
orq $1, %rax
movq %rax, 8(%rsp) # 8-byte Spill
decq %rbx
xorl %r15d, %r15d
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_8: # %._crit_edge49
# in Loop: Header=BB1_3 Depth=1
movq %r14, %rdi
movq %r12, %rsi
movq 16(%rsp), %rdx # 8-byte Reload
callq memcpy@PLT
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
incl %r15d
cmpl 4(%rsp), %r15d # 4-byte Folded Reload
je .LBB1_9
.LBB1_3: # %.preheader46
# =>This Loop Header: Depth=1
# Child Loop BB1_5 Depth 2
# Child Loop BB1_6 Depth 3
cmpl $2, %r13d
jl .LBB1_8
# %bb.4: # %.preheader.preheader
# in Loop: Header=BB1_3 Depth=1
movl $1, %eax
xorl %ecx, %ecx
movq 8(%rsp), %rdx # 8-byte Reload
movq %rbp, %rsi
.p2align 4, 0x90
.LBB1_5: # %.preheader
# Parent Loop BB1_3 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_6 Depth 3
xorl %edi, %edi
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_3 Depth=1
# Parent Loop BB1_5 Depth=2
# => This Inner Loop Header: Depth=3
leal (%rcx,%rdi), %r8d
incl %r8d
movss (%r14,%r8,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
leal (%rdx,%rdi), %r8d
addss (%r14,%r8,4), %xmm0
leal (%rsi,%rdi), %r8d
addss (%r14,%r8,4), %xmm0
leal 2(%rsi,%rdi), %r8d
addss (%r14,%r8,4), %xmm0
mulss %xmm1, %xmm0
leal (%rsi,%rdi), %r8d
incl %r8d
movss %xmm0, (%r12,%r8,4)
incq %rdi
cmpq %rdi, %rbx
jne .LBB1_6
# %bb.7: # %._crit_edge
# in Loop: Header=BB1_5 Depth=2
incl %eax
addq %rbp, %rsi
addq %rbp, %rdx
addq %rbp, %rcx
cmpl %r13d, %eax
jne .LBB1_5
jmp .LBB1_8
.LBB1_9: # %._crit_edge51
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_10:
.cfi_def_cfa_offset 80
movq stderr(%rip), %rdi
movl $.L.str.8, %esi
movq %rbx, %rcx
movl %ecx, %edx
# kill: def $ecx killed $ecx killed $rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z13seq_heat_distPfjj, .Lfunc_end1-_Z13seq_heat_distPfjj
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z13gpu_heat_distPfjj
.LCPI2_0:
.quad 0x3fb0000000000000 # double 0.0625
.text
.globl _Z13gpu_heat_distPfjj
.p2align 4, 0x90
.type _Z13gpu_heat_distPfjj,@function
_Z13gpu_heat_distPfjj: # @_Z13gpu_heat_distPfjj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movl %esi, %r15d
movq %rdi, %r14
movl %esi, %ebx
imull %ebx, %ebx
shll $2, %ebx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %rbx, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %r14, 24(%rsp) # 8-byte Spill
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r15d, %eax
cvtsi2sd %rax, %xmm0
mulsd .LCPI2_0(%rip), %xmm0
callq ceil@PLT
testl %ebp, %ebp
je .LBB2_5
# %bb.1: # %.lr.ph
cvttsd2si %xmm0, %r12
movl %r12d, %eax
shlq $32, %r12
orq %rax, %r12
movabsq $68719476752, %r13 # imm = 0x1000000010
leaq 96(%rsp), %r14
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_4: # in Loop: Header=BB2_2 Depth=1
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rcx, 8(%rsp)
movq %rax, (%rsp)
decl %ebp
je .LBB2_5
.LBB2_2: # =>This Inner Loop Header: Depth=1
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3: # in Loop: Header=BB2_2 Depth=1
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r15d, 20(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z10heatKernelPfS_j, %edi
movq %r14, %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_4
.LBB2_5: # %._crit_edge
movq (%rsp), %rsi
movq 24(%rsp), %rdi # 8-byte Reload
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z13gpu_heat_distPfjj, .Lfunc_end2-_Z13gpu_heat_distPfjj
.cfi_endproc
# -- End function
.globl _Z25__device_stub__heatKernelPfS_j # -- Begin function _Z25__device_stub__heatKernelPfS_j
.p2align 4, 0x90
.type _Z25__device_stub__heatKernelPfS_j,@function
_Z25__device_stub__heatKernelPfS_j: # @_Z25__device_stub__heatKernelPfS_j
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10heatKernelPfS_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z25__device_stub__heatKernelPfS_j, .Lfunc_end3-_Z25__device_stub__heatKernelPfS_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10heatKernelPfS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "usage: heatdist num iterations who\n"
.size .L.str, 38
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "num = dimension of the square matrix (50 and up)\n"
.size .L.str.1, 50
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "iterations = number of iterations till stopping (1 and up)\n"
.size .L.str.2, 60
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "who = 0: sequential code on CPU, 1: GPU execution\n"
.size .L.str.3, 51
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " Cannot allocate the %u x %u array\n"
.size .L.str.4, 36
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Time taken for %s is %lf\n"
.size .L.str.5, 26
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "CPU"
.size .L.str.6, 4
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "GPU"
.size .L.str.7, 4
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz " Cannot allocate temp %u x %u array\n"
.size .L.str.8, 37
.type _Z10heatKernelPfS_j,@object # @_Z10heatKernelPfS_j
.section .rodata,"a",@progbits
.globl _Z10heatKernelPfS_j
.p2align 3, 0x0
_Z10heatKernelPfS_j:
.quad _Z25__device_stub__heatKernelPfS_j
.size _Z10heatKernelPfS_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10heatKernelPfS_j"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__heatKernelPfS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10heatKernelPfS_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10heatKernelPfS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fc600078e0205 */
/*0080*/ ISETP.EQ.OR P0, PT, R3, RZ, P0 ; /* 0x000000ff0300720c */
/* 0x000fda0000702670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fc80003f06070 */
/*00b0*/ ISETP.EQ.OR P0, PT, R0, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0000702670 */
/*00c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R5, R3.reuse, -0x1, RZ ; /* 0xffffffff03057810 */
/* 0x040fe20007ffe0ff */
/*00e0*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*00f0*/ MOV R4, c[0x0][0x170] ; /* 0x00005c0000047a02 */
/* 0x000fe20000000f00 */
/*0100*/ IMAD R10, R3, c[0x0][0x170], R0.reuse ; /* 0x00005c00030a7a24 */
/* 0x100fe200078e0200 */
/*0110*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0120*/ IMAD R5, R5, c[0x0][0x170], R0 ; /* 0x00005c0005057a24 */
/* 0x000fc600078e0200 */
/*0130*/ IADD3 R6, R10, -0x1, RZ ; /* 0xffffffff0a067810 */
/* 0x000fe40007ffe0ff */
/*0140*/ LEA R4, R4, R5, 0x1 ; /* 0x0000000504047211 */
/* 0x000fe200078e08ff */
/*0150*/ IMAD.WIDE.U32 R2, R5, R11, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fe200078e000b */
/*0160*/ IADD3 R8, R10, 0x1, RZ ; /* 0x000000010a087810 */
/* 0x000fc60007ffe0ff */
/*0170*/ IMAD.WIDE.U32 R4, R4, R11.reuse, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x080fe400078e000b */
/*0180*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea4000c1e1900 */
/*0190*/ IMAD.WIDE.U32 R6, R6, R11.reuse, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x080fe400078e000b */
/*01a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*01b0*/ IMAD.WIDE.U32 R8, R8, R11.reuse, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x080fe400078e000b */
/*01c0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ee8000c1e1900 */
/*01d0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000f22000c1e1900 */
/*01e0*/ IMAD.WIDE.U32 R10, R10, R11, c[0x0][0x168] ; /* 0x00005a000a0a7625 */
/* 0x000fc800078e000b */
/*01f0*/ FADD R0, R4, R3 ; /* 0x0000000304007221 */
/* 0x004fc80000000000 */
/*0200*/ FADD R0, R0, R7 ; /* 0x0000000700007221 */
/* 0x008fc80000000000 */
/*0210*/ FADD R0, R0, R9 ; /* 0x0000000900007221 */
/* 0x010fc80000000000 */
/*0220*/ FMUL R3, R0, 0.25 ; /* 0x3e80000000037820 */
/* 0x000fca0000400000 */
/*0230*/ STG.E [R10.64], R3 ; /* 0x000000030a007986 */
/* 0x000fe2000c101904 */
/*0240*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0250*/ BRA 0x250; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10heatKernelPfS_j
.globl _Z10heatKernelPfS_j
.p2align 8
.type _Z10heatKernelPfS_j,@function
_Z10heatKernelPfS_j:
s_load_b32 s4, s[0:1], 0x24
v_bfe_u32 v3, v0, 10, 10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
s_mov_b32 s4, exec_lo
v_cmpx_ne_u32_e32 0, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0xc
s_load_b32 s4, s[0:1], 0x10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s14, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_max_u32_e32 v0, v1, v2
v_cmp_ne_u32_e32 vcc_lo, 0, v2
v_cmp_gt_u32_e64 s2, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_3
v_add_nc_u32_e32 v0, -1, v1
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s4, v[2:3]
v_mad_u64_u32 v[5:6], null, v1, s4, v[2:3]
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[3:4]
v_add_nc_u32_e32 v3, s4, v5
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_lshlrev_b64 v[6:7], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
s_clause 0x1
global_load_b32 v10, v[0:1], off
global_load_b32 v6, v[6:7], off
v_add_nc_u32_e32 v3, -1, v5
v_lshlrev_b64 v[8:9], 2, v[3:4]
v_add_nc_u32_e32 v3, 1, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 2, v[3:4]
v_add_co_u32 v0, vcc_lo, s0, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v9, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_load_b32 v0, v[0:1], off
global_load_b32 v1, v[2:3], off
s_waitcnt vmcnt(2)
v_add_f32_e32 v2, v10, v6
v_mov_b32_e32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, v2, v0
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v0, v1
v_lshlrev_b64 v[0:1], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v2, 0x3e800000, v2
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10heatKernelPfS_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10heatKernelPfS_j, .Lfunc_end0-_Z10heatKernelPfS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10heatKernelPfS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10heatKernelPfS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00173133_00000000-6_heatdist.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string " Cannot allocate temp %u x %u array\n"
.text
.globl _Z13seq_heat_distPfjj
.type _Z13seq_heat_distPfjj, @function
_Z13seq_heat_distPfjj:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbx
movl %esi, %r12d
movl %edx, 16(%rsp)
leal -1(%rsi), %r13d
movl %esi, %edi
imull %esi, %edi
leaq 0(,%rdi,4), %r14
movl $4, %esi
call calloc@PLT
testq %rax, %rax
je .L16
movq %rax, %rbp
movl %r14d, %eax
movq %rax, 24(%rsp)
movq %r14, %rcx
movq %rax, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call __memcpy_chk@PLT
cmpl $0, 16(%rsp)
je .L3
leal -2(%r12,%r12), %eax
movl %eax, 20(%rsp)
movl %r12d, %eax
negl %eax
movl $0, 12(%rsp)
leal 2(%rax,%rax), %r15d
movl $2, %r14d
subl %r12d, %r14d
jmp .L6
.L16:
movl %r12d, %r8d
movl %r12d, %ecx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L9:
leal (%r14,%rcx), %edx
movl %edx, %eax
leal 1(%rcx,%r15), %esi
subl %edx, %esi
.L7:
leal (%rsi,%rax), %r9d
leal (%rdi,%rax), %edx
movss (%rbx,%r9,4), %xmm0
addss (%rbx,%rdx,4), %xmm0
movl %eax, %r9d
addl $1, %eax
movl %eax, %edx
movl %r9d, %r10d
addss (%rbx,%r10,4), %xmm0
leal 2(%r9), %r9d
addss (%rbx,%r9,4), %xmm0
mulss .LC1(%rip), %xmm0
movss %xmm0, 0(%rbp,%rdx,4)
cmpl %eax, %ecx
jne .L7
addl $1, %r8d
addl %r12d, %ecx
cmpl %r8d, %r13d
jne .L9
.L8:
movq 24(%rsp), %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call memcpy@PLT
addl $1, 12(%rsp)
movl 12(%rsp), %eax
movl 16(%rsp), %edi
cmpl %edi, %eax
je .L3
.L6:
movl 20(%rsp), %ecx
movl $1, %r8d
leal 1(%r12), %edi
cmpl $1, %r13d
jg .L9
jmp .L8
.L3:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z13seq_heat_distPfjj, .-_Z13seq_heat_distPfjj
.globl _Z33__device_stub__Z10heatKernelPfS_jPfS_j
.type _Z33__device_stub__Z10heatKernelPfS_jPfS_j, @function
_Z33__device_stub__Z10heatKernelPfS_jPfS_j:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10heatKernelPfS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z33__device_stub__Z10heatKernelPfS_jPfS_j, .-_Z33__device_stub__Z10heatKernelPfS_jPfS_j
.globl _Z10heatKernelPfS_j
.type _Z10heatKernelPfS_j, @function
_Z10heatKernelPfS_j:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10heatKernelPfS_jPfS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10heatKernelPfS_j, .-_Z10heatKernelPfS_j
.globl _Z13gpu_heat_distPfjj
.type _Z13gpu_heat_distPfjj, @function
_Z13gpu_heat_distPfjj:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r13
movl %esi, %r12d
movl %edx, %ebp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl %esi, %eax
imull %esi, %eax
leal 0(,%rax,4), %r14d
movq %rsp, %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r13, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl %r12d, %eax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC2(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC6(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC3(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L28
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC5(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L28:
cvttsd2siq %xmm3, %rax
movl %eax, 16(%rsp)
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $16, 28(%rsp)
movl $16, 32(%rsp)
movl $1, 36(%rsp)
testl %ebp, %ebp
je .L29
movl $0, %ebx
jmp .L31
.L30:
movq (%rsp), %rax
movq 8(%rsp), %rdx
movq %rdx, (%rsp)
movq %rax, 8(%rsp)
addl $1, %ebx
cmpl %ebx, %ebp
je .L29
.L31:
movl 36(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movq 16(%rsp), %rdi
movl 24(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L30
movl %r12d, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z33__device_stub__Z10heatKernelPfS_jPfS_j
jmp .L30
.L29:
movl $2, %ecx
movq %r14, %rdx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z13gpu_heat_distPfjj, .-_Z13gpu_heat_distPfjj
.section .rodata.str1.1,"aMS",@progbits,1
.LC7:
.string "CPU"
.LC8:
.string "GPU"
.section .rodata.str1.8
.align 8
.LC9:
.string "usage: heatdist num iterations who\n"
.align 8
.LC10:
.string "num = dimension of the square matrix (50 and up)\n"
.align 8
.LC11:
.string "iterations = number of iterations till stopping (1 and up)\n"
.align 8
.LC12:
.string "who = 0: sequential code on CPU, 1: GPU execution\n"
.align 8
.LC13:
.string " Cannot allocate the %u x %u array\n"
.section .rodata.str1.1
.LC18:
.string "Time taken for %s is %lf\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
cmpl $4, %edi
jne .L56
movq %rsi, %rbx
movq 24(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movl %eax, %ebp
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl %r14d, %edi
imull %r14d, %edi
movl $4, %esi
call calloc@PLT
movq %rax, %rbx
testq %rax, %rax
je .L38
testl %r14d, %r14d
je .L40
movq %rax, %rdx
leal -1(%r14), %eax
movl %eax, %ecx
leaq 4(%rbx,%rcx,4), %rcx
movss .LC14(%rip), %xmm0
.L41:
movss %xmm0, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L41
movl %r14d, %edi
movl $0, %ecx
movl $0, %edx
movss .LC14(%rip), %xmm0
.L42:
movl %ecx, %esi
movss %xmm0, (%rbx,%rsi,4)
movl %edx, %esi
addl $1, %edx
addl %ebp, %ecx
cmpl %edi, %edx
jne .L42
movl %eax, %ecx
movl $0, %edx
movss .LC14(%rip), %xmm0
.L43:
movl %ecx, %edi
movss %xmm0, (%rbx,%rdi,4)
movl %edx, %edi
addl $1, %edx
addl %ebp, %ecx
cmpl %edi, %esi
jne .L43
imull %r14d, %eax
leal (%rax,%r14), %ecx
movss .LC14(%rip), %xmm0
.L44:
movl %eax, %edx
movss %xmm0, (%rbx,%rdx,4)
addl $1, %eax
cmpl %eax, %ecx
jne .L44
.L40:
leaq 40(%rbx), %rax
leaq 124(%rbx), %rdx
movss .LC15(%rip), %xmm0
.L45:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L45
leal -1(%r14), %ecx
imull %r14d, %ecx
leal 10(%rcx), %eax
addl $31, %ecx
movss .LC16(%rip), %xmm0
.L46:
movl %eax, %edx
movss %xmm0, (%rbx,%rdx,4)
addl $1, %eax
cmpl %eax, %ecx
jne .L46
testl %r13d, %r13d
jne .L47
call clock@PLT
movq %rax, %r13
movl %r12d, %edx
movl %ebp, %esi
movq %rbx, %rdi
call _Z13seq_heat_distPfjj
call clock@PLT
subq %r13, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC17(%rip), %xmm0
leaq .LC7(%rip), %rdx
.L48:
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movl $0, %eax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L56:
.cfi_restore_state
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
movl %r14d, %r8d
movl %r14d, %ecx
leaq .LC13(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L47:
call clock@PLT
movq %rax, %r13
movl %r12d, %edx
movl %ebp, %esi
movq %rbx, %rdi
call _Z13gpu_heat_distPfjj
call clock@PLT
subq %r13, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC17(%rip), %xmm0
leaq .LC8(%rip), %rdx
jmp .L48
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC19:
.string "_Z10heatKernelPfS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z10heatKernelPfS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1048576000
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1068498944
.align 8
.LC3:
.long 0
.long 1127219200
.align 8
.LC5:
.long 0
.long 1072693248
.align 8
.LC6:
.long -1
.long 2147483647
.section .rodata.cst4
.align 4
.LC14:
.long 1116471296
.align 4
.LC15:
.long 1120403456
.align 4
.LC16:
.long 1125515264
.section .rodata.cst8
.align 8
.LC17:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "heatdist.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
cmpl $4, %edi
jne .LBB0_20
# %bb.1:
movq %rsi, %rbx
movq 24(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movl %r14d, %edi
imull %edi, %edi
movl $4, %esi
callq calloc
testq %rax, %rax
je .LBB0_9
# %bb.2: # %.preheader67
movq %rax, %rbx
movl $4294967295, %eax # imm = 0xFFFFFFFF
testl %r14d, %r14d
je .LBB0_3
# %bb.10: # %.lr.ph.preheader
movl %r14d, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB0_11: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1116471296, (%rbx,%rdx,4) # imm = 0x428C0000
incq %rdx
cmpq %rdx, %rcx
jne .LBB0_11
# %bb.12: # %.lr.ph70.preheader
xorl %edx, %edx
movq %rcx, %rsi
.p2align 4, 0x90
.LBB0_13: # %.lr.ph70
# =>This Inner Loop Header: Depth=1
movl %edx, %edi
movl $1116471296, (%rbx,%rdi,4) # imm = 0x428C0000
addq %r14, %rdx
decq %rsi
jne .LBB0_13
# %bb.14: # %.lr.ph72
leaq (%r14,%rax), %rdx
.p2align 4, 0x90
.LBB0_15: # =>This Inner Loop Header: Depth=1
movl %edx, %esi
movl $1116471296, (%rbx,%rsi,4) # imm = 0x428C0000
addq %r14, %rdx
decq %rcx
jne .LBB0_15
# %bb.16: # %.lr.ph74
leaq (%r14,%rax), %rcx
imulq %r14, %rcx
movl %r14d, %edx
.p2align 4, 0x90
.LBB0_17: # =>This Inner Loop Header: Depth=1
movl %ecx, %esi
movl $1116471296, (%rbx,%rsi,4) # imm = 0x428C0000
incq %rcx
decq %rdx
jne .LBB0_17
.LBB0_3: # %.preheader63.preheader
movl $10, %ecx
.p2align 4, 0x90
.LBB0_4: # %.preheader63
# =>This Inner Loop Header: Depth=1
movl $1120403456, (%rbx,%rcx,4) # imm = 0x42C80000
incq %rcx
cmpq $31, %rcx
jne .LBB0_4
# %bb.5: # %.preheader
addq %r14, %rax
imulq %r14, %rax
movl $10, %ecx
.p2align 4, 0x90
.LBB0_6: # =>This Inner Loop Header: Depth=1
leal (%rax,%rcx), %edx
movl $1125515264, (%rbx,%rdx,4) # imm = 0x43160000
incq %rcx
cmpq $31, %rcx
jne .LBB0_6
# %bb.7:
callq clock
movq %rax, %r13
movq %rbx, %rdi
movl %r14d, %esi
movl %r12d, %edx
testl %r15d, %r15d
je .LBB0_8
# %bb.18:
callq _Z13gpu_heat_distPfjj
movl $.L.str.7, %r14d
jmp .LBB0_19
.LBB0_8:
callq _Z13seq_heat_distPfjj
movl $.L.str.6, %r14d
.LBB0_19:
callq clock
subq %r13, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI0_0(%rip), %xmm0
movl $.L.str.5, %edi
movq %r14, %rsi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_20:
.cfi_def_cfa_offset 48
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $37, %esi
movl $1, %edx
callq fwrite@PLT
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $49, %esi
movl $1, %edx
callq fwrite@PLT
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $59, %esi
movl $1, %edx
callq fwrite@PLT
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $50, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.LBB0_9:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl %r14d, %edx
movl %r14d, %ecx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z13seq_heat_distPfjj
.LCPI1_0:
.long 0x3e800000 # float 0.25
.text
.globl _Z13seq_heat_distPfjj
.p2align 4, 0x90
.type _Z13seq_heat_distPfjj,@function
_Z13seq_heat_distPfjj: # @_Z13seq_heat_distPfjj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
# kill: def $esi killed $esi def $rsi
movq %rdi, %r14
movq %rsi, %rbx
movl %esi, %r15d
imull %r15d, %r15d
movl $4, %esi
movq %r15, %rdi
callq calloc
testq %rax, %rax
je .LBB1_10
# %bb.1:
movq %rax, %r12
shll $2, %r15d
movq %rax, %rdi
movq %r14, %rsi
movq %r15, 16(%rsp) # 8-byte Spill
movq %r15, %rdx
callq memcpy@PLT
movl %ebp, 4(%rsp) # 4-byte Spill
testl %ebp, %ebp
je .LBB1_9
# %bb.2: # %.preheader46.lr.ph
movq %rbx, %rax
leal -1(%rbx), %r13d
movl %r13d, %ebx
movl %eax, %ebp
addl %eax, %eax
orq $1, %rax
movq %rax, 8(%rsp) # 8-byte Spill
decq %rbx
xorl %r15d, %r15d
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_8: # %._crit_edge49
# in Loop: Header=BB1_3 Depth=1
movq %r14, %rdi
movq %r12, %rsi
movq 16(%rsp), %rdx # 8-byte Reload
callq memcpy@PLT
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
incl %r15d
cmpl 4(%rsp), %r15d # 4-byte Folded Reload
je .LBB1_9
.LBB1_3: # %.preheader46
# =>This Loop Header: Depth=1
# Child Loop BB1_5 Depth 2
# Child Loop BB1_6 Depth 3
cmpl $2, %r13d
jl .LBB1_8
# %bb.4: # %.preheader.preheader
# in Loop: Header=BB1_3 Depth=1
movl $1, %eax
xorl %ecx, %ecx
movq 8(%rsp), %rdx # 8-byte Reload
movq %rbp, %rsi
.p2align 4, 0x90
.LBB1_5: # %.preheader
# Parent Loop BB1_3 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_6 Depth 3
xorl %edi, %edi
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_3 Depth=1
# Parent Loop BB1_5 Depth=2
# => This Inner Loop Header: Depth=3
leal (%rcx,%rdi), %r8d
incl %r8d
movss (%r14,%r8,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
leal (%rdx,%rdi), %r8d
addss (%r14,%r8,4), %xmm0
leal (%rsi,%rdi), %r8d
addss (%r14,%r8,4), %xmm0
leal 2(%rsi,%rdi), %r8d
addss (%r14,%r8,4), %xmm0
mulss %xmm1, %xmm0
leal (%rsi,%rdi), %r8d
incl %r8d
movss %xmm0, (%r12,%r8,4)
incq %rdi
cmpq %rdi, %rbx
jne .LBB1_6
# %bb.7: # %._crit_edge
# in Loop: Header=BB1_5 Depth=2
incl %eax
addq %rbp, %rsi
addq %rbp, %rdx
addq %rbp, %rcx
cmpl %r13d, %eax
jne .LBB1_5
jmp .LBB1_8
.LBB1_9: # %._crit_edge51
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_10:
.cfi_def_cfa_offset 80
movq stderr(%rip), %rdi
movl $.L.str.8, %esi
movq %rbx, %rcx
movl %ecx, %edx
# kill: def $ecx killed $ecx killed $rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z13seq_heat_distPfjj, .Lfunc_end1-_Z13seq_heat_distPfjj
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z13gpu_heat_distPfjj
.LCPI2_0:
.quad 0x3fb0000000000000 # double 0.0625
.text
.globl _Z13gpu_heat_distPfjj
.p2align 4, 0x90
.type _Z13gpu_heat_distPfjj,@function
_Z13gpu_heat_distPfjj: # @_Z13gpu_heat_distPfjj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movl %esi, %r15d
movq %rdi, %r14
movl %esi, %ebx
imull %ebx, %ebx
shll $2, %ebx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %rbx, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %r14, 24(%rsp) # 8-byte Spill
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r15d, %eax
cvtsi2sd %rax, %xmm0
mulsd .LCPI2_0(%rip), %xmm0
callq ceil@PLT
testl %ebp, %ebp
je .LBB2_5
# %bb.1: # %.lr.ph
cvttsd2si %xmm0, %r12
movl %r12d, %eax
shlq $32, %r12
orq %rax, %r12
movabsq $68719476752, %r13 # imm = 0x1000000010
leaq 96(%rsp), %r14
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_4: # in Loop: Header=BB2_2 Depth=1
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rcx, 8(%rsp)
movq %rax, (%rsp)
decl %ebp
je .LBB2_5
.LBB2_2: # =>This Inner Loop Header: Depth=1
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3: # in Loop: Header=BB2_2 Depth=1
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r15d, 20(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z10heatKernelPfS_j, %edi
movq %r14, %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_4
.LBB2_5: # %._crit_edge
movq (%rsp), %rsi
movq 24(%rsp), %rdi # 8-byte Reload
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z13gpu_heat_distPfjj, .Lfunc_end2-_Z13gpu_heat_distPfjj
.cfi_endproc
# -- End function
.globl _Z25__device_stub__heatKernelPfS_j # -- Begin function _Z25__device_stub__heatKernelPfS_j
.p2align 4, 0x90
.type _Z25__device_stub__heatKernelPfS_j,@function
_Z25__device_stub__heatKernelPfS_j: # @_Z25__device_stub__heatKernelPfS_j
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10heatKernelPfS_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z25__device_stub__heatKernelPfS_j, .Lfunc_end3-_Z25__device_stub__heatKernelPfS_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10heatKernelPfS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "usage: heatdist num iterations who\n"
.size .L.str, 38
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "num = dimension of the square matrix (50 and up)\n"
.size .L.str.1, 50
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "iterations = number of iterations till stopping (1 and up)\n"
.size .L.str.2, 60
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "who = 0: sequential code on CPU, 1: GPU execution\n"
.size .L.str.3, 51
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " Cannot allocate the %u x %u array\n"
.size .L.str.4, 36
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Time taken for %s is %lf\n"
.size .L.str.5, 26
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "CPU"
.size .L.str.6, 4
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "GPU"
.size .L.str.7, 4
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz " Cannot allocate temp %u x %u array\n"
.size .L.str.8, 37
.type _Z10heatKernelPfS_j,@object # @_Z10heatKernelPfS_j
.section .rodata,"a",@progbits
.globl _Z10heatKernelPfS_j
.p2align 3, 0x0
_Z10heatKernelPfS_j:
.quad _Z25__device_stub__heatKernelPfS_j
.size _Z10heatKernelPfS_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10heatKernelPfS_j"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__heatKernelPfS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10heatKernelPfS_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #ifdef GALAX_MODEL_GPU
#include "cuda.h"
#include "kernel.cuh"
#include <mipp.h>
#define DIFF_T (0.1f)
#define EPS (1.0f)
inline __host__ __device__ float3 sub(float3 a, float3 b)
{
return make_float3(a.x - b.x, a.y - b.y, a.z - b.z);
}
inline __host__ __device__ float3 add(float3 a, float3 b)
{
return make_float3(a.x + b.x, a.y + b.y, a.z + b.z);
}
inline __host__ __device__ float3 multi1(float3 a, float3 b)
{
return make_float3(a.x * b.x, a.y * b.y, a.z * b.z);
}
inline __host__ __device__ float3 multi2(float3 a, float b)
{
return make_float3(a.x * b, a.y * b, a.z * b);
}
__global__ void compute_acc(float3 * positionsGPU, float3 * velocitiesGPU, float3 * accelerationsGPU, float* massesGPU, int n_particles)
{
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
for (int j = 0; j < n_particles; j++)
{
if(i != j)
{
const float3 diff = sub(positionsGPU[j] , positionsGPU[i]);
float3 dij3 = multi1(diff,diff);
float dij = dij3.x + dij3.y + dij3.z;
if (dij < 1.0)
{
dij = 10.0;
}
else
{
dij = std::sqrt(dij);
dij = 10.0 / (dij * dij * dij);
}
float3 n = multi2(diff, dij);
float3 m = multi2(n,massesGPU[j]);
accelerationsGPU[i] = add(accelerationsGPU[i],m);
}
}
/*
const mipp::Reg<float> rpos_i = &positionsGPU[i];
mipp::Reg<float> racc_i = &accelerationsGPU[i];
const mipp::Reg<float> value =1.0;
const mipp::Reg<float> zero =0.0;
const mipp::Reg<float> G =10.0;
using T = float;
constexpr int N = mipp::N<T>();
auto vecLoopSize = (n_particles / N)* N;
for (int j = 0; j < vecLoopSize; j += N)
{
const mipp::Reg<float3> rpos_j = &positionsGPU[j];
mipp::Reg<float> masses_j = &massesGPU[j];
if(i != j)
{
const mipp::Reg<float3> diff = sub(rpos_j, rpos_i);
const mipp::Reg<float3> dij3 = multi1(diff,diff);
const mipp::Reg<float> dij = dij3.x + dij3.y + dij3.z;
mipp::Msk<N> msk = (dij < value);
dij = mipp::mask<float, mipp::mul>(msk, dij, dij, zero);
dij = mipp::mask<float, mipp::add>(msk, dij, dij, value);
dij = mipp::sqrt(dij);
dij = G / (dij * dij * dij);
float3 n = multi2(diff, dij);
float3 m = multi2(n,masses_j);
racc_i= add(racc_i,m);
}
}
racc_i.store(&accelerationsGPU[i]);
*/
}
__global__ void maj_pos(float3 * positionsGPU, float3 * velocitiesGPU, float3 * accelerationsGPU)
{
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
velocitiesGPU[i] = add(velocitiesGPU[i], multi2(accelerationsGPU[i], 2.0f));
positionsGPU[i] = add(positionsGPU[i], multi2(velocitiesGPU[i], 0.1f));
}
void update_position_cu(float3* positionsGPU, float3* velocitiesGPU, float3* accelerationsGPU, float* massesGPU, int n_particles)
{
int nthreads = 128;
int nblocks = (n_particles + (nthreads -1)) / nthreads;
compute_acc<<<nblocks, nthreads>>>(positionsGPU, velocitiesGPU, accelerationsGPU, massesGPU, n_particles);
maj_pos <<<nblocks, nthreads>>>(positionsGPU, velocitiesGPU, accelerationsGPU);
}
#endif // GALAX_MODEL_GPU | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #ifdef GALAX_MODEL_GPU
#include "cuda.h"
#include "kernel.cuh"
#include <mipp.h>
#define DIFF_T (0.1f)
#define EPS (1.0f)
inline __host__ __device__ float3 sub(float3 a, float3 b)
{
return make_float3(a.x - b.x, a.y - b.y, a.z - b.z);
}
inline __host__ __device__ float3 add(float3 a, float3 b)
{
return make_float3(a.x + b.x, a.y + b.y, a.z + b.z);
}
inline __host__ __device__ float3 multi1(float3 a, float3 b)
{
return make_float3(a.x * b.x, a.y * b.y, a.z * b.z);
}
inline __host__ __device__ float3 multi2(float3 a, float b)
{
return make_float3(a.x * b, a.y * b, a.z * b);
}
__global__ void compute_acc(float3 * positionsGPU, float3 * velocitiesGPU, float3 * accelerationsGPU, float* massesGPU, int n_particles)
{
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
for (int j = 0; j < n_particles; j++)
{
if(i != j)
{
const float3 diff = sub(positionsGPU[j] , positionsGPU[i]);
float3 dij3 = multi1(diff,diff);
float dij = dij3.x + dij3.y + dij3.z;
if (dij < 1.0)
{
dij = 10.0;
}
else
{
dij = std::sqrt(dij);
dij = 10.0 / (dij * dij * dij);
}
float3 n = multi2(diff, dij);
float3 m = multi2(n,massesGPU[j]);
accelerationsGPU[i] = add(accelerationsGPU[i],m);
}
}
/*
const mipp::Reg<float> rpos_i = &positionsGPU[i];
mipp::Reg<float> racc_i = &accelerationsGPU[i];
const mipp::Reg<float> value =1.0;
const mipp::Reg<float> zero =0.0;
const mipp::Reg<float> G =10.0;
using T = float;
constexpr int N = mipp::N<T>();
auto vecLoopSize = (n_particles / N)* N;
for (int j = 0; j < vecLoopSize; j += N)
{
const mipp::Reg<float3> rpos_j = &positionsGPU[j];
mipp::Reg<float> masses_j = &massesGPU[j];
if(i != j)
{
const mipp::Reg<float3> diff = sub(rpos_j, rpos_i);
const mipp::Reg<float3> dij3 = multi1(diff,diff);
const mipp::Reg<float> dij = dij3.x + dij3.y + dij3.z;
mipp::Msk<N> msk = (dij < value);
dij = mipp::mask<float, mipp::mul>(msk, dij, dij, zero);
dij = mipp::mask<float, mipp::add>(msk, dij, dij, value);
dij = mipp::sqrt(dij);
dij = G / (dij * dij * dij);
float3 n = multi2(diff, dij);
float3 m = multi2(n,masses_j);
racc_i= add(racc_i,m);
}
}
racc_i.store(&accelerationsGPU[i]);
*/
}
__global__ void maj_pos(float3 * positionsGPU, float3 * velocitiesGPU, float3 * accelerationsGPU)
{
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
velocitiesGPU[i] = add(velocitiesGPU[i], multi2(accelerationsGPU[i], 2.0f));
positionsGPU[i] = add(positionsGPU[i], multi2(velocitiesGPU[i], 0.1f));
}
void update_position_cu(float3* positionsGPU, float3* velocitiesGPU, float3* accelerationsGPU, float* massesGPU, int n_particles)
{
int nthreads = 128;
int nblocks = (n_particles + (nthreads -1)) / nthreads;
compute_acc<<<nblocks, nthreads>>>(positionsGPU, velocitiesGPU, accelerationsGPU, massesGPU, n_particles);
maj_pos <<<nblocks, nthreads>>>(positionsGPU, velocitiesGPU, accelerationsGPU);
}
#endif // GALAX_MODEL_GPU | .file "tmpxft_000c89e0_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #ifdef GALAX_MODEL_GPU
#include "cuda.h"
#include "kernel.cuh"
#include <mipp.h>
#define DIFF_T (0.1f)
#define EPS (1.0f)
inline __host__ __device__ float3 sub(float3 a, float3 b)
{
return make_float3(a.x - b.x, a.y - b.y, a.z - b.z);
}
inline __host__ __device__ float3 add(float3 a, float3 b)
{
return make_float3(a.x + b.x, a.y + b.y, a.z + b.z);
}
inline __host__ __device__ float3 multi1(float3 a, float3 b)
{
return make_float3(a.x * b.x, a.y * b.y, a.z * b.z);
}
inline __host__ __device__ float3 multi2(float3 a, float b)
{
return make_float3(a.x * b, a.y * b, a.z * b);
}
__global__ void compute_acc(float3 * positionsGPU, float3 * velocitiesGPU, float3 * accelerationsGPU, float* massesGPU, int n_particles)
{
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
for (int j = 0; j < n_particles; j++)
{
if(i != j)
{
const float3 diff = sub(positionsGPU[j] , positionsGPU[i]);
float3 dij3 = multi1(diff,diff);
float dij = dij3.x + dij3.y + dij3.z;
if (dij < 1.0)
{
dij = 10.0;
}
else
{
dij = std::sqrt(dij);
dij = 10.0 / (dij * dij * dij);
}
float3 n = multi2(diff, dij);
float3 m = multi2(n,massesGPU[j]);
accelerationsGPU[i] = add(accelerationsGPU[i],m);
}
}
/*
const mipp::Reg<float> rpos_i = &positionsGPU[i];
mipp::Reg<float> racc_i = &accelerationsGPU[i];
const mipp::Reg<float> value =1.0;
const mipp::Reg<float> zero =0.0;
const mipp::Reg<float> G =10.0;
using T = float;
constexpr int N = mipp::N<T>();
auto vecLoopSize = (n_particles / N)* N;
for (int j = 0; j < vecLoopSize; j += N)
{
const mipp::Reg<float3> rpos_j = &positionsGPU[j];
mipp::Reg<float> masses_j = &massesGPU[j];
if(i != j)
{
const mipp::Reg<float3> diff = sub(rpos_j, rpos_i);
const mipp::Reg<float3> dij3 = multi1(diff,diff);
const mipp::Reg<float> dij = dij3.x + dij3.y + dij3.z;
mipp::Msk<N> msk = (dij < value);
dij = mipp::mask<float, mipp::mul>(msk, dij, dij, zero);
dij = mipp::mask<float, mipp::add>(msk, dij, dij, value);
dij = mipp::sqrt(dij);
dij = G / (dij * dij * dij);
float3 n = multi2(diff, dij);
float3 m = multi2(n,masses_j);
racc_i= add(racc_i,m);
}
}
racc_i.store(&accelerationsGPU[i]);
*/
}
__global__ void maj_pos(float3 * positionsGPU, float3 * velocitiesGPU, float3 * accelerationsGPU)
{
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
velocitiesGPU[i] = add(velocitiesGPU[i], multi2(accelerationsGPU[i], 2.0f));
positionsGPU[i] = add(positionsGPU[i], multi2(velocitiesGPU[i], 0.1f));
}
void update_position_cu(float3* positionsGPU, float3* velocitiesGPU, float3* accelerationsGPU, float* massesGPU, int n_particles)
{
int nthreads = 128;
int nblocks = (n_particles + (nthreads -1)) / nthreads;
compute_acc<<<nblocks, nthreads>>>(positionsGPU, velocitiesGPU, accelerationsGPU, massesGPU, n_particles);
maj_pos <<<nblocks, nthreads>>>(positionsGPU, velocitiesGPU, accelerationsGPU);
}
#endif // GALAX_MODEL_GPU | #ifdef GALAX_MODEL_GPU
#ifndef __KERNEL_CUH__
#define __KERNEL_CUH__
#include <hip/hip_runtime.h>
#include <stdio.h>
void update_position_cu(float3* positionsGPU, float3* velocitiesGPU, float3* accelerationsGPU, float* massesGPU, int n_particles);
#endif
#endif // GALAX_MODEL_GPU |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifdef GALAX_MODEL_GPU
#ifndef __KERNEL_CUH__
#define __KERNEL_CUH__
#include <hip/hip_runtime.h>
#include <stdio.h>
void update_position_cu(float3* positionsGPU, float3* velocitiesGPU, float3* accelerationsGPU, float* massesGPU, int n_particles);
#endif
#endif // GALAX_MODEL_GPU | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifdef GALAX_MODEL_GPU
#ifndef __KERNEL_CUH__
#define __KERNEL_CUH__
#include <hip/hip_runtime.h>
#include <stdio.h>
void update_position_cu(float3* positionsGPU, float3* velocitiesGPU, float3* accelerationsGPU, float* massesGPU, int n_particles);
#endif
#endif // GALAX_MODEL_GPU | .text
.file "kernel.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c89e0_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kExpand(float* source, float* indices, float* target, int height, int width, int target_width){
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < target_width*height; i += numThreads) {
const int pos = height * (int)indices[i / height] + i % height;
target[i] = (pos < height * width)? source[pos] : 1.0/0.0 - 1.0/0.0;
}
} | code for sm_80
Function : _Z7kExpandPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ ULDC UR5, c[0x0][0x178] ; /* 0x00005e0000057ab9 */
/* 0x000fe20000000800 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe2000f8e023f */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0070*/ ISETP.GE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06070 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ ULDC.64 UR6, c[0x0][0x178] ; /* 0x00005e0000067ab9 */
/* 0x000fe40000000a00 */
/*00a0*/ UIMAD UR5, UR7, UR6, URZ ; /* 0x00000006070572a4 */
/* 0x000fc6000f8e023f */
/*00b0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*00c0*/ I2F.U32.RP R4, c[0x0][0x178] ; /* 0x00005e0000047b06 */
/* 0x001e220000209000 */
/*00d0*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fce0003f45070 */
/*00e0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*00f0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0110*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe200078e00ff */
/*0120*/ IADD3 R5, RZ, -R3, RZ ; /* 0x80000003ff057210 */
/* 0x002fca0007ffe0ff */
/*0130*/ IMAD R5, R5, c[0x0][0x178], RZ ; /* 0x00005e0005057a24 */
/* 0x000fc800078e02ff */
/*0140*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fc800078e0002 */
/*0150*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe400078e00ff */
/*0160*/ IMAD.HI.U32 R5, R3, R0, RZ ; /* 0x0000000003057227 */
/* 0x000fca00078e00ff */
/*0170*/ IADD3 R3, -R5, RZ, RZ ; /* 0x000000ff05037210 */
/* 0x000fca0007ffe1ff */
/*0180*/ IMAD R3, R3, c[0x0][0x178], R0 ; /* 0x00005e0003037a24 */
/* 0x000fca00078e0200 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IADD3 R3, R3, -c[0x0][0x178], RZ ; /* 0x80005e0003030a10 */
/* 0x000fe40007ffe0ff */
/*01b0*/ @P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105050810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105051810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R5, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff05aa12 */
/* 0x000fca00078e33ff */
/*01f0*/ IMAD.WIDE.U32 R2, R5, R2, c[0x0][0x168] ; /* 0x00005a0005027625 */
/* 0x000fcc00078e0002 */
/*0200*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*0210*/ IADD3 R5, -R5, RZ, RZ ; /* 0x000000ff05057210 */
/* 0x000fca0007ffe1ff */
/*0220*/ IMAD R5, R5, c[0x0][0x178], R0 ; /* 0x00005e0005057a24 */
/* 0x000fe200078e0200 */
/*0230*/ F2I.TRUNC.NTZ R4, R2 ; /* 0x0000000200047305 */
/* 0x004064000020f100 */
/*0240*/ MOV R2, 0x280 ; /* 0x0000028000027802 */
/* 0x001fe20000000f00 */
/*0250*/ IMAD R4, R4, c[0x0][0x178], R5 ; /* 0x00005e0004047a24 */
/* 0x002fca00078e0205 */
/*0260*/ ISETP.GE.AND P0, PT, R4, UR5, PT ; /* 0x0000000504007c0c */
/* 0x000fd0000bf06270 */
/*0270*/ CALL.REL.NOINC 0x370 ; /* 0x000000f000007944 */
/* 0x000fea0003c00000 */
/*0280*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc800078e00ff */
/*0290*/ @!P0 IMAD.WIDE R4, R4, R9, c[0x0][0x160] ; /* 0x0000580004048625 */
/* 0x000fcc00078e0209 */
/*02a0*/ @!P0 LDG.E R4, [R4.64] ; /* 0x0000000604048981 */
/* 0x000ea2000c1e1900 */
/*02b0*/ MOV R2, R6 ; /* 0x0000000600027202 */
/* 0x000fe20000000f00 */
/*02c0*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0007 */
/*02d0*/ IMAD.WIDE.U32 R6, R0, R9, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0009 */
/*02e0*/ MOV R9, c[0x0][0x0] ; /* 0x0000000000097a02 */
/* 0x000fc60000000f00 */
/*02f0*/ DADD R2, R2, -R2 ; /* 0x0000000002027229 */
/* 0x000ea40000000802 */
/*0300*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fd000078e0200 */
/*0310*/ @!P0 F2F.F64.F32 R2, R4 ; /* 0x0000000400028310 */
/* 0x004e220000201800 */
/*0320*/ ISETP.GE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fce000bf06070 */
/*0330*/ F2F.F32.F64 R3, R2 ; /* 0x0000000200037310 */
/* 0x001e240000301000 */
/*0340*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x0011e8000c101906 */
/*0350*/ @!P0 BRA 0xc0 ; /* 0xfffffd6000008947 */
/* 0x000fea000383ffff */
/*0360*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0370*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fe200078e00ff */
/*0380*/ MOV R7, 0x7ff00000 ; /* 0x7ff0000000077802 */
/* 0x000fe20000000f00 */
/*0390*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*03a0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffffc5002007950 */
/* 0x000fea0003c3ffff */
/*03b0*/ BRA 0x3b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kExpand(float* source, float* indices, float* target, int height, int width, int target_width){
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < target_width*height; i += numThreads) {
const int pos = height * (int)indices[i / height] + i % height;
target[i] = (pos < height * width)? source[pos] : 1.0/0.0 - 1.0/0.0;
}
} | .file "tmpxft_00050280_00000000-6_kExpand.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z7kExpandPfS_S_iiiPfS_S_iii
.type _Z33__device_stub__Z7kExpandPfS_S_iiiPfS_S_iii, @function
_Z33__device_stub__Z7kExpandPfS_S_iiiPfS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7kExpandPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z7kExpandPfS_S_iiiPfS_S_iii, .-_Z33__device_stub__Z7kExpandPfS_S_iiiPfS_S_iii
.globl _Z7kExpandPfS_S_iii
.type _Z7kExpandPfS_S_iii, @function
_Z7kExpandPfS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z7kExpandPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7kExpandPfS_S_iii, .-_Z7kExpandPfS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7kExpandPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kExpandPfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kExpand(float* source, float* indices, float* target, int height, int width, int target_width){
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < target_width*height; i += numThreads) {
const int pos = height * (int)indices[i / height] + i % height;
target[i] = (pos < height * width)? source[pos] : 1.0/0.0 - 1.0/0.0;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kExpand(float* source, float* indices, float* target, int height, int width, int target_width){
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < target_width*height; i += numThreads) {
const int pos = height * (int)indices[i / height] + i % height;
target[i] = (pos < height * width)? source[pos] : 1.0/0.0 - 1.0/0.0;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kExpand(float* source, float* indices, float* target, int height, int width, int target_width){
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < target_width*height; i += numThreads) {
const int pos = height * (int)indices[i / height] + i % height;
target[i] = (pos < height * width)? source[pos] : 1.0/0.0 - 1.0/0.0;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7kExpandPfS_S_iii
.globl _Z7kExpandPfS_S_iii
.p2align 8
.type _Z7kExpandPfS_S_iii,@function
_Z7kExpandPfS_S_iii:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s8, s[0:1], 0x18
s_load_b32 s9, s[0:1], 0x20
s_add_u32 s2, s0, 40
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s11, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s11, v[0:1]
s_mul_i32 s9, s9, s8
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmpx_gt_u32_e64 s9, v1
s_cbranch_execz .LBB0_5
v_cvt_f32_u32_e32 v0, s8
s_sub_i32 s10, 0, s8
s_load_b32 s12, s[2:3], 0x0
s_clause 0x2
s_load_b32 s13, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_dual_mov_b32 v3, 0 :: v_dual_mul_f32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s12, s11
s_mul_i32 s11, s13, s8
s_mov_b32 s12, 0
v_mul_lo_u32 v2, s10, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
v_mov_b32_e32 v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_cmp_le_u32_e32 vcc_lo, s9, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v6, s0, s2, v6
v_add_co_ci_u32_e64 v7, s0, s3, v7, s0
s_or_b32 s12, vcc_lo, s12
s_waitcnt vmcnt(0)
global_store_b32 v[6:7], v5, off
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execz .LBB0_5
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v1, v0
s_mov_b32 s0, exec_lo
v_mad_u64_u32 v[4:5], null, s10, v2, v[1:2]
v_not_b32_e32 v7, v2
v_add_nc_u32_e32 v8, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mad_u64_u32 v[5:6], null, s8, v7, v[1:2]
v_cmp_le_u32_e32 vcc_lo, s8, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v8, vcc_lo
v_dual_cndmask_b32 v4, v4, v5 :: v_dual_add_nc_u32 v5, 1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s8, v4
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v4, v4
v_sub_nc_u32_e32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[4:5], null, s8, v2, v[1:2]
v_mov_b32_e32 v5, 0x7fc00000
v_cmpx_gt_i32_e64 s11, v4
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v5, v[4:5], off
s_branch .LBB0_2
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kExpandPfS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7kExpandPfS_S_iii, .Lfunc_end0-_Z7kExpandPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kExpandPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7kExpandPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kExpand(float* source, float* indices, float* target, int height, int width, int target_width){
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < target_width*height; i += numThreads) {
const int pos = height * (int)indices[i / height] + i % height;
target[i] = (pos < height * width)? source[pos] : 1.0/0.0 - 1.0/0.0;
}
} | .text
.file "kExpand.hip"
.globl _Z22__device_stub__kExpandPfS_S_iii # -- Begin function _Z22__device_stub__kExpandPfS_S_iii
.p2align 4, 0x90
.type _Z22__device_stub__kExpandPfS_S_iii,@function
_Z22__device_stub__kExpandPfS_S_iii: # @_Z22__device_stub__kExpandPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7kExpandPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z22__device_stub__kExpandPfS_S_iii, .Lfunc_end0-_Z22__device_stub__kExpandPfS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kExpandPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7kExpandPfS_S_iii,@object # @_Z7kExpandPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z7kExpandPfS_S_iii
.p2align 3, 0x0
_Z7kExpandPfS_S_iii:
.quad _Z22__device_stub__kExpandPfS_S_iii
.size _Z7kExpandPfS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7kExpandPfS_S_iii"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__kExpandPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7kExpandPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7kExpandPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ ULDC UR5, c[0x0][0x178] ; /* 0x00005e0000057ab9 */
/* 0x000fe20000000800 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe2000f8e023f */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0070*/ ISETP.GE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06070 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ ULDC.64 UR6, c[0x0][0x178] ; /* 0x00005e0000067ab9 */
/* 0x000fe40000000a00 */
/*00a0*/ UIMAD UR5, UR7, UR6, URZ ; /* 0x00000006070572a4 */
/* 0x000fc6000f8e023f */
/*00b0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*00c0*/ I2F.U32.RP R4, c[0x0][0x178] ; /* 0x00005e0000047b06 */
/* 0x001e220000209000 */
/*00d0*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fce0003f45070 */
/*00e0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*00f0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0110*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe200078e00ff */
/*0120*/ IADD3 R5, RZ, -R3, RZ ; /* 0x80000003ff057210 */
/* 0x002fca0007ffe0ff */
/*0130*/ IMAD R5, R5, c[0x0][0x178], RZ ; /* 0x00005e0005057a24 */
/* 0x000fc800078e02ff */
/*0140*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fc800078e0002 */
/*0150*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe400078e00ff */
/*0160*/ IMAD.HI.U32 R5, R3, R0, RZ ; /* 0x0000000003057227 */
/* 0x000fca00078e00ff */
/*0170*/ IADD3 R3, -R5, RZ, RZ ; /* 0x000000ff05037210 */
/* 0x000fca0007ffe1ff */
/*0180*/ IMAD R3, R3, c[0x0][0x178], R0 ; /* 0x00005e0003037a24 */
/* 0x000fca00078e0200 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IADD3 R3, R3, -c[0x0][0x178], RZ ; /* 0x80005e0003030a10 */
/* 0x000fe40007ffe0ff */
/*01b0*/ @P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105050810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105051810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R5, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff05aa12 */
/* 0x000fca00078e33ff */
/*01f0*/ IMAD.WIDE.U32 R2, R5, R2, c[0x0][0x168] ; /* 0x00005a0005027625 */
/* 0x000fcc00078e0002 */
/*0200*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*0210*/ IADD3 R5, -R5, RZ, RZ ; /* 0x000000ff05057210 */
/* 0x000fca0007ffe1ff */
/*0220*/ IMAD R5, R5, c[0x0][0x178], R0 ; /* 0x00005e0005057a24 */
/* 0x000fe200078e0200 */
/*0230*/ F2I.TRUNC.NTZ R4, R2 ; /* 0x0000000200047305 */
/* 0x004064000020f100 */
/*0240*/ MOV R2, 0x280 ; /* 0x0000028000027802 */
/* 0x001fe20000000f00 */
/*0250*/ IMAD R4, R4, c[0x0][0x178], R5 ; /* 0x00005e0004047a24 */
/* 0x002fca00078e0205 */
/*0260*/ ISETP.GE.AND P0, PT, R4, UR5, PT ; /* 0x0000000504007c0c */
/* 0x000fd0000bf06270 */
/*0270*/ CALL.REL.NOINC 0x370 ; /* 0x000000f000007944 */
/* 0x000fea0003c00000 */
/*0280*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc800078e00ff */
/*0290*/ @!P0 IMAD.WIDE R4, R4, R9, c[0x0][0x160] ; /* 0x0000580004048625 */
/* 0x000fcc00078e0209 */
/*02a0*/ @!P0 LDG.E R4, [R4.64] ; /* 0x0000000604048981 */
/* 0x000ea2000c1e1900 */
/*02b0*/ MOV R2, R6 ; /* 0x0000000600027202 */
/* 0x000fe20000000f00 */
/*02c0*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0007 */
/*02d0*/ IMAD.WIDE.U32 R6, R0, R9, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0009 */
/*02e0*/ MOV R9, c[0x0][0x0] ; /* 0x0000000000097a02 */
/* 0x000fc60000000f00 */
/*02f0*/ DADD R2, R2, -R2 ; /* 0x0000000002027229 */
/* 0x000ea40000000802 */
/*0300*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fd000078e0200 */
/*0310*/ @!P0 F2F.F64.F32 R2, R4 ; /* 0x0000000400028310 */
/* 0x004e220000201800 */
/*0320*/ ISETP.GE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fce000bf06070 */
/*0330*/ F2F.F32.F64 R3, R2 ; /* 0x0000000200037310 */
/* 0x001e240000301000 */
/*0340*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x0011e8000c101906 */
/*0350*/ @!P0 BRA 0xc0 ; /* 0xfffffd6000008947 */
/* 0x000fea000383ffff */
/*0360*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0370*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fe200078e00ff */
/*0380*/ MOV R7, 0x7ff00000 ; /* 0x7ff0000000077802 */
/* 0x000fe20000000f00 */
/*0390*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*03a0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffffc5002007950 */
/* 0x000fea0003c3ffff */
/*03b0*/ BRA 0x3b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7kExpandPfS_S_iii
.globl _Z7kExpandPfS_S_iii
.p2align 8
.type _Z7kExpandPfS_S_iii,@function
_Z7kExpandPfS_S_iii:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s8, s[0:1], 0x18
s_load_b32 s9, s[0:1], 0x20
s_add_u32 s2, s0, 40
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s11, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s11, v[0:1]
s_mul_i32 s9, s9, s8
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmpx_gt_u32_e64 s9, v1
s_cbranch_execz .LBB0_5
v_cvt_f32_u32_e32 v0, s8
s_sub_i32 s10, 0, s8
s_load_b32 s12, s[2:3], 0x0
s_clause 0x2
s_load_b32 s13, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_dual_mov_b32 v3, 0 :: v_dual_mul_f32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s12, s11
s_mul_i32 s11, s13, s8
s_mov_b32 s12, 0
v_mul_lo_u32 v2, s10, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
v_mov_b32_e32 v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_cmp_le_u32_e32 vcc_lo, s9, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v6, s0, s2, v6
v_add_co_ci_u32_e64 v7, s0, s3, v7, s0
s_or_b32 s12, vcc_lo, s12
s_waitcnt vmcnt(0)
global_store_b32 v[6:7], v5, off
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execz .LBB0_5
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v1, v0
s_mov_b32 s0, exec_lo
v_mad_u64_u32 v[4:5], null, s10, v2, v[1:2]
v_not_b32_e32 v7, v2
v_add_nc_u32_e32 v8, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mad_u64_u32 v[5:6], null, s8, v7, v[1:2]
v_cmp_le_u32_e32 vcc_lo, s8, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v8, vcc_lo
v_dual_cndmask_b32 v4, v4, v5 :: v_dual_add_nc_u32 v5, 1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s8, v4
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v4, v4
v_sub_nc_u32_e32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[4:5], null, s8, v2, v[1:2]
v_mov_b32_e32 v5, 0x7fc00000
v_cmpx_gt_i32_e64 s11, v4
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v5, v[4:5], off
s_branch .LBB0_2
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kExpandPfS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7kExpandPfS_S_iii, .Lfunc_end0-_Z7kExpandPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kExpandPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7kExpandPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00050280_00000000-6_kExpand.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z7kExpandPfS_S_iiiPfS_S_iii
.type _Z33__device_stub__Z7kExpandPfS_S_iiiPfS_S_iii, @function
_Z33__device_stub__Z7kExpandPfS_S_iiiPfS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7kExpandPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z7kExpandPfS_S_iiiPfS_S_iii, .-_Z33__device_stub__Z7kExpandPfS_S_iiiPfS_S_iii
.globl _Z7kExpandPfS_S_iii
.type _Z7kExpandPfS_S_iii, @function
_Z7kExpandPfS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z7kExpandPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7kExpandPfS_S_iii, .-_Z7kExpandPfS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7kExpandPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kExpandPfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kExpand.hip"
.globl _Z22__device_stub__kExpandPfS_S_iii # -- Begin function _Z22__device_stub__kExpandPfS_S_iii
.p2align 4, 0x90
.type _Z22__device_stub__kExpandPfS_S_iii,@function
_Z22__device_stub__kExpandPfS_S_iii: # @_Z22__device_stub__kExpandPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7kExpandPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z22__device_stub__kExpandPfS_S_iii, .Lfunc_end0-_Z22__device_stub__kExpandPfS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kExpandPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7kExpandPfS_S_iii,@object # @_Z7kExpandPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z7kExpandPfS_S_iii
.p2align 3, 0x0
_Z7kExpandPfS_S_iii:
.quad _Z22__device_stub__kExpandPfS_S_iii
.size _Z7kExpandPfS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7kExpandPfS_S_iii"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__kExpandPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7kExpandPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* Write GPU code to perform the step(s) involved in counting sort.
Add additional kernels and device functions as needed. */
#define MAX_KERNEL_WIDTH 256
#define HISTOGRAM_SIZE 256
__constant__ int kernel_c[MAX_KERNEL_WIDTH];
__global__ void counting_sort_kernel(int* in, int* bins, int num_elements, int histogram_size)
{
__shared__ int s[HISTOGRAM_SIZE];
/* Initialize shared memory */
if(threadIdx.x < histogram_size)
s[threadIdx.x] = 0;
__syncthreads();
int offset = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
while (offset < num_elements) {
atomicAdd(&s[in[offset]], 1);
offset += stride;
}
__syncthreads();
/* Accumulate histogram in shared memory into global memory */
if (threadIdx.x < histogram_size)
atomicAdd(&bins[threadIdx.x], s[threadIdx.x]);
return;
}
__global__ void scan_kernel(int *out, int *in, int n)
{
/* Dynamically allocated shared memory for storing the scan array */
extern __shared__ int temp[];
int tid = threadIdx.x;
/* Indices for the ping-pong buffers */
int pout = 0;
int pin = 1;
/* Load the in array from global memory into shared memory */
if (tid > 0)
temp[pout * n + tid] = in[tid - 1];
else
temp[pout * n + tid] = 0;
int offset;
for (offset = 1; offset < n; offset *= 2) {
pout = 1 - pout;
pin = 1 - pout;
__syncthreads();
temp[pout * n + tid] = temp[pin * n + tid];
if (tid >= offset)
temp[pout * n + tid] += temp[pin * n + tid - offset];
}
__syncthreads();
out[tid] = temp[pout * n + tid];
}
/* scan_d stored in kernel_c */
__global__ void recreate_array_kernel(int* output, int num_elements, int histogram_size)
{
int offset = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
int curr_bin = 0;
int next_bin = 1;
/*
Stride over the output element
stride over the bins at the same time
if the bin value needs writing to the current offset, write and stride
else move to next bin
runtime = O(bin_size + num_element / total_threads)
*/
/*
if b[prev] =< i < b[curr] ::=> Write+stride
else ::=> bin++
*/
while((offset < num_elements) || (curr_bin < histogram_size)){
if( ( offset >= kernel_c[curr_bin] ) && ( offset < kernel_c[next_bin] ) ){
output[offset] = curr_bin;
offset += stride;
}else{
curr_bin = next_bin;
next_bin++;
}
}
} | code for sm_80
Function : _Z21recreate_array_kernelPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff027624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f06270 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f26270 */
/*0070*/ @!P0 EXIT P1 ; /* 0x000000000000894d */
/* 0x000fea0000800000 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*0090*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe200078e00ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fce0000000a00 */
/*00b0*/ IMAD.SHL.U32 R7, R4, 0x4, RZ ; /* 0x0000000404077824 */
/* 0x000fe200078e00ff */
/*00c0*/ SHF.L.U32 R6, R5, 0x2, RZ ; /* 0x0000000205067819 */
/* 0x000fc800000006ff */
/*00d0*/ LDC R3, c[0x3][R6] ; /* 0x00c0000006037b82 */
/* 0x000e300000000800 */
/*00e0*/ LDC R7, c[0x3][R7] ; /* 0x00c0000007077b82 */
/* 0x000e640000000800 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x002fc80003f06270 */
/*0100*/ ISETP.LT.OR P0, PT, R0, R3, P0 ; /* 0x000000030000720c */
/* 0x001fda0000701670 */
/*0110*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff038424 */
/* 0x000fe200078e00ff */
/*0120*/ @!P0 MOV R9, c[0x0][0x0] ; /* 0x0000000000098a02 */
/* 0x000fe40000000f00 */
/*0130*/ @P0 IADD3 R8, R4, 0x1, RZ ; /* 0x0000000104080810 */
/* 0x000fe20007ffe0ff */
/*0140*/ @!P0 IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000028625 */
/* 0x000fc800078e0203 */
/*0150*/ @!P0 IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009008a24 */
/* 0x000fe200078e0200 */
/*0160*/ @!P0 STG.E [R2.64], R5 ; /* 0x0000000502008986 */
/* 0x0001e4000c101904 */
/*0170*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, R4 ; /* 0x000000ffff050224 */
/* 0x000fe200078e0004 */
/*0180*/ @P0 MOV R4, R8 ; /* 0x0000000800040202 */
/* 0x000fc80000000f00 */
/*0190*/ ISETP.GE.AND P1, PT, R5, c[0x0][0x16c], PT ; /* 0x00005b0005007a0c */
/* 0x000fc80003f26270 */
/*01a0*/ ISETP.LT.OR P1, PT, R0, c[0x0][0x168], !P1 ; /* 0x00005a0000007a0c */
/* 0x000fda0004f21670 */
/*01b0*/ @P1 BRA 0xb0 ; /* 0xfffffef000001947 */
/* 0x001fea000383ffff */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11scan_kernelPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ ISETP.GT.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f04270 */
/*0040*/ @P0 IADD3 R2, R7, -0x1, RZ ; /* 0xffffffff07020810 */
/* 0x000fe40007ffe0ff */
/*0050*/ @P0 MOV R3, 0x4 ; /* 0x0000000400030802 */
/* 0x000fca0000000f00 */
/*0060*/ @P0 IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002020625 */
/* 0x000fcc00078e0203 */
/*0070*/ @P0 LDG.E R2, [R2.64] ; /* 0x0000000402020981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff007624 */
/* 0x000fc600078e00ff */
/*0090*/ @!P0 STS [R7.X4], RZ ; /* 0x000000ff07008388 */
/* 0x0001e40000004800 */
/*00a0*/ ISETP.GE.AND P1, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe20003f26270 */
/*00b0*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fe200000001ff */
/*00c0*/ @P0 STS [R7.X4], R2 ; /* 0x0000000207000388 */
/* 0x0041f60000004800 */
/*00d0*/ @!P1 BRA 0x1f0 ; /* 0x0000011000009947 */
/* 0x000fea0003800000 */
/*00e0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*00f0*/ MOV R2, 0x1 ; /* 0x0000000100027802 */
/* 0x001fc40000000f00 */
/*0100*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0110*/ IMAD R5, R0, c[0x0][0x170], R7 ; /* 0x00005c0000057a24 */
/* 0x000fe200078e0207 */
/*0120*/ ISETP.GE.AND P0, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fc40003f06270 */
/*0130*/ IADD3 R0, -R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fca0007ffe1ff */
/*0140*/ IMAD R3, R0, c[0x0][0x170], R7 ; /* 0x00005c0000037a24 */
/* 0x000fc800078e0207 */
/*0150*/ IMAD.SHL.U32 R9, R3, 0x4, RZ ; /* 0x0000000403097824 */
/* 0x000fe400078e00ff */
/*0160*/ @P0 IADD3 R3, R5, -R2, RZ ; /* 0x8000000205030210 */
/* 0x000fe40007ffe0ff */
/*0170*/ SHF.L.U32 R2, R2, 0x1, RZ ; /* 0x0000000102027819 */
/* 0x000fe200000006ff */
/*0180*/ LDS R6, [R5.X4] ; /* 0x0000000005067984 */
/* 0x000e280000004800 */
/*0190*/ STS [R9], R6 ; /* 0x0000000609007388 */
/* 0x001fe80000000800 */
/*01a0*/ @P0 LDS R3, [R3.X4] ; /* 0x0000000003030984 */
/* 0x000e240000004800 */
/*01b0*/ @P0 IMAD.IADD R4, R6, 0x1, R3 ; /* 0x0000000106040824 */
/* 0x001fca00078e0203 */
/*01c0*/ @P0 STS [R9], R4 ; /* 0x0000000409000388 */
/* 0x0001e20000000800 */
/*01d0*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06270 */
/*01e0*/ @!P0 BRA 0x100 ; /* 0xffffff1000008947 */
/* 0x001fea000383ffff */
/*01f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0200*/ IMAD R5, R0, c[0x0][0x170], R7 ; /* 0x00005c0000057a24 */
/* 0x000fe400078e0207 */
/*0210*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x001fc800078e00ff */
/*0220*/ IMAD.WIDE R2, R7, R2, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x000fe200078e0202 */
/*0230*/ LDS R5, [R5.X4] ; /* 0x0000000005057984 */
/* 0x000e280000004800 */
/*0240*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0250*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0260*/ BRA 0x260; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z20counting_sort_kernelPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x174], PT ; /* 0x00005d0004007a0c */
/* 0x001fe20003f06070 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R4 ; /* 0x0000000003007a24 */
/* 0x002fca00078e0204 */
/*0060*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fce0003f26270 */
/*0070*/ @!P0 STS [R4.X4], RZ ; /* 0x000000ff04008388 */
/* 0x0001e80000004800 */
/*0080*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0090*/ @P1 BRA 0x130 ; /* 0x0000009000001947 */
/* 0x001fea0003800000 */
/*00a0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fcc00078e0203 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ MOV R5, c[0x0][0x0] ; /* 0x0000000000057a02 */
/* 0x000fe20000000f00 */
/*00e0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe80003800000 */
/*00f0*/ IMAD R0, R5, c[0x0][0xc], R0 ; /* 0x0000030005007a24 */
/* 0x000fca00078e0200 */
/*0100*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f26270 */
/*0110*/ ATOMS.POPC.INC.32 RZ, [R2.X4+URZ] ; /* 0x0000000002ff7f8c */
/* 0x0041d8000d00403f */
/*0120*/ @!P1 BRA 0xa0 ; /* 0xffffff7000009947 */
/* 0x000fea000383ffff */
/*0130*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0150*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0160*/ LDS R5, [R4.X4] ; /* 0x0000000004057984 */
/* 0x000e620000004800 */
/*0170*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0180*/ IMAD.WIDE.U32 R2, R4, R3, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x001fca00078e0003 */
/*0190*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x002fe2000c10e184 */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* Write GPU code to perform the step(s) involved in counting sort.
Add additional kernels and device functions as needed. */
#define MAX_KERNEL_WIDTH 256
#define HISTOGRAM_SIZE 256
__constant__ int kernel_c[MAX_KERNEL_WIDTH];
__global__ void counting_sort_kernel(int* in, int* bins, int num_elements, int histogram_size)
{
__shared__ int s[HISTOGRAM_SIZE];
/* Initialize shared memory */
if(threadIdx.x < histogram_size)
s[threadIdx.x] = 0;
__syncthreads();
int offset = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
while (offset < num_elements) {
atomicAdd(&s[in[offset]], 1);
offset += stride;
}
__syncthreads();
/* Accumulate histogram in shared memory into global memory */
if (threadIdx.x < histogram_size)
atomicAdd(&bins[threadIdx.x], s[threadIdx.x]);
return;
}
__global__ void scan_kernel(int *out, int *in, int n)
{
/* Dynamically allocated shared memory for storing the scan array */
extern __shared__ int temp[];
int tid = threadIdx.x;
/* Indices for the ping-pong buffers */
int pout = 0;
int pin = 1;
/* Load the in array from global memory into shared memory */
if (tid > 0)
temp[pout * n + tid] = in[tid - 1];
else
temp[pout * n + tid] = 0;
int offset;
for (offset = 1; offset < n; offset *= 2) {
pout = 1 - pout;
pin = 1 - pout;
__syncthreads();
temp[pout * n + tid] = temp[pin * n + tid];
if (tid >= offset)
temp[pout * n + tid] += temp[pin * n + tid - offset];
}
__syncthreads();
out[tid] = temp[pout * n + tid];
}
/* scan_d stored in kernel_c */
__global__ void recreate_array_kernel(int* output, int num_elements, int histogram_size)
{
int offset = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
int curr_bin = 0;
int next_bin = 1;
/*
Stride over the output element
stride over the bins at the same time
if the bin value needs writing to the current offset, write and stride
else move to next bin
runtime = O(bin_size + num_element / total_threads)
*/
/*
if b[prev] =< i < b[curr] ::=> Write+stride
else ::=> bin++
*/
while((offset < num_elements) || (curr_bin < histogram_size)){
if( ( offset >= kernel_c[curr_bin] ) && ( offset < kernel_c[next_bin] ) ){
output[offset] = curr_bin;
offset += stride;
}else{
curr_bin = next_bin;
next_bin++;
}
}
} | .file "tmpxft_000abb05_00000000-6_counting_sort_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z20counting_sort_kernelPiS_iiPiS_ii
.type _Z44__device_stub__Z20counting_sort_kernelPiS_iiPiS_ii, @function
_Z44__device_stub__Z20counting_sort_kernelPiS_iiPiS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20counting_sort_kernelPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z20counting_sort_kernelPiS_iiPiS_ii, .-_Z44__device_stub__Z20counting_sort_kernelPiS_iiPiS_ii
.globl _Z20counting_sort_kernelPiS_ii
.type _Z20counting_sort_kernelPiS_ii, @function
_Z20counting_sort_kernelPiS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z20counting_sort_kernelPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20counting_sort_kernelPiS_ii, .-_Z20counting_sort_kernelPiS_ii
.globl _Z34__device_stub__Z11scan_kernelPiS_iPiS_i
.type _Z34__device_stub__Z11scan_kernelPiS_iPiS_i, @function
_Z34__device_stub__Z11scan_kernelPiS_iPiS_i:
.LFB2053:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11scan_kernelPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z34__device_stub__Z11scan_kernelPiS_iPiS_i, .-_Z34__device_stub__Z11scan_kernelPiS_iPiS_i
.globl _Z11scan_kernelPiS_i
.type _Z11scan_kernelPiS_i, @function
_Z11scan_kernelPiS_i:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11scan_kernelPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z11scan_kernelPiS_i, .-_Z11scan_kernelPiS_i
.globl _Z43__device_stub__Z21recreate_array_kernelPiiiPiii
.type _Z43__device_stub__Z21recreate_array_kernelPiiiPiii, @function
_Z43__device_stub__Z21recreate_array_kernelPiiiPiii:
.LFB2055:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z21recreate_array_kernelPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z43__device_stub__Z21recreate_array_kernelPiiiPiii, .-_Z43__device_stub__Z21recreate_array_kernelPiiiPiii
.globl _Z21recreate_array_kernelPiii
.type _Z21recreate_array_kernelPiii, @function
_Z21recreate_array_kernelPiii:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z21recreate_array_kernelPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z21recreate_array_kernelPiii, .-_Z21recreate_array_kernelPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z21recreate_array_kernelPiii"
.LC1:
.string "_Z11scan_kernelPiS_i"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_Z20counting_sort_kernelPiS_ii"
.section .rodata.str1.1
.LC3:
.string "kernel_c"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21recreate_array_kernelPiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z11scan_kernelPiS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z20counting_sort_kernelPiS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $1024, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8kernel_c(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL8kernel_c
.comm _ZL8kernel_c,1024,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* Write GPU code to perform the step(s) involved in counting sort.
Add additional kernels and device functions as needed. */
#define MAX_KERNEL_WIDTH 256
#define HISTOGRAM_SIZE 256
__constant__ int kernel_c[MAX_KERNEL_WIDTH];
__global__ void counting_sort_kernel(int* in, int* bins, int num_elements, int histogram_size)
{
__shared__ int s[HISTOGRAM_SIZE];
/* Initialize shared memory */
if(threadIdx.x < histogram_size)
s[threadIdx.x] = 0;
__syncthreads();
int offset = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
while (offset < num_elements) {
atomicAdd(&s[in[offset]], 1);
offset += stride;
}
__syncthreads();
/* Accumulate histogram in shared memory into global memory */
if (threadIdx.x < histogram_size)
atomicAdd(&bins[threadIdx.x], s[threadIdx.x]);
return;
}
__global__ void scan_kernel(int *out, int *in, int n)
{
/* Dynamically allocated shared memory for storing the scan array */
extern __shared__ int temp[];
int tid = threadIdx.x;
/* Indices for the ping-pong buffers */
int pout = 0;
int pin = 1;
/* Load the in array from global memory into shared memory */
if (tid > 0)
temp[pout * n + tid] = in[tid - 1];
else
temp[pout * n + tid] = 0;
int offset;
for (offset = 1; offset < n; offset *= 2) {
pout = 1 - pout;
pin = 1 - pout;
__syncthreads();
temp[pout * n + tid] = temp[pin * n + tid];
if (tid >= offset)
temp[pout * n + tid] += temp[pin * n + tid - offset];
}
__syncthreads();
out[tid] = temp[pout * n + tid];
}
/* scan_d stored in kernel_c */
__global__ void recreate_array_kernel(int* output, int num_elements, int histogram_size)
{
int offset = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
int curr_bin = 0;
int next_bin = 1;
/*
Stride over the output element
stride over the bins at the same time
if the bin value needs writing to the current offset, write and stride
else move to next bin
runtime = O(bin_size + num_element / total_threads)
*/
/*
if b[prev] =< i < b[curr] ::=> Write+stride
else ::=> bin++
*/
while((offset < num_elements) || (curr_bin < histogram_size)){
if( ( offset >= kernel_c[curr_bin] ) && ( offset < kernel_c[next_bin] ) ){
output[offset] = curr_bin;
offset += stride;
}else{
curr_bin = next_bin;
next_bin++;
}
}
} | #include <hip/hip_runtime.h>
/* Write GPU code to perform the step(s) involved in counting sort.
Add additional kernels and device functions as needed. */
#define MAX_KERNEL_WIDTH 256
#define HISTOGRAM_SIZE 256
__constant__ int kernel_c[MAX_KERNEL_WIDTH];
__global__ void counting_sort_kernel(int* in, int* bins, int num_elements, int histogram_size)
{
__shared__ int s[HISTOGRAM_SIZE];
/* Initialize shared memory */
if(threadIdx.x < histogram_size)
s[threadIdx.x] = 0;
__syncthreads();
int offset = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
while (offset < num_elements) {
atomicAdd(&s[in[offset]], 1);
offset += stride;
}
__syncthreads();
/* Accumulate histogram in shared memory into global memory */
if (threadIdx.x < histogram_size)
atomicAdd(&bins[threadIdx.x], s[threadIdx.x]);
return;
}
__global__ void scan_kernel(int *out, int *in, int n)
{
/* Dynamically allocated shared memory for storing the scan array */
extern __shared__ int temp[];
int tid = threadIdx.x;
/* Indices for the ping-pong buffers */
int pout = 0;
int pin = 1;
/* Load the in array from global memory into shared memory */
if (tid > 0)
temp[pout * n + tid] = in[tid - 1];
else
temp[pout * n + tid] = 0;
int offset;
for (offset = 1; offset < n; offset *= 2) {
pout = 1 - pout;
pin = 1 - pout;
__syncthreads();
temp[pout * n + tid] = temp[pin * n + tid];
if (tid >= offset)
temp[pout * n + tid] += temp[pin * n + tid - offset];
}
__syncthreads();
out[tid] = temp[pout * n + tid];
}
/* scan_d stored in kernel_c */
__global__ void recreate_array_kernel(int* output, int num_elements, int histogram_size)
{
int offset = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
int curr_bin = 0;
int next_bin = 1;
/*
Stride over the output element
stride over the bins at the same time
if the bin value needs writing to the current offset, write and stride
else move to next bin
runtime = O(bin_size + num_element / total_threads)
*/
/*
if b[prev] =< i < b[curr] ::=> Write+stride
else ::=> bin++
*/
while((offset < num_elements) || (curr_bin < histogram_size)){
if( ( offset >= kernel_c[curr_bin] ) && ( offset < kernel_c[next_bin] ) ){
output[offset] = curr_bin;
offset += stride;
}else{
curr_bin = next_bin;
next_bin++;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/* Write GPU code to perform the step(s) involved in counting sort.
Add additional kernels and device functions as needed. */
#define MAX_KERNEL_WIDTH 256
#define HISTOGRAM_SIZE 256
__constant__ int kernel_c[MAX_KERNEL_WIDTH];
__global__ void counting_sort_kernel(int* in, int* bins, int num_elements, int histogram_size)
{
__shared__ int s[HISTOGRAM_SIZE];
/* Initialize shared memory */
if(threadIdx.x < histogram_size)
s[threadIdx.x] = 0;
__syncthreads();
int offset = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
while (offset < num_elements) {
atomicAdd(&s[in[offset]], 1);
offset += stride;
}
__syncthreads();
/* Accumulate histogram in shared memory into global memory */
if (threadIdx.x < histogram_size)
atomicAdd(&bins[threadIdx.x], s[threadIdx.x]);
return;
}
__global__ void scan_kernel(int *out, int *in, int n)
{
/* Dynamically allocated shared memory for storing the scan array */
extern __shared__ int temp[];
int tid = threadIdx.x;
/* Indices for the ping-pong buffers */
int pout = 0;
int pin = 1;
/* Load the in array from global memory into shared memory */
if (tid > 0)
temp[pout * n + tid] = in[tid - 1];
else
temp[pout * n + tid] = 0;
int offset;
for (offset = 1; offset < n; offset *= 2) {
pout = 1 - pout;
pin = 1 - pout;
__syncthreads();
temp[pout * n + tid] = temp[pin * n + tid];
if (tid >= offset)
temp[pout * n + tid] += temp[pin * n + tid - offset];
}
__syncthreads();
out[tid] = temp[pout * n + tid];
}
/* scan_d stored in kernel_c */
__global__ void recreate_array_kernel(int* output, int num_elements, int histogram_size)
{
int offset = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
int curr_bin = 0;
int next_bin = 1;
/*
Stride over the output element
stride over the bins at the same time
if the bin value needs writing to the current offset, write and stride
else move to next bin
runtime = O(bin_size + num_element / total_threads)
*/
/*
if b[prev] =< i < b[curr] ::=> Write+stride
else ::=> bin++
*/
while((offset < num_elements) || (curr_bin < histogram_size)){
if( ( offset >= kernel_c[curr_bin] ) && ( offset < kernel_c[next_bin] ) ){
output[offset] = curr_bin;
offset += stride;
}else{
curr_bin = next_bin;
next_bin++;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20counting_sort_kernelPiS_ii
.globl _Z20counting_sort_kernelPiS_ii
.p2align 8
.type _Z20counting_sort_kernelPiS_ii,@function
_Z20counting_sort_kernelPiS_ii:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
v_cmp_gt_u32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v0
ds_store_b32 v1, v2
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x10
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_mov_b32 s9, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_5
s_load_b32 s2, s[4:5], 0x0
s_load_b64 s[6:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v4, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s2, s3
v_add_co_u32 v2, s2, s6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v3, s2, s7, v3, s2
s_ashr_i32 s5, s4, 31
s_lshl_b64 s[6:7], s[4:5], 2
s_mov_b32 s5, 0
.LBB0_4:
global_load_b32 v5, v[2:3], off
v_add_nc_u32_e32 v1, s4, v1
v_add_co_u32 v2, s3, v2, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s3, s7, v3, s3
v_cmp_le_i32_e64 s2, s8, v1
s_delay_alu instid0(VALU_DEP_1)
s_or_b32 s5, s2, s5
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v5, 2, v5
ds_add_u32 v5, v4
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_4
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s9
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_7
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x8
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20counting_sort_kernelPiS_ii
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20counting_sort_kernelPiS_ii, .Lfunc_end0-_Z20counting_sort_kernelPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11scan_kernelPiS_i
.globl _Z11scan_kernelPiS_i
.p2align 8
.type _Z11scan_kernelPiS_i,@function
_Z11scan_kernelPiS_i:
v_mov_b32_e32 v1, 0
s_mov_b32 s2, 0
s_mov_b32 s3, exec_lo
v_cmpx_ne_u32_e32 0, v0
s_cbranch_execz .LBB1_2
s_load_b64 s[4:5], s[0:1], 0x8
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v1, s[4:5] offset:-4
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s3
s_load_b32 s3, s[0:1], 0x10
v_lshl_add_u32 v2, v0, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v2, v1
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s3, 2
s_cbranch_scc1 .LBB1_7
s_mov_b32 s4, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_5
.p2align 6
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s5
s_lshl_b32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s4, s3
s_cbranch_scc0 .LBB1_7
.LBB1_5:
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_sub_i32 s2, 1, s2
s_mov_b32 s5, exec_lo
v_lshl_add_u32 v2, v1, 2, 0
v_mad_u64_u32 v[3:4], null, s2, s3, v[0:1]
ds_load_b32 v2, v2
v_lshl_add_u32 v3, v3, 2, 0
s_waitcnt lgkmcnt(0)
ds_store_b32 v3, v2
v_cmpx_le_u32_e64 s4, v0
s_cbranch_execz .LBB1_4
v_subrev_nc_u32_e32 v1, s4, v1
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v1, v1, 2, 0
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, v1, v2
ds_store_b32 v3, v1
s_branch .LBB1_4
.LBB1_7:
s_set_inst_prefetch_distance 0x2
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_lshlrev_b32_e32 v0, 2, v0
v_lshl_add_u32 v1, v1, 2, 0
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11scan_kernelPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 6
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z11scan_kernelPiS_i, .Lfunc_end1-_Z11scan_kernelPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z21recreate_array_kernelPiii
.globl _Z21recreate_array_kernelPiii
.p2align 8
.type _Z21recreate_array_kernelPiii,@function
_Z21recreate_array_kernelPiii:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
s_add_u32 s4, s0, 16
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s6, 0xffff
s_cmp_gt_i32 s3, 0
v_mad_u64_u32 v[1:2], null, s15, s7, v[0:1]
s_cselect_b32 s8, -1, 0
s_mov_b32 s6, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_or_b32 s8, vcc_lo, s8
s_and_saveexec_b32 s9, s8
s_cbranch_execz .LBB2_9
s_load_b32 s8, s[4:5], 0x0
s_load_b64 s[4:5], s[0:1], 0x0
v_mov_b32_e32 v3, 1
v_mov_b32_e32 v5, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s8, s7
s_branch .LBB2_3
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_le_i32_e32 vcc_lo, s2, v0
v_cmp_le_i32_e64 s0, s3, v5
v_mov_b32_e32 v1, v0
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, exec_lo, s0
s_or_b32 s6, s0, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execz .LBB2_9
.LBB2_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, kernel_c@rel32@lo+4
s_addc_u32 s9, s9, kernel_c@rel32@hi+12
v_lshlrev_b64 v[6:7], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, v6, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
global_load_b32 v0, v[6:7], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e64 s0, v1, v0
v_cmp_ge_i32_e32 vcc_lo, v1, v0
s_and_saveexec_b32 s7, vcc_lo
s_cbranch_execz .LBB2_7
v_ashrrev_i32_e32 v4, 31, v3
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, kernel_c@rel32@lo+4
s_addc_u32 s9, s9, kernel_c@rel32@hi+12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[3:4]
v_add_co_u32 v6, vcc_lo, v6, s8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
s_mov_b32 s9, -1
global_load_b32 v0, v[6:7], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v1, v0
s_and_saveexec_b32 s8, vcc_lo
s_cbranch_execz .LBB2_6
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v0, s1, v1
s_xor_b32 s9, exec_lo, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_add_co_u32 v6, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_store_b32 v[6:7], v5, off
.LBB2_6:
s_or_b32 exec_lo, exec_lo, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s0, s0, exec_lo
s_and_b32 s8, s9, exec_lo
s_or_b32 s0, s0, s8
.LBB2_7:
s_or_b32 exec_lo, exec_lo, s7
s_and_saveexec_b32 s7, s0
s_cbranch_execz .LBB2_2
v_dual_mov_b32 v5, v3 :: v_dual_add_nc_u32 v2, 1, v3
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v0, v1 :: v_dual_mov_b32 v3, v2
s_branch .LBB2_2
.LBB2_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21recreate_array_kernelPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z21recreate_array_kernelPiii, .Lfunc_end2-_Z21recreate_array_kernelPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected kernel_c
.type kernel_c,@object
.section .bss,"aw",@nobits
.globl kernel_c
.p2align 4, 0x0
kernel_c:
.zero 1024
.size kernel_c, 1024
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym kernel_c
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20counting_sort_kernelPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20counting_sort_kernelPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11scan_kernelPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z11scan_kernelPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21recreate_array_kernelPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21recreate_array_kernelPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/* Write GPU code to perform the step(s) involved in counting sort.
Add additional kernels and device functions as needed. */
#define MAX_KERNEL_WIDTH 256
#define HISTOGRAM_SIZE 256
__constant__ int kernel_c[MAX_KERNEL_WIDTH];
__global__ void counting_sort_kernel(int* in, int* bins, int num_elements, int histogram_size)
{
__shared__ int s[HISTOGRAM_SIZE];
/* Initialize shared memory */
if(threadIdx.x < histogram_size)
s[threadIdx.x] = 0;
__syncthreads();
int offset = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
while (offset < num_elements) {
atomicAdd(&s[in[offset]], 1);
offset += stride;
}
__syncthreads();
/* Accumulate histogram in shared memory into global memory */
if (threadIdx.x < histogram_size)
atomicAdd(&bins[threadIdx.x], s[threadIdx.x]);
return;
}
__global__ void scan_kernel(int *out, int *in, int n)
{
/* Dynamically allocated shared memory for storing the scan array */
extern __shared__ int temp[];
int tid = threadIdx.x;
/* Indices for the ping-pong buffers */
int pout = 0;
int pin = 1;
/* Load the in array from global memory into shared memory */
if (tid > 0)
temp[pout * n + tid] = in[tid - 1];
else
temp[pout * n + tid] = 0;
int offset;
for (offset = 1; offset < n; offset *= 2) {
pout = 1 - pout;
pin = 1 - pout;
__syncthreads();
temp[pout * n + tid] = temp[pin * n + tid];
if (tid >= offset)
temp[pout * n + tid] += temp[pin * n + tid - offset];
}
__syncthreads();
out[tid] = temp[pout * n + tid];
}
/* scan_d stored in kernel_c */
__global__ void recreate_array_kernel(int* output, int num_elements, int histogram_size)
{
int offset = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
int curr_bin = 0;
int next_bin = 1;
/*
Stride over the output element
stride over the bins at the same time
if the bin value needs writing to the current offset, write and stride
else move to next bin
runtime = O(bin_size + num_element / total_threads)
*/
/*
if b[prev] =< i < b[curr] ::=> Write+stride
else ::=> bin++
*/
while((offset < num_elements) || (curr_bin < histogram_size)){
if( ( offset >= kernel_c[curr_bin] ) && ( offset < kernel_c[next_bin] ) ){
output[offset] = curr_bin;
offset += stride;
}else{
curr_bin = next_bin;
next_bin++;
}
}
} | .text
.file "counting_sort_kernel.hip"
.globl _Z35__device_stub__counting_sort_kernelPiS_ii # -- Begin function _Z35__device_stub__counting_sort_kernelPiS_ii
.p2align 4, 0x90
.type _Z35__device_stub__counting_sort_kernelPiS_ii,@function
_Z35__device_stub__counting_sort_kernelPiS_ii: # @_Z35__device_stub__counting_sort_kernelPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20counting_sort_kernelPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z35__device_stub__counting_sort_kernelPiS_ii, .Lfunc_end0-_Z35__device_stub__counting_sort_kernelPiS_ii
.cfi_endproc
# -- End function
.globl _Z26__device_stub__scan_kernelPiS_i # -- Begin function _Z26__device_stub__scan_kernelPiS_i
.p2align 4, 0x90
.type _Z26__device_stub__scan_kernelPiS_i,@function
_Z26__device_stub__scan_kernelPiS_i: # @_Z26__device_stub__scan_kernelPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11scan_kernelPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z26__device_stub__scan_kernelPiS_i, .Lfunc_end1-_Z26__device_stub__scan_kernelPiS_i
.cfi_endproc
# -- End function
.globl _Z36__device_stub__recreate_array_kernelPiii # -- Begin function _Z36__device_stub__recreate_array_kernelPiii
.p2align 4, 0x90
.type _Z36__device_stub__recreate_array_kernelPiii,@function
_Z36__device_stub__recreate_array_kernelPiii: # @_Z36__device_stub__recreate_array_kernelPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z21recreate_array_kernelPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z36__device_stub__recreate_array_kernelPiii, .Lfunc_end2-_Z36__device_stub__recreate_array_kernelPiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20counting_sort_kernelPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11scan_kernelPiS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21recreate_array_kernelPiii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $kernel_c, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $1024, %r9d # imm = 0x400
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type kernel_c,@object # @kernel_c
.local kernel_c
.comm kernel_c,1024,16
.type _Z20counting_sort_kernelPiS_ii,@object # @_Z20counting_sort_kernelPiS_ii
.section .rodata,"a",@progbits
.globl _Z20counting_sort_kernelPiS_ii
.p2align 3, 0x0
_Z20counting_sort_kernelPiS_ii:
.quad _Z35__device_stub__counting_sort_kernelPiS_ii
.size _Z20counting_sort_kernelPiS_ii, 8
.type _Z11scan_kernelPiS_i,@object # @_Z11scan_kernelPiS_i
.globl _Z11scan_kernelPiS_i
.p2align 3, 0x0
_Z11scan_kernelPiS_i:
.quad _Z26__device_stub__scan_kernelPiS_i
.size _Z11scan_kernelPiS_i, 8
.type _Z21recreate_array_kernelPiii,@object # @_Z21recreate_array_kernelPiii
.globl _Z21recreate_array_kernelPiii
.p2align 3, 0x0
_Z21recreate_array_kernelPiii:
.quad _Z36__device_stub__recreate_array_kernelPiii
.size _Z21recreate_array_kernelPiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20counting_sort_kernelPiS_ii"
.size .L__unnamed_1, 31
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11scan_kernelPiS_i"
.size .L__unnamed_2, 21
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z21recreate_array_kernelPiii"
.size .L__unnamed_3, 30
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "kernel_c"
.size .L__unnamed_4, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__counting_sort_kernelPiS_ii
.addrsig_sym _Z26__device_stub__scan_kernelPiS_i
.addrsig_sym _Z36__device_stub__recreate_array_kernelPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym kernel_c
.addrsig_sym _Z20counting_sort_kernelPiS_ii
.addrsig_sym _Z11scan_kernelPiS_i
.addrsig_sym _Z21recreate_array_kernelPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z21recreate_array_kernelPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff027624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f06270 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f26270 */
/*0070*/ @!P0 EXIT P1 ; /* 0x000000000000894d */
/* 0x000fea0000800000 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*0090*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe200078e00ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fce0000000a00 */
/*00b0*/ IMAD.SHL.U32 R7, R4, 0x4, RZ ; /* 0x0000000404077824 */
/* 0x000fe200078e00ff */
/*00c0*/ SHF.L.U32 R6, R5, 0x2, RZ ; /* 0x0000000205067819 */
/* 0x000fc800000006ff */
/*00d0*/ LDC R3, c[0x3][R6] ; /* 0x00c0000006037b82 */
/* 0x000e300000000800 */
/*00e0*/ LDC R7, c[0x3][R7] ; /* 0x00c0000007077b82 */
/* 0x000e640000000800 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x002fc80003f06270 */
/*0100*/ ISETP.LT.OR P0, PT, R0, R3, P0 ; /* 0x000000030000720c */
/* 0x001fda0000701670 */
/*0110*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff038424 */
/* 0x000fe200078e00ff */
/*0120*/ @!P0 MOV R9, c[0x0][0x0] ; /* 0x0000000000098a02 */
/* 0x000fe40000000f00 */
/*0130*/ @P0 IADD3 R8, R4, 0x1, RZ ; /* 0x0000000104080810 */
/* 0x000fe20007ffe0ff */
/*0140*/ @!P0 IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000028625 */
/* 0x000fc800078e0203 */
/*0150*/ @!P0 IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009008a24 */
/* 0x000fe200078e0200 */
/*0160*/ @!P0 STG.E [R2.64], R5 ; /* 0x0000000502008986 */
/* 0x0001e4000c101904 */
/*0170*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, R4 ; /* 0x000000ffff050224 */
/* 0x000fe200078e0004 */
/*0180*/ @P0 MOV R4, R8 ; /* 0x0000000800040202 */
/* 0x000fc80000000f00 */
/*0190*/ ISETP.GE.AND P1, PT, R5, c[0x0][0x16c], PT ; /* 0x00005b0005007a0c */
/* 0x000fc80003f26270 */
/*01a0*/ ISETP.LT.OR P1, PT, R0, c[0x0][0x168], !P1 ; /* 0x00005a0000007a0c */
/* 0x000fda0004f21670 */
/*01b0*/ @P1 BRA 0xb0 ; /* 0xfffffef000001947 */
/* 0x001fea000383ffff */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11scan_kernelPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ ISETP.GT.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f04270 */
/*0040*/ @P0 IADD3 R2, R7, -0x1, RZ ; /* 0xffffffff07020810 */
/* 0x000fe40007ffe0ff */
/*0050*/ @P0 MOV R3, 0x4 ; /* 0x0000000400030802 */
/* 0x000fca0000000f00 */
/*0060*/ @P0 IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002020625 */
/* 0x000fcc00078e0203 */
/*0070*/ @P0 LDG.E R2, [R2.64] ; /* 0x0000000402020981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff007624 */
/* 0x000fc600078e00ff */
/*0090*/ @!P0 STS [R7.X4], RZ ; /* 0x000000ff07008388 */
/* 0x0001e40000004800 */
/*00a0*/ ISETP.GE.AND P1, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe20003f26270 */
/*00b0*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fe200000001ff */
/*00c0*/ @P0 STS [R7.X4], R2 ; /* 0x0000000207000388 */
/* 0x0041f60000004800 */
/*00d0*/ @!P1 BRA 0x1f0 ; /* 0x0000011000009947 */
/* 0x000fea0003800000 */
/*00e0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*00f0*/ MOV R2, 0x1 ; /* 0x0000000100027802 */
/* 0x001fc40000000f00 */
/*0100*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0110*/ IMAD R5, R0, c[0x0][0x170], R7 ; /* 0x00005c0000057a24 */
/* 0x000fe200078e0207 */
/*0120*/ ISETP.GE.AND P0, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fc40003f06270 */
/*0130*/ IADD3 R0, -R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fca0007ffe1ff */
/*0140*/ IMAD R3, R0, c[0x0][0x170], R7 ; /* 0x00005c0000037a24 */
/* 0x000fc800078e0207 */
/*0150*/ IMAD.SHL.U32 R9, R3, 0x4, RZ ; /* 0x0000000403097824 */
/* 0x000fe400078e00ff */
/*0160*/ @P0 IADD3 R3, R5, -R2, RZ ; /* 0x8000000205030210 */
/* 0x000fe40007ffe0ff */
/*0170*/ SHF.L.U32 R2, R2, 0x1, RZ ; /* 0x0000000102027819 */
/* 0x000fe200000006ff */
/*0180*/ LDS R6, [R5.X4] ; /* 0x0000000005067984 */
/* 0x000e280000004800 */
/*0190*/ STS [R9], R6 ; /* 0x0000000609007388 */
/* 0x001fe80000000800 */
/*01a0*/ @P0 LDS R3, [R3.X4] ; /* 0x0000000003030984 */
/* 0x000e240000004800 */
/*01b0*/ @P0 IMAD.IADD R4, R6, 0x1, R3 ; /* 0x0000000106040824 */
/* 0x001fca00078e0203 */
/*01c0*/ @P0 STS [R9], R4 ; /* 0x0000000409000388 */
/* 0x0001e20000000800 */
/*01d0*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06270 */
/*01e0*/ @!P0 BRA 0x100 ; /* 0xffffff1000008947 */
/* 0x001fea000383ffff */
/*01f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0200*/ IMAD R5, R0, c[0x0][0x170], R7 ; /* 0x00005c0000057a24 */
/* 0x000fe400078e0207 */
/*0210*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x001fc800078e00ff */
/*0220*/ IMAD.WIDE R2, R7, R2, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x000fe200078e0202 */
/*0230*/ LDS R5, [R5.X4] ; /* 0x0000000005057984 */
/* 0x000e280000004800 */
/*0240*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0250*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0260*/ BRA 0x260; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z20counting_sort_kernelPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x174], PT ; /* 0x00005d0004007a0c */
/* 0x001fe20003f06070 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R4 ; /* 0x0000000003007a24 */
/* 0x002fca00078e0204 */
/*0060*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fce0003f26270 */
/*0070*/ @!P0 STS [R4.X4], RZ ; /* 0x000000ff04008388 */
/* 0x0001e80000004800 */
/*0080*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0090*/ @P1 BRA 0x130 ; /* 0x0000009000001947 */
/* 0x001fea0003800000 */
/*00a0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fcc00078e0203 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ MOV R5, c[0x0][0x0] ; /* 0x0000000000057a02 */
/* 0x000fe20000000f00 */
/*00e0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe80003800000 */
/*00f0*/ IMAD R0, R5, c[0x0][0xc], R0 ; /* 0x0000030005007a24 */
/* 0x000fca00078e0200 */
/*0100*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f26270 */
/*0110*/ ATOMS.POPC.INC.32 RZ, [R2.X4+URZ] ; /* 0x0000000002ff7f8c */
/* 0x0041d8000d00403f */
/*0120*/ @!P1 BRA 0xa0 ; /* 0xffffff7000009947 */
/* 0x000fea000383ffff */
/*0130*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0150*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0160*/ LDS R5, [R4.X4] ; /* 0x0000000004057984 */
/* 0x000e620000004800 */
/*0170*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0180*/ IMAD.WIDE.U32 R2, R4, R3, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x001fca00078e0003 */
/*0190*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x002fe2000c10e184 */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20counting_sort_kernelPiS_ii
.globl _Z20counting_sort_kernelPiS_ii
.p2align 8
.type _Z20counting_sort_kernelPiS_ii,@function
_Z20counting_sort_kernelPiS_ii:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
v_cmp_gt_u32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v0
ds_store_b32 v1, v2
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x10
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_mov_b32 s9, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_5
s_load_b32 s2, s[4:5], 0x0
s_load_b64 s[6:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v4, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s2, s3
v_add_co_u32 v2, s2, s6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v3, s2, s7, v3, s2
s_ashr_i32 s5, s4, 31
s_lshl_b64 s[6:7], s[4:5], 2
s_mov_b32 s5, 0
.LBB0_4:
global_load_b32 v5, v[2:3], off
v_add_nc_u32_e32 v1, s4, v1
v_add_co_u32 v2, s3, v2, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s3, s7, v3, s3
v_cmp_le_i32_e64 s2, s8, v1
s_delay_alu instid0(VALU_DEP_1)
s_or_b32 s5, s2, s5
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v5, 2, v5
ds_add_u32 v5, v4
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_4
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s9
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_7
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x8
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20counting_sort_kernelPiS_ii
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20counting_sort_kernelPiS_ii, .Lfunc_end0-_Z20counting_sort_kernelPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11scan_kernelPiS_i
.globl _Z11scan_kernelPiS_i
.p2align 8
.type _Z11scan_kernelPiS_i,@function
_Z11scan_kernelPiS_i:
v_mov_b32_e32 v1, 0
s_mov_b32 s2, 0
s_mov_b32 s3, exec_lo
v_cmpx_ne_u32_e32 0, v0
s_cbranch_execz .LBB1_2
s_load_b64 s[4:5], s[0:1], 0x8
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v1, s[4:5] offset:-4
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s3
s_load_b32 s3, s[0:1], 0x10
v_lshl_add_u32 v2, v0, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v2, v1
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s3, 2
s_cbranch_scc1 .LBB1_7
s_mov_b32 s4, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_5
.p2align 6
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s5
s_lshl_b32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s4, s3
s_cbranch_scc0 .LBB1_7
.LBB1_5:
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_sub_i32 s2, 1, s2
s_mov_b32 s5, exec_lo
v_lshl_add_u32 v2, v1, 2, 0
v_mad_u64_u32 v[3:4], null, s2, s3, v[0:1]
ds_load_b32 v2, v2
v_lshl_add_u32 v3, v3, 2, 0
s_waitcnt lgkmcnt(0)
ds_store_b32 v3, v2
v_cmpx_le_u32_e64 s4, v0
s_cbranch_execz .LBB1_4
v_subrev_nc_u32_e32 v1, s4, v1
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v1, v1, 2, 0
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, v1, v2
ds_store_b32 v3, v1
s_branch .LBB1_4
.LBB1_7:
s_set_inst_prefetch_distance 0x2
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_lshlrev_b32_e32 v0, 2, v0
v_lshl_add_u32 v1, v1, 2, 0
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11scan_kernelPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 6
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z11scan_kernelPiS_i, .Lfunc_end1-_Z11scan_kernelPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z21recreate_array_kernelPiii
.globl _Z21recreate_array_kernelPiii
.p2align 8
.type _Z21recreate_array_kernelPiii,@function
_Z21recreate_array_kernelPiii:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
s_add_u32 s4, s0, 16
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s6, 0xffff
s_cmp_gt_i32 s3, 0
v_mad_u64_u32 v[1:2], null, s15, s7, v[0:1]
s_cselect_b32 s8, -1, 0
s_mov_b32 s6, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_or_b32 s8, vcc_lo, s8
s_and_saveexec_b32 s9, s8
s_cbranch_execz .LBB2_9
s_load_b32 s8, s[4:5], 0x0
s_load_b64 s[4:5], s[0:1], 0x0
v_mov_b32_e32 v3, 1
v_mov_b32_e32 v5, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s8, s7
s_branch .LBB2_3
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_le_i32_e32 vcc_lo, s2, v0
v_cmp_le_i32_e64 s0, s3, v5
v_mov_b32_e32 v1, v0
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, exec_lo, s0
s_or_b32 s6, s0, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execz .LBB2_9
.LBB2_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, kernel_c@rel32@lo+4
s_addc_u32 s9, s9, kernel_c@rel32@hi+12
v_lshlrev_b64 v[6:7], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, v6, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
global_load_b32 v0, v[6:7], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e64 s0, v1, v0
v_cmp_ge_i32_e32 vcc_lo, v1, v0
s_and_saveexec_b32 s7, vcc_lo
s_cbranch_execz .LBB2_7
v_ashrrev_i32_e32 v4, 31, v3
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, kernel_c@rel32@lo+4
s_addc_u32 s9, s9, kernel_c@rel32@hi+12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[3:4]
v_add_co_u32 v6, vcc_lo, v6, s8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
s_mov_b32 s9, -1
global_load_b32 v0, v[6:7], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v1, v0
s_and_saveexec_b32 s8, vcc_lo
s_cbranch_execz .LBB2_6
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v0, s1, v1
s_xor_b32 s9, exec_lo, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_add_co_u32 v6, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_store_b32 v[6:7], v5, off
.LBB2_6:
s_or_b32 exec_lo, exec_lo, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s0, s0, exec_lo
s_and_b32 s8, s9, exec_lo
s_or_b32 s0, s0, s8
.LBB2_7:
s_or_b32 exec_lo, exec_lo, s7
s_and_saveexec_b32 s7, s0
s_cbranch_execz .LBB2_2
v_dual_mov_b32 v5, v3 :: v_dual_add_nc_u32 v2, 1, v3
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v0, v1 :: v_dual_mov_b32 v3, v2
s_branch .LBB2_2
.LBB2_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21recreate_array_kernelPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z21recreate_array_kernelPiii, .Lfunc_end2-_Z21recreate_array_kernelPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected kernel_c
.type kernel_c,@object
.section .bss,"aw",@nobits
.globl kernel_c
.p2align 4, 0x0
kernel_c:
.zero 1024
.size kernel_c, 1024
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym kernel_c
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20counting_sort_kernelPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20counting_sort_kernelPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11scan_kernelPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z11scan_kernelPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21recreate_array_kernelPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21recreate_array_kernelPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000abb05_00000000-6_counting_sort_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z20counting_sort_kernelPiS_iiPiS_ii
.type _Z44__device_stub__Z20counting_sort_kernelPiS_iiPiS_ii, @function
_Z44__device_stub__Z20counting_sort_kernelPiS_iiPiS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20counting_sort_kernelPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z20counting_sort_kernelPiS_iiPiS_ii, .-_Z44__device_stub__Z20counting_sort_kernelPiS_iiPiS_ii
.globl _Z20counting_sort_kernelPiS_ii
.type _Z20counting_sort_kernelPiS_ii, @function
_Z20counting_sort_kernelPiS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z20counting_sort_kernelPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20counting_sort_kernelPiS_ii, .-_Z20counting_sort_kernelPiS_ii
.globl _Z34__device_stub__Z11scan_kernelPiS_iPiS_i
.type _Z34__device_stub__Z11scan_kernelPiS_iPiS_i, @function
_Z34__device_stub__Z11scan_kernelPiS_iPiS_i:
.LFB2053:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11scan_kernelPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z34__device_stub__Z11scan_kernelPiS_iPiS_i, .-_Z34__device_stub__Z11scan_kernelPiS_iPiS_i
.globl _Z11scan_kernelPiS_i
.type _Z11scan_kernelPiS_i, @function
_Z11scan_kernelPiS_i:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11scan_kernelPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z11scan_kernelPiS_i, .-_Z11scan_kernelPiS_i
.globl _Z43__device_stub__Z21recreate_array_kernelPiiiPiii
.type _Z43__device_stub__Z21recreate_array_kernelPiiiPiii, @function
_Z43__device_stub__Z21recreate_array_kernelPiiiPiii:
.LFB2055:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z21recreate_array_kernelPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z43__device_stub__Z21recreate_array_kernelPiiiPiii, .-_Z43__device_stub__Z21recreate_array_kernelPiiiPiii
.globl _Z21recreate_array_kernelPiii
.type _Z21recreate_array_kernelPiii, @function
_Z21recreate_array_kernelPiii:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z21recreate_array_kernelPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z21recreate_array_kernelPiii, .-_Z21recreate_array_kernelPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z21recreate_array_kernelPiii"
.LC1:
.string "_Z11scan_kernelPiS_i"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_Z20counting_sort_kernelPiS_ii"
.section .rodata.str1.1
.LC3:
.string "kernel_c"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21recreate_array_kernelPiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z11scan_kernelPiS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z20counting_sort_kernelPiS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $1024, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8kernel_c(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL8kernel_c
.comm _ZL8kernel_c,1024,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "counting_sort_kernel.hip"
.globl _Z35__device_stub__counting_sort_kernelPiS_ii # -- Begin function _Z35__device_stub__counting_sort_kernelPiS_ii
.p2align 4, 0x90
.type _Z35__device_stub__counting_sort_kernelPiS_ii,@function
_Z35__device_stub__counting_sort_kernelPiS_ii: # @_Z35__device_stub__counting_sort_kernelPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20counting_sort_kernelPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z35__device_stub__counting_sort_kernelPiS_ii, .Lfunc_end0-_Z35__device_stub__counting_sort_kernelPiS_ii
.cfi_endproc
# -- End function
.globl _Z26__device_stub__scan_kernelPiS_i # -- Begin function _Z26__device_stub__scan_kernelPiS_i
.p2align 4, 0x90
.type _Z26__device_stub__scan_kernelPiS_i,@function
_Z26__device_stub__scan_kernelPiS_i: # @_Z26__device_stub__scan_kernelPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11scan_kernelPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z26__device_stub__scan_kernelPiS_i, .Lfunc_end1-_Z26__device_stub__scan_kernelPiS_i
.cfi_endproc
# -- End function
.globl _Z36__device_stub__recreate_array_kernelPiii # -- Begin function _Z36__device_stub__recreate_array_kernelPiii
.p2align 4, 0x90
.type _Z36__device_stub__recreate_array_kernelPiii,@function
_Z36__device_stub__recreate_array_kernelPiii: # @_Z36__device_stub__recreate_array_kernelPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z21recreate_array_kernelPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z36__device_stub__recreate_array_kernelPiii, .Lfunc_end2-_Z36__device_stub__recreate_array_kernelPiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20counting_sort_kernelPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11scan_kernelPiS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21recreate_array_kernelPiii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $kernel_c, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $1024, %r9d # imm = 0x400
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type kernel_c,@object # @kernel_c
.local kernel_c
.comm kernel_c,1024,16
.type _Z20counting_sort_kernelPiS_ii,@object # @_Z20counting_sort_kernelPiS_ii
.section .rodata,"a",@progbits
.globl _Z20counting_sort_kernelPiS_ii
.p2align 3, 0x0
_Z20counting_sort_kernelPiS_ii:
.quad _Z35__device_stub__counting_sort_kernelPiS_ii
.size _Z20counting_sort_kernelPiS_ii, 8
.type _Z11scan_kernelPiS_i,@object # @_Z11scan_kernelPiS_i
.globl _Z11scan_kernelPiS_i
.p2align 3, 0x0
_Z11scan_kernelPiS_i:
.quad _Z26__device_stub__scan_kernelPiS_i
.size _Z11scan_kernelPiS_i, 8
.type _Z21recreate_array_kernelPiii,@object # @_Z21recreate_array_kernelPiii
.globl _Z21recreate_array_kernelPiii
.p2align 3, 0x0
_Z21recreate_array_kernelPiii:
.quad _Z36__device_stub__recreate_array_kernelPiii
.size _Z21recreate_array_kernelPiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20counting_sort_kernelPiS_ii"
.size .L__unnamed_1, 31
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11scan_kernelPiS_i"
.size .L__unnamed_2, 21
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z21recreate_array_kernelPiii"
.size .L__unnamed_3, 30
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "kernel_c"
.size .L__unnamed_4, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__counting_sort_kernelPiS_ii
.addrsig_sym _Z26__device_stub__scan_kernelPiS_i
.addrsig_sym _Z36__device_stub__recreate_array_kernelPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym kernel_c
.addrsig_sym _Z20counting_sort_kernelPiS_ii
.addrsig_sym _Z11scan_kernelPiS_i
.addrsig_sym _Z21recreate_array_kernelPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
Vector addition
*/
#include <stdio.h>
#define N 128
__global__ void add( int *a, int *b, int *c ) {
int tid = threadIdx.x;
if(tid > N-1) return;
c[tid] = a[tid] + b[tid];
}
int main() {
int host_a[N], host_b[N], host_c[N];
int *dev_a, *dev_b, *dev_c;
for (int i=0; i<N; i++) { host_a[i] = i * i; host_b[i] = - i; }
cudaMalloc( (void**)&dev_a, N * sizeof(int) );
cudaMalloc( (void**)&dev_b, N * sizeof(int) );
cudaMalloc( (void**)&dev_c, N * sizeof(int) );
cudaMemcpy( dev_a, host_a, N * sizeof(int), cudaMemcpyHostToDevice );
cudaMemcpy( dev_b, host_b, N * sizeof(int), cudaMemcpyHostToDevice );
add<<<1,N>>>( dev_a, dev_b, dev_c );
cudaMemcpy( host_c, dev_c, N * sizeof(int), cudaMemcpyDeviceToHost ) ;
for (int i=0; i<N; i++) { printf( "%d + %d = %d\n", host_a[i], host_b[i], host_c[i] ); }
cudaFree( dev_a ); cudaFree( dev_b ); cudaFree( dev_c );
return 0;
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GT.AND P0, PT, R6, 0x7f, PT ; /* 0x0000007f0600780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
Vector addition
*/
#include <stdio.h>
#define N 128
__global__ void add( int *a, int *b, int *c ) {
int tid = threadIdx.x;
if(tid > N-1) return;
c[tid] = a[tid] + b[tid];
}
int main() {
int host_a[N], host_b[N], host_c[N];
int *dev_a, *dev_b, *dev_c;
for (int i=0; i<N; i++) { host_a[i] = i * i; host_b[i] = - i; }
cudaMalloc( (void**)&dev_a, N * sizeof(int) );
cudaMalloc( (void**)&dev_b, N * sizeof(int) );
cudaMalloc( (void**)&dev_c, N * sizeof(int) );
cudaMemcpy( dev_a, host_a, N * sizeof(int), cudaMemcpyHostToDevice );
cudaMemcpy( dev_b, host_b, N * sizeof(int), cudaMemcpyHostToDevice );
add<<<1,N>>>( dev_a, dev_b, dev_c );
cudaMemcpy( host_c, dev_c, N * sizeof(int), cudaMemcpyDeviceToHost ) ;
for (int i=0; i<N; i++) { printf( "%d + %d = %d\n", host_a[i], host_b[i], host_c[i] ); }
cudaFree( dev_a ); cudaFree( dev_b ); cudaFree( dev_c );
return 0;
} | .file "tmpxft_00077353_00000000-6_vector_sum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d + %d = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1608, %rsp
.cfi_def_cfa_offset 1632
movq %fs:40, %rax
movq %rax, 1592(%rsp)
xorl %eax, %eax
.L12:
movl %eax, %edx
imull %eax, %edx
movl %edx, 48(%rsp,%rax,4)
movl %eax, %edx
negl %edx
movl %edx, 560(%rsp,%rax,4)
addq $1, %rax
cmpq $128, %rax
jne .L12
movq %rsp, %rdi
movl $512, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $512, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 560(%rsp), %rsi
movl $1, %ecx
movl $512, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 1072(%rsp), %rdi
movl $2, %ecx
movl $512, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L14:
movl 560(%rsp,%rbx), %ecx
movl 48(%rsp,%rbx), %edx
movl 1072(%rsp,%rbx), %r8d
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $512, %rbx
jne .L14
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 1592(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $1608, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
Vector addition
*/
#include <stdio.h>
#define N 128
__global__ void add( int *a, int *b, int *c ) {
int tid = threadIdx.x;
if(tid > N-1) return;
c[tid] = a[tid] + b[tid];
}
int main() {
int host_a[N], host_b[N], host_c[N];
int *dev_a, *dev_b, *dev_c;
for (int i=0; i<N; i++) { host_a[i] = i * i; host_b[i] = - i; }
cudaMalloc( (void**)&dev_a, N * sizeof(int) );
cudaMalloc( (void**)&dev_b, N * sizeof(int) );
cudaMalloc( (void**)&dev_c, N * sizeof(int) );
cudaMemcpy( dev_a, host_a, N * sizeof(int), cudaMemcpyHostToDevice );
cudaMemcpy( dev_b, host_b, N * sizeof(int), cudaMemcpyHostToDevice );
add<<<1,N>>>( dev_a, dev_b, dev_c );
cudaMemcpy( host_c, dev_c, N * sizeof(int), cudaMemcpyDeviceToHost ) ;
for (int i=0; i<N; i++) { printf( "%d + %d = %d\n", host_a[i], host_b[i], host_c[i] ); }
cudaFree( dev_a ); cudaFree( dev_b ); cudaFree( dev_c );
return 0;
} | /*
Vector addition
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#define N 128
__global__ void add( int *a, int *b, int *c ) {
int tid = threadIdx.x;
if(tid > N-1) return;
c[tid] = a[tid] + b[tid];
}
int main() {
int host_a[N], host_b[N], host_c[N];
int *dev_a, *dev_b, *dev_c;
for (int i=0; i<N; i++) { host_a[i] = i * i; host_b[i] = - i; }
hipMalloc( (void**)&dev_a, N * sizeof(int) );
hipMalloc( (void**)&dev_b, N * sizeof(int) );
hipMalloc( (void**)&dev_c, N * sizeof(int) );
hipMemcpy( dev_a, host_a, N * sizeof(int), hipMemcpyHostToDevice );
hipMemcpy( dev_b, host_b, N * sizeof(int), hipMemcpyHostToDevice );
add<<<1,N>>>( dev_a, dev_b, dev_c );
hipMemcpy( host_c, dev_c, N * sizeof(int), hipMemcpyDeviceToHost ) ;
for (int i=0; i<N; i++) { printf( "%d + %d = %d\n", host_a[i], host_b[i], host_c[i] ); }
hipFree( dev_a ); hipFree( dev_b ); hipFree( dev_c );
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
Vector addition
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#define N 128
__global__ void add( int *a, int *b, int *c ) {
int tid = threadIdx.x;
if(tid > N-1) return;
c[tid] = a[tid] + b[tid];
}
int main() {
int host_a[N], host_b[N], host_c[N];
int *dev_a, *dev_b, *dev_c;
for (int i=0; i<N; i++) { host_a[i] = i * i; host_b[i] = - i; }
hipMalloc( (void**)&dev_a, N * sizeof(int) );
hipMalloc( (void**)&dev_b, N * sizeof(int) );
hipMalloc( (void**)&dev_c, N * sizeof(int) );
hipMemcpy( dev_a, host_a, N * sizeof(int), hipMemcpyHostToDevice );
hipMemcpy( dev_b, host_b, N * sizeof(int), hipMemcpyHostToDevice );
add<<<1,N>>>( dev_a, dev_b, dev_c );
hipMemcpy( host_c, dev_c, N * sizeof(int), hipMemcpyDeviceToHost ) ;
for (int i=0; i<N; i++) { printf( "%d + %d = %d\n", host_a[i], host_b[i], host_c[i] ); }
hipFree( dev_a ); hipFree( dev_b ); hipFree( dev_c );
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 0x80, v0
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
Vector addition
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#define N 128
__global__ void add( int *a, int *b, int *c ) {
int tid = threadIdx.x;
if(tid > N-1) return;
c[tid] = a[tid] + b[tid];
}
int main() {
int host_a[N], host_b[N], host_c[N];
int *dev_a, *dev_b, *dev_c;
for (int i=0; i<N; i++) { host_a[i] = i * i; host_b[i] = - i; }
hipMalloc( (void**)&dev_a, N * sizeof(int) );
hipMalloc( (void**)&dev_b, N * sizeof(int) );
hipMalloc( (void**)&dev_c, N * sizeof(int) );
hipMemcpy( dev_a, host_a, N * sizeof(int), hipMemcpyHostToDevice );
hipMemcpy( dev_b, host_b, N * sizeof(int), hipMemcpyHostToDevice );
add<<<1,N>>>( dev_a, dev_b, dev_c );
hipMemcpy( host_c, dev_c, N * sizeof(int), hipMemcpyDeviceToHost ) ;
for (int i=0; i<N; i++) { printf( "%d + %d = %d\n", host_a[i], host_b[i], host_c[i] ); }
hipFree( dev_a ); hipFree( dev_b ); hipFree( dev_c );
return 0;
} | .text
.file "vector_sum.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1632, %rsp # imm = 0x660
.cfi_def_cfa_offset 1648
.cfi_offset %rbx, -16
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %ecx, %edx
imull %ecx, %edx
movl %edx, 1120(%rsp,%rcx,4)
movl %eax, 608(%rsp,%rcx,4)
incq %rcx
decl %eax
cmpq $128, %rcx
jne .LBB1_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
leaq 8(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
movq %rsp, %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
movq 16(%rsp), %rdi
leaq 1120(%rsp), %rsi
movl $512, %edx # imm = 0x200
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 608(%rsp), %rsi
movl $512, %edx # imm = 0x200
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 127(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $512, %edx # imm = 0x200
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 1120(%rsp,%rbx,4), %esi
movl 608(%rsp,%rbx,4), %edx
movl 96(%rsp,%rbx,4), %ecx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $128, %rbx
jne .LBB1_5
# %bb.6:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $1632, %rsp # imm = 0x660
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d + %d = %d\n"
.size .L.str, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GT.AND P0, PT, R6, 0x7f, PT ; /* 0x0000007f0600780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 0x80, v0
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00077353_00000000-6_vector_sum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d + %d = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1608, %rsp
.cfi_def_cfa_offset 1632
movq %fs:40, %rax
movq %rax, 1592(%rsp)
xorl %eax, %eax
.L12:
movl %eax, %edx
imull %eax, %edx
movl %edx, 48(%rsp,%rax,4)
movl %eax, %edx
negl %edx
movl %edx, 560(%rsp,%rax,4)
addq $1, %rax
cmpq $128, %rax
jne .L12
movq %rsp, %rdi
movl $512, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $512, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 560(%rsp), %rsi
movl $1, %ecx
movl $512, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 1072(%rsp), %rdi
movl $2, %ecx
movl $512, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L14:
movl 560(%rsp,%rbx), %ecx
movl 48(%rsp,%rbx), %edx
movl 1072(%rsp,%rbx), %r8d
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $512, %rbx
jne .L14
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 1592(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $1608, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vector_sum.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1632, %rsp # imm = 0x660
.cfi_def_cfa_offset 1648
.cfi_offset %rbx, -16
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %ecx, %edx
imull %ecx, %edx
movl %edx, 1120(%rsp,%rcx,4)
movl %eax, 608(%rsp,%rcx,4)
incq %rcx
decl %eax
cmpq $128, %rcx
jne .LBB1_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
leaq 8(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
movq %rsp, %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
movq 16(%rsp), %rdi
leaq 1120(%rsp), %rsi
movl $512, %edx # imm = 0x200
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 608(%rsp), %rsi
movl $512, %edx # imm = 0x200
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 127(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $512, %edx # imm = 0x200
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 1120(%rsp,%rbx,4), %esi
movl 608(%rsp,%rbx,4), %edx
movl 96(%rsp,%rbx,4), %ecx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $128, %rbx
jne .LBB1_5
# %bb.6:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $1632, %rsp # imm = 0x660
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d + %d = %d\n"
.size .L.str, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void loop()
{
int curr_loc = threadIdx.x + blockIdx.x * blockDim.x;
printf("This is iteration number %d\n", curr_loc);
}
int main()
{
/*
* we could also do <<<1,10>>> or <<<5,2>>>
*/
int threads = 5;
int blocks = 2;
loop<<<blocks, threads>>>();
cudaDeviceSynchronize();
} | code for sm_80
Function : _Z4loopv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*0070*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fca0007f1e0ff */
/*0080*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe400000e06ff */
/*0090*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fe400078e0200 */
/*00a0*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e260000000a00 */
/*00b0*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0003e40000100800 */
/*00c0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*00d0*/ MOV R11, 0x140 ; /* 0x00000140000b7802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R20, 0xc0 ; /* 0x000000c000147802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fc40000000f00 */
/*0100*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x002fe40000000f00 */
/*0110*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0120*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0130*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x001fea0003c00000 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void loop()
{
int curr_loc = threadIdx.x + blockIdx.x * blockDim.x;
printf("This is iteration number %d\n", curr_loc);
}
int main()
{
/*
* we could also do <<<1,10>>> or <<<5,2>>>
*/
int threads = 5;
int blocks = 2;
loop<<<blocks, threads>>>();
cudaDeviceSynchronize();
} | .file "tmpxft_0002f663_00000000-6_02-multi-block-loop-2-solution.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z4loopvv
.type _Z22__device_stub__Z4loopvv, @function
_Z22__device_stub__Z4loopvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z4loopv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z22__device_stub__Z4loopvv, .-_Z22__device_stub__Z4loopvv
.globl _Z4loopv
.type _Z4loopv, @function
_Z4loopv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z4loopvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4loopv, .-_Z4loopv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $5, 20(%rsp)
movl $1, 24(%rsp)
movl $2, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z22__device_stub__Z4loopvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4loopv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4loopv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void loop()
{
int curr_loc = threadIdx.x + blockIdx.x * blockDim.x;
printf("This is iteration number %d\n", curr_loc);
}
int main()
{
/*
* we could also do <<<1,10>>> or <<<5,2>>>
*/
int threads = 5;
int blocks = 2;
loop<<<blocks, threads>>>();
cudaDeviceSynchronize();
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void loop()
{
int curr_loc = threadIdx.x + blockIdx.x * blockDim.x;
printf("This is iteration number %d\n", curr_loc);
}
int main()
{
/*
* we could also do <<<1,10>>> or <<<5,2>>>
*/
int threads = 5;
int blocks = 2;
loop<<<blocks, threads>>>();
hipDeviceSynchronize();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void loop()
{
int curr_loc = threadIdx.x + blockIdx.x * blockDim.x;
printf("This is iteration number %d\n", curr_loc);
}
int main()
{
/*
* we could also do <<<1,10>>> or <<<5,2>>>
*/
int threads = 5;
int blocks = 2;
loop<<<blocks, threads>>>();
hipDeviceSynchronize();
} | .text
.file "02-multi-block-loop-2-solution.hip"
.globl _Z19__device_stub__loopv # -- Begin function _Z19__device_stub__loopv
.p2align 4, 0x90
.type _Z19__device_stub__loopv,@function
_Z19__device_stub__loopv: # @_Z19__device_stub__loopv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4loopv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z19__device_stub__loopv, .Lfunc_end0-_Z19__device_stub__loopv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 3(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4loopv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4loopv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4loopv,@object # @_Z4loopv
.section .rodata,"a",@progbits
.globl _Z4loopv
.p2align 3, 0x0
_Z4loopv:
.quad _Z19__device_stub__loopv
.size _Z4loopv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4loopv"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__loopv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4loopv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002f663_00000000-6_02-multi-block-loop-2-solution.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z4loopvv
.type _Z22__device_stub__Z4loopvv, @function
_Z22__device_stub__Z4loopvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z4loopv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z22__device_stub__Z4loopvv, .-_Z22__device_stub__Z4loopvv
.globl _Z4loopv
.type _Z4loopv, @function
_Z4loopv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z4loopvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4loopv, .-_Z4loopv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $5, 20(%rsp)
movl $1, 24(%rsp)
movl $2, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z22__device_stub__Z4loopvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4loopv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4loopv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "02-multi-block-loop-2-solution.hip"
.globl _Z19__device_stub__loopv # -- Begin function _Z19__device_stub__loopv
.p2align 4, 0x90
.type _Z19__device_stub__loopv,@function
_Z19__device_stub__loopv: # @_Z19__device_stub__loopv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4loopv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z19__device_stub__loopv, .Lfunc_end0-_Z19__device_stub__loopv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 3(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4loopv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4loopv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4loopv,@object # @_Z4loopv
.section .rodata,"a",@progbits
.globl _Z4loopv
.p2align 3, 0x0
_Z4loopv:
.quad _Z19__device_stub__loopv
.size _Z4loopv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4loopv"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__loopv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4loopv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void transposeOptimized(float *input, float *output, int m, int n){
int colID_input = threadIdx.x + blockDim.x*blockIdx.x;
int rowID_input = threadIdx.y + blockDim.y*blockIdx.y;
__shared__ float sdata[32][33];
// bank ~ 一次传32 words，32次访问 ~ 32次unit time，所以希望存在shared memory里的数据尽可能多地分布在不同bank上
// 希望shared memory中每列数据所在的bank尽可能多
if (rowID_input < m && colID_input < n) {
int index_input = colID_input + rowID_input*n;
sdata[threadIdx.y][threadIdx.x] = input[index_input];
__syncthreads();
int dst_col = threadIdx.x + blockIdx.y * blockDim.y;
int dst_row = threadIdx.y + blockIdx.x * blockDim.x;
output[dst_col + dst_row*m] = sdata[threadIdx.x][threadIdx.y];
}
} | code for sm_80
Function : _Z18transposeOptimizedPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0020*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0030*/ S2R R6, SR_CTAID.Y ; /* 0x0000000000067919 */
/* 0x000e680000002600 */
/*0040*/ S2R R8, SR_TID.Y ; /* 0x0000000000087919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R4, c[0x0][0x0], R5 ; /* 0x0000000004007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R6, c[0x0][0x4], R8 ; /* 0x0000010006037a24 */
/* 0x002fca00078e0208 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x170], P0 ; /* 0x00005c0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R10, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0a7435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R3, R3, c[0x0][0x174], R0 ; /* 0x00005d0003037a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R3, R10, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fcc00078e020a */
/*00e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD R9, R8, 0x21, R5.reuse ; /* 0x0000002108097824 */
/* 0x100fe400078e0205 */
/*0100*/ IMAD R7, R5, 0x21, R8.reuse ; /* 0x0000002105077824 */
/* 0x100fe400078e0208 */
/*0110*/ IMAD R0, R4, c[0x0][0x0], R8 ; /* 0x0000000004007a24 */
/* 0x000fe400078e0208 */
/*0120*/ IMAD R5, R6, c[0x0][0x4], R5 ; /* 0x0000010006057a24 */
/* 0x000fc800078e0205 */
/*0130*/ IMAD R5, R0, c[0x0][0x170], R5 ; /* 0x00005c0000057a24 */
/* 0x000fc800078e0205 */
/*0140*/ IMAD.WIDE R4, R5, R10, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fe200078e020a */
/*0150*/ STS [R9.X4], R2 ; /* 0x0000000209007388 */
/* 0x004fe80000004800 */
/*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0170*/ LDS R7, [R7.X4] ; /* 0x0000000007077984 */
/* 0x000e280000004800 */
/*0180*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x001fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void transposeOptimized(float *input, float *output, int m, int n){
int colID_input = threadIdx.x + blockDim.x*blockIdx.x;
int rowID_input = threadIdx.y + blockDim.y*blockIdx.y;
__shared__ float sdata[32][33];
// bank ~ 一次传32 words，32次访问 ~ 32次unit time，所以希望存在shared memory里的数据尽可能多地分布在不同bank上
// 希望shared memory中每列数据所在的bank尽可能多
if (rowID_input < m && colID_input < n) {
int index_input = colID_input + rowID_input*n;
sdata[threadIdx.y][threadIdx.x] = input[index_input];
__syncthreads();
int dst_col = threadIdx.x + blockIdx.y * blockDim.y;
int dst_row = threadIdx.y + blockIdx.x * blockDim.x;
output[dst_col + dst_row*m] = sdata[threadIdx.x][threadIdx.y];
}
} | .file "tmpxft_000f61d2_00000000-6_matrix-transposition.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z18transposeOptimizedPfS_iiPfS_ii
.type _Z42__device_stub__Z18transposeOptimizedPfS_iiPfS_ii, @function
_Z42__device_stub__Z18transposeOptimizedPfS_iiPfS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18transposeOptimizedPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z18transposeOptimizedPfS_iiPfS_ii, .-_Z42__device_stub__Z18transposeOptimizedPfS_iiPfS_ii
.globl _Z18transposeOptimizedPfS_ii
.type _Z18transposeOptimizedPfS_ii, @function
_Z18transposeOptimizedPfS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z18transposeOptimizedPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18transposeOptimizedPfS_ii, .-_Z18transposeOptimizedPfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18transposeOptimizedPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18transposeOptimizedPfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
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