system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Compile: nvcc -g -G -arch=sm_61 -std=c++11 assignment5-p2.cu -o assignment5-p2
// Execute: ./assignment5-p2
#include <algorithm>
#include <hip/hip_runtime.h>
#include <iostream>
#include <sys/time.h>
#define THRESHOLD (0.000001)
#define N (1 << 24)
#define CHUNK_SIZE 2048
#define CHUNK_SIZE2 2048
using std::cerr;
using std::cout;
using std::endl;
__host__ void host_excl_prefix_sum(float* h_A, float* h_O) {
h_O[0] = 0;
for (int i = 1; i < N; i++) {
h_O[i] = h_O[i - 1] + h_A[i - 1];
}
}
__global__ void kernel_excl_prefix_sum_ver1_1(float* d_in, float* d_out) {
// TODO: Fill in
int i = blockIdx.x * blockDim.x + threadIdx.x;
i *= CHUNK_SIZE;
if(i < N){
for(int j = i+1; j < i+CHUNK_SIZE; j++){
d_out[j] = d_out[j-1] + d_in[j-1];
}
}
}
__global__ void kernel_excl_prefix_sum_ver1_2(float* d_in, float* d_out, long long int curr_chunk) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int times = curr_chunk/CHUNK_SIZE;
int chunk_num = i/times;
int chunk_part = i%times;
int c = (2*chunk_num + 1)*curr_chunk;
float sum = d_out[c-1] + d_in[c-1];
i = c + (curr_chunk * chunk_part)/times;
int upper_limit = i + CHUNK_SIZE;
if(i < N){
for(int j = i; j < upper_limit; j++){
d_out[j] += sum;
}
}
}
__global__ void kernel_excl_prefix_sum_ver2_1(float* d_in, float* d_out) {
// TODO: Fill in
int i = blockIdx.x * blockDim.x + threadIdx.x;
i *= CHUNK_SIZE2;
if(i < N){
for(int j = i+1; j < i+CHUNK_SIZE2; j++){
d_out[j] = d_out[j-1] + d_in[j-1];
}
}
}
__global__ void kernel_excl_prefix_sum_ver2_2(float* d_in, float* d_out, long long int curr_chunk) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int times = curr_chunk/CHUNK_SIZE2;
int chunk_num = i/times;
int chunk_part = i%times;
int c = (2*chunk_num + 1)*curr_chunk;
float sum = d_out[c-1] + d_in[c-1];
i = c + (curr_chunk * chunk_part)/times;
int upper_limit = i + CHUNK_SIZE2;
if(i < N){
for(int j = i; j + 3 < upper_limit; j += 4){
d_out[j] += sum;
d_out[j+1] += sum;
d_out[j+2] += sum;
d_out[j+3] += sum;
}
}
}
__host__ void check_result(float* w_ref, float* w_opt) {
double maxdiff = 0.0, this_diff = 0.0;
int numdiffs = 0;
for (int i = 0; i < N; i++) {
this_diff = w_ref[i] - w_opt[i];
if (fabs(this_diff) > THRESHOLD) {
numdiffs++;
if (this_diff > maxdiff)
maxdiff = this_diff;
}
}
if (numdiffs > 0) {
cout << numdiffs << " Diffs found over threshold " << THRESHOLD << "; Max Diff = " << maxdiff
<< endl;
} else {
cout << "No differences found between base and test versions\n";
}
}
__host__ double rtclock() { // Seconds
struct timezone Tzp;
struct timeval Tp;
int stat;
stat = gettimeofday(&Tp, &Tzp);
if (stat != 0) {
cout << "Error return from gettimeofday: " << stat << "\n";
}
return (Tp.tv_sec + Tp.tv_usec * 1.0e-6);
}
int main() {
size_t size = N * sizeof(float);
float* h_in = (float*)malloc(size);
std::fill_n(h_in, N, 1);
float* h_excl_sum_out = (float*)malloc(size);
std::fill_n(h_excl_sum_out, N, 0);
double clkbegin = rtclock();
host_excl_prefix_sum(h_in, h_excl_sum_out);
double clkend = rtclock();
double time = clkend - clkbegin; // seconds
cout << "Serial time on CPU: " << time * 1000 << " msec" << endl;
float* h_dev_result = (float*)malloc(size);
std::fill_n(h_dev_result, N, 0);
float* d_k1_in;
float* d_k1_out;
hipError_t status;
hipEvent_t start, end;
// TODO: Fill in
status = hipMalloc(&d_k1_in, size);
if (status != hipSuccess) {
fprintf(stderr, "cudaMalloc() failed");
return EXIT_FAILURE;
}
status = hipMalloc(&d_k1_out, size);
if (status != hipSuccess) {
fprintf(stderr, "cudaMalloc() failed");
return EXIT_FAILURE;
}
hipEventCreate(&start);
hipEventCreate(&end);
hipEventRecord(start, 0);
status = hipMemcpy(d_k1_in, h_in, size, hipMemcpyHostToDevice);
if (status != hipSuccess) {
fprintf(stderr, "cudaMemcpy() failed");
return EXIT_FAILURE;
}
status = hipMemcpy(d_k1_out, h_dev_result, size, hipMemcpyHostToDevice);
if (status != hipSuccess) {
fprintf(stderr, "cudaMemcpy() failed");
return EXIT_FAILURE;
}
dim3 threadsPerBlock(256);
dim3 numBlocks(((N/CHUNK_SIZE) + threadsPerBlock.x - 1)/threadsPerBlock.x);
kernel_excl_prefix_sum_ver1_1<<<numBlocks, threadsPerBlock>>>(d_k1_in, d_k1_out);
numBlocks = dim3((N/(2*CHUNK_SIZE) + threadsPerBlock.x - 1)/threadsPerBlock.x);
long long int curr_chunk = CHUNK_SIZE;
while(curr_chunk != N){
kernel_excl_prefix_sum_ver1_2<<<numBlocks, threadsPerBlock>>>(d_k1_in, d_k1_out, curr_chunk);
curr_chunk *= 2;
}
status = hipMemcpy(h_dev_result, d_k1_out, size, hipMemcpyDeviceToHost);
if (status != hipSuccess) {
fprintf(stderr, "cudaMemcpy() failed");
return EXIT_FAILURE;
}
hipEventRecord(end, 0);
hipEventSynchronize(end);
float k_time; // ms
hipEventElapsedTime(&k_time, start, end);
hipEventDestroy(start);
hipEventDestroy(end);
check_result(h_excl_sum_out, h_dev_result);
cout << "Kernel1 time on GPU: " << k_time << " msec" << endl;
// kernel 2
std::fill_n(h_dev_result, N, 0);
float* d_k2_in;
float* d_k2_out;
status = hipMalloc(&d_k2_in, size);
if (status != hipSuccess) {
fprintf(stderr, "cudaMalloc() failed");
return EXIT_FAILURE;
}
status = hipMalloc(&d_k2_out, size);
if (status != hipSuccess) {
fprintf(stderr, "cudaMalloc() failed");
return EXIT_FAILURE;
}
hipEventCreate(&start);
hipEventCreate(&end);
hipEventRecord(start, 0);
status = hipMemcpy(d_k2_in, h_in, size, hipMemcpyHostToDevice);
if (status != hipSuccess) {
fprintf(stderr, "cudaMemcpy() failed");
return EXIT_FAILURE;
}
status = hipMemcpy(d_k2_out, h_dev_result, size, hipMemcpyHostToDevice);
if (status != hipSuccess) {
fprintf(stderr, "cudaMemcpy() failed");
return EXIT_FAILURE;
}
threadsPerBlock = dim3(256);
numBlocks = dim3(((N/CHUNK_SIZE2) + threadsPerBlock.x - 1)/threadsPerBlock.x);
kernel_excl_prefix_sum_ver2_1<<<numBlocks, threadsPerBlock>>>(d_k2_in, d_k2_out);
threadsPerBlock = dim3(256);
numBlocks = dim3((N/(2*CHUNK_SIZE2) + threadsPerBlock.x - 1)/threadsPerBlock.x);
curr_chunk = CHUNK_SIZE2;
while(curr_chunk != N){
kernel_excl_prefix_sum_ver2_2<<<numBlocks, threadsPerBlock>>>(d_k2_in, d_k2_out, curr_chunk);
curr_chunk *= 2;
}
status = hipMemcpy(h_dev_result, d_k2_out, size, hipMemcpyDeviceToHost);
if (status != hipSuccess) {
fprintf(stderr, "cudaMemcpy() failed");
return EXIT_FAILURE;
}
hipEventRecord(end, 0);
hipEventSynchronize(end);
hipEventElapsedTime(&k_time, start, end);
hipEventDestroy(start);
hipEventDestroy(end);
check_result(h_excl_sum_out, h_dev_result);
cout << "Kernel2 time on GPU: " << k_time << " msec" << endl;
// Free device memory
hipFree(d_k1_in);
hipFree(d_k1_out);
hipFree(d_k2_in);
hipFree(d_k2_out);
free(h_in);
free(h_excl_sum_out);
free(h_dev_result);
return EXIT_SUCCESS;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z29kernel_excl_prefix_sum_ver1_1PfS_
.globl _Z29kernel_excl_prefix_sum_ver1_1PfS_
.p2align 8
.type _Z29kernel_excl_prefix_sum_ver1_1PfS_,@function
_Z29kernel_excl_prefix_sum_ver1_1PfS_:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x2000, v1
s_cbranch_execz .LBB0_3
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 11, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v0, v[3:4], off
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_mov_b64 s[0:1], 0
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1)
v_add_co_u32 v5, vcc_lo, v1, s0
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v2, vcc_lo
global_load_b32 v7, v[5:6], off
v_add_co_u32 v5, vcc_lo, v3, s0
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v4, vcc_lo
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmpk_lg_i32 s0, 0x1ffc
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v7
global_store_b32 v[5:6], v0, off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z29kernel_excl_prefix_sum_ver1_1PfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z29kernel_excl_prefix_sum_ver1_1PfS_, .Lfunc_end0-_Z29kernel_excl_prefix_sum_ver1_1PfS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z29kernel_excl_prefix_sum_ver1_2PfS_x
.globl _Z29kernel_excl_prefix_sum_ver1_2PfS_x
.p2align 8
.type _Z29kernel_excl_prefix_sum_ver1_2PfS_x,@function
_Z29kernel_excl_prefix_sum_ver1_2PfS_x:
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x10
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_ashr_i32 s3, s7, 31
s_and_b32 s8, s2, 0xffff
s_lshr_b32 s3, s3, 21
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_u32 s2, s6, s3
s_addc_u32 s3, s7, 0
s_ashr_i64 s[4:5], s[2:3], 11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s2, s4, 31
s_add_i32 s3, s4, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s3, s3, s2
v_cvt_f32_u32_e32 v1, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s8, v[0:1]
s_sub_i32 s8, 0, s3
v_mul_lo_u32 v0, s8, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_mul_hi_u32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v2, v3
v_xor_b32_e32 v4, v4, v3
v_xor_b32_e32 v3, s2, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v1, v0
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v0, s3
v_sub_nc_u32_e32 v1, v4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s3, v1
v_cmp_le_u32_e32 vcc_lo, s3, v1
v_dual_cndmask_b32 v1, v1, v5 :: v_dual_add_nc_u32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s3, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, 1, v0
s_load_b128 s[0:3], s[0:1], 0x0
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v3
v_sub_nc_u32_e32 v8, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_or_b32 v0, v8, 1, 1
v_mul_lo_u32 v0, v0, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[3:4], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, v3, -4
v_add_co_ci_u32_e32 v5, vcc_lo, -1, v4, vcc_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v5, vcc_lo
global_load_b32 v5, v[3:4], off
global_load_b32 v6, v[6:7], off
v_mul_lo_u32 v1, v8, s4
s_bfe_i64 s[0:1], s[4:5], 0x200000
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v2, v1
v_ashrrev_i32_e32 v1, 31, v3
v_mul_lo_u32 v7, v3, s7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mul_lo_u32 v4, v1, s6
v_mad_u64_u32 v[1:2], null, v3, s6, 0
v_mov_b32_e32 v3, 0
v_add3_u32 v2, v2, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v4, s1, v2
v_cmp_ne_u64_e32 vcc_lo, 0, v[3:4]
s_and_saveexec_b32 s5, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s5, exec_lo, s5
s_cbranch_execz .LBB1_2
s_add_u32 s0, s0, s1
s_mov_b32 s6, s1
s_mov_b32 s7, s1
s_addc_u32 s1, s1, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b64 s[8:9], s[0:1], s[6:7]
v_cvt_f32_u32_e32 v3, s8
v_cvt_f32_u32_e32 v4, s9
s_sub_u32 s0, 0, s8
s_subb_u32 s1, 0, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v3, v4, 0x4f800000, v3
v_rcp_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x5f7ffffc, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, 0x2f800000, v3
v_trunc_f32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmamk_f32 v3, v4, 0xcf800000, v3
v_cvt_u32_f32_e32 v4, v4
v_cvt_u32_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v7, s0, v4
v_mul_hi_u32 v8, s0, v3
v_mul_lo_u32 v9, s1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v7, v8, v7
v_mul_lo_u32 v8, s0, v3
v_add_nc_u32_e32 v7, v7, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v3, v8
v_mul_lo_u32 v10, v3, v7
v_mul_hi_u32 v11, v3, v7
v_mul_hi_u32 v12, v4, v8
v_mul_lo_u32 v8, v4, v8
v_mul_hi_u32 v13, v4, v7
v_mul_lo_u32 v7, v4, v7
v_add_co_u32 v9, vcc_lo, v9, v10
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, v9, v8
v_add_co_ci_u32_e32 v8, vcc_lo, v10, v12, vcc_lo
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v13, vcc_lo
v_ashrrev_i32_e32 v12, 31, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, v8, v7
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, v3, v7
v_add_co_ci_u32_e32 v4, vcc_lo, v4, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v7, s0, v3
v_mul_lo_u32 v9, s1, v3
v_mul_lo_u32 v8, s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v7, v7, v8
v_mul_lo_u32 v8, s0, v3
v_add_nc_u32_e32 v7, v7, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v3, v8
v_mul_lo_u32 v10, v3, v7
v_mul_hi_u32 v11, v3, v7
v_mul_hi_u32 v13, v4, v8
v_mul_lo_u32 v8, v4, v8
v_mul_hi_u32 v14, v4, v7
v_mul_lo_u32 v7, v4, v7
v_add_co_u32 v9, vcc_lo, v9, v10
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, v9, v8
v_add_co_ci_u32_e32 v8, vcc_lo, v10, v13, vcc_lo
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v14, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, v12
v_add_co_ci_u32_e32 v2, vcc_lo, v2, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, v8, v7
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v9, v1, v12
v_add_co_u32 v7, vcc_lo, v3, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v10, vcc_lo, v4, v8, vcc_lo
v_xor_b32_e32 v11, v2, v12
v_mul_hi_u32 v13, v9, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[1:2], null, v9, v10, 0
v_mad_u64_u32 v[3:4], null, v11, v7, 0
v_mad_u64_u32 v[7:8], null, v11, v10, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, v13, v1
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, v1, v3
v_add_co_ci_u32_e32 v1, vcc_lo, v2, v4, vcc_lo
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, v1, v7
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v7, s9, v3
v_mad_u64_u32 v[1:2], null, s8, v3, 0
v_mul_lo_u32 v4, s8, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v1, vcc_lo, v9, v1
v_add3_u32 v2, v2, v4, v7
v_add_co_u32 v7, s0, v3, 2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v11, v2
v_subrev_co_ci_u32_e64 v4, s0, s9, v4, vcc_lo
v_sub_co_u32 v8, s0, v1, s8
v_sub_co_ci_u32_e32 v2, vcc_lo, v11, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_subrev_co_ci_u32_e64 v4, s0, 0, v4, s0
v_cmp_le_u32_e32 vcc_lo, s8, v8
v_cndmask_b32_e64 v8, 0, -1, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s9, v4
v_cndmask_b32_e64 v9, 0, -1, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s8, v1
v_cndmask_b32_e64 v1, 0, -1, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s9, v2
v_cndmask_b32_e64 v10, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, s9, v4
v_cndmask_b32_e32 v4, v9, v8, vcc_lo
v_add_co_u32 v8, vcc_lo, v3, 1
v_cmp_eq_u32_e32 vcc_lo, s9, v2
v_cndmask_b32_e32 v1, v10, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_ne_u32_e32 vcc_lo, 0, v4
v_cndmask_b32_e32 v2, v8, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e32 vcc_lo, 0, v1
v_cndmask_b32_e32 v1, v3, v2, vcc_lo
v_xor_b32_e32 v2, s6, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v1, v1, v2
v_sub_co_u32 v3, vcc_lo, v1, v2
.LBB1_2:
s_and_not1_saveexec_b32 s0, s5
s_cbranch_execz .LBB1_4
s_mov_b32 s1, s4
s_sub_i32 s4, 0, s4
v_cvt_f32_u32_e32 v2, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, s4, v2
v_mul_hi_u32 v3, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v2, v3
v_mul_hi_u32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v2, s1
v_sub_nc_u32_e32 v1, v1, v3
v_add_nc_u32_e32 v3, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v4, s1, v1
v_cmp_le_u32_e32 vcc_lo, s1, v1
v_dual_cndmask_b32 v1, v1, v4 :: v_dual_cndmask_b32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s1, v1
v_add_nc_u32_e32 v3, 1, v2
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e32 v3, v2, v3, vcc_lo
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v0, v3
s_mov_b32 s0, exec_lo
v_cmpx_gt_i32_e32 0x1000000, v1
s_cbranch_execz .LBB1_7
v_ashrrev_i32_e32 v2, 31, v1
v_add3_u32 v3, v0, v3, -1
v_add_nc_u32_e32 v4, 0x7ff, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[1:2]
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v5, v6
v_add_co_u32 v0, vcc_lo, s2, v7
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v8, vcc_lo
.LBB1_6:
global_load_b32 v5, v[0:1], off
v_add_nc_u32_e32 v3, 1, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ge_i32_e32 vcc_lo, v3, v4
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_add_f32_e32 v5, v2, v5
global_store_b32 v[0:1], v5, off
v_add_co_u32 v0, s0, v0, 4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, s0, 0, v1, s0
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB1_6
.LBB1_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z29kernel_excl_prefix_sum_ver1_2PfS_x
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z29kernel_excl_prefix_sum_ver1_2PfS_x, .Lfunc_end1-_Z29kernel_excl_prefix_sum_ver1_2PfS_x
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z29kernel_excl_prefix_sum_ver2_1PfS_
.globl _Z29kernel_excl_prefix_sum_ver2_1PfS_
.p2align 8
.type _Z29kernel_excl_prefix_sum_ver2_1PfS_,@function
_Z29kernel_excl_prefix_sum_ver2_1PfS_:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x2000, v1
s_cbranch_execz .LBB2_3
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 11, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v0, v[3:4], off
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_mov_b64 s[0:1], 0
.LBB2_2:
s_delay_alu instid0(SALU_CYCLE_1)
v_add_co_u32 v5, vcc_lo, v1, s0
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v2, vcc_lo
global_load_b32 v7, v[5:6], off
v_add_co_u32 v5, vcc_lo, v3, s0
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v4, vcc_lo
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmpk_lg_i32 s0, 0x1ffc
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v7
global_store_b32 v[5:6], v0, off
s_cbranch_scc1 .LBB2_2
.LBB2_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z29kernel_excl_prefix_sum_ver2_1PfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z29kernel_excl_prefix_sum_ver2_1PfS_, .Lfunc_end2-_Z29kernel_excl_prefix_sum_ver2_1PfS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z29kernel_excl_prefix_sum_ver2_2PfS_x
.globl _Z29kernel_excl_prefix_sum_ver2_2PfS_x
.p2align 8
.type _Z29kernel_excl_prefix_sum_ver2_2PfS_x,@function
_Z29kernel_excl_prefix_sum_ver2_2PfS_x:
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x10
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_ashr_i32 s3, s7, 31
s_and_b32 s8, s2, 0xffff
s_lshr_b32 s3, s3, 21
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_u32 s2, s6, s3
s_addc_u32 s3, s7, 0
s_ashr_i64 s[4:5], s[2:3], 11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s2, s4, 31
s_add_i32 s3, s4, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s3, s3, s2
v_cvt_f32_u32_e32 v1, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s8, v[0:1]
s_sub_i32 s8, 0, s3
v_mul_lo_u32 v0, s8, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_mul_hi_u32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v2, v3
v_xor_b32_e32 v4, v4, v3
v_xor_b32_e32 v3, s2, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v1, v0
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v0, s3
v_sub_nc_u32_e32 v1, v4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s3, v1
v_cmp_le_u32_e32 vcc_lo, s3, v1
v_dual_cndmask_b32 v1, v1, v5 :: v_dual_add_nc_u32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s3, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, 1, v0
s_load_b128 s[0:3], s[0:1], 0x0
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v3
v_sub_nc_u32_e32 v8, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_or_b32 v0, v8, 1, 1
v_mul_lo_u32 v0, v0, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[3:4], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, v3, -4
v_add_co_ci_u32_e32 v5, vcc_lo, -1, v4, vcc_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v5, vcc_lo
global_load_b32 v5, v[3:4], off
global_load_b32 v6, v[6:7], off
v_mul_lo_u32 v1, v8, s4
s_bfe_i64 s[0:1], s[4:5], 0x200000
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v2, v1
v_ashrrev_i32_e32 v1, 31, v3
v_mul_lo_u32 v7, v3, s7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mul_lo_u32 v4, v1, s6
v_mad_u64_u32 v[1:2], null, v3, s6, 0
v_mov_b32_e32 v3, 0
v_add3_u32 v2, v2, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v4, s1, v2
v_cmp_ne_u64_e32 vcc_lo, 0, v[3:4]
s_and_saveexec_b32 s5, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s5, exec_lo, s5
s_cbranch_execz .LBB3_2
s_add_u32 s0, s0, s1
s_mov_b32 s6, s1
s_mov_b32 s7, s1
s_addc_u32 s1, s1, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b64 s[8:9], s[0:1], s[6:7]
v_cvt_f32_u32_e32 v3, s8
v_cvt_f32_u32_e32 v4, s9
s_sub_u32 s0, 0, s8
s_subb_u32 s1, 0, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v3, v4, 0x4f800000, v3
v_rcp_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x5f7ffffc, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, 0x2f800000, v3
v_trunc_f32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmamk_f32 v3, v4, 0xcf800000, v3
v_cvt_u32_f32_e32 v4, v4
v_cvt_u32_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v7, s0, v4
v_mul_hi_u32 v8, s0, v3
v_mul_lo_u32 v9, s1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v7, v8, v7
v_mul_lo_u32 v8, s0, v3
v_add_nc_u32_e32 v7, v7, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v3, v8
v_mul_lo_u32 v10, v3, v7
v_mul_hi_u32 v11, v3, v7
v_mul_hi_u32 v12, v4, v8
v_mul_lo_u32 v8, v4, v8
v_mul_hi_u32 v13, v4, v7
v_mul_lo_u32 v7, v4, v7
v_add_co_u32 v9, vcc_lo, v9, v10
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, v9, v8
v_add_co_ci_u32_e32 v8, vcc_lo, v10, v12, vcc_lo
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v13, vcc_lo
v_ashrrev_i32_e32 v12, 31, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, v8, v7
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, v3, v7
v_add_co_ci_u32_e32 v4, vcc_lo, v4, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v7, s0, v3
v_mul_lo_u32 v9, s1, v3
v_mul_lo_u32 v8, s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v7, v7, v8
v_mul_lo_u32 v8, s0, v3
v_add_nc_u32_e32 v7, v7, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v3, v8
v_mul_lo_u32 v10, v3, v7
v_mul_hi_u32 v11, v3, v7
v_mul_hi_u32 v13, v4, v8
v_mul_lo_u32 v8, v4, v8
v_mul_hi_u32 v14, v4, v7
v_mul_lo_u32 v7, v4, v7
v_add_co_u32 v9, vcc_lo, v9, v10
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, v9, v8
v_add_co_ci_u32_e32 v8, vcc_lo, v10, v13, vcc_lo
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v14, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, v12
v_add_co_ci_u32_e32 v2, vcc_lo, v2, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, v8, v7
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v9, v1, v12
v_add_co_u32 v7, vcc_lo, v3, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v10, vcc_lo, v4, v8, vcc_lo
v_xor_b32_e32 v11, v2, v12
v_mul_hi_u32 v13, v9, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[1:2], null, v9, v10, 0
v_mad_u64_u32 v[3:4], null, v11, v7, 0
v_mad_u64_u32 v[7:8], null, v11, v10, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, v13, v1
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, v1, v3
v_add_co_ci_u32_e32 v1, vcc_lo, v2, v4, vcc_lo
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, v1, v7
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v7, s9, v3
v_mad_u64_u32 v[1:2], null, s8, v3, 0
v_mul_lo_u32 v4, s8, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v1, vcc_lo, v9, v1
v_add3_u32 v2, v2, v4, v7
v_add_co_u32 v7, s0, v3, 2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v11, v2
v_subrev_co_ci_u32_e64 v4, s0, s9, v4, vcc_lo
v_sub_co_u32 v8, s0, v1, s8
v_sub_co_ci_u32_e32 v2, vcc_lo, v11, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_subrev_co_ci_u32_e64 v4, s0, 0, v4, s0
v_cmp_le_u32_e32 vcc_lo, s8, v8
v_cndmask_b32_e64 v8, 0, -1, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s9, v4
v_cndmask_b32_e64 v9, 0, -1, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s8, v1
v_cndmask_b32_e64 v1, 0, -1, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s9, v2
v_cndmask_b32_e64 v10, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, s9, v4
v_cndmask_b32_e32 v4, v9, v8, vcc_lo
v_add_co_u32 v8, vcc_lo, v3, 1
v_cmp_eq_u32_e32 vcc_lo, s9, v2
v_cndmask_b32_e32 v1, v10, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_ne_u32_e32 vcc_lo, 0, v4
v_cndmask_b32_e32 v2, v8, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e32 vcc_lo, 0, v1
v_cndmask_b32_e32 v1, v3, v2, vcc_lo
v_xor_b32_e32 v2, s6, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v1, v1, v2
v_sub_co_u32 v3, vcc_lo, v1, v2
.LBB3_2:
s_and_not1_saveexec_b32 s0, s5
s_cbranch_execz .LBB3_4
s_mov_b32 s1, s4
s_sub_i32 s4, 0, s4
v_cvt_f32_u32_e32 v2, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, s4, v2
v_mul_hi_u32 v3, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v2, v3
v_mul_hi_u32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v2, s1
v_sub_nc_u32_e32 v1, v1, v3
v_add_nc_u32_e32 v3, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v4, s1, v1
v_cmp_le_u32_e32 vcc_lo, s1, v1
v_dual_cndmask_b32 v1, v1, v4 :: v_dual_cndmask_b32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s1, v1
v_add_nc_u32_e32 v3, 1, v2
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e32 v3, v2, v3, vcc_lo
.LBB3_4:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v0, v3
s_mov_b32 s0, exec_lo
v_cmpx_gt_i32_e32 0x1000000, v1
s_cbranch_execz .LBB3_7
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v4, 0x7f9, v1
v_add3_u32 v3, v0, v3, -4
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[1:2]
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v5, v6
v_add_co_u32 v1, vcc_lo, v7, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v8, vcc_lo
v_add_co_u32 v0, vcc_lo, v1, 8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v5, vcc_lo
.p2align 6
.LBB3_6:
s_clause 0x1
global_load_b64 v[5:6], v[0:1], off offset:-8
global_load_b64 v[7:8], v[0:1], off
s_waitcnt vmcnt(1)
v_dual_add_f32 v6, v2, v6 :: v_dual_add_nc_u32 v3, 4, v3
v_add_f32_e32 v5, v2, v5
s_waitcnt vmcnt(0)
v_add_f32_e32 v7, v2, v7
v_add_f32_e32 v8, v2, v8
v_cmp_ge_i32_e32 vcc_lo, v3, v4
s_clause 0x1
global_store_b64 v[0:1], v[5:6], off offset:-8
global_store_b64 v[0:1], v[7:8], off
v_add_co_u32 v0, s0, v0, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v1, s0, 0, v1, s0
s_or_b32 s1, vcc_lo, s1
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB3_6
.LBB3_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z29kernel_excl_prefix_sum_ver2_2PfS_x
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z29kernel_excl_prefix_sum_ver2_2PfS_x, .Lfunc_end3-_Z29kernel_excl_prefix_sum_ver2_2PfS_x
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z29kernel_excl_prefix_sum_ver1_1PfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z29kernel_excl_prefix_sum_ver1_1PfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z29kernel_excl_prefix_sum_ver1_2PfS_x
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z29kernel_excl_prefix_sum_ver1_2PfS_x.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z29kernel_excl_prefix_sum_ver2_1PfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z29kernel_excl_prefix_sum_ver2_1PfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z29kernel_excl_prefix_sum_ver2_2PfS_x
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z29kernel_excl_prefix_sum_ver2_2PfS_x.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Compile: nvcc -g -G -arch=sm_61 -std=c++11 assignment5-p2.cu -o assignment5-p2
// Execute: ./assignment5-p2
#include <algorithm>
#include <hip/hip_runtime.h>
#include <iostream>
#include <sys/time.h>
#define THRESHOLD (0.000001)
#define N (1 << 24)
#define CHUNK_SIZE 2048
#define CHUNK_SIZE2 2048
using std::cerr;
using std::cout;
using std::endl;
__host__ void host_excl_prefix_sum(float* h_A, float* h_O) {
h_O[0] = 0;
for (int i = 1; i < N; i++) {
h_O[i] = h_O[i - 1] + h_A[i - 1];
}
}
__global__ void kernel_excl_prefix_sum_ver1_1(float* d_in, float* d_out) {
// TODO: Fill in
int i = blockIdx.x * blockDim.x + threadIdx.x;
i *= CHUNK_SIZE;
if(i < N){
for(int j = i+1; j < i+CHUNK_SIZE; j++){
d_out[j] = d_out[j-1] + d_in[j-1];
}
}
}
__global__ void kernel_excl_prefix_sum_ver1_2(float* d_in, float* d_out, long long int curr_chunk) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int times = curr_chunk/CHUNK_SIZE;
int chunk_num = i/times;
int chunk_part = i%times;
int c = (2*chunk_num + 1)*curr_chunk;
float sum = d_out[c-1] + d_in[c-1];
i = c + (curr_chunk * chunk_part)/times;
int upper_limit = i + CHUNK_SIZE;
if(i < N){
for(int j = i; j < upper_limit; j++){
d_out[j] += sum;
}
}
}
__global__ void kernel_excl_prefix_sum_ver2_1(float* d_in, float* d_out) {
// TODO: Fill in
int i = blockIdx.x * blockDim.x + threadIdx.x;
i *= CHUNK_SIZE2;
if(i < N){
for(int j = i+1; j < i+CHUNK_SIZE2; j++){
d_out[j] = d_out[j-1] + d_in[j-1];
}
}
}
__global__ void kernel_excl_prefix_sum_ver2_2(float* d_in, float* d_out, long long int curr_chunk) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int times = curr_chunk/CHUNK_SIZE2;
int chunk_num = i/times;
int chunk_part = i%times;
int c = (2*chunk_num + 1)*curr_chunk;
float sum = d_out[c-1] + d_in[c-1];
i = c + (curr_chunk * chunk_part)/times;
int upper_limit = i + CHUNK_SIZE2;
if(i < N){
for(int j = i; j + 3 < upper_limit; j += 4){
d_out[j] += sum;
d_out[j+1] += sum;
d_out[j+2] += sum;
d_out[j+3] += sum;
}
}
}
__host__ void check_result(float* w_ref, float* w_opt) {
double maxdiff = 0.0, this_diff = 0.0;
int numdiffs = 0;
for (int i = 0; i < N; i++) {
this_diff = w_ref[i] - w_opt[i];
if (fabs(this_diff) > THRESHOLD) {
numdiffs++;
if (this_diff > maxdiff)
maxdiff = this_diff;
}
}
if (numdiffs > 0) {
cout << numdiffs << " Diffs found over threshold " << THRESHOLD << "; Max Diff = " << maxdiff
<< endl;
} else {
cout << "No differences found between base and test versions\n";
}
}
__host__ double rtclock() { // Seconds
struct timezone Tzp;
struct timeval Tp;
int stat;
stat = gettimeofday(&Tp, &Tzp);
if (stat != 0) {
cout << "Error return from gettimeofday: " << stat << "\n";
}
return (Tp.tv_sec + Tp.tv_usec * 1.0e-6);
}
int main() {
size_t size = N * sizeof(float);
float* h_in = (float*)malloc(size);
std::fill_n(h_in, N, 1);
float* h_excl_sum_out = (float*)malloc(size);
std::fill_n(h_excl_sum_out, N, 0);
double clkbegin = rtclock();
host_excl_prefix_sum(h_in, h_excl_sum_out);
double clkend = rtclock();
double time = clkend - clkbegin; // seconds
cout << "Serial time on CPU: " << time * 1000 << " msec" << endl;
float* h_dev_result = (float*)malloc(size);
std::fill_n(h_dev_result, N, 0);
float* d_k1_in;
float* d_k1_out;
hipError_t status;
hipEvent_t start, end;
// TODO: Fill in
status = hipMalloc(&d_k1_in, size);
if (status != hipSuccess) {
fprintf(stderr, "cudaMalloc() failed");
return EXIT_FAILURE;
}
status = hipMalloc(&d_k1_out, size);
if (status != hipSuccess) {
fprintf(stderr, "cudaMalloc() failed");
return EXIT_FAILURE;
}
hipEventCreate(&start);
hipEventCreate(&end);
hipEventRecord(start, 0);
status = hipMemcpy(d_k1_in, h_in, size, hipMemcpyHostToDevice);
if (status != hipSuccess) {
fprintf(stderr, "cudaMemcpy() failed");
return EXIT_FAILURE;
}
status = hipMemcpy(d_k1_out, h_dev_result, size, hipMemcpyHostToDevice);
if (status != hipSuccess) {
fprintf(stderr, "cudaMemcpy() failed");
return EXIT_FAILURE;
}
dim3 threadsPerBlock(256);
dim3 numBlocks(((N/CHUNK_SIZE) + threadsPerBlock.x - 1)/threadsPerBlock.x);
kernel_excl_prefix_sum_ver1_1<<<numBlocks, threadsPerBlock>>>(d_k1_in, d_k1_out);
numBlocks = dim3((N/(2*CHUNK_SIZE) + threadsPerBlock.x - 1)/threadsPerBlock.x);
long long int curr_chunk = CHUNK_SIZE;
while(curr_chunk != N){
kernel_excl_prefix_sum_ver1_2<<<numBlocks, threadsPerBlock>>>(d_k1_in, d_k1_out, curr_chunk);
curr_chunk *= 2;
}
status = hipMemcpy(h_dev_result, d_k1_out, size, hipMemcpyDeviceToHost);
if (status != hipSuccess) {
fprintf(stderr, "cudaMemcpy() failed");
return EXIT_FAILURE;
}
hipEventRecord(end, 0);
hipEventSynchronize(end);
float k_time; // ms
hipEventElapsedTime(&k_time, start, end);
hipEventDestroy(start);
hipEventDestroy(end);
check_result(h_excl_sum_out, h_dev_result);
cout << "Kernel1 time on GPU: " << k_time << " msec" << endl;
// kernel 2
std::fill_n(h_dev_result, N, 0);
float* d_k2_in;
float* d_k2_out;
status = hipMalloc(&d_k2_in, size);
if (status != hipSuccess) {
fprintf(stderr, "cudaMalloc() failed");
return EXIT_FAILURE;
}
status = hipMalloc(&d_k2_out, size);
if (status != hipSuccess) {
fprintf(stderr, "cudaMalloc() failed");
return EXIT_FAILURE;
}
hipEventCreate(&start);
hipEventCreate(&end);
hipEventRecord(start, 0);
status = hipMemcpy(d_k2_in, h_in, size, hipMemcpyHostToDevice);
if (status != hipSuccess) {
fprintf(stderr, "cudaMemcpy() failed");
return EXIT_FAILURE;
}
status = hipMemcpy(d_k2_out, h_dev_result, size, hipMemcpyHostToDevice);
if (status != hipSuccess) {
fprintf(stderr, "cudaMemcpy() failed");
return EXIT_FAILURE;
}
threadsPerBlock = dim3(256);
numBlocks = dim3(((N/CHUNK_SIZE2) + threadsPerBlock.x - 1)/threadsPerBlock.x);
kernel_excl_prefix_sum_ver2_1<<<numBlocks, threadsPerBlock>>>(d_k2_in, d_k2_out);
threadsPerBlock = dim3(256);
numBlocks = dim3((N/(2*CHUNK_SIZE2) + threadsPerBlock.x - 1)/threadsPerBlock.x);
curr_chunk = CHUNK_SIZE2;
while(curr_chunk != N){
kernel_excl_prefix_sum_ver2_2<<<numBlocks, threadsPerBlock>>>(d_k2_in, d_k2_out, curr_chunk);
curr_chunk *= 2;
}
status = hipMemcpy(h_dev_result, d_k2_out, size, hipMemcpyDeviceToHost);
if (status != hipSuccess) {
fprintf(stderr, "cudaMemcpy() failed");
return EXIT_FAILURE;
}
hipEventRecord(end, 0);
hipEventSynchronize(end);
hipEventElapsedTime(&k_time, start, end);
hipEventDestroy(start);
hipEventDestroy(end);
check_result(h_excl_sum_out, h_dev_result);
cout << "Kernel2 time on GPU: " << k_time << " msec" << endl;
// Free device memory
hipFree(d_k1_in);
hipFree(d_k1_out);
hipFree(d_k2_in);
hipFree(d_k2_out);
free(h_in);
free(h_excl_sum_out);
free(h_dev_result);
return EXIT_SUCCESS;
} | .text
.file "assignment5-p2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z20host_excl_prefix_sumPfS_ # -- Begin function _Z20host_excl_prefix_sumPfS_
.p2align 4, 0x90
.type _Z20host_excl_prefix_sumPfS_,@function
_Z20host_excl_prefix_sumPfS_: # @_Z20host_excl_prefix_sumPfS_
.cfi_startproc
# %bb.0:
movl $0, (%rsi)
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
addss (%rdi,%rax,4), %xmm0
movss %xmm0, 4(%rsi,%rax,4)
incq %rax
cmpq $16777215, %rax # imm = 0xFFFFFF
jne .LBB0_1
# %bb.2:
retq
.Lfunc_end0:
.size _Z20host_excl_prefix_sumPfS_, .Lfunc_end0-_Z20host_excl_prefix_sumPfS_
.cfi_endproc
# -- End function
.globl _Z44__device_stub__kernel_excl_prefix_sum_ver1_1PfS_ # -- Begin function _Z44__device_stub__kernel_excl_prefix_sum_ver1_1PfS_
.p2align 4, 0x90
.type _Z44__device_stub__kernel_excl_prefix_sum_ver1_1PfS_,@function
_Z44__device_stub__kernel_excl_prefix_sum_ver1_1PfS_: # @_Z44__device_stub__kernel_excl_prefix_sum_ver1_1PfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z29kernel_excl_prefix_sum_ver1_1PfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z44__device_stub__kernel_excl_prefix_sum_ver1_1PfS_, .Lfunc_end1-_Z44__device_stub__kernel_excl_prefix_sum_ver1_1PfS_
.cfi_endproc
# -- End function
.globl _Z44__device_stub__kernel_excl_prefix_sum_ver1_2PfS_x # -- Begin function _Z44__device_stub__kernel_excl_prefix_sum_ver1_2PfS_x
.p2align 4, 0x90
.type _Z44__device_stub__kernel_excl_prefix_sum_ver1_2PfS_x,@function
_Z44__device_stub__kernel_excl_prefix_sum_ver1_2PfS_x: # @_Z44__device_stub__kernel_excl_prefix_sum_ver1_2PfS_x
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z29kernel_excl_prefix_sum_ver1_2PfS_x, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z44__device_stub__kernel_excl_prefix_sum_ver1_2PfS_x, .Lfunc_end2-_Z44__device_stub__kernel_excl_prefix_sum_ver1_2PfS_x
.cfi_endproc
# -- End function
.globl _Z44__device_stub__kernel_excl_prefix_sum_ver2_1PfS_ # -- Begin function _Z44__device_stub__kernel_excl_prefix_sum_ver2_1PfS_
.p2align 4, 0x90
.type _Z44__device_stub__kernel_excl_prefix_sum_ver2_1PfS_,@function
_Z44__device_stub__kernel_excl_prefix_sum_ver2_1PfS_: # @_Z44__device_stub__kernel_excl_prefix_sum_ver2_1PfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z29kernel_excl_prefix_sum_ver2_1PfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z44__device_stub__kernel_excl_prefix_sum_ver2_1PfS_, .Lfunc_end3-_Z44__device_stub__kernel_excl_prefix_sum_ver2_1PfS_
.cfi_endproc
# -- End function
.globl _Z44__device_stub__kernel_excl_prefix_sum_ver2_2PfS_x # -- Begin function _Z44__device_stub__kernel_excl_prefix_sum_ver2_2PfS_x
.p2align 4, 0x90
.type _Z44__device_stub__kernel_excl_prefix_sum_ver2_2PfS_x,@function
_Z44__device_stub__kernel_excl_prefix_sum_ver2_2PfS_x: # @_Z44__device_stub__kernel_excl_prefix_sum_ver2_2PfS_x
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z29kernel_excl_prefix_sum_ver2_2PfS_x, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size _Z44__device_stub__kernel_excl_prefix_sum_ver2_2PfS_x, .Lfunc_end4-_Z44__device_stub__kernel_excl_prefix_sum_ver2_2PfS_x
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z12check_resultPfS_
.LCPI5_0:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI5_1:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z12check_resultPfS_
.p2align 4, 0x90
.type _Z12check_resultPfS_,@function
_Z12check_resultPfS_: # @_Z12check_resultPfS_
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rax
xorpd %xmm4, %xmm4
xorl %ecx, %ecx
movaps .LCPI5_0(%rip), %xmm0 # xmm0 = [NaN,NaN]
movsd .LCPI5_1(%rip), %xmm1 # xmm1 = mem[0],zero
xorl %esi, %esi
jmp .LBB5_1
.p2align 4, 0x90
.LBB5_4: # in Loop: Header=BB5_1 Depth=1
incq %rcx
cmpq $16777216, %rcx # imm = 0x1000000
je .LBB5_5
.LBB5_1: # =>This Inner Loop Header: Depth=1
movss (%rdi,%rcx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss (%rax,%rcx,4), %xmm2
cvtss2sd %xmm2, %xmm2
movaps %xmm2, %xmm3
andps %xmm0, %xmm3
ucomisd %xmm1, %xmm3
jbe .LBB5_4
# %bb.2: # in Loop: Header=BB5_1 Depth=1
incl %esi
ucomisd %xmm4, %xmm2
jbe .LBB5_4
# %bb.3: # in Loop: Header=BB5_1 Depth=1
movapd %xmm2, %xmm4
jmp .LBB5_4
.LBB5_5:
movl $_ZSt4cout, %edi
testl %esi, %esi
jle .LBB5_11
# %bb.6:
movsd %xmm4, (%rsp) # 8-byte Spill
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str, %esi
movl $28, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd .LCPI5_1(%rip), %xmm0 # xmm0 = mem[0],zero
movq %rbx, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $13, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB5_12
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB5_9
# %bb.8:
movzbl 67(%rbx), %ecx
jmp .LBB5_10
.LBB5_11:
movl $.L.str.2, %esi
movl $52, %edx
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l # TAILCALL
.LBB5_9:
.cfi_def_cfa_offset 32
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB5_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB5_12:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end5:
.size _Z12check_resultPfS_, .Lfunc_end5-_Z12check_resultPfS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7rtclockv
.LCPI6_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z7rtclockv
.p2align 4, 0x90
.type _Z7rtclockv,@function
_Z7rtclockv: # @_Z7rtclockv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
leaq 8(%rsp), %rdi
leaq 24(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB6_2
# %bb.1:
movl %eax, %ebx
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $32, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB6_2:
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
mulsd .LCPI6_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z7rtclockv, .Lfunc_end6-_Z7rtclockv
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI7_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.LCPI7_1:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB7_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax) # imm = 0x3F800000
addq $4, %rax
cmpq $67108864, %rax # imm = 0x4000000
jne .LBB7_1
# %bb.2: # %_ZSt6fill_nIPfiiET_S1_T0_RKT1_.exit
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r12
movl $67108864, %edx # imm = 0x4000000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 96(%rsp), %rdi
leaq 8(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB7_4
# %bb.3:
movl %eax, %ebp
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $32, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebp, %esi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB7_4: # %_Z7rtclockv.exit
cvtsi2sdq 104(%rsp), %xmm1
mulsd .LCPI7_0(%rip), %xmm1
movq 96(%rsp), %rax
movl $0, (%r12)
movl $1, %ecx
xorps %xmm0, %xmm0
.p2align 4, 0x90
.LBB7_5: # =>This Inner Loop Header: Depth=1
addss -4(%rbx,%rcx,4), %xmm0
movss %xmm0, (%r12,%rcx,4)
incq %rcx
cmpq $16777216, %rcx # imm = 0x1000000
jne .LBB7_5
# %bb.6: # %_Z20host_excl_prefix_sumPfS_.exit
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
addsd %xmm0, %xmm1
movsd %xmm1, 24(%rsp) # 8-byte Spill
leaq 96(%rsp), %rdi
leaq 8(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB7_8
# %bb.7:
movl %eax, %ebp
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $32, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebp, %esi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB7_8: # %_Z7rtclockv.exit102
xorps %xmm0, %xmm0
cvtsi2sdq 96(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 104(%rsp), %xmm1
mulsd .LCPI7_0(%rip), %xmm1
addsd %xmm0, %xmm1
subsd 24(%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, 24(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI7_1(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.6, %esi
movl $5, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB7_48
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB7_11
# %bb.10:
movzbl 67(%r15), %eax
jmp .LBB7_12
.LBB7_11:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB7_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r14
movl $67108864, %edx # imm = 0x4000000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 152(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
testl %eax, %eax
jne .LBB7_13
# %bb.15:
leaq 136(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
testl %eax, %eax
jne .LBB7_13
# %bb.16:
leaq 32(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 152(%rsp), %rdi
movl $1, %ebp
movl $67108864, %edx # imm = 0x4000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB7_17
# %bb.18:
movq 136(%rsp), %rdi
movl $1, %ebp
movl $67108864, %edx # imm = 0x4000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB7_17
# %bb.19:
movq %r14, 24(%rsp) # 8-byte Spill
movq %r12, 168(%rsp) # 8-byte Spill
movabsq $4294967552, %r14 # imm = 0x100000100
leaq -224(%r14), %rdi
movq %rdi, 176(%rsp) # 8-byte Spill
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_21
# %bb.20:
movq 152(%rsp), %rax
movq 136(%rsp), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z29kernel_excl_prefix_sum_ver1_1PfS_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_21:
movl $2048, %r15d # imm = 0x800
leaq -240(%r14), %r13
leaq 40(%rsp), %r14
leaq 160(%rsp), %r12
leaq 96(%rsp), %rbp
jmp .LBB7_22
.p2align 4, 0x90
.LBB7_24: # in Loop: Header=BB7_22 Depth=1
leaq (%r15,%r15), %rax
cmpq $8388608, %r15 # imm = 0x800000
movq %rax, %r15
je .LBB7_25
.LBB7_22: # =>This Inner Loop Header: Depth=1
movq %r13, %rdi
movl $1, %esi
movabsq $4294967552, %rdx # imm = 0x100000100
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_24
# %bb.23: # in Loop: Header=BB7_22 Depth=1
movq 152(%rsp), %rax
movq 136(%rsp), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r15, 64(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rdi
leaq 48(%rsp), %rsi
movq %r14, %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z29kernel_excl_prefix_sum_ver1_2PfS_x, %edi
movq %rbp, %r9
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB7_24
.LBB7_25:
movq 136(%rsp), %rsi
movl $67108864, %edx # imm = 0x4000000
movq 24(%rsp), %r14 # 8-byte Reload
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB7_26
# %bb.27:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq (%rsp), %rdx
leaq 92(%rsp), %rdi
callq hipEventElapsedTime
movq 32(%rsp), %rdi
callq hipEventDestroy
movq (%rsp), %rdi
callq hipEventDestroy
movq 168(%rsp), %rdi # 8-byte Reload
movq %r14, %rsi
callq _Z12check_resultPfS_
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 92(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.6, %esi
movl $5, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB7_48
# %bb.28: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i128
cmpb $0, 56(%r15)
je .LBB7_30
# %bb.29:
movzbl 67(%r15), %eax
jmp .LBB7_31
.LBB7_30:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB7_31: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit131
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $67108864, %edx # imm = 0x4000000
movq 24(%rsp), %r14 # 8-byte Reload
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 144(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
testl %eax, %eax
jne .LBB7_13
# %bb.32:
leaq 128(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
testl %eax, %eax
jne .LBB7_13
# %bb.33:
leaq 32(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 144(%rsp), %rdi
movl $1, %ebp
movl $67108864, %edx # imm = 0x4000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB7_17
# %bb.34:
movq 128(%rsp), %rdi
movl $1, %ebp
movl $67108864, %edx # imm = 0x4000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB7_17
# %bb.35:
movq 176(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movabsq $4294967552, %rdx # imm = 0x100000100
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_37
# %bb.36:
movq 144(%rsp), %rax
movq 128(%rsp), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z29kernel_excl_prefix_sum_ver2_1PfS_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_37:
movl $2048, %r15d # imm = 0x800
leaq 40(%rsp), %r14
leaq 160(%rsp), %r12
leaq 96(%rsp), %rbp
jmp .LBB7_38
.p2align 4, 0x90
.LBB7_40: # in Loop: Header=BB7_38 Depth=1
leaq (%r15,%r15), %rax
cmpq $8388608, %r15 # imm = 0x800000
movq %rax, %r15
je .LBB7_41
.LBB7_38: # =>This Inner Loop Header: Depth=1
movq %r13, %rdi
movl $1, %esi
movabsq $4294967552, %rdx # imm = 0x100000100
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_40
# %bb.39: # in Loop: Header=BB7_38 Depth=1
movq 144(%rsp), %rax
movq 128(%rsp), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r15, 64(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rdi
leaq 48(%rsp), %rsi
movq %r14, %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z29kernel_excl_prefix_sum_ver2_2PfS_x, %edi
movq %rbp, %r9
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB7_40
.LBB7_41:
movq 128(%rsp), %rsi
movl $67108864, %edx # imm = 0x4000000
movq 24(%rsp), %r14 # 8-byte Reload
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB7_26
# %bb.42:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq (%rsp), %rdx
leaq 92(%rsp), %rdi
callq hipEventElapsedTime
movq 32(%rsp), %rdi
callq hipEventDestroy
movq (%rsp), %rdi
callq hipEventDestroy
movq 168(%rsp), %r12 # 8-byte Reload
movq %r12, %rdi
movq %r14, %rsi
callq _Z12check_resultPfS_
movl $_ZSt4cout, %edi
movl $.L.str.10, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 92(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.6, %esi
movl $5, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB7_48
# %bb.43: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i133
cmpb $0, 56(%r15)
je .LBB7_45
# %bb.44:
movzbl 67(%r15), %eax
jmp .LBB7_46
.LBB7_45:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB7_46: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit136
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 152(%rsp), %rdi
callq hipFree
movq 136(%rsp), %rdi
callq hipFree
movq 144(%rsp), %rdi
callq hipFree
movq 128(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r12, %rdi
callq free
movq 24(%rsp), %rdi # 8-byte Reload
callq free
xorl %ebp, %ebp
jmp .LBB7_47
.LBB7_13:
movq stderr(%rip), %rcx
movl $.L.str.7, %edi
jmp .LBB7_14
.LBB7_17:
movq stderr(%rip), %rcx
movl $.L.str.8, %edi
movl $19, %esi
movl $1, %edx
callq fwrite@PLT
jmp .LBB7_47
.LBB7_26:
movq stderr(%rip), %rcx
movl $.L.str.8, %edi
.LBB7_14:
movl $19, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %ebp
.LBB7_47:
movl %ebp, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB7_48:
.cfi_def_cfa_offset 240
callq _ZSt16__throw_bad_castv
.Lfunc_end7:
.size main, .Lfunc_end7-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z29kernel_excl_prefix_sum_ver1_1PfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z29kernel_excl_prefix_sum_ver1_2PfS_x, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z29kernel_excl_prefix_sum_ver2_1PfS_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z29kernel_excl_prefix_sum_ver2_2PfS_x, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z29kernel_excl_prefix_sum_ver1_1PfS_,@object # @_Z29kernel_excl_prefix_sum_ver1_1PfS_
.section .rodata,"a",@progbits
.globl _Z29kernel_excl_prefix_sum_ver1_1PfS_
.p2align 3, 0x0
_Z29kernel_excl_prefix_sum_ver1_1PfS_:
.quad _Z44__device_stub__kernel_excl_prefix_sum_ver1_1PfS_
.size _Z29kernel_excl_prefix_sum_ver1_1PfS_, 8
.type _Z29kernel_excl_prefix_sum_ver1_2PfS_x,@object # @_Z29kernel_excl_prefix_sum_ver1_2PfS_x
.globl _Z29kernel_excl_prefix_sum_ver1_2PfS_x
.p2align 3, 0x0
_Z29kernel_excl_prefix_sum_ver1_2PfS_x:
.quad _Z44__device_stub__kernel_excl_prefix_sum_ver1_2PfS_x
.size _Z29kernel_excl_prefix_sum_ver1_2PfS_x, 8
.type _Z29kernel_excl_prefix_sum_ver2_1PfS_,@object # @_Z29kernel_excl_prefix_sum_ver2_1PfS_
.globl _Z29kernel_excl_prefix_sum_ver2_1PfS_
.p2align 3, 0x0
_Z29kernel_excl_prefix_sum_ver2_1PfS_:
.quad _Z44__device_stub__kernel_excl_prefix_sum_ver2_1PfS_
.size _Z29kernel_excl_prefix_sum_ver2_1PfS_, 8
.type _Z29kernel_excl_prefix_sum_ver2_2PfS_x,@object # @_Z29kernel_excl_prefix_sum_ver2_2PfS_x
.globl _Z29kernel_excl_prefix_sum_ver2_2PfS_x
.p2align 3, 0x0
_Z29kernel_excl_prefix_sum_ver2_2PfS_x:
.quad _Z44__device_stub__kernel_excl_prefix_sum_ver2_2PfS_x
.size _Z29kernel_excl_prefix_sum_ver2_2PfS_x, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " Diffs found over threshold "
.size .L.str, 29
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "
.size .L.str.1, 14
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "No differences found between base and test versions\n"
.size .L.str.2, 53
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Error return from gettimeofday: "
.size .L.str.3, 33
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\n"
.size .L.str.4, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Serial time on CPU: "
.size .L.str.5, 21
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " msec"
.size .L.str.6, 6
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "cudaMalloc() failed"
.size .L.str.7, 20
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "cudaMemcpy() failed"
.size .L.str.8, 20
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Kernel1 time on GPU: "
.size .L.str.9, 22
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Kernel2 time on GPU: "
.size .L.str.10, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z29kernel_excl_prefix_sum_ver1_1PfS_"
.size .L__unnamed_1, 38
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z29kernel_excl_prefix_sum_ver1_2PfS_x"
.size .L__unnamed_2, 39
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z29kernel_excl_prefix_sum_ver2_1PfS_"
.size .L__unnamed_3, 38
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z29kernel_excl_prefix_sum_ver2_2PfS_x"
.size .L__unnamed_4, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z44__device_stub__kernel_excl_prefix_sum_ver1_1PfS_
.addrsig_sym _Z44__device_stub__kernel_excl_prefix_sum_ver1_2PfS_x
.addrsig_sym _Z44__device_stub__kernel_excl_prefix_sum_ver2_1PfS_
.addrsig_sym _Z44__device_stub__kernel_excl_prefix_sum_ver2_2PfS_x
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z29kernel_excl_prefix_sum_ver1_1PfS_
.addrsig_sym _Z29kernel_excl_prefix_sum_ver1_2PfS_x
.addrsig_sym _Z29kernel_excl_prefix_sum_ver2_1PfS_
.addrsig_sym _Z29kernel_excl_prefix_sum_ver2_2PfS_x
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void check_for_generator_spikes_kernel(int *d_neuron_ids_for_stimulus, float *d_spike_times_for_stimulus, float* d_last_spike_time_of_each_neuron, unsigned char* d_bitarray_of_neuron_spikes, int bitarray_length, int bitarray_maximum_axonal_delay_in_timesteps, float current_time_in_seconds, float timestep, size_t number_of_spikes_in_stimulus, bool high_fidelity_spike_flag) {
// // Get thread IDs
int idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < number_of_spikes_in_stimulus) {
if (fabs(current_time_in_seconds - d_spike_times_for_stimulus[idx]) < 0.5 * timestep) {
__syncthreads();
d_last_spike_time_of_each_neuron[d_neuron_ids_for_stimulus[idx]] = current_time_in_seconds;
if (high_fidelity_spike_flag){
// Get start of the given neuron's bits
int neuron_id_spike_store_start = d_neuron_ids_for_stimulus[idx] * bitarray_length;
// Get offset depending upon the current timestep
int offset_index = (int)(round((float)(current_time_in_seconds / timestep))) % bitarray_maximum_axonal_delay_in_timesteps;
int offset_byte = offset_index / 8;
int offset_bit_pos = offset_index - (8 * offset_byte);
// Get the specific position at which we should be putting the current value
unsigned char byte = d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte];
// Set the specific bit in the byte to on
byte |= (1 << offset_bit_pos);
// Assign the byte
d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte] = byte;
}
} else {
// High fidelity spike storage
if (high_fidelity_spike_flag){
// Get start of the given neuron's bits
int neuron_id_spike_store_start = d_neuron_ids_for_stimulus[idx] * bitarray_length;
// Get offset depending upon the current timestep
int offset_index = (int)(round((float)(current_time_in_seconds / timestep))) % bitarray_maximum_axonal_delay_in_timesteps;
int offset_byte = offset_index / 8;
int offset_bit_pos = offset_index - (8 * offset_byte);
// Get the specific position at which we should be putting the current value
unsigned char byte = d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte];
// Set the specific bit in the byte to on
byte &= ~(1 << offset_bit_pos);
// Assign the byte
d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte] = byte;
}
}
idx += blockDim.x * gridDim.x;
}
__syncthreads();
} | code for sm_80
Function : _Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x190], PT ; /* 0x0000640000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R6, RZ, 0x1f, R0 ; /* 0x0000001fff067819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R6, c[0x0][0x194], PT, P0 ; /* 0x0000650006007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 BRA 0x8a0 ; /* 0x0000082000000947 */
/* 0x000fea0003800000 */
/*0080*/ MUFU.RCP R2, c[0x0][0x18c] ; /* 0x0000630000027b08 */
/* 0x000e220000001000 */
/*0090*/ ULDC UR4, c[0x0][0x188] ; /* 0x0000620000047ab9 */
/* 0x000fe20000000800 */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff057624 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD.U32 R8, RZ, RZ, UR4 ; /* 0x00000004ff087e24 */
/* 0x000fe4000f8e00ff */
/*00c0*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0000 */
/*00d0*/ FCHK P0, R8, c[0x0][0x18c] ; /* 0x0000630008007b02 */
/* 0x000e620000000000 */
/*00e0*/ FFMA R3, R2, -R5, 1 ; /* 0x3f80000002037423 */
/* 0x001fc80000000805 */
/*00f0*/ FFMA R3, R2, R3, R2 ; /* 0x0000000302037223 */
/* 0x000fc80000000002 */
/*0100*/ FFMA R4, R3, c[0x0][0x188], RZ ; /* 0x0000620003047a23 */
/* 0x000fc800000000ff */
/*0110*/ FFMA R2, R4, -R5, c[0x0][0x188] ; /* 0x0000620004027623 */
/* 0x000fc80000000805 */
/*0120*/ FFMA R4, R3, R2, R4 ; /* 0x0000000203047223 */
/* 0x000fe20000000004 */
/*0130*/ @!P0 BRA 0x160 ; /* 0x0000002000008947 */
/* 0x002fea0003800000 */
/*0140*/ MOV R2, 0x160 ; /* 0x0000016000027802 */
/* 0x000fe40000000f00 */
/*0150*/ CALL.REL.NOINC 0x8d0 ; /* 0x0000077000007944 */
/* 0x000fea0003c00000 */
/*0160*/ F2F.F64.F32 R2, c[0x0][0x18c] ; /* 0x0000630000027b10 */
/* 0x000e220000201800 */
/*0170*/ LOP3.LUT R5, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004057812 */
/* 0x000fc800078ec0ff */
/*0180*/ LOP3.LUT R5, R5, 0x3f000000, RZ, 0xfc, !PT ; /* 0x3f00000005057812 */
/* 0x000fe200078efcff */
/*0190*/ DMUL R2, R2, 0.5 ; /* 0x3fe0000002027828 */
/* 0x001e080000000000 */
/*01a0*/ IMAD.SHL.U32 R10, R7.reuse, 0x4, RZ ; /* 0x00000004070a7824 */
/* 0x040fe200078e00ff */
/*01b0*/ SHF.L.U64.HI R11, R7, 0x2, R6 ; /* 0x00000002070b7819 */
/* 0x000fe20000010206 */
/*01c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*01d0*/ IADD3 R8, P0, R10, c[0x0][0x168], RZ ; /* 0x00005a000a087a10 */
/* 0x000fc80007f1e0ff */
/*01e0*/ IADD3.X R9, R11, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b000b097a10 */
/* 0x000fca00007fe4ff */
/*01f0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1900 */
/*0200*/ IADD3 R10, P1, R10, c[0x0][0x160], RZ ; /* 0x000058000a0a7a10 */
/* 0x000fc80007f3e0ff */
/*0210*/ IADD3.X R11, R11, c[0x0][0x164], RZ, P1, !PT ; /* 0x000059000b0b7a10 */
/* 0x000fe20000ffe4ff */
/*0220*/ FADD R6, -R8, c[0x0][0x188] ; /* 0x0000620008067621 */
/* 0x004fcc0000000100 */
/*0230*/ F2F.F64.F32 R6, |R6| ; /* 0x4000000600067310 */
/* 0x000e640000201800 */
/*0240*/ DSETP.GT.AND P0, PT, R2, R6, PT ; /* 0x000000060200722a */
/* 0x003e1c0003f04000 */
/*0250*/ @P0 BRA 0x510 ; /* 0x000002b000000947 */
/* 0x001fea0003800000 */
/*0260*/ ULDC.S8 UR4, c[0x0][0x198] ; /* 0x0000660000047ab9 */
/* 0x000fe40000000200 */
/*0270*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf05270 */
/*0280*/ @!P0 BRA 0x830 ; /* 0x000005a000008947 */
/* 0x000fea0003800000 */
/*0290*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*02a0*/ LDG.E R13, [R10.64] ; /* 0x000000040a0d7981 */
/* 0x0000a2000c1e1900 */
/*02b0*/ IABS R12, c[0x0][0x184] ; /* 0x00006100000c7a13 */
/* 0x000fe20000000000 */
/*02c0*/ FADD.RZ R6, R5, R4 ; /* 0x0000000405067221 */
/* 0x000fc6000000c000 */
/*02d0*/ I2F.RP R9, R12 ; /* 0x0000000c00097306 */
/* 0x000e700000209400 */
/*02e0*/ F2I.TRUNC.NTZ R8, R6 ; /* 0x0000000600087305 */
/* 0x000730000020f100 */
/*02f0*/ MUFU.RCP R9, R9 ; /* 0x0000000900097308 */
/* 0x002e620000001000 */
/*0300*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x008fe200078e00ff */
/*0310*/ ISETP.GE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x010fc40003f46270 */
/*0320*/ IADD3 R7, R9, 0xffffffe, RZ ; /* 0x0ffffffe09077810 */
/* 0x002fe40007ffe0ff */
/*0330*/ IABS R9, R8 ; /* 0x0000000800097213 */
/* 0x000fc80000000000 */
/*0340*/ F2I.FTZ.U32.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e64000021f000 */
/*0350*/ IMAD.MOV R15, RZ, RZ, -R7 ; /* 0x000000ffff0f7224 */
/* 0x002fc800078e0a07 */
/*0360*/ IMAD R11, R15, R12, RZ ; /* 0x0000000c0f0b7224 */
/* 0x001fc800078e02ff */
/*0370*/ IMAD.HI.U32 R10, R7, R11, R6 ; /* 0x0000000b070a7227 */
/* 0x000fcc00078e0006 */
/*0380*/ IMAD.HI.U32 R10, R10, R9, RZ ; /* 0x000000090a0a7227 */
/* 0x000fc800078e00ff */
/*0390*/ IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0a7224 */
/* 0x000fc800078e0a0a */
/*03a0*/ IMAD R7, R12, R10, R9 ; /* 0x0000000a0c077224 */
/* 0x000fca00078e0209 */
/*03b0*/ ISETP.GT.U32.AND P0, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x000fda0003f04070 */
/*03c0*/ @!P0 IMAD.IADD R7, R7, 0x1, -R12 ; /* 0x0000000107078824 */
/* 0x000fe200078e0a0c */
/*03d0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x184], PT ; /* 0x00006100ff007a0c */
/* 0x000fc80003f05270 */
/*03e0*/ ISETP.GT.U32.AND P1, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x000fda0003f24070 */
/*03f0*/ @!P1 IMAD.IADD R7, R7, 0x1, -R12 ; /* 0x0000000107079824 */
/* 0x000fc800078e0a0c */
/*0400*/ IMAD.MOV.U32 R8, RZ, RZ, R7 ; /* 0x000000ffff087224 */
/* 0x000fc800078e0007 */
/*0410*/ @!P2 IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff08a224 */
/* 0x000fe200078e0a08 */
/*0420*/ @!P0 LOP3.LUT R8, RZ, c[0x0][0x184], RZ, 0x33, !PT ; /* 0x00006100ff088a12 */
/* 0x000fc800078e33ff */
/*0430*/ SHF.R.S32.HI R7, RZ, 0x1f, R8 ; /* 0x0000001fff077819 */
/* 0x000fc80000011408 */
/*0440*/ LEA.HI R9, R7, R8, RZ, 0x3 ; /* 0x0000000807097211 */
/* 0x000fc800078f18ff */
/*0450*/ SHF.R.S32.HI R6, RZ, 0x3, R9 ; /* 0x00000003ff067819 */
/* 0x000fca0000011409 */
/*0460*/ IMAD R7, R13, c[0x0][0x180], R6 ; /* 0x000060000d077a24 */
/* 0x004fca00078e0206 */
/*0470*/ IADD3 R6, P0, R7, c[0x0][0x178], RZ ; /* 0x00005e0007067a10 */
/* 0x000fc80007f1e0ff */
/*0480*/ LEA.HI.X.SX32 R7, R7, c[0x0][0x17c], 0x1, P0 ; /* 0x00005f0007077a11 */
/* 0x000fca00000f0eff */
/*0490*/ LDG.E.U8 R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x000ea2000c1e1100 */
/*04a0*/ LOP3.LUT R9, R9, 0xfffffff8, RZ, 0xc0, !PT ; /* 0xfffffff809097812 */
/* 0x000fe200078ec0ff */
/*04b0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x1 ; /* 0x00000001ff0c7424 */
/* 0x000fc800078e00ff */
/*04c0*/ IMAD.IADD R9, R8, 0x1, -R9 ; /* 0x0000000108097824 */
/* 0x000fca00078e0a09 */
/*04d0*/ SHF.L.U32 R9, R12, R9, RZ ; /* 0x000000090c097219 */
/* 0x000fc800000006ff */
/*04e0*/ LOP3.LUT R9, R10, R9, RZ, 0x30, !PT ; /* 0x000000090a097212 */
/* 0x004fca00078e30ff */
/*04f0*/ STG.E.U8 [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e2000c101104 */
/*0500*/ BRA 0x830 ; /* 0x0000032000007947 */
/* 0x000fea0003800000 */
/*0510*/ ULDC.S8 UR4, c[0x0][0x198] ; /* 0x0000660000047ab9 */
/* 0x000fe40000000200 */
/*0520*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf05270 */
/*0530*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0540*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0550*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc40000000a00 */
/*0560*/ LDG.E R6, [R10.64] ; /* 0x000000040a067981 */
/* 0x000ea2000c1e1900 */
/*0570*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe400078e00ff */
/*0580*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff097624 */
/* 0x000fe400078e00ff */
/*0590*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x004fca00078e0207 */
/*05a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e2000c101904 */
/*05b0*/ @!P0 BRA 0x830 ; /* 0x0000027000008947 */
/* 0x000fea0003800000 */
/*05c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*05d0*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x0002a2000c1e1900 */
/*05e0*/ IABS R9, c[0x0][0x184] ; /* 0x0000610000097a13 */
/* 0x001fe20000000000 */
/*05f0*/ FADD.RZ R6, R5, R4 ; /* 0x0000000405067221 */
/* 0x000fe2000000c000 */
/*0600*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x184], PT ; /* 0x00006100ff007a0c */
/* 0x000fe40003f45270 */
/*0610*/ I2F.RP R12, R9 ; /* 0x00000009000c7306 */
/* 0x000e300000209400 */
/*0620*/ F2I.TRUNC.NTZ R8, R6 ; /* 0x0000000600087305 */
/* 0x000670000020f100 */
/*0630*/ MUFU.RCP R12, R12 ; /* 0x0000000c000c7308 */
/* 0x001e220000001000 */
/*0640*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x008fe200078e00ff */
/*0650*/ IABS R10, R8 ; /* 0x00000008000a7213 */
/* 0x002fc40000000000 */
/*0660*/ ISETP.GE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f26270 */
/*0670*/ IADD3 R7, R12, 0xffffffe, RZ ; /* 0x0ffffffe0c077810 */
/* 0x001fcc0007ffe0ff */
/*0680*/ F2I.FTZ.U32.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e24000021f000 */
/*0690*/ IMAD.MOV R14, RZ, RZ, -R7 ; /* 0x000000ffff0e7224 */
/* 0x001fc800078e0a07 */
/*06a0*/ IMAD R13, R14, R9, RZ ; /* 0x000000090e0d7224 */
/* 0x000fc800078e02ff */
/*06b0*/ IMAD.HI.U32 R13, R7, R13, R6 ; /* 0x0000000d070d7227 */
/* 0x000fcc00078e0006 */
/*06c0*/ IMAD.HI.U32 R13, R13, R10, RZ ; /* 0x0000000a0d0d7227 */
/* 0x000fc800078e00ff */
/*06d0*/ IMAD.MOV R13, RZ, RZ, -R13 ; /* 0x000000ffff0d7224 */
/* 0x000fc800078e0a0d */
/*06e0*/ IMAD R10, R9, R13, R10 ; /* 0x0000000d090a7224 */
/* 0x000fca00078e020a */
/*06f0*/ ISETP.GT.U32.AND P0, PT, R9, R10, PT ; /* 0x0000000a0900720c */
/* 0x000fda0003f04070 */
/*0700*/ @!P0 IMAD.IADD R10, R10, 0x1, -R9 ; /* 0x000000010a0a8824 */
/* 0x000fca00078e0a09 */
/*0710*/ ISETP.GT.U32.AND P0, PT, R9, R10, PT ; /* 0x0000000a0900720c */
/* 0x000fda0003f04070 */
/*0720*/ @!P0 IMAD.IADD R10, R10, 0x1, -R9 ; /* 0x000000010a0a8824 */
/* 0x000fc800078e0a09 */
/*0730*/ IMAD.MOV.U32 R8, RZ, RZ, R10 ; /* 0x000000ffff087224 */
/* 0x000fc800078e000a */
/*0740*/ @!P1 IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff089224 */
/* 0x000fe200078e0a08 */
/*0750*/ @!P2 LOP3.LUT R8, RZ, c[0x0][0x184], RZ, 0x33, !PT ; /* 0x00006100ff08aa12 */
/* 0x000fc800078e33ff */
/*0760*/ SHF.R.S32.HI R7, RZ, 0x1f, R8 ; /* 0x0000001fff077819 */
/* 0x000fc80000011408 */
/*0770*/ LEA.HI R9, R7, R8, RZ, 0x3 ; /* 0x0000000807097211 */
/* 0x000fc800078f18ff */
/*0780*/ SHF.R.S32.HI R6, RZ, 0x3, R9 ; /* 0x00000003ff067819 */
/* 0x000fca0000011409 */
/*0790*/ IMAD R7, R11, c[0x0][0x180], R6 ; /* 0x000060000b077a24 */
/* 0x004fca00078e0206 */
/*07a0*/ IADD3 R6, P0, R7, c[0x0][0x178], RZ ; /* 0x00005e0007067a10 */
/* 0x000fc80007f1e0ff */
/*07b0*/ LEA.HI.X.SX32 R7, R7, c[0x0][0x17c], 0x1, P0 ; /* 0x00005f0007077a11 */
/* 0x000fca00000f0eff */
/*07c0*/ LDG.E.U8 R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x000ea2000c1e1100 */
/*07d0*/ LOP3.LUT R9, R9, 0xfffffff8, RZ, 0xc0, !PT ; /* 0xfffffff809097812 */
/* 0x000fe200078ec0ff */
/*07e0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x1 ; /* 0x00000001ff0c7424 */
/* 0x000fc800078e00ff */
/*07f0*/ IMAD.IADD R9, R8, 0x1, -R9 ; /* 0x0000000108097824 */
/* 0x000fca00078e0a09 */
/*0800*/ SHF.L.U32 R9, R12, R9, RZ ; /* 0x000000090c097219 */
/* 0x000fc800000006ff */
/*0810*/ LOP3.LUT R9, R10, R9, RZ, 0xfc, !PT ; /* 0x000000090a097212 */
/* 0x004fca00078efcff */
/*0820*/ STG.E.U8 [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e4000c101104 */
/*0830*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff077624 */
/* 0x001fc800078e00ff */
/*0840*/ IMAD R7, R7, c[0x0][0xc], R0 ; /* 0x0000030007077a24 */
/* 0x000fc800078e0200 */
/*0850*/ IMAD.MOV.U32 R0, RZ, RZ, R7.reuse ; /* 0x000000ffff007224 */
/* 0x100fe200078e0007 */
/*0860*/ ISETP.GE.U32.AND P0, PT, R7, c[0x0][0x190], PT ; /* 0x0000640007007a0c */
/* 0x000fe40003f06070 */
/*0870*/ SHF.R.S32.HI R6, RZ, 0x1f, R7 ; /* 0x0000001fff067819 */
/* 0x000fc80000011407 */
/*0880*/ ISETP.GE.U32.AND.EX P0, PT, R6, c[0x0][0x194], PT, P0 ; /* 0x0000650006007a0c */
/* 0x000fda0003f06100 */
/*0890*/ @!P0 BRA 0x1a0 ; /* 0xfffff90000008947 */
/* 0x000fea000383ffff */
/*08a0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*08b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*08c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08d0*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff0d7624 */
/* 0x000fe400078e00ff */
/*08e0*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff0a7624 */
/* 0x000fe400078e00ff */
/*08f0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff057624 */
/* 0x000fe200078e00ff */
/*0900*/ SHF.R.U32.HI R4, RZ, 0x17, R13 ; /* 0x00000017ff047819 */
/* 0x000fe2000001160d */
/*0910*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff087624 */
/* 0x000fe200078e00ff */
/*0920*/ SHF.R.U32.HI R3, RZ, 0x17, R10 ; /* 0x00000017ff037819 */
/* 0x000fc4000001160a */
/*0930*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fe400078ec0ff */
/*0940*/ LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03037812 */
/* 0x000fe400078ec0ff */
/*0950*/ IADD3 R12, R4, -0x1, RZ ; /* 0xffffffff040c7810 */
/* 0x000fe40007ffe0ff */
/*0960*/ IADD3 R11, R3, -0x1, RZ ; /* 0xffffffff030b7810 */
/* 0x000fe40007ffe0ff */
/*0970*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fc80003f04070 */
/*0980*/ ISETP.GT.U32.OR P0, PT, R11, 0xfd, P0 ; /* 0x000000fd0b00780c */
/* 0x000fda0000704470 */
/*0990*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*09a0*/ @!P0 BRA 0xb20 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*09b0*/ FSETP.GTU.FTZ.AND P0, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fe40003f1c200 */
/*09c0*/ FSETP.GTU.FTZ.AND P1, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fc80003f3c200 */
/*09d0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*09e0*/ @P0 BRA 0xf00 ; /* 0x0000051000000947 */
/* 0x000fea0003800000 */
/*09f0*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R5, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c805 */
/*0a00*/ @!P0 BRA 0xee0 ; /* 0x000004d000008947 */
/* 0x000fea0003800000 */
/*0a10*/ FSETP.NEU.FTZ.AND P2, PT, |R10|.reuse, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x040fe40003f5d200 */
/*0a20*/ FSETP.NEU.FTZ.AND P1, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fe40003f3d200 */
/*0a30*/ FSETP.NEU.FTZ.AND P0, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fd60003f1d200 */
/*0a40*/ @!P1 BRA !P2, 0xee0 ; /* 0x0000049000009947 */
/* 0x000fea0005000000 */
/*0a50*/ LOP3.LUT P2, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fc8000784c0ff */
/*0a60*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0a70*/ @P1 BRA 0xec0 ; /* 0x0000044000001947 */
/* 0x000fea0003800000 */
/*0a80*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*0a90*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0aa0*/ @P0 BRA 0xe90 ; /* 0x000003e000000947 */
/* 0x000fea0003800000 */
/*0ab0*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f06270 */
/*0ac0*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*0ad0*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*0ae0*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*0af0*/ @!P0 FFMA R5, R10, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000a058823 */
/* 0x000fe400000000ff */
/*0b00*/ @!P1 FFMA R8, R13, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000d089823 */
/* 0x000fe200000000ff */
/*0b10*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*0b20*/ LEA R11, R4, 0xc0800000, 0x17 ; /* 0xc0800000040b7811 */
/* 0x000fca00078eb8ff */
/*0b30*/ IMAD.IADD R11, R8, 0x1, -R11 ; /* 0x00000001080b7824 */
/* 0x000fe200078e0a0b */
/*0b40*/ IADD3 R8, R3, -0x7f, RZ ; /* 0xffffff8103087810 */
/* 0x000fc60007ffe0ff */
/*0b50*/ MUFU.RCP R10, R11 ; /* 0x0000000b000a7308 */
/* 0x000e220000001000 */
/*0b60*/ FADD.FTZ R12, -R11, -RZ ; /* 0x800000ff0b0c7221 */
/* 0x000fe40000010100 */
/*0b70*/ IMAD R5, R8.reuse, -0x800000, R5 ; /* 0xff80000008057824 */
/* 0x040fe200078e0205 */
/*0b80*/ IADD3 R8, R8, 0x7f, -R4 ; /* 0x0000007f08087810 */
/* 0x000fca0007ffe804 */
/*0b90*/ IMAD.IADD R8, R8, 0x1, R9 ; /* 0x0000000108087824 */
/* 0x000fe400078e0209 */
/*0ba0*/ FFMA R3, R10, R12, 1 ; /* 0x3f8000000a037423 */
/* 0x001fc8000000000c */
/*0bb0*/ FFMA R14, R10, R3, R10 ; /* 0x000000030a0e7223 */
/* 0x000fc8000000000a */
/*0bc0*/ FFMA R3, R5, R14, RZ ; /* 0x0000000e05037223 */
/* 0x000fc800000000ff */
/*0bd0*/ FFMA R10, R12, R3, R5 ; /* 0x000000030c0a7223 */
/* 0x000fc80000000005 */
/*0be0*/ FFMA R13, R14, R10, R3 ; /* 0x0000000a0e0d7223 */
/* 0x000fc80000000003 */
/*0bf0*/ FFMA R5, R12, R13, R5 ; /* 0x0000000d0c057223 */
/* 0x000fc80000000005 */
/*0c00*/ FFMA R3, R14, R5, R13 ; /* 0x000000050e037223 */
/* 0x000fca000000000d */
/*0c10*/ SHF.R.U32.HI R4, RZ, 0x17, R3 ; /* 0x00000017ff047819 */
/* 0x000fc80000011603 */
/*0c20*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fca00078ec0ff */
/*0c30*/ IMAD.IADD R10, R4, 0x1, R8 ; /* 0x00000001040a7824 */
/* 0x000fca00078e0208 */
/*0c40*/ IADD3 R4, R10, -0x1, RZ ; /* 0xffffffff0a047810 */
/* 0x000fc80007ffe0ff */
/*0c50*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*0c60*/ @!P0 BRA 0xe70 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0c70*/ ISETP.GT.AND P0, PT, R10, 0xfe, PT ; /* 0x000000fe0a00780c */
/* 0x000fda0003f04270 */
/*0c80*/ @P0 BRA 0xe40 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0c90*/ ISETP.GE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fda0003f06270 */
/*0ca0*/ @P0 BRA 0xf10 ; /* 0x0000026000000947 */
/* 0x000fea0003800000 */
/*0cb0*/ ISETP.GE.AND P0, PT, R10, -0x18, PT ; /* 0xffffffe80a00780c */
/* 0x000fe40003f06270 */
/*0cc0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*0cd0*/ @!P0 BRA 0xf10 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*0ce0*/ FFMA.RZ R4, R14, R5.reuse, R13.reuse ; /* 0x000000050e047223 */
/* 0x180fe2000000c00d */
/*0cf0*/ IADD3 R9, R10.reuse, 0x20, RZ ; /* 0x000000200a097810 */
/* 0x040fe40007ffe0ff */
/*0d00*/ ISETP.NE.AND P2, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f45270 */
/*0d10*/ LOP3.LUT R8, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04087812 */
/* 0x000fe200078ec0ff */
/*0d20*/ FFMA.RP R4, R14, R5.reuse, R13.reuse ; /* 0x000000050e047223 */
/* 0x180fe2000000800d */
/*0d30*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f25270 */
/*0d40*/ FFMA.RM R5, R14, R5, R13 ; /* 0x000000050e057223 */
/* 0x000fe2000000400d */
/*0d50*/ LOP3.LUT R8, R8, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000008087812 */
/* 0x000fe200078efcff */
/*0d60*/ IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0a7224 */
/* 0x000fc600078e0a0a */
/*0d70*/ SHF.L.U32 R9, R8, R9, RZ ; /* 0x0000000908097219 */
/* 0x000fe400000006ff */
/*0d80*/ FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fe40003f1d000 */
/*0d90*/ SEL R5, R10, RZ, P2 ; /* 0x000000ff0a057207 */
/* 0x000fe40001000000 */
/*0da0*/ ISETP.NE.AND P1, PT, R9, RZ, P1 ; /* 0x000000ff0900720c */
/* 0x000fe40000f25270 */
/*0db0*/ SHF.R.U32.HI R5, RZ, R5, R8 ; /* 0x00000005ff057219 */
/* 0x000fe40000011608 */
/*0dc0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0dd0*/ SHF.R.U32.HI R9, RZ, 0x1, R5 ; /* 0x00000001ff097819 */
/* 0x000fe40000011605 */
/*0de0*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0df0*/ LOP3.LUT R4, R4, 0x1, R9, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef809 */
/*0e00*/ LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ; /* 0x0000000504047212 */
/* 0x000fca00078ec0ff */
/*0e10*/ IMAD.IADD R4, R9, 0x1, R4 ; /* 0x0000000109047824 */
/* 0x000fca00078e0204 */
/*0e20*/ LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ; /* 0x0000000304037212 */
/* 0x000fe200078efcff */
/*0e30*/ BRA 0xf10 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*0e40*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*0e50*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0e60*/ BRA 0xf10 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*0e70*/ IMAD R3, R8, 0x800000, R3 ; /* 0x0080000008037824 */
/* 0x000fe200078e0203 */
/*0e80*/ BRA 0xf10 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0e90*/ LOP3.LUT R3, R8, 0x80000000, R5, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fc800078e4805 */
/*0ea0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0eb0*/ BRA 0xf10 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0ec0*/ LOP3.LUT R3, R8, 0x80000000, R5, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fe200078e4805 */
/*0ed0*/ BRA 0xf10 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0ee0*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*0ef0*/ BRA 0xf10 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0f00*/ FADD.FTZ R3, R10, c[0x0][0x18c] ; /* 0x000063000a037621 */
/* 0x000fc80000010000 */
/*0f10*/ IMAD.MOV.U32 R4, RZ, RZ, R3 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0003 */
/*0f20*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0f30*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff0c002007950 */
/* 0x000fea0003c3ffff */
/*0f40*/ BRA 0xf40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void check_for_generator_spikes_kernel(int *d_neuron_ids_for_stimulus, float *d_spike_times_for_stimulus, float* d_last_spike_time_of_each_neuron, unsigned char* d_bitarray_of_neuron_spikes, int bitarray_length, int bitarray_maximum_axonal_delay_in_timesteps, float current_time_in_seconds, float timestep, size_t number_of_spikes_in_stimulus, bool high_fidelity_spike_flag) {
// // Get thread IDs
int idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < number_of_spikes_in_stimulus) {
if (fabs(current_time_in_seconds - d_spike_times_for_stimulus[idx]) < 0.5 * timestep) {
__syncthreads();
d_last_spike_time_of_each_neuron[d_neuron_ids_for_stimulus[idx]] = current_time_in_seconds;
if (high_fidelity_spike_flag){
// Get start of the given neuron's bits
int neuron_id_spike_store_start = d_neuron_ids_for_stimulus[idx] * bitarray_length;
// Get offset depending upon the current timestep
int offset_index = (int)(round((float)(current_time_in_seconds / timestep))) % bitarray_maximum_axonal_delay_in_timesteps;
int offset_byte = offset_index / 8;
int offset_bit_pos = offset_index - (8 * offset_byte);
// Get the specific position at which we should be putting the current value
unsigned char byte = d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte];
// Set the specific bit in the byte to on
byte |= (1 << offset_bit_pos);
// Assign the byte
d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte] = byte;
}
} else {
// High fidelity spike storage
if (high_fidelity_spike_flag){
// Get start of the given neuron's bits
int neuron_id_spike_store_start = d_neuron_ids_for_stimulus[idx] * bitarray_length;
// Get offset depending upon the current timestep
int offset_index = (int)(round((float)(current_time_in_seconds / timestep))) % bitarray_maximum_axonal_delay_in_timesteps;
int offset_byte = offset_index / 8;
int offset_bit_pos = offset_index - (8 * offset_byte);
// Get the specific position at which we should be putting the current value
unsigned char byte = d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte];
// Set the specific bit in the byte to on
byte &= ~(1 << offset_bit_pos);
// Assign the byte
d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte] = byte;
}
}
idx += blockDim.x * gridDim.x;
}
__syncthreads();
} | .file "tmpxft_000ea904_00000000-6_check_for_generator_spikes_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z66__device_stub__Z33check_for_generator_spikes_kernelPiPfS0_PhiiffmbPiPfS0_Phiiffmb
.type _Z66__device_stub__Z33check_for_generator_spikes_kernelPiPfS0_PhiiffmbPiPfS0_Phiiffmb, @function
_Z66__device_stub__Z33check_for_generator_spikes_kernelPiPfS0_PhiiffmbPiPfS0_Phiiffmb:
.LFB2051:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movl %r8d, 28(%rsp)
movl %r9d, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movl 248(%rsp), %eax
movb %al, 12(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 28(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 20(%rsp), %rax
movq %rax, 176(%rsp)
leaq 16(%rsp), %rax
movq %rax, 184(%rsp)
leaq 240(%rsp), %rax
movq %rax, 192(%rsp)
leaq 12(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z66__device_stub__Z33check_for_generator_spikes_kernelPiPfS0_PhiiffmbPiPfS0_Phiiffmb, .-_Z66__device_stub__Z33check_for_generator_spikes_kernelPiPfS0_PhiiffmbPiPfS0_Phiiffmb
.globl _Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb
.type _Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb, @function
_Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z66__device_stub__Z33check_for_generator_spikes_kernelPiPfS0_PhiiffmbPiPfS0_Phiiffmb
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb, .-_Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void check_for_generator_spikes_kernel(int *d_neuron_ids_for_stimulus, float *d_spike_times_for_stimulus, float* d_last_spike_time_of_each_neuron, unsigned char* d_bitarray_of_neuron_spikes, int bitarray_length, int bitarray_maximum_axonal_delay_in_timesteps, float current_time_in_seconds, float timestep, size_t number_of_spikes_in_stimulus, bool high_fidelity_spike_flag) {
// // Get thread IDs
int idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < number_of_spikes_in_stimulus) {
if (fabs(current_time_in_seconds - d_spike_times_for_stimulus[idx]) < 0.5 * timestep) {
__syncthreads();
d_last_spike_time_of_each_neuron[d_neuron_ids_for_stimulus[idx]] = current_time_in_seconds;
if (high_fidelity_spike_flag){
// Get start of the given neuron's bits
int neuron_id_spike_store_start = d_neuron_ids_for_stimulus[idx] * bitarray_length;
// Get offset depending upon the current timestep
int offset_index = (int)(round((float)(current_time_in_seconds / timestep))) % bitarray_maximum_axonal_delay_in_timesteps;
int offset_byte = offset_index / 8;
int offset_bit_pos = offset_index - (8 * offset_byte);
// Get the specific position at which we should be putting the current value
unsigned char byte = d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte];
// Set the specific bit in the byte to on
byte |= (1 << offset_bit_pos);
// Assign the byte
d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte] = byte;
}
} else {
// High fidelity spike storage
if (high_fidelity_spike_flag){
// Get start of the given neuron's bits
int neuron_id_spike_store_start = d_neuron_ids_for_stimulus[idx] * bitarray_length;
// Get offset depending upon the current timestep
int offset_index = (int)(round((float)(current_time_in_seconds / timestep))) % bitarray_maximum_axonal_delay_in_timesteps;
int offset_byte = offset_index / 8;
int offset_bit_pos = offset_index - (8 * offset_byte);
// Get the specific position at which we should be putting the current value
unsigned char byte = d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte];
// Set the specific bit in the byte to on
byte &= ~(1 << offset_bit_pos);
// Assign the byte
d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte] = byte;
}
}
idx += blockDim.x * gridDim.x;
}
__syncthreads();
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void check_for_generator_spikes_kernel(int *d_neuron_ids_for_stimulus, float *d_spike_times_for_stimulus, float* d_last_spike_time_of_each_neuron, unsigned char* d_bitarray_of_neuron_spikes, int bitarray_length, int bitarray_maximum_axonal_delay_in_timesteps, float current_time_in_seconds, float timestep, size_t number_of_spikes_in_stimulus, bool high_fidelity_spike_flag) {
// // Get thread IDs
int idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < number_of_spikes_in_stimulus) {
if (fabs(current_time_in_seconds - d_spike_times_for_stimulus[idx]) < 0.5 * timestep) {
__syncthreads();
d_last_spike_time_of_each_neuron[d_neuron_ids_for_stimulus[idx]] = current_time_in_seconds;
if (high_fidelity_spike_flag){
// Get start of the given neuron's bits
int neuron_id_spike_store_start = d_neuron_ids_for_stimulus[idx] * bitarray_length;
// Get offset depending upon the current timestep
int offset_index = (int)(round((float)(current_time_in_seconds / timestep))) % bitarray_maximum_axonal_delay_in_timesteps;
int offset_byte = offset_index / 8;
int offset_bit_pos = offset_index - (8 * offset_byte);
// Get the specific position at which we should be putting the current value
unsigned char byte = d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte];
// Set the specific bit in the byte to on
byte |= (1 << offset_bit_pos);
// Assign the byte
d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte] = byte;
}
} else {
// High fidelity spike storage
if (high_fidelity_spike_flag){
// Get start of the given neuron's bits
int neuron_id_spike_store_start = d_neuron_ids_for_stimulus[idx] * bitarray_length;
// Get offset depending upon the current timestep
int offset_index = (int)(round((float)(current_time_in_seconds / timestep))) % bitarray_maximum_axonal_delay_in_timesteps;
int offset_byte = offset_index / 8;
int offset_bit_pos = offset_index - (8 * offset_byte);
// Get the specific position at which we should be putting the current value
unsigned char byte = d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte];
// Set the specific bit in the byte to on
byte &= ~(1 << offset_bit_pos);
// Assign the byte
d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte] = byte;
}
}
idx += blockDim.x * gridDim.x;
}
__syncthreads();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void check_for_generator_spikes_kernel(int *d_neuron_ids_for_stimulus, float *d_spike_times_for_stimulus, float* d_last_spike_time_of_each_neuron, unsigned char* d_bitarray_of_neuron_spikes, int bitarray_length, int bitarray_maximum_axonal_delay_in_timesteps, float current_time_in_seconds, float timestep, size_t number_of_spikes_in_stimulus, bool high_fidelity_spike_flag) {
// // Get thread IDs
int idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < number_of_spikes_in_stimulus) {
if (fabs(current_time_in_seconds - d_spike_times_for_stimulus[idx]) < 0.5 * timestep) {
__syncthreads();
d_last_spike_time_of_each_neuron[d_neuron_ids_for_stimulus[idx]] = current_time_in_seconds;
if (high_fidelity_spike_flag){
// Get start of the given neuron's bits
int neuron_id_spike_store_start = d_neuron_ids_for_stimulus[idx] * bitarray_length;
// Get offset depending upon the current timestep
int offset_index = (int)(round((float)(current_time_in_seconds / timestep))) % bitarray_maximum_axonal_delay_in_timesteps;
int offset_byte = offset_index / 8;
int offset_bit_pos = offset_index - (8 * offset_byte);
// Get the specific position at which we should be putting the current value
unsigned char byte = d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte];
// Set the specific bit in the byte to on
byte |= (1 << offset_bit_pos);
// Assign the byte
d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte] = byte;
}
} else {
// High fidelity spike storage
if (high_fidelity_spike_flag){
// Get start of the given neuron's bits
int neuron_id_spike_store_start = d_neuron_ids_for_stimulus[idx] * bitarray_length;
// Get offset depending upon the current timestep
int offset_index = (int)(round((float)(current_time_in_seconds / timestep))) % bitarray_maximum_axonal_delay_in_timesteps;
int offset_byte = offset_index / 8;
int offset_bit_pos = offset_index - (8 * offset_byte);
// Get the specific position at which we should be putting the current value
unsigned char byte = d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte];
// Set the specific bit in the byte to on
byte &= ~(1 << offset_bit_pos);
// Assign the byte
d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte] = byte;
}
}
idx += blockDim.x * gridDim.x;
}
__syncthreads();
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb
.globl _Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb
.p2align 8
.type _Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb,@function
_Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x4c
s_load_b64 s[12:13], s[0:1], 0x30
s_add_u32 s2, s0, 64
s_addc_u32 s3, s1, 0
s_mov_b32 s14, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s17, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, s15, s17, v[0:1]
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[12:13], v[5:6]
s_cbranch_execz .LBB0_9
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x20
s_load_b32 s4, s[0:1], 0x38
s_load_b32 s18, s[2:3], 0x0
s_mov_b32 s16, 0
s_waitcnt lgkmcnt(0)
v_div_scale_f32 v3, null, s11, s11, s10
v_div_scale_f32 v7, vcc_lo, s10, s11, s10
s_bitcmp1_b32 s4, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v1, -v3, v4, 1.0
v_fmac_f32_e32 v4, v1, v4
v_cvt_f64_f32_e32 v[1:2], s11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v8, v7, v4
v_fma_f32 v9, -v3, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, v9, v4
v_fma_f32 v3, -v3, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v3, v3, v4, v8
v_div_fixup_f32 v3, v3, s11, s10
s_cselect_b32 s11, -1, 0
s_ashr_i32 s2, s9, 31
s_add_i32 s15, s15, s18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_trunc_f32_e32 v4, v3
v_mul_f64 v[1:2], v[1:2], 0.5
v_sub_f32_e32 v7, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s3, |v7|, 0.5
v_cndmask_b32_e64 v7, 0, 1.0, s3
s_add_i32 s3, s9, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_xor_b32 s9, s3, s2
s_load_b256 s[0:7], s[0:1], 0x0
v_bfi_b32 v3, 0x7fffffff, v7, v3
v_cvt_f32_u32_e32 v7, s9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v3, v4, v3
v_rcp_iflag_f32_e32 v4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f32_e32 v3, v3
v_readfirstlane_b32 s19, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v7, 0x4f7ffffe, v4
v_mad_u64_u32 v[3:4], null, s15, s17, v[0:1]
s_ashr_i32 s15, s19, 31
s_delay_alu instid0(VALU_DEP_2)
v_cvt_u32_f32_e32 v0, v7
s_add_i32 s19, s19, s15
s_mul_i32 s17, s18, s17
s_xor_b32 s18, s19, s15
s_sub_i32 s19, 0, s9
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s20
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_cmp_le_u64_e32 vcc_lo, s[12:13], v[3:4]
v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
v_add_nc_u32_e32 v3, s17, v3
s_or_b32 s16, vcc_lo, s16
s_and_not1_b32 exec_lo, exec_lo, s16
s_cbranch_execz .LBB0_9
.LBB0_3:
v_lshlrev_b64 v[4:5], 2, v[5:6]
s_mov_b32 s20, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v5, vcc_lo
global_load_b32 v6, v[6:7], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v6, s10, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e64 v[6:7], |v6|
v_cmpx_ngt_f64_e32 v[1:2], v[6:7]
s_xor_b32 s20, exec_lo, s20
s_cbranch_execz .LBB0_6
s_and_not1_b32 vcc_lo, exec_lo, s11
s_cbranch_vccnz .LBB0_6
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
v_readfirstlane_b32 s21, v0
global_load_b32 v6, v[4:5], off
s_mul_i32 s22, s19, s21
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s22, s21, s22
s_add_i32 s21, s21, s22
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s21, s18, s21
s_mul_i32 s21, s21, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_sub_i32 s21, s18, s21
s_sub_i32 s22, s21, s9
s_cmp_ge_u32 s21, s9
s_cselect_b32 s21, s22, s21
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_sub_i32 s22, s21, s9
s_cmp_ge_u32 s21, s9
s_cselect_b32 s21, s22, s21
s_xor_b32 s21, s21, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_sub_i32 s21, s21, s15
s_ashr_i32 s22, s21, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshr_b32 s22, s22, 29
s_add_i32 s23, s21, s22
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_ashr_i32 s22, s23, 3
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[4:5], null, v6, s8, s[22:23]
s_and_b32 s22, s23, -8
s_sub_i32 s21, s21, s22
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b32 s21, 1, s21
v_xor_b32_e64 v7, s21, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
global_load_u8 v6, v[4:5], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v6, v6, v7
global_store_b8 v[4:5], v6, off
.LBB0_6:
s_and_not1_saveexec_b32 s20, s20
s_cbranch_execz .LBB0_2
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
global_load_b32 v4, v[4:5], off
v_mov_b32_e32 v7, s10
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[4:5]
v_add_co_u32 v5, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
s_and_not1_b32 vcc_lo, exec_lo, s11
global_store_b32 v[5:6], v7, off
s_cbranch_vccnz .LBB0_2
v_readfirstlane_b32 s21, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s22, s19, s21
s_mul_hi_u32 s22, s21, s22
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s21, s21, s22
s_mul_hi_u32 s21, s18, s21
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s21, s21, s9
s_sub_i32 s21, s18, s21
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_sub_i32 s22, s21, s9
s_cmp_ge_u32 s21, s9
s_cselect_b32 s21, s22, s21
s_sub_i32 s22, s21, s9
s_cmp_ge_u32 s21, s9
s_cselect_b32 s21, s22, s21
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s21, s21, s15
s_sub_i32 s21, s21, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s22, s21, 31
s_lshr_b32 s22, s22, 29
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s23, s21, s22
s_ashr_i32 s22, s23, 3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[5:6], null, v4, s8, s[22:23]
s_and_b32 s22, s23, -8
s_sub_i32 s21, s21, s22
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_lshl_b32 s21, 1, s21
v_ashrrev_i32_e32 v6, 31, v5
v_add_co_u32 v4, vcc_lo, s6, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v6, vcc_lo
global_load_u8 v6, v[4:5], off
s_waitcnt vmcnt(0)
v_or_b32_e32 v6, s21, v6
global_store_b8 v[4:5], v6, off
s_branch .LBB0_2
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb, .Lfunc_end0-_Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 8
.value_kind: by_value
- .offset: 56
.size: 1
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void check_for_generator_spikes_kernel(int *d_neuron_ids_for_stimulus, float *d_spike_times_for_stimulus, float* d_last_spike_time_of_each_neuron, unsigned char* d_bitarray_of_neuron_spikes, int bitarray_length, int bitarray_maximum_axonal_delay_in_timesteps, float current_time_in_seconds, float timestep, size_t number_of_spikes_in_stimulus, bool high_fidelity_spike_flag) {
// // Get thread IDs
int idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < number_of_spikes_in_stimulus) {
if (fabs(current_time_in_seconds - d_spike_times_for_stimulus[idx]) < 0.5 * timestep) {
__syncthreads();
d_last_spike_time_of_each_neuron[d_neuron_ids_for_stimulus[idx]] = current_time_in_seconds;
if (high_fidelity_spike_flag){
// Get start of the given neuron's bits
int neuron_id_spike_store_start = d_neuron_ids_for_stimulus[idx] * bitarray_length;
// Get offset depending upon the current timestep
int offset_index = (int)(round((float)(current_time_in_seconds / timestep))) % bitarray_maximum_axonal_delay_in_timesteps;
int offset_byte = offset_index / 8;
int offset_bit_pos = offset_index - (8 * offset_byte);
// Get the specific position at which we should be putting the current value
unsigned char byte = d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte];
// Set the specific bit in the byte to on
byte |= (1 << offset_bit_pos);
// Assign the byte
d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte] = byte;
}
} else {
// High fidelity spike storage
if (high_fidelity_spike_flag){
// Get start of the given neuron's bits
int neuron_id_spike_store_start = d_neuron_ids_for_stimulus[idx] * bitarray_length;
// Get offset depending upon the current timestep
int offset_index = (int)(round((float)(current_time_in_seconds / timestep))) % bitarray_maximum_axonal_delay_in_timesteps;
int offset_byte = offset_index / 8;
int offset_bit_pos = offset_index - (8 * offset_byte);
// Get the specific position at which we should be putting the current value
unsigned char byte = d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte];
// Set the specific bit in the byte to on
byte &= ~(1 << offset_bit_pos);
// Assign the byte
d_bitarray_of_neuron_spikes[neuron_id_spike_store_start + offset_byte] = byte;
}
}
idx += blockDim.x * gridDim.x;
}
__syncthreads();
} | .text
.file "check_for_generator_spikes_kernel.hip"
.globl _Z48__device_stub__check_for_generator_spikes_kernelPiPfS0_Phiiffmb # -- Begin function _Z48__device_stub__check_for_generator_spikes_kernelPiPfS0_Phiiffmb
.p2align 4, 0x90
.type _Z48__device_stub__check_for_generator_spikes_kernelPiPfS0_Phiiffmb,@function
_Z48__device_stub__check_for_generator_spikes_kernelPiPfS0_Phiiffmb: # @_Z48__device_stub__check_for_generator_spikes_kernelPiPfS0_Phiiffmb
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movzbl 216(%rsp), %eax
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r8d, 28(%rsp)
movl %r9d, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movb %al, 15(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 208(%rsp), %rax
movq %rax, 176(%rsp)
leaq 15(%rsp), %rax
movq %rax, 184(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size _Z48__device_stub__check_for_generator_spikes_kernelPiPfS0_Phiiffmb, .Lfunc_end0-_Z48__device_stub__check_for_generator_spikes_kernelPiPfS0_Phiiffmb
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb,@object # @_Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb
.section .rodata,"a",@progbits
.globl _Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb
.p2align 3, 0x0
_Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb:
.quad _Z48__device_stub__check_for_generator_spikes_kernelPiPfS0_Phiiffmb
.size _Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb"
.size .L__unnamed_1, 53
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z48__device_stub__check_for_generator_spikes_kernelPiPfS0_Phiiffmb
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ea904_00000000-6_check_for_generator_spikes_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z66__device_stub__Z33check_for_generator_spikes_kernelPiPfS0_PhiiffmbPiPfS0_Phiiffmb
.type _Z66__device_stub__Z33check_for_generator_spikes_kernelPiPfS0_PhiiffmbPiPfS0_Phiiffmb, @function
_Z66__device_stub__Z33check_for_generator_spikes_kernelPiPfS0_PhiiffmbPiPfS0_Phiiffmb:
.LFB2051:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movl %r8d, 28(%rsp)
movl %r9d, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movl 248(%rsp), %eax
movb %al, 12(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 28(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 20(%rsp), %rax
movq %rax, 176(%rsp)
leaq 16(%rsp), %rax
movq %rax, 184(%rsp)
leaq 240(%rsp), %rax
movq %rax, 192(%rsp)
leaq 12(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z66__device_stub__Z33check_for_generator_spikes_kernelPiPfS0_PhiiffmbPiPfS0_Phiiffmb, .-_Z66__device_stub__Z33check_for_generator_spikes_kernelPiPfS0_PhiiffmbPiPfS0_Phiiffmb
.globl _Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb
.type _Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb, @function
_Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z66__device_stub__Z33check_for_generator_spikes_kernelPiPfS0_PhiiffmbPiPfS0_Phiiffmb
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb, .-_Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "check_for_generator_spikes_kernel.hip"
.globl _Z48__device_stub__check_for_generator_spikes_kernelPiPfS0_Phiiffmb # -- Begin function _Z48__device_stub__check_for_generator_spikes_kernelPiPfS0_Phiiffmb
.p2align 4, 0x90
.type _Z48__device_stub__check_for_generator_spikes_kernelPiPfS0_Phiiffmb,@function
_Z48__device_stub__check_for_generator_spikes_kernelPiPfS0_Phiiffmb: # @_Z48__device_stub__check_for_generator_spikes_kernelPiPfS0_Phiiffmb
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movzbl 216(%rsp), %eax
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r8d, 28(%rsp)
movl %r9d, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movb %al, 15(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 208(%rsp), %rax
movq %rax, 176(%rsp)
leaq 15(%rsp), %rax
movq %rax, 184(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size _Z48__device_stub__check_for_generator_spikes_kernelPiPfS0_Phiiffmb, .Lfunc_end0-_Z48__device_stub__check_for_generator_spikes_kernelPiPfS0_Phiiffmb
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb,@object # @_Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb
.section .rodata,"a",@progbits
.globl _Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb
.p2align 3, 0x0
_Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb:
.quad _Z48__device_stub__check_for_generator_spikes_kernelPiPfS0_Phiiffmb
.size _Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb"
.size .L__unnamed_1, 53
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z48__device_stub__check_for_generator_spikes_kernelPiPfS0_Phiiffmb
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z33check_for_generator_spikes_kernelPiPfS0_Phiiffmb
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void DrawMaskedColorKernelNearestNeighbor(float *target, int targetWidth, int targetHeight, int inputX, int inputY, float *texture, int textureWidth, int textureHeight, int objectWidth, int objectHeight, float r, float g, float b ) // texture = mask
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
int targetPixels = targetWidth * targetHeight;
int texturePixels = textureWidth * textureHeight;
int objectPixels = objectWidth * objectHeight;
int idObjectRgb = id / objectPixels;
int idObjectPixel = (id - idObjectRgb * objectPixels); // same as (id % objectPixels), but the kernel runs 10% faster
int idObjectY = idObjectPixel / objectWidth;
int idObjectX = (idObjectPixel - idObjectY * objectWidth); // same as (id % textureWidth), but the kernel runs another 10% faster
if (idObjectRgb < 3) // 3 channels that we will write to
{
int targetRgb = idObjectRgb;
// the texture is in BGR format, we want RGB
switch (idObjectRgb)
{
case 0: // R
targetRgb = 2; // B
break;
case 2: // B
targetRgb = 0; // R
break;
}
// if the object pixel offset by inputX, inputY, lies inside the target
if (idObjectX + inputX < targetWidth &&
idObjectX + inputX >= 0 &&
idObjectY + inputY < targetHeight &&
idObjectY + inputY >= 0)
{
// nearest neighbor texture X,Y:
int textureX = textureWidth * idObjectX / objectWidth;
int textureY = textureHeight * idObjectY / objectHeight;
int textureId = textureY * textureWidth + textureX;
int tIndex = targetPixels * targetRgb + targetWidth * (idObjectY + inputY) + (idObjectX + inputX);
int aIndex = textureId + 3 * texturePixels; // the A component of the texture
float a = texture[aIndex];
if (a > 0) // mask allows color here
{
// apply this: target[tIndex] = target[tIndex] * (1.0f - a) + a * color;
target[tIndex] = target[tIndex] * (1.0f - a);
switch (idObjectRgb)
{
case 0:
target[tIndex] += a*r;
break;
case 1:
target[tIndex] += a*g;
break;
case 2:
default:
target[tIndex] += a*b;
break;
}
}
}
}
} | code for sm_80
Function : _Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff037624 */
/* 0x000fe200078e00ff */
/*0020*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e260000002600 */
/*0030*/ IMAD R3, R3, c[0x0][0x188], RZ ; /* 0x0000620003037a24 */
/* 0x000fe200078e02ff */
/*0040*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e280000002500 */
/*0050*/ IABS R11, R3 ; /* 0x00000003000b7213 */
/* 0x000fe20000000000 */
/*0060*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e660000002100 */
/*0070*/ I2F.RP R2, R11 ; /* 0x0000000b00027306 */
/* 0x000eb00000209400 */
/*0080*/ MUFU.RCP R2, R2 ; /* 0x0000000200027308 */
/* 0x004ea20000001000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], R7 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0207 */
/*00a0*/ IMAD R6, R0, c[0x0][0x0], R9 ; /* 0x0000000000067a24 */
/* 0x002fca00078e0209 */
/*00b0*/ IABS R0, R6 ; /* 0x0000000600007213 */
/* 0x000fe40000000000 */
/*00c0*/ IADD3 R4, R2, 0xffffffe, RZ ; /* 0x0ffffffe02047810 */
/* 0x004fe40007ffe0ff */
/*00d0*/ IABS R2, R3 ; /* 0x0000000300027213 */
/* 0x000fe40000000000 */
/*00e0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000066000021f000 */
/*00f0*/ IMAD.MOV R9, RZ, RZ, -R2 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0a02 */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fc400078e00ff */
/*0110*/ IMAD.MOV R8, RZ, RZ, -R5 ; /* 0x000000ffff087224 */
/* 0x002fc800078e0a05 */
/*0120*/ IMAD R7, R8, R11, RZ ; /* 0x0000000b08077224 */
/* 0x000fc800078e02ff */
/*0130*/ IMAD.HI.U32 R5, R5, R7, R4 ; /* 0x0000000705057227 */
/* 0x000fe200078e0004 */
/*0140*/ IABS R7, c[0x0][0x188] ; /* 0x0000620000077a13 */
/* 0x000fc60000000000 */
/*0150*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0000 */
/*0160*/ MOV R0, R7 ; /* 0x0000000700007202 */
/* 0x000fc60000000f00 */
/*0170*/ IMAD.HI.U32 R2, R5, R4, RZ ; /* 0x0000000405027227 */
/* 0x000fe200078e00ff */
/*0180*/ I2F.RP R7, R0 ; /* 0x0000000000077306 */
/* 0x000e260000209400 */
/*0190*/ IMAD R4, R2, R9, R4 ; /* 0x0000000902047224 */
/* 0x000fca00078e0204 */
/*01a0*/ ISETP.GT.U32.AND P1, PT, R11, R4, PT ; /* 0x000000040b00720c */
/* 0x000fe20003f24070 */
/*01b0*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e180000001000 */
/*01c0*/ @!P1 IMAD.IADD R4, R4, 0x1, -R11 ; /* 0x0000000104049824 */
/* 0x000fe200078e0a0b */
/*01d0*/ @!P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102029810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f25270 */
/*01f0*/ ISETP.GE.U32.AND P0, PT, R4, R11, PT ; /* 0x0000000b0400720c */
/* 0x000fe40003f06070 */
/*0200*/ LOP3.LUT R4, R6, R3, RZ, 0x3c, !PT ; /* 0x0000000306047212 */
/* 0x000fc800078e3cff */
/*0210*/ ISETP.GE.AND P2, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f46270 */
/*0220*/ IADD3 R4, R7, 0xffffffe, RZ ; /* 0x0ffffffe07047810 */
/* 0x001fc80007ffe0ff */
/*0230*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000062000021f000 */
/*0240*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fcc0007ffe0ff */
/*0250*/ @!P2 IMAD.MOV R2, RZ, RZ, -R2 ; /* 0x000000ffff02a224 */
/* 0x000fe200078e0a02 */
/*0260*/ @!P1 LOP3.LUT R2, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff029212 */
/* 0x000fe200078e33ff */
/*0270*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*0280*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x188], PT ; /* 0x00006200ff007a0c */
/* 0x000fc60003f45270 */
/*0290*/ IMAD.MOV R7, RZ, RZ, -R2 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0a02 */
/*02a0*/ IMAD.MOV R9, RZ, RZ, -R5 ; /* 0x000000ffff097224 */
/* 0x002fe400078e0a05 */
/*02b0*/ IMAD R8, R3, R7, R6 ; /* 0x0000000703087224 */
/* 0x000fe200078e0206 */
/*02c0*/ LOP3.LUT R6, RZ, c[0x0][0x188], RZ, 0x33, !PT ; /* 0x00006200ff067a12 */
/* 0x000fe200078e33ff */
/*02d0*/ IMAD R7, R9, R0, RZ ; /* 0x0000000009077224 */
/* 0x000fc600078e02ff */
/*02e0*/ IABS R3, R8 ; /* 0x0000000800037213 */
/* 0x000fe20000000000 */
/*02f0*/ IMAD.HI.U32 R7, R5, R7, R4 ; /* 0x0000000705077227 */
/* 0x000fc800078e0004 */
/*0300*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0003 */
/*0310*/ IMAD.HI.U32 R3, R7, R5, RZ ; /* 0x0000000507037227 */
/* 0x000fc800078e00ff */
/*0320*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a03 */
/*0330*/ IMAD R5, R0, R4, R5 ; /* 0x0000000400057224 */
/* 0x000fe200078e0205 */
/*0340*/ LOP3.LUT R4, R8, c[0x0][0x188], RZ, 0x3c, !PT ; /* 0x0000620008047a12 */
/* 0x000fc800078e3cff */
/*0350*/ ISETP.GT.U32.AND P1, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fe40003f24070 */
/*0360*/ ISETP.GE.AND P3, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fd60003f66270 */
/*0370*/ @!P1 IMAD.IADD R5, R5, 0x1, -R0 ; /* 0x0000000105059824 */
/* 0x000fe200078e0a00 */
/*0380*/ @!P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103039810 */
/* 0x000fc80007ffe0ff */
/*0390*/ ISETP.GE.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f06070 */
/*03a0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe40007ffe0ff */
/*03b0*/ ISETP.GT.AND P0, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fc60003f04270 */
/*03c0*/ @!P3 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff03b224 */
/* 0x000fca00078e0a03 */
/*03d0*/ SEL R12, R6, R3, !P2 ; /* 0x00000003060c7207 */
/* 0x000fc80005000000 */
/*03e0*/ IADD3 R3, -R12, RZ, RZ ; /* 0x000000ff0c037210 */
/* 0x000fca0007ffe1ff */
/*03f0*/ IMAD R11, R3, c[0x0][0x188], R8 ; /* 0x00006200030b7a24 */
/* 0x000fe200078e0208 */
/*0400*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fec0003800000 */
/*0410*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f25270 */
/*0420*/ BSSY B0, 0x4c0 ; /* 0x0000009000007945 */
/* 0x000fe20003800000 */
/*0430*/ IADD3 R3, R11, c[0x0][0x170], RZ ; /* 0x00005c000b037a10 */
/* 0x000fe20007ffe0ff */
/*0440*/ IMAD.MOV.U32 R5, RZ, RZ, 0x2 ; /* 0x00000002ff057424 */
/* 0x000fc600078e00ff */
/*0450*/ ISETP.GE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fc80003f06270 */
/*0460*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x168], !P0 ; /* 0x00005a0003007a0c */
/* 0x000fc60004706670 */
/*0470*/ @!P1 BRA 0x4b0 ; /* 0x0000003000009947 */
/* 0x000fea0003800000 */
/*0480*/ ISETP.NE.AND P3, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fda0003f65270 */
/*0490*/ @!P3 IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff05b224 */
/* 0x000fe400078e00ff */
/*04a0*/ @P3 IMAD.MOV.U32 R5, RZ, RZ, R2 ; /* 0x000000ffff053224 */
/* 0x000fe400078e0002 */
/*04b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*04d0*/ IADD3 R4, R12, c[0x0][0x174], RZ ; /* 0x00005d000c047a10 */
/* 0x000fc80007ffe0ff */
/*04e0*/ ISETP.GE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc80003f06270 */
/*04f0*/ ISETP.GE.OR P0, PT, R4, c[0x0][0x16c], !P0 ; /* 0x00005b0004007a0c */
/* 0x000fda0004706670 */
/*0500*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0510*/ IABS R10, c[0x0][0x18c] ; /* 0x00006300000a7a13 */
/* 0x000fe20000000000 */
/*0520*/ IMAD R11, R11, c[0x0][0x180], RZ ; /* 0x000060000b0b7a24 */
/* 0x000fe200078e02ff */
/*0530*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0540*/ IMAD R12, R12, c[0x0][0x184], RZ ; /* 0x000061000c0c7a24 */
/* 0x000fe200078e02ff */
/*0550*/ I2F.RP R13, R10 ; /* 0x0000000a000d7306 */
/* 0x000e240000209400 */
/*0560*/ IABS R14, R11 ; /* 0x0000000b000e7213 */
/* 0x000fe40000000000 */
/*0570*/ LOP3.LUT R11, R11, c[0x0][0x188], RZ, 0x3c, !PT ; /* 0x000062000b0b7a12 */
/* 0x000fc600078e3cff */
/*0580*/ IMAD.HI.U32 R7, R7, R14, RZ ; /* 0x0000000e07077227 */
/* 0x000fe200078e00ff */
/*0590*/ MUFU.RCP R13, R13 ; /* 0x0000000d000d7308 */
/* 0x001e240000001000 */
/*05a0*/ IADD3 R8, R13, 0xffffffe, RZ ; /* 0x0ffffffe0d087810 */
/* 0x001fe40007ffe0ff */
/*05b0*/ IABS R13, R12 ; /* 0x0000000c000d7213 */
/* 0x000fc80000000000 */
/*05c0*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000062000021f000 */
/*05d0*/ LOP3.LUT R12, R12, c[0x0][0x18c], RZ, 0x3c, !PT ; /* 0x000063000c0c7a12 */
/* 0x000fc800078e3cff */
/*05e0*/ ISETP.GE.AND P3, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f66270 */
/*05f0*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x001fe20000000f00 */
/*0600*/ IMAD.MOV R15, RZ, RZ, -R9 ; /* 0x000000ffff0f7224 */
/* 0x002fc800078e0a09 */
/*0610*/ IMAD R15, R15, R10, RZ ; /* 0x0000000a0f0f7224 */
/* 0x000fc800078e02ff */
/*0620*/ IMAD.HI.U32 R9, R9, R15, R8 ; /* 0x0000000f09097227 */
/* 0x000fcc00078e0008 */
/*0630*/ IMAD.HI.U32 R8, R9, R13, RZ ; /* 0x0000000d09087227 */
/* 0x000fc800078e00ff */
/*0640*/ IMAD.MOV R9, RZ, RZ, -R7 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0a07 */
/*0650*/ IMAD.MOV R15, RZ, RZ, -R8 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e0a08 */
/*0660*/ IMAD R9, R0, R9, R14 ; /* 0x0000000900097224 */
/* 0x000fe400078e020e */
/*0670*/ IMAD R13, R10, R15, R13 ; /* 0x0000000f0a0d7224 */
/* 0x000fc600078e020d */
/*0680*/ ISETP.GT.U32.AND P5, PT, R0, R9, PT ; /* 0x000000090000720c */
/* 0x000fe40003fa4070 */
/*0690*/ ISETP.GT.U32.AND P6, PT, R10, R13, PT ; /* 0x0000000d0a00720c */
/* 0x000fd60003fc4070 */
/*06a0*/ @!P5 IMAD.IADD R9, R9, 0x1, -R0 ; /* 0x000000010909d824 */
/* 0x000fe200078e0a00 */
/*06b0*/ @!P5 IADD3 R7, R7, 0x1, RZ ; /* 0x000000010707d810 */
/* 0x000fe20007ffe0ff */
/*06c0*/ @!P6 IMAD.IADD R13, R13, 0x1, -R10 ; /* 0x000000010d0de824 */
/* 0x000fe200078e0a0a */
/*06d0*/ @!P6 IADD3 R8, R8, 0x1, RZ ; /* 0x000000010808e810 */
/* 0x000fe40007ffe0ff */
/*06e0*/ ISETP.GE.U32.AND P4, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fe20003f86070 */
/*06f0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff097624 */
/* 0x000fe200078e00ff */
/*0700*/ ISETP.GE.U32.AND P0, PT, R13, R10, PT ; /* 0x0000000a0d00720c */
/* 0x000fe40003f06070 */
/*0710*/ ISETP.GE.AND P6, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003fc6270 */
/*0720*/ ISETP.NE.AND P5, PT, RZ, c[0x0][0x18c], PT ; /* 0x00006300ff007a0c */
/* 0x000fce0003fa5270 */
/*0730*/ @P4 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107074810 */
/* 0x000fe40007ffe0ff */
/*0740*/ @P0 IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108080810 */
/* 0x000fc60007ffe0ff */
/*0750*/ @!P6 IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff07e224 */
/* 0x000fe200078e0a07 */
/*0760*/ @!P3 IADD3 R8, -R8, RZ, RZ ; /* 0x000000ff0808b210 */
/* 0x000fe40007ffe1ff */
/*0770*/ @!P5 LOP3.LUT R8, RZ, c[0x0][0x18c], RZ, 0x33, !PT ; /* 0x00006300ff08da12 */
/* 0x000fe400078e33ff */
/*0780*/ SEL R7, R6, R7, !P2 ; /* 0x0000000706077207 */
/* 0x000fc60005000000 */
/*0790*/ IMAD R8, R9, 0x3, R8 ; /* 0x0000000309087824 */
/* 0x000fe400078e0208 */
/*07a0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe400078e00ff */
/*07b0*/ IMAD R6, R8, c[0x0][0x180], R7 ; /* 0x0000600008067a24 */
/* 0x000fc800078e0207 */
/*07c0*/ IMAD.WIDE R6, R6, R9, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fcc00078e0209 */
/*07d0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*07e0*/ IMAD R4, R5, c[0x0][0x16c], R4 ; /* 0x00005b0005047a24 */
/* 0x000fc800078e0204 */
/*07f0*/ IMAD R4, R4, c[0x0][0x168], R3 ; /* 0x00005a0004047a24 */
/* 0x000fe200078e0203 */
/*0800*/ FSETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720b */
/* 0x004fda0003f04000 */
/*0810*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0820*/ IMAD.WIDE R4, R4, R9, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0209 */
/*0830*/ LDG.E R3, [R4.64] ; /* 0x0000000404037981 */
/* 0x000ea2000c1e1900 */
/*0840*/ FADD R0, -R6, 1 ; /* 0x3f80000006007421 */
/* 0x000fc80000000100 */
/*0850*/ FMUL R7, R0, R3 ; /* 0x0000000300077220 */
/* 0x004fca0000400000 */
/*0860*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e2000c101904 */
/*0870*/ @!P1 BRA 0x8f0 ; /* 0x0000007000009947 */
/* 0x000fea0003800000 */
/*0880*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f05270 */
/*0890*/ @!P0 FFMA R3, R6, c[0x0][0x194], R7 ; /* 0x0000650006038a23 */
/* 0x000fca0000000007 */
/*08a0*/ @!P0 STG.E [R4.64], R3 ; /* 0x0000000304008986 */
/* 0x0003e2000c101904 */
/*08b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*08c0*/ FFMA R3, R6, c[0x0][0x198], R7 ; /* 0x0000660006037a23 */
/* 0x002fca0000000007 */
/*08d0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x000fe2000c101904 */
/*08e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08f0*/ FFMA R3, R6, c[0x0][0x190], R7 ; /* 0x0000640006037a23 */
/* 0x000fca0000000007 */
/*0900*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x000fe2000c101904 */
/*0910*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0920*/ BRA 0x920; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void DrawMaskedColorKernelNearestNeighbor(float *target, int targetWidth, int targetHeight, int inputX, int inputY, float *texture, int textureWidth, int textureHeight, int objectWidth, int objectHeight, float r, float g, float b ) // texture = mask
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
int targetPixels = targetWidth * targetHeight;
int texturePixels = textureWidth * textureHeight;
int objectPixels = objectWidth * objectHeight;
int idObjectRgb = id / objectPixels;
int idObjectPixel = (id - idObjectRgb * objectPixels); // same as (id % objectPixels), but the kernel runs 10% faster
int idObjectY = idObjectPixel / objectWidth;
int idObjectX = (idObjectPixel - idObjectY * objectWidth); // same as (id % textureWidth), but the kernel runs another 10% faster
if (idObjectRgb < 3) // 3 channels that we will write to
{
int targetRgb = idObjectRgb;
// the texture is in BGR format, we want RGB
switch (idObjectRgb)
{
case 0: // R
targetRgb = 2; // B
break;
case 2: // B
targetRgb = 0; // R
break;
}
// if the object pixel offset by inputX, inputY, lies inside the target
if (idObjectX + inputX < targetWidth &&
idObjectX + inputX >= 0 &&
idObjectY + inputY < targetHeight &&
idObjectY + inputY >= 0)
{
// nearest neighbor texture X,Y:
int textureX = textureWidth * idObjectX / objectWidth;
int textureY = textureHeight * idObjectY / objectHeight;
int textureId = textureY * textureWidth + textureX;
int tIndex = targetPixels * targetRgb + targetWidth * (idObjectY + inputY) + (idObjectX + inputX);
int aIndex = textureId + 3 * texturePixels; // the A component of the texture
float a = texture[aIndex];
if (a > 0) // mask allows color here
{
// apply this: target[tIndex] = target[tIndex] * (1.0f - a) + a * color;
target[tIndex] = target[tIndex] * (1.0f - a);
switch (idObjectRgb)
{
case 0:
target[tIndex] += a*r;
break;
case 1:
target[tIndex] += a*g;
break;
case 2:
default:
target[tIndex] += a*b;
break;
}
}
}
}
} | .file "tmpxft_0006f5e1_00000000-6_DrawMaskedColorKernelNearestNeighbor.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z69__device_stub__Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifffPfiiiiS_iiiifff
.type _Z69__device_stub__Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifffPfiiiiS_iiiifff, @function
_Z69__device_stub__Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifffPfiiiiS_iiiifff:
.LFB2051:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movl %ecx, 28(%rsp)
movl %r8d, 24(%rsp)
movq %r9, 16(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 264(%rsp), %rax
movq %rax, 184(%rsp)
leaq 12(%rsp), %rax
movq %rax, 192(%rsp)
leaq 8(%rsp), %rax
movq %rax, 200(%rsp)
leaq 4(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 248
pushq 56(%rsp)
.cfi_def_cfa_offset 256
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z69__device_stub__Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifffPfiiiiS_iiiifff, .-_Z69__device_stub__Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifffPfiiiiS_iiiifff
.globl _Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff
.type _Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff, @function
_Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z69__device_stub__Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifffPfiiiiS_iiiifff
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff, .-_Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void DrawMaskedColorKernelNearestNeighbor(float *target, int targetWidth, int targetHeight, int inputX, int inputY, float *texture, int textureWidth, int textureHeight, int objectWidth, int objectHeight, float r, float g, float b ) // texture = mask
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
int targetPixels = targetWidth * targetHeight;
int texturePixels = textureWidth * textureHeight;
int objectPixels = objectWidth * objectHeight;
int idObjectRgb = id / objectPixels;
int idObjectPixel = (id - idObjectRgb * objectPixels); // same as (id % objectPixels), but the kernel runs 10% faster
int idObjectY = idObjectPixel / objectWidth;
int idObjectX = (idObjectPixel - idObjectY * objectWidth); // same as (id % textureWidth), but the kernel runs another 10% faster
if (idObjectRgb < 3) // 3 channels that we will write to
{
int targetRgb = idObjectRgb;
// the texture is in BGR format, we want RGB
switch (idObjectRgb)
{
case 0: // R
targetRgb = 2; // B
break;
case 2: // B
targetRgb = 0; // R
break;
}
// if the object pixel offset by inputX, inputY, lies inside the target
if (idObjectX + inputX < targetWidth &&
idObjectX + inputX >= 0 &&
idObjectY + inputY < targetHeight &&
idObjectY + inputY >= 0)
{
// nearest neighbor texture X,Y:
int textureX = textureWidth * idObjectX / objectWidth;
int textureY = textureHeight * idObjectY / objectHeight;
int textureId = textureY * textureWidth + textureX;
int tIndex = targetPixels * targetRgb + targetWidth * (idObjectY + inputY) + (idObjectX + inputX);
int aIndex = textureId + 3 * texturePixels; // the A component of the texture
float a = texture[aIndex];
if (a > 0) // mask allows color here
{
// apply this: target[tIndex] = target[tIndex] * (1.0f - a) + a * color;
target[tIndex] = target[tIndex] * (1.0f - a);
switch (idObjectRgb)
{
case 0:
target[tIndex] += a*r;
break;
case 1:
target[tIndex] += a*g;
break;
case 2:
default:
target[tIndex] += a*b;
break;
}
}
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void DrawMaskedColorKernelNearestNeighbor(float *target, int targetWidth, int targetHeight, int inputX, int inputY, float *texture, int textureWidth, int textureHeight, int objectWidth, int objectHeight, float r, float g, float b ) // texture = mask
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
int targetPixels = targetWidth * targetHeight;
int texturePixels = textureWidth * textureHeight;
int objectPixels = objectWidth * objectHeight;
int idObjectRgb = id / objectPixels;
int idObjectPixel = (id - idObjectRgb * objectPixels); // same as (id % objectPixels), but the kernel runs 10% faster
int idObjectY = idObjectPixel / objectWidth;
int idObjectX = (idObjectPixel - idObjectY * objectWidth); // same as (id % textureWidth), but the kernel runs another 10% faster
if (idObjectRgb < 3) // 3 channels that we will write to
{
int targetRgb = idObjectRgb;
// the texture is in BGR format, we want RGB
switch (idObjectRgb)
{
case 0: // R
targetRgb = 2; // B
break;
case 2: // B
targetRgb = 0; // R
break;
}
// if the object pixel offset by inputX, inputY, lies inside the target
if (idObjectX + inputX < targetWidth &&
idObjectX + inputX >= 0 &&
idObjectY + inputY < targetHeight &&
idObjectY + inputY >= 0)
{
// nearest neighbor texture X,Y:
int textureX = textureWidth * idObjectX / objectWidth;
int textureY = textureHeight * idObjectY / objectHeight;
int textureId = textureY * textureWidth + textureX;
int tIndex = targetPixels * targetRgb + targetWidth * (idObjectY + inputY) + (idObjectX + inputX);
int aIndex = textureId + 3 * texturePixels; // the A component of the texture
float a = texture[aIndex];
if (a > 0) // mask allows color here
{
// apply this: target[tIndex] = target[tIndex] * (1.0f - a) + a * color;
target[tIndex] = target[tIndex] * (1.0f - a);
switch (idObjectRgb)
{
case 0:
target[tIndex] += a*r;
break;
case 1:
target[tIndex] += a*g;
break;
case 2:
default:
target[tIndex] += a*b;
break;
}
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void DrawMaskedColorKernelNearestNeighbor(float *target, int targetWidth, int targetHeight, int inputX, int inputY, float *texture, int textureWidth, int textureHeight, int objectWidth, int objectHeight, float r, float g, float b ) // texture = mask
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
int targetPixels = targetWidth * targetHeight;
int texturePixels = textureWidth * textureHeight;
int objectPixels = objectWidth * objectHeight;
int idObjectRgb = id / objectPixels;
int idObjectPixel = (id - idObjectRgb * objectPixels); // same as (id % objectPixels), but the kernel runs 10% faster
int idObjectY = idObjectPixel / objectWidth;
int idObjectX = (idObjectPixel - idObjectY * objectWidth); // same as (id % textureWidth), but the kernel runs another 10% faster
if (idObjectRgb < 3) // 3 channels that we will write to
{
int targetRgb = idObjectRgb;
// the texture is in BGR format, we want RGB
switch (idObjectRgb)
{
case 0: // R
targetRgb = 2; // B
break;
case 2: // B
targetRgb = 0; // R
break;
}
// if the object pixel offset by inputX, inputY, lies inside the target
if (idObjectX + inputX < targetWidth &&
idObjectX + inputX >= 0 &&
idObjectY + inputY < targetHeight &&
idObjectY + inputY >= 0)
{
// nearest neighbor texture X,Y:
int textureX = textureWidth * idObjectX / objectWidth;
int textureY = textureHeight * idObjectY / objectHeight;
int textureId = textureY * textureWidth + textureX;
int tIndex = targetPixels * targetRgb + targetWidth * (idObjectY + inputY) + (idObjectX + inputX);
int aIndex = textureId + 3 * texturePixels; // the A component of the texture
float a = texture[aIndex];
if (a > 0) // mask allows color here
{
// apply this: target[tIndex] = target[tIndex] * (1.0f - a) + a * color;
target[tIndex] = target[tIndex] * (1.0f - a);
switch (idObjectRgb)
{
case 0:
target[tIndex] += a*r;
break;
case 1:
target[tIndex] += a*g;
break;
case 2:
default:
target[tIndex] += a*b;
break;
}
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff
.globl _Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff
.p2align 8
.type _Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff,@function
_Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff:
s_clause 0x2
s_load_b64 s[8:9], s[0:1], 0x28
s_load_b32 s2, s[0:1], 0x40
s_load_b32 s3, s[0:1], 0x4c
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s9, s8
s_mul_i32 s2, s2, s15
s_ashr_i32 s5, s4, 31
s_and_b32 s3, s3, 0xffff
s_add_i32 s6, s4, s5
s_add_i32 s2, s2, s14
s_xor_b32 s6, s6, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s6
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1)
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_sub_i32 s2, 0, s6
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s2, v3
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v2
v_xor_b32_e32 v4, v4, v2
v_xor_b32_e32 v2, s5, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v3, v0
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v0, s6
v_sub_nc_u32_e32 v3, v4, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s6, v3
v_cmp_le_u32_e32 vcc_lo, s6, v3
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s6, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v0, v2
v_cmpx_gt_i32_e32 3, v2
s_cbranch_execz .LBB0_19
s_ashr_i32 s2, s8, 31
v_mul_lo_u32 v3, v2, s4
s_add_i32 s3, s8, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s3, s3, s2
v_cvt_f32_u32_e32 v0, s3
s_sub_i32 s4, 0, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v4, v1, v3
v_rcp_iflag_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v0, 0x4f7ffffe, v0 :: v_dual_add_nc_u32 v3, v4, v5
v_xor_b32_e32 v6, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v1, s4, v0
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v1, v0, v1
v_add_nc_u32_e32 v3, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v6, v3, 0
v_cmpx_lt_i32_e32 1, v2
s_xor_b32 s4, exec_lo, s4
s_mov_b32 s5, 0
s_or_saveexec_b32 s4, s4
v_mov_b32_e32 v3, s5
s_xor_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v3, v2
s_mov_b32 s5, exec_lo
v_cmpx_eq_u32_e32 0, v2
v_mov_b32_e32 v3, 2
s_or_b32 exec_lo, exec_lo, s5
.LBB0_7:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s4
v_mul_lo_u32 v0, v1, s3
v_xor_b32_e32 v5, s2, v5
s_load_b32 s2, s[0:1], 0x10
v_sub_nc_u32_e32 v0, v6, v0
v_add_nc_u32_e32 v6, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v7, s3, v0
v_cmp_le_u32_e32 vcc_lo, s3, v0
v_dual_cndmask_b32 v1, v1, v6 :: v_dual_cndmask_b32 v0, v0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, 1, v1
v_cmp_le_u32_e32 vcc_lo, s3, v0
s_load_b32 s3, s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v1, v6, vcc_lo
v_xor_b32_e32 v0, v0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v0, v5
v_mul_lo_u32 v0, v5, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v4, v0
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, s2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v0
v_cmp_lt_i32_e64 s2, -1, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_19
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b32 s10, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, s2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s10, v1
v_cmp_lt_i32_e64 s2, -1, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_19
s_ashr_i32 s2, s9, 31
s_ashr_i32 s11, s8, 31
s_add_i32 s4, s9, s2
s_add_i32 s8, s8, s11
s_xor_b32 s9, s4, s2
s_xor_b32 s8, s8, s11
v_cvt_f32_u32_e32 v6, s9
v_cvt_f32_u32_e32 v7, s8
s_load_b128 s[4:7], s[0:1], 0x18
s_sub_i32 s12, 0, s9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v6, v6
v_rcp_iflag_f32_e32 v7, v7
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v6, 0x4f7ffffe, v6 :: v_dual_mul_f32 v7, 0x4f7ffffe, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v6, v6
v_cvt_u32_f32_e32 v7, v7
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v4, v4, s6
v_mul_lo_u32 v5, v5, s7
v_mul_lo_u32 v8, s12, v6
s_sub_i32 s12, 0, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_lo_u32 v10, s12, v7
v_ashrrev_i32_e32 v11, 31, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v9, 31, v5
v_mul_hi_u32 v8, v6, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v4, v4, v11
v_mul_hi_u32 v10, v7, v10
v_add_nc_u32_e32 v5, v5, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v4, v11
v_xor_b32_e32 v5, v5, v9
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v7, v7, v10
v_mul_hi_u32 v7, v4, v7
v_add_nc_u32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_hi_u32 v6, v5, v6
v_mul_lo_u32 v10, v7, s8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v8, v6, s9
v_sub_nc_u32_e32 v4, v4, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v5, v5, v8
v_add_nc_u32_e32 v8, 1, v6
v_subrev_nc_u32_e32 v12, s9, v5
v_cmp_le_u32_e32 vcc_lo, s9, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v6, v6, v8, vcc_lo
v_cndmask_b32_e32 v5, v5, v12, vcc_lo
v_xor_b32_e32 v8, s2, v9
v_add_nc_u32_e32 v9, 1, v7
v_subrev_nc_u32_e32 v12, s8, v4
v_cmp_le_u32_e32 vcc_lo, s8, v4
v_add_nc_u32_e32 v10, 1, v6
v_cmp_le_u32_e64 s2, s9, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v7, v7, v9 :: v_dual_cndmask_b32 v4, v4, v12
v_cndmask_b32_e64 v5, v6, v10, s2
v_xor_b32_e32 v9, s11, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v6, 1, v7
v_cmp_le_u32_e32 vcc_lo, s8, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v5, v5, v8
v_cndmask_b32_e32 v6, v7, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v4, v5, v8
v_xor_b32_e32 v7, v6, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[5:6], null, s7, 3, v[4:5]
v_sub_nc_u32_e32 v4, v7, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[6:7], null, v5, s6, v[4:5]
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[6:7]
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_cmp_lt_f32_e32 vcc_lo, 0, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_19
v_mad_u64_u32 v[5:6], null, v3, s10, v[1:2]
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[6:7], null, v5, s3, v[0:1]
v_sub_f32_e32 v5, 1.0, v4
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[6:7]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_mov_b32 s4, exec_lo
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v3, v5, v3
global_store_b32 v[0:1], v3, off
v_cmpx_lt_i32_e32 0, v2
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_14
s_mov_b32 s2, -1
s_mov_b32 s5, exec_lo
v_cmpx_eq_u32_e32 1, v2
s_cbranch_execz .LBB0_13
s_load_b32 s3, s[0:1], 0x34
s_xor_b32 s2, exec_lo, -1
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s2, s2, exec_lo
.LBB0_14:
s_or_saveexec_b32 s4, s4
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v5, s3
s_xor_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB0_16
s_load_b32 s3, s[0:1], 0x30
v_cmp_ne_u32_e32 vcc_lo, 0, v2
s_and_not1_b32 s2, s2, exec_lo
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v5, s3
s_and_b32 s3, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s2, s2, s3
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_18
s_load_b32 s0, s[0:1], 0x38
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v5, s0
.LBB0_18:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v3, v4, v5
global_store_b32 v[0:1], v3, off
.LBB0_19:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff, .Lfunc_end0-_Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void DrawMaskedColorKernelNearestNeighbor(float *target, int targetWidth, int targetHeight, int inputX, int inputY, float *texture, int textureWidth, int textureHeight, int objectWidth, int objectHeight, float r, float g, float b ) // texture = mask
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
int targetPixels = targetWidth * targetHeight;
int texturePixels = textureWidth * textureHeight;
int objectPixels = objectWidth * objectHeight;
int idObjectRgb = id / objectPixels;
int idObjectPixel = (id - idObjectRgb * objectPixels); // same as (id % objectPixels), but the kernel runs 10% faster
int idObjectY = idObjectPixel / objectWidth;
int idObjectX = (idObjectPixel - idObjectY * objectWidth); // same as (id % textureWidth), but the kernel runs another 10% faster
if (idObjectRgb < 3) // 3 channels that we will write to
{
int targetRgb = idObjectRgb;
// the texture is in BGR format, we want RGB
switch (idObjectRgb)
{
case 0: // R
targetRgb = 2; // B
break;
case 2: // B
targetRgb = 0; // R
break;
}
// if the object pixel offset by inputX, inputY, lies inside the target
if (idObjectX + inputX < targetWidth &&
idObjectX + inputX >= 0 &&
idObjectY + inputY < targetHeight &&
idObjectY + inputY >= 0)
{
// nearest neighbor texture X,Y:
int textureX = textureWidth * idObjectX / objectWidth;
int textureY = textureHeight * idObjectY / objectHeight;
int textureId = textureY * textureWidth + textureX;
int tIndex = targetPixels * targetRgb + targetWidth * (idObjectY + inputY) + (idObjectX + inputX);
int aIndex = textureId + 3 * texturePixels; // the A component of the texture
float a = texture[aIndex];
if (a > 0) // mask allows color here
{
// apply this: target[tIndex] = target[tIndex] * (1.0f - a) + a * color;
target[tIndex] = target[tIndex] * (1.0f - a);
switch (idObjectRgb)
{
case 0:
target[tIndex] += a*r;
break;
case 1:
target[tIndex] += a*g;
break;
case 2:
default:
target[tIndex] += a*b;
break;
}
}
}
}
} | .text
.file "DrawMaskedColorKernelNearestNeighbor.hip"
.globl _Z51__device_stub__DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff # -- Begin function _Z51__device_stub__DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff
.p2align 4, 0x90
.type _Z51__device_stub__DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff,@function
_Z51__device_stub__DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff: # @_Z51__device_stub__DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 88(%rsp)
movl %esi, 28(%rsp)
movl %edx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movq %r9, 80(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 28(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
leaq 4(%rsp), %rax
movq %rax, 192(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size _Z51__device_stub__DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff, .Lfunc_end0-_Z51__device_stub__DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff,@object # @_Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff
.section .rodata,"a",@progbits
.globl _Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff
.p2align 3, 0x0
_Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff:
.quad _Z51__device_stub__DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff
.size _Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff"
.size .L__unnamed_1, 56
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z51__device_stub__DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff037624 */
/* 0x000fe200078e00ff */
/*0020*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e260000002600 */
/*0030*/ IMAD R3, R3, c[0x0][0x188], RZ ; /* 0x0000620003037a24 */
/* 0x000fe200078e02ff */
/*0040*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e280000002500 */
/*0050*/ IABS R11, R3 ; /* 0x00000003000b7213 */
/* 0x000fe20000000000 */
/*0060*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e660000002100 */
/*0070*/ I2F.RP R2, R11 ; /* 0x0000000b00027306 */
/* 0x000eb00000209400 */
/*0080*/ MUFU.RCP R2, R2 ; /* 0x0000000200027308 */
/* 0x004ea20000001000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], R7 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0207 */
/*00a0*/ IMAD R6, R0, c[0x0][0x0], R9 ; /* 0x0000000000067a24 */
/* 0x002fca00078e0209 */
/*00b0*/ IABS R0, R6 ; /* 0x0000000600007213 */
/* 0x000fe40000000000 */
/*00c0*/ IADD3 R4, R2, 0xffffffe, RZ ; /* 0x0ffffffe02047810 */
/* 0x004fe40007ffe0ff */
/*00d0*/ IABS R2, R3 ; /* 0x0000000300027213 */
/* 0x000fe40000000000 */
/*00e0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000066000021f000 */
/*00f0*/ IMAD.MOV R9, RZ, RZ, -R2 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0a02 */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fc400078e00ff */
/*0110*/ IMAD.MOV R8, RZ, RZ, -R5 ; /* 0x000000ffff087224 */
/* 0x002fc800078e0a05 */
/*0120*/ IMAD R7, R8, R11, RZ ; /* 0x0000000b08077224 */
/* 0x000fc800078e02ff */
/*0130*/ IMAD.HI.U32 R5, R5, R7, R4 ; /* 0x0000000705057227 */
/* 0x000fe200078e0004 */
/*0140*/ IABS R7, c[0x0][0x188] ; /* 0x0000620000077a13 */
/* 0x000fc60000000000 */
/*0150*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0000 */
/*0160*/ MOV R0, R7 ; /* 0x0000000700007202 */
/* 0x000fc60000000f00 */
/*0170*/ IMAD.HI.U32 R2, R5, R4, RZ ; /* 0x0000000405027227 */
/* 0x000fe200078e00ff */
/*0180*/ I2F.RP R7, R0 ; /* 0x0000000000077306 */
/* 0x000e260000209400 */
/*0190*/ IMAD R4, R2, R9, R4 ; /* 0x0000000902047224 */
/* 0x000fca00078e0204 */
/*01a0*/ ISETP.GT.U32.AND P1, PT, R11, R4, PT ; /* 0x000000040b00720c */
/* 0x000fe20003f24070 */
/*01b0*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e180000001000 */
/*01c0*/ @!P1 IMAD.IADD R4, R4, 0x1, -R11 ; /* 0x0000000104049824 */
/* 0x000fe200078e0a0b */
/*01d0*/ @!P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102029810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f25270 */
/*01f0*/ ISETP.GE.U32.AND P0, PT, R4, R11, PT ; /* 0x0000000b0400720c */
/* 0x000fe40003f06070 */
/*0200*/ LOP3.LUT R4, R6, R3, RZ, 0x3c, !PT ; /* 0x0000000306047212 */
/* 0x000fc800078e3cff */
/*0210*/ ISETP.GE.AND P2, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f46270 */
/*0220*/ IADD3 R4, R7, 0xffffffe, RZ ; /* 0x0ffffffe07047810 */
/* 0x001fc80007ffe0ff */
/*0230*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000062000021f000 */
/*0240*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fcc0007ffe0ff */
/*0250*/ @!P2 IMAD.MOV R2, RZ, RZ, -R2 ; /* 0x000000ffff02a224 */
/* 0x000fe200078e0a02 */
/*0260*/ @!P1 LOP3.LUT R2, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff029212 */
/* 0x000fe200078e33ff */
/*0270*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*0280*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x188], PT ; /* 0x00006200ff007a0c */
/* 0x000fc60003f45270 */
/*0290*/ IMAD.MOV R7, RZ, RZ, -R2 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0a02 */
/*02a0*/ IMAD.MOV R9, RZ, RZ, -R5 ; /* 0x000000ffff097224 */
/* 0x002fe400078e0a05 */
/*02b0*/ IMAD R8, R3, R7, R6 ; /* 0x0000000703087224 */
/* 0x000fe200078e0206 */
/*02c0*/ LOP3.LUT R6, RZ, c[0x0][0x188], RZ, 0x33, !PT ; /* 0x00006200ff067a12 */
/* 0x000fe200078e33ff */
/*02d0*/ IMAD R7, R9, R0, RZ ; /* 0x0000000009077224 */
/* 0x000fc600078e02ff */
/*02e0*/ IABS R3, R8 ; /* 0x0000000800037213 */
/* 0x000fe20000000000 */
/*02f0*/ IMAD.HI.U32 R7, R5, R7, R4 ; /* 0x0000000705077227 */
/* 0x000fc800078e0004 */
/*0300*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0003 */
/*0310*/ IMAD.HI.U32 R3, R7, R5, RZ ; /* 0x0000000507037227 */
/* 0x000fc800078e00ff */
/*0320*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a03 */
/*0330*/ IMAD R5, R0, R4, R5 ; /* 0x0000000400057224 */
/* 0x000fe200078e0205 */
/*0340*/ LOP3.LUT R4, R8, c[0x0][0x188], RZ, 0x3c, !PT ; /* 0x0000620008047a12 */
/* 0x000fc800078e3cff */
/*0350*/ ISETP.GT.U32.AND P1, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fe40003f24070 */
/*0360*/ ISETP.GE.AND P3, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fd60003f66270 */
/*0370*/ @!P1 IMAD.IADD R5, R5, 0x1, -R0 ; /* 0x0000000105059824 */
/* 0x000fe200078e0a00 */
/*0380*/ @!P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103039810 */
/* 0x000fc80007ffe0ff */
/*0390*/ ISETP.GE.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f06070 */
/*03a0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe40007ffe0ff */
/*03b0*/ ISETP.GT.AND P0, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fc60003f04270 */
/*03c0*/ @!P3 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff03b224 */
/* 0x000fca00078e0a03 */
/*03d0*/ SEL R12, R6, R3, !P2 ; /* 0x00000003060c7207 */
/* 0x000fc80005000000 */
/*03e0*/ IADD3 R3, -R12, RZ, RZ ; /* 0x000000ff0c037210 */
/* 0x000fca0007ffe1ff */
/*03f0*/ IMAD R11, R3, c[0x0][0x188], R8 ; /* 0x00006200030b7a24 */
/* 0x000fe200078e0208 */
/*0400*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fec0003800000 */
/*0410*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f25270 */
/*0420*/ BSSY B0, 0x4c0 ; /* 0x0000009000007945 */
/* 0x000fe20003800000 */
/*0430*/ IADD3 R3, R11, c[0x0][0x170], RZ ; /* 0x00005c000b037a10 */
/* 0x000fe20007ffe0ff */
/*0440*/ IMAD.MOV.U32 R5, RZ, RZ, 0x2 ; /* 0x00000002ff057424 */
/* 0x000fc600078e00ff */
/*0450*/ ISETP.GE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fc80003f06270 */
/*0460*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x168], !P0 ; /* 0x00005a0003007a0c */
/* 0x000fc60004706670 */
/*0470*/ @!P1 BRA 0x4b0 ; /* 0x0000003000009947 */
/* 0x000fea0003800000 */
/*0480*/ ISETP.NE.AND P3, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fda0003f65270 */
/*0490*/ @!P3 IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff05b224 */
/* 0x000fe400078e00ff */
/*04a0*/ @P3 IMAD.MOV.U32 R5, RZ, RZ, R2 ; /* 0x000000ffff053224 */
/* 0x000fe400078e0002 */
/*04b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*04d0*/ IADD3 R4, R12, c[0x0][0x174], RZ ; /* 0x00005d000c047a10 */
/* 0x000fc80007ffe0ff */
/*04e0*/ ISETP.GE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc80003f06270 */
/*04f0*/ ISETP.GE.OR P0, PT, R4, c[0x0][0x16c], !P0 ; /* 0x00005b0004007a0c */
/* 0x000fda0004706670 */
/*0500*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0510*/ IABS R10, c[0x0][0x18c] ; /* 0x00006300000a7a13 */
/* 0x000fe20000000000 */
/*0520*/ IMAD R11, R11, c[0x0][0x180], RZ ; /* 0x000060000b0b7a24 */
/* 0x000fe200078e02ff */
/*0530*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0540*/ IMAD R12, R12, c[0x0][0x184], RZ ; /* 0x000061000c0c7a24 */
/* 0x000fe200078e02ff */
/*0550*/ I2F.RP R13, R10 ; /* 0x0000000a000d7306 */
/* 0x000e240000209400 */
/*0560*/ IABS R14, R11 ; /* 0x0000000b000e7213 */
/* 0x000fe40000000000 */
/*0570*/ LOP3.LUT R11, R11, c[0x0][0x188], RZ, 0x3c, !PT ; /* 0x000062000b0b7a12 */
/* 0x000fc600078e3cff */
/*0580*/ IMAD.HI.U32 R7, R7, R14, RZ ; /* 0x0000000e07077227 */
/* 0x000fe200078e00ff */
/*0590*/ MUFU.RCP R13, R13 ; /* 0x0000000d000d7308 */
/* 0x001e240000001000 */
/*05a0*/ IADD3 R8, R13, 0xffffffe, RZ ; /* 0x0ffffffe0d087810 */
/* 0x001fe40007ffe0ff */
/*05b0*/ IABS R13, R12 ; /* 0x0000000c000d7213 */
/* 0x000fc80000000000 */
/*05c0*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000062000021f000 */
/*05d0*/ LOP3.LUT R12, R12, c[0x0][0x18c], RZ, 0x3c, !PT ; /* 0x000063000c0c7a12 */
/* 0x000fc800078e3cff */
/*05e0*/ ISETP.GE.AND P3, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f66270 */
/*05f0*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x001fe20000000f00 */
/*0600*/ IMAD.MOV R15, RZ, RZ, -R9 ; /* 0x000000ffff0f7224 */
/* 0x002fc800078e0a09 */
/*0610*/ IMAD R15, R15, R10, RZ ; /* 0x0000000a0f0f7224 */
/* 0x000fc800078e02ff */
/*0620*/ IMAD.HI.U32 R9, R9, R15, R8 ; /* 0x0000000f09097227 */
/* 0x000fcc00078e0008 */
/*0630*/ IMAD.HI.U32 R8, R9, R13, RZ ; /* 0x0000000d09087227 */
/* 0x000fc800078e00ff */
/*0640*/ IMAD.MOV R9, RZ, RZ, -R7 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0a07 */
/*0650*/ IMAD.MOV R15, RZ, RZ, -R8 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e0a08 */
/*0660*/ IMAD R9, R0, R9, R14 ; /* 0x0000000900097224 */
/* 0x000fe400078e020e */
/*0670*/ IMAD R13, R10, R15, R13 ; /* 0x0000000f0a0d7224 */
/* 0x000fc600078e020d */
/*0680*/ ISETP.GT.U32.AND P5, PT, R0, R9, PT ; /* 0x000000090000720c */
/* 0x000fe40003fa4070 */
/*0690*/ ISETP.GT.U32.AND P6, PT, R10, R13, PT ; /* 0x0000000d0a00720c */
/* 0x000fd60003fc4070 */
/*06a0*/ @!P5 IMAD.IADD R9, R9, 0x1, -R0 ; /* 0x000000010909d824 */
/* 0x000fe200078e0a00 */
/*06b0*/ @!P5 IADD3 R7, R7, 0x1, RZ ; /* 0x000000010707d810 */
/* 0x000fe20007ffe0ff */
/*06c0*/ @!P6 IMAD.IADD R13, R13, 0x1, -R10 ; /* 0x000000010d0de824 */
/* 0x000fe200078e0a0a */
/*06d0*/ @!P6 IADD3 R8, R8, 0x1, RZ ; /* 0x000000010808e810 */
/* 0x000fe40007ffe0ff */
/*06e0*/ ISETP.GE.U32.AND P4, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fe20003f86070 */
/*06f0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff097624 */
/* 0x000fe200078e00ff */
/*0700*/ ISETP.GE.U32.AND P0, PT, R13, R10, PT ; /* 0x0000000a0d00720c */
/* 0x000fe40003f06070 */
/*0710*/ ISETP.GE.AND P6, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003fc6270 */
/*0720*/ ISETP.NE.AND P5, PT, RZ, c[0x0][0x18c], PT ; /* 0x00006300ff007a0c */
/* 0x000fce0003fa5270 */
/*0730*/ @P4 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107074810 */
/* 0x000fe40007ffe0ff */
/*0740*/ @P0 IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108080810 */
/* 0x000fc60007ffe0ff */
/*0750*/ @!P6 IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff07e224 */
/* 0x000fe200078e0a07 */
/*0760*/ @!P3 IADD3 R8, -R8, RZ, RZ ; /* 0x000000ff0808b210 */
/* 0x000fe40007ffe1ff */
/*0770*/ @!P5 LOP3.LUT R8, RZ, c[0x0][0x18c], RZ, 0x33, !PT ; /* 0x00006300ff08da12 */
/* 0x000fe400078e33ff */
/*0780*/ SEL R7, R6, R7, !P2 ; /* 0x0000000706077207 */
/* 0x000fc60005000000 */
/*0790*/ IMAD R8, R9, 0x3, R8 ; /* 0x0000000309087824 */
/* 0x000fe400078e0208 */
/*07a0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe400078e00ff */
/*07b0*/ IMAD R6, R8, c[0x0][0x180], R7 ; /* 0x0000600008067a24 */
/* 0x000fc800078e0207 */
/*07c0*/ IMAD.WIDE R6, R6, R9, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fcc00078e0209 */
/*07d0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*07e0*/ IMAD R4, R5, c[0x0][0x16c], R4 ; /* 0x00005b0005047a24 */
/* 0x000fc800078e0204 */
/*07f0*/ IMAD R4, R4, c[0x0][0x168], R3 ; /* 0x00005a0004047a24 */
/* 0x000fe200078e0203 */
/*0800*/ FSETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720b */
/* 0x004fda0003f04000 */
/*0810*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0820*/ IMAD.WIDE R4, R4, R9, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0209 */
/*0830*/ LDG.E R3, [R4.64] ; /* 0x0000000404037981 */
/* 0x000ea2000c1e1900 */
/*0840*/ FADD R0, -R6, 1 ; /* 0x3f80000006007421 */
/* 0x000fc80000000100 */
/*0850*/ FMUL R7, R0, R3 ; /* 0x0000000300077220 */
/* 0x004fca0000400000 */
/*0860*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e2000c101904 */
/*0870*/ @!P1 BRA 0x8f0 ; /* 0x0000007000009947 */
/* 0x000fea0003800000 */
/*0880*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f05270 */
/*0890*/ @!P0 FFMA R3, R6, c[0x0][0x194], R7 ; /* 0x0000650006038a23 */
/* 0x000fca0000000007 */
/*08a0*/ @!P0 STG.E [R4.64], R3 ; /* 0x0000000304008986 */
/* 0x0003e2000c101904 */
/*08b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*08c0*/ FFMA R3, R6, c[0x0][0x198], R7 ; /* 0x0000660006037a23 */
/* 0x002fca0000000007 */
/*08d0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x000fe2000c101904 */
/*08e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08f0*/ FFMA R3, R6, c[0x0][0x190], R7 ; /* 0x0000640006037a23 */
/* 0x000fca0000000007 */
/*0900*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x000fe2000c101904 */
/*0910*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0920*/ BRA 0x920; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff
.globl _Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff
.p2align 8
.type _Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff,@function
_Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff:
s_clause 0x2
s_load_b64 s[8:9], s[0:1], 0x28
s_load_b32 s2, s[0:1], 0x40
s_load_b32 s3, s[0:1], 0x4c
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s9, s8
s_mul_i32 s2, s2, s15
s_ashr_i32 s5, s4, 31
s_and_b32 s3, s3, 0xffff
s_add_i32 s6, s4, s5
s_add_i32 s2, s2, s14
s_xor_b32 s6, s6, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s6
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1)
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_sub_i32 s2, 0, s6
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s2, v3
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v2
v_xor_b32_e32 v4, v4, v2
v_xor_b32_e32 v2, s5, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v3, v0
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v0, s6
v_sub_nc_u32_e32 v3, v4, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s6, v3
v_cmp_le_u32_e32 vcc_lo, s6, v3
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s6, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v0, v2
v_cmpx_gt_i32_e32 3, v2
s_cbranch_execz .LBB0_19
s_ashr_i32 s2, s8, 31
v_mul_lo_u32 v3, v2, s4
s_add_i32 s3, s8, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s3, s3, s2
v_cvt_f32_u32_e32 v0, s3
s_sub_i32 s4, 0, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v4, v1, v3
v_rcp_iflag_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v0, 0x4f7ffffe, v0 :: v_dual_add_nc_u32 v3, v4, v5
v_xor_b32_e32 v6, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v1, s4, v0
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v1, v0, v1
v_add_nc_u32_e32 v3, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v6, v3, 0
v_cmpx_lt_i32_e32 1, v2
s_xor_b32 s4, exec_lo, s4
s_mov_b32 s5, 0
s_or_saveexec_b32 s4, s4
v_mov_b32_e32 v3, s5
s_xor_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v3, v2
s_mov_b32 s5, exec_lo
v_cmpx_eq_u32_e32 0, v2
v_mov_b32_e32 v3, 2
s_or_b32 exec_lo, exec_lo, s5
.LBB0_7:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s4
v_mul_lo_u32 v0, v1, s3
v_xor_b32_e32 v5, s2, v5
s_load_b32 s2, s[0:1], 0x10
v_sub_nc_u32_e32 v0, v6, v0
v_add_nc_u32_e32 v6, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v7, s3, v0
v_cmp_le_u32_e32 vcc_lo, s3, v0
v_dual_cndmask_b32 v1, v1, v6 :: v_dual_cndmask_b32 v0, v0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, 1, v1
v_cmp_le_u32_e32 vcc_lo, s3, v0
s_load_b32 s3, s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v1, v6, vcc_lo
v_xor_b32_e32 v0, v0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v0, v5
v_mul_lo_u32 v0, v5, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v4, v0
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, s2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v0
v_cmp_lt_i32_e64 s2, -1, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_19
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b32 s10, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, s2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s10, v1
v_cmp_lt_i32_e64 s2, -1, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_19
s_ashr_i32 s2, s9, 31
s_ashr_i32 s11, s8, 31
s_add_i32 s4, s9, s2
s_add_i32 s8, s8, s11
s_xor_b32 s9, s4, s2
s_xor_b32 s8, s8, s11
v_cvt_f32_u32_e32 v6, s9
v_cvt_f32_u32_e32 v7, s8
s_load_b128 s[4:7], s[0:1], 0x18
s_sub_i32 s12, 0, s9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v6, v6
v_rcp_iflag_f32_e32 v7, v7
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v6, 0x4f7ffffe, v6 :: v_dual_mul_f32 v7, 0x4f7ffffe, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v6, v6
v_cvt_u32_f32_e32 v7, v7
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v4, v4, s6
v_mul_lo_u32 v5, v5, s7
v_mul_lo_u32 v8, s12, v6
s_sub_i32 s12, 0, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_lo_u32 v10, s12, v7
v_ashrrev_i32_e32 v11, 31, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v9, 31, v5
v_mul_hi_u32 v8, v6, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v4, v4, v11
v_mul_hi_u32 v10, v7, v10
v_add_nc_u32_e32 v5, v5, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v4, v11
v_xor_b32_e32 v5, v5, v9
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v7, v7, v10
v_mul_hi_u32 v7, v4, v7
v_add_nc_u32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_hi_u32 v6, v5, v6
v_mul_lo_u32 v10, v7, s8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v8, v6, s9
v_sub_nc_u32_e32 v4, v4, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v5, v5, v8
v_add_nc_u32_e32 v8, 1, v6
v_subrev_nc_u32_e32 v12, s9, v5
v_cmp_le_u32_e32 vcc_lo, s9, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v6, v6, v8, vcc_lo
v_cndmask_b32_e32 v5, v5, v12, vcc_lo
v_xor_b32_e32 v8, s2, v9
v_add_nc_u32_e32 v9, 1, v7
v_subrev_nc_u32_e32 v12, s8, v4
v_cmp_le_u32_e32 vcc_lo, s8, v4
v_add_nc_u32_e32 v10, 1, v6
v_cmp_le_u32_e64 s2, s9, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v7, v7, v9 :: v_dual_cndmask_b32 v4, v4, v12
v_cndmask_b32_e64 v5, v6, v10, s2
v_xor_b32_e32 v9, s11, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v6, 1, v7
v_cmp_le_u32_e32 vcc_lo, s8, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v5, v5, v8
v_cndmask_b32_e32 v6, v7, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v4, v5, v8
v_xor_b32_e32 v7, v6, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[5:6], null, s7, 3, v[4:5]
v_sub_nc_u32_e32 v4, v7, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[6:7], null, v5, s6, v[4:5]
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[6:7]
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_cmp_lt_f32_e32 vcc_lo, 0, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_19
v_mad_u64_u32 v[5:6], null, v3, s10, v[1:2]
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[6:7], null, v5, s3, v[0:1]
v_sub_f32_e32 v5, 1.0, v4
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[6:7]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_mov_b32 s4, exec_lo
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v3, v5, v3
global_store_b32 v[0:1], v3, off
v_cmpx_lt_i32_e32 0, v2
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_14
s_mov_b32 s2, -1
s_mov_b32 s5, exec_lo
v_cmpx_eq_u32_e32 1, v2
s_cbranch_execz .LBB0_13
s_load_b32 s3, s[0:1], 0x34
s_xor_b32 s2, exec_lo, -1
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s2, s2, exec_lo
.LBB0_14:
s_or_saveexec_b32 s4, s4
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v5, s3
s_xor_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB0_16
s_load_b32 s3, s[0:1], 0x30
v_cmp_ne_u32_e32 vcc_lo, 0, v2
s_and_not1_b32 s2, s2, exec_lo
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v5, s3
s_and_b32 s3, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s2, s2, s3
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_18
s_load_b32 s0, s[0:1], 0x38
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v5, s0
.LBB0_18:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v3, v4, v5
global_store_b32 v[0:1], v3, off
.LBB0_19:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff, .Lfunc_end0-_Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006f5e1_00000000-6_DrawMaskedColorKernelNearestNeighbor.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z69__device_stub__Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifffPfiiiiS_iiiifff
.type _Z69__device_stub__Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifffPfiiiiS_iiiifff, @function
_Z69__device_stub__Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifffPfiiiiS_iiiifff:
.LFB2051:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movl %ecx, 28(%rsp)
movl %r8d, 24(%rsp)
movq %r9, 16(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 264(%rsp), %rax
movq %rax, 184(%rsp)
leaq 12(%rsp), %rax
movq %rax, 192(%rsp)
leaq 8(%rsp), %rax
movq %rax, 200(%rsp)
leaq 4(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 248
pushq 56(%rsp)
.cfi_def_cfa_offset 256
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z69__device_stub__Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifffPfiiiiS_iiiifff, .-_Z69__device_stub__Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifffPfiiiiS_iiiifff
.globl _Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff
.type _Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff, @function
_Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z69__device_stub__Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifffPfiiiiS_iiiifff
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff, .-_Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "DrawMaskedColorKernelNearestNeighbor.hip"
.globl _Z51__device_stub__DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff # -- Begin function _Z51__device_stub__DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff
.p2align 4, 0x90
.type _Z51__device_stub__DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff,@function
_Z51__device_stub__DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff: # @_Z51__device_stub__DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 88(%rsp)
movl %esi, 28(%rsp)
movl %edx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movq %r9, 80(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 28(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
leaq 4(%rsp), %rax
movq %rax, 192(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size _Z51__device_stub__DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff, .Lfunc_end0-_Z51__device_stub__DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff,@object # @_Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff
.section .rodata,"a",@progbits
.globl _Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff
.p2align 3, 0x0
_Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff:
.quad _Z51__device_stub__DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff
.size _Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff"
.size .L__unnamed_1, 56
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z51__device_stub__DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z36DrawMaskedColorKernelNearestNeighborPfiiiiS_iiiifff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <time.h>
#include <cuda_runtime.h>
/*
* This example demonstrates a simple vector sum on the host. sumArraysOnHost
* sequentially iterates through vector elements on the host.
*/
void CHECK(const cudaError_t error)
{
if (error != cudaSuccess)
{
fprintf(stderr, "Error: %s:%s:%d, ", __FILE__, __func__, __LINE__);
fprintf(stderr, "code:%d, reason: %s\n", error, cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
}
__global__
void checkIndex(void)
{
//Print thread's coords within a block and the block's
//coords within the grid
printf("Thread coords: (%d %d %d), Block coords: (%d %d %d)\n", threadIdx.x, threadIdx.y, threadIdx.z, blockIdx.x, blockIdx.y, blockIdx.z);
}
__global__
void sumArrays(float *A, float *B, float *C, unsigned int N)
{
unsigned int idx = blockIdx.x*blockDim.x + threadIdx.x;
if (idx < N)
C[idx] = A[idx] + B[idx];
}
__host__
void initialData(float *ip, unsigned int size)
{
// generate different seed for random number
time_t t;
srand((unsigned) time(&t));
int i;
for (i = 0; i < size; i++)
{
ip[i] = (float)(rand() & 0xFF) / 10.0f;
}
}
__host__
int main(int argc, char **argv)
{
int deviceId = 0;
cudaSetDevice(deviceId);
unsigned int nElem = 1<<24;
size_t nBytes = nElem * sizeof(float);
printf("%u elements, %zu B\n", nElem, nBytes);
//Allocate vectors in host memory
float *h_A, *h_B, *h_C, *gpuRef;
h_A = (float *)malloc(nBytes);
h_B = (float *)malloc(nBytes);
h_C = (float *)malloc(nBytes);
gpuRef = (float *)malloc(nBytes);
//Allocate vectors in device memory
float *d_A, *d_B, *d_C;
CHECK(cudaMalloc(&d_A, nBytes));
CHECK(cudaMalloc(&d_B, nBytes));
CHECK(cudaMalloc(&d_C, nBytes));
initialData(h_A, nElem);
initialData(h_B, nElem);
//Copy the vector data over the device memory
CHECK(cudaMemcpy(d_A, h_A, nBytes, cudaMemcpyHostToDevice));
CHECK(cudaMemcpy(d_B, h_B, nBytes, cudaMemcpyHostToDevice));
int deviceCount = 0, maxDevice = 0;
unsigned long long maxMemory = 0;
CHECK(cudaGetDeviceCount(&deviceCount));
printf("Number of devices: %d\n", deviceCount);
if (deviceCount > 1)
{
int device;
for (device = 0; device < deviceCount; device++)
{
cudaDeviceProp props;
CHECK(cudaGetDeviceProperties(&props, device));
if (maxMemory < props.totalGlobalMem)
{
maxMemory = props.totalGlobalMem;
maxDevice = device;
}
}
CHECK(cudaSetDevice(maxDevice));
printf("Device with largest total global memory: %d (%llu B)\n", maxDevice, maxMemory);
}
//cudaDeviceProp prop;
//CHECK(cudaGetDeviceProperties(&prop,
//Define the grid and block dimensions
unsigned int blockSize = 1024;
dim3 block(blockSize);
dim3 grid((nElem + block.x-1)/block.x);
printf("Block dim3: <%d %d %d>\n", block.x, block.y, block.z);
printf("Grid dim3: <%d %d %d>\n", grid.x, grid.y, grid.z);
unsigned int totalThreads = block.x*block.y*block.z*grid.x*grid.y*grid.z;
printf("Total threads: %u\n", totalThreads);
//Invoke the kernel on the device
//checkIndex<<<grid, block>>>();
//All kernel invocations must return from device
//before control returns to the host
//cudaDeviceSynchronize();
sumArrays<<<grid, block>>>(d_A, d_B, d_C, nElem);
//Copy the result vector back to the host
CHECK(cudaMemcpy(gpuRef, d_C, nBytes, cudaMemcpyDeviceToHost));
//Deallocate the device memory vectors
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
//Done using the device. Clean up all state on the device
//and flush profiling data.
cudaDeviceReset();
//Deallocate the host memory vectors
free(h_A);
free(h_B);
free(h_C);
free(gpuRef);
return 0;
} | code for sm_80
Function : _Z9sumArraysPfS_S_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0007 */
/*0090*/ IMAD.WIDE.U32 R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0007 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0007 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10checkIndexv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000e220000002200 */
/*0020*/ IADD3 R1, R1, -0x18, RZ ; /* 0xffffffe801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x0] ; /* 0x01000000ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R0, 0x8 ; /* 0x0000000800007802 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0060*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x4] ; /* 0x01000100ff057624 */
/* 0x000fe200078e00ff */
/*0080*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0002a20000000a00 */
/*0090*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000ee40000002500 */
/*00a0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fc400000e06ff */
/*00b0*/ S2R R10, SR_TID.Z ; /* 0x00000000000a7919 */
/* 0x000ee80000002300 */
/*00c0*/ S2R R13, SR_CTAID.Z ; /* 0x00000000000d7919 */
/* 0x000f280000002700 */
/*00d0*/ S2R R12, SR_CTAID.Y ; /* 0x00000000000c7919 */
/* 0x000f280000002600 */
/*00e0*/ STL.64 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0013e80000100a00 */
/*00f0*/ STL.64 [R1+0x8], R10 ; /* 0x0000080a01007387 */
/* 0x0083e80000100a00 */
/*0100*/ STL.64 [R1+0x10], R12 ; /* 0x0000100c01007387 */
/* 0x0103e40000100a00 */
/*0110*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x006fe40000000000 */
/*0120*/ MOV R11, 0x190 ; /* 0x00000190000b7802 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R20, 0x110 ; /* 0x0000011000147802 */
/* 0x000fc40000000f00 */
/*0140*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0150*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0160*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0170*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0180*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <time.h>
#include <cuda_runtime.h>
/*
* This example demonstrates a simple vector sum on the host. sumArraysOnHost
* sequentially iterates through vector elements on the host.
*/
void CHECK(const cudaError_t error)
{
if (error != cudaSuccess)
{
fprintf(stderr, "Error: %s:%s:%d, ", __FILE__, __func__, __LINE__);
fprintf(stderr, "code:%d, reason: %s\n", error, cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
}
__global__
void checkIndex(void)
{
//Print thread's coords within a block and the block's
//coords within the grid
printf("Thread coords: (%d %d %d), Block coords: (%d %d %d)\n", threadIdx.x, threadIdx.y, threadIdx.z, blockIdx.x, blockIdx.y, blockIdx.z);
}
__global__
void sumArrays(float *A, float *B, float *C, unsigned int N)
{
unsigned int idx = blockIdx.x*blockDim.x + threadIdx.x;
if (idx < N)
C[idx] = A[idx] + B[idx];
}
__host__
void initialData(float *ip, unsigned int size)
{
// generate different seed for random number
time_t t;
srand((unsigned) time(&t));
int i;
for (i = 0; i < size; i++)
{
ip[i] = (float)(rand() & 0xFF) / 10.0f;
}
}
__host__
int main(int argc, char **argv)
{
int deviceId = 0;
cudaSetDevice(deviceId);
unsigned int nElem = 1<<24;
size_t nBytes = nElem * sizeof(float);
printf("%u elements, %zu B\n", nElem, nBytes);
//Allocate vectors in host memory
float *h_A, *h_B, *h_C, *gpuRef;
h_A = (float *)malloc(nBytes);
h_B = (float *)malloc(nBytes);
h_C = (float *)malloc(nBytes);
gpuRef = (float *)malloc(nBytes);
//Allocate vectors in device memory
float *d_A, *d_B, *d_C;
CHECK(cudaMalloc(&d_A, nBytes));
CHECK(cudaMalloc(&d_B, nBytes));
CHECK(cudaMalloc(&d_C, nBytes));
initialData(h_A, nElem);
initialData(h_B, nElem);
//Copy the vector data over the device memory
CHECK(cudaMemcpy(d_A, h_A, nBytes, cudaMemcpyHostToDevice));
CHECK(cudaMemcpy(d_B, h_B, nBytes, cudaMemcpyHostToDevice));
int deviceCount = 0, maxDevice = 0;
unsigned long long maxMemory = 0;
CHECK(cudaGetDeviceCount(&deviceCount));
printf("Number of devices: %d\n", deviceCount);
if (deviceCount > 1)
{
int device;
for (device = 0; device < deviceCount; device++)
{
cudaDeviceProp props;
CHECK(cudaGetDeviceProperties(&props, device));
if (maxMemory < props.totalGlobalMem)
{
maxMemory = props.totalGlobalMem;
maxDevice = device;
}
}
CHECK(cudaSetDevice(maxDevice));
printf("Device with largest total global memory: %d (%llu B)\n", maxDevice, maxMemory);
}
//cudaDeviceProp prop;
//CHECK(cudaGetDeviceProperties(&prop,
//Define the grid and block dimensions
unsigned int blockSize = 1024;
dim3 block(blockSize);
dim3 grid((nElem + block.x-1)/block.x);
printf("Block dim3: <%d %d %d>\n", block.x, block.y, block.z);
printf("Grid dim3: <%d %d %d>\n", grid.x, grid.y, grid.z);
unsigned int totalThreads = block.x*block.y*block.z*grid.x*grid.y*grid.z;
printf("Total threads: %u\n", totalThreads);
//Invoke the kernel on the device
//checkIndex<<<grid, block>>>();
//All kernel invocations must return from device
//before control returns to the host
//cudaDeviceSynchronize();
sumArrays<<<grid, block>>>(d_A, d_B, d_C, nElem);
//Copy the result vector back to the host
CHECK(cudaMemcpy(gpuRef, d_C, nBytes, cudaMemcpyDeviceToHost));
//Deallocate the device memory vectors
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
//Done using the device. Clean up all state on the device
//and flush profiling data.
cudaDeviceReset();
//Deallocate the host memory vectors
free(h_A);
free(h_B);
free(h_C);
free(gpuRef);
return 0;
} | .file "tmpxft_00011ae6_00000000-6_sumArraysOnHost.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CHECK"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/blessley/CudaCode/master/vectorSum/sumArraysOnHost.cu"
.section .rodata.str1.1
.LC2:
.string "Error: %s:%s:%d, "
.LC3:
.string "code:%d, reason: %s\n"
.text
.globl _Z5CHECK9cudaError
.type _Z5CHECK9cudaError, @function
_Z5CHECK9cudaError:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
ret
.L8:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edi, %ebx
movl $15, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z5CHECK9cudaError, .-_Z5CHECK9cudaError
.globl _Z11initialDataPfj
.type _Z11initialDataPfj, @function
_Z11initialDataPfj:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r12
movl %esi, %ebp
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
call time@PLT
movl %eax, %edi
call srand@PLT
testl %ebp, %ebp
je .L9
movq %r12, %rbx
movl %ebp, %ebp
leaq (%r12,%rbp,4), %rbp
.L11:
call rand@PLT
movzbl %al, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
divss .LC4(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L11
.L9:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z11initialDataPfj, .-_Z11initialDataPfj
.globl _Z29__device_stub__Z10checkIndexvv
.type _Z29__device_stub__Z10checkIndexvv, @function
_Z29__device_stub__Z10checkIndexvv:
.LFB2084:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10checkIndexv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z29__device_stub__Z10checkIndexvv, .-_Z29__device_stub__Z10checkIndexvv
.globl _Z10checkIndexv
.type _Z10checkIndexv, @function
_Z10checkIndexv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10checkIndexvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10checkIndexv, .-_Z10checkIndexv
.globl _Z33__device_stub__Z9sumArraysPfS_S_jPfS_S_j
.type _Z33__device_stub__Z9sumArraysPfS_S_jPfS_S_j, @function
_Z33__device_stub__Z9sumArraysPfS_S_jPfS_S_j:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9sumArraysPfS_S_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z33__device_stub__Z9sumArraysPfS_S_jPfS_S_j, .-_Z33__device_stub__Z9sumArraysPfS_S_jPfS_S_j
.globl _Z9sumArraysPfS_S_j
.type _Z9sumArraysPfS_S_j, @function
_Z9sumArraysPfS_S_j:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9sumArraysPfS_S_jPfS_S_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z9sumArraysPfS_S_j, .-_Z9sumArraysPfS_S_j
.section .rodata.str1.1
.LC5:
.string "%u elements, %zu B\n"
.LC6:
.string "Number of devices: %d\n"
.section .rodata.str1.8
.align 8
.LC7:
.string "Device with largest total global memory: %d (%llu B)\n"
.section .rodata.str1.1
.LC8:
.string "Block dim3: <%d %d %d>\n"
.LC9:
.string "Grid dim3: <%d %d %d>\n"
.LC10:
.string "Total threads: %u\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1128, %rsp
.cfi_def_cfa_offset 1184
movq %fs:40, %rax
movq %rax, 1112(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
movl $67108864, %ecx
movl $16777216, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $67108864, %edi
call malloc@PLT
movq %rax, %r13
movl $67108864, %edi
call malloc@PLT
movq %rax, %r12
movl $67108864, %edi
call malloc@PLT
movq %rax, %r15
leaq 32(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
movl %eax, %edi
call _Z5CHECK9cudaError
leaq 40(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
movl %eax, %edi
call _Z5CHECK9cudaError
leaq 48(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
movl %eax, %edi
call _Z5CHECK9cudaError
movl $16777216, %esi
movq %r13, %rdi
call _Z11initialDataPfj
movl $16777216, %esi
movq %r12, %rdi
call _Z11initialDataPfj
movl $1, %ecx
movl $67108864, %edx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z5CHECK9cudaError
movl $1, %ecx
movl $67108864, %edx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z5CHECK9cudaError
movl $0, 28(%rsp)
leaq 28(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl %eax, %edi
call _Z5CHECK9cudaError
movl 28(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $1, 28(%rsp)
jle .L33
movl $0, %ebx
movl $0, %ebp
movl $0, 12(%rsp)
leaq 80(%rsp), %r14
jmp .L35
.L34:
addl $1, %ebx
cmpl %ebx, 28(%rsp)
jle .L41
.L35:
movl %ebx, %esi
movq %r14, %rdi
call cudaGetDeviceProperties_v2@PLT
movl %eax, %edi
call _Z5CHECK9cudaError
movq 368(%rsp), %rax
cmpq %rax, %rbp
jnb .L34
movq %rax, %rbp
movl %ebx, 12(%rsp)
jmp .L34
.L41:
movl 12(%rsp), %ebx
movl %ebx, %edi
call cudaSetDevice@PLT
movl %eax, %edi
call _Z5CHECK9cudaError
movq %rbp, %rcx
movl %ebx, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L33:
movl $1, %r8d
movl $1, %ecx
movl $1024, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %r8d
movl $1, %ecx
movl $16384, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16777216, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16384, 68(%rsp)
movl $1, 72(%rsp)
movl $1024, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movl $1, %ecx
movq 68(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L36:
movl $2, %ecx
movl $67108864, %edx
movq 48(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z5CHECK9cudaError
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
call cudaDeviceReset@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq 1112(%rsp), %rax
subq %fs:40, %rax
jne .L43
movl $0, %eax
addq $1128, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
movl $16777216, %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z33__device_stub__Z9sumArraysPfS_S_jPfS_S_j
jmp .L36
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z9sumArraysPfS_S_j"
.LC12:
.string "_Z10checkIndexv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z9sumArraysPfS_S_j(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z10checkIndexv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 1092616192
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
#include <time.h>
#include <cuda_runtime.h>
/*
* This example demonstrates a simple vector sum on the host. sumArraysOnHost
* sequentially iterates through vector elements on the host.
*/
void CHECK(const cudaError_t error)
{
if (error != cudaSuccess)
{
fprintf(stderr, "Error: %s:%s:%d, ", __FILE__, __func__, __LINE__);
fprintf(stderr, "code:%d, reason: %s\n", error, cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
}
__global__
void checkIndex(void)
{
//Print thread's coords within a block and the block's
//coords within the grid
printf("Thread coords: (%d %d %d), Block coords: (%d %d %d)\n", threadIdx.x, threadIdx.y, threadIdx.z, blockIdx.x, blockIdx.y, blockIdx.z);
}
__global__
void sumArrays(float *A, float *B, float *C, unsigned int N)
{
unsigned int idx = blockIdx.x*blockDim.x + threadIdx.x;
if (idx < N)
C[idx] = A[idx] + B[idx];
}
__host__
void initialData(float *ip, unsigned int size)
{
// generate different seed for random number
time_t t;
srand((unsigned) time(&t));
int i;
for (i = 0; i < size; i++)
{
ip[i] = (float)(rand() & 0xFF) / 10.0f;
}
}
__host__
int main(int argc, char **argv)
{
int deviceId = 0;
cudaSetDevice(deviceId);
unsigned int nElem = 1<<24;
size_t nBytes = nElem * sizeof(float);
printf("%u elements, %zu B\n", nElem, nBytes);
//Allocate vectors in host memory
float *h_A, *h_B, *h_C, *gpuRef;
h_A = (float *)malloc(nBytes);
h_B = (float *)malloc(nBytes);
h_C = (float *)malloc(nBytes);
gpuRef = (float *)malloc(nBytes);
//Allocate vectors in device memory
float *d_A, *d_B, *d_C;
CHECK(cudaMalloc(&d_A, nBytes));
CHECK(cudaMalloc(&d_B, nBytes));
CHECK(cudaMalloc(&d_C, nBytes));
initialData(h_A, nElem);
initialData(h_B, nElem);
//Copy the vector data over the device memory
CHECK(cudaMemcpy(d_A, h_A, nBytes, cudaMemcpyHostToDevice));
CHECK(cudaMemcpy(d_B, h_B, nBytes, cudaMemcpyHostToDevice));
int deviceCount = 0, maxDevice = 0;
unsigned long long maxMemory = 0;
CHECK(cudaGetDeviceCount(&deviceCount));
printf("Number of devices: %d\n", deviceCount);
if (deviceCount > 1)
{
int device;
for (device = 0; device < deviceCount; device++)
{
cudaDeviceProp props;
CHECK(cudaGetDeviceProperties(&props, device));
if (maxMemory < props.totalGlobalMem)
{
maxMemory = props.totalGlobalMem;
maxDevice = device;
}
}
CHECK(cudaSetDevice(maxDevice));
printf("Device with largest total global memory: %d (%llu B)\n", maxDevice, maxMemory);
}
//cudaDeviceProp prop;
//CHECK(cudaGetDeviceProperties(&prop,
//Define the grid and block dimensions
unsigned int blockSize = 1024;
dim3 block(blockSize);
dim3 grid((nElem + block.x-1)/block.x);
printf("Block dim3: <%d %d %d>\n", block.x, block.y, block.z);
printf("Grid dim3: <%d %d %d>\n", grid.x, grid.y, grid.z);
unsigned int totalThreads = block.x*block.y*block.z*grid.x*grid.y*grid.z;
printf("Total threads: %u\n", totalThreads);
//Invoke the kernel on the device
//checkIndex<<<grid, block>>>();
//All kernel invocations must return from device
//before control returns to the host
//cudaDeviceSynchronize();
sumArrays<<<grid, block>>>(d_A, d_B, d_C, nElem);
//Copy the result vector back to the host
CHECK(cudaMemcpy(gpuRef, d_C, nBytes, cudaMemcpyDeviceToHost));
//Deallocate the device memory vectors
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
//Done using the device. Clean up all state on the device
//and flush profiling data.
cudaDeviceReset();
//Deallocate the host memory vectors
free(h_A);
free(h_B);
free(h_C);
free(gpuRef);
return 0;
} | #include <stdlib.h>
#include <stdio.h>
#include <time.h>
#include <hip/hip_runtime.h>
/*
* This example demonstrates a simple vector sum on the host. sumArraysOnHost
* sequentially iterates through vector elements on the host.
*/
void CHECK(const hipError_t error)
{
if (error != hipSuccess)
{
fprintf(stderr, "Error: %s:%s:%d, ", __FILE__, __func__, __LINE__);
fprintf(stderr, "code:%d, reason: %s\n", error, hipGetErrorString(error));
exit(EXIT_FAILURE);
}
}
__global__
void checkIndex(void)
{
//Print thread's coords within a block and the block's
//coords within the grid
printf("Thread coords: (%d %d %d), Block coords: (%d %d %d)\n", threadIdx.x, threadIdx.y, threadIdx.z, blockIdx.x, blockIdx.y, blockIdx.z);
}
__global__
void sumArrays(float *A, float *B, float *C, unsigned int N)
{
unsigned int idx = blockIdx.x*blockDim.x + threadIdx.x;
if (idx < N)
C[idx] = A[idx] + B[idx];
}
__host__
void initialData(float *ip, unsigned int size)
{
// generate different seed for random number
time_t t;
srand((unsigned) time(&t));
int i;
for (i = 0; i < size; i++)
{
ip[i] = (float)(rand() & 0xFF) / 10.0f;
}
}
__host__
int main(int argc, char **argv)
{
int deviceId = 0;
hipSetDevice(deviceId);
unsigned int nElem = 1<<24;
size_t nBytes = nElem * sizeof(float);
printf("%u elements, %zu B\n", nElem, nBytes);
//Allocate vectors in host memory
float *h_A, *h_B, *h_C, *gpuRef;
h_A = (float *)malloc(nBytes);
h_B = (float *)malloc(nBytes);
h_C = (float *)malloc(nBytes);
gpuRef = (float *)malloc(nBytes);
//Allocate vectors in device memory
float *d_A, *d_B, *d_C;
CHECK(hipMalloc(&d_A, nBytes));
CHECK(hipMalloc(&d_B, nBytes));
CHECK(hipMalloc(&d_C, nBytes));
initialData(h_A, nElem);
initialData(h_B, nElem);
//Copy the vector data over the device memory
CHECK(hipMemcpy(d_A, h_A, nBytes, hipMemcpyHostToDevice));
CHECK(hipMemcpy(d_B, h_B, nBytes, hipMemcpyHostToDevice));
int deviceCount = 0, maxDevice = 0;
unsigned long long maxMemory = 0;
CHECK(hipGetDeviceCount(&deviceCount));
printf("Number of devices: %d\n", deviceCount);
if (deviceCount > 1)
{
int device;
for (device = 0; device < deviceCount; device++)
{
hipDeviceProp_t props;
CHECK(hipGetDeviceProperties(&props, device));
if (maxMemory < props.totalGlobalMem)
{
maxMemory = props.totalGlobalMem;
maxDevice = device;
}
}
CHECK(hipSetDevice(maxDevice));
printf("Device with largest total global memory: %d (%llu B)\n", maxDevice, maxMemory);
}
//cudaDeviceProp prop;
//CHECK(cudaGetDeviceProperties(&prop,
//Define the grid and block dimensions
unsigned int blockSize = 1024;
dim3 block(blockSize);
dim3 grid((nElem + block.x-1)/block.x);
printf("Block dim3: <%d %d %d>\n", block.x, block.y, block.z);
printf("Grid dim3: <%d %d %d>\n", grid.x, grid.y, grid.z);
unsigned int totalThreads = block.x*block.y*block.z*grid.x*grid.y*grid.z;
printf("Total threads: %u\n", totalThreads);
//Invoke the kernel on the device
//checkIndex<<<grid, block>>>();
//All kernel invocations must return from device
//before control returns to the host
//cudaDeviceSynchronize();
sumArrays<<<grid, block>>>(d_A, d_B, d_C, nElem);
//Copy the result vector back to the host
CHECK(hipMemcpy(gpuRef, d_C, nBytes, hipMemcpyDeviceToHost));
//Deallocate the device memory vectors
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
//Done using the device. Clean up all state on the device
//and flush profiling data.
hipDeviceReset();
//Deallocate the host memory vectors
free(h_A);
free(h_B);
free(h_C);
free(gpuRef);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <time.h>
#include <hip/hip_runtime.h>
/*
* This example demonstrates a simple vector sum on the host. sumArraysOnHost
* sequentially iterates through vector elements on the host.
*/
void CHECK(const hipError_t error)
{
if (error != hipSuccess)
{
fprintf(stderr, "Error: %s:%s:%d, ", __FILE__, __func__, __LINE__);
fprintf(stderr, "code:%d, reason: %s\n", error, hipGetErrorString(error));
exit(EXIT_FAILURE);
}
}
__global__
void checkIndex(void)
{
//Print thread's coords within a block and the block's
//coords within the grid
printf("Thread coords: (%d %d %d), Block coords: (%d %d %d)\n", threadIdx.x, threadIdx.y, threadIdx.z, blockIdx.x, blockIdx.y, blockIdx.z);
}
__global__
void sumArrays(float *A, float *B, float *C, unsigned int N)
{
unsigned int idx = blockIdx.x*blockDim.x + threadIdx.x;
if (idx < N)
C[idx] = A[idx] + B[idx];
}
__host__
void initialData(float *ip, unsigned int size)
{
// generate different seed for random number
time_t t;
srand((unsigned) time(&t));
int i;
for (i = 0; i < size; i++)
{
ip[i] = (float)(rand() & 0xFF) / 10.0f;
}
}
__host__
int main(int argc, char **argv)
{
int deviceId = 0;
hipSetDevice(deviceId);
unsigned int nElem = 1<<24;
size_t nBytes = nElem * sizeof(float);
printf("%u elements, %zu B\n", nElem, nBytes);
//Allocate vectors in host memory
float *h_A, *h_B, *h_C, *gpuRef;
h_A = (float *)malloc(nBytes);
h_B = (float *)malloc(nBytes);
h_C = (float *)malloc(nBytes);
gpuRef = (float *)malloc(nBytes);
//Allocate vectors in device memory
float *d_A, *d_B, *d_C;
CHECK(hipMalloc(&d_A, nBytes));
CHECK(hipMalloc(&d_B, nBytes));
CHECK(hipMalloc(&d_C, nBytes));
initialData(h_A, nElem);
initialData(h_B, nElem);
//Copy the vector data over the device memory
CHECK(hipMemcpy(d_A, h_A, nBytes, hipMemcpyHostToDevice));
CHECK(hipMemcpy(d_B, h_B, nBytes, hipMemcpyHostToDevice));
int deviceCount = 0, maxDevice = 0;
unsigned long long maxMemory = 0;
CHECK(hipGetDeviceCount(&deviceCount));
printf("Number of devices: %d\n", deviceCount);
if (deviceCount > 1)
{
int device;
for (device = 0; device < deviceCount; device++)
{
hipDeviceProp_t props;
CHECK(hipGetDeviceProperties(&props, device));
if (maxMemory < props.totalGlobalMem)
{
maxMemory = props.totalGlobalMem;
maxDevice = device;
}
}
CHECK(hipSetDevice(maxDevice));
printf("Device with largest total global memory: %d (%llu B)\n", maxDevice, maxMemory);
}
//cudaDeviceProp prop;
//CHECK(cudaGetDeviceProperties(&prop,
//Define the grid and block dimensions
unsigned int blockSize = 1024;
dim3 block(blockSize);
dim3 grid((nElem + block.x-1)/block.x);
printf("Block dim3: <%d %d %d>\n", block.x, block.y, block.z);
printf("Grid dim3: <%d %d %d>\n", grid.x, grid.y, grid.z);
unsigned int totalThreads = block.x*block.y*block.z*grid.x*grid.y*grid.z;
printf("Total threads: %u\n", totalThreads);
//Invoke the kernel on the device
//checkIndex<<<grid, block>>>();
//All kernel invocations must return from device
//before control returns to the host
//cudaDeviceSynchronize();
sumArrays<<<grid, block>>>(d_A, d_B, d_C, nElem);
//Copy the result vector back to the host
CHECK(hipMemcpy(gpuRef, d_C, nBytes, hipMemcpyDeviceToHost));
//Deallocate the device memory vectors
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
//Done using the device. Clean up all state on the device
//and flush profiling data.
hipDeviceReset();
//Deallocate the host memory vectors
free(h_A);
free(h_B);
free(h_C);
free(gpuRef);
return 0;
} | .text
.file "sumArraysOnHost.hip"
.globl _Z5CHECK10hipError_t # -- Begin function _Z5CHECK10hipError_t
.p2align 4, 0x90
.type _Z5CHECK10hipError_t,@function
_Z5CHECK10hipError_t: # @_Z5CHECK10hipError_t
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB0_2
# %bb.1:
retq
.LBB0_2:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq stderr(%rip), %rax
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $.L__func__._Z5CHECK10hipError_t, %ecx
movl %edi, %ebx
movq %rax, %rdi
movl $15, %r8d
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %r14
movl %ebx, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movq %r14, %rdi
movl %ebx, %edx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z5CHECK10hipError_t, .Lfunc_end0-_Z5CHECK10hipError_t
.cfi_endproc
# -- End function
.globl _Z25__device_stub__checkIndexv # -- Begin function _Z25__device_stub__checkIndexv
.p2align 4, 0x90
.type _Z25__device_stub__checkIndexv,@function
_Z25__device_stub__checkIndexv: # @_Z25__device_stub__checkIndexv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10checkIndexv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z25__device_stub__checkIndexv, .Lfunc_end1-_Z25__device_stub__checkIndexv
.cfi_endproc
# -- End function
.globl _Z24__device_stub__sumArraysPfS_S_j # -- Begin function _Z24__device_stub__sumArraysPfS_S_j
.p2align 4, 0x90
.type _Z24__device_stub__sumArraysPfS_S_j,@function
_Z24__device_stub__sumArraysPfS_S_j: # @_Z24__device_stub__sumArraysPfS_S_j
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9sumArraysPfS_S_j, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z24__device_stub__sumArraysPfS_S_j, .Lfunc_end2-_Z24__device_stub__sumArraysPfS_S_j
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z11initialDataPfj
.LCPI3_0:
.long 0x41200000 # float 10
.text
.globl _Z11initialDataPfj
.p2align 4, 0x90
.type _Z11initialDataPfj,@function
_Z11initialDataPfj: # @_Z11initialDataPfj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movq %rsp, %rdi
callq time
movl %eax, %edi
callq srand
testl %ebp, %ebp
je .LBB3_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss .LCPI3_0(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB3_2
.LBB3_3: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z11initialDataPfj, .Lfunc_end3-_Z11initialDataPfj
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x41200000 # float 10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1608, %rsp # imm = 0x648
.cfi_def_cfa_offset 1664
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %edi, %edi
callq hipSetDevice
movl $.L.str.3, %edi
movl $67108864, %edx # imm = 0x4000000
movl $16777216, %esi # imm = 0x1000000
xorl %eax, %eax
callq printf
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %rbx
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r14
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r13
leaq 32(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
testl %eax, %eax
jne .LBB4_1
# %bb.3: # %_Z5CHECK10hipError_t.exit
leaq 24(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
testl %eax, %eax
jne .LBB4_1
# %bb.4: # %_Z5CHECK10hipError_t.exit48
leaq 16(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
testl %eax, %eax
jne .LBB4_1
# %bb.5: # %_Z5CHECK10hipError_t.exit50
leaq 128(%rsp), %rdi
callq time
movl %eax, %edi
callq srand
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_6: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss .LCPI4_0(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq $16777216, %r15 # imm = 0x1000000
jne .LBB4_6
# %bb.7: # %_Z11initialDataPfj.exit
leaq 128(%rsp), %rdi
callq time
movl %eax, %edi
callq srand
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_8: # %.lr.ph.i51
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss .LCPI4_0(%rip), %xmm0
movss %xmm0, (%r14,%r15,4)
incq %r15
cmpq $16777216, %r15 # imm = 0x1000000
jne .LBB4_8
# %bb.9: # %_Z11initialDataPfj.exit55
movq 32(%rsp), %rdi
movl $67108864, %edx # imm = 0x4000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_1
# %bb.10: # %_Z5CHECK10hipError_t.exit57
movq 24(%rsp), %rdi
movl $67108864, %edx # imm = 0x4000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_1
# %bb.11: # %_Z5CHECK10hipError_t.exit59
movl $0, 12(%rsp)
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
testl %eax, %eax
jne .LBB4_1
# %bb.12: # %_Z5CHECK10hipError_t.exit61
movl 12(%rsp), %esi
xorl %r12d, %r12d
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
cmpl $2, 12(%rsp)
jl .LBB4_21
# %bb.13: # %.preheader
movq %r13, 48(%rsp) # 8-byte Spill
cmpl $0, 12(%rsp)
jle .LBB4_14
# %bb.15: # %.lr.ph
xorl %r12d, %r12d
xorl %r13d, %r13d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB4_16: # =>This Inner Loop Header: Depth=1
leaq 128(%rsp), %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB4_17
# %bb.18: # %_Z5CHECK10hipError_t.exit63
# in Loop: Header=BB4_16 Depth=1
movq 416(%rsp), %rax
cmpq %rax, %r13
cmovbeq %rax, %r13
cmovbl %ebp, %r12d
incl %ebp
cmpl 12(%rsp), %ebp
jl .LBB4_16
jmp .LBB4_19
.LBB4_14:
xorl %r13d, %r13d
.LBB4_19: # %._crit_edge
movl %r12d, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB4_1
# %bb.20: # %_Z5CHECK10hipError_t.exit65
movl $.L.str.5, %edi
movl %r12d, %esi
movq %r13, %rdx
xorl %eax, %eax
callq printf
movq 48(%rsp), %r13 # 8-byte Reload
.LBB4_21:
movl $.L.str.6, %edi
movl $1024, %esi # imm = 0x400
movl $1, %edx
movl $1, %ecx
xorl %eax, %eax
callq printf
movl $.L.str.7, %edi
movl $16384, %esi # imm = 0x4000
movl $1, %edx
movl $1, %ecx
xorl %eax, %eax
callq printf
movl $.L.str.8, %edi
movl $16777216, %esi # imm = 0x1000000
xorl %eax, %eax
callq printf
movabsq $4294968320, %rdx # imm = 0x100000400
leaq 15360(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_23
# %bb.22:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $16777216, 44(%rsp) # imm = 0x1000000
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 44(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z9sumArraysPfS_S_j, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_23:
movq 16(%rsp), %rsi
movl $67108864, %edx # imm = 0x4000000
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_1
# %bb.24: # %_Z5CHECK10hipError_t.exit67
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
callq hipDeviceReset
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r13, %rdi
callq free
xorl %eax, %eax
addq $1608, %rsp # imm = 0x648
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_17:
.cfi_def_cfa_offset 1664
movl %eax, %r15d
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $.L__func__._Z5CHECK10hipError_t, %ecx
movl $15, %r8d
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rbx
movl %r15d, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movq %rbx, %rdi
movl %r15d, %edx
jmp .LBB4_2
.LBB4_1:
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $.L__func__._Z5CHECK10hipError_t, %ecx
movl $15, %r8d
movl %eax, %ebx
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %r14
movl %ebx, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movq %r14, %rdi
movl %ebx, %edx
.LBB4_2:
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10checkIndexv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9sumArraysPfS_S_j, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error: %s:%s:%d, "
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/blessley/CudaCode/master/vectorSum/sumArraysOnHost.hip"
.size .L.str.1, 112
.type .L__func__._Z5CHECK10hipError_t,@object # @__func__._Z5CHECK10hipError_t
.L__func__._Z5CHECK10hipError_t:
.asciz "CHECK"
.size .L__func__._Z5CHECK10hipError_t, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "code:%d, reason: %s\n"
.size .L.str.2, 21
.type _Z10checkIndexv,@object # @_Z10checkIndexv
.section .rodata,"a",@progbits
.globl _Z10checkIndexv
.p2align 3, 0x0
_Z10checkIndexv:
.quad _Z25__device_stub__checkIndexv
.size _Z10checkIndexv, 8
.type _Z9sumArraysPfS_S_j,@object # @_Z9sumArraysPfS_S_j
.globl _Z9sumArraysPfS_S_j
.p2align 3, 0x0
_Z9sumArraysPfS_S_j:
.quad _Z24__device_stub__sumArraysPfS_S_j
.size _Z9sumArraysPfS_S_j, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "%u elements, %zu B\n"
.size .L.str.3, 20
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Number of devices: %d\n"
.size .L.str.4, 23
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Device with largest total global memory: %d (%llu B)\n"
.size .L.str.5, 54
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Block dim3: <%d %d %d>\n"
.size .L.str.6, 24
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Grid dim3: <%d %d %d>\n"
.size .L.str.7, 23
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Total threads: %u\n"
.size .L.str.8, 19
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10checkIndexv"
.size .L__unnamed_1, 16
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9sumArraysPfS_S_j"
.size .L__unnamed_2, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__checkIndexv
.addrsig_sym _Z24__device_stub__sumArraysPfS_S_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10checkIndexv
.addrsig_sym _Z9sumArraysPfS_S_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00011ae6_00000000-6_sumArraysOnHost.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CHECK"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/blessley/CudaCode/master/vectorSum/sumArraysOnHost.cu"
.section .rodata.str1.1
.LC2:
.string "Error: %s:%s:%d, "
.LC3:
.string "code:%d, reason: %s\n"
.text
.globl _Z5CHECK9cudaError
.type _Z5CHECK9cudaError, @function
_Z5CHECK9cudaError:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
ret
.L8:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edi, %ebx
movl $15, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z5CHECK9cudaError, .-_Z5CHECK9cudaError
.globl _Z11initialDataPfj
.type _Z11initialDataPfj, @function
_Z11initialDataPfj:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r12
movl %esi, %ebp
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
call time@PLT
movl %eax, %edi
call srand@PLT
testl %ebp, %ebp
je .L9
movq %r12, %rbx
movl %ebp, %ebp
leaq (%r12,%rbp,4), %rbp
.L11:
call rand@PLT
movzbl %al, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
divss .LC4(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L11
.L9:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z11initialDataPfj, .-_Z11initialDataPfj
.globl _Z29__device_stub__Z10checkIndexvv
.type _Z29__device_stub__Z10checkIndexvv, @function
_Z29__device_stub__Z10checkIndexvv:
.LFB2084:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10checkIndexv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z29__device_stub__Z10checkIndexvv, .-_Z29__device_stub__Z10checkIndexvv
.globl _Z10checkIndexv
.type _Z10checkIndexv, @function
_Z10checkIndexv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10checkIndexvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10checkIndexv, .-_Z10checkIndexv
.globl _Z33__device_stub__Z9sumArraysPfS_S_jPfS_S_j
.type _Z33__device_stub__Z9sumArraysPfS_S_jPfS_S_j, @function
_Z33__device_stub__Z9sumArraysPfS_S_jPfS_S_j:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9sumArraysPfS_S_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z33__device_stub__Z9sumArraysPfS_S_jPfS_S_j, .-_Z33__device_stub__Z9sumArraysPfS_S_jPfS_S_j
.globl _Z9sumArraysPfS_S_j
.type _Z9sumArraysPfS_S_j, @function
_Z9sumArraysPfS_S_j:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9sumArraysPfS_S_jPfS_S_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z9sumArraysPfS_S_j, .-_Z9sumArraysPfS_S_j
.section .rodata.str1.1
.LC5:
.string "%u elements, %zu B\n"
.LC6:
.string "Number of devices: %d\n"
.section .rodata.str1.8
.align 8
.LC7:
.string "Device with largest total global memory: %d (%llu B)\n"
.section .rodata.str1.1
.LC8:
.string "Block dim3: <%d %d %d>\n"
.LC9:
.string "Grid dim3: <%d %d %d>\n"
.LC10:
.string "Total threads: %u\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1128, %rsp
.cfi_def_cfa_offset 1184
movq %fs:40, %rax
movq %rax, 1112(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
movl $67108864, %ecx
movl $16777216, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $67108864, %edi
call malloc@PLT
movq %rax, %r13
movl $67108864, %edi
call malloc@PLT
movq %rax, %r12
movl $67108864, %edi
call malloc@PLT
movq %rax, %r15
leaq 32(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
movl %eax, %edi
call _Z5CHECK9cudaError
leaq 40(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
movl %eax, %edi
call _Z5CHECK9cudaError
leaq 48(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
movl %eax, %edi
call _Z5CHECK9cudaError
movl $16777216, %esi
movq %r13, %rdi
call _Z11initialDataPfj
movl $16777216, %esi
movq %r12, %rdi
call _Z11initialDataPfj
movl $1, %ecx
movl $67108864, %edx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z5CHECK9cudaError
movl $1, %ecx
movl $67108864, %edx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z5CHECK9cudaError
movl $0, 28(%rsp)
leaq 28(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl %eax, %edi
call _Z5CHECK9cudaError
movl 28(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $1, 28(%rsp)
jle .L33
movl $0, %ebx
movl $0, %ebp
movl $0, 12(%rsp)
leaq 80(%rsp), %r14
jmp .L35
.L34:
addl $1, %ebx
cmpl %ebx, 28(%rsp)
jle .L41
.L35:
movl %ebx, %esi
movq %r14, %rdi
call cudaGetDeviceProperties_v2@PLT
movl %eax, %edi
call _Z5CHECK9cudaError
movq 368(%rsp), %rax
cmpq %rax, %rbp
jnb .L34
movq %rax, %rbp
movl %ebx, 12(%rsp)
jmp .L34
.L41:
movl 12(%rsp), %ebx
movl %ebx, %edi
call cudaSetDevice@PLT
movl %eax, %edi
call _Z5CHECK9cudaError
movq %rbp, %rcx
movl %ebx, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L33:
movl $1, %r8d
movl $1, %ecx
movl $1024, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %r8d
movl $1, %ecx
movl $16384, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16777216, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16384, 68(%rsp)
movl $1, 72(%rsp)
movl $1024, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movl $1, %ecx
movq 68(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L36:
movl $2, %ecx
movl $67108864, %edx
movq 48(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z5CHECK9cudaError
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
call cudaDeviceReset@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq 1112(%rsp), %rax
subq %fs:40, %rax
jne .L43
movl $0, %eax
addq $1128, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
movl $16777216, %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z33__device_stub__Z9sumArraysPfS_S_jPfS_S_j
jmp .L36
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z9sumArraysPfS_S_j"
.LC12:
.string "_Z10checkIndexv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z9sumArraysPfS_S_j(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z10checkIndexv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 1092616192
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sumArraysOnHost.hip"
.globl _Z5CHECK10hipError_t # -- Begin function _Z5CHECK10hipError_t
.p2align 4, 0x90
.type _Z5CHECK10hipError_t,@function
_Z5CHECK10hipError_t: # @_Z5CHECK10hipError_t
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB0_2
# %bb.1:
retq
.LBB0_2:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq stderr(%rip), %rax
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $.L__func__._Z5CHECK10hipError_t, %ecx
movl %edi, %ebx
movq %rax, %rdi
movl $15, %r8d
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %r14
movl %ebx, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movq %r14, %rdi
movl %ebx, %edx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z5CHECK10hipError_t, .Lfunc_end0-_Z5CHECK10hipError_t
.cfi_endproc
# -- End function
.globl _Z25__device_stub__checkIndexv # -- Begin function _Z25__device_stub__checkIndexv
.p2align 4, 0x90
.type _Z25__device_stub__checkIndexv,@function
_Z25__device_stub__checkIndexv: # @_Z25__device_stub__checkIndexv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10checkIndexv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z25__device_stub__checkIndexv, .Lfunc_end1-_Z25__device_stub__checkIndexv
.cfi_endproc
# -- End function
.globl _Z24__device_stub__sumArraysPfS_S_j # -- Begin function _Z24__device_stub__sumArraysPfS_S_j
.p2align 4, 0x90
.type _Z24__device_stub__sumArraysPfS_S_j,@function
_Z24__device_stub__sumArraysPfS_S_j: # @_Z24__device_stub__sumArraysPfS_S_j
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9sumArraysPfS_S_j, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z24__device_stub__sumArraysPfS_S_j, .Lfunc_end2-_Z24__device_stub__sumArraysPfS_S_j
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z11initialDataPfj
.LCPI3_0:
.long 0x41200000 # float 10
.text
.globl _Z11initialDataPfj
.p2align 4, 0x90
.type _Z11initialDataPfj,@function
_Z11initialDataPfj: # @_Z11initialDataPfj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movq %rsp, %rdi
callq time
movl %eax, %edi
callq srand
testl %ebp, %ebp
je .LBB3_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss .LCPI3_0(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB3_2
.LBB3_3: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z11initialDataPfj, .Lfunc_end3-_Z11initialDataPfj
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x41200000 # float 10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1608, %rsp # imm = 0x648
.cfi_def_cfa_offset 1664
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %edi, %edi
callq hipSetDevice
movl $.L.str.3, %edi
movl $67108864, %edx # imm = 0x4000000
movl $16777216, %esi # imm = 0x1000000
xorl %eax, %eax
callq printf
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %rbx
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r14
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r13
leaq 32(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
testl %eax, %eax
jne .LBB4_1
# %bb.3: # %_Z5CHECK10hipError_t.exit
leaq 24(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
testl %eax, %eax
jne .LBB4_1
# %bb.4: # %_Z5CHECK10hipError_t.exit48
leaq 16(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
testl %eax, %eax
jne .LBB4_1
# %bb.5: # %_Z5CHECK10hipError_t.exit50
leaq 128(%rsp), %rdi
callq time
movl %eax, %edi
callq srand
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_6: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss .LCPI4_0(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq $16777216, %r15 # imm = 0x1000000
jne .LBB4_6
# %bb.7: # %_Z11initialDataPfj.exit
leaq 128(%rsp), %rdi
callq time
movl %eax, %edi
callq srand
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_8: # %.lr.ph.i51
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss .LCPI4_0(%rip), %xmm0
movss %xmm0, (%r14,%r15,4)
incq %r15
cmpq $16777216, %r15 # imm = 0x1000000
jne .LBB4_8
# %bb.9: # %_Z11initialDataPfj.exit55
movq 32(%rsp), %rdi
movl $67108864, %edx # imm = 0x4000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_1
# %bb.10: # %_Z5CHECK10hipError_t.exit57
movq 24(%rsp), %rdi
movl $67108864, %edx # imm = 0x4000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_1
# %bb.11: # %_Z5CHECK10hipError_t.exit59
movl $0, 12(%rsp)
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
testl %eax, %eax
jne .LBB4_1
# %bb.12: # %_Z5CHECK10hipError_t.exit61
movl 12(%rsp), %esi
xorl %r12d, %r12d
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
cmpl $2, 12(%rsp)
jl .LBB4_21
# %bb.13: # %.preheader
movq %r13, 48(%rsp) # 8-byte Spill
cmpl $0, 12(%rsp)
jle .LBB4_14
# %bb.15: # %.lr.ph
xorl %r12d, %r12d
xorl %r13d, %r13d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB4_16: # =>This Inner Loop Header: Depth=1
leaq 128(%rsp), %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB4_17
# %bb.18: # %_Z5CHECK10hipError_t.exit63
# in Loop: Header=BB4_16 Depth=1
movq 416(%rsp), %rax
cmpq %rax, %r13
cmovbeq %rax, %r13
cmovbl %ebp, %r12d
incl %ebp
cmpl 12(%rsp), %ebp
jl .LBB4_16
jmp .LBB4_19
.LBB4_14:
xorl %r13d, %r13d
.LBB4_19: # %._crit_edge
movl %r12d, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB4_1
# %bb.20: # %_Z5CHECK10hipError_t.exit65
movl $.L.str.5, %edi
movl %r12d, %esi
movq %r13, %rdx
xorl %eax, %eax
callq printf
movq 48(%rsp), %r13 # 8-byte Reload
.LBB4_21:
movl $.L.str.6, %edi
movl $1024, %esi # imm = 0x400
movl $1, %edx
movl $1, %ecx
xorl %eax, %eax
callq printf
movl $.L.str.7, %edi
movl $16384, %esi # imm = 0x4000
movl $1, %edx
movl $1, %ecx
xorl %eax, %eax
callq printf
movl $.L.str.8, %edi
movl $16777216, %esi # imm = 0x1000000
xorl %eax, %eax
callq printf
movabsq $4294968320, %rdx # imm = 0x100000400
leaq 15360(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_23
# %bb.22:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $16777216, 44(%rsp) # imm = 0x1000000
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 44(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z9sumArraysPfS_S_j, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_23:
movq 16(%rsp), %rsi
movl $67108864, %edx # imm = 0x4000000
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_1
# %bb.24: # %_Z5CHECK10hipError_t.exit67
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
callq hipDeviceReset
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r13, %rdi
callq free
xorl %eax, %eax
addq $1608, %rsp # imm = 0x648
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_17:
.cfi_def_cfa_offset 1664
movl %eax, %r15d
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $.L__func__._Z5CHECK10hipError_t, %ecx
movl $15, %r8d
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rbx
movl %r15d, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movq %rbx, %rdi
movl %r15d, %edx
jmp .LBB4_2
.LBB4_1:
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $.L__func__._Z5CHECK10hipError_t, %ecx
movl $15, %r8d
movl %eax, %ebx
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %r14
movl %ebx, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movq %r14, %rdi
movl %ebx, %edx
.LBB4_2:
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10checkIndexv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9sumArraysPfS_S_j, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error: %s:%s:%d, "
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/blessley/CudaCode/master/vectorSum/sumArraysOnHost.hip"
.size .L.str.1, 112
.type .L__func__._Z5CHECK10hipError_t,@object # @__func__._Z5CHECK10hipError_t
.L__func__._Z5CHECK10hipError_t:
.asciz "CHECK"
.size .L__func__._Z5CHECK10hipError_t, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "code:%d, reason: %s\n"
.size .L.str.2, 21
.type _Z10checkIndexv,@object # @_Z10checkIndexv
.section .rodata,"a",@progbits
.globl _Z10checkIndexv
.p2align 3, 0x0
_Z10checkIndexv:
.quad _Z25__device_stub__checkIndexv
.size _Z10checkIndexv, 8
.type _Z9sumArraysPfS_S_j,@object # @_Z9sumArraysPfS_S_j
.globl _Z9sumArraysPfS_S_j
.p2align 3, 0x0
_Z9sumArraysPfS_S_j:
.quad _Z24__device_stub__sumArraysPfS_S_j
.size _Z9sumArraysPfS_S_j, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "%u elements, %zu B\n"
.size .L.str.3, 20
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Number of devices: %d\n"
.size .L.str.4, 23
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Device with largest total global memory: %d (%llu B)\n"
.size .L.str.5, 54
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Block dim3: <%d %d %d>\n"
.size .L.str.6, 24
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Grid dim3: <%d %d %d>\n"
.size .L.str.7, 23
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Total threads: %u\n"
.size .L.str.8, 19
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10checkIndexv"
.size .L__unnamed_1, 16
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9sumArraysPfS_S_j"
.size .L__unnamed_2, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__checkIndexv
.addrsig_sym _Z24__device_stub__sumArraysPfS_S_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10checkIndexv
.addrsig_sym _Z9sumArraysPfS_S_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#define CHECK(call) \
{ \
cudaError_t err = call; \
if (err != cudaSuccess) \
{ \
printf("%s in %s at line %d!\n", cudaGetErrorString(err), __FILE__, __LINE__); \
exit(EXIT_FAILURE); \
} \
}
__global__ void cubeVecKernel(int *in, int *out, int n)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n)
{
out[i] = in[i] * in[i] * in[i];
}
}
void cubeVec(int *in, int *out, int n, bool useDevice = false)
{
if (useDevice == false)
{
for (int i = 0; i < n; i++)
{
out[i] = in[i] * in[i] * in[i];
}
}
else // Use device
{
// Host allocates memories on device
int *d_in, *d_out;
CHECK(cudaMalloc(&d_in, n * sizeof(int)));
CHECK(cudaMalloc(&d_out, n * sizeof(int)));
// Host copies data to device memories
CHECK(cudaMemcpy(d_in, in, n * sizeof(int), cudaMemcpyHostToDevice));
// Host invokes kernel function to add vectors on device
dim3 blockSize(512);
dim3 gridSize((n - 1) / blockSize.x + 1);
cubeVecKernel<<<gridSize, blockSize>>>(d_in, d_out, n);
// Host copies result from device memory
CHECK(cudaMemcpy(out, d_out, n * sizeof(int), cudaMemcpyDeviceToHost));
// Host frees device memories
CHECK(cudaFree(d_in));
CHECK(cudaFree(d_out));
}
}
int main()
{
int n; // Vector size
int *in; // Input vectors
int *out, *correctOut; // Output vector
// Input data into "n"
n = 100000;
// Allocate memories for "in", "out"
in = (int *)malloc(n * sizeof(int));
out = (int *)malloc(n * sizeof(int));
correctOut = (int *)malloc(n * sizeof(int));
// Input data into "in"
for (int i = 0; i < n; i++)
{
in[i] = rand() & 0xff; // Random int in [0, 255]
}
// Cube vec on host
cubeVec(in, correctOut, n);
// Cube vec on device
cubeVec(in, out, n, true);
// Check correctness
for (int i = 0; i < n; i++)
{
if (out[i] != correctOut[i])
{
printf("INCORRECT :(\n");
return 1;
}
}
printf("CORRECT :)\n");
} | code for sm_80
Function : _Z13cubeVecKernelPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0205 */
/*00b0*/ IMAD R7, R2, R2, RZ ; /* 0x0000000202077224 */
/* 0x004fc800078e02ff */
/*00c0*/ IMAD R7, R2, R7, RZ ; /* 0x0000000702077224 */
/* 0x000fca00078e02ff */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define CHECK(call) \
{ \
cudaError_t err = call; \
if (err != cudaSuccess) \
{ \
printf("%s in %s at line %d!\n", cudaGetErrorString(err), __FILE__, __LINE__); \
exit(EXIT_FAILURE); \
} \
}
__global__ void cubeVecKernel(int *in, int *out, int n)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n)
{
out[i] = in[i] * in[i] * in[i];
}
}
void cubeVec(int *in, int *out, int n, bool useDevice = false)
{
if (useDevice == false)
{
for (int i = 0; i < n; i++)
{
out[i] = in[i] * in[i] * in[i];
}
}
else // Use device
{
// Host allocates memories on device
int *d_in, *d_out;
CHECK(cudaMalloc(&d_in, n * sizeof(int)));
CHECK(cudaMalloc(&d_out, n * sizeof(int)));
// Host copies data to device memories
CHECK(cudaMemcpy(d_in, in, n * sizeof(int), cudaMemcpyHostToDevice));
// Host invokes kernel function to add vectors on device
dim3 blockSize(512);
dim3 gridSize((n - 1) / blockSize.x + 1);
cubeVecKernel<<<gridSize, blockSize>>>(d_in, d_out, n);
// Host copies result from device memory
CHECK(cudaMemcpy(out, d_out, n * sizeof(int), cudaMemcpyDeviceToHost));
// Host frees device memories
CHECK(cudaFree(d_in));
CHECK(cudaFree(d_out));
}
}
int main()
{
int n; // Vector size
int *in; // Input vectors
int *out, *correctOut; // Output vector
// Input data into "n"
n = 100000;
// Allocate memories for "in", "out"
in = (int *)malloc(n * sizeof(int));
out = (int *)malloc(n * sizeof(int));
correctOut = (int *)malloc(n * sizeof(int));
// Input data into "in"
for (int i = 0; i < n; i++)
{
in[i] = rand() & 0xff; // Random int in [0, 255]
}
// Cube vec on host
cubeVec(in, correctOut, n);
// Cube vec on device
cubeVec(in, out, n, true);
// Check correctness
for (int i = 0; i < n; i++)
{
if (out[i] != correctOut[i])
{
printf("INCORRECT :(\n");
return 1;
}
}
printf("CORRECT :)\n");
} | .file "tmpxft_0002e3ae_00000000-6_VecCube.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z13cubeVecKernelPiS_iPiS_i
.type _Z36__device_stub__Z13cubeVecKernelPiS_iPiS_i, @function
_Z36__device_stub__Z13cubeVecKernelPiS_iPiS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13cubeVecKernelPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z36__device_stub__Z13cubeVecKernelPiS_iPiS_i, .-_Z36__device_stub__Z13cubeVecKernelPiS_iPiS_i
.globl _Z13cubeVecKernelPiS_i
.type _Z13cubeVecKernelPiS_i, @function
_Z13cubeVecKernelPiS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13cubeVecKernelPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z13cubeVecKernelPiS_i, .-_Z13cubeVecKernelPiS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/haunt98/learn-cuda/master/VecCube.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%s in %s at line %d!\n"
.text
.globl _Z7cubeVecPiS_ib
.type _Z7cubeVecPiS_ib, @function
_Z7cubeVecPiS_ib:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbp
movq %rsi, %rbx
movl %edx, %r12d
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
testb %cl, %cl
jne .L12
testl %edx, %edx
jle .L11
movslq %edx, %rsi
salq $2, %rsi
.L14:
movl 0(%rbp,%rax), %ecx
movl %ecx, %edx
imull %ecx, %edx
imull %ecx, %edx
movl %edx, (%rbx,%rax)
addq $4, %rax
cmpq %rsi, %rax
jne .L14
.L11:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movslq %edx, %r13
salq $2, %r13
movq %rsp, %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L26
leaq 8(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L27
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L28
movl $1, 20(%rsp)
leal -1(%r12), %eax
shrl $9, %eax
addl $1, %eax
movl %eax, 28(%rsp)
movl $1, 32(%rsp)
movl $512, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L18:
movl $2, %ecx
movq %r13, %rdx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L30
movq (%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L31
movq 8(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
je .L11
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $51, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L26:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $35, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L27:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $36, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L28:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $39, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L29:
movl %r12d, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z36__device_stub__Z13cubeVecKernelPiS_iPiS_i
jmp .L18
.L30:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $47, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L31:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $50, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z7cubeVecPiS_ib, .-_Z7cubeVecPiS_ib
.section .rodata.str1.1
.LC2:
.string "INCORRECT :(\n"
.LC3:
.string "CORRECT :)\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl $400000, %edi
call malloc@PLT
movq %rax, %r14
movl $400000, %edi
call malloc@PLT
movq %rax, %r12
movl $400000, %edi
call malloc@PLT
movq %rax, %r13
movq %r14, %rbx
leaq 400000(%r14), %rbp
.L33:
call rand@PLT
movzbl %al, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L33
movl $0, %ecx
movl $100000, %edx
movq %r13, %rsi
movq %r14, %rdi
call _Z7cubeVecPiS_ib
movl $1, %ecx
movl $100000, %edx
movq %r12, %rsi
movq %r14, %rdi
call _Z7cubeVecPiS_ib
movl $0, %eax
.L36:
movl 0(%r13,%rax), %edx
cmpl %edx, (%r12,%rax)
jne .L40
addq $4, %rax
cmpq $400000, %rax
jne .L36
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L32
.L40:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
.L32:
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z13cubeVecKernelPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z13cubeVecKernelPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define CHECK(call) \
{ \
cudaError_t err = call; \
if (err != cudaSuccess) \
{ \
printf("%s in %s at line %d!\n", cudaGetErrorString(err), __FILE__, __LINE__); \
exit(EXIT_FAILURE); \
} \
}
__global__ void cubeVecKernel(int *in, int *out, int n)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n)
{
out[i] = in[i] * in[i] * in[i];
}
}
void cubeVec(int *in, int *out, int n, bool useDevice = false)
{
if (useDevice == false)
{
for (int i = 0; i < n; i++)
{
out[i] = in[i] * in[i] * in[i];
}
}
else // Use device
{
// Host allocates memories on device
int *d_in, *d_out;
CHECK(cudaMalloc(&d_in, n * sizeof(int)));
CHECK(cudaMalloc(&d_out, n * sizeof(int)));
// Host copies data to device memories
CHECK(cudaMemcpy(d_in, in, n * sizeof(int), cudaMemcpyHostToDevice));
// Host invokes kernel function to add vectors on device
dim3 blockSize(512);
dim3 gridSize((n - 1) / blockSize.x + 1);
cubeVecKernel<<<gridSize, blockSize>>>(d_in, d_out, n);
// Host copies result from device memory
CHECK(cudaMemcpy(out, d_out, n * sizeof(int), cudaMemcpyDeviceToHost));
// Host frees device memories
CHECK(cudaFree(d_in));
CHECK(cudaFree(d_out));
}
}
int main()
{
int n; // Vector size
int *in; // Input vectors
int *out, *correctOut; // Output vector
// Input data into "n"
n = 100000;
// Allocate memories for "in", "out"
in = (int *)malloc(n * sizeof(int));
out = (int *)malloc(n * sizeof(int));
correctOut = (int *)malloc(n * sizeof(int));
// Input data into "in"
for (int i = 0; i < n; i++)
{
in[i] = rand() & 0xff; // Random int in [0, 255]
}
// Cube vec on host
cubeVec(in, correctOut, n);
// Cube vec on device
cubeVec(in, out, n, true);
// Check correctness
for (int i = 0; i < n; i++)
{
if (out[i] != correctOut[i])
{
printf("INCORRECT :(\n");
return 1;
}
}
printf("CORRECT :)\n");
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define CHECK(call) \
{ \
hipError_t err = call; \
if (err != hipSuccess) \
{ \
printf("%s in %s at line %d!\n", hipGetErrorString(err), __FILE__, __LINE__); \
exit(EXIT_FAILURE); \
} \
}
__global__ void cubeVecKernel(int *in, int *out, int n)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n)
{
out[i] = in[i] * in[i] * in[i];
}
}
void cubeVec(int *in, int *out, int n, bool useDevice = false)
{
if (useDevice == false)
{
for (int i = 0; i < n; i++)
{
out[i] = in[i] * in[i] * in[i];
}
}
else // Use device
{
// Host allocates memories on device
int *d_in, *d_out;
CHECK(hipMalloc(&d_in, n * sizeof(int)));
CHECK(hipMalloc(&d_out, n * sizeof(int)));
// Host copies data to device memories
CHECK(hipMemcpy(d_in, in, n * sizeof(int), hipMemcpyHostToDevice));
// Host invokes kernel function to add vectors on device
dim3 blockSize(512);
dim3 gridSize((n - 1) / blockSize.x + 1);
cubeVecKernel<<<gridSize, blockSize>>>(d_in, d_out, n);
// Host copies result from device memory
CHECK(hipMemcpy(out, d_out, n * sizeof(int), hipMemcpyDeviceToHost));
// Host frees device memories
CHECK(hipFree(d_in));
CHECK(hipFree(d_out));
}
}
int main()
{
int n; // Vector size
int *in; // Input vectors
int *out, *correctOut; // Output vector
// Input data into "n"
n = 100000;
// Allocate memories for "in", "out"
in = (int *)malloc(n * sizeof(int));
out = (int *)malloc(n * sizeof(int));
correctOut = (int *)malloc(n * sizeof(int));
// Input data into "in"
for (int i = 0; i < n; i++)
{
in[i] = rand() & 0xff; // Random int in [0, 255]
}
// Cube vec on host
cubeVec(in, correctOut, n);
// Cube vec on device
cubeVec(in, out, n, true);
// Check correctness
for (int i = 0; i < n; i++)
{
if (out[i] != correctOut[i])
{
printf("INCORRECT :(\n");
return 1;
}
}
printf("CORRECT :)\n");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define CHECK(call) \
{ \
hipError_t err = call; \
if (err != hipSuccess) \
{ \
printf("%s in %s at line %d!\n", hipGetErrorString(err), __FILE__, __LINE__); \
exit(EXIT_FAILURE); \
} \
}
__global__ void cubeVecKernel(int *in, int *out, int n)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n)
{
out[i] = in[i] * in[i] * in[i];
}
}
void cubeVec(int *in, int *out, int n, bool useDevice = false)
{
if (useDevice == false)
{
for (int i = 0; i < n; i++)
{
out[i] = in[i] * in[i] * in[i];
}
}
else // Use device
{
// Host allocates memories on device
int *d_in, *d_out;
CHECK(hipMalloc(&d_in, n * sizeof(int)));
CHECK(hipMalloc(&d_out, n * sizeof(int)));
// Host copies data to device memories
CHECK(hipMemcpy(d_in, in, n * sizeof(int), hipMemcpyHostToDevice));
// Host invokes kernel function to add vectors on device
dim3 blockSize(512);
dim3 gridSize((n - 1) / blockSize.x + 1);
cubeVecKernel<<<gridSize, blockSize>>>(d_in, d_out, n);
// Host copies result from device memory
CHECK(hipMemcpy(out, d_out, n * sizeof(int), hipMemcpyDeviceToHost));
// Host frees device memories
CHECK(hipFree(d_in));
CHECK(hipFree(d_out));
}
}
int main()
{
int n; // Vector size
int *in; // Input vectors
int *out, *correctOut; // Output vector
// Input data into "n"
n = 100000;
// Allocate memories for "in", "out"
in = (int *)malloc(n * sizeof(int));
out = (int *)malloc(n * sizeof(int));
correctOut = (int *)malloc(n * sizeof(int));
// Input data into "in"
for (int i = 0; i < n; i++)
{
in[i] = rand() & 0xff; // Random int in [0, 255]
}
// Cube vec on host
cubeVec(in, correctOut, n);
// Cube vec on device
cubeVec(in, out, n, true);
// Check correctness
for (int i = 0; i < n; i++)
{
if (out[i] != correctOut[i])
{
printf("INCORRECT :(\n");
return 1;
}
}
printf("CORRECT :)\n");
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13cubeVecKernelPiS_i
.globl _Z13cubeVecKernelPiS_i
.p2align 8
.type _Z13cubeVecKernelPiS_i,@function
_Z13cubeVecKernelPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v3, v2, v2
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13cubeVecKernelPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13cubeVecKernelPiS_i, .Lfunc_end0-_Z13cubeVecKernelPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13cubeVecKernelPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13cubeVecKernelPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define CHECK(call) \
{ \
hipError_t err = call; \
if (err != hipSuccess) \
{ \
printf("%s in %s at line %d!\n", hipGetErrorString(err), __FILE__, __LINE__); \
exit(EXIT_FAILURE); \
} \
}
__global__ void cubeVecKernel(int *in, int *out, int n)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n)
{
out[i] = in[i] * in[i] * in[i];
}
}
void cubeVec(int *in, int *out, int n, bool useDevice = false)
{
if (useDevice == false)
{
for (int i = 0; i < n; i++)
{
out[i] = in[i] * in[i] * in[i];
}
}
else // Use device
{
// Host allocates memories on device
int *d_in, *d_out;
CHECK(hipMalloc(&d_in, n * sizeof(int)));
CHECK(hipMalloc(&d_out, n * sizeof(int)));
// Host copies data to device memories
CHECK(hipMemcpy(d_in, in, n * sizeof(int), hipMemcpyHostToDevice));
// Host invokes kernel function to add vectors on device
dim3 blockSize(512);
dim3 gridSize((n - 1) / blockSize.x + 1);
cubeVecKernel<<<gridSize, blockSize>>>(d_in, d_out, n);
// Host copies result from device memory
CHECK(hipMemcpy(out, d_out, n * sizeof(int), hipMemcpyDeviceToHost));
// Host frees device memories
CHECK(hipFree(d_in));
CHECK(hipFree(d_out));
}
}
int main()
{
int n; // Vector size
int *in; // Input vectors
int *out, *correctOut; // Output vector
// Input data into "n"
n = 100000;
// Allocate memories for "in", "out"
in = (int *)malloc(n * sizeof(int));
out = (int *)malloc(n * sizeof(int));
correctOut = (int *)malloc(n * sizeof(int));
// Input data into "in"
for (int i = 0; i < n; i++)
{
in[i] = rand() & 0xff; // Random int in [0, 255]
}
// Cube vec on host
cubeVec(in, correctOut, n);
// Cube vec on device
cubeVec(in, out, n, true);
// Check correctness
for (int i = 0; i < n; i++)
{
if (out[i] != correctOut[i])
{
printf("INCORRECT :(\n");
return 1;
}
}
printf("CORRECT :)\n");
} | .text
.file "VecCube.hip"
.globl _Z28__device_stub__cubeVecKernelPiS_i # -- Begin function _Z28__device_stub__cubeVecKernelPiS_i
.p2align 4, 0x90
.type _Z28__device_stub__cubeVecKernelPiS_i,@function
_Z28__device_stub__cubeVecKernelPiS_i: # @_Z28__device_stub__cubeVecKernelPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13cubeVecKernelPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__cubeVecKernelPiS_i, .Lfunc_end0-_Z28__device_stub__cubeVecKernelPiS_i
.cfi_endproc
# -- End function
.globl _Z7cubeVecPiS_ib # -- Begin function _Z7cubeVecPiS_ib
.p2align 4, 0x90
.type _Z7cubeVecPiS_ib,@function
_Z7cubeVecPiS_ib: # @_Z7cubeVecPiS_ib
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %edx, %r15d
movq %rsi, %rbx
movq %rdi, %r12
testl %ecx, %ecx
je .LBB1_1
# %bb.5:
movslq %r15d, %r14
shlq $2, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_6
# %bb.8:
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_9
# %bb.10:
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_11
# %bb.12:
leal -1(%r15), %eax
shrl $9, %eax
movabsq $4294967296, %rdx # imm = 0x100000000
leaq (%rdx,%rax), %rdi
incq %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_14
# %bb.13:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r15d, 28(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13cubeVecKernelPiS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_14:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_15
# %bb.16:
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_17
# %bb.18:
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB1_4
# %bb.19:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $53, %ecx
jmp .LBB1_7
.LBB1_1: # %.preheader
testl %r15d, %r15d
jle .LBB1_4
# %bb.2: # %.lr.ph.preheader
movl %r15d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%r12,%rcx,4), %edx
movl %edx, %esi
imull %edx, %esi
imull %edx, %esi
movl %esi, (%rbx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_3
.LBB1_4: # %.loopexit
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_6:
.cfi_def_cfa_offset 160
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $37, %ecx
jmp .LBB1_7
.LBB1_9:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $38, %ecx
jmp .LBB1_7
.LBB1_11:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $41, %ecx
jmp .LBB1_7
.LBB1_15:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $49, %ecx
jmp .LBB1_7
.LBB1_17:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $52, %ecx
.LBB1_7:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z7cubeVecPiS_ib, .Lfunc_end1-_Z7cubeVecPiS_ib
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $400000, %edi # imm = 0x61A80
callq malloc
movq %rax, %r15
movl $400000, %edi # imm = 0x61A80
callq malloc
movq %rax, %rbx
movl $400000, %edi # imm = 0x61A80
callq malloc
movq %rax, %r14
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
movl %eax, (%r15,%r12,4)
incq %r12
cmpq $100000, %r12 # imm = 0x186A0
jne .LBB2_1
# %bb.2: # %.lr.ph.i.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl (%r15,%rax,4), %ecx
movl %ecx, %edx
imull %ecx, %edx
imull %ecx, %edx
movl %edx, (%r14,%rax,4)
incq %rax
cmpq $100000, %rax # imm = 0x186A0
jne .LBB2_3
# %bb.4: # %_Z7cubeVecPiS_ib.exit
movl $1, %ebp
movq %r15, %rdi
movq %rbx, %rsi
movl $100000, %edx # imm = 0x186A0
movl $1, %ecx
callq _Z7cubeVecPiS_ib
movl (%rbx), %eax
cmpl (%r14), %eax
jne .LBB2_5
# %bb.6: # %.lr.ph.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_7: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cmpq $99999, %rax # imm = 0x1869F
je .LBB2_11
# %bb.8: # in Loop: Header=BB2_7 Depth=1
movl 4(%rbx,%rax,4), %edx
leaq 1(%rax), %rcx
cmpl 4(%r14,%rax,4), %edx
movq %rcx, %rax
je .LBB2_7
# %bb.9: # %._crit_edge.loopexit
decq %rcx
cmpq $99999, %rcx # imm = 0x1869F
setae %bl
jmp .LBB2_10
.LBB2_5:
xorl %ebx, %ebx
.LBB2_10: # %._crit_edge
movl $.Lstr, %edi
callq puts@PLT
testb %bl, %bl
je .LBB2_14
.LBB2_13:
movl $.Lstr.1, %edi
callq puts@PLT
.LBB2_14:
movl %ebp, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_11: # %.loopexit.loopexit
.cfi_def_cfa_offset 48
setae %bl
xorl %ebp, %ebp
testb %bl, %bl
jne .LBB2_13
jmp .LBB2_14
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13cubeVecKernelPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13cubeVecKernelPiS_i,@object # @_Z13cubeVecKernelPiS_i
.section .rodata,"a",@progbits
.globl _Z13cubeVecKernelPiS_i
.p2align 3, 0x0
_Z13cubeVecKernelPiS_i:
.quad _Z28__device_stub__cubeVecKernelPiS_i
.size _Z13cubeVecKernelPiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s in %s at line %d!\n"
.size .L.str, 22
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/haunt98/learn-cuda/master/VecCube.hip"
.size .L.str.1, 95
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13cubeVecKernelPiS_i"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "INCORRECT :("
.size .Lstr, 13
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "CORRECT :)"
.size .Lstr.1, 11
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__cubeVecKernelPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13cubeVecKernelPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13cubeVecKernelPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0205 */
/*00b0*/ IMAD R7, R2, R2, RZ ; /* 0x0000000202077224 */
/* 0x004fc800078e02ff */
/*00c0*/ IMAD R7, R2, R7, RZ ; /* 0x0000000702077224 */
/* 0x000fca00078e02ff */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13cubeVecKernelPiS_i
.globl _Z13cubeVecKernelPiS_i
.p2align 8
.type _Z13cubeVecKernelPiS_i,@function
_Z13cubeVecKernelPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v3, v2, v2
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13cubeVecKernelPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13cubeVecKernelPiS_i, .Lfunc_end0-_Z13cubeVecKernelPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13cubeVecKernelPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13cubeVecKernelPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002e3ae_00000000-6_VecCube.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z13cubeVecKernelPiS_iPiS_i
.type _Z36__device_stub__Z13cubeVecKernelPiS_iPiS_i, @function
_Z36__device_stub__Z13cubeVecKernelPiS_iPiS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13cubeVecKernelPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z36__device_stub__Z13cubeVecKernelPiS_iPiS_i, .-_Z36__device_stub__Z13cubeVecKernelPiS_iPiS_i
.globl _Z13cubeVecKernelPiS_i
.type _Z13cubeVecKernelPiS_i, @function
_Z13cubeVecKernelPiS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13cubeVecKernelPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z13cubeVecKernelPiS_i, .-_Z13cubeVecKernelPiS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/haunt98/learn-cuda/master/VecCube.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%s in %s at line %d!\n"
.text
.globl _Z7cubeVecPiS_ib
.type _Z7cubeVecPiS_ib, @function
_Z7cubeVecPiS_ib:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbp
movq %rsi, %rbx
movl %edx, %r12d
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
testb %cl, %cl
jne .L12
testl %edx, %edx
jle .L11
movslq %edx, %rsi
salq $2, %rsi
.L14:
movl 0(%rbp,%rax), %ecx
movl %ecx, %edx
imull %ecx, %edx
imull %ecx, %edx
movl %edx, (%rbx,%rax)
addq $4, %rax
cmpq %rsi, %rax
jne .L14
.L11:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movslq %edx, %r13
salq $2, %r13
movq %rsp, %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L26
leaq 8(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L27
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L28
movl $1, 20(%rsp)
leal -1(%r12), %eax
shrl $9, %eax
addl $1, %eax
movl %eax, 28(%rsp)
movl $1, 32(%rsp)
movl $512, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L18:
movl $2, %ecx
movq %r13, %rdx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L30
movq (%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L31
movq 8(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
je .L11
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $51, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L26:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $35, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L27:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $36, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L28:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $39, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L29:
movl %r12d, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z36__device_stub__Z13cubeVecKernelPiS_iPiS_i
jmp .L18
.L30:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $47, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L31:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $50, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z7cubeVecPiS_ib, .-_Z7cubeVecPiS_ib
.section .rodata.str1.1
.LC2:
.string "INCORRECT :(\n"
.LC3:
.string "CORRECT :)\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl $400000, %edi
call malloc@PLT
movq %rax, %r14
movl $400000, %edi
call malloc@PLT
movq %rax, %r12
movl $400000, %edi
call malloc@PLT
movq %rax, %r13
movq %r14, %rbx
leaq 400000(%r14), %rbp
.L33:
call rand@PLT
movzbl %al, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L33
movl $0, %ecx
movl $100000, %edx
movq %r13, %rsi
movq %r14, %rdi
call _Z7cubeVecPiS_ib
movl $1, %ecx
movl $100000, %edx
movq %r12, %rsi
movq %r14, %rdi
call _Z7cubeVecPiS_ib
movl $0, %eax
.L36:
movl 0(%r13,%rax), %edx
cmpl %edx, (%r12,%rax)
jne .L40
addq $4, %rax
cmpq $400000, %rax
jne .L36
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L32
.L40:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
.L32:
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z13cubeVecKernelPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z13cubeVecKernelPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "VecCube.hip"
.globl _Z28__device_stub__cubeVecKernelPiS_i # -- Begin function _Z28__device_stub__cubeVecKernelPiS_i
.p2align 4, 0x90
.type _Z28__device_stub__cubeVecKernelPiS_i,@function
_Z28__device_stub__cubeVecKernelPiS_i: # @_Z28__device_stub__cubeVecKernelPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13cubeVecKernelPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__cubeVecKernelPiS_i, .Lfunc_end0-_Z28__device_stub__cubeVecKernelPiS_i
.cfi_endproc
# -- End function
.globl _Z7cubeVecPiS_ib # -- Begin function _Z7cubeVecPiS_ib
.p2align 4, 0x90
.type _Z7cubeVecPiS_ib,@function
_Z7cubeVecPiS_ib: # @_Z7cubeVecPiS_ib
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %edx, %r15d
movq %rsi, %rbx
movq %rdi, %r12
testl %ecx, %ecx
je .LBB1_1
# %bb.5:
movslq %r15d, %r14
shlq $2, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_6
# %bb.8:
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_9
# %bb.10:
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_11
# %bb.12:
leal -1(%r15), %eax
shrl $9, %eax
movabsq $4294967296, %rdx # imm = 0x100000000
leaq (%rdx,%rax), %rdi
incq %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_14
# %bb.13:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r15d, 28(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13cubeVecKernelPiS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_14:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_15
# %bb.16:
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_17
# %bb.18:
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB1_4
# %bb.19:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $53, %ecx
jmp .LBB1_7
.LBB1_1: # %.preheader
testl %r15d, %r15d
jle .LBB1_4
# %bb.2: # %.lr.ph.preheader
movl %r15d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%r12,%rcx,4), %edx
movl %edx, %esi
imull %edx, %esi
imull %edx, %esi
movl %esi, (%rbx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_3
.LBB1_4: # %.loopexit
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_6:
.cfi_def_cfa_offset 160
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $37, %ecx
jmp .LBB1_7
.LBB1_9:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $38, %ecx
jmp .LBB1_7
.LBB1_11:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $41, %ecx
jmp .LBB1_7
.LBB1_15:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $49, %ecx
jmp .LBB1_7
.LBB1_17:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $52, %ecx
.LBB1_7:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z7cubeVecPiS_ib, .Lfunc_end1-_Z7cubeVecPiS_ib
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $400000, %edi # imm = 0x61A80
callq malloc
movq %rax, %r15
movl $400000, %edi # imm = 0x61A80
callq malloc
movq %rax, %rbx
movl $400000, %edi # imm = 0x61A80
callq malloc
movq %rax, %r14
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
movl %eax, (%r15,%r12,4)
incq %r12
cmpq $100000, %r12 # imm = 0x186A0
jne .LBB2_1
# %bb.2: # %.lr.ph.i.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl (%r15,%rax,4), %ecx
movl %ecx, %edx
imull %ecx, %edx
imull %ecx, %edx
movl %edx, (%r14,%rax,4)
incq %rax
cmpq $100000, %rax # imm = 0x186A0
jne .LBB2_3
# %bb.4: # %_Z7cubeVecPiS_ib.exit
movl $1, %ebp
movq %r15, %rdi
movq %rbx, %rsi
movl $100000, %edx # imm = 0x186A0
movl $1, %ecx
callq _Z7cubeVecPiS_ib
movl (%rbx), %eax
cmpl (%r14), %eax
jne .LBB2_5
# %bb.6: # %.lr.ph.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_7: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cmpq $99999, %rax # imm = 0x1869F
je .LBB2_11
# %bb.8: # in Loop: Header=BB2_7 Depth=1
movl 4(%rbx,%rax,4), %edx
leaq 1(%rax), %rcx
cmpl 4(%r14,%rax,4), %edx
movq %rcx, %rax
je .LBB2_7
# %bb.9: # %._crit_edge.loopexit
decq %rcx
cmpq $99999, %rcx # imm = 0x1869F
setae %bl
jmp .LBB2_10
.LBB2_5:
xorl %ebx, %ebx
.LBB2_10: # %._crit_edge
movl $.Lstr, %edi
callq puts@PLT
testb %bl, %bl
je .LBB2_14
.LBB2_13:
movl $.Lstr.1, %edi
callq puts@PLT
.LBB2_14:
movl %ebp, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_11: # %.loopexit.loopexit
.cfi_def_cfa_offset 48
setae %bl
xorl %ebp, %ebp
testb %bl, %bl
jne .LBB2_13
jmp .LBB2_14
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13cubeVecKernelPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13cubeVecKernelPiS_i,@object # @_Z13cubeVecKernelPiS_i
.section .rodata,"a",@progbits
.globl _Z13cubeVecKernelPiS_i
.p2align 3, 0x0
_Z13cubeVecKernelPiS_i:
.quad _Z28__device_stub__cubeVecKernelPiS_i
.size _Z13cubeVecKernelPiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s in %s at line %d!\n"
.size .L.str, 22
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/haunt98/learn-cuda/master/VecCube.hip"
.size .L.str.1, 95
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13cubeVecKernelPiS_i"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "INCORRECT :("
.size .Lstr, 13
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "CORRECT :)"
.size .Lstr.1, 11
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__cubeVecKernelPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13cubeVecKernelPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
//nvcc -o mutual_outlinks mutual_outlinks.cu -arch sm_20
//find mean number of mutual outlinks
//among all pairs of websites
//checking all (i,j) pairs
//thread k will handle all i such that
//i%totth = k, where totth is the number of threads
__global__ void procpairs(int *m, int *tot, int n){
int totth = gridDim.x * blockDim.x;
int me = blockIdx.x*blockDim.x + threadIdx.x;
int i,j,k,sum = 0;
for(i = me; i<n; i+= totth){
for(j = i+i; j<n; j++){
for(k= 0; k<n ; k++)
sum += m[n*i+k]*m[n*j+k];
}
}
atomicAdd(tot, sum);
}
int main(){
int n = 10, nblk = 4;
int *hm, *dm, htot, *dtot;
int msize = n*n*sizeof(int);
hm = (int *) malloc(msize);
int i,j;
for( i = 0; i < n; i++){
hm[n*i + i] = 0;
for(j=0;j<n; j++)
if(j != i) hm[i*n +j] = rand()%2;
}
cudaMalloc((void **) &dm, msize);
cudaMemcpy(dm, hm, msize, cudaMemcpyHostToDevice);
htot = 0;
cudaMalloc((void **) &dtot, sizeof(int));
cudaMemcpy(dtot, &htot, sizeof(int), cudaMemcpyHostToDevice);
dim3 dimGrid(nblk, 1);
dim3 dimBlock(192, 1, 1);
procpairs<<<dimGrid, dimBlock>>>(dm, dtot, n);
cudaThreadSynchronize();
cudaMemcpy(&htot, dtot, sizeof(int), cudaMemcpyDeviceToHost);
return 0;
} | code for sm_80
Function : _Z9procpairsPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0020*/ MOV R8, c[0x0][0x170] ; /* 0x00005c0000087a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ BSSY B0, 0xaf0 ; /* 0x00000aa000007945 */
/* 0x000fe20003800000 */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fe20003f06270 */
/*0070*/ HFMA2.MMA R14, -RZ, RZ, 0, 0 ; /* 0x00000000ff0e7435 */
/* 0x000fe200000001ff */
/*0080*/ IMAD R9, R9, c[0x0][0x0], R0 ; /* 0x0000000009097a24 */
/* 0x001fca00078e0200 */
/*0090*/ ISETP.GE.OR P0, PT, R9, c[0x0][0x170], !P0 ; /* 0x00005c0009007a0c */
/* 0x000fda0004706670 */
/*00a0*/ @P0 BRA 0xae0 ; /* 0x00000a3000000947 */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R0, R8.reuse, -0x1, RZ ; /* 0xffffffff08007810 */
/* 0x040fe20007ffe0ff */
/*00c0*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e00ff */
/*00d0*/ LOP3.LUT R8, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308087812 */
/* 0x000fe400078ec0ff */
/*00e0*/ ISETP.GE.U32.AND P1, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f26070 */
/*00f0*/ IADD3 R10, -R8, c[0x0][0x170], RZ ; /* 0x00005c00080a7a10 */
/* 0x000fe40007ffe1ff */
/*0100*/ SHF.L.U32 R11, R9, 0x1, RZ ; /* 0x00000001090b7819 */
/* 0x000fe200000006ff */
/*0110*/ BSSY B1, 0xaa0 ; /* 0x0000098000017945 */
/* 0x000fe60003800000 */
/*0120*/ ISETP.GE.AND P0, PT, R11, c[0x0][0x170], PT ; /* 0x00005c000b007a0c */
/* 0x000fda0003f06270 */
/*0130*/ @P0 BRA 0xa90 ; /* 0x0000095000000947 */
/* 0x000fea0003800000 */
/*0140*/ IMAD R13, R9, c[0x0][0x170], RZ ; /* 0x00005c00090d7a24 */
/* 0x000fe400078e02ff */
/*0150*/ IMAD R15, R11.reuse, c[0x0][0x170], RZ ; /* 0x00005c000b0f7a24 */
/* 0x040fe200078e02ff */
/*0160*/ IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x000fe20007ffe0ff */
/*0170*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fc600000001ff */
/*0180*/ ISETP.GE.AND P2, PT, R11, c[0x0][0x170], PT ; /* 0x00005c000b007a0c */
/* 0x000fe20003f46270 */
/*0190*/ @!P1 BRA 0x950 ; /* 0x000007b000009947 */
/* 0x000fea0003800000 */
/*01a0*/ ISETP.GT.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f04270 */
/*01b0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*01c0*/ MOV R16, c[0x0][0x160] ; /* 0x0000580000107a02 */
/* 0x000fe40000000f00 */
/*01d0*/ MOV R17, c[0x0][0x164] ; /* 0x0000590000117a02 */
/* 0x000fe40000000f00 */
/*01e0*/ MOV R12, R10 ; /* 0x0000000a000c7202 */
/* 0x000fce0000000f00 */
/*01f0*/ @!P0 BRA 0x810 ; /* 0x0000061000008947 */
/* 0x000fea0003800000 */
/*0200*/ ISETP.GT.AND P3, PT, R12, 0xc, PT ; /* 0x0000000c0c00780c */
/* 0x000fe40003f64270 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0220*/ @!P3 BRA 0x5e0 ; /* 0x000003b00000b947 */
/* 0x000fea0003800000 */
/*0230*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0240*/ MOV R5, R17 ; /* 0x0000001100057202 */
/* 0x000fe20000000f00 */
/*0250*/ IMAD.MOV.U32 R4, RZ, RZ, R16 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0010 */
/*0260*/ IMAD.WIDE R2, R13, 0x4, R4 ; /* 0x000000040d027825 */
/* 0x000fc800078e0204 */
/*0270*/ IMAD.WIDE R6, R15, 0x4, R4 ; /* 0x000000040f067825 */
/* 0x000fe200078e0204 */
/*0280*/ LDG.E R20, [R2.64] ; /* 0x0000000602147981 */
/* 0x000ea8000c1e1900 */
/*0290*/ LDG.E R23, [R6.64] ; /* 0x0000000606177981 */
/* 0x000ea8000c1e1900 */
/*02a0*/ LDG.E R26, [R2.64+0x4] ; /* 0x00000406021a7981 */
/* 0x000ee8000c1e1900 */
/*02b0*/ LDG.E R27, [R6.64+0x4] ; /* 0x00000406061b7981 */
/* 0x000ee8000c1e1900 */
/*02c0*/ LDG.E R18, [R6.64+0x8] ; /* 0x0000080606127981 */
/* 0x000f28000c1e1900 */
/*02d0*/ LDG.E R21, [R2.64+0x8] ; /* 0x0000080602157981 */
/* 0x000f28000c1e1900 */
/*02e0*/ LDG.E R16, [R6.64+0xc] ; /* 0x00000c0606107981 */
/* 0x000f68000c1e1900 */
/*02f0*/ LDG.E R19, [R2.64+0xc] ; /* 0x00000c0602137981 */
/* 0x000f68000c1e1900 */
/*0300*/ LDG.E R17, [R6.64+0x10] ; /* 0x0000100606117981 */
/* 0x000f68000c1e1900 */
/*0310*/ LDG.E R24, [R2.64+0x10] ; /* 0x0000100602187981 */
/* 0x000f68000c1e1900 */
/*0320*/ LDG.E R22, [R6.64+0x14] ; /* 0x0000140606167981 */
/* 0x000f68000c1e1900 */
/*0330*/ LDG.E R25, [R2.64+0x14] ; /* 0x0000140602197981 */
/* 0x000f68000c1e1900 */
/*0340*/ LDG.E R29, [R2.64+0x3c] ; /* 0x00003c06021d7981 */
/* 0x000f62000c1e1900 */
/*0350*/ IMAD R20, R23, R20, R14 ; /* 0x0000001417147224 */
/* 0x004fc600078e020e */
/*0360*/ LDG.E R23, [R2.64+0x18] ; /* 0x0000180602177981 */
/* 0x000ea8000c1e1900 */
/*0370*/ LDG.E R14, [R2.64+0x24] ; /* 0x00002406020e7981 */
/* 0x000ea2000c1e1900 */
/*0380*/ IMAD R26, R27, R26, R20 ; /* 0x0000001a1b1a7224 */
/* 0x008fc600078e0214 */
/*0390*/ LDG.E R20, [R6.64+0x18] ; /* 0x0000180606147981 */
/* 0x000ea8000c1e1900 */
/*03a0*/ LDG.E R27, [R2.64+0x34] ; /* 0x00003406021b7981 */
/* 0x000ee2000c1e1900 */
/*03b0*/ IMAD R26, R18, R21, R26 ; /* 0x00000015121a7224 */
/* 0x010fc600078e021a */
/*03c0*/ LDG.E R18, [R6.64+0x1c] ; /* 0x00001c0606127981 */
/* 0x000f28000c1e1900 */
/*03d0*/ LDG.E R21, [R2.64+0x1c] ; /* 0x00001c0602157981 */
/* 0x000f22000c1e1900 */
/*03e0*/ IMAD R26, R16, R19, R26 ; /* 0x00000013101a7224 */
/* 0x020fc600078e021a */
/*03f0*/ LDG.E R16, [R6.64+0x20] ; /* 0x0000200606107981 */
/* 0x000f68000c1e1900 */
/*0400*/ LDG.E R19, [R2.64+0x20] ; /* 0x0000200602137981 */
/* 0x000f62000c1e1900 */
/*0410*/ IMAD R24, R17, R24, R26 ; /* 0x0000001811187224 */
/* 0x000fc600078e021a */
/*0420*/ LDG.E R17, [R6.64+0x24] ; /* 0x0000240606117981 */
/* 0x000ee8000c1e1900 */
/*0430*/ LDG.E R26, [R2.64+0x38] ; /* 0x00003806021a7981 */
/* 0x000ee2000c1e1900 */
/*0440*/ IMAD R24, R22, R25, R24 ; /* 0x0000001916187224 */
/* 0x000fc600078e0218 */
/*0450*/ LDG.E R22, [R6.64+0x28] ; /* 0x0000280606167981 */
/* 0x000ee8000c1e1900 */
/*0460*/ LDG.E R25, [R2.64+0x28] ; /* 0x0000280602197981 */
/* 0x000ee2000c1e1900 */
/*0470*/ IMAD R24, R20, R23, R24 ; /* 0x0000001714187224 */
/* 0x004fc600078e0218 */
/*0480*/ LDG.E R20, [R6.64+0x2c] ; /* 0x00002c0606147981 */
/* 0x000ea8000c1e1900 */
/*0490*/ LDG.E R23, [R2.64+0x2c] ; /* 0x00002c0602177981 */
/* 0x000ea2000c1e1900 */
/*04a0*/ IMAD R24, R18, R21, R24 ; /* 0x0000001512187224 */
/* 0x010fc600078e0218 */
/*04b0*/ LDG.E R18, [R6.64+0x30] ; /* 0x0000300606127981 */
/* 0x000f28000c1e1900 */
/*04c0*/ LDG.E R21, [R2.64+0x30] ; /* 0x0000300602157981 */
/* 0x000f22000c1e1900 */
/*04d0*/ IMAD R28, R16, R19, R24 ; /* 0x00000013101c7224 */
/* 0x020fc600078e0218 */
/*04e0*/ LDG.E R16, [R6.64+0x34] ; /* 0x0000340606107981 */
/* 0x000f68000c1e1900 */
/*04f0*/ LDG.E R19, [R6.64+0x38] ; /* 0x0000380606137981 */
/* 0x000f68000c1e1900 */
/*0500*/ LDG.E R24, [R6.64+0x3c] ; /* 0x00003c0606187981 */
/* 0x000f62000c1e1900 */
/*0510*/ IMAD R14, R17, R14, R28 ; /* 0x0000000e110e7224 */
/* 0x008fe200078e021c */
/*0520*/ IADD3 R12, R12, -0x10, RZ ; /* 0xfffffff00c0c7810 */
/* 0x000fc60007ffe0ff */
/*0530*/ IMAD R14, R22, R25, R14 ; /* 0x00000019160e7224 */
/* 0x000fe200078e020e */
/*0540*/ ISETP.GT.AND P3, PT, R12, 0xc, PT ; /* 0x0000000c0c00780c */
/* 0x000fe40003f64270 */
/*0550*/ IADD3 R0, R0, 0x10, RZ ; /* 0x0000001000007810 */
/* 0x000fe20007ffe0ff */
/*0560*/ IMAD R14, R20, R23, R14 ; /* 0x00000017140e7224 */
/* 0x004fc800078e020e */
/*0570*/ IMAD R14, R18, R21, R14 ; /* 0x00000015120e7224 */
/* 0x010fc800078e020e */
/*0580*/ IMAD R14, R16, R27, R14 ; /* 0x0000001b100e7224 */
/* 0x020fe200078e020e */
/*0590*/ IADD3 R16, P4, R4, 0x40, RZ ; /* 0x0000004004107810 */
/* 0x000fc60007f9e0ff */
/*05a0*/ IMAD R14, R19, R26, R14 ; /* 0x0000001a130e7224 */
/* 0x000fe200078e020e */
/*05b0*/ IADD3.X R17, RZ, R5, RZ, P4, !PT ; /* 0x00000005ff117210 */
/* 0x000fc600027fe4ff */
/*05c0*/ IMAD R14, R24, R29, R14 ; /* 0x0000001d180e7224 */
/* 0x000fe200078e020e */
/*05d0*/ @P3 BRA 0x240 ; /* 0xfffffc6000003947 */
/* 0x000fea000383ffff */
/*05e0*/ ISETP.GT.AND P3, PT, R12, 0x4, PT ; /* 0x000000040c00780c */
/* 0x000fda0003f64270 */
/*05f0*/ @!P3 BRA 0x7f0 ; /* 0x000001f00000b947 */
/* 0x000fea0003800000 */
/*0600*/ IMAD.WIDE R2, R15, 0x4, R16 ; /* 0x000000040f027825 */
/* 0x000fc800078e0210 */
/*0610*/ IMAD.WIDE R4, R13, 0x4, R16 ; /* 0x000000040d047825 */
/* 0x000fe200078e0210 */
/*0620*/ LDG.E R23, [R2.64] ; /* 0x0000000602177981 */
/* 0x000ea8000c1e1900 */
/*0630*/ LDG.E R22, [R4.64] ; /* 0x0000000604167981 */
/* 0x000ea8000c1e1900 */
/*0640*/ LDG.E R6, [R2.64+0x4] ; /* 0x0000040602067981 */
/* 0x000ee8000c1e1900 */
/*0650*/ LDG.E R7, [R4.64+0x4] ; /* 0x0000040604077981 */
/* 0x000ee8000c1e1900 */
/*0660*/ LDG.E R18, [R2.64+0x8] ; /* 0x0000080602127981 */
/* 0x000f28000c1e1900 */
/*0670*/ LDG.E R19, [R4.64+0x8] ; /* 0x0000080604137981 */
/* 0x000f28000c1e1900 */
/*0680*/ LDG.E R20, [R2.64+0xc] ; /* 0x00000c0602147981 */
/* 0x000f68000c1e1900 */
/*0690*/ LDG.E R21, [R4.64+0xc] ; /* 0x00000c0604157981 */
/* 0x000f68000c1e1900 */
/*06a0*/ LDG.E R24, [R4.64+0x10] ; /* 0x0000100604187981 */
/* 0x000f68000c1e1900 */
/*06b0*/ LDG.E R29, [R4.64+0x14] ; /* 0x00001406041d7981 */
/* 0x000f68000c1e1900 */
/*06c0*/ LDG.E R27, [R4.64+0x18] ; /* 0x00001806041b7981 */
/* 0x000f68000c1e1900 */
/*06d0*/ LDG.E R25, [R2.64+0x1c] ; /* 0x00001c0602197981 */
/* 0x000f68000c1e1900 */
/*06e0*/ LDG.E R26, [R4.64+0x1c] ; /* 0x00001c06041a7981 */
/* 0x000f62000c1e1900 */
/*06f0*/ IMAD R28, R23, R22, R14 ; /* 0x00000016171c7224 */
/* 0x004fc600078e020e */
/*0700*/ LDG.E R23, [R2.64+0x10] ; /* 0x0000100602177981 */
/* 0x000ea8000c1e1900 */
/*0710*/ LDG.E R22, [R2.64+0x14] ; /* 0x0000140602167981 */
/* 0x000ea8000c1e1900 */
/*0720*/ LDG.E R14, [R2.64+0x18] ; /* 0x00001806020e7981 */
/* 0x000ea2000c1e1900 */
/*0730*/ IMAD R6, R6, R7, R28 ; /* 0x0000000706067224 */
/* 0x008fc800078e021c */
/*0740*/ IMAD R6, R18, R19, R6 ; /* 0x0000001312067224 */
/* 0x010fc800078e0206 */
/*0750*/ IMAD R6, R20, R21, R6 ; /* 0x0000001514067224 */
/* 0x020fe200078e0206 */
/*0760*/ IADD3 R16, P3, R16, 0x20, RZ ; /* 0x0000002010107810 */
/* 0x000fe40007f7e0ff */
/*0770*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0780*/ IADD3 R0, R0, 0x8, RZ ; /* 0x0000000800007810 */
/* 0x000fe40007ffe0ff */
/*0790*/ IADD3 R12, R12, -0x8, RZ ; /* 0xfffffff80c0c7810 */
/* 0x000fe40007ffe0ff */
/*07a0*/ IADD3.X R17, RZ, R17, RZ, P3, !PT ; /* 0x00000011ff117210 */
/* 0x000fe20001ffe4ff */
/*07b0*/ IMAD R6, R23, R24, R6 ; /* 0x0000001817067224 */
/* 0x004fc800078e0206 */
/*07c0*/ IMAD R6, R22, R29, R6 ; /* 0x0000001d16067224 */
/* 0x000fc800078e0206 */
/*07d0*/ IMAD R14, R14, R27, R6 ; /* 0x0000001b0e0e7224 */
/* 0x000fc800078e0206 */
/*07e0*/ IMAD R14, R25, R26, R14 ; /* 0x0000001a190e7224 */
/* 0x000fe400078e020e */
/*07f0*/ ISETP.NE.OR P0, PT, R12, RZ, P0 ; /* 0x000000ff0c00720c */
/* 0x000fda0000705670 */
/*0800*/ @!P0 BRA 0x950 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0810*/ IMAD.WIDE R4, R13, 0x4, R16 ; /* 0x000000040d047825 */
/* 0x000fc800078e0210 */
/*0820*/ IMAD.WIDE R2, R15, 0x4, R16 ; /* 0x000000040f027825 */
/* 0x000fe200078e0210 */
/*0830*/ LDG.E R6, [R4.64] ; /* 0x0000000604067981 */
/* 0x000ea8000c1e1900 */
/*0840*/ LDG.E R7, [R2.64] ; /* 0x0000000602077981 */
/* 0x000ea8000c1e1900 */
/*0850*/ LDG.E R18, [R4.64+0x4] ; /* 0x0000040604127981 */
/* 0x000ee8000c1e1900 */
/*0860*/ LDG.E R19, [R2.64+0x4] ; /* 0x0000040602137981 */
/* 0x000ee8000c1e1900 */
/*0870*/ LDG.E R21, [R2.64+0x8] ; /* 0x0000080602157981 */
/* 0x000f28000c1e1900 */
/*0880*/ LDG.E R20, [R4.64+0x8] ; /* 0x0000080604147981 */
/* 0x000f28000c1e1900 */
/*0890*/ LDG.E R23, [R2.64+0xc] ; /* 0x00000c0602177981 */
/* 0x000f68000c1e1900 */
/*08a0*/ LDG.E R22, [R4.64+0xc] ; /* 0x00000c0604167981 */
/* 0x000f62000c1e1900 */
/*08b0*/ IADD3 R12, R12, -0x4, RZ ; /* 0xfffffffc0c0c7810 */
/* 0x000fc40007ffe0ff */
/*08c0*/ IADD3 R16, P3, R16, 0x10, RZ ; /* 0x0000001010107810 */
/* 0x000fe40007f7e0ff */
/*08d0*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f05270 */
/*08e0*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x000fe20007ffe0ff */
/*08f0*/ IMAD.X R17, RZ, RZ, R17, P3 ; /* 0x000000ffff117224 */
/* 0x000fe400018e0611 */
/*0900*/ IMAD R6, R7, R6, R14 ; /* 0x0000000607067224 */
/* 0x004fc800078e020e */
/*0910*/ IMAD R6, R19, R18, R6 ; /* 0x0000001213067224 */
/* 0x008fc800078e0206 */
/*0920*/ IMAD R6, R21, R20, R6 ; /* 0x0000001415067224 */
/* 0x010fc800078e0206 */
/*0930*/ IMAD R14, R23, R22, R6 ; /* 0x00000016170e7224 */
/* 0x020fe200078e0206 */
/*0940*/ @P0 BRA 0x810 ; /* 0xfffffec000000947 */
/* 0x000fea000383ffff */
/*0950*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*0960*/ @!P0 BRA 0xa80 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0970*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0980*/ IADD3 R4, R15, R0.reuse, RZ ; /* 0x000000000f047210 */
/* 0x080fe40007ffe0ff */
/*0990*/ IADD3 R2, R13, R0, RZ ; /* 0x000000000d027210 */
/* 0x000fce0007ffe0ff */
/*09a0*/ IMAD.WIDE R4, R4, R3, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0203 */
/*09b0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe200078e0203 */
/*09c0*/ LDG.E R7, [R4.64] ; /* 0x0000000604077981 */
/* 0x000ea8000c1e1900 */
/*09d0*/ LDG.E R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x000ea2000c1e1900 */
/*09e0*/ ISETP.NE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fe20003f05270 */
/*09f0*/ IMAD R14, R7, R0, R14 ; /* 0x00000000070e7224 */
/* 0x004fd800078e020e */
/*0a00*/ @!P0 BRA 0xa80 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*0a10*/ ISETP.NE.AND P0, PT, R8, 0x2, PT ; /* 0x000000020800780c */
/* 0x000fe20003f05270 */
/*0a20*/ LDG.E R7, [R4.64+0x4] ; /* 0x0000040604077981 */
/* 0x000ea8000c1e1900 */
/*0a30*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040602007981 */
/* 0x000eb0000c1e1900 */
/*0a40*/ @P0 LDG.E R15, [R4.64+0x8] ; /* 0x00000806040f0981 */
/* 0x000ee8000c1e1900 */
/*0a50*/ @P0 LDG.E R6, [R2.64+0x8] ; /* 0x0000080602060981 */
/* 0x000ee2000c1e1900 */
/*0a60*/ IMAD R14, R7, R0, R14 ; /* 0x00000000070e7224 */
/* 0x004fc800078e020e */
/*0a70*/ @P0 IMAD R14, R15, R6, R14 ; /* 0x000000060f0e0224 */
/* 0x008fe400078e020e */
/*0a80*/ @!P2 BRA 0x150 ; /* 0xfffff6c00000a947 */
/* 0x000fea000383ffff */
/*0a90*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0aa0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff007624 */
/* 0x000fc800078e00ff */
/*0ab0*/ IMAD R9, R0, c[0x0][0x0], R9 ; /* 0x0000000000097a24 */
/* 0x000fca00078e0209 */
/*0ac0*/ ISETP.GE.AND P0, PT, R9, c[0x0][0x170], PT ; /* 0x00005c0009007a0c */
/* 0x000fda0003f06270 */
/*0ad0*/ @!P0 BRA 0x100 ; /* 0xfffff62000008947 */
/* 0x000fea000383ffff */
/*0ae0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0af0*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */
/* 0x000e220000000000 */
/*0b00*/ REDUX.SUM UR5, R14 ; /* 0x000000000e0573c4 */
/* 0x000e62000000c000 */
/*0b10*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe200038e0100 */
/*0b20*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0b30*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fe200080e0000 */
/*0b40*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fca0000000f00 */
/*0b50*/ ISETP.EQ.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x001fe4000bf02070 */
/*0b60*/ MOV R5, UR5 ; /* 0x0000000500057c02 */
/* 0x002fd60008000f00 */
/*0b70*/ @P0 RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200098e */
/* 0x000fe2000c10e186 */
/*0b80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b90*/ BRA 0xb90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
//nvcc -o mutual_outlinks mutual_outlinks.cu -arch sm_20
//find mean number of mutual outlinks
//among all pairs of websites
//checking all (i,j) pairs
//thread k will handle all i such that
//i%totth = k, where totth is the number of threads
__global__ void procpairs(int *m, int *tot, int n){
int totth = gridDim.x * blockDim.x;
int me = blockIdx.x*blockDim.x + threadIdx.x;
int i,j,k,sum = 0;
for(i = me; i<n; i+= totth){
for(j = i+i; j<n; j++){
for(k= 0; k<n ; k++)
sum += m[n*i+k]*m[n*j+k];
}
}
atomicAdd(tot, sum);
}
int main(){
int n = 10, nblk = 4;
int *hm, *dm, htot, *dtot;
int msize = n*n*sizeof(int);
hm = (int *) malloc(msize);
int i,j;
for( i = 0; i < n; i++){
hm[n*i + i] = 0;
for(j=0;j<n; j++)
if(j != i) hm[i*n +j] = rand()%2;
}
cudaMalloc((void **) &dm, msize);
cudaMemcpy(dm, hm, msize, cudaMemcpyHostToDevice);
htot = 0;
cudaMalloc((void **) &dtot, sizeof(int));
cudaMemcpy(dtot, &htot, sizeof(int), cudaMemcpyHostToDevice);
dim3 dimGrid(nblk, 1);
dim3 dimBlock(192, 1, 1);
procpairs<<<dimGrid, dimBlock>>>(dm, dtot, n);
cudaThreadSynchronize();
cudaMemcpy(&htot, dtot, sizeof(int), cudaMemcpyDeviceToHost);
return 0;
} | .file "tmpxft_000ae176_00000000-6_mutual_outlinks.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z9procpairsPiS_iPiS_i
.type _Z31__device_stub__Z9procpairsPiS_iPiS_i, @function
_Z31__device_stub__Z9procpairsPiS_iPiS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9procpairsPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z9procpairsPiS_iPiS_i, .-_Z31__device_stub__Z9procpairsPiS_iPiS_i
.globl _Z9procpairsPiS_i
.type _Z9procpairsPiS_i, @function
_Z9procpairsPiS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9procpairsPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9procpairsPiS_i, .-_Z9procpairsPiS_i
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $400, %edi
call malloc@PLT
movq %rax, %r13
movq %rax, %r14
movl $0, %r12d
movl $0, %ebp
jmp .L14
.L21:
call rand@PLT
leal (%rbx,%r12), %edx
movslq %edx, %rdx
movl %eax, %ecx
shrl $31, %ecx
addl %ecx, %eax
andl $1, %eax
subl %ecx, %eax
movl %eax, 0(%r13,%rdx,4)
.L12:
addl $1, %ebx
cmpl $10, %ebx
je .L20
.L13:
cmpl %ebx, %ebp
jne .L21
jmp .L12
.L20:
addl $1, %ebp
addq $44, %r14
addl $10, %r12d
cmpl $10, %ebp
je .L22
.L14:
movl $0, (%r14)
movl $0, %ebx
jmp .L13
.L22:
leaq 16(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $400, %edx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, 12(%rsp)
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 12(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 32(%rsp)
movl $1, 36(%rsp)
movl $192, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L15:
call cudaThreadSynchronize@PLT
leaq 12(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl $10, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z31__device_stub__Z9procpairsPiS_iPiS_i
jmp .L15
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9procpairsPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9procpairsPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
//nvcc -o mutual_outlinks mutual_outlinks.cu -arch sm_20
//find mean number of mutual outlinks
//among all pairs of websites
//checking all (i,j) pairs
//thread k will handle all i such that
//i%totth = k, where totth is the number of threads
__global__ void procpairs(int *m, int *tot, int n){
int totth = gridDim.x * blockDim.x;
int me = blockIdx.x*blockDim.x + threadIdx.x;
int i,j,k,sum = 0;
for(i = me; i<n; i+= totth){
for(j = i+i; j<n; j++){
for(k= 0; k<n ; k++)
sum += m[n*i+k]*m[n*j+k];
}
}
atomicAdd(tot, sum);
}
int main(){
int n = 10, nblk = 4;
int *hm, *dm, htot, *dtot;
int msize = n*n*sizeof(int);
hm = (int *) malloc(msize);
int i,j;
for( i = 0; i < n; i++){
hm[n*i + i] = 0;
for(j=0;j<n; j++)
if(j != i) hm[i*n +j] = rand()%2;
}
cudaMalloc((void **) &dm, msize);
cudaMemcpy(dm, hm, msize, cudaMemcpyHostToDevice);
htot = 0;
cudaMalloc((void **) &dtot, sizeof(int));
cudaMemcpy(dtot, &htot, sizeof(int), cudaMemcpyHostToDevice);
dim3 dimGrid(nblk, 1);
dim3 dimBlock(192, 1, 1);
procpairs<<<dimGrid, dimBlock>>>(dm, dtot, n);
cudaThreadSynchronize();
cudaMemcpy(&htot, dtot, sizeof(int), cudaMemcpyDeviceToHost);
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
//nvcc -o mutual_outlinks mutual_outlinks.cu -arch sm_20
//find mean number of mutual outlinks
//among all pairs of websites
//checking all (i,j) pairs
//thread k will handle all i such that
//i%totth = k, where totth is the number of threads
__global__ void procpairs(int *m, int *tot, int n){
int totth = gridDim.x * blockDim.x;
int me = blockIdx.x*blockDim.x + threadIdx.x;
int i,j,k,sum = 0;
for(i = me; i<n; i+= totth){
for(j = i+i; j<n; j++){
for(k= 0; k<n ; k++)
sum += m[n*i+k]*m[n*j+k];
}
}
atomicAdd(tot, sum);
}
int main(){
int n = 10, nblk = 4;
int *hm, *dm, htot, *dtot;
int msize = n*n*sizeof(int);
hm = (int *) malloc(msize);
int i,j;
for( i = 0; i < n; i++){
hm[n*i + i] = 0;
for(j=0;j<n; j++)
if(j != i) hm[i*n +j] = rand()%2;
}
hipMalloc((void **) &dm, msize);
hipMemcpy(dm, hm, msize, hipMemcpyHostToDevice);
htot = 0;
hipMalloc((void **) &dtot, sizeof(int));
hipMemcpy(dtot, &htot, sizeof(int), hipMemcpyHostToDevice);
dim3 dimGrid(nblk, 1);
dim3 dimBlock(192, 1, 1);
procpairs<<<dimGrid, dimBlock>>>(dm, dtot, n);
hipDeviceSynchronize();
hipMemcpy(&htot, dtot, sizeof(int), hipMemcpyDeviceToHost);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
//nvcc -o mutual_outlinks mutual_outlinks.cu -arch sm_20
//find mean number of mutual outlinks
//among all pairs of websites
//checking all (i,j) pairs
//thread k will handle all i such that
//i%totth = k, where totth is the number of threads
__global__ void procpairs(int *m, int *tot, int n){
int totth = gridDim.x * blockDim.x;
int me = blockIdx.x*blockDim.x + threadIdx.x;
int i,j,k,sum = 0;
for(i = me; i<n; i+= totth){
for(j = i+i; j<n; j++){
for(k= 0; k<n ; k++)
sum += m[n*i+k]*m[n*j+k];
}
}
atomicAdd(tot, sum);
}
int main(){
int n = 10, nblk = 4;
int *hm, *dm, htot, *dtot;
int msize = n*n*sizeof(int);
hm = (int *) malloc(msize);
int i,j;
for( i = 0; i < n; i++){
hm[n*i + i] = 0;
for(j=0;j<n; j++)
if(j != i) hm[i*n +j] = rand()%2;
}
hipMalloc((void **) &dm, msize);
hipMemcpy(dm, hm, msize, hipMemcpyHostToDevice);
htot = 0;
hipMalloc((void **) &dtot, sizeof(int));
hipMemcpy(dtot, &htot, sizeof(int), hipMemcpyHostToDevice);
dim3 dimGrid(nblk, 1);
dim3 dimBlock(192, 1, 1);
procpairs<<<dimGrid, dimBlock>>>(dm, dtot, n);
hipDeviceSynchronize();
hipMemcpy(&htot, dtot, sizeof(int), hipMemcpyDeviceToHost);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9procpairsPiS_i
.globl _Z9procpairsPiS_i
.p2align 8
.type _Z9procpairsPiS_i,@function
_Z9procpairsPiS_i:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s5, 0xffff
s_mov_b32 s5, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_11
s_load_b32 s7, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x0
v_mul_lo_u32 v2, s4, v1
v_mov_b32_e32 v0, 0
s_cmp_gt_i32 s4, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_lshlrev_b32_e32 v10, 1, v2
s_waitcnt lgkmcnt(0)
s_mul_i32 s6, s7, s6
s_cselect_b32 s7, -1, 0
s_mul_i32 s9, s6, s4
s_lshl_b32 s10, s9, 1
s_branch .LBB0_4
.LBB0_2:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s12
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
s_or_b32 exec_lo, exec_lo, s11
v_add_nc_u32_e32 v1, s6, v1
v_add_nc_u32_e32 v10, s10, v10
v_add_nc_u32_e32 v2, s9, v2
v_cmp_le_i32_e32 vcc_lo, s4, v1
s_or_b32 s8, vcc_lo, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execz .LBB0_10
.LBB0_4:
v_lshlrev_b32_e32 v11, 1, v1
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s4, v11
s_cbranch_execz .LBB0_3
v_ashrrev_i32_e32 v3, 31, v2
v_mov_b32_e32 v5, v10
s_mov_b32 s12, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_7
.p2align 6
.LBB0_6:
v_add_nc_u32_e32 v11, 1, v11
v_add_nc_u32_e32 v5, s4, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s4, v11
s_or_b32 s12, vcc_lo, s12
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execz .LBB0_2
.LBB0_7:
s_and_not1_b32 vcc_lo, exec_lo, s7
s_cbranch_vccnz .LBB0_6
v_ashrrev_i32_e32 v6, 31, v5
v_dual_mov_b32 v9, v4 :: v_dual_mov_b32 v8, v3
s_mov_b32 s13, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
.p2align 6
.LBB0_9:
global_load_b32 v14, v[8:9], off
global_load_b32 v15, v[6:7], off
v_add_co_u32 v6, vcc_lo, v6, 4
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, v8, 4
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
s_add_i32 s13, s13, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s13, 0
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[12:13], null, v15, v14, v[0:1]
v_mov_b32_e32 v0, v12
s_cbranch_scc1 .LBB0_9
s_branch .LBB0_6
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s8
.LBB0_11:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s5
s_mov_b32 s3, exec_lo
s_mov_b32 s2, 0
.LBB0_12:
s_ctz_i32_b32 s4, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s5, v0, s4
s_lshl_b32 s4, 1, s4
s_and_not1_b32 s3, s3, s4
s_delay_alu instid0(VALU_DEP_1)
s_add_i32 s2, s2, s5
s_cmp_lg_u32 s3, 0
s_cbranch_scc1 .LBB0_12
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_15
s_load_b64 s[0:1], s[0:1], 0x8
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9procpairsPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9procpairsPiS_i, .Lfunc_end0-_Z9procpairsPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9procpairsPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9procpairsPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
//nvcc -o mutual_outlinks mutual_outlinks.cu -arch sm_20
//find mean number of mutual outlinks
//among all pairs of websites
//checking all (i,j) pairs
//thread k will handle all i such that
//i%totth = k, where totth is the number of threads
__global__ void procpairs(int *m, int *tot, int n){
int totth = gridDim.x * blockDim.x;
int me = blockIdx.x*blockDim.x + threadIdx.x;
int i,j,k,sum = 0;
for(i = me; i<n; i+= totth){
for(j = i+i; j<n; j++){
for(k= 0; k<n ; k++)
sum += m[n*i+k]*m[n*j+k];
}
}
atomicAdd(tot, sum);
}
int main(){
int n = 10, nblk = 4;
int *hm, *dm, htot, *dtot;
int msize = n*n*sizeof(int);
hm = (int *) malloc(msize);
int i,j;
for( i = 0; i < n; i++){
hm[n*i + i] = 0;
for(j=0;j<n; j++)
if(j != i) hm[i*n +j] = rand()%2;
}
hipMalloc((void **) &dm, msize);
hipMemcpy(dm, hm, msize, hipMemcpyHostToDevice);
htot = 0;
hipMalloc((void **) &dtot, sizeof(int));
hipMemcpy(dtot, &htot, sizeof(int), hipMemcpyHostToDevice);
dim3 dimGrid(nblk, 1);
dim3 dimBlock(192, 1, 1);
procpairs<<<dimGrid, dimBlock>>>(dm, dtot, n);
hipDeviceSynchronize();
hipMemcpy(&htot, dtot, sizeof(int), hipMemcpyDeviceToHost);
return 0;
} | .text
.file "mutual_outlinks.hip"
.globl _Z24__device_stub__procpairsPiS_i # -- Begin function _Z24__device_stub__procpairsPiS_i
.p2align 4, 0x90
.type _Z24__device_stub__procpairsPiS_i,@function
_Z24__device_stub__procpairsPiS_i: # @_Z24__device_stub__procpairsPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9procpairsPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__procpairsPiS_i, .Lfunc_end0-_Z24__device_stub__procpairsPiS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
movq %rax, %r15
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_1 Depth=1
incq %r14
addq $40, %r15
cmpq $10, %r14
je .LBB1_6
.LBB1_1: # =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
imulq $44, %r14, %rax
movl $0, (%rbx,%rax)
xorl %r12d, %r12d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_4: # in Loop: Header=BB1_2 Depth=2
incq %r12
cmpq $10, %r12
je .LBB1_5
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
cmpq %r12, %r14
je .LBB1_4
# %bb.3: # in Loop: Header=BB1_2 Depth=2
callq rand
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
andl $-2, %ecx
subl %ecx, %eax
movl %eax, (%r15,%r12,4)
jmp .LBB1_4
.LBB1_6:
leaq 24(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
movq 24(%rsp), %rdi
movl $400, %edx # imm = 0x190
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $0, 4(%rsp)
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 4(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967300, %rdi # imm = 0x100000004
leaq 188(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $10, 20(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9procpairsPiS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
leaq 4(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9procpairsPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9procpairsPiS_i,@object # @_Z9procpairsPiS_i
.section .rodata,"a",@progbits
.globl _Z9procpairsPiS_i
.p2align 3, 0x0
_Z9procpairsPiS_i:
.quad _Z24__device_stub__procpairsPiS_i
.size _Z9procpairsPiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9procpairsPiS_i"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__procpairsPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9procpairsPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9procpairsPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0020*/ MOV R8, c[0x0][0x170] ; /* 0x00005c0000087a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ BSSY B0, 0xaf0 ; /* 0x00000aa000007945 */
/* 0x000fe20003800000 */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fe20003f06270 */
/*0070*/ HFMA2.MMA R14, -RZ, RZ, 0, 0 ; /* 0x00000000ff0e7435 */
/* 0x000fe200000001ff */
/*0080*/ IMAD R9, R9, c[0x0][0x0], R0 ; /* 0x0000000009097a24 */
/* 0x001fca00078e0200 */
/*0090*/ ISETP.GE.OR P0, PT, R9, c[0x0][0x170], !P0 ; /* 0x00005c0009007a0c */
/* 0x000fda0004706670 */
/*00a0*/ @P0 BRA 0xae0 ; /* 0x00000a3000000947 */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R0, R8.reuse, -0x1, RZ ; /* 0xffffffff08007810 */
/* 0x040fe20007ffe0ff */
/*00c0*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e00ff */
/*00d0*/ LOP3.LUT R8, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308087812 */
/* 0x000fe400078ec0ff */
/*00e0*/ ISETP.GE.U32.AND P1, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f26070 */
/*00f0*/ IADD3 R10, -R8, c[0x0][0x170], RZ ; /* 0x00005c00080a7a10 */
/* 0x000fe40007ffe1ff */
/*0100*/ SHF.L.U32 R11, R9, 0x1, RZ ; /* 0x00000001090b7819 */
/* 0x000fe200000006ff */
/*0110*/ BSSY B1, 0xaa0 ; /* 0x0000098000017945 */
/* 0x000fe60003800000 */
/*0120*/ ISETP.GE.AND P0, PT, R11, c[0x0][0x170], PT ; /* 0x00005c000b007a0c */
/* 0x000fda0003f06270 */
/*0130*/ @P0 BRA 0xa90 ; /* 0x0000095000000947 */
/* 0x000fea0003800000 */
/*0140*/ IMAD R13, R9, c[0x0][0x170], RZ ; /* 0x00005c00090d7a24 */
/* 0x000fe400078e02ff */
/*0150*/ IMAD R15, R11.reuse, c[0x0][0x170], RZ ; /* 0x00005c000b0f7a24 */
/* 0x040fe200078e02ff */
/*0160*/ IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x000fe20007ffe0ff */
/*0170*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fc600000001ff */
/*0180*/ ISETP.GE.AND P2, PT, R11, c[0x0][0x170], PT ; /* 0x00005c000b007a0c */
/* 0x000fe20003f46270 */
/*0190*/ @!P1 BRA 0x950 ; /* 0x000007b000009947 */
/* 0x000fea0003800000 */
/*01a0*/ ISETP.GT.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f04270 */
/*01b0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*01c0*/ MOV R16, c[0x0][0x160] ; /* 0x0000580000107a02 */
/* 0x000fe40000000f00 */
/*01d0*/ MOV R17, c[0x0][0x164] ; /* 0x0000590000117a02 */
/* 0x000fe40000000f00 */
/*01e0*/ MOV R12, R10 ; /* 0x0000000a000c7202 */
/* 0x000fce0000000f00 */
/*01f0*/ @!P0 BRA 0x810 ; /* 0x0000061000008947 */
/* 0x000fea0003800000 */
/*0200*/ ISETP.GT.AND P3, PT, R12, 0xc, PT ; /* 0x0000000c0c00780c */
/* 0x000fe40003f64270 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0220*/ @!P3 BRA 0x5e0 ; /* 0x000003b00000b947 */
/* 0x000fea0003800000 */
/*0230*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0240*/ MOV R5, R17 ; /* 0x0000001100057202 */
/* 0x000fe20000000f00 */
/*0250*/ IMAD.MOV.U32 R4, RZ, RZ, R16 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0010 */
/*0260*/ IMAD.WIDE R2, R13, 0x4, R4 ; /* 0x000000040d027825 */
/* 0x000fc800078e0204 */
/*0270*/ IMAD.WIDE R6, R15, 0x4, R4 ; /* 0x000000040f067825 */
/* 0x000fe200078e0204 */
/*0280*/ LDG.E R20, [R2.64] ; /* 0x0000000602147981 */
/* 0x000ea8000c1e1900 */
/*0290*/ LDG.E R23, [R6.64] ; /* 0x0000000606177981 */
/* 0x000ea8000c1e1900 */
/*02a0*/ LDG.E R26, [R2.64+0x4] ; /* 0x00000406021a7981 */
/* 0x000ee8000c1e1900 */
/*02b0*/ LDG.E R27, [R6.64+0x4] ; /* 0x00000406061b7981 */
/* 0x000ee8000c1e1900 */
/*02c0*/ LDG.E R18, [R6.64+0x8] ; /* 0x0000080606127981 */
/* 0x000f28000c1e1900 */
/*02d0*/ LDG.E R21, [R2.64+0x8] ; /* 0x0000080602157981 */
/* 0x000f28000c1e1900 */
/*02e0*/ LDG.E R16, [R6.64+0xc] ; /* 0x00000c0606107981 */
/* 0x000f68000c1e1900 */
/*02f0*/ LDG.E R19, [R2.64+0xc] ; /* 0x00000c0602137981 */
/* 0x000f68000c1e1900 */
/*0300*/ LDG.E R17, [R6.64+0x10] ; /* 0x0000100606117981 */
/* 0x000f68000c1e1900 */
/*0310*/ LDG.E R24, [R2.64+0x10] ; /* 0x0000100602187981 */
/* 0x000f68000c1e1900 */
/*0320*/ LDG.E R22, [R6.64+0x14] ; /* 0x0000140606167981 */
/* 0x000f68000c1e1900 */
/*0330*/ LDG.E R25, [R2.64+0x14] ; /* 0x0000140602197981 */
/* 0x000f68000c1e1900 */
/*0340*/ LDG.E R29, [R2.64+0x3c] ; /* 0x00003c06021d7981 */
/* 0x000f62000c1e1900 */
/*0350*/ IMAD R20, R23, R20, R14 ; /* 0x0000001417147224 */
/* 0x004fc600078e020e */
/*0360*/ LDG.E R23, [R2.64+0x18] ; /* 0x0000180602177981 */
/* 0x000ea8000c1e1900 */
/*0370*/ LDG.E R14, [R2.64+0x24] ; /* 0x00002406020e7981 */
/* 0x000ea2000c1e1900 */
/*0380*/ IMAD R26, R27, R26, R20 ; /* 0x0000001a1b1a7224 */
/* 0x008fc600078e0214 */
/*0390*/ LDG.E R20, [R6.64+0x18] ; /* 0x0000180606147981 */
/* 0x000ea8000c1e1900 */
/*03a0*/ LDG.E R27, [R2.64+0x34] ; /* 0x00003406021b7981 */
/* 0x000ee2000c1e1900 */
/*03b0*/ IMAD R26, R18, R21, R26 ; /* 0x00000015121a7224 */
/* 0x010fc600078e021a */
/*03c0*/ LDG.E R18, [R6.64+0x1c] ; /* 0x00001c0606127981 */
/* 0x000f28000c1e1900 */
/*03d0*/ LDG.E R21, [R2.64+0x1c] ; /* 0x00001c0602157981 */
/* 0x000f22000c1e1900 */
/*03e0*/ IMAD R26, R16, R19, R26 ; /* 0x00000013101a7224 */
/* 0x020fc600078e021a */
/*03f0*/ LDG.E R16, [R6.64+0x20] ; /* 0x0000200606107981 */
/* 0x000f68000c1e1900 */
/*0400*/ LDG.E R19, [R2.64+0x20] ; /* 0x0000200602137981 */
/* 0x000f62000c1e1900 */
/*0410*/ IMAD R24, R17, R24, R26 ; /* 0x0000001811187224 */
/* 0x000fc600078e021a */
/*0420*/ LDG.E R17, [R6.64+0x24] ; /* 0x0000240606117981 */
/* 0x000ee8000c1e1900 */
/*0430*/ LDG.E R26, [R2.64+0x38] ; /* 0x00003806021a7981 */
/* 0x000ee2000c1e1900 */
/*0440*/ IMAD R24, R22, R25, R24 ; /* 0x0000001916187224 */
/* 0x000fc600078e0218 */
/*0450*/ LDG.E R22, [R6.64+0x28] ; /* 0x0000280606167981 */
/* 0x000ee8000c1e1900 */
/*0460*/ LDG.E R25, [R2.64+0x28] ; /* 0x0000280602197981 */
/* 0x000ee2000c1e1900 */
/*0470*/ IMAD R24, R20, R23, R24 ; /* 0x0000001714187224 */
/* 0x004fc600078e0218 */
/*0480*/ LDG.E R20, [R6.64+0x2c] ; /* 0x00002c0606147981 */
/* 0x000ea8000c1e1900 */
/*0490*/ LDG.E R23, [R2.64+0x2c] ; /* 0x00002c0602177981 */
/* 0x000ea2000c1e1900 */
/*04a0*/ IMAD R24, R18, R21, R24 ; /* 0x0000001512187224 */
/* 0x010fc600078e0218 */
/*04b0*/ LDG.E R18, [R6.64+0x30] ; /* 0x0000300606127981 */
/* 0x000f28000c1e1900 */
/*04c0*/ LDG.E R21, [R2.64+0x30] ; /* 0x0000300602157981 */
/* 0x000f22000c1e1900 */
/*04d0*/ IMAD R28, R16, R19, R24 ; /* 0x00000013101c7224 */
/* 0x020fc600078e0218 */
/*04e0*/ LDG.E R16, [R6.64+0x34] ; /* 0x0000340606107981 */
/* 0x000f68000c1e1900 */
/*04f0*/ LDG.E R19, [R6.64+0x38] ; /* 0x0000380606137981 */
/* 0x000f68000c1e1900 */
/*0500*/ LDG.E R24, [R6.64+0x3c] ; /* 0x00003c0606187981 */
/* 0x000f62000c1e1900 */
/*0510*/ IMAD R14, R17, R14, R28 ; /* 0x0000000e110e7224 */
/* 0x008fe200078e021c */
/*0520*/ IADD3 R12, R12, -0x10, RZ ; /* 0xfffffff00c0c7810 */
/* 0x000fc60007ffe0ff */
/*0530*/ IMAD R14, R22, R25, R14 ; /* 0x00000019160e7224 */
/* 0x000fe200078e020e */
/*0540*/ ISETP.GT.AND P3, PT, R12, 0xc, PT ; /* 0x0000000c0c00780c */
/* 0x000fe40003f64270 */
/*0550*/ IADD3 R0, R0, 0x10, RZ ; /* 0x0000001000007810 */
/* 0x000fe20007ffe0ff */
/*0560*/ IMAD R14, R20, R23, R14 ; /* 0x00000017140e7224 */
/* 0x004fc800078e020e */
/*0570*/ IMAD R14, R18, R21, R14 ; /* 0x00000015120e7224 */
/* 0x010fc800078e020e */
/*0580*/ IMAD R14, R16, R27, R14 ; /* 0x0000001b100e7224 */
/* 0x020fe200078e020e */
/*0590*/ IADD3 R16, P4, R4, 0x40, RZ ; /* 0x0000004004107810 */
/* 0x000fc60007f9e0ff */
/*05a0*/ IMAD R14, R19, R26, R14 ; /* 0x0000001a130e7224 */
/* 0x000fe200078e020e */
/*05b0*/ IADD3.X R17, RZ, R5, RZ, P4, !PT ; /* 0x00000005ff117210 */
/* 0x000fc600027fe4ff */
/*05c0*/ IMAD R14, R24, R29, R14 ; /* 0x0000001d180e7224 */
/* 0x000fe200078e020e */
/*05d0*/ @P3 BRA 0x240 ; /* 0xfffffc6000003947 */
/* 0x000fea000383ffff */
/*05e0*/ ISETP.GT.AND P3, PT, R12, 0x4, PT ; /* 0x000000040c00780c */
/* 0x000fda0003f64270 */
/*05f0*/ @!P3 BRA 0x7f0 ; /* 0x000001f00000b947 */
/* 0x000fea0003800000 */
/*0600*/ IMAD.WIDE R2, R15, 0x4, R16 ; /* 0x000000040f027825 */
/* 0x000fc800078e0210 */
/*0610*/ IMAD.WIDE R4, R13, 0x4, R16 ; /* 0x000000040d047825 */
/* 0x000fe200078e0210 */
/*0620*/ LDG.E R23, [R2.64] ; /* 0x0000000602177981 */
/* 0x000ea8000c1e1900 */
/*0630*/ LDG.E R22, [R4.64] ; /* 0x0000000604167981 */
/* 0x000ea8000c1e1900 */
/*0640*/ LDG.E R6, [R2.64+0x4] ; /* 0x0000040602067981 */
/* 0x000ee8000c1e1900 */
/*0650*/ LDG.E R7, [R4.64+0x4] ; /* 0x0000040604077981 */
/* 0x000ee8000c1e1900 */
/*0660*/ LDG.E R18, [R2.64+0x8] ; /* 0x0000080602127981 */
/* 0x000f28000c1e1900 */
/*0670*/ LDG.E R19, [R4.64+0x8] ; /* 0x0000080604137981 */
/* 0x000f28000c1e1900 */
/*0680*/ LDG.E R20, [R2.64+0xc] ; /* 0x00000c0602147981 */
/* 0x000f68000c1e1900 */
/*0690*/ LDG.E R21, [R4.64+0xc] ; /* 0x00000c0604157981 */
/* 0x000f68000c1e1900 */
/*06a0*/ LDG.E R24, [R4.64+0x10] ; /* 0x0000100604187981 */
/* 0x000f68000c1e1900 */
/*06b0*/ LDG.E R29, [R4.64+0x14] ; /* 0x00001406041d7981 */
/* 0x000f68000c1e1900 */
/*06c0*/ LDG.E R27, [R4.64+0x18] ; /* 0x00001806041b7981 */
/* 0x000f68000c1e1900 */
/*06d0*/ LDG.E R25, [R2.64+0x1c] ; /* 0x00001c0602197981 */
/* 0x000f68000c1e1900 */
/*06e0*/ LDG.E R26, [R4.64+0x1c] ; /* 0x00001c06041a7981 */
/* 0x000f62000c1e1900 */
/*06f0*/ IMAD R28, R23, R22, R14 ; /* 0x00000016171c7224 */
/* 0x004fc600078e020e */
/*0700*/ LDG.E R23, [R2.64+0x10] ; /* 0x0000100602177981 */
/* 0x000ea8000c1e1900 */
/*0710*/ LDG.E R22, [R2.64+0x14] ; /* 0x0000140602167981 */
/* 0x000ea8000c1e1900 */
/*0720*/ LDG.E R14, [R2.64+0x18] ; /* 0x00001806020e7981 */
/* 0x000ea2000c1e1900 */
/*0730*/ IMAD R6, R6, R7, R28 ; /* 0x0000000706067224 */
/* 0x008fc800078e021c */
/*0740*/ IMAD R6, R18, R19, R6 ; /* 0x0000001312067224 */
/* 0x010fc800078e0206 */
/*0750*/ IMAD R6, R20, R21, R6 ; /* 0x0000001514067224 */
/* 0x020fe200078e0206 */
/*0760*/ IADD3 R16, P3, R16, 0x20, RZ ; /* 0x0000002010107810 */
/* 0x000fe40007f7e0ff */
/*0770*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0780*/ IADD3 R0, R0, 0x8, RZ ; /* 0x0000000800007810 */
/* 0x000fe40007ffe0ff */
/*0790*/ IADD3 R12, R12, -0x8, RZ ; /* 0xfffffff80c0c7810 */
/* 0x000fe40007ffe0ff */
/*07a0*/ IADD3.X R17, RZ, R17, RZ, P3, !PT ; /* 0x00000011ff117210 */
/* 0x000fe20001ffe4ff */
/*07b0*/ IMAD R6, R23, R24, R6 ; /* 0x0000001817067224 */
/* 0x004fc800078e0206 */
/*07c0*/ IMAD R6, R22, R29, R6 ; /* 0x0000001d16067224 */
/* 0x000fc800078e0206 */
/*07d0*/ IMAD R14, R14, R27, R6 ; /* 0x0000001b0e0e7224 */
/* 0x000fc800078e0206 */
/*07e0*/ IMAD R14, R25, R26, R14 ; /* 0x0000001a190e7224 */
/* 0x000fe400078e020e */
/*07f0*/ ISETP.NE.OR P0, PT, R12, RZ, P0 ; /* 0x000000ff0c00720c */
/* 0x000fda0000705670 */
/*0800*/ @!P0 BRA 0x950 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0810*/ IMAD.WIDE R4, R13, 0x4, R16 ; /* 0x000000040d047825 */
/* 0x000fc800078e0210 */
/*0820*/ IMAD.WIDE R2, R15, 0x4, R16 ; /* 0x000000040f027825 */
/* 0x000fe200078e0210 */
/*0830*/ LDG.E R6, [R4.64] ; /* 0x0000000604067981 */
/* 0x000ea8000c1e1900 */
/*0840*/ LDG.E R7, [R2.64] ; /* 0x0000000602077981 */
/* 0x000ea8000c1e1900 */
/*0850*/ LDG.E R18, [R4.64+0x4] ; /* 0x0000040604127981 */
/* 0x000ee8000c1e1900 */
/*0860*/ LDG.E R19, [R2.64+0x4] ; /* 0x0000040602137981 */
/* 0x000ee8000c1e1900 */
/*0870*/ LDG.E R21, [R2.64+0x8] ; /* 0x0000080602157981 */
/* 0x000f28000c1e1900 */
/*0880*/ LDG.E R20, [R4.64+0x8] ; /* 0x0000080604147981 */
/* 0x000f28000c1e1900 */
/*0890*/ LDG.E R23, [R2.64+0xc] ; /* 0x00000c0602177981 */
/* 0x000f68000c1e1900 */
/*08a0*/ LDG.E R22, [R4.64+0xc] ; /* 0x00000c0604167981 */
/* 0x000f62000c1e1900 */
/*08b0*/ IADD3 R12, R12, -0x4, RZ ; /* 0xfffffffc0c0c7810 */
/* 0x000fc40007ffe0ff */
/*08c0*/ IADD3 R16, P3, R16, 0x10, RZ ; /* 0x0000001010107810 */
/* 0x000fe40007f7e0ff */
/*08d0*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f05270 */
/*08e0*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x000fe20007ffe0ff */
/*08f0*/ IMAD.X R17, RZ, RZ, R17, P3 ; /* 0x000000ffff117224 */
/* 0x000fe400018e0611 */
/*0900*/ IMAD R6, R7, R6, R14 ; /* 0x0000000607067224 */
/* 0x004fc800078e020e */
/*0910*/ IMAD R6, R19, R18, R6 ; /* 0x0000001213067224 */
/* 0x008fc800078e0206 */
/*0920*/ IMAD R6, R21, R20, R6 ; /* 0x0000001415067224 */
/* 0x010fc800078e0206 */
/*0930*/ IMAD R14, R23, R22, R6 ; /* 0x00000016170e7224 */
/* 0x020fe200078e0206 */
/*0940*/ @P0 BRA 0x810 ; /* 0xfffffec000000947 */
/* 0x000fea000383ffff */
/*0950*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*0960*/ @!P0 BRA 0xa80 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0970*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0980*/ IADD3 R4, R15, R0.reuse, RZ ; /* 0x000000000f047210 */
/* 0x080fe40007ffe0ff */
/*0990*/ IADD3 R2, R13, R0, RZ ; /* 0x000000000d027210 */
/* 0x000fce0007ffe0ff */
/*09a0*/ IMAD.WIDE R4, R4, R3, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0203 */
/*09b0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe200078e0203 */
/*09c0*/ LDG.E R7, [R4.64] ; /* 0x0000000604077981 */
/* 0x000ea8000c1e1900 */
/*09d0*/ LDG.E R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x000ea2000c1e1900 */
/*09e0*/ ISETP.NE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fe20003f05270 */
/*09f0*/ IMAD R14, R7, R0, R14 ; /* 0x00000000070e7224 */
/* 0x004fd800078e020e */
/*0a00*/ @!P0 BRA 0xa80 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*0a10*/ ISETP.NE.AND P0, PT, R8, 0x2, PT ; /* 0x000000020800780c */
/* 0x000fe20003f05270 */
/*0a20*/ LDG.E R7, [R4.64+0x4] ; /* 0x0000040604077981 */
/* 0x000ea8000c1e1900 */
/*0a30*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040602007981 */
/* 0x000eb0000c1e1900 */
/*0a40*/ @P0 LDG.E R15, [R4.64+0x8] ; /* 0x00000806040f0981 */
/* 0x000ee8000c1e1900 */
/*0a50*/ @P0 LDG.E R6, [R2.64+0x8] ; /* 0x0000080602060981 */
/* 0x000ee2000c1e1900 */
/*0a60*/ IMAD R14, R7, R0, R14 ; /* 0x00000000070e7224 */
/* 0x004fc800078e020e */
/*0a70*/ @P0 IMAD R14, R15, R6, R14 ; /* 0x000000060f0e0224 */
/* 0x008fe400078e020e */
/*0a80*/ @!P2 BRA 0x150 ; /* 0xfffff6c00000a947 */
/* 0x000fea000383ffff */
/*0a90*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0aa0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff007624 */
/* 0x000fc800078e00ff */
/*0ab0*/ IMAD R9, R0, c[0x0][0x0], R9 ; /* 0x0000000000097a24 */
/* 0x000fca00078e0209 */
/*0ac0*/ ISETP.GE.AND P0, PT, R9, c[0x0][0x170], PT ; /* 0x00005c0009007a0c */
/* 0x000fda0003f06270 */
/*0ad0*/ @!P0 BRA 0x100 ; /* 0xfffff62000008947 */
/* 0x000fea000383ffff */
/*0ae0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0af0*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */
/* 0x000e220000000000 */
/*0b00*/ REDUX.SUM UR5, R14 ; /* 0x000000000e0573c4 */
/* 0x000e62000000c000 */
/*0b10*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe200038e0100 */
/*0b20*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0b30*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fe200080e0000 */
/*0b40*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fca0000000f00 */
/*0b50*/ ISETP.EQ.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x001fe4000bf02070 */
/*0b60*/ MOV R5, UR5 ; /* 0x0000000500057c02 */
/* 0x002fd60008000f00 */
/*0b70*/ @P0 RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200098e */
/* 0x000fe2000c10e186 */
/*0b80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b90*/ BRA 0xb90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9procpairsPiS_i
.globl _Z9procpairsPiS_i
.p2align 8
.type _Z9procpairsPiS_i,@function
_Z9procpairsPiS_i:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s5, 0xffff
s_mov_b32 s5, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_11
s_load_b32 s7, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x0
v_mul_lo_u32 v2, s4, v1
v_mov_b32_e32 v0, 0
s_cmp_gt_i32 s4, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_lshlrev_b32_e32 v10, 1, v2
s_waitcnt lgkmcnt(0)
s_mul_i32 s6, s7, s6
s_cselect_b32 s7, -1, 0
s_mul_i32 s9, s6, s4
s_lshl_b32 s10, s9, 1
s_branch .LBB0_4
.LBB0_2:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s12
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
s_or_b32 exec_lo, exec_lo, s11
v_add_nc_u32_e32 v1, s6, v1
v_add_nc_u32_e32 v10, s10, v10
v_add_nc_u32_e32 v2, s9, v2
v_cmp_le_i32_e32 vcc_lo, s4, v1
s_or_b32 s8, vcc_lo, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execz .LBB0_10
.LBB0_4:
v_lshlrev_b32_e32 v11, 1, v1
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s4, v11
s_cbranch_execz .LBB0_3
v_ashrrev_i32_e32 v3, 31, v2
v_mov_b32_e32 v5, v10
s_mov_b32 s12, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_7
.p2align 6
.LBB0_6:
v_add_nc_u32_e32 v11, 1, v11
v_add_nc_u32_e32 v5, s4, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s4, v11
s_or_b32 s12, vcc_lo, s12
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execz .LBB0_2
.LBB0_7:
s_and_not1_b32 vcc_lo, exec_lo, s7
s_cbranch_vccnz .LBB0_6
v_ashrrev_i32_e32 v6, 31, v5
v_dual_mov_b32 v9, v4 :: v_dual_mov_b32 v8, v3
s_mov_b32 s13, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
.p2align 6
.LBB0_9:
global_load_b32 v14, v[8:9], off
global_load_b32 v15, v[6:7], off
v_add_co_u32 v6, vcc_lo, v6, 4
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, v8, 4
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
s_add_i32 s13, s13, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s13, 0
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[12:13], null, v15, v14, v[0:1]
v_mov_b32_e32 v0, v12
s_cbranch_scc1 .LBB0_9
s_branch .LBB0_6
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s8
.LBB0_11:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s5
s_mov_b32 s3, exec_lo
s_mov_b32 s2, 0
.LBB0_12:
s_ctz_i32_b32 s4, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s5, v0, s4
s_lshl_b32 s4, 1, s4
s_and_not1_b32 s3, s3, s4
s_delay_alu instid0(VALU_DEP_1)
s_add_i32 s2, s2, s5
s_cmp_lg_u32 s3, 0
s_cbranch_scc1 .LBB0_12
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_15
s_load_b64 s[0:1], s[0:1], 0x8
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9procpairsPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9procpairsPiS_i, .Lfunc_end0-_Z9procpairsPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9procpairsPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9procpairsPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ae176_00000000-6_mutual_outlinks.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z9procpairsPiS_iPiS_i
.type _Z31__device_stub__Z9procpairsPiS_iPiS_i, @function
_Z31__device_stub__Z9procpairsPiS_iPiS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9procpairsPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z9procpairsPiS_iPiS_i, .-_Z31__device_stub__Z9procpairsPiS_iPiS_i
.globl _Z9procpairsPiS_i
.type _Z9procpairsPiS_i, @function
_Z9procpairsPiS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9procpairsPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9procpairsPiS_i, .-_Z9procpairsPiS_i
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $400, %edi
call malloc@PLT
movq %rax, %r13
movq %rax, %r14
movl $0, %r12d
movl $0, %ebp
jmp .L14
.L21:
call rand@PLT
leal (%rbx,%r12), %edx
movslq %edx, %rdx
movl %eax, %ecx
shrl $31, %ecx
addl %ecx, %eax
andl $1, %eax
subl %ecx, %eax
movl %eax, 0(%r13,%rdx,4)
.L12:
addl $1, %ebx
cmpl $10, %ebx
je .L20
.L13:
cmpl %ebx, %ebp
jne .L21
jmp .L12
.L20:
addl $1, %ebp
addq $44, %r14
addl $10, %r12d
cmpl $10, %ebp
je .L22
.L14:
movl $0, (%r14)
movl $0, %ebx
jmp .L13
.L22:
leaq 16(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $400, %edx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, 12(%rsp)
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 12(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 32(%rsp)
movl $1, 36(%rsp)
movl $192, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L15:
call cudaThreadSynchronize@PLT
leaq 12(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl $10, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z31__device_stub__Z9procpairsPiS_iPiS_i
jmp .L15
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9procpairsPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9procpairsPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mutual_outlinks.hip"
.globl _Z24__device_stub__procpairsPiS_i # -- Begin function _Z24__device_stub__procpairsPiS_i
.p2align 4, 0x90
.type _Z24__device_stub__procpairsPiS_i,@function
_Z24__device_stub__procpairsPiS_i: # @_Z24__device_stub__procpairsPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9procpairsPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__procpairsPiS_i, .Lfunc_end0-_Z24__device_stub__procpairsPiS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
movq %rax, %r15
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_1 Depth=1
incq %r14
addq $40, %r15
cmpq $10, %r14
je .LBB1_6
.LBB1_1: # =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
imulq $44, %r14, %rax
movl $0, (%rbx,%rax)
xorl %r12d, %r12d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_4: # in Loop: Header=BB1_2 Depth=2
incq %r12
cmpq $10, %r12
je .LBB1_5
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
cmpq %r12, %r14
je .LBB1_4
# %bb.3: # in Loop: Header=BB1_2 Depth=2
callq rand
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
andl $-2, %ecx
subl %ecx, %eax
movl %eax, (%r15,%r12,4)
jmp .LBB1_4
.LBB1_6:
leaq 24(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
movq 24(%rsp), %rdi
movl $400, %edx # imm = 0x190
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $0, 4(%rsp)
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 4(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967300, %rdi # imm = 0x100000004
leaq 188(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $10, 20(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9procpairsPiS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
leaq 4(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9procpairsPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9procpairsPiS_i,@object # @_Z9procpairsPiS_i
.section .rodata,"a",@progbits
.globl _Z9procpairsPiS_i
.p2align 3, 0x0
_Z9procpairsPiS_i:
.quad _Z24__device_stub__procpairsPiS_i
.size _Z9procpairsPiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9procpairsPiS_i"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__procpairsPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9procpairsPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define GREENWICH_LON (0.0f)
#define PI (3.141592653589793f)
#define DEG2RAD (PI / 180.0f)
#define RAD2DEG (180.0f / PI)
#define i_dt (threadIdx.z)
#define i_dxy (blockIdx.x + (blockIdx.y * gridDim.x))
#define i_dxyt (i_dxy + gridDim.x * gridDim.y * i_dt)
__device__ void getdeclination(float *declination, float *gamma)
{
const float g = gamma[i_dt] * DEG2RAD;
declination[i_dt] = round((0.006918f - 0.399912f * cos(g) +
0.070257f * sin(g) -
0.006758f * cos(2.0f * g) +
0.000907f * sin(2.0f * g) -
0.002697f * cos(3.0f * g) +
0.00148f * sin(3.0f * g)) * RAD2DEG);
}
__device__ float gethourlyangle(float *lat, float *lon,
float *decimalhour, float *gamma)
{
const float g = gamma[i_dt] * DEG2RAD;
float timeequation = (0.000075f + 0.001868f * cos(g) -
0.032077f * sin(g) -
0.014615f * cos(2.0f * g) -
0.04089f * sin(2.0f * g)) * (12.0f / PI);
float lon_diff = (GREENWICH_LON - lon[i_dxy]) * DEG2RAD;
float tst_hour = decimalhour[i_dt] - lon_diff * (12.0f / PI) +
timeequation;
float lat_sign = lat[i_dxy] / abs(lat[i_dxy]);
return ((tst_hour - 12.0f) * lat_sign * PI / 12.0f) * RAD2DEG;
}
__device__ float getzenithangle(float *declination,
float *lat, float *lon, float *decimalhour, float *gamma)
{
float hourlyangle;
hourlyangle = gethourlyangle(lat, lon, decimalhour, gamma) * DEG2RAD;
float lat_r = lat[i_dxy] * DEG2RAD;
float dec_r = declination[i_dt] * DEG2RAD;
return (acos(sin(dec_r) * sin(lat_r) + cos(dec_r) *
cos(lat_r) * cos(hourlyangle)) * RAD2DEG);
}
__device__ float getelevation(float zenithangle)
{
float za = zenithangle * DEG2RAD;
return ((PI / 2.0f) - za) * RAD2DEG;
}
__device__ float getexcentricity(float *gamma)
{
const float g = gamma[i_dt] * DEG2RAD;
return (1.000110f + 0.034221f * cos(g) +
0.001280f * sin(g) +
0.000719f * cos(2.0f * g) +
0.000077f * sin(2.0f * g));
}
__device__ float getcorrectedelevation(float elevation)
{
float e = elevation * DEG2RAD;
float p = pow(e, 2.0f);
return (e +
0.061359f * ((0.1594f + 1.1230f * e +
0.065656f * p) /
(1.0f + 28.9344f * e +
277.3971f * p))) * RAD2DEG;
}
__device__ float getopticalpath(float correctedelevation,
float *dem, float *HEIGHT)
{
float ce = correctedelevation;
if (ce < 0) { ce = 0.0f; }
// In the next line the correctedelevation is used over a degree base.
float p = pow(ce + 6.07995f, -1.6364f);
return(exp(-dem[i_dxy]/HEIGHT[0]) /
(sin(ce * DEG2RAD) + 0.50572f * p));
}
__device__ float getopticaldepth(float opticalpath)
{
float tmp = 1.0f;
if (opticalpath <= 20.0f){
tmp = (6.6296f + 1.7513f * opticalpath -
0.1202f * pow(opticalpath, 2.0f) +
0.0065f * pow(opticalpath, 3.0f) -
0.00013f * pow(opticalpath, 4.0f));
} else {
tmp = (10.4f + 0.718f * opticalpath);
}
tmp = 1.0f / tmp;
return tmp;
}
__device__ float getbeamtransmission(float *linke,
float opticalpath, float opticaldepth)
{
return exp(-0.8662f * linke[i_dxyt] * opticalpath *
opticaldepth);
}
__device__ float gethorizontalirradiance(float *EXT_RAD,
float *excentricity, float *zenithangle)
{
float radzenith = zenithangle[i_dxyt] * DEG2RAD;
return EXT_RAD[0] * excentricity[i_dt] *
cos(radzenith);
}
__device__ float getbeamirradiance(float *EXT_RAD,
float *excentricity, float *zenithangle, float solarelevation,
float *linke, float *dem, float *HEIGHT)
{
float corrected = getcorrectedelevation(solarelevation);
float opticalpath = getopticalpath(corrected, dem,
HEIGHT);
float opticaldepth = getopticaldepth(opticalpath);
return gethorizontalirradiance(EXT_RAD,
excentricity, zenithangle) *
getbeamtransmission(linke, opticalpath,
opticaldepth);
}
__device__ float getzenithdiffusetransmitance(float *linke)
{
return -0.015843f + 0.030543f * linke[i_dxyt] +
0.0003797f * pow(linke[i_dxyt], 2.0f);
}
__device__ float getangularcorrection(float solarelevation,
float *linke)
{
float sin_se = sin(solarelevation * DEG2RAD);
float squared_linke = pow(linke[i_dxyt], 2.0f);
float a0 = 0.264631f - 0.061581f * linke[i_dxyt] +
0.0031408f * squared_linke;
float a1 = 2.0402f + 0.018945f * linke[i_dxyt] -
0.011161f * squared_linke;
float a2 = -1.3025f + 0.039231f * linke[i_dxyt] +
0.0085079f * squared_linke;
float ztdifftr = getzenithdiffusetransmitance(linke);
if (a0 * ztdifftr < 0.002f){
a0 = 0.002f / ztdifftr;
}
return a0 + a1 * sin_se + a2 * pow(sin_se, 2.0f);
}
__device__ float getdiffusetransmitance(float *linke,
float solarelevation)
{
return getzenithdiffusetransmitance(linke) *
getangularcorrection(solarelevation, linke);
}
__device__ void gettransmitance(float *transmitance, float *linke,
float opticalpath, float opticaldepth, float solarelevation)
{
transmitance[i_dxyt] = getbeamtransmission(linke, opticalpath,
opticaldepth) +
getdiffusetransmitance(linke, solarelevation);
}
__device__ float getdiffuseirradiance(float *EXT_RAD,
float *excentricity, float solarelevation, float *linketurbidity)
{
return EXT_RAD[0] * excentricity[i_dt] *
getdiffusetransmitance(linketurbidity, solarelevation);
}
__device__ void getglobalirradiance(float *gc, float beamirradiance,
float diffuseirradiance)
{
gc[i_dxyt] = beamirradiance + diffuseirradiance;
}
#define rpol 6356.5838f
#define req 6378.1690f
#define h 42166.55637f
//define h 42164.0f
__device__ float getsatellitalzenithangle(float *lat,
float *lon, float *sub_lon)
{
float la = lat[i_dxy] * DEG2RAD;
float lon_diff = (lon[i_dxy] - sub_lon[0]) * DEG2RAD;
float lat_cos_only = cos(la);
float re = rpol / (sqrt(1 - (pow(req, 2.0f) - pow(rpol, 2.0f)) /
(pow(req, 2.0f)) * pow(lat_cos_only, 2.0f)));
float lat_cos = re * lat_cos_only;
float r1 = h - lat_cos * cos(lon_diff);
float r2 = - lat_cos * sin(lon_diff);
float r3 = re * sin(la);
float rs = sqrt(pow(r1, 2.0f) + pow(r2, 2.0f) + pow(r3, 2.0f));
return (PI - acos((pow(h, 2.0f) -
pow(re, 2.0f) - pow(rs, 2.0f)) / (-2.0f * re * rs))) * RAD2DEG;
}
__device__ float getatmosphericradiance(float *EXT_RAD,
float *i0met, float diffuseclearsky, float satellitalzenithangle)
{
float anglerelation = pow(0.5f / cos(satellitalzenithangle * DEG2RAD),
0.8f);
return ((i0met[0] * diffuseclearsky * anglerelation) /
(PI * EXT_RAD[0]));
}
__device__ float getdifferentialalbedo(float firstalbedo,
float secondalbedo, float t_earth, float t_sat)
{
return (firstalbedo - secondalbedo) / (t_earth * t_sat);
}
__device__ void getalbedo(float *albedo, float radiance,
float *i0met, float *excentricity, float zenithangle)
{
albedo[i_dxyt] = ((PI * radiance) /
(i0met[0] * excentricity[i_dt] *
cos(zenithangle * DEG2RAD)));
}
__device__ float geteffectivealbedo(float solarangle)
{
return 0.78f - 0.13f * (1.0f -
exp(-4.0f * pow(cos(solarangle * DEG2RAD), 5.0f)));
}
__device__ void getcloudalbedo(float *result, float effectivealbedo,
float atmosphericalbedo, float t_earth, float t_sat)
{
float ca = getdifferentialalbedo(effectivealbedo, atmosphericalbedo,
t_earth, t_sat);
if (ca < 0.2f) { ca = 0.2f; }
float effectiveproportion = 2.24f * effectivealbedo;
if ( ca > effectiveproportion) { ca = effectiveproportion; }
result[i_dxyt] = ca;
}
__global__ void update_temporalcache(float *declination,
float *solarangle, float *solarelevation, float *excentricity,
float *gc, float *atmosphericalbedo, float *t_sat, float *t_earth,
float *cloudalbedo, float *lat, float *lon, float *decimalhour,
float *gamma, float *dem, float *linke, float *SAT_LON,
float *i0met, float *EXT_RAD, float *HEIGHT)
{
float bc, dc, satellitalzenithangle, atmosphericradiance,
satellitalelevation, satellital_opticalpath,
satellital_opticaldepth, solar_opticalpath,
solar_opticaldepth, effectivealbedo;
getdeclination(declination, gamma);
solarangle[i_dxyt] = getzenithangle(declination, lat, lon,
decimalhour, gamma);
solarelevation[i_dxyt] = getelevation(solarangle[i_dxyt]);
excentricity[i_dt] = getexcentricity(gamma);
bc = getbeamirradiance(EXT_RAD, excentricity, solarangle,
solarelevation[i_dxyt], linke, dem, HEIGHT);
dc = getdiffuseirradiance(EXT_RAD, excentricity,
solarelevation[i_dxyt], linke);
getglobalirradiance(gc, bc, dc);
satellitalzenithangle = getsatellitalzenithangle(lat, lon, SAT_LON);
atmosphericradiance = getatmosphericradiance(EXT_RAD, i0met,
dc,
satellitalzenithangle);
getalbedo(atmosphericalbedo, atmosphericradiance, i0met,
excentricity, satellitalzenithangle);
satellitalelevation = getelevation(satellitalzenithangle);
satellital_opticalpath = getopticalpath(
getcorrectedelevation(satellitalelevation), dem, HEIGHT);
satellital_opticaldepth = getopticaldepth(satellital_opticalpath);
gettransmitance(t_sat, linke, satellital_opticalpath,
satellital_opticaldepth, satellitalelevation);
solar_opticalpath = getopticalpath(
getcorrectedelevation(solarelevation[i_dxyt]), dem,
HEIGHT);
solar_opticaldepth = getopticaldepth(solar_opticalpath);
gettransmitance(t_earth, linke, solar_opticalpath, solar_opticaldepth,
solarelevation[i_dxyt]);
effectivealbedo = geteffectivealbedo(solarangle[i_dxyt]);
getcloudalbedo(cloudalbedo, effectivealbedo,
atmosphericalbedo[i_dxyt], t_earth[i_dxyt],
t_sat[i_dxyt]);
} | .file "tmpxft_000d0909_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14getdeclinationPfS_
.type _Z14getdeclinationPfS_, @function
_Z14getdeclinationPfS_:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z14getdeclinationPfS_, .-_Z14getdeclinationPfS_
.globl _Z14gethourlyanglePfS_S_S_
.type _Z14gethourlyanglePfS_S_S_, @function
_Z14gethourlyanglePfS_S_S_:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z14gethourlyanglePfS_S_S_, .-_Z14gethourlyanglePfS_S_S_
.globl _Z14getzenithanglePfS_S_S_S_
.type _Z14getzenithanglePfS_S_S_S_, @function
_Z14getzenithanglePfS_S_S_S_:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z14getzenithanglePfS_S_S_S_, .-_Z14getzenithanglePfS_S_S_S_
.globl _Z12getelevationf
.type _Z12getelevationf, @function
_Z12getelevationf:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z12getelevationf, .-_Z12getelevationf
.globl _Z15getexcentricityPf
.type _Z15getexcentricityPf, @function
_Z15getexcentricityPf:
.LFB2061:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z15getexcentricityPf, .-_Z15getexcentricityPf
.globl _Z21getcorrectedelevationf
.type _Z21getcorrectedelevationf, @function
_Z21getcorrectedelevationf:
.LFB2062:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2062:
.size _Z21getcorrectedelevationf, .-_Z21getcorrectedelevationf
.globl _Z14getopticalpathfPfS_
.type _Z14getopticalpathfPfS_, @function
_Z14getopticalpathfPfS_:
.LFB2063:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2063:
.size _Z14getopticalpathfPfS_, .-_Z14getopticalpathfPfS_
.globl _Z15getopticaldepthf
.type _Z15getopticaldepthf, @function
_Z15getopticaldepthf:
.LFB2064:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2064:
.size _Z15getopticaldepthf, .-_Z15getopticaldepthf
.globl _Z19getbeamtransmissionPfff
.type _Z19getbeamtransmissionPfff, @function
_Z19getbeamtransmissionPfff:
.LFB2065:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2065:
.size _Z19getbeamtransmissionPfff, .-_Z19getbeamtransmissionPfff
.globl _Z23gethorizontalirradiancePfS_S_
.type _Z23gethorizontalirradiancePfS_S_, @function
_Z23gethorizontalirradiancePfS_S_:
.LFB2066:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2066:
.size _Z23gethorizontalirradiancePfS_S_, .-_Z23gethorizontalirradiancePfS_S_
.globl _Z17getbeamirradiancePfS_S_fS_S_S_
.type _Z17getbeamirradiancePfS_S_fS_S_S_, @function
_Z17getbeamirradiancePfS_S_fS_S_S_:
.LFB2067:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2067:
.size _Z17getbeamirradiancePfS_S_fS_S_S_, .-_Z17getbeamirradiancePfS_S_fS_S_S_
.globl _Z28getzenithdiffusetransmitancePf
.type _Z28getzenithdiffusetransmitancePf, @function
_Z28getzenithdiffusetransmitancePf:
.LFB2068:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2068:
.size _Z28getzenithdiffusetransmitancePf, .-_Z28getzenithdiffusetransmitancePf
.globl _Z20getangularcorrectionfPf
.type _Z20getangularcorrectionfPf, @function
_Z20getangularcorrectionfPf:
.LFB2069:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2069:
.size _Z20getangularcorrectionfPf, .-_Z20getangularcorrectionfPf
.globl _Z22getdiffusetransmitancePff
.type _Z22getdiffusetransmitancePff, @function
_Z22getdiffusetransmitancePff:
.LFB2070:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2070:
.size _Z22getdiffusetransmitancePff, .-_Z22getdiffusetransmitancePff
.globl _Z15gettransmitancePfS_fff
.type _Z15gettransmitancePfS_fff, @function
_Z15gettransmitancePfS_fff:
.LFB2071:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2071:
.size _Z15gettransmitancePfS_fff, .-_Z15gettransmitancePfS_fff
.globl _Z20getdiffuseirradiancePfS_fS_
.type _Z20getdiffuseirradiancePfS_fS_, @function
_Z20getdiffuseirradiancePfS_fS_:
.LFB2072:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2072:
.size _Z20getdiffuseirradiancePfS_fS_, .-_Z20getdiffuseirradiancePfS_fS_
.globl _Z19getglobalirradiancePfff
.type _Z19getglobalirradiancePfff, @function
_Z19getglobalirradiancePfff:
.LFB2073:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2073:
.size _Z19getglobalirradiancePfff, .-_Z19getglobalirradiancePfff
.globl _Z24getsatellitalzenithanglePfS_S_
.type _Z24getsatellitalzenithanglePfS_S_, @function
_Z24getsatellitalzenithanglePfS_S_:
.LFB2074:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2074:
.size _Z24getsatellitalzenithanglePfS_S_, .-_Z24getsatellitalzenithanglePfS_S_
.globl _Z22getatmosphericradiancePfS_ff
.type _Z22getatmosphericradiancePfS_ff, @function
_Z22getatmosphericradiancePfS_ff:
.LFB2075:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2075:
.size _Z22getatmosphericradiancePfS_ff, .-_Z22getatmosphericradiancePfS_ff
.globl _Z21getdifferentialalbedoffff
.type _Z21getdifferentialalbedoffff, @function
_Z21getdifferentialalbedoffff:
.LFB2076:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2076:
.size _Z21getdifferentialalbedoffff, .-_Z21getdifferentialalbedoffff
.globl _Z9getalbedoPffS_S_f
.type _Z9getalbedoPffS_S_f, @function
_Z9getalbedoPffS_S_f:
.LFB2077:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2077:
.size _Z9getalbedoPffS_S_f, .-_Z9getalbedoPffS_S_f
.globl _Z18geteffectivealbedof
.type _Z18geteffectivealbedof, @function
_Z18geteffectivealbedof:
.LFB2078:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2078:
.size _Z18geteffectivealbedof, .-_Z18geteffectivealbedof
.globl _Z14getcloudalbedoPfffff
.type _Z14getcloudalbedoPfffff, @function
_Z14getcloudalbedoPfffff:
.LFB2079:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2079:
.size _Z14getcloudalbedoPfffff, .-_Z14getcloudalbedoPfffff
.globl _Z76__device_stub__Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_PfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
.type _Z76__device_stub__Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_PfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_, @function
_Z76__device_stub__Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_PfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_:
.LFB2104:
.cfi_startproc
endbr64
subq $392, %rsp
.cfi_def_cfa_offset 400
movq %rdi, 152(%rsp)
movq %rsi, 144(%rsp)
movq %rdx, 136(%rsp)
movq %rcx, 128(%rsp)
movq %r8, 120(%rsp)
movq %r9, 112(%rsp)
movq 400(%rsp), %rax
movq %rax, 104(%rsp)
movq 408(%rsp), %rax
movq %rax, 96(%rsp)
movq 416(%rsp), %rax
movq %rax, 88(%rsp)
movq 424(%rsp), %rax
movq %rax, 80(%rsp)
movq 432(%rsp), %rax
movq %rax, 72(%rsp)
movq 440(%rsp), %rax
movq %rax, 64(%rsp)
movq 448(%rsp), %rax
movq %rax, 56(%rsp)
movq 456(%rsp), %rax
movq %rax, 48(%rsp)
movq 464(%rsp), %rax
movq %rax, 40(%rsp)
movq 472(%rsp), %rax
movq %rax, 32(%rsp)
movq 480(%rsp), %rax
movq %rax, 24(%rsp)
movq 488(%rsp), %rax
movq %rax, 16(%rsp)
movq 496(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 376(%rsp)
xorl %eax, %eax
leaq 152(%rsp), %rax
movq %rax, 224(%rsp)
leaq 144(%rsp), %rax
movq %rax, 232(%rsp)
leaq 136(%rsp), %rax
movq %rax, 240(%rsp)
leaq 128(%rsp), %rax
movq %rax, 248(%rsp)
leaq 120(%rsp), %rax
movq %rax, 256(%rsp)
leaq 112(%rsp), %rax
movq %rax, 264(%rsp)
leaq 104(%rsp), %rax
movq %rax, 272(%rsp)
leaq 96(%rsp), %rax
movq %rax, 280(%rsp)
leaq 88(%rsp), %rax
movq %rax, 288(%rsp)
leaq 80(%rsp), %rax
movq %rax, 296(%rsp)
leaq 72(%rsp), %rax
movq %rax, 304(%rsp)
leaq 64(%rsp), %rax
movq %rax, 312(%rsp)
leaq 56(%rsp), %rax
movq %rax, 320(%rsp)
leaq 48(%rsp), %rax
movq %rax, 328(%rsp)
leaq 40(%rsp), %rax
movq %rax, 336(%rsp)
leaq 32(%rsp), %rax
movq %rax, 344(%rsp)
leaq 24(%rsp), %rax
movq %rax, 352(%rsp)
leaq 16(%rsp), %rax
movq %rax, 360(%rsp)
leaq 8(%rsp), %rax
movq %rax, 368(%rsp)
movl $1, 176(%rsp)
movl $1, 180(%rsp)
movl $1, 184(%rsp)
movl $1, 188(%rsp)
movl $1, 192(%rsp)
movl $1, 196(%rsp)
leaq 168(%rsp), %rcx
leaq 160(%rsp), %rdx
leaq 188(%rsp), %rsi
leaq 176(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L53
.L49:
movq 376(%rsp), %rax
subq %fs:40, %rax
jne .L54
addq $392, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
pushq 168(%rsp)
.cfi_def_cfa_offset 408
pushq 168(%rsp)
.cfi_def_cfa_offset 416
leaq 240(%rsp), %r9
movq 204(%rsp), %rcx
movl 212(%rsp), %r8d
movq 192(%rsp), %rsi
movl 200(%rsp), %edx
leaq _Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 400
jmp .L49
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2104:
.size _Z76__device_stub__Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_PfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_, .-_Z76__device_stub__Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_PfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
.globl _Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
.type _Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_, @function
_Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_:
.LFB2105:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 120(%rsp)
.cfi_def_cfa_offset 32
pushq 120(%rsp)
.cfi_def_cfa_offset 40
pushq 120(%rsp)
.cfi_def_cfa_offset 48
pushq 120(%rsp)
.cfi_def_cfa_offset 56
pushq 120(%rsp)
.cfi_def_cfa_offset 64
pushq 120(%rsp)
.cfi_def_cfa_offset 72
pushq 120(%rsp)
.cfi_def_cfa_offset 80
pushq 120(%rsp)
.cfi_def_cfa_offset 88
pushq 120(%rsp)
.cfi_def_cfa_offset 96
pushq 120(%rsp)
.cfi_def_cfa_offset 104
pushq 120(%rsp)
.cfi_def_cfa_offset 112
pushq 120(%rsp)
.cfi_def_cfa_offset 120
pushq 120(%rsp)
.cfi_def_cfa_offset 128
call _Z76__device_stub__Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_PfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
addq $120, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2105:
.size _Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_, .-_Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2107:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2107:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define GREENWICH_LON (0.0f)
#define PI (3.141592653589793f)
#define DEG2RAD (PI / 180.0f)
#define RAD2DEG (180.0f / PI)
#define i_dt (threadIdx.z)
#define i_dxy (blockIdx.x + (blockIdx.y * gridDim.x))
#define i_dxyt (i_dxy + gridDim.x * gridDim.y * i_dt)
__device__ void getdeclination(float *declination, float *gamma)
{
const float g = gamma[i_dt] * DEG2RAD;
declination[i_dt] = round((0.006918f - 0.399912f * cos(g) +
0.070257f * sin(g) -
0.006758f * cos(2.0f * g) +
0.000907f * sin(2.0f * g) -
0.002697f * cos(3.0f * g) +
0.00148f * sin(3.0f * g)) * RAD2DEG);
}
__device__ float gethourlyangle(float *lat, float *lon,
float *decimalhour, float *gamma)
{
const float g = gamma[i_dt] * DEG2RAD;
float timeequation = (0.000075f + 0.001868f * cos(g) -
0.032077f * sin(g) -
0.014615f * cos(2.0f * g) -
0.04089f * sin(2.0f * g)) * (12.0f / PI);
float lon_diff = (GREENWICH_LON - lon[i_dxy]) * DEG2RAD;
float tst_hour = decimalhour[i_dt] - lon_diff * (12.0f / PI) +
timeequation;
float lat_sign = lat[i_dxy] / abs(lat[i_dxy]);
return ((tst_hour - 12.0f) * lat_sign * PI / 12.0f) * RAD2DEG;
}
__device__ float getzenithangle(float *declination,
float *lat, float *lon, float *decimalhour, float *gamma)
{
float hourlyangle;
hourlyangle = gethourlyangle(lat, lon, decimalhour, gamma) * DEG2RAD;
float lat_r = lat[i_dxy] * DEG2RAD;
float dec_r = declination[i_dt] * DEG2RAD;
return (acos(sin(dec_r) * sin(lat_r) + cos(dec_r) *
cos(lat_r) * cos(hourlyangle)) * RAD2DEG);
}
__device__ float getelevation(float zenithangle)
{
float za = zenithangle * DEG2RAD;
return ((PI / 2.0f) - za) * RAD2DEG;
}
__device__ float getexcentricity(float *gamma)
{
const float g = gamma[i_dt] * DEG2RAD;
return (1.000110f + 0.034221f * cos(g) +
0.001280f * sin(g) +
0.000719f * cos(2.0f * g) +
0.000077f * sin(2.0f * g));
}
__device__ float getcorrectedelevation(float elevation)
{
float e = elevation * DEG2RAD;
float p = pow(e, 2.0f);
return (e +
0.061359f * ((0.1594f + 1.1230f * e +
0.065656f * p) /
(1.0f + 28.9344f * e +
277.3971f * p))) * RAD2DEG;
}
__device__ float getopticalpath(float correctedelevation,
float *dem, float *HEIGHT)
{
float ce = correctedelevation;
if (ce < 0) { ce = 0.0f; }
// In the next line the correctedelevation is used over a degree base.
float p = pow(ce + 6.07995f, -1.6364f);
return(exp(-dem[i_dxy]/HEIGHT[0]) /
(sin(ce * DEG2RAD) + 0.50572f * p));
}
__device__ float getopticaldepth(float opticalpath)
{
float tmp = 1.0f;
if (opticalpath <= 20.0f){
tmp = (6.6296f + 1.7513f * opticalpath -
0.1202f * pow(opticalpath, 2.0f) +
0.0065f * pow(opticalpath, 3.0f) -
0.00013f * pow(opticalpath, 4.0f));
} else {
tmp = (10.4f + 0.718f * opticalpath);
}
tmp = 1.0f / tmp;
return tmp;
}
__device__ float getbeamtransmission(float *linke,
float opticalpath, float opticaldepth)
{
return exp(-0.8662f * linke[i_dxyt] * opticalpath *
opticaldepth);
}
__device__ float gethorizontalirradiance(float *EXT_RAD,
float *excentricity, float *zenithangle)
{
float radzenith = zenithangle[i_dxyt] * DEG2RAD;
return EXT_RAD[0] * excentricity[i_dt] *
cos(radzenith);
}
__device__ float getbeamirradiance(float *EXT_RAD,
float *excentricity, float *zenithangle, float solarelevation,
float *linke, float *dem, float *HEIGHT)
{
float corrected = getcorrectedelevation(solarelevation);
float opticalpath = getopticalpath(corrected, dem,
HEIGHT);
float opticaldepth = getopticaldepth(opticalpath);
return gethorizontalirradiance(EXT_RAD,
excentricity, zenithangle) *
getbeamtransmission(linke, opticalpath,
opticaldepth);
}
__device__ float getzenithdiffusetransmitance(float *linke)
{
return -0.015843f + 0.030543f * linke[i_dxyt] +
0.0003797f * pow(linke[i_dxyt], 2.0f);
}
__device__ float getangularcorrection(float solarelevation,
float *linke)
{
float sin_se = sin(solarelevation * DEG2RAD);
float squared_linke = pow(linke[i_dxyt], 2.0f);
float a0 = 0.264631f - 0.061581f * linke[i_dxyt] +
0.0031408f * squared_linke;
float a1 = 2.0402f + 0.018945f * linke[i_dxyt] -
0.011161f * squared_linke;
float a2 = -1.3025f + 0.039231f * linke[i_dxyt] +
0.0085079f * squared_linke;
float ztdifftr = getzenithdiffusetransmitance(linke);
if (a0 * ztdifftr < 0.002f){
a0 = 0.002f / ztdifftr;
}
return a0 + a1 * sin_se + a2 * pow(sin_se, 2.0f);
}
__device__ float getdiffusetransmitance(float *linke,
float solarelevation)
{
return getzenithdiffusetransmitance(linke) *
getangularcorrection(solarelevation, linke);
}
__device__ void gettransmitance(float *transmitance, float *linke,
float opticalpath, float opticaldepth, float solarelevation)
{
transmitance[i_dxyt] = getbeamtransmission(linke, opticalpath,
opticaldepth) +
getdiffusetransmitance(linke, solarelevation);
}
__device__ float getdiffuseirradiance(float *EXT_RAD,
float *excentricity, float solarelevation, float *linketurbidity)
{
return EXT_RAD[0] * excentricity[i_dt] *
getdiffusetransmitance(linketurbidity, solarelevation);
}
__device__ void getglobalirradiance(float *gc, float beamirradiance,
float diffuseirradiance)
{
gc[i_dxyt] = beamirradiance + diffuseirradiance;
}
#define rpol 6356.5838f
#define req 6378.1690f
#define h 42166.55637f
//define h 42164.0f
__device__ float getsatellitalzenithangle(float *lat,
float *lon, float *sub_lon)
{
float la = lat[i_dxy] * DEG2RAD;
float lon_diff = (lon[i_dxy] - sub_lon[0]) * DEG2RAD;
float lat_cos_only = cos(la);
float re = rpol / (sqrt(1 - (pow(req, 2.0f) - pow(rpol, 2.0f)) /
(pow(req, 2.0f)) * pow(lat_cos_only, 2.0f)));
float lat_cos = re * lat_cos_only;
float r1 = h - lat_cos * cos(lon_diff);
float r2 = - lat_cos * sin(lon_diff);
float r3 = re * sin(la);
float rs = sqrt(pow(r1, 2.0f) + pow(r2, 2.0f) + pow(r3, 2.0f));
return (PI - acos((pow(h, 2.0f) -
pow(re, 2.0f) - pow(rs, 2.0f)) / (-2.0f * re * rs))) * RAD2DEG;
}
__device__ float getatmosphericradiance(float *EXT_RAD,
float *i0met, float diffuseclearsky, float satellitalzenithangle)
{
float anglerelation = pow(0.5f / cos(satellitalzenithangle * DEG2RAD),
0.8f);
return ((i0met[0] * diffuseclearsky * anglerelation) /
(PI * EXT_RAD[0]));
}
__device__ float getdifferentialalbedo(float firstalbedo,
float secondalbedo, float t_earth, float t_sat)
{
return (firstalbedo - secondalbedo) / (t_earth * t_sat);
}
__device__ void getalbedo(float *albedo, float radiance,
float *i0met, float *excentricity, float zenithangle)
{
albedo[i_dxyt] = ((PI * radiance) /
(i0met[0] * excentricity[i_dt] *
cos(zenithangle * DEG2RAD)));
}
__device__ float geteffectivealbedo(float solarangle)
{
return 0.78f - 0.13f * (1.0f -
exp(-4.0f * pow(cos(solarangle * DEG2RAD), 5.0f)));
}
__device__ void getcloudalbedo(float *result, float effectivealbedo,
float atmosphericalbedo, float t_earth, float t_sat)
{
float ca = getdifferentialalbedo(effectivealbedo, atmosphericalbedo,
t_earth, t_sat);
if (ca < 0.2f) { ca = 0.2f; }
float effectiveproportion = 2.24f * effectivealbedo;
if ( ca > effectiveproportion) { ca = effectiveproportion; }
result[i_dxyt] = ca;
}
__global__ void update_temporalcache(float *declination,
float *solarangle, float *solarelevation, float *excentricity,
float *gc, float *atmosphericalbedo, float *t_sat, float *t_earth,
float *cloudalbedo, float *lat, float *lon, float *decimalhour,
float *gamma, float *dem, float *linke, float *SAT_LON,
float *i0met, float *EXT_RAD, float *HEIGHT)
{
float bc, dc, satellitalzenithangle, atmosphericradiance,
satellitalelevation, satellital_opticalpath,
satellital_opticaldepth, solar_opticalpath,
solar_opticaldepth, effectivealbedo;
getdeclination(declination, gamma);
solarangle[i_dxyt] = getzenithangle(declination, lat, lon,
decimalhour, gamma);
solarelevation[i_dxyt] = getelevation(solarangle[i_dxyt]);
excentricity[i_dt] = getexcentricity(gamma);
bc = getbeamirradiance(EXT_RAD, excentricity, solarangle,
solarelevation[i_dxyt], linke, dem, HEIGHT);
dc = getdiffuseirradiance(EXT_RAD, excentricity,
solarelevation[i_dxyt], linke);
getglobalirradiance(gc, bc, dc);
satellitalzenithangle = getsatellitalzenithangle(lat, lon, SAT_LON);
atmosphericradiance = getatmosphericradiance(EXT_RAD, i0met,
dc,
satellitalzenithangle);
getalbedo(atmosphericalbedo, atmosphericradiance, i0met,
excentricity, satellitalzenithangle);
satellitalelevation = getelevation(satellitalzenithangle);
satellital_opticalpath = getopticalpath(
getcorrectedelevation(satellitalelevation), dem, HEIGHT);
satellital_opticaldepth = getopticaldepth(satellital_opticalpath);
gettransmitance(t_sat, linke, satellital_opticalpath,
satellital_opticaldepth, satellitalelevation);
solar_opticalpath = getopticalpath(
getcorrectedelevation(solarelevation[i_dxyt]), dem,
HEIGHT);
solar_opticaldepth = getopticaldepth(solar_opticalpath);
gettransmitance(t_earth, linke, solar_opticalpath, solar_opticaldepth,
solarelevation[i_dxyt]);
effectivealbedo = geteffectivealbedo(solarangle[i_dxyt]);
getcloudalbedo(cloudalbedo, effectivealbedo,
atmosphericalbedo[i_dxyt], t_earth[i_dxyt],
t_sat[i_dxyt]);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define GREENWICH_LON (0.0f)
#define PI (3.141592653589793f)
#define DEG2RAD (PI / 180.0f)
#define RAD2DEG (180.0f / PI)
#define i_dt (threadIdx.z)
#define i_dxy (blockIdx.x + (blockIdx.y * gridDim.x))
#define i_dxyt (i_dxy + gridDim.x * gridDim.y * i_dt)
__device__ void getdeclination(float *declination, float *gamma)
{
const float g = gamma[i_dt] * DEG2RAD;
declination[i_dt] = round((0.006918f - 0.399912f * cos(g) +
0.070257f * sin(g) -
0.006758f * cos(2.0f * g) +
0.000907f * sin(2.0f * g) -
0.002697f * cos(3.0f * g) +
0.00148f * sin(3.0f * g)) * RAD2DEG);
}
__device__ float gethourlyangle(float *lat, float *lon,
float *decimalhour, float *gamma)
{
const float g = gamma[i_dt] * DEG2RAD;
float timeequation = (0.000075f + 0.001868f * cos(g) -
0.032077f * sin(g) -
0.014615f * cos(2.0f * g) -
0.04089f * sin(2.0f * g)) * (12.0f / PI);
float lon_diff = (GREENWICH_LON - lon[i_dxy]) * DEG2RAD;
float tst_hour = decimalhour[i_dt] - lon_diff * (12.0f / PI) +
timeequation;
float lat_sign = lat[i_dxy] / abs(lat[i_dxy]);
return ((tst_hour - 12.0f) * lat_sign * PI / 12.0f) * RAD2DEG;
}
__device__ float getzenithangle(float *declination,
float *lat, float *lon, float *decimalhour, float *gamma)
{
float hourlyangle;
hourlyangle = gethourlyangle(lat, lon, decimalhour, gamma) * DEG2RAD;
float lat_r = lat[i_dxy] * DEG2RAD;
float dec_r = declination[i_dt] * DEG2RAD;
return (acos(sin(dec_r) * sin(lat_r) + cos(dec_r) *
cos(lat_r) * cos(hourlyangle)) * RAD2DEG);
}
__device__ float getelevation(float zenithangle)
{
float za = zenithangle * DEG2RAD;
return ((PI / 2.0f) - za) * RAD2DEG;
}
__device__ float getexcentricity(float *gamma)
{
const float g = gamma[i_dt] * DEG2RAD;
return (1.000110f + 0.034221f * cos(g) +
0.001280f * sin(g) +
0.000719f * cos(2.0f * g) +
0.000077f * sin(2.0f * g));
}
__device__ float getcorrectedelevation(float elevation)
{
float e = elevation * DEG2RAD;
float p = pow(e, 2.0f);
return (e +
0.061359f * ((0.1594f + 1.1230f * e +
0.065656f * p) /
(1.0f + 28.9344f * e +
277.3971f * p))) * RAD2DEG;
}
__device__ float getopticalpath(float correctedelevation,
float *dem, float *HEIGHT)
{
float ce = correctedelevation;
if (ce < 0) { ce = 0.0f; }
// In the next line the correctedelevation is used over a degree base.
float p = pow(ce + 6.07995f, -1.6364f);
return(exp(-dem[i_dxy]/HEIGHT[0]) /
(sin(ce * DEG2RAD) + 0.50572f * p));
}
__device__ float getopticaldepth(float opticalpath)
{
float tmp = 1.0f;
if (opticalpath <= 20.0f){
tmp = (6.6296f + 1.7513f * opticalpath -
0.1202f * pow(opticalpath, 2.0f) +
0.0065f * pow(opticalpath, 3.0f) -
0.00013f * pow(opticalpath, 4.0f));
} else {
tmp = (10.4f + 0.718f * opticalpath);
}
tmp = 1.0f / tmp;
return tmp;
}
__device__ float getbeamtransmission(float *linke,
float opticalpath, float opticaldepth)
{
return exp(-0.8662f * linke[i_dxyt] * opticalpath *
opticaldepth);
}
__device__ float gethorizontalirradiance(float *EXT_RAD,
float *excentricity, float *zenithangle)
{
float radzenith = zenithangle[i_dxyt] * DEG2RAD;
return EXT_RAD[0] * excentricity[i_dt] *
cos(radzenith);
}
__device__ float getbeamirradiance(float *EXT_RAD,
float *excentricity, float *zenithangle, float solarelevation,
float *linke, float *dem, float *HEIGHT)
{
float corrected = getcorrectedelevation(solarelevation);
float opticalpath = getopticalpath(corrected, dem,
HEIGHT);
float opticaldepth = getopticaldepth(opticalpath);
return gethorizontalirradiance(EXT_RAD,
excentricity, zenithangle) *
getbeamtransmission(linke, opticalpath,
opticaldepth);
}
__device__ float getzenithdiffusetransmitance(float *linke)
{
return -0.015843f + 0.030543f * linke[i_dxyt] +
0.0003797f * pow(linke[i_dxyt], 2.0f);
}
__device__ float getangularcorrection(float solarelevation,
float *linke)
{
float sin_se = sin(solarelevation * DEG2RAD);
float squared_linke = pow(linke[i_dxyt], 2.0f);
float a0 = 0.264631f - 0.061581f * linke[i_dxyt] +
0.0031408f * squared_linke;
float a1 = 2.0402f + 0.018945f * linke[i_dxyt] -
0.011161f * squared_linke;
float a2 = -1.3025f + 0.039231f * linke[i_dxyt] +
0.0085079f * squared_linke;
float ztdifftr = getzenithdiffusetransmitance(linke);
if (a0 * ztdifftr < 0.002f){
a0 = 0.002f / ztdifftr;
}
return a0 + a1 * sin_se + a2 * pow(sin_se, 2.0f);
}
__device__ float getdiffusetransmitance(float *linke,
float solarelevation)
{
return getzenithdiffusetransmitance(linke) *
getangularcorrection(solarelevation, linke);
}
__device__ void gettransmitance(float *transmitance, float *linke,
float opticalpath, float opticaldepth, float solarelevation)
{
transmitance[i_dxyt] = getbeamtransmission(linke, opticalpath,
opticaldepth) +
getdiffusetransmitance(linke, solarelevation);
}
__device__ float getdiffuseirradiance(float *EXT_RAD,
float *excentricity, float solarelevation, float *linketurbidity)
{
return EXT_RAD[0] * excentricity[i_dt] *
getdiffusetransmitance(linketurbidity, solarelevation);
}
__device__ void getglobalirradiance(float *gc, float beamirradiance,
float diffuseirradiance)
{
gc[i_dxyt] = beamirradiance + diffuseirradiance;
}
#define rpol 6356.5838f
#define req 6378.1690f
#define h 42166.55637f
//define h 42164.0f
__device__ float getsatellitalzenithangle(float *lat,
float *lon, float *sub_lon)
{
float la = lat[i_dxy] * DEG2RAD;
float lon_diff = (lon[i_dxy] - sub_lon[0]) * DEG2RAD;
float lat_cos_only = cos(la);
float re = rpol / (sqrt(1 - (pow(req, 2.0f) - pow(rpol, 2.0f)) /
(pow(req, 2.0f)) * pow(lat_cos_only, 2.0f)));
float lat_cos = re * lat_cos_only;
float r1 = h - lat_cos * cos(lon_diff);
float r2 = - lat_cos * sin(lon_diff);
float r3 = re * sin(la);
float rs = sqrt(pow(r1, 2.0f) + pow(r2, 2.0f) + pow(r3, 2.0f));
return (PI - acos((pow(h, 2.0f) -
pow(re, 2.0f) - pow(rs, 2.0f)) / (-2.0f * re * rs))) * RAD2DEG;
}
__device__ float getatmosphericradiance(float *EXT_RAD,
float *i0met, float diffuseclearsky, float satellitalzenithangle)
{
float anglerelation = pow(0.5f / cos(satellitalzenithangle * DEG2RAD),
0.8f);
return ((i0met[0] * diffuseclearsky * anglerelation) /
(PI * EXT_RAD[0]));
}
__device__ float getdifferentialalbedo(float firstalbedo,
float secondalbedo, float t_earth, float t_sat)
{
return (firstalbedo - secondalbedo) / (t_earth * t_sat);
}
__device__ void getalbedo(float *albedo, float radiance,
float *i0met, float *excentricity, float zenithangle)
{
albedo[i_dxyt] = ((PI * radiance) /
(i0met[0] * excentricity[i_dt] *
cos(zenithangle * DEG2RAD)));
}
__device__ float geteffectivealbedo(float solarangle)
{
return 0.78f - 0.13f * (1.0f -
exp(-4.0f * pow(cos(solarangle * DEG2RAD), 5.0f)));
}
__device__ void getcloudalbedo(float *result, float effectivealbedo,
float atmosphericalbedo, float t_earth, float t_sat)
{
float ca = getdifferentialalbedo(effectivealbedo, atmosphericalbedo,
t_earth, t_sat);
if (ca < 0.2f) { ca = 0.2f; }
float effectiveproportion = 2.24f * effectivealbedo;
if ( ca > effectiveproportion) { ca = effectiveproportion; }
result[i_dxyt] = ca;
}
__global__ void update_temporalcache(float *declination,
float *solarangle, float *solarelevation, float *excentricity,
float *gc, float *atmosphericalbedo, float *t_sat, float *t_earth,
float *cloudalbedo, float *lat, float *lon, float *decimalhour,
float *gamma, float *dem, float *linke, float *SAT_LON,
float *i0met, float *EXT_RAD, float *HEIGHT)
{
float bc, dc, satellitalzenithangle, atmosphericradiance,
satellitalelevation, satellital_opticalpath,
satellital_opticaldepth, solar_opticalpath,
solar_opticaldepth, effectivealbedo;
getdeclination(declination, gamma);
solarangle[i_dxyt] = getzenithangle(declination, lat, lon,
decimalhour, gamma);
solarelevation[i_dxyt] = getelevation(solarangle[i_dxyt]);
excentricity[i_dt] = getexcentricity(gamma);
bc = getbeamirradiance(EXT_RAD, excentricity, solarangle,
solarelevation[i_dxyt], linke, dem, HEIGHT);
dc = getdiffuseirradiance(EXT_RAD, excentricity,
solarelevation[i_dxyt], linke);
getglobalirradiance(gc, bc, dc);
satellitalzenithangle = getsatellitalzenithangle(lat, lon, SAT_LON);
atmosphericradiance = getatmosphericradiance(EXT_RAD, i0met,
dc,
satellitalzenithangle);
getalbedo(atmosphericalbedo, atmosphericradiance, i0met,
excentricity, satellitalzenithangle);
satellitalelevation = getelevation(satellitalzenithangle);
satellital_opticalpath = getopticalpath(
getcorrectedelevation(satellitalelevation), dem, HEIGHT);
satellital_opticaldepth = getopticaldepth(satellital_opticalpath);
gettransmitance(t_sat, linke, satellital_opticalpath,
satellital_opticaldepth, satellitalelevation);
solar_opticalpath = getopticalpath(
getcorrectedelevation(solarelevation[i_dxyt]), dem,
HEIGHT);
solar_opticaldepth = getopticaldepth(solar_opticalpath);
gettransmitance(t_earth, linke, solar_opticalpath, solar_opticaldepth,
solarelevation[i_dxyt]);
effectivealbedo = geteffectivealbedo(solarangle[i_dxyt]);
getcloudalbedo(cloudalbedo, effectivealbedo,
atmosphericalbedo[i_dxyt], t_earth[i_dxyt],
t_sat[i_dxyt]);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define GREENWICH_LON (0.0f)
#define PI (3.141592653589793f)
#define DEG2RAD (PI / 180.0f)
#define RAD2DEG (180.0f / PI)
#define i_dt (threadIdx.z)
#define i_dxy (blockIdx.x + (blockIdx.y * gridDim.x))
#define i_dxyt (i_dxy + gridDim.x * gridDim.y * i_dt)
__device__ void getdeclination(float *declination, float *gamma)
{
const float g = gamma[i_dt] * DEG2RAD;
declination[i_dt] = round((0.006918f - 0.399912f * cos(g) +
0.070257f * sin(g) -
0.006758f * cos(2.0f * g) +
0.000907f * sin(2.0f * g) -
0.002697f * cos(3.0f * g) +
0.00148f * sin(3.0f * g)) * RAD2DEG);
}
__device__ float gethourlyangle(float *lat, float *lon,
float *decimalhour, float *gamma)
{
const float g = gamma[i_dt] * DEG2RAD;
float timeequation = (0.000075f + 0.001868f * cos(g) -
0.032077f * sin(g) -
0.014615f * cos(2.0f * g) -
0.04089f * sin(2.0f * g)) * (12.0f / PI);
float lon_diff = (GREENWICH_LON - lon[i_dxy]) * DEG2RAD;
float tst_hour = decimalhour[i_dt] - lon_diff * (12.0f / PI) +
timeequation;
float lat_sign = lat[i_dxy] / abs(lat[i_dxy]);
return ((tst_hour - 12.0f) * lat_sign * PI / 12.0f) * RAD2DEG;
}
__device__ float getzenithangle(float *declination,
float *lat, float *lon, float *decimalhour, float *gamma)
{
float hourlyangle;
hourlyangle = gethourlyangle(lat, lon, decimalhour, gamma) * DEG2RAD;
float lat_r = lat[i_dxy] * DEG2RAD;
float dec_r = declination[i_dt] * DEG2RAD;
return (acos(sin(dec_r) * sin(lat_r) + cos(dec_r) *
cos(lat_r) * cos(hourlyangle)) * RAD2DEG);
}
__device__ float getelevation(float zenithangle)
{
float za = zenithangle * DEG2RAD;
return ((PI / 2.0f) - za) * RAD2DEG;
}
__device__ float getexcentricity(float *gamma)
{
const float g = gamma[i_dt] * DEG2RAD;
return (1.000110f + 0.034221f * cos(g) +
0.001280f * sin(g) +
0.000719f * cos(2.0f * g) +
0.000077f * sin(2.0f * g));
}
__device__ float getcorrectedelevation(float elevation)
{
float e = elevation * DEG2RAD;
float p = pow(e, 2.0f);
return (e +
0.061359f * ((0.1594f + 1.1230f * e +
0.065656f * p) /
(1.0f + 28.9344f * e +
277.3971f * p))) * RAD2DEG;
}
__device__ float getopticalpath(float correctedelevation,
float *dem, float *HEIGHT)
{
float ce = correctedelevation;
if (ce < 0) { ce = 0.0f; }
// In the next line the correctedelevation is used over a degree base.
float p = pow(ce + 6.07995f, -1.6364f);
return(exp(-dem[i_dxy]/HEIGHT[0]) /
(sin(ce * DEG2RAD) + 0.50572f * p));
}
__device__ float getopticaldepth(float opticalpath)
{
float tmp = 1.0f;
if (opticalpath <= 20.0f){
tmp = (6.6296f + 1.7513f * opticalpath -
0.1202f * pow(opticalpath, 2.0f) +
0.0065f * pow(opticalpath, 3.0f) -
0.00013f * pow(opticalpath, 4.0f));
} else {
tmp = (10.4f + 0.718f * opticalpath);
}
tmp = 1.0f / tmp;
return tmp;
}
__device__ float getbeamtransmission(float *linke,
float opticalpath, float opticaldepth)
{
return exp(-0.8662f * linke[i_dxyt] * opticalpath *
opticaldepth);
}
__device__ float gethorizontalirradiance(float *EXT_RAD,
float *excentricity, float *zenithangle)
{
float radzenith = zenithangle[i_dxyt] * DEG2RAD;
return EXT_RAD[0] * excentricity[i_dt] *
cos(radzenith);
}
__device__ float getbeamirradiance(float *EXT_RAD,
float *excentricity, float *zenithangle, float solarelevation,
float *linke, float *dem, float *HEIGHT)
{
float corrected = getcorrectedelevation(solarelevation);
float opticalpath = getopticalpath(corrected, dem,
HEIGHT);
float opticaldepth = getopticaldepth(opticalpath);
return gethorizontalirradiance(EXT_RAD,
excentricity, zenithangle) *
getbeamtransmission(linke, opticalpath,
opticaldepth);
}
__device__ float getzenithdiffusetransmitance(float *linke)
{
return -0.015843f + 0.030543f * linke[i_dxyt] +
0.0003797f * pow(linke[i_dxyt], 2.0f);
}
__device__ float getangularcorrection(float solarelevation,
float *linke)
{
float sin_se = sin(solarelevation * DEG2RAD);
float squared_linke = pow(linke[i_dxyt], 2.0f);
float a0 = 0.264631f - 0.061581f * linke[i_dxyt] +
0.0031408f * squared_linke;
float a1 = 2.0402f + 0.018945f * linke[i_dxyt] -
0.011161f * squared_linke;
float a2 = -1.3025f + 0.039231f * linke[i_dxyt] +
0.0085079f * squared_linke;
float ztdifftr = getzenithdiffusetransmitance(linke);
if (a0 * ztdifftr < 0.002f){
a0 = 0.002f / ztdifftr;
}
return a0 + a1 * sin_se + a2 * pow(sin_se, 2.0f);
}
__device__ float getdiffusetransmitance(float *linke,
float solarelevation)
{
return getzenithdiffusetransmitance(linke) *
getangularcorrection(solarelevation, linke);
}
__device__ void gettransmitance(float *transmitance, float *linke,
float opticalpath, float opticaldepth, float solarelevation)
{
transmitance[i_dxyt] = getbeamtransmission(linke, opticalpath,
opticaldepth) +
getdiffusetransmitance(linke, solarelevation);
}
__device__ float getdiffuseirradiance(float *EXT_RAD,
float *excentricity, float solarelevation, float *linketurbidity)
{
return EXT_RAD[0] * excentricity[i_dt] *
getdiffusetransmitance(linketurbidity, solarelevation);
}
__device__ void getglobalirradiance(float *gc, float beamirradiance,
float diffuseirradiance)
{
gc[i_dxyt] = beamirradiance + diffuseirradiance;
}
#define rpol 6356.5838f
#define req 6378.1690f
#define h 42166.55637f
//define h 42164.0f
__device__ float getsatellitalzenithangle(float *lat,
float *lon, float *sub_lon)
{
float la = lat[i_dxy] * DEG2RAD;
float lon_diff = (lon[i_dxy] - sub_lon[0]) * DEG2RAD;
float lat_cos_only = cos(la);
float re = rpol / (sqrt(1 - (pow(req, 2.0f) - pow(rpol, 2.0f)) /
(pow(req, 2.0f)) * pow(lat_cos_only, 2.0f)));
float lat_cos = re * lat_cos_only;
float r1 = h - lat_cos * cos(lon_diff);
float r2 = - lat_cos * sin(lon_diff);
float r3 = re * sin(la);
float rs = sqrt(pow(r1, 2.0f) + pow(r2, 2.0f) + pow(r3, 2.0f));
return (PI - acos((pow(h, 2.0f) -
pow(re, 2.0f) - pow(rs, 2.0f)) / (-2.0f * re * rs))) * RAD2DEG;
}
__device__ float getatmosphericradiance(float *EXT_RAD,
float *i0met, float diffuseclearsky, float satellitalzenithangle)
{
float anglerelation = pow(0.5f / cos(satellitalzenithangle * DEG2RAD),
0.8f);
return ((i0met[0] * diffuseclearsky * anglerelation) /
(PI * EXT_RAD[0]));
}
__device__ float getdifferentialalbedo(float firstalbedo,
float secondalbedo, float t_earth, float t_sat)
{
return (firstalbedo - secondalbedo) / (t_earth * t_sat);
}
__device__ void getalbedo(float *albedo, float radiance,
float *i0met, float *excentricity, float zenithangle)
{
albedo[i_dxyt] = ((PI * radiance) /
(i0met[0] * excentricity[i_dt] *
cos(zenithangle * DEG2RAD)));
}
__device__ float geteffectivealbedo(float solarangle)
{
return 0.78f - 0.13f * (1.0f -
exp(-4.0f * pow(cos(solarangle * DEG2RAD), 5.0f)));
}
__device__ void getcloudalbedo(float *result, float effectivealbedo,
float atmosphericalbedo, float t_earth, float t_sat)
{
float ca = getdifferentialalbedo(effectivealbedo, atmosphericalbedo,
t_earth, t_sat);
if (ca < 0.2f) { ca = 0.2f; }
float effectiveproportion = 2.24f * effectivealbedo;
if ( ca > effectiveproportion) { ca = effectiveproportion; }
result[i_dxyt] = ca;
}
__global__ void update_temporalcache(float *declination,
float *solarangle, float *solarelevation, float *excentricity,
float *gc, float *atmosphericalbedo, float *t_sat, float *t_earth,
float *cloudalbedo, float *lat, float *lon, float *decimalhour,
float *gamma, float *dem, float *linke, float *SAT_LON,
float *i0met, float *EXT_RAD, float *HEIGHT)
{
float bc, dc, satellitalzenithangle, atmosphericradiance,
satellitalelevation, satellital_opticalpath,
satellital_opticaldepth, solar_opticalpath,
solar_opticaldepth, effectivealbedo;
getdeclination(declination, gamma);
solarangle[i_dxyt] = getzenithangle(declination, lat, lon,
decimalhour, gamma);
solarelevation[i_dxyt] = getelevation(solarangle[i_dxyt]);
excentricity[i_dt] = getexcentricity(gamma);
bc = getbeamirradiance(EXT_RAD, excentricity, solarangle,
solarelevation[i_dxyt], linke, dem, HEIGHT);
dc = getdiffuseirradiance(EXT_RAD, excentricity,
solarelevation[i_dxyt], linke);
getglobalirradiance(gc, bc, dc);
satellitalzenithangle = getsatellitalzenithangle(lat, lon, SAT_LON);
atmosphericradiance = getatmosphericradiance(EXT_RAD, i0met,
dc,
satellitalzenithangle);
getalbedo(atmosphericalbedo, atmosphericradiance, i0met,
excentricity, satellitalzenithangle);
satellitalelevation = getelevation(satellitalzenithangle);
satellital_opticalpath = getopticalpath(
getcorrectedelevation(satellitalelevation), dem, HEIGHT);
satellital_opticaldepth = getopticaldepth(satellital_opticalpath);
gettransmitance(t_sat, linke, satellital_opticalpath,
satellital_opticaldepth, satellitalelevation);
solar_opticalpath = getopticalpath(
getcorrectedelevation(solarelevation[i_dxyt]), dem,
HEIGHT);
solar_opticaldepth = getopticaldepth(solar_opticalpath);
gettransmitance(t_earth, linke, solar_opticalpath, solar_opticaldepth,
solarelevation[i_dxyt]);
effectivealbedo = geteffectivealbedo(solarangle[i_dxyt]);
getcloudalbedo(cloudalbedo, effectivealbedo,
atmosphericalbedo[i_dxyt], t_earth[i_dxyt],
t_sat[i_dxyt]);
} | .text
.file "kernel.hip"
.globl _Z35__device_stub__update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_ # -- Begin function _Z35__device_stub__update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
.p2align 4, 0x90
.type _Z35__device_stub__update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_,@function
_Z35__device_stub__update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_: # @_Z35__device_stub__update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
.cfi_startproc
# %bb.0:
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 256(%rsp), %rax
movq %rax, 144(%rsp)
leaq 264(%rsp), %rax
movq %rax, 152(%rsp)
leaq 272(%rsp), %rax
movq %rax, 160(%rsp)
leaq 280(%rsp), %rax
movq %rax, 168(%rsp)
leaq 288(%rsp), %rax
movq %rax, 176(%rsp)
leaq 296(%rsp), %rax
movq %rax, 184(%rsp)
leaq 304(%rsp), %rax
movq %rax, 192(%rsp)
leaq 312(%rsp), %rax
movq %rax, 200(%rsp)
leaq 320(%rsp), %rax
movq %rax, 208(%rsp)
leaq 328(%rsp), %rax
movq %rax, 216(%rsp)
leaq 336(%rsp), %rax
movq %rax, 224(%rsp)
leaq 344(%rsp), %rax
movq %rax, 232(%rsp)
leaq 352(%rsp), %rax
movq %rax, 240(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $264, %rsp # imm = 0x108
.cfi_adjust_cfa_offset -264
retq
.Lfunc_end0:
.size _Z35__device_stub__update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_, .Lfunc_end0-_Z35__device_stub__update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_,@object # @_Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
.section .rodata,"a",@progbits
.globl _Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
.p2align 3, 0x0
_Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_:
.quad _Z35__device_stub__update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
.size _Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_"
.size .L__unnamed_1, 63
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d0909_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14getdeclinationPfS_
.type _Z14getdeclinationPfS_, @function
_Z14getdeclinationPfS_:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z14getdeclinationPfS_, .-_Z14getdeclinationPfS_
.globl _Z14gethourlyanglePfS_S_S_
.type _Z14gethourlyanglePfS_S_S_, @function
_Z14gethourlyanglePfS_S_S_:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z14gethourlyanglePfS_S_S_, .-_Z14gethourlyanglePfS_S_S_
.globl _Z14getzenithanglePfS_S_S_S_
.type _Z14getzenithanglePfS_S_S_S_, @function
_Z14getzenithanglePfS_S_S_S_:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z14getzenithanglePfS_S_S_S_, .-_Z14getzenithanglePfS_S_S_S_
.globl _Z12getelevationf
.type _Z12getelevationf, @function
_Z12getelevationf:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z12getelevationf, .-_Z12getelevationf
.globl _Z15getexcentricityPf
.type _Z15getexcentricityPf, @function
_Z15getexcentricityPf:
.LFB2061:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z15getexcentricityPf, .-_Z15getexcentricityPf
.globl _Z21getcorrectedelevationf
.type _Z21getcorrectedelevationf, @function
_Z21getcorrectedelevationf:
.LFB2062:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2062:
.size _Z21getcorrectedelevationf, .-_Z21getcorrectedelevationf
.globl _Z14getopticalpathfPfS_
.type _Z14getopticalpathfPfS_, @function
_Z14getopticalpathfPfS_:
.LFB2063:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2063:
.size _Z14getopticalpathfPfS_, .-_Z14getopticalpathfPfS_
.globl _Z15getopticaldepthf
.type _Z15getopticaldepthf, @function
_Z15getopticaldepthf:
.LFB2064:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2064:
.size _Z15getopticaldepthf, .-_Z15getopticaldepthf
.globl _Z19getbeamtransmissionPfff
.type _Z19getbeamtransmissionPfff, @function
_Z19getbeamtransmissionPfff:
.LFB2065:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2065:
.size _Z19getbeamtransmissionPfff, .-_Z19getbeamtransmissionPfff
.globl _Z23gethorizontalirradiancePfS_S_
.type _Z23gethorizontalirradiancePfS_S_, @function
_Z23gethorizontalirradiancePfS_S_:
.LFB2066:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2066:
.size _Z23gethorizontalirradiancePfS_S_, .-_Z23gethorizontalirradiancePfS_S_
.globl _Z17getbeamirradiancePfS_S_fS_S_S_
.type _Z17getbeamirradiancePfS_S_fS_S_S_, @function
_Z17getbeamirradiancePfS_S_fS_S_S_:
.LFB2067:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2067:
.size _Z17getbeamirradiancePfS_S_fS_S_S_, .-_Z17getbeamirradiancePfS_S_fS_S_S_
.globl _Z28getzenithdiffusetransmitancePf
.type _Z28getzenithdiffusetransmitancePf, @function
_Z28getzenithdiffusetransmitancePf:
.LFB2068:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2068:
.size _Z28getzenithdiffusetransmitancePf, .-_Z28getzenithdiffusetransmitancePf
.globl _Z20getangularcorrectionfPf
.type _Z20getangularcorrectionfPf, @function
_Z20getangularcorrectionfPf:
.LFB2069:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2069:
.size _Z20getangularcorrectionfPf, .-_Z20getangularcorrectionfPf
.globl _Z22getdiffusetransmitancePff
.type _Z22getdiffusetransmitancePff, @function
_Z22getdiffusetransmitancePff:
.LFB2070:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2070:
.size _Z22getdiffusetransmitancePff, .-_Z22getdiffusetransmitancePff
.globl _Z15gettransmitancePfS_fff
.type _Z15gettransmitancePfS_fff, @function
_Z15gettransmitancePfS_fff:
.LFB2071:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2071:
.size _Z15gettransmitancePfS_fff, .-_Z15gettransmitancePfS_fff
.globl _Z20getdiffuseirradiancePfS_fS_
.type _Z20getdiffuseirradiancePfS_fS_, @function
_Z20getdiffuseirradiancePfS_fS_:
.LFB2072:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2072:
.size _Z20getdiffuseirradiancePfS_fS_, .-_Z20getdiffuseirradiancePfS_fS_
.globl _Z19getglobalirradiancePfff
.type _Z19getglobalirradiancePfff, @function
_Z19getglobalirradiancePfff:
.LFB2073:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2073:
.size _Z19getglobalirradiancePfff, .-_Z19getglobalirradiancePfff
.globl _Z24getsatellitalzenithanglePfS_S_
.type _Z24getsatellitalzenithanglePfS_S_, @function
_Z24getsatellitalzenithanglePfS_S_:
.LFB2074:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2074:
.size _Z24getsatellitalzenithanglePfS_S_, .-_Z24getsatellitalzenithanglePfS_S_
.globl _Z22getatmosphericradiancePfS_ff
.type _Z22getatmosphericradiancePfS_ff, @function
_Z22getatmosphericradiancePfS_ff:
.LFB2075:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2075:
.size _Z22getatmosphericradiancePfS_ff, .-_Z22getatmosphericradiancePfS_ff
.globl _Z21getdifferentialalbedoffff
.type _Z21getdifferentialalbedoffff, @function
_Z21getdifferentialalbedoffff:
.LFB2076:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2076:
.size _Z21getdifferentialalbedoffff, .-_Z21getdifferentialalbedoffff
.globl _Z9getalbedoPffS_S_f
.type _Z9getalbedoPffS_S_f, @function
_Z9getalbedoPffS_S_f:
.LFB2077:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2077:
.size _Z9getalbedoPffS_S_f, .-_Z9getalbedoPffS_S_f
.globl _Z18geteffectivealbedof
.type _Z18geteffectivealbedof, @function
_Z18geteffectivealbedof:
.LFB2078:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2078:
.size _Z18geteffectivealbedof, .-_Z18geteffectivealbedof
.globl _Z14getcloudalbedoPfffff
.type _Z14getcloudalbedoPfffff, @function
_Z14getcloudalbedoPfffff:
.LFB2079:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2079:
.size _Z14getcloudalbedoPfffff, .-_Z14getcloudalbedoPfffff
.globl _Z76__device_stub__Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_PfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
.type _Z76__device_stub__Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_PfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_, @function
_Z76__device_stub__Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_PfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_:
.LFB2104:
.cfi_startproc
endbr64
subq $392, %rsp
.cfi_def_cfa_offset 400
movq %rdi, 152(%rsp)
movq %rsi, 144(%rsp)
movq %rdx, 136(%rsp)
movq %rcx, 128(%rsp)
movq %r8, 120(%rsp)
movq %r9, 112(%rsp)
movq 400(%rsp), %rax
movq %rax, 104(%rsp)
movq 408(%rsp), %rax
movq %rax, 96(%rsp)
movq 416(%rsp), %rax
movq %rax, 88(%rsp)
movq 424(%rsp), %rax
movq %rax, 80(%rsp)
movq 432(%rsp), %rax
movq %rax, 72(%rsp)
movq 440(%rsp), %rax
movq %rax, 64(%rsp)
movq 448(%rsp), %rax
movq %rax, 56(%rsp)
movq 456(%rsp), %rax
movq %rax, 48(%rsp)
movq 464(%rsp), %rax
movq %rax, 40(%rsp)
movq 472(%rsp), %rax
movq %rax, 32(%rsp)
movq 480(%rsp), %rax
movq %rax, 24(%rsp)
movq 488(%rsp), %rax
movq %rax, 16(%rsp)
movq 496(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 376(%rsp)
xorl %eax, %eax
leaq 152(%rsp), %rax
movq %rax, 224(%rsp)
leaq 144(%rsp), %rax
movq %rax, 232(%rsp)
leaq 136(%rsp), %rax
movq %rax, 240(%rsp)
leaq 128(%rsp), %rax
movq %rax, 248(%rsp)
leaq 120(%rsp), %rax
movq %rax, 256(%rsp)
leaq 112(%rsp), %rax
movq %rax, 264(%rsp)
leaq 104(%rsp), %rax
movq %rax, 272(%rsp)
leaq 96(%rsp), %rax
movq %rax, 280(%rsp)
leaq 88(%rsp), %rax
movq %rax, 288(%rsp)
leaq 80(%rsp), %rax
movq %rax, 296(%rsp)
leaq 72(%rsp), %rax
movq %rax, 304(%rsp)
leaq 64(%rsp), %rax
movq %rax, 312(%rsp)
leaq 56(%rsp), %rax
movq %rax, 320(%rsp)
leaq 48(%rsp), %rax
movq %rax, 328(%rsp)
leaq 40(%rsp), %rax
movq %rax, 336(%rsp)
leaq 32(%rsp), %rax
movq %rax, 344(%rsp)
leaq 24(%rsp), %rax
movq %rax, 352(%rsp)
leaq 16(%rsp), %rax
movq %rax, 360(%rsp)
leaq 8(%rsp), %rax
movq %rax, 368(%rsp)
movl $1, 176(%rsp)
movl $1, 180(%rsp)
movl $1, 184(%rsp)
movl $1, 188(%rsp)
movl $1, 192(%rsp)
movl $1, 196(%rsp)
leaq 168(%rsp), %rcx
leaq 160(%rsp), %rdx
leaq 188(%rsp), %rsi
leaq 176(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L53
.L49:
movq 376(%rsp), %rax
subq %fs:40, %rax
jne .L54
addq $392, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
pushq 168(%rsp)
.cfi_def_cfa_offset 408
pushq 168(%rsp)
.cfi_def_cfa_offset 416
leaq 240(%rsp), %r9
movq 204(%rsp), %rcx
movl 212(%rsp), %r8d
movq 192(%rsp), %rsi
movl 200(%rsp), %edx
leaq _Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 400
jmp .L49
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2104:
.size _Z76__device_stub__Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_PfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_, .-_Z76__device_stub__Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_PfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
.globl _Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
.type _Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_, @function
_Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_:
.LFB2105:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 120(%rsp)
.cfi_def_cfa_offset 32
pushq 120(%rsp)
.cfi_def_cfa_offset 40
pushq 120(%rsp)
.cfi_def_cfa_offset 48
pushq 120(%rsp)
.cfi_def_cfa_offset 56
pushq 120(%rsp)
.cfi_def_cfa_offset 64
pushq 120(%rsp)
.cfi_def_cfa_offset 72
pushq 120(%rsp)
.cfi_def_cfa_offset 80
pushq 120(%rsp)
.cfi_def_cfa_offset 88
pushq 120(%rsp)
.cfi_def_cfa_offset 96
pushq 120(%rsp)
.cfi_def_cfa_offset 104
pushq 120(%rsp)
.cfi_def_cfa_offset 112
pushq 120(%rsp)
.cfi_def_cfa_offset 120
pushq 120(%rsp)
.cfi_def_cfa_offset 128
call _Z76__device_stub__Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_PfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
addq $120, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2105:
.size _Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_, .-_Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2107:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2107:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z35__device_stub__update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_ # -- Begin function _Z35__device_stub__update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
.p2align 4, 0x90
.type _Z35__device_stub__update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_,@function
_Z35__device_stub__update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_: # @_Z35__device_stub__update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
.cfi_startproc
# %bb.0:
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 256(%rsp), %rax
movq %rax, 144(%rsp)
leaq 264(%rsp), %rax
movq %rax, 152(%rsp)
leaq 272(%rsp), %rax
movq %rax, 160(%rsp)
leaq 280(%rsp), %rax
movq %rax, 168(%rsp)
leaq 288(%rsp), %rax
movq %rax, 176(%rsp)
leaq 296(%rsp), %rax
movq %rax, 184(%rsp)
leaq 304(%rsp), %rax
movq %rax, 192(%rsp)
leaq 312(%rsp), %rax
movq %rax, 200(%rsp)
leaq 320(%rsp), %rax
movq %rax, 208(%rsp)
leaq 328(%rsp), %rax
movq %rax, 216(%rsp)
leaq 336(%rsp), %rax
movq %rax, 224(%rsp)
leaq 344(%rsp), %rax
movq %rax, 232(%rsp)
leaq 352(%rsp), %rax
movq %rax, 240(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $264, %rsp # imm = 0x108
.cfi_adjust_cfa_offset -264
retq
.Lfunc_end0:
.size _Z35__device_stub__update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_, .Lfunc_end0-_Z35__device_stub__update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_,@object # @_Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
.section .rodata,"a",@progbits
.globl _Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
.p2align 3, 0x0
_Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_:
.quad _Z35__device_stub__update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
.size _Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_"
.size .L__unnamed_1, 63
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20update_temporalcachePfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
Demo: CUDA program to compute the squares of the first N natural numners
*/
#include <stdio.h>
typedef float data_t; // makes it easy to change type later
__global__ void square(data_t *d_in, data_t *d_out); // kernel function
// note the use of __global__
void printArray( data_t a[], int num_elements );
int main(){
const int num_elements = 64;
int block_size = sizeof(data_t) * num_elements;
// set-up sample data to beb procesed
data_t h_in[num_elements];
for ( int idx=0; idx < num_elements; idx++ )
h_in[idx] = idx;
// define device data pointers
data_t *d_in = NULL;
data_t *d_out = NULL;
// allocate device memory
cudaMalloc( (void **) &d_in, block_size );
cudaMalloc( (void **) &d_out, block_size );
// transfer data to device memory
cudaMemcpy( d_in, h_in, block_size, cudaMemcpyHostToDevice );
// launch kernel
const int threads_per_block = num_elements;
square <<< 1, threads_per_block >>> (d_out, d_in);
// retrieve data from device memory
data_t h_out[num_elements];
cudaMemcpy( h_out, d_out, block_size, cudaMemcpyDeviceToHost );
// free device memory
cudaFree( d_in );
cudaFree( d_out );
// display results
printArray( h_out, num_elements );
}
// kernel definition
__global__ void square(data_t *d_out, data_t *d_in){
int t_idx = threadIdx.x; // get thread id
d_out[t_idx] = d_in[t_idx] * d_in[t_idx];
}
void printArray( data_t a[], int num_elements ){
for( int idx = 0; idx < num_elements; idx++ )
printf("%5.1f%c", a[idx], ((idx % 4) != 3) ? '\t' : '\n');
printf("\n");
} | code for sm_80
Function : _Z6squarePfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x001fcc00078e0205 */
/*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0205 */
/*0070*/ FMUL R7, R2, R2 ; /* 0x0000000202077220 */
/* 0x004fca0000400000 */
/*0080*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
Demo: CUDA program to compute the squares of the first N natural numners
*/
#include <stdio.h>
typedef float data_t; // makes it easy to change type later
__global__ void square(data_t *d_in, data_t *d_out); // kernel function
// note the use of __global__
void printArray( data_t a[], int num_elements );
int main(){
const int num_elements = 64;
int block_size = sizeof(data_t) * num_elements;
// set-up sample data to beb procesed
data_t h_in[num_elements];
for ( int idx=0; idx < num_elements; idx++ )
h_in[idx] = idx;
// define device data pointers
data_t *d_in = NULL;
data_t *d_out = NULL;
// allocate device memory
cudaMalloc( (void **) &d_in, block_size );
cudaMalloc( (void **) &d_out, block_size );
// transfer data to device memory
cudaMemcpy( d_in, h_in, block_size, cudaMemcpyHostToDevice );
// launch kernel
const int threads_per_block = num_elements;
square <<< 1, threads_per_block >>> (d_out, d_in);
// retrieve data from device memory
data_t h_out[num_elements];
cudaMemcpy( h_out, d_out, block_size, cudaMemcpyDeviceToHost );
// free device memory
cudaFree( d_in );
cudaFree( d_out );
// display results
printArray( h_out, num_elements );
}
// kernel definition
__global__ void square(data_t *d_out, data_t *d_in){
int t_idx = threadIdx.x; // get thread id
d_out[t_idx] = d_in[t_idx] * d_in[t_idx];
}
void printArray( data_t a[], int num_elements ){
for( int idx = 0; idx < num_elements; idx++ )
printf("%5.1f%c", a[idx], ((idx % 4) != 3) ? '\t' : '\n');
printf("\n");
} | .file "tmpxft_00158ddf_00000000-6_square.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%5.1f%c"
.LC1:
.string "\n"
.text
.globl _Z10printArrayPfi
.type _Z10printArrayPfi, @function
_Z10printArrayPfi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
testl %esi, %esi
jle .L4
movq %rdi, %r12
movslq %esi, %rbp
movl $0, %ebx
leaq .LC0(%rip), %r13
.L6:
movl %ebx, %edx
sarl $31, %edx
shrl $30, %edx
leal (%rdx,%rbx), %eax
andl $3, %eax
subl %edx, %eax
cmpl $3, %eax
sete %dl
movzbl %dl, %edx
addl $9, %edx
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbp, %rbx
jne .L6
.L4:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z10printArrayPfi, .-_Z10printArrayPfi
.globl _Z27__device_stub__Z6squarePfS_PfS_
.type _Z27__device_stub__Z6squarePfS_PfS_, @function
_Z27__device_stub__Z6squarePfS_PfS_:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6squarePfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z27__device_stub__Z6squarePfS_PfS_, .-_Z27__device_stub__Z6squarePfS_PfS_
.globl _Z6squarePfS_
.type _Z6squarePfS_, @function
_Z6squarePfS_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6squarePfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z6squarePfS_, .-_Z6squarePfS_
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $576, %rsp
.cfi_def_cfa_offset 592
movq %fs:40, %rax
movq %rax, 568(%rsp)
xorl %eax, %eax
.L19:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 48(%rsp,%rax,4)
addq $1, %rax
cmpq $64, %rax
jne .L19
movq $0, 8(%rsp)
movq $0, 16(%rsp)
leaq 8(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $256, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $64, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
leaq 304(%rsp), %rbx
movl $2, %ecx
movl $256, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movl $64, %esi
movq %rbx, %rdi
call _Z10printArrayPfi
movq 568(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $576, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z27__device_stub__Z6squarePfS_PfS_
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z6squarePfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6squarePfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
Demo: CUDA program to compute the squares of the first N natural numners
*/
#include <stdio.h>
typedef float data_t; // makes it easy to change type later
__global__ void square(data_t *d_in, data_t *d_out); // kernel function
// note the use of __global__
void printArray( data_t a[], int num_elements );
int main(){
const int num_elements = 64;
int block_size = sizeof(data_t) * num_elements;
// set-up sample data to beb procesed
data_t h_in[num_elements];
for ( int idx=0; idx < num_elements; idx++ )
h_in[idx] = idx;
// define device data pointers
data_t *d_in = NULL;
data_t *d_out = NULL;
// allocate device memory
cudaMalloc( (void **) &d_in, block_size );
cudaMalloc( (void **) &d_out, block_size );
// transfer data to device memory
cudaMemcpy( d_in, h_in, block_size, cudaMemcpyHostToDevice );
// launch kernel
const int threads_per_block = num_elements;
square <<< 1, threads_per_block >>> (d_out, d_in);
// retrieve data from device memory
data_t h_out[num_elements];
cudaMemcpy( h_out, d_out, block_size, cudaMemcpyDeviceToHost );
// free device memory
cudaFree( d_in );
cudaFree( d_out );
// display results
printArray( h_out, num_elements );
}
// kernel definition
__global__ void square(data_t *d_out, data_t *d_in){
int t_idx = threadIdx.x; // get thread id
d_out[t_idx] = d_in[t_idx] * d_in[t_idx];
}
void printArray( data_t a[], int num_elements ){
for( int idx = 0; idx < num_elements; idx++ )
printf("%5.1f%c", a[idx], ((idx % 4) != 3) ? '\t' : '\n');
printf("\n");
} | /*
Demo: CUDA program to compute the squares of the first N natural numners
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
typedef float data_t; // makes it easy to change type later
__global__ void square(data_t *d_in, data_t *d_out); // kernel function
// note the use of __global__
void printArray( data_t a[], int num_elements );
int main(){
const int num_elements = 64;
int block_size = sizeof(data_t) * num_elements;
// set-up sample data to beb procesed
data_t h_in[num_elements];
for ( int idx=0; idx < num_elements; idx++ )
h_in[idx] = idx;
// define device data pointers
data_t *d_in = NULL;
data_t *d_out = NULL;
// allocate device memory
hipMalloc( (void **) &d_in, block_size );
hipMalloc( (void **) &d_out, block_size );
// transfer data to device memory
hipMemcpy( d_in, h_in, block_size, hipMemcpyHostToDevice );
// launch kernel
const int threads_per_block = num_elements;
square <<< 1, threads_per_block >>> (d_out, d_in);
// retrieve data from device memory
data_t h_out[num_elements];
hipMemcpy( h_out, d_out, block_size, hipMemcpyDeviceToHost );
// free device memory
hipFree( d_in );
hipFree( d_out );
// display results
printArray( h_out, num_elements );
}
// kernel definition
__global__ void square(data_t *d_out, data_t *d_in){
int t_idx = threadIdx.x; // get thread id
d_out[t_idx] = d_in[t_idx] * d_in[t_idx];
}
void printArray( data_t a[], int num_elements ){
for( int idx = 0; idx < num_elements; idx++ )
printf("%5.1f%c", a[idx], ((idx % 4) != 3) ? '\t' : '\n');
printf("\n");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
Demo: CUDA program to compute the squares of the first N natural numners
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
typedef float data_t; // makes it easy to change type later
__global__ void square(data_t *d_in, data_t *d_out); // kernel function
// note the use of __global__
void printArray( data_t a[], int num_elements );
int main(){
const int num_elements = 64;
int block_size = sizeof(data_t) * num_elements;
// set-up sample data to beb procesed
data_t h_in[num_elements];
for ( int idx=0; idx < num_elements; idx++ )
h_in[idx] = idx;
// define device data pointers
data_t *d_in = NULL;
data_t *d_out = NULL;
// allocate device memory
hipMalloc( (void **) &d_in, block_size );
hipMalloc( (void **) &d_out, block_size );
// transfer data to device memory
hipMemcpy( d_in, h_in, block_size, hipMemcpyHostToDevice );
// launch kernel
const int threads_per_block = num_elements;
square <<< 1, threads_per_block >>> (d_out, d_in);
// retrieve data from device memory
data_t h_out[num_elements];
hipMemcpy( h_out, d_out, block_size, hipMemcpyDeviceToHost );
// free device memory
hipFree( d_in );
hipFree( d_out );
// display results
printArray( h_out, num_elements );
}
// kernel definition
__global__ void square(data_t *d_out, data_t *d_in){
int t_idx = threadIdx.x; // get thread id
d_out[t_idx] = d_in[t_idx] * d_in[t_idx];
}
void printArray( data_t a[], int num_elements ){
for( int idx = 0; idx < num_elements; idx++ )
printf("%5.1f%c", a[idx], ((idx % 4) != 3) ? '\t' : '\n');
printf("\n");
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6squarePfS_
.globl _Z6squarePfS_
.p2align 8
.type _Z6squarePfS_,@function
_Z6squarePfS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[2:3]
s_waitcnt vmcnt(0)
v_mul_f32_e32 v1, v1, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6squarePfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6squarePfS_, .Lfunc_end0-_Z6squarePfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6squarePfS_
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z6squarePfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
Demo: CUDA program to compute the squares of the first N natural numners
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
typedef float data_t; // makes it easy to change type later
__global__ void square(data_t *d_in, data_t *d_out); // kernel function
// note the use of __global__
void printArray( data_t a[], int num_elements );
int main(){
const int num_elements = 64;
int block_size = sizeof(data_t) * num_elements;
// set-up sample data to beb procesed
data_t h_in[num_elements];
for ( int idx=0; idx < num_elements; idx++ )
h_in[idx] = idx;
// define device data pointers
data_t *d_in = NULL;
data_t *d_out = NULL;
// allocate device memory
hipMalloc( (void **) &d_in, block_size );
hipMalloc( (void **) &d_out, block_size );
// transfer data to device memory
hipMemcpy( d_in, h_in, block_size, hipMemcpyHostToDevice );
// launch kernel
const int threads_per_block = num_elements;
square <<< 1, threads_per_block >>> (d_out, d_in);
// retrieve data from device memory
data_t h_out[num_elements];
hipMemcpy( h_out, d_out, block_size, hipMemcpyDeviceToHost );
// free device memory
hipFree( d_in );
hipFree( d_out );
// display results
printArray( h_out, num_elements );
}
// kernel definition
__global__ void square(data_t *d_out, data_t *d_in){
int t_idx = threadIdx.x; // get thread id
d_out[t_idx] = d_in[t_idx] * d_in[t_idx];
}
void printArray( data_t a[], int num_elements ){
for( int idx = 0; idx < num_elements; idx++ )
printf("%5.1f%c", a[idx], ((idx % 4) != 3) ? '\t' : '\n');
printf("\n");
} | .text
.file "square.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $592, %rsp # imm = 0x250
.cfi_def_cfa_offset 608
.cfi_offset %rbx, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, 336(%rsp,%rax,4)
incq %rax
cmpq $64, %rax
jne .LBB0_1
# %bb.2:
movq $0, 8(%rsp)
movq $0, (%rsp)
leaq 8(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movq %rsp, %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movq 8(%rsp), %rdi
leaq 336(%rsp), %rsi
movl $256, %edx # imm = 0x100
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 63(%rdi), %rdx
xorl %ebx, %ebx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_4
# %bb.3:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6squarePfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_4:
movq (%rsp), %rsi
leaq 80(%rsp), %rdi
movl $256, %edx # imm = 0x100
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
.p2align 4, 0x90
.LBB0_5: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss 80(%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl %ebx, %eax
notl %eax
andl $3, %eax
cmpl $1, %eax
movl $0, %esi
adcl $9, %esi
movl $.L.str, %edi
movb $1, %al
callq printf
incq %rbx
cmpq $64, %rbx
jne .LBB0_5
# %bb.6: # %_Z10printArrayPfi.exit
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $592, %rsp # imm = 0x250
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z21__device_stub__squarePfS_ # -- Begin function _Z21__device_stub__squarePfS_
.p2align 4, 0x90
.type _Z21__device_stub__squarePfS_,@function
_Z21__device_stub__squarePfS_: # @_Z21__device_stub__squarePfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6squarePfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z21__device_stub__squarePfS_, .Lfunc_end1-_Z21__device_stub__squarePfS_
.cfi_endproc
# -- End function
.globl _Z10printArrayPfi # -- Begin function _Z10printArrayPfi
.p2align 4, 0x90
.type _Z10printArrayPfi,@function
_Z10printArrayPfi: # @_Z10printArrayPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl %r15d, %eax
notl %eax
andl $3, %eax
cmpl $1, %eax
movl $0, %esi
adcl $9, %esi
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB2_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB2_4: # %._crit_edge
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end2:
.size _Z10printArrayPfi, .Lfunc_end2-_Z10printArrayPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6squarePfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6squarePfS_,@object # @_Z6squarePfS_
.section .rodata,"a",@progbits
.globl _Z6squarePfS_
.p2align 3, 0x0
_Z6squarePfS_:
.quad _Z21__device_stub__squarePfS_
.size _Z6squarePfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%5.1f%c"
.size .L.str, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6squarePfS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__squarePfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6squarePfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6squarePfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x001fcc00078e0205 */
/*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0205 */
/*0070*/ FMUL R7, R2, R2 ; /* 0x0000000202077220 */
/* 0x004fca0000400000 */
/*0080*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6squarePfS_
.globl _Z6squarePfS_
.p2align 8
.type _Z6squarePfS_,@function
_Z6squarePfS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[2:3]
s_waitcnt vmcnt(0)
v_mul_f32_e32 v1, v1, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6squarePfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6squarePfS_, .Lfunc_end0-_Z6squarePfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6squarePfS_
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z6squarePfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00158ddf_00000000-6_square.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%5.1f%c"
.LC1:
.string "\n"
.text
.globl _Z10printArrayPfi
.type _Z10printArrayPfi, @function
_Z10printArrayPfi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
testl %esi, %esi
jle .L4
movq %rdi, %r12
movslq %esi, %rbp
movl $0, %ebx
leaq .LC0(%rip), %r13
.L6:
movl %ebx, %edx
sarl $31, %edx
shrl $30, %edx
leal (%rdx,%rbx), %eax
andl $3, %eax
subl %edx, %eax
cmpl $3, %eax
sete %dl
movzbl %dl, %edx
addl $9, %edx
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbp, %rbx
jne .L6
.L4:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z10printArrayPfi, .-_Z10printArrayPfi
.globl _Z27__device_stub__Z6squarePfS_PfS_
.type _Z27__device_stub__Z6squarePfS_PfS_, @function
_Z27__device_stub__Z6squarePfS_PfS_:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6squarePfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z27__device_stub__Z6squarePfS_PfS_, .-_Z27__device_stub__Z6squarePfS_PfS_
.globl _Z6squarePfS_
.type _Z6squarePfS_, @function
_Z6squarePfS_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6squarePfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z6squarePfS_, .-_Z6squarePfS_
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $576, %rsp
.cfi_def_cfa_offset 592
movq %fs:40, %rax
movq %rax, 568(%rsp)
xorl %eax, %eax
.L19:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 48(%rsp,%rax,4)
addq $1, %rax
cmpq $64, %rax
jne .L19
movq $0, 8(%rsp)
movq $0, 16(%rsp)
leaq 8(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $256, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $64, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
leaq 304(%rsp), %rbx
movl $2, %ecx
movl $256, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movl $64, %esi
movq %rbx, %rdi
call _Z10printArrayPfi
movq 568(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $576, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z27__device_stub__Z6squarePfS_PfS_
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z6squarePfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6squarePfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "square.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $592, %rsp # imm = 0x250
.cfi_def_cfa_offset 608
.cfi_offset %rbx, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, 336(%rsp,%rax,4)
incq %rax
cmpq $64, %rax
jne .LBB0_1
# %bb.2:
movq $0, 8(%rsp)
movq $0, (%rsp)
leaq 8(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movq %rsp, %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movq 8(%rsp), %rdi
leaq 336(%rsp), %rsi
movl $256, %edx # imm = 0x100
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 63(%rdi), %rdx
xorl %ebx, %ebx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_4
# %bb.3:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6squarePfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_4:
movq (%rsp), %rsi
leaq 80(%rsp), %rdi
movl $256, %edx # imm = 0x100
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
.p2align 4, 0x90
.LBB0_5: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss 80(%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl %ebx, %eax
notl %eax
andl $3, %eax
cmpl $1, %eax
movl $0, %esi
adcl $9, %esi
movl $.L.str, %edi
movb $1, %al
callq printf
incq %rbx
cmpq $64, %rbx
jne .LBB0_5
# %bb.6: # %_Z10printArrayPfi.exit
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $592, %rsp # imm = 0x250
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z21__device_stub__squarePfS_ # -- Begin function _Z21__device_stub__squarePfS_
.p2align 4, 0x90
.type _Z21__device_stub__squarePfS_,@function
_Z21__device_stub__squarePfS_: # @_Z21__device_stub__squarePfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6squarePfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z21__device_stub__squarePfS_, .Lfunc_end1-_Z21__device_stub__squarePfS_
.cfi_endproc
# -- End function
.globl _Z10printArrayPfi # -- Begin function _Z10printArrayPfi
.p2align 4, 0x90
.type _Z10printArrayPfi,@function
_Z10printArrayPfi: # @_Z10printArrayPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl %r15d, %eax
notl %eax
andl $3, %eax
cmpl $1, %eax
movl $0, %esi
adcl $9, %esi
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB2_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB2_4: # %._crit_edge
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end2:
.size _Z10printArrayPfi, .Lfunc_end2-_Z10printArrayPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6squarePfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6squarePfS_,@object # @_Z6squarePfS_
.section .rodata,"a",@progbits
.globl _Z6squarePfS_
.p2align 3, 0x0
_Z6squarePfS_:
.quad _Z21__device_stub__squarePfS_
.size _Z6squarePfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%5.1f%c"
.size .L.str, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6squarePfS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__squarePfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6squarePfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdio.h>
#include <math.h>
#include <time.h>
int* m_malloc(int n) {
return (int* )malloc(sizeof (int) * n * n);
}
void m_fill_random(int * mat, int n) {
//srand((unsigned int)time(NULL));
// int seed = rand();
// use same seed to draw the same image again on every test
srand(rand());
int i;
for (i = 0; i < n * n; i++) {
mat[i] = rand() % 10;
}
}
void mm_cpu(int * A, int * B, int * C, int n) {
int i, j, k;
for (i = 0; i < n; i++)
for (j = 0; j < n; j++) {
C[i * n + j] = 0;
for (k = 0; k < n; k++)
C[i * n + j] += A[i * n + k] * B[k * n + j];
}
}
void print_mat(int * A, int * B, int * C, int n) {
int i, j;
for (i = 0; i < n; i++) {
for (j = 0; j < n; j++)
printf("%d ", A[i * n + j]);
printf("\n");
}
printf("\n\n");
for (i = 0; i < n; i++) {
for (j = 0; j < n; j++)
printf("%d ", B[i * n + j]);
printf("\n");
}
printf("\n \n");
for (i = 0; i < n; i++) {
for (j = 0; j < n; j++)
printf("%d ", C[i * n + j]);
printf("\n");
}
}
// Matrices are stored in row-major order:
// M(row, col) = *(M.elements + row * M.width + col)
typedef struct {
int width;
int height;
int stride; // necessario para o metodo com shared memory
int* elements;
} Matrix;
// Thread block size
#define BLOCK_SIZE 16
// GET e SET elementos do device
__device__ float GetElement(const Matrix A, int row, int col) { // Get a matrix element
return A.elements[row * A.stride + col];
}
__device__ void SetElement(Matrix A, int row, int col, float value) { // Set a matrix element
A.elements[row * A.stride + col] = value;
}
// Get the BLOCK_SIZExBLOCK_SIZE sub-matrix Asub of A that is located col sub-matrices to the right and row
__device__ Matrix GetSubMatrix(Matrix A, int row, int col) { // sub-matrices down from the upper-left corner of A
Matrix Asub;
Asub.width = BLOCK_SIZE;
Asub.height = BLOCK_SIZE;
Asub.stride = A.stride;
Asub.elements = &A.elements[A.stride * BLOCK_SIZE * row + BLOCK_SIZE * col];
return Asub;
}
// Forward declaration of the matrix multiplication kernel
__global__ void MatMulKernel_g(const Matrix, const Matrix, Matrix);
__global__ void MatMulKernel_s(const Matrix, const Matrix, Matrix);
void MatMul_g(const Matrix A, const Matrix B, Matrix C, int device);
void MatMul_s(const Matrix A, const Matrix B, Matrix C, int device);
int main() {
clock_t t;
float time;
int co = 2;
int size[7] = {256, 512, 1024, 2048, 4096, 8192, 16384}; // more sizes
int n = size[co];
printf("======= Matriz %dx%d =======\n", n, n);
int* A = m_malloc(n);
int* B = m_malloc(n);
int* C = m_malloc(n);
Matrix mA;
mA.width = n;
mA.height = n;
mA.elements = A;
Matrix mB;
mB.width = n;
mB.height = n;
mB.elements = B;
Matrix mC;
mC.width = n;
mC.height = n;
mC.elements = C;
m_fill_random(A, n);
m_fill_random(B, n);
time = 0;
t = clock();
mm_cpu(A, B, C, n);
time = (float)(clock() - t);
time = time / CLOCKS_PER_SEC;
printf("CPU = %10.1fms \n", time * 1000);
int count = 1;
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, count);
cudaSetDevice(count);
t = clock();
MatMul_g(mA, mB, mC, count);
time = (float)(clock() - t);
time = time / CLOCKS_PER_SEC;
printf("GPU_GLOBAL - %s = %10.1fms \n", prop.name, time * 1000);
t = clock();
MatMul_s(mA, mB, mC, count);
time = (float)(clock() - t);
time = time / CLOCKS_PER_SEC;
printf("GPU_SHARED - %s = %10.1fms \n", prop.name, time * 1000);
free(A);
free(B);
free(C);
return 0;
}
// Matrix multiplication - Host code
// Matrix dimensions are assumed to be multiples of BLOCK_SIZE
void MatMul_g(const Matrix A, const Matrix B, Matrix C, int device) {
// Load A and B to device memory
Matrix d_A;
d_A.width = A.width;
d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
cudaSetDevice(device);
cudaMalloc(&d_A.elements, size);
cudaMemcpy(d_A.elements, A.elements, size, cudaMemcpyHostToDevice);
Matrix d_B;
d_B.width = B.width;
d_B.height = B.height;
size = B.width * B.height * sizeof(float);
cudaMalloc(&d_B.elements, size);
cudaMemcpy(d_B.elements, B.elements, size, cudaMemcpyHostToDevice);
// Allocate C in device memory
Matrix d_C;
d_C.width = C.width;
d_C.height = C.height;
size = C.width * C.height * sizeof(float);
cudaMalloc(&d_C.elements, size);
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B.width / dimBlock.x, A.height / dimBlock.y);
MatMulKernel_g <<< dimGrid, dimBlock>>>(d_A, d_B, d_C);
// Read C from device memory
cudaMemcpy(C.elements, d_C.elements, size, cudaMemcpyDeviceToHost);
// Free device memory
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
}
// PRATICAMENTE IGUAL AO ANTERIOR, COM A DIFERENCA
// QUE O KERNEL INVOCADO AQUI EH O DE SHARED AO INVES DO GLOBAL
void MatMul_s(const Matrix A, const Matrix B, Matrix C, int device) {
// Load A and B to device memory
Matrix d_A;
d_A.width = A.width;
d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
cudaSetDevice(device);
cudaMalloc(&d_A.elements, size);
cudaMemcpy(d_A.elements, A.elements, size, cudaMemcpyHostToDevice);
Matrix d_B;
d_B.width = B.width;
d_B.height = B.height;
size = B.width * B.height * sizeof(float);
cudaMalloc(&d_B.elements, size);
cudaMemcpy(d_B.elements, B.elements, size, cudaMemcpyHostToDevice);
// Allocate C in device memory
Matrix d_C;
d_C.width = C.width;
d_C.height = C.height;
size = C.width * C.height * sizeof(float);
cudaMalloc(&d_C.elements, size);
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B.width / dimBlock.x, A.height / dimBlock.y);
MatMulKernel_s <<< dimGrid, dimBlock>>>(d_A, d_B, d_C);
// Read C from device memory
cudaMemcpy(C.elements, d_C.elements, size, cudaMemcpyDeviceToHost);
// Free device memory
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
}
// MULTIPLICACAO DE MATRIZES UTILIZANDO MEMORIA GLOBAL
__global__ void MatMulKernel_g(Matrix A, Matrix B, Matrix C) {
// Each thread computes one element of C by accumulating results into Cvalue
float Cvalue = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
for (int e = 0; e < A.width; ++e)
Cvalue += A.elements[row * A.width + e] * B.elements[e * B.width + col];
C.elements[row * C.width + col] = Cvalue;
}
// MULTIPLICACAO DE MATRIZES UTILIZANDO MEMORIA COMPARTILHADA
__global__ void MatMulKernel_s(Matrix A, Matrix B, Matrix C)
{
// Block row and column
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
// Each thread block computes one sub-matrix Csub of C
Matrix Csub = GetSubMatrix(C, blockRow, blockCol);
// Each thread computes one element of Csub
// by accumulating results into Cvalue
float Cvalue = 0;
// Thread row and column within Csub
int row = threadIdx.y;
int col = threadIdx.x;
// Loop over all the sub-matrices of A and B that are
// required to compute Csub
// Multiply each pair of sub-matrices together
// and accumulate the results
for (int m = 0; m < (A.width / BLOCK_SIZE); ++m) {
// Get sub-matrix Asub of A
Matrix Asub = GetSubMatrix(A, blockRow, m);
// Get sub-matrix Bsub of B
Matrix Bsub = GetSubMatrix(B, m, blockCol);
// Shared memory used to store Asub and Bsub respectively
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
// Load Asub and Bsub from device memory to shared memory
// Each thread loads one element of each sub-matrix
As[row][col] = GetElement(Asub, row, col);
Bs[row][col] = GetElement(Bsub, row, col);
// Synchronize to make sure the sub-matrices are loaded
// before starting the computation
__syncthreads();
// Multiply Asub and Bsub together
for (int e = 0; e < BLOCK_SIZE; ++e)
Cvalue += As[row][e] * Bs[e][col];
// Synchronize to make sure that the preceding
// computation is done before loading two new
// sub-matrices of A and B in the next iteration
__syncthreads();
}
// Write Csub to device memory Each thread writes one element
SetElement(Csub, row, col, Cvalue);
} | .file "tmpxft_00101858_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2069:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2069:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8m_malloci
.type _Z8m_malloci, @function
_Z8m_malloci:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movslq %edi, %rdi
imulq %rdi, %rdi
salq $2, %rdi
call malloc@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z8m_malloci, .-_Z8m_malloci
.globl _Z13m_fill_randomPii
.type _Z13m_fill_randomPii, @function
_Z13m_fill_randomPii:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbp
movl %esi, %ebx
call rand@PLT
movl %eax, %edi
call srand@PLT
movl %ebx, %esi
imull %ebx, %esi
testl %esi, %esi
jle .L5
movq %rbp, %rbx
movslq %esi, %rsi
leaq 0(%rbp,%rsi,4), %rbp
.L7:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L7
.L5:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z13m_fill_randomPii, .-_Z13m_fill_randomPii
.globl _Z6mm_cpuPiS_S_i
.type _Z6mm_cpuPiS_S_i, @function
_Z6mm_cpuPiS_S_i:
.LFB2059:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L18
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rdi, %r8
movq %rsi, %r13
movq %rdx, %r12
movl %ecx, %ebp
movslq %ecx, %rdi
salq $2, %rdi
movq %r8, %rbx
addq %rdi, %r8
movl $0, %r14d
movl $0, %r15d
jmp .L12
.L15:
movl %eax, %r11d
.L14:
movq %r9, %rsi
movl $0, (%r9)
movq %r10, %rcx
movq %rbx, %rax
.L13:
movl (%rax), %edx
imull (%rcx), %edx
addl %edx, (%rsi)
addq $4, %rax
addq %rdi, %rcx
cmpq %r8, %rax
jne .L13
leal 1(%r11), %eax
addq $4, %r9
addq $4, %r10
cmpl %eax, %ebp
jne .L15
leal 1(%r14), %eax
addq %rdi, %rbx
addq %rdi, %r8
addq %rdi, %r12
cmpl %r11d, %r14d
je .L10
movl %eax, %r14d
.L12:
movq %r13, %r10
movq %r12, %r9
movl %r15d, %r11d
jmp .L14
.L10:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2059:
.size _Z6mm_cpuPiS_S_i, .-_Z6mm_cpuPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.LC2:
.string "\n\n"
.LC3:
.string "\n \n"
.text
.globl _Z9print_matPiS_S_i
.type _Z9print_matPiS_S_i, @function
_Z9print_matPiS_S_i:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 12(%rsp)
testl %ecx, %ecx
jle .L22
movslq %ecx, %r14
leaq 0(,%r14,4), %r15
leaq (%rdi,%r15), %rbp
negq %r14
salq $2, %r14
movl $0, %r13d
leaq .LC0(%rip), %r12
.L23:
leaq 0(%rbp,%r14), %rbx
.L24:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L24
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leal 1(%r13), %eax
addq %r15, %rbp
cmpl %eax, 12(%rsp)
je .L25
movl %eax, %r13d
jmp .L23
.L25:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 16(%rsp), %rbp
addq %r15, %rbp
movl $0, 12(%rsp)
leaq .LC0(%rip), %r12
.L26:
leaq 0(%rbp,%r14), %rbx
.L27:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L27
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 12(%rsp), %ecx
leal 1(%rcx), %eax
addq %r15, %rbp
cmpl %ecx, %r13d
je .L28
movl %eax, 12(%rsp)
jmp .L26
.L28:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rbp
addq %r15, %rbp
movl $0, 12(%rsp)
leaq .LC0(%rip), %r12
.L29:
leaq 0(%rbp,%r14), %rbx
.L30:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L30
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 12(%rsp), %ecx
leal 1(%rcx), %eax
addq %r15, %rbp
cmpl %ecx, %r13d
je .L21
movl %eax, 12(%rsp)
jmp .L29
.L22:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L21:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z9print_matPiS_S_i, .-_Z9print_matPiS_S_i
.globl _Z10GetElement6Matrixii
.type _Z10GetElement6Matrixii, @function
_Z10GetElement6Matrixii:
.LFB2061:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z10GetElement6Matrixii, .-_Z10GetElement6Matrixii
.globl _Z10SetElement6Matrixiif
.type _Z10SetElement6Matrixiif, @function
_Z10SetElement6Matrixiif:
.LFB2062:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2062:
.size _Z10SetElement6Matrixiif, .-_Z10SetElement6Matrixiif
.globl _Z12GetSubMatrix6Matrixii
.type _Z12GetSubMatrix6Matrixii, @function
_Z12GetSubMatrix6Matrixii:
.LFB2063:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2063:
.size _Z12GetSubMatrix6Matrixii, .-_Z12GetSubMatrix6Matrixii
.globl _Z43__device_stub__Z14MatMulKernel_g6MatrixS_S_R6MatrixS0_S0_
.type _Z43__device_stub__Z14MatMulKernel_g6MatrixS_S_R6MatrixS0_S0_, @function
_Z43__device_stub__Z14MatMulKernel_g6MatrixS_S_R6MatrixS0_S0_:
.LFB2091:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 80(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L46
.L42:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L47
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 120
pushq 8(%rsp)
.cfi_def_cfa_offset 128
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z14MatMulKernel_g6MatrixS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L42
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2091:
.size _Z43__device_stub__Z14MatMulKernel_g6MatrixS_S_R6MatrixS0_S0_, .-_Z43__device_stub__Z14MatMulKernel_g6MatrixS_S_R6MatrixS0_S0_
.globl _Z14MatMulKernel_g6MatrixS_S_
.type _Z14MatMulKernel_g6MatrixS_S_, @function
_Z14MatMulKernel_g6MatrixS_S_:
.LFB2092:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq 64(%rsp), %rdx
leaq 40(%rsp), %rsi
leaq 16(%rsp), %rdi
call _Z43__device_stub__Z14MatMulKernel_g6MatrixS_S_R6MatrixS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _Z14MatMulKernel_g6MatrixS_S_, .-_Z14MatMulKernel_g6MatrixS_S_
.globl _Z8MatMul_g6MatrixS_S_i
.type _Z8MatMul_g6MatrixS_S_i, @function
_Z8MatMul_g6MatrixS_S_i:
.LFB2065:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $232, %rsp
.cfi_def_cfa_offset 288
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
movl 288(%rsp), %r15d
movl 292(%rsp), %r12d
movl 312(%rsp), %r13d
movl 316(%rsp), %ebp
movl 336(%rsp), %ebx
movl 340(%rsp), %r14d
movl %r15d, 32(%rsp)
movl %r12d, 36(%rsp)
imull %r12d, %r15d
movslq %r15d, %r15
salq $2, %r15
call cudaSetDevice@PLT
leaq 48(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r15, %rdx
movq 304(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %r13d, 64(%rsp)
movl %ebp, 68(%rsp)
imull %r13d, %ebp
movslq %ebp, %rbp
salq $2, %rbp
leaq 80(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 328(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebx, 96(%rsp)
movl %r14d, 100(%rsp)
imull %r14d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 112(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
shrl $4, %r13d
movl %r13d, 20(%rsp)
shrl $4, %r12d
movl %r12d, 24(%rsp)
movl $16, 8(%rsp)
movl $16, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L54
.L51:
movl $2, %ecx
movq %rbx, %rdx
movq 112(%rsp), %rsi
movq 352(%rsp), %rdi
call cudaMemcpy@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 112(%rsp), %rdi
call cudaFree@PLT
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L55
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
movdqa 32(%rsp), %xmm0
movaps %xmm0, 128(%rsp)
movq 48(%rsp), %rax
movq %rax, 144(%rsp)
movdqa 64(%rsp), %xmm1
movaps %xmm1, 160(%rsp)
movq 80(%rsp), %rax
movq %rax, 176(%rsp)
movdqa 96(%rsp), %xmm2
movaps %xmm2, 192(%rsp)
movq 112(%rsp), %rax
movq %rax, 208(%rsp)
leaq 192(%rsp), %rdx
leaq 160(%rsp), %rsi
leaq 128(%rsp), %rdi
call _Z43__device_stub__Z14MatMulKernel_g6MatrixS_S_R6MatrixS0_S0_
jmp .L51
.L55:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2065:
.size _Z8MatMul_g6MatrixS_S_i, .-_Z8MatMul_g6MatrixS_S_i
.globl _Z43__device_stub__Z14MatMulKernel_s6MatrixS_S_R6MatrixS0_S0_
.type _Z43__device_stub__Z14MatMulKernel_s6MatrixS_S_R6MatrixS0_S0_, @function
_Z43__device_stub__Z14MatMulKernel_s6MatrixS_S_R6MatrixS0_S0_:
.LFB2093:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 80(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L60
.L56:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L61
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 120
pushq 8(%rsp)
.cfi_def_cfa_offset 128
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z14MatMulKernel_s6MatrixS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L56
.L61:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2093:
.size _Z43__device_stub__Z14MatMulKernel_s6MatrixS_S_R6MatrixS0_S0_, .-_Z43__device_stub__Z14MatMulKernel_s6MatrixS_S_R6MatrixS0_S0_
.globl _Z14MatMulKernel_s6MatrixS_S_
.type _Z14MatMulKernel_s6MatrixS_S_, @function
_Z14MatMulKernel_s6MatrixS_S_:
.LFB2094:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq 64(%rsp), %rdx
leaq 40(%rsp), %rsi
leaq 16(%rsp), %rdi
call _Z43__device_stub__Z14MatMulKernel_s6MatrixS_S_R6MatrixS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2094:
.size _Z14MatMulKernel_s6MatrixS_S_, .-_Z14MatMulKernel_s6MatrixS_S_
.globl _Z8MatMul_s6MatrixS_S_i
.type _Z8MatMul_s6MatrixS_S_i, @function
_Z8MatMul_s6MatrixS_S_i:
.LFB2066:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $232, %rsp
.cfi_def_cfa_offset 288
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
movl 288(%rsp), %r15d
movl 292(%rsp), %r12d
movl 312(%rsp), %r13d
movl 316(%rsp), %ebp
movl 336(%rsp), %ebx
movl 340(%rsp), %r14d
movl %r15d, 32(%rsp)
movl %r12d, 36(%rsp)
imull %r12d, %r15d
movslq %r15d, %r15
salq $2, %r15
call cudaSetDevice@PLT
leaq 48(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r15, %rdx
movq 304(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %r13d, 64(%rsp)
movl %ebp, 68(%rsp)
imull %r13d, %ebp
movslq %ebp, %rbp
salq $2, %rbp
leaq 80(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 328(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebx, 96(%rsp)
movl %r14d, 100(%rsp)
imull %r14d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 112(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
shrl $4, %r13d
movl %r13d, 20(%rsp)
shrl $4, %r12d
movl %r12d, 24(%rsp)
movl $16, 8(%rsp)
movl $16, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L68
.L65:
movl $2, %ecx
movq %rbx, %rdx
movq 112(%rsp), %rsi
movq 352(%rsp), %rdi
call cudaMemcpy@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 112(%rsp), %rdi
call cudaFree@PLT
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L69
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L68:
.cfi_restore_state
movdqa 32(%rsp), %xmm0
movaps %xmm0, 128(%rsp)
movq 48(%rsp), %rax
movq %rax, 144(%rsp)
movdqa 64(%rsp), %xmm1
movaps %xmm1, 160(%rsp)
movq 80(%rsp), %rax
movq %rax, 176(%rsp)
movdqa 96(%rsp), %xmm2
movaps %xmm2, 192(%rsp)
movq 112(%rsp), %rax
movq %rax, 208(%rsp)
leaq 192(%rsp), %rdx
leaq 160(%rsp), %rsi
leaq 128(%rsp), %rdi
call _Z43__device_stub__Z14MatMulKernel_s6MatrixS_S_R6MatrixS0_S0_
jmp .L65
.L69:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2066:
.size _Z8MatMul_s6MatrixS_S_i, .-_Z8MatMul_s6MatrixS_S_i
.section .rodata.str1.1
.LC4:
.string "======= Matriz %dx%d =======\n"
.LC7:
.string "CPU = %10.1fms \n"
.LC8:
.string "GPU_GLOBAL - %s = %10.1fms \n"
.LC9:
.string "GPU_SHARED - %s = %10.1fms \n"
.text
.globl main
.type main, @function
main:
.LFB2064:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $1136, %rsp
.cfi_def_cfa_offset 1184
movq %fs:40, %rax
movq %rax, 1128(%rsp)
xorl %eax, %eax
movl $1024, %ecx
movl $1024, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
movl $1024, (%rsp)
movl $1024, 4(%rsp)
movq %rbp, 16(%rsp)
movl $1024, 32(%rsp)
movl $1024, 36(%rsp)
movq %rbx, 48(%rsp)
movl $1024, 64(%rsp)
movl $1024, 68(%rsp)
movq %rax, 80(%rsp)
movl $1024, %esi
movq %rbp, %rdi
call _Z13m_fill_randomPii
movl $1024, %esi
movq %rbx, %rdi
call _Z13m_fill_randomPii
call clock@PLT
movq %rax, %r13
movl $1024, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z6mm_cpuPiS_S_i
call clock@PLT
subq %r13, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC5(%rip), %xmm0
mulss .LC6(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 96(%rsp), %r13
movl $1, %esi
movq %r13, %rdi
call cudaGetDeviceProperties_v2@PLT
movl $1, %edi
call cudaSetDevice@PLT
call clock@PLT
movq %rax, %r14
subq $80, %rsp
.cfi_def_cfa_offset 1264
movdqa 144(%rsp), %xmm1
movups %xmm1, 48(%rsp)
movq 160(%rsp), %rax
movq %rax, 64(%rsp)
movdqa 112(%rsp), %xmm2
movups %xmm2, 24(%rsp)
movq 128(%rsp), %rax
movq %rax, 40(%rsp)
movdqa 80(%rsp), %xmm3
movups %xmm3, (%rsp)
movq 96(%rsp), %rax
movq %rax, 16(%rsp)
movl $1, %edi
call _Z8MatMul_g6MatrixS_S_i
addq $80, %rsp
.cfi_def_cfa_offset 1184
call clock@PLT
subq %r14, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC5(%rip), %xmm0
mulss .LC6(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %r13, %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call clock@PLT
movq %rax, %r14
subq $80, %rsp
.cfi_def_cfa_offset 1264
movdqa 144(%rsp), %xmm4
movups %xmm4, 48(%rsp)
movq 160(%rsp), %rax
movq %rax, 64(%rsp)
movdqa 112(%rsp), %xmm5
movups %xmm5, 24(%rsp)
movq 128(%rsp), %rax
movq %rax, 40(%rsp)
movdqa 80(%rsp), %xmm6
movups %xmm6, (%rsp)
movq 96(%rsp), %rax
movq %rax, 16(%rsp)
movl $1, %edi
call _Z8MatMul_s6MatrixS_S_i
addq $80, %rsp
.cfi_def_cfa_offset 1184
call clock@PLT
subq %r14, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC5(%rip), %xmm0
mulss .LC6(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %r13, %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 1128(%rsp), %rax
subq %fs:40, %rax
jne .L73
movl $0, %eax
addq $1136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L73:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2064:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z14MatMulKernel_s6MatrixS_S_"
.LC11:
.string "_Z14MatMulKernel_g6MatrixS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2096:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z14MatMulKernel_s6MatrixS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z14MatMulKernel_g6MatrixS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 1232348160
.align 4
.LC6:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdio.h>
#include <math.h>
#include <time.h>
int* m_malloc(int n) {
return (int* )malloc(sizeof (int) * n * n);
}
void m_fill_random(int * mat, int n) {
//srand((unsigned int)time(NULL));
// int seed = rand();
// use same seed to draw the same image again on every test
srand(rand());
int i;
for (i = 0; i < n * n; i++) {
mat[i] = rand() % 10;
}
}
void mm_cpu(int * A, int * B, int * C, int n) {
int i, j, k;
for (i = 0; i < n; i++)
for (j = 0; j < n; j++) {
C[i * n + j] = 0;
for (k = 0; k < n; k++)
C[i * n + j] += A[i * n + k] * B[k * n + j];
}
}
void print_mat(int * A, int * B, int * C, int n) {
int i, j;
for (i = 0; i < n; i++) {
for (j = 0; j < n; j++)
printf("%d ", A[i * n + j]);
printf("\n");
}
printf("\n\n");
for (i = 0; i < n; i++) {
for (j = 0; j < n; j++)
printf("%d ", B[i * n + j]);
printf("\n");
}
printf("\n \n");
for (i = 0; i < n; i++) {
for (j = 0; j < n; j++)
printf("%d ", C[i * n + j]);
printf("\n");
}
}
// Matrices are stored in row-major order:
// M(row, col) = *(M.elements + row * M.width + col)
typedef struct {
int width;
int height;
int stride; // necessario para o metodo com shared memory
int* elements;
} Matrix;
// Thread block size
#define BLOCK_SIZE 16
// GET e SET elementos do device
__device__ float GetElement(const Matrix A, int row, int col) { // Get a matrix element
return A.elements[row * A.stride + col];
}
__device__ void SetElement(Matrix A, int row, int col, float value) { // Set a matrix element
A.elements[row * A.stride + col] = value;
}
// Get the BLOCK_SIZExBLOCK_SIZE sub-matrix Asub of A that is located col sub-matrices to the right and row
__device__ Matrix GetSubMatrix(Matrix A, int row, int col) { // sub-matrices down from the upper-left corner of A
Matrix Asub;
Asub.width = BLOCK_SIZE;
Asub.height = BLOCK_SIZE;
Asub.stride = A.stride;
Asub.elements = &A.elements[A.stride * BLOCK_SIZE * row + BLOCK_SIZE * col];
return Asub;
}
// Forward declaration of the matrix multiplication kernel
__global__ void MatMulKernel_g(const Matrix, const Matrix, Matrix);
__global__ void MatMulKernel_s(const Matrix, const Matrix, Matrix);
void MatMul_g(const Matrix A, const Matrix B, Matrix C, int device);
void MatMul_s(const Matrix A, const Matrix B, Matrix C, int device);
int main() {
clock_t t;
float time;
int co = 2;
int size[7] = {256, 512, 1024, 2048, 4096, 8192, 16384}; // more sizes
int n = size[co];
printf("======= Matriz %dx%d =======\n", n, n);
int* A = m_malloc(n);
int* B = m_malloc(n);
int* C = m_malloc(n);
Matrix mA;
mA.width = n;
mA.height = n;
mA.elements = A;
Matrix mB;
mB.width = n;
mB.height = n;
mB.elements = B;
Matrix mC;
mC.width = n;
mC.height = n;
mC.elements = C;
m_fill_random(A, n);
m_fill_random(B, n);
time = 0;
t = clock();
mm_cpu(A, B, C, n);
time = (float)(clock() - t);
time = time / CLOCKS_PER_SEC;
printf("CPU = %10.1fms \n", time * 1000);
int count = 1;
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, count);
cudaSetDevice(count);
t = clock();
MatMul_g(mA, mB, mC, count);
time = (float)(clock() - t);
time = time / CLOCKS_PER_SEC;
printf("GPU_GLOBAL - %s = %10.1fms \n", prop.name, time * 1000);
t = clock();
MatMul_s(mA, mB, mC, count);
time = (float)(clock() - t);
time = time / CLOCKS_PER_SEC;
printf("GPU_SHARED - %s = %10.1fms \n", prop.name, time * 1000);
free(A);
free(B);
free(C);
return 0;
}
// Matrix multiplication - Host code
// Matrix dimensions are assumed to be multiples of BLOCK_SIZE
void MatMul_g(const Matrix A, const Matrix B, Matrix C, int device) {
// Load A and B to device memory
Matrix d_A;
d_A.width = A.width;
d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
cudaSetDevice(device);
cudaMalloc(&d_A.elements, size);
cudaMemcpy(d_A.elements, A.elements, size, cudaMemcpyHostToDevice);
Matrix d_B;
d_B.width = B.width;
d_B.height = B.height;
size = B.width * B.height * sizeof(float);
cudaMalloc(&d_B.elements, size);
cudaMemcpy(d_B.elements, B.elements, size, cudaMemcpyHostToDevice);
// Allocate C in device memory
Matrix d_C;
d_C.width = C.width;
d_C.height = C.height;
size = C.width * C.height * sizeof(float);
cudaMalloc(&d_C.elements, size);
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B.width / dimBlock.x, A.height / dimBlock.y);
MatMulKernel_g <<< dimGrid, dimBlock>>>(d_A, d_B, d_C);
// Read C from device memory
cudaMemcpy(C.elements, d_C.elements, size, cudaMemcpyDeviceToHost);
// Free device memory
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
}
// PRATICAMENTE IGUAL AO ANTERIOR, COM A DIFERENCA
// QUE O KERNEL INVOCADO AQUI EH O DE SHARED AO INVES DO GLOBAL
void MatMul_s(const Matrix A, const Matrix B, Matrix C, int device) {
// Load A and B to device memory
Matrix d_A;
d_A.width = A.width;
d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
cudaSetDevice(device);
cudaMalloc(&d_A.elements, size);
cudaMemcpy(d_A.elements, A.elements, size, cudaMemcpyHostToDevice);
Matrix d_B;
d_B.width = B.width;
d_B.height = B.height;
size = B.width * B.height * sizeof(float);
cudaMalloc(&d_B.elements, size);
cudaMemcpy(d_B.elements, B.elements, size, cudaMemcpyHostToDevice);
// Allocate C in device memory
Matrix d_C;
d_C.width = C.width;
d_C.height = C.height;
size = C.width * C.height * sizeof(float);
cudaMalloc(&d_C.elements, size);
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B.width / dimBlock.x, A.height / dimBlock.y);
MatMulKernel_s <<< dimGrid, dimBlock>>>(d_A, d_B, d_C);
// Read C from device memory
cudaMemcpy(C.elements, d_C.elements, size, cudaMemcpyDeviceToHost);
// Free device memory
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
}
// MULTIPLICACAO DE MATRIZES UTILIZANDO MEMORIA GLOBAL
__global__ void MatMulKernel_g(Matrix A, Matrix B, Matrix C) {
// Each thread computes one element of C by accumulating results into Cvalue
float Cvalue = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
for (int e = 0; e < A.width; ++e)
Cvalue += A.elements[row * A.width + e] * B.elements[e * B.width + col];
C.elements[row * C.width + col] = Cvalue;
}
// MULTIPLICACAO DE MATRIZES UTILIZANDO MEMORIA COMPARTILHADA
__global__ void MatMulKernel_s(Matrix A, Matrix B, Matrix C)
{
// Block row and column
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
// Each thread block computes one sub-matrix Csub of C
Matrix Csub = GetSubMatrix(C, blockRow, blockCol);
// Each thread computes one element of Csub
// by accumulating results into Cvalue
float Cvalue = 0;
// Thread row and column within Csub
int row = threadIdx.y;
int col = threadIdx.x;
// Loop over all the sub-matrices of A and B that are
// required to compute Csub
// Multiply each pair of sub-matrices together
// and accumulate the results
for (int m = 0; m < (A.width / BLOCK_SIZE); ++m) {
// Get sub-matrix Asub of A
Matrix Asub = GetSubMatrix(A, blockRow, m);
// Get sub-matrix Bsub of B
Matrix Bsub = GetSubMatrix(B, m, blockCol);
// Shared memory used to store Asub and Bsub respectively
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
// Load Asub and Bsub from device memory to shared memory
// Each thread loads one element of each sub-matrix
As[row][col] = GetElement(Asub, row, col);
Bs[row][col] = GetElement(Bsub, row, col);
// Synchronize to make sure the sub-matrices are loaded
// before starting the computation
__syncthreads();
// Multiply Asub and Bsub together
for (int e = 0; e < BLOCK_SIZE; ++e)
Cvalue += As[row][e] * Bs[e][col];
// Synchronize to make sure that the preceding
// computation is done before loading two new
// sub-matrices of A and B in the next iteration
__syncthreads();
}
// Write Csub to device memory Each thread writes one element
SetElement(Csub, row, col, Cvalue);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdio.h>
#include <math.h>
#include <time.h>
int* m_malloc(int n) {
return (int* )malloc(sizeof (int) * n * n);
}
void m_fill_random(int * mat, int n) {
//srand((unsigned int)time(NULL));
// int seed = rand();
// use same seed to draw the same image again on every test
srand(rand());
int i;
for (i = 0; i < n * n; i++) {
mat[i] = rand() % 10;
}
}
void mm_cpu(int * A, int * B, int * C, int n) {
int i, j, k;
for (i = 0; i < n; i++)
for (j = 0; j < n; j++) {
C[i * n + j] = 0;
for (k = 0; k < n; k++)
C[i * n + j] += A[i * n + k] * B[k * n + j];
}
}
void print_mat(int * A, int * B, int * C, int n) {
int i, j;
for (i = 0; i < n; i++) {
for (j = 0; j < n; j++)
printf("%d ", A[i * n + j]);
printf("\n");
}
printf("\n\n");
for (i = 0; i < n; i++) {
for (j = 0; j < n; j++)
printf("%d ", B[i * n + j]);
printf("\n");
}
printf("\n \n");
for (i = 0; i < n; i++) {
for (j = 0; j < n; j++)
printf("%d ", C[i * n + j]);
printf("\n");
}
}
// Matrices are stored in row-major order:
// M(row, col) = *(M.elements + row * M.width + col)
typedef struct {
int width;
int height;
int stride; // necessario para o metodo com shared memory
int* elements;
} Matrix;
// Thread block size
#define BLOCK_SIZE 16
// GET e SET elementos do device
__device__ float GetElement(const Matrix A, int row, int col) { // Get a matrix element
return A.elements[row * A.stride + col];
}
__device__ void SetElement(Matrix A, int row, int col, float value) { // Set a matrix element
A.elements[row * A.stride + col] = value;
}
// Get the BLOCK_SIZExBLOCK_SIZE sub-matrix Asub of A that is located col sub-matrices to the right and row
__device__ Matrix GetSubMatrix(Matrix A, int row, int col) { // sub-matrices down from the upper-left corner of A
Matrix Asub;
Asub.width = BLOCK_SIZE;
Asub.height = BLOCK_SIZE;
Asub.stride = A.stride;
Asub.elements = &A.elements[A.stride * BLOCK_SIZE * row + BLOCK_SIZE * col];
return Asub;
}
// Forward declaration of the matrix multiplication kernel
__global__ void MatMulKernel_g(const Matrix, const Matrix, Matrix);
__global__ void MatMulKernel_s(const Matrix, const Matrix, Matrix);
void MatMul_g(const Matrix A, const Matrix B, Matrix C, int device);
void MatMul_s(const Matrix A, const Matrix B, Matrix C, int device);
int main() {
clock_t t;
float time;
int co = 2;
int size[7] = {256, 512, 1024, 2048, 4096, 8192, 16384}; // more sizes
int n = size[co];
printf("======= Matriz %dx%d =======\n", n, n);
int* A = m_malloc(n);
int* B = m_malloc(n);
int* C = m_malloc(n);
Matrix mA;
mA.width = n;
mA.height = n;
mA.elements = A;
Matrix mB;
mB.width = n;
mB.height = n;
mB.elements = B;
Matrix mC;
mC.width = n;
mC.height = n;
mC.elements = C;
m_fill_random(A, n);
m_fill_random(B, n);
time = 0;
t = clock();
mm_cpu(A, B, C, n);
time = (float)(clock() - t);
time = time / CLOCKS_PER_SEC;
printf("CPU = %10.1fms \n", time * 1000);
int count = 1;
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, count);
hipSetDevice(count);
t = clock();
MatMul_g(mA, mB, mC, count);
time = (float)(clock() - t);
time = time / CLOCKS_PER_SEC;
printf("GPU_GLOBAL - %s = %10.1fms \n", prop.name, time * 1000);
t = clock();
MatMul_s(mA, mB, mC, count);
time = (float)(clock() - t);
time = time / CLOCKS_PER_SEC;
printf("GPU_SHARED - %s = %10.1fms \n", prop.name, time * 1000);
free(A);
free(B);
free(C);
return 0;
}
// Matrix multiplication - Host code
// Matrix dimensions are assumed to be multiples of BLOCK_SIZE
void MatMul_g(const Matrix A, const Matrix B, Matrix C, int device) {
// Load A and B to device memory
Matrix d_A;
d_A.width = A.width;
d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
hipSetDevice(device);
hipMalloc(&d_A.elements, size);
hipMemcpy(d_A.elements, A.elements, size, hipMemcpyHostToDevice);
Matrix d_B;
d_B.width = B.width;
d_B.height = B.height;
size = B.width * B.height * sizeof(float);
hipMalloc(&d_B.elements, size);
hipMemcpy(d_B.elements, B.elements, size, hipMemcpyHostToDevice);
// Allocate C in device memory
Matrix d_C;
d_C.width = C.width;
d_C.height = C.height;
size = C.width * C.height * sizeof(float);
hipMalloc(&d_C.elements, size);
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B.width / dimBlock.x, A.height / dimBlock.y);
MatMulKernel_g <<< dimGrid, dimBlock>>>(d_A, d_B, d_C);
// Read C from device memory
hipMemcpy(C.elements, d_C.elements, size, hipMemcpyDeviceToHost);
// Free device memory
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
}
// PRATICAMENTE IGUAL AO ANTERIOR, COM A DIFERENCA
// QUE O KERNEL INVOCADO AQUI EH O DE SHARED AO INVES DO GLOBAL
void MatMul_s(const Matrix A, const Matrix B, Matrix C, int device) {
// Load A and B to device memory
Matrix d_A;
d_A.width = A.width;
d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
hipSetDevice(device);
hipMalloc(&d_A.elements, size);
hipMemcpy(d_A.elements, A.elements, size, hipMemcpyHostToDevice);
Matrix d_B;
d_B.width = B.width;
d_B.height = B.height;
size = B.width * B.height * sizeof(float);
hipMalloc(&d_B.elements, size);
hipMemcpy(d_B.elements, B.elements, size, hipMemcpyHostToDevice);
// Allocate C in device memory
Matrix d_C;
d_C.width = C.width;
d_C.height = C.height;
size = C.width * C.height * sizeof(float);
hipMalloc(&d_C.elements, size);
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B.width / dimBlock.x, A.height / dimBlock.y);
MatMulKernel_s <<< dimGrid, dimBlock>>>(d_A, d_B, d_C);
// Read C from device memory
hipMemcpy(C.elements, d_C.elements, size, hipMemcpyDeviceToHost);
// Free device memory
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
}
// MULTIPLICACAO DE MATRIZES UTILIZANDO MEMORIA GLOBAL
__global__ void MatMulKernel_g(Matrix A, Matrix B, Matrix C) {
// Each thread computes one element of C by accumulating results into Cvalue
float Cvalue = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
for (int e = 0; e < A.width; ++e)
Cvalue += A.elements[row * A.width + e] * B.elements[e * B.width + col];
C.elements[row * C.width + col] = Cvalue;
}
// MULTIPLICACAO DE MATRIZES UTILIZANDO MEMORIA COMPARTILHADA
__global__ void MatMulKernel_s(Matrix A, Matrix B, Matrix C)
{
// Block row and column
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
// Each thread block computes one sub-matrix Csub of C
Matrix Csub = GetSubMatrix(C, blockRow, blockCol);
// Each thread computes one element of Csub
// by accumulating results into Cvalue
float Cvalue = 0;
// Thread row and column within Csub
int row = threadIdx.y;
int col = threadIdx.x;
// Loop over all the sub-matrices of A and B that are
// required to compute Csub
// Multiply each pair of sub-matrices together
// and accumulate the results
for (int m = 0; m < (A.width / BLOCK_SIZE); ++m) {
// Get sub-matrix Asub of A
Matrix Asub = GetSubMatrix(A, blockRow, m);
// Get sub-matrix Bsub of B
Matrix Bsub = GetSubMatrix(B, m, blockCol);
// Shared memory used to store Asub and Bsub respectively
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
// Load Asub and Bsub from device memory to shared memory
// Each thread loads one element of each sub-matrix
As[row][col] = GetElement(Asub, row, col);
Bs[row][col] = GetElement(Bsub, row, col);
// Synchronize to make sure the sub-matrices are loaded
// before starting the computation
__syncthreads();
// Multiply Asub and Bsub together
for (int e = 0; e < BLOCK_SIZE; ++e)
Cvalue += As[row][e] * Bs[e][col];
// Synchronize to make sure that the preceding
// computation is done before loading two new
// sub-matrices of A and B in the next iteration
__syncthreads();
}
// Write Csub to device memory Each thread writes one element
SetElement(Csub, row, col, Cvalue);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdio.h>
#include <math.h>
#include <time.h>
int* m_malloc(int n) {
return (int* )malloc(sizeof (int) * n * n);
}
void m_fill_random(int * mat, int n) {
//srand((unsigned int)time(NULL));
// int seed = rand();
// use same seed to draw the same image again on every test
srand(rand());
int i;
for (i = 0; i < n * n; i++) {
mat[i] = rand() % 10;
}
}
void mm_cpu(int * A, int * B, int * C, int n) {
int i, j, k;
for (i = 0; i < n; i++)
for (j = 0; j < n; j++) {
C[i * n + j] = 0;
for (k = 0; k < n; k++)
C[i * n + j] += A[i * n + k] * B[k * n + j];
}
}
void print_mat(int * A, int * B, int * C, int n) {
int i, j;
for (i = 0; i < n; i++) {
for (j = 0; j < n; j++)
printf("%d ", A[i * n + j]);
printf("\n");
}
printf("\n\n");
for (i = 0; i < n; i++) {
for (j = 0; j < n; j++)
printf("%d ", B[i * n + j]);
printf("\n");
}
printf("\n \n");
for (i = 0; i < n; i++) {
for (j = 0; j < n; j++)
printf("%d ", C[i * n + j]);
printf("\n");
}
}
// Matrices are stored in row-major order:
// M(row, col) = *(M.elements + row * M.width + col)
typedef struct {
int width;
int height;
int stride; // necessario para o metodo com shared memory
int* elements;
} Matrix;
// Thread block size
#define BLOCK_SIZE 16
// GET e SET elementos do device
__device__ float GetElement(const Matrix A, int row, int col) { // Get a matrix element
return A.elements[row * A.stride + col];
}
__device__ void SetElement(Matrix A, int row, int col, float value) { // Set a matrix element
A.elements[row * A.stride + col] = value;
}
// Get the BLOCK_SIZExBLOCK_SIZE sub-matrix Asub of A that is located col sub-matrices to the right and row
__device__ Matrix GetSubMatrix(Matrix A, int row, int col) { // sub-matrices down from the upper-left corner of A
Matrix Asub;
Asub.width = BLOCK_SIZE;
Asub.height = BLOCK_SIZE;
Asub.stride = A.stride;
Asub.elements = &A.elements[A.stride * BLOCK_SIZE * row + BLOCK_SIZE * col];
return Asub;
}
// Forward declaration of the matrix multiplication kernel
__global__ void MatMulKernel_g(const Matrix, const Matrix, Matrix);
__global__ void MatMulKernel_s(const Matrix, const Matrix, Matrix);
void MatMul_g(const Matrix A, const Matrix B, Matrix C, int device);
void MatMul_s(const Matrix A, const Matrix B, Matrix C, int device);
int main() {
clock_t t;
float time;
int co = 2;
int size[7] = {256, 512, 1024, 2048, 4096, 8192, 16384}; // more sizes
int n = size[co];
printf("======= Matriz %dx%d =======\n", n, n);
int* A = m_malloc(n);
int* B = m_malloc(n);
int* C = m_malloc(n);
Matrix mA;
mA.width = n;
mA.height = n;
mA.elements = A;
Matrix mB;
mB.width = n;
mB.height = n;
mB.elements = B;
Matrix mC;
mC.width = n;
mC.height = n;
mC.elements = C;
m_fill_random(A, n);
m_fill_random(B, n);
time = 0;
t = clock();
mm_cpu(A, B, C, n);
time = (float)(clock() - t);
time = time / CLOCKS_PER_SEC;
printf("CPU = %10.1fms \n", time * 1000);
int count = 1;
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, count);
hipSetDevice(count);
t = clock();
MatMul_g(mA, mB, mC, count);
time = (float)(clock() - t);
time = time / CLOCKS_PER_SEC;
printf("GPU_GLOBAL - %s = %10.1fms \n", prop.name, time * 1000);
t = clock();
MatMul_s(mA, mB, mC, count);
time = (float)(clock() - t);
time = time / CLOCKS_PER_SEC;
printf("GPU_SHARED - %s = %10.1fms \n", prop.name, time * 1000);
free(A);
free(B);
free(C);
return 0;
}
// Matrix multiplication - Host code
// Matrix dimensions are assumed to be multiples of BLOCK_SIZE
void MatMul_g(const Matrix A, const Matrix B, Matrix C, int device) {
// Load A and B to device memory
Matrix d_A;
d_A.width = A.width;
d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
hipSetDevice(device);
hipMalloc(&d_A.elements, size);
hipMemcpy(d_A.elements, A.elements, size, hipMemcpyHostToDevice);
Matrix d_B;
d_B.width = B.width;
d_B.height = B.height;
size = B.width * B.height * sizeof(float);
hipMalloc(&d_B.elements, size);
hipMemcpy(d_B.elements, B.elements, size, hipMemcpyHostToDevice);
// Allocate C in device memory
Matrix d_C;
d_C.width = C.width;
d_C.height = C.height;
size = C.width * C.height * sizeof(float);
hipMalloc(&d_C.elements, size);
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B.width / dimBlock.x, A.height / dimBlock.y);
MatMulKernel_g <<< dimGrid, dimBlock>>>(d_A, d_B, d_C);
// Read C from device memory
hipMemcpy(C.elements, d_C.elements, size, hipMemcpyDeviceToHost);
// Free device memory
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
}
// PRATICAMENTE IGUAL AO ANTERIOR, COM A DIFERENCA
// QUE O KERNEL INVOCADO AQUI EH O DE SHARED AO INVES DO GLOBAL
void MatMul_s(const Matrix A, const Matrix B, Matrix C, int device) {
// Load A and B to device memory
Matrix d_A;
d_A.width = A.width;
d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
hipSetDevice(device);
hipMalloc(&d_A.elements, size);
hipMemcpy(d_A.elements, A.elements, size, hipMemcpyHostToDevice);
Matrix d_B;
d_B.width = B.width;
d_B.height = B.height;
size = B.width * B.height * sizeof(float);
hipMalloc(&d_B.elements, size);
hipMemcpy(d_B.elements, B.elements, size, hipMemcpyHostToDevice);
// Allocate C in device memory
Matrix d_C;
d_C.width = C.width;
d_C.height = C.height;
size = C.width * C.height * sizeof(float);
hipMalloc(&d_C.elements, size);
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B.width / dimBlock.x, A.height / dimBlock.y);
MatMulKernel_s <<< dimGrid, dimBlock>>>(d_A, d_B, d_C);
// Read C from device memory
hipMemcpy(C.elements, d_C.elements, size, hipMemcpyDeviceToHost);
// Free device memory
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
}
// MULTIPLICACAO DE MATRIZES UTILIZANDO MEMORIA GLOBAL
__global__ void MatMulKernel_g(Matrix A, Matrix B, Matrix C) {
// Each thread computes one element of C by accumulating results into Cvalue
float Cvalue = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
for (int e = 0; e < A.width; ++e)
Cvalue += A.elements[row * A.width + e] * B.elements[e * B.width + col];
C.elements[row * C.width + col] = Cvalue;
}
// MULTIPLICACAO DE MATRIZES UTILIZANDO MEMORIA COMPARTILHADA
__global__ void MatMulKernel_s(Matrix A, Matrix B, Matrix C)
{
// Block row and column
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
// Each thread block computes one sub-matrix Csub of C
Matrix Csub = GetSubMatrix(C, blockRow, blockCol);
// Each thread computes one element of Csub
// by accumulating results into Cvalue
float Cvalue = 0;
// Thread row and column within Csub
int row = threadIdx.y;
int col = threadIdx.x;
// Loop over all the sub-matrices of A and B that are
// required to compute Csub
// Multiply each pair of sub-matrices together
// and accumulate the results
for (int m = 0; m < (A.width / BLOCK_SIZE); ++m) {
// Get sub-matrix Asub of A
Matrix Asub = GetSubMatrix(A, blockRow, m);
// Get sub-matrix Bsub of B
Matrix Bsub = GetSubMatrix(B, m, blockCol);
// Shared memory used to store Asub and Bsub respectively
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
// Load Asub and Bsub from device memory to shared memory
// Each thread loads one element of each sub-matrix
As[row][col] = GetElement(Asub, row, col);
Bs[row][col] = GetElement(Bsub, row, col);
// Synchronize to make sure the sub-matrices are loaded
// before starting the computation
__syncthreads();
// Multiply Asub and Bsub together
for (int e = 0; e < BLOCK_SIZE; ++e)
Cvalue += As[row][e] * Bs[e][col];
// Synchronize to make sure that the preceding
// computation is done before loading two new
// sub-matrices of A and B in the next iteration
__syncthreads();
}
// Write Csub to device memory Each thread writes one element
SetElement(Csub, row, col, Cvalue);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14MatMulKernel_g6MatrixS_S_
.globl _Z14MatMulKernel_g6MatrixS_S_
.p2align 8
.type _Z14MatMulKernel_g6MatrixS_S_,@function
_Z14MatMulKernel_g6MatrixS_S_:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x54
s_load_b32 s6, s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x40
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s4, v[3:4]
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB0_4
s_load_b64 s[8:9], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v2, v0, s6
s_clause 0x1
s_load_b32 s7, s[0:1], 0x18
s_load_b64 s[4:5], s[0:1], 0x28
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s6, s6, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s6, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s7, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_mul_lo_u32 v5, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v5, v5
v_add_f32_e32 v6, v6, v5
s_cbranch_scc0 .LBB0_2
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v2, v6
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
.LBB0_5:
s_load_b32 s0, s[0:1], 0x30
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s0, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14MatMulKernel_g6MatrixS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 328
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14MatMulKernel_g6MatrixS_S_, .Lfunc_end0-_Z14MatMulKernel_g6MatrixS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14MatMulKernel_s6MatrixS_S_
.globl _Z14MatMulKernel_s6MatrixS_S_
.p2align 8
.type _Z14MatMulKernel_s6MatrixS_S_,@function
_Z14MatMulKernel_s6MatrixS_S_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x40
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s5, 16
s_cbranch_scc1 .LBB1_6
s_clause 0x3
s_load_b32 s10, s[0:1], 0x8
s_load_b32 s4, s[0:1], 0x20
s_load_b64 s[6:7], s[0:1], 0x10
s_load_b64 s[8:9], s[0:1], 0x28
v_lshlrev_b32_e32 v10, 2, v0
v_lshlrev_b32_e32 v2, 6, v1
s_ashr_i32 s11, s5, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_lshr_b32 s11, s11, 28
v_add_nc_u32_e32 v3, 0x400, v10
s_add_i32 s5, s5, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
s_ashr_i32 s5, s5, 4
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[4:5], null, s10, v1, v[0:1]
v_mad_u64_u32 v[6:7], null, s4, v1, v[0:1]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[8:9], 2, v[4:5]
v_add_nc_u32_e32 v4, v2, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[10:11], 2, v[6:7]
v_add_co_u32 v6, vcc_lo, s6, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v9, vcc_lo
v_add_co_u32 v8, vcc_lo, s8, v10
v_dual_mov_b32 v10, 0 :: v_dual_add_nc_u32 v5, v3, v2
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v11, vcc_lo
s_mul_i32 s6, s10, s15
s_mov_b32 s7, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB1_2:
s_mul_i32 s8, s7, s4
s_add_i32 s9, s7, s6
s_add_i32 s10, s8, s14
s_lshl_b32 s8, s9, 4
s_lshl_b32 s10, s10, 4
s_ashr_i32 s9, s8, 31
s_ashr_i32 s11, s10, 31
s_lshl_b64 s[8:9], s[8:9], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_u32 v11, vcc_lo, v6, s8
v_add_co_ci_u32_e32 v12, vcc_lo, s9, v7, vcc_lo
s_lshl_b64 s[8:9], s[10:11], 2
v_add_co_u32 v13, vcc_lo, v8, s8
v_add_co_ci_u32_e32 v14, vcc_lo, s9, v9, vcc_lo
global_load_b32 v11, v[11:12], off
global_load_b32 v12, v[13:14], off
s_mov_b32 s8, 0
s_waitcnt vmcnt(1)
v_cvt_f32_i32_e32 v13, v11
v_mov_b32_e32 v11, v3
s_waitcnt vmcnt(0)
v_cvt_f32_i32_e32 v12, v12
ds_store_b32 v4, v13
ds_store_b32 v5, v12
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB1_3:
v_add_nc_u32_e32 v12, s8, v2
s_add_i32 s8, s8, 4
ds_load_b32 v13, v11
ds_load_b32 v12, v12
v_add_nc_u32_e32 v11, 64, v11
s_cmp_eq_u32 s8, 64
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v10, v12, v13
s_cbranch_scc0 .LBB1_3
s_add_i32 s7, s7, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s7, s5
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_2
s_set_inst_prefetch_distance 0x2
v_cvt_i32_f32_e32 v2, v10
.LBB1_6:
s_load_b32 s0, s[0:1], 0x38
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[3:4], null, s0, v1, v[0:1]
s_mul_i32 s0, s0, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s0, s14
s_lshl_b32 s0, s0, 4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_ashr_i32 s1, s0, 31
v_ashrrev_i32_e32 v4, 31, v3
s_lshl_b64 s[0:1], s[0:1], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14MatMulKernel_s6MatrixS_S_
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 72
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z14MatMulKernel_s6MatrixS_S_, .Lfunc_end1-_Z14MatMulKernel_s6MatrixS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 24
.value_kind: by_value
- .offset: 24
.size: 24
.value_kind: by_value
- .offset: 48
.size: 24
.value_kind: by_value
- .offset: 72
.size: 4
.value_kind: hidden_block_count_x
- .offset: 76
.size: 4
.value_kind: hidden_block_count_y
- .offset: 80
.size: 4
.value_kind: hidden_block_count_z
- .offset: 84
.size: 2
.value_kind: hidden_group_size_x
- .offset: 86
.size: 2
.value_kind: hidden_group_size_y
- .offset: 88
.size: 2
.value_kind: hidden_group_size_z
- .offset: 90
.size: 2
.value_kind: hidden_remainder_x
- .offset: 92
.size: 2
.value_kind: hidden_remainder_y
- .offset: 94
.size: 2
.value_kind: hidden_remainder_z
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 136
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 328
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14MatMulKernel_g6MatrixS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14MatMulKernel_g6MatrixS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 24
.value_kind: by_value
- .offset: 24
.size: 24
.value_kind: by_value
- .offset: 48
.size: 24
.value_kind: by_value
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 72
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14MatMulKernel_s6MatrixS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14MatMulKernel_s6MatrixS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdio.h>
#include <math.h>
#include <time.h>
int* m_malloc(int n) {
return (int* )malloc(sizeof (int) * n * n);
}
void m_fill_random(int * mat, int n) {
//srand((unsigned int)time(NULL));
// int seed = rand();
// use same seed to draw the same image again on every test
srand(rand());
int i;
for (i = 0; i < n * n; i++) {
mat[i] = rand() % 10;
}
}
void mm_cpu(int * A, int * B, int * C, int n) {
int i, j, k;
for (i = 0; i < n; i++)
for (j = 0; j < n; j++) {
C[i * n + j] = 0;
for (k = 0; k < n; k++)
C[i * n + j] += A[i * n + k] * B[k * n + j];
}
}
void print_mat(int * A, int * B, int * C, int n) {
int i, j;
for (i = 0; i < n; i++) {
for (j = 0; j < n; j++)
printf("%d ", A[i * n + j]);
printf("\n");
}
printf("\n\n");
for (i = 0; i < n; i++) {
for (j = 0; j < n; j++)
printf("%d ", B[i * n + j]);
printf("\n");
}
printf("\n \n");
for (i = 0; i < n; i++) {
for (j = 0; j < n; j++)
printf("%d ", C[i * n + j]);
printf("\n");
}
}
// Matrices are stored in row-major order:
// M(row, col) = *(M.elements + row * M.width + col)
typedef struct {
int width;
int height;
int stride; // necessario para o metodo com shared memory
int* elements;
} Matrix;
// Thread block size
#define BLOCK_SIZE 16
// GET e SET elementos do device
__device__ float GetElement(const Matrix A, int row, int col) { // Get a matrix element
return A.elements[row * A.stride + col];
}
__device__ void SetElement(Matrix A, int row, int col, float value) { // Set a matrix element
A.elements[row * A.stride + col] = value;
}
// Get the BLOCK_SIZExBLOCK_SIZE sub-matrix Asub of A that is located col sub-matrices to the right and row
__device__ Matrix GetSubMatrix(Matrix A, int row, int col) { // sub-matrices down from the upper-left corner of A
Matrix Asub;
Asub.width = BLOCK_SIZE;
Asub.height = BLOCK_SIZE;
Asub.stride = A.stride;
Asub.elements = &A.elements[A.stride * BLOCK_SIZE * row + BLOCK_SIZE * col];
return Asub;
}
// Forward declaration of the matrix multiplication kernel
__global__ void MatMulKernel_g(const Matrix, const Matrix, Matrix);
__global__ void MatMulKernel_s(const Matrix, const Matrix, Matrix);
void MatMul_g(const Matrix A, const Matrix B, Matrix C, int device);
void MatMul_s(const Matrix A, const Matrix B, Matrix C, int device);
int main() {
clock_t t;
float time;
int co = 2;
int size[7] = {256, 512, 1024, 2048, 4096, 8192, 16384}; // more sizes
int n = size[co];
printf("======= Matriz %dx%d =======\n", n, n);
int* A = m_malloc(n);
int* B = m_malloc(n);
int* C = m_malloc(n);
Matrix mA;
mA.width = n;
mA.height = n;
mA.elements = A;
Matrix mB;
mB.width = n;
mB.height = n;
mB.elements = B;
Matrix mC;
mC.width = n;
mC.height = n;
mC.elements = C;
m_fill_random(A, n);
m_fill_random(B, n);
time = 0;
t = clock();
mm_cpu(A, B, C, n);
time = (float)(clock() - t);
time = time / CLOCKS_PER_SEC;
printf("CPU = %10.1fms \n", time * 1000);
int count = 1;
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, count);
hipSetDevice(count);
t = clock();
MatMul_g(mA, mB, mC, count);
time = (float)(clock() - t);
time = time / CLOCKS_PER_SEC;
printf("GPU_GLOBAL - %s = %10.1fms \n", prop.name, time * 1000);
t = clock();
MatMul_s(mA, mB, mC, count);
time = (float)(clock() - t);
time = time / CLOCKS_PER_SEC;
printf("GPU_SHARED - %s = %10.1fms \n", prop.name, time * 1000);
free(A);
free(B);
free(C);
return 0;
}
// Matrix multiplication - Host code
// Matrix dimensions are assumed to be multiples of BLOCK_SIZE
void MatMul_g(const Matrix A, const Matrix B, Matrix C, int device) {
// Load A and B to device memory
Matrix d_A;
d_A.width = A.width;
d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
hipSetDevice(device);
hipMalloc(&d_A.elements, size);
hipMemcpy(d_A.elements, A.elements, size, hipMemcpyHostToDevice);
Matrix d_B;
d_B.width = B.width;
d_B.height = B.height;
size = B.width * B.height * sizeof(float);
hipMalloc(&d_B.elements, size);
hipMemcpy(d_B.elements, B.elements, size, hipMemcpyHostToDevice);
// Allocate C in device memory
Matrix d_C;
d_C.width = C.width;
d_C.height = C.height;
size = C.width * C.height * sizeof(float);
hipMalloc(&d_C.elements, size);
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B.width / dimBlock.x, A.height / dimBlock.y);
MatMulKernel_g <<< dimGrid, dimBlock>>>(d_A, d_B, d_C);
// Read C from device memory
hipMemcpy(C.elements, d_C.elements, size, hipMemcpyDeviceToHost);
// Free device memory
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
}
// PRATICAMENTE IGUAL AO ANTERIOR, COM A DIFERENCA
// QUE O KERNEL INVOCADO AQUI EH O DE SHARED AO INVES DO GLOBAL
void MatMul_s(const Matrix A, const Matrix B, Matrix C, int device) {
// Load A and B to device memory
Matrix d_A;
d_A.width = A.width;
d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
hipSetDevice(device);
hipMalloc(&d_A.elements, size);
hipMemcpy(d_A.elements, A.elements, size, hipMemcpyHostToDevice);
Matrix d_B;
d_B.width = B.width;
d_B.height = B.height;
size = B.width * B.height * sizeof(float);
hipMalloc(&d_B.elements, size);
hipMemcpy(d_B.elements, B.elements, size, hipMemcpyHostToDevice);
// Allocate C in device memory
Matrix d_C;
d_C.width = C.width;
d_C.height = C.height;
size = C.width * C.height * sizeof(float);
hipMalloc(&d_C.elements, size);
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B.width / dimBlock.x, A.height / dimBlock.y);
MatMulKernel_s <<< dimGrid, dimBlock>>>(d_A, d_B, d_C);
// Read C from device memory
hipMemcpy(C.elements, d_C.elements, size, hipMemcpyDeviceToHost);
// Free device memory
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
}
// MULTIPLICACAO DE MATRIZES UTILIZANDO MEMORIA GLOBAL
__global__ void MatMulKernel_g(Matrix A, Matrix B, Matrix C) {
// Each thread computes one element of C by accumulating results into Cvalue
float Cvalue = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
for (int e = 0; e < A.width; ++e)
Cvalue += A.elements[row * A.width + e] * B.elements[e * B.width + col];
C.elements[row * C.width + col] = Cvalue;
}
// MULTIPLICACAO DE MATRIZES UTILIZANDO MEMORIA COMPARTILHADA
__global__ void MatMulKernel_s(Matrix A, Matrix B, Matrix C)
{
// Block row and column
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
// Each thread block computes one sub-matrix Csub of C
Matrix Csub = GetSubMatrix(C, blockRow, blockCol);
// Each thread computes one element of Csub
// by accumulating results into Cvalue
float Cvalue = 0;
// Thread row and column within Csub
int row = threadIdx.y;
int col = threadIdx.x;
// Loop over all the sub-matrices of A and B that are
// required to compute Csub
// Multiply each pair of sub-matrices together
// and accumulate the results
for (int m = 0; m < (A.width / BLOCK_SIZE); ++m) {
// Get sub-matrix Asub of A
Matrix Asub = GetSubMatrix(A, blockRow, m);
// Get sub-matrix Bsub of B
Matrix Bsub = GetSubMatrix(B, m, blockCol);
// Shared memory used to store Asub and Bsub respectively
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
// Load Asub and Bsub from device memory to shared memory
// Each thread loads one element of each sub-matrix
As[row][col] = GetElement(Asub, row, col);
Bs[row][col] = GetElement(Bsub, row, col);
// Synchronize to make sure the sub-matrices are loaded
// before starting the computation
__syncthreads();
// Multiply Asub and Bsub together
for (int e = 0; e < BLOCK_SIZE; ++e)
Cvalue += As[row][e] * Bs[e][col];
// Synchronize to make sure that the preceding
// computation is done before loading two new
// sub-matrices of A and B in the next iteration
__syncthreads();
}
// Write Csub to device memory Each thread writes one element
SetElement(Csub, row, col, Cvalue);
} | .text
.file "main.hip"
.globl _Z8m_malloci # -- Begin function _Z8m_malloci
.p2align 4, 0x90
.type _Z8m_malloci,@function
_Z8m_malloci: # @_Z8m_malloci
.cfi_startproc
# %bb.0:
movslq %edi, %rdi
imulq %rdi, %rdi
shlq $2, %rdi
jmp malloc # TAILCALL
.Lfunc_end0:
.size _Z8m_malloci, .Lfunc_end0-_Z8m_malloci
.cfi_endproc
# -- End function
.globl _Z13m_fill_randomPii # -- Begin function _Z13m_fill_randomPii
.p2align 4, 0x90
.type _Z13m_fill_randomPii,@function
_Z13m_fill_randomPii: # @_Z13m_fill_randomPii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %ebx
movq %rdi, %r14
callq rand
movl %eax, %edi
callq srand
testl %ebx, %ebx
je .LBB1_3
# %bb.1: # %.lr.ph.preheader
imull %ebx, %ebx
cmpl $1, %ebx
adcl $0, %ebx
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%r14,%r15,4)
incq %r15
cmpq %r15, %rbx
jne .LBB1_2
.LBB1_3: # %._crit_edge
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z13m_fill_randomPii, .Lfunc_end1-_Z13m_fill_randomPii
.cfi_endproc
# -- End function
.globl _Z6mm_cpuPiS_S_i # -- Begin function _Z6mm_cpuPiS_S_i
.p2align 4, 0x90
.type _Z6mm_cpuPiS_S_i,@function
_Z6mm_cpuPiS_S_i: # @_Z6mm_cpuPiS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, -8(%rsp) # 8-byte Spill
testl %ecx, %ecx
jle .LBB2_7
# %bb.1: # %.preheader.lr.ph
movl %ecx, %eax
leaq (,%rax,4), %r8
xorl %edx, %edx
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
# Child Loop BB2_4 Depth 3
movl %edx, %r11d
leaq (%rdi,%r11,4), %r11
movq %r10, %rbx
imulq %rax, %rbx
movq -8(%rsp), %r9 # 8-byte Reload
leaq (%r9,%rbx,4), %rbx
movq %rsi, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph
# Parent Loop BB2_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_4 Depth 3
movl $0, (%rbx,%r15,4)
xorl %r12d, %r12d
movq %r14, %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# Parent Loop BB2_3 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r13), %r9d
imull (%r11,%r12,4), %r9d
addl %r9d, %ebp
movl %ebp, (%rbx,%r15,4)
incq %r12
addq %r8, %r13
cmpq %r12, %rax
jne .LBB2_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB2_3 Depth=2
incq %r15
addq $4, %r14
cmpq %rax, %r15
jne .LBB2_3
# %bb.6: # %._crit_edge30
# in Loop: Header=BB2_2 Depth=1
incq %r10
addl %ecx, %edx
cmpq %rax, %r10
jne .LBB2_2
.LBB2_7: # %._crit_edge32
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z6mm_cpuPiS_S_i, .Lfunc_end2-_Z6mm_cpuPiS_S_i
.cfi_endproc
# -- End function
.globl _Z9print_matPiS_S_i # -- Begin function _Z9print_matPiS_S_i
.p2align 4, 0x90
.type _Z9print_matPiS_S_i,@function
_Z9print_matPiS_S_i: # @_Z9print_matPiS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebx
movq %rdx, 16(%rsp) # 8-byte Spill
movq %rsi, 8(%rsp) # 8-byte Spill
movq %rdi, (%rsp) # 8-byte Spill
movl %ecx, %r13d
testl %ecx, %ecx
jle .LBB3_5
# %bb.1: # %.preheader38.lr.ph
xorl %ebp, %ebp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_2: # %.preheader38
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
movl %ebp, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_3: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r15,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq %r12, %r13
jne .LBB3_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addl %ebx, %ebp
cmpq %r13, %r14
jne .LBB3_2
.LBB3_5: # %._crit_edge41
movl $.Lstr, %edi
callq puts@PLT
testl %ebx, %ebx
jle .LBB3_10
# %bb.6: # %.preheader37.lr.ph
xorl %ebp, %ebp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_7: # %.preheader37
# =>This Loop Header: Depth=1
# Child Loop BB3_8 Depth 2
movl %ebp, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_8: # Parent Loop BB3_7 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r15,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq %r12, %r13
jne .LBB3_8
# %bb.9: # %._crit_edge44
# in Loop: Header=BB3_7 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addl %ebx, %ebp
cmpq %r13, %r14
jne .LBB3_7
.LBB3_10: # %._crit_edge46
movl $.Lstr.1, %edi
callq puts@PLT
testl %ebx, %ebx
jle .LBB3_15
# %bb.11: # %.preheader.lr.ph
xorl %ebp, %ebp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_12: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_13 Depth 2
movl %ebp, %eax
movq 16(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_13: # Parent Loop BB3_12 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r15,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq %r12, %r13
jne .LBB3_13
# %bb.14: # %._crit_edge49
# in Loop: Header=BB3_12 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addl %ebx, %ebp
cmpq %r13, %r14
jne .LBB3_12
.LBB3_15: # %._crit_edge51
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z9print_matPiS_S_i, .Lfunc_end3-_Z9print_matPiS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x49742400 # float 1.0E+6
.LCPI4_1:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0: # %.lr.ph.preheader.i
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1688, %rsp # imm = 0x698
.cfi_def_cfa_offset 1744
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %r12d, %r12d
movl $.L.str.4, %edi
movl $1024, %esi # imm = 0x400
movl $1024, %edx # imm = 0x400
xorl %eax, %eax
callq printf
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r15
callq rand
movl %eax, %edi
callq srand
.p2align 4, 0x90
.LBB4_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r12,4)
incq %r12
cmpq $1048576, %r12 # imm = 0x100000
jne .LBB4_1
# %bb.2: # %_Z13m_fill_randomPii.exit
callq rand
movl %eax, %edi
callq srand
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_3: # %.lr.ph.i72
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%r14,%r12,4)
incq %r12
cmpq $1048576, %r12 # imm = 0x100000
jne .LBB4_3
# %bb.4: # %_Z13m_fill_randomPii.exit76
xorl %r13d, %r13d
callq clock
movq %rax, %r12
movq %rbx, %rax
.p2align 4, 0x90
.LBB4_5: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_6 Depth 2
# Child Loop BB4_7 Depth 3
movq %r13, %rcx
shlq $12, %rcx
addq %r15, %rcx
movq %r14, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB4_6: # %.lr.ph.i77
# Parent Loop BB4_5 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_7 Depth 3
movl $0, (%rcx,%rsi,4)
xorl %edi, %edi
movq %rdx, %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB4_7: # Parent Loop BB4_5 Depth=1
# Parent Loop BB4_6 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r8), %r10d
imull (%rax,%rdi,4), %r10d
addl %r10d, %r9d
incq %rdi
addq $4096, %r8 # imm = 0x1000
cmpq $1024, %rdi # imm = 0x400
jne .LBB4_7
# %bb.8: # %._crit_edge.i
# in Loop: Header=BB4_6 Depth=2
movl %r9d, (%rcx,%rsi,4)
incq %rsi
addq $4, %rdx
cmpq $1024, %rsi # imm = 0x400
jne .LBB4_6
# %bb.9: # %._crit_edge30.i
# in Loop: Header=BB4_5 Depth=1
incq %r13
addq $4096, %rax # imm = 0x1000
cmpq $1024, %r13 # imm = 0x400
jne .LBB4_5
# %bb.10: # %_Z6mm_cpuPiS_S_i.exit
callq clock
subq %r12, %rax
cvtsi2ss %rax, %xmm0
divss .LCPI4_0(%rip), %xmm0
mulss .LCPI4_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
leaq 216(%rsp), %r12
movq %r12, %rdi
movl $1, %esi
callq hipGetDevicePropertiesR0600
movl $1, %edi
callq hipSetDevice
callq clock
movq %rax, %r13
movabsq $4398046512128, %rbp # imm = 0x40000000400
movq %rbp, 144(%rsp)
movq %rbx, 160(%rsp)
movq %rbp, 120(%rsp)
movq %r14, 136(%rsp)
movq %rbp, 192(%rsp)
movq %r15, 208(%rsp)
movq %r15, 64(%rsp)
movups 192(%rsp), %xmm0
movups %xmm0, 48(%rsp)
movq 136(%rsp), %rax
movq %rax, 40(%rsp)
movups 120(%rsp), %xmm0
movups %xmm0, 24(%rsp)
movq 160(%rsp), %rax
movq %rax, 16(%rsp)
movups 144(%rsp), %xmm0
movups %xmm0, (%rsp)
movl $1, %edi
callq _Z8MatMul_g6MatrixS_S_i
callq clock
subq %r13, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
divss .LCPI4_0(%rip), %xmm0
mulss .LCPI4_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movq %r12, %rsi
movb $1, %al
callq printf
callq clock
movq %rax, %r13
movq %rbp, 96(%rsp)
movq %rbx, 112(%rsp)
movq %rbp, 72(%rsp)
movq %r14, 88(%rsp)
movq %rbp, 168(%rsp)
movq %r15, 184(%rsp)
movq %r15, 64(%rsp)
movups 168(%rsp), %xmm0
movups %xmm0, 48(%rsp)
movq 88(%rsp), %rax
movq %rax, 40(%rsp)
movups 72(%rsp), %xmm0
movups %xmm0, 24(%rsp)
movq 112(%rsp), %rax
movq %rax, 16(%rsp)
movups 96(%rsp), %xmm0
movups %xmm0, (%rsp)
movl $1, %edi
callq _Z8MatMul_s6MatrixS_S_i
callq clock
subq %r13, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
divss .LCPI4_0(%rip), %xmm0
mulss .LCPI4_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movq %r12, %rsi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $1688, %rsp # imm = 0x698
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.globl _Z8MatMul_g6MatrixS_S_i # -- Begin function _Z8MatMul_g6MatrixS_S_i
.p2align 4, 0x90
.type _Z8MatMul_g6MatrixS_S_i,@function
_Z8MatMul_g6MatrixS_S_i: # @_Z8MatMul_g6MatrixS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $248, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 336(%rsp), %r15
movl 288(%rsp), %eax
movl 292(%rsp), %r14d
movl %eax, 56(%rsp)
movl %r14d, 60(%rsp)
imull %r14d, %eax
movslq %eax, %rbx
shlq $2, %rbx
callq hipSetDevice
leaq 72(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 72(%rsp), %rdi
movq 304(%rsp), %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl 312(%rsp), %r12d
movl 316(%rsp), %eax
movl %r12d, 32(%rsp)
movl %eax, 36(%rsp)
imull %r12d, %eax
movslq %eax, %rbx
shlq $2, %rbx
leaq 48(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 48(%rsp), %rdi
movq 328(%rsp), %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl 336(%rsp), %eax
movl 340(%rsp), %ecx
movl %eax, 8(%rsp)
movl %ecx, 12(%rsp)
imull %eax, %ecx
movslq %ecx, %rbx
shlq $2, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
shrl $4, %r12d
shrl $4, %r14d
shlq $32, %r14
orq %r12, %r14
movabsq $68719476752, %rdx # imm = 0x1000000010
movq %r14, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq 72(%rsp), %rax
movq %rax, 176(%rsp)
movups 56(%rsp), %xmm0
movaps %xmm0, 160(%rsp)
movq 48(%rsp), %rax
movq %rax, 208(%rsp)
movups 32(%rsp), %xmm0
movaps %xmm0, 192(%rsp)
movq 24(%rsp), %rax
movq %rax, 240(%rsp)
movups 8(%rsp), %xmm0
movaps %xmm0, 224(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 192(%rsp), %rax
movq %rax, 136(%rsp)
leaq 224(%rsp), %rax
movq %rax, 144(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z14MatMulKernel_g6MatrixS_S_, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
movq 16(%r15), %rdi
movq 24(%rsp), %rsi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 72(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
addq $248, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z8MatMul_g6MatrixS_S_i, .Lfunc_end5-_Z8MatMul_g6MatrixS_S_i
.cfi_endproc
# -- End function
.globl _Z8MatMul_s6MatrixS_S_i # -- Begin function _Z8MatMul_s6MatrixS_S_i
.p2align 4, 0x90
.type _Z8MatMul_s6MatrixS_S_i,@function
_Z8MatMul_s6MatrixS_S_i: # @_Z8MatMul_s6MatrixS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $248, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 336(%rsp), %r15
movl 288(%rsp), %eax
movl 292(%rsp), %r14d
movl %eax, 56(%rsp)
movl %r14d, 60(%rsp)
imull %r14d, %eax
movslq %eax, %rbx
shlq $2, %rbx
callq hipSetDevice
leaq 72(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 72(%rsp), %rdi
movq 304(%rsp), %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl 312(%rsp), %r12d
movl 316(%rsp), %eax
movl %r12d, 32(%rsp)
movl %eax, 36(%rsp)
imull %r12d, %eax
movslq %eax, %rbx
shlq $2, %rbx
leaq 48(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 48(%rsp), %rdi
movq 328(%rsp), %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl 336(%rsp), %eax
movl 340(%rsp), %ecx
movl %eax, 8(%rsp)
movl %ecx, 12(%rsp)
imull %eax, %ecx
movslq %ecx, %rbx
shlq $2, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
shrl $4, %r12d
shrl $4, %r14d
shlq $32, %r14
orq %r12, %r14
movabsq $68719476752, %rdx # imm = 0x1000000010
movq %r14, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_2
# %bb.1:
movq 72(%rsp), %rax
movq %rax, 176(%rsp)
movups 56(%rsp), %xmm0
movaps %xmm0, 160(%rsp)
movq 48(%rsp), %rax
movq %rax, 208(%rsp)
movups 32(%rsp), %xmm0
movaps %xmm0, 192(%rsp)
movq 24(%rsp), %rax
movq %rax, 240(%rsp)
movups 8(%rsp), %xmm0
movaps %xmm0, 224(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 192(%rsp), %rax
movq %rax, 136(%rsp)
leaq 224(%rsp), %rax
movq %rax, 144(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z14MatMulKernel_s6MatrixS_S_, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_2:
movq 16(%r15), %rdi
movq 24(%rsp), %rsi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 72(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
addq $248, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z8MatMul_s6MatrixS_S_i, .Lfunc_end6-_Z8MatMul_s6MatrixS_S_i
.cfi_endproc
# -- End function
.globl _Z29__device_stub__MatMulKernel_g6MatrixS_S_ # -- Begin function _Z29__device_stub__MatMulKernel_g6MatrixS_S_
.p2align 4, 0x90
.type _Z29__device_stub__MatMulKernel_g6MatrixS_S_,@function
_Z29__device_stub__MatMulKernel_g6MatrixS_S_: # @_Z29__device_stub__MatMulKernel_g6MatrixS_S_
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
leaq 80(%rsp), %rax
movq %rax, 48(%rsp)
leaq 104(%rsp), %rax
movq %rax, 56(%rsp)
leaq 128(%rsp), %rax
movq %rax, 64(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z14MatMulKernel_g6MatrixS_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end7:
.size _Z29__device_stub__MatMulKernel_g6MatrixS_S_, .Lfunc_end7-_Z29__device_stub__MatMulKernel_g6MatrixS_S_
.cfi_endproc
# -- End function
.globl _Z29__device_stub__MatMulKernel_s6MatrixS_S_ # -- Begin function _Z29__device_stub__MatMulKernel_s6MatrixS_S_
.p2align 4, 0x90
.type _Z29__device_stub__MatMulKernel_s6MatrixS_S_,@function
_Z29__device_stub__MatMulKernel_s6MatrixS_S_: # @_Z29__device_stub__MatMulKernel_s6MatrixS_S_
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
leaq 80(%rsp), %rax
movq %rax, 48(%rsp)
leaq 104(%rsp), %rax
movq %rax, 56(%rsp)
leaq 128(%rsp), %rax
movq %rax, 64(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z14MatMulKernel_s6MatrixS_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end8:
.size _Z29__device_stub__MatMulKernel_s6MatrixS_S_, .Lfunc_end8-_Z29__device_stub__MatMulKernel_s6MatrixS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB9_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB9_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14MatMulKernel_g6MatrixS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14MatMulKernel_s6MatrixS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end9:
.size __hip_module_ctor, .Lfunc_end9-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB10_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB10_2:
retq
.Lfunc_end10:
.size __hip_module_dtor, .Lfunc_end10-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "======= Matriz %dx%d =======\n"
.size .L.str.4, 30
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "CPU = %10.1fms \n"
.size .L.str.5, 19
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "GPU_GLOBAL - %s = %10.1fms \n"
.size .L.str.6, 29
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "GPU_SHARED - %s = %10.1fms \n"
.size .L.str.7, 29
.type _Z14MatMulKernel_g6MatrixS_S_,@object # @_Z14MatMulKernel_g6MatrixS_S_
.section .rodata,"a",@progbits
.globl _Z14MatMulKernel_g6MatrixS_S_
.p2align 3, 0x0
_Z14MatMulKernel_g6MatrixS_S_:
.quad _Z29__device_stub__MatMulKernel_g6MatrixS_S_
.size _Z14MatMulKernel_g6MatrixS_S_, 8
.type _Z14MatMulKernel_s6MatrixS_S_,@object # @_Z14MatMulKernel_s6MatrixS_S_
.globl _Z14MatMulKernel_s6MatrixS_S_
.p2align 3, 0x0
_Z14MatMulKernel_s6MatrixS_S_:
.quad _Z29__device_stub__MatMulKernel_s6MatrixS_S_
.size _Z14MatMulKernel_s6MatrixS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14MatMulKernel_g6MatrixS_S_"
.size .L__unnamed_1, 30
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z14MatMulKernel_s6MatrixS_S_"
.size .L__unnamed_2, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n"
.size .Lstr, 2
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n "
.size .Lstr.1, 3
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__MatMulKernel_g6MatrixS_S_
.addrsig_sym _Z29__device_stub__MatMulKernel_s6MatrixS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14MatMulKernel_g6MatrixS_S_
.addrsig_sym _Z14MatMulKernel_s6MatrixS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
int main(int argc, char *argv[]){
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, 0);
printf(" Device: \"%s\"\n", deviceProp.name);
printf(" Compute Capability: %d.%d\n", deviceProp.major, deviceProp.minor);
printf(" Multiprocessors count: %d\n", deviceProp.multiProcessorCount);
printf(" Total amount of shared memory per block: %lu bytes\n", deviceProp.sharedMemPerBlock);
printf(" Total number of registers available per block: %d\n", deviceProp.regsPerBlock);
printf(" Maximum number of threads per multiprocessor: %d\n", deviceProp.maxThreadsPerMultiProcessor);
printf(" Maximum number of threads per block: %d\n", deviceProp.maxThreadsPerBlock);
printf(" Warp size: %d\n", deviceProp.warpSize);
printf(" Max dimension size of a thread block (x,y,z): (%d, %d, %d)\n",
deviceProp.maxThreadsDim[0],
deviceProp.maxThreadsDim[1],
deviceProp.maxThreadsDim[2]);
printf(" Max dimension size of a grid size (x,y,z): (%d, %d, %d)\n",
deviceProp.maxGridSize[0],
deviceProp.maxGridSize[1],
deviceProp.maxGridSize[2]);
printf(" Total global mem: %0.f MBytes\n", deviceProp.totalGlobalMem/1048576.0f);
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
int main(int argc, char *argv[]){
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, 0);
printf(" Device: \"%s\"\n", deviceProp.name);
printf(" Compute Capability: %d.%d\n", deviceProp.major, deviceProp.minor);
printf(" Multiprocessors count: %d\n", deviceProp.multiProcessorCount);
printf(" Total amount of shared memory per block: %lu bytes\n", deviceProp.sharedMemPerBlock);
printf(" Total number of registers available per block: %d\n", deviceProp.regsPerBlock);
printf(" Maximum number of threads per multiprocessor: %d\n", deviceProp.maxThreadsPerMultiProcessor);
printf(" Maximum number of threads per block: %d\n", deviceProp.maxThreadsPerBlock);
printf(" Warp size: %d\n", deviceProp.warpSize);
printf(" Max dimension size of a thread block (x,y,z): (%d, %d, %d)\n",
deviceProp.maxThreadsDim[0],
deviceProp.maxThreadsDim[1],
deviceProp.maxThreadsDim[2]);
printf(" Max dimension size of a grid size (x,y,z): (%d, %d, %d)\n",
deviceProp.maxGridSize[0],
deviceProp.maxGridSize[1],
deviceProp.maxGridSize[2]);
printf(" Total global mem: %0.f MBytes\n", deviceProp.totalGlobalMem/1048576.0f);
return 0;
} | .file "tmpxft_001a69ad_00000000-6_device.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string " Device: \"%s\"\n"
.align 8
.LC1:
.string " Compute Capability: %d.%d\n"
.align 8
.LC2:
.string " Multiprocessors count: %d\n"
.align 8
.LC3:
.string " Total amount of shared memory per block: %lu bytes\n"
.align 8
.LC4:
.string " Total number of registers available per block: %d\n"
.align 8
.LC5:
.string " Maximum number of threads per multiprocessor: %d\n"
.align 8
.LC6:
.string " Maximum number of threads per block: %d\n"
.align 8
.LC7:
.string " Warp size: %d\n"
.align 8
.LC8:
.string " Max dimension size of a thread block (x,y,z): (%d, %d, %d)\n"
.align 8
.LC9:
.string " Max dimension size of a grid size (x,y,z): (%d, %d, %d)\n"
.align 8
.LC11:
.string " Total global mem: %0.f MBytes\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1040, %rsp
.cfi_def_cfa_offset 1056
movq %fs:40, %rax
movq %rax, 1032(%rsp)
xorl %eax, %eax
movq %rsp, %rbx
movl $0, %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 364(%rsp), %ecx
movl 360(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 388(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 296(%rsp), %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 304(%rsp), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 624(%rsp), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 320(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 308(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 332(%rsp), %r8d
movl 328(%rsp), %ecx
movl 324(%rsp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 344(%rsp), %r8d
movl 340(%rsp), %ecx
movl 336(%rsp), %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 288(%rsp), %rax
testq %rax, %rax
js .L4
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
.L5:
mulss .LC10(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L8
movl $0, %eax
addq $1040, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L4:
.cfi_restore_state
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
addss %xmm0, %xmm0
jmp .L5
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC10:
.long 897581056
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
int main(int argc, char *argv[]){
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, 0);
printf(" Device: \"%s\"\n", deviceProp.name);
printf(" Compute Capability: %d.%d\n", deviceProp.major, deviceProp.minor);
printf(" Multiprocessors count: %d\n", deviceProp.multiProcessorCount);
printf(" Total amount of shared memory per block: %lu bytes\n", deviceProp.sharedMemPerBlock);
printf(" Total number of registers available per block: %d\n", deviceProp.regsPerBlock);
printf(" Maximum number of threads per multiprocessor: %d\n", deviceProp.maxThreadsPerMultiProcessor);
printf(" Maximum number of threads per block: %d\n", deviceProp.maxThreadsPerBlock);
printf(" Warp size: %d\n", deviceProp.warpSize);
printf(" Max dimension size of a thread block (x,y,z): (%d, %d, %d)\n",
deviceProp.maxThreadsDim[0],
deviceProp.maxThreadsDim[1],
deviceProp.maxThreadsDim[2]);
printf(" Max dimension size of a grid size (x,y,z): (%d, %d, %d)\n",
deviceProp.maxGridSize[0],
deviceProp.maxGridSize[1],
deviceProp.maxGridSize[2]);
printf(" Total global mem: %0.f MBytes\n", deviceProp.totalGlobalMem/1048576.0f);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
int main(int argc, char *argv[]){
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, 0);
printf(" Device: \"%s\"\n", deviceProp.name);
printf(" Compute Capability: %d.%d\n", deviceProp.major, deviceProp.minor);
printf(" Multiprocessors count: %d\n", deviceProp.multiProcessorCount);
printf(" Total amount of shared memory per block: %lu bytes\n", deviceProp.sharedMemPerBlock);
printf(" Total number of registers available per block: %d\n", deviceProp.regsPerBlock);
printf(" Maximum number of threads per multiprocessor: %d\n", deviceProp.maxThreadsPerMultiProcessor);
printf(" Maximum number of threads per block: %d\n", deviceProp.maxThreadsPerBlock);
printf(" Warp size: %d\n", deviceProp.warpSize);
printf(" Max dimension size of a thread block (x,y,z): (%d, %d, %d)\n",
deviceProp.maxThreadsDim[0],
deviceProp.maxThreadsDim[1],
deviceProp.maxThreadsDim[2]);
printf(" Max dimension size of a grid size (x,y,z): (%d, %d, %d)\n",
deviceProp.maxGridSize[0],
deviceProp.maxGridSize[1],
deviceProp.maxGridSize[2]);
printf(" Total global mem: %0.f MBytes\n", deviceProp.totalGlobalMem/1048576.0f);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
int main(int argc, char *argv[]){
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, 0);
printf(" Device: \"%s\"\n", deviceProp.name);
printf(" Compute Capability: %d.%d\n", deviceProp.major, deviceProp.minor);
printf(" Multiprocessors count: %d\n", deviceProp.multiProcessorCount);
printf(" Total amount of shared memory per block: %lu bytes\n", deviceProp.sharedMemPerBlock);
printf(" Total number of registers available per block: %d\n", deviceProp.regsPerBlock);
printf(" Maximum number of threads per multiprocessor: %d\n", deviceProp.maxThreadsPerMultiProcessor);
printf(" Maximum number of threads per block: %d\n", deviceProp.maxThreadsPerBlock);
printf(" Warp size: %d\n", deviceProp.warpSize);
printf(" Max dimension size of a thread block (x,y,z): (%d, %d, %d)\n",
deviceProp.maxThreadsDim[0],
deviceProp.maxThreadsDim[1],
deviceProp.maxThreadsDim[2]);
printf(" Max dimension size of a grid size (x,y,z): (%d, %d, %d)\n",
deviceProp.maxGridSize[0],
deviceProp.maxGridSize[1],
deviceProp.maxGridSize[2]);
printf(" Total global mem: %0.f MBytes\n", deviceProp.totalGlobalMem/1048576.0f);
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
int main(int argc, char *argv[]){
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, 0);
printf(" Device: \"%s\"\n", deviceProp.name);
printf(" Compute Capability: %d.%d\n", deviceProp.major, deviceProp.minor);
printf(" Multiprocessors count: %d\n", deviceProp.multiProcessorCount);
printf(" Total amount of shared memory per block: %lu bytes\n", deviceProp.sharedMemPerBlock);
printf(" Total number of registers available per block: %d\n", deviceProp.regsPerBlock);
printf(" Maximum number of threads per multiprocessor: %d\n", deviceProp.maxThreadsPerMultiProcessor);
printf(" Maximum number of threads per block: %d\n", deviceProp.maxThreadsPerBlock);
printf(" Warp size: %d\n", deviceProp.warpSize);
printf(" Max dimension size of a thread block (x,y,z): (%d, %d, %d)\n",
deviceProp.maxThreadsDim[0],
deviceProp.maxThreadsDim[1],
deviceProp.maxThreadsDim[2]);
printf(" Max dimension size of a grid size (x,y,z): (%d, %d, %d)\n",
deviceProp.maxGridSize[0],
deviceProp.maxGridSize[1],
deviceProp.maxGridSize[2]);
printf(" Total global mem: %0.f MBytes\n", deviceProp.totalGlobalMem/1048576.0f);
return 0;
} | .text
.file "device.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x35800000 # float 9.53674316E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1472, %rsp # imm = 0x5C0
.cfi_def_cfa_offset 1488
.cfi_offset %rbx, -16
movq %rsp, %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 360(%rsp), %esi
movl 364(%rsp), %edx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl 388(%rsp), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movq 296(%rsp), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl 304(%rsp), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl 624(%rsp), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 320(%rsp), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl 308(%rsp), %esi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl 324(%rsp), %esi
movl 328(%rsp), %edx
movl 332(%rsp), %ecx
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movl 336(%rsp), %esi
movl 340(%rsp), %edx
movl 344(%rsp), %ecx
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movq 288(%rsp), %rax
testq %rax, %rax
js .LBB0_1
# %bb.2:
cvtsi2ss %rax, %xmm0
jmp .LBB0_3
.LBB0_1:
movq %rax, %rcx
shrq %rcx
andl $1, %eax
orq %rcx, %rax
cvtsi2ss %rax, %xmm0
addss %xmm0, %xmm0
.LBB0_3:
mulss .LCPI0_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.10, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $1472, %rsp # imm = 0x5C0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " Device: \"%s\"\n"
.size .L.str, 55
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " Compute Capability: %d.%d\n"
.size .L.str.1, 56
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " Multiprocessors count: %d\n"
.size .L.str.2, 53
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " Total amount of shared memory per block: %lu bytes\n"
.size .L.str.3, 60
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " Total number of registers available per block: %d\n"
.size .L.str.4, 53
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " Maximum number of threads per multiprocessor: %d\n"
.size .L.str.5, 53
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " Maximum number of threads per block: %d\n"
.size .L.str.6, 53
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " Warp size: %d\n"
.size .L.str.7, 53
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz " Max dimension size of a thread block (x,y,z): (%d, %d, %d)\n"
.size .L.str.8, 63
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " Max dimension size of a grid size (x,y,z): (%d, %d, %d)\n"
.size .L.str.9, 63
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz " Total global mem: %0.f MBytes\n"
.size .L.str.10, 62
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a69ad_00000000-6_device.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string " Device: \"%s\"\n"
.align 8
.LC1:
.string " Compute Capability: %d.%d\n"
.align 8
.LC2:
.string " Multiprocessors count: %d\n"
.align 8
.LC3:
.string " Total amount of shared memory per block: %lu bytes\n"
.align 8
.LC4:
.string " Total number of registers available per block: %d\n"
.align 8
.LC5:
.string " Maximum number of threads per multiprocessor: %d\n"
.align 8
.LC6:
.string " Maximum number of threads per block: %d\n"
.align 8
.LC7:
.string " Warp size: %d\n"
.align 8
.LC8:
.string " Max dimension size of a thread block (x,y,z): (%d, %d, %d)\n"
.align 8
.LC9:
.string " Max dimension size of a grid size (x,y,z): (%d, %d, %d)\n"
.align 8
.LC11:
.string " Total global mem: %0.f MBytes\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1040, %rsp
.cfi_def_cfa_offset 1056
movq %fs:40, %rax
movq %rax, 1032(%rsp)
xorl %eax, %eax
movq %rsp, %rbx
movl $0, %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 364(%rsp), %ecx
movl 360(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 388(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 296(%rsp), %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 304(%rsp), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 624(%rsp), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 320(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 308(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 332(%rsp), %r8d
movl 328(%rsp), %ecx
movl 324(%rsp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 344(%rsp), %r8d
movl 340(%rsp), %ecx
movl 336(%rsp), %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 288(%rsp), %rax
testq %rax, %rax
js .L4
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
.L5:
mulss .LC10(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L8
movl $0, %eax
addq $1040, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L4:
.cfi_restore_state
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
addss %xmm0, %xmm0
jmp .L5
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC10:
.long 897581056
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "device.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x35800000 # float 9.53674316E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1472, %rsp # imm = 0x5C0
.cfi_def_cfa_offset 1488
.cfi_offset %rbx, -16
movq %rsp, %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 360(%rsp), %esi
movl 364(%rsp), %edx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl 388(%rsp), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movq 296(%rsp), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl 304(%rsp), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl 624(%rsp), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 320(%rsp), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl 308(%rsp), %esi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl 324(%rsp), %esi
movl 328(%rsp), %edx
movl 332(%rsp), %ecx
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movl 336(%rsp), %esi
movl 340(%rsp), %edx
movl 344(%rsp), %ecx
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movq 288(%rsp), %rax
testq %rax, %rax
js .LBB0_1
# %bb.2:
cvtsi2ss %rax, %xmm0
jmp .LBB0_3
.LBB0_1:
movq %rax, %rcx
shrq %rcx
andl $1, %eax
orq %rcx, %rax
cvtsi2ss %rax, %xmm0
addss %xmm0, %xmm0
.LBB0_3:
mulss .LCPI0_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.10, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $1472, %rsp # imm = 0x5C0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " Device: \"%s\"\n"
.size .L.str, 55
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " Compute Capability: %d.%d\n"
.size .L.str.1, 56
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " Multiprocessors count: %d\n"
.size .L.str.2, 53
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " Total amount of shared memory per block: %lu bytes\n"
.size .L.str.3, 60
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " Total number of registers available per block: %d\n"
.size .L.str.4, 53
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " Maximum number of threads per multiprocessor: %d\n"
.size .L.str.5, 53
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " Maximum number of threads per block: %d\n"
.size .L.str.6, 53
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " Warp size: %d\n"
.size .L.str.7, 53
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz " Max dimension size of a thread block (x,y,z): (%d, %d, %d)\n"
.size .L.str.8, 63
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " Max dimension size of a grid size (x,y,z): (%d, %d, %d)\n"
.size .L.str.9, 63
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz " Total global mem: %0.f MBytes\n"
.size .L.str.10, 62
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#define GIGABYTE 1000000000
struct entry
{
int origIndex;
float xValue, yValue;
};//entry
int h_binarySearchLB(entry * data, float val, int n)
{
//return index of greatest leftmost xValue that is greater than val
int left = 0;
int right = n;
int mid;
while (left != right)
{
mid = (left+right)/2;
if (data[mid].xValue <= val)
left = mid + 1;
else
right = mid;
}//while
return left;
}//binarySearchLB
int h_binarySearchUB(entry * data, float val, int n)
{
//return index of greatest leftmost xValue that is greater than val
int left = 0;
int right = n;
int mid;
while (left != right)
{
mid = (left+right)/2;
if (data[mid].xValue >= val)
right = mid;
else
left = mid + 1;
}//while
return left;
}//binarySearchUB
__device__ int binarySearchLB(entry * data, float val, int n)//val is x val +/- tuning parameter
{
//return index of greatest leftmost xValue that is greater than val
int left = 0;
int right = n;
int mid;
while (left != right)
{
mid = (left+right)/2;
if (data[mid].xValue <= val)
left = mid + 1;
else
right = mid;
}//while
return left;
}//binarySearchLB
__device__ int binarySearchUB(entry * data, float val, int n)
{
//return index of greatest leftmost xValue that is greater than val
int left = 0;
int right = n;
int mid;
while (left != right)
{
mid = (left+right)/2;
if (data[mid].xValue >= val)
right = mid;
else
left = mid + 1;
}//while
return left;
}//binarySearchUB
__global__ void kernel1(entry * array, int n, float h)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int lowerBound = binarySearchLB(array, array[idx].xValue-h, n);//binsearchlb device func
int upperBound = binarySearchUB(array, array[idx].xValue+h, n);//ub is device func
float avg = 0;
//calculate y average
for (int i=lowerBound; i<upperBound; i++)
avg += array[i].yValue;
avg = avg/((float) (upperBound-lowerBound));
//yValue stores the avg
array[idx].yValue = avg;
}//kernel1
__global__ void kernel2(entry * array, int n)
{
float avg = 0;
for (int i=0; i<n; i++)
avg += array[i].yValue;
avg = avg / (float) n;
array[0].yValue = avg;
}//kernel2
void merge(entry * a, int low, int high)
{
int pivot = (low+high)/2;
int i = 0;
int j = low;
int k = pivot+1;
entry * temp = new entry[high-low+1];
while ((j <= pivot) && (k <= high))
{
if (a[j].xValue < a[k].xValue)
temp[i++] = a[j++];
else
temp[i++] = a[k++];
}//while
while (j <= pivot)
temp[i++] = a[j++];
while (k <= high)
temp[i++] = a[k++];
for (int h=low; h<= high; h++)
a[h] = temp[h-low];
delete [] temp;
}//merge
void mergeSort(entry * a, int low, int high)
{
int pivot;
if (low < high)
{
pivot = (low+high)/2;
mergeSort(a, low, pivot);
mergeSort(a, pivot+1, high);
merge(a, low, high);
}//if
}//mergeSort
void smoothc(float * x, float * y, float * m, int n, float h)
{
entry * array = new entry[n];
entry * deviceArray;
int * countArray = new int[n];// should not be there, mem leak
int blockSize = 1024;//num thread per block
//creat array of structs
for (int i=0; i<n; i++)
{
entry temp;
temp.origIndex = i;
temp.xValue = x[i];
temp.yValue = y[i];
array[i] = temp;
}//for
//sort by xValue
mergeSort(array, 0, n-1);
if (n < GIGABYTE/sizeof(entry))// if fits into 1 gig of mem hard code in line 5
{
//put array onto device array
cudaMalloc(&deviceArray, sizeof(entry) * n);
cudaMemcpy(deviceArray, array, sizeof(entry) * n, cudaMemcpyHostToDevice);
dim3 dimBlock(blockSize);
dim3 dimGrid(ceil(n/blockSize));
//stores smoothed average in yValue
kernel1 <<< dimGrid, dimBlock >>> (deviceArray, n, h);//send to line 96
cudaMemcpy(array, deviceArray, sizeof(entry) * n, cudaMemcpyDeviceToHost);
//rearrange array in original order
for (int i=0; i<n; i++)
m[array[i].origIndex] = array[i].yValue;
cudaFree(deviceArray);
}//if
else //have to chunk up data
{
int lb, ub;
for (int i=0; i<n; i++)
{
lb = h_binarySearchLB(array, array[i].xValue-h, n);
ub = h_binarySearchUB(array, array[i].xValue+h, n);
entry * chunkArray = new entry[ub-lb];
for (int j=0; j<ub-lb; j++)
chunkArray[j] = array[lb+j];
cudaMalloc(&deviceArray, sizeof(entry) * (ub-lb));
cudaMemcpy(deviceArray, chunkArray, sizeof(entry) * (ub-lb), cudaMemcpyHostToDevice);
kernel2 <<< 1, 1 >>> (deviceArray, ub-lb);
cudaMemcpy(chunkArray, deviceArray, sizeof(entry) * (ub-lb), cudaMemcpyDeviceToHost);
m[array[i].origIndex] = chunkArray[0].yValue;//store y avg
cudaFree(deviceArray);
delete [] chunkArray;
}//for
}//else
delete [] array;
}//smoothc
/*
int main()
{
int n = 200;
float * x = new float[n];
float * y = new float[n];
float * m = new float[n];
float h = 2;
for (int i=0; i<n; i++)
{
x[i] = rand() % 100;
y[i] = rand() % 100;
}//for
float x[20] = {1, 1,2,2, 3,3, 4,4, 5,5, 6,6, 7,7, 8,8, 9,9, 10,10};
float y[20] = {11,11, 12,12, 13,13, 14,14, 15,15, 16,16, 17,17, 18,18, 19,19, 20,20};
float m[20];
int n = 20;
float h = 2;
smoothc(x, y, m, n, h);
// delete [] x;
// delete [] y;
// delete [] m;
}//main
*/ | .file "tmpxft_0005e66d_00000000-6_SmoothC.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z16h_binarySearchLBP5entryfi
.type _Z16h_binarySearchLBP5entryfi, @function
_Z16h_binarySearchLBP5entryfi:
.LFB2057:
.cfi_startproc
endbr64
movl $0, %ecx
.L5:
cmpl %ecx, %esi
je .L11
leal (%rsi,%rcx), %edx
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
movslq %eax, %rdx
leaq (%rdx,%rdx,2), %rdx
comiss 4(%rdi,%rdx,4), %xmm0
jnb .L12
movl %eax, %esi
jmp .L5
.L12:
leal 1(%rax), %ecx
jmp .L5
.L11:
movl %ecx, %eax
ret
.cfi_endproc
.LFE2057:
.size _Z16h_binarySearchLBP5entryfi, .-_Z16h_binarySearchLBP5entryfi
.globl _Z16h_binarySearchUBP5entryfi
.type _Z16h_binarySearchUBP5entryfi, @function
_Z16h_binarySearchUBP5entryfi:
.LFB2058:
.cfi_startproc
endbr64
movl $0, %ecx
.L15:
cmpl %ecx, %esi
je .L18
leal (%rsi,%rcx), %edx
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
movslq %eax, %rdx
leaq (%rdx,%rdx,2), %rdx
movss 4(%rdi,%rdx,4), %xmm1
comiss %xmm0, %xmm1
jb .L19
movl %eax, %esi
jmp .L15
.L19:
leal 1(%rax), %ecx
jmp .L15
.L18:
movl %ecx, %eax
ret
.cfi_endproc
.LFE2058:
.size _Z16h_binarySearchUBP5entryfi, .-_Z16h_binarySearchUBP5entryfi
.globl _Z14binarySearchLBP5entryfi
.type _Z14binarySearchLBP5entryfi, @function
_Z14binarySearchLBP5entryfi:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z14binarySearchLBP5entryfi, .-_Z14binarySearchLBP5entryfi
.globl _Z14binarySearchUBP5entryfi
.type _Z14binarySearchUBP5entryfi, @function
_Z14binarySearchUBP5entryfi:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z14binarySearchUBP5entryfi, .-_Z14binarySearchUBP5entryfi
.globl _Z5mergeP5entryii
.type _Z5mergeP5entryii, @function
_Z5mergeP5entryii:
.LFB2061:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl %edx, %r12d
leal (%rsi,%rdx), %eax
movl %eax, %r14d
shrl $31, %r14d
addl %eax, %r14d
sarl %r14d
movl %edx, %eax
subl %esi, %eax
addl $1, %eax
cltq
movabsq $768614336404564650, %rdx
cmpq %rax, %rdx
jb .L25
movq %rdi, %rbp
movl %esi, %r13d
leal 1(%r14), %ebx
leaq (%rax,%rax,2), %rdi
salq $2, %rdi
call _Znam@PLT
movq %rax, %rdi
cmpl %r14d, %r13d
jg .L40
movl %r13d, %edx
movl $1, %ecx
cmpl %ebx, %r12d
jge .L32
.L40:
movl %r13d, %edx
movl $0, %r9d
.L28:
cmpl %edx, %r14d
jl .L34
movl %edx, %r10d
movl %r14d, %eax
subl %edx, %eax
leaq 3(%rax,%rax,2), %r8
salq $2, %r8
movslq %edx, %rdx
leaq (%rdx,%rdx,2), %rax
leaq 0(%rbp,%rax,4), %rcx
movslq %r9d, %rax
leaq (%rax,%rax,2), %rax
leaq (%rdi,%rax,4), %rdx
movl $0, %eax
.L35:
movq (%rcx,%rax), %rsi
movq %rsi, (%rdx,%rax)
movl 8(%rcx,%rax), %esi
movl %esi, 8(%rdx,%rax)
addq $12, %rax
cmpq %r8, %rax
jne .L35
leal 1(%r9,%r14), %r9d
subl %r10d, %r9d
.L34:
cmpl %ebx, %r12d
jl .L36
movl %r12d, %eax
subl %ebx, %eax
leaq 3(%rax,%rax,2), %r8
salq $2, %r8
movslq %ebx, %rbx
leaq (%rbx,%rbx,2), %rax
leaq 0(%rbp,%rax,4), %rcx
movslq %r9d, %r9
leaq (%r9,%r9,2), %rax
leaq (%rdi,%rax,4), %rdx
movl $0, %eax
.L37:
movq (%rcx,%rax), %rsi
movq %rsi, (%rdx,%rax)
movl 8(%rcx,%rax), %esi
movl %esi, 8(%rdx,%rax)
addq $12, %rax
cmpq %r8, %rax
jne .L37
.L36:
cmpl %r12d, %r13d
jg .L38
subl %r13d, %r12d
leaq 3(%r12,%r12,2), %rsi
salq $2, %rsi
movslq %r13d, %r13
leaq 0(%r13,%r13,2), %rax
leaq 0(%rbp,%rax,4), %rdx
movl $0, %eax
.L39:
movq (%rdi,%rax), %rcx
movq %rcx, (%rdx,%rax)
movl 8(%rdi,%rax), %ecx
movl %ecx, 8(%rdx,%rax)
addq $12, %rax
cmpq %rsi, %rax
jne .L39
.L38:
call _ZdaPv@PLT
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
call __cxa_throw_bad_array_new_length@PLT
.L47:
addl $1, %ebx
movl %ecx, %r9d
movq (%rsi), %r8
movq %r8, (%rax)
movl 8(%rsi), %esi
movl %esi, 8(%rax)
.L31:
addl $1, %ecx
addq $12, %rax
cmpl %r14d, %edx
jg .L28
cmpl %r12d, %ebx
jg .L28
.L32:
movslq %edx, %rsi
leaq (%rsi,%rsi,2), %rsi
leaq 0(%rbp,%rsi,4), %r8
movslq %ebx, %rsi
leaq (%rsi,%rsi,2), %rsi
leaq 0(%rbp,%rsi,4), %rsi
movss 4(%rsi), %xmm0
comiss 4(%r8), %xmm0
jbe .L47
addl $1, %edx
movl %ecx, %r9d
movq (%r8), %rsi
movq %rsi, (%rax)
movl 8(%r8), %esi
movl %esi, 8(%rax)
jmp .L31
.cfi_endproc
.LFE2061:
.size _Z5mergeP5entryii, .-_Z5mergeP5entryii
.globl _Z9mergeSortP5entryii
.type _Z9mergeSortP5entryii, @function
_Z9mergeSortP5entryii:
.LFB2062:
.cfi_startproc
endbr64
cmpl %edx, %esi
jl .L55
ret
.L55:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r12
movl %esi, %ebx
movl %edx, %ebp
leal (%rsi,%rdx), %eax
movl %eax, %r13d
shrl $31, %r13d
addl %eax, %r13d
sarl %r13d
movl %r13d, %edx
call _Z9mergeSortP5entryii
leal 1(%r13), %esi
movl %ebp, %edx
movq %r12, %rdi
call _Z9mergeSortP5entryii
movl %ebp, %edx
movl %ebx, %esi
movq %r12, %rdi
call _Z5mergeP5entryii
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z9mergeSortP5entryii, .-_Z9mergeSortP5entryii
.globl _Z33__device_stub__Z7kernel1P5entryifP5entryif
.type _Z33__device_stub__Z7kernel1P5entryifP5entryif, @function
_Z33__device_stub__Z7kernel1P5entryifP5entryif:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movss %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L60
.L56:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L61
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7kernel1P5entryif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L56
.L61:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z33__device_stub__Z7kernel1P5entryifP5entryif, .-_Z33__device_stub__Z7kernel1P5entryifP5entryif
.globl _Z7kernel1P5entryif
.type _Z7kernel1P5entryif, @function
_Z7kernel1P5entryif:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z7kernel1P5entryifP5entryif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z7kernel1P5entryif, .-_Z7kernel1P5entryif
.globl _Z32__device_stub__Z7kernel2P5entryiP5entryi
.type _Z32__device_stub__Z7kernel2P5entryiP5entryi, @function
_Z32__device_stub__Z7kernel2P5entryiP5entryi:
.LFB2090:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L68
.L64:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L69
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L68:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7kernel2P5entryi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L64
.L69:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z32__device_stub__Z7kernel2P5entryiP5entryi, .-_Z32__device_stub__Z7kernel2P5entryiP5entryi
.globl _Z7kernel2P5entryi
.type _Z7kernel2P5entryi, @function
_Z7kernel2P5entryi:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z7kernel2P5entryiP5entryi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z7kernel2P5entryi, .-_Z7kernel2P5entryi
.globl _Z7smoothcPfS_S_if
.type _Z7smoothcPfS_S_if, @function
_Z7smoothcPfS_S_if:
.LFB2063:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdx, 24(%rsp)
movss %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movslq %ecx, %rbx
movabsq $768614336404564650, %rax
cmpq %rbx, %rax
jb .L73
movq %rdi, %rbp
movq %rsi, %r12
movl %ecx, %r14d
leaq (%rbx,%rbx,2), %rax
leaq 0(,%rax,4), %r13
movq %r13, %rdi
call _Znam@PLT
movq %rax, %r15
movq %rax, %rdx
movl $0, %eax
testl %r14d, %r14d
jle .L75
.L77:
movss 0(%rbp,%rax,4), %xmm1
movss (%r12,%rax,4), %xmm0
movl %eax, (%rdx)
movss %xmm1, 4(%rdx)
movss %xmm0, 8(%rdx)
addq $1, %rax
addq $12, %rdx
cmpq %rax, %rbx
jne .L77
.L75:
leal -1(%r14), %edx
movl $0, %esi
movq %r15, %rdi
call _Z9mergeSortP5entryii
movq %r15, %rdi
movl $0, %eax
cmpq $83333332, %rbx
jbe .L100
movq %r15, 8(%rsp)
movl %eax, %r15d
movl %r14d, 4(%rsp)
movq %rdi, %r14
jmp .L89
.L73:
movq 72(%rsp), %rax
subq %fs:40, %rax
je .L76
call __stack_chk_fail@PLT
.L76:
call __cxa_throw_bad_array_new_length@PLT
.L100:
leaq 40(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r15, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
leal 1023(%r14), %eax
testl %r14d, %r14d
cmovns %r14d, %eax
sarl $10, %eax
movl %eax, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L101
.L79:
movl $2, %ecx
movq %r13, %rdx
movq 40(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
testl %r14d, %r14d
jle .L80
movq %r15, %rax
addq %r15, %r13
movq 24(%rsp), %rcx
.L81:
movslq (%rax), %rdx
movss 8(%rax), %xmm0
movss %xmm0, (%rcx,%rdx,4)
addq $12, %rax
cmpq %rax, %r13
jne .L81
.L80:
movq 40(%rsp), %rdi
call cudaFree@PLT
jmp .L82
.L101:
movss (%rsp), %xmm0
movl %r14d, %esi
movq 40(%rsp), %rdi
call _Z33__device_stub__Z7kernel1P5entryifP5entryif
jmp .L79
.L83:
movq 72(%rsp), %rax
subq %fs:40, %rax
je .L86
call __stack_chk_fail@PLT
.L86:
call __cxa_throw_bad_array_new_length@PLT
.L88:
movl $2, %ecx
movq %rbp, %rdx
movq 40(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rax
movslq (%rax), %rax
movss 8(%rbx), %xmm0
movq 24(%rsp), %rsi
movss %xmm0, (%rsi,%rax,4)
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
addl $1, %r15d
addq $12, %r14
cmpl %r15d, 4(%rsp)
jle .L102
.L89:
movq %r14, 16(%rsp)
movl 4(%r14), %ebx
movd %ebx, %xmm0
subss (%rsp), %xmm0
movl 4(%rsp), %r13d
movl %r13d, %esi
movq 8(%rsp), %rbp
movq %rbp, %rdi
call _Z16h_binarySearchLBP5entryfi
movl %eax, %r12d
movd %ebx, %xmm0
addss (%rsp), %xmm0
movl %r13d, %esi
movq %rbp, %rdi
call _Z16h_binarySearchUBP5entryfi
subl %r12d, %eax
movl %eax, %r13d
cltq
movabsq $768614336404564650, %rsi
cmpq %rax, %rsi
jb .L83
leaq (%rax,%rax,2), %rbp
salq $2, %rbp
movq %rbp, %rdi
call _Znam@PLT
movq %rax, %rbx
testl %r13d, %r13d
jle .L85
movslq %r12d, %r12
leaq (%r12,%r12,2), %rax
movq 8(%rsp), %rsi
leaq (%rsi,%rax,4), %rdx
movl $0, %eax
.L87:
movq (%rdx,%rax), %rcx
movq %rcx, (%rbx,%rax)
movl 8(%rdx,%rax), %ecx
movl %ecx, 8(%rbx,%rax)
addq $12, %rax
cmpq %rax, %rbp
jne .L87
.L85:
leaq 40(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %rbx, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L88
movl %r13d, %esi
movq 40(%rsp), %rdi
call _Z32__device_stub__Z7kernel2P5entryiP5entryi
jmp .L88
.L102:
movq 8(%rsp), %r15
.L82:
movq %r15, %rdi
call _ZdaPv@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L103
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L103:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size _Z7smoothcPfS_S_if, .-_Z7smoothcPfS_S_if
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7kernel2P5entryi"
.LC1:
.string "_Z7kernel1P5entryif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2093:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernel2P5entryi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernel1P5entryif(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#define GIGABYTE 1000000000
struct entry
{
int origIndex;
float xValue, yValue;
};//entry
int h_binarySearchLB(entry * data, float val, int n)
{
//return index of greatest leftmost xValue that is greater than val
int left = 0;
int right = n;
int mid;
while (left != right)
{
mid = (left+right)/2;
if (data[mid].xValue <= val)
left = mid + 1;
else
right = mid;
}//while
return left;
}//binarySearchLB
int h_binarySearchUB(entry * data, float val, int n)
{
//return index of greatest leftmost xValue that is greater than val
int left = 0;
int right = n;
int mid;
while (left != right)
{
mid = (left+right)/2;
if (data[mid].xValue >= val)
right = mid;
else
left = mid + 1;
}//while
return left;
}//binarySearchUB
__device__ int binarySearchLB(entry * data, float val, int n)//val is x val +/- tuning parameter
{
//return index of greatest leftmost xValue that is greater than val
int left = 0;
int right = n;
int mid;
while (left != right)
{
mid = (left+right)/2;
if (data[mid].xValue <= val)
left = mid + 1;
else
right = mid;
}//while
return left;
}//binarySearchLB
__device__ int binarySearchUB(entry * data, float val, int n)
{
//return index of greatest leftmost xValue that is greater than val
int left = 0;
int right = n;
int mid;
while (left != right)
{
mid = (left+right)/2;
if (data[mid].xValue >= val)
right = mid;
else
left = mid + 1;
}//while
return left;
}//binarySearchUB
__global__ void kernel1(entry * array, int n, float h)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int lowerBound = binarySearchLB(array, array[idx].xValue-h, n);//binsearchlb device func
int upperBound = binarySearchUB(array, array[idx].xValue+h, n);//ub is device func
float avg = 0;
//calculate y average
for (int i=lowerBound; i<upperBound; i++)
avg += array[i].yValue;
avg = avg/((float) (upperBound-lowerBound));
//yValue stores the avg
array[idx].yValue = avg;
}//kernel1
__global__ void kernel2(entry * array, int n)
{
float avg = 0;
for (int i=0; i<n; i++)
avg += array[i].yValue;
avg = avg / (float) n;
array[0].yValue = avg;
}//kernel2
void merge(entry * a, int low, int high)
{
int pivot = (low+high)/2;
int i = 0;
int j = low;
int k = pivot+1;
entry * temp = new entry[high-low+1];
while ((j <= pivot) && (k <= high))
{
if (a[j].xValue < a[k].xValue)
temp[i++] = a[j++];
else
temp[i++] = a[k++];
}//while
while (j <= pivot)
temp[i++] = a[j++];
while (k <= high)
temp[i++] = a[k++];
for (int h=low; h<= high; h++)
a[h] = temp[h-low];
delete [] temp;
}//merge
void mergeSort(entry * a, int low, int high)
{
int pivot;
if (low < high)
{
pivot = (low+high)/2;
mergeSort(a, low, pivot);
mergeSort(a, pivot+1, high);
merge(a, low, high);
}//if
}//mergeSort
void smoothc(float * x, float * y, float * m, int n, float h)
{
entry * array = new entry[n];
entry * deviceArray;
int * countArray = new int[n];// should not be there, mem leak
int blockSize = 1024;//num thread per block
//creat array of structs
for (int i=0; i<n; i++)
{
entry temp;
temp.origIndex = i;
temp.xValue = x[i];
temp.yValue = y[i];
array[i] = temp;
}//for
//sort by xValue
mergeSort(array, 0, n-1);
if (n < GIGABYTE/sizeof(entry))// if fits into 1 gig of mem hard code in line 5
{
//put array onto device array
cudaMalloc(&deviceArray, sizeof(entry) * n);
cudaMemcpy(deviceArray, array, sizeof(entry) * n, cudaMemcpyHostToDevice);
dim3 dimBlock(blockSize);
dim3 dimGrid(ceil(n/blockSize));
//stores smoothed average in yValue
kernel1 <<< dimGrid, dimBlock >>> (deviceArray, n, h);//send to line 96
cudaMemcpy(array, deviceArray, sizeof(entry) * n, cudaMemcpyDeviceToHost);
//rearrange array in original order
for (int i=0; i<n; i++)
m[array[i].origIndex] = array[i].yValue;
cudaFree(deviceArray);
}//if
else //have to chunk up data
{
int lb, ub;
for (int i=0; i<n; i++)
{
lb = h_binarySearchLB(array, array[i].xValue-h, n);
ub = h_binarySearchUB(array, array[i].xValue+h, n);
entry * chunkArray = new entry[ub-lb];
for (int j=0; j<ub-lb; j++)
chunkArray[j] = array[lb+j];
cudaMalloc(&deviceArray, sizeof(entry) * (ub-lb));
cudaMemcpy(deviceArray, chunkArray, sizeof(entry) * (ub-lb), cudaMemcpyHostToDevice);
kernel2 <<< 1, 1 >>> (deviceArray, ub-lb);
cudaMemcpy(chunkArray, deviceArray, sizeof(entry) * (ub-lb), cudaMemcpyDeviceToHost);
m[array[i].origIndex] = chunkArray[0].yValue;//store y avg
cudaFree(deviceArray);
delete [] chunkArray;
}//for
}//else
delete [] array;
}//smoothc
/*
int main()
{
int n = 200;
float * x = new float[n];
float * y = new float[n];
float * m = new float[n];
float h = 2;
for (int i=0; i<n; i++)
{
x[i] = rand() % 100;
y[i] = rand() % 100;
}//for
float x[20] = {1, 1,2,2, 3,3, 4,4, 5,5, 6,6, 7,7, 8,8, 9,9, 10,10};
float y[20] = {11,11, 12,12, 13,13, 14,14, 15,15, 16,16, 17,17, 18,18, 19,19, 20,20};
float m[20];
int n = 20;
float h = 2;
smoothc(x, y, m, n, h);
// delete [] x;
// delete [] y;
// delete [] m;
}//main
*/ | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define GIGABYTE 1000000000
struct entry
{
int origIndex;
float xValue, yValue;
};//entry
int h_binarySearchLB(entry * data, float val, int n)
{
//return index of greatest leftmost xValue that is greater than val
int left = 0;
int right = n;
int mid;
while (left != right)
{
mid = (left+right)/2;
if (data[mid].xValue <= val)
left = mid + 1;
else
right = mid;
}//while
return left;
}//binarySearchLB
int h_binarySearchUB(entry * data, float val, int n)
{
//return index of greatest leftmost xValue that is greater than val
int left = 0;
int right = n;
int mid;
while (left != right)
{
mid = (left+right)/2;
if (data[mid].xValue >= val)
right = mid;
else
left = mid + 1;
}//while
return left;
}//binarySearchUB
__device__ int binarySearchLB(entry * data, float val, int n)//val is x val +/- tuning parameter
{
//return index of greatest leftmost xValue that is greater than val
int left = 0;
int right = n;
int mid;
while (left != right)
{
mid = (left+right)/2;
if (data[mid].xValue <= val)
left = mid + 1;
else
right = mid;
}//while
return left;
}//binarySearchLB
__device__ int binarySearchUB(entry * data, float val, int n)
{
//return index of greatest leftmost xValue that is greater than val
int left = 0;
int right = n;
int mid;
while (left != right)
{
mid = (left+right)/2;
if (data[mid].xValue >= val)
right = mid;
else
left = mid + 1;
}//while
return left;
}//binarySearchUB
__global__ void kernel1(entry * array, int n, float h)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int lowerBound = binarySearchLB(array, array[idx].xValue-h, n);//binsearchlb device func
int upperBound = binarySearchUB(array, array[idx].xValue+h, n);//ub is device func
float avg = 0;
//calculate y average
for (int i=lowerBound; i<upperBound; i++)
avg += array[i].yValue;
avg = avg/((float) (upperBound-lowerBound));
//yValue stores the avg
array[idx].yValue = avg;
}//kernel1
__global__ void kernel2(entry * array, int n)
{
float avg = 0;
for (int i=0; i<n; i++)
avg += array[i].yValue;
avg = avg / (float) n;
array[0].yValue = avg;
}//kernel2
void merge(entry * a, int low, int high)
{
int pivot = (low+high)/2;
int i = 0;
int j = low;
int k = pivot+1;
entry * temp = new entry[high-low+1];
while ((j <= pivot) && (k <= high))
{
if (a[j].xValue < a[k].xValue)
temp[i++] = a[j++];
else
temp[i++] = a[k++];
}//while
while (j <= pivot)
temp[i++] = a[j++];
while (k <= high)
temp[i++] = a[k++];
for (int h=low; h<= high; h++)
a[h] = temp[h-low];
delete [] temp;
}//merge
void mergeSort(entry * a, int low, int high)
{
int pivot;
if (low < high)
{
pivot = (low+high)/2;
mergeSort(a, low, pivot);
mergeSort(a, pivot+1, high);
merge(a, low, high);
}//if
}//mergeSort
void smoothc(float * x, float * y, float * m, int n, float h)
{
entry * array = new entry[n];
entry * deviceArray;
int * countArray = new int[n];// should not be there, mem leak
int blockSize = 1024;//num thread per block
//creat array of structs
for (int i=0; i<n; i++)
{
entry temp;
temp.origIndex = i;
temp.xValue = x[i];
temp.yValue = y[i];
array[i] = temp;
}//for
//sort by xValue
mergeSort(array, 0, n-1);
if (n < GIGABYTE/sizeof(entry))// if fits into 1 gig of mem hard code in line 5
{
//put array onto device array
hipMalloc(&deviceArray, sizeof(entry) * n);
hipMemcpy(deviceArray, array, sizeof(entry) * n, hipMemcpyHostToDevice);
dim3 dimBlock(blockSize);
dim3 dimGrid(ceil(n/blockSize));
//stores smoothed average in yValue
kernel1 <<< dimGrid, dimBlock >>> (deviceArray, n, h);//send to line 96
hipMemcpy(array, deviceArray, sizeof(entry) * n, hipMemcpyDeviceToHost);
//rearrange array in original order
for (int i=0; i<n; i++)
m[array[i].origIndex] = array[i].yValue;
hipFree(deviceArray);
}//if
else //have to chunk up data
{
int lb, ub;
for (int i=0; i<n; i++)
{
lb = h_binarySearchLB(array, array[i].xValue-h, n);
ub = h_binarySearchUB(array, array[i].xValue+h, n);
entry * chunkArray = new entry[ub-lb];
for (int j=0; j<ub-lb; j++)
chunkArray[j] = array[lb+j];
hipMalloc(&deviceArray, sizeof(entry) * (ub-lb));
hipMemcpy(deviceArray, chunkArray, sizeof(entry) * (ub-lb), hipMemcpyHostToDevice);
kernel2 <<< 1, 1 >>> (deviceArray, ub-lb);
hipMemcpy(chunkArray, deviceArray, sizeof(entry) * (ub-lb), hipMemcpyDeviceToHost);
m[array[i].origIndex] = chunkArray[0].yValue;//store y avg
hipFree(deviceArray);
delete [] chunkArray;
}//for
}//else
delete [] array;
}//smoothc
/*
int main()
{
int n = 200;
float * x = new float[n];
float * y = new float[n];
float * m = new float[n];
float h = 2;
for (int i=0; i<n; i++)
{
x[i] = rand() % 100;
y[i] = rand() % 100;
}//for
float x[20] = {1, 1,2,2, 3,3, 4,4, 5,5, 6,6, 7,7, 8,8, 9,9, 10,10};
float y[20] = {11,11, 12,12, 13,13, 14,14, 15,15, 16,16, 17,17, 18,18, 19,19, 20,20};
float m[20];
int n = 20;
float h = 2;
smoothc(x, y, m, n, h);
// delete [] x;
// delete [] y;
// delete [] m;
}//main
*/ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define GIGABYTE 1000000000
struct entry
{
int origIndex;
float xValue, yValue;
};//entry
int h_binarySearchLB(entry * data, float val, int n)
{
//return index of greatest leftmost xValue that is greater than val
int left = 0;
int right = n;
int mid;
while (left != right)
{
mid = (left+right)/2;
if (data[mid].xValue <= val)
left = mid + 1;
else
right = mid;
}//while
return left;
}//binarySearchLB
int h_binarySearchUB(entry * data, float val, int n)
{
//return index of greatest leftmost xValue that is greater than val
int left = 0;
int right = n;
int mid;
while (left != right)
{
mid = (left+right)/2;
if (data[mid].xValue >= val)
right = mid;
else
left = mid + 1;
}//while
return left;
}//binarySearchUB
__device__ int binarySearchLB(entry * data, float val, int n)//val is x val +/- tuning parameter
{
//return index of greatest leftmost xValue that is greater than val
int left = 0;
int right = n;
int mid;
while (left != right)
{
mid = (left+right)/2;
if (data[mid].xValue <= val)
left = mid + 1;
else
right = mid;
}//while
return left;
}//binarySearchLB
__device__ int binarySearchUB(entry * data, float val, int n)
{
//return index of greatest leftmost xValue that is greater than val
int left = 0;
int right = n;
int mid;
while (left != right)
{
mid = (left+right)/2;
if (data[mid].xValue >= val)
right = mid;
else
left = mid + 1;
}//while
return left;
}//binarySearchUB
__global__ void kernel1(entry * array, int n, float h)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int lowerBound = binarySearchLB(array, array[idx].xValue-h, n);//binsearchlb device func
int upperBound = binarySearchUB(array, array[idx].xValue+h, n);//ub is device func
float avg = 0;
//calculate y average
for (int i=lowerBound; i<upperBound; i++)
avg += array[i].yValue;
avg = avg/((float) (upperBound-lowerBound));
//yValue stores the avg
array[idx].yValue = avg;
}//kernel1
__global__ void kernel2(entry * array, int n)
{
float avg = 0;
for (int i=0; i<n; i++)
avg += array[i].yValue;
avg = avg / (float) n;
array[0].yValue = avg;
}//kernel2
void merge(entry * a, int low, int high)
{
int pivot = (low+high)/2;
int i = 0;
int j = low;
int k = pivot+1;
entry * temp = new entry[high-low+1];
while ((j <= pivot) && (k <= high))
{
if (a[j].xValue < a[k].xValue)
temp[i++] = a[j++];
else
temp[i++] = a[k++];
}//while
while (j <= pivot)
temp[i++] = a[j++];
while (k <= high)
temp[i++] = a[k++];
for (int h=low; h<= high; h++)
a[h] = temp[h-low];
delete [] temp;
}//merge
void mergeSort(entry * a, int low, int high)
{
int pivot;
if (low < high)
{
pivot = (low+high)/2;
mergeSort(a, low, pivot);
mergeSort(a, pivot+1, high);
merge(a, low, high);
}//if
}//mergeSort
void smoothc(float * x, float * y, float * m, int n, float h)
{
entry * array = new entry[n];
entry * deviceArray;
int * countArray = new int[n];// should not be there, mem leak
int blockSize = 1024;//num thread per block
//creat array of structs
for (int i=0; i<n; i++)
{
entry temp;
temp.origIndex = i;
temp.xValue = x[i];
temp.yValue = y[i];
array[i] = temp;
}//for
//sort by xValue
mergeSort(array, 0, n-1);
if (n < GIGABYTE/sizeof(entry))// if fits into 1 gig of mem hard code in line 5
{
//put array onto device array
hipMalloc(&deviceArray, sizeof(entry) * n);
hipMemcpy(deviceArray, array, sizeof(entry) * n, hipMemcpyHostToDevice);
dim3 dimBlock(blockSize);
dim3 dimGrid(ceil(n/blockSize));
//stores smoothed average in yValue
kernel1 <<< dimGrid, dimBlock >>> (deviceArray, n, h);//send to line 96
hipMemcpy(array, deviceArray, sizeof(entry) * n, hipMemcpyDeviceToHost);
//rearrange array in original order
for (int i=0; i<n; i++)
m[array[i].origIndex] = array[i].yValue;
hipFree(deviceArray);
}//if
else //have to chunk up data
{
int lb, ub;
for (int i=0; i<n; i++)
{
lb = h_binarySearchLB(array, array[i].xValue-h, n);
ub = h_binarySearchUB(array, array[i].xValue+h, n);
entry * chunkArray = new entry[ub-lb];
for (int j=0; j<ub-lb; j++)
chunkArray[j] = array[lb+j];
hipMalloc(&deviceArray, sizeof(entry) * (ub-lb));
hipMemcpy(deviceArray, chunkArray, sizeof(entry) * (ub-lb), hipMemcpyHostToDevice);
kernel2 <<< 1, 1 >>> (deviceArray, ub-lb);
hipMemcpy(chunkArray, deviceArray, sizeof(entry) * (ub-lb), hipMemcpyDeviceToHost);
m[array[i].origIndex] = chunkArray[0].yValue;//store y avg
hipFree(deviceArray);
delete [] chunkArray;
}//for
}//else
delete [] array;
}//smoothc
/*
int main()
{
int n = 200;
float * x = new float[n];
float * y = new float[n];
float * m = new float[n];
float h = 2;
for (int i=0; i<n; i++)
{
x[i] = rand() % 100;
y[i] = rand() % 100;
}//for
float x[20] = {1, 1,2,2, 3,3, 4,4, 5,5, 6,6, 7,7, 8,8, 9,9, 10,10};
float y[20] = {11,11, 12,12, 13,13, 14,14, 15,15, 16,16, 17,17, 18,18, 19,19, 20,20};
float m[20];
int n = 20;
float h = 2;
smoothc(x, y, m, n, h);
// delete [] x;
// delete [] y;
// delete [] m;
}//main
*/ | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7kernel1P5entryif
.globl _Z7kernel1P5entryif
.p2align 8
.type _Z7kernel1P5entryif,@function
_Z7kernel1P5entryif:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s2, 0xffff
s_cmp_lg_u32 s6, 0
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
v_mov_b32_e32 v0, 0
s_cselect_b32 s0, -1, 0
s_cmp_eq_u32 s6, 0
s_delay_alu instid0(VALU_DEP_2)
v_mad_i64_i32 v[2:3], null, v1, 12, s[4:5]
global_load_b32 v2, v[2:3], off offset:4
s_cbranch_scc1 .LBB0_4
s_waitcnt vmcnt(0)
v_dual_subrev_f32 v3, s7, v2 :: v_dual_mov_b32 v0, 0
v_mov_b32_e32 v4, s6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, v4, v0
v_lshrrev_b32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, v5, v6
v_ashrrev_i32_e32 v7, 1, v5
s_delay_alu instid0(VALU_DEP_1)
v_mad_i64_i32 v[5:6], null, v7, 12, s[4:5]
global_load_b32 v5, v[5:6], off offset:4
v_add_nc_u32_e32 v6, 1, v7
s_waitcnt vmcnt(0)
v_cmp_nle_f32_e32 vcc_lo, v5, v3
v_cndmask_b32_e32 v4, v4, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v6, v0, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, v0, v4
s_or_b32 s1, vcc_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s1
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB0_8
s_waitcnt vmcnt(0)
v_dual_add_f32 v2, s7, v2 :: v_dual_mov_b32 v3, s6
v_mov_b32_e32 v4, 0
s_mov_b32 s0, 0
.LBB0_6:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, v3, v4
v_lshrrev_b32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, v5, v6
v_ashrrev_i32_e32 v7, 1, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_mad_i64_i32 v[5:6], null, v7, 12, s[4:5]
global_load_b32 v5, v[5:6], off offset:4
v_add_nc_u32_e32 v6, 1, v7
s_waitcnt vmcnt(0)
v_cmp_nge_f32_e32 vcc_lo, v5, v2
v_dual_cndmask_b32 v4, v4, v6 :: v_dual_cndmask_b32 v3, v7, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, v4, v3
s_or_b32 s0, vcc_lo, s0
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_6
s_or_b32 exec_lo, exec_lo, s0
s_branch .LBB0_9
.LBB0_8:
v_mov_b32_e32 v4, 0
.LBB0_9:
v_mov_b32_e32 v5, 0
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_gt_i32_e64 v4, v0
s_cbranch_execz .LBB0_13
s_waitcnt vmcnt(0)
v_mad_i64_i32 v[2:3], null, v0, 12, s[4:5]
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v6, v0
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, v2, 8
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
.LBB0_11:
global_load_b32 v7, v[2:3], off
v_add_nc_u32_e32 v6, 1, v6
v_add_co_u32 v2, vcc_lo, v2, 12
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v5, v5, v7
v_cmp_ge_i32_e64 s0, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, s0, s2
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_11
s_or_b32 exec_lo, exec_lo, s2
.LBB0_13:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s1
v_sub_nc_u32_e32 v0, v4, v0
v_cvt_f32_i32_e32 v0, v0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v2, null, v0, v0, v5
v_rcp_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_fma_f32 v4, -v2, v3, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, v4, v3
v_div_scale_f32 v4, vcc_lo, v5, v0, v5
v_mul_f32_e32 v6, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v2, v6, v4
v_fmac_f32_e32 v6, v7, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v2, -v2, v6, v4
v_div_fmas_f32 v4, v2, v3, v6
v_mad_i64_i32 v[2:3], null, v1, 12, s[4:5]
s_delay_alu instid0(VALU_DEP_2)
v_div_fixup_f32 v0, v4, v0, v5
global_store_b32 v[2:3], v0, off offset:8
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernel1P5entryif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7kernel1P5entryif, .Lfunc_end0-_Z7kernel1P5entryif
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7kernel2P5entryi
.globl _Z7kernel2P5entryi
.p2align 8
.type _Z7kernel2P5entryi,@function
_Z7kernel2P5entryi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB1_3
s_add_u32 s2, s0, 8
s_addc_u32 s3, s1, 0
s_mov_b32 s5, s4
.LBB1_2:
s_load_b32 s6, s[2:3], 0x0
s_add_i32 s5, s5, -1
s_add_u32 s2, s2, 12
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s5, 0
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, s6, v0
s_cbranch_scc0 .LBB1_2
.LBB1_3:
v_cvt_f32_i32_e32 v1, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v2, null, v1, v1, v0
v_div_scale_f32 v5, vcc_lo, v0, v1, v0
v_rcp_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_fma_f32 v4, -v2, v3, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, v4, v3
v_mul_f32_e32 v4, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, -v2, v4, v5
v_fmac_f32_e32 v4, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v2, -v2, v4, v5
v_div_fmas_f32 v2, v2, v3, v4
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v0, v2, v1, v0
v_mov_b32_e32 v1, 0
global_store_b32 v1, v0, s[0:1] offset:8
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernel2P5entryi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 7
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7kernel2P5entryi, .Lfunc_end1-_Z7kernel2P5entryi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernel1P5entryif
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7kernel1P5entryif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernel2P5entryi
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: _Z7kernel2P5entryi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define GIGABYTE 1000000000
struct entry
{
int origIndex;
float xValue, yValue;
};//entry
int h_binarySearchLB(entry * data, float val, int n)
{
//return index of greatest leftmost xValue that is greater than val
int left = 0;
int right = n;
int mid;
while (left != right)
{
mid = (left+right)/2;
if (data[mid].xValue <= val)
left = mid + 1;
else
right = mid;
}//while
return left;
}//binarySearchLB
int h_binarySearchUB(entry * data, float val, int n)
{
//return index of greatest leftmost xValue that is greater than val
int left = 0;
int right = n;
int mid;
while (left != right)
{
mid = (left+right)/2;
if (data[mid].xValue >= val)
right = mid;
else
left = mid + 1;
}//while
return left;
}//binarySearchUB
__device__ int binarySearchLB(entry * data, float val, int n)//val is x val +/- tuning parameter
{
//return index of greatest leftmost xValue that is greater than val
int left = 0;
int right = n;
int mid;
while (left != right)
{
mid = (left+right)/2;
if (data[mid].xValue <= val)
left = mid + 1;
else
right = mid;
}//while
return left;
}//binarySearchLB
__device__ int binarySearchUB(entry * data, float val, int n)
{
//return index of greatest leftmost xValue that is greater than val
int left = 0;
int right = n;
int mid;
while (left != right)
{
mid = (left+right)/2;
if (data[mid].xValue >= val)
right = mid;
else
left = mid + 1;
}//while
return left;
}//binarySearchUB
__global__ void kernel1(entry * array, int n, float h)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int lowerBound = binarySearchLB(array, array[idx].xValue-h, n);//binsearchlb device func
int upperBound = binarySearchUB(array, array[idx].xValue+h, n);//ub is device func
float avg = 0;
//calculate y average
for (int i=lowerBound; i<upperBound; i++)
avg += array[i].yValue;
avg = avg/((float) (upperBound-lowerBound));
//yValue stores the avg
array[idx].yValue = avg;
}//kernel1
__global__ void kernel2(entry * array, int n)
{
float avg = 0;
for (int i=0; i<n; i++)
avg += array[i].yValue;
avg = avg / (float) n;
array[0].yValue = avg;
}//kernel2
void merge(entry * a, int low, int high)
{
int pivot = (low+high)/2;
int i = 0;
int j = low;
int k = pivot+1;
entry * temp = new entry[high-low+1];
while ((j <= pivot) && (k <= high))
{
if (a[j].xValue < a[k].xValue)
temp[i++] = a[j++];
else
temp[i++] = a[k++];
}//while
while (j <= pivot)
temp[i++] = a[j++];
while (k <= high)
temp[i++] = a[k++];
for (int h=low; h<= high; h++)
a[h] = temp[h-low];
delete [] temp;
}//merge
void mergeSort(entry * a, int low, int high)
{
int pivot;
if (low < high)
{
pivot = (low+high)/2;
mergeSort(a, low, pivot);
mergeSort(a, pivot+1, high);
merge(a, low, high);
}//if
}//mergeSort
void smoothc(float * x, float * y, float * m, int n, float h)
{
entry * array = new entry[n];
entry * deviceArray;
int * countArray = new int[n];// should not be there, mem leak
int blockSize = 1024;//num thread per block
//creat array of structs
for (int i=0; i<n; i++)
{
entry temp;
temp.origIndex = i;
temp.xValue = x[i];
temp.yValue = y[i];
array[i] = temp;
}//for
//sort by xValue
mergeSort(array, 0, n-1);
if (n < GIGABYTE/sizeof(entry))// if fits into 1 gig of mem hard code in line 5
{
//put array onto device array
hipMalloc(&deviceArray, sizeof(entry) * n);
hipMemcpy(deviceArray, array, sizeof(entry) * n, hipMemcpyHostToDevice);
dim3 dimBlock(blockSize);
dim3 dimGrid(ceil(n/blockSize));
//stores smoothed average in yValue
kernel1 <<< dimGrid, dimBlock >>> (deviceArray, n, h);//send to line 96
hipMemcpy(array, deviceArray, sizeof(entry) * n, hipMemcpyDeviceToHost);
//rearrange array in original order
for (int i=0; i<n; i++)
m[array[i].origIndex] = array[i].yValue;
hipFree(deviceArray);
}//if
else //have to chunk up data
{
int lb, ub;
for (int i=0; i<n; i++)
{
lb = h_binarySearchLB(array, array[i].xValue-h, n);
ub = h_binarySearchUB(array, array[i].xValue+h, n);
entry * chunkArray = new entry[ub-lb];
for (int j=0; j<ub-lb; j++)
chunkArray[j] = array[lb+j];
hipMalloc(&deviceArray, sizeof(entry) * (ub-lb));
hipMemcpy(deviceArray, chunkArray, sizeof(entry) * (ub-lb), hipMemcpyHostToDevice);
kernel2 <<< 1, 1 >>> (deviceArray, ub-lb);
hipMemcpy(chunkArray, deviceArray, sizeof(entry) * (ub-lb), hipMemcpyDeviceToHost);
m[array[i].origIndex] = chunkArray[0].yValue;//store y avg
hipFree(deviceArray);
delete [] chunkArray;
}//for
}//else
delete [] array;
}//smoothc
/*
int main()
{
int n = 200;
float * x = new float[n];
float * y = new float[n];
float * m = new float[n];
float h = 2;
for (int i=0; i<n; i++)
{
x[i] = rand() % 100;
y[i] = rand() % 100;
}//for
float x[20] = {1, 1,2,2, 3,3, 4,4, 5,5, 6,6, 7,7, 8,8, 9,9, 10,10};
float y[20] = {11,11, 12,12, 13,13, 14,14, 15,15, 16,16, 17,17, 18,18, 19,19, 20,20};
float m[20];
int n = 20;
float h = 2;
smoothc(x, y, m, n, h);
// delete [] x;
// delete [] y;
// delete [] m;
}//main
*/ | .text
.file "SmoothC.hip"
.globl _Z16h_binarySearchLBP5entryfi # -- Begin function _Z16h_binarySearchLBP5entryfi
.p2align 4, 0x90
.type _Z16h_binarySearchLBP5entryfi,@function
_Z16h_binarySearchLBP5entryfi: # @_Z16h_binarySearchLBP5entryfi
.cfi_startproc
# %bb.0:
# kill: def $esi killed $esi def $rsi
xorl %eax, %eax
testl %esi, %esi
jne .LBB0_1
jmp .LBB0_5
.p2align 4, 0x90
.LBB0_3: # %.lr.ph
# in Loop: Header=BB0_1 Depth=1
incl %ecx
movl %ecx, %eax
cmpl %esi, %eax
je .LBB0_5
.LBB0_1: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leal (%rax,%rsi), %edx
movl %edx, %ecx
shrl $31, %ecx
addl %edx, %ecx
sarl %ecx
movslq %ecx, %rdx
leaq (%rdx,%rdx,2), %rdx
ucomiss 4(%rdi,%rdx,4), %xmm0
jae .LBB0_3
# %bb.2: # in Loop: Header=BB0_1 Depth=1
movl %ecx, %esi
cmpl %esi, %eax
jne .LBB0_1
.LBB0_5: # %._crit_edge
# kill: def $eax killed $eax killed $rax
retq
.Lfunc_end0:
.size _Z16h_binarySearchLBP5entryfi, .Lfunc_end0-_Z16h_binarySearchLBP5entryfi
.cfi_endproc
# -- End function
.globl _Z16h_binarySearchUBP5entryfi # -- Begin function _Z16h_binarySearchUBP5entryfi
.p2align 4, 0x90
.type _Z16h_binarySearchUBP5entryfi,@function
_Z16h_binarySearchUBP5entryfi: # @_Z16h_binarySearchUBP5entryfi
.cfi_startproc
# %bb.0:
# kill: def $esi killed $esi def $rsi
xorl %eax, %eax
testl %esi, %esi
jne .LBB1_1
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_3: # %.lr.ph
# in Loop: Header=BB1_1 Depth=1
movl %ecx, %esi
cmpl %esi, %eax
je .LBB1_5
.LBB1_1: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leal (%rax,%rsi), %edx
movl %edx, %ecx
shrl $31, %ecx
addl %edx, %ecx
sarl %ecx
movslq %ecx, %rdx
leaq (%rdx,%rdx,2), %rdx
movss 4(%rdi,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
jae .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
incl %ecx
movl %ecx, %eax
cmpl %esi, %eax
jne .LBB1_1
.LBB1_5: # %._crit_edge
# kill: def $eax killed $eax killed $rax
retq
.Lfunc_end1:
.size _Z16h_binarySearchUBP5entryfi, .Lfunc_end1-_Z16h_binarySearchUBP5entryfi
.cfi_endproc
# -- End function
.globl _Z22__device_stub__kernel1P5entryif # -- Begin function _Z22__device_stub__kernel1P5entryif
.p2align 4, 0x90
.type _Z22__device_stub__kernel1P5entryif,@function
_Z22__device_stub__kernel1P5entryif: # @_Z22__device_stub__kernel1P5entryif
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movss %xmm0, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7kernel1P5entryif, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z22__device_stub__kernel1P5entryif, .Lfunc_end2-_Z22__device_stub__kernel1P5entryif
.cfi_endproc
# -- End function
.globl _Z22__device_stub__kernel2P5entryi # -- Begin function _Z22__device_stub__kernel2P5entryi
.p2align 4, 0x90
.type _Z22__device_stub__kernel2P5entryi,@function
_Z22__device_stub__kernel2P5entryi: # @_Z22__device_stub__kernel2P5entryi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7kernel2P5entryi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z22__device_stub__kernel2P5entryi, .Lfunc_end3-_Z22__device_stub__kernel2P5entryi
.cfi_endproc
# -- End function
.globl _Z5mergeP5entryii # -- Begin function _Z5mergeP5entryii
.p2align 4, 0x90
.type _Z5mergeP5entryii,@function
_Z5mergeP5entryii: # @_Z5mergeP5entryii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movl %esi, %r15d
movq %rdi, %r14
leal (%rbx,%r15), %eax
movl %eax, %r13d
shrl $31, %r13d
addl %eax, %r13d
sarl %r13d
leal 1(%r13), %ebp
movl %edx, %eax
subl %esi, %eax
incl %eax
cltq
movl $12, %ecx
mulq %rcx
movq $-1, %rdi
cmovnoq %rax, %rdi
callq _Znam
xorl %r12d, %r12d
cmpl %r15d, %r13d
jl .LBB4_2
# %bb.1:
cmpl %ebx, %r13d
jge .LBB4_2
# %bb.10: # %.lr.ph.preheader
xorl %r12d, %r12d
movq %rax, %rcx
movl %r15d, %r11d
.p2align 4, 0x90
.LBB4_11: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movslq %r11d, %rsi
leaq (%rsi,%rsi,2), %rdi
movslq %ebp, %r9
leaq (%r9,%r9,2), %rdx
movss 4(%r14,%rdx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %edx, %edx
xorl %r8d, %r8d
ucomiss 4(%r14,%rdi,4), %xmm0
setbe %dil
seta %r10b
ja .LBB4_13
# %bb.12: # %.lr.ph
# in Loop: Header=BB4_11 Depth=1
movq %r9, %rsi
.LBB4_13: # %.lr.ph
# in Loop: Header=BB4_11 Depth=1
leaq (%rsi,%rsi,2), %rsi
movb %r10b, %r8b
addl %r8d, %r11d
movb %dil, %dl
addl %edx, %ebp
movl 8(%r14,%rsi,4), %edx
movl %edx, 8(%rcx)
movq (%r14,%rsi,4), %rdx
movq %rdx, (%rcx)
incl %r12d
cmpl %r13d, %r11d
jg .LBB4_3
# %bb.14: # %.lr.ph
# in Loop: Header=BB4_11 Depth=1
addq $12, %rcx
cmpl %ebx, %ebp
jle .LBB4_11
jmp .LBB4_3
.LBB4_2:
movl %r15d, %r11d
.LBB4_3: # %.preheader54
subl %r11d, %r13d
jl .LBB4_5
# %bb.4: # %.lr.ph63.preheader
movl %r12d, %ecx
leaq (%rcx,%rcx,2), %rcx
leaq (%rax,%rcx,4), %rdi
movslq %r11d, %rcx
leaq (%rcx,%rcx,2), %rcx
leaq (%r14,%rcx,4), %rsi
leaq (%r13,%r13,2), %rcx
leaq 12(,%rcx,4), %rdx
movq %r15, (%rsp) # 8-byte Spill
movq %rax, %r15
callq memcpy@PLT
movq %r15, %rax
movq (%rsp), %r15 # 8-byte Reload
addl %r13d, %r12d
incl %r12d
.LBB4_5: # %.preheader53
movl %ebx, %edx
subl %ebp, %edx
jl .LBB4_7
# %bb.6: # %.lr.ph68.preheader
movl %r12d, %ecx
leaq (%rcx,%rcx,2), %rcx
leaq (%rax,%rcx,4), %rdi
movslq %ebp, %rcx
leaq (%rcx,%rcx,2), %rcx
leaq (%r14,%rcx,4), %rsi
leaq (%rdx,%rdx,2), %rcx
leaq 12(,%rcx,4), %rdx
movq %r15, %r12
movq %rax, %r15
callq memcpy@PLT
movq %r15, %rax
movq %r12, %r15
.LBB4_7: # %.preheader
subl %r15d, %ebx
jl .LBB4_9
# %bb.8: # %.lr.ph71.preheader
movslq %r15d, %rcx
leaq (%rcx,%rcx,2), %rcx
leaq (%r14,%rcx,4), %rdi
leaq (%rbx,%rbx,2), %rcx
leaq 12(,%rcx,4), %rdx
movq %rax, %rsi
movq %rax, %rbx
callq memcpy@PLT
movq %rbx, %rax
.LBB4_9: # %._crit_edge
movq %rax, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp _ZdaPv # TAILCALL
.Lfunc_end4:
.size _Z5mergeP5entryii, .Lfunc_end4-_Z5mergeP5entryii
.cfi_endproc
# -- End function
.globl _Z9mergeSortP5entryii # -- Begin function _Z9mergeSortP5entryii
.p2align 4, 0x90
.type _Z9mergeSortP5entryii,@function
_Z9mergeSortP5entryii: # @_Z9mergeSortP5entryii
.cfi_startproc
# %bb.0:
cmpl %edx, %esi
jge .LBB5_1
# %bb.2:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movl %esi, %r14d
leal (%rbx,%r14), %eax
movl %eax, %ebp
shrl $31, %ebp
addl %eax, %ebp
sarl %ebp
movq %rdi, %r15
movl %ebp, %edx
callq _Z9mergeSortP5entryii
incl %ebp
movq %r15, %rdi
movl %ebp, %esi
movl %ebx, %edx
callq _Z9mergeSortP5entryii
movq %r15, %rdi
movl %r14d, %esi
movl %ebx, %edx
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp _Z5mergeP5entryii # TAILCALL
.LBB5_1: # %common.ret
.cfi_restore %rbx
.cfi_restore %rbp
.cfi_restore %r14
.cfi_restore %r15
retq
.Lfunc_end5:
.size _Z9mergeSortP5entryii, .Lfunc_end5-_Z9mergeSortP5entryii
.cfi_endproc
# -- End function
.globl _Z7smoothcPfS_S_if # -- Begin function _Z7smoothcPfS_S_if
.p2align 4, 0x90
.type _Z7smoothcPfS_S_if,@function
_Z7smoothcPfS_S_if: # @_Z7smoothcPfS_S_if
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movss %xmm0, 16(%rsp) # 4-byte Spill
# kill: def $ecx killed $ecx def $rcx
movq %rdx, %rbx
movq %rsi, %r13
movq %rdi, %rbp
movq %rcx, 24(%rsp) # 8-byte Spill
movslq %ecx, %r12
movl $12, %ecx
movq %r12, %rax
mulq %rcx
movq $-1, %rdi
cmovnoq %rax, %rdi
callq _Znam
movq %rax, %r14
testl %r12d, %r12d
jle .LBB6_3
# %bb.1: # %.lr.ph.preheader
movl 24(%rsp), %eax # 4-byte Reload
leaq 8(%r14), %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB6_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rbp,%rdx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%r13,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movl %edx, -8(%rcx)
movss %xmm0, -4(%rcx)
movss %xmm1, (%rcx)
incq %rdx
addq $12, %rcx
cmpq %rdx, %rax
jne .LBB6_2
.LBB6_3: # %._crit_edge
movq 24(%rsp), %r13 # 8-byte Reload
leal -1(%r13), %edx
movq %r14, %rdi
xorl %esi, %esi
callq _Z9mergeSortP5entryii
cmpl $83333333, %r13d # imm = 0x4F790D5
jae .LBB6_4
# %bb.9:
shlq $2, %r12
leaq (%r12,%r12,2), %r12
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r13d, %eax
shrl $10, %eax
movabsq $4294967297, %rdx # imm = 0x100000001
leaq (%rax,%rdx), %rdi
decq %rdi
addq $1023, %rdx # imm = 0x3FF
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_11
# %bb.10:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl %r13d, 20(%rsp)
movss 16(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 92(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 92(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7kernel1P5entryif, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_11:
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
testl %r13d, %r13d
je .LBB6_14
# %bb.12: # %.lr.ph118.preheader
cmpl $2, %r13d
movl $1, %eax
cmovgel %r13d, %eax
shlq $2, %rax
leaq (%rax,%rax,2), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB6_13: # %.lr.ph118
# =>This Inner Loop Header: Depth=1
movss 8(%r14,%rcx), %xmm0 # xmm0 = mem[0],zero,zero,zero
movslq (%r14,%rcx), %rdx
movss %xmm0, (%rbx,%rdx,4)
addq $12, %rcx
cmpq %rcx, %rax
jne .LBB6_13
.LBB6_14: # %._crit_edge119
movq 8(%rsp), %rdi
callq hipFree
jmp .LBB6_27
.LBB6_4: # %.preheader
testl %r13d, %r13d
jle .LBB6_27
# %bb.5: # %.lr.ph115
movl %r13d, %eax
movq %rax, 120(%rsp) # 8-byte Spill
xorl %eax, %eax
movq %rbx, 128(%rsp) # 8-byte Spill
jmp .LBB6_6
.p2align 4, 0x90
.LBB6_26: # in Loop: Header=BB6_6 Depth=1
movq 136(%rsp), %rax # 8-byte Reload
leaq (%r14,%rax,4), %rbx
movq 8(%rsp), %rsi
movq %rbp, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movss 8(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movslq (%rbx), %rax
movq 128(%rsp), %rbx # 8-byte Reload
movss %xmm0, (%rbx,%rax,4)
movq 8(%rsp), %rdi
callq hipFree
movq %rbp, %rdi
callq _ZdaPv
movq 144(%rsp), %rax # 8-byte Reload
incq %rax
cmpq 120(%rsp), %rax # 8-byte Folded Reload
movq 24(%rsp), %r13 # 8-byte Reload
je .LBB6_27
.LBB6_6: # =>This Loop Header: Depth=1
# Child Loop BB6_7 Depth 2
# Child Loop BB6_18 Depth 2
movq %rax, 144(%rsp) # 8-byte Spill
leaq (%rax,%rax,2), %rax
movq %rax, 136(%rsp) # 8-byte Spill
movss 4(%r14,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps %xmm0, %xmm1
subss 16(%rsp), %xmm1 # 4-byte Folded Reload
xorl %r15d, %r15d
movl %r13d, %eax
jmp .LBB6_7
.p2align 4, 0x90
.LBB6_15: # %.lr.ph.i
# in Loop: Header=BB6_7 Depth=2
incl %ecx
movl %ecx, %r15d
cmpl %eax, %r15d
je .LBB6_17
.LBB6_7: # %.lr.ph.i
# Parent Loop BB6_6 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rax,%r15), %edx
movl %edx, %ecx
shrl $31, %ecx
addl %edx, %ecx
sarl %ecx
movslq %ecx, %rdx
leaq (%rdx,%rdx,2), %rdx
ucomiss 4(%r14,%rdx,4), %xmm1
jae .LBB6_15
# %bb.8: # in Loop: Header=BB6_7 Depth=2
movl %ecx, %eax
cmpl %eax, %r15d
jne .LBB6_7
.LBB6_17: # %_Z16h_binarySearchLBP5entryfi.exit
# in Loop: Header=BB6_6 Depth=1
addss 16(%rsp), %xmm0 # 4-byte Folded Reload
xorl %r12d, %r12d
movl %r13d, %eax
jmp .LBB6_18
.p2align 4, 0x90
.LBB6_20: # %.lr.ph.i91
# in Loop: Header=BB6_18 Depth=2
movl %ecx, %eax
cmpl %eax, %r12d
je .LBB6_22
.LBB6_18: # %.lr.ph.i91
# Parent Loop BB6_6 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rax,%r12), %edx
movl %edx, %ecx
shrl $31, %ecx
addl %edx, %ecx
sarl %ecx
movslq %ecx, %rdx
leaq (%rdx,%rdx,2), %rdx
movss 4(%r14,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
jae .LBB6_20
# %bb.19: # in Loop: Header=BB6_18 Depth=2
incl %ecx
movl %ecx, %r12d
cmpl %eax, %r12d
jne .LBB6_18
.LBB6_22: # %_Z16h_binarySearchUBP5entryfi.exit
# in Loop: Header=BB6_6 Depth=1
movl %r12d, %ebx
subl %r15d, %ebx
movslq %ebx, %r13
movq %r13, %rax
movl $12, %ecx
mulq %rcx
movq $-1, %rcx
cmovoq %rcx, %rax
movq %rax, %rdi
callq _Znam
movq %rax, %rbp
testl %r13d, %r13d
jle .LBB6_24
# %bb.23: # %.lr.ph112.preheader
# in Loop: Header=BB6_6 Depth=1
movslq %r15d, %rax
leaq (%rax,%rax,2), %rax
leaq (%r14,%rax,4), %rsi
notl %r15d
addl %r15d, %r12d
leaq (%r12,%r12,2), %rax
leaq 12(,%rax,4), %rdx
movq %rbp, %rdi
callq memcpy@PLT
.LBB6_24: # %._crit_edge113
# in Loop: Header=BB6_6 Depth=1
shlq $2, %r13
leaq (%r13,%r13,2), %r13
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %rbp, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_26
# %bb.25: # in Loop: Header=BB6_6 Depth=1
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl %ebx, 20(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z7kernel2P5entryi, %edi
leaq 96(%rsp), %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB6_26
.LBB6_27: # %.loopexit
movq %r14, %rdi
callq _ZdaPv
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z7smoothcPfS_S_if, .Lfunc_end6-_Z7smoothcPfS_S_if
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernel1P5entryif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernel2P5entryi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7kernel1P5entryif,@object # @_Z7kernel1P5entryif
.section .rodata,"a",@progbits
.globl _Z7kernel1P5entryif
.p2align 3, 0x0
_Z7kernel1P5entryif:
.quad _Z22__device_stub__kernel1P5entryif
.size _Z7kernel1P5entryif, 8
.type _Z7kernel2P5entryi,@object # @_Z7kernel2P5entryi
.globl _Z7kernel2P5entryi
.p2align 3, 0x0
_Z7kernel2P5entryi:
.quad _Z22__device_stub__kernel2P5entryi
.size _Z7kernel2P5entryi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7kernel1P5entryif"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7kernel2P5entryi"
.size .L__unnamed_2, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__kernel1P5entryif
.addrsig_sym _Z22__device_stub__kernel2P5entryi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7kernel1P5entryif
.addrsig_sym _Z7kernel2P5entryi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005e66d_00000000-6_SmoothC.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z16h_binarySearchLBP5entryfi
.type _Z16h_binarySearchLBP5entryfi, @function
_Z16h_binarySearchLBP5entryfi:
.LFB2057:
.cfi_startproc
endbr64
movl $0, %ecx
.L5:
cmpl %ecx, %esi
je .L11
leal (%rsi,%rcx), %edx
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
movslq %eax, %rdx
leaq (%rdx,%rdx,2), %rdx
comiss 4(%rdi,%rdx,4), %xmm0
jnb .L12
movl %eax, %esi
jmp .L5
.L12:
leal 1(%rax), %ecx
jmp .L5
.L11:
movl %ecx, %eax
ret
.cfi_endproc
.LFE2057:
.size _Z16h_binarySearchLBP5entryfi, .-_Z16h_binarySearchLBP5entryfi
.globl _Z16h_binarySearchUBP5entryfi
.type _Z16h_binarySearchUBP5entryfi, @function
_Z16h_binarySearchUBP5entryfi:
.LFB2058:
.cfi_startproc
endbr64
movl $0, %ecx
.L15:
cmpl %ecx, %esi
je .L18
leal (%rsi,%rcx), %edx
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
movslq %eax, %rdx
leaq (%rdx,%rdx,2), %rdx
movss 4(%rdi,%rdx,4), %xmm1
comiss %xmm0, %xmm1
jb .L19
movl %eax, %esi
jmp .L15
.L19:
leal 1(%rax), %ecx
jmp .L15
.L18:
movl %ecx, %eax
ret
.cfi_endproc
.LFE2058:
.size _Z16h_binarySearchUBP5entryfi, .-_Z16h_binarySearchUBP5entryfi
.globl _Z14binarySearchLBP5entryfi
.type _Z14binarySearchLBP5entryfi, @function
_Z14binarySearchLBP5entryfi:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z14binarySearchLBP5entryfi, .-_Z14binarySearchLBP5entryfi
.globl _Z14binarySearchUBP5entryfi
.type _Z14binarySearchUBP5entryfi, @function
_Z14binarySearchUBP5entryfi:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z14binarySearchUBP5entryfi, .-_Z14binarySearchUBP5entryfi
.globl _Z5mergeP5entryii
.type _Z5mergeP5entryii, @function
_Z5mergeP5entryii:
.LFB2061:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl %edx, %r12d
leal (%rsi,%rdx), %eax
movl %eax, %r14d
shrl $31, %r14d
addl %eax, %r14d
sarl %r14d
movl %edx, %eax
subl %esi, %eax
addl $1, %eax
cltq
movabsq $768614336404564650, %rdx
cmpq %rax, %rdx
jb .L25
movq %rdi, %rbp
movl %esi, %r13d
leal 1(%r14), %ebx
leaq (%rax,%rax,2), %rdi
salq $2, %rdi
call _Znam@PLT
movq %rax, %rdi
cmpl %r14d, %r13d
jg .L40
movl %r13d, %edx
movl $1, %ecx
cmpl %ebx, %r12d
jge .L32
.L40:
movl %r13d, %edx
movl $0, %r9d
.L28:
cmpl %edx, %r14d
jl .L34
movl %edx, %r10d
movl %r14d, %eax
subl %edx, %eax
leaq 3(%rax,%rax,2), %r8
salq $2, %r8
movslq %edx, %rdx
leaq (%rdx,%rdx,2), %rax
leaq 0(%rbp,%rax,4), %rcx
movslq %r9d, %rax
leaq (%rax,%rax,2), %rax
leaq (%rdi,%rax,4), %rdx
movl $0, %eax
.L35:
movq (%rcx,%rax), %rsi
movq %rsi, (%rdx,%rax)
movl 8(%rcx,%rax), %esi
movl %esi, 8(%rdx,%rax)
addq $12, %rax
cmpq %r8, %rax
jne .L35
leal 1(%r9,%r14), %r9d
subl %r10d, %r9d
.L34:
cmpl %ebx, %r12d
jl .L36
movl %r12d, %eax
subl %ebx, %eax
leaq 3(%rax,%rax,2), %r8
salq $2, %r8
movslq %ebx, %rbx
leaq (%rbx,%rbx,2), %rax
leaq 0(%rbp,%rax,4), %rcx
movslq %r9d, %r9
leaq (%r9,%r9,2), %rax
leaq (%rdi,%rax,4), %rdx
movl $0, %eax
.L37:
movq (%rcx,%rax), %rsi
movq %rsi, (%rdx,%rax)
movl 8(%rcx,%rax), %esi
movl %esi, 8(%rdx,%rax)
addq $12, %rax
cmpq %r8, %rax
jne .L37
.L36:
cmpl %r12d, %r13d
jg .L38
subl %r13d, %r12d
leaq 3(%r12,%r12,2), %rsi
salq $2, %rsi
movslq %r13d, %r13
leaq 0(%r13,%r13,2), %rax
leaq 0(%rbp,%rax,4), %rdx
movl $0, %eax
.L39:
movq (%rdi,%rax), %rcx
movq %rcx, (%rdx,%rax)
movl 8(%rdi,%rax), %ecx
movl %ecx, 8(%rdx,%rax)
addq $12, %rax
cmpq %rsi, %rax
jne .L39
.L38:
call _ZdaPv@PLT
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
call __cxa_throw_bad_array_new_length@PLT
.L47:
addl $1, %ebx
movl %ecx, %r9d
movq (%rsi), %r8
movq %r8, (%rax)
movl 8(%rsi), %esi
movl %esi, 8(%rax)
.L31:
addl $1, %ecx
addq $12, %rax
cmpl %r14d, %edx
jg .L28
cmpl %r12d, %ebx
jg .L28
.L32:
movslq %edx, %rsi
leaq (%rsi,%rsi,2), %rsi
leaq 0(%rbp,%rsi,4), %r8
movslq %ebx, %rsi
leaq (%rsi,%rsi,2), %rsi
leaq 0(%rbp,%rsi,4), %rsi
movss 4(%rsi), %xmm0
comiss 4(%r8), %xmm0
jbe .L47
addl $1, %edx
movl %ecx, %r9d
movq (%r8), %rsi
movq %rsi, (%rax)
movl 8(%r8), %esi
movl %esi, 8(%rax)
jmp .L31
.cfi_endproc
.LFE2061:
.size _Z5mergeP5entryii, .-_Z5mergeP5entryii
.globl _Z9mergeSortP5entryii
.type _Z9mergeSortP5entryii, @function
_Z9mergeSortP5entryii:
.LFB2062:
.cfi_startproc
endbr64
cmpl %edx, %esi
jl .L55
ret
.L55:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r12
movl %esi, %ebx
movl %edx, %ebp
leal (%rsi,%rdx), %eax
movl %eax, %r13d
shrl $31, %r13d
addl %eax, %r13d
sarl %r13d
movl %r13d, %edx
call _Z9mergeSortP5entryii
leal 1(%r13), %esi
movl %ebp, %edx
movq %r12, %rdi
call _Z9mergeSortP5entryii
movl %ebp, %edx
movl %ebx, %esi
movq %r12, %rdi
call _Z5mergeP5entryii
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z9mergeSortP5entryii, .-_Z9mergeSortP5entryii
.globl _Z33__device_stub__Z7kernel1P5entryifP5entryif
.type _Z33__device_stub__Z7kernel1P5entryifP5entryif, @function
_Z33__device_stub__Z7kernel1P5entryifP5entryif:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movss %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L60
.L56:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L61
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7kernel1P5entryif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L56
.L61:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z33__device_stub__Z7kernel1P5entryifP5entryif, .-_Z33__device_stub__Z7kernel1P5entryifP5entryif
.globl _Z7kernel1P5entryif
.type _Z7kernel1P5entryif, @function
_Z7kernel1P5entryif:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z7kernel1P5entryifP5entryif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z7kernel1P5entryif, .-_Z7kernel1P5entryif
.globl _Z32__device_stub__Z7kernel2P5entryiP5entryi
.type _Z32__device_stub__Z7kernel2P5entryiP5entryi, @function
_Z32__device_stub__Z7kernel2P5entryiP5entryi:
.LFB2090:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L68
.L64:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L69
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L68:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7kernel2P5entryi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L64
.L69:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z32__device_stub__Z7kernel2P5entryiP5entryi, .-_Z32__device_stub__Z7kernel2P5entryiP5entryi
.globl _Z7kernel2P5entryi
.type _Z7kernel2P5entryi, @function
_Z7kernel2P5entryi:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z7kernel2P5entryiP5entryi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z7kernel2P5entryi, .-_Z7kernel2P5entryi
.globl _Z7smoothcPfS_S_if
.type _Z7smoothcPfS_S_if, @function
_Z7smoothcPfS_S_if:
.LFB2063:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdx, 24(%rsp)
movss %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movslq %ecx, %rbx
movabsq $768614336404564650, %rax
cmpq %rbx, %rax
jb .L73
movq %rdi, %rbp
movq %rsi, %r12
movl %ecx, %r14d
leaq (%rbx,%rbx,2), %rax
leaq 0(,%rax,4), %r13
movq %r13, %rdi
call _Znam@PLT
movq %rax, %r15
movq %rax, %rdx
movl $0, %eax
testl %r14d, %r14d
jle .L75
.L77:
movss 0(%rbp,%rax,4), %xmm1
movss (%r12,%rax,4), %xmm0
movl %eax, (%rdx)
movss %xmm1, 4(%rdx)
movss %xmm0, 8(%rdx)
addq $1, %rax
addq $12, %rdx
cmpq %rax, %rbx
jne .L77
.L75:
leal -1(%r14), %edx
movl $0, %esi
movq %r15, %rdi
call _Z9mergeSortP5entryii
movq %r15, %rdi
movl $0, %eax
cmpq $83333332, %rbx
jbe .L100
movq %r15, 8(%rsp)
movl %eax, %r15d
movl %r14d, 4(%rsp)
movq %rdi, %r14
jmp .L89
.L73:
movq 72(%rsp), %rax
subq %fs:40, %rax
je .L76
call __stack_chk_fail@PLT
.L76:
call __cxa_throw_bad_array_new_length@PLT
.L100:
leaq 40(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r15, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
leal 1023(%r14), %eax
testl %r14d, %r14d
cmovns %r14d, %eax
sarl $10, %eax
movl %eax, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L101
.L79:
movl $2, %ecx
movq %r13, %rdx
movq 40(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
testl %r14d, %r14d
jle .L80
movq %r15, %rax
addq %r15, %r13
movq 24(%rsp), %rcx
.L81:
movslq (%rax), %rdx
movss 8(%rax), %xmm0
movss %xmm0, (%rcx,%rdx,4)
addq $12, %rax
cmpq %rax, %r13
jne .L81
.L80:
movq 40(%rsp), %rdi
call cudaFree@PLT
jmp .L82
.L101:
movss (%rsp), %xmm0
movl %r14d, %esi
movq 40(%rsp), %rdi
call _Z33__device_stub__Z7kernel1P5entryifP5entryif
jmp .L79
.L83:
movq 72(%rsp), %rax
subq %fs:40, %rax
je .L86
call __stack_chk_fail@PLT
.L86:
call __cxa_throw_bad_array_new_length@PLT
.L88:
movl $2, %ecx
movq %rbp, %rdx
movq 40(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rax
movslq (%rax), %rax
movss 8(%rbx), %xmm0
movq 24(%rsp), %rsi
movss %xmm0, (%rsi,%rax,4)
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
addl $1, %r15d
addq $12, %r14
cmpl %r15d, 4(%rsp)
jle .L102
.L89:
movq %r14, 16(%rsp)
movl 4(%r14), %ebx
movd %ebx, %xmm0
subss (%rsp), %xmm0
movl 4(%rsp), %r13d
movl %r13d, %esi
movq 8(%rsp), %rbp
movq %rbp, %rdi
call _Z16h_binarySearchLBP5entryfi
movl %eax, %r12d
movd %ebx, %xmm0
addss (%rsp), %xmm0
movl %r13d, %esi
movq %rbp, %rdi
call _Z16h_binarySearchUBP5entryfi
subl %r12d, %eax
movl %eax, %r13d
cltq
movabsq $768614336404564650, %rsi
cmpq %rax, %rsi
jb .L83
leaq (%rax,%rax,2), %rbp
salq $2, %rbp
movq %rbp, %rdi
call _Znam@PLT
movq %rax, %rbx
testl %r13d, %r13d
jle .L85
movslq %r12d, %r12
leaq (%r12,%r12,2), %rax
movq 8(%rsp), %rsi
leaq (%rsi,%rax,4), %rdx
movl $0, %eax
.L87:
movq (%rdx,%rax), %rcx
movq %rcx, (%rbx,%rax)
movl 8(%rdx,%rax), %ecx
movl %ecx, 8(%rbx,%rax)
addq $12, %rax
cmpq %rax, %rbp
jne .L87
.L85:
leaq 40(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %rbx, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L88
movl %r13d, %esi
movq 40(%rsp), %rdi
call _Z32__device_stub__Z7kernel2P5entryiP5entryi
jmp .L88
.L102:
movq 8(%rsp), %r15
.L82:
movq %r15, %rdi
call _ZdaPv@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L103
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L103:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size _Z7smoothcPfS_S_if, .-_Z7smoothcPfS_S_if
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7kernel2P5entryi"
.LC1:
.string "_Z7kernel1P5entryif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2093:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernel2P5entryi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernel1P5entryif(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "SmoothC.hip"
.globl _Z16h_binarySearchLBP5entryfi # -- Begin function _Z16h_binarySearchLBP5entryfi
.p2align 4, 0x90
.type _Z16h_binarySearchLBP5entryfi,@function
_Z16h_binarySearchLBP5entryfi: # @_Z16h_binarySearchLBP5entryfi
.cfi_startproc
# %bb.0:
# kill: def $esi killed $esi def $rsi
xorl %eax, %eax
testl %esi, %esi
jne .LBB0_1
jmp .LBB0_5
.p2align 4, 0x90
.LBB0_3: # %.lr.ph
# in Loop: Header=BB0_1 Depth=1
incl %ecx
movl %ecx, %eax
cmpl %esi, %eax
je .LBB0_5
.LBB0_1: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leal (%rax,%rsi), %edx
movl %edx, %ecx
shrl $31, %ecx
addl %edx, %ecx
sarl %ecx
movslq %ecx, %rdx
leaq (%rdx,%rdx,2), %rdx
ucomiss 4(%rdi,%rdx,4), %xmm0
jae .LBB0_3
# %bb.2: # in Loop: Header=BB0_1 Depth=1
movl %ecx, %esi
cmpl %esi, %eax
jne .LBB0_1
.LBB0_5: # %._crit_edge
# kill: def $eax killed $eax killed $rax
retq
.Lfunc_end0:
.size _Z16h_binarySearchLBP5entryfi, .Lfunc_end0-_Z16h_binarySearchLBP5entryfi
.cfi_endproc
# -- End function
.globl _Z16h_binarySearchUBP5entryfi # -- Begin function _Z16h_binarySearchUBP5entryfi
.p2align 4, 0x90
.type _Z16h_binarySearchUBP5entryfi,@function
_Z16h_binarySearchUBP5entryfi: # @_Z16h_binarySearchUBP5entryfi
.cfi_startproc
# %bb.0:
# kill: def $esi killed $esi def $rsi
xorl %eax, %eax
testl %esi, %esi
jne .LBB1_1
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_3: # %.lr.ph
# in Loop: Header=BB1_1 Depth=1
movl %ecx, %esi
cmpl %esi, %eax
je .LBB1_5
.LBB1_1: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leal (%rax,%rsi), %edx
movl %edx, %ecx
shrl $31, %ecx
addl %edx, %ecx
sarl %ecx
movslq %ecx, %rdx
leaq (%rdx,%rdx,2), %rdx
movss 4(%rdi,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
jae .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
incl %ecx
movl %ecx, %eax
cmpl %esi, %eax
jne .LBB1_1
.LBB1_5: # %._crit_edge
# kill: def $eax killed $eax killed $rax
retq
.Lfunc_end1:
.size _Z16h_binarySearchUBP5entryfi, .Lfunc_end1-_Z16h_binarySearchUBP5entryfi
.cfi_endproc
# -- End function
.globl _Z22__device_stub__kernel1P5entryif # -- Begin function _Z22__device_stub__kernel1P5entryif
.p2align 4, 0x90
.type _Z22__device_stub__kernel1P5entryif,@function
_Z22__device_stub__kernel1P5entryif: # @_Z22__device_stub__kernel1P5entryif
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movss %xmm0, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7kernel1P5entryif, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z22__device_stub__kernel1P5entryif, .Lfunc_end2-_Z22__device_stub__kernel1P5entryif
.cfi_endproc
# -- End function
.globl _Z22__device_stub__kernel2P5entryi # -- Begin function _Z22__device_stub__kernel2P5entryi
.p2align 4, 0x90
.type _Z22__device_stub__kernel2P5entryi,@function
_Z22__device_stub__kernel2P5entryi: # @_Z22__device_stub__kernel2P5entryi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7kernel2P5entryi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z22__device_stub__kernel2P5entryi, .Lfunc_end3-_Z22__device_stub__kernel2P5entryi
.cfi_endproc
# -- End function
.globl _Z5mergeP5entryii # -- Begin function _Z5mergeP5entryii
.p2align 4, 0x90
.type _Z5mergeP5entryii,@function
_Z5mergeP5entryii: # @_Z5mergeP5entryii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movl %esi, %r15d
movq %rdi, %r14
leal (%rbx,%r15), %eax
movl %eax, %r13d
shrl $31, %r13d
addl %eax, %r13d
sarl %r13d
leal 1(%r13), %ebp
movl %edx, %eax
subl %esi, %eax
incl %eax
cltq
movl $12, %ecx
mulq %rcx
movq $-1, %rdi
cmovnoq %rax, %rdi
callq _Znam
xorl %r12d, %r12d
cmpl %r15d, %r13d
jl .LBB4_2
# %bb.1:
cmpl %ebx, %r13d
jge .LBB4_2
# %bb.10: # %.lr.ph.preheader
xorl %r12d, %r12d
movq %rax, %rcx
movl %r15d, %r11d
.p2align 4, 0x90
.LBB4_11: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movslq %r11d, %rsi
leaq (%rsi,%rsi,2), %rdi
movslq %ebp, %r9
leaq (%r9,%r9,2), %rdx
movss 4(%r14,%rdx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %edx, %edx
xorl %r8d, %r8d
ucomiss 4(%r14,%rdi,4), %xmm0
setbe %dil
seta %r10b
ja .LBB4_13
# %bb.12: # %.lr.ph
# in Loop: Header=BB4_11 Depth=1
movq %r9, %rsi
.LBB4_13: # %.lr.ph
# in Loop: Header=BB4_11 Depth=1
leaq (%rsi,%rsi,2), %rsi
movb %r10b, %r8b
addl %r8d, %r11d
movb %dil, %dl
addl %edx, %ebp
movl 8(%r14,%rsi,4), %edx
movl %edx, 8(%rcx)
movq (%r14,%rsi,4), %rdx
movq %rdx, (%rcx)
incl %r12d
cmpl %r13d, %r11d
jg .LBB4_3
# %bb.14: # %.lr.ph
# in Loop: Header=BB4_11 Depth=1
addq $12, %rcx
cmpl %ebx, %ebp
jle .LBB4_11
jmp .LBB4_3
.LBB4_2:
movl %r15d, %r11d
.LBB4_3: # %.preheader54
subl %r11d, %r13d
jl .LBB4_5
# %bb.4: # %.lr.ph63.preheader
movl %r12d, %ecx
leaq (%rcx,%rcx,2), %rcx
leaq (%rax,%rcx,4), %rdi
movslq %r11d, %rcx
leaq (%rcx,%rcx,2), %rcx
leaq (%r14,%rcx,4), %rsi
leaq (%r13,%r13,2), %rcx
leaq 12(,%rcx,4), %rdx
movq %r15, (%rsp) # 8-byte Spill
movq %rax, %r15
callq memcpy@PLT
movq %r15, %rax
movq (%rsp), %r15 # 8-byte Reload
addl %r13d, %r12d
incl %r12d
.LBB4_5: # %.preheader53
movl %ebx, %edx
subl %ebp, %edx
jl .LBB4_7
# %bb.6: # %.lr.ph68.preheader
movl %r12d, %ecx
leaq (%rcx,%rcx,2), %rcx
leaq (%rax,%rcx,4), %rdi
movslq %ebp, %rcx
leaq (%rcx,%rcx,2), %rcx
leaq (%r14,%rcx,4), %rsi
leaq (%rdx,%rdx,2), %rcx
leaq 12(,%rcx,4), %rdx
movq %r15, %r12
movq %rax, %r15
callq memcpy@PLT
movq %r15, %rax
movq %r12, %r15
.LBB4_7: # %.preheader
subl %r15d, %ebx
jl .LBB4_9
# %bb.8: # %.lr.ph71.preheader
movslq %r15d, %rcx
leaq (%rcx,%rcx,2), %rcx
leaq (%r14,%rcx,4), %rdi
leaq (%rbx,%rbx,2), %rcx
leaq 12(,%rcx,4), %rdx
movq %rax, %rsi
movq %rax, %rbx
callq memcpy@PLT
movq %rbx, %rax
.LBB4_9: # %._crit_edge
movq %rax, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp _ZdaPv # TAILCALL
.Lfunc_end4:
.size _Z5mergeP5entryii, .Lfunc_end4-_Z5mergeP5entryii
.cfi_endproc
# -- End function
.globl _Z9mergeSortP5entryii # -- Begin function _Z9mergeSortP5entryii
.p2align 4, 0x90
.type _Z9mergeSortP5entryii,@function
_Z9mergeSortP5entryii: # @_Z9mergeSortP5entryii
.cfi_startproc
# %bb.0:
cmpl %edx, %esi
jge .LBB5_1
# %bb.2:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movl %esi, %r14d
leal (%rbx,%r14), %eax
movl %eax, %ebp
shrl $31, %ebp
addl %eax, %ebp
sarl %ebp
movq %rdi, %r15
movl %ebp, %edx
callq _Z9mergeSortP5entryii
incl %ebp
movq %r15, %rdi
movl %ebp, %esi
movl %ebx, %edx
callq _Z9mergeSortP5entryii
movq %r15, %rdi
movl %r14d, %esi
movl %ebx, %edx
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp _Z5mergeP5entryii # TAILCALL
.LBB5_1: # %common.ret
.cfi_restore %rbx
.cfi_restore %rbp
.cfi_restore %r14
.cfi_restore %r15
retq
.Lfunc_end5:
.size _Z9mergeSortP5entryii, .Lfunc_end5-_Z9mergeSortP5entryii
.cfi_endproc
# -- End function
.globl _Z7smoothcPfS_S_if # -- Begin function _Z7smoothcPfS_S_if
.p2align 4, 0x90
.type _Z7smoothcPfS_S_if,@function
_Z7smoothcPfS_S_if: # @_Z7smoothcPfS_S_if
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movss %xmm0, 16(%rsp) # 4-byte Spill
# kill: def $ecx killed $ecx def $rcx
movq %rdx, %rbx
movq %rsi, %r13
movq %rdi, %rbp
movq %rcx, 24(%rsp) # 8-byte Spill
movslq %ecx, %r12
movl $12, %ecx
movq %r12, %rax
mulq %rcx
movq $-1, %rdi
cmovnoq %rax, %rdi
callq _Znam
movq %rax, %r14
testl %r12d, %r12d
jle .LBB6_3
# %bb.1: # %.lr.ph.preheader
movl 24(%rsp), %eax # 4-byte Reload
leaq 8(%r14), %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB6_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rbp,%rdx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%r13,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movl %edx, -8(%rcx)
movss %xmm0, -4(%rcx)
movss %xmm1, (%rcx)
incq %rdx
addq $12, %rcx
cmpq %rdx, %rax
jne .LBB6_2
.LBB6_3: # %._crit_edge
movq 24(%rsp), %r13 # 8-byte Reload
leal -1(%r13), %edx
movq %r14, %rdi
xorl %esi, %esi
callq _Z9mergeSortP5entryii
cmpl $83333333, %r13d # imm = 0x4F790D5
jae .LBB6_4
# %bb.9:
shlq $2, %r12
leaq (%r12,%r12,2), %r12
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r13d, %eax
shrl $10, %eax
movabsq $4294967297, %rdx # imm = 0x100000001
leaq (%rax,%rdx), %rdi
decq %rdi
addq $1023, %rdx # imm = 0x3FF
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_11
# %bb.10:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl %r13d, 20(%rsp)
movss 16(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 92(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 92(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7kernel1P5entryif, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_11:
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
testl %r13d, %r13d
je .LBB6_14
# %bb.12: # %.lr.ph118.preheader
cmpl $2, %r13d
movl $1, %eax
cmovgel %r13d, %eax
shlq $2, %rax
leaq (%rax,%rax,2), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB6_13: # %.lr.ph118
# =>This Inner Loop Header: Depth=1
movss 8(%r14,%rcx), %xmm0 # xmm0 = mem[0],zero,zero,zero
movslq (%r14,%rcx), %rdx
movss %xmm0, (%rbx,%rdx,4)
addq $12, %rcx
cmpq %rcx, %rax
jne .LBB6_13
.LBB6_14: # %._crit_edge119
movq 8(%rsp), %rdi
callq hipFree
jmp .LBB6_27
.LBB6_4: # %.preheader
testl %r13d, %r13d
jle .LBB6_27
# %bb.5: # %.lr.ph115
movl %r13d, %eax
movq %rax, 120(%rsp) # 8-byte Spill
xorl %eax, %eax
movq %rbx, 128(%rsp) # 8-byte Spill
jmp .LBB6_6
.p2align 4, 0x90
.LBB6_26: # in Loop: Header=BB6_6 Depth=1
movq 136(%rsp), %rax # 8-byte Reload
leaq (%r14,%rax,4), %rbx
movq 8(%rsp), %rsi
movq %rbp, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movss 8(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movslq (%rbx), %rax
movq 128(%rsp), %rbx # 8-byte Reload
movss %xmm0, (%rbx,%rax,4)
movq 8(%rsp), %rdi
callq hipFree
movq %rbp, %rdi
callq _ZdaPv
movq 144(%rsp), %rax # 8-byte Reload
incq %rax
cmpq 120(%rsp), %rax # 8-byte Folded Reload
movq 24(%rsp), %r13 # 8-byte Reload
je .LBB6_27
.LBB6_6: # =>This Loop Header: Depth=1
# Child Loop BB6_7 Depth 2
# Child Loop BB6_18 Depth 2
movq %rax, 144(%rsp) # 8-byte Spill
leaq (%rax,%rax,2), %rax
movq %rax, 136(%rsp) # 8-byte Spill
movss 4(%r14,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps %xmm0, %xmm1
subss 16(%rsp), %xmm1 # 4-byte Folded Reload
xorl %r15d, %r15d
movl %r13d, %eax
jmp .LBB6_7
.p2align 4, 0x90
.LBB6_15: # %.lr.ph.i
# in Loop: Header=BB6_7 Depth=2
incl %ecx
movl %ecx, %r15d
cmpl %eax, %r15d
je .LBB6_17
.LBB6_7: # %.lr.ph.i
# Parent Loop BB6_6 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rax,%r15), %edx
movl %edx, %ecx
shrl $31, %ecx
addl %edx, %ecx
sarl %ecx
movslq %ecx, %rdx
leaq (%rdx,%rdx,2), %rdx
ucomiss 4(%r14,%rdx,4), %xmm1
jae .LBB6_15
# %bb.8: # in Loop: Header=BB6_7 Depth=2
movl %ecx, %eax
cmpl %eax, %r15d
jne .LBB6_7
.LBB6_17: # %_Z16h_binarySearchLBP5entryfi.exit
# in Loop: Header=BB6_6 Depth=1
addss 16(%rsp), %xmm0 # 4-byte Folded Reload
xorl %r12d, %r12d
movl %r13d, %eax
jmp .LBB6_18
.p2align 4, 0x90
.LBB6_20: # %.lr.ph.i91
# in Loop: Header=BB6_18 Depth=2
movl %ecx, %eax
cmpl %eax, %r12d
je .LBB6_22
.LBB6_18: # %.lr.ph.i91
# Parent Loop BB6_6 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rax,%r12), %edx
movl %edx, %ecx
shrl $31, %ecx
addl %edx, %ecx
sarl %ecx
movslq %ecx, %rdx
leaq (%rdx,%rdx,2), %rdx
movss 4(%r14,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
jae .LBB6_20
# %bb.19: # in Loop: Header=BB6_18 Depth=2
incl %ecx
movl %ecx, %r12d
cmpl %eax, %r12d
jne .LBB6_18
.LBB6_22: # %_Z16h_binarySearchUBP5entryfi.exit
# in Loop: Header=BB6_6 Depth=1
movl %r12d, %ebx
subl %r15d, %ebx
movslq %ebx, %r13
movq %r13, %rax
movl $12, %ecx
mulq %rcx
movq $-1, %rcx
cmovoq %rcx, %rax
movq %rax, %rdi
callq _Znam
movq %rax, %rbp
testl %r13d, %r13d
jle .LBB6_24
# %bb.23: # %.lr.ph112.preheader
# in Loop: Header=BB6_6 Depth=1
movslq %r15d, %rax
leaq (%rax,%rax,2), %rax
leaq (%r14,%rax,4), %rsi
notl %r15d
addl %r15d, %r12d
leaq (%r12,%r12,2), %rax
leaq 12(,%rax,4), %rdx
movq %rbp, %rdi
callq memcpy@PLT
.LBB6_24: # %._crit_edge113
# in Loop: Header=BB6_6 Depth=1
shlq $2, %r13
leaq (%r13,%r13,2), %r13
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %rbp, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_26
# %bb.25: # in Loop: Header=BB6_6 Depth=1
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl %ebx, 20(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z7kernel2P5entryi, %edi
leaq 96(%rsp), %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB6_26
.LBB6_27: # %.loopexit
movq %r14, %rdi
callq _ZdaPv
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z7smoothcPfS_S_if, .Lfunc_end6-_Z7smoothcPfS_S_if
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernel1P5entryif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernel2P5entryi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7kernel1P5entryif,@object # @_Z7kernel1P5entryif
.section .rodata,"a",@progbits
.globl _Z7kernel1P5entryif
.p2align 3, 0x0
_Z7kernel1P5entryif:
.quad _Z22__device_stub__kernel1P5entryif
.size _Z7kernel1P5entryif, 8
.type _Z7kernel2P5entryi,@object # @_Z7kernel2P5entryi
.globl _Z7kernel2P5entryi
.p2align 3, 0x0
_Z7kernel2P5entryi:
.quad _Z22__device_stub__kernel2P5entryi
.size _Z7kernel2P5entryi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7kernel1P5entryif"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7kernel2P5entryi"
.size .L__unnamed_2, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__kernel1P5entryif
.addrsig_sym _Z22__device_stub__kernel2P5entryi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7kernel1P5entryif
.addrsig_sym _Z7kernel2P5entryi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#define SZ 8
__global__ void AplusB(int *ret, int a, int b) {
ret[threadIdx.x] = a + b + threadIdx.x;
}
int main() {
int *ret;
cudaMallocManaged(&ret, SZ * sizeof(int));
AplusB<<<1, SZ>>>(ret, 10, 100);
cudaDeviceSynchronize();
for (int i = 0; i < SZ; i++)
printf("%d: A+B = %d\n", i, ret[i]);
cudaFree(ret);
return 0;
} | code for sm_80
Function : _Z6AplusBPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IADD3 R0, R2, c[0x0][0x168], RZ ; /* 0x00005a0002007a10 */
/* 0x001fd00007ffe0ff */
/*0050*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe200078e0003 */
/*0060*/ IADD3 R5, R0, c[0x0][0x16c], RZ ; /* 0x00005b0000057a10 */
/* 0x000fca0007ffe0ff */
/*0070*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#define SZ 8
__global__ void AplusB(int *ret, int a, int b) {
ret[threadIdx.x] = a + b + threadIdx.x;
}
int main() {
int *ret;
cudaMallocManaged(&ret, SZ * sizeof(int));
AplusB<<<1, SZ>>>(ret, 10, 100);
cudaDeviceSynchronize();
for (int i = 0; i < SZ; i++)
printf("%d: A+B = %d\n", i, ret[i]);
cudaFree(ret);
return 0;
} | .file "tmpxft_000a69e6_00000000-6_unifMemCUDAexPart2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6AplusBPiiiPiii
.type _Z27__device_stub__Z6AplusBPiiiPiii, @function
_Z27__device_stub__Z6AplusBPiiiPiii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6AplusBPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z6AplusBPiiiPiii, .-_Z27__device_stub__Z6AplusBPiiiPiii
.globl _Z6AplusBPiii
.type _Z6AplusBPiii, @function
_Z6AplusBPiii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6AplusBPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6AplusBPiii, .-_Z6AplusBPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d: A+B = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $32, %esi
call cudaMallocManaged@PLT
movl $8, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L13:
movq 8(%rsp), %rax
movl (%rax,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $8, %rbx
jne .L13
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl $100, %edx
movl $10, %esi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z6AplusBPiiiPiii
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z6AplusBPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6AplusBPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#define SZ 8
__global__ void AplusB(int *ret, int a, int b) {
ret[threadIdx.x] = a + b + threadIdx.x;
}
int main() {
int *ret;
cudaMallocManaged(&ret, SZ * sizeof(int));
AplusB<<<1, SZ>>>(ret, 10, 100);
cudaDeviceSynchronize();
for (int i = 0; i < SZ; i++)
printf("%d: A+B = %d\n", i, ret[i]);
cudaFree(ret);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define SZ 8
__global__ void AplusB(int *ret, int a, int b) {
ret[threadIdx.x] = a + b + threadIdx.x;
}
int main() {
int *ret;
hipMallocManaged(&ret, SZ * sizeof(int));
AplusB<<<1, SZ>>>(ret, 10, 100);
hipDeviceSynchronize();
for (int i = 0; i < SZ; i++)
printf("%d: A+B = %d\n", i, ret[i]);
hipFree(ret);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define SZ 8
__global__ void AplusB(int *ret, int a, int b) {
ret[threadIdx.x] = a + b + threadIdx.x;
}
int main() {
int *ret;
hipMallocManaged(&ret, SZ * sizeof(int));
AplusB<<<1, SZ>>>(ret, 10, 100);
hipDeviceSynchronize();
for (int i = 0; i < SZ; i++)
printf("%d: A+B = %d\n", i, ret[i]);
hipFree(ret);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6AplusBPiii
.globl _Z6AplusBPiii
.p2align 8
.type _Z6AplusBPiii,@function
_Z6AplusBPiii:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add3_u32 v1, s3, s2, v0
v_lshlrev_b32_e32 v0, 2, v0
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6AplusBPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6AplusBPiii, .Lfunc_end0-_Z6AplusBPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6AplusBPiii
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z6AplusBPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define SZ 8
__global__ void AplusB(int *ret, int a, int b) {
ret[threadIdx.x] = a + b + threadIdx.x;
}
int main() {
int *ret;
hipMallocManaged(&ret, SZ * sizeof(int));
AplusB<<<1, SZ>>>(ret, 10, 100);
hipDeviceSynchronize();
for (int i = 0; i < SZ; i++)
printf("%d: A+B = %d\n", i, ret[i]);
hipFree(ret);
return 0;
} | .text
.file "unifMemCUDAexPart2.hip"
.globl _Z21__device_stub__AplusBPiii # -- Begin function _Z21__device_stub__AplusBPiii
.p2align 4, 0x90
.type _Z21__device_stub__AplusBPiii,@function
_Z21__device_stub__AplusBPiii: # @_Z21__device_stub__AplusBPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6AplusBPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__AplusBPiii, .Lfunc_end0-_Z21__device_stub__AplusBPiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $112, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -16
leaq 8(%rsp), %rdi
movl $32, %esi
movl $1, %edx
callq hipMallocManaged
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 7(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $10, 20(%rsp)
movl $100, 16(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6AplusBPiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rax
movl (%rax,%rbx,4), %edx
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $8, %rbx
jne .LBB1_3
# %bb.4:
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6AplusBPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6AplusBPiii,@object # @_Z6AplusBPiii
.section .rodata,"a",@progbits
.globl _Z6AplusBPiii
.p2align 3, 0x0
_Z6AplusBPiii:
.quad _Z21__device_stub__AplusBPiii
.size _Z6AplusBPiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d: A+B = %d\n"
.size .L.str, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6AplusBPiii"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__AplusBPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6AplusBPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6AplusBPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IADD3 R0, R2, c[0x0][0x168], RZ ; /* 0x00005a0002007a10 */
/* 0x001fd00007ffe0ff */
/*0050*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe200078e0003 */
/*0060*/ IADD3 R5, R0, c[0x0][0x16c], RZ ; /* 0x00005b0000057a10 */
/* 0x000fca0007ffe0ff */
/*0070*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6AplusBPiii
.globl _Z6AplusBPiii
.p2align 8
.type _Z6AplusBPiii,@function
_Z6AplusBPiii:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add3_u32 v1, s3, s2, v0
v_lshlrev_b32_e32 v0, 2, v0
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6AplusBPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6AplusBPiii, .Lfunc_end0-_Z6AplusBPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6AplusBPiii
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z6AplusBPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a69e6_00000000-6_unifMemCUDAexPart2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6AplusBPiiiPiii
.type _Z27__device_stub__Z6AplusBPiiiPiii, @function
_Z27__device_stub__Z6AplusBPiiiPiii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6AplusBPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z6AplusBPiiiPiii, .-_Z27__device_stub__Z6AplusBPiiiPiii
.globl _Z6AplusBPiii
.type _Z6AplusBPiii, @function
_Z6AplusBPiii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6AplusBPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6AplusBPiii, .-_Z6AplusBPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d: A+B = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $32, %esi
call cudaMallocManaged@PLT
movl $8, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L13:
movq 8(%rsp), %rax
movl (%rax,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $8, %rbx
jne .L13
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl $100, %edx
movl $10, %esi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z6AplusBPiiiPiii
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z6AplusBPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6AplusBPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "unifMemCUDAexPart2.hip"
.globl _Z21__device_stub__AplusBPiii # -- Begin function _Z21__device_stub__AplusBPiii
.p2align 4, 0x90
.type _Z21__device_stub__AplusBPiii,@function
_Z21__device_stub__AplusBPiii: # @_Z21__device_stub__AplusBPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6AplusBPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__AplusBPiii, .Lfunc_end0-_Z21__device_stub__AplusBPiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $112, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -16
leaq 8(%rsp), %rdi
movl $32, %esi
movl $1, %edx
callq hipMallocManaged
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 7(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $10, 20(%rsp)
movl $100, 16(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6AplusBPiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rax
movl (%rax,%rbx,4), %edx
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $8, %rbx
jne .LBB1_3
# %bb.4:
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6AplusBPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6AplusBPiii,@object # @_Z6AplusBPiii
.section .rodata,"a",@progbits
.globl _Z6AplusBPiii
.p2align 3, 0x0
_Z6AplusBPiii:
.quad _Z21__device_stub__AplusBPiii
.size _Z6AplusBPiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d: A+B = %d\n"
.size .L.str, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6AplusBPiii"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__AplusBPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6AplusBPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,float var_2,int var_3,int var_4,float var_5,float var_6,float var_7,float var_8,float* var_9,float var_10,float var_11,float var_12) {
for (int i=0; i < var_1; ++i) {
if (comp >= (var_2 / -1.0817E-36f)) {
comp = cosf(-1.9800E34f / (var_5 + ldexpf((-1.8078E-42f * +1.4986E-41f), 2)));
float tmp_1 = -1.4794E-35f;
float tmp_2 = -1.9424E-37f;
comp += tmp_2 / tmp_1 - (-1.3063E-18f - -1.0401E-35f * +1.2162E-43f - var_6);
if (comp >= +0.0f / var_7 / ceilf(+1.0071E-44f)) {
comp += log10f((+1.3650E-35f + var_8));
}
for (int i=0; i < var_3; ++i) {
comp += -1.2400E-37f + +1.4328E-42f;
var_9[i] = +1.6281E-15f;
float tmp_3 = +1.6286E36f;
comp = tmp_3 / var_9[i] * -1.9352E-41f * -1.4034E-44f + -1.6408E-13f + var_10 * +1.1786E7f;
}
for (int i=0; i < var_4; ++i) {
comp = (var_11 + var_12);
}
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
float tmp_3 = atof(argv[3]);
int tmp_4 = atoi(argv[4]);
int tmp_5 = atoi(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float* tmp_10 = initPointer( atof(argv[10]) );
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13);
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_0010608a_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z38__device_stub__Z7computefifiiffffPfffffifiiffffPffff
.type _Z38__device_stub__Z7computefifiiffffPfffffifiiffffPffff, @function
_Z38__device_stub__Z7computefifiiffffPfffffifiiffffPffff:
.LFB2083:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movss %xmm0, 60(%rsp)
movl %edi, 56(%rsp)
movss %xmm1, 52(%rsp)
movl %esi, 48(%rsp)
movl %edx, 44(%rsp)
movss %xmm2, 40(%rsp)
movss %xmm3, 36(%rsp)
movss %xmm4, 32(%rsp)
movss %xmm5, 28(%rsp)
movq %rcx, 16(%rsp)
movss %xmm6, 24(%rsp)
movss %xmm7, 12(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rax
movq %rax, 168(%rsp)
leaq 36(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 28(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 24(%rsp), %rax
movq %rax, 208(%rsp)
leaq 12(%rsp), %rax
movq %rax, 216(%rsp)
leaq 256(%rsp), %rax
movq %rax, 224(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 264
pushq 72(%rsp)
.cfi_def_cfa_offset 272
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z7computefifiiffffPffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z38__device_stub__Z7computefifiiffffPfffffifiiffffPffff, .-_Z38__device_stub__Z7computefifiiffffPfffffifiiffffPffff
.globl _Z7computefifiiffffPffff
.type _Z7computefifiiffffPffff, @function
_Z7computefifiiffffPffff:
.LFB2084:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movss 32(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z38__device_stub__Z7computefifiiffffPfffffifiiffffPffff
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefifiiffffPffff, .-_Z7computefifiiffffPffff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $112, %rsp
.cfi_def_cfa_offset 160
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 24(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 32(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movq 40(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r14
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 100(%rsp), %rdx
movl $1, %ecx
movq 88(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 72(%rsp), %xmm0
subq $16, %rsp
.cfi_def_cfa_offset 176
pxor %xmm1, %xmm1
cvtsd2ss 24(%rsp), %xmm1
movss %xmm1, (%rsp)
pxor %xmm7, %xmm7
cvtsd2ss 32(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 40(%rsp), %xmm6
movq %r14, %rcx
pxor %xmm5, %xmm5
cvtsd2ss 48(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 56(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 64(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtsd2ss 72(%rsp), %xmm2
movl %r13d, %edx
movl %r12d, %esi
pxor %xmm1, %xmm1
cvtsd2ss 80(%rsp), %xmm1
movl %ebp, %edi
call _Z38__device_stub__Z7computefifiiffffPfffffifiiffffPffff
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7computefifiiffffPffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefifiiffffPffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,float var_2,int var_3,int var_4,float var_5,float var_6,float var_7,float var_8,float* var_9,float var_10,float var_11,float var_12) {
for (int i=0; i < var_1; ++i) {
if (comp >= (var_2 / -1.0817E-36f)) {
comp = cosf(-1.9800E34f / (var_5 + ldexpf((-1.8078E-42f * +1.4986E-41f), 2)));
float tmp_1 = -1.4794E-35f;
float tmp_2 = -1.9424E-37f;
comp += tmp_2 / tmp_1 - (-1.3063E-18f - -1.0401E-35f * +1.2162E-43f - var_6);
if (comp >= +0.0f / var_7 / ceilf(+1.0071E-44f)) {
comp += log10f((+1.3650E-35f + var_8));
}
for (int i=0; i < var_3; ++i) {
comp += -1.2400E-37f + +1.4328E-42f;
var_9[i] = +1.6281E-15f;
float tmp_3 = +1.6286E36f;
comp = tmp_3 / var_9[i] * -1.9352E-41f * -1.4034E-44f + -1.6408E-13f + var_10 * +1.1786E7f;
}
for (int i=0; i < var_4; ++i) {
comp = (var_11 + var_12);
}
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
float tmp_3 = atof(argv[3]);
int tmp_4 = atoi(argv[4]);
int tmp_5 = atoi(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float* tmp_10 = initPointer( atof(argv[10]) );
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13);
cudaDeviceSynchronize();
return 0;
} | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,float var_2,int var_3,int var_4,float var_5,float var_6,float var_7,float var_8,float* var_9,float var_10,float var_11,float var_12) {
for (int i=0; i < var_1; ++i) {
if (comp >= (var_2 / -1.0817E-36f)) {
comp = cosf(-1.9800E34f / (var_5 + ldexpf((-1.8078E-42f * +1.4986E-41f), 2)));
float tmp_1 = -1.4794E-35f;
float tmp_2 = -1.9424E-37f;
comp += tmp_2 / tmp_1 - (-1.3063E-18f - -1.0401E-35f * +1.2162E-43f - var_6);
if (comp >= +0.0f / var_7 / ceilf(+1.0071E-44f)) {
comp += log10f((+1.3650E-35f + var_8));
}
for (int i=0; i < var_3; ++i) {
comp += -1.2400E-37f + +1.4328E-42f;
var_9[i] = +1.6281E-15f;
float tmp_3 = +1.6286E36f;
comp = tmp_3 / var_9[i] * -1.9352E-41f * -1.4034E-44f + -1.6408E-13f + var_10 * +1.1786E7f;
}
for (int i=0; i < var_4; ++i) {
comp = (var_11 + var_12);
}
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
float tmp_3 = atof(argv[3]);
int tmp_4 = atoi(argv[4]);
int tmp_5 = atoi(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float* tmp_10 = initPointer( atof(argv[10]) );
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13);
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,float var_2,int var_3,int var_4,float var_5,float var_6,float var_7,float var_8,float* var_9,float var_10,float var_11,float var_12) {
for (int i=0; i < var_1; ++i) {
if (comp >= (var_2 / -1.0817E-36f)) {
comp = cosf(-1.9800E34f / (var_5 + ldexpf((-1.8078E-42f * +1.4986E-41f), 2)));
float tmp_1 = -1.4794E-35f;
float tmp_2 = -1.9424E-37f;
comp += tmp_2 / tmp_1 - (-1.3063E-18f - -1.0401E-35f * +1.2162E-43f - var_6);
if (comp >= +0.0f / var_7 / ceilf(+1.0071E-44f)) {
comp += log10f((+1.3650E-35f + var_8));
}
for (int i=0; i < var_3; ++i) {
comp += -1.2400E-37f + +1.4328E-42f;
var_9[i] = +1.6281E-15f;
float tmp_3 = +1.6286E36f;
comp = tmp_3 / var_9[i] * -1.9352E-41f * -1.4034E-44f + -1.6408E-13f + var_10 * +1.1786E7f;
}
for (int i=0; i < var_4; ++i) {
comp = (var_11 + var_12);
}
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
float tmp_3 = atof(argv[3]);
int tmp_4 = atoi(argv[4]);
int tmp_5 = atoi(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float* tmp_10 = initPointer( atof(argv[10]) );
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13);
hipDeviceSynchronize();
return 0;
} | .text
.file "test.hip"
.globl _Z22__device_stub__computefifiiffffPffff # -- Begin function _Z22__device_stub__computefifiiffffPffff
.p2align 4, 0x90
.type _Z22__device_stub__computefifiiffffPffff,@function
_Z22__device_stub__computefifiiffffPffff: # @_Z22__device_stub__computefifiiffffPffff
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movss %xmm0, 52(%rsp)
movl %edi, 48(%rsp)
movss %xmm1, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movss %xmm2, 32(%rsp)
movss %xmm3, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 20(%rsp)
movq %rcx, 104(%rsp)
movss %xmm6, 16(%rsp)
movss %xmm7, 12(%rsp)
leaq 52(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rax
movq %rax, 120(%rsp)
leaq 44(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rax
movq %rax, 136(%rsp)
leaq 36(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 28(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 20(%rsp), %rax
movq %rax, 176(%rsp)
leaq 104(%rsp), %rax
movq %rax, 184(%rsp)
leaq 16(%rsp), %rax
movq %rax, 192(%rsp)
leaq 12(%rsp), %rax
movq %rax, 200(%rsp)
leaq 224(%rsp), %rax
movq %rax, 208(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z7computefifiiffffPffff, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end0:
.size _Z22__device_stub__computefifiiffffPffff, .Lfunc_end0-_Z22__device_stub__computefifiiffffPffff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 336
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r15
movq 8(%rsi), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
callq strtod
movsd %xmm0, 112(%rsp) # 8-byte Spill
movq 16(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 24(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 104(%rsp) # 8-byte Spill
movq 32(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 40(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movq 48(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 96(%rsp) # 8-byte Spill
movq 56(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 88(%rsp) # 8-byte Spill
movq 64(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 80(%rsp) # 8-byte Spill
movq 72(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 72(%rsp) # 8-byte Spill
movq 80(%r15), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss (%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %r13
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%r13,%rbp,4)
incq %rbp
cmpq $10, %rbp
jne .LBB2_1
# %bb.2: # %_Z11initPointerf.exit
movq 88(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, (%rsp) # 8-byte Spill
movq 96(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 64(%rsp) # 8-byte Spill
movq 104(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 56(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movsd 56(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movsd 64(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
cvtsd2ss %xmm1, %xmm1
movsd (%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
cvtsd2ss %xmm2, %xmm2
movsd 72(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
cvtsd2ss %xmm3, %xmm3
movsd 80(%rsp), %xmm4 # 8-byte Reload
# xmm4 = mem[0],zero
cvtsd2ss %xmm4, %xmm4
movsd 88(%rsp), %xmm5 # 8-byte Reload
# xmm5 = mem[0],zero
cvtsd2ss %xmm5, %xmm5
movsd 96(%rsp), %xmm6 # 8-byte Reload
# xmm6 = mem[0],zero
cvtsd2ss %xmm6, %xmm6
movsd 104(%rsp), %xmm7 # 8-byte Reload
# xmm7 = mem[0],zero
cvtsd2ss %xmm7, %xmm7
movsd 112(%rsp), %xmm8 # 8-byte Reload
# xmm8 = mem[0],zero
cvtsd2ss %xmm8, %xmm8
movss %xmm8, 52(%rsp)
movl %ebx, 48(%rsp)
movss %xmm7, 44(%rsp)
movl %r14d, 40(%rsp)
movl %r12d, 36(%rsp)
movss %xmm6, 32(%rsp)
movss %xmm5, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm3, 20(%rsp)
movq %r13, 168(%rsp)
movss %xmm2, 16(%rsp)
movss %xmm1, 12(%rsp)
movss %xmm0, 8(%rsp)
leaq 52(%rsp), %rax
movq %rax, 176(%rsp)
leaq 48(%rsp), %rax
movq %rax, 184(%rsp)
leaq 44(%rsp), %rax
movq %rax, 192(%rsp)
leaq 40(%rsp), %rax
movq %rax, 200(%rsp)
leaq 36(%rsp), %rax
movq %rax, 208(%rsp)
leaq 32(%rsp), %rax
movq %rax, 216(%rsp)
leaq 28(%rsp), %rax
movq %rax, 224(%rsp)
leaq 24(%rsp), %rax
movq %rax, 232(%rsp)
leaq 20(%rsp), %rax
movq %rax, 240(%rsp)
leaq 168(%rsp), %rax
movq %rax, 248(%rsp)
leaq 16(%rsp), %rax
movq %rax, 256(%rsp)
leaq 12(%rsp), %rax
movq %rax, 264(%rsp)
leaq 8(%rsp), %rax
movq %rax, 272(%rsp)
leaq 152(%rsp), %rdi
leaq 136(%rsp), %rsi
leaq 128(%rsp), %rdx
leaq 120(%rsp), %rcx
callq __hipPopCallConfiguration
movq 152(%rsp), %rsi
movl 160(%rsp), %edx
movq 136(%rsp), %rcx
movl 144(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z7computefifiiffffPffff, %edi
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefifiiffffPffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefifiiffffPffff,@object # @_Z7computefifiiffffPffff
.section .rodata,"a",@progbits
.globl _Z7computefifiiffffPffff
.p2align 3, 0x0
_Z7computefifiiffffPffff:
.quad _Z22__device_stub__computefifiiffffPffff
.size _Z7computefifiiffffPffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefifiiffffPffff"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefifiiffffPffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefifiiffffPffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010608a_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z38__device_stub__Z7computefifiiffffPfffffifiiffffPffff
.type _Z38__device_stub__Z7computefifiiffffPfffffifiiffffPffff, @function
_Z38__device_stub__Z7computefifiiffffPfffffifiiffffPffff:
.LFB2083:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movss %xmm0, 60(%rsp)
movl %edi, 56(%rsp)
movss %xmm1, 52(%rsp)
movl %esi, 48(%rsp)
movl %edx, 44(%rsp)
movss %xmm2, 40(%rsp)
movss %xmm3, 36(%rsp)
movss %xmm4, 32(%rsp)
movss %xmm5, 28(%rsp)
movq %rcx, 16(%rsp)
movss %xmm6, 24(%rsp)
movss %xmm7, 12(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rax
movq %rax, 168(%rsp)
leaq 36(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 28(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 24(%rsp), %rax
movq %rax, 208(%rsp)
leaq 12(%rsp), %rax
movq %rax, 216(%rsp)
leaq 256(%rsp), %rax
movq %rax, 224(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 264
pushq 72(%rsp)
.cfi_def_cfa_offset 272
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z7computefifiiffffPffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z38__device_stub__Z7computefifiiffffPfffffifiiffffPffff, .-_Z38__device_stub__Z7computefifiiffffPfffffifiiffffPffff
.globl _Z7computefifiiffffPffff
.type _Z7computefifiiffffPffff, @function
_Z7computefifiiffffPffff:
.LFB2084:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movss 32(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z38__device_stub__Z7computefifiiffffPfffffifiiffffPffff
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefifiiffffPffff, .-_Z7computefifiiffffPffff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $112, %rsp
.cfi_def_cfa_offset 160
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 24(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 32(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movq 40(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r14
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 100(%rsp), %rdx
movl $1, %ecx
movq 88(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 72(%rsp), %xmm0
subq $16, %rsp
.cfi_def_cfa_offset 176
pxor %xmm1, %xmm1
cvtsd2ss 24(%rsp), %xmm1
movss %xmm1, (%rsp)
pxor %xmm7, %xmm7
cvtsd2ss 32(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 40(%rsp), %xmm6
movq %r14, %rcx
pxor %xmm5, %xmm5
cvtsd2ss 48(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 56(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 64(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtsd2ss 72(%rsp), %xmm2
movl %r13d, %edx
movl %r12d, %esi
pxor %xmm1, %xmm1
cvtsd2ss 80(%rsp), %xmm1
movl %ebp, %edi
call _Z38__device_stub__Z7computefifiiffffPfffffifiiffffPffff
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7computefifiiffffPffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefifiiffffPffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.globl _Z22__device_stub__computefifiiffffPffff # -- Begin function _Z22__device_stub__computefifiiffffPffff
.p2align 4, 0x90
.type _Z22__device_stub__computefifiiffffPffff,@function
_Z22__device_stub__computefifiiffffPffff: # @_Z22__device_stub__computefifiiffffPffff
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movss %xmm0, 52(%rsp)
movl %edi, 48(%rsp)
movss %xmm1, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movss %xmm2, 32(%rsp)
movss %xmm3, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 20(%rsp)
movq %rcx, 104(%rsp)
movss %xmm6, 16(%rsp)
movss %xmm7, 12(%rsp)
leaq 52(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rax
movq %rax, 120(%rsp)
leaq 44(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rax
movq %rax, 136(%rsp)
leaq 36(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 28(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 20(%rsp), %rax
movq %rax, 176(%rsp)
leaq 104(%rsp), %rax
movq %rax, 184(%rsp)
leaq 16(%rsp), %rax
movq %rax, 192(%rsp)
leaq 12(%rsp), %rax
movq %rax, 200(%rsp)
leaq 224(%rsp), %rax
movq %rax, 208(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z7computefifiiffffPffff, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end0:
.size _Z22__device_stub__computefifiiffffPffff, .Lfunc_end0-_Z22__device_stub__computefifiiffffPffff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 336
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r15
movq 8(%rsi), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
callq strtod
movsd %xmm0, 112(%rsp) # 8-byte Spill
movq 16(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 24(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 104(%rsp) # 8-byte Spill
movq 32(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 40(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movq 48(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 96(%rsp) # 8-byte Spill
movq 56(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 88(%rsp) # 8-byte Spill
movq 64(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 80(%rsp) # 8-byte Spill
movq 72(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 72(%rsp) # 8-byte Spill
movq 80(%r15), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss (%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %r13
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%r13,%rbp,4)
incq %rbp
cmpq $10, %rbp
jne .LBB2_1
# %bb.2: # %_Z11initPointerf.exit
movq 88(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, (%rsp) # 8-byte Spill
movq 96(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 64(%rsp) # 8-byte Spill
movq 104(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 56(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movsd 56(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movsd 64(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
cvtsd2ss %xmm1, %xmm1
movsd (%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
cvtsd2ss %xmm2, %xmm2
movsd 72(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
cvtsd2ss %xmm3, %xmm3
movsd 80(%rsp), %xmm4 # 8-byte Reload
# xmm4 = mem[0],zero
cvtsd2ss %xmm4, %xmm4
movsd 88(%rsp), %xmm5 # 8-byte Reload
# xmm5 = mem[0],zero
cvtsd2ss %xmm5, %xmm5
movsd 96(%rsp), %xmm6 # 8-byte Reload
# xmm6 = mem[0],zero
cvtsd2ss %xmm6, %xmm6
movsd 104(%rsp), %xmm7 # 8-byte Reload
# xmm7 = mem[0],zero
cvtsd2ss %xmm7, %xmm7
movsd 112(%rsp), %xmm8 # 8-byte Reload
# xmm8 = mem[0],zero
cvtsd2ss %xmm8, %xmm8
movss %xmm8, 52(%rsp)
movl %ebx, 48(%rsp)
movss %xmm7, 44(%rsp)
movl %r14d, 40(%rsp)
movl %r12d, 36(%rsp)
movss %xmm6, 32(%rsp)
movss %xmm5, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm3, 20(%rsp)
movq %r13, 168(%rsp)
movss %xmm2, 16(%rsp)
movss %xmm1, 12(%rsp)
movss %xmm0, 8(%rsp)
leaq 52(%rsp), %rax
movq %rax, 176(%rsp)
leaq 48(%rsp), %rax
movq %rax, 184(%rsp)
leaq 44(%rsp), %rax
movq %rax, 192(%rsp)
leaq 40(%rsp), %rax
movq %rax, 200(%rsp)
leaq 36(%rsp), %rax
movq %rax, 208(%rsp)
leaq 32(%rsp), %rax
movq %rax, 216(%rsp)
leaq 28(%rsp), %rax
movq %rax, 224(%rsp)
leaq 24(%rsp), %rax
movq %rax, 232(%rsp)
leaq 20(%rsp), %rax
movq %rax, 240(%rsp)
leaq 168(%rsp), %rax
movq %rax, 248(%rsp)
leaq 16(%rsp), %rax
movq %rax, 256(%rsp)
leaq 12(%rsp), %rax
movq %rax, 264(%rsp)
leaq 8(%rsp), %rax
movq %rax, 272(%rsp)
leaq 152(%rsp), %rdi
leaq 136(%rsp), %rsi
leaq 128(%rsp), %rdx
leaq 120(%rsp), %rcx
callq __hipPopCallConfiguration
movq 152(%rsp), %rsi
movl 160(%rsp), %edx
movq 136(%rsp), %rcx
movl 144(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z7computefifiiffffPffff, %edi
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefifiiffffPffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefifiiffffPffff,@object # @_Z7computefifiiffffPffff
.section .rodata,"a",@progbits
.globl _Z7computefifiiffffPffff
.p2align 3, 0x0
_Z7computefifiiffffPffff:
.quad _Z22__device_stub__computefifiiffffPffff
.size _Z7computefifiiffffPffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefifiiffffPffff"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefifiiffffPffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefifiiffffPffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_runtime.h>
#define NUM_BITS 2
#define DEBUG 1
__device__ void dispArr(int *arr, int n) {
int i;
//threadId with in a block, DMat doc to start with
int thId = threadIdx.x;
if (thId == 0) {
printf("\n");
for (i = 0; i < n; i++) {
printf(" %d ", arr[i]);
}
printf("\n");
}
}
//scan array arr of size n=nThreads, power of 2
__device__ void preSubScan(int *arr, int n, int prev) {
int i, d, ai, bi, offset, temp;
//threadId with in a block, DMat doc to start with
int thId = threadIdx.x;
//number of threads in blocks
int nThreads = blockDim.x;
d = 0;
offset = 1;
//build sum in place up the tree
for (d = n>>1; d > 0; d >>=1) {
__syncthreads();
if (thId < d) {
ai = offset*(2*thId+1) - 1;
bi = offset*(2*thId+2) - 1;
arr[bi] += arr[ai];
}
offset*=2;
}
//clear last element
if (thId == 0) {
arr[n-1] = 0;
}
//traverse down tree & build scan
for (int d = 1; d < n; d *=2) {
offset = offset >> 1;
__syncthreads();
if (thId < d) {
ai = offset*(2*thId + 1) - 1;
bi = offset*(2*thId + 2) - 1;
temp = arr[ai];
arr[ai] = arr[bi];
arr[bi] += temp;
}
}
for (i = thId; i < n; i+=nThreads) {
arr[i] += prev;
}
__syncthreads();
}
//works efficiently for power of 2
__device__ void scan(int *arr, int n) {
int i, j, prev, next, temp;
//threadId with in a block, DMat doc to start with
int thId = threadIdx.x;
//number of threads in blocks
int nThreads = blockDim.x;
//divide the simpred into nThreads blocks,
//scan each block in parallel, with next iteration using results from prev blocks
prev = 0;
next = 0;
for (i = 0; i < n; i += nThreads) {
dispArr(arr, n);
next = 0;
if (i+nThreads-1 < n)
next = arr[i+nThreads-1];
if (n - i >= nThreads) {
if (thId == 0) {
printf("\ncalling presub scan i=%d nThreads=%d", i, nThreads);
}
preSubScan(arr + i, nThreads, (i>0?arr[i-1]:0) + prev);
} else {
//not power of 2 perform serial scan for others
//this will be last iteration of loop
if (thId == 0) {
printf("\ndoing naive scan i=%d nThreads=%d", i, nThreads);
dispArr(arr, n);
for (j = i; j < n; j++) {
if (j > 0)
temp = prev + arr[j-1];
else
temp = prev;
prev = arr[j];
arr[j] = temp;
printf("\ntemp=%d prev=%d arr[%d]=%d", temp, prev, j, arr[j]);
}
dispArr(arr, n);
}
}//end else
prev = next;
}//end for
__syncthreads();
}
__device__ void d_dispFArr(float *arr, int n) {
int i;
//threadId with in a block, DMat doc to start with
int thId = threadIdx.x;
if (thId == 0) {
printf("\n");
for (i = 0; i < n; i++) {
printf(" %f ", arr[i]);
}
printf("\n");
}
}
//assuming sizeof int == sizeof float
__device__ void computeAtomicHisto(int *aggHisto, float *arrElem, int numElem,
int numBits, int bitpos) {
int i, j;
int numBuckets = 1 << numBits;
int mask = (1 << numBits) - 1;
int key;
void *vptr;
int *iptr;
//thread id within a block
int threadId = threadIdx.x;
//number of threads in block
int nThreads = blockDim.x;
for (i = threadId; i < numElem; i+=nThreads) {
vptr = (void*)(arrElem + i);
iptr = (int*)vptr;
key = ( (*iptr) >> bitpos) & mask;
atomicAdd(&(aggHisto[key]), 1);
}
}
//assuming sizeof int == sizeof float
__device__ void writeSortedVals(int *aggHisto, float *fromKeys, float *toKeys,
int *fromVals, int *toVals,
int numBits, int bitpos, int n) {
int i, key;
int mask = (1 << numBits) - 1;
void *vptr;
int *iptr;
for (i = 0; i < n; i++) {
vptr = (void*)(fromKeys + i);
iptr = (int*)vptr;
key = ( (*iptr) >> bitpos) & mask;
if (DEBUG) {
printf("toKeys[%d] = %f\n", aggHisto[key], fromKeys[i]);
}
toKeys[aggHisto[key]] = fromKeys[i];
toVals[aggHisto[key]] = fromVals[i];
aggHisto[key]++;
}
}
__device__ void zeroedInt(int *arr, int count) {
int i;
//thread id within a block
int threadId = threadIdx.x;
//number of threads in block
int nThreads = blockDim.x;
for (i = threadId; i < count; i+=nThreads) {
arr[i] = 0;
}
}
//shared mem space for aggregated histogram
//numbits means bits at a time
__device__ void radixSort(float *fromKeys, float *toKeys,
int *fromVals, int *toVals,
int *aggHisto,
int n, int numBits) {
int i, j, elemPerThread;
//get current block number
int blockId = blockIdx.x;
//thread id within a block
int threadId = threadIdx.x;
//number of threads in block
int nThreads = blockDim.x;
//global thread id
int globalThreadId = blockIdx.x * blockDim.x + threadIdx.x;
//shared mem space to copy array to be sorted
float *tempFSwap;
int *tempISwap;
//bucket size
int bucketSize = 1 << numBits;
if (threadId == 0 && DEBUG) {
printf("\n fromKeys: ");
d_dispFArr(fromKeys, n);
}
//for each numbits chunk do following
for (i = 0; i < sizeof(float)*8; i+=numBits) {
if (threadId == 0 && DEBUG) {
printf("\n fromKeys b4 zeroed histo : ");
d_dispFArr(fromKeys, n);
}
//reset histogram
zeroedInt(aggHisto, bucketSize);
if (threadId == 0 && DEBUG) {
printf("\n fromKeys b4 histo : ");
d_dispFArr(fromKeys, n);
}
//aggregate in histogram in shared mem
computeAtomicHisto(aggHisto, fromKeys, n,
numBits, i);
if (threadId == 0 && DEBUG) {
printf("\naggHisto, bitpos:%d:", i);
dispArr(aggHisto, bucketSize);
printf("\n fromKey after histo : ");
d_dispFArr(fromKeys, n);
}
//perform scan on aggHisto (assuming power of 2)
scan(aggHisto, bucketSize);
if (threadId == 0 && DEBUG) {
printf("\naggHisto after scan, bitpos:%d:", i);
dispArr(aggHisto, bucketSize);
}
__syncthreads();
if (threadId == 0) {
//copy values to correct output by a single thread
writeSortedVals(aggHisto, fromKeys, toKeys,
fromVals, toVals,
numBits, i, n);
}
__syncthreads();
if (threadId == 0 && DEBUG) {
printf("\n sorted toKeys: ");
d_dispFArr(toKeys, n);
}
//toKeys contains the sorted arr, for the next iteration point fromKeys to this location
tempFSwap = toKeys;
toKeys = fromKeys;
fromKeys = tempFSwap;
if (threadId == 0 && DEBUG) {
printf("\n after swap toKeys: ");
d_dispFArr(toKeys, n);
printf("\n after swap fromKeys: ");
d_dispFArr(fromKeys, n);
}
//toVals contains the sorted vals by keys,
//for the next iteration point fromVals to this location
tempISwap = toVals;
toVals = fromVals;
fromVals = tempISwap;
}
//at this point fromKeys and fromVal will contain sorted arr in mem
}
__global__ void testRadixSort(float *d_keys, int *d_vals, int n) {
int i, j;
extern __shared__ int s[];
int numBits = NUM_BITS;
//thread id within a block
int thId = threadIdx.x;
//number of threads in block
int nThreads = blockDim.x;
int *fromVals = s;
float *fromKeys = (float *)&d_keys[n];
int *toVals = (int *)&fromKeys[n];
float *toKeys = (float *)&toVals[n];
int *aggHisto = (int *)&toKeys[n];
//copy keys and val to shared mem
for (i = thId; i < n; i+=nThreads) {
fromKeys[i] = d_keys[i];
fromVals[i] = d_vals[i];
}
radixSort(fromKeys, toKeys, fromVals, toVals, aggHisto, n, numBits);
//copy sorted values back
for (i = thId; i < n; i+=nThreads) {
d_keys[i] = fromKeys[i];
d_vals[i] = fromVals[i];
}
}
int main(int argc, char *argv[]) {
float h_fKeys[] = {1.0, 0.4, 0.316228, 0.365148, 0.670820, 0.447214, 0.258199, 0.4,
0.258199, 0.316228, 0.258199, 0.258199, 0.258199, 0.258199,
0.258199, 0.258199};
int h_iVal[] = {0, 53, 54, 81, 98, 195, 283, 583, 598, 615, 654, 690, 768, 904, 919,
946};
/*
float h_fKeys[] = {1.0, 0.4, 0.316228, 0.365148, 0.670820};
int h_iVal[] = {0, 53, 54, 81, 98 };
float h_fKeys[] = {1.0, 0.4, 0.3, 0.2, 0.6};
int h_iVal[] = {0, 53, 54, 81, 98 };
*/
int n = 16;
int i;
int numBits = NUM_BITS;
float *d_keys;
int *d_val;
cudaMalloc((void **) &d_keys, sizeof(float)*n);
cudaMemcpy((void *) d_keys, (void *) h_fKeys, sizeof(float)*n, cudaMemcpyHostToDevice );
cudaMalloc((void **) &d_val, sizeof(int)*n);
cudaMemcpy((void *) d_val, (void *) h_iVal, sizeof(int)*n, cudaMemcpyHostToDevice );
testRadixSort<<<1, 128,
sizeof(int)*(2*n + (1<<numBits))
+ sizeof(float)*(2*n)>>>(d_keys, d_val, n);
cudaMemcpy((void *) h_iVal, (void *) d_val, sizeof(int)*n, cudaMemcpyDeviceToHost );
cudaMemcpy((void *) h_fKeys, (void *) d_keys, sizeof(float)*n, cudaMemcpyDeviceToHost );
printf("\n");
for (i = 0; i < n; i++) {
printf(" %f %d, ", h_fKeys[i], h_iVal[i]);
}
printf("\n");
return 0;
} | .file "tmpxft_001791c1_00000000-6_testRadixSort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2068:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7dispArrPii
.type _Z7dispArrPii, @function
_Z7dispArrPii:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z7dispArrPii, .-_Z7dispArrPii
.globl _Z10preSubScanPiii
.type _Z10preSubScanPiii, @function
_Z10preSubScanPiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z10preSubScanPiii, .-_Z10preSubScanPiii
.globl _Z4scanPii
.type _Z4scanPii, @function
_Z4scanPii:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z4scanPii, .-_Z4scanPii
.globl _Z10d_dispFArrPfi
.type _Z10d_dispFArrPfi, @function
_Z10d_dispFArrPfi:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z10d_dispFArrPfi, .-_Z10d_dispFArrPfi
.globl _Z18computeAtomicHistoPiPfiii
.type _Z18computeAtomicHistoPiPfiii, @function
_Z18computeAtomicHistoPiPfiii:
.LFB2061:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z18computeAtomicHistoPiPfiii, .-_Z18computeAtomicHistoPiPfiii
.globl _Z15writeSortedValsPiPfS0_S_S_iii
.type _Z15writeSortedValsPiPfS0_S_S_iii, @function
_Z15writeSortedValsPiPfS0_S_S_iii:
.LFB2062:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2062:
.size _Z15writeSortedValsPiPfS0_S_S_iii, .-_Z15writeSortedValsPiPfS0_S_S_iii
.globl _Z9zeroedIntPii
.type _Z9zeroedIntPii, @function
_Z9zeroedIntPii:
.LFB2063:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2063:
.size _Z9zeroedIntPii, .-_Z9zeroedIntPii
.globl _Z9radixSortPfS_PiS0_S0_ii
.type _Z9radixSortPfS_PiS0_S0_ii, @function
_Z9radixSortPfS_PiS0_S0_ii:
.LFB2064:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2064:
.size _Z9radixSortPfS_PiS0_S0_ii, .-_Z9radixSortPfS_PiS0_S0_ii
.globl _Z36__device_stub__Z13testRadixSortPfPiiPfPii
.type _Z36__device_stub__Z13testRadixSortPfPiiPfPii, @function
_Z36__device_stub__Z13testRadixSortPfPiiPfPii:
.LFB2090:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13testRadixSortPfPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z36__device_stub__Z13testRadixSortPfPiiPfPii, .-_Z36__device_stub__Z13testRadixSortPfPiiPfPii
.globl _Z13testRadixSortPfPii
.type _Z13testRadixSortPfPii, @function
_Z13testRadixSortPfPii:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13testRadixSortPfPiiPfPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z13testRadixSortPfPii, .-_Z13testRadixSortPfPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC7:
.string "\n"
.LC8:
.string " %f %d, "
.text
.globl main
.type main, @function
main:
.LFB2065:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $200, %rsp
.cfi_def_cfa_offset 224
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
movl $0x3f800000, 48(%rsp)
movss .LC1(%rip), %xmm2
movss %xmm2, 52(%rsp)
movss .LC2(%rip), %xmm1
movss %xmm1, 56(%rsp)
movl $0x3ebaf4ae, 60(%rsp)
movl $0x3f2bbadc, 64(%rsp)
movl $0x3ee4f93c, 68(%rsp)
movss .LC6(%rip), %xmm0
movss %xmm0, 72(%rsp)
movss %xmm2, 76(%rsp)
movss %xmm0, 80(%rsp)
movss %xmm1, 84(%rsp)
movss %xmm0, 88(%rsp)
movss %xmm0, 92(%rsp)
movss %xmm0, 96(%rsp)
movss %xmm0, 100(%rsp)
movss %xmm0, 104(%rsp)
movss %xmm0, 108(%rsp)
movl $0, 112(%rsp)
movl $53, 116(%rsp)
movl $54, 120(%rsp)
movl $81, 124(%rsp)
movl $98, 128(%rsp)
movl $195, 132(%rsp)
movl $283, 136(%rsp)
movl $583, 140(%rsp)
movl $598, 144(%rsp)
movl $615, 148(%rsp)
movl $654, 152(%rsp)
movl $690, 156(%rsp)
movl $768, 160(%rsp)
movl $904, 164(%rsp)
movl $919, 168(%rsp)
movl $946, 172(%rsp)
leaq 8(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 112(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $272, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L28:
leaq 112(%rsp), %rdi
movl $2, %ecx
movl $64, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq 48(%rsp), %rdi
movl $2, %ecx
movl $64, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC8(%rip), %rbp
.L29:
movl 112(%rsp,%rbx), %edx
pxor %xmm0, %xmm0
cvtss2sd 48(%rsp,%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $64, %rbx
jne .L29
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movl $16, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z36__device_stub__Z13testRadixSortPfPiiPfPii
jmp .L28
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2065:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z13testRadixSortPfPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z13testRadixSortPfPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1053609165
.align 4
.LC2:
.long 1050798243
.align 4
.LC6:
.long 1048851113
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime.h>
#define NUM_BITS 2
#define DEBUG 1
__device__ void dispArr(int *arr, int n) {
int i;
//threadId with in a block, DMat doc to start with
int thId = threadIdx.x;
if (thId == 0) {
printf("\n");
for (i = 0; i < n; i++) {
printf(" %d ", arr[i]);
}
printf("\n");
}
}
//scan array arr of size n=nThreads, power of 2
__device__ void preSubScan(int *arr, int n, int prev) {
int i, d, ai, bi, offset, temp;
//threadId with in a block, DMat doc to start with
int thId = threadIdx.x;
//number of threads in blocks
int nThreads = blockDim.x;
d = 0;
offset = 1;
//build sum in place up the tree
for (d = n>>1; d > 0; d >>=1) {
__syncthreads();
if (thId < d) {
ai = offset*(2*thId+1) - 1;
bi = offset*(2*thId+2) - 1;
arr[bi] += arr[ai];
}
offset*=2;
}
//clear last element
if (thId == 0) {
arr[n-1] = 0;
}
//traverse down tree & build scan
for (int d = 1; d < n; d *=2) {
offset = offset >> 1;
__syncthreads();
if (thId < d) {
ai = offset*(2*thId + 1) - 1;
bi = offset*(2*thId + 2) - 1;
temp = arr[ai];
arr[ai] = arr[bi];
arr[bi] += temp;
}
}
for (i = thId; i < n; i+=nThreads) {
arr[i] += prev;
}
__syncthreads();
}
//works efficiently for power of 2
__device__ void scan(int *arr, int n) {
int i, j, prev, next, temp;
//threadId with in a block, DMat doc to start with
int thId = threadIdx.x;
//number of threads in blocks
int nThreads = blockDim.x;
//divide the simpred into nThreads blocks,
//scan each block in parallel, with next iteration using results from prev blocks
prev = 0;
next = 0;
for (i = 0; i < n; i += nThreads) {
dispArr(arr, n);
next = 0;
if (i+nThreads-1 < n)
next = arr[i+nThreads-1];
if (n - i >= nThreads) {
if (thId == 0) {
printf("\ncalling presub scan i=%d nThreads=%d", i, nThreads);
}
preSubScan(arr + i, nThreads, (i>0?arr[i-1]:0) + prev);
} else {
//not power of 2 perform serial scan for others
//this will be last iteration of loop
if (thId == 0) {
printf("\ndoing naive scan i=%d nThreads=%d", i, nThreads);
dispArr(arr, n);
for (j = i; j < n; j++) {
if (j > 0)
temp = prev + arr[j-1];
else
temp = prev;
prev = arr[j];
arr[j] = temp;
printf("\ntemp=%d prev=%d arr[%d]=%d", temp, prev, j, arr[j]);
}
dispArr(arr, n);
}
}//end else
prev = next;
}//end for
__syncthreads();
}
__device__ void d_dispFArr(float *arr, int n) {
int i;
//threadId with in a block, DMat doc to start with
int thId = threadIdx.x;
if (thId == 0) {
printf("\n");
for (i = 0; i < n; i++) {
printf(" %f ", arr[i]);
}
printf("\n");
}
}
//assuming sizeof int == sizeof float
__device__ void computeAtomicHisto(int *aggHisto, float *arrElem, int numElem,
int numBits, int bitpos) {
int i, j;
int numBuckets = 1 << numBits;
int mask = (1 << numBits) - 1;
int key;
void *vptr;
int *iptr;
//thread id within a block
int threadId = threadIdx.x;
//number of threads in block
int nThreads = blockDim.x;
for (i = threadId; i < numElem; i+=nThreads) {
vptr = (void*)(arrElem + i);
iptr = (int*)vptr;
key = ( (*iptr) >> bitpos) & mask;
atomicAdd(&(aggHisto[key]), 1);
}
}
//assuming sizeof int == sizeof float
__device__ void writeSortedVals(int *aggHisto, float *fromKeys, float *toKeys,
int *fromVals, int *toVals,
int numBits, int bitpos, int n) {
int i, key;
int mask = (1 << numBits) - 1;
void *vptr;
int *iptr;
for (i = 0; i < n; i++) {
vptr = (void*)(fromKeys + i);
iptr = (int*)vptr;
key = ( (*iptr) >> bitpos) & mask;
if (DEBUG) {
printf("toKeys[%d] = %f\n", aggHisto[key], fromKeys[i]);
}
toKeys[aggHisto[key]] = fromKeys[i];
toVals[aggHisto[key]] = fromVals[i];
aggHisto[key]++;
}
}
__device__ void zeroedInt(int *arr, int count) {
int i;
//thread id within a block
int threadId = threadIdx.x;
//number of threads in block
int nThreads = blockDim.x;
for (i = threadId; i < count; i+=nThreads) {
arr[i] = 0;
}
}
//shared mem space for aggregated histogram
//numbits means bits at a time
__device__ void radixSort(float *fromKeys, float *toKeys,
int *fromVals, int *toVals,
int *aggHisto,
int n, int numBits) {
int i, j, elemPerThread;
//get current block number
int blockId = blockIdx.x;
//thread id within a block
int threadId = threadIdx.x;
//number of threads in block
int nThreads = blockDim.x;
//global thread id
int globalThreadId = blockIdx.x * blockDim.x + threadIdx.x;
//shared mem space to copy array to be sorted
float *tempFSwap;
int *tempISwap;
//bucket size
int bucketSize = 1 << numBits;
if (threadId == 0 && DEBUG) {
printf("\n fromKeys: ");
d_dispFArr(fromKeys, n);
}
//for each numbits chunk do following
for (i = 0; i < sizeof(float)*8; i+=numBits) {
if (threadId == 0 && DEBUG) {
printf("\n fromKeys b4 zeroed histo : ");
d_dispFArr(fromKeys, n);
}
//reset histogram
zeroedInt(aggHisto, bucketSize);
if (threadId == 0 && DEBUG) {
printf("\n fromKeys b4 histo : ");
d_dispFArr(fromKeys, n);
}
//aggregate in histogram in shared mem
computeAtomicHisto(aggHisto, fromKeys, n,
numBits, i);
if (threadId == 0 && DEBUG) {
printf("\naggHisto, bitpos:%d:", i);
dispArr(aggHisto, bucketSize);
printf("\n fromKey after histo : ");
d_dispFArr(fromKeys, n);
}
//perform scan on aggHisto (assuming power of 2)
scan(aggHisto, bucketSize);
if (threadId == 0 && DEBUG) {
printf("\naggHisto after scan, bitpos:%d:", i);
dispArr(aggHisto, bucketSize);
}
__syncthreads();
if (threadId == 0) {
//copy values to correct output by a single thread
writeSortedVals(aggHisto, fromKeys, toKeys,
fromVals, toVals,
numBits, i, n);
}
__syncthreads();
if (threadId == 0 && DEBUG) {
printf("\n sorted toKeys: ");
d_dispFArr(toKeys, n);
}
//toKeys contains the sorted arr, for the next iteration point fromKeys to this location
tempFSwap = toKeys;
toKeys = fromKeys;
fromKeys = tempFSwap;
if (threadId == 0 && DEBUG) {
printf("\n after swap toKeys: ");
d_dispFArr(toKeys, n);
printf("\n after swap fromKeys: ");
d_dispFArr(fromKeys, n);
}
//toVals contains the sorted vals by keys,
//for the next iteration point fromVals to this location
tempISwap = toVals;
toVals = fromVals;
fromVals = tempISwap;
}
//at this point fromKeys and fromVal will contain sorted arr in mem
}
__global__ void testRadixSort(float *d_keys, int *d_vals, int n) {
int i, j;
extern __shared__ int s[];
int numBits = NUM_BITS;
//thread id within a block
int thId = threadIdx.x;
//number of threads in block
int nThreads = blockDim.x;
int *fromVals = s;
float *fromKeys = (float *)&d_keys[n];
int *toVals = (int *)&fromKeys[n];
float *toKeys = (float *)&toVals[n];
int *aggHisto = (int *)&toKeys[n];
//copy keys and val to shared mem
for (i = thId; i < n; i+=nThreads) {
fromKeys[i] = d_keys[i];
fromVals[i] = d_vals[i];
}
radixSort(fromKeys, toKeys, fromVals, toVals, aggHisto, n, numBits);
//copy sorted values back
for (i = thId; i < n; i+=nThreads) {
d_keys[i] = fromKeys[i];
d_vals[i] = fromVals[i];
}
}
int main(int argc, char *argv[]) {
float h_fKeys[] = {1.0, 0.4, 0.316228, 0.365148, 0.670820, 0.447214, 0.258199, 0.4,
0.258199, 0.316228, 0.258199, 0.258199, 0.258199, 0.258199,
0.258199, 0.258199};
int h_iVal[] = {0, 53, 54, 81, 98, 195, 283, 583, 598, 615, 654, 690, 768, 904, 919,
946};
/*
float h_fKeys[] = {1.0, 0.4, 0.316228, 0.365148, 0.670820};
int h_iVal[] = {0, 53, 54, 81, 98 };
float h_fKeys[] = {1.0, 0.4, 0.3, 0.2, 0.6};
int h_iVal[] = {0, 53, 54, 81, 98 };
*/
int n = 16;
int i;
int numBits = NUM_BITS;
float *d_keys;
int *d_val;
cudaMalloc((void **) &d_keys, sizeof(float)*n);
cudaMemcpy((void *) d_keys, (void *) h_fKeys, sizeof(float)*n, cudaMemcpyHostToDevice );
cudaMalloc((void **) &d_val, sizeof(int)*n);
cudaMemcpy((void *) d_val, (void *) h_iVal, sizeof(int)*n, cudaMemcpyHostToDevice );
testRadixSort<<<1, 128,
sizeof(int)*(2*n + (1<<numBits))
+ sizeof(float)*(2*n)>>>(d_keys, d_val, n);
cudaMemcpy((void *) h_iVal, (void *) d_val, sizeof(int)*n, cudaMemcpyDeviceToHost );
cudaMemcpy((void *) h_fKeys, (void *) d_keys, sizeof(float)*n, cudaMemcpyDeviceToHost );
printf("\n");
for (i = 0; i < n; i++) {
printf(" %f %d, ", h_fKeys[i], h_iVal[i]);
}
printf("\n");
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#define NUM_BITS 2
#define DEBUG 1
__device__ void dispArr(int *arr, int n) {
int i;
//threadId with in a block, DMat doc to start with
int thId = threadIdx.x;
if (thId == 0) {
printf("\n");
for (i = 0; i < n; i++) {
printf(" %d ", arr[i]);
}
printf("\n");
}
}
//scan array arr of size n=nThreads, power of 2
__device__ void preSubScan(int *arr, int n, int prev) {
int i, d, ai, bi, offset, temp;
//threadId with in a block, DMat doc to start with
int thId = threadIdx.x;
//number of threads in blocks
int nThreads = blockDim.x;
d = 0;
offset = 1;
//build sum in place up the tree
for (d = n>>1; d > 0; d >>=1) {
__syncthreads();
if (thId < d) {
ai = offset*(2*thId+1) - 1;
bi = offset*(2*thId+2) - 1;
arr[bi] += arr[ai];
}
offset*=2;
}
//clear last element
if (thId == 0) {
arr[n-1] = 0;
}
//traverse down tree & build scan
for (int d = 1; d < n; d *=2) {
offset = offset >> 1;
__syncthreads();
if (thId < d) {
ai = offset*(2*thId + 1) - 1;
bi = offset*(2*thId + 2) - 1;
temp = arr[ai];
arr[ai] = arr[bi];
arr[bi] += temp;
}
}
for (i = thId; i < n; i+=nThreads) {
arr[i] += prev;
}
__syncthreads();
}
//works efficiently for power of 2
__device__ void scan(int *arr, int n) {
int i, j, prev, next, temp;
//threadId with in a block, DMat doc to start with
int thId = threadIdx.x;
//number of threads in blocks
int nThreads = blockDim.x;
//divide the simpred into nThreads blocks,
//scan each block in parallel, with next iteration using results from prev blocks
prev = 0;
next = 0;
for (i = 0; i < n; i += nThreads) {
dispArr(arr, n);
next = 0;
if (i+nThreads-1 < n)
next = arr[i+nThreads-1];
if (n - i >= nThreads) {
if (thId == 0) {
printf("\ncalling presub scan i=%d nThreads=%d", i, nThreads);
}
preSubScan(arr + i, nThreads, (i>0?arr[i-1]:0) + prev);
} else {
//not power of 2 perform serial scan for others
//this will be last iteration of loop
if (thId == 0) {
printf("\ndoing naive scan i=%d nThreads=%d", i, nThreads);
dispArr(arr, n);
for (j = i; j < n; j++) {
if (j > 0)
temp = prev + arr[j-1];
else
temp = prev;
prev = arr[j];
arr[j] = temp;
printf("\ntemp=%d prev=%d arr[%d]=%d", temp, prev, j, arr[j]);
}
dispArr(arr, n);
}
}//end else
prev = next;
}//end for
__syncthreads();
}
__device__ void d_dispFArr(float *arr, int n) {
int i;
//threadId with in a block, DMat doc to start with
int thId = threadIdx.x;
if (thId == 0) {
printf("\n");
for (i = 0; i < n; i++) {
printf(" %f ", arr[i]);
}
printf("\n");
}
}
//assuming sizeof int == sizeof float
__device__ void computeAtomicHisto(int *aggHisto, float *arrElem, int numElem,
int numBits, int bitpos) {
int i, j;
int numBuckets = 1 << numBits;
int mask = (1 << numBits) - 1;
int key;
void *vptr;
int *iptr;
//thread id within a block
int threadId = threadIdx.x;
//number of threads in block
int nThreads = blockDim.x;
for (i = threadId; i < numElem; i+=nThreads) {
vptr = (void*)(arrElem + i);
iptr = (int*)vptr;
key = ( (*iptr) >> bitpos) & mask;
atomicAdd(&(aggHisto[key]), 1);
}
}
//assuming sizeof int == sizeof float
__device__ void writeSortedVals(int *aggHisto, float *fromKeys, float *toKeys,
int *fromVals, int *toVals,
int numBits, int bitpos, int n) {
int i, key;
int mask = (1 << numBits) - 1;
void *vptr;
int *iptr;
for (i = 0; i < n; i++) {
vptr = (void*)(fromKeys + i);
iptr = (int*)vptr;
key = ( (*iptr) >> bitpos) & mask;
if (DEBUG) {
printf("toKeys[%d] = %f\n", aggHisto[key], fromKeys[i]);
}
toKeys[aggHisto[key]] = fromKeys[i];
toVals[aggHisto[key]] = fromVals[i];
aggHisto[key]++;
}
}
__device__ void zeroedInt(int *arr, int count) {
int i;
//thread id within a block
int threadId = threadIdx.x;
//number of threads in block
int nThreads = blockDim.x;
for (i = threadId; i < count; i+=nThreads) {
arr[i] = 0;
}
}
//shared mem space for aggregated histogram
//numbits means bits at a time
__device__ void radixSort(float *fromKeys, float *toKeys,
int *fromVals, int *toVals,
int *aggHisto,
int n, int numBits) {
int i, j, elemPerThread;
//get current block number
int blockId = blockIdx.x;
//thread id within a block
int threadId = threadIdx.x;
//number of threads in block
int nThreads = blockDim.x;
//global thread id
int globalThreadId = blockIdx.x * blockDim.x + threadIdx.x;
//shared mem space to copy array to be sorted
float *tempFSwap;
int *tempISwap;
//bucket size
int bucketSize = 1 << numBits;
if (threadId == 0 && DEBUG) {
printf("\n fromKeys: ");
d_dispFArr(fromKeys, n);
}
//for each numbits chunk do following
for (i = 0; i < sizeof(float)*8; i+=numBits) {
if (threadId == 0 && DEBUG) {
printf("\n fromKeys b4 zeroed histo : ");
d_dispFArr(fromKeys, n);
}
//reset histogram
zeroedInt(aggHisto, bucketSize);
if (threadId == 0 && DEBUG) {
printf("\n fromKeys b4 histo : ");
d_dispFArr(fromKeys, n);
}
//aggregate in histogram in shared mem
computeAtomicHisto(aggHisto, fromKeys, n,
numBits, i);
if (threadId == 0 && DEBUG) {
printf("\naggHisto, bitpos:%d:", i);
dispArr(aggHisto, bucketSize);
printf("\n fromKey after histo : ");
d_dispFArr(fromKeys, n);
}
//perform scan on aggHisto (assuming power of 2)
scan(aggHisto, bucketSize);
if (threadId == 0 && DEBUG) {
printf("\naggHisto after scan, bitpos:%d:", i);
dispArr(aggHisto, bucketSize);
}
__syncthreads();
if (threadId == 0) {
//copy values to correct output by a single thread
writeSortedVals(aggHisto, fromKeys, toKeys,
fromVals, toVals,
numBits, i, n);
}
__syncthreads();
if (threadId == 0 && DEBUG) {
printf("\n sorted toKeys: ");
d_dispFArr(toKeys, n);
}
//toKeys contains the sorted arr, for the next iteration point fromKeys to this location
tempFSwap = toKeys;
toKeys = fromKeys;
fromKeys = tempFSwap;
if (threadId == 0 && DEBUG) {
printf("\n after swap toKeys: ");
d_dispFArr(toKeys, n);
printf("\n after swap fromKeys: ");
d_dispFArr(fromKeys, n);
}
//toVals contains the sorted vals by keys,
//for the next iteration point fromVals to this location
tempISwap = toVals;
toVals = fromVals;
fromVals = tempISwap;
}
//at this point fromKeys and fromVal will contain sorted arr in mem
}
__global__ void testRadixSort(float *d_keys, int *d_vals, int n) {
int i, j;
extern __shared__ int s[];
int numBits = NUM_BITS;
//thread id within a block
int thId = threadIdx.x;
//number of threads in block
int nThreads = blockDim.x;
int *fromVals = s;
float *fromKeys = (float *)&d_keys[n];
int *toVals = (int *)&fromKeys[n];
float *toKeys = (float *)&toVals[n];
int *aggHisto = (int *)&toKeys[n];
//copy keys and val to shared mem
for (i = thId; i < n; i+=nThreads) {
fromKeys[i] = d_keys[i];
fromVals[i] = d_vals[i];
}
radixSort(fromKeys, toKeys, fromVals, toVals, aggHisto, n, numBits);
//copy sorted values back
for (i = thId; i < n; i+=nThreads) {
d_keys[i] = fromKeys[i];
d_vals[i] = fromVals[i];
}
}
int main(int argc, char *argv[]) {
float h_fKeys[] = {1.0, 0.4, 0.316228, 0.365148, 0.670820, 0.447214, 0.258199, 0.4,
0.258199, 0.316228, 0.258199, 0.258199, 0.258199, 0.258199,
0.258199, 0.258199};
int h_iVal[] = {0, 53, 54, 81, 98, 195, 283, 583, 598, 615, 654, 690, 768, 904, 919,
946};
/*
float h_fKeys[] = {1.0, 0.4, 0.316228, 0.365148, 0.670820};
int h_iVal[] = {0, 53, 54, 81, 98 };
float h_fKeys[] = {1.0, 0.4, 0.3, 0.2, 0.6};
int h_iVal[] = {0, 53, 54, 81, 98 };
*/
int n = 16;
int i;
int numBits = NUM_BITS;
float *d_keys;
int *d_val;
hipMalloc((void **) &d_keys, sizeof(float)*n);
hipMemcpy((void *) d_keys, (void *) h_fKeys, sizeof(float)*n, hipMemcpyHostToDevice );
hipMalloc((void **) &d_val, sizeof(int)*n);
hipMemcpy((void *) d_val, (void *) h_iVal, sizeof(int)*n, hipMemcpyHostToDevice );
testRadixSort<<<1, 128,
sizeof(int)*(2*n + (1<<numBits))
+ sizeof(float)*(2*n)>>>(d_keys, d_val, n);
hipMemcpy((void *) h_iVal, (void *) d_val, sizeof(int)*n, hipMemcpyDeviceToHost );
hipMemcpy((void *) h_fKeys, (void *) d_keys, sizeof(float)*n, hipMemcpyDeviceToHost );
printf("\n");
for (i = 0; i < n; i++) {
printf(" %f %d, ", h_fKeys[i], h_iVal[i]);
}
printf("\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#define NUM_BITS 2
#define DEBUG 1
__device__ void dispArr(int *arr, int n) {
int i;
//threadId with in a block, DMat doc to start with
int thId = threadIdx.x;
if (thId == 0) {
printf("\n");
for (i = 0; i < n; i++) {
printf(" %d ", arr[i]);
}
printf("\n");
}
}
//scan array arr of size n=nThreads, power of 2
__device__ void preSubScan(int *arr, int n, int prev) {
int i, d, ai, bi, offset, temp;
//threadId with in a block, DMat doc to start with
int thId = threadIdx.x;
//number of threads in blocks
int nThreads = blockDim.x;
d = 0;
offset = 1;
//build sum in place up the tree
for (d = n>>1; d > 0; d >>=1) {
__syncthreads();
if (thId < d) {
ai = offset*(2*thId+1) - 1;
bi = offset*(2*thId+2) - 1;
arr[bi] += arr[ai];
}
offset*=2;
}
//clear last element
if (thId == 0) {
arr[n-1] = 0;
}
//traverse down tree & build scan
for (int d = 1; d < n; d *=2) {
offset = offset >> 1;
__syncthreads();
if (thId < d) {
ai = offset*(2*thId + 1) - 1;
bi = offset*(2*thId + 2) - 1;
temp = arr[ai];
arr[ai] = arr[bi];
arr[bi] += temp;
}
}
for (i = thId; i < n; i+=nThreads) {
arr[i] += prev;
}
__syncthreads();
}
//works efficiently for power of 2
__device__ void scan(int *arr, int n) {
int i, j, prev, next, temp;
//threadId with in a block, DMat doc to start with
int thId = threadIdx.x;
//number of threads in blocks
int nThreads = blockDim.x;
//divide the simpred into nThreads blocks,
//scan each block in parallel, with next iteration using results from prev blocks
prev = 0;
next = 0;
for (i = 0; i < n; i += nThreads) {
dispArr(arr, n);
next = 0;
if (i+nThreads-1 < n)
next = arr[i+nThreads-1];
if (n - i >= nThreads) {
if (thId == 0) {
printf("\ncalling presub scan i=%d nThreads=%d", i, nThreads);
}
preSubScan(arr + i, nThreads, (i>0?arr[i-1]:0) + prev);
} else {
//not power of 2 perform serial scan for others
//this will be last iteration of loop
if (thId == 0) {
printf("\ndoing naive scan i=%d nThreads=%d", i, nThreads);
dispArr(arr, n);
for (j = i; j < n; j++) {
if (j > 0)
temp = prev + arr[j-1];
else
temp = prev;
prev = arr[j];
arr[j] = temp;
printf("\ntemp=%d prev=%d arr[%d]=%d", temp, prev, j, arr[j]);
}
dispArr(arr, n);
}
}//end else
prev = next;
}//end for
__syncthreads();
}
__device__ void d_dispFArr(float *arr, int n) {
int i;
//threadId with in a block, DMat doc to start with
int thId = threadIdx.x;
if (thId == 0) {
printf("\n");
for (i = 0; i < n; i++) {
printf(" %f ", arr[i]);
}
printf("\n");
}
}
//assuming sizeof int == sizeof float
__device__ void computeAtomicHisto(int *aggHisto, float *arrElem, int numElem,
int numBits, int bitpos) {
int i, j;
int numBuckets = 1 << numBits;
int mask = (1 << numBits) - 1;
int key;
void *vptr;
int *iptr;
//thread id within a block
int threadId = threadIdx.x;
//number of threads in block
int nThreads = blockDim.x;
for (i = threadId; i < numElem; i+=nThreads) {
vptr = (void*)(arrElem + i);
iptr = (int*)vptr;
key = ( (*iptr) >> bitpos) & mask;
atomicAdd(&(aggHisto[key]), 1);
}
}
//assuming sizeof int == sizeof float
__device__ void writeSortedVals(int *aggHisto, float *fromKeys, float *toKeys,
int *fromVals, int *toVals,
int numBits, int bitpos, int n) {
int i, key;
int mask = (1 << numBits) - 1;
void *vptr;
int *iptr;
for (i = 0; i < n; i++) {
vptr = (void*)(fromKeys + i);
iptr = (int*)vptr;
key = ( (*iptr) >> bitpos) & mask;
if (DEBUG) {
printf("toKeys[%d] = %f\n", aggHisto[key], fromKeys[i]);
}
toKeys[aggHisto[key]] = fromKeys[i];
toVals[aggHisto[key]] = fromVals[i];
aggHisto[key]++;
}
}
__device__ void zeroedInt(int *arr, int count) {
int i;
//thread id within a block
int threadId = threadIdx.x;
//number of threads in block
int nThreads = blockDim.x;
for (i = threadId; i < count; i+=nThreads) {
arr[i] = 0;
}
}
//shared mem space for aggregated histogram
//numbits means bits at a time
__device__ void radixSort(float *fromKeys, float *toKeys,
int *fromVals, int *toVals,
int *aggHisto,
int n, int numBits) {
int i, j, elemPerThread;
//get current block number
int blockId = blockIdx.x;
//thread id within a block
int threadId = threadIdx.x;
//number of threads in block
int nThreads = blockDim.x;
//global thread id
int globalThreadId = blockIdx.x * blockDim.x + threadIdx.x;
//shared mem space to copy array to be sorted
float *tempFSwap;
int *tempISwap;
//bucket size
int bucketSize = 1 << numBits;
if (threadId == 0 && DEBUG) {
printf("\n fromKeys: ");
d_dispFArr(fromKeys, n);
}
//for each numbits chunk do following
for (i = 0; i < sizeof(float)*8; i+=numBits) {
if (threadId == 0 && DEBUG) {
printf("\n fromKeys b4 zeroed histo : ");
d_dispFArr(fromKeys, n);
}
//reset histogram
zeroedInt(aggHisto, bucketSize);
if (threadId == 0 && DEBUG) {
printf("\n fromKeys b4 histo : ");
d_dispFArr(fromKeys, n);
}
//aggregate in histogram in shared mem
computeAtomicHisto(aggHisto, fromKeys, n,
numBits, i);
if (threadId == 0 && DEBUG) {
printf("\naggHisto, bitpos:%d:", i);
dispArr(aggHisto, bucketSize);
printf("\n fromKey after histo : ");
d_dispFArr(fromKeys, n);
}
//perform scan on aggHisto (assuming power of 2)
scan(aggHisto, bucketSize);
if (threadId == 0 && DEBUG) {
printf("\naggHisto after scan, bitpos:%d:", i);
dispArr(aggHisto, bucketSize);
}
__syncthreads();
if (threadId == 0) {
//copy values to correct output by a single thread
writeSortedVals(aggHisto, fromKeys, toKeys,
fromVals, toVals,
numBits, i, n);
}
__syncthreads();
if (threadId == 0 && DEBUG) {
printf("\n sorted toKeys: ");
d_dispFArr(toKeys, n);
}
//toKeys contains the sorted arr, for the next iteration point fromKeys to this location
tempFSwap = toKeys;
toKeys = fromKeys;
fromKeys = tempFSwap;
if (threadId == 0 && DEBUG) {
printf("\n after swap toKeys: ");
d_dispFArr(toKeys, n);
printf("\n after swap fromKeys: ");
d_dispFArr(fromKeys, n);
}
//toVals contains the sorted vals by keys,
//for the next iteration point fromVals to this location
tempISwap = toVals;
toVals = fromVals;
fromVals = tempISwap;
}
//at this point fromKeys and fromVal will contain sorted arr in mem
}
__global__ void testRadixSort(float *d_keys, int *d_vals, int n) {
int i, j;
extern __shared__ int s[];
int numBits = NUM_BITS;
//thread id within a block
int thId = threadIdx.x;
//number of threads in block
int nThreads = blockDim.x;
int *fromVals = s;
float *fromKeys = (float *)&d_keys[n];
int *toVals = (int *)&fromKeys[n];
float *toKeys = (float *)&toVals[n];
int *aggHisto = (int *)&toKeys[n];
//copy keys and val to shared mem
for (i = thId; i < n; i+=nThreads) {
fromKeys[i] = d_keys[i];
fromVals[i] = d_vals[i];
}
radixSort(fromKeys, toKeys, fromVals, toVals, aggHisto, n, numBits);
//copy sorted values back
for (i = thId; i < n; i+=nThreads) {
d_keys[i] = fromKeys[i];
d_vals[i] = fromVals[i];
}
}
int main(int argc, char *argv[]) {
float h_fKeys[] = {1.0, 0.4, 0.316228, 0.365148, 0.670820, 0.447214, 0.258199, 0.4,
0.258199, 0.316228, 0.258199, 0.258199, 0.258199, 0.258199,
0.258199, 0.258199};
int h_iVal[] = {0, 53, 54, 81, 98, 195, 283, 583, 598, 615, 654, 690, 768, 904, 919,
946};
/*
float h_fKeys[] = {1.0, 0.4, 0.316228, 0.365148, 0.670820};
int h_iVal[] = {0, 53, 54, 81, 98 };
float h_fKeys[] = {1.0, 0.4, 0.3, 0.2, 0.6};
int h_iVal[] = {0, 53, 54, 81, 98 };
*/
int n = 16;
int i;
int numBits = NUM_BITS;
float *d_keys;
int *d_val;
hipMalloc((void **) &d_keys, sizeof(float)*n);
hipMemcpy((void *) d_keys, (void *) h_fKeys, sizeof(float)*n, hipMemcpyHostToDevice );
hipMalloc((void **) &d_val, sizeof(int)*n);
hipMemcpy((void *) d_val, (void *) h_iVal, sizeof(int)*n, hipMemcpyHostToDevice );
testRadixSort<<<1, 128,
sizeof(int)*(2*n + (1<<numBits))
+ sizeof(float)*(2*n)>>>(d_keys, d_val, n);
hipMemcpy((void *) h_iVal, (void *) d_val, sizeof(int)*n, hipMemcpyDeviceToHost );
hipMemcpy((void *) h_fKeys, (void *) d_keys, sizeof(float)*n, hipMemcpyDeviceToHost );
printf("\n");
for (i = 0; i < n; i++) {
printf(" %f %d, ", h_fKeys[i], h_iVal[i]);
}
printf("\n");
return 0;
} | .text
.file "testRadixSort.hip"
.globl _Z28__device_stub__testRadixSortPfPii # -- Begin function _Z28__device_stub__testRadixSortPfPii
.p2align 4, 0x90
.type _Z28__device_stub__testRadixSortPfPii,@function
_Z28__device_stub__testRadixSortPfPii: # @_Z28__device_stub__testRadixSortPfPii
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13testRadixSortPfPii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__testRadixSortPfPii, .Lfunc_end0-_Z28__device_stub__testRadixSortPfPii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3f800000 # float 1
.long 0x3ecccccd # float 0.400000006
.long 0x3ea1e8a3 # float 0.316228002
.long 0x3ebaf4ae # float 0.365148008
.LCPI1_1:
.long 0x3f2bbadc # float 0.670819998
.long 0x3ee4f93c # float 0.447214007
.long 0x3e8432a9 # float 0.258199006
.long 0x3ecccccd # float 0.400000006
.LCPI1_2:
.long 0x3e8432a9 # float 0.258199006
.long 0x3ea1e8a3 # float 0.316228002
.long 0x3e8432a9 # float 0.258199006
.long 0x3e8432a9 # float 0.258199006
.LCPI1_3:
.long 0x3e8432a9 # float 0.258199006
.long 0x3e8432a9 # float 0.258199006
.long 0x3e8432a9 # float 0.258199006
.long 0x3e8432a9 # float 0.258199006
.LCPI1_4:
.long 0 # 0x0
.long 53 # 0x35
.long 54 # 0x36
.long 81 # 0x51
.LCPI1_5:
.long 98 # 0x62
.long 195 # 0xc3
.long 283 # 0x11b
.long 583 # 0x247
.LCPI1_6:
.long 598 # 0x256
.long 615 # 0x267
.long 654 # 0x28e
.long 690 # 0x2b2
.LCPI1_7:
.long 768 # 0x300
.long 904 # 0x388
.long 919 # 0x397
.long 946 # 0x3b2
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $256, %rsp # imm = 0x100
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -16
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [1.0E+0,4.00000006E-1,3.16228002E-1,3.65148008E-1]
movaps %xmm0, 192(%rsp)
movaps .LCPI1_1(%rip), %xmm0 # xmm0 = [6.70819998E-1,4.47214007E-1,2.58199006E-1,4.00000006E-1]
movaps %xmm0, 208(%rsp)
movaps .LCPI1_2(%rip), %xmm0 # xmm0 = [2.58199006E-1,3.16228002E-1,2.58199006E-1,2.58199006E-1]
movaps %xmm0, 224(%rsp)
movaps .LCPI1_3(%rip), %xmm0 # xmm0 = [2.58199006E-1,2.58199006E-1,2.58199006E-1,2.58199006E-1]
movaps %xmm0, 240(%rsp)
movaps .LCPI1_4(%rip), %xmm0 # xmm0 = [0,53,54,81]
movaps %xmm0, 128(%rsp)
movaps .LCPI1_5(%rip), %xmm0 # xmm0 = [98,195,283,583]
movaps %xmm0, 144(%rsp)
movaps .LCPI1_6(%rip), %xmm0 # xmm0 = [598,615,654,690]
movaps %xmm0, 160(%rsp)
movaps .LCPI1_7(%rip), %xmm0 # xmm0 = [768,904,919,946]
movaps %xmm0, 176(%rsp)
leaq 16(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 192(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 127(%rdi), %rdx
movl $272, %r8d # imm = 0x110
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $16, 28(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13testRadixSortPfPii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 128(%rsp), %rdi
movl $64, %edx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rsi
leaq 192(%rsp), %rdi
movl $64, %edx
movl $2, %ecx
callq hipMemcpy
movl $10, %edi
callq putchar@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movss 192(%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl 128(%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %rbx
cmpq $16, %rbx
jne .LBB1_3
# %bb.4:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $256, %rsp # imm = 0x100
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13testRadixSortPfPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13testRadixSortPfPii,@object # @_Z13testRadixSortPfPii
.section .rodata,"a",@progbits
.globl _Z13testRadixSortPfPii
.p2align 3, 0x0
_Z13testRadixSortPfPii:
.quad _Z28__device_stub__testRadixSortPfPii
.size _Z13testRadixSortPfPii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz " %f %d, "
.size .L.str.1, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13testRadixSortPfPii"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__testRadixSortPfPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13testRadixSortPfPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001791c1_00000000-6_testRadixSort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2068:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7dispArrPii
.type _Z7dispArrPii, @function
_Z7dispArrPii:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z7dispArrPii, .-_Z7dispArrPii
.globl _Z10preSubScanPiii
.type _Z10preSubScanPiii, @function
_Z10preSubScanPiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z10preSubScanPiii, .-_Z10preSubScanPiii
.globl _Z4scanPii
.type _Z4scanPii, @function
_Z4scanPii:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z4scanPii, .-_Z4scanPii
.globl _Z10d_dispFArrPfi
.type _Z10d_dispFArrPfi, @function
_Z10d_dispFArrPfi:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z10d_dispFArrPfi, .-_Z10d_dispFArrPfi
.globl _Z18computeAtomicHistoPiPfiii
.type _Z18computeAtomicHistoPiPfiii, @function
_Z18computeAtomicHistoPiPfiii:
.LFB2061:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z18computeAtomicHistoPiPfiii, .-_Z18computeAtomicHistoPiPfiii
.globl _Z15writeSortedValsPiPfS0_S_S_iii
.type _Z15writeSortedValsPiPfS0_S_S_iii, @function
_Z15writeSortedValsPiPfS0_S_S_iii:
.LFB2062:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2062:
.size _Z15writeSortedValsPiPfS0_S_S_iii, .-_Z15writeSortedValsPiPfS0_S_S_iii
.globl _Z9zeroedIntPii
.type _Z9zeroedIntPii, @function
_Z9zeroedIntPii:
.LFB2063:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2063:
.size _Z9zeroedIntPii, .-_Z9zeroedIntPii
.globl _Z9radixSortPfS_PiS0_S0_ii
.type _Z9radixSortPfS_PiS0_S0_ii, @function
_Z9radixSortPfS_PiS0_S0_ii:
.LFB2064:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2064:
.size _Z9radixSortPfS_PiS0_S0_ii, .-_Z9radixSortPfS_PiS0_S0_ii
.globl _Z36__device_stub__Z13testRadixSortPfPiiPfPii
.type _Z36__device_stub__Z13testRadixSortPfPiiPfPii, @function
_Z36__device_stub__Z13testRadixSortPfPiiPfPii:
.LFB2090:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13testRadixSortPfPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z36__device_stub__Z13testRadixSortPfPiiPfPii, .-_Z36__device_stub__Z13testRadixSortPfPiiPfPii
.globl _Z13testRadixSortPfPii
.type _Z13testRadixSortPfPii, @function
_Z13testRadixSortPfPii:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13testRadixSortPfPiiPfPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z13testRadixSortPfPii, .-_Z13testRadixSortPfPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC7:
.string "\n"
.LC8:
.string " %f %d, "
.text
.globl main
.type main, @function
main:
.LFB2065:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $200, %rsp
.cfi_def_cfa_offset 224
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
movl $0x3f800000, 48(%rsp)
movss .LC1(%rip), %xmm2
movss %xmm2, 52(%rsp)
movss .LC2(%rip), %xmm1
movss %xmm1, 56(%rsp)
movl $0x3ebaf4ae, 60(%rsp)
movl $0x3f2bbadc, 64(%rsp)
movl $0x3ee4f93c, 68(%rsp)
movss .LC6(%rip), %xmm0
movss %xmm0, 72(%rsp)
movss %xmm2, 76(%rsp)
movss %xmm0, 80(%rsp)
movss %xmm1, 84(%rsp)
movss %xmm0, 88(%rsp)
movss %xmm0, 92(%rsp)
movss %xmm0, 96(%rsp)
movss %xmm0, 100(%rsp)
movss %xmm0, 104(%rsp)
movss %xmm0, 108(%rsp)
movl $0, 112(%rsp)
movl $53, 116(%rsp)
movl $54, 120(%rsp)
movl $81, 124(%rsp)
movl $98, 128(%rsp)
movl $195, 132(%rsp)
movl $283, 136(%rsp)
movl $583, 140(%rsp)
movl $598, 144(%rsp)
movl $615, 148(%rsp)
movl $654, 152(%rsp)
movl $690, 156(%rsp)
movl $768, 160(%rsp)
movl $904, 164(%rsp)
movl $919, 168(%rsp)
movl $946, 172(%rsp)
leaq 8(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 112(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $272, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L28:
leaq 112(%rsp), %rdi
movl $2, %ecx
movl $64, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq 48(%rsp), %rdi
movl $2, %ecx
movl $64, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC8(%rip), %rbp
.L29:
movl 112(%rsp,%rbx), %edx
pxor %xmm0, %xmm0
cvtss2sd 48(%rsp,%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $64, %rbx
jne .L29
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movl $16, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z36__device_stub__Z13testRadixSortPfPiiPfPii
jmp .L28
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2065:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z13testRadixSortPfPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z13testRadixSortPfPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1053609165
.align 4
.LC2:
.long 1050798243
.align 4
.LC6:
.long 1048851113
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "testRadixSort.hip"
.globl _Z28__device_stub__testRadixSortPfPii # -- Begin function _Z28__device_stub__testRadixSortPfPii
.p2align 4, 0x90
.type _Z28__device_stub__testRadixSortPfPii,@function
_Z28__device_stub__testRadixSortPfPii: # @_Z28__device_stub__testRadixSortPfPii
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13testRadixSortPfPii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__testRadixSortPfPii, .Lfunc_end0-_Z28__device_stub__testRadixSortPfPii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3f800000 # float 1
.long 0x3ecccccd # float 0.400000006
.long 0x3ea1e8a3 # float 0.316228002
.long 0x3ebaf4ae # float 0.365148008
.LCPI1_1:
.long 0x3f2bbadc # float 0.670819998
.long 0x3ee4f93c # float 0.447214007
.long 0x3e8432a9 # float 0.258199006
.long 0x3ecccccd # float 0.400000006
.LCPI1_2:
.long 0x3e8432a9 # float 0.258199006
.long 0x3ea1e8a3 # float 0.316228002
.long 0x3e8432a9 # float 0.258199006
.long 0x3e8432a9 # float 0.258199006
.LCPI1_3:
.long 0x3e8432a9 # float 0.258199006
.long 0x3e8432a9 # float 0.258199006
.long 0x3e8432a9 # float 0.258199006
.long 0x3e8432a9 # float 0.258199006
.LCPI1_4:
.long 0 # 0x0
.long 53 # 0x35
.long 54 # 0x36
.long 81 # 0x51
.LCPI1_5:
.long 98 # 0x62
.long 195 # 0xc3
.long 283 # 0x11b
.long 583 # 0x247
.LCPI1_6:
.long 598 # 0x256
.long 615 # 0x267
.long 654 # 0x28e
.long 690 # 0x2b2
.LCPI1_7:
.long 768 # 0x300
.long 904 # 0x388
.long 919 # 0x397
.long 946 # 0x3b2
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $256, %rsp # imm = 0x100
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -16
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [1.0E+0,4.00000006E-1,3.16228002E-1,3.65148008E-1]
movaps %xmm0, 192(%rsp)
movaps .LCPI1_1(%rip), %xmm0 # xmm0 = [6.70819998E-1,4.47214007E-1,2.58199006E-1,4.00000006E-1]
movaps %xmm0, 208(%rsp)
movaps .LCPI1_2(%rip), %xmm0 # xmm0 = [2.58199006E-1,3.16228002E-1,2.58199006E-1,2.58199006E-1]
movaps %xmm0, 224(%rsp)
movaps .LCPI1_3(%rip), %xmm0 # xmm0 = [2.58199006E-1,2.58199006E-1,2.58199006E-1,2.58199006E-1]
movaps %xmm0, 240(%rsp)
movaps .LCPI1_4(%rip), %xmm0 # xmm0 = [0,53,54,81]
movaps %xmm0, 128(%rsp)
movaps .LCPI1_5(%rip), %xmm0 # xmm0 = [98,195,283,583]
movaps %xmm0, 144(%rsp)
movaps .LCPI1_6(%rip), %xmm0 # xmm0 = [598,615,654,690]
movaps %xmm0, 160(%rsp)
movaps .LCPI1_7(%rip), %xmm0 # xmm0 = [768,904,919,946]
movaps %xmm0, 176(%rsp)
leaq 16(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 192(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 127(%rdi), %rdx
movl $272, %r8d # imm = 0x110
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $16, 28(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13testRadixSortPfPii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 128(%rsp), %rdi
movl $64, %edx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rsi
leaq 192(%rsp), %rdi
movl $64, %edx
movl $2, %ecx
callq hipMemcpy
movl $10, %edi
callq putchar@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movss 192(%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl 128(%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %rbx
cmpq $16, %rbx
jne .LBB1_3
# %bb.4:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $256, %rsp # imm = 0x100
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13testRadixSortPfPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13testRadixSortPfPii,@object # @_Z13testRadixSortPfPii
.section .rodata,"a",@progbits
.globl _Z13testRadixSortPfPii
.p2align 3, 0x0
_Z13testRadixSortPfPii:
.quad _Z28__device_stub__testRadixSortPfPii
.size _Z13testRadixSortPfPii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz " %f %d, "
.size .L.str.1, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13testRadixSortPfPii"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__testRadixSortPfPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13testRadixSortPfPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void add(int *res, int a, int b) {
*res = a + b;
}
int main(void) {
int res;
int *device_res = NULL;
cudaError_t mres;
// Allocate memory on the device
// You cannot dereference this in host code!
mres = cudaMalloc(&device_res, sizeof(int));
if (mres != cudaSuccess) {
printf("Malloc failed\n");
return -1;
}
// Do computation
add<<<1,1>>>(device_res, 2, 7);
// Copy result back to host
mres = cudaMemcpy(&res, device_res, sizeof(int), cudaMemcpyDeviceToHost);
if (mres != cudaSuccess) {
printf("Memcpy failed\n");
return -1;
}
// Now free the memory we allocated on the device
mres = cudaFree(device_res);
if (mres != cudaSuccess) {
printf("Free failed\n");
return -1;
}
printf("2 + 7 = %d\n", res);
return 0;
} | code for sm_80
Function : _Z3addPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe40000000f00 */
/*0050*/ IADD3 R5, R5, c[0x0][0x168], RZ ; /* 0x00005a0005057a10 */
/* 0x000fca0007ffe0ff */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void add(int *res, int a, int b) {
*res = a + b;
}
int main(void) {
int res;
int *device_res = NULL;
cudaError_t mres;
// Allocate memory on the device
// You cannot dereference this in host code!
mres = cudaMalloc(&device_res, sizeof(int));
if (mres != cudaSuccess) {
printf("Malloc failed\n");
return -1;
}
// Do computation
add<<<1,1>>>(device_res, 2, 7);
// Copy result back to host
mres = cudaMemcpy(&res, device_res, sizeof(int), cudaMemcpyDeviceToHost);
if (mres != cudaSuccess) {
printf("Memcpy failed\n");
return -1;
}
// Now free the memory we allocated on the device
mres = cudaFree(device_res);
if (mres != cudaSuccess) {
printf("Free failed\n");
return -1;
}
printf("2 + 7 = %d\n", res);
return 0;
} | .file "tmpxft_0003953c_00000000-6_scalar_adder.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z3addPiiiPiii
.type _Z24__device_stub__Z3addPiiiPiii, @function
_Z24__device_stub__Z3addPiiiPiii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z3addPiiiPiii, .-_Z24__device_stub__Z3addPiiiPiii
.globl _Z3addPiii
.type _Z3addPiii, @function
_Z3addPiii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3addPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiii, .-_Z3addPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Malloc failed\n"
.LC1:
.string "Memcpy failed\n"
.LC2:
.string "Free failed\n"
.LC3:
.string "2 + 7 = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L19
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L14:
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L21
movq 8(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L22
movl 28(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
.L11:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L23
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %eax
jmp .L11
.L20:
movl $7, %edx
movl $2, %esi
movq 8(%rsp), %rdi
call _Z24__device_stub__Z3addPiiiPiii
jmp .L14
.L21:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %eax
jmp .L11
.L22:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %eax
jmp .L11
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z3addPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void add(int *res, int a, int b) {
*res = a + b;
}
int main(void) {
int res;
int *device_res = NULL;
cudaError_t mres;
// Allocate memory on the device
// You cannot dereference this in host code!
mres = cudaMalloc(&device_res, sizeof(int));
if (mres != cudaSuccess) {
printf("Malloc failed\n");
return -1;
}
// Do computation
add<<<1,1>>>(device_res, 2, 7);
// Copy result back to host
mres = cudaMemcpy(&res, device_res, sizeof(int), cudaMemcpyDeviceToHost);
if (mres != cudaSuccess) {
printf("Memcpy failed\n");
return -1;
}
// Now free the memory we allocated on the device
mres = cudaFree(device_res);
if (mres != cudaSuccess) {
printf("Free failed\n");
return -1;
}
printf("2 + 7 = %d\n", res);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void add(int *res, int a, int b) {
*res = a + b;
}
int main(void) {
int res;
int *device_res = NULL;
hipError_t mres;
// Allocate memory on the device
// You cannot dereference this in host code!
mres = hipMalloc(&device_res, sizeof(int));
if (mres != hipSuccess) {
printf("Malloc failed\n");
return -1;
}
// Do computation
add<<<1,1>>>(device_res, 2, 7);
// Copy result back to host
mres = hipMemcpy(&res, device_res, sizeof(int), hipMemcpyDeviceToHost);
if (mres != hipSuccess) {
printf("Memcpy failed\n");
return -1;
}
// Now free the memory we allocated on the device
mres = hipFree(device_res);
if (mres != hipSuccess) {
printf("Free failed\n");
return -1;
}
printf("2 + 7 = %d\n", res);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void add(int *res, int a, int b) {
*res = a + b;
}
int main(void) {
int res;
int *device_res = NULL;
hipError_t mres;
// Allocate memory on the device
// You cannot dereference this in host code!
mres = hipMalloc(&device_res, sizeof(int));
if (mres != hipSuccess) {
printf("Malloc failed\n");
return -1;
}
// Do computation
add<<<1,1>>>(device_res, 2, 7);
// Copy result back to host
mres = hipMemcpy(&res, device_res, sizeof(int), hipMemcpyDeviceToHost);
if (mres != hipSuccess) {
printf("Memcpy failed\n");
return -1;
}
// Now free the memory we allocated on the device
mres = hipFree(device_res);
if (mres != hipSuccess) {
printf("Free failed\n");
return -1;
}
printf("2 + 7 = %d\n", res);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiii
.globl _Z3addPiii
.p2align 8
.type _Z3addPiii,@function
_Z3addPiii:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiii, .Lfunc_end0-_Z3addPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiii
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z3addPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void add(int *res, int a, int b) {
*res = a + b;
}
int main(void) {
int res;
int *device_res = NULL;
hipError_t mres;
// Allocate memory on the device
// You cannot dereference this in host code!
mres = hipMalloc(&device_res, sizeof(int));
if (mres != hipSuccess) {
printf("Malloc failed\n");
return -1;
}
// Do computation
add<<<1,1>>>(device_res, 2, 7);
// Copy result back to host
mres = hipMemcpy(&res, device_res, sizeof(int), hipMemcpyDeviceToHost);
if (mres != hipSuccess) {
printf("Memcpy failed\n");
return -1;
}
// Now free the memory we allocated on the device
mres = hipFree(device_res);
if (mres != hipSuccess) {
printf("Free failed\n");
return -1;
}
printf("2 + 7 = %d\n", res);
return 0;
} | .text
.file "scalar_adder.hip"
.globl _Z18__device_stub__addPiii # -- Begin function _Z18__device_stub__addPiii
.p2align 4, 0x90
.type _Z18__device_stub__addPiii,@function
_Z18__device_stub__addPiii: # @_Z18__device_stub__addPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3addPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiii, .Lfunc_end0-_Z18__device_stub__addPiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq $0, (%rsp)
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
je .LBB1_3
# %bb.1:
movl $.Lstr.2, %edi
jmp .LBB1_2
.LBB1_3:
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq (%rsp), %rax
movq %rax, 96(%rsp)
movl $2, 12(%rsp)
movl $7, 8(%rsp)
leaq 96(%rsp), %rax
movq %rax, 16(%rsp)
leaq 12(%rsp), %rax
movq %rax, 24(%rsp)
leaq 8(%rsp), %rax
movq %rax, 32(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z3addPiii, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movq (%rsp), %rsi
leaq 16(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_7
# %bb.6:
movl $.Lstr.1, %edi
jmp .LBB1_2
.LBB1_7:
movq (%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB1_9
# %bb.8:
movl $.Lstr, %edi
.LBB1_2:
callq puts@PLT
movl $-1, %eax
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.LBB1_9:
.cfi_def_cfa_offset 112
movl 16(%rsp), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiii,@object # @_Z3addPiii
.section .rodata,"a",@progbits
.globl _Z3addPiii
.p2align 3, 0x0
_Z3addPiii:
.quad _Z18__device_stub__addPiii
.size _Z3addPiii, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "2 + 7 = %d\n"
.size .L.str.3, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiii"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Free failed"
.size .Lstr, 12
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Memcpy failed"
.size .Lstr.1, 14
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Malloc failed"
.size .Lstr.2, 14
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe40000000f00 */
/*0050*/ IADD3 R5, R5, c[0x0][0x168], RZ ; /* 0x00005a0005057a10 */
/* 0x000fca0007ffe0ff */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiii
.globl _Z3addPiii
.p2align 8
.type _Z3addPiii,@function
_Z3addPiii:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiii, .Lfunc_end0-_Z3addPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiii
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z3addPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003953c_00000000-6_scalar_adder.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z3addPiiiPiii
.type _Z24__device_stub__Z3addPiiiPiii, @function
_Z24__device_stub__Z3addPiiiPiii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z3addPiiiPiii, .-_Z24__device_stub__Z3addPiiiPiii
.globl _Z3addPiii
.type _Z3addPiii, @function
_Z3addPiii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3addPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiii, .-_Z3addPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Malloc failed\n"
.LC1:
.string "Memcpy failed\n"
.LC2:
.string "Free failed\n"
.LC3:
.string "2 + 7 = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L19
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L14:
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L21
movq 8(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L22
movl 28(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
.L11:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L23
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %eax
jmp .L11
.L20:
movl $7, %edx
movl $2, %esi
movq 8(%rsp), %rdi
call _Z24__device_stub__Z3addPiiiPiii
jmp .L14
.L21:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %eax
jmp .L11
.L22:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %eax
jmp .L11
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z3addPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "scalar_adder.hip"
.globl _Z18__device_stub__addPiii # -- Begin function _Z18__device_stub__addPiii
.p2align 4, 0x90
.type _Z18__device_stub__addPiii,@function
_Z18__device_stub__addPiii: # @_Z18__device_stub__addPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3addPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiii, .Lfunc_end0-_Z18__device_stub__addPiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq $0, (%rsp)
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
je .LBB1_3
# %bb.1:
movl $.Lstr.2, %edi
jmp .LBB1_2
.LBB1_3:
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq (%rsp), %rax
movq %rax, 96(%rsp)
movl $2, 12(%rsp)
movl $7, 8(%rsp)
leaq 96(%rsp), %rax
movq %rax, 16(%rsp)
leaq 12(%rsp), %rax
movq %rax, 24(%rsp)
leaq 8(%rsp), %rax
movq %rax, 32(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z3addPiii, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movq (%rsp), %rsi
leaq 16(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_7
# %bb.6:
movl $.Lstr.1, %edi
jmp .LBB1_2
.LBB1_7:
movq (%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB1_9
# %bb.8:
movl $.Lstr, %edi
.LBB1_2:
callq puts@PLT
movl $-1, %eax
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.LBB1_9:
.cfi_def_cfa_offset 112
movl 16(%rsp), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiii,@object # @_Z3addPiii
.section .rodata,"a",@progbits
.globl _Z3addPiii
.p2align 3, 0x0
_Z3addPiii:
.quad _Z18__device_stub__addPiii
.size _Z3addPiii, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "2 + 7 = %d\n"
.size .L.str.3, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiii"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Free failed"
.size .Lstr, 12
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Memcpy failed"
.size .Lstr.1, 14
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Malloc failed"
.size .Lstr.2, 14
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void cycfold_multichannel(const float2 *pol0, const float2 *pol1,
const double *phase, const double *step,
const int fftlen, const int overlap, const int nbin, const int nlag,
const int num_fft,
float2 *xx, float2 *yy, float2 *xy, unsigned *hits) {
// Lag is specified with threadIdx.x and blockIdx.x since there could be
// more lags than allowed threads.
const int ilaga = threadIdx.x;
const int nlaga = blockDim.x;
const int ilagb = blockIdx.x;
const int ilag = ilagb*nlaga + ilaga;
// Phase bin is blockIdx.y
const int ibin = blockIdx.y;
// Filterbank channel is blockIdx.z
const int ichan = blockIdx.z;
const int num_valid_samples = fftlen - overlap;
// accumulators for the various lag terms
float2 foldxxlag = make_float2(0,0);
float2 foldyylag = make_float2(0,0);
float2 foldxylag = make_float2(0,0);
__shared__ int samp0;
__shared__ int samp1;
// Number of hits for this phase/lag bin
int foldcount = 0;
for (int ifft=0; ifft < num_fft; ifft++){
//Pointers to the first valid sample for this channel and fft
const float2 *ptr0 = pol0 +ichan*fftlen*num_fft + ifft*fftlen + overlap/2;
const float2 *ptr1 = pol1 + ichan*fftlen*num_fft + ifft*fftlen + overlap/2;
// Fold info
const double bin0 = phase[ifft];
const double bins_per_sample = step[ifft]; // bins/sample
const double samples_per_bin = 1.0/bins_per_sample; // samples/bin
const int num_turns = ((double)num_valid_samples*bins_per_sample)/(double)nbin + 2;
// Loop over number of pulse periods in data block
for (int iturn=0; iturn<num_turns; iturn++) {
// Determine range of samples needed for this bin, turn
if(ilaga == 0){
samp0 = samples_per_bin*((double)ibin-bin0+(double)iturn*nbin)+0.5;
samp1 = samples_per_bin*((double)ibin-bin0+(double)iturn*nbin+1)+0.5;
// Range checks
if (samp0<0) { samp0=0; }
if (samp1<0) { samp1=0; }
if (samp0>num_valid_samples) { samp0=num_valid_samples; }
if (samp1>num_valid_samples) { samp1=num_valid_samples; }
}
__syncthreads();
// Read in and add samples
int lag_index;
for (int isamp=samp0; isamp<samp1; isamp++) {
lag_index = isamp + ilag -nlag/2;
if((lag_index >= 0) && (lag_index < num_valid_samples)){
float2 p0 = ptr0[isamp];
float2 p0lag = ptr0[lag_index];
float2 p1 = ptr1[isamp];
float2 p1lag = ptr1[lag_index];
// <Pol0 x Pol0_lag*>
foldxxlag.x += p0.x*p0lag.x + p0.y*p0lag.y;
foldxxlag.y += p0.y*p0lag.x - p0.x*p0lag.y;
// <Pol1 x Pol1_lag*>
foldyylag.x += p1.x*p1lag.x + p1.y*p1lag.y;
foldyylag.y += p1.y*p1lag.x - p1.x*p1lag.y;
// <Pol0 x Pol1_lag*>
foldxylag.x += p0.x*p1lag.x + p0.y*p1lag.y;
foldxylag.y += p0.y*p1lag.x - p0.x*p1lag.y;
foldcount++;
}
}
}
}
xx[ichan*nlag*nbin+nlag*ibin+ilag] = foldxxlag;
yy[ichan*nlag*nbin+nlag*ibin+ilag] = foldyylag;
xy[ichan*nlag*nbin+nlag*ibin+ilag] = foldxylag;
hits[ichan*nlag*nbin+nlag*ibin+ilag] = foldcount;
} | .file "tmpxft_001220a4_00000000-6_multichannel_shared.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z72__device_stub__Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_PjPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj
.type _Z72__device_stub__Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_PjPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj, @function
_Z72__device_stub__Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_PjPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj:
.LFB2081:
.cfi_startproc
endbr64
subq $264, %rsp
.cfi_def_cfa_offset 272
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movl %r8d, 44(%rsp)
movl %r9d, 40(%rsp)
movq 296(%rsp), %rax
movq %rax, 32(%rsp)
movq 304(%rsp), %rax
movq %rax, 24(%rsp)
movq 312(%rsp), %rax
movq %rax, 16(%rsp)
movq 320(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 44(%rsp), %rax
movq %rax, 176(%rsp)
leaq 40(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 280(%rsp), %rax
movq %rax, 200(%rsp)
leaq 288(%rsp), %rax
movq %rax, 208(%rsp)
leaq 32(%rsp), %rax
movq %rax, 216(%rsp)
leaq 24(%rsp), %rax
movq %rax, 224(%rsp)
leaq 16(%rsp), %rax
movq %rax, 232(%rsp)
leaq 8(%rsp), %rax
movq %rax, 240(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 280
pushq 88(%rsp)
.cfi_def_cfa_offset 288
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 272
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z72__device_stub__Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_PjPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj, .-_Z72__device_stub__Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_PjPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj
.globl _Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj
.type _Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj, @function
_Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj:
.LFB2082:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 72(%rsp)
.cfi_def_cfa_offset 32
pushq 72(%rsp)
.cfi_def_cfa_offset 40
pushq 72(%rsp)
.cfi_def_cfa_offset 48
pushq 72(%rsp)
.cfi_def_cfa_offset 56
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 72
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 80
call _Z72__device_stub__Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_PjPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj
addq $72, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj, .-_Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void cycfold_multichannel(const float2 *pol0, const float2 *pol1,
const double *phase, const double *step,
const int fftlen, const int overlap, const int nbin, const int nlag,
const int num_fft,
float2 *xx, float2 *yy, float2 *xy, unsigned *hits) {
// Lag is specified with threadIdx.x and blockIdx.x since there could be
// more lags than allowed threads.
const int ilaga = threadIdx.x;
const int nlaga = blockDim.x;
const int ilagb = blockIdx.x;
const int ilag = ilagb*nlaga + ilaga;
// Phase bin is blockIdx.y
const int ibin = blockIdx.y;
// Filterbank channel is blockIdx.z
const int ichan = blockIdx.z;
const int num_valid_samples = fftlen - overlap;
// accumulators for the various lag terms
float2 foldxxlag = make_float2(0,0);
float2 foldyylag = make_float2(0,0);
float2 foldxylag = make_float2(0,0);
__shared__ int samp0;
__shared__ int samp1;
// Number of hits for this phase/lag bin
int foldcount = 0;
for (int ifft=0; ifft < num_fft; ifft++){
//Pointers to the first valid sample for this channel and fft
const float2 *ptr0 = pol0 +ichan*fftlen*num_fft + ifft*fftlen + overlap/2;
const float2 *ptr1 = pol1 + ichan*fftlen*num_fft + ifft*fftlen + overlap/2;
// Fold info
const double bin0 = phase[ifft];
const double bins_per_sample = step[ifft]; // bins/sample
const double samples_per_bin = 1.0/bins_per_sample; // samples/bin
const int num_turns = ((double)num_valid_samples*bins_per_sample)/(double)nbin + 2;
// Loop over number of pulse periods in data block
for (int iturn=0; iturn<num_turns; iturn++) {
// Determine range of samples needed for this bin, turn
if(ilaga == 0){
samp0 = samples_per_bin*((double)ibin-bin0+(double)iturn*nbin)+0.5;
samp1 = samples_per_bin*((double)ibin-bin0+(double)iturn*nbin+1)+0.5;
// Range checks
if (samp0<0) { samp0=0; }
if (samp1<0) { samp1=0; }
if (samp0>num_valid_samples) { samp0=num_valid_samples; }
if (samp1>num_valid_samples) { samp1=num_valid_samples; }
}
__syncthreads();
// Read in and add samples
int lag_index;
for (int isamp=samp0; isamp<samp1; isamp++) {
lag_index = isamp + ilag -nlag/2;
if((lag_index >= 0) && (lag_index < num_valid_samples)){
float2 p0 = ptr0[isamp];
float2 p0lag = ptr0[lag_index];
float2 p1 = ptr1[isamp];
float2 p1lag = ptr1[lag_index];
// <Pol0 x Pol0_lag*>
foldxxlag.x += p0.x*p0lag.x + p0.y*p0lag.y;
foldxxlag.y += p0.y*p0lag.x - p0.x*p0lag.y;
// <Pol1 x Pol1_lag*>
foldyylag.x += p1.x*p1lag.x + p1.y*p1lag.y;
foldyylag.y += p1.y*p1lag.x - p1.x*p1lag.y;
// <Pol0 x Pol1_lag*>
foldxylag.x += p0.x*p1lag.x + p0.y*p1lag.y;
foldxylag.y += p0.y*p1lag.x - p0.x*p1lag.y;
foldcount++;
}
}
}
}
xx[ichan*nlag*nbin+nlag*ibin+ilag] = foldxxlag;
yy[ichan*nlag*nbin+nlag*ibin+ilag] = foldyylag;
xy[ichan*nlag*nbin+nlag*ibin+ilag] = foldxylag;
hits[ichan*nlag*nbin+nlag*ibin+ilag] = foldcount;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void cycfold_multichannel(const float2 *pol0, const float2 *pol1,
const double *phase, const double *step,
const int fftlen, const int overlap, const int nbin, const int nlag,
const int num_fft,
float2 *xx, float2 *yy, float2 *xy, unsigned *hits) {
// Lag is specified with threadIdx.x and blockIdx.x since there could be
// more lags than allowed threads.
const int ilaga = threadIdx.x;
const int nlaga = blockDim.x;
const int ilagb = blockIdx.x;
const int ilag = ilagb*nlaga + ilaga;
// Phase bin is blockIdx.y
const int ibin = blockIdx.y;
// Filterbank channel is blockIdx.z
const int ichan = blockIdx.z;
const int num_valid_samples = fftlen - overlap;
// accumulators for the various lag terms
float2 foldxxlag = make_float2(0,0);
float2 foldyylag = make_float2(0,0);
float2 foldxylag = make_float2(0,0);
__shared__ int samp0;
__shared__ int samp1;
// Number of hits for this phase/lag bin
int foldcount = 0;
for (int ifft=0; ifft < num_fft; ifft++){
//Pointers to the first valid sample for this channel and fft
const float2 *ptr0 = pol0 +ichan*fftlen*num_fft + ifft*fftlen + overlap/2;
const float2 *ptr1 = pol1 + ichan*fftlen*num_fft + ifft*fftlen + overlap/2;
// Fold info
const double bin0 = phase[ifft];
const double bins_per_sample = step[ifft]; // bins/sample
const double samples_per_bin = 1.0/bins_per_sample; // samples/bin
const int num_turns = ((double)num_valid_samples*bins_per_sample)/(double)nbin + 2;
// Loop over number of pulse periods in data block
for (int iturn=0; iturn<num_turns; iturn++) {
// Determine range of samples needed for this bin, turn
if(ilaga == 0){
samp0 = samples_per_bin*((double)ibin-bin0+(double)iturn*nbin)+0.5;
samp1 = samples_per_bin*((double)ibin-bin0+(double)iturn*nbin+1)+0.5;
// Range checks
if (samp0<0) { samp0=0; }
if (samp1<0) { samp1=0; }
if (samp0>num_valid_samples) { samp0=num_valid_samples; }
if (samp1>num_valid_samples) { samp1=num_valid_samples; }
}
__syncthreads();
// Read in and add samples
int lag_index;
for (int isamp=samp0; isamp<samp1; isamp++) {
lag_index = isamp + ilag -nlag/2;
if((lag_index >= 0) && (lag_index < num_valid_samples)){
float2 p0 = ptr0[isamp];
float2 p0lag = ptr0[lag_index];
float2 p1 = ptr1[isamp];
float2 p1lag = ptr1[lag_index];
// <Pol0 x Pol0_lag*>
foldxxlag.x += p0.x*p0lag.x + p0.y*p0lag.y;
foldxxlag.y += p0.y*p0lag.x - p0.x*p0lag.y;
// <Pol1 x Pol1_lag*>
foldyylag.x += p1.x*p1lag.x + p1.y*p1lag.y;
foldyylag.y += p1.y*p1lag.x - p1.x*p1lag.y;
// <Pol0 x Pol1_lag*>
foldxylag.x += p0.x*p1lag.x + p0.y*p1lag.y;
foldxylag.y += p0.y*p1lag.x - p0.x*p1lag.y;
foldcount++;
}
}
}
}
xx[ichan*nlag*nbin+nlag*ibin+ilag] = foldxxlag;
yy[ichan*nlag*nbin+nlag*ibin+ilag] = foldyylag;
xy[ichan*nlag*nbin+nlag*ibin+ilag] = foldxylag;
hits[ichan*nlag*nbin+nlag*ibin+ilag] = foldcount;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void cycfold_multichannel(const float2 *pol0, const float2 *pol1,
const double *phase, const double *step,
const int fftlen, const int overlap, const int nbin, const int nlag,
const int num_fft,
float2 *xx, float2 *yy, float2 *xy, unsigned *hits) {
// Lag is specified with threadIdx.x and blockIdx.x since there could be
// more lags than allowed threads.
const int ilaga = threadIdx.x;
const int nlaga = blockDim.x;
const int ilagb = blockIdx.x;
const int ilag = ilagb*nlaga + ilaga;
// Phase bin is blockIdx.y
const int ibin = blockIdx.y;
// Filterbank channel is blockIdx.z
const int ichan = blockIdx.z;
const int num_valid_samples = fftlen - overlap;
// accumulators for the various lag terms
float2 foldxxlag = make_float2(0,0);
float2 foldyylag = make_float2(0,0);
float2 foldxylag = make_float2(0,0);
__shared__ int samp0;
__shared__ int samp1;
// Number of hits for this phase/lag bin
int foldcount = 0;
for (int ifft=0; ifft < num_fft; ifft++){
//Pointers to the first valid sample for this channel and fft
const float2 *ptr0 = pol0 +ichan*fftlen*num_fft + ifft*fftlen + overlap/2;
const float2 *ptr1 = pol1 + ichan*fftlen*num_fft + ifft*fftlen + overlap/2;
// Fold info
const double bin0 = phase[ifft];
const double bins_per_sample = step[ifft]; // bins/sample
const double samples_per_bin = 1.0/bins_per_sample; // samples/bin
const int num_turns = ((double)num_valid_samples*bins_per_sample)/(double)nbin + 2;
// Loop over number of pulse periods in data block
for (int iturn=0; iturn<num_turns; iturn++) {
// Determine range of samples needed for this bin, turn
if(ilaga == 0){
samp0 = samples_per_bin*((double)ibin-bin0+(double)iturn*nbin)+0.5;
samp1 = samples_per_bin*((double)ibin-bin0+(double)iturn*nbin+1)+0.5;
// Range checks
if (samp0<0) { samp0=0; }
if (samp1<0) { samp1=0; }
if (samp0>num_valid_samples) { samp0=num_valid_samples; }
if (samp1>num_valid_samples) { samp1=num_valid_samples; }
}
__syncthreads();
// Read in and add samples
int lag_index;
for (int isamp=samp0; isamp<samp1; isamp++) {
lag_index = isamp + ilag -nlag/2;
if((lag_index >= 0) && (lag_index < num_valid_samples)){
float2 p0 = ptr0[isamp];
float2 p0lag = ptr0[lag_index];
float2 p1 = ptr1[isamp];
float2 p1lag = ptr1[lag_index];
// <Pol0 x Pol0_lag*>
foldxxlag.x += p0.x*p0lag.x + p0.y*p0lag.y;
foldxxlag.y += p0.y*p0lag.x - p0.x*p0lag.y;
// <Pol1 x Pol1_lag*>
foldyylag.x += p1.x*p1lag.x + p1.y*p1lag.y;
foldyylag.y += p1.y*p1lag.x - p1.x*p1lag.y;
// <Pol0 x Pol1_lag*>
foldxylag.x += p0.x*p1lag.x + p0.y*p1lag.y;
foldxylag.y += p0.y*p1lag.x - p0.x*p1lag.y;
foldcount++;
}
}
}
}
xx[ichan*nlag*nbin+nlag*ibin+ilag] = foldxxlag;
yy[ichan*nlag*nbin+nlag*ibin+ilag] = foldyylag;
xy[ichan*nlag*nbin+nlag*ibin+ilag] = foldxylag;
hits[ichan*nlag*nbin+nlag*ibin+ilag] = foldcount;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj
.globl _Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj
.p2align 8
.type _Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj,@function
_Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x64
s_load_b32 s25, s[0:1], 0x30
s_load_b64 s[16:17], s[0:1], 0x28
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_cmp_lt_i32 s25, 1
s_mul_i32 s24, s13, s2
s_mov_b32 s13, 0
s_cbranch_scc1 .LBB0_20
s_clause 0x1
s_load_b64 s[18:19], s[0:1], 0x20
s_load_b256 s[4:11], s[0:1], 0x0
v_cvt_f64_i32_e32 v[7:8], s16
v_cvt_f64_i32_e32 v[9:10], s14
v_cmp_eq_u32_e64 s2, 0, v0
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v23, 0
v_dual_mov_b32 v14, 0 :: v_dual_mov_b32 v1, 0
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v3, 0
v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v5, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s15, s18
s_sub_i32 s26, s18, s19
s_mul_i32 s20, s3, s25
v_cvt_f64_i32_e32 v[11:12], s26
s_ashr_i32 s21, s20, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[22:23], s[20:21], 3
s_add_u32 s3, s4, s22
s_addc_u32 s12, s5, s23
s_lshr_b32 s20, s19, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s19, s19, s20
s_mov_b32 s20, s13
s_ashr_i32 s28, s19, 1
s_ashr_i32 s29, s28, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[30:31], s[28:29], 3
s_add_u32 s19, s3, s30
s_addc_u32 s27, s12, s31
s_add_u32 s3, s6, s22
s_addc_u32 s12, s7, s23
s_add_u32 s28, s3, s30
s_addc_u32 s29, s12, s31
s_lshr_b32 s3, s17, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s17, s3
s_ashr_i32 s3, s3, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s3, s24, s3
s_add_u32 s12, s30, s22
s_addc_u32 s21, s31, s23
s_or_b32 s12, s12, 4
v_add_nc_u32_e32 v24, s3, v0
s_add_u32 s30, s4, s12
s_addc_u32 s31, s5, s21
s_add_u32 s33, s6, s12
s_addc_u32 s34, s7, s21
s_mov_b32 s12, s13
s_branch .LBB0_3
.LBB0_2:
s_add_i32 s12, s12, 1
s_add_i32 s20, s20, s18
s_cmp_eq_u32 s12, s25
s_cbranch_scc1 .LBB0_21
.LBB0_3:
s_lshl_b64 s[4:5], s[12:13], 3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
s_add_u32 s6, s10, s4
s_addc_u32 s7, s11, s5
s_load_b64 s[6:7], s[6:7], 0x0
s_waitcnt lgkmcnt(0)
v_mul_f64 v[15:16], s[6:7], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[17:18], null, v[7:8], v[7:8], v[15:16]
v_rcp_f64_e32 v[19:20], v[17:18]
s_waitcnt_depctr 0xfff
v_fma_f64 v[21:22], -v[17:18], v[19:20], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[19:20], v[19:20], v[21:22], v[19:20]
v_fma_f64 v[21:22], -v[17:18], v[19:20], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[19:20], v[19:20], v[21:22], v[19:20]
v_div_scale_f64 v[21:22], vcc_lo, v[15:16], v[7:8], v[15:16]
v_mul_f64 v[25:26], v[21:22], v[19:20]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], -v[17:18], v[25:26], v[21:22]
v_div_fmas_f64 v[17:18], v[17:18], v[19:20], v[25:26]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[15:16], v[17:18], v[7:8], v[15:16]
v_add_f64 v[15:16], v[15:16], 2.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f64_e32 v25, v[15:16]
v_cmp_gt_i32_e32 vcc_lo, 1, v25
s_cbranch_vccnz .LBB0_2
v_div_scale_f64 v[15:16], null, s[6:7], s[6:7], 1.0
v_div_scale_f64 v[21:22], vcc_lo, 1.0, s[6:7], 1.0
s_mul_i32 s22, s12, s18
s_ashr_i32 s21, s20, 31
s_ashr_i32 s23, s22, 31
s_lshl_b64 s[40:41], s[20:21], 3
s_lshl_b64 s[22:23], s[22:23], 3
s_mov_b32 s42, 0
s_add_u32 s21, s19, s22
s_addc_u32 s35, s27, s23
s_add_u32 s36, s28, s22
s_addc_u32 s37, s29, s23
s_add_u32 s4, s8, s4
s_addc_u32 s5, s9, s5
s_add_u32 s38, s30, s40
s_load_b64 s[4:5], s[4:5], 0x0
s_addc_u32 s39, s31, s41
s_add_u32 s40, s33, s40
s_addc_u32 s41, s34, s41
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[17:18], v[15:16]
s_waitcnt_depctr 0xfff
v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0
v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0
v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[19:20], v[21:22], v[17:18]
v_fma_f64 v[15:16], -v[15:16], v[19:20], v[21:22]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_div_fmas_f64 v[15:16], v[15:16], v[17:18], v[19:20]
s_waitcnt lgkmcnt(0)
v_add_f64 v[17:18], v[9:10], -s[4:5]
v_mov_b32_e32 v19, 0
v_mov_b32_e32 v20, 0
v_div_fixup_f64 v[15:16], v[15:16], s[6:7], 1.0
s_branch .LBB0_6
.LBB0_5:
v_add_f64 v[19:20], v[19:20], 1.0
s_add_i32 s42, s42, 1
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, s42, v25
s_cbranch_vccnz .LBB0_2
.LBB0_6:
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[21:22], v[7:8], v[19:20], v[17:18]
v_add_f64 v[26:27], v[21:22], 1.0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[21:22], v[15:16], v[21:22], 0.5
v_fma_f64 v[26:27], v[15:16], v[26:27], 0.5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_i32_f64_e32 v21, v[21:22]
v_cvt_i32_f64_e32 v13, v[26:27]
s_delay_alu instid0(VALU_DEP_2)
v_cmp_lt_i32_e32 vcc_lo, -1, v21
ds_store_2addr_b32 v14, v21, v13 offset1:1
s_cbranch_vccnz .LBB0_9
ds_store_b32 v14, v14
.LBB0_9:
v_cmp_lt_i32_e32 vcc_lo, -1, v13
s_cbranch_vccnz .LBB0_11
ds_store_b32 v14, v14 offset:4
.LBB0_11:
ds_load_b32 v13, v14
s_waitcnt lgkmcnt(0)
v_cmp_ge_i32_e32 vcc_lo, s26, v13
s_cbranch_vccnz .LBB0_13
v_mov_b32_e32 v13, s26
ds_store_b32 v14, v13
.LBB0_13:
ds_load_b32 v13, v14 offset:4
s_waitcnt lgkmcnt(0)
v_cmp_ge_i32_e32 vcc_lo, s26, v13
s_cbranch_vccnz .LBB0_15
v_mov_b32_e32 v13, s26
ds_store_b32 v14, v13 offset:4
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[21:22], v14 offset1:1
s_waitcnt lgkmcnt(0)
v_cmp_ge_i32_e32 vcc_lo, v21, v22
v_readfirstlane_b32 s4, v21
s_cbranch_vccnz .LBB0_5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s5, s4, 31
s_lshl_b64 s[22:23], s[4:5], 3
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s6, s38, s22
s_addc_u32 s7, s39, s23
s_add_u32 s22, s40, s22
s_addc_u32 s23, s41, s23
s_branch .LBB0_18
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s3
s_add_i32 s4, s4, 1
s_add_u32 s6, s6, 8
v_cmp_ge_i32_e32 vcc_lo, s4, v22
s_addc_u32 s7, s7, 0
s_add_u32 s22, s22, 8
s_addc_u32 s23, s23, 0
s_cbranch_vccnz .LBB0_5
.LBB0_18:
v_add_nc_u32_e32 v13, s4, v24
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v13
v_cmp_gt_i32_e64 s3, s26, v13
s_and_b32 s5, vcc_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s5
s_cbranch_execz .LBB0_17
v_lshlrev_b64 v[26:27], 3, v[13:14]
s_add_u32 s44, s6, -4
s_addc_u32 s45, s7, -1
s_add_u32 s46, s22, -4
s_addc_u32 s47, s23, -1
v_add_nc_u32_e32 v23, 1, v23
v_add_co_u32 v28, vcc_lo, s21, v26
v_add_co_ci_u32_e32 v29, vcc_lo, s35, v27, vcc_lo
v_add_co_u32 v26, vcc_lo, s36, v26
v_add_co_ci_u32_e32 v27, vcc_lo, s37, v27, vcc_lo
global_load_b64 v[28:29], v[28:29], off
global_load_b64 v[26:27], v[26:27], off
s_clause 0x1
s_load_b32 s5, s[6:7], 0x0
s_load_b32 s43, s[44:45], 0x0
s_clause 0x1
s_load_b32 s44, s[22:23], 0x0
s_load_b32 s45, s[46:47], 0x0
s_waitcnt vmcnt(1) lgkmcnt(0)
v_mul_f32_e32 v21, s43, v29
s_waitcnt vmcnt(0)
v_dual_mul_f32 v13, s5, v29 :: v_dual_mul_f32 v30, s45, v27
v_mul_f32_e32 v31, s5, v27
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_fma_f32 v21, s5, v28, -v21
v_mul_f32_e32 v29, s44, v27
v_mul_f32_e32 v27, s43, v27
v_fmac_f32_e32 v13, s43, v28
v_fma_f32 v28, s44, v26, -v30
v_dual_add_f32 v2, v2, v21 :: v_dual_fmac_f32 v29, s45, v26
v_fmac_f32_e32 v31, s43, v26
v_fma_f32 v26, s5, v26, -v27
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_dual_add_f32 v1, v1, v13 :: v_dual_add_f32 v4, v4, v28
v_add_f32_e32 v3, v3, v29
s_delay_alu instid0(VALU_DEP_3)
v_dual_add_f32 v5, v5, v31 :: v_dual_add_f32 v6, v6, v26
s_branch .LBB0_17
.LBB0_20:
v_dual_mov_b32 v23, 0 :: v_dual_mov_b32 v4, 0
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v6, 0
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v5, 0
.LBB0_21:
s_mul_i32 s8, s15, s16
s_load_b256 s[0:7], s[0:1], 0x38
s_add_i32 s8, s8, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s8, s8, s17
v_add3_u32 v7, s8, s24, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[9:10], 3, v[7:8]
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v11, vcc_lo, s0, v9
v_add_co_ci_u32_e32 v12, vcc_lo, s1, v10, vcc_lo
v_add_co_u32 v13, vcc_lo, s2, v9
v_add_co_ci_u32_e32 v14, vcc_lo, s3, v10, vcc_lo
v_add_co_u32 v9, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_store_b64 v[11:12], v[1:2], off
global_store_b64 v[13:14], v[3:4], off
global_store_b64 v[9:10], v[5:6], off
global_store_b32 v[7:8], v23, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj
.amdhsa_group_segment_fixed_size 8
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 344
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 48
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj, .Lfunc_end0-_Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 80
.size: 8
.value_kind: global_buffer
- .offset: 88
.size: 4
.value_kind: hidden_block_count_x
- .offset: 92
.size: 4
.value_kind: hidden_block_count_y
- .offset: 96
.size: 4
.value_kind: hidden_block_count_z
- .offset: 100
.size: 2
.value_kind: hidden_group_size_x
- .offset: 102
.size: 2
.value_kind: hidden_group_size_y
- .offset: 104
.size: 2
.value_kind: hidden_group_size_z
- .offset: 106
.size: 2
.value_kind: hidden_remainder_x
- .offset: 108
.size: 2
.value_kind: hidden_remainder_y
- .offset: 110
.size: 2
.value_kind: hidden_remainder_z
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 144
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 152
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8
.kernarg_segment_align: 8
.kernarg_segment_size: 344
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj
.private_segment_fixed_size: 0
.sgpr_count: 50
.sgpr_spill_count: 0
.symbol: _Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void cycfold_multichannel(const float2 *pol0, const float2 *pol1,
const double *phase, const double *step,
const int fftlen, const int overlap, const int nbin, const int nlag,
const int num_fft,
float2 *xx, float2 *yy, float2 *xy, unsigned *hits) {
// Lag is specified with threadIdx.x and blockIdx.x since there could be
// more lags than allowed threads.
const int ilaga = threadIdx.x;
const int nlaga = blockDim.x;
const int ilagb = blockIdx.x;
const int ilag = ilagb*nlaga + ilaga;
// Phase bin is blockIdx.y
const int ibin = blockIdx.y;
// Filterbank channel is blockIdx.z
const int ichan = blockIdx.z;
const int num_valid_samples = fftlen - overlap;
// accumulators for the various lag terms
float2 foldxxlag = make_float2(0,0);
float2 foldyylag = make_float2(0,0);
float2 foldxylag = make_float2(0,0);
__shared__ int samp0;
__shared__ int samp1;
// Number of hits for this phase/lag bin
int foldcount = 0;
for (int ifft=0; ifft < num_fft; ifft++){
//Pointers to the first valid sample for this channel and fft
const float2 *ptr0 = pol0 +ichan*fftlen*num_fft + ifft*fftlen + overlap/2;
const float2 *ptr1 = pol1 + ichan*fftlen*num_fft + ifft*fftlen + overlap/2;
// Fold info
const double bin0 = phase[ifft];
const double bins_per_sample = step[ifft]; // bins/sample
const double samples_per_bin = 1.0/bins_per_sample; // samples/bin
const int num_turns = ((double)num_valid_samples*bins_per_sample)/(double)nbin + 2;
// Loop over number of pulse periods in data block
for (int iturn=0; iturn<num_turns; iturn++) {
// Determine range of samples needed for this bin, turn
if(ilaga == 0){
samp0 = samples_per_bin*((double)ibin-bin0+(double)iturn*nbin)+0.5;
samp1 = samples_per_bin*((double)ibin-bin0+(double)iturn*nbin+1)+0.5;
// Range checks
if (samp0<0) { samp0=0; }
if (samp1<0) { samp1=0; }
if (samp0>num_valid_samples) { samp0=num_valid_samples; }
if (samp1>num_valid_samples) { samp1=num_valid_samples; }
}
__syncthreads();
// Read in and add samples
int lag_index;
for (int isamp=samp0; isamp<samp1; isamp++) {
lag_index = isamp + ilag -nlag/2;
if((lag_index >= 0) && (lag_index < num_valid_samples)){
float2 p0 = ptr0[isamp];
float2 p0lag = ptr0[lag_index];
float2 p1 = ptr1[isamp];
float2 p1lag = ptr1[lag_index];
// <Pol0 x Pol0_lag*>
foldxxlag.x += p0.x*p0lag.x + p0.y*p0lag.y;
foldxxlag.y += p0.y*p0lag.x - p0.x*p0lag.y;
// <Pol1 x Pol1_lag*>
foldyylag.x += p1.x*p1lag.x + p1.y*p1lag.y;
foldyylag.y += p1.y*p1lag.x - p1.x*p1lag.y;
// <Pol0 x Pol1_lag*>
foldxylag.x += p0.x*p1lag.x + p0.y*p1lag.y;
foldxylag.y += p0.y*p1lag.x - p0.x*p1lag.y;
foldcount++;
}
}
}
}
xx[ichan*nlag*nbin+nlag*ibin+ilag] = foldxxlag;
yy[ichan*nlag*nbin+nlag*ibin+ilag] = foldyylag;
xy[ichan*nlag*nbin+nlag*ibin+ilag] = foldxylag;
hits[ichan*nlag*nbin+nlag*ibin+ilag] = foldcount;
} | .text
.file "multichannel_shared.hip"
.globl _Z35__device_stub__cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj # -- Begin function _Z35__device_stub__cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj
.p2align 4, 0x90
.type _Z35__device_stub__cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj,@function
_Z35__device_stub__cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj: # @_Z35__device_stub__cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size _Z35__device_stub__cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj, .Lfunc_end0-_Z35__device_stub__cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj,@object # @_Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj
.section .rodata,"a",@progbits
.globl _Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj
.p2align 3, 0x0
_Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj:
.quad _Z35__device_stub__cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj
.size _Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj"
.size .L__unnamed_1, 77
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001220a4_00000000-6_multichannel_shared.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z72__device_stub__Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_PjPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj
.type _Z72__device_stub__Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_PjPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj, @function
_Z72__device_stub__Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_PjPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj:
.LFB2081:
.cfi_startproc
endbr64
subq $264, %rsp
.cfi_def_cfa_offset 272
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movl %r8d, 44(%rsp)
movl %r9d, 40(%rsp)
movq 296(%rsp), %rax
movq %rax, 32(%rsp)
movq 304(%rsp), %rax
movq %rax, 24(%rsp)
movq 312(%rsp), %rax
movq %rax, 16(%rsp)
movq 320(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 44(%rsp), %rax
movq %rax, 176(%rsp)
leaq 40(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 280(%rsp), %rax
movq %rax, 200(%rsp)
leaq 288(%rsp), %rax
movq %rax, 208(%rsp)
leaq 32(%rsp), %rax
movq %rax, 216(%rsp)
leaq 24(%rsp), %rax
movq %rax, 224(%rsp)
leaq 16(%rsp), %rax
movq %rax, 232(%rsp)
leaq 8(%rsp), %rax
movq %rax, 240(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 280
pushq 88(%rsp)
.cfi_def_cfa_offset 288
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 272
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z72__device_stub__Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_PjPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj, .-_Z72__device_stub__Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_PjPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj
.globl _Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj
.type _Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj, @function
_Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj:
.LFB2082:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 72(%rsp)
.cfi_def_cfa_offset 32
pushq 72(%rsp)
.cfi_def_cfa_offset 40
pushq 72(%rsp)
.cfi_def_cfa_offset 48
pushq 72(%rsp)
.cfi_def_cfa_offset 56
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 72
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 80
call _Z72__device_stub__Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_PjPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj
addq $72, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj, .-_Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "multichannel_shared.hip"
.globl _Z35__device_stub__cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj # -- Begin function _Z35__device_stub__cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj
.p2align 4, 0x90
.type _Z35__device_stub__cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj,@function
_Z35__device_stub__cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj: # @_Z35__device_stub__cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size _Z35__device_stub__cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj, .Lfunc_end0-_Z35__device_stub__cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj,@object # @_Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj
.section .rodata,"a",@progbits
.globl _Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj
.p2align 3, 0x0
_Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj:
.quad _Z35__device_stub__cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj
.size _Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj"
.size .L__unnamed_1, 77
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <float.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <time.h>
#define BLOCK_SIZE 50
//Um teste comparando a eficiência de uma
//multiplicação de matrizes por CPU ou GPU
//utilizando memória compartilhada ou global
typedef struct {
int width;
int height;
int stride;
float *elements;
} Matrix;
void startSeed()
{
srand(time(NULL));
int seed = rand();
srand(seed);
}
void draw_random(Matrix mat) {
for (int i = 0; i < mat.height*mat.width; i++)
{
mat.elements[i] = (float) (rand() % 10);
}
}
void disp_img(Matrix mat) {
for (int i = 0; i < mat.height; i++)
{
for (int j = 0; j < mat.width; j++)
{
printf("%5.0f", mat.elements[i*mat.width + j]);
}
printf("\n");
}
printf("\n");
}
Matrix createMatrix(int height, int width)
{
Matrix mat;
mat.width = width;
mat.height = height;
mat.elements = (float*) malloc(mat.width*mat.height*sizeof(float));
for(int i = 0; i < mat.height; i++)
for(int j = 0; j < mat.width; j++)
mat.elements[i*mat.width + j] = 0;
return mat;
}
void multiMatrixCPU(Matrix A, Matrix B, Matrix C)
{
for (int i = 0; i < A.height; i++) {
for (int j = 0; j < B.width; j++) {
C.elements[j + i * B.width] = 0;
for (int k = 0; k < A.width; k++) {
C.elements[j + i * C.width] += A.elements[k + i * A.width] * B.elements[j + k * B.width];
}
}
}
}
__device__ float GetElement(const Matrix A, int row, int col)
{
return A.elements[row * A.stride + col];
}
__device__ void SetElement(Matrix A, int row, int col,
float value)
{
A.elements[row * A.stride + col] = value;
}
__device__ Matrix GetSubMatrix(Matrix A, int row, int col)
{
Matrix Asub;
Asub.width = BLOCK_SIZE;
Asub.height = BLOCK_SIZE;
Asub.stride = A.stride;
Asub.elements = &A.elements[A.stride * BLOCK_SIZE * row + BLOCK_SIZE * col];
return Asub;
}
__global__ void MatMulKernelShared(Matrix A, Matrix B, Matrix C)
{
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
Matrix Csub = GetSubMatrix(C, blockRow, blockCol);
float Cvalue = 0;
int row = threadIdx.y;
int col = threadIdx.x;
for (int m = 0; m < (A.width / BLOCK_SIZE); ++m) {
Matrix Asub = GetSubMatrix(A, blockRow, m);
Matrix Bsub = GetSubMatrix(B, m, blockCol);
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
As[row][col] = GetElement(Asub, row, col);
Bs[row][col] = GetElement(Bsub, row, col);
__syncthreads();
for (int e = 0; e < BLOCK_SIZE; ++e)
Cvalue += As[row][e] * Bs[e][col];
__syncthreads();
}
SetElement(Csub, row, col, Cvalue);
}
void MatMulShared(const Matrix A, const Matrix B, Matrix C)
{
Matrix d_A;
d_A.width = d_A.stride = A.width;
d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
cudaMalloc(&d_A.elements, size);
cudaMemcpy(d_A.elements, A.elements, size, cudaMemcpyHostToDevice);
Matrix d_B;
d_B.width = d_B.stride = B.width;
d_B.height = B.height;
size = B.width * B.height * sizeof(float);
cudaMalloc(&d_B.elements, size);
cudaMemcpy(d_B.elements, B.elements, size, cudaMemcpyHostToDevice);
Matrix d_C;
d_C.width = d_C.stride = C.width;
d_C.height = C.height;
size = C.width * C.height * sizeof(float);
cudaMalloc(&d_C.elements, size);
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B.width / dimBlock.x, A.height / dimBlock.y);
MatMulKernelShared<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
cudaMemcpy(C.elements, d_C.elements, size, cudaMemcpyDeviceToHost);
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
}
__global__ void MatMulKernel(Matrix A, Matrix B, Matrix C)
{
// Each thread computes one element of C
// by accumulating results into Cvalue
float Cvalue = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if (row < A.height && col < B.width)
{
for (int e = 0; e < A.width; e++)
Cvalue += (A.elements[row * A.width + e]) * (B.elements[e * B.width + col]);
C.elements[row * C.width + col] = Cvalue;
}
}
void MatMul(const Matrix A, const Matrix B, Matrix C)
{
// Load A and B to device memory
Matrix d_A;
d_A.width = A.width;
d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
cudaMalloc(&d_A.elements, size);
cudaMemcpy(d_A.elements, A.elements, size, cudaMemcpyHostToDevice);
Matrix d_B;
d_B.width = B.width;
d_B.height = B.height;
size = B.width * B.height * sizeof(float);
cudaMalloc(&d_B.elements, size);
cudaMemcpy(d_B.elements, B.elements, size, cudaMemcpyHostToDevice);
// Allocate C in device memory
Matrix d_C;
d_C.width = C.width;
d_C.height = C.height;
size = C.width * C.height * sizeof(float);
cudaMalloc(&d_C.elements, size);
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid((B.width + dimBlock.x - 1) / dimBlock.x, (A.height + dimBlock.y - 1) / dimBlock.y);
MatMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
cudaThreadSynchronize();
// Read C from device memory
cudaMemcpy(C.elements, d_C.elements, size, cudaMemcpyDeviceToHost);
// Free device memory
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
}
int main(int argc, char* argv[])
{
clock_t tic;
clock_t toc;
Matrix A;
Matrix B;
Matrix C;
int a;
int b;
int c;
startSeed();
int num_devices, device;
printf("Multiplicação de Matrizes\n");
printf("Neste programa foi utilizado um BLOCK_SIZE = 50\n\n");
cudaGetDeviceCount(&num_devices);
for (device = 0; device < num_devices; device++) {
cudaDeviceProp properties;
cudaGetDeviceProperties(&properties, device);
cudaSetDevice(device);
printf("Utilizando uma %s:\n\n", properties.name);
for (int i = 100; i <= 1000; i += 100)
{
a = i;
b = i;
c = i;
A = createMatrix(a, b);
B = createMatrix(b, c);
C = createMatrix(A.height, B.width);
printf("A[%d][%d] * B[%d][%d]\n", a, b, b, c);
draw_random(A);
draw_random(B);
tic = clock();
MatMul(A, B, C);
toc = clock();
printf("GPU (global): %.3fms\n", (double)(toc - tic) / CLOCKS_PER_SEC*1000);
C = createMatrix(A.height, B.width);
draw_random(A);
draw_random(B);
tic = clock();
MatMulShared(A, B, C);
toc = clock();
printf("GPU (shared): %.3fms\n", (double)(toc - tic) / CLOCKS_PER_SEC*1000);
C = createMatrix(A.height, B.width);
draw_random(A);
draw_random(B);
tic = clock();
multiMatrixCPU(A, B, C);
toc = clock();
printf("CPU: %.3fms\n", (double)(toc - tic) / CLOCKS_PER_SEC*1000);
printf("\n");
}
}
} | .file "tmpxft_0006b14f_00000000-6_multiplicaMatrizScript.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2070:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2070:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9startSeedv
.type _Z9startSeedv, @function
_Z9startSeedv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
call rand@PLT
movl %eax, %edi
call srand@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z9startSeedv, .-_Z9startSeedv
.globl _Z11draw_random6Matrix
.type _Z11draw_random6Matrix, @function
_Z11draw_random6Matrix:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl 36(%rsp), %ebp
imull 32(%rsp), %ebp
testl %ebp, %ebp
jle .L5
movslq %ebp, %rbp
salq $2, %rbp
movl $0, %ebx
.L7:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movq 48(%rsp), %rax
movss %xmm0, (%rax,%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L7
.L5:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z11draw_random6Matrix, .-_Z11draw_random6Matrix
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%5.0f"
.LC1:
.string "\n"
.text
.globl _Z8disp_img6Matrix
.type _Z8disp_img6Matrix, @function
_Z8disp_img6Matrix:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl 84(%rsp), %eax
movl %eax, 4(%rsp)
movl 80(%rsp), %r15d
testl %eax, %eax
jle .L11
movl $0, %r14d
movl $0, %r13d
movslq %r15d, %rax
movq %rax, 8(%rsp)
leaq .LC0(%rip), %r12
jmp .L12
.L14:
movslq %r14d, %rbp
leaq 0(,%rbp,4), %rbx
movq 8(%rsp), %rax
addq %rax, %rbp
salq $2, %rbp
.L13:
movq 96(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L13
.L15:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addl %r15d, %r14d
movl 4(%rsp), %eax
cmpl %eax, %r13d
je .L11
.L12:
testl %r15d, %r15d
jg .L14
jmp .L15
.L11:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z8disp_img6Matrix, .-_Z8disp_img6Matrix
.globl _Z12createMatrixii
.type _Z12createMatrixii, @function
_Z12createMatrixii:
.LFB2060:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
movl %esi, %ebp
movl %edx, %ebx
movl %edx, (%rdi)
movl %esi, 4(%rdi)
movl %edx, %edi
imull %esi, %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, 16(%r12)
testl %ebp, %ebp
jle .L18
movl $0, %edi
movl $0, %esi
movslq %ebx, %r8
jmp .L20
.L22:
movslq %edi, %rcx
leaq (%rax,%rcx,4), %rdx
addq %r8, %rcx
leaq (%rax,%rcx,4), %rcx
.L21:
movl $0x00000000, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L21
.L23:
addl $1, %esi
addl %ebx, %edi
cmpl %esi, %ebp
je .L18
.L20:
testl %ebx, %ebx
jg .L22
jmp .L23
.L18:
movq %r12, %rax
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z12createMatrixii, .-_Z12createMatrixii
.globl _Z14multiMatrixCPU6MatrixS_S_
.type _Z14multiMatrixCPU6MatrixS_S_, @function
_Z14multiMatrixCPU6MatrixS_S_:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movl 60(%rsp), %eax
movl %eax, -20(%rsp)
movl 56(%rsp), %r10d
movl 80(%rsp), %r15d
movl 104(%rsp), %esi
movl %esi, -24(%rsp)
movq 120(%rsp), %r12
testl %eax, %eax
jle .L26
movq 72(%rsp), %rax
movq 96(%rsp), %rcx
movq %rcx, -16(%rsp)
movslq %r15d, %rbp
leaq 0(,%rbp,4), %rdi
movl $0, %r11d
movl $0, %ecx
movl $0, %r14d
movl $0, %edx
movslq %r10d, %rsi
movq %rsi, -8(%rsp)
movl %r15d, %r8d
movl %r14d, %esi
jmp .L28
.L32:
movq -16(%rsp), %r13
movslq %esi, %r9
leaq (%r12,%r9,4), %r14
movslq %ecx, %r9
leaq (%rax,%r9,4), %r15
movq -8(%rsp), %rbx
addq %rbx, %r9
leaq (%rax,%r9,4), %r9
movl $0, %ebx
movq %rax, -40(%rsp)
movl %r8d, -32(%rsp)
movl %edx, -28(%rsp)
.L31:
movl $0x00000000, (%r14,%rbx,4)
testl %r10d, %r10d
jle .L29
leal (%r11,%rbx), %eax
cltq
leaq (%r12,%rax,4), %r8
movq %r13, %rdx
movq %r15, %rax
.L30:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
addss (%r8), %xmm0
movss %xmm0, (%r8)
addq $4, %rax
addq %rdi, %rdx
cmpq %r9, %rax
jne .L30
.L29:
addq $1, %rbx
addq $4, %r13
cmpq %rbx, %rbp
jne .L31
movq -40(%rsp), %rax
movl -32(%rsp), %r8d
movl -28(%rsp), %edx
.L33:
addl $1, %edx
addl %r8d, %esi
addl %r10d, %ecx
movl -24(%rsp), %ebx
addl %ebx, %r11d
movl -20(%rsp), %ebx
cmpl %ebx, %edx
je .L26
.L28:
testl %r8d, %r8d
jg .L32
jmp .L33
.L26:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z14multiMatrixCPU6MatrixS_S_, .-_Z14multiMatrixCPU6MatrixS_S_
.globl _Z10GetElement6Matrixii
.type _Z10GetElement6Matrixii, @function
_Z10GetElement6Matrixii:
.LFB2062:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2062:
.size _Z10GetElement6Matrixii, .-_Z10GetElement6Matrixii
.globl _Z10SetElement6Matrixiif
.type _Z10SetElement6Matrixiif, @function
_Z10SetElement6Matrixiif:
.LFB2063:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2063:
.size _Z10SetElement6Matrixiif, .-_Z10SetElement6Matrixiif
.globl _Z12GetSubMatrix6Matrixii
.type _Z12GetSubMatrix6Matrixii, @function
_Z12GetSubMatrix6Matrixii:
.LFB2064:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2064:
.size _Z12GetSubMatrix6Matrixii, .-_Z12GetSubMatrix6Matrixii
.globl _Z47__device_stub__Z18MatMulKernelShared6MatrixS_S_R6MatrixS0_S0_
.type _Z47__device_stub__Z18MatMulKernelShared6MatrixS_S_R6MatrixS0_S0_, @function
_Z47__device_stub__Z18MatMulKernelShared6MatrixS_S_R6MatrixS0_S0_:
.LFB2092:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 80(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 120
pushq 8(%rsp)
.cfi_def_cfa_offset 128
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z18MatMulKernelShared6MatrixS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2092:
.size _Z47__device_stub__Z18MatMulKernelShared6MatrixS_S_R6MatrixS0_S0_, .-_Z47__device_stub__Z18MatMulKernelShared6MatrixS_S_R6MatrixS0_S0_
.globl _Z18MatMulKernelShared6MatrixS_S_
.type _Z18MatMulKernelShared6MatrixS_S_, @function
_Z18MatMulKernelShared6MatrixS_S_:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq 64(%rsp), %rdx
leaq 40(%rsp), %rsi
leaq 16(%rsp), %rdi
call _Z47__device_stub__Z18MatMulKernelShared6MatrixS_S_R6MatrixS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _Z18MatMulKernelShared6MatrixS_S_, .-_Z18MatMulKernelShared6MatrixS_S_
.globl _Z12MatMulShared6MatrixS_S_
.type _Z12MatMulShared6MatrixS_S_, @function
_Z12MatMulShared6MatrixS_S_:
.LFB2065:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $232, %rsp
.cfi_def_cfa_offset 288
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
movl 288(%rsp), %eax
movl 292(%rsp), %r12d
movl 312(%rsp), %ebp
movl 316(%rsp), %r13d
movl 336(%rsp), %ebx
movl 340(%rsp), %r14d
movl %eax, 40(%rsp)
movl %eax, 32(%rsp)
movl %r12d, 36(%rsp)
imull %r12d, %eax
movslq %eax, %r15
salq $2, %r15
leaq 48(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r15, %rdx
movq 304(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebp, 72(%rsp)
movl %ebp, 64(%rsp)
movl %r13d, 68(%rsp)
imull %ebp, %r13d
movslq %r13d, %r13
salq $2, %r13
leaq 80(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq 328(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebx, 104(%rsp)
movl %ebx, 96(%rsp)
movl %r14d, 100(%rsp)
imull %r14d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 112(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %ebp, %ebp
imulq $1374389535, %rbp, %rbp
shrq $36, %rbp
movl %ebp, 20(%rsp)
movl %r12d, %r12d
imulq $1374389535, %r12, %r12
shrq $36, %r12
movl %r12d, 24(%rsp)
movl $50, 8(%rsp)
movl $50, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L55
.L52:
movl $2, %ecx
movq %rbx, %rdx
movq 112(%rsp), %rsi
movq 352(%rsp), %rdi
call cudaMemcpy@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 112(%rsp), %rdi
call cudaFree@PLT
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L56
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
movdqa 32(%rsp), %xmm0
movaps %xmm0, 128(%rsp)
movq 48(%rsp), %rax
movq %rax, 144(%rsp)
movdqa 64(%rsp), %xmm1
movaps %xmm1, 160(%rsp)
movq 80(%rsp), %rax
movq %rax, 176(%rsp)
movdqa 96(%rsp), %xmm2
movaps %xmm2, 192(%rsp)
movq 112(%rsp), %rax
movq %rax, 208(%rsp)
leaq 192(%rsp), %rdx
leaq 160(%rsp), %rsi
leaq 128(%rsp), %rdi
call _Z47__device_stub__Z18MatMulKernelShared6MatrixS_S_R6MatrixS0_S0_
jmp .L52
.L56:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2065:
.size _Z12MatMulShared6MatrixS_S_, .-_Z12MatMulShared6MatrixS_S_
.globl _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
.type _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_, @function
_Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_:
.LFB2094:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 80(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L61
.L57:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L62
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L61:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 120
pushq 8(%rsp)
.cfi_def_cfa_offset 128
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12MatMulKernel6MatrixS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L57
.L62:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2094:
.size _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_, .-_Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
.globl _Z12MatMulKernel6MatrixS_S_
.type _Z12MatMulKernel6MatrixS_S_, @function
_Z12MatMulKernel6MatrixS_S_:
.LFB2095:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq 64(%rsp), %rdx
leaq 40(%rsp), %rsi
leaq 16(%rsp), %rdi
call _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _Z12MatMulKernel6MatrixS_S_, .-_Z12MatMulKernel6MatrixS_S_
.globl _Z6MatMul6MatrixS_S_
.type _Z6MatMul6MatrixS_S_, @function
_Z6MatMul6MatrixS_S_:
.LFB2066:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $232, %rsp
.cfi_def_cfa_offset 288
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
movl 288(%rsp), %r15d
movl 292(%rsp), %r12d
movl 312(%rsp), %r13d
movl 316(%rsp), %ebp
movl 336(%rsp), %ebx
movl 340(%rsp), %r14d
movl %r15d, 32(%rsp)
movl %r12d, 36(%rsp)
imull %r12d, %r15d
movslq %r15d, %r15
salq $2, %r15
leaq 48(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r15, %rdx
movq 304(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %r13d, 64(%rsp)
movl %ebp, 68(%rsp)
imull %r13d, %ebp
movslq %ebp, %rbp
salq $2, %rbp
leaq 80(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 328(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebx, 96(%rsp)
movl %r14d, 100(%rsp)
imull %r14d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 112(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leal 49(%r13), %eax
imulq $1374389535, %rax, %rax
shrq $36, %rax
movl %eax, 20(%rsp)
leal 49(%r12), %eax
imulq $1374389535, %rax, %rax
shrq $36, %rax
movl %eax, 24(%rsp)
movl $50, 8(%rsp)
movl $50, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L69
.L66:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 112(%rsp), %rsi
movq 352(%rsp), %rdi
call cudaMemcpy@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 112(%rsp), %rdi
call cudaFree@PLT
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L70
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L69:
.cfi_restore_state
movdqa 32(%rsp), %xmm0
movaps %xmm0, 128(%rsp)
movq 48(%rsp), %rax
movq %rax, 144(%rsp)
movdqa 64(%rsp), %xmm1
movaps %xmm1, 160(%rsp)
movq 80(%rsp), %rax
movq %rax, 176(%rsp)
movdqa 96(%rsp), %xmm2
movaps %xmm2, 192(%rsp)
movq 112(%rsp), %rax
movq %rax, 208(%rsp)
leaq 192(%rsp), %rdx
leaq 160(%rsp), %rsi
leaq 128(%rsp), %rdi
call _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
jmp .L66
.L70:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2066:
.size _Z6MatMul6MatrixS_S_, .-_Z6MatMul6MatrixS_S_
.section .rodata.str1.1
.LC3:
.string "Multiplica\303\247\303\243o de Matrizes\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Neste programa foi utilizado um BLOCK_SIZE = 50\n\n"
.section .rodata.str1.1
.LC5:
.string "Utilizando uma %s:\n\n"
.LC6:
.string "A[%d][%d] * B[%d][%d]\n"
.LC9:
.string "GPU (global): %.3fms\n"
.LC10:
.string "GPU (shared): %.3fms\n"
.LC11:
.string "CPU: %.3fms\n"
.text
.globl main
.type main, @function
main:
.LFB2067:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1176, %rsp
.cfi_def_cfa_offset 1232
movq %fs:40, %rax
movq %rax, 1160(%rsp)
xorl %eax, %eax
call _Z9startSeedv
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 28(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 28(%rsp)
jle .L72
movl $0, 12(%rsp)
.L74:
leaq 128(%rsp), %rbx
movl 12(%rsp), %r15d
movl %r15d, %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movl %r15d, %edi
call cudaSetDevice@PLT
movq %rbx, %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $100, %ebx
leaq .LC9(%rip), %r15
.L73:
leaq 32(%rsp), %rdi
movl %ebx, %edx
movl %ebx, %esi
call _Z12createMatrixii
movl 36(%rsp), %r12d
leaq 64(%rsp), %rdi
movl %ebx, %edx
movl %ebx, %esi
call _Z12createMatrixii
movl 64(%rsp), %r13d
leaq 96(%rsp), %rbp
movl %r13d, %edx
movl %r12d, %esi
movq %rbp, %rdi
call _Z12createMatrixii
movl %ebx, %r9d
movl %ebx, %r8d
movl %ebx, %ecx
movl %ebx, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
subq $32, %rsp
.cfi_def_cfa_offset 1264
movdqa 64(%rsp), %xmm1
movups %xmm1, (%rsp)
movq 80(%rsp), %rax
movq %rax, 16(%rsp)
call _Z11draw_random6Matrix
movdqa 96(%rsp), %xmm2
movups %xmm2, (%rsp)
movq 112(%rsp), %rax
movq %rax, 16(%rsp)
call _Z11draw_random6Matrix
addq $32, %rsp
.cfi_def_cfa_offset 1232
call clock@PLT
movq %rax, %r14
subq $80, %rsp
.cfi_def_cfa_offset 1312
movdqa 176(%rsp), %xmm3
movups %xmm3, 48(%rsp)
movq 192(%rsp), %rax
movq %rax, 64(%rsp)
movdqa 144(%rsp), %xmm4
movups %xmm4, 24(%rsp)
movq 160(%rsp), %rax
movq %rax, 40(%rsp)
movdqa 112(%rsp), %xmm5
movups %xmm5, (%rsp)
movq 128(%rsp), %rax
movq %rax, 16(%rsp)
call _Z6MatMul6MatrixS_S_
addq $80, %rsp
.cfi_def_cfa_offset 1232
call clock@PLT
subq %r14, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC7(%rip), %xmm0
mulsd .LC8(%rip), %xmm0
movq %r15, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl %r13d, %edx
movl %r12d, %esi
movq %rbp, %rdi
call _Z12createMatrixii
subq $32, %rsp
.cfi_def_cfa_offset 1264
movdqa 64(%rsp), %xmm6
movups %xmm6, (%rsp)
movq 80(%rsp), %rax
movq %rax, 16(%rsp)
call _Z11draw_random6Matrix
movdqa 96(%rsp), %xmm7
movups %xmm7, (%rsp)
movq 112(%rsp), %rax
movq %rax, 16(%rsp)
call _Z11draw_random6Matrix
addq $32, %rsp
.cfi_def_cfa_offset 1232
call clock@PLT
movq %rax, %r14
subq $80, %rsp
.cfi_def_cfa_offset 1312
movdqa 176(%rsp), %xmm1
movups %xmm1, 48(%rsp)
movq 192(%rsp), %rax
movq %rax, 64(%rsp)
movdqa 144(%rsp), %xmm2
movups %xmm2, 24(%rsp)
movq 160(%rsp), %rax
movq %rax, 40(%rsp)
movdqa 112(%rsp), %xmm3
movups %xmm3, (%rsp)
movq 128(%rsp), %rax
movq %rax, 16(%rsp)
call _Z12MatMulShared6MatrixS_S_
addq $80, %rsp
.cfi_def_cfa_offset 1232
call clock@PLT
subq %r14, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC7(%rip), %xmm0
mulsd .LC8(%rip), %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl %r13d, %edx
movl %r12d, %esi
movq %rbp, %rdi
call _Z12createMatrixii
subq $32, %rsp
.cfi_def_cfa_offset 1264
movdqa 64(%rsp), %xmm4
movups %xmm4, (%rsp)
movq 80(%rsp), %rax
movq %rax, 16(%rsp)
call _Z11draw_random6Matrix
movdqa 96(%rsp), %xmm5
movups %xmm5, (%rsp)
movq 112(%rsp), %rax
movq %rax, 16(%rsp)
call _Z11draw_random6Matrix
addq $32, %rsp
.cfi_def_cfa_offset 1232
call clock@PLT
movq %rax, %rbp
subq $80, %rsp
.cfi_def_cfa_offset 1312
movdqa 176(%rsp), %xmm6
movups %xmm6, 48(%rsp)
movq 192(%rsp), %rax
movq %rax, 64(%rsp)
movdqa 144(%rsp), %xmm7
movups %xmm7, 24(%rsp)
movq 160(%rsp), %rax
movq %rax, 40(%rsp)
movdqa 112(%rsp), %xmm1
movups %xmm1, (%rsp)
movq 128(%rsp), %rax
movq %rax, 16(%rsp)
call _Z14multiMatrixCPU6MatrixS_S_
addq $80, %rsp
.cfi_def_cfa_offset 1232
call clock@PLT
subq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC7(%rip), %xmm0
mulsd .LC8(%rip), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $100, %ebx
cmpl $1100, %ebx
jne .L73
addl $1, 12(%rsp)
movl 12(%rsp), %eax
cmpl %eax, 28(%rsp)
jg .L74
.L72:
movq 1160(%rsp), %rax
subq %fs:40, %rax
jne .L79
movl $0, %eax
addq $1176, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L79:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2067:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z12MatMulKernel6MatrixS_S_"
.section .rodata.str1.8
.align 8
.LC13:
.string "_Z18MatMulKernelShared6MatrixS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2097:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z12MatMulKernel6MatrixS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z18MatMulKernelShared6MatrixS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC7:
.long 0
.long 1093567616
.align 8
.LC8:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <float.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <time.h>
#define BLOCK_SIZE 50
//Um teste comparando a eficiência de uma
//multiplicação de matrizes por CPU ou GPU
//utilizando memória compartilhada ou global
typedef struct {
int width;
int height;
int stride;
float *elements;
} Matrix;
void startSeed()
{
srand(time(NULL));
int seed = rand();
srand(seed);
}
void draw_random(Matrix mat) {
for (int i = 0; i < mat.height*mat.width; i++)
{
mat.elements[i] = (float) (rand() % 10);
}
}
void disp_img(Matrix mat) {
for (int i = 0; i < mat.height; i++)
{
for (int j = 0; j < mat.width; j++)
{
printf("%5.0f", mat.elements[i*mat.width + j]);
}
printf("\n");
}
printf("\n");
}
Matrix createMatrix(int height, int width)
{
Matrix mat;
mat.width = width;
mat.height = height;
mat.elements = (float*) malloc(mat.width*mat.height*sizeof(float));
for(int i = 0; i < mat.height; i++)
for(int j = 0; j < mat.width; j++)
mat.elements[i*mat.width + j] = 0;
return mat;
}
void multiMatrixCPU(Matrix A, Matrix B, Matrix C)
{
for (int i = 0; i < A.height; i++) {
for (int j = 0; j < B.width; j++) {
C.elements[j + i * B.width] = 0;
for (int k = 0; k < A.width; k++) {
C.elements[j + i * C.width] += A.elements[k + i * A.width] * B.elements[j + k * B.width];
}
}
}
}
__device__ float GetElement(const Matrix A, int row, int col)
{
return A.elements[row * A.stride + col];
}
__device__ void SetElement(Matrix A, int row, int col,
float value)
{
A.elements[row * A.stride + col] = value;
}
__device__ Matrix GetSubMatrix(Matrix A, int row, int col)
{
Matrix Asub;
Asub.width = BLOCK_SIZE;
Asub.height = BLOCK_SIZE;
Asub.stride = A.stride;
Asub.elements = &A.elements[A.stride * BLOCK_SIZE * row + BLOCK_SIZE * col];
return Asub;
}
__global__ void MatMulKernelShared(Matrix A, Matrix B, Matrix C)
{
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
Matrix Csub = GetSubMatrix(C, blockRow, blockCol);
float Cvalue = 0;
int row = threadIdx.y;
int col = threadIdx.x;
for (int m = 0; m < (A.width / BLOCK_SIZE); ++m) {
Matrix Asub = GetSubMatrix(A, blockRow, m);
Matrix Bsub = GetSubMatrix(B, m, blockCol);
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
As[row][col] = GetElement(Asub, row, col);
Bs[row][col] = GetElement(Bsub, row, col);
__syncthreads();
for (int e = 0; e < BLOCK_SIZE; ++e)
Cvalue += As[row][e] * Bs[e][col];
__syncthreads();
}
SetElement(Csub, row, col, Cvalue);
}
void MatMulShared(const Matrix A, const Matrix B, Matrix C)
{
Matrix d_A;
d_A.width = d_A.stride = A.width;
d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
cudaMalloc(&d_A.elements, size);
cudaMemcpy(d_A.elements, A.elements, size, cudaMemcpyHostToDevice);
Matrix d_B;
d_B.width = d_B.stride = B.width;
d_B.height = B.height;
size = B.width * B.height * sizeof(float);
cudaMalloc(&d_B.elements, size);
cudaMemcpy(d_B.elements, B.elements, size, cudaMemcpyHostToDevice);
Matrix d_C;
d_C.width = d_C.stride = C.width;
d_C.height = C.height;
size = C.width * C.height * sizeof(float);
cudaMalloc(&d_C.elements, size);
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B.width / dimBlock.x, A.height / dimBlock.y);
MatMulKernelShared<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
cudaMemcpy(C.elements, d_C.elements, size, cudaMemcpyDeviceToHost);
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
}
__global__ void MatMulKernel(Matrix A, Matrix B, Matrix C)
{
// Each thread computes one element of C
// by accumulating results into Cvalue
float Cvalue = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if (row < A.height && col < B.width)
{
for (int e = 0; e < A.width; e++)
Cvalue += (A.elements[row * A.width + e]) * (B.elements[e * B.width + col]);
C.elements[row * C.width + col] = Cvalue;
}
}
void MatMul(const Matrix A, const Matrix B, Matrix C)
{
// Load A and B to device memory
Matrix d_A;
d_A.width = A.width;
d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
cudaMalloc(&d_A.elements, size);
cudaMemcpy(d_A.elements, A.elements, size, cudaMemcpyHostToDevice);
Matrix d_B;
d_B.width = B.width;
d_B.height = B.height;
size = B.width * B.height * sizeof(float);
cudaMalloc(&d_B.elements, size);
cudaMemcpy(d_B.elements, B.elements, size, cudaMemcpyHostToDevice);
// Allocate C in device memory
Matrix d_C;
d_C.width = C.width;
d_C.height = C.height;
size = C.width * C.height * sizeof(float);
cudaMalloc(&d_C.elements, size);
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid((B.width + dimBlock.x - 1) / dimBlock.x, (A.height + dimBlock.y - 1) / dimBlock.y);
MatMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
cudaThreadSynchronize();
// Read C from device memory
cudaMemcpy(C.elements, d_C.elements, size, cudaMemcpyDeviceToHost);
// Free device memory
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
}
int main(int argc, char* argv[])
{
clock_t tic;
clock_t toc;
Matrix A;
Matrix B;
Matrix C;
int a;
int b;
int c;
startSeed();
int num_devices, device;
printf("Multiplicação de Matrizes\n");
printf("Neste programa foi utilizado um BLOCK_SIZE = 50\n\n");
cudaGetDeviceCount(&num_devices);
for (device = 0; device < num_devices; device++) {
cudaDeviceProp properties;
cudaGetDeviceProperties(&properties, device);
cudaSetDevice(device);
printf("Utilizando uma %s:\n\n", properties.name);
for (int i = 100; i <= 1000; i += 100)
{
a = i;
b = i;
c = i;
A = createMatrix(a, b);
B = createMatrix(b, c);
C = createMatrix(A.height, B.width);
printf("A[%d][%d] * B[%d][%d]\n", a, b, b, c);
draw_random(A);
draw_random(B);
tic = clock();
MatMul(A, B, C);
toc = clock();
printf("GPU (global): %.3fms\n", (double)(toc - tic) / CLOCKS_PER_SEC*1000);
C = createMatrix(A.height, B.width);
draw_random(A);
draw_random(B);
tic = clock();
MatMulShared(A, B, C);
toc = clock();
printf("GPU (shared): %.3fms\n", (double)(toc - tic) / CLOCKS_PER_SEC*1000);
C = createMatrix(A.height, B.width);
draw_random(A);
draw_random(B);
tic = clock();
multiMatrixCPU(A, B, C);
toc = clock();
printf("CPU: %.3fms\n", (double)(toc - tic) / CLOCKS_PER_SEC*1000);
printf("\n");
}
}
} | #include <hip/hip_runtime.h>
#include <float.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <time.h>
#define BLOCK_SIZE 50
//Um teste comparando a eficiência de uma
//multiplicação de matrizes por CPU ou GPU
//utilizando memória compartilhada ou global
typedef struct {
int width;
int height;
int stride;
float *elements;
} Matrix;
void startSeed()
{
srand(time(NULL));
int seed = rand();
srand(seed);
}
void draw_random(Matrix mat) {
for (int i = 0; i < mat.height*mat.width; i++)
{
mat.elements[i] = (float) (rand() % 10);
}
}
void disp_img(Matrix mat) {
for (int i = 0; i < mat.height; i++)
{
for (int j = 0; j < mat.width; j++)
{
printf("%5.0f", mat.elements[i*mat.width + j]);
}
printf("\n");
}
printf("\n");
}
Matrix createMatrix(int height, int width)
{
Matrix mat;
mat.width = width;
mat.height = height;
mat.elements = (float*) malloc(mat.width*mat.height*sizeof(float));
for(int i = 0; i < mat.height; i++)
for(int j = 0; j < mat.width; j++)
mat.elements[i*mat.width + j] = 0;
return mat;
}
void multiMatrixCPU(Matrix A, Matrix B, Matrix C)
{
for (int i = 0; i < A.height; i++) {
for (int j = 0; j < B.width; j++) {
C.elements[j + i * B.width] = 0;
for (int k = 0; k < A.width; k++) {
C.elements[j + i * C.width] += A.elements[k + i * A.width] * B.elements[j + k * B.width];
}
}
}
}
__device__ float GetElement(const Matrix A, int row, int col)
{
return A.elements[row * A.stride + col];
}
__device__ void SetElement(Matrix A, int row, int col,
float value)
{
A.elements[row * A.stride + col] = value;
}
__device__ Matrix GetSubMatrix(Matrix A, int row, int col)
{
Matrix Asub;
Asub.width = BLOCK_SIZE;
Asub.height = BLOCK_SIZE;
Asub.stride = A.stride;
Asub.elements = &A.elements[A.stride * BLOCK_SIZE * row + BLOCK_SIZE * col];
return Asub;
}
__global__ void MatMulKernelShared(Matrix A, Matrix B, Matrix C)
{
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
Matrix Csub = GetSubMatrix(C, blockRow, blockCol);
float Cvalue = 0;
int row = threadIdx.y;
int col = threadIdx.x;
for (int m = 0; m < (A.width / BLOCK_SIZE); ++m) {
Matrix Asub = GetSubMatrix(A, blockRow, m);
Matrix Bsub = GetSubMatrix(B, m, blockCol);
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
As[row][col] = GetElement(Asub, row, col);
Bs[row][col] = GetElement(Bsub, row, col);
__syncthreads();
for (int e = 0; e < BLOCK_SIZE; ++e)
Cvalue += As[row][e] * Bs[e][col];
__syncthreads();
}
SetElement(Csub, row, col, Cvalue);
}
void MatMulShared(const Matrix A, const Matrix B, Matrix C)
{
Matrix d_A;
d_A.width = d_A.stride = A.width;
d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
hipMalloc(&d_A.elements, size);
hipMemcpy(d_A.elements, A.elements, size, hipMemcpyHostToDevice);
Matrix d_B;
d_B.width = d_B.stride = B.width;
d_B.height = B.height;
size = B.width * B.height * sizeof(float);
hipMalloc(&d_B.elements, size);
hipMemcpy(d_B.elements, B.elements, size, hipMemcpyHostToDevice);
Matrix d_C;
d_C.width = d_C.stride = C.width;
d_C.height = C.height;
size = C.width * C.height * sizeof(float);
hipMalloc(&d_C.elements, size);
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B.width / dimBlock.x, A.height / dimBlock.y);
MatMulKernelShared<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
hipMemcpy(C.elements, d_C.elements, size, hipMemcpyDeviceToHost);
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
}
__global__ void MatMulKernel(Matrix A, Matrix B, Matrix C)
{
// Each thread computes one element of C
// by accumulating results into Cvalue
float Cvalue = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if (row < A.height && col < B.width)
{
for (int e = 0; e < A.width; e++)
Cvalue += (A.elements[row * A.width + e]) * (B.elements[e * B.width + col]);
C.elements[row * C.width + col] = Cvalue;
}
}
void MatMul(const Matrix A, const Matrix B, Matrix C)
{
// Load A and B to device memory
Matrix d_A;
d_A.width = A.width;
d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
hipMalloc(&d_A.elements, size);
hipMemcpy(d_A.elements, A.elements, size, hipMemcpyHostToDevice);
Matrix d_B;
d_B.width = B.width;
d_B.height = B.height;
size = B.width * B.height * sizeof(float);
hipMalloc(&d_B.elements, size);
hipMemcpy(d_B.elements, B.elements, size, hipMemcpyHostToDevice);
// Allocate C in device memory
Matrix d_C;
d_C.width = C.width;
d_C.height = C.height;
size = C.width * C.height * sizeof(float);
hipMalloc(&d_C.elements, size);
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid((B.width + dimBlock.x - 1) / dimBlock.x, (A.height + dimBlock.y - 1) / dimBlock.y);
MatMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
hipDeviceSynchronize();
// Read C from device memory
hipMemcpy(C.elements, d_C.elements, size, hipMemcpyDeviceToHost);
// Free device memory
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
}
int main(int argc, char* argv[])
{
clock_t tic;
clock_t toc;
Matrix A;
Matrix B;
Matrix C;
int a;
int b;
int c;
startSeed();
int num_devices, device;
printf("Multiplicação de Matrizes\n");
printf("Neste programa foi utilizado um BLOCK_SIZE = 50\n\n");
hipGetDeviceCount(&num_devices);
for (device = 0; device < num_devices; device++) {
hipDeviceProp_t properties;
hipGetDeviceProperties(&properties, device);
hipSetDevice(device);
printf("Utilizando uma %s:\n\n", properties.name);
for (int i = 100; i <= 1000; i += 100)
{
a = i;
b = i;
c = i;
A = createMatrix(a, b);
B = createMatrix(b, c);
C = createMatrix(A.height, B.width);
printf("A[%d][%d] * B[%d][%d]\n", a, b, b, c);
draw_random(A);
draw_random(B);
tic = clock();
MatMul(A, B, C);
toc = clock();
printf("GPU (global): %.3fms\n", (double)(toc - tic) / CLOCKS_PER_SEC*1000);
C = createMatrix(A.height, B.width);
draw_random(A);
draw_random(B);
tic = clock();
MatMulShared(A, B, C);
toc = clock();
printf("GPU (shared): %.3fms\n", (double)(toc - tic) / CLOCKS_PER_SEC*1000);
C = createMatrix(A.height, B.width);
draw_random(A);
draw_random(B);
tic = clock();
multiMatrixCPU(A, B, C);
toc = clock();
printf("CPU: %.3fms\n", (double)(toc - tic) / CLOCKS_PER_SEC*1000);
printf("\n");
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <float.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <time.h>
#define BLOCK_SIZE 50
//Um teste comparando a eficiência de uma
//multiplicação de matrizes por CPU ou GPU
//utilizando memória compartilhada ou global
typedef struct {
int width;
int height;
int stride;
float *elements;
} Matrix;
void startSeed()
{
srand(time(NULL));
int seed = rand();
srand(seed);
}
void draw_random(Matrix mat) {
for (int i = 0; i < mat.height*mat.width; i++)
{
mat.elements[i] = (float) (rand() % 10);
}
}
void disp_img(Matrix mat) {
for (int i = 0; i < mat.height; i++)
{
for (int j = 0; j < mat.width; j++)
{
printf("%5.0f", mat.elements[i*mat.width + j]);
}
printf("\n");
}
printf("\n");
}
Matrix createMatrix(int height, int width)
{
Matrix mat;
mat.width = width;
mat.height = height;
mat.elements = (float*) malloc(mat.width*mat.height*sizeof(float));
for(int i = 0; i < mat.height; i++)
for(int j = 0; j < mat.width; j++)
mat.elements[i*mat.width + j] = 0;
return mat;
}
void multiMatrixCPU(Matrix A, Matrix B, Matrix C)
{
for (int i = 0; i < A.height; i++) {
for (int j = 0; j < B.width; j++) {
C.elements[j + i * B.width] = 0;
for (int k = 0; k < A.width; k++) {
C.elements[j + i * C.width] += A.elements[k + i * A.width] * B.elements[j + k * B.width];
}
}
}
}
__device__ float GetElement(const Matrix A, int row, int col)
{
return A.elements[row * A.stride + col];
}
__device__ void SetElement(Matrix A, int row, int col,
float value)
{
A.elements[row * A.stride + col] = value;
}
__device__ Matrix GetSubMatrix(Matrix A, int row, int col)
{
Matrix Asub;
Asub.width = BLOCK_SIZE;
Asub.height = BLOCK_SIZE;
Asub.stride = A.stride;
Asub.elements = &A.elements[A.stride * BLOCK_SIZE * row + BLOCK_SIZE * col];
return Asub;
}
__global__ void MatMulKernelShared(Matrix A, Matrix B, Matrix C)
{
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
Matrix Csub = GetSubMatrix(C, blockRow, blockCol);
float Cvalue = 0;
int row = threadIdx.y;
int col = threadIdx.x;
for (int m = 0; m < (A.width / BLOCK_SIZE); ++m) {
Matrix Asub = GetSubMatrix(A, blockRow, m);
Matrix Bsub = GetSubMatrix(B, m, blockCol);
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
As[row][col] = GetElement(Asub, row, col);
Bs[row][col] = GetElement(Bsub, row, col);
__syncthreads();
for (int e = 0; e < BLOCK_SIZE; ++e)
Cvalue += As[row][e] * Bs[e][col];
__syncthreads();
}
SetElement(Csub, row, col, Cvalue);
}
void MatMulShared(const Matrix A, const Matrix B, Matrix C)
{
Matrix d_A;
d_A.width = d_A.stride = A.width;
d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
hipMalloc(&d_A.elements, size);
hipMemcpy(d_A.elements, A.elements, size, hipMemcpyHostToDevice);
Matrix d_B;
d_B.width = d_B.stride = B.width;
d_B.height = B.height;
size = B.width * B.height * sizeof(float);
hipMalloc(&d_B.elements, size);
hipMemcpy(d_B.elements, B.elements, size, hipMemcpyHostToDevice);
Matrix d_C;
d_C.width = d_C.stride = C.width;
d_C.height = C.height;
size = C.width * C.height * sizeof(float);
hipMalloc(&d_C.elements, size);
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B.width / dimBlock.x, A.height / dimBlock.y);
MatMulKernelShared<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
hipMemcpy(C.elements, d_C.elements, size, hipMemcpyDeviceToHost);
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
}
__global__ void MatMulKernel(Matrix A, Matrix B, Matrix C)
{
// Each thread computes one element of C
// by accumulating results into Cvalue
float Cvalue = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if (row < A.height && col < B.width)
{
for (int e = 0; e < A.width; e++)
Cvalue += (A.elements[row * A.width + e]) * (B.elements[e * B.width + col]);
C.elements[row * C.width + col] = Cvalue;
}
}
void MatMul(const Matrix A, const Matrix B, Matrix C)
{
// Load A and B to device memory
Matrix d_A;
d_A.width = A.width;
d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
hipMalloc(&d_A.elements, size);
hipMemcpy(d_A.elements, A.elements, size, hipMemcpyHostToDevice);
Matrix d_B;
d_B.width = B.width;
d_B.height = B.height;
size = B.width * B.height * sizeof(float);
hipMalloc(&d_B.elements, size);
hipMemcpy(d_B.elements, B.elements, size, hipMemcpyHostToDevice);
// Allocate C in device memory
Matrix d_C;
d_C.width = C.width;
d_C.height = C.height;
size = C.width * C.height * sizeof(float);
hipMalloc(&d_C.elements, size);
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid((B.width + dimBlock.x - 1) / dimBlock.x, (A.height + dimBlock.y - 1) / dimBlock.y);
MatMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
hipDeviceSynchronize();
// Read C from device memory
hipMemcpy(C.elements, d_C.elements, size, hipMemcpyDeviceToHost);
// Free device memory
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
}
int main(int argc, char* argv[])
{
clock_t tic;
clock_t toc;
Matrix A;
Matrix B;
Matrix C;
int a;
int b;
int c;
startSeed();
int num_devices, device;
printf("Multiplicação de Matrizes\n");
printf("Neste programa foi utilizado um BLOCK_SIZE = 50\n\n");
hipGetDeviceCount(&num_devices);
for (device = 0; device < num_devices; device++) {
hipDeviceProp_t properties;
hipGetDeviceProperties(&properties, device);
hipSetDevice(device);
printf("Utilizando uma %s:\n\n", properties.name);
for (int i = 100; i <= 1000; i += 100)
{
a = i;
b = i;
c = i;
A = createMatrix(a, b);
B = createMatrix(b, c);
C = createMatrix(A.height, B.width);
printf("A[%d][%d] * B[%d][%d]\n", a, b, b, c);
draw_random(A);
draw_random(B);
tic = clock();
MatMul(A, B, C);
toc = clock();
printf("GPU (global): %.3fms\n", (double)(toc - tic) / CLOCKS_PER_SEC*1000);
C = createMatrix(A.height, B.width);
draw_random(A);
draw_random(B);
tic = clock();
MatMulShared(A, B, C);
toc = clock();
printf("GPU (shared): %.3fms\n", (double)(toc - tic) / CLOCKS_PER_SEC*1000);
C = createMatrix(A.height, B.width);
draw_random(A);
draw_random(B);
tic = clock();
multiMatrixCPU(A, B, C);
toc = clock();
printf("CPU: %.3fms\n", (double)(toc - tic) / CLOCKS_PER_SEC*1000);
printf("\n");
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18MatMulKernelShared6MatrixS_S_
.globl _Z18MatMulKernelShared6MatrixS_S_
.p2align 8
.type _Z18MatMulKernelShared6MatrixS_S_,@function
_Z18MatMulKernelShared6MatrixS_S_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x40
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s5, 50
s_cbranch_scc1 .LBB0_5
s_clause 0x3
s_load_b32 s10, s[0:1], 0x8
s_load_b32 s4, s[0:1], 0x20
s_load_b64 s[6:7], s[0:1], 0x10
s_load_b64 s[8:9], s[0:1], 0x28
v_lshlrev_b32_e32 v2, 2, v0
s_mul_hi_i32 s5, s5, 0x51eb851f
v_mul_u32_u24_e32 v3, 0xc8, v1
s_lshr_b32 s11, s5, 31
s_ashr_i32 s5, s5, 4
v_add_nc_u32_e32 v4, 0x2710, v2
s_add_i32 s5, s5, s11
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[5:6], null, s10, v1, v[0:1]
v_mad_u64_u32 v[7:8], null, s4, v1, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v6, 31, v5
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[9:10], 2, v[5:6]
v_mad_u32_u24 v5, v1, 0xc8, v2
v_lshlrev_b64 v[11:12], 2, v[7:8]
v_mad_u32_u24 v6, v1, 0xc8, v4
v_mov_b32_e32 v2, 0
v_add_co_u32 v7, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v10, vcc_lo
v_add_co_u32 v9, vcc_lo, s8, v11
v_add_co_ci_u32_e32 v10, vcc_lo, s9, v12, vcc_lo
s_mul_i32 s6, s10, s15
s_mov_b32 s7, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_mul_i32 s8, s7, s4
s_add_i32 s9, s7, s6
s_add_i32 s10, s8, s14
s_mul_i32 s8, s9, 50
s_mul_i32 s10, s10, 50
s_ashr_i32 s9, s8, 31
s_ashr_i32 s11, s10, 31
s_lshl_b64 s[8:9], s[8:9], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_u32 v11, vcc_lo, v7, s8
v_add_co_ci_u32_e32 v12, vcc_lo, s9, v8, vcc_lo
s_lshl_b64 s[8:9], s[10:11], 2
v_add_co_u32 v13, vcc_lo, v9, s8
v_add_co_ci_u32_e32 v14, vcc_lo, s9, v10, vcc_lo
global_load_b32 v12, v[11:12], off
global_load_b32 v13, v[13:14], off
v_mov_b32_e32 v11, v4
s_mov_b32 s8, 0
s_waitcnt vmcnt(1)
ds_store_b32 v5, v12
s_waitcnt vmcnt(0)
ds_store_b32 v6, v13
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v12, s8, v3
s_add_i32 s8, s8, 4
ds_load_b32 v13, v11
ds_load_b32 v12, v12
v_add_nc_u32_e32 v11, 0xc8, v11
s_cmpk_eq_i32 s8, 0xc8
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v12, v13
s_cbranch_scc0 .LBB0_3
s_add_i32 s7, s7, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s7, s5
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_load_b32 s0, s[0:1], 0x38
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[3:4], null, s0, v1, v[0:1]
s_mul_i32 s0, s0, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s0, s14
s_mul_i32 s0, s0, 50
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_ashr_i32 s1, s0, 31
v_ashrrev_i32_e32 v4, 31, v3
s_lshl_b64 s[0:1], s[0:1], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18MatMulKernelShared6MatrixS_S_
.amdhsa_group_segment_fixed_size 20000
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 72
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18MatMulKernelShared6MatrixS_S_, .Lfunc_end0-_Z18MatMulKernelShared6MatrixS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12MatMulKernel6MatrixS_S_
.globl _Z12MatMulKernel6MatrixS_S_
.p2align 8
.type _Z12MatMulKernel6MatrixS_S_,@function
_Z12MatMulKernel6MatrixS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x54
s_load_b32 s3, s[0:1], 0x4
s_load_b32 s6, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s7, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[0:1], null, s15, s7, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s3, v0
v_cmp_gt_i32_e64 s2, s6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_6
s_clause 0x1
s_load_b32 s7, s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x40
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s7, 1
s_cbranch_scc1 .LBB1_4
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b64 s[4:5], s[4:5], 0x10
v_mul_lo_u32 v2, v0, s7
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
.p2align 6
.LBB1_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s7, s7, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s7, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s6, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB1_3
s_branch .LBB1_5
.LBB1_4:
v_mov_b32_e32 v6, 0
.LBB1_5:
s_load_b32 s0, s[0:1], 0x30
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB1_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12MatMulKernel6MatrixS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 328
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z12MatMulKernel6MatrixS_S_, .Lfunc_end1-_Z12MatMulKernel6MatrixS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 24
.value_kind: by_value
- .offset: 24
.size: 24
.value_kind: by_value
- .offset: 48
.size: 24
.value_kind: by_value
.group_segment_fixed_size: 20000
.kernarg_segment_align: 8
.kernarg_segment_size: 72
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18MatMulKernelShared6MatrixS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18MatMulKernelShared6MatrixS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 24
.value_kind: by_value
- .offset: 24
.size: 24
.value_kind: by_value
- .offset: 48
.size: 24
.value_kind: by_value
- .offset: 72
.size: 4
.value_kind: hidden_block_count_x
- .offset: 76
.size: 4
.value_kind: hidden_block_count_y
- .offset: 80
.size: 4
.value_kind: hidden_block_count_z
- .offset: 84
.size: 2
.value_kind: hidden_group_size_x
- .offset: 86
.size: 2
.value_kind: hidden_group_size_y
- .offset: 88
.size: 2
.value_kind: hidden_group_size_z
- .offset: 90
.size: 2
.value_kind: hidden_remainder_x
- .offset: 92
.size: 2
.value_kind: hidden_remainder_y
- .offset: 94
.size: 2
.value_kind: hidden_remainder_z
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 136
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 328
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12MatMulKernel6MatrixS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12MatMulKernel6MatrixS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <float.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <time.h>
#define BLOCK_SIZE 50
//Um teste comparando a eficiência de uma
//multiplicação de matrizes por CPU ou GPU
//utilizando memória compartilhada ou global
typedef struct {
int width;
int height;
int stride;
float *elements;
} Matrix;
void startSeed()
{
srand(time(NULL));
int seed = rand();
srand(seed);
}
void draw_random(Matrix mat) {
for (int i = 0; i < mat.height*mat.width; i++)
{
mat.elements[i] = (float) (rand() % 10);
}
}
void disp_img(Matrix mat) {
for (int i = 0; i < mat.height; i++)
{
for (int j = 0; j < mat.width; j++)
{
printf("%5.0f", mat.elements[i*mat.width + j]);
}
printf("\n");
}
printf("\n");
}
Matrix createMatrix(int height, int width)
{
Matrix mat;
mat.width = width;
mat.height = height;
mat.elements = (float*) malloc(mat.width*mat.height*sizeof(float));
for(int i = 0; i < mat.height; i++)
for(int j = 0; j < mat.width; j++)
mat.elements[i*mat.width + j] = 0;
return mat;
}
void multiMatrixCPU(Matrix A, Matrix B, Matrix C)
{
for (int i = 0; i < A.height; i++) {
for (int j = 0; j < B.width; j++) {
C.elements[j + i * B.width] = 0;
for (int k = 0; k < A.width; k++) {
C.elements[j + i * C.width] += A.elements[k + i * A.width] * B.elements[j + k * B.width];
}
}
}
}
__device__ float GetElement(const Matrix A, int row, int col)
{
return A.elements[row * A.stride + col];
}
__device__ void SetElement(Matrix A, int row, int col,
float value)
{
A.elements[row * A.stride + col] = value;
}
__device__ Matrix GetSubMatrix(Matrix A, int row, int col)
{
Matrix Asub;
Asub.width = BLOCK_SIZE;
Asub.height = BLOCK_SIZE;
Asub.stride = A.stride;
Asub.elements = &A.elements[A.stride * BLOCK_SIZE * row + BLOCK_SIZE * col];
return Asub;
}
__global__ void MatMulKernelShared(Matrix A, Matrix B, Matrix C)
{
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
Matrix Csub = GetSubMatrix(C, blockRow, blockCol);
float Cvalue = 0;
int row = threadIdx.y;
int col = threadIdx.x;
for (int m = 0; m < (A.width / BLOCK_SIZE); ++m) {
Matrix Asub = GetSubMatrix(A, blockRow, m);
Matrix Bsub = GetSubMatrix(B, m, blockCol);
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
As[row][col] = GetElement(Asub, row, col);
Bs[row][col] = GetElement(Bsub, row, col);
__syncthreads();
for (int e = 0; e < BLOCK_SIZE; ++e)
Cvalue += As[row][e] * Bs[e][col];
__syncthreads();
}
SetElement(Csub, row, col, Cvalue);
}
void MatMulShared(const Matrix A, const Matrix B, Matrix C)
{
Matrix d_A;
d_A.width = d_A.stride = A.width;
d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
hipMalloc(&d_A.elements, size);
hipMemcpy(d_A.elements, A.elements, size, hipMemcpyHostToDevice);
Matrix d_B;
d_B.width = d_B.stride = B.width;
d_B.height = B.height;
size = B.width * B.height * sizeof(float);
hipMalloc(&d_B.elements, size);
hipMemcpy(d_B.elements, B.elements, size, hipMemcpyHostToDevice);
Matrix d_C;
d_C.width = d_C.stride = C.width;
d_C.height = C.height;
size = C.width * C.height * sizeof(float);
hipMalloc(&d_C.elements, size);
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B.width / dimBlock.x, A.height / dimBlock.y);
MatMulKernelShared<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
hipMemcpy(C.elements, d_C.elements, size, hipMemcpyDeviceToHost);
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
}
__global__ void MatMulKernel(Matrix A, Matrix B, Matrix C)
{
// Each thread computes one element of C
// by accumulating results into Cvalue
float Cvalue = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if (row < A.height && col < B.width)
{
for (int e = 0; e < A.width; e++)
Cvalue += (A.elements[row * A.width + e]) * (B.elements[e * B.width + col]);
C.elements[row * C.width + col] = Cvalue;
}
}
void MatMul(const Matrix A, const Matrix B, Matrix C)
{
// Load A and B to device memory
Matrix d_A;
d_A.width = A.width;
d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
hipMalloc(&d_A.elements, size);
hipMemcpy(d_A.elements, A.elements, size, hipMemcpyHostToDevice);
Matrix d_B;
d_B.width = B.width;
d_B.height = B.height;
size = B.width * B.height * sizeof(float);
hipMalloc(&d_B.elements, size);
hipMemcpy(d_B.elements, B.elements, size, hipMemcpyHostToDevice);
// Allocate C in device memory
Matrix d_C;
d_C.width = C.width;
d_C.height = C.height;
size = C.width * C.height * sizeof(float);
hipMalloc(&d_C.elements, size);
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid((B.width + dimBlock.x - 1) / dimBlock.x, (A.height + dimBlock.y - 1) / dimBlock.y);
MatMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
hipDeviceSynchronize();
// Read C from device memory
hipMemcpy(C.elements, d_C.elements, size, hipMemcpyDeviceToHost);
// Free device memory
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
}
int main(int argc, char* argv[])
{
clock_t tic;
clock_t toc;
Matrix A;
Matrix B;
Matrix C;
int a;
int b;
int c;
startSeed();
int num_devices, device;
printf("Multiplicação de Matrizes\n");
printf("Neste programa foi utilizado um BLOCK_SIZE = 50\n\n");
hipGetDeviceCount(&num_devices);
for (device = 0; device < num_devices; device++) {
hipDeviceProp_t properties;
hipGetDeviceProperties(&properties, device);
hipSetDevice(device);
printf("Utilizando uma %s:\n\n", properties.name);
for (int i = 100; i <= 1000; i += 100)
{
a = i;
b = i;
c = i;
A = createMatrix(a, b);
B = createMatrix(b, c);
C = createMatrix(A.height, B.width);
printf("A[%d][%d] * B[%d][%d]\n", a, b, b, c);
draw_random(A);
draw_random(B);
tic = clock();
MatMul(A, B, C);
toc = clock();
printf("GPU (global): %.3fms\n", (double)(toc - tic) / CLOCKS_PER_SEC*1000);
C = createMatrix(A.height, B.width);
draw_random(A);
draw_random(B);
tic = clock();
MatMulShared(A, B, C);
toc = clock();
printf("GPU (shared): %.3fms\n", (double)(toc - tic) / CLOCKS_PER_SEC*1000);
C = createMatrix(A.height, B.width);
draw_random(A);
draw_random(B);
tic = clock();
multiMatrixCPU(A, B, C);
toc = clock();
printf("CPU: %.3fms\n", (double)(toc - tic) / CLOCKS_PER_SEC*1000);
printf("\n");
}
}
} | .text
.file "multiplicaMatrizScript.hip"
.globl _Z9startSeedv # -- Begin function _Z9startSeedv
.p2align 4, 0x90
.type _Z9startSeedv,@function
_Z9startSeedv: # @_Z9startSeedv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
callq rand
movl %eax, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp srand # TAILCALL
.Lfunc_end0:
.size _Z9startSeedv, .Lfunc_end0-_Z9startSeedv
.cfi_endproc
# -- End function
.globl _Z11draw_random6Matrix # -- Begin function _Z11draw_random6Matrix
.p2align 4, 0x90
.type _Z11draw_random6Matrix,@function
_Z11draw_random6Matrix: # @_Z11draw_random6Matrix
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl 32(%rsp), %eax
imull 36(%rsp), %eax
testl %eax, %eax
jle .LBB1_3
# %bb.1: # %.lr.ph
leaq 32(%rsp), %rcx
movq 16(%rcx), %rbx
movl %eax, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
.LBB1_3: # %._crit_edge
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11draw_random6Matrix, .Lfunc_end1-_Z11draw_random6Matrix
.cfi_endproc
# -- End function
.globl _Z8disp_img6Matrix # -- Begin function _Z8disp_img6Matrix
.p2align 4, 0x90
.type _Z8disp_img6Matrix,@function
_Z8disp_img6Matrix: # @_Z8disp_img6Matrix
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl 68(%rsp), %ebx
testl %ebx, %ebx
jle .LBB2_6
# %bb.1: # %.preheader.lr.ph
leaq 64(%rsp), %rax
movl (%rax), %r14d
movq 16(%rax), %rax
movq %rax, (%rsp) # 8-byte Spill
xorl %r12d, %r12d
xorl %r13d, %r13d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addl %r14d, %r12d
cmpq %rbx, %r13
je .LBB2_6
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
testl %r14d, %r14d
jle .LBB2_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
movl %r12d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbp,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB2_4
jmp .LBB2_5
.LBB2_6: # %._crit_edge11
movl $10, %edi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end2:
.size _Z8disp_img6Matrix, .Lfunc_end2-_Z8disp_img6Matrix
.cfi_endproc
# -- End function
.globl _Z12createMatrixii # -- Begin function _Z12createMatrixii
.p2align 4, 0x90
.type _Z12createMatrixii,@function
_Z12createMatrixii: # @_Z12createMatrixii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movl %esi, %ebp
movq %rdi, %r14
movl %edx, (%rdi)
movl %esi, 4(%rdi)
movl %edx, %eax
imull %esi, %eax
movslq %eax, %rdi
shlq $2, %rdi
callq malloc
movq %rax, 16(%r14)
testl %ebp, %ebp
jle .LBB3_5
# %bb.1: # %.preheader.lr.ph
movq %rax, %r15
movl %ebx, %r12d
shlq $2, %r12
movl %ebp, %r13d
xorl %ebp, %ebp
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_4: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
addl %ebx, %ebp
decq %r13
je .LBB3_5
.LBB3_2: # %.preheader
# =>This Inner Loop Header: Depth=1
testl %ebx, %ebx
jle .LBB3_4
# %bb.3: # %.lr.ph
# in Loop: Header=BB3_2 Depth=1
movl %ebp, %eax
leaq (%r15,%rax,4), %rdi
xorl %esi, %esi
movq %r12, %rdx
callq memset@PLT
jmp .LBB3_4
.LBB3_5: # %._crit_edge12
movq %r14, %rax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z12createMatrixii, .Lfunc_end3-_Z12createMatrixii
.cfi_endproc
# -- End function
.globl _Z14multiMatrixCPU6MatrixS_S_ # -- Begin function _Z14multiMatrixCPU6MatrixS_S_
.p2align 4, 0x90
.type _Z14multiMatrixCPU6MatrixS_S_,@function
_Z14multiMatrixCPU6MatrixS_S_: # @_Z14multiMatrixCPU6MatrixS_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl 60(%rsp), %eax
testl %eax, %eax
jle .LBB4_9
# %bb.1: # %.preheader.lr.ph
leaq 104(%rsp), %rdi
leaq 80(%rsp), %r8
leaq 56(%rsp), %r9
movl (%r8), %ecx
movq 16(%rdi), %rdx
movl (%r9), %esi
movq 16(%r9), %r9
movq %r9, -8(%rsp) # 8-byte Spill
movq 16(%r8), %r8
movq %r8, -16(%rsp) # 8-byte Spill
movslq (%rdi), %rdi
movq %rdi, -24(%rsp) # 8-byte Spill
movslq %ecx, %r10
leaq (,%r10,4), %r11
xorl %ebx, %ebx
xorl %r14d, %r14d
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_8: # %._crit_edge21
# in Loop: Header=BB4_2 Depth=1
incq %r14
addl %esi, %ebx
cmpq %rax, %r14
je .LBB4_9
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_4 Depth 2
# Child Loop BB4_6 Depth 3
testl %ecx, %ecx
jle .LBB4_8
# %bb.3: # %.lr.ph20
# in Loop: Header=BB4_2 Depth=1
movl %ebx, %edi
movq -8(%rsp), %r8 # 8-byte Reload
leaq (%r8,%rdi,4), %r15
movq %r14, %rdi
imulq %r10, %rdi
movq %r14, %r8
imulq -24(%rsp), %r8 # 8-byte Folded Reload
leaq (%rdx,%rdi,4), %r12
leaq (%rdx,%r8,4), %r13
movq -16(%rsp), %r8 # 8-byte Reload
xorl %edi, %edi
jmp .LBB4_4
.p2align 4, 0x90
.LBB4_7: # %._crit_edge
# in Loop: Header=BB4_4 Depth=2
incq %rdi
addq $4, %r8
cmpq %rcx, %rdi
je .LBB4_8
.LBB4_4: # Parent Loop BB4_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_6 Depth 3
movl $0, (%r12,%rdi,4)
testl %esi, %esi
jle .LBB4_7
# %bb.5: # %.lr.ph
# in Loop: Header=BB4_4 Depth=2
movss (%r13,%rdi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %r8, %rbp
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB4_6: # Parent Loop BB4_2 Depth=1
# Parent Loop BB4_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r15,%r9,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rbp), %xmm1
addss %xmm1, %xmm0
movss %xmm0, (%r13,%rdi,4)
incq %r9
addq %r11, %rbp
cmpq %r9, %rsi
jne .LBB4_6
jmp .LBB4_7
.LBB4_9: # %._crit_edge23
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z14multiMatrixCPU6MatrixS_S_, .Lfunc_end4-_Z14multiMatrixCPU6MatrixS_S_
.cfi_endproc
# -- End function
.globl _Z33__device_stub__MatMulKernelShared6MatrixS_S_ # -- Begin function _Z33__device_stub__MatMulKernelShared6MatrixS_S_
.p2align 4, 0x90
.type _Z33__device_stub__MatMulKernelShared6MatrixS_S_,@function
_Z33__device_stub__MatMulKernelShared6MatrixS_S_: # @_Z33__device_stub__MatMulKernelShared6MatrixS_S_
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
leaq 80(%rsp), %rax
movq %rax, 48(%rsp)
leaq 104(%rsp), %rax
movq %rax, 56(%rsp)
leaq 128(%rsp), %rax
movq %rax, 64(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z18MatMulKernelShared6MatrixS_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end5:
.size _Z33__device_stub__MatMulKernelShared6MatrixS_S_, .Lfunc_end5-_Z33__device_stub__MatMulKernelShared6MatrixS_S_
.cfi_endproc
# -- End function
.globl _Z12MatMulShared6MatrixS_S_ # -- Begin function _Z12MatMulShared6MatrixS_S_
.p2align 4, 0x90
.type _Z12MatMulShared6MatrixS_S_,@function
_Z12MatMulShared6MatrixS_S_: # @_Z12MatMulShared6MatrixS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $248, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 336(%rsp), %r14
movl 288(%rsp), %eax
movl 292(%rsp), %r15d
movl %eax, 64(%rsp)
movl %eax, 56(%rsp)
movl %r15d, 60(%rsp)
imull %r15d, %eax
movslq %eax, %rbx
shlq $2, %rbx
leaq 72(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 72(%rsp), %rdi
movq 304(%rsp), %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl 312(%rsp), %r12d
movl 316(%rsp), %eax
movl %r12d, 40(%rsp)
movl %r12d, 32(%rsp)
movl %eax, 36(%rsp)
imull %r12d, %eax
movslq %eax, %rbx
shlq $2, %rbx
leaq 48(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 48(%rsp), %rdi
movq 328(%rsp), %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl 336(%rsp), %eax
movl 340(%rsp), %ecx
movl %eax, 16(%rsp)
movl %eax, 8(%rsp)
movl %ecx, 12(%rsp)
imull %eax, %ecx
movslq %ecx, %rbx
shlq $2, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
imulq $1374389535, %r12, %rax # imm = 0x51EB851F
shrq $36, %rax
imulq $1374389535, %r15, %rcx # imm = 0x51EB851F
shrq $4, %rcx
movabsq $576460748008456192, %rdi # imm = 0x7FFFFFF00000000
andq %rcx, %rdi
orq %rax, %rdi
movabsq $214748364850, %rdx # imm = 0x3200000032
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_2
# %bb.1:
movq 72(%rsp), %rax
movq %rax, 176(%rsp)
movups 56(%rsp), %xmm0
movaps %xmm0, 160(%rsp)
movq 48(%rsp), %rax
movq %rax, 208(%rsp)
movups 32(%rsp), %xmm0
movaps %xmm0, 192(%rsp)
movq 24(%rsp), %rax
movq %rax, 240(%rsp)
movups 8(%rsp), %xmm0
movaps %xmm0, 224(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 192(%rsp), %rax
movq %rax, 136(%rsp)
leaq 224(%rsp), %rax
movq %rax, 144(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z18MatMulKernelShared6MatrixS_S_, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_2:
movq 16(%r14), %rdi
movq 24(%rsp), %rsi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 72(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
addq $248, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z12MatMulShared6MatrixS_S_, .Lfunc_end6-_Z12MatMulShared6MatrixS_S_
.cfi_endproc
# -- End function
.globl _Z27__device_stub__MatMulKernel6MatrixS_S_ # -- Begin function _Z27__device_stub__MatMulKernel6MatrixS_S_
.p2align 4, 0x90
.type _Z27__device_stub__MatMulKernel6MatrixS_S_,@function
_Z27__device_stub__MatMulKernel6MatrixS_S_: # @_Z27__device_stub__MatMulKernel6MatrixS_S_
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
leaq 80(%rsp), %rax
movq %rax, 48(%rsp)
leaq 104(%rsp), %rax
movq %rax, 56(%rsp)
leaq 128(%rsp), %rax
movq %rax, 64(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12MatMulKernel6MatrixS_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end7:
.size _Z27__device_stub__MatMulKernel6MatrixS_S_, .Lfunc_end7-_Z27__device_stub__MatMulKernel6MatrixS_S_
.cfi_endproc
# -- End function
.globl _Z6MatMul6MatrixS_S_ # -- Begin function _Z6MatMul6MatrixS_S_
.p2align 4, 0x90
.type _Z6MatMul6MatrixS_S_,@function
_Z6MatMul6MatrixS_S_: # @_Z6MatMul6MatrixS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $248, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 336(%rsp), %r14
movl 288(%rsp), %eax
movl 292(%rsp), %r15d
movl %eax, 56(%rsp)
movl %r15d, 60(%rsp)
imull %r15d, %eax
movslq %eax, %rbx
shlq $2, %rbx
leaq 72(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 72(%rsp), %rdi
movq 304(%rsp), %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl 312(%rsp), %r12d
movl 316(%rsp), %eax
movl %r12d, 32(%rsp)
movl %eax, 36(%rsp)
imull %r12d, %eax
movslq %eax, %rbx
shlq $2, %rbx
leaq 48(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 48(%rsp), %rdi
movq 328(%rsp), %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl 336(%rsp), %eax
movl 340(%rsp), %ecx
movl %eax, 8(%rsp)
movl %ecx, 12(%rsp)
imull %eax, %ecx
movslq %ecx, %rbx
shlq $2, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
addl $49, %r12d
imulq $1374389535, %r12, %rax # imm = 0x51EB851F
shrq $36, %rax
addl $49, %r15d
imulq $1374389535, %r15, %rcx # imm = 0x51EB851F
shrq $4, %rcx
movabsq $576460748008456192, %rdi # imm = 0x7FFFFFF00000000
andq %rcx, %rdi
orq %rax, %rdi
movabsq $214748364850, %rdx # imm = 0x3200000032
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_2
# %bb.1:
movq 72(%rsp), %rax
movq %rax, 176(%rsp)
movups 56(%rsp), %xmm0
movaps %xmm0, 160(%rsp)
movq 48(%rsp), %rax
movq %rax, 208(%rsp)
movups 32(%rsp), %xmm0
movaps %xmm0, 192(%rsp)
movq 24(%rsp), %rax
movq %rax, 240(%rsp)
movups 8(%rsp), %xmm0
movaps %xmm0, 224(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 192(%rsp), %rax
movq %rax, 136(%rsp)
leaq 224(%rsp), %rax
movq %rax, 144(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z12MatMulKernel6MatrixS_S_, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB8_2:
callq hipDeviceSynchronize
movq 16(%r14), %rdi
movq 24(%rsp), %rsi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 72(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
addq $248, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size _Z6MatMul6MatrixS_S_, .Lfunc_end8-_Z6MatMul6MatrixS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI9_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI9_1:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1736, %rsp # imm = 0x6C8
.cfi_def_cfa_offset 1792
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
callq rand
movl %eax, %edi
callq srand
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
leaq 72(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 72(%rsp)
jle .LBB9_17
# %bb.1: # %.lr.ph
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB9_2: # =>This Loop Header: Depth=1
# Child Loop BB9_3 Depth 2
# Child Loop BB9_4 Depth 3
# Child Loop BB9_6 Depth 3
# Child Loop BB9_8 Depth 3
# Child Loop BB9_10 Depth 3
# Child Loop BB9_12 Depth 3
# Child Loop BB9_14 Depth 3
leaq 264(%rsp), %rbx
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl %ebp, 76(%rsp) # 4-byte Spill
movl %ebp, %edi
callq hipSetDevice
movl $.L.str.4, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl $40000, %r14d # imm = 0x9C40
movl $100, %ebx
movl $30000, %eax # imm = 0x7530
movl $10000, %ebp # imm = 0x2710
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB9_3: # %_Z12createMatrixii.exit
# Parent Loop BB9_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB9_4 Depth 3
# Child Loop BB9_6 Depth 3
# Child Loop BB9_8 Depth 3
# Child Loop BB9_10 Depth 3
# Child Loop BB9_12 Depth 3
# Child Loop BB9_14 Depth 3
movq %rax, 112(%rsp) # 8-byte Spill
movl %ebx, %r15d
imull %r15d, %r15d
shll $2, %r15d
andl $-64, %r15d
movq %r15, %rdi
callq malloc
movq %rax, %r13
movq %rax, %rdi
xorl %esi, %esi
movq %r14, %rdx
callq memset@PLT
movq %r12, 104(%rsp) # 8-byte Spill
imulq $80000, %r12, %rax # imm = 0x13880
addq $120000, %rax # imm = 0x1D4C0
movq %rax, 96(%rsp) # 8-byte Spill
movq %r15, %rdi
callq malloc
movq %rax, %r12
movq %rax, %rdi
xorl %esi, %esi
movq %r14, %rdx
callq memset@PLT
movq %r15, %rdi
callq malloc
movq %rax, 88(%rsp) # 8-byte Spill
movq %rax, %rdi
xorl %esi, %esi
movq %r14, 80(%rsp) # 8-byte Spill
movq %r14, %rdx
callq memset@PLT
movl $.L.str.5, %edi
movl %ebx, %esi
movl %ebx, %edx
movl %ebx, %ecx
movl %ebx, %r8d
xorl %eax, %eax
callq printf
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB9_4: # Parent Loop BB9_2 Depth=1
# Parent Loop BB9_3 Depth=2
# => This Inner Loop Header: Depth=3
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r13,%r14,4)
incq %r14
cmpq %r14, %rbp
jne .LBB9_4
# %bb.5: # %.lr.ph.i89.preheader
# in Loop: Header=BB9_3 Depth=2
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB9_6: # %.lr.ph.i89
# Parent Loop BB9_2 Depth=1
# Parent Loop BB9_3 Depth=2
# => This Inner Loop Header: Depth=3
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r12,%r14,4)
incq %r14
cmpq %r14, %rbp
jne .LBB9_6
# %bb.7: # %_Z11draw_random6Matrix.exit94
# in Loop: Header=BB9_3 Depth=2
callq clock
movq %rax, %r14
movl %ebx, 192(%rsp)
movl %ebx, 196(%rsp)
movq %r13, 208(%rsp)
movl %ebx, 168(%rsp)
movl %ebx, 172(%rsp)
movq %r12, 184(%rsp)
movl %ebx, 240(%rsp)
movl %ebx, 244(%rsp)
movq 88(%rsp), %rax # 8-byte Reload
movq %rax, 256(%rsp)
movq %rax, 64(%rsp)
movups 240(%rsp), %xmm0
movups %xmm0, 48(%rsp)
movq 184(%rsp), %rax
movq %rax, 40(%rsp)
movups 168(%rsp), %xmm0
movups %xmm0, 24(%rsp)
movq 208(%rsp), %rax
movq %rax, 16(%rsp)
movups 192(%rsp), %xmm0
movups %xmm0, (%rsp)
callq _Z6MatMul6MatrixS_S_
callq clock
subq %r14, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI9_0(%rip), %xmm0
mulsd .LCPI9_1(%rip), %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movq %r15, %rdi
callq malloc
movq %rax, %r15
movq %rax, %rdi
xorl %esi, %esi
movq 80(%rsp), %rdx # 8-byte Reload
callq memset@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB9_8: # Parent Loop BB9_2 Depth=1
# Parent Loop BB9_3 Depth=2
# => This Inner Loop Header: Depth=3
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r13,%r14,4)
incq %r14
cmpq %r14, %rbp
jne .LBB9_8
# %bb.9: # %.lr.ph.i113.preheader
# in Loop: Header=BB9_3 Depth=2
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB9_10: # %.lr.ph.i113
# Parent Loop BB9_2 Depth=1
# Parent Loop BB9_3 Depth=2
# => This Inner Loop Header: Depth=3
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r12,%r14,4)
incq %r14
cmpq %r14, %rbp
jne .LBB9_10
# %bb.11: # %_Z11draw_random6Matrix.exit118
# in Loop: Header=BB9_3 Depth=2
callq clock
movq %rax, %r14
movl %ebx, 144(%rsp)
movl %ebx, 148(%rsp)
movq %r13, 160(%rsp)
movl %ebx, 120(%rsp)
movl %ebx, 124(%rsp)
movq %r12, 136(%rsp)
movl %ebx, 216(%rsp)
movl %ebx, 220(%rsp)
movq %r15, 232(%rsp)
movq %r15, 64(%rsp)
movups 216(%rsp), %xmm0
movups %xmm0, 48(%rsp)
movq 136(%rsp), %rax
movq %rax, 40(%rsp)
movups 120(%rsp), %xmm0
movups %xmm0, 24(%rsp)
movq 160(%rsp), %rax
movq %rax, 16(%rsp)
movups 144(%rsp), %xmm0
movups %xmm0, (%rsp)
callq _Z12MatMulShared6MatrixS_S_
callq clock
subq %r14, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI9_0(%rip), %xmm0
mulsd .LCPI9_1(%rip), %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB9_12: # Parent Loop BB9_2 Depth=1
# Parent Loop BB9_3 Depth=2
# => This Inner Loop Header: Depth=3
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r13,%r14,4)
incq %r14
cmpq %r14, %rbp
jne .LBB9_12
# %bb.13: # %.lr.ph.i137.preheader
# in Loop: Header=BB9_3 Depth=2
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB9_14: # %.lr.ph.i137
# Parent Loop BB9_2 Depth=1
# Parent Loop BB9_3 Depth=2
# => This Inner Loop Header: Depth=3
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r12,%r14,4)
incq %r14
cmpq %r14, %rbp
jne .LBB9_14
# %bb.15: # %_Z11draw_random6Matrix.exit142
# in Loop: Header=BB9_3 Depth=2
callq clock
movq %rax, %r14
callq clock
subq %r14, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI9_0(%rip), %xmm0
mulsd .LCPI9_1(%rip), %xmm0
movl $.L.str.8, %edi
movb $1, %al
callq printf
movl $10, %edi
callq putchar@PLT
addq $100, %rbx
movq 104(%rsp), %r12 # 8-byte Reload
incq %r12
movq 80(%rsp), %r14 # 8-byte Reload
addq 96(%rsp), %r14 # 8-byte Folded Reload
movq 112(%rsp), %rax # 8-byte Reload
addq %rax, %rbp
addq $20000, %rax # imm = 0x4E20
cmpq $10, %r12
jne .LBB9_3
# %bb.16: # in Loop: Header=BB9_2 Depth=1
movl 76(%rsp), %ebp # 4-byte Reload
incl %ebp
cmpl 72(%rsp), %ebp
jl .LBB9_2
.LBB9_17: # %._crit_edge
xorl %eax, %eax
addq $1736, %rsp # imm = 0x6C8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end9:
.size main, .Lfunc_end9-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB10_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB10_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18MatMulKernelShared6MatrixS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12MatMulKernel6MatrixS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end10:
.size __hip_module_ctor, .Lfunc_end10-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB11_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB11_2:
retq
.Lfunc_end11:
.size __hip_module_dtor, .Lfunc_end11-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%5.0f"
.size .L.str, 6
.type _Z18MatMulKernelShared6MatrixS_S_,@object # @_Z18MatMulKernelShared6MatrixS_S_
.section .rodata,"a",@progbits
.globl _Z18MatMulKernelShared6MatrixS_S_
.p2align 3, 0x0
_Z18MatMulKernelShared6MatrixS_S_:
.quad _Z33__device_stub__MatMulKernelShared6MatrixS_S_
.size _Z18MatMulKernelShared6MatrixS_S_, 8
.type _Z12MatMulKernel6MatrixS_S_,@object # @_Z12MatMulKernel6MatrixS_S_
.globl _Z12MatMulKernel6MatrixS_S_
.p2align 3, 0x0
_Z12MatMulKernel6MatrixS_S_:
.quad _Z27__device_stub__MatMulKernel6MatrixS_S_
.size _Z12MatMulKernel6MatrixS_S_, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "Utilizando uma %s:\n\n"
.size .L.str.4, 21
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "A[%d][%d] * B[%d][%d]\n"
.size .L.str.5, 23
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "GPU (global): %.3fms\n"
.size .L.str.6, 22
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "GPU (shared): %.3fms\n"
.size .L.str.7, 22
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "CPU: %.3fms\n"
.size .L.str.8, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z18MatMulKernelShared6MatrixS_S_"
.size .L__unnamed_1, 34
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12MatMulKernel6MatrixS_S_"
.size .L__unnamed_2, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Multiplica\303\247\303\243o de Matrizes"
.size .Lstr, 28
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Neste programa foi utilizado um BLOCK_SIZE = 50\n"
.size .Lstr.1, 49
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__MatMulKernelShared6MatrixS_S_
.addrsig_sym _Z27__device_stub__MatMulKernel6MatrixS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18MatMulKernelShared6MatrixS_S_
.addrsig_sym _Z12MatMulKernel6MatrixS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // input: radius (1), nsample (1), xyz1 (b,n,3), xyz2 (b,m,3)
// output: idx (b,m,nsample), pts_cnt (b,m)
__global__ void query_ball_point_gpu(int b, int n, int m, float radius, int nsample, const float *xyz1, const float *xyz2, int *idx, int *pts_cnt) {
int batch_index = blockIdx.x;
xyz1 += n*3*batch_index;
xyz2 += m*3*batch_index;
idx += m*nsample*batch_index;
pts_cnt += m*batch_index; // counting how many unique points selected in local region
int index = threadIdx.x;
int stride = blockDim.x;
for (int j=index;j<m;j+=stride) {
int cnt = 0;
for (int k=0;k<n;++k) {
if (cnt == nsample)
break; // only pick the FIRST nsample points in the ball
float x2=xyz2[j*3+0];
float y2=xyz2[j*3+1];
float z2=xyz2[j*3+2];
float x1=xyz1[k*3+0];
float y1=xyz1[k*3+1];
float z1=xyz1[k*3+2];
float d=max(sqrtf((x2-x1)*(x2-x1)+(y2-y1)*(y2-y1)+(z2-z1)*(z2-z1)),1e-20f);
if (d<radius) {
if (cnt==0) { // set ALL indices to k, s.t. if there are less points in ball than nsample, we still have valid (repeating) indices
for (int l=0;l<nsample;++l)
idx[j*nsample+l] = k;
}
idx[j*nsample+cnt] = k;
cnt+=1;
}
}
pts_cnt[j] = cnt;
}
}
// input: points (b,n,c), idx (b,m,nsample)
// output: out (b,m,nsample,c)
__global__ void group_point_gpu(int b, int n, int c, int m, int nsample, const float *points, const int *idx, float *out) {
int batch_index = blockIdx.x;
points += n*c*batch_index;
idx += m*nsample*batch_index;
out += m*nsample*c*batch_index;
int index = threadIdx.x;
int stride = blockDim.x;
for (int j=index;j<m;j+=stride) {
for (int k=0;k<nsample;++k) {
int ii = idx[j*nsample+k];
for (int l=0;l<c;++l) {
out[j*nsample*c+k*c+l] = points[ii*c+l];
}
}
}
}
// input: grad_out (b,m,nsample,c), idx (b,m,nsample),
// output: grad_points (b,n,c)
__global__ void group_point_grad_gpu(int b, int n, int c, int m, int nsample, const float *grad_out, const int *idx, float *grad_points) {
int batch_index = blockIdx.x;
idx += m*nsample*batch_index;
grad_out += m*nsample*c*batch_index;
grad_points += n*c*batch_index;
int index = threadIdx.x;
int stride = blockDim.x;
for (int j=index;j<m;j+=stride) {
for (int k=0;k<nsample;++k) {
int ii = idx[j*nsample+k];
for (int l=0;l<c;++l) {
atomicAdd(&grad_points[ii*c+l], grad_out[j*nsample*c+k*c+l]);
}
}
}
}
// input: k (1), distance matrix dist (b,m,n)
// output: idx (b,m,n), dist_out (b,m,n)
// only the top k results within n are useful
__global__ void selection_sort_gpu(int b, int n, int m, int k, const float *dist, int *outi, float *out) {
int batch_index = blockIdx.x;
dist+=m*n*batch_index;
outi+=m*n*batch_index;
out+=m*n*batch_index;
int index = threadIdx.x;
int stride = blockDim.x;
// copy from dist to dist_out
for (int j=index;j<m;j+=stride) {
for (int s=0;s<n;++s) {
out[j*n+s] = dist[j*n+s];
outi[j*n+s] = s;
}
}
float *p_dist;
for (int j=index;j<m;j+=stride) {
p_dist = out+j*n;
// selection sort for the first k elements
for (int s=0;s<k;++s) {
int min=s;
// find the min
for (int t=s+1;t<n;++t) {
if (p_dist[t]<p_dist[min]) {
min = t;
}
}
// swap min-th and i-th element
if (min!=s) {
float tmp = p_dist[min];
p_dist[min] = p_dist[s];
p_dist[s] = tmp;
int tmpi = outi[j*n+min];
outi[j*n+min] = outi[j*n+s];
outi[j*n+s] = tmpi;
}
}
}
}
void queryBallPointLauncher(int b, int n, int m, float radius, int nsample, const float *xyz1, const float *xyz2, int *idx, int *pts_cnt) {
query_ball_point_gpu<<<b,256>>>(b,n,m,radius,nsample,xyz1,xyz2,idx,pts_cnt);
//cudaDeviceSynchronize();
}
void selectionSortLauncher(int b, int n, int m, int k, const float *dist, int *outi, float *out) {
selection_sort_gpu<<<b,256>>>(b,n,m,k,dist,outi,out);
//cudaDeviceSynchronize();
}
void groupPointLauncher(int b, int n, int c, int m, int nsample, const float *points, const int *idx, float *out){
group_point_gpu<<<b,256>>>(b,n,c,m,nsample,points,idx,out);
//cudaDeviceSynchronize();
}
void groupPointGradLauncher(int b, int n, int c, int m, int nsample, const float *grad_out, const int *idx, float *grad_points){
group_point_grad_gpu<<<b,256>>>(b,n,c,m,nsample,grad_out,idx,grad_points);
//group_point_grad_gpu<<<1,1>>>(b,n,c,m,nsample,grad_out,idx,grad_points);
//cudaDeviceSynchronize();
} | .file "tmpxft_00120fe8_00000000-6_tf_grouping_g.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2033:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z54__device_stub__Z20query_ball_point_gpuiiifiPKfS0_PiS1_iiifiPKfS0_PiS1_
.type _Z54__device_stub__Z20query_ball_point_gpuiiifiPKfS0_PiS1_iiifiPKfS0_PiS1_, @function
_Z54__device_stub__Z20query_ball_point_gpuiiifiPKfS0_PiS1_iiifiPKfS0_PiS1_:
.LFB2055:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movl %edx, 52(%rsp)
movss %xmm0, 48(%rsp)
movl %ecx, 44(%rsp)
movq %r8, 32(%rsp)
movq %r9, 24(%rsp)
movq 224(%rsp), %rax
movq %rax, 16(%rsp)
movq 232(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
leaq 16(%rsp), %rax
movq %rax, 184(%rsp)
leaq 8(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z20query_ball_point_gpuiiifiPKfS0_PiS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z54__device_stub__Z20query_ball_point_gpuiiifiPKfS0_PiS1_iiifiPKfS0_PiS1_, .-_Z54__device_stub__Z20query_ball_point_gpuiiifiPKfS0_PiS1_iiifiPKfS0_PiS1_
.globl _Z20query_ball_point_gpuiiifiPKfS0_PiS1_
.type _Z20query_ball_point_gpuiiifiPKfS0_PiS1_, @function
_Z20query_ball_point_gpuiiifiPKfS0_PiS1_:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z54__device_stub__Z20query_ball_point_gpuiiifiPKfS0_PiS1_iiifiPKfS0_PiS1_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z20query_ball_point_gpuiiifiPKfS0_PiS1_, .-_Z20query_ball_point_gpuiiifiPKfS0_PiS1_
.globl _Z22queryBallPointLauncheriiifiPKfS0_PiS1_
.type _Z22queryBallPointLauncheriiifiPKfS0_PiS1_, @function
_Z22queryBallPointLauncheriiifiPKfS0_PiS1_:
.LFB2027:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movss %xmm0, 12(%rsp)
movl %ecx, %r13d
movq %r8, %r14
movq %r9, %r15
movl $256, 36(%rsp)
movl $1, 40(%rsp)
movl %edi, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 120(%rsp)
.cfi_def_cfa_offset 120
pushq 120(%rsp)
.cfi_def_cfa_offset 128
movq %r15, %r9
movq %r14, %r8
movl %r13d, %ecx
movss 28(%rsp), %xmm0
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z54__device_stub__Z20query_ball_point_gpuiiifiPKfS0_PiS1_iiifiPKfS0_PiS1_
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z22queryBallPointLauncheriiifiPKfS0_PiS1_, .-_Z22queryBallPointLauncheriiifiPKfS0_PiS1_
.globl _Z46__device_stub__Z15group_point_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf
.type _Z46__device_stub__Z15group_point_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf, @function
_Z46__device_stub__Z15group_point_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf:
.LFB2057:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movl %ecx, 32(%rsp)
movl %r8d, 28(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq 216(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movq %rsp, %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15group_point_gpuiiiiiPKfPKiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z46__device_stub__Z15group_point_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf, .-_Z46__device_stub__Z15group_point_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf
.globl _Z15group_point_gpuiiiiiPKfPKiPf
.type _Z15group_point_gpuiiiiiPKfPKiPf, @function
_Z15group_point_gpuiiiiiPKfPKiPf:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z46__device_stub__Z15group_point_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z15group_point_gpuiiiiiPKfPKiPf, .-_Z15group_point_gpuiiiiiPKfPKiPf
.globl _Z18groupPointLauncheriiiiiPKfPKiPf
.type _Z18groupPointLauncheriiiiiPKfPKiPf, @function
_Z18groupPointLauncheriiiiiPKfPKiPf:
.LFB2029:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r13d
movl %r8d, %r14d
movq %r9, %r15
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl %edi, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L23:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 104
pushq 104(%rsp)
.cfi_def_cfa_offset 112
movq %r15, %r9
movl %r14d, %r8d
movl %r13d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z46__device_stub__Z15group_point_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L23
.cfi_endproc
.LFE2029:
.size _Z18groupPointLauncheriiiiiPKfPKiPf, .-_Z18groupPointLauncheriiiiiPKfPKiPf
.globl _Z51__device_stub__Z20group_point_grad_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf
.type _Z51__device_stub__Z20group_point_grad_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf, @function
_Z51__device_stub__Z20group_point_grad_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf:
.LFB2059:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movl %ecx, 32(%rsp)
movl %r8d, 28(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq 216(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movq %rsp, %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20group_point_grad_gpuiiiiiPKfPKiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z51__device_stub__Z20group_point_grad_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf, .-_Z51__device_stub__Z20group_point_grad_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf
.globl _Z20group_point_grad_gpuiiiiiPKfPKiPf
.type _Z20group_point_grad_gpuiiiiiPKfPKiPf, @function
_Z20group_point_grad_gpuiiiiiPKfPKiPf:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z51__device_stub__Z20group_point_grad_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z20group_point_grad_gpuiiiiiPKfPKiPf, .-_Z20group_point_grad_gpuiiiiiPKfPKiPf
.globl _Z22groupPointGradLauncheriiiiiPKfPKiPf
.type _Z22groupPointGradLauncheriiiiiPKfPKiPf, @function
_Z22groupPointGradLauncheriiiiiPKfPKiPf:
.LFB2030:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r13d
movl %r8d, %r14d
movq %r9, %r15
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl %edi, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L35:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 104
pushq 104(%rsp)
.cfi_def_cfa_offset 112
movq %r15, %r9
movl %r14d, %r8d
movl %r13d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z51__device_stub__Z20group_point_grad_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L35
.cfi_endproc
.LFE2030:
.size _Z22groupPointGradLauncheriiiiiPKfPKiPf, .-_Z22groupPointGradLauncheriiiiiPKfPKiPf
.globl _Z47__device_stub__Z18selection_sort_gpuiiiiPKfPiPfiiiiPKfPiPf
.type _Z47__device_stub__Z18selection_sort_gpuiiiiPKfPiPfiiiiPKfPiPf, @function
_Z47__device_stub__Z18selection_sort_gpuiiiiPKfPiPfiiiiPKfPiPf:
.LFB2061:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movl %ecx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 192(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L43
.L39:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L44
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18selection_sort_gpuiiiiPKfPiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L39
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z47__device_stub__Z18selection_sort_gpuiiiiPKfPiPfiiiiPKfPiPf, .-_Z47__device_stub__Z18selection_sort_gpuiiiiPKfPiPfiiiiPKfPiPf
.globl _Z18selection_sort_gpuiiiiPKfPiPf
.type _Z18selection_sort_gpuiiiiPKfPiPf, @function
_Z18selection_sort_gpuiiiiPKfPiPf:
.LFB2062:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z47__device_stub__Z18selection_sort_gpuiiiiPKfPiPfiiiiPKfPiPf
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z18selection_sort_gpuiiiiPKfPiPf, .-_Z18selection_sort_gpuiiiiPKfPiPf
.globl _Z21selectionSortLauncheriiiiPKfPiPf
.type _Z21selectionSortLauncheriiiiPKfPiPf, @function
_Z21selectionSortLauncheriiiiPKfPiPf:
.LFB2028:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r13d
movq %r8, %r14
movq %r9, %r15
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl %edi, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L47:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 104
pushq 104(%rsp)
.cfi_def_cfa_offset 112
movq %r15, %r9
movq %r14, %r8
movl %r13d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z47__device_stub__Z18selection_sort_gpuiiiiPKfPiPfiiiiPKfPiPf
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L47
.cfi_endproc
.LFE2028:
.size _Z21selectionSortLauncheriiiiPKfPiPf, .-_Z21selectionSortLauncheriiiiPKfPiPf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18selection_sort_gpuiiiiPKfPiPf"
.align 8
.LC1:
.string "_Z20group_point_grad_gpuiiiiiPKfPKiPf"
.align 8
.LC2:
.string "_Z15group_point_gpuiiiiiPKfPKiPf"
.align 8
.LC3:
.string "_Z20query_ball_point_gpuiiifiPKfS0_PiS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2064:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18selection_sort_gpuiiiiPKfPiPf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z20group_point_grad_gpuiiiiiPKfPKiPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z15group_point_gpuiiiiiPKfPKiPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z20query_ball_point_gpuiiifiPKfS0_PiS1_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // input: radius (1), nsample (1), xyz1 (b,n,3), xyz2 (b,m,3)
// output: idx (b,m,nsample), pts_cnt (b,m)
__global__ void query_ball_point_gpu(int b, int n, int m, float radius, int nsample, const float *xyz1, const float *xyz2, int *idx, int *pts_cnt) {
int batch_index = blockIdx.x;
xyz1 += n*3*batch_index;
xyz2 += m*3*batch_index;
idx += m*nsample*batch_index;
pts_cnt += m*batch_index; // counting how many unique points selected in local region
int index = threadIdx.x;
int stride = blockDim.x;
for (int j=index;j<m;j+=stride) {
int cnt = 0;
for (int k=0;k<n;++k) {
if (cnt == nsample)
break; // only pick the FIRST nsample points in the ball
float x2=xyz2[j*3+0];
float y2=xyz2[j*3+1];
float z2=xyz2[j*3+2];
float x1=xyz1[k*3+0];
float y1=xyz1[k*3+1];
float z1=xyz1[k*3+2];
float d=max(sqrtf((x2-x1)*(x2-x1)+(y2-y1)*(y2-y1)+(z2-z1)*(z2-z1)),1e-20f);
if (d<radius) {
if (cnt==0) { // set ALL indices to k, s.t. if there are less points in ball than nsample, we still have valid (repeating) indices
for (int l=0;l<nsample;++l)
idx[j*nsample+l] = k;
}
idx[j*nsample+cnt] = k;
cnt+=1;
}
}
pts_cnt[j] = cnt;
}
}
// input: points (b,n,c), idx (b,m,nsample)
// output: out (b,m,nsample,c)
__global__ void group_point_gpu(int b, int n, int c, int m, int nsample, const float *points, const int *idx, float *out) {
int batch_index = blockIdx.x;
points += n*c*batch_index;
idx += m*nsample*batch_index;
out += m*nsample*c*batch_index;
int index = threadIdx.x;
int stride = blockDim.x;
for (int j=index;j<m;j+=stride) {
for (int k=0;k<nsample;++k) {
int ii = idx[j*nsample+k];
for (int l=0;l<c;++l) {
out[j*nsample*c+k*c+l] = points[ii*c+l];
}
}
}
}
// input: grad_out (b,m,nsample,c), idx (b,m,nsample),
// output: grad_points (b,n,c)
__global__ void group_point_grad_gpu(int b, int n, int c, int m, int nsample, const float *grad_out, const int *idx, float *grad_points) {
int batch_index = blockIdx.x;
idx += m*nsample*batch_index;
grad_out += m*nsample*c*batch_index;
grad_points += n*c*batch_index;
int index = threadIdx.x;
int stride = blockDim.x;
for (int j=index;j<m;j+=stride) {
for (int k=0;k<nsample;++k) {
int ii = idx[j*nsample+k];
for (int l=0;l<c;++l) {
atomicAdd(&grad_points[ii*c+l], grad_out[j*nsample*c+k*c+l]);
}
}
}
}
// input: k (1), distance matrix dist (b,m,n)
// output: idx (b,m,n), dist_out (b,m,n)
// only the top k results within n are useful
__global__ void selection_sort_gpu(int b, int n, int m, int k, const float *dist, int *outi, float *out) {
int batch_index = blockIdx.x;
dist+=m*n*batch_index;
outi+=m*n*batch_index;
out+=m*n*batch_index;
int index = threadIdx.x;
int stride = blockDim.x;
// copy from dist to dist_out
for (int j=index;j<m;j+=stride) {
for (int s=0;s<n;++s) {
out[j*n+s] = dist[j*n+s];
outi[j*n+s] = s;
}
}
float *p_dist;
for (int j=index;j<m;j+=stride) {
p_dist = out+j*n;
// selection sort for the first k elements
for (int s=0;s<k;++s) {
int min=s;
// find the min
for (int t=s+1;t<n;++t) {
if (p_dist[t]<p_dist[min]) {
min = t;
}
}
// swap min-th and i-th element
if (min!=s) {
float tmp = p_dist[min];
p_dist[min] = p_dist[s];
p_dist[s] = tmp;
int tmpi = outi[j*n+min];
outi[j*n+min] = outi[j*n+s];
outi[j*n+s] = tmpi;
}
}
}
}
void queryBallPointLauncher(int b, int n, int m, float radius, int nsample, const float *xyz1, const float *xyz2, int *idx, int *pts_cnt) {
query_ball_point_gpu<<<b,256>>>(b,n,m,radius,nsample,xyz1,xyz2,idx,pts_cnt);
//cudaDeviceSynchronize();
}
void selectionSortLauncher(int b, int n, int m, int k, const float *dist, int *outi, float *out) {
selection_sort_gpu<<<b,256>>>(b,n,m,k,dist,outi,out);
//cudaDeviceSynchronize();
}
void groupPointLauncher(int b, int n, int c, int m, int nsample, const float *points, const int *idx, float *out){
group_point_gpu<<<b,256>>>(b,n,c,m,nsample,points,idx,out);
//cudaDeviceSynchronize();
}
void groupPointGradLauncher(int b, int n, int c, int m, int nsample, const float *grad_out, const int *idx, float *grad_points){
group_point_grad_gpu<<<b,256>>>(b,n,c,m,nsample,grad_out,idx,grad_points);
//group_point_grad_gpu<<<1,1>>>(b,n,c,m,nsample,grad_out,idx,grad_points);
//cudaDeviceSynchronize();
} | #include <hip/hip_runtime.h>
// input: radius (1), nsample (1), xyz1 (b,n,3), xyz2 (b,m,3)
// output: idx (b,m,nsample), pts_cnt (b,m)
__global__ void query_ball_point_gpu(int b, int n, int m, float radius, int nsample, const float *xyz1, const float *xyz2, int *idx, int *pts_cnt) {
int batch_index = blockIdx.x;
xyz1 += n*3*batch_index;
xyz2 += m*3*batch_index;
idx += m*nsample*batch_index;
pts_cnt += m*batch_index; // counting how many unique points selected in local region
int index = threadIdx.x;
int stride = blockDim.x;
for (int j=index;j<m;j+=stride) {
int cnt = 0;
for (int k=0;k<n;++k) {
if (cnt == nsample)
break; // only pick the FIRST nsample points in the ball
float x2=xyz2[j*3+0];
float y2=xyz2[j*3+1];
float z2=xyz2[j*3+2];
float x1=xyz1[k*3+0];
float y1=xyz1[k*3+1];
float z1=xyz1[k*3+2];
float d=max(sqrtf((x2-x1)*(x2-x1)+(y2-y1)*(y2-y1)+(z2-z1)*(z2-z1)),1e-20f);
if (d<radius) {
if (cnt==0) { // set ALL indices to k, s.t. if there are less points in ball than nsample, we still have valid (repeating) indices
for (int l=0;l<nsample;++l)
idx[j*nsample+l] = k;
}
idx[j*nsample+cnt] = k;
cnt+=1;
}
}
pts_cnt[j] = cnt;
}
}
// input: points (b,n,c), idx (b,m,nsample)
// output: out (b,m,nsample,c)
__global__ void group_point_gpu(int b, int n, int c, int m, int nsample, const float *points, const int *idx, float *out) {
int batch_index = blockIdx.x;
points += n*c*batch_index;
idx += m*nsample*batch_index;
out += m*nsample*c*batch_index;
int index = threadIdx.x;
int stride = blockDim.x;
for (int j=index;j<m;j+=stride) {
for (int k=0;k<nsample;++k) {
int ii = idx[j*nsample+k];
for (int l=0;l<c;++l) {
out[j*nsample*c+k*c+l] = points[ii*c+l];
}
}
}
}
// input: grad_out (b,m,nsample,c), idx (b,m,nsample),
// output: grad_points (b,n,c)
__global__ void group_point_grad_gpu(int b, int n, int c, int m, int nsample, const float *grad_out, const int *idx, float *grad_points) {
int batch_index = blockIdx.x;
idx += m*nsample*batch_index;
grad_out += m*nsample*c*batch_index;
grad_points += n*c*batch_index;
int index = threadIdx.x;
int stride = blockDim.x;
for (int j=index;j<m;j+=stride) {
for (int k=0;k<nsample;++k) {
int ii = idx[j*nsample+k];
for (int l=0;l<c;++l) {
atomicAdd(&grad_points[ii*c+l], grad_out[j*nsample*c+k*c+l]);
}
}
}
}
// input: k (1), distance matrix dist (b,m,n)
// output: idx (b,m,n), dist_out (b,m,n)
// only the top k results within n are useful
__global__ void selection_sort_gpu(int b, int n, int m, int k, const float *dist, int *outi, float *out) {
int batch_index = blockIdx.x;
dist+=m*n*batch_index;
outi+=m*n*batch_index;
out+=m*n*batch_index;
int index = threadIdx.x;
int stride = blockDim.x;
// copy from dist to dist_out
for (int j=index;j<m;j+=stride) {
for (int s=0;s<n;++s) {
out[j*n+s] = dist[j*n+s];
outi[j*n+s] = s;
}
}
float *p_dist;
for (int j=index;j<m;j+=stride) {
p_dist = out+j*n;
// selection sort for the first k elements
for (int s=0;s<k;++s) {
int min=s;
// find the min
for (int t=s+1;t<n;++t) {
if (p_dist[t]<p_dist[min]) {
min = t;
}
}
// swap min-th and i-th element
if (min!=s) {
float tmp = p_dist[min];
p_dist[min] = p_dist[s];
p_dist[s] = tmp;
int tmpi = outi[j*n+min];
outi[j*n+min] = outi[j*n+s];
outi[j*n+s] = tmpi;
}
}
}
}
void queryBallPointLauncher(int b, int n, int m, float radius, int nsample, const float *xyz1, const float *xyz2, int *idx, int *pts_cnt) {
query_ball_point_gpu<<<b,256>>>(b,n,m,radius,nsample,xyz1,xyz2,idx,pts_cnt);
//cudaDeviceSynchronize();
}
void selectionSortLauncher(int b, int n, int m, int k, const float *dist, int *outi, float *out) {
selection_sort_gpu<<<b,256>>>(b,n,m,k,dist,outi,out);
//cudaDeviceSynchronize();
}
void groupPointLauncher(int b, int n, int c, int m, int nsample, const float *points, const int *idx, float *out){
group_point_gpu<<<b,256>>>(b,n,c,m,nsample,points,idx,out);
//cudaDeviceSynchronize();
}
void groupPointGradLauncher(int b, int n, int c, int m, int nsample, const float *grad_out, const int *idx, float *grad_points){
group_point_grad_gpu<<<b,256>>>(b,n,c,m,nsample,grad_out,idx,grad_points);
//group_point_grad_gpu<<<1,1>>>(b,n,c,m,nsample,grad_out,idx,grad_points);
//cudaDeviceSynchronize();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// input: radius (1), nsample (1), xyz1 (b,n,3), xyz2 (b,m,3)
// output: idx (b,m,nsample), pts_cnt (b,m)
__global__ void query_ball_point_gpu(int b, int n, int m, float radius, int nsample, const float *xyz1, const float *xyz2, int *idx, int *pts_cnt) {
int batch_index = blockIdx.x;
xyz1 += n*3*batch_index;
xyz2 += m*3*batch_index;
idx += m*nsample*batch_index;
pts_cnt += m*batch_index; // counting how many unique points selected in local region
int index = threadIdx.x;
int stride = blockDim.x;
for (int j=index;j<m;j+=stride) {
int cnt = 0;
for (int k=0;k<n;++k) {
if (cnt == nsample)
break; // only pick the FIRST nsample points in the ball
float x2=xyz2[j*3+0];
float y2=xyz2[j*3+1];
float z2=xyz2[j*3+2];
float x1=xyz1[k*3+0];
float y1=xyz1[k*3+1];
float z1=xyz1[k*3+2];
float d=max(sqrtf((x2-x1)*(x2-x1)+(y2-y1)*(y2-y1)+(z2-z1)*(z2-z1)),1e-20f);
if (d<radius) {
if (cnt==0) { // set ALL indices to k, s.t. if there are less points in ball than nsample, we still have valid (repeating) indices
for (int l=0;l<nsample;++l)
idx[j*nsample+l] = k;
}
idx[j*nsample+cnt] = k;
cnt+=1;
}
}
pts_cnt[j] = cnt;
}
}
// input: points (b,n,c), idx (b,m,nsample)
// output: out (b,m,nsample,c)
__global__ void group_point_gpu(int b, int n, int c, int m, int nsample, const float *points, const int *idx, float *out) {
int batch_index = blockIdx.x;
points += n*c*batch_index;
idx += m*nsample*batch_index;
out += m*nsample*c*batch_index;
int index = threadIdx.x;
int stride = blockDim.x;
for (int j=index;j<m;j+=stride) {
for (int k=0;k<nsample;++k) {
int ii = idx[j*nsample+k];
for (int l=0;l<c;++l) {
out[j*nsample*c+k*c+l] = points[ii*c+l];
}
}
}
}
// input: grad_out (b,m,nsample,c), idx (b,m,nsample),
// output: grad_points (b,n,c)
__global__ void group_point_grad_gpu(int b, int n, int c, int m, int nsample, const float *grad_out, const int *idx, float *grad_points) {
int batch_index = blockIdx.x;
idx += m*nsample*batch_index;
grad_out += m*nsample*c*batch_index;
grad_points += n*c*batch_index;
int index = threadIdx.x;
int stride = blockDim.x;
for (int j=index;j<m;j+=stride) {
for (int k=0;k<nsample;++k) {
int ii = idx[j*nsample+k];
for (int l=0;l<c;++l) {
atomicAdd(&grad_points[ii*c+l], grad_out[j*nsample*c+k*c+l]);
}
}
}
}
// input: k (1), distance matrix dist (b,m,n)
// output: idx (b,m,n), dist_out (b,m,n)
// only the top k results within n are useful
__global__ void selection_sort_gpu(int b, int n, int m, int k, const float *dist, int *outi, float *out) {
int batch_index = blockIdx.x;
dist+=m*n*batch_index;
outi+=m*n*batch_index;
out+=m*n*batch_index;
int index = threadIdx.x;
int stride = blockDim.x;
// copy from dist to dist_out
for (int j=index;j<m;j+=stride) {
for (int s=0;s<n;++s) {
out[j*n+s] = dist[j*n+s];
outi[j*n+s] = s;
}
}
float *p_dist;
for (int j=index;j<m;j+=stride) {
p_dist = out+j*n;
// selection sort for the first k elements
for (int s=0;s<k;++s) {
int min=s;
// find the min
for (int t=s+1;t<n;++t) {
if (p_dist[t]<p_dist[min]) {
min = t;
}
}
// swap min-th and i-th element
if (min!=s) {
float tmp = p_dist[min];
p_dist[min] = p_dist[s];
p_dist[s] = tmp;
int tmpi = outi[j*n+min];
outi[j*n+min] = outi[j*n+s];
outi[j*n+s] = tmpi;
}
}
}
}
void queryBallPointLauncher(int b, int n, int m, float radius, int nsample, const float *xyz1, const float *xyz2, int *idx, int *pts_cnt) {
query_ball_point_gpu<<<b,256>>>(b,n,m,radius,nsample,xyz1,xyz2,idx,pts_cnt);
//cudaDeviceSynchronize();
}
void selectionSortLauncher(int b, int n, int m, int k, const float *dist, int *outi, float *out) {
selection_sort_gpu<<<b,256>>>(b,n,m,k,dist,outi,out);
//cudaDeviceSynchronize();
}
void groupPointLauncher(int b, int n, int c, int m, int nsample, const float *points, const int *idx, float *out){
group_point_gpu<<<b,256>>>(b,n,c,m,nsample,points,idx,out);
//cudaDeviceSynchronize();
}
void groupPointGradLauncher(int b, int n, int c, int m, int nsample, const float *grad_out, const int *idx, float *grad_points){
group_point_grad_gpu<<<b,256>>>(b,n,c,m,nsample,grad_out,idx,grad_points);
//group_point_grad_gpu<<<1,1>>>(b,n,c,m,nsample,grad_out,idx,grad_points);
//cudaDeviceSynchronize();
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20query_ball_point_gpuiiifiPKfS0_PiS1_
.globl _Z20query_ball_point_gpuiiifiPKfS0_PiS1_
.p2align 8
.type _Z20query_ball_point_gpuiiifiPKfS0_PiS1_,@function
_Z20query_ball_point_gpuiiifiPKfS0_PiS1_:
s_load_b32 s12, s[0:1], 0x8
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s12, v0
s_cbranch_execz .LBB0_12
s_clause 0x2
s_load_b32 s13, s[0:1], 0x4
s_load_b256 s[4:11], s[0:1], 0x18
s_load_b64 s[2:3], s[0:1], 0xc
s_mul_i32 s16, s15, s12
s_load_b32 s18, s[0:1], 0x44
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s14, s15, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mul_i32 s14, s14, 3
v_mul_lo_u32 v5, v0, s3
s_ashr_i32 s15, s14, 31
s_lshl_b64 s[0:1], s[14:15], 2
s_mul_i32 s14, s16, 3
s_add_u32 s4, s4, s0
s_addc_u32 s5, s5, s1
s_ashr_i32 s15, s14, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[14:15], 2
s_mul_i32 s14, s16, s3
s_add_u32 s6, s6, s0
s_addc_u32 s7, s7, s1
s_ashr_i32 s15, s14, 31
s_lshl_b64 s[0:1], s[14:15], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_u32 s8, s8, s0
s_addc_u32 s9, s9, s1
s_ashr_i32 s17, s16, 31
s_lshl_b64 s[0:1], s[16:17], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s10, s10, s0
s_addc_u32 s11, s11, s1
s_and_b32 s14, s18, 0xffff
s_cmp_gt_i32 s13, 0
s_mov_b32 s1, 0
s_cselect_b32 s0, -1, 0
s_cmp_lg_u32 s3, 0
s_mul_i32 s16, s3, s14
s_cselect_b32 s15, -1, 0
s_mov_b32 s18, 0
s_and_b32 s15, s0, s15
s_cmp_lt_i32 s3, 1
s_cselect_b32 s0, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s17, s0, -1
s_branch .LBB0_4
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s19
.LBB0_3:
v_lshlrev_b64 v[2:3], 2, v[0:1]
v_add_nc_u32_e32 v0, s14, v0
v_add_nc_u32_e32 v5, s16, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_le_i32_e32 vcc_lo, s12, v0
v_add_co_u32 v2, s0, s10, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s11, v3, s0
s_or_b32 s18, vcc_lo, s18
global_store_b32 v[2:3], v10, off
s_and_not1_b32 exec_lo, exec_lo, s18
s_cbranch_execz .LBB0_12
.LBB0_4:
v_mov_b32_e32 v10, 0
s_and_not1_b32 vcc_lo, exec_lo, s15
s_cbranch_vccnz .LBB0_3
v_lshl_add_u32 v2, v0, 1, v0
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v10, 0
v_ashrrev_i32_e32 v6, 31, v5
v_mul_lo_u32 v11, v0, s3
s_mov_b32 s19, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_mov_b32 s20, 0
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v2, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s8, v6
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
global_load_b96 v[2:4], v[2:3], off
s_branch .LBB0_8
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s21
v_add_nc_u32_e32 v8, v10, v11
v_mov_b32_e32 v12, s20
v_add_nc_u32_e32 v10, 1, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
global_store_b32 v[8:9], v12, off
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s0
s_add_i32 s20, s20, 1
v_cmp_eq_u32_e32 vcc_lo, s3, v10
s_cmp_ge_i32 s20, s13
s_cselect_b32 s0, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, s0, vcc_lo
s_and_b32 s0, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s19, s0, s19
s_and_not1_b32 exec_lo, exec_lo, s19
s_cbranch_execz .LBB0_2
.LBB0_8:
s_mul_i32 s0, s20, 3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[22:23], s[0:1], 2
s_add_u32 s22, s4, s22
s_addc_u32 s23, s5, s23
s_clause 0x1
s_load_b64 s[24:25], s[22:23], 0x0
s_load_b32 s0, s[22:23], 0x8
s_waitcnt vmcnt(0) lgkmcnt(0)
v_dual_subrev_f32 v8, s25, v3 :: v_dual_subrev_f32 v9, s24, v2
v_subrev_f32_e32 v12, s0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v8, v8, v8
v_fmac_f32_e32 v8, v9, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, v12, v12
v_mul_f32_e32 v9, 0x4f800000, v8
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v8, v8, v9, vcc_lo
v_sqrt_f32_e32 v9, v8
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v12, -1, v9
v_add_nc_u32_e32 v13, 1, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v14, -v12, v9, v8
v_fma_f32 v15, -v13, v9, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s0, 0, v14
v_cndmask_b32_e64 v9, v9, v12, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s0, 0, v15
v_cndmask_b32_e64 v9, v9, v13, s0
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v12, 0x37800000, v9
v_cndmask_b32_e32 v9, v9, v12, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v8, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v8, v9, v8, vcc_lo
v_max_f32_e32 v8, 0x1e3ce508, v8
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_f32_e32 s2, v8
s_cbranch_execz .LBB0_7
v_cmp_eq_u32_e32 vcc_lo, 0, v10
s_and_b32 s22, vcc_lo, s17
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s21, s22
s_cbranch_execz .LBB0_6
v_dual_mov_b32 v12, s20 :: v_dual_mov_b32 v9, v7
v_mov_b32_e32 v8, v6
s_mov_b32 s22, s3
.LBB0_11:
global_store_b32 v[8:9], v12, off
v_add_co_u32 v8, vcc_lo, v8, 4
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
s_add_i32 s22, s22, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s22, 0
s_cbranch_scc1 .LBB0_11
s_branch .LBB0_6
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20query_ball_point_gpuiiifiPKfS0_PiS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 26
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20query_ball_point_gpuiiifiPKfS0_PiS1_, .Lfunc_end0-_Z20query_ball_point_gpuiiifiPKfS0_PiS1_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15group_point_gpuiiiiiPKfPKiPf
.globl _Z15group_point_gpuiiiiiPKfPKiPf
.p2align 8
.type _Z15group_point_gpuiiiiiPKfPKiPf,@function
_Z15group_point_gpuiiiiiPKfPKiPf:
s_load_b32 s8, s[0:1], 0xc
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s8, v0
s_cbranch_execz .LBB1_9
s_clause 0x4
s_load_b64 s[2:3], s[0:1], 0x4
s_load_b32 s9, s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x18
s_load_b32 s18, s[0:1], 0x3c
s_load_b64 s[12:13], s[0:1], 0x28
v_mov_b32_e32 v2, 0
s_mov_b32 s0, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s15, s3
s_mul_i32 s16, s9, s8
s_mul_i32 s14, s1, s2
s_mul_i32 s10, s16, s15
s_mul_i32 s16, s1, s16
s_ashr_i32 s11, s10, 31
s_ashr_i32 s15, s14, 31
s_lshl_b64 s[10:11], s[10:11], 2
s_mul_i32 s19, s9, s3
s_add_u32 s1, s6, s10
s_addc_u32 s2, s7, s11
s_ashr_i32 s17, s16, 31
s_and_b32 s6, s18, 0xffff
s_cmp_gt_i32 s9, 0
v_mul_lo_u32 v8, s19, v0
s_cselect_b32 s7, -1, 0
s_cmp_gt_i32 s3, 0
s_cselect_b32 s10, -1, 0
s_lshl_b64 s[16:17], s[16:17], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s11, s12, s16
s_addc_u32 s12, s13, s17
s_lshl_b64 s[14:15], s[14:15], 2
s_mul_i32 s13, s19, s6
s_add_u32 s4, s4, s14
s_addc_u32 s5, s5, s15
s_branch .LBB1_3
.LBB1_2:
s_set_inst_prefetch_distance 0x2
v_add_nc_u32_e32 v0, s6, v0
v_add_nc_u32_e32 v8, s13, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s8, v0
s_or_b32 s0, vcc_lo, s0
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB1_9
.LBB1_3:
s_and_not1_b32 vcc_lo, exec_lo, s7
s_cbranch_vccnz .LBB1_2
v_mul_lo_u32 v9, v0, s9
v_mov_b32_e32 v3, v8
s_mov_b32 s14, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_6
.p2align 6
.LBB1_5:
v_add_nc_u32_e32 v3, s3, v3
s_add_i32 s14, s14, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s14, s9
s_cbranch_scc1 .LBB1_2
.LBB1_6:
s_and_not1_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB1_5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, s14, v9
s_mov_b32 s15, s3
v_lshlrev_b64 v[4:5], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s1, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s2, v5, vcc_lo
global_load_b32 v1, v[4:5], off
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], 2, v[3:4]
v_add_co_u32 v4, vcc_lo, s11, v10
s_waitcnt vmcnt(0)
v_mul_lo_u32 v5, v1, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_ci_u32_e32 v5, vcc_lo, s12, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
.LBB1_8:
global_load_b32 v1, v[6:7], off
v_add_co_u32 v6, vcc_lo, v6, 4
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
s_add_i32 s15, s15, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s15, 0
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v1, off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_cbranch_scc0 .LBB1_8
s_branch .LBB1_5
.LBB1_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15group_point_gpuiiiiiPKfPKiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z15group_point_gpuiiiiiPKfPKiPf, .Lfunc_end1-_Z15group_point_gpuiiiiiPKfPKiPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z20group_point_grad_gpuiiiiiPKfPKiPf
.globl _Z20group_point_grad_gpuiiiiiPKfPKiPf
.p2align 8
.type _Z20group_point_grad_gpuiiiiiPKfPKiPf,@function
_Z20group_point_grad_gpuiiiiiPKfPKiPf:
s_load_b32 s4, s[0:1], 0xc
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s4, v0
s_cbranch_execz .LBB2_11
s_clause 0x4
s_load_b32 s5, s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x4
s_load_b128 s[8:11], s[0:1], 0x18
s_load_b64 s[12:13], s[0:1], 0x28
s_load_b32 s14, s[0:1], 0x3c
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s6, s5, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_mul_i32 s0, s6, s15
s_mul_i32 s15, s15, s3
s_ashr_i32 s1, s0, 31
s_mul_i32 s6, s15, s6
s_lshl_b64 s[0:1], s[0:1], 2
s_add_u32 s0, s10, s0
s_addc_u32 s1, s11, s1
s_ashr_i32 s7, s6, 31
s_mul_i32 s10, s15, s2
s_lshl_b64 s[6:7], s[6:7], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_u32 s2, s8, s6
s_addc_u32 s6, s9, s7
s_ashr_i32 s11, s10, 31
s_lshl_b64 s[8:9], s[10:11], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s7, s12, s8
s_addc_u32 s8, s13, s9
s_and_b32 s9, s14, 0xffff
s_cmp_gt_i32 s5, 0
s_mov_b32 s12, 0
s_cselect_b32 s10, -1, 0
s_cmp_gt_i32 s3, 0
s_cselect_b32 s11, -1, 0
s_branch .LBB2_3
.LBB2_2:
v_add_nc_u32_e32 v0, s9, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s4, v0
s_or_b32 s12, vcc_lo, s12
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execz .LBB2_11
.LBB2_3:
s_and_not1_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB2_2
v_mul_lo_u32 v7, v0, s5
s_mov_b32 s13, 0
s_branch .LBB2_6
.LBB2_5:
s_add_i32 s13, s13, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s13, s5
s_cbranch_scc1 .LBB2_2
.LBB2_6:
s_and_not1_b32 vcc_lo, exec_lo, s11
s_cbranch_vccnz .LBB2_5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, s13, v7
s_mov_b32 s14, 0
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_mul_lo_u32 v1, v1, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v8, v3, s3
.p2align 6
.LBB2_8:
v_add_nc_u32_e32 v3, s14, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, s14, v8
s_mov_b32 s15, 0
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v9, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v10, vcc_lo, s6, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s7, v5
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s8, v6, vcc_lo
global_load_b32 v9, v[9:10], off
global_load_b32 v6, v[3:4], off
.LBB2_9:
s_waitcnt vmcnt(0)
v_add_f32_e32 v5, v6, v9
global_atomic_cmpswap_b32 v5, v[3:4], v[5:6], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v5, v6
v_mov_b32_e32 v6, v5
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB2_9
s_or_b32 exec_lo, exec_lo, s15
s_add_i32 s14, s14, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s14, s3
s_cbranch_scc0 .LBB2_8
s_branch .LBB2_5
.LBB2_11:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20group_point_grad_gpuiiiiiPKfPKiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z20group_point_grad_gpuiiiiiPKfPKiPf, .Lfunc_end2-_Z20group_point_grad_gpuiiiiiPKfPKiPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z18selection_sort_gpuiiiiPKfPiPf
.globl _Z18selection_sort_gpuiiiiPKfPiPf
.p2align 8
.type _Z18selection_sort_gpuiiiiPKfPiPf,@function
_Z18selection_sort_gpuiiiiPKfPiPf:
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x4
s_load_b32 s10, s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x18
s_mov_b32 s11, exec_lo
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s15, s2
s_and_b32 s10, s10, 0xffff
s_mul_i32 s8, s8, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s9, s8, 31
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB3_6
s_load_b64 s[20:21], s[0:1], 0x10
s_cmp_gt_i32 s2, 0
v_mul_lo_u32 v1, v0, s2
s_cselect_b32 s12, -1, 0
s_lshl_b64 s[22:23], s[8:9], 2
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v9, v0
s_add_u32 s14, s4, s22
s_addc_u32 s15, s5, s23
s_add_u32 s17, s6, s22
s_addc_u32 s18, s7, s23
s_mov_b32 s13, 0
s_mul_i32 s16, s2, s10
s_waitcnt lgkmcnt(0)
s_add_u32 s19, s20, s22
s_addc_u32 s20, s21, s23
s_set_inst_prefetch_distance 0x1
s_branch .LBB3_3
.p2align 6
.LBB3_2:
v_add_nc_u32_e32 v9, s10, v9
v_add_nc_u32_e32 v1, s16, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s3, v9
s_or_b32 s13, vcc_lo, s13
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execz .LBB3_6
.LBB3_3:
s_and_not1_b32 vcc_lo, exec_lo, s12
s_cbranch_vccnz .LBB3_2
v_lshlrev_b64 v[7:8], 2, v[1:2]
s_mov_b32 s21, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s14, v7
v_add_co_ci_u32_e32 v4, vcc_lo, s15, v8, vcc_lo
v_add_co_u32 v5, vcc_lo, s17, v7
v_add_co_ci_u32_e32 v6, vcc_lo, s18, v8, vcc_lo
v_add_co_u32 v7, vcc_lo, s19, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s20, v8, vcc_lo
.p2align 6
.LBB3_5:
global_load_b32 v10, v[7:8], off
v_mov_b32_e32 v11, s21
v_add_co_u32 v7, vcc_lo, v7, 4
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
global_store_b32 v[3:4], v11, off
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_add_i32 s21, s21, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, s21
s_waitcnt vmcnt(0)
global_store_b32 v[5:6], v10, off
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_cbranch_scc0 .LBB3_5
s_branch .LBB3_2
.LBB3_6:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s11, exec_lo
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB3_17
s_load_b32 s11, s[0:1], 0xc
s_lshl_b64 s[8:9], s[8:9], 2
v_mul_lo_u32 v1, v0, s2
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_add_u32 s6, s8, s6
s_addc_u32 s7, s9, s7
s_mov_b32 s1, 0
s_mul_i32 s13, s2, s10
s_mov_b32 s14, 0
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s11, 0
s_cselect_b32 s8, -1, 0
s_add_u32 s9, s6, 4
s_addc_u32 s12, s7, 0
s_branch .LBB3_9
.LBB3_8:
v_add_nc_u32_e32 v0, s10, v0
v_add_nc_u32_e32 v1, s13, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s3, v0
s_or_b32 s14, vcc_lo, s14
s_and_not1_b32 exec_lo, exec_lo, s14
s_cbranch_execz .LBB3_17
.LBB3_9:
s_and_not1_b32 vcc_lo, exec_lo, s8
s_cbranch_vccnz .LBB3_8
v_mul_lo_u32 v3, v0, s2
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[7:8], 2, v[3:4]
v_add_co_u32 v4, vcc_lo, s9, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s12, v6, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v8, vcc_lo
s_branch .LBB3_12
.LBB3_11:
s_or_b32 exec_lo, exec_lo, s16
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_cmp_eq_u32 s15, s11
s_mov_b32 s0, s15
s_cbranch_scc1 .LBB3_8
.LBB3_12:
v_mov_b32_e32 v6, s0
s_add_i32 s15, s0, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s15, s2
s_cbranch_scc1 .LBB3_15
v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v9, v5
v_mov_b32_e32 v8, v4
s_mov_b32 s16, s15
.p2align 6
.LBB3_14:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[11:12], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v11, vcc_lo, v2, v11
v_add_co_ci_u32_e32 v12, vcc_lo, v10, v12, vcc_lo
global_load_b32 v7, v[8:9], off
global_load_b32 v11, v[11:12], off
v_add_co_u32 v8, vcc_lo, v8, 4
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
s_waitcnt vmcnt(0)
v_cmp_lt_f32_e32 vcc_lo, v7, v11
v_cndmask_b32_e64 v6, v6, s16, vcc_lo
s_add_i32 s16, s16, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s16, s2
s_cbranch_scc0 .LBB3_14
.LBB3_15:
s_mov_b32 s16, exec_lo
v_cmpx_ne_u32_e64 s0, v6
s_cbranch_execz .LBB3_11
v_ashrrev_i32_e32 v7, 31, v6
v_add_nc_u32_e32 v8, s0, v3
v_add_nc_u32_e32 v11, v6, v3
s_lshl_b64 s[18:19], s[0:1], 2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_ashrrev_i32_e32 v9, 31, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, v2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, v10, v7, vcc_lo
v_add_co_u32 v13, vcc_lo, v2, s18
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_ci_u32_e32 v14, vcc_lo, s19, v10, vcc_lo
v_add_co_u32 v8, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v11, vcc_lo, s4, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
s_clause 0x1
global_load_b32 v15, v[13:14], off
global_load_b32 v16, v[6:7], off
s_clause 0x1
global_load_b32 v17, v[8:9], off
global_load_b32 v18, v[11:12], off
s_waitcnt vmcnt(3)
global_store_b32 v[6:7], v15, off
s_waitcnt vmcnt(2)
global_store_b32 v[13:14], v16, off
s_waitcnt vmcnt(1)
global_store_b32 v[11:12], v17, off
s_waitcnt vmcnt(0)
global_store_b32 v[8:9], v18, off
s_branch .LBB3_11
.LBB3_17:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18selection_sort_gpuiiiiPKfPiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 19
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z18selection_sort_gpuiiiiPKfPiPf, .Lfunc_end3-_Z18selection_sort_gpuiiiiPKfPiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20query_ball_point_gpuiiifiPKfS0_PiS1_
.private_segment_fixed_size: 0
.sgpr_count: 28
.sgpr_spill_count: 0
.symbol: _Z20query_ball_point_gpuiiifiPKfS0_PiS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
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.size: 4
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.size: 4
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.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
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.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
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.size: 8
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.size: 4
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.size: 2
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.size: 2
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.size: 2
.value_kind: hidden_remainder_y
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.size: 2
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.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15group_point_gpuiiiiiPKfPKiPf
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z15group_point_gpuiiiiiPKfPKiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
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.size: 4
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.offset: 32
.size: 8
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.size: 2
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.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20group_point_grad_gpuiiiiiPKfPKiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20group_point_grad_gpuiiiiiPKfPKiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
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- .args:
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.size: 4
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.size: 8
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.size: 8
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.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18selection_sort_gpuiiiiPKfPiPf
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z18selection_sort_gpuiiiiPKfPiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 19
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// input: radius (1), nsample (1), xyz1 (b,n,3), xyz2 (b,m,3)
// output: idx (b,m,nsample), pts_cnt (b,m)
__global__ void query_ball_point_gpu(int b, int n, int m, float radius, int nsample, const float *xyz1, const float *xyz2, int *idx, int *pts_cnt) {
int batch_index = blockIdx.x;
xyz1 += n*3*batch_index;
xyz2 += m*3*batch_index;
idx += m*nsample*batch_index;
pts_cnt += m*batch_index; // counting how many unique points selected in local region
int index = threadIdx.x;
int stride = blockDim.x;
for (int j=index;j<m;j+=stride) {
int cnt = 0;
for (int k=0;k<n;++k) {
if (cnt == nsample)
break; // only pick the FIRST nsample points in the ball
float x2=xyz2[j*3+0];
float y2=xyz2[j*3+1];
float z2=xyz2[j*3+2];
float x1=xyz1[k*3+0];
float y1=xyz1[k*3+1];
float z1=xyz1[k*3+2];
float d=max(sqrtf((x2-x1)*(x2-x1)+(y2-y1)*(y2-y1)+(z2-z1)*(z2-z1)),1e-20f);
if (d<radius) {
if (cnt==0) { // set ALL indices to k, s.t. if there are less points in ball than nsample, we still have valid (repeating) indices
for (int l=0;l<nsample;++l)
idx[j*nsample+l] = k;
}
idx[j*nsample+cnt] = k;
cnt+=1;
}
}
pts_cnt[j] = cnt;
}
}
// input: points (b,n,c), idx (b,m,nsample)
// output: out (b,m,nsample,c)
__global__ void group_point_gpu(int b, int n, int c, int m, int nsample, const float *points, const int *idx, float *out) {
int batch_index = blockIdx.x;
points += n*c*batch_index;
idx += m*nsample*batch_index;
out += m*nsample*c*batch_index;
int index = threadIdx.x;
int stride = blockDim.x;
for (int j=index;j<m;j+=stride) {
for (int k=0;k<nsample;++k) {
int ii = idx[j*nsample+k];
for (int l=0;l<c;++l) {
out[j*nsample*c+k*c+l] = points[ii*c+l];
}
}
}
}
// input: grad_out (b,m,nsample,c), idx (b,m,nsample),
// output: grad_points (b,n,c)
__global__ void group_point_grad_gpu(int b, int n, int c, int m, int nsample, const float *grad_out, const int *idx, float *grad_points) {
int batch_index = blockIdx.x;
idx += m*nsample*batch_index;
grad_out += m*nsample*c*batch_index;
grad_points += n*c*batch_index;
int index = threadIdx.x;
int stride = blockDim.x;
for (int j=index;j<m;j+=stride) {
for (int k=0;k<nsample;++k) {
int ii = idx[j*nsample+k];
for (int l=0;l<c;++l) {
atomicAdd(&grad_points[ii*c+l], grad_out[j*nsample*c+k*c+l]);
}
}
}
}
// input: k (1), distance matrix dist (b,m,n)
// output: idx (b,m,n), dist_out (b,m,n)
// only the top k results within n are useful
__global__ void selection_sort_gpu(int b, int n, int m, int k, const float *dist, int *outi, float *out) {
int batch_index = blockIdx.x;
dist+=m*n*batch_index;
outi+=m*n*batch_index;
out+=m*n*batch_index;
int index = threadIdx.x;
int stride = blockDim.x;
// copy from dist to dist_out
for (int j=index;j<m;j+=stride) {
for (int s=0;s<n;++s) {
out[j*n+s] = dist[j*n+s];
outi[j*n+s] = s;
}
}
float *p_dist;
for (int j=index;j<m;j+=stride) {
p_dist = out+j*n;
// selection sort for the first k elements
for (int s=0;s<k;++s) {
int min=s;
// find the min
for (int t=s+1;t<n;++t) {
if (p_dist[t]<p_dist[min]) {
min = t;
}
}
// swap min-th and i-th element
if (min!=s) {
float tmp = p_dist[min];
p_dist[min] = p_dist[s];
p_dist[s] = tmp;
int tmpi = outi[j*n+min];
outi[j*n+min] = outi[j*n+s];
outi[j*n+s] = tmpi;
}
}
}
}
void queryBallPointLauncher(int b, int n, int m, float radius, int nsample, const float *xyz1, const float *xyz2, int *idx, int *pts_cnt) {
query_ball_point_gpu<<<b,256>>>(b,n,m,radius,nsample,xyz1,xyz2,idx,pts_cnt);
//cudaDeviceSynchronize();
}
void selectionSortLauncher(int b, int n, int m, int k, const float *dist, int *outi, float *out) {
selection_sort_gpu<<<b,256>>>(b,n,m,k,dist,outi,out);
//cudaDeviceSynchronize();
}
void groupPointLauncher(int b, int n, int c, int m, int nsample, const float *points, const int *idx, float *out){
group_point_gpu<<<b,256>>>(b,n,c,m,nsample,points,idx,out);
//cudaDeviceSynchronize();
}
void groupPointGradLauncher(int b, int n, int c, int m, int nsample, const float *grad_out, const int *idx, float *grad_points){
group_point_grad_gpu<<<b,256>>>(b,n,c,m,nsample,grad_out,idx,grad_points);
//group_point_grad_gpu<<<1,1>>>(b,n,c,m,nsample,grad_out,idx,grad_points);
//cudaDeviceSynchronize();
} | .text
.file "tf_grouping_g.hip"
.globl _Z35__device_stub__query_ball_point_gpuiiifiPKfS0_PiS1_ # -- Begin function _Z35__device_stub__query_ball_point_gpuiiifiPKfS0_PiS1_
.p2align 4, 0x90
.type _Z35__device_stub__query_ball_point_gpuiiifiPKfS0_PiS1_,@function
_Z35__device_stub__query_ball_point_gpuiiifiPKfS0_PiS1_: # @_Z35__device_stub__query_ball_point_gpuiiifiPKfS0_PiS1_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movss %xmm0, 16(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 88(%rsp)
movq %r9, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rax
movq %rax, 144(%rsp)
leaq 176(%rsp), %rax
movq %rax, 152(%rsp)
leaq 184(%rsp), %rax
movq %rax, 160(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20query_ball_point_gpuiiifiPKfS0_PiS1_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z35__device_stub__query_ball_point_gpuiiifiPKfS0_PiS1_, .Lfunc_end0-_Z35__device_stub__query_ball_point_gpuiiifiPKfS0_PiS1_
.cfi_endproc
# -- End function
.globl _Z30__device_stub__group_point_gpuiiiiiPKfPKiPf # -- Begin function _Z30__device_stub__group_point_gpuiiiiiPKfPKiPf
.p2align 4, 0x90
.type _Z30__device_stub__group_point_gpuiiiiiPKfPKiPf,@function
_Z30__device_stub__group_point_gpuiiiiiPKfPKiPf: # @_Z30__device_stub__group_point_gpuiiiiiPKfPKiPf
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15group_point_gpuiiiiiPKfPKiPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z30__device_stub__group_point_gpuiiiiiPKfPKiPf, .Lfunc_end1-_Z30__device_stub__group_point_gpuiiiiiPKfPKiPf
.cfi_endproc
# -- End function
.globl _Z35__device_stub__group_point_grad_gpuiiiiiPKfPKiPf # -- Begin function _Z35__device_stub__group_point_grad_gpuiiiiiPKfPKiPf
.p2align 4, 0x90
.type _Z35__device_stub__group_point_grad_gpuiiiiiPKfPKiPf,@function
_Z35__device_stub__group_point_grad_gpuiiiiiPKfPKiPf: # @_Z35__device_stub__group_point_grad_gpuiiiiiPKfPKiPf
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20group_point_grad_gpuiiiiiPKfPKiPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z35__device_stub__group_point_grad_gpuiiiiiPKfPKiPf, .Lfunc_end2-_Z35__device_stub__group_point_grad_gpuiiiiiPKfPKiPf
.cfi_endproc
# -- End function
.globl _Z33__device_stub__selection_sort_gpuiiiiPKfPiPf # -- Begin function _Z33__device_stub__selection_sort_gpuiiiiPKfPiPf
.p2align 4, 0x90
.type _Z33__device_stub__selection_sort_gpuiiiiPKfPiPf,@function
_Z33__device_stub__selection_sort_gpuiiiiPKfPiPf: # @_Z33__device_stub__selection_sort_gpuiiiiPKfPiPf
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18selection_sort_gpuiiiiPKfPiPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end3:
.size _Z33__device_stub__selection_sort_gpuiiiiPKfPiPf, .Lfunc_end3-_Z33__device_stub__selection_sort_gpuiiiiPKfPiPf
.cfi_endproc
# -- End function
.globl _Z22queryBallPointLauncheriiifiPKfS0_PiS1_ # -- Begin function _Z22queryBallPointLauncheriiifiPKfS0_PiS1_
.p2align 4, 0x90
.type _Z22queryBallPointLauncheriiifiPKfS0_PiS1_,@function
_Z22queryBallPointLauncheriiifiPKfS0_PiS1_: # @_Z22queryBallPointLauncheriiifiPKfS0_PiS1_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movq %r8, %r14
movl %ecx, %ebp
movss %xmm0, 8(%rsp) # 4-byte Spill
movl %edx, %r15d
movl %esi, %r12d
movl %edi, %r13d
movl %edi, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movq 248(%rsp), %rax
movq 240(%rsp), %rcx
movl %r13d, 28(%rsp)
movl %r12d, 24(%rsp)
movl %r15d, 20(%rsp)
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 16(%rsp)
movl %ebp, 12(%rsp)
movq %r14, 104(%rsp)
movq %rbx, 96(%rsp)
movq %rcx, 88(%rsp)
movq %rax, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 104(%rsp), %rax
movq %rax, 152(%rsp)
leaq 96(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rax
movq %rax, 168(%rsp)
leaq 80(%rsp), %rax
movq %rax, 176(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z20query_ball_point_gpuiiifiPKfS0_PiS1_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z22queryBallPointLauncheriiifiPKfS0_PiS1_, .Lfunc_end4-_Z22queryBallPointLauncheriiifiPKfS0_PiS1_
.cfi_endproc
# -- End function
.globl _Z21selectionSortLauncheriiiiPKfPiPf # -- Begin function _Z21selectionSortLauncheriiiiPKfPiPf
.p2align 4, 0x90
.type _Z21selectionSortLauncheriiiiPKfPiPf,@function
_Z21selectionSortLauncheriiiiPKfPiPf: # @_Z21selectionSortLauncheriiiiPKfPiPf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movq %r8, %r14
movl %ecx, %ebp
movl %edx, %r15d
movl %esi, %r12d
movl %edi, %r13d
movl %edi, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq 208(%rsp), %rax
movl %r13d, 20(%rsp)
movl %r12d, 16(%rsp)
movl %r15d, 12(%rsp)
movl %ebp, 8(%rsp)
movq %r14, 88(%rsp)
movq %rbx, 80(%rsp)
movq %rax, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18selection_sort_gpuiiiiPKfPiPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z21selectionSortLauncheriiiiPKfPiPf, .Lfunc_end5-_Z21selectionSortLauncheriiiiPKfPiPf
.cfi_endproc
# -- End function
.globl _Z18groupPointLauncheriiiiiPKfPKiPf # -- Begin function _Z18groupPointLauncheriiiiiPKfPKiPf
.p2align 4, 0x90
.type _Z18groupPointLauncheriiiiiPKfPKiPf,@function
_Z18groupPointLauncheriiiiiPKfPKiPf: # @_Z18groupPointLauncheriiiiiPKfPKiPf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movl %r8d, %ebp
movl %ecx, %r14d
movl %edx, %r15d
movl %esi, %r12d
movl %edi, %r13d
movl %edi, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_2
# %bb.1:
movq 232(%rsp), %rax
movq 224(%rsp), %rcx
movl %r13d, 20(%rsp)
movl %r12d, 16(%rsp)
movl %r15d, 12(%rsp)
movl %r14d, 8(%rsp)
movl %ebp, 4(%rsp)
movq %rbx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rax, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15group_point_gpuiiiiiPKfPKiPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_2:
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z18groupPointLauncheriiiiiPKfPKiPf, .Lfunc_end6-_Z18groupPointLauncheriiiiiPKfPKiPf
.cfi_endproc
# -- End function
.globl _Z22groupPointGradLauncheriiiiiPKfPKiPf # -- Begin function _Z22groupPointGradLauncheriiiiiPKfPKiPf
.p2align 4, 0x90
.type _Z22groupPointGradLauncheriiiiiPKfPKiPf,@function
_Z22groupPointGradLauncheriiiiiPKfPKiPf: # @_Z22groupPointGradLauncheriiiiiPKfPKiPf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movl %r8d, %ebp
movl %ecx, %r14d
movl %edx, %r15d
movl %esi, %r12d
movl %edi, %r13d
movl %edi, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_2
# %bb.1:
movq 232(%rsp), %rax
movq 224(%rsp), %rcx
movl %r13d, 20(%rsp)
movl %r12d, 16(%rsp)
movl %r15d, 12(%rsp)
movl %r14d, 8(%rsp)
movl %ebp, 4(%rsp)
movq %rbx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rax, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20group_point_grad_gpuiiiiiPKfPKiPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_2:
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _Z22groupPointGradLauncheriiiiiPKfPKiPf, .Lfunc_end7-_Z22groupPointGradLauncheriiiiiPKfPKiPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20query_ball_point_gpuiiifiPKfS0_PiS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15group_point_gpuiiiiiPKfPKiPf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20group_point_grad_gpuiiiiiPKfPKiPf, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18selection_sort_gpuiiiiPKfPiPf, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20query_ball_point_gpuiiifiPKfS0_PiS1_,@object # @_Z20query_ball_point_gpuiiifiPKfS0_PiS1_
.section .rodata,"a",@progbits
.globl _Z20query_ball_point_gpuiiifiPKfS0_PiS1_
.p2align 3, 0x0
_Z20query_ball_point_gpuiiifiPKfS0_PiS1_:
.quad _Z35__device_stub__query_ball_point_gpuiiifiPKfS0_PiS1_
.size _Z20query_ball_point_gpuiiifiPKfS0_PiS1_, 8
.type _Z15group_point_gpuiiiiiPKfPKiPf,@object # @_Z15group_point_gpuiiiiiPKfPKiPf
.globl _Z15group_point_gpuiiiiiPKfPKiPf
.p2align 3, 0x0
_Z15group_point_gpuiiiiiPKfPKiPf:
.quad _Z30__device_stub__group_point_gpuiiiiiPKfPKiPf
.size _Z15group_point_gpuiiiiiPKfPKiPf, 8
.type _Z20group_point_grad_gpuiiiiiPKfPKiPf,@object # @_Z20group_point_grad_gpuiiiiiPKfPKiPf
.globl _Z20group_point_grad_gpuiiiiiPKfPKiPf
.p2align 3, 0x0
_Z20group_point_grad_gpuiiiiiPKfPKiPf:
.quad _Z35__device_stub__group_point_grad_gpuiiiiiPKfPKiPf
.size _Z20group_point_grad_gpuiiiiiPKfPKiPf, 8
.type _Z18selection_sort_gpuiiiiPKfPiPf,@object # @_Z18selection_sort_gpuiiiiPKfPiPf
.globl _Z18selection_sort_gpuiiiiPKfPiPf
.p2align 3, 0x0
_Z18selection_sort_gpuiiiiPKfPiPf:
.quad _Z33__device_stub__selection_sort_gpuiiiiPKfPiPf
.size _Z18selection_sort_gpuiiiiPKfPiPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20query_ball_point_gpuiiifiPKfS0_PiS1_"
.size .L__unnamed_1, 41
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15group_point_gpuiiiiiPKfPKiPf"
.size .L__unnamed_2, 33
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z20group_point_grad_gpuiiiiiPKfPKiPf"
.size .L__unnamed_3, 38
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z18selection_sort_gpuiiiiPKfPiPf"
.size .L__unnamed_4, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__query_ball_point_gpuiiifiPKfS0_PiS1_
.addrsig_sym _Z30__device_stub__group_point_gpuiiiiiPKfPKiPf
.addrsig_sym _Z35__device_stub__group_point_grad_gpuiiiiiPKfPKiPf
.addrsig_sym _Z33__device_stub__selection_sort_gpuiiiiPKfPiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20query_ball_point_gpuiiifiPKfS0_PiS1_
.addrsig_sym _Z15group_point_gpuiiiiiPKfPKiPf
.addrsig_sym _Z20group_point_grad_gpuiiiiiPKfPKiPf
.addrsig_sym _Z18selection_sort_gpuiiiiPKfPiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00120fe8_00000000-6_tf_grouping_g.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2033:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z54__device_stub__Z20query_ball_point_gpuiiifiPKfS0_PiS1_iiifiPKfS0_PiS1_
.type _Z54__device_stub__Z20query_ball_point_gpuiiifiPKfS0_PiS1_iiifiPKfS0_PiS1_, @function
_Z54__device_stub__Z20query_ball_point_gpuiiifiPKfS0_PiS1_iiifiPKfS0_PiS1_:
.LFB2055:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movl %edx, 52(%rsp)
movss %xmm0, 48(%rsp)
movl %ecx, 44(%rsp)
movq %r8, 32(%rsp)
movq %r9, 24(%rsp)
movq 224(%rsp), %rax
movq %rax, 16(%rsp)
movq 232(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
leaq 16(%rsp), %rax
movq %rax, 184(%rsp)
leaq 8(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z20query_ball_point_gpuiiifiPKfS0_PiS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z54__device_stub__Z20query_ball_point_gpuiiifiPKfS0_PiS1_iiifiPKfS0_PiS1_, .-_Z54__device_stub__Z20query_ball_point_gpuiiifiPKfS0_PiS1_iiifiPKfS0_PiS1_
.globl _Z20query_ball_point_gpuiiifiPKfS0_PiS1_
.type _Z20query_ball_point_gpuiiifiPKfS0_PiS1_, @function
_Z20query_ball_point_gpuiiifiPKfS0_PiS1_:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z54__device_stub__Z20query_ball_point_gpuiiifiPKfS0_PiS1_iiifiPKfS0_PiS1_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z20query_ball_point_gpuiiifiPKfS0_PiS1_, .-_Z20query_ball_point_gpuiiifiPKfS0_PiS1_
.globl _Z22queryBallPointLauncheriiifiPKfS0_PiS1_
.type _Z22queryBallPointLauncheriiifiPKfS0_PiS1_, @function
_Z22queryBallPointLauncheriiifiPKfS0_PiS1_:
.LFB2027:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movss %xmm0, 12(%rsp)
movl %ecx, %r13d
movq %r8, %r14
movq %r9, %r15
movl $256, 36(%rsp)
movl $1, 40(%rsp)
movl %edi, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 120(%rsp)
.cfi_def_cfa_offset 120
pushq 120(%rsp)
.cfi_def_cfa_offset 128
movq %r15, %r9
movq %r14, %r8
movl %r13d, %ecx
movss 28(%rsp), %xmm0
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z54__device_stub__Z20query_ball_point_gpuiiifiPKfS0_PiS1_iiifiPKfS0_PiS1_
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z22queryBallPointLauncheriiifiPKfS0_PiS1_, .-_Z22queryBallPointLauncheriiifiPKfS0_PiS1_
.globl _Z46__device_stub__Z15group_point_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf
.type _Z46__device_stub__Z15group_point_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf, @function
_Z46__device_stub__Z15group_point_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf:
.LFB2057:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movl %ecx, 32(%rsp)
movl %r8d, 28(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq 216(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movq %rsp, %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15group_point_gpuiiiiiPKfPKiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z46__device_stub__Z15group_point_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf, .-_Z46__device_stub__Z15group_point_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf
.globl _Z15group_point_gpuiiiiiPKfPKiPf
.type _Z15group_point_gpuiiiiiPKfPKiPf, @function
_Z15group_point_gpuiiiiiPKfPKiPf:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z46__device_stub__Z15group_point_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z15group_point_gpuiiiiiPKfPKiPf, .-_Z15group_point_gpuiiiiiPKfPKiPf
.globl _Z18groupPointLauncheriiiiiPKfPKiPf
.type _Z18groupPointLauncheriiiiiPKfPKiPf, @function
_Z18groupPointLauncheriiiiiPKfPKiPf:
.LFB2029:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r13d
movl %r8d, %r14d
movq %r9, %r15
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl %edi, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L23:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 104
pushq 104(%rsp)
.cfi_def_cfa_offset 112
movq %r15, %r9
movl %r14d, %r8d
movl %r13d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z46__device_stub__Z15group_point_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L23
.cfi_endproc
.LFE2029:
.size _Z18groupPointLauncheriiiiiPKfPKiPf, .-_Z18groupPointLauncheriiiiiPKfPKiPf
.globl _Z51__device_stub__Z20group_point_grad_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf
.type _Z51__device_stub__Z20group_point_grad_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf, @function
_Z51__device_stub__Z20group_point_grad_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf:
.LFB2059:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movl %ecx, 32(%rsp)
movl %r8d, 28(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq 216(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movq %rsp, %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20group_point_grad_gpuiiiiiPKfPKiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z51__device_stub__Z20group_point_grad_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf, .-_Z51__device_stub__Z20group_point_grad_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf
.globl _Z20group_point_grad_gpuiiiiiPKfPKiPf
.type _Z20group_point_grad_gpuiiiiiPKfPKiPf, @function
_Z20group_point_grad_gpuiiiiiPKfPKiPf:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z51__device_stub__Z20group_point_grad_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z20group_point_grad_gpuiiiiiPKfPKiPf, .-_Z20group_point_grad_gpuiiiiiPKfPKiPf
.globl _Z22groupPointGradLauncheriiiiiPKfPKiPf
.type _Z22groupPointGradLauncheriiiiiPKfPKiPf, @function
_Z22groupPointGradLauncheriiiiiPKfPKiPf:
.LFB2030:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r13d
movl %r8d, %r14d
movq %r9, %r15
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl %edi, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L35:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 104
pushq 104(%rsp)
.cfi_def_cfa_offset 112
movq %r15, %r9
movl %r14d, %r8d
movl %r13d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z51__device_stub__Z20group_point_grad_gpuiiiiiPKfPKiPfiiiiiPKfPKiPf
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L35
.cfi_endproc
.LFE2030:
.size _Z22groupPointGradLauncheriiiiiPKfPKiPf, .-_Z22groupPointGradLauncheriiiiiPKfPKiPf
.globl _Z47__device_stub__Z18selection_sort_gpuiiiiPKfPiPfiiiiPKfPiPf
.type _Z47__device_stub__Z18selection_sort_gpuiiiiPKfPiPfiiiiPKfPiPf, @function
_Z47__device_stub__Z18selection_sort_gpuiiiiPKfPiPfiiiiPKfPiPf:
.LFB2061:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movl %ecx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 192(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L43
.L39:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L44
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18selection_sort_gpuiiiiPKfPiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L39
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z47__device_stub__Z18selection_sort_gpuiiiiPKfPiPfiiiiPKfPiPf, .-_Z47__device_stub__Z18selection_sort_gpuiiiiPKfPiPfiiiiPKfPiPf
.globl _Z18selection_sort_gpuiiiiPKfPiPf
.type _Z18selection_sort_gpuiiiiPKfPiPf, @function
_Z18selection_sort_gpuiiiiPKfPiPf:
.LFB2062:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z47__device_stub__Z18selection_sort_gpuiiiiPKfPiPfiiiiPKfPiPf
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z18selection_sort_gpuiiiiPKfPiPf, .-_Z18selection_sort_gpuiiiiPKfPiPf
.globl _Z21selectionSortLauncheriiiiPKfPiPf
.type _Z21selectionSortLauncheriiiiPKfPiPf, @function
_Z21selectionSortLauncheriiiiPKfPiPf:
.LFB2028:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r13d
movq %r8, %r14
movq %r9, %r15
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl %edi, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L47:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 104
pushq 104(%rsp)
.cfi_def_cfa_offset 112
movq %r15, %r9
movq %r14, %r8
movl %r13d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z47__device_stub__Z18selection_sort_gpuiiiiPKfPiPfiiiiPKfPiPf
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L47
.cfi_endproc
.LFE2028:
.size _Z21selectionSortLauncheriiiiPKfPiPf, .-_Z21selectionSortLauncheriiiiPKfPiPf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18selection_sort_gpuiiiiPKfPiPf"
.align 8
.LC1:
.string "_Z20group_point_grad_gpuiiiiiPKfPKiPf"
.align 8
.LC2:
.string "_Z15group_point_gpuiiiiiPKfPKiPf"
.align 8
.LC3:
.string "_Z20query_ball_point_gpuiiifiPKfS0_PiS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2064:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18selection_sort_gpuiiiiPKfPiPf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z20group_point_grad_gpuiiiiiPKfPKiPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z15group_point_gpuiiiiiPKfPKiPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z20query_ball_point_gpuiiifiPKfS0_PiS1_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "tf_grouping_g.hip"
.globl _Z35__device_stub__query_ball_point_gpuiiifiPKfS0_PiS1_ # -- Begin function _Z35__device_stub__query_ball_point_gpuiiifiPKfS0_PiS1_
.p2align 4, 0x90
.type _Z35__device_stub__query_ball_point_gpuiiifiPKfS0_PiS1_,@function
_Z35__device_stub__query_ball_point_gpuiiifiPKfS0_PiS1_: # @_Z35__device_stub__query_ball_point_gpuiiifiPKfS0_PiS1_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movss %xmm0, 16(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 88(%rsp)
movq %r9, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rax
movq %rax, 144(%rsp)
leaq 176(%rsp), %rax
movq %rax, 152(%rsp)
leaq 184(%rsp), %rax
movq %rax, 160(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20query_ball_point_gpuiiifiPKfS0_PiS1_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z35__device_stub__query_ball_point_gpuiiifiPKfS0_PiS1_, .Lfunc_end0-_Z35__device_stub__query_ball_point_gpuiiifiPKfS0_PiS1_
.cfi_endproc
# -- End function
.globl _Z30__device_stub__group_point_gpuiiiiiPKfPKiPf # -- Begin function _Z30__device_stub__group_point_gpuiiiiiPKfPKiPf
.p2align 4, 0x90
.type _Z30__device_stub__group_point_gpuiiiiiPKfPKiPf,@function
_Z30__device_stub__group_point_gpuiiiiiPKfPKiPf: # @_Z30__device_stub__group_point_gpuiiiiiPKfPKiPf
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15group_point_gpuiiiiiPKfPKiPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z30__device_stub__group_point_gpuiiiiiPKfPKiPf, .Lfunc_end1-_Z30__device_stub__group_point_gpuiiiiiPKfPKiPf
.cfi_endproc
# -- End function
.globl _Z35__device_stub__group_point_grad_gpuiiiiiPKfPKiPf # -- Begin function _Z35__device_stub__group_point_grad_gpuiiiiiPKfPKiPf
.p2align 4, 0x90
.type _Z35__device_stub__group_point_grad_gpuiiiiiPKfPKiPf,@function
_Z35__device_stub__group_point_grad_gpuiiiiiPKfPKiPf: # @_Z35__device_stub__group_point_grad_gpuiiiiiPKfPKiPf
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20group_point_grad_gpuiiiiiPKfPKiPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z35__device_stub__group_point_grad_gpuiiiiiPKfPKiPf, .Lfunc_end2-_Z35__device_stub__group_point_grad_gpuiiiiiPKfPKiPf
.cfi_endproc
# -- End function
.globl _Z33__device_stub__selection_sort_gpuiiiiPKfPiPf # -- Begin function _Z33__device_stub__selection_sort_gpuiiiiPKfPiPf
.p2align 4, 0x90
.type _Z33__device_stub__selection_sort_gpuiiiiPKfPiPf,@function
_Z33__device_stub__selection_sort_gpuiiiiPKfPiPf: # @_Z33__device_stub__selection_sort_gpuiiiiPKfPiPf
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18selection_sort_gpuiiiiPKfPiPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end3:
.size _Z33__device_stub__selection_sort_gpuiiiiPKfPiPf, .Lfunc_end3-_Z33__device_stub__selection_sort_gpuiiiiPKfPiPf
.cfi_endproc
# -- End function
.globl _Z22queryBallPointLauncheriiifiPKfS0_PiS1_ # -- Begin function _Z22queryBallPointLauncheriiifiPKfS0_PiS1_
.p2align 4, 0x90
.type _Z22queryBallPointLauncheriiifiPKfS0_PiS1_,@function
_Z22queryBallPointLauncheriiifiPKfS0_PiS1_: # @_Z22queryBallPointLauncheriiifiPKfS0_PiS1_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movq %r8, %r14
movl %ecx, %ebp
movss %xmm0, 8(%rsp) # 4-byte Spill
movl %edx, %r15d
movl %esi, %r12d
movl %edi, %r13d
movl %edi, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movq 248(%rsp), %rax
movq 240(%rsp), %rcx
movl %r13d, 28(%rsp)
movl %r12d, 24(%rsp)
movl %r15d, 20(%rsp)
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 16(%rsp)
movl %ebp, 12(%rsp)
movq %r14, 104(%rsp)
movq %rbx, 96(%rsp)
movq %rcx, 88(%rsp)
movq %rax, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 104(%rsp), %rax
movq %rax, 152(%rsp)
leaq 96(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rax
movq %rax, 168(%rsp)
leaq 80(%rsp), %rax
movq %rax, 176(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z20query_ball_point_gpuiiifiPKfS0_PiS1_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z22queryBallPointLauncheriiifiPKfS0_PiS1_, .Lfunc_end4-_Z22queryBallPointLauncheriiifiPKfS0_PiS1_
.cfi_endproc
# -- End function
.globl _Z21selectionSortLauncheriiiiPKfPiPf # -- Begin function _Z21selectionSortLauncheriiiiPKfPiPf
.p2align 4, 0x90
.type _Z21selectionSortLauncheriiiiPKfPiPf,@function
_Z21selectionSortLauncheriiiiPKfPiPf: # @_Z21selectionSortLauncheriiiiPKfPiPf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movq %r8, %r14
movl %ecx, %ebp
movl %edx, %r15d
movl %esi, %r12d
movl %edi, %r13d
movl %edi, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq 208(%rsp), %rax
movl %r13d, 20(%rsp)
movl %r12d, 16(%rsp)
movl %r15d, 12(%rsp)
movl %ebp, 8(%rsp)
movq %r14, 88(%rsp)
movq %rbx, 80(%rsp)
movq %rax, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18selection_sort_gpuiiiiPKfPiPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z21selectionSortLauncheriiiiPKfPiPf, .Lfunc_end5-_Z21selectionSortLauncheriiiiPKfPiPf
.cfi_endproc
# -- End function
.globl _Z18groupPointLauncheriiiiiPKfPKiPf # -- Begin function _Z18groupPointLauncheriiiiiPKfPKiPf
.p2align 4, 0x90
.type _Z18groupPointLauncheriiiiiPKfPKiPf,@function
_Z18groupPointLauncheriiiiiPKfPKiPf: # @_Z18groupPointLauncheriiiiiPKfPKiPf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movl %r8d, %ebp
movl %ecx, %r14d
movl %edx, %r15d
movl %esi, %r12d
movl %edi, %r13d
movl %edi, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_2
# %bb.1:
movq 232(%rsp), %rax
movq 224(%rsp), %rcx
movl %r13d, 20(%rsp)
movl %r12d, 16(%rsp)
movl %r15d, 12(%rsp)
movl %r14d, 8(%rsp)
movl %ebp, 4(%rsp)
movq %rbx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rax, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15group_point_gpuiiiiiPKfPKiPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_2:
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z18groupPointLauncheriiiiiPKfPKiPf, .Lfunc_end6-_Z18groupPointLauncheriiiiiPKfPKiPf
.cfi_endproc
# -- End function
.globl _Z22groupPointGradLauncheriiiiiPKfPKiPf # -- Begin function _Z22groupPointGradLauncheriiiiiPKfPKiPf
.p2align 4, 0x90
.type _Z22groupPointGradLauncheriiiiiPKfPKiPf,@function
_Z22groupPointGradLauncheriiiiiPKfPKiPf: # @_Z22groupPointGradLauncheriiiiiPKfPKiPf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movl %r8d, %ebp
movl %ecx, %r14d
movl %edx, %r15d
movl %esi, %r12d
movl %edi, %r13d
movl %edi, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_2
# %bb.1:
movq 232(%rsp), %rax
movq 224(%rsp), %rcx
movl %r13d, 20(%rsp)
movl %r12d, 16(%rsp)
movl %r15d, 12(%rsp)
movl %r14d, 8(%rsp)
movl %ebp, 4(%rsp)
movq %rbx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rax, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20group_point_grad_gpuiiiiiPKfPKiPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_2:
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _Z22groupPointGradLauncheriiiiiPKfPKiPf, .Lfunc_end7-_Z22groupPointGradLauncheriiiiiPKfPKiPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20query_ball_point_gpuiiifiPKfS0_PiS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15group_point_gpuiiiiiPKfPKiPf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20group_point_grad_gpuiiiiiPKfPKiPf, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18selection_sort_gpuiiiiPKfPiPf, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20query_ball_point_gpuiiifiPKfS0_PiS1_,@object # @_Z20query_ball_point_gpuiiifiPKfS0_PiS1_
.section .rodata,"a",@progbits
.globl _Z20query_ball_point_gpuiiifiPKfS0_PiS1_
.p2align 3, 0x0
_Z20query_ball_point_gpuiiifiPKfS0_PiS1_:
.quad _Z35__device_stub__query_ball_point_gpuiiifiPKfS0_PiS1_
.size _Z20query_ball_point_gpuiiifiPKfS0_PiS1_, 8
.type _Z15group_point_gpuiiiiiPKfPKiPf,@object # @_Z15group_point_gpuiiiiiPKfPKiPf
.globl _Z15group_point_gpuiiiiiPKfPKiPf
.p2align 3, 0x0
_Z15group_point_gpuiiiiiPKfPKiPf:
.quad _Z30__device_stub__group_point_gpuiiiiiPKfPKiPf
.size _Z15group_point_gpuiiiiiPKfPKiPf, 8
.type _Z20group_point_grad_gpuiiiiiPKfPKiPf,@object # @_Z20group_point_grad_gpuiiiiiPKfPKiPf
.globl _Z20group_point_grad_gpuiiiiiPKfPKiPf
.p2align 3, 0x0
_Z20group_point_grad_gpuiiiiiPKfPKiPf:
.quad _Z35__device_stub__group_point_grad_gpuiiiiiPKfPKiPf
.size _Z20group_point_grad_gpuiiiiiPKfPKiPf, 8
.type _Z18selection_sort_gpuiiiiPKfPiPf,@object # @_Z18selection_sort_gpuiiiiPKfPiPf
.globl _Z18selection_sort_gpuiiiiPKfPiPf
.p2align 3, 0x0
_Z18selection_sort_gpuiiiiPKfPiPf:
.quad _Z33__device_stub__selection_sort_gpuiiiiPKfPiPf
.size _Z18selection_sort_gpuiiiiPKfPiPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20query_ball_point_gpuiiifiPKfS0_PiS1_"
.size .L__unnamed_1, 41
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15group_point_gpuiiiiiPKfPKiPf"
.size .L__unnamed_2, 33
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z20group_point_grad_gpuiiiiiPKfPKiPf"
.size .L__unnamed_3, 38
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z18selection_sort_gpuiiiiPKfPiPf"
.size .L__unnamed_4, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__query_ball_point_gpuiiifiPKfS0_PiS1_
.addrsig_sym _Z30__device_stub__group_point_gpuiiiiiPKfPKiPf
.addrsig_sym _Z35__device_stub__group_point_grad_gpuiiiiiPKfPKiPf
.addrsig_sym _Z33__device_stub__selection_sort_gpuiiiiPKfPiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20query_ball_point_gpuiiifiPKfS0_PiS1_
.addrsig_sym _Z15group_point_gpuiiiiiPKfPKiPf
.addrsig_sym _Z20group_point_grad_gpuiiiiiPKfPKiPf
.addrsig_sym _Z18selection_sort_gpuiiiiPKfPiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cstdlib>
#include <math.h>
#include <chrono>
#include <iomanip>
#include <fstream>
using namespace std;
using namespace std::chrono;
typedef unsigned long long ULL;
ofstream primeresult;
ofstream timeresult;
__global__ void cuda_erastothenes_sieve (ULL *marked, ULL *limit, ULL *n, int *totalThreads) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
//printf("index %d,limit %llu , n %llu , totalThreads %d \n",index, *limit , *n , *totalThreads);
//printf("block %d, thread %d \n", blockIdx.x, threadIdx.x);
marked[0]=1;
marked[1]=1;
index=index+2;
if(*totalThreads>*n || index >*limit){
return ;
}else if(*totalThreads ==1){
for(ULL p=2;p<=*limit;p++){
for(ULL multiple=2*p; multiple<*n; multiple+=p){
marked[multiple]=1;
}
}
}
else{
//printf("index %d,limit %llu , n %llu , totalThreads %d \n",index, *limit , *n , *totalThreads);
for(ULL p=index;p<=*limit;p+=*totalThreads){
if(marked[p]==1 || p%2==0 && p>2) return;
//printf("index %d , p%llu \n",index,p);
for(ULL multiple=2*p; multiple<*n; multiple+=p){
//printf("multiple %llu \n",multiple);
marked[multiple]=1;
}
}
}
__syncthreads();
}
int main(int argc, char **argv){
ULL size;
ULL *list,*d_list,limit,*d_limit,*d_n,n;
n=atoi(argv[1]);
int threads=atoi(argv[2]);
//int thread_per_block=atoi(argv[3]);
int blocks= floor(n/threads);
int totalThreads = threads;
int *d_totalThreads;
primeresult.open("cudaSieveList.txt");
timeresult.open("cudaSieveResult.txt",ios::out | ios::app );
size = n*sizeof(ULL);
limit = floor(sqrt(n));
cudaMalloc((void**)&d_list,size);
cudaMalloc((void**)&d_limit,sizeof(ULL));
cudaMalloc((void**)&d_n,sizeof(ULL));
cudaMalloc((void**)&d_totalThreads,sizeof(int));
list = (ULL*) malloc(size);
memset(list,0,size);
cudaMemset(d_list, 0, size);
cudaMemcpy(d_list ,list ,size ,cudaMemcpyHostToDevice);
cudaMemcpy(d_limit ,&limit ,sizeof(ULL) ,cudaMemcpyHostToDevice);
cudaMemcpy(d_n ,&n ,sizeof(ULL) ,cudaMemcpyHostToDevice);
cudaMemcpy(d_totalThreads ,&totalThreads ,sizeof(int) ,cudaMemcpyHostToDevice);
auto begin= std::chrono::high_resolution_clock::now();
cuda_erastothenes_sieve<<<blocks,threads>>>(d_list,d_limit,d_n,d_totalThreads);
auto end = std::chrono::high_resolution_clock::now();
auto duration = duration_cast<std::chrono::microseconds>(end - begin);
timeresult<<duration.count()<<endl;
cudaMemcpy(list,d_list, size, cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
// check for error
cudaError_t error = cudaGetLastError();
if(error != cudaSuccess)
{
// print the CUDA error message and exit
printf("CUDA error: %s\n", cudaGetErrorString(error));
return 0;
}
for(ULL i=0;i<n;i++){
if(list[i]==0){
primeresult<<i<<endl;
//cout<<i<<endl;
};
}
//cout<<duration.count()<<endl;
free(list);
cudaFree(d_list);
cudaFree(d_limit);
cudaFree(d_n);
primeresult.close();
timeresult.close();
return 0;
} | code for sm_80
Function : _Z23cuda_erastothenes_sievePyS_S_Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff067624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR12, c[0x0][0x118] ; /* 0x00004600000c7ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff077624 */
/* 0x000fe400078e00ff */
/*0040*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fe400078e00ff */
/*0050*/ IMAD.MOV.U32 R9, RZ, RZ, 0x0 ; /* 0x00000000ff097424 */
/* 0x000fe400078e00ff */
/*0060*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe400078e00ff */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff057624 */
/* 0x000fe200078e00ff */
/*0080*/ STG.E.64 [R6.64], R8 ; /* 0x0000000806007986 */
/* 0x0001e2000c101b0c */
/*0090*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fc400078e00ff */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fe200078e00ff */
/*00b0*/ STG.E.64 [R6.64+0x8], R8 ; /* 0x0000080806007986 */
/* 0x0001e8000c101b0c */
/*00c0*/ LDG.E R10, [R4.64] ; /* 0x0000000c040a7981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E.64 R12, [R2.64] ; /* 0x0000000c020c7981 */
/* 0x000ee2000c1e1b00 */
/*00e0*/ SHF.R.S32.HI R0, RZ, 0x1f, R10 ; /* 0x0000001fff007819 */
/* 0x004fc4000001140a */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R12, R10, PT ; /* 0x0000000a0c00720c */
/* 0x008fc80003f06070 */
/*0100*/ ISETP.GE.U32.AND.EX P0, PT, R13, R0, PT, P0 ; /* 0x000000000d00720c */
/* 0x000fda0003f06100 */
/*0110*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0120*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff067624 */
/* 0x001fe400078e00ff */
/*0130*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff077624 */
/* 0x000fca00078e00ff */
/*0140*/ LDG.E.64 R14, [R6.64] ; /* 0x0000000c060e7981 */
/* 0x000ea8000c1e1b00 */
/*0150*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0160*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e240000002500 */
/*0170*/ IMAD R0, R9, c[0x0][0x0], R0 ; /* 0x0000000009007a24 */
/* 0x001fca00078e0200 */
/*0180*/ IADD3 R0, R0, 0x2, RZ ; /* 0x0000000200007810 */
/* 0x000fc80007ffe0ff */
/*0190*/ SHF.R.S32.HI R11, RZ, 0x1f, R0 ; /* 0x0000001fff0b7819 */
/* 0x000fe40000011400 */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R14, R0, PT ; /* 0x000000000e00720c */
/* 0x004fc80003f06070 */
/*01b0*/ ISETP.GE.U32.AND.EX P0, PT, R15, R11, PT, P0 ; /* 0x0000000b0f00720c */
/* 0x000fda0003f06100 */
/*01c0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.NE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fe20003f05270 */
/*01e0*/ IMAD.MOV.U32 R8, RZ, RZ, R14 ; /* 0x000000ffff087224 */
/* 0x000fe400078e000e */
/*01f0*/ IMAD.MOV.U32 R9, RZ, RZ, R15 ; /* 0x000000ffff097224 */
/* 0x000fd400078e000f */
/*0200*/ @!P0 BRA 0x520 ; /* 0x0000031000008947 */
/* 0x000fea0003800000 */
/*0210*/ LEA R14, P0, R0, c[0x0][0x160], 0x3 ; /* 0x00005800000e7a11 */
/* 0x000fc800078018ff */
/*0220*/ LEA.HI.X R15, R0, c[0x0][0x164], R11, 0x3, P0 ; /* 0x00005900000f7a11 */
/* 0x000fcc00000f1c0b */
/*0230*/ LDG.E.64 R14, [R14.64] ; /* 0x0000000c0e0e7981 */
/* 0x000ea4000c1e1b00 */
/*0240*/ ISETP.NE.U32.AND P0, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x004fc80003f05070 */
/*0250*/ ISETP.NE.AND.EX P0, PT, R15, RZ, PT, P0 ; /* 0x000000ff0f00720c */
/* 0x000fda0003f05300 */
/*0260*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0270*/ LOP3.LUT R14, R0.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x00000001000e7812 */
/* 0x040fe400078ec0ff */
/*0280*/ ISETP.GT.U32.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe40003f04070 */
/*0290*/ ISETP.NE.U32.AND P1, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fe40003f25070 */
/*02a0*/ ISETP.GT.U32.AND.EX P0, PT, R11, RZ, PT, P0 ; /* 0x000000ff0b00720c */
/* 0x000fe40003f04100 */
/*02b0*/ ISETP.NE.U32.AND.EX P1, PT, RZ, RZ, PT, P1 ; /* 0x000000ffff00720c */
/* 0x000fda0003f25110 */
/*02c0*/ @P1 EXIT P0 ; /* 0x000000000000194d */
/* 0x001fea0000000000 */
/*02d0*/ IMAD.SHL.U32 R15, R0.reuse, 0x2, RZ ; /* 0x00000002000f7824 */
/* 0x040fe200078e00ff */
/*02e0*/ SHF.L.U64.HI R14, R0, 0x1, R11 ; /* 0x00000001000e7819 */
/* 0x000fe2000001020b */
/*02f0*/ BSSY B0, 0x460 ; /* 0x0000016000007945 */
/* 0x000fe60003800000 */
/*0300*/ ISETP.GE.U32.AND P0, PT, R15, R12, PT ; /* 0x0000000c0f00720c */
/* 0x000fc80003f06070 */
/*0310*/ ISETP.GE.U32.AND.EX P0, PT, R14, R13, PT, P0 ; /* 0x0000000d0e00720c */
/* 0x000fda0003f06100 */
/*0320*/ @P0 BRA 0x450 ; /* 0x0000012000000947 */
/* 0x000fea0003800000 */
/*0330*/ BSSY B1, 0x410 ; /* 0x000000d000017945 */
/* 0x000fe20003800000 */
/*0340*/ IMAD.MOV.U32 R10, RZ, RZ, R14 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e000e */
/*0350*/ LEA R8, P0, R15.reuse, c[0x0][0x160], 0x3 ; /* 0x000058000f087a11 */
/* 0x040fe200078018ff */
/*0360*/ IMAD.MOV.U32 R12, RZ, RZ, 0x1 ; /* 0x00000001ff0c7424 */
/* 0x000fe400078e00ff */
/*0370*/ IMAD.MOV.U32 R13, RZ, RZ, 0x0 ; /* 0x00000000ff0d7424 */
/* 0x000fe200078e00ff */
/*0380*/ LEA.HI.X R9, R15, c[0x0][0x164], R10, 0x3, P0 ; /* 0x000059000f097a11 */
/* 0x000fca00000f1c0a */
/*0390*/ STG.E.64 [R8.64], R12 ; /* 0x0000000c08007986 */
/* 0x0001e8000c101b0c */
/*03a0*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000c02107981 */
/* 0x000ea2000c1e1b00 */
/*03b0*/ IADD3 R15, P0, R0, R15, RZ ; /* 0x0000000f000f7210 */
/* 0x000fca0007f1e0ff */
/*03c0*/ IMAD.X R10, R11, 0x1, R10, P0 ; /* 0x000000010b0a7824 */
/* 0x000fe200000e060a */
/*03d0*/ ISETP.GE.U32.AND P0, PT, R15, R16, PT ; /* 0x000000100f00720c */
/* 0x004fc80003f06070 */
/*03e0*/ ISETP.GE.U32.AND.EX P0, PT, R10, R17, PT, P0 ; /* 0x000000110a00720c */
/* 0x000fda0003f06100 */
/*03f0*/ @!P0 BRA 0x350 ; /* 0xffffff5000008947 */
/* 0x001fea000383ffff */
/*0400*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0410*/ LDG.E R10, [R4.64] ; /* 0x0000000c040a7981 */
/* 0x000168000c1e1900 */
/*0420*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000c06087981 */
/* 0x000162000c1e1b00 */
/*0430*/ IMAD.MOV.U32 R12, RZ, RZ, R16 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0010 */
/*0440*/ IMAD.MOV.U32 R13, RZ, RZ, R17 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0011 */
/*0450*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0460*/ IADD3 R0, P0, R10, R0, RZ ; /* 0x000000000a007210 */
/* 0x020fc80007f1e0ff */
/*0470*/ LEA.HI.X.SX32 R11, R10, R11, 0x1, P0 ; /* 0x0000000b0a0b7211 */
/* 0x000fe400000f0eff */
/*0480*/ ISETP.GT.U32.AND P0, PT, R0, R8, PT ; /* 0x000000080000720c */
/* 0x000fc80003f04070 */
/*0490*/ ISETP.GT.U32.AND.EX P0, PT, R11, R9, PT, P0 ; /* 0x000000090b00720c */
/* 0x000fda0003f04100 */
/*04a0*/ @P0 BRA 0x730 ; /* 0x0000028000000947 */
/* 0x000fea0003800000 */
/*04b0*/ LEA R14, P0, R0, c[0x0][0x160], 0x3 ; /* 0x00005800000e7a11 */
/* 0x000fc800078018ff */
/*04c0*/ LEA.HI.X R15, R0, c[0x0][0x164], R11, 0x3, P0 ; /* 0x00005900000f7a11 */
/* 0x000fcc00000f1c0b */
/*04d0*/ LDG.E.64 R14, [R14.64] ; /* 0x0000000c0e0e7981 */
/* 0x000ea4000c1e1b00 */
/*04e0*/ ISETP.NE.U32.AND P0, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x004fc80003f05070 */
/*04f0*/ ISETP.NE.AND.EX P0, PT, R15, RZ, PT, P0 ; /* 0x000000ff0f00720c */
/* 0x000fda0003f05300 */
/*0500*/ @P0 BRA 0x270 ; /* 0xfffffd6000000947 */
/* 0x000fea000383ffff */
/*0510*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0520*/ ISETP.GE.U32.AND P0, PT, R8, 0x2, PT ; /* 0x000000020800780c */
/* 0x000fc80003f06070 */
/*0530*/ ISETP.GE.U32.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fda0003f06100 */
/*0540*/ @!P0 BRA 0x730 ; /* 0x000001e000008947 */
/* 0x000fea0003800000 */
/*0550*/ UMOV UR9, 0x2 ; /* 0x0000000200097882 */
/* 0x000fe40000000000 */
/*0560*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0570*/ USHF.L.U64.HI UR8, UR9, 0x1, UR4 ; /* 0x0000000109087899 */
/* 0x000fe40008010204 */
/*0580*/ USHF.L.U32 UR7, UR9, 0x1, URZ ; /* 0x0000000109077899 */
/* 0x000fc8000800063f */
/*0590*/ IMAD.U32 R0, RZ, RZ, UR8 ; /* 0x00000008ff007e24 */
/* 0x000fe4000f8e00ff */
/*05a0*/ ISETP.LE.U32.AND P0, PT, R12, UR7, PT ; /* 0x000000070c007c0c */
/* 0x000fc8000bf03070 */
/*05b0*/ ISETP.GE.U32.AND.EX P0, PT, R0, R13, PT, P0 ; /* 0x0000000d0000720c */
/* 0x000fda0003f06100 */
/*05c0*/ @P0 BRA 0x6d0 ; /* 0x0000010000000947 */
/* 0x001fea0003800000 */
/*05d0*/ ULDC.64 UR10, c[0x0][0x160] ; /* 0x00005800000a7ab9 */
/* 0x000fe20000000a00 */
/*05e0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fe200078e00ff */
/*05f0*/ ULEA UR5, UP0, UR7, UR10, 0x3 ; /* 0x0000000a07057291 */
/* 0x000fe2000f80183f */
/*0600*/ IMAD.MOV.U32 R9, RZ, RZ, 0x0 ; /* 0x00000000ff097424 */
/* 0x000fc600078e00ff */
/*0610*/ ULEA.HI.X UR6, UR7, UR11, UR8, 0x3, UP0 ; /* 0x0000000b07067291 */
/* 0x000fe400080f1c08 */
/*0620*/ IMAD.U32 R4, RZ, RZ, UR5 ; /* 0x00000005ff047e24 */
/* 0x000fc8000f8e00ff */
/*0630*/ IMAD.U32 R5, RZ, RZ, UR6 ; /* 0x00000006ff057e24 */
/* 0x000fca000f8e00ff */
/*0640*/ STG.E.64 [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x0001e8000c101b0c */
/*0650*/ LDG.E.64 R12, [R2.64] ; /* 0x0000000c020c7981 */
/* 0x000ea2000c1e1b00 */
/*0660*/ UIADD3 UR7, UP0, UR9, UR7, URZ ; /* 0x0000000709077290 */
/* 0x000fc8000ff1e03f */
/*0670*/ UIADD3.X UR8, UR4, UR8, URZ, UP0, !UPT ; /* 0x0000000804087290 */
/* 0x000fcc00087fe43f */
/*0680*/ IMAD.U32 R0, RZ, RZ, UR8 ; /* 0x00000008ff007e24 */
/* 0x000fe2000f8e00ff */
/*0690*/ ISETP.LE.U32.AND P0, PT, R12, UR7, PT ; /* 0x000000070c007c0c */
/* 0x004fc8000bf03070 */
/*06a0*/ ISETP.GE.U32.AND.EX P0, PT, R0, R13, PT, P0 ; /* 0x0000000d0000720c */
/* 0x000fda0003f06100 */
/*06b0*/ @!P0 BRA 0x5d0 ; /* 0xffffff1000008947 */
/* 0x001fea000383ffff */
/*06c0*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000c06087981 */
/* 0x000164000c1e1b00 */
/*06d0*/ UIADD3 UR9, UP0, UR9, 0x1, URZ ; /* 0x0000000109097890 */
/* 0x000fc8000ff1e03f */
/*06e0*/ UIADD3.X UR4, URZ, UR4, URZ, UP0, !UPT ; /* 0x000000043f047290 */
/* 0x000fe400087fe43f */
/*06f0*/ ISETP.LT.U32.AND P0, PT, R8, UR9, PT ; /* 0x0000000908007c0c */
/* 0x020fc8000bf01070 */
/*0700*/ IMAD.U32 R0, RZ, RZ, UR4 ; /* 0x00000004ff007e24 */
/* 0x000fca000f8e00ff */
/*0710*/ ISETP.GT.U32.AND.EX P0, PT, R0, R9, PT, P0 ; /* 0x000000090000720c */
/* 0x000fda0003f04100 */
/*0720*/ @!P0 BRA 0x570 ; /* 0xfffffe4000008947 */
/* 0x000fea000383ffff */
/*0730*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0740*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0750*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0760*/ BRA 0x760; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cstdlib>
#include <math.h>
#include <chrono>
#include <iomanip>
#include <fstream>
using namespace std;
using namespace std::chrono;
typedef unsigned long long ULL;
ofstream primeresult;
ofstream timeresult;
__global__ void cuda_erastothenes_sieve (ULL *marked, ULL *limit, ULL *n, int *totalThreads) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
//printf("index %d,limit %llu , n %llu , totalThreads %d \n",index, *limit , *n , *totalThreads);
//printf("block %d, thread %d \n", blockIdx.x, threadIdx.x);
marked[0]=1;
marked[1]=1;
index=index+2;
if(*totalThreads>*n || index >*limit){
return ;
}else if(*totalThreads ==1){
for(ULL p=2;p<=*limit;p++){
for(ULL multiple=2*p; multiple<*n; multiple+=p){
marked[multiple]=1;
}
}
}
else{
//printf("index %d,limit %llu , n %llu , totalThreads %d \n",index, *limit , *n , *totalThreads);
for(ULL p=index;p<=*limit;p+=*totalThreads){
if(marked[p]==1 || p%2==0 && p>2) return;
//printf("index %d , p%llu \n",index,p);
for(ULL multiple=2*p; multiple<*n; multiple+=p){
//printf("multiple %llu \n",multiple);
marked[multiple]=1;
}
}
}
__syncthreads();
}
int main(int argc, char **argv){
ULL size;
ULL *list,*d_list,limit,*d_limit,*d_n,n;
n=atoi(argv[1]);
int threads=atoi(argv[2]);
//int thread_per_block=atoi(argv[3]);
int blocks= floor(n/threads);
int totalThreads = threads;
int *d_totalThreads;
primeresult.open("cudaSieveList.txt");
timeresult.open("cudaSieveResult.txt",ios::out | ios::app );
size = n*sizeof(ULL);
limit = floor(sqrt(n));
cudaMalloc((void**)&d_list,size);
cudaMalloc((void**)&d_limit,sizeof(ULL));
cudaMalloc((void**)&d_n,sizeof(ULL));
cudaMalloc((void**)&d_totalThreads,sizeof(int));
list = (ULL*) malloc(size);
memset(list,0,size);
cudaMemset(d_list, 0, size);
cudaMemcpy(d_list ,list ,size ,cudaMemcpyHostToDevice);
cudaMemcpy(d_limit ,&limit ,sizeof(ULL) ,cudaMemcpyHostToDevice);
cudaMemcpy(d_n ,&n ,sizeof(ULL) ,cudaMemcpyHostToDevice);
cudaMemcpy(d_totalThreads ,&totalThreads ,sizeof(int) ,cudaMemcpyHostToDevice);
auto begin= std::chrono::high_resolution_clock::now();
cuda_erastothenes_sieve<<<blocks,threads>>>(d_list,d_limit,d_n,d_totalThreads);
auto end = std::chrono::high_resolution_clock::now();
auto duration = duration_cast<std::chrono::microseconds>(end - begin);
timeresult<<duration.count()<<endl;
cudaMemcpy(list,d_list, size, cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
// check for error
cudaError_t error = cudaGetLastError();
if(error != cudaSuccess)
{
// print the CUDA error message and exit
printf("CUDA error: %s\n", cudaGetErrorString(error));
return 0;
}
for(ULL i=0;i<n;i++){
if(list[i]==0){
primeresult<<i<<endl;
//cout<<i<<endl;
};
}
//cout<<duration.count()<<endl;
free(list);
cudaFree(d_list);
cudaFree(d_limit);
cudaFree(d_n);
primeresult.close();
timeresult.close();
return 0;
} | .file "tmpxft_0005cbe5_00000000-6_cudaSieve.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4144:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4144:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z23cuda_erastothenes_sievePyS_S_PiPyS_S_Pi
.type _Z49__device_stub__Z23cuda_erastothenes_sievePyS_S_PiPyS_S_Pi, @function
_Z49__device_stub__Z23cuda_erastothenes_sievePyS_S_PiPyS_S_Pi:
.LFB4166:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23cuda_erastothenes_sievePyS_S_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4166:
.size _Z49__device_stub__Z23cuda_erastothenes_sievePyS_S_PiPyS_S_Pi, .-_Z49__device_stub__Z23cuda_erastothenes_sievePyS_S_PiPyS_S_Pi
.globl _Z23cuda_erastothenes_sievePyS_S_Pi
.type _Z23cuda_erastothenes_sievePyS_S_Pi, @function
_Z23cuda_erastothenes_sievePyS_S_Pi:
.LFB4167:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z23cuda_erastothenes_sievePyS_S_PiPyS_S_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4167:
.size _Z23cuda_erastothenes_sievePyS_S_Pi, .-_Z23cuda_erastothenes_sievePyS_S_Pi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "cudaSieveList.txt"
.LC1:
.string "cudaSieveResult.txt"
.LC6:
.string "CUDA error: %s\n"
.text
.globl main
.type main, @function
main:
.LFB4138:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $96, %rsp
.cfi_def_cfa_offset 144
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
cltq
movq %rax, 48(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movslq %eax, %rcx
movq 48(%rsp), %rax
movl $0, %edx
divq %rcx
testq %rax, %rax
js .L12
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
.L13:
cvttsd2sil %xmm0, %r14d
movl %r12d, 12(%rsp)
movl $16, %edx
leaq .LC0(%rip), %rsi
leaq primeresult(%rip), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
movl $17, %edx
leaq .LC1(%rip), %rsi
leaq timeresult(%rip), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
movq 48(%rsp), %rax
leaq 0(,%rax,8), %rbx
testq %rax, %rax
js .L14
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
.L15:
pxor %xmm1, %xmm1
ucomisd %xmm0, %xmm1
ja .L37
sqrtsd %xmm0, %xmm0
.L18:
movapd %xmm0, %xmm1
movsd .LC7(%rip), %xmm2
movapd %xmm0, %xmm3
andpd %xmm2, %xmm3
movsd .LC3(%rip), %xmm4
ucomisd %xmm3, %xmm4
jbe .L19
cvttsd2siq %xmm0, %rax
pxor %xmm3, %xmm3
cvtsi2sdq %rax, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
movapd %xmm3, %xmm1
.L19:
comisd .LC5(%rip), %xmm1
jnb .L20
cvttsd2siq %xmm1, %rax
movq %rax, 24(%rsp)
.L21:
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rcx
movq %rbx, %rdx
movl $0, %esi
movq %rax, %rdi
call __memset_chk@PLT
movq %rbx, %rdx
movl $0, %esi
movq 16(%rsp), %rdi
call cudaMemset@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rsi
movl $1, %ecx
movl $8, %edx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $8, %edx
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
leaq 12(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r13
movl %r12d, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl %r14d, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L22:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %r13, %rax
movq %rax, %rcx
movabsq $2361183241434822607, %rdx
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
movq %rdx, %rsi
leaq timeresult(%rip), %rdi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L23
movl $0, %ebx
leaq primeresult(%rip), %r13
cmpq $0, 48(%rsp)
jne .L24
.L25:
movq %rbp, %rdi
call free@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
leaq primeresult(%rip), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
leaq timeresult(%rip), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
.L26:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L40
movl $0, %eax
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
jmp .L13
.L14:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
jmp .L15
.L37:
call sqrt@PLT
jmp .L18
.L20:
subsd .LC5(%rip), %xmm1
cvttsd2siq %xmm1, %rax
movq %rax, 24(%rsp)
btcq $63, 24(%rsp)
jmp .L21
.L39:
movq 56(%rsp), %rcx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z49__device_stub__Z23cuda_erastothenes_sievePyS_S_PiPyS_S_Pi
jmp .L22
.L23:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L26
.L42:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L41
call _ZSt16__throw_bad_castv@PLT
.L41:
call __stack_chk_fail@PLT
.L30:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
.L31:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.L27:
addq $1, %rbx
cmpq 48(%rsp), %rbx
jnb .L25
.L24:
cmpq $0, 0(%rbp,%rbx,8)
jne .L27
movq %rbx, %rsi
movq %r13, %rdi
call _ZNSo9_M_insertIyEERSoT_@PLT
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r14
testq %r14, %r14
je .L42
cmpb $0, 56(%r14)
je .L30
movzbl 67(%r14), %esi
jmp .L31
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4138:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "_Z23cuda_erastothenes_sievePyS_S_Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4169:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z23cuda_erastothenes_sievePyS_S_Pi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4169:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.text
.type _GLOBAL__sub_I_primeresult, @function
_GLOBAL__sub_I_primeresult:
.LFB4900:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
leaq primeresult(%rip), %rbx
movq %rbx, %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev@PLT
leaq __dso_handle(%rip), %r12
movq %r12, %rdx
movq %rbx, %rsi
movq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@GOTPCREL(%rip), %rbx
movq %rbx, %rdi
call __cxa_atexit@PLT
leaq timeresult(%rip), %rbp
movq %rbp, %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev@PLT
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call __cxa_atexit@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4900:
.size _GLOBAL__sub_I_primeresult, .-_GLOBAL__sub_I_primeresult
.section .init_array
.align 8
.quad _GLOBAL__sub_I_primeresult
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl timeresult
.bss
.align 32
.type timeresult, @object
.size timeresult, 512
timeresult:
.zero 512
.globl primeresult
.align 32
.type primeresult, @object
.size primeresult, 512
primeresult:
.zero 512
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1127219200
.align 8
.LC5:
.long 0
.long 1138753536
.align 8
.LC7:
.long -1
.long 2147483647
.hidden __dso_handle
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cstdlib>
#include <math.h>
#include <chrono>
#include <iomanip>
#include <fstream>
using namespace std;
using namespace std::chrono;
typedef unsigned long long ULL;
ofstream primeresult;
ofstream timeresult;
__global__ void cuda_erastothenes_sieve (ULL *marked, ULL *limit, ULL *n, int *totalThreads) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
//printf("index %d,limit %llu , n %llu , totalThreads %d \n",index, *limit , *n , *totalThreads);
//printf("block %d, thread %d \n", blockIdx.x, threadIdx.x);
marked[0]=1;
marked[1]=1;
index=index+2;
if(*totalThreads>*n || index >*limit){
return ;
}else if(*totalThreads ==1){
for(ULL p=2;p<=*limit;p++){
for(ULL multiple=2*p; multiple<*n; multiple+=p){
marked[multiple]=1;
}
}
}
else{
//printf("index %d,limit %llu , n %llu , totalThreads %d \n",index, *limit , *n , *totalThreads);
for(ULL p=index;p<=*limit;p+=*totalThreads){
if(marked[p]==1 || p%2==0 && p>2) return;
//printf("index %d , p%llu \n",index,p);
for(ULL multiple=2*p; multiple<*n; multiple+=p){
//printf("multiple %llu \n",multiple);
marked[multiple]=1;
}
}
}
__syncthreads();
}
int main(int argc, char **argv){
ULL size;
ULL *list,*d_list,limit,*d_limit,*d_n,n;
n=atoi(argv[1]);
int threads=atoi(argv[2]);
//int thread_per_block=atoi(argv[3]);
int blocks= floor(n/threads);
int totalThreads = threads;
int *d_totalThreads;
primeresult.open("cudaSieveList.txt");
timeresult.open("cudaSieveResult.txt",ios::out | ios::app );
size = n*sizeof(ULL);
limit = floor(sqrt(n));
cudaMalloc((void**)&d_list,size);
cudaMalloc((void**)&d_limit,sizeof(ULL));
cudaMalloc((void**)&d_n,sizeof(ULL));
cudaMalloc((void**)&d_totalThreads,sizeof(int));
list = (ULL*) malloc(size);
memset(list,0,size);
cudaMemset(d_list, 0, size);
cudaMemcpy(d_list ,list ,size ,cudaMemcpyHostToDevice);
cudaMemcpy(d_limit ,&limit ,sizeof(ULL) ,cudaMemcpyHostToDevice);
cudaMemcpy(d_n ,&n ,sizeof(ULL) ,cudaMemcpyHostToDevice);
cudaMemcpy(d_totalThreads ,&totalThreads ,sizeof(int) ,cudaMemcpyHostToDevice);
auto begin= std::chrono::high_resolution_clock::now();
cuda_erastothenes_sieve<<<blocks,threads>>>(d_list,d_limit,d_n,d_totalThreads);
auto end = std::chrono::high_resolution_clock::now();
auto duration = duration_cast<std::chrono::microseconds>(end - begin);
timeresult<<duration.count()<<endl;
cudaMemcpy(list,d_list, size, cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
// check for error
cudaError_t error = cudaGetLastError();
if(error != cudaSuccess)
{
// print the CUDA error message and exit
printf("CUDA error: %s\n", cudaGetErrorString(error));
return 0;
}
for(ULL i=0;i<n;i++){
if(list[i]==0){
primeresult<<i<<endl;
//cout<<i<<endl;
};
}
//cout<<duration.count()<<endl;
free(list);
cudaFree(d_list);
cudaFree(d_limit);
cudaFree(d_n);
primeresult.close();
timeresult.close();
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
#include <math.h>
#include <chrono>
#include <iomanip>
#include <fstream>
using namespace std;
using namespace std::chrono;
typedef unsigned long long ULL;
ofstream primeresult;
ofstream timeresult;
__global__ void cuda_erastothenes_sieve (ULL *marked, ULL *limit, ULL *n, int *totalThreads) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
//printf("index %d,limit %llu , n %llu , totalThreads %d \n",index, *limit , *n , *totalThreads);
//printf("block %d, thread %d \n", blockIdx.x, threadIdx.x);
marked[0]=1;
marked[1]=1;
index=index+2;
if(*totalThreads>*n || index >*limit){
return ;
}else if(*totalThreads ==1){
for(ULL p=2;p<=*limit;p++){
for(ULL multiple=2*p; multiple<*n; multiple+=p){
marked[multiple]=1;
}
}
}
else{
//printf("index %d,limit %llu , n %llu , totalThreads %d \n",index, *limit , *n , *totalThreads);
for(ULL p=index;p<=*limit;p+=*totalThreads){
if(marked[p]==1 || p%2==0 && p>2) return;
//printf("index %d , p%llu \n",index,p);
for(ULL multiple=2*p; multiple<*n; multiple+=p){
//printf("multiple %llu \n",multiple);
marked[multiple]=1;
}
}
}
__syncthreads();
}
int main(int argc, char **argv){
ULL size;
ULL *list,*d_list,limit,*d_limit,*d_n,n;
n=atoi(argv[1]);
int threads=atoi(argv[2]);
//int thread_per_block=atoi(argv[3]);
int blocks= floor(n/threads);
int totalThreads = threads;
int *d_totalThreads;
primeresult.open("cudaSieveList.txt");
timeresult.open("cudaSieveResult.txt",ios::out | ios::app );
size = n*sizeof(ULL);
limit = floor(sqrt(n));
hipMalloc((void**)&d_list,size);
hipMalloc((void**)&d_limit,sizeof(ULL));
hipMalloc((void**)&d_n,sizeof(ULL));
hipMalloc((void**)&d_totalThreads,sizeof(int));
list = (ULL*) malloc(size);
memset(list,0,size);
hipMemset(d_list, 0, size);
hipMemcpy(d_list ,list ,size ,hipMemcpyHostToDevice);
hipMemcpy(d_limit ,&limit ,sizeof(ULL) ,hipMemcpyHostToDevice);
hipMemcpy(d_n ,&n ,sizeof(ULL) ,hipMemcpyHostToDevice);
hipMemcpy(d_totalThreads ,&totalThreads ,sizeof(int) ,hipMemcpyHostToDevice);
auto begin= std::chrono::high_resolution_clock::now();
cuda_erastothenes_sieve<<<blocks,threads>>>(d_list,d_limit,d_n,d_totalThreads);
auto end = std::chrono::high_resolution_clock::now();
auto duration = duration_cast<std::chrono::microseconds>(end - begin);
timeresult<<duration.count()<<endl;
hipMemcpy(list,d_list, size, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
// check for error
hipError_t error = hipGetLastError();
if(error != hipSuccess)
{
// print the CUDA error message and exit
printf("CUDA error: %s\n", hipGetErrorString(error));
return 0;
}
for(ULL i=0;i<n;i++){
if(list[i]==0){
primeresult<<i<<endl;
//cout<<i<<endl;
};
}
//cout<<duration.count()<<endl;
free(list);
hipFree(d_list);
hipFree(d_limit);
hipFree(d_n);
primeresult.close();
timeresult.close();
return 0;
} |
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